truffle: src/share/vm/opto/regmask.cpp annotate

annotate src/share/vm/opto/regmask.cpp @ 14391:d2907f74462e

8016586: PPC64 (part 3): basic changes for PPC64 Summary: added #includes needed for ppc64 port. Renamed _MODEL_ppc to _MODEL_ppc_32 and renamed corresponding old _ppc files to _ppc_32. Reviewed-by: dholmes, kvn

author	goetz
date	Thu, 20 Jun 2013 16:30:44 -0700
parents	2c673161698a
children	4ca6dc0799b6 78bbf4d43a14

rev	line source
0 a61af66fc99e Initial load duke parents: diff changeset	1 /*
8044 2c673161698a 8007402: Code cleanup to remove Parfait false positive drchase parents: 7636 diff changeset	2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
0 a61af66fc99e Initial load duke parents: diff changeset	3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
a61af66fc99e Initial load duke parents: diff changeset	4 *
a61af66fc99e Initial load duke parents: diff changeset	5 * This code is free software; you can redistribute it and/or modify it
a61af66fc99e Initial load duke parents: diff changeset	6 * under the terms of the GNU General Public License version 2 only, as
a61af66fc99e Initial load duke parents: diff changeset	7 * published by the Free Software Foundation.
a61af66fc99e Initial load duke parents: diff changeset	8 *
a61af66fc99e Initial load duke parents: diff changeset	9 * This code is distributed in the hope that it will be useful, but WITHOUT
a61af66fc99e Initial load duke parents: diff changeset	10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
a61af66fc99e Initial load duke parents: diff changeset	11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
a61af66fc99e Initial load duke parents: diff changeset	12 * version 2 for more details (a copy is included in the LICENSE file that
a61af66fc99e Initial load duke parents: diff changeset	13 * accompanied this code).
a61af66fc99e Initial load duke parents: diff changeset	14 *
a61af66fc99e Initial load duke parents: diff changeset	15 * You should have received a copy of the GNU General Public License version
a61af66fc99e Initial load duke parents: diff changeset	16 * 2 along with this work; if not, write to the Free Software Foundation,
a61af66fc99e Initial load duke parents: diff changeset	17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
a61af66fc99e Initial load duke parents: diff changeset	18 *
1552 c18cbe5936b8 6941466: Oracle rebranding changes for Hotspot repositories trims parents: 0 diff changeset	19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
c18cbe5936b8 6941466: Oracle rebranding changes for Hotspot repositories trims parents: 0 diff changeset	20 * or visit www.oracle.com if you need additional information or have any
c18cbe5936b8 6941466: Oracle rebranding changes for Hotspot repositories trims parents: 0 diff changeset	21 * questions.
0 a61af66fc99e Initial load duke parents: diff changeset	22 *
a61af66fc99e Initial load duke parents: diff changeset	23 */
a61af66fc99e Initial load duke parents: diff changeset	24
1972 f95d63e2154a 6989984: Use standard include model for Hospot stefank parents: 1552 diff changeset	25 #include "precompiled.hpp"
f95d63e2154a 6989984: Use standard include model for Hospot stefank parents: 1552 diff changeset	26 #include "opto/compile.hpp"
f95d63e2154a 6989984: Use standard include model for Hospot stefank parents: 1552 diff changeset	27 #include "opto/regmask.hpp"
f95d63e2154a 6989984: Use standard include model for Hospot stefank parents: 1552 diff changeset	28 #ifdef TARGET_ARCH_MODEL_x86_32
f95d63e2154a 6989984: Use standard include model for Hospot stefank parents: 1552 diff changeset	29 # include "adfiles/ad_x86_32.hpp"
f95d63e2154a 6989984: Use standard include model for Hospot stefank parents: 1552 diff changeset	30 #endif
f95d63e2154a 6989984: Use standard include model for Hospot stefank parents: 1552 diff changeset	31 #ifdef TARGET_ARCH_MODEL_x86_64
f95d63e2154a 6989984: Use standard include model for Hospot stefank parents: 1552 diff changeset	32 # include "adfiles/ad_x86_64.hpp"
f95d63e2154a 6989984: Use standard include model for Hospot stefank parents: 1552 diff changeset	33 #endif
f95d63e2154a 6989984: Use standard include model for Hospot stefank parents: 1552 diff changeset	34 #ifdef TARGET_ARCH_MODEL_sparc
f95d63e2154a 6989984: Use standard include model for Hospot stefank parents: 1552 diff changeset	35 # include "adfiles/ad_sparc.hpp"
f95d63e2154a 6989984: Use standard include model for Hospot stefank parents: 1552 diff changeset	36 #endif
f95d63e2154a 6989984: Use standard include model for Hospot stefank parents: 1552 diff changeset	37 #ifdef TARGET_ARCH_MODEL_zero
f95d63e2154a 6989984: Use standard include model for Hospot stefank parents: 1552 diff changeset	38 # include "adfiles/ad_zero.hpp"
f95d63e2154a 6989984: Use standard include model for Hospot stefank parents: 1552 diff changeset	39 #endif
2192 b92c45f2bc75 7016023: Enable building ARM and PPC from src/closed repository bobv parents: 1972 diff changeset	40 #ifdef TARGET_ARCH_MODEL_arm
b92c45f2bc75 7016023: Enable building ARM and PPC from src/closed repository bobv parents: 1972 diff changeset	41 # include "adfiles/ad_arm.hpp"
b92c45f2bc75 7016023: Enable building ARM and PPC from src/closed repository bobv parents: 1972 diff changeset	42 #endif
14391 d2907f74462e 8016586: PPC64 (part 3): basic changes for PPC64 goetz parents: 8044 diff changeset	43 #ifdef TARGET_ARCH_MODEL_ppc_32
d2907f74462e 8016586: PPC64 (part 3): basic changes for PPC64 goetz parents: 8044 diff changeset	44 # include "adfiles/ad_ppc_32.hpp"
d2907f74462e 8016586: PPC64 (part 3): basic changes for PPC64 goetz parents: 8044 diff changeset	45 #endif
d2907f74462e 8016586: PPC64 (part 3): basic changes for PPC64 goetz parents: 8044 diff changeset	46 #ifdef TARGET_ARCH_MODEL_ppc_64
d2907f74462e 8016586: PPC64 (part 3): basic changes for PPC64 goetz parents: 8044 diff changeset	47 # include "adfiles/ad_ppc_64.hpp"
2192 b92c45f2bc75 7016023: Enable building ARM and PPC from src/closed repository bobv parents: 1972 diff changeset	48 #endif
0 a61af66fc99e Initial load duke parents: diff changeset	49
a61af66fc99e Initial load duke parents: diff changeset	50 #define RM_SIZE _RM_SIZE /* a constant private to the class RegMask */
a61af66fc99e Initial load duke parents: diff changeset	51
a61af66fc99e Initial load duke parents: diff changeset	52 //-------------Non-zero bit search methods used by RegMask---------------------
a61af66fc99e Initial load duke parents: diff changeset	53 // Find lowest 1, or return 32 if empty
a61af66fc99e Initial load duke parents: diff changeset	54 int find_lowest_bit( uint32 mask ) {
a61af66fc99e Initial load duke parents: diff changeset	55 int n = 0;
a61af66fc99e Initial load duke parents: diff changeset	56 if( (mask & 0xffff) == 0 ) {
a61af66fc99e Initial load duke parents: diff changeset	57 mask >>= 16;
a61af66fc99e Initial load duke parents: diff changeset	58 n += 16;
a61af66fc99e Initial load duke parents: diff changeset	59 }
a61af66fc99e Initial load duke parents: diff changeset	60 if( (mask & 0xff) == 0 ) {
a61af66fc99e Initial load duke parents: diff changeset	61 mask >>= 8;
a61af66fc99e Initial load duke parents: diff changeset	62 n += 8;
a61af66fc99e Initial load duke parents: diff changeset	63 }
a61af66fc99e Initial load duke parents: diff changeset	64 if( (mask & 0xf) == 0 ) {
a61af66fc99e Initial load duke parents: diff changeset	65 mask >>= 4;
a61af66fc99e Initial load duke parents: diff changeset	66 n += 4;
a61af66fc99e Initial load duke parents: diff changeset	67 }
a61af66fc99e Initial load duke parents: diff changeset	68 if( (mask & 0x3) == 0 ) {
a61af66fc99e Initial load duke parents: diff changeset	69 mask >>= 2;
a61af66fc99e Initial load duke parents: diff changeset	70 n += 2;
a61af66fc99e Initial load duke parents: diff changeset	71 }
a61af66fc99e Initial load duke parents: diff changeset	72 if( (mask & 0x1) == 0 ) {
a61af66fc99e Initial load duke parents: diff changeset	73 mask >>= 1;
a61af66fc99e Initial load duke parents: diff changeset	74 n += 1;
a61af66fc99e Initial load duke parents: diff changeset	75 }
a61af66fc99e Initial load duke parents: diff changeset	76 if( mask == 0 ) {
a61af66fc99e Initial load duke parents: diff changeset	77 n = 32;
a61af66fc99e Initial load duke parents: diff changeset	78 }
a61af66fc99e Initial load duke parents: diff changeset	79 return n;
a61af66fc99e Initial load duke parents: diff changeset	80 }
a61af66fc99e Initial load duke parents: diff changeset	81
a61af66fc99e Initial load duke parents: diff changeset	82 // Find highest 1, or return 32 if empty
a61af66fc99e Initial load duke parents: diff changeset	83 int find_hihghest_bit( uint32 mask ) {
a61af66fc99e Initial load duke parents: diff changeset	84 int n = 0;
a61af66fc99e Initial load duke parents: diff changeset	85 if( mask > 0xffff ) {
a61af66fc99e Initial load duke parents: diff changeset	86 mask >>= 16;
a61af66fc99e Initial load duke parents: diff changeset	87 n += 16;
a61af66fc99e Initial load duke parents: diff changeset	88 }
a61af66fc99e Initial load duke parents: diff changeset	89 if( mask > 0xff ) {
a61af66fc99e Initial load duke parents: diff changeset	90 mask >>= 8;
a61af66fc99e Initial load duke parents: diff changeset	91 n += 8;
a61af66fc99e Initial load duke parents: diff changeset	92 }
a61af66fc99e Initial load duke parents: diff changeset	93 if( mask > 0xf ) {
a61af66fc99e Initial load duke parents: diff changeset	94 mask >>= 4;
a61af66fc99e Initial load duke parents: diff changeset	95 n += 4;
a61af66fc99e Initial load duke parents: diff changeset	96 }
a61af66fc99e Initial load duke parents: diff changeset	97 if( mask > 0x3 ) {
a61af66fc99e Initial load duke parents: diff changeset	98 mask >>= 2;
a61af66fc99e Initial load duke parents: diff changeset	99 n += 2;
a61af66fc99e Initial load duke parents: diff changeset	100 }
a61af66fc99e Initial load duke parents: diff changeset	101 if( mask > 0x1 ) {
a61af66fc99e Initial load duke parents: diff changeset	102 mask >>= 1;
a61af66fc99e Initial load duke parents: diff changeset	103 n += 1;
a61af66fc99e Initial load duke parents: diff changeset	104 }
a61af66fc99e Initial load duke parents: diff changeset	105 if( mask == 0 ) {
a61af66fc99e Initial load duke parents: diff changeset	106 n = 32;
a61af66fc99e Initial load duke parents: diff changeset	107 }
a61af66fc99e Initial load duke parents: diff changeset	108 return n;
a61af66fc99e Initial load duke parents: diff changeset	109 }
a61af66fc99e Initial load duke parents: diff changeset	110
a61af66fc99e Initial load duke parents: diff changeset	111 //------------------------------dump-------------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	112
a61af66fc99e Initial load duke parents: diff changeset	113 #ifndef PRODUCT
7636 a7114d3d712e 8005055: pass outputStream to more opto debug routines kvn parents: 6179 diff changeset	114 void OptoReg::dump(int r, outputStream *st) {
a7114d3d712e 8005055: pass outputStream to more opto debug routines kvn parents: 6179 diff changeset	115 switch (r) {
a7114d3d712e 8005055: pass outputStream to more opto debug routines kvn parents: 6179 diff changeset	116 case Special: st->print("r---"); break;
a7114d3d712e 8005055: pass outputStream to more opto debug routines kvn parents: 6179 diff changeset	117 case Bad: st->print("rBAD"); break;
0 a61af66fc99e Initial load duke parents: diff changeset	118 default:
7636 a7114d3d712e 8005055: pass outputStream to more opto debug routines kvn parents: 6179 diff changeset	119 if (r < _last_Mach_Reg) st->print(Matcher::regName[r]);
a7114d3d712e 8005055: pass outputStream to more opto debug routines kvn parents: 6179 diff changeset	120 else st->print("rS%d",r);
0 a61af66fc99e Initial load duke parents: diff changeset	121 break;
a61af66fc99e Initial load duke parents: diff changeset	122 }
a61af66fc99e Initial load duke parents: diff changeset	123 }
a61af66fc99e Initial load duke parents: diff changeset	124 #endif
a61af66fc99e Initial load duke parents: diff changeset	125
a61af66fc99e Initial load duke parents: diff changeset	126
a61af66fc99e Initial load duke parents: diff changeset	127 //=============================================================================
a61af66fc99e Initial load duke parents: diff changeset	128 const RegMask RegMask::Empty(
a61af66fc99e Initial load duke parents: diff changeset	129 # define BODY(I) 0,
a61af66fc99e Initial load duke parents: diff changeset	130 FORALL_BODY
a61af66fc99e Initial load duke parents: diff changeset	131 # undef BODY
a61af66fc99e Initial load duke parents: diff changeset	132 0
a61af66fc99e Initial load duke parents: diff changeset	133 );
a61af66fc99e Initial load duke parents: diff changeset	134
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	135 //=============================================================================
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	136 bool RegMask::is_vector(uint ireg) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	137 return (ireg == Op_VecS \|\| ireg == Op_VecD \|\| ireg == Op_VecX \|\| ireg == Op_VecY);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	138 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	139
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	140 int RegMask::num_registers(uint ireg) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	141 switch(ireg) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	142 case Op_VecY:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	143 return 8;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	144 case Op_VecX:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	145 return 4;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	146 case Op_VecD:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	147 case Op_RegD:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	148 case Op_RegL:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	149 #ifdef _LP64
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	150 case Op_RegP:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	151 #endif
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	152 return 2;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	153 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	154 // Op_VecS and the rest ideal registers.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	155 return 1;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	156 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	157
0 a61af66fc99e Initial load duke parents: diff changeset	158 //------------------------------find_first_pair--------------------------------
a61af66fc99e Initial load duke parents: diff changeset	159 // Find the lowest-numbered register pair in the mask. Return the
a61af66fc99e Initial load duke parents: diff changeset	160 // HIGHEST register number in the pair, or BAD if no pairs.
a61af66fc99e Initial load duke parents: diff changeset	161 OptoReg::Name RegMask::find_first_pair() const {
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	162 verify_pairs();
0 a61af66fc99e Initial load duke parents: diff changeset	163 for( int i = 0; i < RM_SIZE; i++ ) {
a61af66fc99e Initial load duke parents: diff changeset	164 if( _A[i] ) { // Found some bits
a61af66fc99e Initial load duke parents: diff changeset	165 int bit = _A[i] & -_A[i]; // Extract low bit
a61af66fc99e Initial load duke parents: diff changeset	166 // Convert to bit number, return hi bit in pair
a61af66fc99e Initial load duke parents: diff changeset	167 return OptoReg::Name((i<<_LogWordBits)+find_lowest_bit(bit)+1);
a61af66fc99e Initial load duke parents: diff changeset	168 }
a61af66fc99e Initial load duke parents: diff changeset	169 }
a61af66fc99e Initial load duke parents: diff changeset	170 return OptoReg::Bad;
a61af66fc99e Initial load duke parents: diff changeset	171 }
a61af66fc99e Initial load duke parents: diff changeset	172
a61af66fc99e Initial load duke parents: diff changeset	173 //------------------------------ClearToPairs-----------------------------------
a61af66fc99e Initial load duke parents: diff changeset	174 // Clear out partial bits; leave only bit pairs
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	175 void RegMask::clear_to_pairs() {
0 a61af66fc99e Initial load duke parents: diff changeset	176 for( int i = 0; i < RM_SIZE; i++ ) {
a61af66fc99e Initial load duke parents: diff changeset	177 int bits = _A[i];
a61af66fc99e Initial load duke parents: diff changeset	178 bits &= ((bits & 0x55555555)<<1); // 1 hi-bit set for each pair
a61af66fc99e Initial load duke parents: diff changeset	179 bits \|= (bits>>1); // Smear 1 hi-bit into a pair
a61af66fc99e Initial load duke parents: diff changeset	180 _A[i] = bits;
a61af66fc99e Initial load duke parents: diff changeset	181 }
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	182 verify_pairs();
0 a61af66fc99e Initial load duke parents: diff changeset	183 }
a61af66fc99e Initial load duke parents: diff changeset	184
a61af66fc99e Initial load duke parents: diff changeset	185 //------------------------------SmearToPairs-----------------------------------
a61af66fc99e Initial load duke parents: diff changeset	186 // Smear out partial bits; leave only bit pairs
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	187 void RegMask::smear_to_pairs() {
0 a61af66fc99e Initial load duke parents: diff changeset	188 for( int i = 0; i < RM_SIZE; i++ ) {
a61af66fc99e Initial load duke parents: diff changeset	189 int bits = _A[i];
a61af66fc99e Initial load duke parents: diff changeset	190 bits \|= ((bits & 0x55555555)<<1); // Smear lo bit hi per pair
a61af66fc99e Initial load duke parents: diff changeset	191 bits \|= ((bits & 0xAAAAAAAA)>>1); // Smear hi bit lo per pair
a61af66fc99e Initial load duke parents: diff changeset	192 _A[i] = bits;
a61af66fc99e Initial load duke parents: diff changeset	193 }
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	194 verify_pairs();
0 a61af66fc99e Initial load duke parents: diff changeset	195 }
a61af66fc99e Initial load duke parents: diff changeset	196
a61af66fc99e Initial load duke parents: diff changeset	197 //------------------------------is_aligned_pairs-------------------------------
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	198 bool RegMask::is_aligned_pairs() const {
0 a61af66fc99e Initial load duke parents: diff changeset	199 // Assert that the register mask contains only bit pairs.
a61af66fc99e Initial load duke parents: diff changeset	200 for( int i = 0; i < RM_SIZE; i++ ) {
a61af66fc99e Initial load duke parents: diff changeset	201 int bits = _A[i];
a61af66fc99e Initial load duke parents: diff changeset	202 while( bits ) { // Check bits for pairing
a61af66fc99e Initial load duke parents: diff changeset	203 int bit = bits & -bits; // Extract low bit
a61af66fc99e Initial load duke parents: diff changeset	204 // Low bit is not odd means its mis-aligned.
a61af66fc99e Initial load duke parents: diff changeset	205 if( (bit & 0x55555555) == 0 ) return false;
a61af66fc99e Initial load duke parents: diff changeset	206 bits -= bit; // Remove bit from mask
a61af66fc99e Initial load duke parents: diff changeset	207 // Check for aligned adjacent bit
a61af66fc99e Initial load duke parents: diff changeset	208 if( (bits & (bit<<1)) == 0 ) return false;
a61af66fc99e Initial load duke parents: diff changeset	209 bits -= (bit<<1); // Remove other halve of pair
a61af66fc99e Initial load duke parents: diff changeset	210 }
a61af66fc99e Initial load duke parents: diff changeset	211 }
a61af66fc99e Initial load duke parents: diff changeset	212 return true;
a61af66fc99e Initial load duke parents: diff changeset	213 }
a61af66fc99e Initial load duke parents: diff changeset	214
a61af66fc99e Initial load duke parents: diff changeset	215 //------------------------------is_bound1--------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	216 // Return TRUE if the mask contains a single bit
a61af66fc99e Initial load duke parents: diff changeset	217 int RegMask::is_bound1() const {
a61af66fc99e Initial load duke parents: diff changeset	218 if( is_AllStack() ) return false;
a61af66fc99e Initial load duke parents: diff changeset	219 int bit = -1; // Set to hold the one bit allowed
a61af66fc99e Initial load duke parents: diff changeset	220 for( int i = 0; i < RM_SIZE; i++ ) {
a61af66fc99e Initial load duke parents: diff changeset	221 if( _A[i] ) { // Found some bits
a61af66fc99e Initial load duke parents: diff changeset	222 if( bit != -1 ) return false; // Already had bits, so fail
a61af66fc99e Initial load duke parents: diff changeset	223 bit = _A[i] & -_A[i]; // Extract 1 bit from mask
a61af66fc99e Initial load duke parents: diff changeset	224 if( bit != _A[i] ) return false; // Found many bits, so fail
a61af66fc99e Initial load duke parents: diff changeset	225 }
a61af66fc99e Initial load duke parents: diff changeset	226 }
a61af66fc99e Initial load duke parents: diff changeset	227 // True for both the empty mask and for a single bit
a61af66fc99e Initial load duke parents: diff changeset	228 return true;
a61af66fc99e Initial load duke parents: diff changeset	229 }
a61af66fc99e Initial load duke parents: diff changeset	230
a61af66fc99e Initial load duke parents: diff changeset	231 //------------------------------is_bound2--------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	232 // Return TRUE if the mask contains an adjacent pair of bits and no other bits.
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	233 int RegMask::is_bound_pair() const {
0 a61af66fc99e Initial load duke parents: diff changeset	234 if( is_AllStack() ) return false;
a61af66fc99e Initial load duke parents: diff changeset	235
a61af66fc99e Initial load duke parents: diff changeset	236 int bit = -1; // Set to hold the one bit allowed
a61af66fc99e Initial load duke parents: diff changeset	237 for( int i = 0; i < RM_SIZE; i++ ) {
a61af66fc99e Initial load duke parents: diff changeset	238 if( _A[i] ) { // Found some bits
a61af66fc99e Initial load duke parents: diff changeset	239 if( bit != -1 ) return false; // Already had bits, so fail
a61af66fc99e Initial load duke parents: diff changeset	240 bit = _A[i] & -(_A[i]); // Extract 1 bit from mask
a61af66fc99e Initial load duke parents: diff changeset	241 if( (bit << 1) != 0 ) { // Bit pair stays in same word?
a61af66fc99e Initial load duke parents: diff changeset	242 if( (bit \| (bit<<1)) != _A[i] )
a61af66fc99e Initial load duke parents: diff changeset	243 return false; // Require adjacent bit pair and no more bits
a61af66fc99e Initial load duke parents: diff changeset	244 } else { // Else its a split-pair case
a61af66fc99e Initial load duke parents: diff changeset	245 if( bit != _A[i] ) return false; // Found many bits, so fail
a61af66fc99e Initial load duke parents: diff changeset	246 i++; // Skip iteration forward
8044 2c673161698a 8007402: Code cleanup to remove Parfait false positive drchase parents: 7636 diff changeset	247 if( i >= RM_SIZE \|\| _A[i] != 1 )
2c673161698a 8007402: Code cleanup to remove Parfait false positive drchase parents: 7636 diff changeset	248 return false; // Require 1 lo bit in next word
0 a61af66fc99e Initial load duke parents: diff changeset	249 }
a61af66fc99e Initial load duke parents: diff changeset	250 }
a61af66fc99e Initial load duke parents: diff changeset	251 }
a61af66fc99e Initial load duke parents: diff changeset	252 // True for both the empty mask and for a bit pair
a61af66fc99e Initial load duke parents: diff changeset	253 return true;
a61af66fc99e Initial load duke parents: diff changeset	254 }
a61af66fc99e Initial load duke parents: diff changeset	255
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	256 static int low_bits[3] = { 0x55555555, 0x11111111, 0x01010101 };
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	257 //------------------------------find_first_set---------------------------------
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	258 // Find the lowest-numbered register set in the mask. Return the
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	259 // HIGHEST register number in the set, or BAD if no sets.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	260 // Works also for size 1.
8044 2c673161698a 8007402: Code cleanup to remove Parfait false positive drchase parents: 7636 diff changeset	261 OptoReg::Name RegMask::find_first_set(const int size) const {
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	262 verify_sets(size);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	263 for (int i = 0; i < RM_SIZE; i++) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	264 if (_A[i]) { // Found some bits
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	265 int bit = _A[i] & -_A[i]; // Extract low bit
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	266 // Convert to bit number, return hi bit in pair
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	267 return OptoReg::Name((i<<_LogWordBits)+find_lowest_bit(bit)+(size-1));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	268 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	269 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	270 return OptoReg::Bad;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	271 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	272
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	273 //------------------------------clear_to_sets----------------------------------
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	274 // Clear out partial bits; leave only aligned adjacent bit pairs
8044 2c673161698a 8007402: Code cleanup to remove Parfait false positive drchase parents: 7636 diff changeset	275 void RegMask::clear_to_sets(const int size) {
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	276 if (size == 1) return;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	277 assert(2 <= size && size <= 8, "update low bits table");
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	278 assert(is_power_of_2(size), "sanity");
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	279 int low_bits_mask = low_bits[size>>2];
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	280 for (int i = 0; i < RM_SIZE; i++) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	281 int bits = _A[i];
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	282 int sets = (bits & low_bits_mask);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	283 for (int j = 1; j < size; j++) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	284 sets = (bits & (sets<<1)); // filter bits which produce whole sets
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	285 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	286 sets \|= (sets>>1); // Smear 1 hi-bit into a set
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	287 if (size > 2) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	288 sets \|= (sets>>2); // Smear 2 hi-bits into a set
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	289 if (size > 4) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	290 sets \|= (sets>>4); // Smear 4 hi-bits into a set
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	291 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	292 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	293 _A[i] = sets;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	294 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	295 verify_sets(size);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	296 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	297
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	298 //------------------------------smear_to_sets----------------------------------
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	299 // Smear out partial bits to aligned adjacent bit sets
8044 2c673161698a 8007402: Code cleanup to remove Parfait false positive drchase parents: 7636 diff changeset	300 void RegMask::smear_to_sets(const int size) {
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	301 if (size == 1) return;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	302 assert(2 <= size && size <= 8, "update low bits table");
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	303 assert(is_power_of_2(size), "sanity");
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	304 int low_bits_mask = low_bits[size>>2];
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	305 for (int i = 0; i < RM_SIZE; i++) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	306 int bits = _A[i];
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	307 int sets = 0;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	308 for (int j = 0; j < size; j++) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	309 sets \|= (bits & low_bits_mask); // collect partial bits
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	310 bits = bits>>1;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	311 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	312 sets \|= (sets<<1); // Smear 1 lo-bit into a set
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	313 if (size > 2) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	314 sets \|= (sets<<2); // Smear 2 lo-bits into a set
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	315 if (size > 4) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	316 sets \|= (sets<<4); // Smear 4 lo-bits into a set
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	317 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	318 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	319 _A[i] = sets;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	320 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	321 verify_sets(size);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	322 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	323
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	324 //------------------------------is_aligned_set--------------------------------
8044 2c673161698a 8007402: Code cleanup to remove Parfait false positive drchase parents: 7636 diff changeset	325 bool RegMask::is_aligned_sets(const int size) const {
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	326 if (size == 1) return true;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	327 assert(2 <= size && size <= 8, "update low bits table");
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	328 assert(is_power_of_2(size), "sanity");
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	329 int low_bits_mask = low_bits[size>>2];
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	330 // Assert that the register mask contains only bit sets.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	331 for (int i = 0; i < RM_SIZE; i++) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	332 int bits = _A[i];
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	333 while (bits) { // Check bits for pairing
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	334 int bit = bits & -bits; // Extract low bit
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	335 // Low bit is not odd means its mis-aligned.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	336 if ((bit & low_bits_mask) == 0) return false;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	337 // Do extra work since (bit << size) may overflow.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	338 int hi_bit = bit << (size-1); // high bit
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	339 int set = hi_bit + ((hi_bit-1) & ~(bit-1));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	340 // Check for aligned adjacent bits in this set
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	341 if ((bits & set) != set) return false;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	342 bits -= set; // Remove this set
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	343 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	344 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	345 return true;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	346 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	347
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	348 //------------------------------is_bound_set-----------------------------------
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	349 // Return TRUE if the mask contains one adjacent set of bits and no other bits.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	350 // Works also for size 1.
8044 2c673161698a 8007402: Code cleanup to remove Parfait false positive drchase parents: 7636 diff changeset	351 int RegMask::is_bound_set(const int size) const {
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	352 if( is_AllStack() ) return false;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	353 assert(1 <= size && size <= 8, "update low bits table");
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	354 int bit = -1; // Set to hold the one bit allowed
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	355 for (int i = 0; i < RM_SIZE; i++) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	356 if (_A[i] ) { // Found some bits
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	357 if (bit != -1)
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	358 return false; // Already had bits, so fail
8044 2c673161698a 8007402: Code cleanup to remove Parfait false positive drchase parents: 7636 diff changeset	359 bit = _A[i] & -_A[i]; // Extract low bit from mask
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	360 int hi_bit = bit << (size-1); // high bit
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	361 if (hi_bit != 0) { // Bit set stays in same word?
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	362 int set = hi_bit + ((hi_bit-1) & ~(bit-1));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	363 if (set != _A[i])
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	364 return false; // Require adjacent bit set and no more bits
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	365 } else { // Else its a split-set case
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	366 if (((-1) & ~(bit-1)) != _A[i])
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	367 return false; // Found many bits, so fail
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	368 i++; // Skip iteration forward and check high part
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	369 // The lower 24 bits should be 0 since it is split case and size <= 8.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	370 int set = bit>>24;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	371 set = set & -set; // Remove sign extension.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	372 set = (((set << size) - 1) >> 8);
8044 2c673161698a 8007402: Code cleanup to remove Parfait false positive drchase parents: 7636 diff changeset	373 if (i >= RM_SIZE \|\| _A[i] != set)
2c673161698a 8007402: Code cleanup to remove Parfait false positive drchase parents: 7636 diff changeset	374 return false; // Require expected low bits in next word
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	375 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	376 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	377 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	378 // True for both the empty mask and for a bit set
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	379 return true;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	380 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 2426 diff changeset	381
0 a61af66fc99e Initial load duke parents: diff changeset	382 //------------------------------is_UP------------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	383 // UP means register only, Register plus stack, or stack only is DOWN
a61af66fc99e Initial load duke parents: diff changeset	384 bool RegMask::is_UP() const {
a61af66fc99e Initial load duke parents: diff changeset	385 // Quick common case check for DOWN (any stack slot is legal)
a61af66fc99e Initial load duke parents: diff changeset	386 if( is_AllStack() )
a61af66fc99e Initial load duke parents: diff changeset	387 return false;
a61af66fc99e Initial load duke parents: diff changeset	388 // Slower check for any stack bits set (also DOWN)
a61af66fc99e Initial load duke parents: diff changeset	389 if( overlap(Matcher::STACK_ONLY_mask) )
a61af66fc99e Initial load duke parents: diff changeset	390 return false;
a61af66fc99e Initial load duke parents: diff changeset	391 // Not DOWN, so must be UP
a61af66fc99e Initial load duke parents: diff changeset	392 return true;
a61af66fc99e Initial load duke parents: diff changeset	393 }
a61af66fc99e Initial load duke parents: diff changeset	394
a61af66fc99e Initial load duke parents: diff changeset	395 //------------------------------Size-------------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	396 // Compute size of register mask in bits
a61af66fc99e Initial load duke parents: diff changeset	397 uint RegMask::Size() const {
a61af66fc99e Initial load duke parents: diff changeset	398 extern uint8 bitsInByte[256];
a61af66fc99e Initial load duke parents: diff changeset	399 uint sum = 0;
a61af66fc99e Initial load duke parents: diff changeset	400 for( int i = 0; i < RM_SIZE; i++ )
a61af66fc99e Initial load duke parents: diff changeset	401 sum +=
a61af66fc99e Initial load duke parents: diff changeset	402 bitsInByte[(_A[i]>>24) & 0xff] +
a61af66fc99e Initial load duke parents: diff changeset	403 bitsInByte[(_A[i]>>16) & 0xff] +
a61af66fc99e Initial load duke parents: diff changeset	404 bitsInByte[(_A[i]>> 8) & 0xff] +
a61af66fc99e Initial load duke parents: diff changeset	405 bitsInByte[ _A[i] & 0xff];
a61af66fc99e Initial load duke parents: diff changeset	406 return sum;
a61af66fc99e Initial load duke parents: diff changeset	407 }
a61af66fc99e Initial load duke parents: diff changeset	408
a61af66fc99e Initial load duke parents: diff changeset	409 #ifndef PRODUCT
a61af66fc99e Initial load duke parents: diff changeset	410 //------------------------------print------------------------------------------
7636 a7114d3d712e 8005055: pass outputStream to more opto debug routines kvn parents: 6179 diff changeset	411 void RegMask::dump(outputStream *st) const {
a7114d3d712e 8005055: pass outputStream to more opto debug routines kvn parents: 6179 diff changeset	412 st->print("[");
0 a61af66fc99e Initial load duke parents: diff changeset	413 RegMask rm = *this; // Structure copy into local temp
a61af66fc99e Initial load duke parents: diff changeset	414
a61af66fc99e Initial load duke parents: diff changeset	415 OptoReg::Name start = rm.find_first_elem(); // Get a register
7636 a7114d3d712e 8005055: pass outputStream to more opto debug routines kvn parents: 6179 diff changeset	416 if (OptoReg::is_valid(start)) { // Check for empty mask
0 a61af66fc99e Initial load duke parents: diff changeset	417 rm.Remove(start); // Yank from mask
7636 a7114d3d712e 8005055: pass outputStream to more opto debug routines kvn parents: 6179 diff changeset	418 OptoReg::dump(start, st); // Print register
0 a61af66fc99e Initial load duke parents: diff changeset	419 OptoReg::Name last = start;
a61af66fc99e Initial load duke parents: diff changeset	420
a61af66fc99e Initial load duke parents: diff changeset	421 // Now I have printed an initial register.
a61af66fc99e Initial load duke parents: diff changeset	422 // Print adjacent registers as "rX-rZ" instead of "rX,rY,rZ".
a61af66fc99e Initial load duke parents: diff changeset	423 // Begin looping over the remaining registers.
7636 a7114d3d712e 8005055: pass outputStream to more opto debug routines kvn parents: 6179 diff changeset	424 while (1) { //
0 a61af66fc99e Initial load duke parents: diff changeset	425 OptoReg::Name reg = rm.find_first_elem(); // Get a register
7636 a7114d3d712e 8005055: pass outputStream to more opto debug routines kvn parents: 6179 diff changeset	426 if (!OptoReg::is_valid(reg))
0 a61af66fc99e Initial load duke parents: diff changeset	427 break; // Empty mask, end loop
a61af66fc99e Initial load duke parents: diff changeset	428 rm.Remove(reg); // Yank from mask
a61af66fc99e Initial load duke parents: diff changeset	429
7636 a7114d3d712e 8005055: pass outputStream to more opto debug routines kvn parents: 6179 diff changeset	430 if (last+1 == reg) { // See if they are adjacent
0 a61af66fc99e Initial load duke parents: diff changeset	431 // Adjacent registers just collect into long runs, no printing.
a61af66fc99e Initial load duke parents: diff changeset	432 last = reg;
a61af66fc99e Initial load duke parents: diff changeset	433 } else { // Ending some kind of run
7636 a7114d3d712e 8005055: pass outputStream to more opto debug routines kvn parents: 6179 diff changeset	434 if (start == last) { // 1-register run; no special printing
a7114d3d712e 8005055: pass outputStream to more opto debug routines kvn parents: 6179 diff changeset	435 } else if (start+1 == last) {
a7114d3d712e 8005055: pass outputStream to more opto debug routines kvn parents: 6179 diff changeset	436 st->print(","); // 2-register run; print as "rX,rY"
a7114d3d712e 8005055: pass outputStream to more opto debug routines kvn parents: 6179 diff changeset	437 OptoReg::dump(last, st);
0 a61af66fc99e Initial load duke parents: diff changeset	438 } else { // Multi-register run; print as "rX-rZ"
7636 a7114d3d712e 8005055: pass outputStream to more opto debug routines kvn parents: 6179 diff changeset	439 st->print("-");
a7114d3d712e 8005055: pass outputStream to more opto debug routines kvn parents: 6179 diff changeset	440 OptoReg::dump(last, st);
0 a61af66fc99e Initial load duke parents: diff changeset	441 }
7636 a7114d3d712e 8005055: pass outputStream to more opto debug routines kvn parents: 6179 diff changeset	442 st->print(","); // Seperate start of new run
0 a61af66fc99e Initial load duke parents: diff changeset	443 start = last = reg; // Start a new register run
7636 a7114d3d712e 8005055: pass outputStream to more opto debug routines kvn parents: 6179 diff changeset	444 OptoReg::dump(start, st); // Print register
0 a61af66fc99e Initial load duke parents: diff changeset	445 } // End of if ending a register run or not
a61af66fc99e Initial load duke parents: diff changeset	446 } // End of while regmask not empty
a61af66fc99e Initial load duke parents: diff changeset	447
7636 a7114d3d712e 8005055: pass outputStream to more opto debug routines kvn parents: 6179 diff changeset	448 if (start == last) { // 1-register run; no special printing
a7114d3d712e 8005055: pass outputStream to more opto debug routines kvn parents: 6179 diff changeset	449 } else if (start+1 == last) {
a7114d3d712e 8005055: pass outputStream to more opto debug routines kvn parents: 6179 diff changeset	450 st->print(","); // 2-register run; print as "rX,rY"
a7114d3d712e 8005055: pass outputStream to more opto debug routines kvn parents: 6179 diff changeset	451 OptoReg::dump(last, st);
0 a61af66fc99e Initial load duke parents: diff changeset	452 } else { // Multi-register run; print as "rX-rZ"
7636 a7114d3d712e 8005055: pass outputStream to more opto debug routines kvn parents: 6179 diff changeset	453 st->print("-");
a7114d3d712e 8005055: pass outputStream to more opto debug routines kvn parents: 6179 diff changeset	454 OptoReg::dump(last, st);
0 a61af66fc99e Initial load duke parents: diff changeset	455 }
7636 a7114d3d712e 8005055: pass outputStream to more opto debug routines kvn parents: 6179 diff changeset	456 if (rm.is_AllStack()) st->print("...");
0 a61af66fc99e Initial load duke parents: diff changeset	457 }
7636 a7114d3d712e 8005055: pass outputStream to more opto debug routines kvn parents: 6179 diff changeset	458 st->print("]");
0 a61af66fc99e Initial load duke parents: diff changeset	459 }
a61af66fc99e Initial load duke parents: diff changeset	460 #endif

Mercurial > hg > truffle

annotate src/share/vm/opto/regmask.cpp @ 14391:d2907f74462e