Mercurial > hg > truffle
annotate src/cpu/x86/vm/assembler_x86.hpp @ 2119:d4fca0a6abde
7011386: race in objArrayKlass::array_klass_impl
Summary: Move _lower_dimension field initialization before _higher_dimension and add storestore barrier.
Reviewed-by: dholmes, iveresov, never
author | kvn |
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date | Tue, 11 Jan 2011 20:26:13 -0800 |
parents | 2f644f85485d |
children | b1a2afa37ec4 |
rev | line source |
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0 | 1 /* |
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2 * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
0 | 22 * |
23 */ | |
24 | |
1972 | 25 #ifndef CPU_X86_VM_ASSEMBLER_X86_HPP |
26 #define CPU_X86_VM_ASSEMBLER_X86_HPP | |
27 | |
0 | 28 class BiasedLockingCounters; |
29 | |
30 // Contains all the definitions needed for x86 assembly code generation. | |
31 | |
32 // Calling convention | |
33 class Argument VALUE_OBJ_CLASS_SPEC { | |
34 public: | |
35 enum { | |
36 #ifdef _LP64 | |
37 #ifdef _WIN64 | |
38 n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...) | |
39 n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... ) | |
40 #else | |
41 n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...) | |
42 n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... ) | |
43 #endif // _WIN64 | |
44 n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ... | |
45 n_float_register_parameters_j = 8 // j_farg0, j_farg1, ... | |
46 #else | |
47 n_register_parameters = 0 // 0 registers used to pass arguments | |
48 #endif // _LP64 | |
49 }; | |
50 }; | |
51 | |
52 | |
53 #ifdef _LP64 | |
54 // Symbolically name the register arguments used by the c calling convention. | |
55 // Windows is different from linux/solaris. So much for standards... | |
56 | |
57 #ifdef _WIN64 | |
58 | |
59 REGISTER_DECLARATION(Register, c_rarg0, rcx); | |
60 REGISTER_DECLARATION(Register, c_rarg1, rdx); | |
61 REGISTER_DECLARATION(Register, c_rarg2, r8); | |
62 REGISTER_DECLARATION(Register, c_rarg3, r9); | |
63 | |
304 | 64 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); |
65 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); | |
66 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); | |
67 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); | |
0 | 68 |
69 #else | |
70 | |
71 REGISTER_DECLARATION(Register, c_rarg0, rdi); | |
72 REGISTER_DECLARATION(Register, c_rarg1, rsi); | |
73 REGISTER_DECLARATION(Register, c_rarg2, rdx); | |
74 REGISTER_DECLARATION(Register, c_rarg3, rcx); | |
75 REGISTER_DECLARATION(Register, c_rarg4, r8); | |
76 REGISTER_DECLARATION(Register, c_rarg5, r9); | |
77 | |
304 | 78 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); |
79 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); | |
80 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); | |
81 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); | |
82 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4); | |
83 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5); | |
84 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6); | |
85 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7); | |
0 | 86 |
87 #endif // _WIN64 | |
88 | |
89 // Symbolically name the register arguments used by the Java calling convention. | |
90 // We have control over the convention for java so we can do what we please. | |
91 // What pleases us is to offset the java calling convention so that when | |
92 // we call a suitable jni method the arguments are lined up and we don't | |
93 // have to do little shuffling. A suitable jni method is non-static and a | |
94 // small number of arguments (two fewer args on windows) | |
95 // | |
96 // |-------------------------------------------------------| | |
97 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 | | |
98 // |-------------------------------------------------------| | |
99 // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg) | |
100 // | rdi rsi rdx rcx r8 r9 | solaris/linux | |
101 // |-------------------------------------------------------| | |
102 // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 | | |
103 // |-------------------------------------------------------| | |
104 | |
105 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1); | |
106 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2); | |
107 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3); | |
108 // Windows runs out of register args here | |
109 #ifdef _WIN64 | |
110 REGISTER_DECLARATION(Register, j_rarg3, rdi); | |
111 REGISTER_DECLARATION(Register, j_rarg4, rsi); | |
112 #else | |
113 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4); | |
114 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5); | |
115 #endif /* _WIN64 */ | |
116 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0); | |
117 | |
304 | 118 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0); |
119 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1); | |
120 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2); | |
121 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3); | |
122 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4); | |
123 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5); | |
124 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6); | |
125 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7); | |
0 | 126 |
127 REGISTER_DECLARATION(Register, rscratch1, r10); // volatile | |
128 REGISTER_DECLARATION(Register, rscratch2, r11); // volatile | |
129 | |
304 | 130 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved |
0 | 131 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved |
132 | |
304 | 133 #else |
134 // rscratch1 will apear in 32bit code that is dead but of course must compile | |
135 // Using noreg ensures if the dead code is incorrectly live and executed it | |
136 // will cause an assertion failure | |
137 #define rscratch1 noreg | |
2002 | 138 #define rscratch2 noreg |
304 | 139 |
0 | 140 #endif // _LP64 |
141 | |
1564 | 142 // JSR 292 fixed register usages: |
143 REGISTER_DECLARATION(Register, rbp_mh_SP_save, rbp); | |
144 | |
0 | 145 // Address is an abstraction used to represent a memory location |
146 // using any of the amd64 addressing modes with one object. | |
147 // | |
148 // Note: A register location is represented via a Register, not | |
149 // via an address for efficiency & simplicity reasons. | |
150 | |
151 class ArrayAddress; | |
152 | |
153 class Address VALUE_OBJ_CLASS_SPEC { | |
154 public: | |
155 enum ScaleFactor { | |
156 no_scale = -1, | |
157 times_1 = 0, | |
158 times_2 = 1, | |
159 times_4 = 2, | |
304 | 160 times_8 = 3, |
161 times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4) | |
0 | 162 }; |
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163 static ScaleFactor times(int size) { |
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164 assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size"); |
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165 if (size == 8) return times_8; |
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166 if (size == 4) return times_4; |
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167 if (size == 2) return times_2; |
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168 return times_1; |
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169 } |
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170 static int scale_size(ScaleFactor scale) { |
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171 assert(scale != no_scale, ""); |
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172 assert(((1 << (int)times_1) == 1 && |
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173 (1 << (int)times_2) == 2 && |
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174 (1 << (int)times_4) == 4 && |
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175 (1 << (int)times_8) == 8), ""); |
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176 return (1 << (int)scale); |
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177 } |
0 | 178 |
179 private: | |
180 Register _base; | |
181 Register _index; | |
182 ScaleFactor _scale; | |
183 int _disp; | |
184 RelocationHolder _rspec; | |
185 | |
304 | 186 // Easily misused constructors make them private |
187 // %%% can we make these go away? | |
188 NOT_LP64(Address(address loc, RelocationHolder spec);) | |
189 Address(int disp, address loc, relocInfo::relocType rtype); | |
190 Address(int disp, address loc, RelocationHolder spec); | |
0 | 191 |
192 public: | |
304 | 193 |
194 int disp() { return _disp; } | |
0 | 195 // creation |
196 Address() | |
197 : _base(noreg), | |
198 _index(noreg), | |
199 _scale(no_scale), | |
200 _disp(0) { | |
201 } | |
202 | |
203 // No default displacement otherwise Register can be implicitly | |
204 // converted to 0(Register) which is quite a different animal. | |
205 | |
206 Address(Register base, int disp) | |
207 : _base(base), | |
208 _index(noreg), | |
209 _scale(no_scale), | |
210 _disp(disp) { | |
211 } | |
212 | |
213 Address(Register base, Register index, ScaleFactor scale, int disp = 0) | |
214 : _base (base), | |
215 _index(index), | |
216 _scale(scale), | |
217 _disp (disp) { | |
218 assert(!index->is_valid() == (scale == Address::no_scale), | |
219 "inconsistent address"); | |
220 } | |
221 | |
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222 Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0) |
622
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223 : _base (base), |
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224 _index(index.register_or_noreg()), |
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225 _scale(scale), |
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226 _disp (disp + (index.constant_or_zero() * scale_size(scale))) { |
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227 if (!index.is_register()) scale = Address::no_scale; |
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228 assert(!_index->is_valid() == (scale == Address::no_scale), |
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229 "inconsistent address"); |
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230 } |
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231 |
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232 Address plus_disp(int disp) const { |
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233 Address a = (*this); |
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234 a._disp += disp; |
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235 return a; |
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236 } |
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237 |
0 | 238 // The following two overloads are used in connection with the |
239 // ByteSize type (see sizes.hpp). They simplify the use of | |
240 // ByteSize'd arguments in assembly code. Note that their equivalent | |
241 // for the optimized build are the member functions with int disp | |
242 // argument since ByteSize is mapped to an int type in that case. | |
243 // | |
244 // Note: DO NOT introduce similar overloaded functions for WordSize | |
245 // arguments as in the optimized mode, both ByteSize and WordSize | |
246 // are mapped to the same type and thus the compiler cannot make a | |
247 // distinction anymore (=> compiler errors). | |
248 | |
249 #ifdef ASSERT | |
250 Address(Register base, ByteSize disp) | |
251 : _base(base), | |
252 _index(noreg), | |
253 _scale(no_scale), | |
254 _disp(in_bytes(disp)) { | |
255 } | |
256 | |
257 Address(Register base, Register index, ScaleFactor scale, ByteSize disp) | |
258 : _base(base), | |
259 _index(index), | |
260 _scale(scale), | |
261 _disp(in_bytes(disp)) { | |
262 assert(!index->is_valid() == (scale == Address::no_scale), | |
263 "inconsistent address"); | |
264 } | |
622
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265 |
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266 Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp) |
622
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267 : _base (base), |
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268 _index(index.register_or_noreg()), |
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269 _scale(scale), |
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270 _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) { |
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271 if (!index.is_register()) scale = Address::no_scale; |
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272 assert(!_index->is_valid() == (scale == Address::no_scale), |
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273 "inconsistent address"); |
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274 } |
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275 |
0 | 276 #endif // ASSERT |
277 | |
278 // accessors | |
342
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279 bool uses(Register reg) const { return _base == reg || _index == reg; } |
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280 Register base() const { return _base; } |
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281 Register index() const { return _index; } |
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282 ScaleFactor scale() const { return _scale; } |
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283 int disp() const { return _disp; } |
0 | 284 |
285 // Convert the raw encoding form into the form expected by the constructor for | |
286 // Address. An index of 4 (rsp) corresponds to having no index, so convert | |
287 // that to noreg for the Address constructor. | |
624 | 288 static Address make_raw(int base, int index, int scale, int disp, bool disp_is_oop); |
0 | 289 |
290 static Address make_array(ArrayAddress); | |
291 | |
292 private: | |
293 bool base_needs_rex() const { | |
294 return _base != noreg && _base->encoding() >= 8; | |
295 } | |
296 | |
297 bool index_needs_rex() const { | |
298 return _index != noreg &&_index->encoding() >= 8; | |
299 } | |
300 | |
301 relocInfo::relocType reloc() const { return _rspec.type(); } | |
302 | |
303 friend class Assembler; | |
304 friend class MacroAssembler; | |
305 friend class LIR_Assembler; // base/index/scale/disp | |
306 }; | |
307 | |
308 // | |
309 // AddressLiteral has been split out from Address because operands of this type | |
310 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out | |
311 // the few instructions that need to deal with address literals are unique and the | |
312 // MacroAssembler does not have to implement every instruction in the Assembler | |
313 // in order to search for address literals that may need special handling depending | |
314 // on the instruction and the platform. As small step on the way to merging i486/amd64 | |
315 // directories. | |
316 // | |
317 class AddressLiteral VALUE_OBJ_CLASS_SPEC { | |
318 friend class ArrayAddress; | |
319 RelocationHolder _rspec; | |
320 // Typically we use AddressLiterals we want to use their rval | |
321 // However in some situations we want the lval (effect address) of the item. | |
322 // We provide a special factory for making those lvals. | |
323 bool _is_lval; | |
324 | |
325 // If the target is far we'll need to load the ea of this to | |
326 // a register to reach it. Otherwise if near we can do rip | |
327 // relative addressing. | |
328 | |
329 address _target; | |
330 | |
331 protected: | |
332 // creation | |
333 AddressLiteral() | |
334 : _is_lval(false), | |
335 _target(NULL) | |
336 {} | |
337 | |
338 public: | |
339 | |
340 | |
341 AddressLiteral(address target, relocInfo::relocType rtype); | |
342 | |
343 AddressLiteral(address target, RelocationHolder const& rspec) | |
344 : _rspec(rspec), | |
345 _is_lval(false), | |
346 _target(target) | |
347 {} | |
348 | |
349 AddressLiteral addr() { | |
350 AddressLiteral ret = *this; | |
351 ret._is_lval = true; | |
352 return ret; | |
353 } | |
354 | |
355 | |
356 private: | |
357 | |
358 address target() { return _target; } | |
359 bool is_lval() { return _is_lval; } | |
360 | |
361 relocInfo::relocType reloc() const { return _rspec.type(); } | |
362 const RelocationHolder& rspec() const { return _rspec; } | |
363 | |
364 friend class Assembler; | |
365 friend class MacroAssembler; | |
366 friend class Address; | |
367 friend class LIR_Assembler; | |
368 }; | |
369 | |
370 // Convience classes | |
371 class RuntimeAddress: public AddressLiteral { | |
372 | |
373 public: | |
374 | |
375 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {} | |
376 | |
377 }; | |
378 | |
379 class OopAddress: public AddressLiteral { | |
380 | |
381 public: | |
382 | |
383 OopAddress(address target) : AddressLiteral(target, relocInfo::oop_type){} | |
384 | |
385 }; | |
386 | |
387 class ExternalAddress: public AddressLiteral { | |
388 | |
389 public: | |
390 | |
391 ExternalAddress(address target) : AddressLiteral(target, relocInfo::external_word_type){} | |
392 | |
393 }; | |
394 | |
395 class InternalAddress: public AddressLiteral { | |
396 | |
397 public: | |
398 | |
399 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {} | |
400 | |
401 }; | |
402 | |
403 // x86 can do array addressing as a single operation since disp can be an absolute | |
404 // address amd64 can't. We create a class that expresses the concept but does extra | |
405 // magic on amd64 to get the final result | |
406 | |
407 class ArrayAddress VALUE_OBJ_CLASS_SPEC { | |
408 private: | |
409 | |
410 AddressLiteral _base; | |
411 Address _index; | |
412 | |
413 public: | |
414 | |
415 ArrayAddress() {}; | |
416 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {}; | |
417 AddressLiteral base() { return _base; } | |
418 Address index() { return _index; } | |
419 | |
420 }; | |
421 | |
304 | 422 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512 / wordSize); |
0 | 423 |
424 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction | |
425 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write | |
426 // is what you get. The Assembler is generating code into a CodeBuffer. | |
427 | |
428 class Assembler : public AbstractAssembler { | |
429 friend class AbstractAssembler; // for the non-virtual hack | |
430 friend class LIR_Assembler; // as_Address() | |
304 | 431 friend class StubGenerator; |
0 | 432 |
433 public: | |
434 enum Condition { // The x86 condition codes used for conditional jumps/moves. | |
435 zero = 0x4, | |
436 notZero = 0x5, | |
437 equal = 0x4, | |
438 notEqual = 0x5, | |
439 less = 0xc, | |
440 lessEqual = 0xe, | |
441 greater = 0xf, | |
442 greaterEqual = 0xd, | |
443 below = 0x2, | |
444 belowEqual = 0x6, | |
445 above = 0x7, | |
446 aboveEqual = 0x3, | |
447 overflow = 0x0, | |
448 noOverflow = 0x1, | |
449 carrySet = 0x2, | |
450 carryClear = 0x3, | |
451 negative = 0x8, | |
452 positive = 0x9, | |
453 parity = 0xa, | |
454 noParity = 0xb | |
455 }; | |
456 | |
457 enum Prefix { | |
458 // segment overrides | |
459 CS_segment = 0x2e, | |
460 SS_segment = 0x36, | |
461 DS_segment = 0x3e, | |
462 ES_segment = 0x26, | |
463 FS_segment = 0x64, | |
464 GS_segment = 0x65, | |
465 | |
466 REX = 0x40, | |
467 | |
468 REX_B = 0x41, | |
469 REX_X = 0x42, | |
470 REX_XB = 0x43, | |
471 REX_R = 0x44, | |
472 REX_RB = 0x45, | |
473 REX_RX = 0x46, | |
474 REX_RXB = 0x47, | |
475 | |
476 REX_W = 0x48, | |
477 | |
478 REX_WB = 0x49, | |
479 REX_WX = 0x4A, | |
480 REX_WXB = 0x4B, | |
481 REX_WR = 0x4C, | |
482 REX_WRB = 0x4D, | |
483 REX_WRX = 0x4E, | |
484 REX_WRXB = 0x4F | |
485 }; | |
486 | |
487 enum WhichOperand { | |
488 // input to locate_operand, and format code for relocations | |
304 | 489 imm_operand = 0, // embedded 32-bit|64-bit immediate operand |
0 | 490 disp32_operand = 1, // embedded 32-bit displacement or address |
491 call32_operand = 2, // embedded 32-bit self-relative displacement | |
304 | 492 #ifndef _LP64 |
0 | 493 _WhichOperand_limit = 3 |
304 | 494 #else |
495 narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop | |
496 _WhichOperand_limit = 4 | |
497 #endif | |
0 | 498 }; |
499 | |
304 | 500 |
501 | |
502 // NOTE: The general philopsophy of the declarations here is that 64bit versions | |
503 // of instructions are freely declared without the need for wrapping them an ifdef. | |
504 // (Some dangerous instructions are ifdef's out of inappropriate jvm's.) | |
505 // In the .cpp file the implementations are wrapped so that they are dropped out | |
506 // of the resulting jvm. This is done mostly to keep the footprint of KERNEL | |
507 // to the size it was prior to merging up the 32bit and 64bit assemblers. | |
508 // | |
509 // This does mean you'll get a linker/runtime error if you use a 64bit only instruction | |
510 // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down. | |
511 | |
512 private: | |
513 | |
514 | |
515 // 64bit prefixes | |
516 int prefix_and_encode(int reg_enc, bool byteinst = false); | |
517 int prefixq_and_encode(int reg_enc); | |
518 | |
519 int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false); | |
520 int prefixq_and_encode(int dst_enc, int src_enc); | |
521 | |
522 void prefix(Register reg); | |
523 void prefix(Address adr); | |
524 void prefixq(Address adr); | |
525 | |
526 void prefix(Address adr, Register reg, bool byteinst = false); | |
527 void prefixq(Address adr, Register reg); | |
528 | |
529 void prefix(Address adr, XMMRegister reg); | |
530 | |
531 void prefetch_prefix(Address src); | |
532 | |
533 // Helper functions for groups of instructions | |
534 void emit_arith_b(int op1, int op2, Register dst, int imm8); | |
535 | |
536 void emit_arith(int op1, int op2, Register dst, int32_t imm32); | |
537 // only 32bit?? | |
538 void emit_arith(int op1, int op2, Register dst, jobject obj); | |
539 void emit_arith(int op1, int op2, Register dst, Register src); | |
540 | |
541 void emit_operand(Register reg, | |
542 Register base, Register index, Address::ScaleFactor scale, | |
543 int disp, | |
544 RelocationHolder const& rspec, | |
545 int rip_relative_correction = 0); | |
546 | |
547 void emit_operand(Register reg, Address adr, int rip_relative_correction = 0); | |
548 | |
549 // operands that only take the original 32bit registers | |
550 void emit_operand32(Register reg, Address adr); | |
551 | |
552 void emit_operand(XMMRegister reg, | |
553 Register base, Register index, Address::ScaleFactor scale, | |
554 int disp, | |
555 RelocationHolder const& rspec); | |
556 | |
557 void emit_operand(XMMRegister reg, Address adr); | |
558 | |
559 void emit_operand(MMXRegister reg, Address adr); | |
560 | |
561 // workaround gcc (3.2.1-7) bug | |
562 void emit_operand(Address adr, MMXRegister reg); | |
563 | |
564 | |
565 // Immediate-to-memory forms | |
566 void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32); | |
567 | |
568 void emit_farith(int b1, int b2, int i); | |
569 | |
570 | |
571 protected: | |
572 #ifdef ASSERT | |
573 void check_relocation(RelocationHolder const& rspec, int format); | |
574 #endif | |
575 | |
576 inline void emit_long64(jlong x); | |
577 | |
578 void emit_data(jint data, relocInfo::relocType rtype, int format); | |
579 void emit_data(jint data, RelocationHolder const& rspec, int format); | |
580 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0); | |
581 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0); | |
582 | |
583 | |
584 bool reachable(AddressLiteral adr) NOT_LP64({ return true;}); | |
585 | |
586 // These are all easily abused and hence protected | |
587 | |
588 // 32BIT ONLY SECTION | |
589 #ifndef _LP64 | |
590 // Make these disappear in 64bit mode since they would never be correct | |
591 void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY | |
592 void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY | |
593 | |
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594 void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY |
304 | 595 void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY |
596 | |
597 void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY | |
598 #else | |
599 // 64BIT ONLY SECTION | |
600 void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY | |
642
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601 |
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602 void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec); |
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603 void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec); |
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604 |
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605 void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec); |
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606 void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec); |
304 | 607 #endif // _LP64 |
608 | |
609 // These are unique in that we are ensured by the caller that the 32bit | |
610 // relative in these instructions will always be able to reach the potentially | |
611 // 64bit address described by entry. Since they can take a 64bit address they | |
612 // don't have the 32 suffix like the other instructions in this class. | |
613 | |
614 void call_literal(address entry, RelocationHolder const& rspec); | |
615 void jmp_literal(address entry, RelocationHolder const& rspec); | |
616 | |
617 // Avoid using directly section | |
618 // Instructions in this section are actually usable by anyone without danger | |
619 // of failure but have performance issues that are addressed my enhanced | |
620 // instructions which will do the proper thing base on the particular cpu. | |
621 // We protect them because we don't trust you... | |
622 | |
623 // Don't use next inc() and dec() methods directly. INC & DEC instructions | |
624 // could cause a partial flag stall since they don't set CF flag. | |
625 // Use MacroAssembler::decrement() & MacroAssembler::increment() methods | |
626 // which call inc() & dec() or add() & sub() in accordance with | |
627 // the product flag UseIncDec value. | |
628 | |
629 void decl(Register dst); | |
630 void decl(Address dst); | |
631 void decq(Register dst); | |
632 void decq(Address dst); | |
633 | |
634 void incl(Register dst); | |
635 void incl(Address dst); | |
636 void incq(Register dst); | |
637 void incq(Address dst); | |
638 | |
639 // New cpus require use of movsd and movss to avoid partial register stall | |
640 // when loading from memory. But for old Opteron use movlpd instead of movsd. | |
641 // The selection is done in MacroAssembler::movdbl() and movflt(). | |
642 | |
643 // Move Scalar Single-Precision Floating-Point Values | |
644 void movss(XMMRegister dst, Address src); | |
645 void movss(XMMRegister dst, XMMRegister src); | |
646 void movss(Address dst, XMMRegister src); | |
647 | |
648 // Move Scalar Double-Precision Floating-Point Values | |
649 void movsd(XMMRegister dst, Address src); | |
650 void movsd(XMMRegister dst, XMMRegister src); | |
651 void movsd(Address dst, XMMRegister src); | |
652 void movlpd(XMMRegister dst, Address src); | |
653 | |
654 // New cpus require use of movaps and movapd to avoid partial register stall | |
655 // when moving between registers. | |
656 void movaps(XMMRegister dst, XMMRegister src); | |
657 void movapd(XMMRegister dst, XMMRegister src); | |
658 | |
659 // End avoid using directly | |
660 | |
661 | |
662 // Instruction prefixes | |
663 void prefix(Prefix p); | |
664 | |
0 | 665 public: |
666 | |
667 // Creation | |
668 Assembler(CodeBuffer* code) : AbstractAssembler(code) {} | |
669 | |
670 // Decoding | |
671 static address locate_operand(address inst, WhichOperand which); | |
672 static address locate_next_instruction(address inst); | |
673 | |
304 | 674 // Utilities |
675 | |
676 #ifdef _LP64 | |
677 static bool is_simm(int64_t x, int nbits) { return -( CONST64(1) << (nbits-1) ) <= x && x < ( CONST64(1) << (nbits-1) ); } | |
678 static bool is_simm32(int64_t x) { return x == (int64_t)(int32_t)x; } | |
679 #else | |
680 static bool is_simm(int32_t x, int nbits) { return -( 1 << (nbits-1) ) <= x && x < ( 1 << (nbits-1) ); } | |
681 static bool is_simm32(int32_t x) { return true; } | |
682 #endif // LP64 | |
683 | |
684 // Generic instructions | |
685 // Does 32bit or 64bit as needed for the platform. In some sense these | |
686 // belong in macro assembler but there is no need for both varieties to exist | |
687 | |
688 void lea(Register dst, Address src); | |
689 | |
690 void mov(Register dst, Register src); | |
691 | |
692 void pusha(); | |
693 void popa(); | |
694 | |
695 void pushf(); | |
696 void popf(); | |
697 | |
698 void push(int32_t imm32); | |
699 | |
700 void push(Register src); | |
701 | |
702 void pop(Register dst); | |
703 | |
704 // These are dummies to prevent surprise implicit conversions to Register | |
705 void push(void* v); | |
706 void pop(void* v); | |
707 | |
708 | |
709 // These do register sized moves/scans | |
710 void rep_mov(); | |
711 void rep_set(); | |
712 void repne_scan(); | |
713 #ifdef _LP64 | |
714 void repne_scanl(); | |
715 #endif | |
716 | |
717 // Vanilla instructions in lexical order | |
718 | |
719 void adcl(Register dst, int32_t imm32); | |
0 | 720 void adcl(Register dst, Address src); |
721 void adcl(Register dst, Register src); | |
722 | |
304 | 723 void adcq(Register dst, int32_t imm32); |
724 void adcq(Register dst, Address src); | |
725 void adcq(Register dst, Register src); | |
726 | |
727 | |
728 void addl(Address dst, int32_t imm32); | |
0 | 729 void addl(Address dst, Register src); |
304 | 730 void addl(Register dst, int32_t imm32); |
0 | 731 void addl(Register dst, Address src); |
732 void addl(Register dst, Register src); | |
733 | |
304 | 734 void addq(Address dst, int32_t imm32); |
735 void addq(Address dst, Register src); | |
736 void addq(Register dst, int32_t imm32); | |
737 void addq(Register dst, Address src); | |
738 void addq(Register dst, Register src); | |
739 | |
740 | |
0 | 741 void addr_nop_4(); |
742 void addr_nop_5(); | |
743 void addr_nop_7(); | |
744 void addr_nop_8(); | |
745 | |
304 | 746 // Add Scalar Double-Precision Floating-Point Values |
747 void addsd(XMMRegister dst, Address src); | |
748 void addsd(XMMRegister dst, XMMRegister src); | |
749 | |
750 // Add Scalar Single-Precision Floating-Point Values | |
751 void addss(XMMRegister dst, Address src); | |
752 void addss(XMMRegister dst, XMMRegister src); | |
753 | |
754 void andl(Register dst, int32_t imm32); | |
755 void andl(Register dst, Address src); | |
756 void andl(Register dst, Register src); | |
757 | |
758 void andq(Register dst, int32_t imm32); | |
759 void andq(Register dst, Address src); | |
760 void andq(Register dst, Register src); | |
761 | |
762 | |
763 // Bitwise Logical AND of Packed Double-Precision Floating-Point Values | |
764 void andpd(XMMRegister dst, Address src); | |
765 void andpd(XMMRegister dst, XMMRegister src); | |
766 | |
775
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767 void bsfl(Register dst, Register src); |
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768 void bsrl(Register dst, Register src); |
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769 |
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770 #ifdef _LP64 |
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771 void bsfq(Register dst, Register src); |
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772 void bsrq(Register dst, Register src); |
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773 #endif |
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774 |
304 | 775 void bswapl(Register reg); |
776 | |
777 void bswapq(Register reg); | |
778 | |
0 | 779 void call(Label& L, relocInfo::relocType rtype); |
780 void call(Register reg); // push pc; pc <- reg | |
781 void call(Address adr); // push pc; pc <- adr | |
782 | |
304 | 783 void cdql(); |
784 | |
785 void cdqq(); | |
786 | |
787 void cld() { emit_byte(0xfc); } | |
788 | |
789 void clflush(Address adr); | |
790 | |
791 void cmovl(Condition cc, Register dst, Register src); | |
792 void cmovl(Condition cc, Register dst, Address src); | |
793 | |
794 void cmovq(Condition cc, Register dst, Register src); | |
795 void cmovq(Condition cc, Register dst, Address src); | |
796 | |
797 | |
798 void cmpb(Address dst, int imm8); | |
799 | |
800 void cmpl(Address dst, int32_t imm32); | |
801 | |
802 void cmpl(Register dst, int32_t imm32); | |
803 void cmpl(Register dst, Register src); | |
804 void cmpl(Register dst, Address src); | |
805 | |
806 void cmpq(Address dst, int32_t imm32); | |
807 void cmpq(Address dst, Register src); | |
808 | |
809 void cmpq(Register dst, int32_t imm32); | |
810 void cmpq(Register dst, Register src); | |
811 void cmpq(Register dst, Address src); | |
812 | |
813 // these are dummies used to catch attempting to convert NULL to Register | |
814 void cmpl(Register dst, void* junk); // dummy | |
815 void cmpq(Register dst, void* junk); // dummy | |
816 | |
817 void cmpw(Address dst, int imm16); | |
818 | |
819 void cmpxchg8 (Address adr); | |
820 | |
821 void cmpxchgl(Register reg, Address adr); | |
822 | |
823 void cmpxchgq(Register reg, Address adr); | |
824 | |
825 // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS | |
826 void comisd(XMMRegister dst, Address src); | |
827 | |
828 // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS | |
829 void comiss(XMMRegister dst, Address src); | |
830 | |
831 // Identify processor type and features | |
832 void cpuid() { | |
833 emit_byte(0x0F); | |
834 emit_byte(0xA2); | |
835 } | |
836 | |
837 // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value | |
838 void cvtsd2ss(XMMRegister dst, XMMRegister src); | |
839 | |
840 // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value | |
841 void cvtsi2sdl(XMMRegister dst, Register src); | |
842 void cvtsi2sdq(XMMRegister dst, Register src); | |
843 | |
844 // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value | |
845 void cvtsi2ssl(XMMRegister dst, Register src); | |
846 void cvtsi2ssq(XMMRegister dst, Register src); | |
847 | |
848 // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value | |
849 void cvtdq2pd(XMMRegister dst, XMMRegister src); | |
850 | |
851 // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value | |
852 void cvtdq2ps(XMMRegister dst, XMMRegister src); | |
853 | |
854 // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value | |
855 void cvtss2sd(XMMRegister dst, XMMRegister src); | |
856 | |
857 // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer | |
858 void cvttsd2sil(Register dst, Address src); | |
859 void cvttsd2sil(Register dst, XMMRegister src); | |
860 void cvttsd2siq(Register dst, XMMRegister src); | |
861 | |
862 // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer | |
863 void cvttss2sil(Register dst, XMMRegister src); | |
864 void cvttss2siq(Register dst, XMMRegister src); | |
865 | |
866 // Divide Scalar Double-Precision Floating-Point Values | |
867 void divsd(XMMRegister dst, Address src); | |
868 void divsd(XMMRegister dst, XMMRegister src); | |
869 | |
870 // Divide Scalar Single-Precision Floating-Point Values | |
871 void divss(XMMRegister dst, Address src); | |
872 void divss(XMMRegister dst, XMMRegister src); | |
873 | |
874 void emms(); | |
875 | |
876 void fabs(); | |
877 | |
878 void fadd(int i); | |
879 | |
880 void fadd_d(Address src); | |
881 void fadd_s(Address src); | |
882 | |
883 // "Alternate" versions of x87 instructions place result down in FPU | |
884 // stack instead of on TOS | |
885 | |
886 void fadda(int i); // "alternate" fadd | |
887 void faddp(int i = 1); | |
888 | |
889 void fchs(); | |
890 | |
891 void fcom(int i); | |
892 | |
893 void fcomp(int i = 1); | |
894 void fcomp_d(Address src); | |
895 void fcomp_s(Address src); | |
896 | |
897 void fcompp(); | |
898 | |
899 void fcos(); | |
900 | |
901 void fdecstp(); | |
902 | |
903 void fdiv(int i); | |
904 void fdiv_d(Address src); | |
905 void fdivr_s(Address src); | |
906 void fdiva(int i); // "alternate" fdiv | |
907 void fdivp(int i = 1); | |
908 | |
909 void fdivr(int i); | |
910 void fdivr_d(Address src); | |
911 void fdiv_s(Address src); | |
912 | |
913 void fdivra(int i); // "alternate" reversed fdiv | |
914 | |
915 void fdivrp(int i = 1); | |
916 | |
917 void ffree(int i = 0); | |
918 | |
919 void fild_d(Address adr); | |
920 void fild_s(Address adr); | |
921 | |
922 void fincstp(); | |
923 | |
924 void finit(); | |
925 | |
926 void fist_s (Address adr); | |
927 void fistp_d(Address adr); | |
928 void fistp_s(Address adr); | |
929 | |
930 void fld1(); | |
931 | |
932 void fld_d(Address adr); | |
933 void fld_s(Address adr); | |
934 void fld_s(int index); | |
935 void fld_x(Address adr); // extended-precision (80-bit) format | |
936 | |
937 void fldcw(Address src); | |
938 | |
939 void fldenv(Address src); | |
940 | |
941 void fldlg2(); | |
942 | |
943 void fldln2(); | |
944 | |
945 void fldz(); | |
946 | |
947 void flog(); | |
948 void flog10(); | |
949 | |
950 void fmul(int i); | |
951 | |
952 void fmul_d(Address src); | |
953 void fmul_s(Address src); | |
954 | |
955 void fmula(int i); // "alternate" fmul | |
956 | |
957 void fmulp(int i = 1); | |
958 | |
959 void fnsave(Address dst); | |
960 | |
961 void fnstcw(Address src); | |
962 | |
963 void fnstsw_ax(); | |
964 | |
965 void fprem(); | |
966 void fprem1(); | |
967 | |
968 void frstor(Address src); | |
969 | |
970 void fsin(); | |
971 | |
972 void fsqrt(); | |
973 | |
974 void fst_d(Address adr); | |
975 void fst_s(Address adr); | |
976 | |
977 void fstp_d(Address adr); | |
978 void fstp_d(int index); | |
979 void fstp_s(Address adr); | |
980 void fstp_x(Address adr); // extended-precision (80-bit) format | |
981 | |
982 void fsub(int i); | |
983 void fsub_d(Address src); | |
984 void fsub_s(Address src); | |
985 | |
986 void fsuba(int i); // "alternate" fsub | |
987 | |
988 void fsubp(int i = 1); | |
989 | |
990 void fsubr(int i); | |
991 void fsubr_d(Address src); | |
992 void fsubr_s(Address src); | |
993 | |
994 void fsubra(int i); // "alternate" reversed fsub | |
995 | |
996 void fsubrp(int i = 1); | |
997 | |
998 void ftan(); | |
999 | |
1000 void ftst(); | |
1001 | |
1002 void fucomi(int i = 1); | |
1003 void fucomip(int i = 1); | |
1004 | |
1005 void fwait(); | |
1006 | |
1007 void fxch(int i = 1); | |
1008 | |
1009 void fxrstor(Address src); | |
1010 | |
1011 void fxsave(Address dst); | |
1012 | |
1013 void fyl2x(); | |
1014 | |
1015 void hlt(); | |
1016 | |
1017 void idivl(Register src); | |
1920 | 1018 void divl(Register src); // Unsigned division |
304 | 1019 |
1020 void idivq(Register src); | |
1021 | |
1022 void imull(Register dst, Register src); | |
1023 void imull(Register dst, Register src, int value); | |
1024 | |
1025 void imulq(Register dst, Register src); | |
1026 void imulq(Register dst, Register src, int value); | |
1027 | |
0 | 1028 |
1029 // jcc is the generic conditional branch generator to run- | |
1030 // time routines, jcc is used for branches to labels. jcc | |
1031 // takes a branch opcode (cc) and a label (L) and generates | |
1032 // either a backward branch or a forward branch and links it | |
1033 // to the label fixup chain. Usage: | |
1034 // | |
1035 // Label L; // unbound label | |
1036 // jcc(cc, L); // forward branch to unbound label | |
1037 // bind(L); // bind label to the current pc | |
1038 // jcc(cc, L); // backward branch to bound label | |
1039 // bind(L); // illegal: a label may be bound only once | |
1040 // | |
1041 // Note: The same Label can be used for forward and backward branches | |
1042 // but it may be bound only once. | |
1043 | |
1044 void jcc(Condition cc, Label& L, | |
1045 relocInfo::relocType rtype = relocInfo::none); | |
1046 | |
1047 // Conditional jump to a 8-bit offset to L. | |
1048 // WARNING: be very careful using this for forward jumps. If the label is | |
1049 // not bound within an 8-bit offset of this instruction, a run-time error | |
1050 // will occur. | |
1051 void jccb(Condition cc, Label& L); | |
1052 | |
304 | 1053 void jmp(Address entry); // pc <- entry |
1054 | |
1055 // Label operations & relative jumps (PPUM Appendix D) | |
1056 void jmp(Label& L, relocInfo::relocType rtype = relocInfo::none); // unconditional jump to L | |
1057 | |
1058 void jmp(Register entry); // pc <- entry | |
1059 | |
1060 // Unconditional 8-bit offset jump to L. | |
1061 // WARNING: be very careful using this for forward jumps. If the label is | |
1062 // not bound within an 8-bit offset of this instruction, a run-time error | |
1063 // will occur. | |
1064 void jmpb(Label& L); | |
1065 | |
1066 void ldmxcsr( Address src ); | |
1067 | |
1068 void leal(Register dst, Address src); | |
1069 | |
1070 void leaq(Register dst, Address src); | |
1071 | |
1072 void lfence() { | |
1073 emit_byte(0x0F); | |
1074 emit_byte(0xAE); | |
1075 emit_byte(0xE8); | |
1076 } | |
1077 | |
1078 void lock(); | |
1079 | |
775
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1080 void lzcntl(Register dst, Register src); |
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1081 |
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1082 #ifdef _LP64 |
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1083 void lzcntq(Register dst, Register src); |
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1084 #endif |
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1085 |
304 | 1086 enum Membar_mask_bits { |
1087 StoreStore = 1 << 3, | |
1088 LoadStore = 1 << 2, | |
1089 StoreLoad = 1 << 1, | |
1090 LoadLoad = 1 << 0 | |
1091 }; | |
1092 | |
671
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1093 // Serializes memory and blows flags |
304 | 1094 void membar(Membar_mask_bits order_constraint) { |
671
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1095 if (os::is_MP()) { |
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1096 // We only have to handle StoreLoad |
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1097 if (order_constraint & StoreLoad) { |
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1098 // All usable chips support "locked" instructions which suffice |
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1099 // as barriers, and are much faster than the alternative of |
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1100 // using cpuid instruction. We use here a locked add [esp],0. |
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1101 // This is conveniently otherwise a no-op except for blowing |
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1102 // flags. |
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1103 // Any change to this code may need to revisit other places in |
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1104 // the code where this idiom is used, in particular the |
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1105 // orderAccess code. |
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1106 lock(); |
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1107 addl(Address(rsp, 0), 0);// Assert the lock# signal here |
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1108 } |
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1109 } |
304 | 1110 } |
1111 | |
1112 void mfence(); | |
1113 | |
1114 // Moves | |
1115 | |
1116 void mov64(Register dst, int64_t imm64); | |
1117 | |
1118 void movb(Address dst, Register src); | |
1119 void movb(Address dst, int imm8); | |
1120 void movb(Register dst, Address src); | |
1121 | |
1122 void movdl(XMMRegister dst, Register src); | |
1123 void movdl(Register dst, XMMRegister src); | |
1124 | |
1125 // Move Double Quadword | |
1126 void movdq(XMMRegister dst, Register src); | |
1127 void movdq(Register dst, XMMRegister src); | |
1128 | |
1129 // Move Aligned Double Quadword | |
1130 void movdqa(Address dst, XMMRegister src); | |
1131 void movdqa(XMMRegister dst, Address src); | |
1132 void movdqa(XMMRegister dst, XMMRegister src); | |
1133 | |
405 | 1134 // Move Unaligned Double Quadword |
1135 void movdqu(Address dst, XMMRegister src); | |
1136 void movdqu(XMMRegister dst, Address src); | |
1137 void movdqu(XMMRegister dst, XMMRegister src); | |
1138 | |
304 | 1139 void movl(Register dst, int32_t imm32); |
1140 void movl(Address dst, int32_t imm32); | |
1141 void movl(Register dst, Register src); | |
1142 void movl(Register dst, Address src); | |
1143 void movl(Address dst, Register src); | |
1144 | |
1145 // These dummies prevent using movl from converting a zero (like NULL) into Register | |
1146 // by giving the compiler two choices it can't resolve | |
1147 | |
1148 void movl(Address dst, void* junk); | |
1149 void movl(Register dst, void* junk); | |
1150 | |
1151 #ifdef _LP64 | |
1152 void movq(Register dst, Register src); | |
1153 void movq(Register dst, Address src); | |
1154 void movq(Address dst, Register src); | |
1155 #endif | |
1156 | |
1157 void movq(Address dst, MMXRegister src ); | |
1158 void movq(MMXRegister dst, Address src ); | |
1159 | |
1160 #ifdef _LP64 | |
1161 // These dummies prevent using movq from converting a zero (like NULL) into Register | |
1162 // by giving the compiler two choices it can't resolve | |
1163 | |
1164 void movq(Address dst, void* dummy); | |
1165 void movq(Register dst, void* dummy); | |
1166 #endif | |
1167 | |
1168 // Move Quadword | |
1169 void movq(Address dst, XMMRegister src); | |
1170 void movq(XMMRegister dst, Address src); | |
1171 | |
1172 void movsbl(Register dst, Address src); | |
1173 void movsbl(Register dst, Register src); | |
1174 | |
1175 #ifdef _LP64 | |
624 | 1176 void movsbq(Register dst, Address src); |
1177 void movsbq(Register dst, Register src); | |
1178 | |
304 | 1179 // Move signed 32bit immediate to 64bit extending sign |
1180 void movslq(Address dst, int32_t imm64); | |
1181 void movslq(Register dst, int32_t imm64); | |
1182 | |
1183 void movslq(Register dst, Address src); | |
1184 void movslq(Register dst, Register src); | |
1185 void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous | |
1186 #endif | |
1187 | |
1188 void movswl(Register dst, Address src); | |
1189 void movswl(Register dst, Register src); | |
1190 | |
624 | 1191 #ifdef _LP64 |
1192 void movswq(Register dst, Address src); | |
1193 void movswq(Register dst, Register src); | |
1194 #endif | |
1195 | |
304 | 1196 void movw(Address dst, int imm16); |
1197 void movw(Register dst, Address src); | |
1198 void movw(Address dst, Register src); | |
1199 | |
1200 void movzbl(Register dst, Address src); | |
1201 void movzbl(Register dst, Register src); | |
1202 | |
624 | 1203 #ifdef _LP64 |
1204 void movzbq(Register dst, Address src); | |
1205 void movzbq(Register dst, Register src); | |
1206 #endif | |
1207 | |
304 | 1208 void movzwl(Register dst, Address src); |
1209 void movzwl(Register dst, Register src); | |
1210 | |
624 | 1211 #ifdef _LP64 |
1212 void movzwq(Register dst, Address src); | |
1213 void movzwq(Register dst, Register src); | |
1214 #endif | |
1215 | |
304 | 1216 void mull(Address src); |
1217 void mull(Register src); | |
1218 | |
1219 // Multiply Scalar Double-Precision Floating-Point Values | |
1220 void mulsd(XMMRegister dst, Address src); | |
1221 void mulsd(XMMRegister dst, XMMRegister src); | |
1222 | |
1223 // Multiply Scalar Single-Precision Floating-Point Values | |
1224 void mulss(XMMRegister dst, Address src); | |
1225 void mulss(XMMRegister dst, XMMRegister src); | |
1226 | |
1227 void negl(Register dst); | |
1228 | |
1229 #ifdef _LP64 | |
1230 void negq(Register dst); | |
1231 #endif | |
1232 | |
1233 void nop(int i = 1); | |
1234 | |
1235 void notl(Register dst); | |
1236 | |
1237 #ifdef _LP64 | |
1238 void notq(Register dst); | |
1239 #endif | |
1240 | |
1241 void orl(Address dst, int32_t imm32); | |
1242 void orl(Register dst, int32_t imm32); | |
1243 void orl(Register dst, Address src); | |
1244 void orl(Register dst, Register src); | |
1245 | |
1246 void orq(Address dst, int32_t imm32); | |
1247 void orq(Register dst, int32_t imm32); | |
1248 void orq(Register dst, Address src); | |
1249 void orq(Register dst, Register src); | |
1250 | |
681 | 1251 // SSE4.2 string instructions |
1252 void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8); | |
1253 void pcmpestri(XMMRegister xmm1, Address src, int imm8); | |
1254 | |
1060 | 1255 #ifndef _LP64 // no 32bit push/pop on amd64 |
304 | 1256 void popl(Address dst); |
1060 | 1257 #endif |
304 | 1258 |
1259 #ifdef _LP64 | |
1260 void popq(Address dst); | |
1261 #endif | |
1262 | |
643
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1263 void popcntl(Register dst, Address src); |
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1264 void popcntl(Register dst, Register src); |
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1265 |
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1266 #ifdef _LP64 |
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1267 void popcntq(Register dst, Address src); |
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1268 void popcntq(Register dst, Register src); |
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1269 #endif |
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1270 |
304 | 1271 // Prefetches (SSE, SSE2, 3DNOW only) |
1272 | |
1273 void prefetchnta(Address src); | |
1274 void prefetchr(Address src); | |
1275 void prefetcht0(Address src); | |
1276 void prefetcht1(Address src); | |
1277 void prefetcht2(Address src); | |
1278 void prefetchw(Address src); | |
1279 | |
1280 // Shuffle Packed Doublewords | |
1281 void pshufd(XMMRegister dst, XMMRegister src, int mode); | |
1282 void pshufd(XMMRegister dst, Address src, int mode); | |
1283 | |
1284 // Shuffle Packed Low Words | |
1285 void pshuflw(XMMRegister dst, XMMRegister src, int mode); | |
1286 void pshuflw(XMMRegister dst, Address src, int mode); | |
1287 | |
1288 // Shift Right Logical Quadword Immediate | |
1289 void psrlq(XMMRegister dst, int shift); | |
1290 | |
681 | 1291 // Logical Compare Double Quadword |
1292 void ptest(XMMRegister dst, XMMRegister src); | |
1293 void ptest(XMMRegister dst, Address src); | |
1294 | |
304 | 1295 // Interleave Low Bytes |
1296 void punpcklbw(XMMRegister dst, XMMRegister src); | |
1297 | |
1060 | 1298 #ifndef _LP64 // no 32bit push/pop on amd64 |
304 | 1299 void pushl(Address src); |
1060 | 1300 #endif |
304 | 1301 |
1302 void pushq(Address src); | |
1303 | |
1304 // Xor Packed Byte Integer Values | |
1305 void pxor(XMMRegister dst, Address src); | |
1306 void pxor(XMMRegister dst, XMMRegister src); | |
1307 | |
1308 void rcll(Register dst, int imm8); | |
1309 | |
1310 void rclq(Register dst, int imm8); | |
1311 | |
1312 void ret(int imm16); | |
0 | 1313 |
1314 void sahf(); | |
1315 | |
304 | 1316 void sarl(Register dst, int imm8); |
1317 void sarl(Register dst); | |
1318 | |
1319 void sarq(Register dst, int imm8); | |
1320 void sarq(Register dst); | |
1321 | |
1322 void sbbl(Address dst, int32_t imm32); | |
1323 void sbbl(Register dst, int32_t imm32); | |
1324 void sbbl(Register dst, Address src); | |
1325 void sbbl(Register dst, Register src); | |
1326 | |
1327 void sbbq(Address dst, int32_t imm32); | |
1328 void sbbq(Register dst, int32_t imm32); | |
1329 void sbbq(Register dst, Address src); | |
1330 void sbbq(Register dst, Register src); | |
1331 | |
1332 void setb(Condition cc, Register dst); | |
1333 | |
1334 void shldl(Register dst, Register src); | |
1335 | |
1336 void shll(Register dst, int imm8); | |
1337 void shll(Register dst); | |
1338 | |
1339 void shlq(Register dst, int imm8); | |
1340 void shlq(Register dst); | |
1341 | |
1342 void shrdl(Register dst, Register src); | |
1343 | |
1344 void shrl(Register dst, int imm8); | |
1345 void shrl(Register dst); | |
1346 | |
1347 void shrq(Register dst, int imm8); | |
1348 void shrq(Register dst); | |
1349 | |
1350 void smovl(); // QQQ generic? | |
1351 | |
1352 // Compute Square Root of Scalar Double-Precision Floating-Point Value | |
1353 void sqrtsd(XMMRegister dst, Address src); | |
1354 void sqrtsd(XMMRegister dst, XMMRegister src); | |
1355 | |
2008 | 1356 // Compute Square Root of Scalar Single-Precision Floating-Point Value |
1357 void sqrtss(XMMRegister dst, Address src); | |
1358 void sqrtss(XMMRegister dst, XMMRegister src); | |
1359 | |
304 | 1360 void std() { emit_byte(0xfd); } |
1361 | |
1362 void stmxcsr( Address dst ); | |
1363 | |
1364 void subl(Address dst, int32_t imm32); | |
1365 void subl(Address dst, Register src); | |
1366 void subl(Register dst, int32_t imm32); | |
1367 void subl(Register dst, Address src); | |
1368 void subl(Register dst, Register src); | |
1369 | |
1370 void subq(Address dst, int32_t imm32); | |
1371 void subq(Address dst, Register src); | |
1372 void subq(Register dst, int32_t imm32); | |
1373 void subq(Register dst, Address src); | |
1374 void subq(Register dst, Register src); | |
1375 | |
1376 | |
1377 // Subtract Scalar Double-Precision Floating-Point Values | |
1378 void subsd(XMMRegister dst, Address src); | |
0 | 1379 void subsd(XMMRegister dst, XMMRegister src); |
1380 | |
304 | 1381 // Subtract Scalar Single-Precision Floating-Point Values |
1382 void subss(XMMRegister dst, Address src); | |
1383 void subss(XMMRegister dst, XMMRegister src); | |
1384 | |
1385 void testb(Register dst, int imm8); | |
1386 | |
1387 void testl(Register dst, int32_t imm32); | |
1388 void testl(Register dst, Register src); | |
1389 void testl(Register dst, Address src); | |
1390 | |
1391 void testq(Register dst, int32_t imm32); | |
1392 void testq(Register dst, Register src); | |
1393 | |
1394 | |
1395 // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS | |
1396 void ucomisd(XMMRegister dst, Address src); | |
0 | 1397 void ucomisd(XMMRegister dst, XMMRegister src); |
1398 | |
304 | 1399 // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS |
1400 void ucomiss(XMMRegister dst, Address src); | |
1401 void ucomiss(XMMRegister dst, XMMRegister src); | |
1402 | |
1403 void xaddl(Address dst, Register src); | |
1404 | |
1405 void xaddq(Address dst, Register src); | |
1406 | |
1407 void xchgl(Register reg, Address adr); | |
1408 void xchgl(Register dst, Register src); | |
1409 | |
1410 void xchgq(Register reg, Address adr); | |
1411 void xchgq(Register dst, Register src); | |
1412 | |
1413 void xorl(Register dst, int32_t imm32); | |
1414 void xorl(Register dst, Address src); | |
1415 void xorl(Register dst, Register src); | |
1416 | |
1417 void xorq(Register dst, Address src); | |
1418 void xorq(Register dst, Register src); | |
1419 | |
1420 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values | |
1421 void xorpd(XMMRegister dst, Address src); | |
1422 void xorpd(XMMRegister dst, XMMRegister src); | |
1423 | |
1424 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values | |
1425 void xorps(XMMRegister dst, Address src); | |
0 | 1426 void xorps(XMMRegister dst, XMMRegister src); |
304 | 1427 |
1428 void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0 | |
0 | 1429 }; |
1430 | |
1431 | |
1432 // MacroAssembler extends Assembler by frequently used macros. | |
1433 // | |
1434 // Instructions for which a 'better' code sequence exists depending | |
1435 // on arguments should also go in here. | |
1436 | |
1437 class MacroAssembler: public Assembler { | |
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1438 friend class LIR_Assembler; |
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1439 friend class Runtime1; // as_Address() |
0 | 1440 protected: |
1441 | |
1442 Address as_Address(AddressLiteral adr); | |
1443 Address as_Address(ArrayAddress adr); | |
1444 | |
1445 // Support for VM calls | |
1446 // | |
1447 // This is the base routine called by the different versions of call_VM_leaf. The interpreter | |
1448 // may customize this version by overriding it for its purposes (e.g., to save/restore | |
1449 // additional registers when doing a VM call). | |
1450 #ifdef CC_INTERP | |
1451 // c++ interpreter never wants to use interp_masm version of call_VM | |
1452 #define VIRTUAL | |
1453 #else | |
1454 #define VIRTUAL virtual | |
1455 #endif | |
1456 | |
1457 VIRTUAL void call_VM_leaf_base( | |
1458 address entry_point, // the entry point | |
1459 int number_of_arguments // the number of arguments to pop after the call | |
1460 ); | |
1461 | |
1462 // This is the base routine called by the different versions of call_VM. The interpreter | |
1463 // may customize this version by overriding it for its purposes (e.g., to save/restore | |
1464 // additional registers when doing a VM call). | |
1465 // | |
1466 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base | |
1467 // returns the register which contains the thread upon return. If a thread register has been | |
1468 // specified, the return value will correspond to that register. If no last_java_sp is specified | |
1469 // (noreg) than rsp will be used instead. | |
1470 VIRTUAL void call_VM_base( // returns the register containing the thread upon return | |
1471 Register oop_result, // where an oop-result ends up if any; use noreg otherwise | |
1472 Register java_thread, // the thread if computed before ; use noreg otherwise | |
1473 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise | |
1474 address entry_point, // the entry point | |
1475 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call | |
1476 bool check_exceptions // whether to check for pending exceptions after return | |
1477 ); | |
1478 | |
1479 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code. | |
1480 // The implementation is only non-empty for the InterpreterMacroAssembler, | |
1481 // as only the interpreter handles PopFrame and ForceEarlyReturn requests. | |
1482 virtual void check_and_handle_popframe(Register java_thread); | |
1483 virtual void check_and_handle_earlyret(Register java_thread); | |
1484 | |
1485 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true); | |
1486 | |
1487 // helpers for FPU flag access | |
1488 // tmp is a temporary register, if none is available use noreg | |
1489 void save_rax (Register tmp); | |
1490 void restore_rax(Register tmp); | |
1491 | |
1492 public: | |
1493 MacroAssembler(CodeBuffer* code) : Assembler(code) {} | |
1494 | |
1495 // Support for NULL-checks | |
1496 // | |
1497 // Generates code that causes a NULL OS exception if the content of reg is NULL. | |
1498 // If the accessed location is M[reg + offset] and the offset is known, provide the | |
1499 // offset. No explicit code generation is needed if the offset is within a certain | |
1500 // range (0 <= offset <= page_size). | |
1501 | |
1502 void null_check(Register reg, int offset = -1); | |
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1503 static bool needs_explicit_null_check(intptr_t offset); |
0 | 1504 |
1505 // Required platform-specific helpers for Label::patch_instructions. | |
1506 // They _shadow_ the declarations in AbstractAssembler, which are undefined. | |
1507 void pd_patch_instruction(address branch, address target); | |
1508 #ifndef PRODUCT | |
1509 static void pd_print_patched_instruction(address branch); | |
1510 #endif | |
1511 | |
1512 // The following 4 methods return the offset of the appropriate move instruction | |
1513 | |
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1514 // Support for fast byte/short loading with zero extension (depending on particular CPU) |
0 | 1515 int load_unsigned_byte(Register dst, Address src); |
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1516 int load_unsigned_short(Register dst, Address src); |
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1517 |
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1518 // Support for fast byte/short loading with sign extension (depending on particular CPU) |
0 | 1519 int load_signed_byte(Register dst, Address src); |
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1520 int load_signed_short(Register dst, Address src); |
0 | 1521 |
1522 // Support for sign-extension (hi:lo = extend_sign(lo)) | |
1523 void extend_sign(Register hi, Register lo); | |
1524 | |
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1525 // Loading values by size and signed-ness |
1503 | 1526 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed); |
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1527 |
0 | 1528 // Support for inc/dec with optimal instruction selection depending on value |
304 | 1529 |
1530 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; } | |
1531 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; } | |
1532 | |
1533 void decrementl(Address dst, int value = 1); | |
1534 void decrementl(Register reg, int value = 1); | |
1535 | |
1536 void decrementq(Register reg, int value = 1); | |
1537 void decrementq(Address dst, int value = 1); | |
1538 | |
1539 void incrementl(Address dst, int value = 1); | |
1540 void incrementl(Register reg, int value = 1); | |
1541 | |
1542 void incrementq(Register reg, int value = 1); | |
1543 void incrementq(Address dst, int value = 1); | |
1544 | |
0 | 1545 |
1546 // Support optimal SSE move instructions. | |
1547 void movflt(XMMRegister dst, XMMRegister src) { | |
1548 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; } | |
1549 else { movss (dst, src); return; } | |
1550 } | |
1551 void movflt(XMMRegister dst, Address src) { movss(dst, src); } | |
1552 void movflt(XMMRegister dst, AddressLiteral src); | |
1553 void movflt(Address dst, XMMRegister src) { movss(dst, src); } | |
1554 | |
1555 void movdbl(XMMRegister dst, XMMRegister src) { | |
1556 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; } | |
1557 else { movsd (dst, src); return; } | |
1558 } | |
1559 | |
1560 void movdbl(XMMRegister dst, AddressLiteral src); | |
1561 | |
1562 void movdbl(XMMRegister dst, Address src) { | |
1563 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; } | |
1564 else { movlpd(dst, src); return; } | |
1565 } | |
1566 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); } | |
1567 | |
304 | 1568 void incrementl(AddressLiteral dst); |
1569 void incrementl(ArrayAddress dst); | |
0 | 1570 |
1571 // Alignment | |
1572 void align(int modulus); | |
1573 | |
1574 // Misc | |
1575 void fat_nop(); // 5 byte nop | |
1576 | |
1577 // Stack frame creation/removal | |
1578 void enter(); | |
1579 void leave(); | |
1580 | |
1581 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information) | |
1582 // The pointer will be loaded into the thread register. | |
1583 void get_thread(Register thread); | |
1584 | |
362 | 1585 |
0 | 1586 // Support for VM calls |
1587 // | |
1588 // It is imperative that all calls into the VM are handled via the call_VM macros. | |
1589 // They make sure that the stack linkage is setup correctly. call_VM's correspond | |
1590 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points. | |
1591 | |
304 | 1592 |
1593 void call_VM(Register oop_result, | |
1594 address entry_point, | |
1595 bool check_exceptions = true); | |
1596 void call_VM(Register oop_result, | |
1597 address entry_point, | |
1598 Register arg_1, | |
1599 bool check_exceptions = true); | |
1600 void call_VM(Register oop_result, | |
1601 address entry_point, | |
1602 Register arg_1, Register arg_2, | |
1603 bool check_exceptions = true); | |
1604 void call_VM(Register oop_result, | |
1605 address entry_point, | |
1606 Register arg_1, Register arg_2, Register arg_3, | |
1607 bool check_exceptions = true); | |
1608 | |
1609 // Overloadings with last_Java_sp | |
1610 void call_VM(Register oop_result, | |
1611 Register last_java_sp, | |
1612 address entry_point, | |
1613 int number_of_arguments = 0, | |
1614 bool check_exceptions = true); | |
1615 void call_VM(Register oop_result, | |
1616 Register last_java_sp, | |
1617 address entry_point, | |
1618 Register arg_1, bool | |
1619 check_exceptions = true); | |
1620 void call_VM(Register oop_result, | |
1621 Register last_java_sp, | |
1622 address entry_point, | |
1623 Register arg_1, Register arg_2, | |
1624 bool check_exceptions = true); | |
1625 void call_VM(Register oop_result, | |
1626 Register last_java_sp, | |
1627 address entry_point, | |
1628 Register arg_1, Register arg_2, Register arg_3, | |
1629 bool check_exceptions = true); | |
1630 | |
1631 void call_VM_leaf(address entry_point, | |
1632 int number_of_arguments = 0); | |
1633 void call_VM_leaf(address entry_point, | |
1634 Register arg_1); | |
1635 void call_VM_leaf(address entry_point, | |
1636 Register arg_1, Register arg_2); | |
1637 void call_VM_leaf(address entry_point, | |
1638 Register arg_1, Register arg_2, Register arg_3); | |
0 | 1639 |
1640 // last Java Frame (fills frame anchor) | |
304 | 1641 void set_last_Java_frame(Register thread, |
1642 Register last_java_sp, | |
1643 Register last_java_fp, | |
1644 address last_java_pc); | |
1645 | |
1646 // thread in the default location (r15_thread on 64bit) | |
1647 void set_last_Java_frame(Register last_java_sp, | |
1648 Register last_java_fp, | |
1649 address last_java_pc); | |
1650 | |
0 | 1651 void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc); |
1652 | |
304 | 1653 // thread in the default location (r15_thread on 64bit) |
1654 void reset_last_Java_frame(bool clear_fp, bool clear_pc); | |
1655 | |
0 | 1656 // Stores |
1657 void store_check(Register obj); // store check for obj - register is destroyed afterwards | |
1658 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed) | |
1659 | |
362 | 1660 void g1_write_barrier_pre(Register obj, |
1661 #ifndef _LP64 | |
1662 Register thread, | |
1663 #endif | |
1664 Register tmp, | |
1665 Register tmp2, | |
1666 bool tosca_live); | |
1667 void g1_write_barrier_post(Register store_addr, | |
1668 Register new_val, | |
1669 #ifndef _LP64 | |
1670 Register thread, | |
1671 #endif | |
1672 Register tmp, | |
1673 Register tmp2); | |
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1674 |
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1675 |
0 | 1676 // split store_check(Register obj) to enhance instruction interleaving |
1677 void store_check_part_1(Register obj); | |
1678 void store_check_part_2(Register obj); | |
1679 | |
1680 // C 'boolean' to Java boolean: x == 0 ? 0 : 1 | |
1681 void c2bool(Register x); | |
1682 | |
1683 // C++ bool manipulation | |
1684 | |
1685 void movbool(Register dst, Address src); | |
1686 void movbool(Address dst, bool boolconst); | |
1687 void movbool(Address dst, Register src); | |
1688 void testbool(Register dst); | |
1689 | |
304 | 1690 // oop manipulations |
1691 void load_klass(Register dst, Register src); | |
1692 void store_klass(Register dst, Register src); | |
1693 | |
1846 | 1694 void load_heap_oop(Register dst, Address src); |
1695 void store_heap_oop(Address dst, Register src); | |
1696 | |
1697 // Used for storing NULL. All other oop constants should be | |
1698 // stored using routines that take a jobject. | |
1699 void store_heap_oop_null(Address dst); | |
1700 | |
304 | 1701 void load_prototype_header(Register dst, Register src); |
1702 | |
1703 #ifdef _LP64 | |
1704 void store_klass_gap(Register dst, Register src); | |
1705 | |
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1706 // This dummy is to prevent a call to store_heap_oop from |
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1707 // converting a zero (like NULL) into a Register by giving |
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1708 // the compiler two choices it can't resolve |
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1709 |
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1710 void store_heap_oop(Address dst, void* dummy); |
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1711 |
304 | 1712 void encode_heap_oop(Register r); |
1713 void decode_heap_oop(Register r); | |
1714 void encode_heap_oop_not_null(Register r); | |
1715 void decode_heap_oop_not_null(Register r); | |
1716 void encode_heap_oop_not_null(Register dst, Register src); | |
1717 void decode_heap_oop_not_null(Register dst, Register src); | |
1718 | |
1719 void set_narrow_oop(Register dst, jobject obj); | |
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1720 void set_narrow_oop(Address dst, jobject obj); |
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1721 void cmp_narrow_oop(Register dst, jobject obj); |
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1722 void cmp_narrow_oop(Address dst, jobject obj); |
304 | 1723 |
1724 // if heap base register is used - reinit it with the correct value | |
1725 void reinit_heapbase(); | |
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1727 DEBUG_ONLY(void verify_heapbase(const char* msg);) |
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1728 |
304 | 1729 #endif // _LP64 |
1730 | |
1731 // Int division/remainder for Java | |
0 | 1732 // (as idivl, but checks for special case as described in JVM spec.) |
1733 // returns idivl instruction offset for implicit exception handling | |
1734 int corrected_idivl(Register reg); | |
1735 | |
304 | 1736 // Long division/remainder for Java |
1737 // (as idivq, but checks for special case as described in JVM spec.) | |
1738 // returns idivq instruction offset for implicit exception handling | |
1739 int corrected_idivq(Register reg); | |
1740 | |
0 | 1741 void int3(); |
1742 | |
304 | 1743 // Long operation macros for a 32bit cpu |
0 | 1744 // Long negation for Java |
1745 void lneg(Register hi, Register lo); | |
1746 | |
1747 // Long multiplication for Java | |
304 | 1748 // (destroys contents of eax, ebx, ecx and edx) |
0 | 1749 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y |
1750 | |
1751 // Long shifts for Java | |
1752 // (semantics as described in JVM spec.) | |
1753 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f) | |
1754 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f) | |
1755 | |
1756 // Long compare for Java | |
1757 // (semantics as described in JVM spec.) | |
1758 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y) | |
1759 | |
304 | 1760 |
1761 // misc | |
1762 | |
1763 // Sign extension | |
1764 void sign_extend_short(Register reg); | |
1765 void sign_extend_byte(Register reg); | |
1766 | |
1767 // Division by power of 2, rounding towards 0 | |
1768 void division_with_shift(Register reg, int shift_value); | |
1769 | |
0 | 1770 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows: |
1771 // | |
1772 // CF (corresponds to C0) if x < y | |
1773 // PF (corresponds to C2) if unordered | |
1774 // ZF (corresponds to C3) if x = y | |
1775 // | |
1776 // The arguments are in reversed order on the stack (i.e., top of stack is first argument). | |
1777 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code) | |
1778 void fcmp(Register tmp); | |
1779 // Variant of the above which allows y to be further down the stack | |
1780 // and which only pops x and y if specified. If pop_right is | |
1781 // specified then pop_left must also be specified. | |
1782 void fcmp(Register tmp, int index, bool pop_left, bool pop_right); | |
1783 | |
1784 // Floating-point comparison for Java | |
1785 // Compares the top-most stack entries on the FPU stack and stores the result in dst. | |
1786 // The arguments are in reversed order on the stack (i.e., top of stack is first argument). | |
1787 // (semantics as described in JVM spec.) | |
1788 void fcmp2int(Register dst, bool unordered_is_less); | |
1789 // Variant of the above which allows y to be further down the stack | |
1790 // and which only pops x and y if specified. If pop_right is | |
1791 // specified then pop_left must also be specified. | |
1792 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right); | |
1793 | |
1794 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards) | |
1795 // tmp is a temporary register, if none is available use noreg | |
1796 void fremr(Register tmp); | |
1797 | |
1798 | |
1799 // same as fcmp2int, but using SSE2 | |
1800 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less); | |
1801 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less); | |
1802 | |
1803 // Inlined sin/cos generator for Java; must not use CPU instruction | |
1804 // directly on Intel as it does not have high enough precision | |
1805 // outside of the range [-pi/4, pi/4]. Extra argument indicate the | |
1806 // number of FPU stack slots in use; all but the topmost will | |
1807 // require saving if a slow case is necessary. Assumes argument is | |
1808 // on FP TOS; result is on FP TOS. No cpu registers are changed by | |
1809 // this code. | |
1810 void trigfunc(char trig, int num_fpu_regs_in_use = 1); | |
1811 | |
1812 // branch to L if FPU flag C2 is set/not set | |
1813 // tmp is a temporary register, if none is available use noreg | |
1814 void jC2 (Register tmp, Label& L); | |
1815 void jnC2(Register tmp, Label& L); | |
1816 | |
1817 // Pop ST (ffree & fincstp combined) | |
1818 void fpop(); | |
1819 | |
1820 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack | |
1821 void push_fTOS(); | |
1822 | |
1823 // pops double TOS element from CPU stack and pushes on FPU stack | |
1824 void pop_fTOS(); | |
1825 | |
1826 void empty_FPU_stack(); | |
1827 | |
1828 void push_IU_state(); | |
1829 void pop_IU_state(); | |
1830 | |
1831 void push_FPU_state(); | |
1832 void pop_FPU_state(); | |
1833 | |
1834 void push_CPU_state(); | |
1835 void pop_CPU_state(); | |
1836 | |
1837 // Round up to a power of two | |
1838 void round_to(Register reg, int modulus); | |
1839 | |
1840 // Callee saved registers handling | |
1841 void push_callee_saved_registers(); | |
1842 void pop_callee_saved_registers(); | |
1843 | |
1844 // allocation | |
1845 void eden_allocate( | |
1846 Register obj, // result: pointer to object after successful allocation | |
1847 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise | |
1848 int con_size_in_bytes, // object size in bytes if known at compile time | |
1849 Register t1, // temp register | |
1850 Label& slow_case // continuation point if fast allocation fails | |
1851 ); | |
1852 void tlab_allocate( | |
1853 Register obj, // result: pointer to object after successful allocation | |
1854 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise | |
1855 int con_size_in_bytes, // object size in bytes if known at compile time | |
1856 Register t1, // temp register | |
1857 Register t2, // temp register | |
1858 Label& slow_case // continuation point if fast allocation fails | |
1859 ); | |
1860 void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); | |
1861 | |
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1862 // interface method calling |
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1863 void lookup_interface_method(Register recv_klass, |
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1864 Register intf_klass, |
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1865 RegisterOrConstant itable_index, |
623
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1866 Register method_result, |
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1867 Register scan_temp, |
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1868 Label& no_such_interface); |
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1869 |
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1870 // Test sub_klass against super_klass, with fast and slow paths. |
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1871 |
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1872 // The fast path produces a tri-state answer: yes / no / maybe-slow. |
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1873 // One of the three labels can be NULL, meaning take the fall-through. |
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1874 // If super_check_offset is -1, the value is loaded up from super_klass. |
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1875 // No registers are killed, except temp_reg. |
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1876 void check_klass_subtype_fast_path(Register sub_klass, |
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1877 Register super_klass, |
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1878 Register temp_reg, |
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1879 Label* L_success, |
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1880 Label* L_failure, |
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1881 Label* L_slow_path, |
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1882 RegisterOrConstant super_check_offset = RegisterOrConstant(-1)); |
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1883 |
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1884 // The rest of the type check; must be wired to a corresponding fast path. |
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1885 // It does not repeat the fast path logic, so don't use it standalone. |
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1886 // The temp_reg and temp2_reg can be noreg, if no temps are available. |
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1887 // Updates the sub's secondary super cache as necessary. |
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1888 // If set_cond_codes, condition codes will be Z on success, NZ on failure. |
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1889 void check_klass_subtype_slow_path(Register sub_klass, |
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1890 Register super_klass, |
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1891 Register temp_reg, |
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1892 Register temp2_reg, |
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1893 Label* L_success, |
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1894 Label* L_failure, |
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1895 bool set_cond_codes = false); |
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1896 |
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1897 // Simplified, combined version, good for typical uses. |
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1898 // Falls through on failure. |
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1899 void check_klass_subtype(Register sub_klass, |
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1900 Register super_klass, |
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1901 Register temp_reg, |
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1902 Label& L_success); |
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1903 |
710 | 1904 // method handles (JSR 292) |
1905 void check_method_handle_type(Register mtype_reg, Register mh_reg, | |
1906 Register temp_reg, | |
1907 Label& wrong_method_type); | |
1908 void load_method_handle_vmslots(Register vmslots_reg, Register mh_reg, | |
1909 Register temp_reg); | |
1910 void jump_to_method_handle_entry(Register mh_reg, Register temp_reg); | |
1911 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0); | |
1912 | |
1913 | |
0 | 1914 //---- |
1915 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0 | |
1916 | |
1917 // Debugging | |
304 | 1918 |
1919 // only if +VerifyOops | |
1920 void verify_oop(Register reg, const char* s = "broken oop"); | |
0 | 1921 void verify_oop_addr(Address addr, const char * s = "broken oop addr"); |
1922 | |
304 | 1923 // only if +VerifyFPU |
1924 void verify_FPU(int stack_depth, const char* s = "illegal FPU state"); | |
1925 | |
1926 // prints msg, dumps registers and stops execution | |
1927 void stop(const char* msg); | |
1928 | |
1929 // prints msg and continues | |
1930 void warn(const char* msg); | |
1931 | |
1932 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg); | |
1933 static void debug64(char* msg, int64_t pc, int64_t regs[]); | |
1934 | |
0 | 1935 void os_breakpoint(); |
304 | 1936 |
0 | 1937 void untested() { stop("untested"); } |
304 | 1938 |
1846 | 1939 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); } |
304 | 1940 |
0 | 1941 void should_not_reach_here() { stop("should not reach here"); } |
304 | 1942 |
0 | 1943 void print_CPU_state(); |
1944 | |
1945 // Stack overflow checking | |
1946 void bang_stack_with_offset(int offset) { | |
1947 // stack grows down, caller passes positive offset | |
1948 assert(offset > 0, "must bang with negative offset"); | |
1949 movl(Address(rsp, (-offset)), rax); | |
1950 } | |
1951 | |
1952 // Writes to stack successive pages until offset reached to check for | |
1953 // stack overflow + shadow pages. Also, clobbers tmp | |
1954 void bang_stack_size(Register size, Register tmp); | |
1955 | |
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1956 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, |
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1957 Register tmp, |
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1958 int offset); |
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1959 |
0 | 1960 // Support for serializing memory accesses between threads |
1961 void serialize_memory(Register thread, Register tmp); | |
1962 | |
1963 void verify_tlab(); | |
1964 | |
1965 // Biased locking support | |
1966 // lock_reg and obj_reg must be loaded up with the appropriate values. | |
1967 // swap_reg must be rax, and is killed. | |
1968 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will | |
1969 // be killed; if not supplied, push/pop will be used internally to | |
1970 // allocate a temporary (inefficient, avoid if possible). | |
1971 // Optional slow case is for implementations (interpreter and C1) which branch to | |
1972 // slow case directly. Leaves condition codes set for C2's Fast_Lock node. | |
1973 // Returns offset of first potentially-faulting instruction for null | |
1974 // check info (currently consumed only by C1). If | |
1975 // swap_reg_contains_mark is true then returns -1 as it is assumed | |
1976 // the calling code has already passed any potential faults. | |
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1977 int biased_locking_enter(Register lock_reg, Register obj_reg, |
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1978 Register swap_reg, Register tmp_reg, |
0 | 1979 bool swap_reg_contains_mark, |
1980 Label& done, Label* slow_case = NULL, | |
1981 BiasedLockingCounters* counters = NULL); | |
1982 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done); | |
1983 | |
1984 | |
1985 Condition negate_condition(Condition cond); | |
1986 | |
1987 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit | |
1988 // operands. In general the names are modified to avoid hiding the instruction in Assembler | |
1989 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers | |
1990 // here in MacroAssembler. The major exception to this rule is call | |
1991 | |
1992 // Arithmetics | |
1993 | |
304 | 1994 |
1995 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; } | |
1996 void addptr(Address dst, Register src); | |
1997 | |
1998 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); } | |
1999 void addptr(Register dst, int32_t src); | |
2000 void addptr(Register dst, Register src); | |
2001 | |
2002 void andptr(Register dst, int32_t src); | |
2003 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; } | |
2004 | |
2005 void cmp8(AddressLiteral src1, int imm); | |
2006 | |
2007 // renamed to drag out the casting of address to int32_t/intptr_t | |
0 | 2008 void cmp32(Register src1, int32_t imm); |
2009 | |
2010 void cmp32(AddressLiteral src1, int32_t imm); | |
2011 // compare reg - mem, or reg - &mem | |
2012 void cmp32(Register src1, AddressLiteral src2); | |
2013 | |
2014 void cmp32(Register src1, Address src2); | |
2015 | |
304 | 2016 #ifndef _LP64 |
2017 void cmpoop(Address dst, jobject obj); | |
2018 void cmpoop(Register dst, jobject obj); | |
2019 #endif // _LP64 | |
2020 | |
0 | 2021 // NOTE src2 must be the lval. This is NOT an mem-mem compare |
2022 void cmpptr(Address src1, AddressLiteral src2); | |
2023 | |
2024 void cmpptr(Register src1, AddressLiteral src2); | |
2025 | |
304 | 2026 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } |
2027 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } | |
2028 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } | |
2029 | |
2030 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } | |
2031 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } | |
2032 | |
2033 // cmp64 to avoild hiding cmpq | |
2034 void cmp64(Register src1, AddressLiteral src); | |
2035 | |
2036 void cmpxchgptr(Register reg, Address adr); | |
2037 | |
2038 void locked_cmpxchgptr(Register reg, AddressLiteral adr); | |
2039 | |
2040 | |
2041 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); } | |
2042 | |
2043 | |
2044 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); } | |
2045 | |
2046 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); } | |
2047 | |
2048 void shlptr(Register dst, int32_t shift); | |
2049 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); } | |
2050 | |
2051 void shrptr(Register dst, int32_t shift); | |
2052 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); } | |
2053 | |
2054 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); } | |
2055 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); } | |
2056 | |
2057 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); } | |
2058 | |
2059 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); } | |
2060 void subptr(Register dst, int32_t src); | |
2061 void subptr(Register dst, Register src); | |
2062 | |
2063 | |
2064 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); } | |
2065 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); } | |
2066 | |
2067 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; } | |
2068 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; } | |
2069 | |
2070 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; } | |
2071 | |
2072 | |
0 | 2073 |
2074 // Helper functions for statistics gathering. | |
2075 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes. | |
2076 void cond_inc32(Condition cond, AddressLiteral counter_addr); | |
2077 // Unconditional atomic increment. | |
2078 void atomic_incl(AddressLiteral counter_addr); | |
2079 | |
2080 void lea(Register dst, AddressLiteral adr); | |
2081 void lea(Address dst, AddressLiteral adr); | |
304 | 2082 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); } |
2083 | |
2084 void leal32(Register dst, Address src) { leal(dst, src); } | |
2085 | |
2086 void test32(Register src1, AddressLiteral src2); | |
2087 | |
2088 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } | |
2089 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } | |
2090 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } | |
2091 | |
2092 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); } | |
2093 void testptr(Register src1, Register src2); | |
2094 | |
2095 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); } | |
2096 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); } | |
0 | 2097 |
2098 // Calls | |
2099 | |
2100 void call(Label& L, relocInfo::relocType rtype); | |
2101 void call(Register entry); | |
2102 | |
2103 // NOTE: this call tranfers to the effective address of entry NOT | |
2104 // the address contained by entry. This is because this is more natural | |
2105 // for jumps/calls. | |
2106 void call(AddressLiteral entry); | |
2107 | |
2108 // Jumps | |
2109 | |
2110 // NOTE: these jumps tranfer to the effective address of dst NOT | |
2111 // the address contained by dst. This is because this is more natural | |
2112 // for jumps/calls. | |
2113 void jump(AddressLiteral dst); | |
2114 void jump_cc(Condition cc, AddressLiteral dst); | |
2115 | |
2116 // 32bit can do a case table jump in one instruction but we no longer allow the base | |
2117 // to be installed in the Address class. This jump will tranfers to the address | |
2118 // contained in the location described by entry (not the address of entry) | |
2119 void jump(ArrayAddress entry); | |
2120 | |
2121 // Floating | |
2122 | |
2123 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); } | |
2124 void andpd(XMMRegister dst, AddressLiteral src); | |
2125 | |
2126 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); } | |
2127 void comiss(XMMRegister dst, AddressLiteral src); | |
2128 | |
2129 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); } | |
2130 void comisd(XMMRegister dst, AddressLiteral src); | |
2131 | |
2008 | 2132 void fadd_s(Address src) { Assembler::fadd_s(src); } |
2133 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); } | |
2134 | |
0 | 2135 void fldcw(Address src) { Assembler::fldcw(src); } |
2136 void fldcw(AddressLiteral src); | |
2137 | |
2138 void fld_s(int index) { Assembler::fld_s(index); } | |
2139 void fld_s(Address src) { Assembler::fld_s(src); } | |
2140 void fld_s(AddressLiteral src); | |
2141 | |
2142 void fld_d(Address src) { Assembler::fld_d(src); } | |
2143 void fld_d(AddressLiteral src); | |
2144 | |
2145 void fld_x(Address src) { Assembler::fld_x(src); } | |
2146 void fld_x(AddressLiteral src); | |
2147 | |
2008 | 2148 void fmul_s(Address src) { Assembler::fmul_s(src); } |
2149 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); } | |
2150 | |
0 | 2151 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); } |
2152 void ldmxcsr(AddressLiteral src); | |
2153 | |
304 | 2154 private: |
2155 // these are private because users should be doing movflt/movdbl | |
2156 | |
0 | 2157 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); } |
2158 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); } | |
2159 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); } | |
2160 void movss(XMMRegister dst, AddressLiteral src); | |
2161 | |
304 | 2162 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); } |
2163 void movlpd(XMMRegister dst, AddressLiteral src); | |
2164 | |
2165 public: | |
2166 | |
2008 | 2167 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); } |
2168 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); } | |
2169 void addsd(XMMRegister dst, AddressLiteral src) { Assembler::addsd(dst, as_Address(src)); } | |
2170 | |
2171 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); } | |
2172 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); } | |
2173 void addss(XMMRegister dst, AddressLiteral src) { Assembler::addss(dst, as_Address(src)); } | |
2174 | |
2175 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); } | |
2176 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); } | |
2177 void divsd(XMMRegister dst, AddressLiteral src) { Assembler::divsd(dst, as_Address(src)); } | |
2178 | |
2179 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); } | |
2180 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); } | |
2181 void divss(XMMRegister dst, AddressLiteral src) { Assembler::divss(dst, as_Address(src)); } | |
2182 | |
2183 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); } | |
2184 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); } | |
2185 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); } | |
2186 void movsd(XMMRegister dst, AddressLiteral src) { Assembler::movsd(dst, as_Address(src)); } | |
2187 | |
2188 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); } | |
2189 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); } | |
2190 void mulsd(XMMRegister dst, AddressLiteral src) { Assembler::mulsd(dst, as_Address(src)); } | |
2191 | |
2192 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); } | |
2193 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); } | |
2194 void mulss(XMMRegister dst, AddressLiteral src) { Assembler::mulss(dst, as_Address(src)); } | |
2195 | |
2196 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); } | |
2197 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); } | |
2198 void sqrtsd(XMMRegister dst, AddressLiteral src) { Assembler::sqrtsd(dst, as_Address(src)); } | |
2199 | |
2200 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); } | |
2201 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); } | |
2202 void sqrtss(XMMRegister dst, AddressLiteral src) { Assembler::sqrtss(dst, as_Address(src)); } | |
2203 | |
2204 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); } | |
2205 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); } | |
2206 void subsd(XMMRegister dst, AddressLiteral src) { Assembler::subsd(dst, as_Address(src)); } | |
2207 | |
2208 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); } | |
2209 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); } | |
2210 void subss(XMMRegister dst, AddressLiteral src) { Assembler::subss(dst, as_Address(src)); } | |
0 | 2211 |
2212 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); } | |
2213 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); } | |
2214 void ucomiss(XMMRegister dst, AddressLiteral src); | |
2215 | |
2216 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); } | |
2217 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); } | |
2218 void ucomisd(XMMRegister dst, AddressLiteral src); | |
2219 | |
2220 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values | |
2221 void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); } | |
2222 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); } | |
2223 void xorpd(XMMRegister dst, AddressLiteral src); | |
2224 | |
2225 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values | |
2226 void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); } | |
2227 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); } | |
2228 void xorps(XMMRegister dst, AddressLiteral src); | |
2229 | |
2230 // Data | |
2231 | |
304 | 2232 void cmov(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); } |
2233 | |
2234 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); } | |
2235 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); } | |
2236 | |
0 | 2237 void movoop(Register dst, jobject obj); |
2238 void movoop(Address dst, jobject obj); | |
2239 | |
2240 void movptr(ArrayAddress dst, Register src); | |
2241 // can this do an lea? | |
2242 void movptr(Register dst, ArrayAddress src); | |
2243 | |
304 | 2244 void movptr(Register dst, Address src); |
2245 | |
0 | 2246 void movptr(Register dst, AddressLiteral src); |
2247 | |
304 | 2248 void movptr(Register dst, intptr_t src); |
2249 void movptr(Register dst, Register src); | |
2250 void movptr(Address dst, intptr_t src); | |
2251 | |
2252 void movptr(Address dst, Register src); | |
2253 | |
2254 #ifdef _LP64 | |
2255 // Generally the next two are only used for moving NULL | |
2256 // Although there are situations in initializing the mark word where | |
2257 // they could be used. They are dangerous. | |
2258 | |
2259 // They only exist on LP64 so that int32_t and intptr_t are not the same | |
2260 // and we have ambiguous declarations. | |
2261 | |
2262 void movptr(Address dst, int32_t imm32); | |
2263 void movptr(Register dst, int32_t imm32); | |
2264 #endif // _LP64 | |
2265 | |
0 | 2266 // to avoid hiding movl |
2267 void mov32(AddressLiteral dst, Register src); | |
2268 void mov32(Register dst, AddressLiteral src); | |
304 | 2269 |
0 | 2270 // to avoid hiding movb |
2271 void movbyte(ArrayAddress dst, int src); | |
2272 | |
2273 // Can push value or effective address | |
2274 void pushptr(AddressLiteral src); | |
2275 | |
304 | 2276 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); } |
2277 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); } | |
2278 | |
2279 void pushoop(jobject obj); | |
2280 | |
2281 // sign extend as need a l to ptr sized element | |
2282 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); } | |
2283 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); } | |
2284 | |
986
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2285 // IndexOf strings. |
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2286 void string_indexof(Register str1, Register str2, |
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2287 Register cnt1, Register cnt2, Register result, |
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2288 XMMRegister vec, Register tmp); |
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2289 |
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2290 // Compare strings. |
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2291 void string_compare(Register str1, Register str2, |
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2292 Register cnt1, Register cnt2, Register result, |
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2293 XMMRegister vec1, XMMRegister vec2); |
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2294 |
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2295 // Compare char[] arrays. |
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2296 void char_arrays_equals(bool is_array_equ, Register ary1, Register ary2, |
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2297 Register limit, Register result, Register chr, |
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2298 XMMRegister vec1, XMMRegister vec2); |
304 | 2299 |
1763 | 2300 // Fill primitive arrays |
2301 void generate_fill(BasicType t, bool aligned, | |
2302 Register to, Register value, Register count, | |
2303 Register rtmp, XMMRegister xtmp); | |
2304 | |
0 | 2305 #undef VIRTUAL |
2306 | |
2307 }; | |
2308 | |
2309 /** | |
2310 * class SkipIfEqual: | |
2311 * | |
2312 * Instantiating this class will result in assembly code being output that will | |
2313 * jump around any code emitted between the creation of the instance and it's | |
2314 * automatic destruction at the end of a scope block, depending on the value of | |
2315 * the flag passed to the constructor, which will be checked at run-time. | |
2316 */ | |
2317 class SkipIfEqual { | |
2318 private: | |
2319 MacroAssembler* _masm; | |
2320 Label _label; | |
2321 | |
2322 public: | |
2323 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value); | |
2324 ~SkipIfEqual(); | |
2325 }; | |
2326 | |
2327 #ifdef ASSERT | |
2328 inline bool AbstractAssembler::pd_check_instruction_mark() { return true; } | |
2329 #endif | |
1972 | 2330 |
2331 #endif // CPU_X86_VM_ASSEMBLER_X86_HPP |