Mercurial > hg > truffle
annotate src/cpu/x86/vm/assembler_x86.hpp @ 1932:e6500c6c5e24
Removed launch configuration.
author | Thomas Wuerthinger <wuerthinger@ssw.jku.at> |
---|---|
date | Tue, 21 Dec 2010 17:09:37 +0100 |
parents | 2fe998383789 |
children | f95d63e2154a |
rev | line source |
---|---|
0 | 1 /* |
1552
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1503
diff
changeset
|
2 * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
1552
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1503
diff
changeset
|
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1503
diff
changeset
|
20 * or visit www.oracle.com if you need additional information or have any |
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1503
diff
changeset
|
21 * questions. |
0 | 22 * |
23 */ | |
24 | |
25 class BiasedLockingCounters; | |
26 | |
27 // Contains all the definitions needed for x86 assembly code generation. | |
28 | |
29 // Calling convention | |
30 class Argument VALUE_OBJ_CLASS_SPEC { | |
31 public: | |
32 enum { | |
33 #ifdef _LP64 | |
34 #ifdef _WIN64 | |
35 n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...) | |
36 n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... ) | |
37 #else | |
38 n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...) | |
39 n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... ) | |
40 #endif // _WIN64 | |
41 n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ... | |
42 n_float_register_parameters_j = 8 // j_farg0, j_farg1, ... | |
43 #else | |
44 n_register_parameters = 0 // 0 registers used to pass arguments | |
45 #endif // _LP64 | |
46 }; | |
47 }; | |
48 | |
49 | |
50 #ifdef _LP64 | |
51 // Symbolically name the register arguments used by the c calling convention. | |
52 // Windows is different from linux/solaris. So much for standards... | |
53 | |
54 #ifdef _WIN64 | |
55 | |
56 REGISTER_DECLARATION(Register, c_rarg0, rcx); | |
57 REGISTER_DECLARATION(Register, c_rarg1, rdx); | |
58 REGISTER_DECLARATION(Register, c_rarg2, r8); | |
59 REGISTER_DECLARATION(Register, c_rarg3, r9); | |
60 | |
304 | 61 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); |
62 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); | |
63 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); | |
64 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); | |
0 | 65 |
66 #else | |
67 | |
68 REGISTER_DECLARATION(Register, c_rarg0, rdi); | |
69 REGISTER_DECLARATION(Register, c_rarg1, rsi); | |
70 REGISTER_DECLARATION(Register, c_rarg2, rdx); | |
71 REGISTER_DECLARATION(Register, c_rarg3, rcx); | |
72 REGISTER_DECLARATION(Register, c_rarg4, r8); | |
73 REGISTER_DECLARATION(Register, c_rarg5, r9); | |
74 | |
304 | 75 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); |
76 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); | |
77 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); | |
78 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); | |
79 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4); | |
80 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5); | |
81 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6); | |
82 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7); | |
0 | 83 |
84 #endif // _WIN64 | |
85 | |
86 // Symbolically name the register arguments used by the Java calling convention. | |
87 // We have control over the convention for java so we can do what we please. | |
88 // What pleases us is to offset the java calling convention so that when | |
89 // we call a suitable jni method the arguments are lined up and we don't | |
90 // have to do little shuffling. A suitable jni method is non-static and a | |
91 // small number of arguments (two fewer args on windows) | |
92 // | |
93 // |-------------------------------------------------------| | |
94 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 | | |
95 // |-------------------------------------------------------| | |
96 // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg) | |
97 // | rdi rsi rdx rcx r8 r9 | solaris/linux | |
98 // |-------------------------------------------------------| | |
99 // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 | | |
100 // |-------------------------------------------------------| | |
101 | |
102 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1); | |
103 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2); | |
104 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3); | |
105 // Windows runs out of register args here | |
106 #ifdef _WIN64 | |
107 REGISTER_DECLARATION(Register, j_rarg3, rdi); | |
108 REGISTER_DECLARATION(Register, j_rarg4, rsi); | |
109 #else | |
110 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4); | |
111 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5); | |
112 #endif /* _WIN64 */ | |
113 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0); | |
114 | |
304 | 115 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0); |
116 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1); | |
117 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2); | |
118 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3); | |
119 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4); | |
120 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5); | |
121 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6); | |
122 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7); | |
0 | 123 |
124 REGISTER_DECLARATION(Register, rscratch1, r10); // volatile | |
125 REGISTER_DECLARATION(Register, rscratch2, r11); // volatile | |
126 | |
304 | 127 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved |
0 | 128 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved |
129 | |
304 | 130 #else |
131 // rscratch1 will apear in 32bit code that is dead but of course must compile | |
132 // Using noreg ensures if the dead code is incorrectly live and executed it | |
133 // will cause an assertion failure | |
134 #define rscratch1 noreg | |
135 | |
0 | 136 #endif // _LP64 |
137 | |
1564 | 138 // JSR 292 fixed register usages: |
139 REGISTER_DECLARATION(Register, rbp_mh_SP_save, rbp); | |
140 | |
0 | 141 // Address is an abstraction used to represent a memory location |
142 // using any of the amd64 addressing modes with one object. | |
143 // | |
144 // Note: A register location is represented via a Register, not | |
145 // via an address for efficiency & simplicity reasons. | |
146 | |
147 class ArrayAddress; | |
148 | |
149 class Address VALUE_OBJ_CLASS_SPEC { | |
150 public: | |
151 enum ScaleFactor { | |
152 no_scale = -1, | |
153 times_1 = 0, | |
154 times_2 = 1, | |
155 times_4 = 2, | |
304 | 156 times_8 = 3, |
157 times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4) | |
0 | 158 }; |
622
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
159 static ScaleFactor times(int size) { |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
160 assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size"); |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
161 if (size == 8) return times_8; |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
162 if (size == 4) return times_4; |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
163 if (size == 2) return times_2; |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
164 return times_1; |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
165 } |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
166 static int scale_size(ScaleFactor scale) { |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
167 assert(scale != no_scale, ""); |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
168 assert(((1 << (int)times_1) == 1 && |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
169 (1 << (int)times_2) == 2 && |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
170 (1 << (int)times_4) == 4 && |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
171 (1 << (int)times_8) == 8), ""); |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
172 return (1 << (int)scale); |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
173 } |
0 | 174 |
175 private: | |
176 Register _base; | |
177 Register _index; | |
178 ScaleFactor _scale; | |
179 int _disp; | |
180 RelocationHolder _rspec; | |
181 | |
304 | 182 // Easily misused constructors make them private |
183 // %%% can we make these go away? | |
184 NOT_LP64(Address(address loc, RelocationHolder spec);) | |
185 Address(int disp, address loc, relocInfo::relocType rtype); | |
186 Address(int disp, address loc, RelocationHolder spec); | |
0 | 187 |
188 public: | |
304 | 189 |
190 int disp() { return _disp; } | |
0 | 191 // creation |
192 Address() | |
193 : _base(noreg), | |
194 _index(noreg), | |
195 _scale(no_scale), | |
196 _disp(0) { | |
197 } | |
198 | |
199 // No default displacement otherwise Register can be implicitly | |
200 // converted to 0(Register) which is quite a different animal. | |
201 | |
202 Address(Register base, int disp) | |
203 : _base(base), | |
204 _index(noreg), | |
205 _scale(no_scale), | |
206 _disp(disp) { | |
207 } | |
208 | |
209 Address(Register base, Register index, ScaleFactor scale, int disp = 0) | |
210 : _base (base), | |
211 _index(index), | |
212 _scale(scale), | |
213 _disp (disp) { | |
214 assert(!index->is_valid() == (scale == Address::no_scale), | |
215 "inconsistent address"); | |
216 } | |
217 | |
665
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
644
diff
changeset
|
218 Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0) |
622
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
219 : _base (base), |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
220 _index(index.register_or_noreg()), |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
221 _scale(scale), |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
222 _disp (disp + (index.constant_or_zero() * scale_size(scale))) { |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
223 if (!index.is_register()) scale = Address::no_scale; |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
224 assert(!_index->is_valid() == (scale == Address::no_scale), |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
225 "inconsistent address"); |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
226 } |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
227 |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
228 Address plus_disp(int disp) const { |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
229 Address a = (*this); |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
230 a._disp += disp; |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
231 return a; |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
232 } |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
233 |
0 | 234 // The following two overloads are used in connection with the |
235 // ByteSize type (see sizes.hpp). They simplify the use of | |
236 // ByteSize'd arguments in assembly code. Note that their equivalent | |
237 // for the optimized build are the member functions with int disp | |
238 // argument since ByteSize is mapped to an int type in that case. | |
239 // | |
240 // Note: DO NOT introduce similar overloaded functions for WordSize | |
241 // arguments as in the optimized mode, both ByteSize and WordSize | |
242 // are mapped to the same type and thus the compiler cannot make a | |
243 // distinction anymore (=> compiler errors). | |
244 | |
245 #ifdef ASSERT | |
246 Address(Register base, ByteSize disp) | |
247 : _base(base), | |
248 _index(noreg), | |
249 _scale(no_scale), | |
250 _disp(in_bytes(disp)) { | |
251 } | |
252 | |
253 Address(Register base, Register index, ScaleFactor scale, ByteSize disp) | |
254 : _base(base), | |
255 _index(index), | |
256 _scale(scale), | |
257 _disp(in_bytes(disp)) { | |
258 assert(!index->is_valid() == (scale == Address::no_scale), | |
259 "inconsistent address"); | |
260 } | |
622
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
261 |
665
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
644
diff
changeset
|
262 Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp) |
622
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
263 : _base (base), |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
264 _index(index.register_or_noreg()), |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
265 _scale(scale), |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
266 _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) { |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
267 if (!index.is_register()) scale = Address::no_scale; |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
268 assert(!_index->is_valid() == (scale == Address::no_scale), |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
269 "inconsistent address"); |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
270 } |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
271 |
0 | 272 #endif // ASSERT |
273 | |
274 // accessors | |
342
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
ysr
parents:
71
diff
changeset
|
275 bool uses(Register reg) const { return _base == reg || _index == reg; } |
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
ysr
parents:
71
diff
changeset
|
276 Register base() const { return _base; } |
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
ysr
parents:
71
diff
changeset
|
277 Register index() const { return _index; } |
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
ysr
parents:
71
diff
changeset
|
278 ScaleFactor scale() const { return _scale; } |
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
ysr
parents:
71
diff
changeset
|
279 int disp() const { return _disp; } |
0 | 280 |
281 // Convert the raw encoding form into the form expected by the constructor for | |
282 // Address. An index of 4 (rsp) corresponds to having no index, so convert | |
283 // that to noreg for the Address constructor. | |
624 | 284 static Address make_raw(int base, int index, int scale, int disp, bool disp_is_oop); |
0 | 285 |
286 static Address make_array(ArrayAddress); | |
287 | |
288 private: | |
289 bool base_needs_rex() const { | |
290 return _base != noreg && _base->encoding() >= 8; | |
291 } | |
292 | |
293 bool index_needs_rex() const { | |
294 return _index != noreg &&_index->encoding() >= 8; | |
295 } | |
296 | |
297 relocInfo::relocType reloc() const { return _rspec.type(); } | |
298 | |
299 friend class Assembler; | |
300 friend class MacroAssembler; | |
301 friend class LIR_Assembler; // base/index/scale/disp | |
302 }; | |
303 | |
304 // | |
305 // AddressLiteral has been split out from Address because operands of this type | |
306 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out | |
307 // the few instructions that need to deal with address literals are unique and the | |
308 // MacroAssembler does not have to implement every instruction in the Assembler | |
309 // in order to search for address literals that may need special handling depending | |
310 // on the instruction and the platform. As small step on the way to merging i486/amd64 | |
311 // directories. | |
312 // | |
313 class AddressLiteral VALUE_OBJ_CLASS_SPEC { | |
314 friend class ArrayAddress; | |
315 RelocationHolder _rspec; | |
316 // Typically we use AddressLiterals we want to use their rval | |
317 // However in some situations we want the lval (effect address) of the item. | |
318 // We provide a special factory for making those lvals. | |
319 bool _is_lval; | |
320 | |
321 // If the target is far we'll need to load the ea of this to | |
322 // a register to reach it. Otherwise if near we can do rip | |
323 // relative addressing. | |
324 | |
325 address _target; | |
326 | |
327 protected: | |
328 // creation | |
329 AddressLiteral() | |
330 : _is_lval(false), | |
331 _target(NULL) | |
332 {} | |
333 | |
334 public: | |
335 | |
336 | |
337 AddressLiteral(address target, relocInfo::relocType rtype); | |
338 | |
339 AddressLiteral(address target, RelocationHolder const& rspec) | |
340 : _rspec(rspec), | |
341 _is_lval(false), | |
342 _target(target) | |
343 {} | |
344 | |
345 AddressLiteral addr() { | |
346 AddressLiteral ret = *this; | |
347 ret._is_lval = true; | |
348 return ret; | |
349 } | |
350 | |
351 | |
352 private: | |
353 | |
354 address target() { return _target; } | |
355 bool is_lval() { return _is_lval; } | |
356 | |
357 relocInfo::relocType reloc() const { return _rspec.type(); } | |
358 const RelocationHolder& rspec() const { return _rspec; } | |
359 | |
360 friend class Assembler; | |
361 friend class MacroAssembler; | |
362 friend class Address; | |
363 friend class LIR_Assembler; | |
364 }; | |
365 | |
366 // Convience classes | |
367 class RuntimeAddress: public AddressLiteral { | |
368 | |
369 public: | |
370 | |
371 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {} | |
372 | |
373 }; | |
374 | |
375 class OopAddress: public AddressLiteral { | |
376 | |
377 public: | |
378 | |
379 OopAddress(address target) : AddressLiteral(target, relocInfo::oop_type){} | |
380 | |
381 }; | |
382 | |
383 class ExternalAddress: public AddressLiteral { | |
384 | |
385 public: | |
386 | |
387 ExternalAddress(address target) : AddressLiteral(target, relocInfo::external_word_type){} | |
388 | |
389 }; | |
390 | |
391 class InternalAddress: public AddressLiteral { | |
392 | |
393 public: | |
394 | |
395 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {} | |
396 | |
397 }; | |
398 | |
399 // x86 can do array addressing as a single operation since disp can be an absolute | |
400 // address amd64 can't. We create a class that expresses the concept but does extra | |
401 // magic on amd64 to get the final result | |
402 | |
403 class ArrayAddress VALUE_OBJ_CLASS_SPEC { | |
404 private: | |
405 | |
406 AddressLiteral _base; | |
407 Address _index; | |
408 | |
409 public: | |
410 | |
411 ArrayAddress() {}; | |
412 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {}; | |
413 AddressLiteral base() { return _base; } | |
414 Address index() { return _index; } | |
415 | |
416 }; | |
417 | |
304 | 418 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512 / wordSize); |
0 | 419 |
420 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction | |
421 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write | |
422 // is what you get. The Assembler is generating code into a CodeBuffer. | |
423 | |
424 class Assembler : public AbstractAssembler { | |
425 friend class AbstractAssembler; // for the non-virtual hack | |
426 friend class LIR_Assembler; // as_Address() | |
304 | 427 friend class StubGenerator; |
0 | 428 |
429 public: | |
430 enum Condition { // The x86 condition codes used for conditional jumps/moves. | |
431 zero = 0x4, | |
432 notZero = 0x5, | |
433 equal = 0x4, | |
434 notEqual = 0x5, | |
435 less = 0xc, | |
436 lessEqual = 0xe, | |
437 greater = 0xf, | |
438 greaterEqual = 0xd, | |
439 below = 0x2, | |
440 belowEqual = 0x6, | |
441 above = 0x7, | |
442 aboveEqual = 0x3, | |
443 overflow = 0x0, | |
444 noOverflow = 0x1, | |
445 carrySet = 0x2, | |
446 carryClear = 0x3, | |
447 negative = 0x8, | |
448 positive = 0x9, | |
449 parity = 0xa, | |
450 noParity = 0xb | |
451 }; | |
452 | |
453 enum Prefix { | |
454 // segment overrides | |
455 CS_segment = 0x2e, | |
456 SS_segment = 0x36, | |
457 DS_segment = 0x3e, | |
458 ES_segment = 0x26, | |
459 FS_segment = 0x64, | |
460 GS_segment = 0x65, | |
461 | |
462 REX = 0x40, | |
463 | |
464 REX_B = 0x41, | |
465 REX_X = 0x42, | |
466 REX_XB = 0x43, | |
467 REX_R = 0x44, | |
468 REX_RB = 0x45, | |
469 REX_RX = 0x46, | |
470 REX_RXB = 0x47, | |
471 | |
472 REX_W = 0x48, | |
473 | |
474 REX_WB = 0x49, | |
475 REX_WX = 0x4A, | |
476 REX_WXB = 0x4B, | |
477 REX_WR = 0x4C, | |
478 REX_WRB = 0x4D, | |
479 REX_WRX = 0x4E, | |
480 REX_WRXB = 0x4F | |
481 }; | |
482 | |
483 enum WhichOperand { | |
484 // input to locate_operand, and format code for relocations | |
304 | 485 imm_operand = 0, // embedded 32-bit|64-bit immediate operand |
0 | 486 disp32_operand = 1, // embedded 32-bit displacement or address |
487 call32_operand = 2, // embedded 32-bit self-relative displacement | |
304 | 488 #ifndef _LP64 |
0 | 489 _WhichOperand_limit = 3 |
304 | 490 #else |
491 narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop | |
492 _WhichOperand_limit = 4 | |
493 #endif | |
0 | 494 }; |
495 | |
304 | 496 |
497 | |
498 // NOTE: The general philopsophy of the declarations here is that 64bit versions | |
499 // of instructions are freely declared without the need for wrapping them an ifdef. | |
500 // (Some dangerous instructions are ifdef's out of inappropriate jvm's.) | |
501 // In the .cpp file the implementations are wrapped so that they are dropped out | |
502 // of the resulting jvm. This is done mostly to keep the footprint of KERNEL | |
503 // to the size it was prior to merging up the 32bit and 64bit assemblers. | |
504 // | |
505 // This does mean you'll get a linker/runtime error if you use a 64bit only instruction | |
506 // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down. | |
507 | |
508 private: | |
509 | |
510 | |
511 // 64bit prefixes | |
512 int prefix_and_encode(int reg_enc, bool byteinst = false); | |
513 int prefixq_and_encode(int reg_enc); | |
514 | |
515 int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false); | |
516 int prefixq_and_encode(int dst_enc, int src_enc); | |
517 | |
518 void prefix(Register reg); | |
519 void prefix(Address adr); | |
520 void prefixq(Address adr); | |
521 | |
522 void prefix(Address adr, Register reg, bool byteinst = false); | |
523 void prefixq(Address adr, Register reg); | |
524 | |
525 void prefix(Address adr, XMMRegister reg); | |
526 | |
527 void prefetch_prefix(Address src); | |
528 | |
529 // Helper functions for groups of instructions | |
530 void emit_arith_b(int op1, int op2, Register dst, int imm8); | |
531 | |
532 void emit_arith(int op1, int op2, Register dst, int32_t imm32); | |
533 // only 32bit?? | |
534 void emit_arith(int op1, int op2, Register dst, jobject obj); | |
535 void emit_arith(int op1, int op2, Register dst, Register src); | |
536 | |
537 void emit_operand(Register reg, | |
538 Register base, Register index, Address::ScaleFactor scale, | |
539 int disp, | |
540 RelocationHolder const& rspec, | |
541 int rip_relative_correction = 0); | |
542 | |
543 void emit_operand(Register reg, Address adr, int rip_relative_correction = 0); | |
544 | |
545 // operands that only take the original 32bit registers | |
546 void emit_operand32(Register reg, Address adr); | |
547 | |
548 void emit_operand(XMMRegister reg, | |
549 Register base, Register index, Address::ScaleFactor scale, | |
550 int disp, | |
551 RelocationHolder const& rspec); | |
552 | |
553 void emit_operand(XMMRegister reg, Address adr); | |
554 | |
555 void emit_operand(MMXRegister reg, Address adr); | |
556 | |
557 // workaround gcc (3.2.1-7) bug | |
558 void emit_operand(Address adr, MMXRegister reg); | |
559 | |
560 | |
561 // Immediate-to-memory forms | |
562 void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32); | |
563 | |
564 void emit_farith(int b1, int b2, int i); | |
565 | |
566 | |
567 protected: | |
568 #ifdef ASSERT | |
569 void check_relocation(RelocationHolder const& rspec, int format); | |
570 #endif | |
571 | |
572 inline void emit_long64(jlong x); | |
573 | |
574 void emit_data(jint data, relocInfo::relocType rtype, int format); | |
575 void emit_data(jint data, RelocationHolder const& rspec, int format); | |
576 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0); | |
577 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0); | |
578 | |
579 | |
580 bool reachable(AddressLiteral adr) NOT_LP64({ return true;}); | |
581 | |
582 // These are all easily abused and hence protected | |
583 | |
584 // 32BIT ONLY SECTION | |
585 #ifndef _LP64 | |
586 // Make these disappear in 64bit mode since they would never be correct | |
587 void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY | |
588 void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY | |
589 | |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
590 void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY |
304 | 591 void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY |
592 | |
593 void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY | |
594 #else | |
595 // 64BIT ONLY SECTION | |
596 void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY | |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
597 |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
598 void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
599 void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
600 |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
601 void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
602 void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec); |
304 | 603 #endif // _LP64 |
604 | |
605 // These are unique in that we are ensured by the caller that the 32bit | |
606 // relative in these instructions will always be able to reach the potentially | |
607 // 64bit address described by entry. Since they can take a 64bit address they | |
608 // don't have the 32 suffix like the other instructions in this class. | |
609 | |
610 void call_literal(address entry, RelocationHolder const& rspec); | |
611 void jmp_literal(address entry, RelocationHolder const& rspec); | |
612 | |
613 // Avoid using directly section | |
614 // Instructions in this section are actually usable by anyone without danger | |
615 // of failure but have performance issues that are addressed my enhanced | |
616 // instructions which will do the proper thing base on the particular cpu. | |
617 // We protect them because we don't trust you... | |
618 | |
619 // Don't use next inc() and dec() methods directly. INC & DEC instructions | |
620 // could cause a partial flag stall since they don't set CF flag. | |
621 // Use MacroAssembler::decrement() & MacroAssembler::increment() methods | |
622 // which call inc() & dec() or add() & sub() in accordance with | |
623 // the product flag UseIncDec value. | |
624 | |
625 void decl(Register dst); | |
626 void decl(Address dst); | |
627 void decq(Register dst); | |
628 void decq(Address dst); | |
629 | |
630 void incl(Register dst); | |
631 void incl(Address dst); | |
632 void incq(Register dst); | |
633 void incq(Address dst); | |
634 | |
635 // New cpus require use of movsd and movss to avoid partial register stall | |
636 // when loading from memory. But for old Opteron use movlpd instead of movsd. | |
637 // The selection is done in MacroAssembler::movdbl() and movflt(). | |
638 | |
639 // Move Scalar Single-Precision Floating-Point Values | |
640 void movss(XMMRegister dst, Address src); | |
641 void movss(XMMRegister dst, XMMRegister src); | |
642 void movss(Address dst, XMMRegister src); | |
643 | |
644 // Move Scalar Double-Precision Floating-Point Values | |
645 void movsd(XMMRegister dst, Address src); | |
646 void movsd(XMMRegister dst, XMMRegister src); | |
647 void movsd(Address dst, XMMRegister src); | |
648 void movlpd(XMMRegister dst, Address src); | |
649 | |
650 // New cpus require use of movaps and movapd to avoid partial register stall | |
651 // when moving between registers. | |
652 void movaps(XMMRegister dst, XMMRegister src); | |
653 void movapd(XMMRegister dst, XMMRegister src); | |
654 | |
655 // End avoid using directly | |
656 | |
657 | |
658 // Instruction prefixes | |
659 void prefix(Prefix p); | |
660 | |
0 | 661 public: |
662 | |
663 // Creation | |
664 Assembler(CodeBuffer* code) : AbstractAssembler(code) {} | |
665 | |
666 // Decoding | |
667 static address locate_operand(address inst, WhichOperand which); | |
668 static address locate_next_instruction(address inst); | |
669 | |
304 | 670 // Utilities |
671 | |
672 #ifdef _LP64 | |
673 static bool is_simm(int64_t x, int nbits) { return -( CONST64(1) << (nbits-1) ) <= x && x < ( CONST64(1) << (nbits-1) ); } | |
674 static bool is_simm32(int64_t x) { return x == (int64_t)(int32_t)x; } | |
675 #else | |
676 static bool is_simm(int32_t x, int nbits) { return -( 1 << (nbits-1) ) <= x && x < ( 1 << (nbits-1) ); } | |
677 static bool is_simm32(int32_t x) { return true; } | |
678 #endif // LP64 | |
679 | |
680 // Generic instructions | |
681 // Does 32bit or 64bit as needed for the platform. In some sense these | |
682 // belong in macro assembler but there is no need for both varieties to exist | |
683 | |
684 void lea(Register dst, Address src); | |
685 | |
686 void mov(Register dst, Register src); | |
687 | |
688 void pusha(); | |
689 void popa(); | |
690 | |
691 void pushf(); | |
692 void popf(); | |
693 | |
694 void push(int32_t imm32); | |
695 | |
696 void push(Register src); | |
697 | |
698 void pop(Register dst); | |
699 | |
700 // These are dummies to prevent surprise implicit conversions to Register | |
701 void push(void* v); | |
702 void pop(void* v); | |
703 | |
704 | |
705 // These do register sized moves/scans | |
706 void rep_mov(); | |
707 void rep_set(); | |
708 void repne_scan(); | |
709 #ifdef _LP64 | |
710 void repne_scanl(); | |
711 #endif | |
712 | |
713 // Vanilla instructions in lexical order | |
714 | |
715 void adcl(Register dst, int32_t imm32); | |
0 | 716 void adcl(Register dst, Address src); |
717 void adcl(Register dst, Register src); | |
718 | |
304 | 719 void adcq(Register dst, int32_t imm32); |
720 void adcq(Register dst, Address src); | |
721 void adcq(Register dst, Register src); | |
722 | |
723 | |
724 void addl(Address dst, int32_t imm32); | |
0 | 725 void addl(Address dst, Register src); |
304 | 726 void addl(Register dst, int32_t imm32); |
0 | 727 void addl(Register dst, Address src); |
728 void addl(Register dst, Register src); | |
729 | |
304 | 730 void addq(Address dst, int32_t imm32); |
731 void addq(Address dst, Register src); | |
732 void addq(Register dst, int32_t imm32); | |
733 void addq(Register dst, Address src); | |
734 void addq(Register dst, Register src); | |
735 | |
736 | |
0 | 737 void addr_nop_4(); |
738 void addr_nop_5(); | |
739 void addr_nop_7(); | |
740 void addr_nop_8(); | |
741 | |
304 | 742 // Add Scalar Double-Precision Floating-Point Values |
743 void addsd(XMMRegister dst, Address src); | |
744 void addsd(XMMRegister dst, XMMRegister src); | |
745 | |
746 // Add Scalar Single-Precision Floating-Point Values | |
747 void addss(XMMRegister dst, Address src); | |
748 void addss(XMMRegister dst, XMMRegister src); | |
749 | |
750 void andl(Register dst, int32_t imm32); | |
751 void andl(Register dst, Address src); | |
752 void andl(Register dst, Register src); | |
753 | |
754 void andq(Register dst, int32_t imm32); | |
755 void andq(Register dst, Address src); | |
756 void andq(Register dst, Register src); | |
757 | |
758 | |
759 // Bitwise Logical AND of Packed Double-Precision Floating-Point Values | |
760 void andpd(XMMRegister dst, Address src); | |
761 void andpd(XMMRegister dst, XMMRegister src); | |
762 | |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
763 void bsfl(Register dst, Register src); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
764 void bsrl(Register dst, Register src); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
765 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
766 #ifdef _LP64 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
767 void bsfq(Register dst, Register src); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
768 void bsrq(Register dst, Register src); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
769 #endif |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
770 |
304 | 771 void bswapl(Register reg); |
772 | |
773 void bswapq(Register reg); | |
774 | |
0 | 775 void call(Label& L, relocInfo::relocType rtype); |
776 void call(Register reg); // push pc; pc <- reg | |
777 void call(Address adr); // push pc; pc <- adr | |
778 | |
304 | 779 void cdql(); |
780 | |
781 void cdqq(); | |
782 | |
783 void cld() { emit_byte(0xfc); } | |
784 | |
785 void clflush(Address adr); | |
786 | |
787 void cmovl(Condition cc, Register dst, Register src); | |
788 void cmovl(Condition cc, Register dst, Address src); | |
789 | |
790 void cmovq(Condition cc, Register dst, Register src); | |
791 void cmovq(Condition cc, Register dst, Address src); | |
792 | |
793 | |
794 void cmpb(Address dst, int imm8); | |
795 | |
796 void cmpl(Address dst, int32_t imm32); | |
797 | |
798 void cmpl(Register dst, int32_t imm32); | |
799 void cmpl(Register dst, Register src); | |
800 void cmpl(Register dst, Address src); | |
801 | |
802 void cmpq(Address dst, int32_t imm32); | |
803 void cmpq(Address dst, Register src); | |
804 | |
805 void cmpq(Register dst, int32_t imm32); | |
806 void cmpq(Register dst, Register src); | |
807 void cmpq(Register dst, Address src); | |
808 | |
809 // these are dummies used to catch attempting to convert NULL to Register | |
810 void cmpl(Register dst, void* junk); // dummy | |
811 void cmpq(Register dst, void* junk); // dummy | |
812 | |
813 void cmpw(Address dst, int imm16); | |
814 | |
815 void cmpxchg8 (Address adr); | |
816 | |
817 void cmpxchgl(Register reg, Address adr); | |
818 | |
819 void cmpxchgq(Register reg, Address adr); | |
820 | |
821 // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS | |
822 void comisd(XMMRegister dst, Address src); | |
823 | |
824 // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS | |
825 void comiss(XMMRegister dst, Address src); | |
826 | |
827 // Identify processor type and features | |
828 void cpuid() { | |
829 emit_byte(0x0F); | |
830 emit_byte(0xA2); | |
831 } | |
832 | |
833 // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value | |
834 void cvtsd2ss(XMMRegister dst, XMMRegister src); | |
835 | |
836 // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value | |
837 void cvtsi2sdl(XMMRegister dst, Register src); | |
838 void cvtsi2sdq(XMMRegister dst, Register src); | |
839 | |
840 // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value | |
841 void cvtsi2ssl(XMMRegister dst, Register src); | |
842 void cvtsi2ssq(XMMRegister dst, Register src); | |
843 | |
844 // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value | |
845 void cvtdq2pd(XMMRegister dst, XMMRegister src); | |
846 | |
847 // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value | |
848 void cvtdq2ps(XMMRegister dst, XMMRegister src); | |
849 | |
850 // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value | |
851 void cvtss2sd(XMMRegister dst, XMMRegister src); | |
852 | |
853 // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer | |
854 void cvttsd2sil(Register dst, Address src); | |
855 void cvttsd2sil(Register dst, XMMRegister src); | |
856 void cvttsd2siq(Register dst, XMMRegister src); | |
857 | |
858 // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer | |
859 void cvttss2sil(Register dst, XMMRegister src); | |
860 void cvttss2siq(Register dst, XMMRegister src); | |
861 | |
862 // Divide Scalar Double-Precision Floating-Point Values | |
863 void divsd(XMMRegister dst, Address src); | |
864 void divsd(XMMRegister dst, XMMRegister src); | |
865 | |
866 // Divide Scalar Single-Precision Floating-Point Values | |
867 void divss(XMMRegister dst, Address src); | |
868 void divss(XMMRegister dst, XMMRegister src); | |
869 | |
870 void emms(); | |
871 | |
872 void fabs(); | |
873 | |
874 void fadd(int i); | |
875 | |
876 void fadd_d(Address src); | |
877 void fadd_s(Address src); | |
878 | |
879 // "Alternate" versions of x87 instructions place result down in FPU | |
880 // stack instead of on TOS | |
881 | |
882 void fadda(int i); // "alternate" fadd | |
883 void faddp(int i = 1); | |
884 | |
885 void fchs(); | |
886 | |
887 void fcom(int i); | |
888 | |
889 void fcomp(int i = 1); | |
890 void fcomp_d(Address src); | |
891 void fcomp_s(Address src); | |
892 | |
893 void fcompp(); | |
894 | |
895 void fcos(); | |
896 | |
897 void fdecstp(); | |
898 | |
899 void fdiv(int i); | |
900 void fdiv_d(Address src); | |
901 void fdivr_s(Address src); | |
902 void fdiva(int i); // "alternate" fdiv | |
903 void fdivp(int i = 1); | |
904 | |
905 void fdivr(int i); | |
906 void fdivr_d(Address src); | |
907 void fdiv_s(Address src); | |
908 | |
909 void fdivra(int i); // "alternate" reversed fdiv | |
910 | |
911 void fdivrp(int i = 1); | |
912 | |
913 void ffree(int i = 0); | |
914 | |
915 void fild_d(Address adr); | |
916 void fild_s(Address adr); | |
917 | |
918 void fincstp(); | |
919 | |
920 void finit(); | |
921 | |
922 void fist_s (Address adr); | |
923 void fistp_d(Address adr); | |
924 void fistp_s(Address adr); | |
925 | |
926 void fld1(); | |
927 | |
928 void fld_d(Address adr); | |
929 void fld_s(Address adr); | |
930 void fld_s(int index); | |
931 void fld_x(Address adr); // extended-precision (80-bit) format | |
932 | |
933 void fldcw(Address src); | |
934 | |
935 void fldenv(Address src); | |
936 | |
937 void fldlg2(); | |
938 | |
939 void fldln2(); | |
940 | |
941 void fldz(); | |
942 | |
943 void flog(); | |
944 void flog10(); | |
945 | |
946 void fmul(int i); | |
947 | |
948 void fmul_d(Address src); | |
949 void fmul_s(Address src); | |
950 | |
951 void fmula(int i); // "alternate" fmul | |
952 | |
953 void fmulp(int i = 1); | |
954 | |
955 void fnsave(Address dst); | |
956 | |
957 void fnstcw(Address src); | |
958 | |
959 void fnstsw_ax(); | |
960 | |
961 void fprem(); | |
962 void fprem1(); | |
963 | |
964 void frstor(Address src); | |
965 | |
966 void fsin(); | |
967 | |
968 void fsqrt(); | |
969 | |
970 void fst_d(Address adr); | |
971 void fst_s(Address adr); | |
972 | |
973 void fstp_d(Address adr); | |
974 void fstp_d(int index); | |
975 void fstp_s(Address adr); | |
976 void fstp_x(Address adr); // extended-precision (80-bit) format | |
977 | |
978 void fsub(int i); | |
979 void fsub_d(Address src); | |
980 void fsub_s(Address src); | |
981 | |
982 void fsuba(int i); // "alternate" fsub | |
983 | |
984 void fsubp(int i = 1); | |
985 | |
986 void fsubr(int i); | |
987 void fsubr_d(Address src); | |
988 void fsubr_s(Address src); | |
989 | |
990 void fsubra(int i); // "alternate" reversed fsub | |
991 | |
992 void fsubrp(int i = 1); | |
993 | |
994 void ftan(); | |
995 | |
996 void ftst(); | |
997 | |
998 void fucomi(int i = 1); | |
999 void fucomip(int i = 1); | |
1000 | |
1001 void fwait(); | |
1002 | |
1003 void fxch(int i = 1); | |
1004 | |
1005 void fxrstor(Address src); | |
1006 | |
1007 void fxsave(Address dst); | |
1008 | |
1009 void fyl2x(); | |
1010 | |
1011 void hlt(); | |
1012 | |
1013 void idivl(Register src); | |
1920 | 1014 void divl(Register src); // Unsigned division |
304 | 1015 |
1016 void idivq(Register src); | |
1017 | |
1018 void imull(Register dst, Register src); | |
1019 void imull(Register dst, Register src, int value); | |
1020 | |
1021 void imulq(Register dst, Register src); | |
1022 void imulq(Register dst, Register src, int value); | |
1023 | |
0 | 1024 |
1025 // jcc is the generic conditional branch generator to run- | |
1026 // time routines, jcc is used for branches to labels. jcc | |
1027 // takes a branch opcode (cc) and a label (L) and generates | |
1028 // either a backward branch or a forward branch and links it | |
1029 // to the label fixup chain. Usage: | |
1030 // | |
1031 // Label L; // unbound label | |
1032 // jcc(cc, L); // forward branch to unbound label | |
1033 // bind(L); // bind label to the current pc | |
1034 // jcc(cc, L); // backward branch to bound label | |
1035 // bind(L); // illegal: a label may be bound only once | |
1036 // | |
1037 // Note: The same Label can be used for forward and backward branches | |
1038 // but it may be bound only once. | |
1039 | |
1040 void jcc(Condition cc, Label& L, | |
1041 relocInfo::relocType rtype = relocInfo::none); | |
1042 | |
1043 // Conditional jump to a 8-bit offset to L. | |
1044 // WARNING: be very careful using this for forward jumps. If the label is | |
1045 // not bound within an 8-bit offset of this instruction, a run-time error | |
1046 // will occur. | |
1047 void jccb(Condition cc, Label& L); | |
1048 | |
304 | 1049 void jmp(Address entry); // pc <- entry |
1050 | |
1051 // Label operations & relative jumps (PPUM Appendix D) | |
1052 void jmp(Label& L, relocInfo::relocType rtype = relocInfo::none); // unconditional jump to L | |
1053 | |
1054 void jmp(Register entry); // pc <- entry | |
1055 | |
1056 // Unconditional 8-bit offset jump to L. | |
1057 // WARNING: be very careful using this for forward jumps. If the label is | |
1058 // not bound within an 8-bit offset of this instruction, a run-time error | |
1059 // will occur. | |
1060 void jmpb(Label& L); | |
1061 | |
1062 void ldmxcsr( Address src ); | |
1063 | |
1064 void leal(Register dst, Address src); | |
1065 | |
1066 void leaq(Register dst, Address src); | |
1067 | |
1068 void lfence() { | |
1069 emit_byte(0x0F); | |
1070 emit_byte(0xAE); | |
1071 emit_byte(0xE8); | |
1072 } | |
1073 | |
1074 void lock(); | |
1075 | |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
1076 void lzcntl(Register dst, Register src); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
1077 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
1078 #ifdef _LP64 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
1079 void lzcntq(Register dst, Register src); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
1080 #endif |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
1081 |
304 | 1082 enum Membar_mask_bits { |
1083 StoreStore = 1 << 3, | |
1084 LoadStore = 1 << 2, | |
1085 StoreLoad = 1 << 1, | |
1086 LoadLoad = 1 << 0 | |
1087 }; | |
1088 | |
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
665
diff
changeset
|
1089 // Serializes memory and blows flags |
304 | 1090 void membar(Membar_mask_bits order_constraint) { |
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
665
diff
changeset
|
1091 if (os::is_MP()) { |
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
665
diff
changeset
|
1092 // We only have to handle StoreLoad |
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
665
diff
changeset
|
1093 if (order_constraint & StoreLoad) { |
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
665
diff
changeset
|
1094 // All usable chips support "locked" instructions which suffice |
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
665
diff
changeset
|
1095 // as barriers, and are much faster than the alternative of |
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
665
diff
changeset
|
1096 // using cpuid instruction. We use here a locked add [esp],0. |
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
665
diff
changeset
|
1097 // This is conveniently otherwise a no-op except for blowing |
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
665
diff
changeset
|
1098 // flags. |
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
665
diff
changeset
|
1099 // Any change to this code may need to revisit other places in |
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
665
diff
changeset
|
1100 // the code where this idiom is used, in particular the |
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
665
diff
changeset
|
1101 // orderAccess code. |
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
665
diff
changeset
|
1102 lock(); |
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
665
diff
changeset
|
1103 addl(Address(rsp, 0), 0);// Assert the lock# signal here |
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
665
diff
changeset
|
1104 } |
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
665
diff
changeset
|
1105 } |
304 | 1106 } |
1107 | |
1108 void mfence(); | |
1109 | |
1110 // Moves | |
1111 | |
1112 void mov64(Register dst, int64_t imm64); | |
1113 | |
1114 void movb(Address dst, Register src); | |
1115 void movb(Address dst, int imm8); | |
1116 void movb(Register dst, Address src); | |
1117 | |
1118 void movdl(XMMRegister dst, Register src); | |
1119 void movdl(Register dst, XMMRegister src); | |
1120 | |
1121 // Move Double Quadword | |
1122 void movdq(XMMRegister dst, Register src); | |
1123 void movdq(Register dst, XMMRegister src); | |
1124 | |
1125 // Move Aligned Double Quadword | |
1126 void movdqa(Address dst, XMMRegister src); | |
1127 void movdqa(XMMRegister dst, Address src); | |
1128 void movdqa(XMMRegister dst, XMMRegister src); | |
1129 | |
405 | 1130 // Move Unaligned Double Quadword |
1131 void movdqu(Address dst, XMMRegister src); | |
1132 void movdqu(XMMRegister dst, Address src); | |
1133 void movdqu(XMMRegister dst, XMMRegister src); | |
1134 | |
304 | 1135 void movl(Register dst, int32_t imm32); |
1136 void movl(Address dst, int32_t imm32); | |
1137 void movl(Register dst, Register src); | |
1138 void movl(Register dst, Address src); | |
1139 void movl(Address dst, Register src); | |
1140 | |
1141 // These dummies prevent using movl from converting a zero (like NULL) into Register | |
1142 // by giving the compiler two choices it can't resolve | |
1143 | |
1144 void movl(Address dst, void* junk); | |
1145 void movl(Register dst, void* junk); | |
1146 | |
1147 #ifdef _LP64 | |
1148 void movq(Register dst, Register src); | |
1149 void movq(Register dst, Address src); | |
1150 void movq(Address dst, Register src); | |
1151 #endif | |
1152 | |
1153 void movq(Address dst, MMXRegister src ); | |
1154 void movq(MMXRegister dst, Address src ); | |
1155 | |
1156 #ifdef _LP64 | |
1157 // These dummies prevent using movq from converting a zero (like NULL) into Register | |
1158 // by giving the compiler two choices it can't resolve | |
1159 | |
1160 void movq(Address dst, void* dummy); | |
1161 void movq(Register dst, void* dummy); | |
1162 #endif | |
1163 | |
1164 // Move Quadword | |
1165 void movq(Address dst, XMMRegister src); | |
1166 void movq(XMMRegister dst, Address src); | |
1167 | |
1168 void movsbl(Register dst, Address src); | |
1169 void movsbl(Register dst, Register src); | |
1170 | |
1171 #ifdef _LP64 | |
624 | 1172 void movsbq(Register dst, Address src); |
1173 void movsbq(Register dst, Register src); | |
1174 | |
304 | 1175 // Move signed 32bit immediate to 64bit extending sign |
1176 void movslq(Address dst, int32_t imm64); | |
1177 void movslq(Register dst, int32_t imm64); | |
1178 | |
1179 void movslq(Register dst, Address src); | |
1180 void movslq(Register dst, Register src); | |
1181 void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous | |
1182 #endif | |
1183 | |
1184 void movswl(Register dst, Address src); | |
1185 void movswl(Register dst, Register src); | |
1186 | |
624 | 1187 #ifdef _LP64 |
1188 void movswq(Register dst, Address src); | |
1189 void movswq(Register dst, Register src); | |
1190 #endif | |
1191 | |
304 | 1192 void movw(Address dst, int imm16); |
1193 void movw(Register dst, Address src); | |
1194 void movw(Address dst, Register src); | |
1195 | |
1196 void movzbl(Register dst, Address src); | |
1197 void movzbl(Register dst, Register src); | |
1198 | |
624 | 1199 #ifdef _LP64 |
1200 void movzbq(Register dst, Address src); | |
1201 void movzbq(Register dst, Register src); | |
1202 #endif | |
1203 | |
304 | 1204 void movzwl(Register dst, Address src); |
1205 void movzwl(Register dst, Register src); | |
1206 | |
624 | 1207 #ifdef _LP64 |
1208 void movzwq(Register dst, Address src); | |
1209 void movzwq(Register dst, Register src); | |
1210 #endif | |
1211 | |
304 | 1212 void mull(Address src); |
1213 void mull(Register src); | |
1214 | |
1215 // Multiply Scalar Double-Precision Floating-Point Values | |
1216 void mulsd(XMMRegister dst, Address src); | |
1217 void mulsd(XMMRegister dst, XMMRegister src); | |
1218 | |
1219 // Multiply Scalar Single-Precision Floating-Point Values | |
1220 void mulss(XMMRegister dst, Address src); | |
1221 void mulss(XMMRegister dst, XMMRegister src); | |
1222 | |
1223 void negl(Register dst); | |
1224 | |
1225 #ifdef _LP64 | |
1226 void negq(Register dst); | |
1227 #endif | |
1228 | |
1229 void nop(int i = 1); | |
1230 | |
1231 void notl(Register dst); | |
1232 | |
1233 #ifdef _LP64 | |
1234 void notq(Register dst); | |
1235 #endif | |
1236 | |
1237 void orl(Address dst, int32_t imm32); | |
1238 void orl(Register dst, int32_t imm32); | |
1239 void orl(Register dst, Address src); | |
1240 void orl(Register dst, Register src); | |
1241 | |
1242 void orq(Address dst, int32_t imm32); | |
1243 void orq(Register dst, int32_t imm32); | |
1244 void orq(Register dst, Address src); | |
1245 void orq(Register dst, Register src); | |
1246 | |
681 | 1247 // SSE4.2 string instructions |
1248 void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8); | |
1249 void pcmpestri(XMMRegister xmm1, Address src, int imm8); | |
1250 | |
1060 | 1251 #ifndef _LP64 // no 32bit push/pop on amd64 |
304 | 1252 void popl(Address dst); |
1060 | 1253 #endif |
304 | 1254 |
1255 #ifdef _LP64 | |
1256 void popq(Address dst); | |
1257 #endif | |
1258 | |
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
1259 void popcntl(Register dst, Address src); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
1260 void popcntl(Register dst, Register src); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
1261 |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
1262 #ifdef _LP64 |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
1263 void popcntq(Register dst, Address src); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
1264 void popcntq(Register dst, Register src); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
1265 #endif |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
1266 |
304 | 1267 // Prefetches (SSE, SSE2, 3DNOW only) |
1268 | |
1269 void prefetchnta(Address src); | |
1270 void prefetchr(Address src); | |
1271 void prefetcht0(Address src); | |
1272 void prefetcht1(Address src); | |
1273 void prefetcht2(Address src); | |
1274 void prefetchw(Address src); | |
1275 | |
1276 // Shuffle Packed Doublewords | |
1277 void pshufd(XMMRegister dst, XMMRegister src, int mode); | |
1278 void pshufd(XMMRegister dst, Address src, int mode); | |
1279 | |
1280 // Shuffle Packed Low Words | |
1281 void pshuflw(XMMRegister dst, XMMRegister src, int mode); | |
1282 void pshuflw(XMMRegister dst, Address src, int mode); | |
1283 | |
1284 // Shift Right Logical Quadword Immediate | |
1285 void psrlq(XMMRegister dst, int shift); | |
1286 | |
681 | 1287 // Logical Compare Double Quadword |
1288 void ptest(XMMRegister dst, XMMRegister src); | |
1289 void ptest(XMMRegister dst, Address src); | |
1290 | |
304 | 1291 // Interleave Low Bytes |
1292 void punpcklbw(XMMRegister dst, XMMRegister src); | |
1293 | |
1060 | 1294 #ifndef _LP64 // no 32bit push/pop on amd64 |
304 | 1295 void pushl(Address src); |
1060 | 1296 #endif |
304 | 1297 |
1298 void pushq(Address src); | |
1299 | |
1300 // Xor Packed Byte Integer Values | |
1301 void pxor(XMMRegister dst, Address src); | |
1302 void pxor(XMMRegister dst, XMMRegister src); | |
1303 | |
1304 void rcll(Register dst, int imm8); | |
1305 | |
1306 void rclq(Register dst, int imm8); | |
1307 | |
1308 void ret(int imm16); | |
0 | 1309 |
1310 void sahf(); | |
1311 | |
304 | 1312 void sarl(Register dst, int imm8); |
1313 void sarl(Register dst); | |
1314 | |
1315 void sarq(Register dst, int imm8); | |
1316 void sarq(Register dst); | |
1317 | |
1318 void sbbl(Address dst, int32_t imm32); | |
1319 void sbbl(Register dst, int32_t imm32); | |
1320 void sbbl(Register dst, Address src); | |
1321 void sbbl(Register dst, Register src); | |
1322 | |
1323 void sbbq(Address dst, int32_t imm32); | |
1324 void sbbq(Register dst, int32_t imm32); | |
1325 void sbbq(Register dst, Address src); | |
1326 void sbbq(Register dst, Register src); | |
1327 | |
1328 void setb(Condition cc, Register dst); | |
1329 | |
1330 void shldl(Register dst, Register src); | |
1331 | |
1332 void shll(Register dst, int imm8); | |
1333 void shll(Register dst); | |
1334 | |
1335 void shlq(Register dst, int imm8); | |
1336 void shlq(Register dst); | |
1337 | |
1338 void shrdl(Register dst, Register src); | |
1339 | |
1340 void shrl(Register dst, int imm8); | |
1341 void shrl(Register dst); | |
1342 | |
1343 void shrq(Register dst, int imm8); | |
1344 void shrq(Register dst); | |
1345 | |
1346 void smovl(); // QQQ generic? | |
1347 | |
1348 // Compute Square Root of Scalar Double-Precision Floating-Point Value | |
1349 void sqrtsd(XMMRegister dst, Address src); | |
1350 void sqrtsd(XMMRegister dst, XMMRegister src); | |
1351 | |
1352 void std() { emit_byte(0xfd); } | |
1353 | |
1354 void stmxcsr( Address dst ); | |
1355 | |
1356 void subl(Address dst, int32_t imm32); | |
1357 void subl(Address dst, Register src); | |
1358 void subl(Register dst, int32_t imm32); | |
1359 void subl(Register dst, Address src); | |
1360 void subl(Register dst, Register src); | |
1361 | |
1362 void subq(Address dst, int32_t imm32); | |
1363 void subq(Address dst, Register src); | |
1364 void subq(Register dst, int32_t imm32); | |
1365 void subq(Register dst, Address src); | |
1366 void subq(Register dst, Register src); | |
1367 | |
1368 | |
1369 // Subtract Scalar Double-Precision Floating-Point Values | |
1370 void subsd(XMMRegister dst, Address src); | |
0 | 1371 void subsd(XMMRegister dst, XMMRegister src); |
1372 | |
304 | 1373 // Subtract Scalar Single-Precision Floating-Point Values |
1374 void subss(XMMRegister dst, Address src); | |
1375 void subss(XMMRegister dst, XMMRegister src); | |
1376 | |
1377 void testb(Register dst, int imm8); | |
1378 | |
1379 void testl(Register dst, int32_t imm32); | |
1380 void testl(Register dst, Register src); | |
1381 void testl(Register dst, Address src); | |
1382 | |
1383 void testq(Register dst, int32_t imm32); | |
1384 void testq(Register dst, Register src); | |
1385 | |
1386 | |
1387 // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS | |
1388 void ucomisd(XMMRegister dst, Address src); | |
0 | 1389 void ucomisd(XMMRegister dst, XMMRegister src); |
1390 | |
304 | 1391 // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS |
1392 void ucomiss(XMMRegister dst, Address src); | |
1393 void ucomiss(XMMRegister dst, XMMRegister src); | |
1394 | |
1395 void xaddl(Address dst, Register src); | |
1396 | |
1397 void xaddq(Address dst, Register src); | |
1398 | |
1399 void xchgl(Register reg, Address adr); | |
1400 void xchgl(Register dst, Register src); | |
1401 | |
1402 void xchgq(Register reg, Address adr); | |
1403 void xchgq(Register dst, Register src); | |
1404 | |
1405 void xorl(Register dst, int32_t imm32); | |
1406 void xorl(Register dst, Address src); | |
1407 void xorl(Register dst, Register src); | |
1408 | |
1409 void xorq(Register dst, Address src); | |
1410 void xorq(Register dst, Register src); | |
1411 | |
1412 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values | |
1413 void xorpd(XMMRegister dst, Address src); | |
1414 void xorpd(XMMRegister dst, XMMRegister src); | |
1415 | |
1416 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values | |
1417 void xorps(XMMRegister dst, Address src); | |
0 | 1418 void xorps(XMMRegister dst, XMMRegister src); |
304 | 1419 |
1420 void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0 | |
0 | 1421 }; |
1422 | |
1423 | |
1424 // MacroAssembler extends Assembler by frequently used macros. | |
1425 // | |
1426 // Instructions for which a 'better' code sequence exists depending | |
1427 // on arguments should also go in here. | |
1428 | |
1429 class MacroAssembler: public Assembler { | |
342
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
ysr
parents:
71
diff
changeset
|
1430 friend class LIR_Assembler; |
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
ysr
parents:
71
diff
changeset
|
1431 friend class Runtime1; // as_Address() |
0 | 1432 protected: |
1433 | |
1434 Address as_Address(AddressLiteral adr); | |
1435 Address as_Address(ArrayAddress adr); | |
1436 | |
1437 // Support for VM calls | |
1438 // | |
1439 // This is the base routine called by the different versions of call_VM_leaf. The interpreter | |
1440 // may customize this version by overriding it for its purposes (e.g., to save/restore | |
1441 // additional registers when doing a VM call). | |
1442 #ifdef CC_INTERP | |
1443 // c++ interpreter never wants to use interp_masm version of call_VM | |
1444 #define VIRTUAL | |
1445 #else | |
1446 #define VIRTUAL virtual | |
1447 #endif | |
1448 | |
1449 VIRTUAL void call_VM_leaf_base( | |
1450 address entry_point, // the entry point | |
1451 int number_of_arguments // the number of arguments to pop after the call | |
1452 ); | |
1453 | |
1454 // This is the base routine called by the different versions of call_VM. The interpreter | |
1455 // may customize this version by overriding it for its purposes (e.g., to save/restore | |
1456 // additional registers when doing a VM call). | |
1457 // | |
1458 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base | |
1459 // returns the register which contains the thread upon return. If a thread register has been | |
1460 // specified, the return value will correspond to that register. If no last_java_sp is specified | |
1461 // (noreg) than rsp will be used instead. | |
1462 VIRTUAL void call_VM_base( // returns the register containing the thread upon return | |
1463 Register oop_result, // where an oop-result ends up if any; use noreg otherwise | |
1464 Register java_thread, // the thread if computed before ; use noreg otherwise | |
1465 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise | |
1466 address entry_point, // the entry point | |
1467 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call | |
1468 bool check_exceptions // whether to check for pending exceptions after return | |
1469 ); | |
1470 | |
1471 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code. | |
1472 // The implementation is only non-empty for the InterpreterMacroAssembler, | |
1473 // as only the interpreter handles PopFrame and ForceEarlyReturn requests. | |
1474 virtual void check_and_handle_popframe(Register java_thread); | |
1475 virtual void check_and_handle_earlyret(Register java_thread); | |
1476 | |
1477 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true); | |
1478 | |
1479 // helpers for FPU flag access | |
1480 // tmp is a temporary register, if none is available use noreg | |
1481 void save_rax (Register tmp); | |
1482 void restore_rax(Register tmp); | |
1483 | |
1484 public: | |
1485 MacroAssembler(CodeBuffer* code) : Assembler(code) {} | |
1486 | |
1487 // Support for NULL-checks | |
1488 // | |
1489 // Generates code that causes a NULL OS exception if the content of reg is NULL. | |
1490 // If the accessed location is M[reg + offset] and the offset is known, provide the | |
1491 // offset. No explicit code generation is needed if the offset is within a certain | |
1492 // range (0 <= offset <= page_size). | |
1493 | |
1494 void null_check(Register reg, int offset = -1); | |
168
7793bd37a336
6705887: Compressed Oops: generate x64 addressing and implicit null checks with narrow oops
kvn
parents:
71
diff
changeset
|
1495 static bool needs_explicit_null_check(intptr_t offset); |
0 | 1496 |
1497 // Required platform-specific helpers for Label::patch_instructions. | |
1498 // They _shadow_ the declarations in AbstractAssembler, which are undefined. | |
1499 void pd_patch_instruction(address branch, address target); | |
1500 #ifndef PRODUCT | |
1501 static void pd_print_patched_instruction(address branch); | |
1502 #endif | |
1503 | |
1504 // The following 4 methods return the offset of the appropriate move instruction | |
1505 | |
622
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
1506 // Support for fast byte/short loading with zero extension (depending on particular CPU) |
0 | 1507 int load_unsigned_byte(Register dst, Address src); |
622
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
1508 int load_unsigned_short(Register dst, Address src); |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
1509 |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
1510 // Support for fast byte/short loading with sign extension (depending on particular CPU) |
0 | 1511 int load_signed_byte(Register dst, Address src); |
622
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
1512 int load_signed_short(Register dst, Address src); |
0 | 1513 |
1514 // Support for sign-extension (hi:lo = extend_sign(lo)) | |
1515 void extend_sign(Register hi, Register lo); | |
1516 | |
622
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
1517 // Loading values by size and signed-ness |
1503 | 1518 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed); |
622
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
1519 |
0 | 1520 // Support for inc/dec with optimal instruction selection depending on value |
304 | 1521 |
1522 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; } | |
1523 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; } | |
1524 | |
1525 void decrementl(Address dst, int value = 1); | |
1526 void decrementl(Register reg, int value = 1); | |
1527 | |
1528 void decrementq(Register reg, int value = 1); | |
1529 void decrementq(Address dst, int value = 1); | |
1530 | |
1531 void incrementl(Address dst, int value = 1); | |
1532 void incrementl(Register reg, int value = 1); | |
1533 | |
1534 void incrementq(Register reg, int value = 1); | |
1535 void incrementq(Address dst, int value = 1); | |
1536 | |
0 | 1537 |
1538 // Support optimal SSE move instructions. | |
1539 void movflt(XMMRegister dst, XMMRegister src) { | |
1540 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; } | |
1541 else { movss (dst, src); return; } | |
1542 } | |
1543 void movflt(XMMRegister dst, Address src) { movss(dst, src); } | |
1544 void movflt(XMMRegister dst, AddressLiteral src); | |
1545 void movflt(Address dst, XMMRegister src) { movss(dst, src); } | |
1546 | |
1547 void movdbl(XMMRegister dst, XMMRegister src) { | |
1548 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; } | |
1549 else { movsd (dst, src); return; } | |
1550 } | |
1551 | |
1552 void movdbl(XMMRegister dst, AddressLiteral src); | |
1553 | |
1554 void movdbl(XMMRegister dst, Address src) { | |
1555 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; } | |
1556 else { movlpd(dst, src); return; } | |
1557 } | |
1558 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); } | |
1559 | |
304 | 1560 void incrementl(AddressLiteral dst); |
1561 void incrementl(ArrayAddress dst); | |
0 | 1562 |
1563 // Alignment | |
1564 void align(int modulus); | |
1565 | |
1566 // Misc | |
1567 void fat_nop(); // 5 byte nop | |
1568 | |
1569 // Stack frame creation/removal | |
1570 void enter(); | |
1571 void leave(); | |
1572 | |
1573 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information) | |
1574 // The pointer will be loaded into the thread register. | |
1575 void get_thread(Register thread); | |
1576 | |
362 | 1577 |
0 | 1578 // Support for VM calls |
1579 // | |
1580 // It is imperative that all calls into the VM are handled via the call_VM macros. | |
1581 // They make sure that the stack linkage is setup correctly. call_VM's correspond | |
1582 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points. | |
1583 | |
304 | 1584 |
1585 void call_VM(Register oop_result, | |
1586 address entry_point, | |
1587 bool check_exceptions = true); | |
1588 void call_VM(Register oop_result, | |
1589 address entry_point, | |
1590 Register arg_1, | |
1591 bool check_exceptions = true); | |
1592 void call_VM(Register oop_result, | |
1593 address entry_point, | |
1594 Register arg_1, Register arg_2, | |
1595 bool check_exceptions = true); | |
1596 void call_VM(Register oop_result, | |
1597 address entry_point, | |
1598 Register arg_1, Register arg_2, Register arg_3, | |
1599 bool check_exceptions = true); | |
1600 | |
1601 // Overloadings with last_Java_sp | |
1602 void call_VM(Register oop_result, | |
1603 Register last_java_sp, | |
1604 address entry_point, | |
1605 int number_of_arguments = 0, | |
1606 bool check_exceptions = true); | |
1607 void call_VM(Register oop_result, | |
1608 Register last_java_sp, | |
1609 address entry_point, | |
1610 Register arg_1, bool | |
1611 check_exceptions = true); | |
1612 void call_VM(Register oop_result, | |
1613 Register last_java_sp, | |
1614 address entry_point, | |
1615 Register arg_1, Register arg_2, | |
1616 bool check_exceptions = true); | |
1617 void call_VM(Register oop_result, | |
1618 Register last_java_sp, | |
1619 address entry_point, | |
1620 Register arg_1, Register arg_2, Register arg_3, | |
1621 bool check_exceptions = true); | |
1622 | |
1623 void call_VM_leaf(address entry_point, | |
1624 int number_of_arguments = 0); | |
1625 void call_VM_leaf(address entry_point, | |
1626 Register arg_1); | |
1627 void call_VM_leaf(address entry_point, | |
1628 Register arg_1, Register arg_2); | |
1629 void call_VM_leaf(address entry_point, | |
1630 Register arg_1, Register arg_2, Register arg_3); | |
0 | 1631 |
1632 // last Java Frame (fills frame anchor) | |
304 | 1633 void set_last_Java_frame(Register thread, |
1634 Register last_java_sp, | |
1635 Register last_java_fp, | |
1636 address last_java_pc); | |
1637 | |
1638 // thread in the default location (r15_thread on 64bit) | |
1639 void set_last_Java_frame(Register last_java_sp, | |
1640 Register last_java_fp, | |
1641 address last_java_pc); | |
1642 | |
0 | 1643 void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc); |
1644 | |
304 | 1645 // thread in the default location (r15_thread on 64bit) |
1646 void reset_last_Java_frame(bool clear_fp, bool clear_pc); | |
1647 | |
0 | 1648 // Stores |
1649 void store_check(Register obj); // store check for obj - register is destroyed afterwards | |
1650 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed) | |
1651 | |
362 | 1652 void g1_write_barrier_pre(Register obj, |
1653 #ifndef _LP64 | |
1654 Register thread, | |
1655 #endif | |
1656 Register tmp, | |
1657 Register tmp2, | |
1658 bool tosca_live); | |
1659 void g1_write_barrier_post(Register store_addr, | |
1660 Register new_val, | |
1661 #ifndef _LP64 | |
1662 Register thread, | |
1663 #endif | |
1664 Register tmp, | |
1665 Register tmp2); | |
342
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
ysr
parents:
71
diff
changeset
|
1666 |
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
ysr
parents:
71
diff
changeset
|
1667 |
0 | 1668 // split store_check(Register obj) to enhance instruction interleaving |
1669 void store_check_part_1(Register obj); | |
1670 void store_check_part_2(Register obj); | |
1671 | |
1672 // C 'boolean' to Java boolean: x == 0 ? 0 : 1 | |
1673 void c2bool(Register x); | |
1674 | |
1675 // C++ bool manipulation | |
1676 | |
1677 void movbool(Register dst, Address src); | |
1678 void movbool(Address dst, bool boolconst); | |
1679 void movbool(Address dst, Register src); | |
1680 void testbool(Register dst); | |
1681 | |
304 | 1682 // oop manipulations |
1683 void load_klass(Register dst, Register src); | |
1684 void store_klass(Register dst, Register src); | |
1685 | |
1846 | 1686 void load_heap_oop(Register dst, Address src); |
1687 void store_heap_oop(Address dst, Register src); | |
1688 | |
1689 // Used for storing NULL. All other oop constants should be | |
1690 // stored using routines that take a jobject. | |
1691 void store_heap_oop_null(Address dst); | |
1692 | |
304 | 1693 void load_prototype_header(Register dst, Register src); |
1694 | |
1695 #ifdef _LP64 | |
1696 void store_klass_gap(Register dst, Register src); | |
1697 | |
1047
beb8f45ee9f0
6889740: G1: OpenDS fails with "unhandled exception in compiled code"
johnc
parents:
986
diff
changeset
|
1698 // This dummy is to prevent a call to store_heap_oop from |
beb8f45ee9f0
6889740: G1: OpenDS fails with "unhandled exception in compiled code"
johnc
parents:
986
diff
changeset
|
1699 // converting a zero (like NULL) into a Register by giving |
beb8f45ee9f0
6889740: G1: OpenDS fails with "unhandled exception in compiled code"
johnc
parents:
986
diff
changeset
|
1700 // the compiler two choices it can't resolve |
beb8f45ee9f0
6889740: G1: OpenDS fails with "unhandled exception in compiled code"
johnc
parents:
986
diff
changeset
|
1701 |
beb8f45ee9f0
6889740: G1: OpenDS fails with "unhandled exception in compiled code"
johnc
parents:
986
diff
changeset
|
1702 void store_heap_oop(Address dst, void* dummy); |
beb8f45ee9f0
6889740: G1: OpenDS fails with "unhandled exception in compiled code"
johnc
parents:
986
diff
changeset
|
1703 |
304 | 1704 void encode_heap_oop(Register r); |
1705 void decode_heap_oop(Register r); | |
1706 void encode_heap_oop_not_null(Register r); | |
1707 void decode_heap_oop_not_null(Register r); | |
1708 void encode_heap_oop_not_null(Register dst, Register src); | |
1709 void decode_heap_oop_not_null(Register dst, Register src); | |
1710 | |
1711 void set_narrow_oop(Register dst, jobject obj); | |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
1712 void set_narrow_oop(Address dst, jobject obj); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
1713 void cmp_narrow_oop(Register dst, jobject obj); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
1714 void cmp_narrow_oop(Address dst, jobject obj); |
304 | 1715 |
1716 // if heap base register is used - reinit it with the correct value | |
1717 void reinit_heapbase(); | |
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1579
diff
changeset
|
1718 |
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1579
diff
changeset
|
1719 DEBUG_ONLY(void verify_heapbase(const char* msg);) |
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1579
diff
changeset
|
1720 |
304 | 1721 #endif // _LP64 |
1722 | |
1723 // Int division/remainder for Java | |
0 | 1724 // (as idivl, but checks for special case as described in JVM spec.) |
1725 // returns idivl instruction offset for implicit exception handling | |
1726 int corrected_idivl(Register reg); | |
1727 | |
304 | 1728 // Long division/remainder for Java |
1729 // (as idivq, but checks for special case as described in JVM spec.) | |
1730 // returns idivq instruction offset for implicit exception handling | |
1731 int corrected_idivq(Register reg); | |
1732 | |
0 | 1733 void int3(); |
1734 | |
304 | 1735 // Long operation macros for a 32bit cpu |
0 | 1736 // Long negation for Java |
1737 void lneg(Register hi, Register lo); | |
1738 | |
1739 // Long multiplication for Java | |
304 | 1740 // (destroys contents of eax, ebx, ecx and edx) |
0 | 1741 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y |
1742 | |
1743 // Long shifts for Java | |
1744 // (semantics as described in JVM spec.) | |
1745 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f) | |
1746 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f) | |
1747 | |
1748 // Long compare for Java | |
1749 // (semantics as described in JVM spec.) | |
1750 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y) | |
1751 | |
304 | 1752 |
1753 // misc | |
1754 | |
1755 // Sign extension | |
1756 void sign_extend_short(Register reg); | |
1757 void sign_extend_byte(Register reg); | |
1758 | |
1759 // Division by power of 2, rounding towards 0 | |
1760 void division_with_shift(Register reg, int shift_value); | |
1761 | |
0 | 1762 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows: |
1763 // | |
1764 // CF (corresponds to C0) if x < y | |
1765 // PF (corresponds to C2) if unordered | |
1766 // ZF (corresponds to C3) if x = y | |
1767 // | |
1768 // The arguments are in reversed order on the stack (i.e., top of stack is first argument). | |
1769 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code) | |
1770 void fcmp(Register tmp); | |
1771 // Variant of the above which allows y to be further down the stack | |
1772 // and which only pops x and y if specified. If pop_right is | |
1773 // specified then pop_left must also be specified. | |
1774 void fcmp(Register tmp, int index, bool pop_left, bool pop_right); | |
1775 | |
1776 // Floating-point comparison for Java | |
1777 // Compares the top-most stack entries on the FPU stack and stores the result in dst. | |
1778 // The arguments are in reversed order on the stack (i.e., top of stack is first argument). | |
1779 // (semantics as described in JVM spec.) | |
1780 void fcmp2int(Register dst, bool unordered_is_less); | |
1781 // Variant of the above which allows y to be further down the stack | |
1782 // and which only pops x and y if specified. If pop_right is | |
1783 // specified then pop_left must also be specified. | |
1784 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right); | |
1785 | |
1786 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards) | |
1787 // tmp is a temporary register, if none is available use noreg | |
1788 void fremr(Register tmp); | |
1789 | |
1790 | |
1791 // same as fcmp2int, but using SSE2 | |
1792 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less); | |
1793 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less); | |
1794 | |
1795 // Inlined sin/cos generator for Java; must not use CPU instruction | |
1796 // directly on Intel as it does not have high enough precision | |
1797 // outside of the range [-pi/4, pi/4]. Extra argument indicate the | |
1798 // number of FPU stack slots in use; all but the topmost will | |
1799 // require saving if a slow case is necessary. Assumes argument is | |
1800 // on FP TOS; result is on FP TOS. No cpu registers are changed by | |
1801 // this code. | |
1802 void trigfunc(char trig, int num_fpu_regs_in_use = 1); | |
1803 | |
1804 // branch to L if FPU flag C2 is set/not set | |
1805 // tmp is a temporary register, if none is available use noreg | |
1806 void jC2 (Register tmp, Label& L); | |
1807 void jnC2(Register tmp, Label& L); | |
1808 | |
1809 // Pop ST (ffree & fincstp combined) | |
1810 void fpop(); | |
1811 | |
1812 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack | |
1813 void push_fTOS(); | |
1814 | |
1815 // pops double TOS element from CPU stack and pushes on FPU stack | |
1816 void pop_fTOS(); | |
1817 | |
1818 void empty_FPU_stack(); | |
1819 | |
1820 void push_IU_state(); | |
1821 void pop_IU_state(); | |
1822 | |
1823 void push_FPU_state(); | |
1824 void pop_FPU_state(); | |
1825 | |
1826 void push_CPU_state(); | |
1827 void pop_CPU_state(); | |
1828 | |
1829 // Round up to a power of two | |
1830 void round_to(Register reg, int modulus); | |
1831 | |
1832 // Callee saved registers handling | |
1833 void push_callee_saved_registers(); | |
1834 void pop_callee_saved_registers(); | |
1835 | |
1836 // allocation | |
1837 void eden_allocate( | |
1838 Register obj, // result: pointer to object after successful allocation | |
1839 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise | |
1840 int con_size_in_bytes, // object size in bytes if known at compile time | |
1841 Register t1, // temp register | |
1842 Label& slow_case // continuation point if fast allocation fails | |
1843 ); | |
1844 void tlab_allocate( | |
1845 Register obj, // result: pointer to object after successful allocation | |
1846 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise | |
1847 int con_size_in_bytes, // object size in bytes if known at compile time | |
1848 Register t1, // temp register | |
1849 Register t2, // temp register | |
1850 Label& slow_case // continuation point if fast allocation fails | |
1851 ); | |
1852 void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); | |
1853 | |
623
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
1854 // interface method calling |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
1855 void lookup_interface_method(Register recv_klass, |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
1856 Register intf_klass, |
665
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
644
diff
changeset
|
1857 RegisterOrConstant itable_index, |
623
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
1858 Register method_result, |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
1859 Register scan_temp, |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
1860 Label& no_such_interface); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
1861 |
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1862 // Test sub_klass against super_klass, with fast and slow paths. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1863 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1864 // The fast path produces a tri-state answer: yes / no / maybe-slow. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1865 // One of the three labels can be NULL, meaning take the fall-through. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1866 // If super_check_offset is -1, the value is loaded up from super_klass. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1867 // No registers are killed, except temp_reg. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1868 void check_klass_subtype_fast_path(Register sub_klass, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1869 Register super_klass, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1870 Register temp_reg, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1871 Label* L_success, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1872 Label* L_failure, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1873 Label* L_slow_path, |
665
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
644
diff
changeset
|
1874 RegisterOrConstant super_check_offset = RegisterOrConstant(-1)); |
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1875 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1876 // The rest of the type check; must be wired to a corresponding fast path. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1877 // It does not repeat the fast path logic, so don't use it standalone. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1878 // The temp_reg and temp2_reg can be noreg, if no temps are available. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1879 // Updates the sub's secondary super cache as necessary. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1880 // If set_cond_codes, condition codes will be Z on success, NZ on failure. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1881 void check_klass_subtype_slow_path(Register sub_klass, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1882 Register super_klass, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1883 Register temp_reg, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1884 Register temp2_reg, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1885 Label* L_success, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1886 Label* L_failure, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1887 bool set_cond_codes = false); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1888 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1889 // Simplified, combined version, good for typical uses. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1890 // Falls through on failure. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1891 void check_klass_subtype(Register sub_klass, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1892 Register super_klass, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1893 Register temp_reg, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1894 Label& L_success); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1895 |
710 | 1896 // method handles (JSR 292) |
1897 void check_method_handle_type(Register mtype_reg, Register mh_reg, | |
1898 Register temp_reg, | |
1899 Label& wrong_method_type); | |
1900 void load_method_handle_vmslots(Register vmslots_reg, Register mh_reg, | |
1901 Register temp_reg); | |
1902 void jump_to_method_handle_entry(Register mh_reg, Register temp_reg); | |
1903 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0); | |
1904 | |
1905 | |
0 | 1906 //---- |
1907 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0 | |
1908 | |
1909 // Debugging | |
304 | 1910 |
1911 // only if +VerifyOops | |
1912 void verify_oop(Register reg, const char* s = "broken oop"); | |
0 | 1913 void verify_oop_addr(Address addr, const char * s = "broken oop addr"); |
1914 | |
304 | 1915 // only if +VerifyFPU |
1916 void verify_FPU(int stack_depth, const char* s = "illegal FPU state"); | |
1917 | |
1918 // prints msg, dumps registers and stops execution | |
1919 void stop(const char* msg); | |
1920 | |
1921 // prints msg and continues | |
1922 void warn(const char* msg); | |
1923 | |
1924 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg); | |
1925 static void debug64(char* msg, int64_t pc, int64_t regs[]); | |
1926 | |
0 | 1927 void os_breakpoint(); |
304 | 1928 |
0 | 1929 void untested() { stop("untested"); } |
304 | 1930 |
1846 | 1931 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); } |
304 | 1932 |
0 | 1933 void should_not_reach_here() { stop("should not reach here"); } |
304 | 1934 |
0 | 1935 void print_CPU_state(); |
1936 | |
1937 // Stack overflow checking | |
1938 void bang_stack_with_offset(int offset) { | |
1939 // stack grows down, caller passes positive offset | |
1940 assert(offset > 0, "must bang with negative offset"); | |
1941 movl(Address(rsp, (-offset)), rax); | |
1942 } | |
1943 | |
1944 // Writes to stack successive pages until offset reached to check for | |
1945 // stack overflow + shadow pages. Also, clobbers tmp | |
1946 void bang_stack_size(Register size, Register tmp); | |
1947 | |
665
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
644
diff
changeset
|
1948 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, |
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
644
diff
changeset
|
1949 Register tmp, |
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
644
diff
changeset
|
1950 int offset); |
622
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
1951 |
0 | 1952 // Support for serializing memory accesses between threads |
1953 void serialize_memory(Register thread, Register tmp); | |
1954 | |
1955 void verify_tlab(); | |
1956 | |
1957 // Biased locking support | |
1958 // lock_reg and obj_reg must be loaded up with the appropriate values. | |
1959 // swap_reg must be rax, and is killed. | |
1960 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will | |
1961 // be killed; if not supplied, push/pop will be used internally to | |
1962 // allocate a temporary (inefficient, avoid if possible). | |
1963 // Optional slow case is for implementations (interpreter and C1) which branch to | |
1964 // slow case directly. Leaves condition codes set for C2's Fast_Lock node. | |
1965 // Returns offset of first potentially-faulting instruction for null | |
1966 // check info (currently consumed only by C1). If | |
1967 // swap_reg_contains_mark is true then returns -1 as it is assumed | |
1968 // the calling code has already passed any potential faults. | |
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
405
diff
changeset
|
1969 int biased_locking_enter(Register lock_reg, Register obj_reg, |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
405
diff
changeset
|
1970 Register swap_reg, Register tmp_reg, |
0 | 1971 bool swap_reg_contains_mark, |
1972 Label& done, Label* slow_case = NULL, | |
1973 BiasedLockingCounters* counters = NULL); | |
1974 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done); | |
1975 | |
1976 | |
1977 Condition negate_condition(Condition cond); | |
1978 | |
1979 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit | |
1980 // operands. In general the names are modified to avoid hiding the instruction in Assembler | |
1981 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers | |
1982 // here in MacroAssembler. The major exception to this rule is call | |
1983 | |
1984 // Arithmetics | |
1985 | |
304 | 1986 |
1987 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; } | |
1988 void addptr(Address dst, Register src); | |
1989 | |
1990 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); } | |
1991 void addptr(Register dst, int32_t src); | |
1992 void addptr(Register dst, Register src); | |
1993 | |
1994 void andptr(Register dst, int32_t src); | |
1995 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; } | |
1996 | |
1997 void cmp8(AddressLiteral src1, int imm); | |
1998 | |
1999 // renamed to drag out the casting of address to int32_t/intptr_t | |
0 | 2000 void cmp32(Register src1, int32_t imm); |
2001 | |
2002 void cmp32(AddressLiteral src1, int32_t imm); | |
2003 // compare reg - mem, or reg - &mem | |
2004 void cmp32(Register src1, AddressLiteral src2); | |
2005 | |
2006 void cmp32(Register src1, Address src2); | |
2007 | |
304 | 2008 #ifndef _LP64 |
2009 void cmpoop(Address dst, jobject obj); | |
2010 void cmpoop(Register dst, jobject obj); | |
2011 #endif // _LP64 | |
2012 | |
0 | 2013 // NOTE src2 must be the lval. This is NOT an mem-mem compare |
2014 void cmpptr(Address src1, AddressLiteral src2); | |
2015 | |
2016 void cmpptr(Register src1, AddressLiteral src2); | |
2017 | |
304 | 2018 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } |
2019 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } | |
2020 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } | |
2021 | |
2022 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } | |
2023 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } | |
2024 | |
2025 // cmp64 to avoild hiding cmpq | |
2026 void cmp64(Register src1, AddressLiteral src); | |
2027 | |
2028 void cmpxchgptr(Register reg, Address adr); | |
2029 | |
2030 void locked_cmpxchgptr(Register reg, AddressLiteral adr); | |
2031 | |
2032 | |
2033 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); } | |
2034 | |
2035 | |
2036 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); } | |
2037 | |
2038 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); } | |
2039 | |
2040 void shlptr(Register dst, int32_t shift); | |
2041 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); } | |
2042 | |
2043 void shrptr(Register dst, int32_t shift); | |
2044 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); } | |
2045 | |
2046 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); } | |
2047 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); } | |
2048 | |
2049 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); } | |
2050 | |
2051 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); } | |
2052 void subptr(Register dst, int32_t src); | |
2053 void subptr(Register dst, Register src); | |
2054 | |
2055 | |
2056 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); } | |
2057 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); } | |
2058 | |
2059 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; } | |
2060 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; } | |
2061 | |
2062 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; } | |
2063 | |
2064 | |
0 | 2065 |
2066 // Helper functions for statistics gathering. | |
2067 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes. | |
2068 void cond_inc32(Condition cond, AddressLiteral counter_addr); | |
2069 // Unconditional atomic increment. | |
2070 void atomic_incl(AddressLiteral counter_addr); | |
2071 | |
2072 void lea(Register dst, AddressLiteral adr); | |
2073 void lea(Address dst, AddressLiteral adr); | |
304 | 2074 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); } |
2075 | |
2076 void leal32(Register dst, Address src) { leal(dst, src); } | |
2077 | |
2078 void test32(Register src1, AddressLiteral src2); | |
2079 | |
2080 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } | |
2081 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } | |
2082 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } | |
2083 | |
2084 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); } | |
2085 void testptr(Register src1, Register src2); | |
2086 | |
2087 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); } | |
2088 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); } | |
0 | 2089 |
2090 // Calls | |
2091 | |
2092 void call(Label& L, relocInfo::relocType rtype); | |
2093 void call(Register entry); | |
2094 | |
2095 // NOTE: this call tranfers to the effective address of entry NOT | |
2096 // the address contained by entry. This is because this is more natural | |
2097 // for jumps/calls. | |
2098 void call(AddressLiteral entry); | |
2099 | |
2100 // Jumps | |
2101 | |
2102 // NOTE: these jumps tranfer to the effective address of dst NOT | |
2103 // the address contained by dst. This is because this is more natural | |
2104 // for jumps/calls. | |
2105 void jump(AddressLiteral dst); | |
2106 void jump_cc(Condition cc, AddressLiteral dst); | |
2107 | |
2108 // 32bit can do a case table jump in one instruction but we no longer allow the base | |
2109 // to be installed in the Address class. This jump will tranfers to the address | |
2110 // contained in the location described by entry (not the address of entry) | |
2111 void jump(ArrayAddress entry); | |
2112 | |
2113 // Floating | |
2114 | |
2115 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); } | |
2116 void andpd(XMMRegister dst, AddressLiteral src); | |
2117 | |
2118 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); } | |
2119 void comiss(XMMRegister dst, AddressLiteral src); | |
2120 | |
2121 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); } | |
2122 void comisd(XMMRegister dst, AddressLiteral src); | |
2123 | |
2124 void fldcw(Address src) { Assembler::fldcw(src); } | |
2125 void fldcw(AddressLiteral src); | |
2126 | |
2127 void fld_s(int index) { Assembler::fld_s(index); } | |
2128 void fld_s(Address src) { Assembler::fld_s(src); } | |
2129 void fld_s(AddressLiteral src); | |
2130 | |
2131 void fld_d(Address src) { Assembler::fld_d(src); } | |
2132 void fld_d(AddressLiteral src); | |
2133 | |
2134 void fld_x(Address src) { Assembler::fld_x(src); } | |
2135 void fld_x(AddressLiteral src); | |
2136 | |
2137 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); } | |
2138 void ldmxcsr(AddressLiteral src); | |
2139 | |
304 | 2140 private: |
2141 // these are private because users should be doing movflt/movdbl | |
2142 | |
0 | 2143 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); } |
2144 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); } | |
2145 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); } | |
2146 void movss(XMMRegister dst, AddressLiteral src); | |
2147 | |
304 | 2148 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); } |
2149 void movlpd(XMMRegister dst, AddressLiteral src); | |
2150 | |
2151 public: | |
2152 | |
0 | 2153 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); } |
2154 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); } | |
2155 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); } | |
2156 void movsd(XMMRegister dst, AddressLiteral src); | |
2157 | |
2158 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); } | |
2159 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); } | |
2160 void ucomiss(XMMRegister dst, AddressLiteral src); | |
2161 | |
2162 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); } | |
2163 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); } | |
2164 void ucomisd(XMMRegister dst, AddressLiteral src); | |
2165 | |
2166 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values | |
2167 void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); } | |
2168 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); } | |
2169 void xorpd(XMMRegister dst, AddressLiteral src); | |
2170 | |
2171 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values | |
2172 void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); } | |
2173 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); } | |
2174 void xorps(XMMRegister dst, AddressLiteral src); | |
2175 | |
2176 // Data | |
2177 | |
304 | 2178 void cmov(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); } |
2179 | |
2180 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); } | |
2181 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); } | |
2182 | |
0 | 2183 void movoop(Register dst, jobject obj); |
2184 void movoop(Address dst, jobject obj); | |
2185 | |
2186 void movptr(ArrayAddress dst, Register src); | |
2187 // can this do an lea? | |
2188 void movptr(Register dst, ArrayAddress src); | |
2189 | |
304 | 2190 void movptr(Register dst, Address src); |
2191 | |
0 | 2192 void movptr(Register dst, AddressLiteral src); |
2193 | |
304 | 2194 void movptr(Register dst, intptr_t src); |
2195 void movptr(Register dst, Register src); | |
2196 void movptr(Address dst, intptr_t src); | |
2197 | |
2198 void movptr(Address dst, Register src); | |
2199 | |
2200 #ifdef _LP64 | |
2201 // Generally the next two are only used for moving NULL | |
2202 // Although there are situations in initializing the mark word where | |
2203 // they could be used. They are dangerous. | |
2204 | |
2205 // They only exist on LP64 so that int32_t and intptr_t are not the same | |
2206 // and we have ambiguous declarations. | |
2207 | |
2208 void movptr(Address dst, int32_t imm32); | |
2209 void movptr(Register dst, int32_t imm32); | |
2210 #endif // _LP64 | |
2211 | |
0 | 2212 // to avoid hiding movl |
2213 void mov32(AddressLiteral dst, Register src); | |
2214 void mov32(Register dst, AddressLiteral src); | |
304 | 2215 |
0 | 2216 // to avoid hiding movb |
2217 void movbyte(ArrayAddress dst, int src); | |
2218 | |
2219 // Can push value or effective address | |
2220 void pushptr(AddressLiteral src); | |
2221 | |
304 | 2222 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); } |
2223 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); } | |
2224 | |
2225 void pushoop(jobject obj); | |
2226 | |
2227 // sign extend as need a l to ptr sized element | |
2228 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); } | |
2229 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); } | |
2230 | |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
775
diff
changeset
|
2231 // IndexOf strings. |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
775
diff
changeset
|
2232 void string_indexof(Register str1, Register str2, |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
775
diff
changeset
|
2233 Register cnt1, Register cnt2, Register result, |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
775
diff
changeset
|
2234 XMMRegister vec, Register tmp); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
775
diff
changeset
|
2235 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
775
diff
changeset
|
2236 // Compare strings. |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
775
diff
changeset
|
2237 void string_compare(Register str1, Register str2, |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
775
diff
changeset
|
2238 Register cnt1, Register cnt2, Register result, |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
775
diff
changeset
|
2239 XMMRegister vec1, XMMRegister vec2); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
775
diff
changeset
|
2240 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
775
diff
changeset
|
2241 // Compare char[] arrays. |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
775
diff
changeset
|
2242 void char_arrays_equals(bool is_array_equ, Register ary1, Register ary2, |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
775
diff
changeset
|
2243 Register limit, Register result, Register chr, |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
775
diff
changeset
|
2244 XMMRegister vec1, XMMRegister vec2); |
304 | 2245 |
1763 | 2246 // Fill primitive arrays |
2247 void generate_fill(BasicType t, bool aligned, | |
2248 Register to, Register value, Register count, | |
2249 Register rtmp, XMMRegister xtmp); | |
2250 | |
0 | 2251 #undef VIRTUAL |
2252 | |
2253 }; | |
2254 | |
2255 /** | |
2256 * class SkipIfEqual: | |
2257 * | |
2258 * Instantiating this class will result in assembly code being output that will | |
2259 * jump around any code emitted between the creation of the instance and it's | |
2260 * automatic destruction at the end of a scope block, depending on the value of | |
2261 * the flag passed to the constructor, which will be checked at run-time. | |
2262 */ | |
2263 class SkipIfEqual { | |
2264 private: | |
2265 MacroAssembler* _masm; | |
2266 Label _label; | |
2267 | |
2268 public: | |
2269 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value); | |
2270 ~SkipIfEqual(); | |
2271 }; | |
2272 | |
2273 #ifdef ASSERT | |
2274 inline bool AbstractAssembler::pd_check_instruction_mark() { return true; } | |
2275 #endif |