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comparison src/cpu/x86/vm/x86_64.ad @ 6614:006050192a5a

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6340864: Implement vectorization optimizations in hotspot-server Summary: Added asm encoding and mach nodes for vector arithmetic instructions on x86. Reviewed-by: roland
author kvn
date Mon, 20 Aug 2012 09:07:21 -0700
parents 8c92982cbbc4
children da91efe96a93
comparison
equal deleted inserted replaced
6594:d5ec46c7da5c 6614:006050192a5a
1511 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); 1511 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1512 __ end_a_stub(); 1512 __ end_a_stub();
1513 return offset; 1513 return offset;
1514 } 1514 }
1515 1515
1516
1517 const bool Matcher::match_rule_supported(int opcode) {
1518 if (!has_match_rule(opcode))
1519 return false;
1520
1521 switch (opcode) {
1522 case Op_PopCountI:
1523 case Op_PopCountL:
1524 if (!UsePopCountInstruction)
1525 return false;
1526 break;
1527 }
1528
1529 return true; // Per default match rules are supported.
1530 }
1531
1532 int Matcher::regnum_to_fpu_offset(int regnum) 1516 int Matcher::regnum_to_fpu_offset(int regnum)
1533 { 1517 {
1534 return regnum - 32; // The FP registers are in the second chunk 1518 return regnum - 32; // The FP registers are in the second chunk
1535 } 1519 }
1536 1520
6425 } 6409 }
6426 %} 6410 %}
6427 ins_pipe(ialu_reg_reg); // XXX 6411 ins_pipe(ialu_reg_reg); // XXX
6428 %} 6412 %}
6429 6413
6414 // Convert oop into int for vectors alignment masking
6415 instruct convP2I(rRegI dst, rRegP src)
6416 %{
6417 match(Set dst (ConvL2I (CastP2X src)));
6418
6419 format %{ "movl $dst, $src\t# ptr -> int" %}
6420 ins_encode %{
6421 __ movl($dst$$Register, $src$$Register);
6422 %}
6423 ins_pipe(ialu_reg_reg); // XXX
6424 %}
6425
6426 // Convert compressed oop into int for vectors alignment masking
6427 // in case of 32bit oops (heap < 4Gb).
6428 instruct convN2I(rRegI dst, rRegN src)
6429 %{
6430 predicate(Universe::narrow_oop_shift() == 0);
6431 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6432
6433 format %{ "movl $dst, $src\t# compressed ptr -> int" %}
6434 ins_encode %{
6435 __ movl($dst$$Register, $src$$Register);
6436 %}
6437 ins_pipe(ialu_reg_reg); // XXX
6438 %}
6430 6439
6431 // Convert oop pointer into compressed form 6440 // Convert oop pointer into compressed form
6432 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{ 6441 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
6433 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); 6442 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6434 match(Set dst (EncodeP src)); 6443 match(Set dst (EncodeP src));
10047 __ movdq($dst$$Register, $src$$XMMRegister); 10056 __ movdq($dst$$Register, $src$$XMMRegister);
10048 %} 10057 %}
10049 ins_pipe( pipe_slow ); 10058 ins_pipe( pipe_slow );
10050 %} 10059 %}
10051 10060
10052 // The next instructions have long latency and use Int unit. Set high cost.
10053 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{ 10061 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
10054 match(Set dst (MoveI2F src)); 10062 match(Set dst (MoveI2F src));
10055 effect(DEF dst, USE src); 10063 effect(DEF dst, USE src);
10056 ins_cost(300); 10064 ins_cost(100);
10057 format %{ "movd $dst,$src\t# MoveI2F" %} 10065 format %{ "movd $dst,$src\t# MoveI2F" %}
10058 ins_encode %{ 10066 ins_encode %{
10059 __ movdl($dst$$XMMRegister, $src$$Register); 10067 __ movdl($dst$$XMMRegister, $src$$Register);
10060 %} 10068 %}
10061 ins_pipe( pipe_slow ); 10069 ins_pipe( pipe_slow );
10062 %} 10070 %}
10063 10071
10064 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{ 10072 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
10065 match(Set dst (MoveL2D src)); 10073 match(Set dst (MoveL2D src));
10066 effect(DEF dst, USE src); 10074 effect(DEF dst, USE src);
10067 ins_cost(300); 10075 ins_cost(100);
10068 format %{ "movd $dst,$src\t# MoveL2D" %} 10076 format %{ "movd $dst,$src\t# MoveL2D" %}
10069 ins_encode %{ 10077 ins_encode %{
10070 __ movdq($dst$$XMMRegister, $src$$Register); 10078 __ movdq($dst$$XMMRegister, $src$$Register);
10071 %} 10079 %}
10072 ins_pipe( pipe_slow ); 10080 ins_pipe( pipe_slow );