annotate src/cpu/x86/vm/x86_64.ad @ 6614:006050192a5a

6340864: Implement vectorization optimizations in hotspot-server Summary: Added asm encoding and mach nodes for vector arithmetic instructions on x86. Reviewed-by: roland
author kvn
date Mon, 20 Aug 2012 09:07:21 -0700
parents 8c92982cbbc4
children da91efe96a93
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1 //
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2 // Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved.
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3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 //
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5 // This code is free software; you can redistribute it and/or modify it
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6 // under the terms of the GNU General Public License version 2 only, as
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7 // published by the Free Software Foundation.
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8 //
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9 // This code is distributed in the hope that it will be useful, but WITHOUT
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10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 // version 2 for more details (a copy is included in the LICENSE file that
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13 // accompanied this code).
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14 //
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15 // You should have received a copy of the GNU General Public License version
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16 // 2 along with this work; if not, write to the Free Software Foundation,
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17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 //
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c18cbe5936b8 6941466: Oracle rebranding changes for Hotspot repositories
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19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
c18cbe5936b8 6941466: Oracle rebranding changes for Hotspot repositories
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20 // or visit www.oracle.com if you need additional information or have any
c18cbe5936b8 6941466: Oracle rebranding changes for Hotspot repositories
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21 // questions.
0
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22 //
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23 //
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24
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25 // AMD64 Architecture Description File
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26
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27 //----------REGISTER DEFINITION BLOCK------------------------------------------
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28 // This information is used by the matcher and the register allocator to
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29 // describe individual registers and classes of registers within the target
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30 // archtecture.
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31
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32 register %{
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33 //----------Architecture Description Register Definitions----------------------
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34 // General Registers
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35 // "reg_def" name ( register save type, C convention save type,
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36 // ideal register type, encoding );
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37 // Register Save Types:
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38 //
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39 // NS = No-Save: The register allocator assumes that these registers
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40 // can be used without saving upon entry to the method, &
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41 // that they do not need to be saved at call sites.
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42 //
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43 // SOC = Save-On-Call: The register allocator assumes that these registers
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44 // can be used without saving upon entry to the method,
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45 // but that they must be saved at call sites.
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46 //
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47 // SOE = Save-On-Entry: The register allocator assumes that these registers
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48 // must be saved before using them upon entry to the
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49 // method, but they do not need to be saved at call
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50 // sites.
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51 //
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52 // AS = Always-Save: The register allocator assumes that these registers
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53 // must be saved before using them upon entry to the
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54 // method, & that they must be saved at call sites.
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55 //
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56 // Ideal Register Type is used to determine how to save & restore a
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57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
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58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
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59 //
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60 // The encoding number is the actual bit-pattern placed into the opcodes.
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61
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62 // General Registers
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63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
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64 // used as byte registers)
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65
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66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
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67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
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68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
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69
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70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
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71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
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72
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73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
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74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
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75
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76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
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77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
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78
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79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
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80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
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81
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82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
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83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
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84
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85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
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86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
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87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
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88
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89 #ifdef _WIN64
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90
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91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
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92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
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93
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94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
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95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
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96
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97 #else
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98
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99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
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100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
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101
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102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
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103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
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104
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105 #endif
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106
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107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
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108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
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109
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110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
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111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
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112
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113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
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114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
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115
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116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
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117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
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118
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119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
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120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
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121
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122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
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123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
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124
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125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
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126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
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127
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128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
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129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
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130
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131
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132 // Floating Point Registers
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133
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134 // Specify priority of register selection within phases of register
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135 // allocation. Highest priority is first. A useful heuristic is to
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136 // give registers a low priority when they are required by machine
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137 // instructions, like EAX and EDX on I486, and choose no-save registers
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138 // before save-on-call, & save-on-call before save-on-entry. Registers
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139 // which participate in fixed calling sequences should come last.
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140 // Registers which are used as pairs must fall on an even boundary.
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141
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142 alloc_class chunk0(R10, R10_H,
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143 R11, R11_H,
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144 R8, R8_H,
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145 R9, R9_H,
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146 R12, R12_H,
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147 RCX, RCX_H,
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148 RBX, RBX_H,
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149 RDI, RDI_H,
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150 RDX, RDX_H,
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151 RSI, RSI_H,
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152 RAX, RAX_H,
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153 RBP, RBP_H,
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154 R13, R13_H,
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155 R14, R14_H,
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156 R15, R15_H,
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157 RSP, RSP_H);
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158
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159
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160 //----------Architecture Description Register Classes--------------------------
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161 // Several register classes are automatically defined based upon information in
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162 // this architecture description.
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163 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
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164 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
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165 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
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166 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
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167 //
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168
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169 // Class for all pointer registers (including RSP)
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170 reg_class any_reg(RAX, RAX_H,
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171 RDX, RDX_H,
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172 RBP, RBP_H,
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173 RDI, RDI_H,
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174 RSI, RSI_H,
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175 RCX, RCX_H,
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176 RBX, RBX_H,
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177 RSP, RSP_H,
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178 R8, R8_H,
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179 R9, R9_H,
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180 R10, R10_H,
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181 R11, R11_H,
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182 R12, R12_H,
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183 R13, R13_H,
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184 R14, R14_H,
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185 R15, R15_H);
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186
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187 // Class for all pointer registers except RSP
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188 reg_class ptr_reg(RAX, RAX_H,
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189 RDX, RDX_H,
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190 RBP, RBP_H,
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191 RDI, RDI_H,
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192 RSI, RSI_H,
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193 RCX, RCX_H,
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194 RBX, RBX_H,
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195 R8, R8_H,
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196 R9, R9_H,
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197 R10, R10_H,
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198 R11, R11_H,
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199 R13, R13_H,
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200 R14, R14_H);
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201
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202 // Class for all pointer registers except RAX and RSP
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203 reg_class ptr_no_rax_reg(RDX, RDX_H,
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204 RBP, RBP_H,
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205 RDI, RDI_H,
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206 RSI, RSI_H,
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207 RCX, RCX_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
208 RBX, RBX_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
209 R8, R8_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
210 R9, R9_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
211 R10, R10_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
212 R11, R11_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
213 R13, R13_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
214 R14, R14_H);
a61af66fc99e Initial load
duke
parents:
diff changeset
215
a61af66fc99e Initial load
duke
parents:
diff changeset
216 reg_class ptr_no_rbp_reg(RDX, RDX_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
217 RAX, RAX_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
218 RDI, RDI_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
219 RSI, RSI_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
220 RCX, RCX_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
221 RBX, RBX_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
222 R8, R8_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
223 R9, R9_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
224 R10, R10_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
225 R11, R11_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
226 R13, R13_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
227 R14, R14_H);
a61af66fc99e Initial load
duke
parents:
diff changeset
228
a61af66fc99e Initial load
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parents:
diff changeset
229 // Class for all pointer registers except RAX, RBX and RSP
a61af66fc99e Initial load
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parents:
diff changeset
230 reg_class ptr_no_rax_rbx_reg(RDX, RDX_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
231 RBP, RBP_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
232 RDI, RDI_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
233 RSI, RSI_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
234 RCX, RCX_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
235 R8, R8_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
236 R9, R9_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
237 R10, R10_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
238 R11, R11_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
239 R13, R13_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
240 R14, R14_H);
a61af66fc99e Initial load
duke
parents:
diff changeset
241
a61af66fc99e Initial load
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parents:
diff changeset
242 // Singleton class for RAX pointer register
a61af66fc99e Initial load
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parents:
diff changeset
243 reg_class ptr_rax_reg(RAX, RAX_H);
a61af66fc99e Initial load
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parents:
diff changeset
244
a61af66fc99e Initial load
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parents:
diff changeset
245 // Singleton class for RBX pointer register
a61af66fc99e Initial load
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parents:
diff changeset
246 reg_class ptr_rbx_reg(RBX, RBX_H);
a61af66fc99e Initial load
duke
parents:
diff changeset
247
a61af66fc99e Initial load
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parents:
diff changeset
248 // Singleton class for RSI pointer register
a61af66fc99e Initial load
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parents:
diff changeset
249 reg_class ptr_rsi_reg(RSI, RSI_H);
a61af66fc99e Initial load
duke
parents:
diff changeset
250
a61af66fc99e Initial load
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parents:
diff changeset
251 // Singleton class for RDI pointer register
a61af66fc99e Initial load
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parents:
diff changeset
252 reg_class ptr_rdi_reg(RDI, RDI_H);
a61af66fc99e Initial load
duke
parents:
diff changeset
253
a61af66fc99e Initial load
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parents:
diff changeset
254 // Singleton class for RBP pointer register
a61af66fc99e Initial load
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parents:
diff changeset
255 reg_class ptr_rbp_reg(RBP, RBP_H);
a61af66fc99e Initial load
duke
parents:
diff changeset
256
a61af66fc99e Initial load
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parents:
diff changeset
257 // Singleton class for stack pointer
a61af66fc99e Initial load
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parents:
diff changeset
258 reg_class ptr_rsp_reg(RSP, RSP_H);
a61af66fc99e Initial load
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parents:
diff changeset
259
a61af66fc99e Initial load
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parents:
diff changeset
260 // Singleton class for TLS pointer
a61af66fc99e Initial load
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parents:
diff changeset
261 reg_class ptr_r15_reg(R15, R15_H);
a61af66fc99e Initial load
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parents:
diff changeset
262
a61af66fc99e Initial load
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parents:
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263 // Class for all long registers (except RSP)
a61af66fc99e Initial load
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parents:
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264 reg_class long_reg(RAX, RAX_H,
a61af66fc99e Initial load
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parents:
diff changeset
265 RDX, RDX_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
266 RBP, RBP_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
267 RDI, RDI_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
268 RSI, RSI_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
269 RCX, RCX_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
270 RBX, RBX_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
271 R8, R8_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
272 R9, R9_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
273 R10, R10_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
274 R11, R11_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
275 R13, R13_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
276 R14, R14_H);
a61af66fc99e Initial load
duke
parents:
diff changeset
277
a61af66fc99e Initial load
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parents:
diff changeset
278 // Class for all long registers except RAX, RDX (and RSP)
a61af66fc99e Initial load
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parents:
diff changeset
279 reg_class long_no_rax_rdx_reg(RBP, RBP_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
280 RDI, RDI_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
281 RSI, RSI_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
282 RCX, RCX_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
283 RBX, RBX_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
284 R8, R8_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
285 R9, R9_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
286 R10, R10_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
287 R11, R11_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
288 R13, R13_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
289 R14, R14_H);
a61af66fc99e Initial load
duke
parents:
diff changeset
290
a61af66fc99e Initial load
duke
parents:
diff changeset
291 // Class for all long registers except RCX (and RSP)
a61af66fc99e Initial load
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parents:
diff changeset
292 reg_class long_no_rcx_reg(RBP, RBP_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
293 RDI, RDI_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
294 RSI, RSI_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
295 RAX, RAX_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
296 RDX, RDX_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
297 RBX, RBX_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
298 R8, R8_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
299 R9, R9_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
300 R10, R10_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
301 R11, R11_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
302 R13, R13_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
303 R14, R14_H);
a61af66fc99e Initial load
duke
parents:
diff changeset
304
a61af66fc99e Initial load
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parents:
diff changeset
305 // Class for all long registers except RAX (and RSP)
a61af66fc99e Initial load
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parents:
diff changeset
306 reg_class long_no_rax_reg(RBP, RBP_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
307 RDX, RDX_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
308 RDI, RDI_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
309 RSI, RSI_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
310 RCX, RCX_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
311 RBX, RBX_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
312 R8, R8_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
313 R9, R9_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
314 R10, R10_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
315 R11, R11_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
316 R13, R13_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
317 R14, R14_H);
a61af66fc99e Initial load
duke
parents:
diff changeset
318
a61af66fc99e Initial load
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parents:
diff changeset
319 // Singleton class for RAX long register
a61af66fc99e Initial load
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parents:
diff changeset
320 reg_class long_rax_reg(RAX, RAX_H);
a61af66fc99e Initial load
duke
parents:
diff changeset
321
a61af66fc99e Initial load
duke
parents:
diff changeset
322 // Singleton class for RCX long register
a61af66fc99e Initial load
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parents:
diff changeset
323 reg_class long_rcx_reg(RCX, RCX_H);
a61af66fc99e Initial load
duke
parents:
diff changeset
324
a61af66fc99e Initial load
duke
parents:
diff changeset
325 // Singleton class for RDX long register
a61af66fc99e Initial load
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parents:
diff changeset
326 reg_class long_rdx_reg(RDX, RDX_H);
a61af66fc99e Initial load
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parents:
diff changeset
327
a61af66fc99e Initial load
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parents:
diff changeset
328 // Class for all int registers (except RSP)
a61af66fc99e Initial load
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parents:
diff changeset
329 reg_class int_reg(RAX,
a61af66fc99e Initial load
duke
parents:
diff changeset
330 RDX,
a61af66fc99e Initial load
duke
parents:
diff changeset
331 RBP,
a61af66fc99e Initial load
duke
parents:
diff changeset
332 RDI,
a61af66fc99e Initial load
duke
parents:
diff changeset
333 RSI,
a61af66fc99e Initial load
duke
parents:
diff changeset
334 RCX,
a61af66fc99e Initial load
duke
parents:
diff changeset
335 RBX,
a61af66fc99e Initial load
duke
parents:
diff changeset
336 R8,
a61af66fc99e Initial load
duke
parents:
diff changeset
337 R9,
a61af66fc99e Initial load
duke
parents:
diff changeset
338 R10,
a61af66fc99e Initial load
duke
parents:
diff changeset
339 R11,
a61af66fc99e Initial load
duke
parents:
diff changeset
340 R13,
a61af66fc99e Initial load
duke
parents:
diff changeset
341 R14);
a61af66fc99e Initial load
duke
parents:
diff changeset
342
a61af66fc99e Initial load
duke
parents:
diff changeset
343 // Class for all int registers except RCX (and RSP)
a61af66fc99e Initial load
duke
parents:
diff changeset
344 reg_class int_no_rcx_reg(RAX,
a61af66fc99e Initial load
duke
parents:
diff changeset
345 RDX,
a61af66fc99e Initial load
duke
parents:
diff changeset
346 RBP,
a61af66fc99e Initial load
duke
parents:
diff changeset
347 RDI,
a61af66fc99e Initial load
duke
parents:
diff changeset
348 RSI,
a61af66fc99e Initial load
duke
parents:
diff changeset
349 RBX,
a61af66fc99e Initial load
duke
parents:
diff changeset
350 R8,
a61af66fc99e Initial load
duke
parents:
diff changeset
351 R9,
a61af66fc99e Initial load
duke
parents:
diff changeset
352 R10,
a61af66fc99e Initial load
duke
parents:
diff changeset
353 R11,
a61af66fc99e Initial load
duke
parents:
diff changeset
354 R13,
a61af66fc99e Initial load
duke
parents:
diff changeset
355 R14);
a61af66fc99e Initial load
duke
parents:
diff changeset
356
a61af66fc99e Initial load
duke
parents:
diff changeset
357 // Class for all int registers except RAX, RDX (and RSP)
a61af66fc99e Initial load
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parents:
diff changeset
358 reg_class int_no_rax_rdx_reg(RBP,
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
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parents: 235
diff changeset
359 RDI,
0
a61af66fc99e Initial load
duke
parents:
diff changeset
360 RSI,
a61af66fc99e Initial load
duke
parents:
diff changeset
361 RCX,
a61af66fc99e Initial load
duke
parents:
diff changeset
362 RBX,
a61af66fc99e Initial load
duke
parents:
diff changeset
363 R8,
a61af66fc99e Initial load
duke
parents:
diff changeset
364 R9,
a61af66fc99e Initial load
duke
parents:
diff changeset
365 R10,
a61af66fc99e Initial load
duke
parents:
diff changeset
366 R11,
a61af66fc99e Initial load
duke
parents:
diff changeset
367 R13,
a61af66fc99e Initial load
duke
parents:
diff changeset
368 R14);
a61af66fc99e Initial load
duke
parents:
diff changeset
369
a61af66fc99e Initial load
duke
parents:
diff changeset
370 // Singleton class for RAX int register
a61af66fc99e Initial load
duke
parents:
diff changeset
371 reg_class int_rax_reg(RAX);
a61af66fc99e Initial load
duke
parents:
diff changeset
372
a61af66fc99e Initial load
duke
parents:
diff changeset
373 // Singleton class for RBX int register
a61af66fc99e Initial load
duke
parents:
diff changeset
374 reg_class int_rbx_reg(RBX);
a61af66fc99e Initial load
duke
parents:
diff changeset
375
a61af66fc99e Initial load
duke
parents:
diff changeset
376 // Singleton class for RCX int register
a61af66fc99e Initial load
duke
parents:
diff changeset
377 reg_class int_rcx_reg(RCX);
a61af66fc99e Initial load
duke
parents:
diff changeset
378
a61af66fc99e Initial load
duke
parents:
diff changeset
379 // Singleton class for RCX int register
a61af66fc99e Initial load
duke
parents:
diff changeset
380 reg_class int_rdx_reg(RDX);
a61af66fc99e Initial load
duke
parents:
diff changeset
381
a61af66fc99e Initial load
duke
parents:
diff changeset
382 // Singleton class for RCX int register
a61af66fc99e Initial load
duke
parents:
diff changeset
383 reg_class int_rdi_reg(RDI);
a61af66fc99e Initial load
duke
parents:
diff changeset
384
a61af66fc99e Initial load
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parents:
diff changeset
385 // Singleton class for instruction pointer
a61af66fc99e Initial load
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parents:
diff changeset
386 // reg_class ip_reg(RIP);
a61af66fc99e Initial load
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parents:
diff changeset
387
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
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parents: 6143
diff changeset
388 %}
0
a61af66fc99e Initial load
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parents:
diff changeset
389
a61af66fc99e Initial load
duke
parents:
diff changeset
390 //----------SOURCE BLOCK-------------------------------------------------------
a61af66fc99e Initial load
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parents:
diff changeset
391 // This is a block of C++ code which provides values, functions, and
a61af66fc99e Initial load
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parents:
diff changeset
392 // definitions necessary in the rest of the architecture description
a61af66fc99e Initial load
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parents:
diff changeset
393 source %{
304
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parents: 235
diff changeset
394 #define RELOC_IMM64 Assembler::imm_operand
0
a61af66fc99e Initial load
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parents:
diff changeset
395 #define RELOC_DISP32 Assembler::disp32_operand
a61af66fc99e Initial load
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parents:
diff changeset
396
a61af66fc99e Initial load
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parents:
diff changeset
397 #define __ _masm.
a61af66fc99e Initial load
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parents:
diff changeset
398
1137
97125851f396 6829187: compiler optimizations required for JSR 292
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parents: 989
diff changeset
399 static int preserve_SP_size() {
4759
127b3692c168 7116452: Add support for AVX instructions
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parents: 4121
diff changeset
400 return 3; // rex.w, op, rm(reg/reg)
1137
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
401 }
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
402
0
a61af66fc99e Initial load
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parents:
diff changeset
403 // !!!!! Special hack to get all types of calls to specify the byte offset
a61af66fc99e Initial load
duke
parents:
diff changeset
404 // from the start of the call to the point where the return address
a61af66fc99e Initial load
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parents:
diff changeset
405 // will point.
a61af66fc99e Initial load
duke
parents:
diff changeset
406 int MachCallStaticJavaNode::ret_addr_offset()
a61af66fc99e Initial load
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parents:
diff changeset
407 {
1137
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
408 int offset = 5; // 5 bytes from start of call to where return address points
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
409 if (_method_handle_invoke)
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
410 offset += preserve_SP_size();
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
411 return offset;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
412 }
a61af66fc99e Initial load
duke
parents:
diff changeset
413
a61af66fc99e Initial load
duke
parents:
diff changeset
414 int MachCallDynamicJavaNode::ret_addr_offset()
a61af66fc99e Initial load
duke
parents:
diff changeset
415 {
a61af66fc99e Initial load
duke
parents:
diff changeset
416 return 15; // 15 bytes from start of call to where return address points
a61af66fc99e Initial load
duke
parents:
diff changeset
417 }
a61af66fc99e Initial load
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parents:
diff changeset
418
a61af66fc99e Initial load
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parents:
diff changeset
419 // In os_cpu .ad file
a61af66fc99e Initial load
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parents:
diff changeset
420 // int MachCallRuntimeNode::ret_addr_offset()
a61af66fc99e Initial load
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parents:
diff changeset
421
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
422 // Indicate if the safepoint node needs the polling page as an input,
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
423 // it does if the polling page is more than disp32 away.
0
a61af66fc99e Initial load
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parents:
diff changeset
424 bool SafePointNode::needs_polling_address_input()
a61af66fc99e Initial load
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parents:
diff changeset
425 {
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
426 return Assembler::is_polling_page_far();
0
a61af66fc99e Initial load
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parents:
diff changeset
427 }
a61af66fc99e Initial load
duke
parents:
diff changeset
428
a61af66fc99e Initial load
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parents:
diff changeset
429 //
a61af66fc99e Initial load
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parents:
diff changeset
430 // Compute padding required for nodes which need alignment
a61af66fc99e Initial load
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parents:
diff changeset
431 //
a61af66fc99e Initial load
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parents:
diff changeset
432
a61af66fc99e Initial load
duke
parents:
diff changeset
433 // The address of the call instruction needs to be 4-byte aligned to
a61af66fc99e Initial load
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parents:
diff changeset
434 // ensure that it does not span a cache line so that it can be patched.
a61af66fc99e Initial load
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parents:
diff changeset
435 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
a61af66fc99e Initial load
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parents:
diff changeset
436 {
a61af66fc99e Initial load
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parents:
diff changeset
437 current_offset += 1; // skip call opcode byte
a61af66fc99e Initial load
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parents:
diff changeset
438 return round_to(current_offset, alignment_required()) - current_offset;
a61af66fc99e Initial load
duke
parents:
diff changeset
439 }
a61af66fc99e Initial load
duke
parents:
diff changeset
440
a61af66fc99e Initial load
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parents:
diff changeset
441 // The address of the call instruction needs to be 4-byte aligned to
a61af66fc99e Initial load
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parents:
diff changeset
442 // ensure that it does not span a cache line so that it can be patched.
1137
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
443 int CallStaticJavaHandleNode::compute_padding(int current_offset) const
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
444 {
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
445 current_offset += preserve_SP_size(); // skip mov rbp, rsp
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
446 current_offset += 1; // skip call opcode byte
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
447 return round_to(current_offset, alignment_required()) - current_offset;
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
448 }
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
449
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
450 // The address of the call instruction needs to be 4-byte aligned to
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
451 // ensure that it does not span a cache line so that it can be patched.
0
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parents:
diff changeset
452 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
a61af66fc99e Initial load
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parents:
diff changeset
453 {
a61af66fc99e Initial load
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parents:
diff changeset
454 current_offset += 11; // skip movq instruction + call opcode byte
a61af66fc99e Initial load
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parents:
diff changeset
455 return round_to(current_offset, alignment_required()) - current_offset;
a61af66fc99e Initial load
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parents:
diff changeset
456 }
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parents:
diff changeset
457
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parents:
diff changeset
458 // EMIT_RM()
1748
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parents: 1730
diff changeset
459 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
0
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parents:
diff changeset
460 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
1748
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twisti
parents: 1730
diff changeset
461 cbuf.insts()->emit_int8(c);
0
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parents:
diff changeset
462 }
a61af66fc99e Initial load
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parents:
diff changeset
463
a61af66fc99e Initial load
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parents:
diff changeset
464 // EMIT_CC()
1748
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parents: 1730
diff changeset
465 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
0
a61af66fc99e Initial load
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parents:
diff changeset
466 unsigned char c = (unsigned char) (f1 | f2);
1748
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twisti
parents: 1730
diff changeset
467 cbuf.insts()->emit_int8(c);
0
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parents:
diff changeset
468 }
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parents:
diff changeset
469
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parents:
diff changeset
470 // EMIT_OPCODE()
1748
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parents: 1730
diff changeset
471 void emit_opcode(CodeBuffer &cbuf, int code) {
3e8fbc61cee8 6978355: renaming for 6961697
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parents: 1730
diff changeset
472 cbuf.insts()->emit_int8((unsigned char) code);
0
a61af66fc99e Initial load
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parents:
diff changeset
473 }
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duke
parents:
diff changeset
474
a61af66fc99e Initial load
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parents:
diff changeset
475 // EMIT_OPCODE() w/ relocation information
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duke
parents:
diff changeset
476 void emit_opcode(CodeBuffer &cbuf,
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parents:
diff changeset
477 int code, relocInfo::relocType reloc, int offset, int format)
a61af66fc99e Initial load
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parents:
diff changeset
478 {
1748
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parents: 1730
diff changeset
479 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
0
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duke
parents:
diff changeset
480 emit_opcode(cbuf, code);
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parents:
diff changeset
481 }
a61af66fc99e Initial load
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parents:
diff changeset
482
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parents:
diff changeset
483 // EMIT_D8()
1748
3e8fbc61cee8 6978355: renaming for 6961697
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parents: 1730
diff changeset
484 void emit_d8(CodeBuffer &cbuf, int d8) {
3e8fbc61cee8 6978355: renaming for 6961697
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parents: 1730
diff changeset
485 cbuf.insts()->emit_int8((unsigned char) d8);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
486 }
a61af66fc99e Initial load
duke
parents:
diff changeset
487
a61af66fc99e Initial load
duke
parents:
diff changeset
488 // EMIT_D16()
1748
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twisti
parents: 1730
diff changeset
489 void emit_d16(CodeBuffer &cbuf, int d16) {
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
490 cbuf.insts()->emit_int16(d16);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
491 }
a61af66fc99e Initial load
duke
parents:
diff changeset
492
a61af66fc99e Initial load
duke
parents:
diff changeset
493 // EMIT_D32()
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
494 void emit_d32(CodeBuffer &cbuf, int d32) {
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
495 cbuf.insts()->emit_int32(d32);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
496 }
a61af66fc99e Initial load
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parents:
diff changeset
497
a61af66fc99e Initial load
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parents:
diff changeset
498 // EMIT_D64()
1748
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twisti
parents: 1730
diff changeset
499 void emit_d64(CodeBuffer &cbuf, int64_t d64) {
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twisti
parents: 1730
diff changeset
500 cbuf.insts()->emit_int64(d64);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
501 }
a61af66fc99e Initial load
duke
parents:
diff changeset
502
a61af66fc99e Initial load
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parents:
diff changeset
503 // emit 32 bit value and construct relocation entry from relocInfo::relocType
a61af66fc99e Initial load
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parents:
diff changeset
504 void emit_d32_reloc(CodeBuffer& cbuf,
a61af66fc99e Initial load
duke
parents:
diff changeset
505 int d32,
a61af66fc99e Initial load
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parents:
diff changeset
506 relocInfo::relocType reloc,
a61af66fc99e Initial load
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parents:
diff changeset
507 int format)
a61af66fc99e Initial load
duke
parents:
diff changeset
508 {
a61af66fc99e Initial load
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parents:
diff changeset
509 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
510 cbuf.relocate(cbuf.insts_mark(), reloc, format);
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
511 cbuf.insts()->emit_int32(d32);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
512 }
a61af66fc99e Initial load
duke
parents:
diff changeset
513
a61af66fc99e Initial load
duke
parents:
diff changeset
514 // emit 32 bit value and construct relocation entry from RelocationHolder
1748
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twisti
parents: 1730
diff changeset
515 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
516 #ifdef ASSERT
a61af66fc99e Initial load
duke
parents:
diff changeset
517 if (rspec.reloc()->type() == relocInfo::oop_type &&
a61af66fc99e Initial load
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parents:
diff changeset
518 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
989
148e5441d916 6863023: need non-perm oops in code cache for JSR 292
jrose
parents: 986
diff changeset
519 assert(oop((intptr_t)d32)->is_oop() && (ScavengeRootsInCode || !oop((intptr_t)d32)->is_scavengable()), "cannot embed scavengable oops in code");
0
a61af66fc99e Initial load
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parents:
diff changeset
520 }
a61af66fc99e Initial load
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parents:
diff changeset
521 #endif
1748
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twisti
parents: 1730
diff changeset
522 cbuf.relocate(cbuf.insts_mark(), rspec, format);
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
523 cbuf.insts()->emit_int32(d32);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
524 }
a61af66fc99e Initial load
duke
parents:
diff changeset
525
a61af66fc99e Initial load
duke
parents:
diff changeset
526 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
527 address next_ip = cbuf.insts_end() + 4;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
528 emit_d32_reloc(cbuf, (int) (addr - next_ip),
a61af66fc99e Initial load
duke
parents:
diff changeset
529 external_word_Relocation::spec(addr),
a61af66fc99e Initial load
duke
parents:
diff changeset
530 RELOC_DISP32);
a61af66fc99e Initial load
duke
parents:
diff changeset
531 }
a61af66fc99e Initial load
duke
parents:
diff changeset
532
a61af66fc99e Initial load
duke
parents:
diff changeset
533
a61af66fc99e Initial load
duke
parents:
diff changeset
534 // emit 64 bit value and construct relocation entry from relocInfo::relocType
1748
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twisti
parents: 1730
diff changeset
535 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
536 cbuf.relocate(cbuf.insts_mark(), reloc, format);
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
537 cbuf.insts()->emit_int64(d64);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
538 }
a61af66fc99e Initial load
duke
parents:
diff changeset
539
a61af66fc99e Initial load
duke
parents:
diff changeset
540 // emit 64 bit value and construct relocation entry from RelocationHolder
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
541 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
542 #ifdef ASSERT
a61af66fc99e Initial load
duke
parents:
diff changeset
543 if (rspec.reloc()->type() == relocInfo::oop_type &&
a61af66fc99e Initial load
duke
parents:
diff changeset
544 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
989
148e5441d916 6863023: need non-perm oops in code cache for JSR 292
jrose
parents: 986
diff changeset
545 assert(oop(d64)->is_oop() && (ScavengeRootsInCode || !oop(d64)->is_scavengable()),
148e5441d916 6863023: need non-perm oops in code cache for JSR 292
jrose
parents: 986
diff changeset
546 "cannot embed scavengable oops in code");
0
a61af66fc99e Initial load
duke
parents:
diff changeset
547 }
a61af66fc99e Initial load
duke
parents:
diff changeset
548 #endif
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
549 cbuf.relocate(cbuf.insts_mark(), rspec, format);
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
550 cbuf.insts()->emit_int64(d64);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
551 }
a61af66fc99e Initial load
duke
parents:
diff changeset
552
a61af66fc99e Initial load
duke
parents:
diff changeset
553 // Access stack slot for load or store
a61af66fc99e Initial load
duke
parents:
diff changeset
554 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
a61af66fc99e Initial load
duke
parents:
diff changeset
555 {
a61af66fc99e Initial load
duke
parents:
diff changeset
556 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
a61af66fc99e Initial load
duke
parents:
diff changeset
557 if (-0x80 <= disp && disp < 0x80) {
a61af66fc99e Initial load
duke
parents:
diff changeset
558 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
a61af66fc99e Initial load
duke
parents:
diff changeset
559 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
a61af66fc99e Initial load
duke
parents:
diff changeset
560 emit_d8(cbuf, disp); // Displacement // R/M byte
a61af66fc99e Initial load
duke
parents:
diff changeset
561 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
562 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
a61af66fc99e Initial load
duke
parents:
diff changeset
563 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
a61af66fc99e Initial load
duke
parents:
diff changeset
564 emit_d32(cbuf, disp); // Displacement // R/M byte
a61af66fc99e Initial load
duke
parents:
diff changeset
565 }
a61af66fc99e Initial load
duke
parents:
diff changeset
566 }
a61af66fc99e Initial load
duke
parents:
diff changeset
567
a61af66fc99e Initial load
duke
parents:
diff changeset
568 // rRegI ereg, memory mem) %{ // emit_reg_mem
a61af66fc99e Initial load
duke
parents:
diff changeset
569 void encode_RegMem(CodeBuffer &cbuf,
a61af66fc99e Initial load
duke
parents:
diff changeset
570 int reg,
a61af66fc99e Initial load
duke
parents:
diff changeset
571 int base, int index, int scale, int disp, bool disp_is_oop)
a61af66fc99e Initial load
duke
parents:
diff changeset
572 {
a61af66fc99e Initial load
duke
parents:
diff changeset
573 assert(!disp_is_oop, "cannot have disp");
a61af66fc99e Initial load
duke
parents:
diff changeset
574 int regenc = reg & 7;
a61af66fc99e Initial load
duke
parents:
diff changeset
575 int baseenc = base & 7;
a61af66fc99e Initial load
duke
parents:
diff changeset
576 int indexenc = index & 7;
a61af66fc99e Initial load
duke
parents:
diff changeset
577
a61af66fc99e Initial load
duke
parents:
diff changeset
578 // There is no index & no scale, use form without SIB byte
a61af66fc99e Initial load
duke
parents:
diff changeset
579 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
a61af66fc99e Initial load
duke
parents:
diff changeset
580 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
a61af66fc99e Initial load
duke
parents:
diff changeset
581 if (disp == 0 && base != RBP_enc && base != R13_enc) {
a61af66fc99e Initial load
duke
parents:
diff changeset
582 emit_rm(cbuf, 0x0, regenc, baseenc); // *
a61af66fc99e Initial load
duke
parents:
diff changeset
583 } else if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) {
a61af66fc99e Initial load
duke
parents:
diff changeset
584 // If 8-bit displacement, mode 0x1
a61af66fc99e Initial load
duke
parents:
diff changeset
585 emit_rm(cbuf, 0x1, regenc, baseenc); // *
a61af66fc99e Initial load
duke
parents:
diff changeset
586 emit_d8(cbuf, disp);
a61af66fc99e Initial load
duke
parents:
diff changeset
587 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
588 // If 32-bit displacement
a61af66fc99e Initial load
duke
parents:
diff changeset
589 if (base == -1) { // Special flag for absolute address
a61af66fc99e Initial load
duke
parents:
diff changeset
590 emit_rm(cbuf, 0x0, regenc, 0x5); // *
a61af66fc99e Initial load
duke
parents:
diff changeset
591 if (disp_is_oop) {
a61af66fc99e Initial load
duke
parents:
diff changeset
592 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
a61af66fc99e Initial load
duke
parents:
diff changeset
593 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
594 emit_d32(cbuf, disp);
a61af66fc99e Initial load
duke
parents:
diff changeset
595 }
a61af66fc99e Initial load
duke
parents:
diff changeset
596 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
597 // Normal base + offset
a61af66fc99e Initial load
duke
parents:
diff changeset
598 emit_rm(cbuf, 0x2, regenc, baseenc); // *
a61af66fc99e Initial load
duke
parents:
diff changeset
599 if (disp_is_oop) {
a61af66fc99e Initial load
duke
parents:
diff changeset
600 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
a61af66fc99e Initial load
duke
parents:
diff changeset
601 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
602 emit_d32(cbuf, disp);
a61af66fc99e Initial load
duke
parents:
diff changeset
603 }
a61af66fc99e Initial load
duke
parents:
diff changeset
604 }
a61af66fc99e Initial load
duke
parents:
diff changeset
605 }
a61af66fc99e Initial load
duke
parents:
diff changeset
606 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
607 // Else, encode with the SIB byte
a61af66fc99e Initial load
duke
parents:
diff changeset
608 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
a61af66fc99e Initial load
duke
parents:
diff changeset
609 if (disp == 0 && base != RBP_enc && base != R13_enc) {
a61af66fc99e Initial load
duke
parents:
diff changeset
610 // If no displacement
a61af66fc99e Initial load
duke
parents:
diff changeset
611 emit_rm(cbuf, 0x0, regenc, 0x4); // *
a61af66fc99e Initial load
duke
parents:
diff changeset
612 emit_rm(cbuf, scale, indexenc, baseenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
613 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
614 if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) {
a61af66fc99e Initial load
duke
parents:
diff changeset
615 // If 8-bit displacement, mode 0x1
a61af66fc99e Initial load
duke
parents:
diff changeset
616 emit_rm(cbuf, 0x1, regenc, 0x4); // *
a61af66fc99e Initial load
duke
parents:
diff changeset
617 emit_rm(cbuf, scale, indexenc, baseenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
618 emit_d8(cbuf, disp);
a61af66fc99e Initial load
duke
parents:
diff changeset
619 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
620 // If 32-bit displacement
a61af66fc99e Initial load
duke
parents:
diff changeset
621 if (base == 0x04 ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
622 emit_rm(cbuf, 0x2, regenc, 0x4);
a61af66fc99e Initial load
duke
parents:
diff changeset
623 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
a61af66fc99e Initial load
duke
parents:
diff changeset
624 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
625 emit_rm(cbuf, 0x2, regenc, 0x4);
a61af66fc99e Initial load
duke
parents:
diff changeset
626 emit_rm(cbuf, scale, indexenc, baseenc); // *
a61af66fc99e Initial load
duke
parents:
diff changeset
627 }
a61af66fc99e Initial load
duke
parents:
diff changeset
628 if (disp_is_oop) {
a61af66fc99e Initial load
duke
parents:
diff changeset
629 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
a61af66fc99e Initial load
duke
parents:
diff changeset
630 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
631 emit_d32(cbuf, disp);
a61af66fc99e Initial load
duke
parents:
diff changeset
632 }
a61af66fc99e Initial load
duke
parents:
diff changeset
633 }
a61af66fc99e Initial load
duke
parents:
diff changeset
634 }
a61af66fc99e Initial load
duke
parents:
diff changeset
635 }
a61af66fc99e Initial load
duke
parents:
diff changeset
636 }
a61af66fc99e Initial load
duke
parents:
diff changeset
637
3783
de6a837d75cf 7056380: VM crashes with SIGSEGV in compiled code
never
parents: 3738
diff changeset
638 // This could be in MacroAssembler but it's fairly C2 specific
de6a837d75cf 7056380: VM crashes with SIGSEGV in compiled code
never
parents: 3738
diff changeset
639 void emit_cmpfp_fixup(MacroAssembler& _masm) {
de6a837d75cf 7056380: VM crashes with SIGSEGV in compiled code
never
parents: 3738
diff changeset
640 Label exit;
de6a837d75cf 7056380: VM crashes with SIGSEGV in compiled code
never
parents: 3738
diff changeset
641 __ jccb(Assembler::noParity, exit);
de6a837d75cf 7056380: VM crashes with SIGSEGV in compiled code
never
parents: 3738
diff changeset
642 __ pushf();
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
643 //
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
644 // comiss/ucomiss instructions set ZF,PF,CF flags and
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
645 // zero OF,AF,SF for NaN values.
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
646 // Fixup flags by zeroing ZF,PF so that compare of NaN
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
647 // values returns 'less than' result (CF is set).
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
648 // Leave the rest of flags unchanged.
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
649 //
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
650 // 7 6 5 4 3 2 1 0
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
651 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
652 // 0 0 1 0 1 0 1 1 (0x2B)
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
653 //
3783
de6a837d75cf 7056380: VM crashes with SIGSEGV in compiled code
never
parents: 3738
diff changeset
654 __ andq(Address(rsp, 0), 0xffffff2b);
de6a837d75cf 7056380: VM crashes with SIGSEGV in compiled code
never
parents: 3738
diff changeset
655 __ popf();
de6a837d75cf 7056380: VM crashes with SIGSEGV in compiled code
never
parents: 3738
diff changeset
656 __ bind(exit);
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
657 }
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
658
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
659 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
660 Label done;
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
661 __ movl(dst, -1);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
662 __ jcc(Assembler::parity, done);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
663 __ jcc(Assembler::below, done);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
664 __ setb(Assembler::notEqual, dst);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
665 __ movzbl(dst, dst);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
666 __ bind(done);
3783
de6a837d75cf 7056380: VM crashes with SIGSEGV in compiled code
never
parents: 3738
diff changeset
667 }
de6a837d75cf 7056380: VM crashes with SIGSEGV in compiled code
never
parents: 3738
diff changeset
668
0
a61af66fc99e Initial load
duke
parents:
diff changeset
669
a61af66fc99e Initial load
duke
parents:
diff changeset
670 //=============================================================================
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
671 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
672
4114
6729bbc1fcd6 7003454: order constants in constant table by number of references in code
twisti
parents: 4047
diff changeset
673 int Compile::ConstantTable::calculate_table_base_offset() const {
6729bbc1fcd6 7003454: order constants in constant table by number of references in code
twisti
parents: 4047
diff changeset
674 return 0; // absolute addressing, no offset
6729bbc1fcd6 7003454: order constants in constant table by number of references in code
twisti
parents: 4047
diff changeset
675 }
6729bbc1fcd6 7003454: order constants in constant table by number of references in code
twisti
parents: 4047
diff changeset
676
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
677 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
678 // Empty encoding
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
679 }
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
680
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
681 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
682 return 0;
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
683 }
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
684
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
685 #ifndef PRODUCT
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
686 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
687 st->print("# MachConstantBaseNode (empty encoding)");
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
688 }
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
689 #endif
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
690
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
691
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
692 //=============================================================================
0
a61af66fc99e Initial load
duke
parents:
diff changeset
693 #ifndef PRODUCT
4947
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
694 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
695 Compile* C = ra_->C;
a61af66fc99e Initial load
duke
parents:
diff changeset
696
a61af66fc99e Initial load
duke
parents:
diff changeset
697 int framesize = C->frame_slots() << LogBytesPerInt;
a61af66fc99e Initial load
duke
parents:
diff changeset
698 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
4947
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
699 // Remove wordSize for return addr which is already pushed.
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
700 framesize -= wordSize;
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
701
0
a61af66fc99e Initial load
duke
parents:
diff changeset
702 if (C->need_stack_bang(framesize)) {
4947
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
703 framesize -= wordSize;
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
704 st->print("# stack bang");
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
705 st->print("\n\t");
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
706 st->print("pushq rbp\t# Save rbp");
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
707 if (framesize) {
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
708 st->print("\n\t");
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
709 st->print("subq rsp, #%d\t# Create frame",framesize);
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
710 }
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
711 } else {
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
712 st->print("subq rsp, #%d\t# Create frame",framesize);
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
713 st->print("\n\t");
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
714 framesize -= wordSize;
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
715 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
716 }
a61af66fc99e Initial load
duke
parents:
diff changeset
717
a61af66fc99e Initial load
duke
parents:
diff changeset
718 if (VerifyStackAtCalls) {
4947
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
719 st->print("\n\t");
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
720 framesize -= wordSize;
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
721 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
722 #ifdef ASSERT
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
723 st->print("\n\t");
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
724 st->print("# stack alignment check");
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
725 #endif
0
a61af66fc99e Initial load
duke
parents:
diff changeset
726 }
4947
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
727 st->cr();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
728 }
a61af66fc99e Initial load
duke
parents:
diff changeset
729 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
730
4947
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
731 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
732 Compile* C = ra_->C;
4947
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
733 MacroAssembler _masm(&cbuf);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
734
a61af66fc99e Initial load
duke
parents:
diff changeset
735 int framesize = C->frame_slots() << LogBytesPerInt;
4947
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
736
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
737 __ verified_entry(framesize, C->need_stack_bang(framesize), false);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
738
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
739 C->set_frame_complete(cbuf.insts_size());
0
a61af66fc99e Initial load
duke
parents:
diff changeset
740
4114
6729bbc1fcd6 7003454: order constants in constant table by number of references in code
twisti
parents: 4047
diff changeset
741 if (C->has_mach_constant_base_node()) {
6729bbc1fcd6 7003454: order constants in constant table by number of references in code
twisti
parents: 4047
diff changeset
742 // NOTE: We set the table base offset here because users might be
6729bbc1fcd6 7003454: order constants in constant table by number of references in code
twisti
parents: 4047
diff changeset
743 // emitted before MachConstantBaseNode.
6729bbc1fcd6 7003454: order constants in constant table by number of references in code
twisti
parents: 4047
diff changeset
744 Compile::ConstantTable& constant_table = C->constant_table();
6729bbc1fcd6 7003454: order constants in constant table by number of references in code
twisti
parents: 4047
diff changeset
745 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
6729bbc1fcd6 7003454: order constants in constant table by number of references in code
twisti
parents: 4047
diff changeset
746 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
747 }
a61af66fc99e Initial load
duke
parents:
diff changeset
748
a61af66fc99e Initial load
duke
parents:
diff changeset
749 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
a61af66fc99e Initial load
duke
parents:
diff changeset
750 {
a61af66fc99e Initial load
duke
parents:
diff changeset
751 return MachNode::size(ra_); // too many variables; just compute it
a61af66fc99e Initial load
duke
parents:
diff changeset
752 // the hard way
a61af66fc99e Initial load
duke
parents:
diff changeset
753 }
a61af66fc99e Initial load
duke
parents:
diff changeset
754
a61af66fc99e Initial load
duke
parents:
diff changeset
755 int MachPrologNode::reloc() const
a61af66fc99e Initial load
duke
parents:
diff changeset
756 {
a61af66fc99e Initial load
duke
parents:
diff changeset
757 return 0; // a large enough number
a61af66fc99e Initial load
duke
parents:
diff changeset
758 }
a61af66fc99e Initial load
duke
parents:
diff changeset
759
a61af66fc99e Initial load
duke
parents:
diff changeset
760 //=============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
761 #ifndef PRODUCT
a61af66fc99e Initial load
duke
parents:
diff changeset
762 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
a61af66fc99e Initial load
duke
parents:
diff changeset
763 {
a61af66fc99e Initial load
duke
parents:
diff changeset
764 Compile* C = ra_->C;
a61af66fc99e Initial load
duke
parents:
diff changeset
765 int framesize = C->frame_slots() << LogBytesPerInt;
a61af66fc99e Initial load
duke
parents:
diff changeset
766 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
a61af66fc99e Initial load
duke
parents:
diff changeset
767 // Remove word for return adr already pushed
a61af66fc99e Initial load
duke
parents:
diff changeset
768 // and RBP
a61af66fc99e Initial load
duke
parents:
diff changeset
769 framesize -= 2*wordSize;
a61af66fc99e Initial load
duke
parents:
diff changeset
770
a61af66fc99e Initial load
duke
parents:
diff changeset
771 if (framesize) {
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
772 st->print_cr("addq rsp, %d\t# Destroy frame", framesize);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
773 st->print("\t");
a61af66fc99e Initial load
duke
parents:
diff changeset
774 }
a61af66fc99e Initial load
duke
parents:
diff changeset
775
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
776 st->print_cr("popq rbp");
0
a61af66fc99e Initial load
duke
parents:
diff changeset
777 if (do_polling() && C->is_method_compilation()) {
a61af66fc99e Initial load
duke
parents:
diff changeset
778 st->print("\t");
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
779 if (Assembler::is_polling_page_far()) {
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
780 st->print_cr("movq rscratch1, #polling_page_address\n\t"
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
781 "testl rax, [rscratch1]\t"
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
782 "# Safepoint: poll for GC");
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
783 } else {
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
784 st->print_cr("testl rax, [rip + #offset_to_poll_page]\t"
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
785 "# Safepoint: poll for GC");
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
786 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
787 }
a61af66fc99e Initial load
duke
parents:
diff changeset
788 }
a61af66fc99e Initial load
duke
parents:
diff changeset
789 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
790
a61af66fc99e Initial load
duke
parents:
diff changeset
791 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
a61af66fc99e Initial load
duke
parents:
diff changeset
792 {
a61af66fc99e Initial load
duke
parents:
diff changeset
793 Compile* C = ra_->C;
a61af66fc99e Initial load
duke
parents:
diff changeset
794 int framesize = C->frame_slots() << LogBytesPerInt;
a61af66fc99e Initial load
duke
parents:
diff changeset
795 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
a61af66fc99e Initial load
duke
parents:
diff changeset
796 // Remove word for return adr already pushed
a61af66fc99e Initial load
duke
parents:
diff changeset
797 // and RBP
a61af66fc99e Initial load
duke
parents:
diff changeset
798 framesize -= 2*wordSize;
a61af66fc99e Initial load
duke
parents:
diff changeset
799
a61af66fc99e Initial load
duke
parents:
diff changeset
800 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
a61af66fc99e Initial load
duke
parents:
diff changeset
801
a61af66fc99e Initial load
duke
parents:
diff changeset
802 if (framesize) {
a61af66fc99e Initial load
duke
parents:
diff changeset
803 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
804 if (framesize < 0x80) {
a61af66fc99e Initial load
duke
parents:
diff changeset
805 emit_opcode(cbuf, 0x83); // addq rsp, #framesize
a61af66fc99e Initial load
duke
parents:
diff changeset
806 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
a61af66fc99e Initial load
duke
parents:
diff changeset
807 emit_d8(cbuf, framesize);
a61af66fc99e Initial load
duke
parents:
diff changeset
808 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
809 emit_opcode(cbuf, 0x81); // addq rsp, #framesize
a61af66fc99e Initial load
duke
parents:
diff changeset
810 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
a61af66fc99e Initial load
duke
parents:
diff changeset
811 emit_d32(cbuf, framesize);
a61af66fc99e Initial load
duke
parents:
diff changeset
812 }
a61af66fc99e Initial load
duke
parents:
diff changeset
813 }
a61af66fc99e Initial load
duke
parents:
diff changeset
814
a61af66fc99e Initial load
duke
parents:
diff changeset
815 // popq rbp
a61af66fc99e Initial load
duke
parents:
diff changeset
816 emit_opcode(cbuf, 0x58 | RBP_enc);
a61af66fc99e Initial load
duke
parents:
diff changeset
817
a61af66fc99e Initial load
duke
parents:
diff changeset
818 if (do_polling() && C->is_method_compilation()) {
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
819 MacroAssembler _masm(&cbuf);
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
820 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
821 if (Assembler::is_polling_page_far()) {
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
822 __ lea(rscratch1, polling_page);
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
823 __ relocate(relocInfo::poll_return_type);
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
824 __ testl(rax, Address(rscratch1, 0));
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
825 } else {
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
826 __ testl(rax, polling_page);
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
827 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
828 }
a61af66fc99e Initial load
duke
parents:
diff changeset
829 }
a61af66fc99e Initial load
duke
parents:
diff changeset
830
a61af66fc99e Initial load
duke
parents:
diff changeset
831 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
a61af66fc99e Initial load
duke
parents:
diff changeset
832 {
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
833 return MachNode::size(ra_); // too many variables; just compute it
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
834 // the hard way
0
a61af66fc99e Initial load
duke
parents:
diff changeset
835 }
a61af66fc99e Initial load
duke
parents:
diff changeset
836
a61af66fc99e Initial load
duke
parents:
diff changeset
837 int MachEpilogNode::reloc() const
a61af66fc99e Initial load
duke
parents:
diff changeset
838 {
a61af66fc99e Initial load
duke
parents:
diff changeset
839 return 2; // a large enough number
a61af66fc99e Initial load
duke
parents:
diff changeset
840 }
a61af66fc99e Initial load
duke
parents:
diff changeset
841
a61af66fc99e Initial load
duke
parents:
diff changeset
842 const Pipeline* MachEpilogNode::pipeline() const
a61af66fc99e Initial load
duke
parents:
diff changeset
843 {
a61af66fc99e Initial load
duke
parents:
diff changeset
844 return MachNode::pipeline_class();
a61af66fc99e Initial load
duke
parents:
diff changeset
845 }
a61af66fc99e Initial load
duke
parents:
diff changeset
846
a61af66fc99e Initial load
duke
parents:
diff changeset
847 int MachEpilogNode::safepoint_offset() const
a61af66fc99e Initial load
duke
parents:
diff changeset
848 {
a61af66fc99e Initial load
duke
parents:
diff changeset
849 return 0;
a61af66fc99e Initial load
duke
parents:
diff changeset
850 }
a61af66fc99e Initial load
duke
parents:
diff changeset
851
a61af66fc99e Initial load
duke
parents:
diff changeset
852 //=============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
853
a61af66fc99e Initial load
duke
parents:
diff changeset
854 enum RC {
a61af66fc99e Initial load
duke
parents:
diff changeset
855 rc_bad,
a61af66fc99e Initial load
duke
parents:
diff changeset
856 rc_int,
a61af66fc99e Initial load
duke
parents:
diff changeset
857 rc_float,
a61af66fc99e Initial load
duke
parents:
diff changeset
858 rc_stack
a61af66fc99e Initial load
duke
parents:
diff changeset
859 };
a61af66fc99e Initial load
duke
parents:
diff changeset
860
a61af66fc99e Initial load
duke
parents:
diff changeset
861 static enum RC rc_class(OptoReg::Name reg)
a61af66fc99e Initial load
duke
parents:
diff changeset
862 {
a61af66fc99e Initial load
duke
parents:
diff changeset
863 if( !OptoReg::is_valid(reg) ) return rc_bad;
a61af66fc99e Initial load
duke
parents:
diff changeset
864
a61af66fc99e Initial load
duke
parents:
diff changeset
865 if (OptoReg::is_stack(reg)) return rc_stack;
a61af66fc99e Initial load
duke
parents:
diff changeset
866
a61af66fc99e Initial load
duke
parents:
diff changeset
867 VMReg r = OptoReg::as_VMReg(reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
868
a61af66fc99e Initial load
duke
parents:
diff changeset
869 if (r->is_Register()) return rc_int;
a61af66fc99e Initial load
duke
parents:
diff changeset
870
a61af66fc99e Initial load
duke
parents:
diff changeset
871 assert(r->is_XMMRegister(), "must be");
a61af66fc99e Initial load
duke
parents:
diff changeset
872 return rc_float;
a61af66fc99e Initial load
duke
parents:
diff changeset
873 }
a61af66fc99e Initial load
duke
parents:
diff changeset
874
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
875 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
876 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
877 int src_hi, int dst_hi, uint ireg, outputStream* st);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
878
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
879 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
880 int stack_offset, int reg, uint ireg, outputStream* st);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
881
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
882 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
883 int dst_offset, uint ireg, outputStream* st) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
884 if (cbuf) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
885 MacroAssembler _masm(cbuf);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
886 switch (ireg) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
887 case Op_VecS:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
888 __ movq(Address(rsp, -8), rax);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
889 __ movl(rax, Address(rsp, src_offset));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
890 __ movl(Address(rsp, dst_offset), rax);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
891 __ movq(rax, Address(rsp, -8));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
892 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
893 case Op_VecD:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
894 __ pushq(Address(rsp, src_offset));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
895 __ popq (Address(rsp, dst_offset));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
896 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
897 case Op_VecX:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
898 __ pushq(Address(rsp, src_offset));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
899 __ popq (Address(rsp, dst_offset));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
900 __ pushq(Address(rsp, src_offset+8));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
901 __ popq (Address(rsp, dst_offset+8));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
902 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
903 case Op_VecY:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
904 __ vmovdqu(Address(rsp, -32), xmm0);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
905 __ vmovdqu(xmm0, Address(rsp, src_offset));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
906 __ vmovdqu(Address(rsp, dst_offset), xmm0);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
907 __ vmovdqu(xmm0, Address(rsp, -32));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
908 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
909 default:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
910 ShouldNotReachHere();
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
911 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
912 #ifndef PRODUCT
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
913 } else {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
914 switch (ireg) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
915 case Op_VecS:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
916 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
917 "movl rax, [rsp + #%d]\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
918 "movl [rsp + #%d], rax\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
919 "movq rax, [rsp - #8]",
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
920 src_offset, dst_offset);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
921 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
922 case Op_VecD:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
923 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
924 "popq [rsp + #%d]",
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
925 src_offset, dst_offset);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
926 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
927 case Op_VecX:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
928 st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
929 "popq [rsp + #%d]\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
930 "pushq [rsp + #%d]\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
931 "popq [rsp + #%d]",
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
932 src_offset, dst_offset, src_offset+8, dst_offset+8);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
933 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
934 case Op_VecY:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
935 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
936 "vmovdqu xmm0, [rsp + #%d]\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
937 "vmovdqu [rsp + #%d], xmm0\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
938 "vmovdqu xmm0, [rsp - #32]",
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
939 src_offset, dst_offset);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
940 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
941 default:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
942 ShouldNotReachHere();
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
943 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
944 #endif
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
945 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
946 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
947
0
a61af66fc99e Initial load
duke
parents:
diff changeset
948 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
a61af66fc99e Initial load
duke
parents:
diff changeset
949 PhaseRegAlloc* ra_,
a61af66fc99e Initial load
duke
parents:
diff changeset
950 bool do_size,
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
951 outputStream* st) const {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
952 assert(cbuf != NULL || st != NULL, "sanity");
0
a61af66fc99e Initial load
duke
parents:
diff changeset
953 // Get registers to move
a61af66fc99e Initial load
duke
parents:
diff changeset
954 OptoReg::Name src_second = ra_->get_reg_second(in(1));
a61af66fc99e Initial load
duke
parents:
diff changeset
955 OptoReg::Name src_first = ra_->get_reg_first(in(1));
a61af66fc99e Initial load
duke
parents:
diff changeset
956 OptoReg::Name dst_second = ra_->get_reg_second(this);
a61af66fc99e Initial load
duke
parents:
diff changeset
957 OptoReg::Name dst_first = ra_->get_reg_first(this);
a61af66fc99e Initial load
duke
parents:
diff changeset
958
a61af66fc99e Initial load
duke
parents:
diff changeset
959 enum RC src_second_rc = rc_class(src_second);
a61af66fc99e Initial load
duke
parents:
diff changeset
960 enum RC src_first_rc = rc_class(src_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
961 enum RC dst_second_rc = rc_class(dst_second);
a61af66fc99e Initial load
duke
parents:
diff changeset
962 enum RC dst_first_rc = rc_class(dst_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
963
a61af66fc99e Initial load
duke
parents:
diff changeset
964 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
a61af66fc99e Initial load
duke
parents:
diff changeset
965 "must move at least 1 register" );
a61af66fc99e Initial load
duke
parents:
diff changeset
966
a61af66fc99e Initial load
duke
parents:
diff changeset
967 if (src_first == dst_first && src_second == dst_second) {
a61af66fc99e Initial load
duke
parents:
diff changeset
968 // Self copy, no move
a61af66fc99e Initial load
duke
parents:
diff changeset
969 return 0;
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
970 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
971 if (bottom_type()->isa_vect() != NULL) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
972 uint ireg = ideal_reg();
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
973 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
974 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity");
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
975 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
976 // mem -> mem
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
977 int src_offset = ra_->reg2offset(src_first);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
978 int dst_offset = ra_->reg2offset(dst_first);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
979 vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
980 } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
981 vec_mov_helper(cbuf, false, src_first, dst_first, src_second, dst_second, ireg, st);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
982 } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
983 int stack_offset = ra_->reg2offset(dst_first);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
984 vec_spill_helper(cbuf, false, false, stack_offset, src_first, ireg, st);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
985 } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
986 int stack_offset = ra_->reg2offset(src_first);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
987 vec_spill_helper(cbuf, false, true, stack_offset, dst_first, ireg, st);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
988 } else {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
989 ShouldNotReachHere();
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
990 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
991 return 0;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
992 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
993 if (src_first_rc == rc_stack) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
994 // mem ->
a61af66fc99e Initial load
duke
parents:
diff changeset
995 if (dst_first_rc == rc_stack) {
a61af66fc99e Initial load
duke
parents:
diff changeset
996 // mem -> mem
a61af66fc99e Initial load
duke
parents:
diff changeset
997 assert(src_second != dst_first, "overlap");
a61af66fc99e Initial load
duke
parents:
diff changeset
998 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
a61af66fc99e Initial load
duke
parents:
diff changeset
999 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1000 // 64-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1001 int src_offset = ra_->reg2offset(src_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
1002 int dst_offset = ra_->reg2offset(dst_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
1003 if (cbuf) {
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1004 MacroAssembler _masm(cbuf);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1005 __ pushq(Address(rsp, src_offset));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1006 __ popq (Address(rsp, dst_offset));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1007 #ifndef PRODUCT
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1008 } else {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1009 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1010 "popq [rsp + #%d]",
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1011 src_offset, dst_offset);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1012 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1013 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1014 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1015 // 32-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1016 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1017 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1018 // No pushl/popl, so:
a61af66fc99e Initial load
duke
parents:
diff changeset
1019 int src_offset = ra_->reg2offset(src_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
1020 int dst_offset = ra_->reg2offset(dst_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
1021 if (cbuf) {
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1022 MacroAssembler _masm(cbuf);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1023 __ movq(Address(rsp, -8), rax);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1024 __ movl(rax, Address(rsp, src_offset));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1025 __ movl(Address(rsp, dst_offset), rax);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1026 __ movq(rax, Address(rsp, -8));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1027 #ifndef PRODUCT
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1028 } else {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1029 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1030 "movl rax, [rsp + #%d]\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1031 "movl [rsp + #%d], rax\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1032 "movq rax, [rsp - #8]",
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1033 src_offset, dst_offset);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1034 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1035 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1036 }
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1037 return 0;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1038 } else if (dst_first_rc == rc_int) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1039 // mem -> gpr
a61af66fc99e Initial load
duke
parents:
diff changeset
1040 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
a61af66fc99e Initial load
duke
parents:
diff changeset
1041 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1042 // 64-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1043 int offset = ra_->reg2offset(src_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
1044 if (cbuf) {
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1045 MacroAssembler _masm(cbuf);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1046 __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1047 #ifndef PRODUCT
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1048 } else {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1049 st->print("movq %s, [rsp + #%d]\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1050 Matcher::regName[dst_first],
a61af66fc99e Initial load
duke
parents:
diff changeset
1051 offset);
a61af66fc99e Initial load
duke
parents:
diff changeset
1052 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1053 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1054 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1055 // 32-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1056 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1057 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1058 int offset = ra_->reg2offset(src_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
1059 if (cbuf) {
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1060 MacroAssembler _masm(cbuf);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1061 __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1062 #ifndef PRODUCT
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1063 } else {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1064 st->print("movl %s, [rsp + #%d]\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1065 Matcher::regName[dst_first],
a61af66fc99e Initial load
duke
parents:
diff changeset
1066 offset);
a61af66fc99e Initial load
duke
parents:
diff changeset
1067 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1068 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1069 }
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1070 return 0;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1071 } else if (dst_first_rc == rc_float) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1072 // mem-> xmm
a61af66fc99e Initial load
duke
parents:
diff changeset
1073 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
a61af66fc99e Initial load
duke
parents:
diff changeset
1074 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1075 // 64-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1076 int offset = ra_->reg2offset(src_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
1077 if (cbuf) {
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
1078 MacroAssembler _masm(cbuf);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
1079 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1080 #ifndef PRODUCT
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1081 } else {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1082 st->print("%s %s, [rsp + #%d]\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1083 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
a61af66fc99e Initial load
duke
parents:
diff changeset
1084 Matcher::regName[dst_first],
a61af66fc99e Initial load
duke
parents:
diff changeset
1085 offset);
a61af66fc99e Initial load
duke
parents:
diff changeset
1086 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1087 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1088 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1089 // 32-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1090 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1091 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1092 int offset = ra_->reg2offset(src_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
1093 if (cbuf) {
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
1094 MacroAssembler _masm(cbuf);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
1095 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1096 #ifndef PRODUCT
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1097 } else {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1098 st->print("movss %s, [rsp + #%d]\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1099 Matcher::regName[dst_first],
a61af66fc99e Initial load
duke
parents:
diff changeset
1100 offset);
a61af66fc99e Initial load
duke
parents:
diff changeset
1101 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1102 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1103 }
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1104 return 0;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1105 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1106 } else if (src_first_rc == rc_int) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1107 // gpr ->
a61af66fc99e Initial load
duke
parents:
diff changeset
1108 if (dst_first_rc == rc_stack) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1109 // gpr -> mem
a61af66fc99e Initial load
duke
parents:
diff changeset
1110 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
a61af66fc99e Initial load
duke
parents:
diff changeset
1111 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1112 // 64-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1113 int offset = ra_->reg2offset(dst_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
1114 if (cbuf) {
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1115 MacroAssembler _masm(cbuf);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1116 __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1117 #ifndef PRODUCT
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1118 } else {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1119 st->print("movq [rsp + #%d], %s\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1120 offset,
a61af66fc99e Initial load
duke
parents:
diff changeset
1121 Matcher::regName[src_first]);
a61af66fc99e Initial load
duke
parents:
diff changeset
1122 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1123 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1124 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1125 // 32-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1126 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1127 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1128 int offset = ra_->reg2offset(dst_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
1129 if (cbuf) {
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1130 MacroAssembler _masm(cbuf);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1131 __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1132 #ifndef PRODUCT
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1133 } else {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1134 st->print("movl [rsp + #%d], %s\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1135 offset,
a61af66fc99e Initial load
duke
parents:
diff changeset
1136 Matcher::regName[src_first]);
a61af66fc99e Initial load
duke
parents:
diff changeset
1137 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1138 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1139 }
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1140 return 0;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1141 } else if (dst_first_rc == rc_int) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1142 // gpr -> gpr
a61af66fc99e Initial load
duke
parents:
diff changeset
1143 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
a61af66fc99e Initial load
duke
parents:
diff changeset
1144 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1145 // 64-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1146 if (cbuf) {
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1147 MacroAssembler _masm(cbuf);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1148 __ movq(as_Register(Matcher::_regEncode[dst_first]),
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1149 as_Register(Matcher::_regEncode[src_first]));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1150 #ifndef PRODUCT
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1151 } else {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1152 st->print("movq %s, %s\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1153 Matcher::regName[dst_first],
a61af66fc99e Initial load
duke
parents:
diff changeset
1154 Matcher::regName[src_first]);
a61af66fc99e Initial load
duke
parents:
diff changeset
1155 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1156 }
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1157 return 0;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1158 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1159 // 32-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1160 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1161 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1162 if (cbuf) {
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1163 MacroAssembler _masm(cbuf);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1164 __ movl(as_Register(Matcher::_regEncode[dst_first]),
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1165 as_Register(Matcher::_regEncode[src_first]));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1166 #ifndef PRODUCT
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1167 } else {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1168 st->print("movl %s, %s\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1169 Matcher::regName[dst_first],
a61af66fc99e Initial load
duke
parents:
diff changeset
1170 Matcher::regName[src_first]);
a61af66fc99e Initial load
duke
parents:
diff changeset
1171 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1172 }
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1173 return 0;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1174 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1175 } else if (dst_first_rc == rc_float) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1176 // gpr -> xmm
a61af66fc99e Initial load
duke
parents:
diff changeset
1177 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
a61af66fc99e Initial load
duke
parents:
diff changeset
1178 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1179 // 64-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1180 if (cbuf) {
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
1181 MacroAssembler _masm(cbuf);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
1182 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1183 #ifndef PRODUCT
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1184 } else {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1185 st->print("movdq %s, %s\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1186 Matcher::regName[dst_first],
a61af66fc99e Initial load
duke
parents:
diff changeset
1187 Matcher::regName[src_first]);
a61af66fc99e Initial load
duke
parents:
diff changeset
1188 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1189 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1190 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1191 // 32-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1192 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1193 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1194 if (cbuf) {
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
1195 MacroAssembler _masm(cbuf);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
1196 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1197 #ifndef PRODUCT
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1198 } else {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1199 st->print("movdl %s, %s\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1200 Matcher::regName[dst_first],
a61af66fc99e Initial load
duke
parents:
diff changeset
1201 Matcher::regName[src_first]);
a61af66fc99e Initial load
duke
parents:
diff changeset
1202 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1203 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1204 }
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1205 return 0;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1206 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1207 } else if (src_first_rc == rc_float) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1208 // xmm ->
a61af66fc99e Initial load
duke
parents:
diff changeset
1209 if (dst_first_rc == rc_stack) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1210 // xmm -> mem
a61af66fc99e Initial load
duke
parents:
diff changeset
1211 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
a61af66fc99e Initial load
duke
parents:
diff changeset
1212 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1213 // 64-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1214 int offset = ra_->reg2offset(dst_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
1215 if (cbuf) {
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
1216 MacroAssembler _masm(cbuf);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
1217 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1218 #ifndef PRODUCT
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1219 } else {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1220 st->print("movsd [rsp + #%d], %s\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1221 offset,
a61af66fc99e Initial load
duke
parents:
diff changeset
1222 Matcher::regName[src_first]);
a61af66fc99e Initial load
duke
parents:
diff changeset
1223 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1224 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1225 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1226 // 32-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1227 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1228 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1229 int offset = ra_->reg2offset(dst_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
1230 if (cbuf) {
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
1231 MacroAssembler _masm(cbuf);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
1232 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1233 #ifndef PRODUCT
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1234 } else {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1235 st->print("movss [rsp + #%d], %s\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1236 offset,
a61af66fc99e Initial load
duke
parents:
diff changeset
1237 Matcher::regName[src_first]);
a61af66fc99e Initial load
duke
parents:
diff changeset
1238 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1239 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1240 }
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1241 return 0;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1242 } else if (dst_first_rc == rc_int) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1243 // xmm -> gpr
a61af66fc99e Initial load
duke
parents:
diff changeset
1244 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
a61af66fc99e Initial load
duke
parents:
diff changeset
1245 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1246 // 64-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1247 if (cbuf) {
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
1248 MacroAssembler _masm(cbuf);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
1249 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1250 #ifndef PRODUCT
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1251 } else {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1252 st->print("movdq %s, %s\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1253 Matcher::regName[dst_first],
a61af66fc99e Initial load
duke
parents:
diff changeset
1254 Matcher::regName[src_first]);
a61af66fc99e Initial load
duke
parents:
diff changeset
1255 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1256 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1257 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1258 // 32-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1259 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1260 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1261 if (cbuf) {
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
1262 MacroAssembler _masm(cbuf);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
1263 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1264 #ifndef PRODUCT
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1265 } else {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1266 st->print("movdl %s, %s\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1267 Matcher::regName[dst_first],
a61af66fc99e Initial load
duke
parents:
diff changeset
1268 Matcher::regName[src_first]);
a61af66fc99e Initial load
duke
parents:
diff changeset
1269 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1270 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1271 }
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1272 return 0;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1273 } else if (dst_first_rc == rc_float) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1274 // xmm -> xmm
a61af66fc99e Initial load
duke
parents:
diff changeset
1275 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
a61af66fc99e Initial load
duke
parents:
diff changeset
1276 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1277 // 64-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1278 if (cbuf) {
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
1279 MacroAssembler _masm(cbuf);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
1280 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1281 #ifndef PRODUCT
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1282 } else {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1283 st->print("%s %s, %s\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1284 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
a61af66fc99e Initial load
duke
parents:
diff changeset
1285 Matcher::regName[dst_first],
a61af66fc99e Initial load
duke
parents:
diff changeset
1286 Matcher::regName[src_first]);
a61af66fc99e Initial load
duke
parents:
diff changeset
1287 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1288 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1289 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1290 // 32-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1291 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1292 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1293 if (cbuf) {
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
1294 MacroAssembler _masm(cbuf);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
1295 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1296 #ifndef PRODUCT
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1297 } else {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1298 st->print("%s %s, %s\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1299 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
a61af66fc99e Initial load
duke
parents:
diff changeset
1300 Matcher::regName[dst_first],
a61af66fc99e Initial load
duke
parents:
diff changeset
1301 Matcher::regName[src_first]);
a61af66fc99e Initial load
duke
parents:
diff changeset
1302 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1303 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1304 }
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1305 return 0;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1306 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1307 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1308
a61af66fc99e Initial load
duke
parents:
diff changeset
1309 assert(0," foo ");
a61af66fc99e Initial load
duke
parents:
diff changeset
1310 Unimplemented();
a61af66fc99e Initial load
duke
parents:
diff changeset
1311 return 0;
a61af66fc99e Initial load
duke
parents:
diff changeset
1312 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1313
a61af66fc99e Initial load
duke
parents:
diff changeset
1314 #ifndef PRODUCT
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1315 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1316 implementation(NULL, ra_, false, st);
a61af66fc99e Initial load
duke
parents:
diff changeset
1317 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1318 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1319
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1320 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1321 implementation(&cbuf, ra_, false, NULL);
a61af66fc99e Initial load
duke
parents:
diff changeset
1322 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1323
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1324 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1325 return MachNode::size(ra_);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1326 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1327
a61af66fc99e Initial load
duke
parents:
diff changeset
1328 //=============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
1329 #ifndef PRODUCT
a61af66fc99e Initial load
duke
parents:
diff changeset
1330 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
a61af66fc99e Initial load
duke
parents:
diff changeset
1331 {
a61af66fc99e Initial load
duke
parents:
diff changeset
1332 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
a61af66fc99e Initial load
duke
parents:
diff changeset
1333 int reg = ra_->get_reg_first(this);
a61af66fc99e Initial load
duke
parents:
diff changeset
1334 st->print("leaq %s, [rsp + #%d]\t# box lock",
a61af66fc99e Initial load
duke
parents:
diff changeset
1335 Matcher::regName[reg], offset);
a61af66fc99e Initial load
duke
parents:
diff changeset
1336 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1337 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1338
a61af66fc99e Initial load
duke
parents:
diff changeset
1339 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
a61af66fc99e Initial load
duke
parents:
diff changeset
1340 {
a61af66fc99e Initial load
duke
parents:
diff changeset
1341 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
a61af66fc99e Initial load
duke
parents:
diff changeset
1342 int reg = ra_->get_encode(this);
a61af66fc99e Initial load
duke
parents:
diff changeset
1343 if (offset >= 0x80) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1344 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
a61af66fc99e Initial load
duke
parents:
diff changeset
1345 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
a61af66fc99e Initial load
duke
parents:
diff changeset
1346 emit_rm(cbuf, 0x2, reg & 7, 0x04);
a61af66fc99e Initial load
duke
parents:
diff changeset
1347 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
a61af66fc99e Initial load
duke
parents:
diff changeset
1348 emit_d32(cbuf, offset);
a61af66fc99e Initial load
duke
parents:
diff changeset
1349 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1350 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
a61af66fc99e Initial load
duke
parents:
diff changeset
1351 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
a61af66fc99e Initial load
duke
parents:
diff changeset
1352 emit_rm(cbuf, 0x1, reg & 7, 0x04);
a61af66fc99e Initial load
duke
parents:
diff changeset
1353 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
a61af66fc99e Initial load
duke
parents:
diff changeset
1354 emit_d8(cbuf, offset);
a61af66fc99e Initial load
duke
parents:
diff changeset
1355 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1356 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1357
a61af66fc99e Initial load
duke
parents:
diff changeset
1358 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
a61af66fc99e Initial load
duke
parents:
diff changeset
1359 {
a61af66fc99e Initial load
duke
parents:
diff changeset
1360 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
a61af66fc99e Initial load
duke
parents:
diff changeset
1361 return (offset < 0x80) ? 5 : 8; // REX
a61af66fc99e Initial load
duke
parents:
diff changeset
1362 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1363
a61af66fc99e Initial load
duke
parents:
diff changeset
1364 //=============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
1365
a61af66fc99e Initial load
duke
parents:
diff changeset
1366 // emit call stub, compiled java to interpreter
a61af66fc99e Initial load
duke
parents:
diff changeset
1367 void emit_java_to_interp(CodeBuffer& cbuf)
a61af66fc99e Initial load
duke
parents:
diff changeset
1368 {
a61af66fc99e Initial load
duke
parents:
diff changeset
1369 // Stub is fixed up when the corresponding call is converted from
a61af66fc99e Initial load
duke
parents:
diff changeset
1370 // calling compiled code to calling interpreted code.
a61af66fc99e Initial load
duke
parents:
diff changeset
1371 // movq rbx, 0
a61af66fc99e Initial load
duke
parents:
diff changeset
1372 // jmp -5 # to self
a61af66fc99e Initial load
duke
parents:
diff changeset
1373
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
1374 address mark = cbuf.insts_mark(); // get mark within main instrs section
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
1375
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
1376 // Note that the code buffer's insts_mark is always relative to insts.
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1377 // That's why we must use the macroassembler to generate a stub.
a61af66fc99e Initial load
duke
parents:
diff changeset
1378 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
1379
a61af66fc99e Initial load
duke
parents:
diff changeset
1380 address base =
a61af66fc99e Initial load
duke
parents:
diff changeset
1381 __ start_a_stub(Compile::MAX_stubs_size);
a61af66fc99e Initial load
duke
parents:
diff changeset
1382 if (base == NULL) return; // CodeBuffer::expand failed
a61af66fc99e Initial load
duke
parents:
diff changeset
1383 // static stub relocation stores the instruction address of the call
a61af66fc99e Initial load
duke
parents:
diff changeset
1384 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM64);
a61af66fc99e Initial load
duke
parents:
diff changeset
1385 // static stub relocation also tags the methodOop in the code-stream.
a61af66fc99e Initial load
duke
parents:
diff changeset
1386 __ movoop(rbx, (jobject) NULL); // method is zapped till fixup time
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
1387 // This is recognized as unresolved by relocs/nativeinst/ic code
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1388 __ jump(RuntimeAddress(__ pc()));
a61af66fc99e Initial load
duke
parents:
diff changeset
1389
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
1390 // Update current stubs pointer and restore insts_end.
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1391 __ end_a_stub();
a61af66fc99e Initial load
duke
parents:
diff changeset
1392 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1393
a61af66fc99e Initial load
duke
parents:
diff changeset
1394 // size of call stub, compiled java to interpretor
a61af66fc99e Initial load
duke
parents:
diff changeset
1395 uint size_java_to_interp()
a61af66fc99e Initial load
duke
parents:
diff changeset
1396 {
a61af66fc99e Initial load
duke
parents:
diff changeset
1397 return 15; // movq (1+1+8); jmp (1+4)
a61af66fc99e Initial load
duke
parents:
diff changeset
1398 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1399
a61af66fc99e Initial load
duke
parents:
diff changeset
1400 // relocation entries for call stub, compiled java to interpretor
a61af66fc99e Initial load
duke
parents:
diff changeset
1401 uint reloc_java_to_interp()
a61af66fc99e Initial load
duke
parents:
diff changeset
1402 {
a61af66fc99e Initial load
duke
parents:
diff changeset
1403 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
a61af66fc99e Initial load
duke
parents:
diff changeset
1404 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1405
a61af66fc99e Initial load
duke
parents:
diff changeset
1406 //=============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
1407 #ifndef PRODUCT
a61af66fc99e Initial load
duke
parents:
diff changeset
1408 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
a61af66fc99e Initial load
duke
parents:
diff changeset
1409 {
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
1410 if (UseCompressedOops) {
1571
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
1411 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
1412 if (Universe::narrow_oop_shift() != 0) {
1571
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
1413 st->print_cr("\tdecode_heap_oop_not_null rscratch1, rscratch1");
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
1414 }
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
1415 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check");
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
1416 } else {
1571
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
1417 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
1418 "# Inline cache check");
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
1419 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1420 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
1571
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
1421 st->print_cr("\tnop\t# nops to align entry point");
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1422 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1423 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1424
a61af66fc99e Initial load
duke
parents:
diff changeset
1425 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
a61af66fc99e Initial load
duke
parents:
diff changeset
1426 {
a61af66fc99e Initial load
duke
parents:
diff changeset
1427 MacroAssembler masm(&cbuf);
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
1428 uint insts_size = cbuf.insts_size();
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
1429 if (UseCompressedOops) {
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
1430 masm.load_klass(rscratch1, j_rarg0);
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
1431 masm.cmpptr(rax, rscratch1);
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
1432 } else {
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
1433 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
1434 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1435
a61af66fc99e Initial load
duke
parents:
diff changeset
1436 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
a61af66fc99e Initial load
duke
parents:
diff changeset
1437
a61af66fc99e Initial load
duke
parents:
diff changeset
1438 /* WARNING these NOPs are critical so that verified entry point is properly
1571
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
1439 4 bytes aligned for patching by NativeJump::patch_verified_entry() */
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
1440 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
1571
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
1441 if (OptoBreakpoint) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1442 // Leave space for int3
1571
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
1443 nops_cnt -= 1;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1444 }
1571
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
1445 nops_cnt &= 0x3; // Do not add nops if code is aligned.
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
1446 if (nops_cnt > 0)
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
1447 masm.nop(nops_cnt);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1448 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1449
a61af66fc99e Initial load
duke
parents:
diff changeset
1450 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
a61af66fc99e Initial load
duke
parents:
diff changeset
1451 {
1571
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
1452 return MachNode::size(ra_); // too many variables; just compute it
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
1453 // the hard way
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1454 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1455
a61af66fc99e Initial load
duke
parents:
diff changeset
1456
a61af66fc99e Initial load
duke
parents:
diff changeset
1457 //=============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
1458 uint size_exception_handler()
a61af66fc99e Initial load
duke
parents:
diff changeset
1459 {
a61af66fc99e Initial load
duke
parents:
diff changeset
1460 // NativeCall instruction size is the same as NativeJump.
a61af66fc99e Initial load
duke
parents:
diff changeset
1461 // Note that this value is also credited (in output.cpp) to
a61af66fc99e Initial load
duke
parents:
diff changeset
1462 // the size of the code section.
a61af66fc99e Initial load
duke
parents:
diff changeset
1463 return NativeJump::instruction_size;
a61af66fc99e Initial load
duke
parents:
diff changeset
1464 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1465
a61af66fc99e Initial load
duke
parents:
diff changeset
1466 // Emit exception handler code.
a61af66fc99e Initial load
duke
parents:
diff changeset
1467 int emit_exception_handler(CodeBuffer& cbuf)
a61af66fc99e Initial load
duke
parents:
diff changeset
1468 {
a61af66fc99e Initial load
duke
parents:
diff changeset
1469
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
1470 // Note that the code buffer's insts_mark is always relative to insts.
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1471 // That's why we must use the macroassembler to generate a handler.
a61af66fc99e Initial load
duke
parents:
diff changeset
1472 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
1473 address base =
a61af66fc99e Initial load
duke
parents:
diff changeset
1474 __ start_a_stub(size_exception_handler());
a61af66fc99e Initial load
duke
parents:
diff changeset
1475 if (base == NULL) return 0; // CodeBuffer::expand failed
a61af66fc99e Initial load
duke
parents:
diff changeset
1476 int offset = __ offset();
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
1477 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1478 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
a61af66fc99e Initial load
duke
parents:
diff changeset
1479 __ end_a_stub();
a61af66fc99e Initial load
duke
parents:
diff changeset
1480 return offset;
a61af66fc99e Initial load
duke
parents:
diff changeset
1481 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1482
a61af66fc99e Initial load
duke
parents:
diff changeset
1483 uint size_deopt_handler()
a61af66fc99e Initial load
duke
parents:
diff changeset
1484 {
a61af66fc99e Initial load
duke
parents:
diff changeset
1485 // three 5 byte instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
1486 return 15;
a61af66fc99e Initial load
duke
parents:
diff changeset
1487 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1488
a61af66fc99e Initial load
duke
parents:
diff changeset
1489 // Emit deopt handler code.
a61af66fc99e Initial load
duke
parents:
diff changeset
1490 int emit_deopt_handler(CodeBuffer& cbuf)
a61af66fc99e Initial load
duke
parents:
diff changeset
1491 {
a61af66fc99e Initial load
duke
parents:
diff changeset
1492
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
1493 // Note that the code buffer's insts_mark is always relative to insts.
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1494 // That's why we must use the macroassembler to generate a handler.
a61af66fc99e Initial load
duke
parents:
diff changeset
1495 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
1496 address base =
a61af66fc99e Initial load
duke
parents:
diff changeset
1497 __ start_a_stub(size_deopt_handler());
a61af66fc99e Initial load
duke
parents:
diff changeset
1498 if (base == NULL) return 0; // CodeBuffer::expand failed
a61af66fc99e Initial load
duke
parents:
diff changeset
1499 int offset = __ offset();
a61af66fc99e Initial load
duke
parents:
diff changeset
1500 address the_pc = (address) __ pc();
a61af66fc99e Initial load
duke
parents:
diff changeset
1501 Label next;
a61af66fc99e Initial load
duke
parents:
diff changeset
1502 // push a "the_pc" on the stack without destroying any registers
a61af66fc99e Initial load
duke
parents:
diff changeset
1503 // as they all may be live.
a61af66fc99e Initial load
duke
parents:
diff changeset
1504
a61af66fc99e Initial load
duke
parents:
diff changeset
1505 // push address of "next"
a61af66fc99e Initial load
duke
parents:
diff changeset
1506 __ call(next, relocInfo::none); // reloc none is fine since it is a disp32
a61af66fc99e Initial load
duke
parents:
diff changeset
1507 __ bind(next);
a61af66fc99e Initial load
duke
parents:
diff changeset
1508 // adjust it so it matches "the_pc"
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
1509 __ subptr(Address(rsp, 0), __ offset() - offset);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1510 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
a61af66fc99e Initial load
duke
parents:
diff changeset
1511 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
a61af66fc99e Initial load
duke
parents:
diff changeset
1512 __ end_a_stub();
a61af66fc99e Initial load
duke
parents:
diff changeset
1513 return offset;
a61af66fc99e Initial load
duke
parents:
diff changeset
1514 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1515
a61af66fc99e Initial load
duke
parents:
diff changeset
1516 int Matcher::regnum_to_fpu_offset(int regnum)
a61af66fc99e Initial load
duke
parents:
diff changeset
1517 {
a61af66fc99e Initial load
duke
parents:
diff changeset
1518 return regnum - 32; // The FP registers are in the second chunk
a61af66fc99e Initial load
duke
parents:
diff changeset
1519 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1520
a61af66fc99e Initial load
duke
parents:
diff changeset
1521 // This is UltraSparc specific, true just means we have fast l2f conversion
a61af66fc99e Initial load
duke
parents:
diff changeset
1522 const bool Matcher::convL2FSupported(void) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1523 return true;
a61af66fc99e Initial load
duke
parents:
diff changeset
1524 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1525
a61af66fc99e Initial load
duke
parents:
diff changeset
1526 // Is this branch offset short enough that a short branch can be used?
a61af66fc99e Initial load
duke
parents:
diff changeset
1527 //
a61af66fc99e Initial load
duke
parents:
diff changeset
1528 // NOTE: If the platform does not provide any short branch variants, then
a61af66fc99e Initial load
duke
parents:
diff changeset
1529 // this method should return false for offset 0.
3851
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
1530 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
1531 // The passed offset is relative to address of the branch.
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
1532 // On 86 a branch displacement is calculated relative to address
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
1533 // of a next instruction.
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
1534 offset -= br_size;
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
1535
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
1536 // the short version of jmpConUCF2 contains multiple branches,
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
1537 // making the reach slightly less
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
1538 if (rule == jmpConUCF2_rule)
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
1539 return (-126 <= offset && offset <= 125);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
1540 return (-128 <= offset && offset <= 127);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1541 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1542
a61af66fc99e Initial load
duke
parents:
diff changeset
1543 const bool Matcher::isSimpleConstant64(jlong value) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1544 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
a61af66fc99e Initial load
duke
parents:
diff changeset
1545 //return value == (int) value; // Cf. storeImmL and immL32.
a61af66fc99e Initial load
duke
parents:
diff changeset
1546
a61af66fc99e Initial load
duke
parents:
diff changeset
1547 // Probably always true, even if a temp register is required.
a61af66fc99e Initial load
duke
parents:
diff changeset
1548 return true;
a61af66fc99e Initial load
duke
parents:
diff changeset
1549 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1550
a61af66fc99e Initial load
duke
parents:
diff changeset
1551 // The ecx parameter to rep stosq for the ClearArray node is in words.
a61af66fc99e Initial load
duke
parents:
diff changeset
1552 const bool Matcher::init_array_count_is_in_bytes = false;
a61af66fc99e Initial load
duke
parents:
diff changeset
1553
a61af66fc99e Initial load
duke
parents:
diff changeset
1554 // Threshold size for cleararray.
a61af66fc99e Initial load
duke
parents:
diff changeset
1555 const int Matcher::init_array_short_size = 8 * BytesPerLong;
a61af66fc99e Initial load
duke
parents:
diff changeset
1556
4047
d8cb48376797 7097546: Optimize use of CMOVE instructions
kvn
parents: 3854
diff changeset
1557 // No additional cost for CMOVL.
d8cb48376797 7097546: Optimize use of CMOVE instructions
kvn
parents: 3854
diff changeset
1558 const int Matcher::long_cmove_cost() { return 0; }
d8cb48376797 7097546: Optimize use of CMOVE instructions
kvn
parents: 3854
diff changeset
1559
d8cb48376797 7097546: Optimize use of CMOVE instructions
kvn
parents: 3854
diff changeset
1560 // No CMOVF/CMOVD with SSE2
d8cb48376797 7097546: Optimize use of CMOVE instructions
kvn
parents: 3854
diff changeset
1561 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
d8cb48376797 7097546: Optimize use of CMOVE instructions
kvn
parents: 3854
diff changeset
1562
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1563 // Should the Matcher clone shifts on addressing modes, expecting them
a61af66fc99e Initial load
duke
parents:
diff changeset
1564 // to be subsumed into complex addressing expressions or compute them
a61af66fc99e Initial load
duke
parents:
diff changeset
1565 // into registers? True for Intel but false for most RISCs
a61af66fc99e Initial load
duke
parents:
diff changeset
1566 const bool Matcher::clone_shift_expressions = true;
a61af66fc99e Initial load
duke
parents:
diff changeset
1567
2401
7e88bdae86ec 7029017: Additional architecture support for c2 compiler
roland
parents: 2320
diff changeset
1568 // Do we need to mask the count passed to shift instructions or does
7e88bdae86ec 7029017: Additional architecture support for c2 compiler
roland
parents: 2320
diff changeset
1569 // the cpu only look at the lower 5/6 bits anyway?
7e88bdae86ec 7029017: Additional architecture support for c2 compiler
roland
parents: 2320
diff changeset
1570 const bool Matcher::need_masked_shift_count = false;
7e88bdae86ec 7029017: Additional architecture support for c2 compiler
roland
parents: 2320
diff changeset
1571
1575
3657cb01ffc5 6954029: Improve implicit null check generation with compressed oops
kvn
parents: 1571
diff changeset
1572 bool Matcher::narrow_oop_use_complex_address() {
3657cb01ffc5 6954029: Improve implicit null check generation with compressed oops
kvn
parents: 1571
diff changeset
1573 assert(UseCompressedOops, "only for compressed oops code");
3657cb01ffc5 6954029: Improve implicit null check generation with compressed oops
kvn
parents: 1571
diff changeset
1574 return (LogMinObjAlignmentInBytes <= 3);
3657cb01ffc5 6954029: Improve implicit null check generation with compressed oops
kvn
parents: 1571
diff changeset
1575 }
3657cb01ffc5 6954029: Improve implicit null check generation with compressed oops
kvn
parents: 1571
diff changeset
1576
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1577 // Is it better to copy float constants, or load them directly from
a61af66fc99e Initial load
duke
parents:
diff changeset
1578 // memory? Intel can load a float constant from a direct address,
a61af66fc99e Initial load
duke
parents:
diff changeset
1579 // requiring no extra registers. Most RISCs will have to materialize
a61af66fc99e Initial load
duke
parents:
diff changeset
1580 // an address into a register first, so they would do better to copy
a61af66fc99e Initial load
duke
parents:
diff changeset
1581 // the constant from stack.
a61af66fc99e Initial load
duke
parents:
diff changeset
1582 const bool Matcher::rematerialize_float_constants = true; // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
1583
a61af66fc99e Initial load
duke
parents:
diff changeset
1584 // If CPU can load and store mis-aligned doubles directly then no
a61af66fc99e Initial load
duke
parents:
diff changeset
1585 // fixup is needed. Else we split the double into 2 integer pieces
a61af66fc99e Initial load
duke
parents:
diff changeset
1586 // and move it piece-by-piece. Only happens when passing doubles into
a61af66fc99e Initial load
duke
parents:
diff changeset
1587 // C code as the Java calling convention forces doubles to be aligned.
a61af66fc99e Initial load
duke
parents:
diff changeset
1588 const bool Matcher::misaligned_doubles_ok = true;
a61af66fc99e Initial load
duke
parents:
diff changeset
1589
a61af66fc99e Initial load
duke
parents:
diff changeset
1590 // No-op on amd64
a61af66fc99e Initial load
duke
parents:
diff changeset
1591 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
a61af66fc99e Initial load
duke
parents:
diff changeset
1592
a61af66fc99e Initial load
duke
parents:
diff changeset
1593 // Advertise here if the CPU requires explicit rounding operations to
a61af66fc99e Initial load
duke
parents:
diff changeset
1594 // implement the UseStrictFP mode.
a61af66fc99e Initial load
duke
parents:
diff changeset
1595 const bool Matcher::strict_fp_requires_explicit_rounding = true;
a61af66fc99e Initial load
duke
parents:
diff changeset
1596
1274
2883969d09e7 6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
parents: 1137
diff changeset
1597 // Are floats conerted to double when stored to stack during deoptimization?
2883969d09e7 6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
parents: 1137
diff changeset
1598 // On x64 it is stored without convertion so we can use normal access.
2883969d09e7 6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
parents: 1137
diff changeset
1599 bool Matcher::float_in_double() { return false; }
2883969d09e7 6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
parents: 1137
diff changeset
1600
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1601 // Do ints take an entire long register or just half?
a61af66fc99e Initial load
duke
parents:
diff changeset
1602 const bool Matcher::int_in_long = true;
a61af66fc99e Initial load
duke
parents:
diff changeset
1603
a61af66fc99e Initial load
duke
parents:
diff changeset
1604 // Return whether or not this register is ever used as an argument.
a61af66fc99e Initial load
duke
parents:
diff changeset
1605 // This function is used on startup to build the trampoline stubs in
a61af66fc99e Initial load
duke
parents:
diff changeset
1606 // generateOptoStub. Registers not mentioned will be killed by the VM
a61af66fc99e Initial load
duke
parents:
diff changeset
1607 // call in the trampoline, and arguments in those registers not be
a61af66fc99e Initial load
duke
parents:
diff changeset
1608 // available to the callee.
a61af66fc99e Initial load
duke
parents:
diff changeset
1609 bool Matcher::can_be_java_arg(int reg)
a61af66fc99e Initial load
duke
parents:
diff changeset
1610 {
a61af66fc99e Initial load
duke
parents:
diff changeset
1611 return
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1612 reg == RDI_num || reg == RDI_H_num ||
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1613 reg == RSI_num || reg == RSI_H_num ||
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1614 reg == RDX_num || reg == RDX_H_num ||
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1615 reg == RCX_num || reg == RCX_H_num ||
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1616 reg == R8_num || reg == R8_H_num ||
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1617 reg == R9_num || reg == R9_H_num ||
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1618 reg == R12_num || reg == R12_H_num ||
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1619 reg == XMM0_num || reg == XMM0b_num ||
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1620 reg == XMM1_num || reg == XMM1b_num ||
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1621 reg == XMM2_num || reg == XMM2b_num ||
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1622 reg == XMM3_num || reg == XMM3b_num ||
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1623 reg == XMM4_num || reg == XMM4b_num ||
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1624 reg == XMM5_num || reg == XMM5b_num ||
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1625 reg == XMM6_num || reg == XMM6b_num ||
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1626 reg == XMM7_num || reg == XMM7b_num;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1627 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1628
a61af66fc99e Initial load
duke
parents:
diff changeset
1629 bool Matcher::is_spillable_arg(int reg)
a61af66fc99e Initial load
duke
parents:
diff changeset
1630 {
a61af66fc99e Initial load
duke
parents:
diff changeset
1631 return can_be_java_arg(reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
1632 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1633
1914
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents: 1827
diff changeset
1634 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents: 1827
diff changeset
1635 // In 64 bit mode a code which use multiply when
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents: 1827
diff changeset
1636 // devisor is constant is faster than hardware
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents: 1827
diff changeset
1637 // DIV instruction (it uses MulHiL).
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents: 1827
diff changeset
1638 return false;
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents: 1827
diff changeset
1639 }
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents: 1827
diff changeset
1640
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1641 // Register for DIVI projection of divmodI
a61af66fc99e Initial load
duke
parents:
diff changeset
1642 RegMask Matcher::divI_proj_mask() {
4121
db2e64ca2d5a 7090968: Allow adlc register class to depend on runtime conditions
roland
parents: 4114
diff changeset
1643 return INT_RAX_REG_mask();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1644 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1645
a61af66fc99e Initial load
duke
parents:
diff changeset
1646 // Register for MODI projection of divmodI
a61af66fc99e Initial load
duke
parents:
diff changeset
1647 RegMask Matcher::modI_proj_mask() {
4121
db2e64ca2d5a 7090968: Allow adlc register class to depend on runtime conditions
roland
parents: 4114
diff changeset
1648 return INT_RDX_REG_mask();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1649 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1650
a61af66fc99e Initial load
duke
parents:
diff changeset
1651 // Register for DIVL projection of divmodL
a61af66fc99e Initial load
duke
parents:
diff changeset
1652 RegMask Matcher::divL_proj_mask() {
4121
db2e64ca2d5a 7090968: Allow adlc register class to depend on runtime conditions
roland
parents: 4114
diff changeset
1653 return LONG_RAX_REG_mask();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1654 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1655
a61af66fc99e Initial load
duke
parents:
diff changeset
1656 // Register for MODL projection of divmodL
a61af66fc99e Initial load
duke
parents:
diff changeset
1657 RegMask Matcher::modL_proj_mask() {
4121
db2e64ca2d5a 7090968: Allow adlc register class to depend on runtime conditions
roland
parents: 4114
diff changeset
1658 return LONG_RDX_REG_mask();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1659 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1660
1137
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
1661 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
4121
db2e64ca2d5a 7090968: Allow adlc register class to depend on runtime conditions
roland
parents: 4114
diff changeset
1662 return PTR_RBP_REG_mask();
1137
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
1663 }
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
1664
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
1665 static Address build_address(int b, int i, int s, int d) {
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
1666 Register index = as_Register(i);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
1667 Address::ScaleFactor scale = (Address::ScaleFactor)s;
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
1668 if (index == rsp) {
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
1669 index = noreg;
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
1670 scale = Address::no_scale;
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
1671 }
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
1672 Address addr(as_Register(b), index, scale, d);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
1673 return addr;
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
1674 }
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
1675
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1676 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1677
a61af66fc99e Initial load
duke
parents:
diff changeset
1678 //----------ENCODING BLOCK-----------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
1679 // This block specifies the encoding classes used by the compiler to
a61af66fc99e Initial load
duke
parents:
diff changeset
1680 // output byte streams. Encoding classes are parameterized macros
a61af66fc99e Initial load
duke
parents:
diff changeset
1681 // used by Machine Instruction Nodes in order to generate the bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1682 // encoding of the instruction. Operands specify their base encoding
a61af66fc99e Initial load
duke
parents:
diff changeset
1683 // interface with the interface keyword. There are currently
a61af66fc99e Initial load
duke
parents:
diff changeset
1684 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
a61af66fc99e Initial load
duke
parents:
diff changeset
1685 // COND_INTER. REG_INTER causes an operand to generate a function
a61af66fc99e Initial load
duke
parents:
diff changeset
1686 // which returns its register number when queried. CONST_INTER causes
a61af66fc99e Initial load
duke
parents:
diff changeset
1687 // an operand to generate a function which returns the value of the
a61af66fc99e Initial load
duke
parents:
diff changeset
1688 // constant when queried. MEMORY_INTER causes an operand to generate
a61af66fc99e Initial load
duke
parents:
diff changeset
1689 // four functions which return the Base Register, the Index Register,
a61af66fc99e Initial load
duke
parents:
diff changeset
1690 // the Scale Value, and the Offset Value of the operand when queried.
a61af66fc99e Initial load
duke
parents:
diff changeset
1691 // COND_INTER causes an operand to generate six functions which return
a61af66fc99e Initial load
duke
parents:
diff changeset
1692 // the encoding code (ie - encoding bits for the instruction)
a61af66fc99e Initial load
duke
parents:
diff changeset
1693 // associated with each basic boolean condition for a conditional
a61af66fc99e Initial load
duke
parents:
diff changeset
1694 // instruction.
a61af66fc99e Initial load
duke
parents:
diff changeset
1695 //
a61af66fc99e Initial load
duke
parents:
diff changeset
1696 // Instructions specify two basic values for encoding. Again, a
a61af66fc99e Initial load
duke
parents:
diff changeset
1697 // function is available to check if the constant displacement is an
a61af66fc99e Initial load
duke
parents:
diff changeset
1698 // oop. They use the ins_encode keyword to specify their encoding
a61af66fc99e Initial load
duke
parents:
diff changeset
1699 // classes (which must be a sequence of enc_class names, and their
a61af66fc99e Initial load
duke
parents:
diff changeset
1700 // parameters, specified in the encoding block), and they use the
a61af66fc99e Initial load
duke
parents:
diff changeset
1701 // opcode keyword to specify, in order, their primary, secondary, and
a61af66fc99e Initial load
duke
parents:
diff changeset
1702 // tertiary opcode. Only the opcode sections which a particular
a61af66fc99e Initial load
duke
parents:
diff changeset
1703 // instruction needs for encoding need to be specified.
a61af66fc99e Initial load
duke
parents:
diff changeset
1704 encode %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1705 // Build emit functions for each basic byte or larger field in the
a61af66fc99e Initial load
duke
parents:
diff changeset
1706 // intel encoding scheme (opcode, rm, sib, immediate), and call them
a61af66fc99e Initial load
duke
parents:
diff changeset
1707 // from C++ code in the enc_class source block. Emit functions will
a61af66fc99e Initial load
duke
parents:
diff changeset
1708 // live in the main source block for now. In future, we can
a61af66fc99e Initial load
duke
parents:
diff changeset
1709 // generalize this by adding a syntax that specifies the sizes of
a61af66fc99e Initial load
duke
parents:
diff changeset
1710 // fields in an order, so that the adlc can build the emit functions
a61af66fc99e Initial load
duke
parents:
diff changeset
1711 // automagically
a61af66fc99e Initial load
duke
parents:
diff changeset
1712
a61af66fc99e Initial load
duke
parents:
diff changeset
1713 // Emit primary opcode
a61af66fc99e Initial load
duke
parents:
diff changeset
1714 enc_class OpcP
a61af66fc99e Initial load
duke
parents:
diff changeset
1715 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1716 emit_opcode(cbuf, $primary);
a61af66fc99e Initial load
duke
parents:
diff changeset
1717 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1718
a61af66fc99e Initial load
duke
parents:
diff changeset
1719 // Emit secondary opcode
a61af66fc99e Initial load
duke
parents:
diff changeset
1720 enc_class OpcS
a61af66fc99e Initial load
duke
parents:
diff changeset
1721 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1722 emit_opcode(cbuf, $secondary);
a61af66fc99e Initial load
duke
parents:
diff changeset
1723 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1724
a61af66fc99e Initial load
duke
parents:
diff changeset
1725 // Emit tertiary opcode
a61af66fc99e Initial load
duke
parents:
diff changeset
1726 enc_class OpcT
a61af66fc99e Initial load
duke
parents:
diff changeset
1727 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1728 emit_opcode(cbuf, $tertiary);
a61af66fc99e Initial load
duke
parents:
diff changeset
1729 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1730
a61af66fc99e Initial load
duke
parents:
diff changeset
1731 // Emit opcode directly
a61af66fc99e Initial load
duke
parents:
diff changeset
1732 enc_class Opcode(immI d8)
a61af66fc99e Initial load
duke
parents:
diff changeset
1733 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1734 emit_opcode(cbuf, $d8$$constant);
a61af66fc99e Initial load
duke
parents:
diff changeset
1735 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1736
a61af66fc99e Initial load
duke
parents:
diff changeset
1737 // Emit size prefix
a61af66fc99e Initial load
duke
parents:
diff changeset
1738 enc_class SizePrefix
a61af66fc99e Initial load
duke
parents:
diff changeset
1739 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1740 emit_opcode(cbuf, 0x66);
a61af66fc99e Initial load
duke
parents:
diff changeset
1741 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1742
a61af66fc99e Initial load
duke
parents:
diff changeset
1743 enc_class reg(rRegI reg)
a61af66fc99e Initial load
duke
parents:
diff changeset
1744 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1745 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
a61af66fc99e Initial load
duke
parents:
diff changeset
1746 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1747
a61af66fc99e Initial load
duke
parents:
diff changeset
1748 enc_class reg_reg(rRegI dst, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
1749 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1750 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
a61af66fc99e Initial load
duke
parents:
diff changeset
1751 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1752
a61af66fc99e Initial load
duke
parents:
diff changeset
1753 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
1754 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1755 emit_opcode(cbuf, $opcode$$constant);
a61af66fc99e Initial load
duke
parents:
diff changeset
1756 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
a61af66fc99e Initial load
duke
parents:
diff changeset
1757 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1758
a61af66fc99e Initial load
duke
parents:
diff changeset
1759 enc_class cdql_enc(no_rax_rdx_RegI div)
a61af66fc99e Initial load
duke
parents:
diff changeset
1760 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1761 // Full implementation of Java idiv and irem; checks for
a61af66fc99e Initial load
duke
parents:
diff changeset
1762 // special case as described in JVM spec., p.243 & p.271.
a61af66fc99e Initial load
duke
parents:
diff changeset
1763 //
a61af66fc99e Initial load
duke
parents:
diff changeset
1764 // normal case special case
a61af66fc99e Initial load
duke
parents:
diff changeset
1765 //
a61af66fc99e Initial load
duke
parents:
diff changeset
1766 // input : rax: dividend min_int
a61af66fc99e Initial load
duke
parents:
diff changeset
1767 // reg: divisor -1
a61af66fc99e Initial load
duke
parents:
diff changeset
1768 //
a61af66fc99e Initial load
duke
parents:
diff changeset
1769 // output: rax: quotient (= rax idiv reg) min_int
a61af66fc99e Initial load
duke
parents:
diff changeset
1770 // rdx: remainder (= rax irem reg) 0
a61af66fc99e Initial load
duke
parents:
diff changeset
1771 //
a61af66fc99e Initial load
duke
parents:
diff changeset
1772 // Code sequnce:
a61af66fc99e Initial load
duke
parents:
diff changeset
1773 //
a61af66fc99e Initial load
duke
parents:
diff changeset
1774 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
a61af66fc99e Initial load
duke
parents:
diff changeset
1775 // 5: 75 07/08 jne e <normal>
a61af66fc99e Initial load
duke
parents:
diff changeset
1776 // 7: 33 d2 xor %edx,%edx
a61af66fc99e Initial load
duke
parents:
diff changeset
1777 // [div >= 8 -> offset + 1]
a61af66fc99e Initial load
duke
parents:
diff changeset
1778 // [REX_B]
a61af66fc99e Initial load
duke
parents:
diff changeset
1779 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
a61af66fc99e Initial load
duke
parents:
diff changeset
1780 // c: 74 03/04 je 11 <done>
a61af66fc99e Initial load
duke
parents:
diff changeset
1781 // 000000000000000e <normal>:
a61af66fc99e Initial load
duke
parents:
diff changeset
1782 // e: 99 cltd
a61af66fc99e Initial load
duke
parents:
diff changeset
1783 // [div >= 8 -> offset + 1]
a61af66fc99e Initial load
duke
parents:
diff changeset
1784 // [REX_B]
a61af66fc99e Initial load
duke
parents:
diff changeset
1785 // f: f7 f9 idiv $div
a61af66fc99e Initial load
duke
parents:
diff changeset
1786 // 0000000000000011 <done>:
a61af66fc99e Initial load
duke
parents:
diff changeset
1787
a61af66fc99e Initial load
duke
parents:
diff changeset
1788 // cmp $0x80000000,%eax
a61af66fc99e Initial load
duke
parents:
diff changeset
1789 emit_opcode(cbuf, 0x3d);
a61af66fc99e Initial load
duke
parents:
diff changeset
1790 emit_d8(cbuf, 0x00);
a61af66fc99e Initial load
duke
parents:
diff changeset
1791 emit_d8(cbuf, 0x00);
a61af66fc99e Initial load
duke
parents:
diff changeset
1792 emit_d8(cbuf, 0x00);
a61af66fc99e Initial load
duke
parents:
diff changeset
1793 emit_d8(cbuf, 0x80);
a61af66fc99e Initial load
duke
parents:
diff changeset
1794
a61af66fc99e Initial load
duke
parents:
diff changeset
1795 // jne e <normal>
a61af66fc99e Initial load
duke
parents:
diff changeset
1796 emit_opcode(cbuf, 0x75);
a61af66fc99e Initial load
duke
parents:
diff changeset
1797 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
a61af66fc99e Initial load
duke
parents:
diff changeset
1798
a61af66fc99e Initial load
duke
parents:
diff changeset
1799 // xor %edx,%edx
a61af66fc99e Initial load
duke
parents:
diff changeset
1800 emit_opcode(cbuf, 0x33);
a61af66fc99e Initial load
duke
parents:
diff changeset
1801 emit_d8(cbuf, 0xD2);
a61af66fc99e Initial load
duke
parents:
diff changeset
1802
a61af66fc99e Initial load
duke
parents:
diff changeset
1803 // cmp $0xffffffffffffffff,%ecx
a61af66fc99e Initial load
duke
parents:
diff changeset
1804 if ($div$$reg >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1805 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
1806 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1807 emit_opcode(cbuf, 0x83);
a61af66fc99e Initial load
duke
parents:
diff changeset
1808 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
a61af66fc99e Initial load
duke
parents:
diff changeset
1809 emit_d8(cbuf, 0xFF);
a61af66fc99e Initial load
duke
parents:
diff changeset
1810
a61af66fc99e Initial load
duke
parents:
diff changeset
1811 // je 11 <done>
a61af66fc99e Initial load
duke
parents:
diff changeset
1812 emit_opcode(cbuf, 0x74);
a61af66fc99e Initial load
duke
parents:
diff changeset
1813 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
a61af66fc99e Initial load
duke
parents:
diff changeset
1814
a61af66fc99e Initial load
duke
parents:
diff changeset
1815 // <normal>
a61af66fc99e Initial load
duke
parents:
diff changeset
1816 // cltd
a61af66fc99e Initial load
duke
parents:
diff changeset
1817 emit_opcode(cbuf, 0x99);
a61af66fc99e Initial load
duke
parents:
diff changeset
1818
a61af66fc99e Initial load
duke
parents:
diff changeset
1819 // idivl (note: must be emitted by the user of this rule)
a61af66fc99e Initial load
duke
parents:
diff changeset
1820 // <done>
a61af66fc99e Initial load
duke
parents:
diff changeset
1821 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1822
a61af66fc99e Initial load
duke
parents:
diff changeset
1823 enc_class cdqq_enc(no_rax_rdx_RegL div)
a61af66fc99e Initial load
duke
parents:
diff changeset
1824 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1825 // Full implementation of Java ldiv and lrem; checks for
a61af66fc99e Initial load
duke
parents:
diff changeset
1826 // special case as described in JVM spec., p.243 & p.271.
a61af66fc99e Initial load
duke
parents:
diff changeset
1827 //
a61af66fc99e Initial load
duke
parents:
diff changeset
1828 // normal case special case
a61af66fc99e Initial load
duke
parents:
diff changeset
1829 //
a61af66fc99e Initial load
duke
parents:
diff changeset
1830 // input : rax: dividend min_long
a61af66fc99e Initial load
duke
parents:
diff changeset
1831 // reg: divisor -1
a61af66fc99e Initial load
duke
parents:
diff changeset
1832 //
a61af66fc99e Initial load
duke
parents:
diff changeset
1833 // output: rax: quotient (= rax idiv reg) min_long
a61af66fc99e Initial load
duke
parents:
diff changeset
1834 // rdx: remainder (= rax irem reg) 0
a61af66fc99e Initial load
duke
parents:
diff changeset
1835 //
a61af66fc99e Initial load
duke
parents:
diff changeset
1836 // Code sequnce:
a61af66fc99e Initial load
duke
parents:
diff changeset
1837 //
a61af66fc99e Initial load
duke
parents:
diff changeset
1838 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
a61af66fc99e Initial load
duke
parents:
diff changeset
1839 // 7: 00 00 80
a61af66fc99e Initial load
duke
parents:
diff changeset
1840 // a: 48 39 d0 cmp %rdx,%rax
a61af66fc99e Initial load
duke
parents:
diff changeset
1841 // d: 75 08 jne 17 <normal>
a61af66fc99e Initial load
duke
parents:
diff changeset
1842 // f: 33 d2 xor %edx,%edx
a61af66fc99e Initial load
duke
parents:
diff changeset
1843 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
a61af66fc99e Initial load
duke
parents:
diff changeset
1844 // 15: 74 05 je 1c <done>
a61af66fc99e Initial load
duke
parents:
diff changeset
1845 // 0000000000000017 <normal>:
a61af66fc99e Initial load
duke
parents:
diff changeset
1846 // 17: 48 99 cqto
a61af66fc99e Initial load
duke
parents:
diff changeset
1847 // 19: 48 f7 f9 idiv $div
a61af66fc99e Initial load
duke
parents:
diff changeset
1848 // 000000000000001c <done>:
a61af66fc99e Initial load
duke
parents:
diff changeset
1849
a61af66fc99e Initial load
duke
parents:
diff changeset
1850 // mov $0x8000000000000000,%rdx
a61af66fc99e Initial load
duke
parents:
diff changeset
1851 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
1852 emit_opcode(cbuf, 0xBA);
a61af66fc99e Initial load
duke
parents:
diff changeset
1853 emit_d8(cbuf, 0x00);
a61af66fc99e Initial load
duke
parents:
diff changeset
1854 emit_d8(cbuf, 0x00);
a61af66fc99e Initial load
duke
parents:
diff changeset
1855 emit_d8(cbuf, 0x00);
a61af66fc99e Initial load
duke
parents:
diff changeset
1856 emit_d8(cbuf, 0x00);
a61af66fc99e Initial load
duke
parents:
diff changeset
1857 emit_d8(cbuf, 0x00);
a61af66fc99e Initial load
duke
parents:
diff changeset
1858 emit_d8(cbuf, 0x00);
a61af66fc99e Initial load
duke
parents:
diff changeset
1859 emit_d8(cbuf, 0x00);
a61af66fc99e Initial load
duke
parents:
diff changeset
1860 emit_d8(cbuf, 0x80);
a61af66fc99e Initial load
duke
parents:
diff changeset
1861
a61af66fc99e Initial load
duke
parents:
diff changeset
1862 // cmp %rdx,%rax
a61af66fc99e Initial load
duke
parents:
diff changeset
1863 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
1864 emit_opcode(cbuf, 0x39);
a61af66fc99e Initial load
duke
parents:
diff changeset
1865 emit_d8(cbuf, 0xD0);
a61af66fc99e Initial load
duke
parents:
diff changeset
1866
a61af66fc99e Initial load
duke
parents:
diff changeset
1867 // jne 17 <normal>
a61af66fc99e Initial load
duke
parents:
diff changeset
1868 emit_opcode(cbuf, 0x75);
a61af66fc99e Initial load
duke
parents:
diff changeset
1869 emit_d8(cbuf, 0x08);
a61af66fc99e Initial load
duke
parents:
diff changeset
1870
a61af66fc99e Initial load
duke
parents:
diff changeset
1871 // xor %edx,%edx
a61af66fc99e Initial load
duke
parents:
diff changeset
1872 emit_opcode(cbuf, 0x33);
a61af66fc99e Initial load
duke
parents:
diff changeset
1873 emit_d8(cbuf, 0xD2);
a61af66fc99e Initial load
duke
parents:
diff changeset
1874
a61af66fc99e Initial load
duke
parents:
diff changeset
1875 // cmp $0xffffffffffffffff,$div
a61af66fc99e Initial load
duke
parents:
diff changeset
1876 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
a61af66fc99e Initial load
duke
parents:
diff changeset
1877 emit_opcode(cbuf, 0x83);
a61af66fc99e Initial load
duke
parents:
diff changeset
1878 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
a61af66fc99e Initial load
duke
parents:
diff changeset
1879 emit_d8(cbuf, 0xFF);
a61af66fc99e Initial load
duke
parents:
diff changeset
1880
a61af66fc99e Initial load
duke
parents:
diff changeset
1881 // je 1e <done>
a61af66fc99e Initial load
duke
parents:
diff changeset
1882 emit_opcode(cbuf, 0x74);
a61af66fc99e Initial load
duke
parents:
diff changeset
1883 emit_d8(cbuf, 0x05);
a61af66fc99e Initial load
duke
parents:
diff changeset
1884
a61af66fc99e Initial load
duke
parents:
diff changeset
1885 // <normal>
a61af66fc99e Initial load
duke
parents:
diff changeset
1886 // cqto
a61af66fc99e Initial load
duke
parents:
diff changeset
1887 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
1888 emit_opcode(cbuf, 0x99);
a61af66fc99e Initial load
duke
parents:
diff changeset
1889
a61af66fc99e Initial load
duke
parents:
diff changeset
1890 // idivq (note: must be emitted by the user of this rule)
a61af66fc99e Initial load
duke
parents:
diff changeset
1891 // <done>
a61af66fc99e Initial load
duke
parents:
diff changeset
1892 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1893
a61af66fc99e Initial load
duke
parents:
diff changeset
1894 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
a61af66fc99e Initial load
duke
parents:
diff changeset
1895 enc_class OpcSE(immI imm)
a61af66fc99e Initial load
duke
parents:
diff changeset
1896 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1897 // Emit primary opcode and set sign-extend bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1898 // Check for 8-bit immediate, and set sign extend bit in opcode
a61af66fc99e Initial load
duke
parents:
diff changeset
1899 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1900 emit_opcode(cbuf, $primary | 0x02);
a61af66fc99e Initial load
duke
parents:
diff changeset
1901 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1902 // 32-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
1903 emit_opcode(cbuf, $primary);
a61af66fc99e Initial load
duke
parents:
diff changeset
1904 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1905 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1906
a61af66fc99e Initial load
duke
parents:
diff changeset
1907 enc_class OpcSErm(rRegI dst, immI imm)
a61af66fc99e Initial load
duke
parents:
diff changeset
1908 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1909 // OpcSEr/m
a61af66fc99e Initial load
duke
parents:
diff changeset
1910 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
1911 if (dstenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1912 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
1913 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
1914 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1915 // Emit primary opcode and set sign-extend bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1916 // Check for 8-bit immediate, and set sign extend bit in opcode
a61af66fc99e Initial load
duke
parents:
diff changeset
1917 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1918 emit_opcode(cbuf, $primary | 0x02);
a61af66fc99e Initial load
duke
parents:
diff changeset
1919 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1920 // 32-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
1921 emit_opcode(cbuf, $primary);
a61af66fc99e Initial load
duke
parents:
diff changeset
1922 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1923 // Emit r/m byte with secondary opcode, after primary opcode.
a61af66fc99e Initial load
duke
parents:
diff changeset
1924 emit_rm(cbuf, 0x3, $secondary, dstenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
1925 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1926
a61af66fc99e Initial load
duke
parents:
diff changeset
1927 enc_class OpcSErm_wide(rRegL dst, immI imm)
a61af66fc99e Initial load
duke
parents:
diff changeset
1928 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1929 // OpcSEr/m
a61af66fc99e Initial load
duke
parents:
diff changeset
1930 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
1931 if (dstenc < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1932 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
1933 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1934 emit_opcode(cbuf, Assembler::REX_WB);
a61af66fc99e Initial load
duke
parents:
diff changeset
1935 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
1936 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1937 // Emit primary opcode and set sign-extend bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1938 // Check for 8-bit immediate, and set sign extend bit in opcode
a61af66fc99e Initial load
duke
parents:
diff changeset
1939 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1940 emit_opcode(cbuf, $primary | 0x02);
a61af66fc99e Initial load
duke
parents:
diff changeset
1941 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1942 // 32-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
1943 emit_opcode(cbuf, $primary);
a61af66fc99e Initial load
duke
parents:
diff changeset
1944 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1945 // Emit r/m byte with secondary opcode, after primary opcode.
a61af66fc99e Initial load
duke
parents:
diff changeset
1946 emit_rm(cbuf, 0x3, $secondary, dstenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
1947 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1948
a61af66fc99e Initial load
duke
parents:
diff changeset
1949 enc_class Con8or32(immI imm)
a61af66fc99e Initial load
duke
parents:
diff changeset
1950 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1951 // Check for 8-bit immediate, and set sign extend bit in opcode
a61af66fc99e Initial load
duke
parents:
diff changeset
1952 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1953 $$$emit8$imm$$constant;
a61af66fc99e Initial load
duke
parents:
diff changeset
1954 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1955 // 32-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
1956 $$$emit32$imm$$constant;
a61af66fc99e Initial load
duke
parents:
diff changeset
1957 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1958 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1959
a61af66fc99e Initial load
duke
parents:
diff changeset
1960 enc_class opc2_reg(rRegI dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
1961 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1962 // BSWAP
a61af66fc99e Initial load
duke
parents:
diff changeset
1963 emit_cc(cbuf, $secondary, $dst$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
1964 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1965
a61af66fc99e Initial load
duke
parents:
diff changeset
1966 enc_class opc3_reg(rRegI dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
1967 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1968 // BSWAP
a61af66fc99e Initial load
duke
parents:
diff changeset
1969 emit_cc(cbuf, $tertiary, $dst$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
1970 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1971
a61af66fc99e Initial load
duke
parents:
diff changeset
1972 enc_class reg_opc(rRegI div)
a61af66fc99e Initial load
duke
parents:
diff changeset
1973 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1974 // INC, DEC, IDIV, IMOD, JMP indirect, ...
a61af66fc99e Initial load
duke
parents:
diff changeset
1975 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
a61af66fc99e Initial load
duke
parents:
diff changeset
1976 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1977
a61af66fc99e Initial load
duke
parents:
diff changeset
1978 enc_class enc_cmov(cmpOp cop)
a61af66fc99e Initial load
duke
parents:
diff changeset
1979 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1980 // CMOV
a61af66fc99e Initial load
duke
parents:
diff changeset
1981 $$$emit8$primary;
a61af66fc99e Initial load
duke
parents:
diff changeset
1982 emit_cc(cbuf, $secondary, $cop$$cmpcode);
a61af66fc99e Initial load
duke
parents:
diff changeset
1983 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1984
a61af66fc99e Initial load
duke
parents:
diff changeset
1985 enc_class enc_PartialSubtypeCheck()
a61af66fc99e Initial load
duke
parents:
diff changeset
1986 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1987 Register Rrdi = as_Register(RDI_enc); // result register
a61af66fc99e Initial load
duke
parents:
diff changeset
1988 Register Rrax = as_Register(RAX_enc); // super class
a61af66fc99e Initial load
duke
parents:
diff changeset
1989 Register Rrcx = as_Register(RCX_enc); // killed
a61af66fc99e Initial load
duke
parents:
diff changeset
1990 Register Rrsi = as_Register(RSI_enc); // sub class
644
c517646eef23 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 643
diff changeset
1991 Label miss;
c517646eef23 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 643
diff changeset
1992 const bool set_cond_codes = true;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1993
a61af66fc99e Initial load
duke
parents:
diff changeset
1994 MacroAssembler _masm(&cbuf);
644
c517646eef23 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 643
diff changeset
1995 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
c517646eef23 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 643
diff changeset
1996 NULL, &miss,
c517646eef23 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 643
diff changeset
1997 /*set_cond_codes:*/ true);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1998 if ($primary) {
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
1999 __ xorptr(Rrdi, Rrdi);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2000 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2001 __ bind(miss);
a61af66fc99e Initial load
duke
parents:
diff changeset
2002 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2003
a61af66fc99e Initial load
duke
parents:
diff changeset
2004 enc_class Java_To_Interpreter(method meth)
a61af66fc99e Initial load
duke
parents:
diff changeset
2005 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2006 // CALL Java_To_Interpreter
a61af66fc99e Initial load
duke
parents:
diff changeset
2007 // This is the instruction starting address for relocation info.
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
2008 cbuf.set_insts_mark();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2009 $$$emit8$primary;
a61af66fc99e Initial load
duke
parents:
diff changeset
2010 // CALL directly to the runtime
a61af66fc99e Initial load
duke
parents:
diff changeset
2011 emit_d32_reloc(cbuf,
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
2012 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2013 runtime_call_Relocation::spec(),
a61af66fc99e Initial load
duke
parents:
diff changeset
2014 RELOC_DISP32);
a61af66fc99e Initial load
duke
parents:
diff changeset
2015 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2016
a61af66fc99e Initial load
duke
parents:
diff changeset
2017 enc_class Java_Static_Call(method meth)
a61af66fc99e Initial load
duke
parents:
diff changeset
2018 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2019 // JAVA STATIC CALL
a61af66fc99e Initial load
duke
parents:
diff changeset
2020 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
a61af66fc99e Initial load
duke
parents:
diff changeset
2021 // determine who we intended to call.
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
2022 cbuf.set_insts_mark();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2023 $$$emit8$primary;
a61af66fc99e Initial load
duke
parents:
diff changeset
2024
a61af66fc99e Initial load
duke
parents:
diff changeset
2025 if (!_method) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2026 emit_d32_reloc(cbuf,
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
2027 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2028 runtime_call_Relocation::spec(),
a61af66fc99e Initial load
duke
parents:
diff changeset
2029 RELOC_DISP32);
a61af66fc99e Initial load
duke
parents:
diff changeset
2030 } else if (_optimized_virtual) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2031 emit_d32_reloc(cbuf,
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
2032 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2033 opt_virtual_call_Relocation::spec(),
a61af66fc99e Initial load
duke
parents:
diff changeset
2034 RELOC_DISP32);
a61af66fc99e Initial load
duke
parents:
diff changeset
2035 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2036 emit_d32_reloc(cbuf,
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
2037 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2038 static_call_Relocation::spec(),
a61af66fc99e Initial load
duke
parents:
diff changeset
2039 RELOC_DISP32);
a61af66fc99e Initial load
duke
parents:
diff changeset
2040 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2041 if (_method) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2042 // Emit stub for static call
a61af66fc99e Initial load
duke
parents:
diff changeset
2043 emit_java_to_interp(cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2044 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2045 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2046
a61af66fc99e Initial load
duke
parents:
diff changeset
2047 enc_class Java_Dynamic_Call(method meth)
a61af66fc99e Initial load
duke
parents:
diff changeset
2048 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2049 // JAVA DYNAMIC CALL
a61af66fc99e Initial load
duke
parents:
diff changeset
2050 // !!!!!
a61af66fc99e Initial load
duke
parents:
diff changeset
2051 // Generate "movq rax, -1", placeholder instruction to load oop-info
a61af66fc99e Initial load
duke
parents:
diff changeset
2052 // emit_call_dynamic_prologue( cbuf );
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
2053 cbuf.set_insts_mark();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2054
a61af66fc99e Initial load
duke
parents:
diff changeset
2055 // movq rax, -1
a61af66fc99e Initial load
duke
parents:
diff changeset
2056 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
2057 emit_opcode(cbuf, 0xB8 | RAX_enc);
a61af66fc99e Initial load
duke
parents:
diff changeset
2058 emit_d64_reloc(cbuf,
a61af66fc99e Initial load
duke
parents:
diff changeset
2059 (int64_t) Universe::non_oop_word(),
a61af66fc99e Initial load
duke
parents:
diff changeset
2060 oop_Relocation::spec_for_immediate(), RELOC_IMM64);
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
2061 address virtual_call_oop_addr = cbuf.insts_mark();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2062 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
a61af66fc99e Initial load
duke
parents:
diff changeset
2063 // who we intended to call.
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
2064 cbuf.set_insts_mark();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2065 $$$emit8$primary;
a61af66fc99e Initial load
duke
parents:
diff changeset
2066 emit_d32_reloc(cbuf,
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
2067 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2068 virtual_call_Relocation::spec(virtual_call_oop_addr),
a61af66fc99e Initial load
duke
parents:
diff changeset
2069 RELOC_DISP32);
a61af66fc99e Initial load
duke
parents:
diff changeset
2070 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2071
a61af66fc99e Initial load
duke
parents:
diff changeset
2072 enc_class Java_Compiled_Call(method meth)
a61af66fc99e Initial load
duke
parents:
diff changeset
2073 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2074 // JAVA COMPILED CALL
a61af66fc99e Initial load
duke
parents:
diff changeset
2075 int disp = in_bytes(methodOopDesc:: from_compiled_offset());
a61af66fc99e Initial load
duke
parents:
diff changeset
2076
a61af66fc99e Initial load
duke
parents:
diff changeset
2077 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
a61af66fc99e Initial load
duke
parents:
diff changeset
2078 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
a61af66fc99e Initial load
duke
parents:
diff changeset
2079
a61af66fc99e Initial load
duke
parents:
diff changeset
2080 // callq *disp(%rax)
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
2081 cbuf.set_insts_mark();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2082 $$$emit8$primary;
a61af66fc99e Initial load
duke
parents:
diff changeset
2083 if (disp < 0x80) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2084 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
a61af66fc99e Initial load
duke
parents:
diff changeset
2085 emit_d8(cbuf, disp); // Displacement
a61af66fc99e Initial load
duke
parents:
diff changeset
2086 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2087 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
a61af66fc99e Initial load
duke
parents:
diff changeset
2088 emit_d32(cbuf, disp); // Displacement
a61af66fc99e Initial load
duke
parents:
diff changeset
2089 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2090 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2091
a61af66fc99e Initial load
duke
parents:
diff changeset
2092 enc_class reg_opc_imm(rRegI dst, immI8 shift)
a61af66fc99e Initial load
duke
parents:
diff changeset
2093 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2094 // SAL, SAR, SHR
a61af66fc99e Initial load
duke
parents:
diff changeset
2095 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2096 if (dstenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2097 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2098 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
2099 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2100 $$$emit8$primary;
a61af66fc99e Initial load
duke
parents:
diff changeset
2101 emit_rm(cbuf, 0x3, $secondary, dstenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
2102 $$$emit8$shift$$constant;
a61af66fc99e Initial load
duke
parents:
diff changeset
2103 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2104
a61af66fc99e Initial load
duke
parents:
diff changeset
2105 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
a61af66fc99e Initial load
duke
parents:
diff changeset
2106 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2107 // SAL, SAR, SHR
a61af66fc99e Initial load
duke
parents:
diff changeset
2108 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2109 if (dstenc < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2110 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
2111 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2112 emit_opcode(cbuf, Assembler::REX_WB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2113 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
2114 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2115 $$$emit8$primary;
a61af66fc99e Initial load
duke
parents:
diff changeset
2116 emit_rm(cbuf, 0x3, $secondary, dstenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
2117 $$$emit8$shift$$constant;
a61af66fc99e Initial load
duke
parents:
diff changeset
2118 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2119
a61af66fc99e Initial load
duke
parents:
diff changeset
2120 enc_class load_immI(rRegI dst, immI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2121 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2122 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2123 if (dstenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2124 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2125 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
2126 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2127 emit_opcode(cbuf, 0xB8 | dstenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
2128 $$$emit32$src$$constant;
a61af66fc99e Initial load
duke
parents:
diff changeset
2129 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2130
a61af66fc99e Initial load
duke
parents:
diff changeset
2131 enc_class load_immL(rRegL dst, immL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2132 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2133 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2134 if (dstenc < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2135 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
2136 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2137 emit_opcode(cbuf, Assembler::REX_WB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2138 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
2139 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2140 emit_opcode(cbuf, 0xB8 | dstenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
2141 emit_d64(cbuf, $src$$constant);
a61af66fc99e Initial load
duke
parents:
diff changeset
2142 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2143
a61af66fc99e Initial load
duke
parents:
diff changeset
2144 enc_class load_immUL32(rRegL dst, immUL32 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2145 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2146 // same as load_immI, but this time we care about zeroes in the high word
a61af66fc99e Initial load
duke
parents:
diff changeset
2147 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2148 if (dstenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2149 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2150 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
2151 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2152 emit_opcode(cbuf, 0xB8 | dstenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
2153 $$$emit32$src$$constant;
a61af66fc99e Initial load
duke
parents:
diff changeset
2154 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2155
a61af66fc99e Initial load
duke
parents:
diff changeset
2156 enc_class load_immL32(rRegL dst, immL32 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2157 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2158 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2159 if (dstenc < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2160 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
2161 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2162 emit_opcode(cbuf, Assembler::REX_WB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2163 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
2164 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2165 emit_opcode(cbuf, 0xC7);
a61af66fc99e Initial load
duke
parents:
diff changeset
2166 emit_rm(cbuf, 0x03, 0x00, dstenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
2167 $$$emit32$src$$constant;
a61af66fc99e Initial load
duke
parents:
diff changeset
2168 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2169
a61af66fc99e Initial load
duke
parents:
diff changeset
2170 enc_class load_immP31(rRegP dst, immP32 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2171 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2172 // same as load_immI, but this time we care about zeroes in the high word
a61af66fc99e Initial load
duke
parents:
diff changeset
2173 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2174 if (dstenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2175 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2176 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
2177 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2178 emit_opcode(cbuf, 0xB8 | dstenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
2179 $$$emit32$src$$constant;
a61af66fc99e Initial load
duke
parents:
diff changeset
2180 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2181
a61af66fc99e Initial load
duke
parents:
diff changeset
2182 enc_class load_immP(rRegP dst, immP src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2183 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2184 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2185 if (dstenc < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2186 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
2187 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2188 emit_opcode(cbuf, Assembler::REX_WB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2189 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
2190 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2191 emit_opcode(cbuf, 0xB8 | dstenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
2192 // This next line should be generated from ADLC
a61af66fc99e Initial load
duke
parents:
diff changeset
2193 if ($src->constant_is_oop()) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2194 emit_d64_reloc(cbuf, $src$$constant, relocInfo::oop_type, RELOC_IMM64);
a61af66fc99e Initial load
duke
parents:
diff changeset
2195 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2196 emit_d64(cbuf, $src$$constant);
a61af66fc99e Initial load
duke
parents:
diff changeset
2197 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2198 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2199
a61af66fc99e Initial load
duke
parents:
diff changeset
2200 enc_class Con32(immI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2201 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2202 // Output immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
2203 $$$emit32$src$$constant;
a61af66fc99e Initial load
duke
parents:
diff changeset
2204 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2205
a61af66fc99e Initial load
duke
parents:
diff changeset
2206 enc_class Con64(immL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2207 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2208 // Output immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
2209 emit_d64($src$$constant);
a61af66fc99e Initial load
duke
parents:
diff changeset
2210 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2211
a61af66fc99e Initial load
duke
parents:
diff changeset
2212 enc_class Con32F_as_bits(immF src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2213 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2214 // Output Float immediate bits
a61af66fc99e Initial load
duke
parents:
diff changeset
2215 jfloat jf = $src$$constant;
a61af66fc99e Initial load
duke
parents:
diff changeset
2216 jint jf_as_bits = jint_cast(jf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2217 emit_d32(cbuf, jf_as_bits);
a61af66fc99e Initial load
duke
parents:
diff changeset
2218 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2219
a61af66fc99e Initial load
duke
parents:
diff changeset
2220 enc_class Con16(immI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2221 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2222 // Output immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
2223 $$$emit16$src$$constant;
a61af66fc99e Initial load
duke
parents:
diff changeset
2224 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2225
a61af66fc99e Initial load
duke
parents:
diff changeset
2226 // How is this different from Con32??? XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
2227 enc_class Con_d32(immI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2228 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2229 emit_d32(cbuf,$src$$constant);
a61af66fc99e Initial load
duke
parents:
diff changeset
2230 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2231
a61af66fc99e Initial load
duke
parents:
diff changeset
2232 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI)
a61af66fc99e Initial load
duke
parents:
diff changeset
2233 // Output immediate memory reference
a61af66fc99e Initial load
duke
parents:
diff changeset
2234 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
a61af66fc99e Initial load
duke
parents:
diff changeset
2235 emit_d32(cbuf, 0x00);
a61af66fc99e Initial load
duke
parents:
diff changeset
2236 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2237
a61af66fc99e Initial load
duke
parents:
diff changeset
2238 enc_class lock_prefix()
a61af66fc99e Initial load
duke
parents:
diff changeset
2239 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2240 if (os::is_MP()) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2241 emit_opcode(cbuf, 0xF0); // lock
a61af66fc99e Initial load
duke
parents:
diff changeset
2242 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2243 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2244
a61af66fc99e Initial load
duke
parents:
diff changeset
2245 enc_class REX_mem(memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
2246 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2247 if ($mem$$base >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2248 if ($mem$$index < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2249 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2250 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2251 emit_opcode(cbuf, Assembler::REX_XB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2252 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2253 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2254 if ($mem$$index >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2255 emit_opcode(cbuf, Assembler::REX_X);
a61af66fc99e Initial load
duke
parents:
diff changeset
2256 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2257 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2258 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2259
a61af66fc99e Initial load
duke
parents:
diff changeset
2260 enc_class REX_mem_wide(memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
2261 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2262 if ($mem$$base >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2263 if ($mem$$index < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2264 emit_opcode(cbuf, Assembler::REX_WB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2265 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2266 emit_opcode(cbuf, Assembler::REX_WXB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2267 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2268 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2269 if ($mem$$index < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2270 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
2271 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2272 emit_opcode(cbuf, Assembler::REX_WX);
a61af66fc99e Initial load
duke
parents:
diff changeset
2273 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2274 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2275 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2276
a61af66fc99e Initial load
duke
parents:
diff changeset
2277 // for byte regs
a61af66fc99e Initial load
duke
parents:
diff changeset
2278 enc_class REX_breg(rRegI reg)
a61af66fc99e Initial load
duke
parents:
diff changeset
2279 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2280 if ($reg$$reg >= 4) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2281 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2282 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2283 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2284
a61af66fc99e Initial load
duke
parents:
diff changeset
2285 // for byte regs
a61af66fc99e Initial load
duke
parents:
diff changeset
2286 enc_class REX_reg_breg(rRegI dst, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2287 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2288 if ($dst$$reg < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2289 if ($src$$reg >= 4) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2290 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2291 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2292 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2293 if ($src$$reg < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2294 emit_opcode(cbuf, Assembler::REX_R);
a61af66fc99e Initial load
duke
parents:
diff changeset
2295 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2296 emit_opcode(cbuf, Assembler::REX_RB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2297 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2298 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2299 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2300
a61af66fc99e Initial load
duke
parents:
diff changeset
2301 // for byte regs
a61af66fc99e Initial load
duke
parents:
diff changeset
2302 enc_class REX_breg_mem(rRegI reg, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
2303 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2304 if ($reg$$reg < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2305 if ($mem$$base < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2306 if ($mem$$index >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2307 emit_opcode(cbuf, Assembler::REX_X);
a61af66fc99e Initial load
duke
parents:
diff changeset
2308 } else if ($reg$$reg >= 4) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2309 emit_opcode(cbuf, Assembler::REX);
a61af66fc99e Initial load
duke
parents:
diff changeset
2310 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2311 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2312 if ($mem$$index < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2313 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2314 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2315 emit_opcode(cbuf, Assembler::REX_XB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2316 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2317 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2318 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2319 if ($mem$$base < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2320 if ($mem$$index < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2321 emit_opcode(cbuf, Assembler::REX_R);
a61af66fc99e Initial load
duke
parents:
diff changeset
2322 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2323 emit_opcode(cbuf, Assembler::REX_RX);
a61af66fc99e Initial load
duke
parents:
diff changeset
2324 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2325 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2326 if ($mem$$index < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2327 emit_opcode(cbuf, Assembler::REX_RB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2328 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2329 emit_opcode(cbuf, Assembler::REX_RXB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2330 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2331 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2332 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2333 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2334
a61af66fc99e Initial load
duke
parents:
diff changeset
2335 enc_class REX_reg(rRegI reg)
a61af66fc99e Initial load
duke
parents:
diff changeset
2336 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2337 if ($reg$$reg >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2338 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2339 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2340 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2341
a61af66fc99e Initial load
duke
parents:
diff changeset
2342 enc_class REX_reg_wide(rRegI reg)
a61af66fc99e Initial load
duke
parents:
diff changeset
2343 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2344 if ($reg$$reg < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2345 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
2346 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2347 emit_opcode(cbuf, Assembler::REX_WB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2348 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2349 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2350
a61af66fc99e Initial load
duke
parents:
diff changeset
2351 enc_class REX_reg_reg(rRegI dst, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2352 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2353 if ($dst$$reg < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2354 if ($src$$reg >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2355 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2356 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2357 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2358 if ($src$$reg < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2359 emit_opcode(cbuf, Assembler::REX_R);
a61af66fc99e Initial load
duke
parents:
diff changeset
2360 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2361 emit_opcode(cbuf, Assembler::REX_RB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2362 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2363 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2364 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2365
a61af66fc99e Initial load
duke
parents:
diff changeset
2366 enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2367 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2368 if ($dst$$reg < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2369 if ($src$$reg < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2370 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
2371 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2372 emit_opcode(cbuf, Assembler::REX_WB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2373 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2374 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2375 if ($src$$reg < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2376 emit_opcode(cbuf, Assembler::REX_WR);
a61af66fc99e Initial load
duke
parents:
diff changeset
2377 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2378 emit_opcode(cbuf, Assembler::REX_WRB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2379 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2380 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2381 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2382
a61af66fc99e Initial load
duke
parents:
diff changeset
2383 enc_class REX_reg_mem(rRegI reg, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
2384 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2385 if ($reg$$reg < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2386 if ($mem$$base < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2387 if ($mem$$index >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2388 emit_opcode(cbuf, Assembler::REX_X);
a61af66fc99e Initial load
duke
parents:
diff changeset
2389 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2390 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2391 if ($mem$$index < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2392 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2393 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2394 emit_opcode(cbuf, Assembler::REX_XB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2395 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2396 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2397 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2398 if ($mem$$base < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2399 if ($mem$$index < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2400 emit_opcode(cbuf, Assembler::REX_R);
a61af66fc99e Initial load
duke
parents:
diff changeset
2401 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2402 emit_opcode(cbuf, Assembler::REX_RX);
a61af66fc99e Initial load
duke
parents:
diff changeset
2403 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2404 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2405 if ($mem$$index < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2406 emit_opcode(cbuf, Assembler::REX_RB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2407 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2408 emit_opcode(cbuf, Assembler::REX_RXB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2409 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2410 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2411 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2412 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2413
a61af66fc99e Initial load
duke
parents:
diff changeset
2414 enc_class REX_reg_mem_wide(rRegL reg, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
2415 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2416 if ($reg$$reg < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2417 if ($mem$$base < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2418 if ($mem$$index < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2419 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
2420 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2421 emit_opcode(cbuf, Assembler::REX_WX);
a61af66fc99e Initial load
duke
parents:
diff changeset
2422 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2423 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2424 if ($mem$$index < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2425 emit_opcode(cbuf, Assembler::REX_WB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2426 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2427 emit_opcode(cbuf, Assembler::REX_WXB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2428 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2429 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2430 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2431 if ($mem$$base < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2432 if ($mem$$index < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2433 emit_opcode(cbuf, Assembler::REX_WR);
a61af66fc99e Initial load
duke
parents:
diff changeset
2434 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2435 emit_opcode(cbuf, Assembler::REX_WRX);
a61af66fc99e Initial load
duke
parents:
diff changeset
2436 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2437 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2438 if ($mem$$index < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2439 emit_opcode(cbuf, Assembler::REX_WRB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2440 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2441 emit_opcode(cbuf, Assembler::REX_WRXB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2442 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2443 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2444 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2445 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2446
a61af66fc99e Initial load
duke
parents:
diff changeset
2447 enc_class reg_mem(rRegI ereg, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
2448 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2449 // High registers handle in encode_RegMem
a61af66fc99e Initial load
duke
parents:
diff changeset
2450 int reg = $ereg$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2451 int base = $mem$$base;
a61af66fc99e Initial load
duke
parents:
diff changeset
2452 int index = $mem$$index;
a61af66fc99e Initial load
duke
parents:
diff changeset
2453 int scale = $mem$$scale;
a61af66fc99e Initial load
duke
parents:
diff changeset
2454 int disp = $mem$$disp;
a61af66fc99e Initial load
duke
parents:
diff changeset
2455 bool disp_is_oop = $mem->disp_is_oop();
a61af66fc99e Initial load
duke
parents:
diff changeset
2456
a61af66fc99e Initial load
duke
parents:
diff changeset
2457 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_is_oop);
a61af66fc99e Initial load
duke
parents:
diff changeset
2458 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2459
a61af66fc99e Initial load
duke
parents:
diff changeset
2460 enc_class RM_opc_mem(immI rm_opcode, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
2461 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2462 int rm_byte_opcode = $rm_opcode$$constant;
a61af66fc99e Initial load
duke
parents:
diff changeset
2463
a61af66fc99e Initial load
duke
parents:
diff changeset
2464 // High registers handle in encode_RegMem
a61af66fc99e Initial load
duke
parents:
diff changeset
2465 int base = $mem$$base;
a61af66fc99e Initial load
duke
parents:
diff changeset
2466 int index = $mem$$index;
a61af66fc99e Initial load
duke
parents:
diff changeset
2467 int scale = $mem$$scale;
a61af66fc99e Initial load
duke
parents:
diff changeset
2468 int displace = $mem$$disp;
a61af66fc99e Initial load
duke
parents:
diff changeset
2469
a61af66fc99e Initial load
duke
parents:
diff changeset
2470 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when
a61af66fc99e Initial load
duke
parents:
diff changeset
2471 // working with static
a61af66fc99e Initial load
duke
parents:
diff changeset
2472 // globals
a61af66fc99e Initial load
duke
parents:
diff changeset
2473 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
a61af66fc99e Initial load
duke
parents:
diff changeset
2474 disp_is_oop);
a61af66fc99e Initial load
duke
parents:
diff changeset
2475 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2476
a61af66fc99e Initial load
duke
parents:
diff changeset
2477 enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
a61af66fc99e Initial load
duke
parents:
diff changeset
2478 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2479 int reg_encoding = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2480 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
a61af66fc99e Initial load
duke
parents:
diff changeset
2481 int index = 0x04; // 0x04 indicates no index
a61af66fc99e Initial load
duke
parents:
diff changeset
2482 int scale = 0x00; // 0x00 indicates no scale
a61af66fc99e Initial load
duke
parents:
diff changeset
2483 int displace = $src1$$constant; // 0x00 indicates no displacement
a61af66fc99e Initial load
duke
parents:
diff changeset
2484 bool disp_is_oop = false;
a61af66fc99e Initial load
duke
parents:
diff changeset
2485 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
a61af66fc99e Initial load
duke
parents:
diff changeset
2486 disp_is_oop);
a61af66fc99e Initial load
duke
parents:
diff changeset
2487 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2488
a61af66fc99e Initial load
duke
parents:
diff changeset
2489 enc_class neg_reg(rRegI dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
2490 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2491 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2492 if (dstenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2493 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2494 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
2495 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2496 // NEG $dst
a61af66fc99e Initial load
duke
parents:
diff changeset
2497 emit_opcode(cbuf, 0xF7);
a61af66fc99e Initial load
duke
parents:
diff changeset
2498 emit_rm(cbuf, 0x3, 0x03, dstenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
2499 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2500
a61af66fc99e Initial load
duke
parents:
diff changeset
2501 enc_class neg_reg_wide(rRegI dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
2502 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2503 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2504 if (dstenc < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2505 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
2506 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2507 emit_opcode(cbuf, Assembler::REX_WB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2508 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
2509 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2510 // NEG $dst
a61af66fc99e Initial load
duke
parents:
diff changeset
2511 emit_opcode(cbuf, 0xF7);
a61af66fc99e Initial load
duke
parents:
diff changeset
2512 emit_rm(cbuf, 0x3, 0x03, dstenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
2513 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2514
a61af66fc99e Initial load
duke
parents:
diff changeset
2515 enc_class setLT_reg(rRegI dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
2516 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2517 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2518 if (dstenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2519 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2520 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
2521 } else if (dstenc >= 4) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2522 emit_opcode(cbuf, Assembler::REX);
a61af66fc99e Initial load
duke
parents:
diff changeset
2523 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2524 // SETLT $dst
a61af66fc99e Initial load
duke
parents:
diff changeset
2525 emit_opcode(cbuf, 0x0F);
a61af66fc99e Initial load
duke
parents:
diff changeset
2526 emit_opcode(cbuf, 0x9C);
a61af66fc99e Initial load
duke
parents:
diff changeset
2527 emit_rm(cbuf, 0x3, 0x0, dstenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
2528 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2529
a61af66fc99e Initial load
duke
parents:
diff changeset
2530 enc_class setNZ_reg(rRegI dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
2531 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2532 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2533 if (dstenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2534 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2535 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
2536 } else if (dstenc >= 4) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2537 emit_opcode(cbuf, Assembler::REX);
a61af66fc99e Initial load
duke
parents:
diff changeset
2538 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2539 // SETNZ $dst
a61af66fc99e Initial load
duke
parents:
diff changeset
2540 emit_opcode(cbuf, 0x0F);
a61af66fc99e Initial load
duke
parents:
diff changeset
2541 emit_opcode(cbuf, 0x95);
a61af66fc99e Initial load
duke
parents:
diff changeset
2542 emit_rm(cbuf, 0x3, 0x0, dstenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
2543 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2544
a61af66fc99e Initial load
duke
parents:
diff changeset
2545
a61af66fc99e Initial load
duke
parents:
diff changeset
2546 // Compare the lonogs and set -1, 0, or 1 into dst
a61af66fc99e Initial load
duke
parents:
diff changeset
2547 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
2548 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2549 int src1enc = $src1$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2550 int src2enc = $src2$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2551 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2552
a61af66fc99e Initial load
duke
parents:
diff changeset
2553 // cmpq $src1, $src2
a61af66fc99e Initial load
duke
parents:
diff changeset
2554 if (src1enc < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2555 if (src2enc < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2556 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
2557 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2558 emit_opcode(cbuf, Assembler::REX_WB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2559 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2560 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2561 if (src2enc < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2562 emit_opcode(cbuf, Assembler::REX_WR);
a61af66fc99e Initial load
duke
parents:
diff changeset
2563 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2564 emit_opcode(cbuf, Assembler::REX_WRB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2565 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2566 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2567 emit_opcode(cbuf, 0x3B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2568 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
a61af66fc99e Initial load
duke
parents:
diff changeset
2569
a61af66fc99e Initial load
duke
parents:
diff changeset
2570 // movl $dst, -1
a61af66fc99e Initial load
duke
parents:
diff changeset
2571 if (dstenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2572 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2573 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2574 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
a61af66fc99e Initial load
duke
parents:
diff changeset
2575 emit_d32(cbuf, -1);
a61af66fc99e Initial load
duke
parents:
diff changeset
2576
a61af66fc99e Initial load
duke
parents:
diff changeset
2577 // jl,s done
a61af66fc99e Initial load
duke
parents:
diff changeset
2578 emit_opcode(cbuf, 0x7C);
a61af66fc99e Initial load
duke
parents:
diff changeset
2579 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
a61af66fc99e Initial load
duke
parents:
diff changeset
2580
a61af66fc99e Initial load
duke
parents:
diff changeset
2581 // setne $dst
a61af66fc99e Initial load
duke
parents:
diff changeset
2582 if (dstenc >= 4) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2583 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2584 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2585 emit_opcode(cbuf, 0x0F);
a61af66fc99e Initial load
duke
parents:
diff changeset
2586 emit_opcode(cbuf, 0x95);
a61af66fc99e Initial load
duke
parents:
diff changeset
2587 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
a61af66fc99e Initial load
duke
parents:
diff changeset
2588
a61af66fc99e Initial load
duke
parents:
diff changeset
2589 // movzbl $dst, $dst
a61af66fc99e Initial load
duke
parents:
diff changeset
2590 if (dstenc >= 4) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2591 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2592 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2593 emit_opcode(cbuf, 0x0F);
a61af66fc99e Initial load
duke
parents:
diff changeset
2594 emit_opcode(cbuf, 0xB6);
a61af66fc99e Initial load
duke
parents:
diff changeset
2595 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
a61af66fc99e Initial load
duke
parents:
diff changeset
2596 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2597
a61af66fc99e Initial load
duke
parents:
diff changeset
2598 enc_class Push_ResultXD(regD dst) %{
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
2599 MacroAssembler _masm(&cbuf);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
2600 __ fstp_d(Address(rsp, 0));
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
2601 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
2602 __ addptr(rsp, 8);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2603 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2604
a61af66fc99e Initial load
duke
parents:
diff changeset
2605 enc_class Push_SrcXD(regD src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2606 MacroAssembler _masm(&cbuf);
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
2607 __ subptr(rsp, 8);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
2608 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
2609 __ fld_d(Address(rsp, 0));
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
2610 %}
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
2611
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2612
a61af66fc99e Initial load
duke
parents:
diff changeset
2613 // obj: object to lock
a61af66fc99e Initial load
duke
parents:
diff changeset
2614 // box: box address (header location) -- killed
a61af66fc99e Initial load
duke
parents:
diff changeset
2615 // tmp: rax -- killed
a61af66fc99e Initial load
duke
parents:
diff changeset
2616 // scr: rbx -- killed
a61af66fc99e Initial load
duke
parents:
diff changeset
2617 //
a61af66fc99e Initial load
duke
parents:
diff changeset
2618 // What follows is a direct transliteration of fast_lock() and fast_unlock()
a61af66fc99e Initial load
duke
parents:
diff changeset
2619 // from i486.ad. See that file for comments.
a61af66fc99e Initial load
duke
parents:
diff changeset
2620 // TODO: where possible switch from movq (r, 0) to movl(r,0) and
a61af66fc99e Initial load
duke
parents:
diff changeset
2621 // use the shorter encoding. (Movl clears the high-order 32-bits).
a61af66fc99e Initial load
duke
parents:
diff changeset
2622
a61af66fc99e Initial load
duke
parents:
diff changeset
2623
a61af66fc99e Initial load
duke
parents:
diff changeset
2624 enc_class Fast_Lock(rRegP obj, rRegP box, rax_RegI tmp, rRegP scr)
a61af66fc99e Initial load
duke
parents:
diff changeset
2625 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2626 Register objReg = as_Register((int)$obj$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2627 Register boxReg = as_Register((int)$box$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2628 Register tmpReg = as_Register($tmp$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2629 Register scrReg = as_Register($scr$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2630 MacroAssembler masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2631
a61af66fc99e Initial load
duke
parents:
diff changeset
2632 // Verify uniqueness of register assignments -- necessary but not sufficient
a61af66fc99e Initial load
duke
parents:
diff changeset
2633 assert (objReg != boxReg && objReg != tmpReg &&
a61af66fc99e Initial load
duke
parents:
diff changeset
2634 objReg != scrReg && tmpReg != scrReg, "invariant") ;
a61af66fc99e Initial load
duke
parents:
diff changeset
2635
a61af66fc99e Initial load
duke
parents:
diff changeset
2636 if (_counters != NULL) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2637 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
a61af66fc99e Initial load
duke
parents:
diff changeset
2638 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2639 if (EmitSync & 1) {
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2640 // Without cast to int32_t a movptr will destroy r10 which is typically obj
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2641 masm.movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2642 masm.cmpptr(rsp, (int32_t)NULL_WORD) ;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2643 } else
a61af66fc99e Initial load
duke
parents:
diff changeset
2644 if (EmitSync & 2) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2645 Label DONE_LABEL;
a61af66fc99e Initial load
duke
parents:
diff changeset
2646 if (UseBiasedLocking) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2647 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
a61af66fc99e Initial load
duke
parents:
diff changeset
2648 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
a61af66fc99e Initial load
duke
parents:
diff changeset
2649 }
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2650 // QQQ was movl...
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2651 masm.movptr(tmpReg, 0x1);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2652 masm.orptr(tmpReg, Address(objReg, 0));
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2653 masm.movptr(Address(boxReg, 0), tmpReg);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2654 if (os::is_MP()) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2655 masm.lock();
a61af66fc99e Initial load
duke
parents:
diff changeset
2656 }
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2657 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2658 masm.jcc(Assembler::equal, DONE_LABEL);
a61af66fc99e Initial load
duke
parents:
diff changeset
2659
a61af66fc99e Initial load
duke
parents:
diff changeset
2660 // Recursive locking
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2661 masm.subptr(tmpReg, rsp);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2662 masm.andptr(tmpReg, 7 - os::vm_page_size());
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2663 masm.movptr(Address(boxReg, 0), tmpReg);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2664
a61af66fc99e Initial load
duke
parents:
diff changeset
2665 masm.bind(DONE_LABEL);
a61af66fc99e Initial load
duke
parents:
diff changeset
2666 masm.nop(); // avoid branch to branch
a61af66fc99e Initial load
duke
parents:
diff changeset
2667 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2668 Label DONE_LABEL, IsInflated, Egress;
a61af66fc99e Initial load
duke
parents:
diff changeset
2669
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2670 masm.movptr(tmpReg, Address(objReg, 0)) ;
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2671 masm.testl (tmpReg, 0x02) ; // inflated vs stack-locked|neutral|biased
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2672 masm.jcc (Assembler::notZero, IsInflated) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2673
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2674 // it's stack-locked, biased or neutral
a61af66fc99e Initial load
duke
parents:
diff changeset
2675 // TODO: optimize markword triage order to reduce the number of
a61af66fc99e Initial load
duke
parents:
diff changeset
2676 // conditional branches in the most common cases.
a61af66fc99e Initial load
duke
parents:
diff changeset
2677 // Beware -- there's a subtle invariant that fetch of the markword
a61af66fc99e Initial load
duke
parents:
diff changeset
2678 // at [FETCH], below, will never observe a biased encoding (*101b).
a61af66fc99e Initial load
duke
parents:
diff changeset
2679 // If this invariant is not held we'll suffer exclusion (safety) failure.
a61af66fc99e Initial load
duke
parents:
diff changeset
2680
420
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
2681 if (UseBiasedLocking && !UseOptoBiasInlining) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2682 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, true, DONE_LABEL, NULL, _counters);
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2683 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2684 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2685
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2686 // was q will it destroy high?
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2687 masm.orl (tmpReg, 1) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2688 masm.movptr(Address(boxReg, 0), tmpReg) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2689 if (os::is_MP()) { masm.lock(); }
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2690 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2691 if (_counters != NULL) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2692 masm.cond_inc32(Assembler::equal,
a61af66fc99e Initial load
duke
parents:
diff changeset
2693 ExternalAddress((address) _counters->fast_path_entry_count_addr()));
a61af66fc99e Initial load
duke
parents:
diff changeset
2694 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2695 masm.jcc (Assembler::equal, DONE_LABEL);
a61af66fc99e Initial load
duke
parents:
diff changeset
2696
a61af66fc99e Initial load
duke
parents:
diff changeset
2697 // Recursive locking
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2698 masm.subptr(tmpReg, rsp);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2699 masm.andptr(tmpReg, 7 - os::vm_page_size());
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2700 masm.movptr(Address(boxReg, 0), tmpReg);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2701 if (_counters != NULL) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2702 masm.cond_inc32(Assembler::equal,
a61af66fc99e Initial load
duke
parents:
diff changeset
2703 ExternalAddress((address) _counters->fast_path_entry_count_addr()));
a61af66fc99e Initial load
duke
parents:
diff changeset
2704 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2705 masm.jmp (DONE_LABEL) ;
a61af66fc99e Initial load
duke
parents:
diff changeset
2706
a61af66fc99e Initial load
duke
parents:
diff changeset
2707 masm.bind (IsInflated) ;
a61af66fc99e Initial load
duke
parents:
diff changeset
2708 // It's inflated
a61af66fc99e Initial load
duke
parents:
diff changeset
2709
a61af66fc99e Initial load
duke
parents:
diff changeset
2710 // TODO: someday avoid the ST-before-CAS penalty by
a61af66fc99e Initial load
duke
parents:
diff changeset
2711 // relocating (deferring) the following ST.
a61af66fc99e Initial load
duke
parents:
diff changeset
2712 // We should also think about trying a CAS without having
a61af66fc99e Initial load
duke
parents:
diff changeset
2713 // fetched _owner. If the CAS is successful we may
a61af66fc99e Initial load
duke
parents:
diff changeset
2714 // avoid an RTO->RTS upgrade on the $line.
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2715 // Without cast to int32_t a movptr will destroy r10 which is typically obj
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2716 masm.movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2717
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2718 masm.mov (boxReg, tmpReg) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2719 masm.movptr (tmpReg, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2720 masm.testptr(tmpReg, tmpReg) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2721 masm.jcc (Assembler::notZero, DONE_LABEL) ;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2722
a61af66fc99e Initial load
duke
parents:
diff changeset
2723 // It's inflated and appears unlocked
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2724 if (os::is_MP()) { masm.lock(); }
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2725 masm.cmpxchgptr(r15_thread, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2726 // Intentional fall-through into DONE_LABEL ...
a61af66fc99e Initial load
duke
parents:
diff changeset
2727
a61af66fc99e Initial load
duke
parents:
diff changeset
2728 masm.bind (DONE_LABEL) ;
a61af66fc99e Initial load
duke
parents:
diff changeset
2729 masm.nop () ; // avoid jmp to jmp
a61af66fc99e Initial load
duke
parents:
diff changeset
2730 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2731 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2732
a61af66fc99e Initial load
duke
parents:
diff changeset
2733 // obj: object to unlock
a61af66fc99e Initial load
duke
parents:
diff changeset
2734 // box: box address (displaced header location), killed
a61af66fc99e Initial load
duke
parents:
diff changeset
2735 // RBX: killed tmp; cannot be obj nor box
a61af66fc99e Initial load
duke
parents:
diff changeset
2736 enc_class Fast_Unlock(rRegP obj, rax_RegP box, rRegP tmp)
a61af66fc99e Initial load
duke
parents:
diff changeset
2737 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2738
a61af66fc99e Initial load
duke
parents:
diff changeset
2739 Register objReg = as_Register($obj$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2740 Register boxReg = as_Register($box$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2741 Register tmpReg = as_Register($tmp$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2742 MacroAssembler masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2743
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2744 if (EmitSync & 4) {
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2745 masm.cmpptr(rsp, 0) ;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2746 } else
a61af66fc99e Initial load
duke
parents:
diff changeset
2747 if (EmitSync & 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2748 Label DONE_LABEL;
a61af66fc99e Initial load
duke
parents:
diff changeset
2749 if (UseBiasedLocking) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2750 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
a61af66fc99e Initial load
duke
parents:
diff changeset
2751 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2752
a61af66fc99e Initial load
duke
parents:
diff changeset
2753 // Check whether the displaced header is 0
a61af66fc99e Initial load
duke
parents:
diff changeset
2754 //(=> recursive unlock)
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2755 masm.movptr(tmpReg, Address(boxReg, 0));
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2756 masm.testptr(tmpReg, tmpReg);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2757 masm.jcc(Assembler::zero, DONE_LABEL);
a61af66fc99e Initial load
duke
parents:
diff changeset
2758
a61af66fc99e Initial load
duke
parents:
diff changeset
2759 // If not recursive lock, reset the header to displaced header
a61af66fc99e Initial load
duke
parents:
diff changeset
2760 if (os::is_MP()) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2761 masm.lock();
a61af66fc99e Initial load
duke
parents:
diff changeset
2762 }
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2763 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2764 masm.bind(DONE_LABEL);
a61af66fc99e Initial load
duke
parents:
diff changeset
2765 masm.nop(); // avoid branch to branch
a61af66fc99e Initial load
duke
parents:
diff changeset
2766 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2767 Label DONE_LABEL, Stacked, CheckSucc ;
a61af66fc99e Initial load
duke
parents:
diff changeset
2768
420
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
2769 if (UseBiasedLocking && !UseOptoBiasInlining) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2770 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
a61af66fc99e Initial load
duke
parents:
diff changeset
2771 }
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2772
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2773 masm.movptr(tmpReg, Address(objReg, 0)) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2774 masm.cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2775 masm.jcc (Assembler::zero, DONE_LABEL) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2776 masm.testl (tmpReg, 0x02) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2777 masm.jcc (Assembler::zero, Stacked) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2778
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2779 // It's inflated
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2780 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2781 masm.xorptr(boxReg, r15_thread) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2782 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2783 masm.jcc (Assembler::notZero, DONE_LABEL) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2784 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2785 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2786 masm.jcc (Assembler::notZero, CheckSucc) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2787 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2788 masm.jmp (DONE_LABEL) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2789
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2790 if ((EmitSync & 65536) == 0) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2791 Label LSuccess, LGoSlowPath ;
a61af66fc99e Initial load
duke
parents:
diff changeset
2792 masm.bind (CheckSucc) ;
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2793 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2794 masm.jcc (Assembler::zero, LGoSlowPath) ;
a61af66fc99e Initial load
duke
parents:
diff changeset
2795
a61af66fc99e Initial load
duke
parents:
diff changeset
2796 // I'd much rather use lock:andl m->_owner, 0 as it's faster than the
a61af66fc99e Initial load
duke
parents:
diff changeset
2797 // the explicit ST;MEMBAR combination, but masm doesn't currently support
a61af66fc99e Initial load
duke
parents:
diff changeset
2798 // "ANDQ M,IMM". Don't use MFENCE here. lock:add to TOS, xchg, etc
a61af66fc99e Initial load
duke
parents:
diff changeset
2799 // are all faster when the write buffer is populated.
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2800 masm.movptr (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2801 if (os::is_MP()) {
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2802 masm.lock () ; masm.addl (Address(rsp, 0), 0) ;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2803 }
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2804 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2805 masm.jcc (Assembler::notZero, LSuccess) ;
a61af66fc99e Initial load
duke
parents:
diff changeset
2806
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2807 masm.movptr (boxReg, (int32_t)NULL_WORD) ; // box is really EAX
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2808 if (os::is_MP()) { masm.lock(); }
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2809 masm.cmpxchgptr(r15_thread, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2810 masm.jcc (Assembler::notEqual, LSuccess) ;
a61af66fc99e Initial load
duke
parents:
diff changeset
2811 // Intentional fall-through into slow-path
a61af66fc99e Initial load
duke
parents:
diff changeset
2812
a61af66fc99e Initial load
duke
parents:
diff changeset
2813 masm.bind (LGoSlowPath) ;
a61af66fc99e Initial load
duke
parents:
diff changeset
2814 masm.orl (boxReg, 1) ; // set ICC.ZF=0 to indicate failure
a61af66fc99e Initial load
duke
parents:
diff changeset
2815 masm.jmp (DONE_LABEL) ;
a61af66fc99e Initial load
duke
parents:
diff changeset
2816
a61af66fc99e Initial load
duke
parents:
diff changeset
2817 masm.bind (LSuccess) ;
a61af66fc99e Initial load
duke
parents:
diff changeset
2818 masm.testl (boxReg, 0) ; // set ICC.ZF=1 to indicate success
a61af66fc99e Initial load
duke
parents:
diff changeset
2819 masm.jmp (DONE_LABEL) ;
a61af66fc99e Initial load
duke
parents:
diff changeset
2820 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2821
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2822 masm.bind (Stacked) ;
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2823 masm.movptr(tmpReg, Address (boxReg, 0)) ; // re-fetch
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2824 if (os::is_MP()) { masm.lock(); }
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2825 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2826
a61af66fc99e Initial load
duke
parents:
diff changeset
2827 if (EmitSync & 65536) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2828 masm.bind (CheckSucc) ;
a61af66fc99e Initial load
duke
parents:
diff changeset
2829 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2830 masm.bind(DONE_LABEL);
a61af66fc99e Initial load
duke
parents:
diff changeset
2831 if (EmitSync & 32768) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2832 masm.nop(); // avoid branch to branch
a61af66fc99e Initial load
duke
parents:
diff changeset
2833 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2834 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2835 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2836
169
9148c65abefc 6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents: 168
diff changeset
2837
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2838 enc_class enc_rethrow()
a61af66fc99e Initial load
duke
parents:
diff changeset
2839 %{
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
2840 cbuf.set_insts_mark();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2841 emit_opcode(cbuf, 0xE9); // jmp entry
a61af66fc99e Initial load
duke
parents:
diff changeset
2842 emit_d32_reloc(cbuf,
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
2843 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2844 runtime_call_Relocation::spec(),
a61af66fc99e Initial load
duke
parents:
diff changeset
2845 RELOC_DISP32);
a61af66fc99e Initial load
duke
parents:
diff changeset
2846 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2847
a61af66fc99e Initial load
duke
parents:
diff changeset
2848 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2849
a61af66fc99e Initial load
duke
parents:
diff changeset
2850
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
2851
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2852 //----------FRAME--------------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
2853 // Definition of frame structure and management information.
a61af66fc99e Initial load
duke
parents:
diff changeset
2854 //
a61af66fc99e Initial load
duke
parents:
diff changeset
2855 // S T A C K L A Y O U T Allocators stack-slot number
a61af66fc99e Initial load
duke
parents:
diff changeset
2856 // | (to get allocators register number
a61af66fc99e Initial load
duke
parents:
diff changeset
2857 // G Owned by | | v add OptoReg::stack0())
a61af66fc99e Initial load
duke
parents:
diff changeset
2858 // r CALLER | |
a61af66fc99e Initial load
duke
parents:
diff changeset
2859 // o | +--------+ pad to even-align allocators stack-slot
a61af66fc99e Initial load
duke
parents:
diff changeset
2860 // w V | pad0 | numbers; owned by CALLER
a61af66fc99e Initial load
duke
parents:
diff changeset
2861 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
a61af66fc99e Initial load
duke
parents:
diff changeset
2862 // h ^ | in | 5
a61af66fc99e Initial load
duke
parents:
diff changeset
2863 // | | args | 4 Holes in incoming args owned by SELF
a61af66fc99e Initial load
duke
parents:
diff changeset
2864 // | | | | 3
a61af66fc99e Initial load
duke
parents:
diff changeset
2865 // | | +--------+
a61af66fc99e Initial load
duke
parents:
diff changeset
2866 // V | | old out| Empty on Intel, window on Sparc
a61af66fc99e Initial load
duke
parents:
diff changeset
2867 // | old |preserve| Must be even aligned.
a61af66fc99e Initial load
duke
parents:
diff changeset
2868 // | SP-+--------+----> Matcher::_old_SP, even aligned
a61af66fc99e Initial load
duke
parents:
diff changeset
2869 // | | in | 3 area for Intel ret address
a61af66fc99e Initial load
duke
parents:
diff changeset
2870 // Owned by |preserve| Empty on Sparc.
a61af66fc99e Initial load
duke
parents:
diff changeset
2871 // SELF +--------+
a61af66fc99e Initial load
duke
parents:
diff changeset
2872 // | | pad2 | 2 pad to align old SP
a61af66fc99e Initial load
duke
parents:
diff changeset
2873 // | +--------+ 1
a61af66fc99e Initial load
duke
parents:
diff changeset
2874 // | | locks | 0
a61af66fc99e Initial load
duke
parents:
diff changeset
2875 // | +--------+----> OptoReg::stack0(), even aligned
a61af66fc99e Initial load
duke
parents:
diff changeset
2876 // | | pad1 | 11 pad to align new SP
a61af66fc99e Initial load
duke
parents:
diff changeset
2877 // | +--------+
a61af66fc99e Initial load
duke
parents:
diff changeset
2878 // | | | 10
a61af66fc99e Initial load
duke
parents:
diff changeset
2879 // | | spills | 9 spills
a61af66fc99e Initial load
duke
parents:
diff changeset
2880 // V | | 8 (pad0 slot for callee)
a61af66fc99e Initial load
duke
parents:
diff changeset
2881 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
a61af66fc99e Initial load
duke
parents:
diff changeset
2882 // ^ | out | 7
a61af66fc99e Initial load
duke
parents:
diff changeset
2883 // | | args | 6 Holes in outgoing args owned by CALLEE
a61af66fc99e Initial load
duke
parents:
diff changeset
2884 // Owned by +--------+
a61af66fc99e Initial load
duke
parents:
diff changeset
2885 // CALLEE | new out| 6 Empty on Intel, window on Sparc
a61af66fc99e Initial load
duke
parents:
diff changeset
2886 // | new |preserve| Must be even-aligned.
a61af66fc99e Initial load
duke
parents:
diff changeset
2887 // | SP-+--------+----> Matcher::_new_SP, even aligned
a61af66fc99e Initial load
duke
parents:
diff changeset
2888 // | | |
a61af66fc99e Initial load
duke
parents:
diff changeset
2889 //
a61af66fc99e Initial load
duke
parents:
diff changeset
2890 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
a61af66fc99e Initial load
duke
parents:
diff changeset
2891 // known from SELF's arguments and the Java calling convention.
a61af66fc99e Initial load
duke
parents:
diff changeset
2892 // Region 6-7 is determined per call site.
a61af66fc99e Initial load
duke
parents:
diff changeset
2893 // Note 2: If the calling convention leaves holes in the incoming argument
a61af66fc99e Initial load
duke
parents:
diff changeset
2894 // area, those holes are owned by SELF. Holes in the outgoing area
a61af66fc99e Initial load
duke
parents:
diff changeset
2895 // are owned by the CALLEE. Holes should not be nessecary in the
a61af66fc99e Initial load
duke
parents:
diff changeset
2896 // incoming area, as the Java calling convention is completely under
a61af66fc99e Initial load
duke
parents:
diff changeset
2897 // the control of the AD file. Doubles can be sorted and packed to
a61af66fc99e Initial load
duke
parents:
diff changeset
2898 // avoid holes. Holes in the outgoing arguments may be nessecary for
a61af66fc99e Initial load
duke
parents:
diff changeset
2899 // varargs C calling conventions.
a61af66fc99e Initial load
duke
parents:
diff changeset
2900 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
a61af66fc99e Initial load
duke
parents:
diff changeset
2901 // even aligned with pad0 as needed.
a61af66fc99e Initial load
duke
parents:
diff changeset
2902 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
a61af66fc99e Initial load
duke
parents:
diff changeset
2903 // region 6-11 is even aligned; it may be padded out more so that
a61af66fc99e Initial load
duke
parents:
diff changeset
2904 // the region from SP to FP meets the minimum stack alignment.
a61af66fc99e Initial load
duke
parents:
diff changeset
2905 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
a61af66fc99e Initial load
duke
parents:
diff changeset
2906 // alignment. Region 11, pad1, may be dynamically extended so that
a61af66fc99e Initial load
duke
parents:
diff changeset
2907 // SP meets the minimum alignment.
a61af66fc99e Initial load
duke
parents:
diff changeset
2908
a61af66fc99e Initial load
duke
parents:
diff changeset
2909 frame
a61af66fc99e Initial load
duke
parents:
diff changeset
2910 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2911 // What direction does stack grow in (assumed to be same for C & Java)
a61af66fc99e Initial load
duke
parents:
diff changeset
2912 stack_direction(TOWARDS_LOW);
a61af66fc99e Initial load
duke
parents:
diff changeset
2913
a61af66fc99e Initial load
duke
parents:
diff changeset
2914 // These three registers define part of the calling convention
a61af66fc99e Initial load
duke
parents:
diff changeset
2915 // between compiled code and the interpreter.
a61af66fc99e Initial load
duke
parents:
diff changeset
2916 inline_cache_reg(RAX); // Inline Cache Register
a61af66fc99e Initial load
duke
parents:
diff changeset
2917 interpreter_method_oop_reg(RBX); // Method Oop Register when
a61af66fc99e Initial load
duke
parents:
diff changeset
2918 // calling interpreter
a61af66fc99e Initial load
duke
parents:
diff changeset
2919
a61af66fc99e Initial load
duke
parents:
diff changeset
2920 // Optional: name the operand used by cisc-spilling to access
a61af66fc99e Initial load
duke
parents:
diff changeset
2921 // [stack_pointer + offset]
a61af66fc99e Initial load
duke
parents:
diff changeset
2922 cisc_spilling_operand_name(indOffset32);
a61af66fc99e Initial load
duke
parents:
diff changeset
2923
a61af66fc99e Initial load
duke
parents:
diff changeset
2924 // Number of stack slots consumed by locking an object
a61af66fc99e Initial load
duke
parents:
diff changeset
2925 sync_stack_slots(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
2926
a61af66fc99e Initial load
duke
parents:
diff changeset
2927 // Compiled code's Frame Pointer
a61af66fc99e Initial load
duke
parents:
diff changeset
2928 frame_pointer(RSP);
a61af66fc99e Initial load
duke
parents:
diff changeset
2929
a61af66fc99e Initial load
duke
parents:
diff changeset
2930 // Interpreter stores its frame pointer in a register which is
a61af66fc99e Initial load
duke
parents:
diff changeset
2931 // stored to the stack by I2CAdaptors.
a61af66fc99e Initial load
duke
parents:
diff changeset
2932 // I2CAdaptors convert from interpreted java to compiled java.
a61af66fc99e Initial load
duke
parents:
diff changeset
2933 interpreter_frame_pointer(RBP);
a61af66fc99e Initial load
duke
parents:
diff changeset
2934
a61af66fc99e Initial load
duke
parents:
diff changeset
2935 // Stack alignment requirement
a61af66fc99e Initial load
duke
parents:
diff changeset
2936 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
a61af66fc99e Initial load
duke
parents:
diff changeset
2937
a61af66fc99e Initial load
duke
parents:
diff changeset
2938 // Number of stack slots between incoming argument block and the start of
a61af66fc99e Initial load
duke
parents:
diff changeset
2939 // a new frame. The PROLOG must add this many slots to the stack. The
a61af66fc99e Initial load
duke
parents:
diff changeset
2940 // EPILOG must remove this many slots. amd64 needs two slots for
a61af66fc99e Initial load
duke
parents:
diff changeset
2941 // return address.
a61af66fc99e Initial load
duke
parents:
diff changeset
2942 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls);
a61af66fc99e Initial load
duke
parents:
diff changeset
2943
a61af66fc99e Initial load
duke
parents:
diff changeset
2944 // Number of outgoing stack slots killed above the out_preserve_stack_slots
a61af66fc99e Initial load
duke
parents:
diff changeset
2945 // for calls to C. Supports the var-args backing area for register parms.
a61af66fc99e Initial load
duke
parents:
diff changeset
2946 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
a61af66fc99e Initial load
duke
parents:
diff changeset
2947
a61af66fc99e Initial load
duke
parents:
diff changeset
2948 // The after-PROLOG location of the return address. Location of
a61af66fc99e Initial load
duke
parents:
diff changeset
2949 // return address specifies a type (REG or STACK) and a number
a61af66fc99e Initial load
duke
parents:
diff changeset
2950 // representing the register number (i.e. - use a register name) or
a61af66fc99e Initial load
duke
parents:
diff changeset
2951 // stack slot.
a61af66fc99e Initial load
duke
parents:
diff changeset
2952 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
a61af66fc99e Initial load
duke
parents:
diff changeset
2953 // Otherwise, it is above the locks and verification slot and alignment word
a61af66fc99e Initial load
duke
parents:
diff changeset
2954 return_addr(STACK - 2 +
4950
9b8ce46870df 7145346: VerifyStackAtCalls is broken
kvn
parents: 4947
diff changeset
2955 round_to((Compile::current()->in_preserve_stack_slots() +
9b8ce46870df 7145346: VerifyStackAtCalls is broken
kvn
parents: 4947
diff changeset
2956 Compile::current()->fixed_slots()),
9b8ce46870df 7145346: VerifyStackAtCalls is broken
kvn
parents: 4947
diff changeset
2957 stack_alignment_in_slots()));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2958
a61af66fc99e Initial load
duke
parents:
diff changeset
2959 // Body of function which returns an integer array locating
a61af66fc99e Initial load
duke
parents:
diff changeset
2960 // arguments either in registers or in stack slots. Passed an array
a61af66fc99e Initial load
duke
parents:
diff changeset
2961 // of ideal registers called "sig" and a "length" count. Stack-slot
a61af66fc99e Initial load
duke
parents:
diff changeset
2962 // offsets are based on outgoing arguments, i.e. a CALLER setting up
a61af66fc99e Initial load
duke
parents:
diff changeset
2963 // arguments for a CALLEE. Incoming stack arguments are
a61af66fc99e Initial load
duke
parents:
diff changeset
2964 // automatically biased by the preserve_stack_slots field above.
a61af66fc99e Initial load
duke
parents:
diff changeset
2965
a61af66fc99e Initial load
duke
parents:
diff changeset
2966 calling_convention
a61af66fc99e Initial load
duke
parents:
diff changeset
2967 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2968 // No difference between ingoing/outgoing just pass false
a61af66fc99e Initial load
duke
parents:
diff changeset
2969 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
a61af66fc99e Initial load
duke
parents:
diff changeset
2970 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2971
a61af66fc99e Initial load
duke
parents:
diff changeset
2972 c_calling_convention
a61af66fc99e Initial load
duke
parents:
diff changeset
2973 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2974 // This is obviously always outgoing
a61af66fc99e Initial load
duke
parents:
diff changeset
2975 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
a61af66fc99e Initial load
duke
parents:
diff changeset
2976 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2977
a61af66fc99e Initial load
duke
parents:
diff changeset
2978 // Location of compiled Java return values. Same as C for now.
a61af66fc99e Initial load
duke
parents:
diff changeset
2979 return_value
a61af66fc99e Initial load
duke
parents:
diff changeset
2980 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2981 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
a61af66fc99e Initial load
duke
parents:
diff changeset
2982 "only return normal values");
a61af66fc99e Initial load
duke
parents:
diff changeset
2983
a61af66fc99e Initial load
duke
parents:
diff changeset
2984 static const int lo[Op_RegL + 1] = {
a61af66fc99e Initial load
duke
parents:
diff changeset
2985 0,
a61af66fc99e Initial load
duke
parents:
diff changeset
2986 0,
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
2987 RAX_num, // Op_RegN
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2988 RAX_num, // Op_RegI
a61af66fc99e Initial load
duke
parents:
diff changeset
2989 RAX_num, // Op_RegP
a61af66fc99e Initial load
duke
parents:
diff changeset
2990 XMM0_num, // Op_RegF
a61af66fc99e Initial load
duke
parents:
diff changeset
2991 XMM0_num, // Op_RegD
a61af66fc99e Initial load
duke
parents:
diff changeset
2992 RAX_num // Op_RegL
a61af66fc99e Initial load
duke
parents:
diff changeset
2993 };
a61af66fc99e Initial load
duke
parents:
diff changeset
2994 static const int hi[Op_RegL + 1] = {
a61af66fc99e Initial load
duke
parents:
diff changeset
2995 0,
a61af66fc99e Initial load
duke
parents:
diff changeset
2996 0,
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
2997 OptoReg::Bad, // Op_RegN
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2998 OptoReg::Bad, // Op_RegI
a61af66fc99e Initial load
duke
parents:
diff changeset
2999 RAX_H_num, // Op_RegP
a61af66fc99e Initial load
duke
parents:
diff changeset
3000 OptoReg::Bad, // Op_RegF
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
3001 XMM0b_num, // Op_RegD
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3002 RAX_H_num // Op_RegL
a61af66fc99e Initial load
duke
parents:
diff changeset
3003 };
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
3004 // Excluded flags and vector registers.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
3005 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 5, "missing type");
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3006 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
a61af66fc99e Initial load
duke
parents:
diff changeset
3007 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3008 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3009
a61af66fc99e Initial load
duke
parents:
diff changeset
3010 //----------ATTRIBUTES---------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
3011 //----------Operand Attributes-------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
3012 op_attrib op_cost(0); // Required cost attribute
a61af66fc99e Initial load
duke
parents:
diff changeset
3013
a61af66fc99e Initial load
duke
parents:
diff changeset
3014 //----------Instruction Attributes---------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
3015 ins_attrib ins_cost(100); // Required cost attribute
a61af66fc99e Initial load
duke
parents:
diff changeset
3016 ins_attrib ins_size(8); // Required size attribute (in bits)
a61af66fc99e Initial load
duke
parents:
diff changeset
3017 ins_attrib ins_short_branch(0); // Required flag: is this instruction
a61af66fc99e Initial load
duke
parents:
diff changeset
3018 // a non-matching short branch variant
a61af66fc99e Initial load
duke
parents:
diff changeset
3019 // of some long branch?
a61af66fc99e Initial load
duke
parents:
diff changeset
3020 ins_attrib ins_alignment(1); // Required alignment attribute (must
a61af66fc99e Initial load
duke
parents:
diff changeset
3021 // be a power of 2) specifies the
a61af66fc99e Initial load
duke
parents:
diff changeset
3022 // alignment that some part of the
a61af66fc99e Initial load
duke
parents:
diff changeset
3023 // instruction (not necessarily the
a61af66fc99e Initial load
duke
parents:
diff changeset
3024 // start) requires. If > 1, a
a61af66fc99e Initial load
duke
parents:
diff changeset
3025 // compute_padding() function must be
a61af66fc99e Initial load
duke
parents:
diff changeset
3026 // provided for the instruction
a61af66fc99e Initial load
duke
parents:
diff changeset
3027
a61af66fc99e Initial load
duke
parents:
diff changeset
3028 //----------OPERANDS-----------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
3029 // Operand definitions must precede instruction definitions for correct parsing
a61af66fc99e Initial load
duke
parents:
diff changeset
3030 // in the ADLC because operands constitute user defined types which are used in
a61af66fc99e Initial load
duke
parents:
diff changeset
3031 // instruction definitions.
a61af66fc99e Initial load
duke
parents:
diff changeset
3032
a61af66fc99e Initial load
duke
parents:
diff changeset
3033 //----------Simple Operands----------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
3034 // Immediate Operands
a61af66fc99e Initial load
duke
parents:
diff changeset
3035 // Integer Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
3036 operand immI()
a61af66fc99e Initial load
duke
parents:
diff changeset
3037 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3038 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3039
a61af66fc99e Initial load
duke
parents:
diff changeset
3040 op_cost(10);
a61af66fc99e Initial load
duke
parents:
diff changeset
3041 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3042 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3043 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3044
a61af66fc99e Initial load
duke
parents:
diff changeset
3045 // Constant for test vs zero
a61af66fc99e Initial load
duke
parents:
diff changeset
3046 operand immI0()
a61af66fc99e Initial load
duke
parents:
diff changeset
3047 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3048 predicate(n->get_int() == 0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3049 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3050
a61af66fc99e Initial load
duke
parents:
diff changeset
3051 op_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3052 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3053 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3054 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3055
a61af66fc99e Initial load
duke
parents:
diff changeset
3056 // Constant for increment
a61af66fc99e Initial load
duke
parents:
diff changeset
3057 operand immI1()
a61af66fc99e Initial load
duke
parents:
diff changeset
3058 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3059 predicate(n->get_int() == 1);
a61af66fc99e Initial load
duke
parents:
diff changeset
3060 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3061
a61af66fc99e Initial load
duke
parents:
diff changeset
3062 op_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3063 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3064 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3065 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3066
a61af66fc99e Initial load
duke
parents:
diff changeset
3067 // Constant for decrement
a61af66fc99e Initial load
duke
parents:
diff changeset
3068 operand immI_M1()
a61af66fc99e Initial load
duke
parents:
diff changeset
3069 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3070 predicate(n->get_int() == -1);
a61af66fc99e Initial load
duke
parents:
diff changeset
3071 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3072
a61af66fc99e Initial load
duke
parents:
diff changeset
3073 op_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3074 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3075 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3076 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3077
a61af66fc99e Initial load
duke
parents:
diff changeset
3078 // Valid scale values for addressing modes
a61af66fc99e Initial load
duke
parents:
diff changeset
3079 operand immI2()
a61af66fc99e Initial load
duke
parents:
diff changeset
3080 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3081 predicate(0 <= n->get_int() && (n->get_int() <= 3));
a61af66fc99e Initial load
duke
parents:
diff changeset
3082 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3083
a61af66fc99e Initial load
duke
parents:
diff changeset
3084 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3085 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3086 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3087
a61af66fc99e Initial load
duke
parents:
diff changeset
3088 operand immI8()
a61af66fc99e Initial load
duke
parents:
diff changeset
3089 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3090 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
a61af66fc99e Initial load
duke
parents:
diff changeset
3091 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3092
a61af66fc99e Initial load
duke
parents:
diff changeset
3093 op_cost(5);
a61af66fc99e Initial load
duke
parents:
diff changeset
3094 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3095 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3096 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3097
a61af66fc99e Initial load
duke
parents:
diff changeset
3098 operand immI16()
a61af66fc99e Initial load
duke
parents:
diff changeset
3099 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3100 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
a61af66fc99e Initial load
duke
parents:
diff changeset
3101 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3102
a61af66fc99e Initial load
duke
parents:
diff changeset
3103 op_cost(10);
a61af66fc99e Initial load
duke
parents:
diff changeset
3104 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3105 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3106 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3107
a61af66fc99e Initial load
duke
parents:
diff changeset
3108 // Constant for long shifts
a61af66fc99e Initial load
duke
parents:
diff changeset
3109 operand immI_32()
a61af66fc99e Initial load
duke
parents:
diff changeset
3110 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3111 predicate( n->get_int() == 32 );
a61af66fc99e Initial load
duke
parents:
diff changeset
3112 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3113
a61af66fc99e Initial load
duke
parents:
diff changeset
3114 op_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3115 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3116 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3117 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3118
a61af66fc99e Initial load
duke
parents:
diff changeset
3119 // Constant for long shifts
a61af66fc99e Initial load
duke
parents:
diff changeset
3120 operand immI_64()
a61af66fc99e Initial load
duke
parents:
diff changeset
3121 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3122 predicate( n->get_int() == 64 );
a61af66fc99e Initial load
duke
parents:
diff changeset
3123 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3124
a61af66fc99e Initial load
duke
parents:
diff changeset
3125 op_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3126 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3127 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3128 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3129
a61af66fc99e Initial load
duke
parents:
diff changeset
3130 // Pointer Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
3131 operand immP()
a61af66fc99e Initial load
duke
parents:
diff changeset
3132 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3133 match(ConP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3134
a61af66fc99e Initial load
duke
parents:
diff changeset
3135 op_cost(10);
a61af66fc99e Initial load
duke
parents:
diff changeset
3136 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3137 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3138 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3139
a61af66fc99e Initial load
duke
parents:
diff changeset
3140 // NULL Pointer Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
3141 operand immP0()
a61af66fc99e Initial load
duke
parents:
diff changeset
3142 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3143 predicate(n->get_ptr() == 0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3144 match(ConP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3145
a61af66fc99e Initial load
duke
parents:
diff changeset
3146 op_cost(5);
a61af66fc99e Initial load
duke
parents:
diff changeset
3147 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3148 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3149 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3150
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3151 // Pointer Immediate
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3152 operand immN() %{
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3153 match(ConN);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3154
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3155 op_cost(10);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3156 format %{ %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3157 interface(CONST_INTER);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3158 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3159
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3160 // NULL Pointer Immediate
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3161 operand immN0() %{
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3162 predicate(n->get_narrowcon() == 0);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3163 match(ConN);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3164
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3165 op_cost(5);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3166 format %{ %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3167 interface(CONST_INTER);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3168 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3169
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3170 operand immP31()
a61af66fc99e Initial load
duke
parents:
diff changeset
3171 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3172 predicate(!n->as_Type()->type()->isa_oopptr()
a61af66fc99e Initial load
duke
parents:
diff changeset
3173 && (n->get_ptr() >> 31) == 0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3174 match(ConP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3175
a61af66fc99e Initial load
duke
parents:
diff changeset
3176 op_cost(5);
a61af66fc99e Initial load
duke
parents:
diff changeset
3177 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3178 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3179 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3180
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3181
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3182 // Long Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
3183 operand immL()
a61af66fc99e Initial load
duke
parents:
diff changeset
3184 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3185 match(ConL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3186
a61af66fc99e Initial load
duke
parents:
diff changeset
3187 op_cost(20);
a61af66fc99e Initial load
duke
parents:
diff changeset
3188 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3189 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3190 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3191
a61af66fc99e Initial load
duke
parents:
diff changeset
3192 // Long Immediate 8-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
3193 operand immL8()
a61af66fc99e Initial load
duke
parents:
diff changeset
3194 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3195 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
a61af66fc99e Initial load
duke
parents:
diff changeset
3196 match(ConL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3197
a61af66fc99e Initial load
duke
parents:
diff changeset
3198 op_cost(5);
a61af66fc99e Initial load
duke
parents:
diff changeset
3199 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3200 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3201 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3202
a61af66fc99e Initial load
duke
parents:
diff changeset
3203 // Long Immediate 32-bit unsigned
a61af66fc99e Initial load
duke
parents:
diff changeset
3204 operand immUL32()
a61af66fc99e Initial load
duke
parents:
diff changeset
3205 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3206 predicate(n->get_long() == (unsigned int) (n->get_long()));
a61af66fc99e Initial load
duke
parents:
diff changeset
3207 match(ConL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3208
a61af66fc99e Initial load
duke
parents:
diff changeset
3209 op_cost(10);
a61af66fc99e Initial load
duke
parents:
diff changeset
3210 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3211 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3212 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3213
a61af66fc99e Initial load
duke
parents:
diff changeset
3214 // Long Immediate 32-bit signed
a61af66fc99e Initial load
duke
parents:
diff changeset
3215 operand immL32()
a61af66fc99e Initial load
duke
parents:
diff changeset
3216 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3217 predicate(n->get_long() == (int) (n->get_long()));
a61af66fc99e Initial load
duke
parents:
diff changeset
3218 match(ConL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3219
a61af66fc99e Initial load
duke
parents:
diff changeset
3220 op_cost(15);
a61af66fc99e Initial load
duke
parents:
diff changeset
3221 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3222 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3223 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3224
a61af66fc99e Initial load
duke
parents:
diff changeset
3225 // Long Immediate zero
a61af66fc99e Initial load
duke
parents:
diff changeset
3226 operand immL0()
a61af66fc99e Initial load
duke
parents:
diff changeset
3227 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3228 predicate(n->get_long() == 0L);
a61af66fc99e Initial load
duke
parents:
diff changeset
3229 match(ConL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3230
a61af66fc99e Initial load
duke
parents:
diff changeset
3231 op_cost(10);
a61af66fc99e Initial load
duke
parents:
diff changeset
3232 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3233 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3234 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3235
a61af66fc99e Initial load
duke
parents:
diff changeset
3236 // Constant for increment
a61af66fc99e Initial load
duke
parents:
diff changeset
3237 operand immL1()
a61af66fc99e Initial load
duke
parents:
diff changeset
3238 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3239 predicate(n->get_long() == 1);
a61af66fc99e Initial load
duke
parents:
diff changeset
3240 match(ConL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3241
a61af66fc99e Initial load
duke
parents:
diff changeset
3242 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3243 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3244 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3245
a61af66fc99e Initial load
duke
parents:
diff changeset
3246 // Constant for decrement
a61af66fc99e Initial load
duke
parents:
diff changeset
3247 operand immL_M1()
a61af66fc99e Initial load
duke
parents:
diff changeset
3248 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3249 predicate(n->get_long() == -1);
a61af66fc99e Initial load
duke
parents:
diff changeset
3250 match(ConL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3251
a61af66fc99e Initial load
duke
parents:
diff changeset
3252 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3253 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3254 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3255
a61af66fc99e Initial load
duke
parents:
diff changeset
3256 // Long Immediate: the value 10
a61af66fc99e Initial load
duke
parents:
diff changeset
3257 operand immL10()
a61af66fc99e Initial load
duke
parents:
diff changeset
3258 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3259 predicate(n->get_long() == 10);
a61af66fc99e Initial load
duke
parents:
diff changeset
3260 match(ConL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3261
a61af66fc99e Initial load
duke
parents:
diff changeset
3262 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3263 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3264 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3265
a61af66fc99e Initial load
duke
parents:
diff changeset
3266 // Long immediate from 0 to 127.
a61af66fc99e Initial load
duke
parents:
diff changeset
3267 // Used for a shorter form of long mul by 10.
a61af66fc99e Initial load
duke
parents:
diff changeset
3268 operand immL_127()
a61af66fc99e Initial load
duke
parents:
diff changeset
3269 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3270 predicate(0 <= n->get_long() && n->get_long() < 0x80);
a61af66fc99e Initial load
duke
parents:
diff changeset
3271 match(ConL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3272
a61af66fc99e Initial load
duke
parents:
diff changeset
3273 op_cost(10);
a61af66fc99e Initial load
duke
parents:
diff changeset
3274 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3275 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3276 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3277
a61af66fc99e Initial load
duke
parents:
diff changeset
3278 // Long Immediate: low 32-bit mask
a61af66fc99e Initial load
duke
parents:
diff changeset
3279 operand immL_32bits()
a61af66fc99e Initial load
duke
parents:
diff changeset
3280 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3281 predicate(n->get_long() == 0xFFFFFFFFL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3282 match(ConL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3283 op_cost(20);
a61af66fc99e Initial load
duke
parents:
diff changeset
3284
a61af66fc99e Initial load
duke
parents:
diff changeset
3285 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3286 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3287 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3288
a61af66fc99e Initial load
duke
parents:
diff changeset
3289 // Float Immediate zero
a61af66fc99e Initial load
duke
parents:
diff changeset
3290 operand immF0()
a61af66fc99e Initial load
duke
parents:
diff changeset
3291 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3292 predicate(jint_cast(n->getf()) == 0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3293 match(ConF);
a61af66fc99e Initial load
duke
parents:
diff changeset
3294
a61af66fc99e Initial load
duke
parents:
diff changeset
3295 op_cost(5);
a61af66fc99e Initial load
duke
parents:
diff changeset
3296 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3297 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3298 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3299
a61af66fc99e Initial load
duke
parents:
diff changeset
3300 // Float Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
3301 operand immF()
a61af66fc99e Initial load
duke
parents:
diff changeset
3302 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3303 match(ConF);
a61af66fc99e Initial load
duke
parents:
diff changeset
3304
a61af66fc99e Initial load
duke
parents:
diff changeset
3305 op_cost(15);
a61af66fc99e Initial load
duke
parents:
diff changeset
3306 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3307 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3308 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3309
a61af66fc99e Initial load
duke
parents:
diff changeset
3310 // Double Immediate zero
a61af66fc99e Initial load
duke
parents:
diff changeset
3311 operand immD0()
a61af66fc99e Initial load
duke
parents:
diff changeset
3312 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3313 predicate(jlong_cast(n->getd()) == 0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3314 match(ConD);
a61af66fc99e Initial load
duke
parents:
diff changeset
3315
a61af66fc99e Initial load
duke
parents:
diff changeset
3316 op_cost(5);
a61af66fc99e Initial load
duke
parents:
diff changeset
3317 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3318 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3319 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3320
a61af66fc99e Initial load
duke
parents:
diff changeset
3321 // Double Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
3322 operand immD()
a61af66fc99e Initial load
duke
parents:
diff changeset
3323 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3324 match(ConD);
a61af66fc99e Initial load
duke
parents:
diff changeset
3325
a61af66fc99e Initial load
duke
parents:
diff changeset
3326 op_cost(15);
a61af66fc99e Initial load
duke
parents:
diff changeset
3327 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3328 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3329 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3330
a61af66fc99e Initial load
duke
parents:
diff changeset
3331 // Immediates for special shifts (sign extend)
a61af66fc99e Initial load
duke
parents:
diff changeset
3332
a61af66fc99e Initial load
duke
parents:
diff changeset
3333 // Constants for increment
a61af66fc99e Initial load
duke
parents:
diff changeset
3334 operand immI_16()
a61af66fc99e Initial load
duke
parents:
diff changeset
3335 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3336 predicate(n->get_int() == 16);
a61af66fc99e Initial load
duke
parents:
diff changeset
3337 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3338
a61af66fc99e Initial load
duke
parents:
diff changeset
3339 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3340 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3341 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3342
a61af66fc99e Initial load
duke
parents:
diff changeset
3343 operand immI_24()
a61af66fc99e Initial load
duke
parents:
diff changeset
3344 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3345 predicate(n->get_int() == 24);
a61af66fc99e Initial load
duke
parents:
diff changeset
3346 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3347
a61af66fc99e Initial load
duke
parents:
diff changeset
3348 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3349 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3350 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3351
a61af66fc99e Initial load
duke
parents:
diff changeset
3352 // Constant for byte-wide masking
a61af66fc99e Initial load
duke
parents:
diff changeset
3353 operand immI_255()
a61af66fc99e Initial load
duke
parents:
diff changeset
3354 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3355 predicate(n->get_int() == 255);
a61af66fc99e Initial load
duke
parents:
diff changeset
3356 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3357
a61af66fc99e Initial load
duke
parents:
diff changeset
3358 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3359 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3360 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3361
a61af66fc99e Initial load
duke
parents:
diff changeset
3362 // Constant for short-wide masking
a61af66fc99e Initial load
duke
parents:
diff changeset
3363 operand immI_65535()
a61af66fc99e Initial load
duke
parents:
diff changeset
3364 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3365 predicate(n->get_int() == 65535);
a61af66fc99e Initial load
duke
parents:
diff changeset
3366 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3367
a61af66fc99e Initial load
duke
parents:
diff changeset
3368 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3369 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3370 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3371
a61af66fc99e Initial load
duke
parents:
diff changeset
3372 // Constant for byte-wide masking
a61af66fc99e Initial load
duke
parents:
diff changeset
3373 operand immL_255()
a61af66fc99e Initial load
duke
parents:
diff changeset
3374 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3375 predicate(n->get_long() == 255);
a61af66fc99e Initial load
duke
parents:
diff changeset
3376 match(ConL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3377
a61af66fc99e Initial load
duke
parents:
diff changeset
3378 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3379 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3380 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3381
a61af66fc99e Initial load
duke
parents:
diff changeset
3382 // Constant for short-wide masking
a61af66fc99e Initial load
duke
parents:
diff changeset
3383 operand immL_65535()
a61af66fc99e Initial load
duke
parents:
diff changeset
3384 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3385 predicate(n->get_long() == 65535);
a61af66fc99e Initial load
duke
parents:
diff changeset
3386 match(ConL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3387
a61af66fc99e Initial load
duke
parents:
diff changeset
3388 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3389 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3390 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3391
a61af66fc99e Initial load
duke
parents:
diff changeset
3392 // Register Operands
a61af66fc99e Initial load
duke
parents:
diff changeset
3393 // Integer Register
a61af66fc99e Initial load
duke
parents:
diff changeset
3394 operand rRegI()
a61af66fc99e Initial load
duke
parents:
diff changeset
3395 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3396 constraint(ALLOC_IN_RC(int_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3397 match(RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3398
a61af66fc99e Initial load
duke
parents:
diff changeset
3399 match(rax_RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3400 match(rbx_RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3401 match(rcx_RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3402 match(rdx_RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3403 match(rdi_RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3404
a61af66fc99e Initial load
duke
parents:
diff changeset
3405 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3406 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3407 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3408
a61af66fc99e Initial load
duke
parents:
diff changeset
3409 // Special Registers
a61af66fc99e Initial load
duke
parents:
diff changeset
3410 operand rax_RegI()
a61af66fc99e Initial load
duke
parents:
diff changeset
3411 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3412 constraint(ALLOC_IN_RC(int_rax_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3413 match(RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3414 match(rRegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3415
a61af66fc99e Initial load
duke
parents:
diff changeset
3416 format %{ "RAX" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3417 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3418 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3419
a61af66fc99e Initial load
duke
parents:
diff changeset
3420 // Special Registers
a61af66fc99e Initial load
duke
parents:
diff changeset
3421 operand rbx_RegI()
a61af66fc99e Initial load
duke
parents:
diff changeset
3422 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3423 constraint(ALLOC_IN_RC(int_rbx_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3424 match(RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3425 match(rRegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3426
a61af66fc99e Initial load
duke
parents:
diff changeset
3427 format %{ "RBX" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3428 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3429 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3430
a61af66fc99e Initial load
duke
parents:
diff changeset
3431 operand rcx_RegI()
a61af66fc99e Initial load
duke
parents:
diff changeset
3432 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3433 constraint(ALLOC_IN_RC(int_rcx_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3434 match(RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3435 match(rRegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3436
a61af66fc99e Initial load
duke
parents:
diff changeset
3437 format %{ "RCX" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3438 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3439 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3440
a61af66fc99e Initial load
duke
parents:
diff changeset
3441 operand rdx_RegI()
a61af66fc99e Initial load
duke
parents:
diff changeset
3442 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3443 constraint(ALLOC_IN_RC(int_rdx_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3444 match(RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3445 match(rRegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3446
a61af66fc99e Initial load
duke
parents:
diff changeset
3447 format %{ "RDX" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3448 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3449 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3450
a61af66fc99e Initial load
duke
parents:
diff changeset
3451 operand rdi_RegI()
a61af66fc99e Initial load
duke
parents:
diff changeset
3452 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3453 constraint(ALLOC_IN_RC(int_rdi_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3454 match(RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3455 match(rRegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3456
a61af66fc99e Initial load
duke
parents:
diff changeset
3457 format %{ "RDI" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3458 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3459 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3460
a61af66fc99e Initial load
duke
parents:
diff changeset
3461 operand no_rcx_RegI()
a61af66fc99e Initial load
duke
parents:
diff changeset
3462 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3463 constraint(ALLOC_IN_RC(int_no_rcx_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3464 match(RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3465 match(rax_RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3466 match(rbx_RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3467 match(rdx_RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3468 match(rdi_RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3469
a61af66fc99e Initial load
duke
parents:
diff changeset
3470 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3471 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3472 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3473
a61af66fc99e Initial load
duke
parents:
diff changeset
3474 operand no_rax_rdx_RegI()
a61af66fc99e Initial load
duke
parents:
diff changeset
3475 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3476 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3477 match(RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3478 match(rbx_RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3479 match(rcx_RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3480 match(rdi_RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3481
a61af66fc99e Initial load
duke
parents:
diff changeset
3482 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3483 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3484 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3485
a61af66fc99e Initial load
duke
parents:
diff changeset
3486 // Pointer Register
a61af66fc99e Initial load
duke
parents:
diff changeset
3487 operand any_RegP()
a61af66fc99e Initial load
duke
parents:
diff changeset
3488 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3489 constraint(ALLOC_IN_RC(any_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3490 match(RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3491 match(rax_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3492 match(rbx_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3493 match(rdi_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3494 match(rsi_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3495 match(rbp_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3496 match(r15_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3497 match(rRegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3498
a61af66fc99e Initial load
duke
parents:
diff changeset
3499 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3500 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3501 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3502
a61af66fc99e Initial load
duke
parents:
diff changeset
3503 operand rRegP()
a61af66fc99e Initial load
duke
parents:
diff changeset
3504 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3505 constraint(ALLOC_IN_RC(ptr_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3506 match(RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3507 match(rax_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3508 match(rbx_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3509 match(rdi_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3510 match(rsi_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3511 match(rbp_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3512 match(r15_RegP); // See Q&A below about r15_RegP.
a61af66fc99e Initial load
duke
parents:
diff changeset
3513
a61af66fc99e Initial load
duke
parents:
diff changeset
3514 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3515 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3516 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3517
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3518 operand rRegN() %{
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3519 constraint(ALLOC_IN_RC(int_reg));
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3520 match(RegN);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3521
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3522 format %{ %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3523 interface(REG_INTER);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3524 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3525
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3526 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
a61af66fc99e Initial load
duke
parents:
diff changeset
3527 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
a61af66fc99e Initial load
duke
parents:
diff changeset
3528 // It's fine for an instruction input which expects rRegP to match a r15_RegP.
a61af66fc99e Initial load
duke
parents:
diff changeset
3529 // The output of an instruction is controlled by the allocator, which respects
a61af66fc99e Initial load
duke
parents:
diff changeset
3530 // register class masks, not match rules. Unless an instruction mentions
a61af66fc99e Initial load
duke
parents:
diff changeset
3531 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
a61af66fc99e Initial load
duke
parents:
diff changeset
3532 // by the allocator as an input.
a61af66fc99e Initial load
duke
parents:
diff changeset
3533
a61af66fc99e Initial load
duke
parents:
diff changeset
3534 operand no_rax_RegP()
a61af66fc99e Initial load
duke
parents:
diff changeset
3535 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3536 constraint(ALLOC_IN_RC(ptr_no_rax_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3537 match(RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3538 match(rbx_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3539 match(rsi_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3540 match(rdi_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3541
a61af66fc99e Initial load
duke
parents:
diff changeset
3542 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3543 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3544 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3545
a61af66fc99e Initial load
duke
parents:
diff changeset
3546 operand no_rbp_RegP()
a61af66fc99e Initial load
duke
parents:
diff changeset
3547 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3548 constraint(ALLOC_IN_RC(ptr_no_rbp_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3549 match(RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3550 match(rbx_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3551 match(rsi_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3552 match(rdi_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3553
a61af66fc99e Initial load
duke
parents:
diff changeset
3554 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3555 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3556 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3557
a61af66fc99e Initial load
duke
parents:
diff changeset
3558 operand no_rax_rbx_RegP()
a61af66fc99e Initial load
duke
parents:
diff changeset
3559 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3560 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3561 match(RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3562 match(rsi_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3563 match(rdi_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3564
a61af66fc99e Initial load
duke
parents:
diff changeset
3565 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3566 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3567 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3568
a61af66fc99e Initial load
duke
parents:
diff changeset
3569 // Special Registers
a61af66fc99e Initial load
duke
parents:
diff changeset
3570 // Return a pointer value
a61af66fc99e Initial load
duke
parents:
diff changeset
3571 operand rax_RegP()
a61af66fc99e Initial load
duke
parents:
diff changeset
3572 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3573 constraint(ALLOC_IN_RC(ptr_rax_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3574 match(RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3575 match(rRegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3576
a61af66fc99e Initial load
duke
parents:
diff changeset
3577 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3578 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3579 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3580
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3581 // Special Registers
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3582 // Return a compressed pointer value
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3583 operand rax_RegN()
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3584 %{
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3585 constraint(ALLOC_IN_RC(int_rax_reg));
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3586 match(RegN);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3587 match(rRegN);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3588
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3589 format %{ %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3590 interface(REG_INTER);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3591 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3592
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3593 // Used in AtomicAdd
a61af66fc99e Initial load
duke
parents:
diff changeset
3594 operand rbx_RegP()
a61af66fc99e Initial load
duke
parents:
diff changeset
3595 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3596 constraint(ALLOC_IN_RC(ptr_rbx_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3597 match(RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3598 match(rRegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3599
a61af66fc99e Initial load
duke
parents:
diff changeset
3600 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3601 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3602 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3603
a61af66fc99e Initial load
duke
parents:
diff changeset
3604 operand rsi_RegP()
a61af66fc99e Initial load
duke
parents:
diff changeset
3605 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3606 constraint(ALLOC_IN_RC(ptr_rsi_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3607 match(RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3608 match(rRegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3609
a61af66fc99e Initial load
duke
parents:
diff changeset
3610 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3611 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3612 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3613
a61af66fc99e Initial load
duke
parents:
diff changeset
3614 // Used in rep stosq
a61af66fc99e Initial load
duke
parents:
diff changeset
3615 operand rdi_RegP()
a61af66fc99e Initial load
duke
parents:
diff changeset
3616 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3617 constraint(ALLOC_IN_RC(ptr_rdi_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3618 match(RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3619 match(rRegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3620
a61af66fc99e Initial load
duke
parents:
diff changeset
3621 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3622 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3623 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3624
a61af66fc99e Initial load
duke
parents:
diff changeset
3625 operand rbp_RegP()
a61af66fc99e Initial load
duke
parents:
diff changeset
3626 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3627 constraint(ALLOC_IN_RC(ptr_rbp_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3628 match(RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3629 match(rRegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3630
a61af66fc99e Initial load
duke
parents:
diff changeset
3631 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3632 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3633 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3634
a61af66fc99e Initial load
duke
parents:
diff changeset
3635 operand r15_RegP()
a61af66fc99e Initial load
duke
parents:
diff changeset
3636 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3637 constraint(ALLOC_IN_RC(ptr_r15_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3638 match(RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3639 match(rRegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3640
a61af66fc99e Initial load
duke
parents:
diff changeset
3641 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3642 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3643 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3644
a61af66fc99e Initial load
duke
parents:
diff changeset
3645 operand rRegL()
a61af66fc99e Initial load
duke
parents:
diff changeset
3646 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3647 constraint(ALLOC_IN_RC(long_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3648 match(RegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3649 match(rax_RegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3650 match(rdx_RegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3651
a61af66fc99e Initial load
duke
parents:
diff changeset
3652 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3653 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3654 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3655
a61af66fc99e Initial load
duke
parents:
diff changeset
3656 // Special Registers
a61af66fc99e Initial load
duke
parents:
diff changeset
3657 operand no_rax_rdx_RegL()
a61af66fc99e Initial load
duke
parents:
diff changeset
3658 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3659 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3660 match(RegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3661 match(rRegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3662
a61af66fc99e Initial load
duke
parents:
diff changeset
3663 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3664 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3665 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3666
a61af66fc99e Initial load
duke
parents:
diff changeset
3667 operand no_rax_RegL()
a61af66fc99e Initial load
duke
parents:
diff changeset
3668 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3669 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3670 match(RegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3671 match(rRegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3672 match(rdx_RegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3673
a61af66fc99e Initial load
duke
parents:
diff changeset
3674 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3675 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3676 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3677
a61af66fc99e Initial load
duke
parents:
diff changeset
3678 operand no_rcx_RegL()
a61af66fc99e Initial load
duke
parents:
diff changeset
3679 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3680 constraint(ALLOC_IN_RC(long_no_rcx_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3681 match(RegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3682 match(rRegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3683
a61af66fc99e Initial load
duke
parents:
diff changeset
3684 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3685 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3686 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3687
a61af66fc99e Initial load
duke
parents:
diff changeset
3688 operand rax_RegL()
a61af66fc99e Initial load
duke
parents:
diff changeset
3689 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3690 constraint(ALLOC_IN_RC(long_rax_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3691 match(RegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3692 match(rRegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3693
a61af66fc99e Initial load
duke
parents:
diff changeset
3694 format %{ "RAX" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3695 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3696 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3697
a61af66fc99e Initial load
duke
parents:
diff changeset
3698 operand rcx_RegL()
a61af66fc99e Initial load
duke
parents:
diff changeset
3699 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3700 constraint(ALLOC_IN_RC(long_rcx_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3701 match(RegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3702 match(rRegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3703
a61af66fc99e Initial load
duke
parents:
diff changeset
3704 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3705 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3706 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3707
a61af66fc99e Initial load
duke
parents:
diff changeset
3708 operand rdx_RegL()
a61af66fc99e Initial load
duke
parents:
diff changeset
3709 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3710 constraint(ALLOC_IN_RC(long_rdx_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3711 match(RegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3712 match(rRegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3713
a61af66fc99e Initial load
duke
parents:
diff changeset
3714 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3715 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3716 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3717
a61af66fc99e Initial load
duke
parents:
diff changeset
3718 // Flags register, used as output of compare instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
3719 operand rFlagsReg()
a61af66fc99e Initial load
duke
parents:
diff changeset
3720 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3721 constraint(ALLOC_IN_RC(int_flags));
a61af66fc99e Initial load
duke
parents:
diff changeset
3722 match(RegFlags);
a61af66fc99e Initial load
duke
parents:
diff changeset
3723
a61af66fc99e Initial load
duke
parents:
diff changeset
3724 format %{ "RFLAGS" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3725 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3726 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3727
a61af66fc99e Initial load
duke
parents:
diff changeset
3728 // Flags register, used as output of FLOATING POINT compare instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
3729 operand rFlagsRegU()
a61af66fc99e Initial load
duke
parents:
diff changeset
3730 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3731 constraint(ALLOC_IN_RC(int_flags));
a61af66fc99e Initial load
duke
parents:
diff changeset
3732 match(RegFlags);
a61af66fc99e Initial load
duke
parents:
diff changeset
3733
a61af66fc99e Initial load
duke
parents:
diff changeset
3734 format %{ "RFLAGS_U" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3735 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3736 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3737
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
3738 operand rFlagsRegUCF() %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
3739 constraint(ALLOC_IN_RC(int_flags));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
3740 match(RegFlags);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
3741 predicate(false);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
3742
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
3743 format %{ "RFLAGS_U_CF" %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
3744 interface(REG_INTER);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
3745 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
3746
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3747 // Float register operands
a61af66fc99e Initial load
duke
parents:
diff changeset
3748 operand regF()
a61af66fc99e Initial load
duke
parents:
diff changeset
3749 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3750 constraint(ALLOC_IN_RC(float_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3751 match(RegF);
a61af66fc99e Initial load
duke
parents:
diff changeset
3752
a61af66fc99e Initial load
duke
parents:
diff changeset
3753 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3754 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3755 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3756
a61af66fc99e Initial load
duke
parents:
diff changeset
3757 // Double register operands
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
3758 operand regD()
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3759 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3760 constraint(ALLOC_IN_RC(double_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3761 match(RegD);
a61af66fc99e Initial load
duke
parents:
diff changeset
3762
a61af66fc99e Initial load
duke
parents:
diff changeset
3763 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3764 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3765 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3766
a61af66fc99e Initial load
duke
parents:
diff changeset
3767 //----------Memory Operands----------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
3768 // Direct Memory Operand
a61af66fc99e Initial load
duke
parents:
diff changeset
3769 // operand direct(immP addr)
a61af66fc99e Initial load
duke
parents:
diff changeset
3770 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3771 // match(addr);
a61af66fc99e Initial load
duke
parents:
diff changeset
3772
a61af66fc99e Initial load
duke
parents:
diff changeset
3773 // format %{ "[$addr]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3774 // interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3775 // base(0xFFFFFFFF);
a61af66fc99e Initial load
duke
parents:
diff changeset
3776 // index(0x4);
a61af66fc99e Initial load
duke
parents:
diff changeset
3777 // scale(0x0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3778 // disp($addr);
a61af66fc99e Initial load
duke
parents:
diff changeset
3779 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3780 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3781
a61af66fc99e Initial load
duke
parents:
diff changeset
3782 // Indirect Memory Operand
a61af66fc99e Initial load
duke
parents:
diff changeset
3783 operand indirect(any_RegP reg)
a61af66fc99e Initial load
duke
parents:
diff changeset
3784 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3785 constraint(ALLOC_IN_RC(ptr_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3786 match(reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3787
a61af66fc99e Initial load
duke
parents:
diff changeset
3788 format %{ "[$reg]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3789 interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3790 base($reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3791 index(0x4);
a61af66fc99e Initial load
duke
parents:
diff changeset
3792 scale(0x0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3793 disp(0x0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3794 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3795 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3796
a61af66fc99e Initial load
duke
parents:
diff changeset
3797 // Indirect Memory Plus Short Offset Operand
a61af66fc99e Initial load
duke
parents:
diff changeset
3798 operand indOffset8(any_RegP reg, immL8 off)
a61af66fc99e Initial load
duke
parents:
diff changeset
3799 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3800 constraint(ALLOC_IN_RC(ptr_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3801 match(AddP reg off);
a61af66fc99e Initial load
duke
parents:
diff changeset
3802
a61af66fc99e Initial load
duke
parents:
diff changeset
3803 format %{ "[$reg + $off (8-bit)]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3804 interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3805 base($reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3806 index(0x4);
a61af66fc99e Initial load
duke
parents:
diff changeset
3807 scale(0x0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3808 disp($off);
a61af66fc99e Initial load
duke
parents:
diff changeset
3809 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3810 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3811
a61af66fc99e Initial load
duke
parents:
diff changeset
3812 // Indirect Memory Plus Long Offset Operand
a61af66fc99e Initial load
duke
parents:
diff changeset
3813 operand indOffset32(any_RegP reg, immL32 off)
a61af66fc99e Initial load
duke
parents:
diff changeset
3814 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3815 constraint(ALLOC_IN_RC(ptr_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3816 match(AddP reg off);
a61af66fc99e Initial load
duke
parents:
diff changeset
3817
a61af66fc99e Initial load
duke
parents:
diff changeset
3818 format %{ "[$reg + $off (32-bit)]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3819 interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3820 base($reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3821 index(0x4);
a61af66fc99e Initial load
duke
parents:
diff changeset
3822 scale(0x0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3823 disp($off);
a61af66fc99e Initial load
duke
parents:
diff changeset
3824 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3825 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3826
a61af66fc99e Initial load
duke
parents:
diff changeset
3827 // Indirect Memory Plus Index Register Plus Offset Operand
a61af66fc99e Initial load
duke
parents:
diff changeset
3828 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
a61af66fc99e Initial load
duke
parents:
diff changeset
3829 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3830 constraint(ALLOC_IN_RC(ptr_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3831 match(AddP (AddP reg lreg) off);
a61af66fc99e Initial load
duke
parents:
diff changeset
3832
a61af66fc99e Initial load
duke
parents:
diff changeset
3833 op_cost(10);
a61af66fc99e Initial load
duke
parents:
diff changeset
3834 format %{"[$reg + $off + $lreg]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3835 interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3836 base($reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3837 index($lreg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3838 scale(0x0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3839 disp($off);
a61af66fc99e Initial load
duke
parents:
diff changeset
3840 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3841 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3842
a61af66fc99e Initial load
duke
parents:
diff changeset
3843 // Indirect Memory Plus Index Register Plus Offset Operand
a61af66fc99e Initial load
duke
parents:
diff changeset
3844 operand indIndex(any_RegP reg, rRegL lreg)
a61af66fc99e Initial load
duke
parents:
diff changeset
3845 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3846 constraint(ALLOC_IN_RC(ptr_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3847 match(AddP reg lreg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3848
a61af66fc99e Initial load
duke
parents:
diff changeset
3849 op_cost(10);
a61af66fc99e Initial load
duke
parents:
diff changeset
3850 format %{"[$reg + $lreg]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3851 interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3852 base($reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3853 index($lreg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3854 scale(0x0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3855 disp(0x0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3856 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3857 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3858
a61af66fc99e Initial load
duke
parents:
diff changeset
3859 // Indirect Memory Times Scale Plus Index Register
a61af66fc99e Initial load
duke
parents:
diff changeset
3860 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
a61af66fc99e Initial load
duke
parents:
diff changeset
3861 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3862 constraint(ALLOC_IN_RC(ptr_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3863 match(AddP reg (LShiftL lreg scale));
a61af66fc99e Initial load
duke
parents:
diff changeset
3864
a61af66fc99e Initial load
duke
parents:
diff changeset
3865 op_cost(10);
a61af66fc99e Initial load
duke
parents:
diff changeset
3866 format %{"[$reg + $lreg << $scale]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3867 interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3868 base($reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3869 index($lreg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3870 scale($scale);
a61af66fc99e Initial load
duke
parents:
diff changeset
3871 disp(0x0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3872 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3873 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3874
a61af66fc99e Initial load
duke
parents:
diff changeset
3875 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
a61af66fc99e Initial load
duke
parents:
diff changeset
3876 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
a61af66fc99e Initial load
duke
parents:
diff changeset
3877 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3878 constraint(ALLOC_IN_RC(ptr_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3879 match(AddP (AddP reg (LShiftL lreg scale)) off);
a61af66fc99e Initial load
duke
parents:
diff changeset
3880
a61af66fc99e Initial load
duke
parents:
diff changeset
3881 op_cost(10);
a61af66fc99e Initial load
duke
parents:
diff changeset
3882 format %{"[$reg + $off + $lreg << $scale]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3883 interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3884 base($reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3885 index($lreg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3886 scale($scale);
a61af66fc99e Initial load
duke
parents:
diff changeset
3887 disp($off);
a61af66fc99e Initial load
duke
parents:
diff changeset
3888 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3889 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3890
a61af66fc99e Initial load
duke
parents:
diff changeset
3891 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
a61af66fc99e Initial load
duke
parents:
diff changeset
3892 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
a61af66fc99e Initial load
duke
parents:
diff changeset
3893 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3894 constraint(ALLOC_IN_RC(ptr_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3895 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3896 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
a61af66fc99e Initial load
duke
parents:
diff changeset
3897
a61af66fc99e Initial load
duke
parents:
diff changeset
3898 op_cost(10);
a61af66fc99e Initial load
duke
parents:
diff changeset
3899 format %{"[$reg + $off + $idx << $scale]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3900 interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3901 base($reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3902 index($idx);
a61af66fc99e Initial load
duke
parents:
diff changeset
3903 scale($scale);
a61af66fc99e Initial load
duke
parents:
diff changeset
3904 disp($off);
a61af66fc99e Initial load
duke
parents:
diff changeset
3905 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3906 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3907
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3908 // Indirect Narrow Oop Plus Offset Operand
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3909 // Note: x86 architecture doesn't support "scale * index + offset" without a base
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3910 // we can't free r12 even with Universe::narrow_oop_base() == NULL.
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3911 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
1571
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
3912 predicate(UseCompressedOops && (Universe::narrow_oop_shift() == Address::times_8));
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3913 constraint(ALLOC_IN_RC(ptr_reg));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3914 match(AddP (DecodeN reg) off);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3915
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3916 op_cost(10);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3917 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3918 interface(MEMORY_INTER) %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3919 base(0xc); // R12
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3920 index($reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3921 scale(0x3);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3922 disp($off);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3923 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3924 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3925
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3926 // Indirect Memory Operand
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3927 operand indirectNarrow(rRegN reg)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3928 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3929 predicate(Universe::narrow_oop_shift() == 0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3930 constraint(ALLOC_IN_RC(ptr_reg));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3931 match(DecodeN reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3932
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3933 format %{ "[$reg]" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3934 interface(MEMORY_INTER) %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3935 base($reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3936 index(0x4);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3937 scale(0x0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3938 disp(0x0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3939 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3940 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3941
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3942 // Indirect Memory Plus Short Offset Operand
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3943 operand indOffset8Narrow(rRegN reg, immL8 off)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3944 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3945 predicate(Universe::narrow_oop_shift() == 0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3946 constraint(ALLOC_IN_RC(ptr_reg));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3947 match(AddP (DecodeN reg) off);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3948
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3949 format %{ "[$reg + $off (8-bit)]" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3950 interface(MEMORY_INTER) %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3951 base($reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3952 index(0x4);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3953 scale(0x0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3954 disp($off);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3955 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3956 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3957
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3958 // Indirect Memory Plus Long Offset Operand
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3959 operand indOffset32Narrow(rRegN reg, immL32 off)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3960 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3961 predicate(Universe::narrow_oop_shift() == 0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3962 constraint(ALLOC_IN_RC(ptr_reg));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3963 match(AddP (DecodeN reg) off);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3964
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3965 format %{ "[$reg + $off (32-bit)]" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3966 interface(MEMORY_INTER) %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3967 base($reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3968 index(0x4);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3969 scale(0x0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3970 disp($off);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3971 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3972 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3973
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3974 // Indirect Memory Plus Index Register Plus Offset Operand
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3975 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3976 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3977 predicate(Universe::narrow_oop_shift() == 0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3978 constraint(ALLOC_IN_RC(ptr_reg));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3979 match(AddP (AddP (DecodeN reg) lreg) off);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3980
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3981 op_cost(10);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3982 format %{"[$reg + $off + $lreg]" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3983 interface(MEMORY_INTER) %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3984 base($reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3985 index($lreg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3986 scale(0x0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3987 disp($off);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3988 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3989 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3990
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3991 // Indirect Memory Plus Index Register Plus Offset Operand
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3992 operand indIndexNarrow(rRegN reg, rRegL lreg)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3993 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3994 predicate(Universe::narrow_oop_shift() == 0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3995 constraint(ALLOC_IN_RC(ptr_reg));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3996 match(AddP (DecodeN reg) lreg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3997
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3998 op_cost(10);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3999 format %{"[$reg + $lreg]" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4000 interface(MEMORY_INTER) %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4001 base($reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4002 index($lreg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4003 scale(0x0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4004 disp(0x0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4005 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4006 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4007
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4008 // Indirect Memory Times Scale Plus Index Register
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4009 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4010 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4011 predicate(Universe::narrow_oop_shift() == 0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4012 constraint(ALLOC_IN_RC(ptr_reg));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4013 match(AddP (DecodeN reg) (LShiftL lreg scale));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4014
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4015 op_cost(10);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4016 format %{"[$reg + $lreg << $scale]" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4017 interface(MEMORY_INTER) %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4018 base($reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4019 index($lreg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4020 scale($scale);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4021 disp(0x0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4022 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4023 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4024
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4025 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4026 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4027 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4028 predicate(Universe::narrow_oop_shift() == 0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4029 constraint(ALLOC_IN_RC(ptr_reg));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4030 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4031
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4032 op_cost(10);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4033 format %{"[$reg + $off + $lreg << $scale]" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4034 interface(MEMORY_INTER) %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4035 base($reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4036 index($lreg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4037 scale($scale);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4038 disp($off);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4039 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4040 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4041
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4042 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4043 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4044 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4045 constraint(ALLOC_IN_RC(ptr_reg));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4046 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4047 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4048
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4049 op_cost(10);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4050 format %{"[$reg + $off + $idx << $scale]" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4051 interface(MEMORY_INTER) %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4052 base($reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4053 index($idx);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4054 scale($scale);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4055 disp($off);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4056 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4057 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4058
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4059
0
a61af66fc99e Initial load
duke
parents:
diff changeset
4060 //----------Special Memory Operands--------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
4061 // Stack Slot Operand - This operand is used for loading and storing temporary
a61af66fc99e Initial load
duke
parents:
diff changeset
4062 // values on the stack where a match requires a value to
a61af66fc99e Initial load
duke
parents:
diff changeset
4063 // flow through memory.
a61af66fc99e Initial load
duke
parents:
diff changeset
4064 operand stackSlotP(sRegP reg)
a61af66fc99e Initial load
duke
parents:
diff changeset
4065 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4066 constraint(ALLOC_IN_RC(stack_slots));
a61af66fc99e Initial load
duke
parents:
diff changeset
4067 // No match rule because this operand is only generated in matching
a61af66fc99e Initial load
duke
parents:
diff changeset
4068
a61af66fc99e Initial load
duke
parents:
diff changeset
4069 format %{ "[$reg]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4070 interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4071 base(0x4); // RSP
a61af66fc99e Initial load
duke
parents:
diff changeset
4072 index(0x4); // No Index
a61af66fc99e Initial load
duke
parents:
diff changeset
4073 scale(0x0); // No Scale
a61af66fc99e Initial load
duke
parents:
diff changeset
4074 disp($reg); // Stack Offset
a61af66fc99e Initial load
duke
parents:
diff changeset
4075 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4076 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4077
a61af66fc99e Initial load
duke
parents:
diff changeset
4078 operand stackSlotI(sRegI reg)
a61af66fc99e Initial load
duke
parents:
diff changeset
4079 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4080 constraint(ALLOC_IN_RC(stack_slots));
a61af66fc99e Initial load
duke
parents:
diff changeset
4081 // No match rule because this operand is only generated in matching
a61af66fc99e Initial load
duke
parents:
diff changeset
4082
a61af66fc99e Initial load
duke
parents:
diff changeset
4083 format %{ "[$reg]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4084 interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4085 base(0x4); // RSP
a61af66fc99e Initial load
duke
parents:
diff changeset
4086 index(0x4); // No Index
a61af66fc99e Initial load
duke
parents:
diff changeset
4087 scale(0x0); // No Scale
a61af66fc99e Initial load
duke
parents:
diff changeset
4088 disp($reg); // Stack Offset
a61af66fc99e Initial load
duke
parents:
diff changeset
4089 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4090 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4091
a61af66fc99e Initial load
duke
parents:
diff changeset
4092 operand stackSlotF(sRegF reg)
a61af66fc99e Initial load
duke
parents:
diff changeset
4093 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4094 constraint(ALLOC_IN_RC(stack_slots));
a61af66fc99e Initial load
duke
parents:
diff changeset
4095 // No match rule because this operand is only generated in matching
a61af66fc99e Initial load
duke
parents:
diff changeset
4096
a61af66fc99e Initial load
duke
parents:
diff changeset
4097 format %{ "[$reg]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4098 interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4099 base(0x4); // RSP
a61af66fc99e Initial load
duke
parents:
diff changeset
4100 index(0x4); // No Index
a61af66fc99e Initial load
duke
parents:
diff changeset
4101 scale(0x0); // No Scale
a61af66fc99e Initial load
duke
parents:
diff changeset
4102 disp($reg); // Stack Offset
a61af66fc99e Initial load
duke
parents:
diff changeset
4103 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4104 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4105
a61af66fc99e Initial load
duke
parents:
diff changeset
4106 operand stackSlotD(sRegD reg)
a61af66fc99e Initial load
duke
parents:
diff changeset
4107 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4108 constraint(ALLOC_IN_RC(stack_slots));
a61af66fc99e Initial load
duke
parents:
diff changeset
4109 // No match rule because this operand is only generated in matching
a61af66fc99e Initial load
duke
parents:
diff changeset
4110
a61af66fc99e Initial load
duke
parents:
diff changeset
4111 format %{ "[$reg]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4112 interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4113 base(0x4); // RSP
a61af66fc99e Initial load
duke
parents:
diff changeset
4114 index(0x4); // No Index
a61af66fc99e Initial load
duke
parents:
diff changeset
4115 scale(0x0); // No Scale
a61af66fc99e Initial load
duke
parents:
diff changeset
4116 disp($reg); // Stack Offset
a61af66fc99e Initial load
duke
parents:
diff changeset
4117 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4118 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4119 operand stackSlotL(sRegL reg)
a61af66fc99e Initial load
duke
parents:
diff changeset
4120 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4121 constraint(ALLOC_IN_RC(stack_slots));
a61af66fc99e Initial load
duke
parents:
diff changeset
4122 // No match rule because this operand is only generated in matching
a61af66fc99e Initial load
duke
parents:
diff changeset
4123
a61af66fc99e Initial load
duke
parents:
diff changeset
4124 format %{ "[$reg]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4125 interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4126 base(0x4); // RSP
a61af66fc99e Initial load
duke
parents:
diff changeset
4127 index(0x4); // No Index
a61af66fc99e Initial load
duke
parents:
diff changeset
4128 scale(0x0); // No Scale
a61af66fc99e Initial load
duke
parents:
diff changeset
4129 disp($reg); // Stack Offset
a61af66fc99e Initial load
duke
parents:
diff changeset
4130 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4131 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4132
a61af66fc99e Initial load
duke
parents:
diff changeset
4133 //----------Conditional Branch Operands----------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
4134 // Comparison Op - This is the operation of the comparison, and is limited to
a61af66fc99e Initial load
duke
parents:
diff changeset
4135 // the following set of codes:
a61af66fc99e Initial load
duke
parents:
diff changeset
4136 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
a61af66fc99e Initial load
duke
parents:
diff changeset
4137 //
a61af66fc99e Initial load
duke
parents:
diff changeset
4138 // Other attributes of the comparison, such as unsignedness, are specified
a61af66fc99e Initial load
duke
parents:
diff changeset
4139 // by the comparison instruction that sets a condition code flags register.
a61af66fc99e Initial load
duke
parents:
diff changeset
4140 // That result is represented by a flags operand whose subtype is appropriate
a61af66fc99e Initial load
duke
parents:
diff changeset
4141 // to the unsignedness (etc.) of the comparison.
a61af66fc99e Initial load
duke
parents:
diff changeset
4142 //
a61af66fc99e Initial load
duke
parents:
diff changeset
4143 // Later, the instruction which matches both the Comparison Op (a Bool) and
a61af66fc99e Initial load
duke
parents:
diff changeset
4144 // the flags (produced by the Cmp) specifies the coding of the comparison op
a61af66fc99e Initial load
duke
parents:
diff changeset
4145 // by matching a specific subtype of Bool operand below, such as cmpOpU.
a61af66fc99e Initial load
duke
parents:
diff changeset
4146
a61af66fc99e Initial load
duke
parents:
diff changeset
4147 // Comparision Code
a61af66fc99e Initial load
duke
parents:
diff changeset
4148 operand cmpOp()
a61af66fc99e Initial load
duke
parents:
diff changeset
4149 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4150 match(Bool);
a61af66fc99e Initial load
duke
parents:
diff changeset
4151
a61af66fc99e Initial load
duke
parents:
diff changeset
4152 format %{ "" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4153 interface(COND_INTER) %{
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4154 equal(0x4, "e");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4155 not_equal(0x5, "ne");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4156 less(0xC, "l");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4157 greater_equal(0xD, "ge");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4158 less_equal(0xE, "le");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4159 greater(0xF, "g");
0
a61af66fc99e Initial load
duke
parents:
diff changeset
4160 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4161 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4162
a61af66fc99e Initial load
duke
parents:
diff changeset
4163 // Comparison Code, unsigned compare. Used by FP also, with
a61af66fc99e Initial load
duke
parents:
diff changeset
4164 // C2 (unordered) turned into GT or LT already. The other bits
a61af66fc99e Initial load
duke
parents:
diff changeset
4165 // C0 and C3 are turned into Carry & Zero flags.
a61af66fc99e Initial load
duke
parents:
diff changeset
4166 operand cmpOpU()
a61af66fc99e Initial load
duke
parents:
diff changeset
4167 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4168 match(Bool);
a61af66fc99e Initial load
duke
parents:
diff changeset
4169
a61af66fc99e Initial load
duke
parents:
diff changeset
4170 format %{ "" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4171 interface(COND_INTER) %{
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4172 equal(0x4, "e");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4173 not_equal(0x5, "ne");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4174 less(0x2, "b");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4175 greater_equal(0x3, "nb");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4176 less_equal(0x6, "be");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4177 greater(0x7, "nbe");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4178 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4179 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4180
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4181
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4182 // Floating comparisons that don't require any fixup for the unordered case
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4183 operand cmpOpUCF() %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4184 match(Bool);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4185 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4186 n->as_Bool()->_test._test == BoolTest::ge ||
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4187 n->as_Bool()->_test._test == BoolTest::le ||
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4188 n->as_Bool()->_test._test == BoolTest::gt);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4189 format %{ "" %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4190 interface(COND_INTER) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4191 equal(0x4, "e");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4192 not_equal(0x5, "ne");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4193 less(0x2, "b");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4194 greater_equal(0x3, "nb");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4195 less_equal(0x6, "be");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4196 greater(0x7, "nbe");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4197 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4198 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4199
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4200
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4201 // Floating comparisons that can be fixed up with extra conditional jumps
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4202 operand cmpOpUCF2() %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4203 match(Bool);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4204 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4205 n->as_Bool()->_test._test == BoolTest::eq);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4206 format %{ "" %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4207 interface(COND_INTER) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4208 equal(0x4, "e");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4209 not_equal(0x5, "ne");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4210 less(0x2, "b");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4211 greater_equal(0x3, "nb");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4212 less_equal(0x6, "be");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4213 greater(0x7, "nbe");
0
a61af66fc99e Initial load
duke
parents:
diff changeset
4214 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4215 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4216
a61af66fc99e Initial load
duke
parents:
diff changeset
4217
a61af66fc99e Initial load
duke
parents:
diff changeset
4218 //----------OPERAND CLASSES----------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
4219 // Operand Classes are groups of operands that are used as to simplify
605
98cb887364d3 6810672: Comment typos
twisti
parents: 569
diff changeset
4220 // instruction definitions by not requiring the AD writer to specify separate
0
a61af66fc99e Initial load
duke
parents:
diff changeset
4221 // instructions for every form of operand when the instruction accepts
a61af66fc99e Initial load
duke
parents:
diff changeset
4222 // multiple operand types with the same basic encoding and format. The classic
a61af66fc99e Initial load
duke
parents:
diff changeset
4223 // case of this is memory operands.
a61af66fc99e Initial load
duke
parents:
diff changeset
4224
a61af66fc99e Initial load
duke
parents:
diff changeset
4225 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
4226 indIndexScale, indIndexScaleOffset, indPosIndexScaleOffset,
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4227 indCompressedOopOffset,
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4228 indirectNarrow, indOffset8Narrow, indOffset32Narrow,
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4229 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4230 indIndexScaleOffsetNarrow, indPosIndexScaleOffsetNarrow);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
4231
a61af66fc99e Initial load
duke
parents:
diff changeset
4232 //----------PIPELINE-----------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
4233 // Rules which define the behavior of the target architectures pipeline.
a61af66fc99e Initial load
duke
parents:
diff changeset
4234 pipeline %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4235
a61af66fc99e Initial load
duke
parents:
diff changeset
4236 //----------ATTRIBUTES---------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
4237 attributes %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4238 variable_size_instructions; // Fixed size instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
4239 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
a61af66fc99e Initial load
duke
parents:
diff changeset
4240 instruction_unit_size = 1; // An instruction is 1 bytes long
a61af66fc99e Initial load
duke
parents:
diff changeset
4241 instruction_fetch_unit_size = 16; // The processor fetches one line
a61af66fc99e Initial load
duke
parents:
diff changeset
4242 instruction_fetch_units = 1; // of 16 bytes
a61af66fc99e Initial load
duke
parents:
diff changeset
4243
a61af66fc99e Initial load
duke
parents:
diff changeset
4244 // List of nop instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
4245 nops( MachNop );
a61af66fc99e Initial load
duke
parents:
diff changeset
4246 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4247
a61af66fc99e Initial load
duke
parents:
diff changeset
4248 //----------RESOURCES----------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
4249 // Resources are the functional units available to the machine
a61af66fc99e Initial load
duke
parents:
diff changeset
4250
a61af66fc99e Initial load
duke
parents:
diff changeset
4251 // Generic P2/P3 pipeline
a61af66fc99e Initial load
duke
parents:
diff changeset
4252 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
a61af66fc99e Initial load
duke
parents:
diff changeset
4253 // 3 instructions decoded per cycle.
a61af66fc99e Initial load
duke
parents:
diff changeset
4254 // 2 load/store ops per cycle, 1 branch, 1 FPU,
a61af66fc99e Initial load
duke
parents:
diff changeset
4255 // 3 ALU op, only ALU0 handles mul instructions.
a61af66fc99e Initial load
duke
parents:
diff changeset
4256 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
a61af66fc99e Initial load
duke
parents:
diff changeset
4257 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
a61af66fc99e Initial load
duke
parents:
diff changeset
4258 BR, FPU,
a61af66fc99e Initial load
duke
parents:
diff changeset
4259 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4260
a61af66fc99e Initial load
duke
parents:
diff changeset
4261 //----------PIPELINE DESCRIPTION-----------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
4262 // Pipeline Description specifies the stages in the machine's pipeline
a61af66fc99e Initial load
duke
parents:
diff changeset
4263
a61af66fc99e Initial load
duke
parents:
diff changeset
4264 // Generic P2/P3 pipeline
a61af66fc99e Initial load
duke
parents:
diff changeset
4265 pipe_desc(S0, S1, S2, S3, S4, S5);
a61af66fc99e Initial load
duke
parents:
diff changeset
4266
a61af66fc99e Initial load
duke
parents:
diff changeset
4267 //----------PIPELINE CLASSES---------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
4268 // Pipeline Classes describe the stages in which input and output are
a61af66fc99e Initial load
duke
parents:
diff changeset
4269 // referenced by the hardware pipeline.
a61af66fc99e Initial load
duke
parents:
diff changeset
4270
a61af66fc99e Initial load
duke
parents:
diff changeset
4271 // Naming convention: ialu or fpu
a61af66fc99e Initial load
duke
parents:
diff changeset
4272 // Then: _reg
a61af66fc99e Initial load
duke
parents:
diff changeset
4273 // Then: _reg if there is a 2nd register
a61af66fc99e Initial load
duke
parents:
diff changeset
4274 // Then: _long if it's a pair of instructions implementing a long
a61af66fc99e Initial load
duke
parents:
diff changeset
4275 // Then: _fat if it requires the big decoder
a61af66fc99e Initial load
duke
parents:
diff changeset
4276 // Or: _mem if it requires the big decoder and a memory unit.
a61af66fc99e Initial load
duke
parents:
diff changeset
4277
a61af66fc99e Initial load
duke
parents:
diff changeset
4278 // Integer ALU reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4279 pipe_class ialu_reg(rRegI dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
4280 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4281 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4282 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4283 dst : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4284 DECODE : S0; // any decoder
a61af66fc99e Initial load
duke
parents:
diff changeset
4285 ALU : S3; // any alu
a61af66fc99e Initial load
duke
parents:
diff changeset
4286 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4287
a61af66fc99e Initial load
duke
parents:
diff changeset
4288 // Long ALU reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4289 pipe_class ialu_reg_long(rRegL dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
4290 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4291 instruction_count(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4292 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4293 dst : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4294 DECODE : S0(2); // any 2 decoders
a61af66fc99e Initial load
duke
parents:
diff changeset
4295 ALU : S3(2); // both alus
a61af66fc99e Initial load
duke
parents:
diff changeset
4296 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4297
a61af66fc99e Initial load
duke
parents:
diff changeset
4298 // Integer ALU reg operation using big decoder
a61af66fc99e Initial load
duke
parents:
diff changeset
4299 pipe_class ialu_reg_fat(rRegI dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
4300 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4301 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4302 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4303 dst : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4304 D0 : S0; // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
4305 ALU : S3; // any alu
a61af66fc99e Initial load
duke
parents:
diff changeset
4306 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4307
a61af66fc99e Initial load
duke
parents:
diff changeset
4308 // Long ALU reg operation using big decoder
a61af66fc99e Initial load
duke
parents:
diff changeset
4309 pipe_class ialu_reg_long_fat(rRegL dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
4310 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4311 instruction_count(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4312 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4313 dst : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4314 D0 : S0(2); // big decoder only; twice
a61af66fc99e Initial load
duke
parents:
diff changeset
4315 ALU : S3(2); // any 2 alus
a61af66fc99e Initial load
duke
parents:
diff changeset
4316 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4317
a61af66fc99e Initial load
duke
parents:
diff changeset
4318 // Integer ALU reg-reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4319 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
4320 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4321 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4322 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4323 src : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4324 DECODE : S0; // any decoder
a61af66fc99e Initial load
duke
parents:
diff changeset
4325 ALU : S3; // any alu
a61af66fc99e Initial load
duke
parents:
diff changeset
4326 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4327
a61af66fc99e Initial load
duke
parents:
diff changeset
4328 // Long ALU reg-reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4329 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
4330 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4331 instruction_count(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4332 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4333 src : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4334 DECODE : S0(2); // any 2 decoders
a61af66fc99e Initial load
duke
parents:
diff changeset
4335 ALU : S3(2); // both alus
a61af66fc99e Initial load
duke
parents:
diff changeset
4336 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4337
a61af66fc99e Initial load
duke
parents:
diff changeset
4338 // Integer ALU reg-reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4339 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
4340 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4341 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4342 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4343 src : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4344 D0 : S0; // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
4345 ALU : S3; // any alu
a61af66fc99e Initial load
duke
parents:
diff changeset
4346 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4347
a61af66fc99e Initial load
duke
parents:
diff changeset
4348 // Long ALU reg-reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4349 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
4350 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4351 instruction_count(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4352 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4353 src : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4354 D0 : S0(2); // big decoder only; twice
a61af66fc99e Initial load
duke
parents:
diff changeset
4355 ALU : S3(2); // both alus
a61af66fc99e Initial load
duke
parents:
diff changeset
4356 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4357
a61af66fc99e Initial load
duke
parents:
diff changeset
4358 // Integer ALU reg-mem operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4359 pipe_class ialu_reg_mem(rRegI dst, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
4360 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4361 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4362 dst : S5(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4363 mem : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4364 D0 : S0; // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
4365 ALU : S4; // any alu
a61af66fc99e Initial load
duke
parents:
diff changeset
4366 MEM : S3; // any mem
a61af66fc99e Initial load
duke
parents:
diff changeset
4367 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4368
a61af66fc99e Initial load
duke
parents:
diff changeset
4369 // Integer mem operation (prefetch)
a61af66fc99e Initial load
duke
parents:
diff changeset
4370 pipe_class ialu_mem(memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
4371 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4372 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4373 mem : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4374 D0 : S0; // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
4375 MEM : S3; // any mem
a61af66fc99e Initial load
duke
parents:
diff changeset
4376 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4377
a61af66fc99e Initial load
duke
parents:
diff changeset
4378 // Integer Store to Memory
a61af66fc99e Initial load
duke
parents:
diff changeset
4379 pipe_class ialu_mem_reg(memory mem, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
4380 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4381 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4382 mem : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4383 src : S5(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4384 D0 : S0; // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
4385 ALU : S4; // any alu
a61af66fc99e Initial load
duke
parents:
diff changeset
4386 MEM : S3;
a61af66fc99e Initial load
duke
parents:
diff changeset
4387 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4388
a61af66fc99e Initial load
duke
parents:
diff changeset
4389 // // Long Store to Memory
a61af66fc99e Initial load
duke
parents:
diff changeset
4390 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
4391 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4392 // instruction_count(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4393 // mem : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4394 // src : S5(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4395 // D0 : S0(2); // big decoder only; twice
a61af66fc99e Initial load
duke
parents:
diff changeset
4396 // ALU : S4(2); // any 2 alus
a61af66fc99e Initial load
duke
parents:
diff changeset
4397 // MEM : S3(2); // Both mems
a61af66fc99e Initial load
duke
parents:
diff changeset
4398 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4399
a61af66fc99e Initial load
duke
parents:
diff changeset
4400 // Integer Store to Memory
a61af66fc99e Initial load
duke
parents:
diff changeset
4401 pipe_class ialu_mem_imm(memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
4402 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4403 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4404 mem : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4405 D0 : S0; // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
4406 ALU : S4; // any alu
a61af66fc99e Initial load
duke
parents:
diff changeset
4407 MEM : S3;
a61af66fc99e Initial load
duke
parents:
diff changeset
4408 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4409
a61af66fc99e Initial load
duke
parents:
diff changeset
4410 // Integer ALU0 reg-reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4411 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
4412 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4413 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4414 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4415 src : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4416 D0 : S0; // Big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
4417 ALU0 : S3; // only alu0
a61af66fc99e Initial load
duke
parents:
diff changeset
4418 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4419
a61af66fc99e Initial load
duke
parents:
diff changeset
4420 // Integer ALU0 reg-mem operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4421 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
4422 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4423 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4424 dst : S5(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4425 mem : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4426 D0 : S0; // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
4427 ALU0 : S4; // ALU0 only
a61af66fc99e Initial load
duke
parents:
diff changeset
4428 MEM : S3; // any mem
a61af66fc99e Initial load
duke
parents:
diff changeset
4429 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4430
a61af66fc99e Initial load
duke
parents:
diff changeset
4431 // Integer ALU reg-reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4432 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
a61af66fc99e Initial load
duke
parents:
diff changeset
4433 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4434 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4435 cr : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4436 src1 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4437 src2 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4438 DECODE : S0; // any decoder
a61af66fc99e Initial load
duke
parents:
diff changeset
4439 ALU : S3; // any alu
a61af66fc99e Initial load
duke
parents:
diff changeset
4440 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4441
a61af66fc99e Initial load
duke
parents:
diff changeset
4442 // Integer ALU reg-imm operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4443 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
a61af66fc99e Initial load
duke
parents:
diff changeset
4444 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4445 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4446 cr : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4447 src1 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4448 DECODE : S0; // any decoder
a61af66fc99e Initial load
duke
parents:
diff changeset
4449 ALU : S3; // any alu
a61af66fc99e Initial load
duke
parents:
diff changeset
4450 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4451
a61af66fc99e Initial load
duke
parents:
diff changeset
4452 // Integer ALU reg-mem operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4453 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
a61af66fc99e Initial load
duke
parents:
diff changeset
4454 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4455 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4456 cr : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4457 src1 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4458 src2 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4459 D0 : S0; // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
4460 ALU : S4; // any alu
a61af66fc99e Initial load
duke
parents:
diff changeset
4461 MEM : S3;
a61af66fc99e Initial load
duke
parents:
diff changeset
4462 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4463
a61af66fc99e Initial load
duke
parents:
diff changeset
4464 // Conditional move reg-reg
a61af66fc99e Initial load
duke
parents:
diff changeset
4465 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
a61af66fc99e Initial load
duke
parents:
diff changeset
4466 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4467 instruction_count(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
4468 y : S4(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4469 q : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4470 p : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4471 DECODE : S0(4); // any decoder
a61af66fc99e Initial load
duke
parents:
diff changeset
4472 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4473
a61af66fc99e Initial load
duke
parents:
diff changeset
4474 // Conditional move reg-reg
a61af66fc99e Initial load
duke
parents:
diff changeset
4475 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
4476 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4477 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4478 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4479 src : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4480 cr : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4481 DECODE : S0; // any decoder
a61af66fc99e Initial load
duke
parents:
diff changeset
4482 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4483
a61af66fc99e Initial load
duke
parents:
diff changeset
4484 // Conditional move reg-mem
a61af66fc99e Initial load
duke
parents:
diff changeset
4485 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
4486 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4487 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4488 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4489 src : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4490 cr : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4491 DECODE : S0; // any decoder
a61af66fc99e Initial load
duke
parents:
diff changeset
4492 MEM : S3;
a61af66fc99e Initial load
duke
parents:
diff changeset
4493 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4494
a61af66fc99e Initial load
duke
parents:
diff changeset
4495 // Conditional move reg-reg long
a61af66fc99e Initial load
duke
parents:
diff changeset
4496 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
4497 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4498 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4499 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4500 src : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4501 cr : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4502 DECODE : S0(2); // any 2 decoders
a61af66fc99e Initial load
duke
parents:
diff changeset
4503 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4504
a61af66fc99e Initial load
duke
parents:
diff changeset
4505 // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
4506 // // Conditional move double reg-reg
a61af66fc99e Initial load
duke
parents:
diff changeset
4507 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src)
a61af66fc99e Initial load
duke
parents:
diff changeset
4508 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4509 // single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4510 // dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4511 // src : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4512 // cr : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4513 // DECODE : S0; // any decoder
a61af66fc99e Initial load
duke
parents:
diff changeset
4514 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4515
a61af66fc99e Initial load
duke
parents:
diff changeset
4516 // Float reg-reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4517 pipe_class fpu_reg(regD dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
4518 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4519 instruction_count(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4520 dst : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4521 DECODE : S0(2); // any 2 decoders
a61af66fc99e Initial load
duke
parents:
diff changeset
4522 FPU : S3;
a61af66fc99e Initial load
duke
parents:
diff changeset
4523 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4524
a61af66fc99e Initial load
duke
parents:
diff changeset
4525 // Float reg-reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4526 pipe_class fpu_reg_reg(regD dst, regD src)
a61af66fc99e Initial load
duke
parents:
diff changeset
4527 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4528 instruction_count(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4529 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4530 src : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4531 DECODE : S0(2); // any 2 decoders
a61af66fc99e Initial load
duke
parents:
diff changeset
4532 FPU : S3;
a61af66fc99e Initial load
duke
parents:
diff changeset
4533 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4534
a61af66fc99e Initial load
duke
parents:
diff changeset
4535 // Float reg-reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4536 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
a61af66fc99e Initial load
duke
parents:
diff changeset
4537 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4538 instruction_count(3);
a61af66fc99e Initial load
duke
parents:
diff changeset
4539 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4540 src1 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4541 src2 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4542 DECODE : S0(3); // any 3 decoders
a61af66fc99e Initial load
duke
parents:
diff changeset
4543 FPU : S3(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4544 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4545
a61af66fc99e Initial load
duke
parents:
diff changeset
4546 // Float reg-reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4547 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
a61af66fc99e Initial load
duke
parents:
diff changeset
4548 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4549 instruction_count(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
4550 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4551 src1 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4552 src2 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4553 src3 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4554 DECODE : S0(4); // any 3 decoders
a61af66fc99e Initial load
duke
parents:
diff changeset
4555 FPU : S3(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4556 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4557
a61af66fc99e Initial load
duke
parents:
diff changeset
4558 // Float reg-reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4559 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
a61af66fc99e Initial load
duke
parents:
diff changeset
4560 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4561 instruction_count(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
4562 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4563 src1 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4564 src2 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4565 src3 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4566 DECODE : S1(3); // any 3 decoders
a61af66fc99e Initial load
duke
parents:
diff changeset
4567 D0 : S0; // Big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
4568 FPU : S3(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4569 MEM : S3;
a61af66fc99e Initial load
duke
parents:
diff changeset
4570 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4571
a61af66fc99e Initial load
duke
parents:
diff changeset
4572 // Float reg-mem operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4573 pipe_class fpu_reg_mem(regD dst, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
4574 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4575 instruction_count(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4576 dst : S5(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4577 mem : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4578 D0 : S0; // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
4579 DECODE : S1; // any decoder for FPU POP
a61af66fc99e Initial load
duke
parents:
diff changeset
4580 FPU : S4;
a61af66fc99e Initial load
duke
parents:
diff changeset
4581 MEM : S3; // any mem
a61af66fc99e Initial load
duke
parents:
diff changeset
4582 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4583
a61af66fc99e Initial load
duke
parents:
diff changeset
4584 // Float reg-mem operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4585 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
4586 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4587 instruction_count(3);
a61af66fc99e Initial load
duke
parents:
diff changeset
4588 dst : S5(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4589 src1 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4590 mem : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4591 D0 : S0; // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
4592 DECODE : S1(2); // any decoder for FPU POP
a61af66fc99e Initial load
duke
parents:
diff changeset
4593 FPU : S4;
a61af66fc99e Initial load
duke
parents:
diff changeset
4594 MEM : S3; // any mem
a61af66fc99e Initial load
duke
parents:
diff changeset
4595 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4596
a61af66fc99e Initial load
duke
parents:
diff changeset
4597 // Float mem-reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4598 pipe_class fpu_mem_reg(memory mem, regD src)
a61af66fc99e Initial load
duke
parents:
diff changeset
4599 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4600 instruction_count(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4601 src : S5(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4602 mem : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4603 DECODE : S0; // any decoder for FPU PUSH
a61af66fc99e Initial load
duke
parents:
diff changeset
4604 D0 : S1; // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
4605 FPU : S4;
a61af66fc99e Initial load
duke
parents:
diff changeset
4606 MEM : S3; // any mem
a61af66fc99e Initial load
duke
parents:
diff changeset
4607 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4608
a61af66fc99e Initial load
duke
parents:
diff changeset
4609 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
a61af66fc99e Initial load
duke
parents:
diff changeset
4610 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4611 instruction_count(3);
a61af66fc99e Initial load
duke
parents:
diff changeset
4612 src1 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4613 src2 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4614 mem : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4615 DECODE : S0(2); // any decoder for FPU PUSH
a61af66fc99e Initial load
duke
parents:
diff changeset
4616 D0 : S1; // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
4617 FPU : S4;
a61af66fc99e Initial load
duke
parents:
diff changeset
4618 MEM : S3; // any mem
a61af66fc99e Initial load
duke
parents:
diff changeset
4619 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4620
a61af66fc99e Initial load
duke
parents:
diff changeset
4621 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
a61af66fc99e Initial load
duke
parents:
diff changeset
4622 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4623 instruction_count(3);
a61af66fc99e Initial load
duke
parents:
diff changeset
4624 src1 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4625 src2 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4626 mem : S4(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4627 DECODE : S0; // any decoder for FPU PUSH
a61af66fc99e Initial load
duke
parents:
diff changeset
4628 D0 : S0(2); // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
4629 FPU : S4;
a61af66fc99e Initial load
duke
parents:
diff changeset
4630 MEM : S3(2); // any mem
a61af66fc99e Initial load
duke
parents:
diff changeset
4631 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4632
a61af66fc99e Initial load
duke
parents:
diff changeset
4633 pipe_class fpu_mem_mem(memory dst, memory src1)
a61af66fc99e Initial load
duke
parents:
diff changeset
4634 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4635 instruction_count(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4636 src1 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4637 dst : S4(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4638 D0 : S0(2); // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
4639 MEM : S3(2); // any mem
a61af66fc99e Initial load
duke
parents:
diff changeset
4640 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4641
a61af66fc99e Initial load
duke
parents:
diff changeset
4642 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
a61af66fc99e Initial load
duke
parents:
diff changeset
4643 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4644 instruction_count(3);
a61af66fc99e Initial load
duke
parents:
diff changeset
4645 src1 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4646 src2 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4647 dst : S4(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4648 D0 : S0(3); // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
4649 FPU : S4;
a61af66fc99e Initial load
duke
parents:
diff changeset
4650 MEM : S3(3); // any mem
a61af66fc99e Initial load
duke
parents:
diff changeset
4651 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4652
a61af66fc99e Initial load
duke
parents:
diff changeset
4653 pipe_class fpu_mem_reg_con(memory mem, regD src1)
a61af66fc99e Initial load
duke
parents:
diff changeset
4654 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4655 instruction_count(3);
a61af66fc99e Initial load
duke
parents:
diff changeset
4656 src1 : S4(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4657 mem : S4(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4658 DECODE : S0; // any decoder for FPU PUSH
a61af66fc99e Initial load
duke
parents:
diff changeset
4659 D0 : S0(2); // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
4660 FPU : S4;
a61af66fc99e Initial load
duke
parents:
diff changeset
4661 MEM : S3(2); // any mem
a61af66fc99e Initial load
duke
parents:
diff changeset
4662 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4663
a61af66fc99e Initial load
duke
parents:
diff changeset
4664 // Float load constant
a61af66fc99e Initial load
duke
parents:
diff changeset
4665 pipe_class fpu_reg_con(regD dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
4666 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4667 instruction_count(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4668 dst : S5(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4669 D0 : S0; // big decoder only for the load
a61af66fc99e Initial load
duke
parents:
diff changeset
4670 DECODE : S1; // any decoder for FPU POP
a61af66fc99e Initial load
duke
parents:
diff changeset
4671 FPU : S4;
a61af66fc99e Initial load
duke
parents:
diff changeset
4672 MEM : S3; // any mem
a61af66fc99e Initial load
duke
parents:
diff changeset
4673 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4674
a61af66fc99e Initial load
duke
parents:
diff changeset
4675 // Float load constant
a61af66fc99e Initial load
duke
parents:
diff changeset
4676 pipe_class fpu_reg_reg_con(regD dst, regD src)
a61af66fc99e Initial load
duke
parents:
diff changeset
4677 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4678 instruction_count(3);
a61af66fc99e Initial load
duke
parents:
diff changeset
4679 dst : S5(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4680 src : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4681 D0 : S0; // big decoder only for the load
a61af66fc99e Initial load
duke
parents:
diff changeset
4682 DECODE : S1(2); // any decoder for FPU POP
a61af66fc99e Initial load
duke
parents:
diff changeset
4683 FPU : S4;
a61af66fc99e Initial load
duke
parents:
diff changeset
4684 MEM : S3; // any mem
a61af66fc99e Initial load
duke
parents:
diff changeset
4685 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4686
a61af66fc99e Initial load
duke
parents:
diff changeset
4687 // UnConditional branch
a61af66fc99e Initial load
duke
parents:
diff changeset
4688 pipe_class pipe_jmp(label labl)
a61af66fc99e Initial load
duke
parents:
diff changeset
4689 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4690 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4691 BR : S3;
a61af66fc99e Initial load
duke
parents:
diff changeset
4692 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4693
a61af66fc99e Initial load
duke
parents:
diff changeset
4694 // Conditional branch
a61af66fc99e Initial load
duke
parents:
diff changeset
4695 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
a61af66fc99e Initial load
duke
parents:
diff changeset
4696 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4697 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4698 cr : S1(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4699 BR : S3;
a61af66fc99e Initial load
duke
parents:
diff changeset
4700 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4701
a61af66fc99e Initial load
duke
parents:
diff changeset
4702 // Allocation idiom
a61af66fc99e Initial load
duke
parents:
diff changeset
4703 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
a61af66fc99e Initial load
duke
parents:
diff changeset
4704 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4705 instruction_count(1); force_serialization;
a61af66fc99e Initial load
duke
parents:
diff changeset
4706 fixed_latency(6);
a61af66fc99e Initial load
duke
parents:
diff changeset
4707 heap_ptr : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4708 DECODE : S0(3);
a61af66fc99e Initial load
duke
parents:
diff changeset
4709 D0 : S2;
a61af66fc99e Initial load
duke
parents:
diff changeset
4710 MEM : S3;
a61af66fc99e Initial load
duke
parents:
diff changeset
4711 ALU : S3(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4712 dst : S5(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4713 BR : S5;
a61af66fc99e Initial load
duke
parents:
diff changeset
4714 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4715
a61af66fc99e Initial load
duke
parents:
diff changeset
4716 // Generic big/slow expanded idiom
a61af66fc99e Initial load
duke
parents:
diff changeset
4717 pipe_class pipe_slow()
a61af66fc99e Initial load
duke
parents:
diff changeset
4718 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4719 instruction_count(10); multiple_bundles; force_serialization;
a61af66fc99e Initial load
duke
parents:
diff changeset
4720 fixed_latency(100);
a61af66fc99e Initial load
duke
parents:
diff changeset
4721 D0 : S0(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4722 MEM : S3(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4723 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4724
a61af66fc99e Initial load
duke
parents:
diff changeset
4725 // The real do-nothing guy
a61af66fc99e Initial load
duke
parents:
diff changeset
4726 pipe_class empty()
a61af66fc99e Initial load
duke
parents:
diff changeset
4727 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4728 instruction_count(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
4729 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4730
a61af66fc99e Initial load
duke
parents:
diff changeset
4731 // Define the class for the Nop node
a61af66fc99e Initial load
duke
parents:
diff changeset
4732 define
a61af66fc99e Initial load
duke
parents:
diff changeset
4733 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4734 MachNop = empty;
a61af66fc99e Initial load
duke
parents:
diff changeset
4735 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4736
a61af66fc99e Initial load
duke
parents:
diff changeset
4737 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4738
a61af66fc99e Initial load
duke
parents:
diff changeset
4739 //----------INSTRUCTIONS-------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
4740 //
a61af66fc99e Initial load
duke
parents:
diff changeset
4741 // match -- States which machine-independent subtree may be replaced
a61af66fc99e Initial load
duke
parents:
diff changeset
4742 // by this instruction.
a61af66fc99e Initial load
duke
parents:
diff changeset
4743 // ins_cost -- The estimated cost of this instruction is used by instruction
a61af66fc99e Initial load
duke
parents:
diff changeset
4744 // selection to identify a minimum cost tree of machine
a61af66fc99e Initial load
duke
parents:
diff changeset
4745 // instructions that matches a tree of machine-independent
a61af66fc99e Initial load
duke
parents:
diff changeset
4746 // instructions.
a61af66fc99e Initial load
duke
parents:
diff changeset
4747 // format -- A string providing the disassembly for this instruction.
a61af66fc99e Initial load
duke
parents:
diff changeset
4748 // The value of an instruction's operand may be inserted
a61af66fc99e Initial load
duke
parents:
diff changeset
4749 // by referring to it with a '$' prefix.
a61af66fc99e Initial load
duke
parents:
diff changeset
4750 // opcode -- Three instruction opcodes may be provided. These are referred
a61af66fc99e Initial load
duke
parents:
diff changeset
4751 // to within an encode class as $primary, $secondary, and $tertiary
a61af66fc99e Initial load
duke
parents:
diff changeset
4752 // rrspectively. The primary opcode is commonly used to
a61af66fc99e Initial load
duke
parents:
diff changeset
4753 // indicate the type of machine instruction, while secondary
a61af66fc99e Initial load
duke
parents:
diff changeset
4754 // and tertiary are often used for prefix options or addressing
a61af66fc99e Initial load
duke
parents:
diff changeset
4755 // modes.
a61af66fc99e Initial load
duke
parents:
diff changeset
4756 // ins_encode -- A list of encode classes with parameters. The encode class
a61af66fc99e Initial load
duke
parents:
diff changeset
4757 // name must have been defined in an 'enc_class' specification
a61af66fc99e Initial load
duke
parents:
diff changeset
4758 // in the encode section of the architecture description.
a61af66fc99e Initial load
duke
parents:
diff changeset
4759
a61af66fc99e Initial load
duke
parents:
diff changeset
4760
a61af66fc99e Initial load
duke
parents:
diff changeset
4761 //----------Load/Store/Move Instructions---------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
4762 //----------Load Instructions--------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
4763
a61af66fc99e Initial load
duke
parents:
diff changeset
4764 // Load Byte (8 bit signed)
a61af66fc99e Initial load
duke
parents:
diff changeset
4765 instruct loadB(rRegI dst, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
4766 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4767 match(Set dst (LoadB mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
4768
a61af66fc99e Initial load
duke
parents:
diff changeset
4769 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
4770 format %{ "movsbl $dst, $mem\t# byte" %}
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4771
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4772 ins_encode %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4773 __ movsbl($dst$$Register, $mem$$Address);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4774 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4775
0
a61af66fc99e Initial load
duke
parents:
diff changeset
4776 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
4777 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4778
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4779 // Load Byte (8 bit signed) into Long Register
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4780 instruct loadB2L(rRegL dst, memory mem)
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4781 %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4782 match(Set dst (ConvI2L (LoadB mem)));
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4783
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4784 ins_cost(125);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4785 format %{ "movsbq $dst, $mem\t# byte -> long" %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4786
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4787 ins_encode %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4788 __ movsbq($dst$$Register, $mem$$Address);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4789 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4790
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4791 ins_pipe(ialu_reg_mem);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4792 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4793
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4794 // Load Unsigned Byte (8 bit UNsigned)
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4795 instruct loadUB(rRegI dst, memory mem)
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4796 %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4797 match(Set dst (LoadUB mem));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
4798
a61af66fc99e Initial load
duke
parents:
diff changeset
4799 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
4800 format %{ "movzbl $dst, $mem\t# ubyte" %}
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4801
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4802 ins_encode %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4803 __ movzbl($dst$$Register, $mem$$Address);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4804 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4805
0
a61af66fc99e Initial load
duke
parents:
diff changeset
4806 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
4807 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4808
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4809 // Load Unsigned Byte (8 bit UNsigned) into Long Register
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4810 instruct loadUB2L(rRegL dst, memory mem)
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4811 %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4812 match(Set dst (ConvI2L (LoadUB mem)));
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4813
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4814 ins_cost(125);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4815 format %{ "movzbq $dst, $mem\t# ubyte -> long" %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4816
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4817 ins_encode %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4818 __ movzbq($dst$$Register, $mem$$Address);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4819 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4820
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4821 ins_pipe(ialu_reg_mem);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4822 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
4823
824
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4824 // Load Unsigned Byte (8 bit UNsigned) with a 8-bit mask into Long Register
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4825 instruct loadUB2L_immI8(rRegL dst, memory mem, immI8 mask, rFlagsReg cr) %{
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4826 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4827 effect(KILL cr);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4828
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4829 format %{ "movzbq $dst, $mem\t# ubyte & 8-bit mask -> long\n\t"
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4830 "andl $dst, $mask" %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4831 ins_encode %{
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4832 Register Rdst = $dst$$Register;
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4833 __ movzbq(Rdst, $mem$$Address);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4834 __ andl(Rdst, $mask$$constant);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4835 %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4836 ins_pipe(ialu_reg_mem);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4837 %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4838
0
a61af66fc99e Initial load
duke
parents:
diff changeset
4839 // Load Short (16 bit signed)
a61af66fc99e Initial load
duke
parents:
diff changeset
4840 instruct loadS(rRegI dst, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
4841 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4842 match(Set dst (LoadS mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
4843
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4844 ins_cost(125);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
4845 format %{ "movswl $dst, $mem\t# short" %}
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4846
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4847 ins_encode %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4848 __ movswl($dst$$Register, $mem$$Address);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4849 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4850
0
a61af66fc99e Initial load
duke
parents:
diff changeset
4851 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
4852 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4853
785
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4854 // Load Short (16 bit signed) to Byte (8 bit signed)
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4855 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4856 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4857
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4858 ins_cost(125);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4859 format %{ "movsbl $dst, $mem\t# short -> byte" %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4860 ins_encode %{
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4861 __ movsbl($dst$$Register, $mem$$Address);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4862 %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4863 ins_pipe(ialu_reg_mem);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4864 %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4865
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4866 // Load Short (16 bit signed) into Long Register
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4867 instruct loadS2L(rRegL dst, memory mem)
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4868 %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4869 match(Set dst (ConvI2L (LoadS mem)));
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4870
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4871 ins_cost(125);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4872 format %{ "movswq $dst, $mem\t# short -> long" %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4873
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4874 ins_encode %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4875 __ movswq($dst$$Register, $mem$$Address);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4876 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4877
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4878 ins_pipe(ialu_reg_mem);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4879 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
4880
558
3b5ac9e7e6ea 6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents: 420
diff changeset
4881 // Load Unsigned Short/Char (16 bit UNsigned)
3b5ac9e7e6ea 6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents: 420
diff changeset
4882 instruct loadUS(rRegI dst, memory mem)
3b5ac9e7e6ea 6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents: 420
diff changeset
4883 %{
3b5ac9e7e6ea 6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents: 420
diff changeset
4884 match(Set dst (LoadUS mem));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
4885
a61af66fc99e Initial load
duke
parents:
diff changeset
4886 ins_cost(125);
558
3b5ac9e7e6ea 6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents: 420
diff changeset
4887 format %{ "movzwl $dst, $mem\t# ushort/char" %}
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4888
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4889 ins_encode %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4890 __ movzwl($dst$$Register, $mem$$Address);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4891 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4892
0
a61af66fc99e Initial load
duke
parents:
diff changeset
4893 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
4894 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4895
785
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4896 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4897 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4898 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4899
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4900 ins_cost(125);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4901 format %{ "movsbl $dst, $mem\t# ushort -> byte" %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4902 ins_encode %{
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4903 __ movsbl($dst$$Register, $mem$$Address);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4904 %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4905 ins_pipe(ialu_reg_mem);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4906 %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4907
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4908 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4909 instruct loadUS2L(rRegL dst, memory mem)
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4910 %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4911 match(Set dst (ConvI2L (LoadUS mem)));
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4912
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4913 ins_cost(125);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4914 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4915
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4916 ins_encode %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4917 __ movzwq($dst$$Register, $mem$$Address);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4918 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4919
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4920 ins_pipe(ialu_reg_mem);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4921 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
4922
824
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4923 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4924 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4925 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4926
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4927 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4928 ins_encode %{
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4929 __ movzbq($dst$$Register, $mem$$Address);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4930 %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4931 ins_pipe(ialu_reg_mem);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4932 %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4933
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4934 // Load Unsigned Short/Char (16 bit UNsigned) with mask into Long Register
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4935 instruct loadUS2L_immI16(rRegL dst, memory mem, immI16 mask, rFlagsReg cr) %{
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4936 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4937 effect(KILL cr);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4938
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4939 format %{ "movzwq $dst, $mem\t# ushort/char & 16-bit mask -> long\n\t"
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4940 "andl $dst, $mask" %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4941 ins_encode %{
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4942 Register Rdst = $dst$$Register;
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4943 __ movzwq(Rdst, $mem$$Address);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4944 __ andl(Rdst, $mask$$constant);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4945 %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4946 ins_pipe(ialu_reg_mem);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4947 %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4948
0
a61af66fc99e Initial load
duke
parents:
diff changeset
4949 // Load Integer
a61af66fc99e Initial load
duke
parents:
diff changeset
4950 instruct loadI(rRegI dst, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
4951 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4952 match(Set dst (LoadI mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
4953
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4954 ins_cost(125);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
4955 format %{ "movl $dst, $mem\t# int" %}
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4956
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4957 ins_encode %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4958 __ movl($dst$$Register, $mem$$Address);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4959 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4960
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4961 ins_pipe(ialu_reg_mem);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4962 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4963
785
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4964 // Load Integer (32 bit signed) to Byte (8 bit signed)
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4965 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4966 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4967
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4968 ins_cost(125);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4969 format %{ "movsbl $dst, $mem\t# int -> byte" %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4970 ins_encode %{
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4971 __ movsbl($dst$$Register, $mem$$Address);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4972 %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4973 ins_pipe(ialu_reg_mem);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4974 %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4975
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4976 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4977 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4978 match(Set dst (AndI (LoadI mem) mask));
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4979
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4980 ins_cost(125);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4981 format %{ "movzbl $dst, $mem\t# int -> ubyte" %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4982 ins_encode %{
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4983 __ movzbl($dst$$Register, $mem$$Address);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4984 %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4985 ins_pipe(ialu_reg_mem);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4986 %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4987
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4988 // Load Integer (32 bit signed) to Short (16 bit signed)
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4989 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4990 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4991
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4992 ins_cost(125);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4993 format %{ "movswl $dst, $mem\t# int -> short" %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4994 ins_encode %{
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4995 __ movswl($dst$$Register, $mem$$Address);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4996 %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4997 ins_pipe(ialu_reg_mem);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4998 %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4999
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5000 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5001 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5002 match(Set dst (AndI (LoadI mem) mask));
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5003
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5004 ins_cost(125);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5005 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5006 ins_encode %{
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5007 __ movzwl($dst$$Register, $mem$$Address);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5008 %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5009 ins_pipe(ialu_reg_mem);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5010 %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5011
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5012 // Load Integer into Long Register
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5013 instruct loadI2L(rRegL dst, memory mem)
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5014 %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5015 match(Set dst (ConvI2L (LoadI mem)));
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5016
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5017 ins_cost(125);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5018 format %{ "movslq $dst, $mem\t# int -> long" %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5019
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5020 ins_encode %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5021 __ movslq($dst$$Register, $mem$$Address);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5022 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5023
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5024 ins_pipe(ialu_reg_mem);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5025 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5026
824
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5027 // Load Integer with mask 0xFF into Long Register
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5028 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5029 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5030
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5031 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5032 ins_encode %{
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5033 __ movzbq($dst$$Register, $mem$$Address);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5034 %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5035 ins_pipe(ialu_reg_mem);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5036 %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5037
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5038 // Load Integer with mask 0xFFFF into Long Register
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5039 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5040 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5041
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5042 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5043 ins_encode %{
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5044 __ movzwq($dst$$Register, $mem$$Address);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5045 %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5046 ins_pipe(ialu_reg_mem);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5047 %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5048
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5049 // Load Integer with a 32-bit mask into Long Register
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5050 instruct loadI2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5051 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5052 effect(KILL cr);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5053
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5054 format %{ "movl $dst, $mem\t# int & 32-bit mask -> long\n\t"
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5055 "andl $dst, $mask" %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5056 ins_encode %{
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5057 Register Rdst = $dst$$Register;
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5058 __ movl(Rdst, $mem$$Address);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5059 __ andl(Rdst, $mask$$constant);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5060 %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5061 ins_pipe(ialu_reg_mem);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5062 %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5063
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5064 // Load Unsigned Integer into Long Register
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5065 instruct loadUI2L(rRegL dst, memory mem)
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5066 %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5067 match(Set dst (LoadUI2L mem));
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5068
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5069 ins_cost(125);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5070 format %{ "movl $dst, $mem\t# uint -> long" %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5071
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5072 ins_encode %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5073 __ movl($dst$$Register, $mem$$Address);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5074 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5075
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5076 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5077 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5078
a61af66fc99e Initial load
duke
parents:
diff changeset
5079 // Load Long
a61af66fc99e Initial load
duke
parents:
diff changeset
5080 instruct loadL(rRegL dst, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
5081 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5082 match(Set dst (LoadL mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5083
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5084 ins_cost(125);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5085 format %{ "movq $dst, $mem\t# long" %}
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5086
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5087 ins_encode %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5088 __ movq($dst$$Register, $mem$$Address);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5089 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5090
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5091 ins_pipe(ialu_reg_mem); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5092 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5093
a61af66fc99e Initial load
duke
parents:
diff changeset
5094 // Load Range
a61af66fc99e Initial load
duke
parents:
diff changeset
5095 instruct loadRange(rRegI dst, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
5096 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5097 match(Set dst (LoadRange mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5098
a61af66fc99e Initial load
duke
parents:
diff changeset
5099 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5100 format %{ "movl $dst, $mem\t# range" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5101 opcode(0x8B);
a61af66fc99e Initial load
duke
parents:
diff changeset
5102 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5103 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5104 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5105
a61af66fc99e Initial load
duke
parents:
diff changeset
5106 // Load Pointer
a61af66fc99e Initial load
duke
parents:
diff changeset
5107 instruct loadP(rRegP dst, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
5108 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5109 match(Set dst (LoadP mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5110
a61af66fc99e Initial load
duke
parents:
diff changeset
5111 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5112 format %{ "movq $dst, $mem\t# ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5113 opcode(0x8B);
a61af66fc99e Initial load
duke
parents:
diff changeset
5114 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5115 ins_pipe(ialu_reg_mem); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5116 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5117
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5118 // Load Compressed Pointer
163
885ed790ecf0 6695810: null oop passed to encode_heap_oop_not_null
kvn
parents: 145
diff changeset
5119 instruct loadN(rRegN dst, memory mem)
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5120 %{
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5121 match(Set dst (LoadN mem));
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5122
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5123 ins_cost(125); // XXX
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5124 format %{ "movl $dst, $mem\t# compressed ptr" %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5125 ins_encode %{
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5126 __ movl($dst$$Register, $mem$$Address);
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5127 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5128 ins_pipe(ialu_reg_mem); // XXX
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5129 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5130
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5131
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5132 // Load Klass Pointer
a61af66fc99e Initial load
duke
parents:
diff changeset
5133 instruct loadKlass(rRegP dst, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
5134 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5135 match(Set dst (LoadKlass mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5136
a61af66fc99e Initial load
duke
parents:
diff changeset
5137 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5138 format %{ "movq $dst, $mem\t# class" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5139 opcode(0x8B);
a61af66fc99e Initial load
duke
parents:
diff changeset
5140 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5141 ins_pipe(ialu_reg_mem); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5142 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5143
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
5144 // Load narrow Klass Pointer
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
5145 instruct loadNKlass(rRegN dst, memory mem)
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
5146 %{
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
5147 match(Set dst (LoadNKlass mem));
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5148
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5149 ins_cost(125); // XXX
182
44abbb0d4c18 6709093: Compressed Oops: reduce size of compiled methods
kvn
parents: 169
diff changeset
5150 format %{ "movl $dst, $mem\t# compressed klass ptr" %}
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5151 ins_encode %{
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5152 __ movl($dst$$Register, $mem$$Address);
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5153 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5154 ins_pipe(ialu_reg_mem); // XXX
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5155 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5156
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5157 // Load Float
a61af66fc99e Initial load
duke
parents:
diff changeset
5158 instruct loadF(regF dst, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
5159 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5160 match(Set dst (LoadF mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5161
a61af66fc99e Initial load
duke
parents:
diff changeset
5162 ins_cost(145); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5163 format %{ "movss $dst, $mem\t# float" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
5164 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
5165 __ movflt($dst$$XMMRegister, $mem$$Address);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
5166 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5167 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5168 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5169
a61af66fc99e Initial load
duke
parents:
diff changeset
5170 // Load Double
a61af66fc99e Initial load
duke
parents:
diff changeset
5171 instruct loadD_partial(regD dst, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
5172 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5173 predicate(!UseXmmLoadAndClearUpper);
a61af66fc99e Initial load
duke
parents:
diff changeset
5174 match(Set dst (LoadD mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5175
a61af66fc99e Initial load
duke
parents:
diff changeset
5176 ins_cost(145); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5177 format %{ "movlpd $dst, $mem\t# double" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
5178 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
5179 __ movdbl($dst$$XMMRegister, $mem$$Address);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
5180 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5181 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5182 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5183
a61af66fc99e Initial load
duke
parents:
diff changeset
5184 instruct loadD(regD dst, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
5185 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5186 predicate(UseXmmLoadAndClearUpper);
a61af66fc99e Initial load
duke
parents:
diff changeset
5187 match(Set dst (LoadD mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5188
a61af66fc99e Initial load
duke
parents:
diff changeset
5189 ins_cost(145); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5190 format %{ "movsd $dst, $mem\t# double" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
5191 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
5192 __ movdbl($dst$$XMMRegister, $mem$$Address);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
5193 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5194 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5195 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5196
a61af66fc99e Initial load
duke
parents:
diff changeset
5197 // Load Effective Address
a61af66fc99e Initial load
duke
parents:
diff changeset
5198 instruct leaP8(rRegP dst, indOffset8 mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
5199 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5200 match(Set dst mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5201
a61af66fc99e Initial load
duke
parents:
diff changeset
5202 ins_cost(110); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5203 format %{ "leaq $dst, $mem\t# ptr 8" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5204 opcode(0x8D);
a61af66fc99e Initial load
duke
parents:
diff changeset
5205 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5206 ins_pipe(ialu_reg_reg_fat);
a61af66fc99e Initial load
duke
parents:
diff changeset
5207 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5208
a61af66fc99e Initial load
duke
parents:
diff changeset
5209 instruct leaP32(rRegP dst, indOffset32 mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
5210 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5211 match(Set dst mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5212
a61af66fc99e Initial load
duke
parents:
diff changeset
5213 ins_cost(110);
a61af66fc99e Initial load
duke
parents:
diff changeset
5214 format %{ "leaq $dst, $mem\t# ptr 32" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5215 opcode(0x8D);
a61af66fc99e Initial load
duke
parents:
diff changeset
5216 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5217 ins_pipe(ialu_reg_reg_fat);
a61af66fc99e Initial load
duke
parents:
diff changeset
5218 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5219
a61af66fc99e Initial load
duke
parents:
diff changeset
5220 // instruct leaPIdx(rRegP dst, indIndex mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
5221 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5222 // match(Set dst mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5223
a61af66fc99e Initial load
duke
parents:
diff changeset
5224 // ins_cost(110);
a61af66fc99e Initial load
duke
parents:
diff changeset
5225 // format %{ "leaq $dst, $mem\t# ptr idx" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5226 // opcode(0x8D);
a61af66fc99e Initial load
duke
parents:
diff changeset
5227 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5228 // ins_pipe(ialu_reg_reg_fat);
a61af66fc99e Initial load
duke
parents:
diff changeset
5229 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5230
a61af66fc99e Initial load
duke
parents:
diff changeset
5231 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
5232 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5233 match(Set dst mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5234
a61af66fc99e Initial load
duke
parents:
diff changeset
5235 ins_cost(110);
a61af66fc99e Initial load
duke
parents:
diff changeset
5236 format %{ "leaq $dst, $mem\t# ptr idxoff" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5237 opcode(0x8D);
a61af66fc99e Initial load
duke
parents:
diff changeset
5238 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5239 ins_pipe(ialu_reg_reg_fat);
a61af66fc99e Initial load
duke
parents:
diff changeset
5240 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5241
a61af66fc99e Initial load
duke
parents:
diff changeset
5242 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
5243 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5244 match(Set dst mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5245
a61af66fc99e Initial load
duke
parents:
diff changeset
5246 ins_cost(110);
a61af66fc99e Initial load
duke
parents:
diff changeset
5247 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5248 opcode(0x8D);
a61af66fc99e Initial load
duke
parents:
diff changeset
5249 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5250 ins_pipe(ialu_reg_reg_fat);
a61af66fc99e Initial load
duke
parents:
diff changeset
5251 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5252
a61af66fc99e Initial load
duke
parents:
diff changeset
5253 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
5254 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5255 match(Set dst mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5256
a61af66fc99e Initial load
duke
parents:
diff changeset
5257 ins_cost(110);
a61af66fc99e Initial load
duke
parents:
diff changeset
5258 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5259 opcode(0x8D);
a61af66fc99e Initial load
duke
parents:
diff changeset
5260 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5261 ins_pipe(ialu_reg_reg_fat);
a61af66fc99e Initial load
duke
parents:
diff changeset
5262 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5263
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5264 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5265 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5266 match(Set dst mem);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5267
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5268 ins_cost(110);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5269 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5270 opcode(0x8D);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5271 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5272 ins_pipe(ialu_reg_reg_fat);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5273 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5274
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5275 // Load Effective Address which uses Narrow (32-bits) oop
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5276 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5277 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5278 predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5279 match(Set dst mem);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5280
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5281 ins_cost(110);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5282 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5283 opcode(0x8D);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5284 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5285 ins_pipe(ialu_reg_reg_fat);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5286 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5287
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5288 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5289 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5290 predicate(Universe::narrow_oop_shift() == 0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5291 match(Set dst mem);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5292
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5293 ins_cost(110); // XXX
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5294 format %{ "leaq $dst, $mem\t# ptr off8narrow" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5295 opcode(0x8D);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5296 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5297 ins_pipe(ialu_reg_reg_fat);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5298 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5299
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5300 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5301 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5302 predicate(Universe::narrow_oop_shift() == 0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5303 match(Set dst mem);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5304
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5305 ins_cost(110);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5306 format %{ "leaq $dst, $mem\t# ptr off32narrow" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5307 opcode(0x8D);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5308 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5309 ins_pipe(ialu_reg_reg_fat);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5310 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5311
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5312 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5313 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5314 predicate(Universe::narrow_oop_shift() == 0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5315 match(Set dst mem);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5316
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5317 ins_cost(110);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5318 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5319 opcode(0x8D);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5320 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5321 ins_pipe(ialu_reg_reg_fat);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5322 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5323
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5324 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5325 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5326 predicate(Universe::narrow_oop_shift() == 0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5327 match(Set dst mem);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5328
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5329 ins_cost(110);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5330 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5331 opcode(0x8D);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5332 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5333 ins_pipe(ialu_reg_reg_fat);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5334 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5335
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5336 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5337 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5338 predicate(Universe::narrow_oop_shift() == 0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5339 match(Set dst mem);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5340
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5341 ins_cost(110);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5342 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5343 opcode(0x8D);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5344 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5345 ins_pipe(ialu_reg_reg_fat);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5346 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5347
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5348 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5349 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5350 predicate(Universe::narrow_oop_shift() == 0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5351 match(Set dst mem);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5352
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5353 ins_cost(110);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5354 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5355 opcode(0x8D);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5356 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5357 ins_pipe(ialu_reg_reg_fat);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5358 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5359
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5360 instruct loadConI(rRegI dst, immI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5361 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5362 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5363
a61af66fc99e Initial load
duke
parents:
diff changeset
5364 format %{ "movl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5365 ins_encode(load_immI(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5366 ins_pipe(ialu_reg_fat); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5367 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5368
a61af66fc99e Initial load
duke
parents:
diff changeset
5369 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
5370 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5371 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5372 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
5373
a61af66fc99e Initial load
duke
parents:
diff changeset
5374 ins_cost(50);
a61af66fc99e Initial load
duke
parents:
diff changeset
5375 format %{ "xorl $dst, $dst\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5376 opcode(0x33); /* + rd */
a61af66fc99e Initial load
duke
parents:
diff changeset
5377 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
5378 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
5379 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5380
a61af66fc99e Initial load
duke
parents:
diff changeset
5381 instruct loadConL(rRegL dst, immL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5382 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5383 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5384
a61af66fc99e Initial load
duke
parents:
diff changeset
5385 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
5386 format %{ "movq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5387 ins_encode(load_immL(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5388 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
5389 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5390
a61af66fc99e Initial load
duke
parents:
diff changeset
5391 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
5392 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5393 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5394 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
5395
a61af66fc99e Initial load
duke
parents:
diff changeset
5396 ins_cost(50);
a61af66fc99e Initial load
duke
parents:
diff changeset
5397 format %{ "xorl $dst, $dst\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5398 opcode(0x33); /* + rd */
a61af66fc99e Initial load
duke
parents:
diff changeset
5399 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
5400 ins_pipe(ialu_reg); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5401 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5402
a61af66fc99e Initial load
duke
parents:
diff changeset
5403 instruct loadConUL32(rRegL dst, immUL32 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5404 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5405 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5406
a61af66fc99e Initial load
duke
parents:
diff changeset
5407 ins_cost(60);
a61af66fc99e Initial load
duke
parents:
diff changeset
5408 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5409 ins_encode(load_immUL32(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5410 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
5411 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5412
a61af66fc99e Initial load
duke
parents:
diff changeset
5413 instruct loadConL32(rRegL dst, immL32 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5414 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5415 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5416
a61af66fc99e Initial load
duke
parents:
diff changeset
5417 ins_cost(70);
a61af66fc99e Initial load
duke
parents:
diff changeset
5418 format %{ "movq $dst, $src\t# long (32-bit)" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5419 ins_encode(load_immL32(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5420 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
5421 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5422
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
5423 instruct loadConP(rRegP dst, immP con) %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
5424 match(Set dst con);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
5425
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
5426 format %{ "movq $dst, $con\t# ptr" %}
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
5427 ins_encode(load_immP(dst, con));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5428 ins_pipe(ialu_reg_fat); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5429 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5430
a61af66fc99e Initial load
duke
parents:
diff changeset
5431 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
5432 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5433 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5434 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
5435
a61af66fc99e Initial load
duke
parents:
diff changeset
5436 ins_cost(50);
a61af66fc99e Initial load
duke
parents:
diff changeset
5437 format %{ "xorl $dst, $dst\t# ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5438 opcode(0x33); /* + rd */
a61af66fc99e Initial load
duke
parents:
diff changeset
5439 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
5440 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
5441 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5442
a61af66fc99e Initial load
duke
parents:
diff changeset
5443 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
5444 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5445 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5446 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
5447
a61af66fc99e Initial load
duke
parents:
diff changeset
5448 ins_cost(60);
a61af66fc99e Initial load
duke
parents:
diff changeset
5449 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5450 ins_encode(load_immP31(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5451 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
5452 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5453
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
5454 instruct loadConF(regF dst, immF con) %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
5455 match(Set dst con);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5456 ins_cost(125);
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
5457 format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
5458 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
5459 __ movflt($dst$$XMMRegister, $constantaddress($con));
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
5460 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5461 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
5462 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5463
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5464 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5465 match(Set dst src);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5466 effect(KILL cr);
124
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
5467 format %{ "xorq $dst, $src\t# compressed NULL ptr" %}
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5468 ins_encode %{
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5469 __ xorq($dst$$Register, $dst$$Register);
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5470 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5471 ins_pipe(ialu_reg);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5472 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5473
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
5474 instruct loadConN(rRegN dst, immN src) %{
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5475 match(Set dst src);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5476
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5477 ins_cost(125);
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
5478 format %{ "movl $dst, $src\t# compressed ptr" %}
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5479 ins_encode %{
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5480 address con = (address)$src$$constant;
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5481 if (con == NULL) {
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5482 ShouldNotReachHere();
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5483 } else {
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5484 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant);
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5485 }
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5486 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5487 ins_pipe(ialu_reg_fat); // XXX
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5488 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5489
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5490 instruct loadConF0(regF dst, immF0 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5491 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5492 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5493 ins_cost(100);
a61af66fc99e Initial load
duke
parents:
diff changeset
5494
a61af66fc99e Initial load
duke
parents:
diff changeset
5495 format %{ "xorps $dst, $dst\t# float 0.0" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
5496 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
5497 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
5498 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5499 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
5500 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5501
a61af66fc99e Initial load
duke
parents:
diff changeset
5502 // Use the same format since predicate() can not be used here.
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
5503 instruct loadConD(regD dst, immD con) %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
5504 match(Set dst con);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5505 ins_cost(125);
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
5506 format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
5507 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
5508 __ movdbl($dst$$XMMRegister, $constantaddress($con));
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
5509 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5510 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
5511 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5512
a61af66fc99e Initial load
duke
parents:
diff changeset
5513 instruct loadConD0(regD dst, immD0 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5514 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5515 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5516 ins_cost(100);
a61af66fc99e Initial load
duke
parents:
diff changeset
5517
a61af66fc99e Initial load
duke
parents:
diff changeset
5518 format %{ "xorpd $dst, $dst\t# double 0.0" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
5519 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
5520 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
5521 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5522 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
5523 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5524
a61af66fc99e Initial load
duke
parents:
diff changeset
5525 instruct loadSSI(rRegI dst, stackSlotI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5526 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5527 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5528
a61af66fc99e Initial load
duke
parents:
diff changeset
5529 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
5530 format %{ "movl $dst, $src\t# int stk" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5531 opcode(0x8B);
a61af66fc99e Initial load
duke
parents:
diff changeset
5532 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5533 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5534 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5535
a61af66fc99e Initial load
duke
parents:
diff changeset
5536 instruct loadSSL(rRegL dst, stackSlotL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5537 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5538 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5539
a61af66fc99e Initial load
duke
parents:
diff changeset
5540 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
5541 format %{ "movq $dst, $src\t# long stk" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5542 opcode(0x8B);
a61af66fc99e Initial load
duke
parents:
diff changeset
5543 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5544 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5545 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5546
a61af66fc99e Initial load
duke
parents:
diff changeset
5547 instruct loadSSP(rRegP dst, stackSlotP src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5548 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5549 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5550
a61af66fc99e Initial load
duke
parents:
diff changeset
5551 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
5552 format %{ "movq $dst, $src\t# ptr stk" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5553 opcode(0x8B);
a61af66fc99e Initial load
duke
parents:
diff changeset
5554 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5555 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5556 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5557
a61af66fc99e Initial load
duke
parents:
diff changeset
5558 instruct loadSSF(regF dst, stackSlotF src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5559 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5560 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5561
a61af66fc99e Initial load
duke
parents:
diff changeset
5562 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
5563 format %{ "movss $dst, $src\t# float stk" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
5564 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
5565 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
5566 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5567 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5568 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5569
a61af66fc99e Initial load
duke
parents:
diff changeset
5570 // Use the same format since predicate() can not be used here.
a61af66fc99e Initial load
duke
parents:
diff changeset
5571 instruct loadSSD(regD dst, stackSlotD src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5572 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5573 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5574
a61af66fc99e Initial load
duke
parents:
diff changeset
5575 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
5576 format %{ "movsd $dst, $src\t# double stk" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5577 ins_encode %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5578 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
a61af66fc99e Initial load
duke
parents:
diff changeset
5579 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5580 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5581 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5582
a61af66fc99e Initial load
duke
parents:
diff changeset
5583 // Prefetch instructions.
a61af66fc99e Initial load
duke
parents:
diff changeset
5584 // Must be safe to execute with invalid address (cannot fault).
a61af66fc99e Initial load
duke
parents:
diff changeset
5585
a61af66fc99e Initial load
duke
parents:
diff changeset
5586 instruct prefetchr( memory mem ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5587 predicate(ReadPrefetchInstr==3);
a61af66fc99e Initial load
duke
parents:
diff changeset
5588 match(PrefetchRead mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5589 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
5590
a61af66fc99e Initial load
duke
parents:
diff changeset
5591 format %{ "PREFETCHR $mem\t# Prefetch into level 1 cache" %}
3854
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5592 ins_encode %{
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5593 __ prefetchr($mem$$Address);
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5594 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5595 ins_pipe(ialu_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5596 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5597
a61af66fc99e Initial load
duke
parents:
diff changeset
5598 instruct prefetchrNTA( memory mem ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5599 predicate(ReadPrefetchInstr==0);
a61af66fc99e Initial load
duke
parents:
diff changeset
5600 match(PrefetchRead mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5601 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
5602
a61af66fc99e Initial load
duke
parents:
diff changeset
5603 format %{ "PREFETCHNTA $mem\t# Prefetch into non-temporal cache for read" %}
3854
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5604 ins_encode %{
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5605 __ prefetchnta($mem$$Address);
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5606 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5607 ins_pipe(ialu_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5608 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5609
a61af66fc99e Initial load
duke
parents:
diff changeset
5610 instruct prefetchrT0( memory mem ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5611 predicate(ReadPrefetchInstr==1);
a61af66fc99e Initial load
duke
parents:
diff changeset
5612 match(PrefetchRead mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5613 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
5614
a61af66fc99e Initial load
duke
parents:
diff changeset
5615 format %{ "PREFETCHT0 $mem\t# prefetch into L1 and L2 caches for read" %}
3854
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5616 ins_encode %{
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5617 __ prefetcht0($mem$$Address);
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5618 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5619 ins_pipe(ialu_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5620 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5621
a61af66fc99e Initial load
duke
parents:
diff changeset
5622 instruct prefetchrT2( memory mem ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5623 predicate(ReadPrefetchInstr==2);
a61af66fc99e Initial load
duke
parents:
diff changeset
5624 match(PrefetchRead mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5625 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
5626
a61af66fc99e Initial load
duke
parents:
diff changeset
5627 format %{ "PREFETCHT2 $mem\t# prefetch into L2 caches for read" %}
3854
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5628 ins_encode %{
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5629 __ prefetcht2($mem$$Address);
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5630 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5631 ins_pipe(ialu_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5632 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5633
a61af66fc99e Initial load
duke
parents:
diff changeset
5634 instruct prefetchwNTA( memory mem ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5635 match(PrefetchWrite mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5636 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
5637
a61af66fc99e Initial load
duke
parents:
diff changeset
5638 format %{ "PREFETCHNTA $mem\t# Prefetch to non-temporal cache for write" %}
3854
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5639 ins_encode %{
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5640 __ prefetchnta($mem$$Address);
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5641 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5642 ins_pipe(ialu_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5643 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5644
3854
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5645 // Prefetch instructions for allocation.
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5646
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5647 instruct prefetchAlloc( memory mem ) %{
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5648 predicate(AllocatePrefetchInstr==3);
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5649 match(PrefetchAllocation mem);
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5650 ins_cost(125);
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5651
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5652 format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %}
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5653 ins_encode %{
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5654 __ prefetchw($mem$$Address);
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5655 %}
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5656 ins_pipe(ialu_mem);
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5657 %}
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5658
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5659 instruct prefetchAllocNTA( memory mem ) %{
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5660 predicate(AllocatePrefetchInstr==0);
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5661 match(PrefetchAllocation mem);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5662 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
5663
3854
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5664 format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %}
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5665 ins_encode %{
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5666 __ prefetchnta($mem$$Address);
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5667 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5668 ins_pipe(ialu_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5669 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5670
3854
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5671 instruct prefetchAllocT0( memory mem ) %{
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5672 predicate(AllocatePrefetchInstr==1);
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5673 match(PrefetchAllocation mem);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5674 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
5675
3854
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5676 format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %}
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5677 ins_encode %{
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5678 __ prefetcht0($mem$$Address);
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5679 %}
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5680 ins_pipe(ialu_mem);
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5681 %}
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5682
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5683 instruct prefetchAllocT2( memory mem ) %{
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5684 predicate(AllocatePrefetchInstr==2);
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5685 match(PrefetchAllocation mem);
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5686 ins_cost(125);
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5687
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5688 format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %}
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5689 ins_encode %{
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5690 __ prefetcht2($mem$$Address);
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5691 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5692 ins_pipe(ialu_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5693 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5694
a61af66fc99e Initial load
duke
parents:
diff changeset
5695 //----------Store Instructions-------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
5696
a61af66fc99e Initial load
duke
parents:
diff changeset
5697 // Store Byte
a61af66fc99e Initial load
duke
parents:
diff changeset
5698 instruct storeB(memory mem, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5699 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5700 match(Set mem (StoreB mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5701
a61af66fc99e Initial load
duke
parents:
diff changeset
5702 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5703 format %{ "movb $mem, $src\t# byte" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5704 opcode(0x88);
a61af66fc99e Initial load
duke
parents:
diff changeset
5705 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5706 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
5707 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5708
a61af66fc99e Initial load
duke
parents:
diff changeset
5709 // Store Char/Short
a61af66fc99e Initial load
duke
parents:
diff changeset
5710 instruct storeC(memory mem, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5711 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5712 match(Set mem (StoreC mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5713
a61af66fc99e Initial load
duke
parents:
diff changeset
5714 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5715 format %{ "movw $mem, $src\t# char/short" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5716 opcode(0x89);
a61af66fc99e Initial load
duke
parents:
diff changeset
5717 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5718 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
5719 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5720
a61af66fc99e Initial load
duke
parents:
diff changeset
5721 // Store Integer
a61af66fc99e Initial load
duke
parents:
diff changeset
5722 instruct storeI(memory mem, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5723 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5724 match(Set mem (StoreI mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5725
a61af66fc99e Initial load
duke
parents:
diff changeset
5726 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5727 format %{ "movl $mem, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5728 opcode(0x89);
a61af66fc99e Initial load
duke
parents:
diff changeset
5729 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5730 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
5731 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5732
a61af66fc99e Initial load
duke
parents:
diff changeset
5733 // Store Long
a61af66fc99e Initial load
duke
parents:
diff changeset
5734 instruct storeL(memory mem, rRegL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5735 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5736 match(Set mem (StoreL mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5737
a61af66fc99e Initial load
duke
parents:
diff changeset
5738 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5739 format %{ "movq $mem, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5740 opcode(0x89);
a61af66fc99e Initial load
duke
parents:
diff changeset
5741 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5742 ins_pipe(ialu_mem_reg); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5743 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5744
a61af66fc99e Initial load
duke
parents:
diff changeset
5745 // Store Pointer
a61af66fc99e Initial load
duke
parents:
diff changeset
5746 instruct storeP(memory mem, any_RegP src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5747 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5748 match(Set mem (StoreP mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5749
a61af66fc99e Initial load
duke
parents:
diff changeset
5750 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5751 format %{ "movq $mem, $src\t# ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5752 opcode(0x89);
a61af66fc99e Initial load
duke
parents:
diff changeset
5753 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5754 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
5755 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5756
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5757 instruct storeImmP0(memory mem, immP0 zero)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5758 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5759 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5760 match(Set mem (StoreP mem zero));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5761
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5762 ins_cost(125); // XXX
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5763 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5764 ins_encode %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5765 __ movq($mem$$Address, r12);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5766 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5767 ins_pipe(ialu_mem_reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5768 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5769
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5770 // Store NULL Pointer, mark word, or other simple pointer constant.
a61af66fc99e Initial load
duke
parents:
diff changeset
5771 instruct storeImmP(memory mem, immP31 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5772 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5773 match(Set mem (StoreP mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5774
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5775 ins_cost(150); // XXX
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5776 format %{ "movq $mem, $src\t# ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5777 opcode(0xC7); /* C7 /0 */
a61af66fc99e Initial load
duke
parents:
diff changeset
5778 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5779 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
5780 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5781
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5782 // Store Compressed Pointer
163
885ed790ecf0 6695810: null oop passed to encode_heap_oop_not_null
kvn
parents: 145
diff changeset
5783 instruct storeN(memory mem, rRegN src)
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5784 %{
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5785 match(Set mem (StoreN mem src));
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5786
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5787 ins_cost(125); // XXX
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
5788 format %{ "movl $mem, $src\t# compressed ptr" %}
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5789 ins_encode %{
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5790 __ movl($mem$$Address, $src$$Register);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5791 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5792 ins_pipe(ialu_mem_reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5793 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5794
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5795 instruct storeImmN0(memory mem, immN0 zero)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5796 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5797 predicate(Universe::narrow_oop_base() == NULL);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5798 match(Set mem (StoreN mem zero));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5799
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5800 ins_cost(125); // XXX
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5801 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5802 ins_encode %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5803 __ movl($mem$$Address, r12);
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5804 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5805 ins_pipe(ialu_mem_reg);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5806 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5807
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5808 instruct storeImmN(memory mem, immN src)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5809 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5810 match(Set mem (StoreN mem src));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5811
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5812 ins_cost(150); // XXX
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5813 format %{ "movl $mem, $src\t# compressed ptr" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5814 ins_encode %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5815 address con = (address)$src$$constant;
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5816 if (con == NULL) {
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5817 __ movl($mem$$Address, (int32_t)0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5818 } else {
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5819 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5820 }
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5821 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5822 ins_pipe(ialu_mem_imm);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5823 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5824
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5825 // Store Integer Immediate
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5826 instruct storeImmI0(memory mem, immI0 zero)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5827 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5828 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5829 match(Set mem (StoreI mem zero));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5830
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5831 ins_cost(125); // XXX
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5832 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5833 ins_encode %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5834 __ movl($mem$$Address, r12);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5835 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5836 ins_pipe(ialu_mem_reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5837 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5838
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5839 instruct storeImmI(memory mem, immI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5840 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5841 match(Set mem (StoreI mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5842
a61af66fc99e Initial load
duke
parents:
diff changeset
5843 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
5844 format %{ "movl $mem, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5845 opcode(0xC7); /* C7 /0 */
a61af66fc99e Initial load
duke
parents:
diff changeset
5846 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5847 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
5848 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5849
a61af66fc99e Initial load
duke
parents:
diff changeset
5850 // Store Long Immediate
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5851 instruct storeImmL0(memory mem, immL0 zero)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5852 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5853 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5854 match(Set mem (StoreL mem zero));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5855
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5856 ins_cost(125); // XXX
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5857 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5858 ins_encode %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5859 __ movq($mem$$Address, r12);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5860 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5861 ins_pipe(ialu_mem_reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5862 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5863
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5864 instruct storeImmL(memory mem, immL32 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5865 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5866 match(Set mem (StoreL mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5867
a61af66fc99e Initial load
duke
parents:
diff changeset
5868 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
5869 format %{ "movq $mem, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5870 opcode(0xC7); /* C7 /0 */
a61af66fc99e Initial load
duke
parents:
diff changeset
5871 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5872 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
5873 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5874
a61af66fc99e Initial load
duke
parents:
diff changeset
5875 // Store Short/Char Immediate
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5876 instruct storeImmC0(memory mem, immI0 zero)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5877 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5878 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5879 match(Set mem (StoreC mem zero));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5880
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5881 ins_cost(125); // XXX
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5882 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5883 ins_encode %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5884 __ movw($mem$$Address, r12);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5885 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5886 ins_pipe(ialu_mem_reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5887 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5888
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5889 instruct storeImmI16(memory mem, immI16 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5890 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5891 predicate(UseStoreImmI16);
a61af66fc99e Initial load
duke
parents:
diff changeset
5892 match(Set mem (StoreC mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5893
a61af66fc99e Initial load
duke
parents:
diff changeset
5894 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
5895 format %{ "movw $mem, $src\t# short/char" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5896 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
a61af66fc99e Initial load
duke
parents:
diff changeset
5897 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5898 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
5899 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5900
a61af66fc99e Initial load
duke
parents:
diff changeset
5901 // Store Byte Immediate
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5902 instruct storeImmB0(memory mem, immI0 zero)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5903 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5904 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5905 match(Set mem (StoreB mem zero));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5906
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5907 ins_cost(125); // XXX
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5908 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5909 ins_encode %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5910 __ movb($mem$$Address, r12);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5911 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5912 ins_pipe(ialu_mem_reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5913 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5914
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5915 instruct storeImmB(memory mem, immI8 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5916 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5917 match(Set mem (StoreB mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5918
a61af66fc99e Initial load
duke
parents:
diff changeset
5919 ins_cost(150); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5920 format %{ "movb $mem, $src\t# byte" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5921 opcode(0xC6); /* C6 /0 */
a61af66fc99e Initial load
duke
parents:
diff changeset
5922 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5923 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
5924 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5925
a61af66fc99e Initial load
duke
parents:
diff changeset
5926 // Store CMS card-mark Immediate
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5927 instruct storeImmCM0_reg(memory mem, immI0 zero)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5928 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5929 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5930 match(Set mem (StoreCM mem zero));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5931
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5932 ins_cost(125); // XXX
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5933 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5934 ins_encode %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5935 __ movb($mem$$Address, r12);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5936 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5937 ins_pipe(ialu_mem_reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5938 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5939
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5940 instruct storeImmCM0(memory mem, immI0 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5941 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5942 match(Set mem (StoreCM mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5943
a61af66fc99e Initial load
duke
parents:
diff changeset
5944 ins_cost(150); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5945 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5946 opcode(0xC6); /* C6 /0 */
a61af66fc99e Initial load
duke
parents:
diff changeset
5947 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5948 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
5949 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5950
a61af66fc99e Initial load
duke
parents:
diff changeset
5951 // Store Float
a61af66fc99e Initial load
duke
parents:
diff changeset
5952 instruct storeF(memory mem, regF src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5953 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5954 match(Set mem (StoreF mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5955
a61af66fc99e Initial load
duke
parents:
diff changeset
5956 ins_cost(95); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5957 format %{ "movss $mem, $src\t# float" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
5958 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
5959 __ movflt($mem$$Address, $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
5960 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5961 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5962 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5963
a61af66fc99e Initial load
duke
parents:
diff changeset
5964 // Store immediate Float value (it is faster than store from XMM register)
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5965 instruct storeF0(memory mem, immF0 zero)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5966 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5967 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5968 match(Set mem (StoreF mem zero));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5969
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5970 ins_cost(25); // XXX
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5971 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5972 ins_encode %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5973 __ movl($mem$$Address, r12);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5974 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5975 ins_pipe(ialu_mem_reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5976 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5977
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5978 instruct storeF_imm(memory mem, immF src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5979 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5980 match(Set mem (StoreF mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5981
a61af66fc99e Initial load
duke
parents:
diff changeset
5982 ins_cost(50);
a61af66fc99e Initial load
duke
parents:
diff changeset
5983 format %{ "movl $mem, $src\t# float" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5984 opcode(0xC7); /* C7 /0 */
a61af66fc99e Initial load
duke
parents:
diff changeset
5985 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5986 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
5987 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5988
a61af66fc99e Initial load
duke
parents:
diff changeset
5989 // Store Double
a61af66fc99e Initial load
duke
parents:
diff changeset
5990 instruct storeD(memory mem, regD src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5991 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5992 match(Set mem (StoreD mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5993
a61af66fc99e Initial load
duke
parents:
diff changeset
5994 ins_cost(95); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5995 format %{ "movsd $mem, $src\t# double" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
5996 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
5997 __ movdbl($mem$$Address, $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
5998 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5999 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6000 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6001
a61af66fc99e Initial load
duke
parents:
diff changeset
6002 // Store immediate double 0.0 (it is faster than store from XMM register)
a61af66fc99e Initial load
duke
parents:
diff changeset
6003 instruct storeD0_imm(memory mem, immD0 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6004 %{
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6005 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6006 match(Set mem (StoreD mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6007
a61af66fc99e Initial load
duke
parents:
diff changeset
6008 ins_cost(50);
a61af66fc99e Initial load
duke
parents:
diff changeset
6009 format %{ "movq $mem, $src\t# double 0." %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6010 opcode(0xC7); /* C7 /0 */
a61af66fc99e Initial load
duke
parents:
diff changeset
6011 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6012 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
6013 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6014
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6015 instruct storeD0(memory mem, immD0 zero)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6016 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6017 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6018 match(Set mem (StoreD mem zero));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6019
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6020 ins_cost(25); // XXX
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6021 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6022 ins_encode %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6023 __ movq($mem$$Address, r12);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6024 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6025 ins_pipe(ialu_mem_reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6026 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6027
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6028 instruct storeSSI(stackSlotI dst, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6029 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6030 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
6031
a61af66fc99e Initial load
duke
parents:
diff changeset
6032 ins_cost(100);
a61af66fc99e Initial load
duke
parents:
diff changeset
6033 format %{ "movl $dst, $src\t# int stk" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6034 opcode(0x89);
a61af66fc99e Initial load
duke
parents:
diff changeset
6035 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
6036 ins_pipe( ialu_mem_reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
6037 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6038
a61af66fc99e Initial load
duke
parents:
diff changeset
6039 instruct storeSSL(stackSlotL dst, rRegL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6040 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6041 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
6042
a61af66fc99e Initial load
duke
parents:
diff changeset
6043 ins_cost(100);
a61af66fc99e Initial load
duke
parents:
diff changeset
6044 format %{ "movq $dst, $src\t# long stk" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6045 opcode(0x89);
a61af66fc99e Initial load
duke
parents:
diff changeset
6046 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
6047 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6048 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6049
a61af66fc99e Initial load
duke
parents:
diff changeset
6050 instruct storeSSP(stackSlotP dst, rRegP src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6051 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6052 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
6053
a61af66fc99e Initial load
duke
parents:
diff changeset
6054 ins_cost(100);
a61af66fc99e Initial load
duke
parents:
diff changeset
6055 format %{ "movq $dst, $src\t# ptr stk" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6056 opcode(0x89);
a61af66fc99e Initial load
duke
parents:
diff changeset
6057 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
6058 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6059 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6060
a61af66fc99e Initial load
duke
parents:
diff changeset
6061 instruct storeSSF(stackSlotF dst, regF src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6062 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6063 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
6064
a61af66fc99e Initial load
duke
parents:
diff changeset
6065 ins_cost(95); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6066 format %{ "movss $dst, $src\t# float stk" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6067 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6068 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6069 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6070 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6071 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6072
a61af66fc99e Initial load
duke
parents:
diff changeset
6073 instruct storeSSD(stackSlotD dst, regD src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6074 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6075 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
6076
a61af66fc99e Initial load
duke
parents:
diff changeset
6077 ins_cost(95); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6078 format %{ "movsd $dst, $src\t# double stk" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6079 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6080 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6081 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6082 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6083 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6084
a61af66fc99e Initial load
duke
parents:
diff changeset
6085 //----------BSWAP Instructions-------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
6086 instruct bytes_reverse_int(rRegI dst) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6087 match(Set dst (ReverseBytesI dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
6088
a61af66fc99e Initial load
duke
parents:
diff changeset
6089 format %{ "bswapl $dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6090 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */
a61af66fc99e Initial load
duke
parents:
diff changeset
6091 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6092 ins_pipe( ialu_reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
6093 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6094
a61af66fc99e Initial load
duke
parents:
diff changeset
6095 instruct bytes_reverse_long(rRegL dst) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6096 match(Set dst (ReverseBytesL dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
6097
a61af66fc99e Initial load
duke
parents:
diff changeset
6098 format %{ "bswapq $dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6099 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */
a61af66fc99e Initial load
duke
parents:
diff changeset
6100 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6101 ins_pipe( ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6102 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6103
6138
ccaa67adfe5b 7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents: 6084
diff changeset
6104 instruct bytes_reverse_unsigned_short(rRegI dst, rFlagsReg cr) %{
1396
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
6105 match(Set dst (ReverseBytesUS dst));
6138
ccaa67adfe5b 7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents: 6084
diff changeset
6106 effect(KILL cr);
1396
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
6107
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
6108 format %{ "bswapl $dst\n\t"
1396
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
6109 "shrl $dst,16\n\t" %}
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
6110 ins_encode %{
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
6111 __ bswapl($dst$$Register);
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
6112 __ shrl($dst$$Register, 16);
1396
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
6113 %}
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
6114 ins_pipe( ialu_reg );
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
6115 %}
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
6116
6138
ccaa67adfe5b 7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents: 6084
diff changeset
6117 instruct bytes_reverse_short(rRegI dst, rFlagsReg cr) %{
1396
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
6118 match(Set dst (ReverseBytesS dst));
6138
ccaa67adfe5b 7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents: 6084
diff changeset
6119 effect(KILL cr);
1396
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
6120
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
6121 format %{ "bswapl $dst\n\t"
1396
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
6122 "sar $dst,16\n\t" %}
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
6123 ins_encode %{
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
6124 __ bswapl($dst$$Register);
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
6125 __ sarl($dst$$Register, 16);
1396
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
6126 %}
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
6127 ins_pipe( ialu_reg );
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
6128 %}
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
6129
775
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6130 //---------- Zeros Count Instructions ------------------------------------------
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6131
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6132 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6133 predicate(UseCountLeadingZerosInstruction);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6134 match(Set dst (CountLeadingZerosI src));
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6135 effect(KILL cr);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6136
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6137 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6138 ins_encode %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6139 __ lzcntl($dst$$Register, $src$$Register);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6140 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6141 ins_pipe(ialu_reg);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6142 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6143
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6144 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6145 predicate(!UseCountLeadingZerosInstruction);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6146 match(Set dst (CountLeadingZerosI src));
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6147 effect(KILL cr);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6148
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6149 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6150 "jnz skip\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6151 "movl $dst, -1\n"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6152 "skip:\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6153 "negl $dst\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6154 "addl $dst, 31" %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6155 ins_encode %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6156 Register Rdst = $dst$$Register;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6157 Register Rsrc = $src$$Register;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6158 Label skip;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6159 __ bsrl(Rdst, Rsrc);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6160 __ jccb(Assembler::notZero, skip);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6161 __ movl(Rdst, -1);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6162 __ bind(skip);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6163 __ negl(Rdst);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6164 __ addl(Rdst, BitsPerInt - 1);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6165 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6166 ins_pipe(ialu_reg);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6167 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6168
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6169 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6170 predicate(UseCountLeadingZerosInstruction);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6171 match(Set dst (CountLeadingZerosL src));
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6172 effect(KILL cr);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6173
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6174 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6175 ins_encode %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6176 __ lzcntq($dst$$Register, $src$$Register);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6177 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6178 ins_pipe(ialu_reg);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6179 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6180
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6181 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6182 predicate(!UseCountLeadingZerosInstruction);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6183 match(Set dst (CountLeadingZerosL src));
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6184 effect(KILL cr);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6185
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6186 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6187 "jnz skip\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6188 "movl $dst, -1\n"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6189 "skip:\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6190 "negl $dst\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6191 "addl $dst, 63" %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6192 ins_encode %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6193 Register Rdst = $dst$$Register;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6194 Register Rsrc = $src$$Register;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6195 Label skip;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6196 __ bsrq(Rdst, Rsrc);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6197 __ jccb(Assembler::notZero, skip);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6198 __ movl(Rdst, -1);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6199 __ bind(skip);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6200 __ negl(Rdst);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6201 __ addl(Rdst, BitsPerLong - 1);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6202 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6203 ins_pipe(ialu_reg);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6204 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6205
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6206 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6207 match(Set dst (CountTrailingZerosI src));
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6208 effect(KILL cr);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6209
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6210 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6211 "jnz done\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6212 "movl $dst, 32\n"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6213 "done:" %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6214 ins_encode %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6215 Register Rdst = $dst$$Register;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6216 Label done;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6217 __ bsfl(Rdst, $src$$Register);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6218 __ jccb(Assembler::notZero, done);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6219 __ movl(Rdst, BitsPerInt);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6220 __ bind(done);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6221 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6222 ins_pipe(ialu_reg);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6223 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6224
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6225 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6226 match(Set dst (CountTrailingZerosL src));
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6227 effect(KILL cr);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6228
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6229 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6230 "jnz done\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6231 "movl $dst, 64\n"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6232 "done:" %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6233 ins_encode %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6234 Register Rdst = $dst$$Register;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6235 Label done;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6236 __ bsfq(Rdst, $src$$Register);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6237 __ jccb(Assembler::notZero, done);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6238 __ movl(Rdst, BitsPerLong);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6239 __ bind(done);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6240 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6241 ins_pipe(ialu_reg);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6242 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6243
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6244
643
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6245 //---------- Population Count Instructions -------------------------------------
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6246
6138
ccaa67adfe5b 7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents: 6084
diff changeset
6247 instruct popCountI(rRegI dst, rRegI src, rFlagsReg cr) %{
643
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6248 predicate(UsePopCountInstruction);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6249 match(Set dst (PopCountI src));
6138
ccaa67adfe5b 7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents: 6084
diff changeset
6250 effect(KILL cr);
643
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6251
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6252 format %{ "popcnt $dst, $src" %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6253 ins_encode %{
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6254 __ popcntl($dst$$Register, $src$$Register);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6255 %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6256 ins_pipe(ialu_reg);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6257 %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6258
6138
ccaa67adfe5b 7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents: 6084
diff changeset
6259 instruct popCountI_mem(rRegI dst, memory mem, rFlagsReg cr) %{
643
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6260 predicate(UsePopCountInstruction);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6261 match(Set dst (PopCountI (LoadI mem)));
6138
ccaa67adfe5b 7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents: 6084
diff changeset
6262 effect(KILL cr);
643
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6263
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6264 format %{ "popcnt $dst, $mem" %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6265 ins_encode %{
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6266 __ popcntl($dst$$Register, $mem$$Address);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6267 %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6268 ins_pipe(ialu_reg);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6269 %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6270
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6271 // Note: Long.bitCount(long) returns an int.
6138
ccaa67adfe5b 7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents: 6084
diff changeset
6272 instruct popCountL(rRegI dst, rRegL src, rFlagsReg cr) %{
643
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6273 predicate(UsePopCountInstruction);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6274 match(Set dst (PopCountL src));
6138
ccaa67adfe5b 7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents: 6084
diff changeset
6275 effect(KILL cr);
643
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6276
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6277 format %{ "popcnt $dst, $src" %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6278 ins_encode %{
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6279 __ popcntq($dst$$Register, $src$$Register);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6280 %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6281 ins_pipe(ialu_reg);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6282 %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6283
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6284 // Note: Long.bitCount(long) returns an int.
6138
ccaa67adfe5b 7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents: 6084
diff changeset
6285 instruct popCountL_mem(rRegI dst, memory mem, rFlagsReg cr) %{
643
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6286 predicate(UsePopCountInstruction);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6287 match(Set dst (PopCountL (LoadL mem)));
6138
ccaa67adfe5b 7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents: 6084
diff changeset
6288 effect(KILL cr);
643
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6289
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6290 format %{ "popcnt $dst, $mem" %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6291 ins_encode %{
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6292 __ popcntq($dst$$Register, $mem$$Address);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6293 %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6294 ins_pipe(ialu_reg);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6295 %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6296
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6297
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6298 //----------MemBar Instructions-----------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
6299 // Memory barrier flavors
a61af66fc99e Initial load
duke
parents:
diff changeset
6300
a61af66fc99e Initial load
duke
parents:
diff changeset
6301 instruct membar_acquire()
a61af66fc99e Initial load
duke
parents:
diff changeset
6302 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6303 match(MemBarAcquire);
a61af66fc99e Initial load
duke
parents:
diff changeset
6304 ins_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
6305
a61af66fc99e Initial load
duke
parents:
diff changeset
6306 size(0);
671
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 647
diff changeset
6307 format %{ "MEMBAR-acquire ! (empty encoding)" %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6308 ins_encode();
a61af66fc99e Initial load
duke
parents:
diff changeset
6309 ins_pipe(empty);
a61af66fc99e Initial load
duke
parents:
diff changeset
6310 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6311
a61af66fc99e Initial load
duke
parents:
diff changeset
6312 instruct membar_acquire_lock()
a61af66fc99e Initial load
duke
parents:
diff changeset
6313 %{
3849
f1c12354c3f7 7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents: 3842
diff changeset
6314 match(MemBarAcquireLock);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6315 ins_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
6316
a61af66fc99e Initial load
duke
parents:
diff changeset
6317 size(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
6318 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6319 ins_encode();
a61af66fc99e Initial load
duke
parents:
diff changeset
6320 ins_pipe(empty);
a61af66fc99e Initial load
duke
parents:
diff changeset
6321 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6322
a61af66fc99e Initial load
duke
parents:
diff changeset
6323 instruct membar_release()
a61af66fc99e Initial load
duke
parents:
diff changeset
6324 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6325 match(MemBarRelease);
a61af66fc99e Initial load
duke
parents:
diff changeset
6326 ins_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
6327
a61af66fc99e Initial load
duke
parents:
diff changeset
6328 size(0);
671
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 647
diff changeset
6329 format %{ "MEMBAR-release ! (empty encoding)" %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6330 ins_encode();
a61af66fc99e Initial load
duke
parents:
diff changeset
6331 ins_pipe(empty);
a61af66fc99e Initial load
duke
parents:
diff changeset
6332 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6333
a61af66fc99e Initial load
duke
parents:
diff changeset
6334 instruct membar_release_lock()
a61af66fc99e Initial load
duke
parents:
diff changeset
6335 %{
3849
f1c12354c3f7 7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents: 3842
diff changeset
6336 match(MemBarReleaseLock);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6337 ins_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
6338
a61af66fc99e Initial load
duke
parents:
diff changeset
6339 size(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
6340 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6341 ins_encode();
a61af66fc99e Initial load
duke
parents:
diff changeset
6342 ins_pipe(empty);
a61af66fc99e Initial load
duke
parents:
diff changeset
6343 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6344
671
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 647
diff changeset
6345 instruct membar_volatile(rFlagsReg cr) %{
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6346 match(MemBarVolatile);
671
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 647
diff changeset
6347 effect(KILL cr);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6348 ins_cost(400);
a61af66fc99e Initial load
duke
parents:
diff changeset
6349
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
6350 format %{
671
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 647
diff changeset
6351 $$template
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 647
diff changeset
6352 if (os::is_MP()) {
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 647
diff changeset
6353 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile"
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 647
diff changeset
6354 } else {
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 647
diff changeset
6355 $$emit$$"MEMBAR-volatile ! (empty encoding)"
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 647
diff changeset
6356 }
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 647
diff changeset
6357 %}
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 647
diff changeset
6358 ins_encode %{
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 647
diff changeset
6359 __ membar(Assembler::StoreLoad);
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 647
diff changeset
6360 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6361 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
6362 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6363
a61af66fc99e Initial load
duke
parents:
diff changeset
6364 instruct unnecessary_membar_volatile()
a61af66fc99e Initial load
duke
parents:
diff changeset
6365 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6366 match(MemBarVolatile);
a61af66fc99e Initial load
duke
parents:
diff changeset
6367 predicate(Matcher::post_store_load_barrier(n));
a61af66fc99e Initial load
duke
parents:
diff changeset
6368 ins_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
6369
a61af66fc99e Initial load
duke
parents:
diff changeset
6370 size(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
6371 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6372 ins_encode();
a61af66fc99e Initial load
duke
parents:
diff changeset
6373 ins_pipe(empty);
a61af66fc99e Initial load
duke
parents:
diff changeset
6374 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6375
4763
1dc233a8c7fe 7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents: 4762
diff changeset
6376 instruct membar_storestore() %{
1dc233a8c7fe 7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents: 4762
diff changeset
6377 match(MemBarStoreStore);
1dc233a8c7fe 7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents: 4762
diff changeset
6378 ins_cost(0);
1dc233a8c7fe 7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents: 4762
diff changeset
6379
1dc233a8c7fe 7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents: 4762
diff changeset
6380 size(0);
1dc233a8c7fe 7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents: 4762
diff changeset
6381 format %{ "MEMBAR-storestore (empty encoding)" %}
1dc233a8c7fe 7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents: 4762
diff changeset
6382 ins_encode( );
1dc233a8c7fe 7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents: 4762
diff changeset
6383 ins_pipe(empty);
1dc233a8c7fe 7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents: 4762
diff changeset
6384 %}
1dc233a8c7fe 7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents: 4762
diff changeset
6385
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6386 //----------Move Instructions--------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
6387
a61af66fc99e Initial load
duke
parents:
diff changeset
6388 instruct castX2P(rRegP dst, rRegL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6389 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6390 match(Set dst (CastX2P src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6391
a61af66fc99e Initial load
duke
parents:
diff changeset
6392 format %{ "movq $dst, $src\t# long->ptr" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6393 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6394 if ($dst$$reg != $src$$reg) {
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6395 __ movptr($dst$$Register, $src$$Register);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6396 }
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6397 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6398 ins_pipe(ialu_reg_reg); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6399 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6400
a61af66fc99e Initial load
duke
parents:
diff changeset
6401 instruct castP2X(rRegL dst, rRegP src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6402 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6403 match(Set dst (CastP2X src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6404
a61af66fc99e Initial load
duke
parents:
diff changeset
6405 format %{ "movq $dst, $src\t# ptr -> long" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6406 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6407 if ($dst$$reg != $src$$reg) {
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6408 __ movptr($dst$$Register, $src$$Register);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6409 }
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6410 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6411 ins_pipe(ialu_reg_reg); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6412 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6413
6614
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6414 // Convert oop into int for vectors alignment masking
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6415 instruct convP2I(rRegI dst, rRegP src)
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6416 %{
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6417 match(Set dst (ConvL2I (CastP2X src)));
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6418
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6419 format %{ "movl $dst, $src\t# ptr -> int" %}
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6420 ins_encode %{
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6421 __ movl($dst$$Register, $src$$Register);
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6422 %}
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6423 ins_pipe(ialu_reg_reg); // XXX
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6424 %}
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6425
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6426 // Convert compressed oop into int for vectors alignment masking
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6427 // in case of 32bit oops (heap < 4Gb).
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6428 instruct convN2I(rRegI dst, rRegN src)
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6429 %{
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6430 predicate(Universe::narrow_oop_shift() == 0);
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6431 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6432
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6433 format %{ "movl $dst, $src\t# compressed ptr -> int" %}
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6434 ins_encode %{
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6435 __ movl($dst$$Register, $src$$Register);
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6436 %}
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6437 ins_pipe(ialu_reg_reg); // XXX
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6438 %}
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6439
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6440 // Convert oop pointer into compressed form
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6441 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
221
1e026f8da827 6710487: More than half of JDI Regression tests hang with COOPs in -Xcomp mode
kvn
parents: 182
diff changeset
6442 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6443 match(Set dst (EncodeP src));
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6444 effect(KILL cr);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6445 format %{ "encode_heap_oop $dst,$src" %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6446 ins_encode %{
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6447 Register s = $src$$Register;
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6448 Register d = $dst$$Register;
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6449 if (s != d) {
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6450 __ movq(d, s);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6451 }
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6452 __ encode_heap_oop(d);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6453 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6454 ins_pipe(ialu_reg_long);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6455 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6456
124
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6457 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
221
1e026f8da827 6710487: More than half of JDI Regression tests hang with COOPs in -Xcomp mode
kvn
parents: 182
diff changeset
6458 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
124
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6459 match(Set dst (EncodeP src));
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6460 effect(KILL cr);
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6461 format %{ "encode_heap_oop_not_null $dst,$src" %}
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6462 ins_encode %{
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6463 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
124
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6464 %}
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6465 ins_pipe(ialu_reg_long);
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6466 %}
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6467
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6468 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
182
44abbb0d4c18 6709093: Compressed Oops: reduce size of compiled methods
kvn
parents: 169
diff changeset
6469 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
44abbb0d4c18 6709093: Compressed Oops: reduce size of compiled methods
kvn
parents: 169
diff changeset
6470 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6471 match(Set dst (DecodeN src));
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6472 effect(KILL cr);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6473 format %{ "decode_heap_oop $dst,$src" %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6474 ins_encode %{
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6475 Register s = $src$$Register;
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6476 Register d = $dst$$Register;
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6477 if (s != d) {
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6478 __ movq(d, s);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6479 }
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6480 __ decode_heap_oop(d);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6481 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6482 ins_pipe(ialu_reg_long);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6483 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6484
1571
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
6485 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
182
44abbb0d4c18 6709093: Compressed Oops: reduce size of compiled methods
kvn
parents: 169
diff changeset
6486 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
44abbb0d4c18 6709093: Compressed Oops: reduce size of compiled methods
kvn
parents: 169
diff changeset
6487 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
124
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6488 match(Set dst (DecodeN src));
1571
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
6489 effect(KILL cr);
124
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6490 format %{ "decode_heap_oop_not_null $dst,$src" %}
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6491 ins_encode %{
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6492 Register s = $src$$Register;
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6493 Register d = $dst$$Register;
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6494 if (s != d) {
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6495 __ decode_heap_oop_not_null(d, s);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6496 } else {
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6497 __ decode_heap_oop_not_null(d);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6498 }
124
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6499 %}
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6500 ins_pipe(ialu_reg_long);
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6501 %}
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6502
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6503
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6504 //----------Conditional Move---------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
6505 // Jump
a61af66fc99e Initial load
duke
parents:
diff changeset
6506 // dummy instruction for generating temp registers
a61af66fc99e Initial load
duke
parents:
diff changeset
6507 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6508 match(Jump (LShiftL switch_val shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
6509 ins_cost(350);
a61af66fc99e Initial load
duke
parents:
diff changeset
6510 predicate(false);
a61af66fc99e Initial load
duke
parents:
diff changeset
6511 effect(TEMP dest);
a61af66fc99e Initial load
duke
parents:
diff changeset
6512
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6513 format %{ "leaq $dest, [$constantaddress]\n\t"
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6514 "jmp [$dest + $switch_val << $shift]\n\t" %}
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6515 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6516 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6517 // to do that and the compiler is using that register as one it can allocate.
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6518 // So we build it all by hand.
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6519 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6520 // ArrayAddress dispatch(table, index);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6521 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6522 __ lea($dest$$Register, $constantaddress);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6523 __ jmp(dispatch);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6524 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6525 ins_pipe(pipe_jmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
6526 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6527
a61af66fc99e Initial load
duke
parents:
diff changeset
6528 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6529 match(Jump (AddL (LShiftL switch_val shift) offset));
a61af66fc99e Initial load
duke
parents:
diff changeset
6530 ins_cost(350);
a61af66fc99e Initial load
duke
parents:
diff changeset
6531 effect(TEMP dest);
a61af66fc99e Initial load
duke
parents:
diff changeset
6532
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6533 format %{ "leaq $dest, [$constantaddress]\n\t"
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6534 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %}
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6535 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6536 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6537 // to do that and the compiler is using that register as one it can allocate.
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6538 // So we build it all by hand.
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6539 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6540 // ArrayAddress dispatch(table, index);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6541 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6542 __ lea($dest$$Register, $constantaddress);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6543 __ jmp(dispatch);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6544 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6545 ins_pipe(pipe_jmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
6546 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6547
a61af66fc99e Initial load
duke
parents:
diff changeset
6548 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6549 match(Jump switch_val);
a61af66fc99e Initial load
duke
parents:
diff changeset
6550 ins_cost(350);
a61af66fc99e Initial load
duke
parents:
diff changeset
6551 effect(TEMP dest);
a61af66fc99e Initial load
duke
parents:
diff changeset
6552
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6553 format %{ "leaq $dest, [$constantaddress]\n\t"
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6554 "jmp [$dest + $switch_val]\n\t" %}
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6555 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6556 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6557 // to do that and the compiler is using that register as one it can allocate.
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6558 // So we build it all by hand.
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6559 // Address index(noreg, switch_reg, Address::times_1);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6560 // ArrayAddress dispatch(table, index);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6561 Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6562 __ lea($dest$$Register, $constantaddress);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6563 __ jmp(dispatch);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6564 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6565 ins_pipe(pipe_jmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
6566 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6567
a61af66fc99e Initial load
duke
parents:
diff changeset
6568 // Conditional move
a61af66fc99e Initial load
duke
parents:
diff changeset
6569 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
a61af66fc99e Initial load
duke
parents:
diff changeset
6570 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6571 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6572
a61af66fc99e Initial load
duke
parents:
diff changeset
6573 ins_cost(200); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6574 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6575 opcode(0x0F, 0x40);
a61af66fc99e Initial load
duke
parents:
diff changeset
6576 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6577 ins_pipe(pipe_cmov_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6578 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6579
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6580 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6581 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6582
a61af66fc99e Initial load
duke
parents:
diff changeset
6583 ins_cost(200); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6584 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6585 opcode(0x0F, 0x40);
a61af66fc99e Initial load
duke
parents:
diff changeset
6586 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6587 ins_pipe(pipe_cmov_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6588 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6589
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6590 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6591 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6592 ins_cost(200);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6593 expand %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6594 cmovI_regU(cop, cr, dst, src);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6595 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6596 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6597
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6598 // Conditional move
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6599 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6600 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
a61af66fc99e Initial load
duke
parents:
diff changeset
6601
a61af66fc99e Initial load
duke
parents:
diff changeset
6602 ins_cost(250); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6603 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6604 opcode(0x0F, 0x40);
a61af66fc99e Initial load
duke
parents:
diff changeset
6605 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6606 ins_pipe(pipe_cmov_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
6607 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6608
a61af66fc99e Initial load
duke
parents:
diff changeset
6609 // Conditional move
a61af66fc99e Initial load
duke
parents:
diff changeset
6610 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6611 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6612 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
a61af66fc99e Initial load
duke
parents:
diff changeset
6613
a61af66fc99e Initial load
duke
parents:
diff changeset
6614 ins_cost(250); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6615 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6616 opcode(0x0F, 0x40);
a61af66fc99e Initial load
duke
parents:
diff changeset
6617 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6618 ins_pipe(pipe_cmov_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
6619 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6620
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6621 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6622 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6623 ins_cost(250);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6624 expand %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6625 cmovI_memU(cop, cr, dst, src);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6626 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6627 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6628
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6629 // Conditional move
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6630 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6631 %{
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6632 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6633
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6634 ins_cost(200); // XXX
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6635 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6636 opcode(0x0F, 0x40);
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6637 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6638 ins_pipe(pipe_cmov_reg);
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6639 %}
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6640
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6641 // Conditional move
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6642 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src)
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6643 %{
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6644 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6645
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6646 ins_cost(200); // XXX
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6647 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6648 opcode(0x0F, 0x40);
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6649 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6650 ins_pipe(pipe_cmov_reg);
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6651 %}
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6652
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6653 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6654 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6655 ins_cost(200);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6656 expand %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6657 cmovN_regU(cop, cr, dst, src);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6658 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6659 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6660
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6661 // Conditional move
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6662 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
a61af66fc99e Initial load
duke
parents:
diff changeset
6663 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6664 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6665
a61af66fc99e Initial load
duke
parents:
diff changeset
6666 ins_cost(200); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6667 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6668 opcode(0x0F, 0x40);
a61af66fc99e Initial load
duke
parents:
diff changeset
6669 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6670 ins_pipe(pipe_cmov_reg); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6671 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6672
a61af66fc99e Initial load
duke
parents:
diff changeset
6673 // Conditional move
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6674 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src)
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6675 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6676 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6677
a61af66fc99e Initial load
duke
parents:
diff changeset
6678 ins_cost(200); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6679 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6680 opcode(0x0F, 0x40);
a61af66fc99e Initial load
duke
parents:
diff changeset
6681 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6682 ins_pipe(pipe_cmov_reg); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6683 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6684
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6685 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6686 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6687 ins_cost(200);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6688 expand %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6689 cmovP_regU(cop, cr, dst, src);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6690 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6691 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6692
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6693 // DISABLED: Requires the ADLC to emit a bottom_type call that
a61af66fc99e Initial load
duke
parents:
diff changeset
6694 // correctly meets the two pointer arguments; one is an incoming
a61af66fc99e Initial load
duke
parents:
diff changeset
6695 // register but the other is a memory operand. ALSO appears to
a61af66fc99e Initial load
duke
parents:
diff changeset
6696 // be buggy with implicit null checks.
a61af66fc99e Initial load
duke
parents:
diff changeset
6697 //
a61af66fc99e Initial load
duke
parents:
diff changeset
6698 //// Conditional move
a61af66fc99e Initial load
duke
parents:
diff changeset
6699 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6700 //%{
a61af66fc99e Initial load
duke
parents:
diff changeset
6701 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
a61af66fc99e Initial load
duke
parents:
diff changeset
6702 // ins_cost(250);
a61af66fc99e Initial load
duke
parents:
diff changeset
6703 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6704 // opcode(0x0F,0x40);
a61af66fc99e Initial load
duke
parents:
diff changeset
6705 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6706 // ins_pipe( pipe_cmov_mem );
a61af66fc99e Initial load
duke
parents:
diff changeset
6707 //%}
a61af66fc99e Initial load
duke
parents:
diff changeset
6708 //
a61af66fc99e Initial load
duke
parents:
diff changeset
6709 //// Conditional move
a61af66fc99e Initial load
duke
parents:
diff changeset
6710 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6711 //%{
a61af66fc99e Initial load
duke
parents:
diff changeset
6712 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
a61af66fc99e Initial load
duke
parents:
diff changeset
6713 // ins_cost(250);
a61af66fc99e Initial load
duke
parents:
diff changeset
6714 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6715 // opcode(0x0F,0x40);
a61af66fc99e Initial load
duke
parents:
diff changeset
6716 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6717 // ins_pipe( pipe_cmov_mem );
a61af66fc99e Initial load
duke
parents:
diff changeset
6718 //%}
a61af66fc99e Initial load
duke
parents:
diff changeset
6719
a61af66fc99e Initial load
duke
parents:
diff changeset
6720 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6721 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6722 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6723
a61af66fc99e Initial load
duke
parents:
diff changeset
6724 ins_cost(200); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6725 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6726 opcode(0x0F, 0x40);
a61af66fc99e Initial load
duke
parents:
diff changeset
6727 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6728 ins_pipe(pipe_cmov_reg); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6729 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6730
a61af66fc99e Initial load
duke
parents:
diff changeset
6731 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6732 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6733 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
a61af66fc99e Initial load
duke
parents:
diff changeset
6734
a61af66fc99e Initial load
duke
parents:
diff changeset
6735 ins_cost(200); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6736 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6737 opcode(0x0F, 0x40);
a61af66fc99e Initial load
duke
parents:
diff changeset
6738 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6739 ins_pipe(pipe_cmov_mem); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6740 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6741
a61af66fc99e Initial load
duke
parents:
diff changeset
6742 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6743 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6744 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6745
a61af66fc99e Initial load
duke
parents:
diff changeset
6746 ins_cost(200); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6747 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6748 opcode(0x0F, 0x40);
a61af66fc99e Initial load
duke
parents:
diff changeset
6749 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6750 ins_pipe(pipe_cmov_reg); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6751 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6752
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6753 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6754 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6755 ins_cost(200);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6756 expand %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6757 cmovL_regU(cop, cr, dst, src);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6758 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6759 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6760
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6761 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6762 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6763 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
a61af66fc99e Initial load
duke
parents:
diff changeset
6764
a61af66fc99e Initial load
duke
parents:
diff changeset
6765 ins_cost(200); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6766 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6767 opcode(0x0F, 0x40);
a61af66fc99e Initial load
duke
parents:
diff changeset
6768 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6769 ins_pipe(pipe_cmov_mem); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6770 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6771
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6772 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6773 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6774 ins_cost(200);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6775 expand %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6776 cmovL_memU(cop, cr, dst, src);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6777 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6778 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6779
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6780 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6781 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6782 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6783
a61af66fc99e Initial load
duke
parents:
diff changeset
6784 ins_cost(200); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6785 format %{ "jn$cop skip\t# signed cmove float\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
6786 "movss $dst, $src\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
6787 "skip:" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6788 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6789 Label Lskip;
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6790 // Invert sense of branch from sense of CMOV
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6791 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6792 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6793 __ bind(Lskip);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6794 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6795 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
6796 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6797
a61af66fc99e Initial load
duke
parents:
diff changeset
6798 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6799 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6800 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src))));
a61af66fc99e Initial load
duke
parents:
diff changeset
6801
a61af66fc99e Initial load
duke
parents:
diff changeset
6802 // ins_cost(200); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6803 // format %{ "jn$cop skip\t# signed cmove float\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
6804 // "movss $dst, $src\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
6805 // "skip:" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6806 // ins_encode(enc_cmovf_mem_branch(cop, dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6807 // ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
6808 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6809
a61af66fc99e Initial load
duke
parents:
diff changeset
6810 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6811 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6812 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6813
a61af66fc99e Initial load
duke
parents:
diff changeset
6814 ins_cost(200); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6815 format %{ "jn$cop skip\t# unsigned cmove float\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
6816 "movss $dst, $src\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
6817 "skip:" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6818 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6819 Label Lskip;
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6820 // Invert sense of branch from sense of CMOV
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6821 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6822 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6823 __ bind(Lskip);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6824 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6825 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
6826 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6827
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6828 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6829 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6830 ins_cost(200);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6831 expand %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6832 cmovF_regU(cop, cr, dst, src);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6833 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6834 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6835
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6836 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6837 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6838 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6839
a61af66fc99e Initial load
duke
parents:
diff changeset
6840 ins_cost(200); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6841 format %{ "jn$cop skip\t# signed cmove double\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
6842 "movsd $dst, $src\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
6843 "skip:" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6844 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6845 Label Lskip;
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6846 // Invert sense of branch from sense of CMOV
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6847 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6848 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6849 __ bind(Lskip);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6850 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6851 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
6852 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6853
a61af66fc99e Initial load
duke
parents:
diff changeset
6854 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6855 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6856 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6857
a61af66fc99e Initial load
duke
parents:
diff changeset
6858 ins_cost(200); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6859 format %{ "jn$cop skip\t# unsigned cmove double\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
6860 "movsd $dst, $src\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
6861 "skip:" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6862 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6863 Label Lskip;
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6864 // Invert sense of branch from sense of CMOV
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6865 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6866 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6867 __ bind(Lskip);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6868 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6869 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
6870 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6871
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6872 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6873 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6874 ins_cost(200);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6875 expand %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6876 cmovD_regU(cop, cr, dst, src);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6877 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6878 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6879
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6880 //----------Arithmetic Instructions--------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
6881 //----------Addition Instructions----------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
6882
a61af66fc99e Initial load
duke
parents:
diff changeset
6883 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
6884 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6885 match(Set dst (AddI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6886 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
6887
a61af66fc99e Initial load
duke
parents:
diff changeset
6888 format %{ "addl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6889 opcode(0x03);
a61af66fc99e Initial load
duke
parents:
diff changeset
6890 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6891 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6892 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6893
a61af66fc99e Initial load
duke
parents:
diff changeset
6894 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
6895 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6896 match(Set dst (AddI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6897 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
6898
a61af66fc99e Initial load
duke
parents:
diff changeset
6899 format %{ "addl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6900 opcode(0x81, 0x00); /* /0 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
6901 ins_encode(OpcSErm(dst, src), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6902 ins_pipe( ialu_reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
6903 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6904
a61af66fc99e Initial load
duke
parents:
diff changeset
6905 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
6906 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6907 match(Set dst (AddI dst (LoadI src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6908 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
6909
a61af66fc99e Initial load
duke
parents:
diff changeset
6910 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6911 format %{ "addl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6912 opcode(0x03);
a61af66fc99e Initial load
duke
parents:
diff changeset
6913 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6914 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
6915 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6916
a61af66fc99e Initial load
duke
parents:
diff changeset
6917 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
6918 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6919 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6920 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
6921
a61af66fc99e Initial load
duke
parents:
diff changeset
6922 ins_cost(150); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6923 format %{ "addl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6924 opcode(0x01); /* Opcode 01 /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
6925 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
6926 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6927 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6928
a61af66fc99e Initial load
duke
parents:
diff changeset
6929 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
6930 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6931 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6932 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
6933
a61af66fc99e Initial load
duke
parents:
diff changeset
6934 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6935 format %{ "addl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6936 opcode(0x81); /* Opcode 81 /0 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
6937 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6938 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
6939 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6940
a61af66fc99e Initial load
duke
parents:
diff changeset
6941 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
6942 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6943 predicate(UseIncDec);
a61af66fc99e Initial load
duke
parents:
diff changeset
6944 match(Set dst (AddI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6945 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
6946
a61af66fc99e Initial load
duke
parents:
diff changeset
6947 format %{ "incl $dst\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6948 opcode(0xFF, 0x00); // FF /0
a61af66fc99e Initial load
duke
parents:
diff changeset
6949 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
6950 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6951 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6952
a61af66fc99e Initial load
duke
parents:
diff changeset
6953 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
6954 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6955 predicate(UseIncDec);
a61af66fc99e Initial load
duke
parents:
diff changeset
6956 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6957 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
6958
a61af66fc99e Initial load
duke
parents:
diff changeset
6959 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6960 format %{ "incl $dst\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6961 opcode(0xFF); /* Opcode FF /0 */
a61af66fc99e Initial load
duke
parents:
diff changeset
6962 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
6963 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
6964 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6965
a61af66fc99e Initial load
duke
parents:
diff changeset
6966 // XXX why does that use AddI
a61af66fc99e Initial load
duke
parents:
diff changeset
6967 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
6968 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6969 predicate(UseIncDec);
a61af66fc99e Initial load
duke
parents:
diff changeset
6970 match(Set dst (AddI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6971 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
6972
a61af66fc99e Initial load
duke
parents:
diff changeset
6973 format %{ "decl $dst\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6974 opcode(0xFF, 0x01); // FF /1
a61af66fc99e Initial load
duke
parents:
diff changeset
6975 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
6976 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6977 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6978
a61af66fc99e Initial load
duke
parents:
diff changeset
6979 // XXX why does that use AddI
a61af66fc99e Initial load
duke
parents:
diff changeset
6980 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
6981 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6982 predicate(UseIncDec);
a61af66fc99e Initial load
duke
parents:
diff changeset
6983 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6984 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
6985
a61af66fc99e Initial load
duke
parents:
diff changeset
6986 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6987 format %{ "decl $dst\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6988 opcode(0xFF); /* Opcode FF /1 */
a61af66fc99e Initial load
duke
parents:
diff changeset
6989 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
6990 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
6991 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6992
a61af66fc99e Initial load
duke
parents:
diff changeset
6993 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1)
a61af66fc99e Initial load
duke
parents:
diff changeset
6994 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6995 match(Set dst (AddI src0 src1));
a61af66fc99e Initial load
duke
parents:
diff changeset
6996
a61af66fc99e Initial load
duke
parents:
diff changeset
6997 ins_cost(110);
a61af66fc99e Initial load
duke
parents:
diff changeset
6998 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6999 opcode(0x8D); /* 0x8D /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
7000 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7001 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7002 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7003
a61af66fc99e Initial load
duke
parents:
diff changeset
7004 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7005 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7006 match(Set dst (AddL dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7007 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7008
a61af66fc99e Initial load
duke
parents:
diff changeset
7009 format %{ "addq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7010 opcode(0x03);
a61af66fc99e Initial load
duke
parents:
diff changeset
7011 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7012 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7013 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7014
a61af66fc99e Initial load
duke
parents:
diff changeset
7015 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7016 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7017 match(Set dst (AddL dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7018 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7019
a61af66fc99e Initial load
duke
parents:
diff changeset
7020 format %{ "addq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7021 opcode(0x81, 0x00); /* /0 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
7022 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7023 ins_pipe( ialu_reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
7024 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7025
a61af66fc99e Initial load
duke
parents:
diff changeset
7026 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7027 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7028 match(Set dst (AddL dst (LoadL src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7029 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7030
a61af66fc99e Initial load
duke
parents:
diff changeset
7031 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7032 format %{ "addq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7033 opcode(0x03);
a61af66fc99e Initial load
duke
parents:
diff changeset
7034 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7035 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
7036 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7037
a61af66fc99e Initial load
duke
parents:
diff changeset
7038 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7039 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7040 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7041 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7042
a61af66fc99e Initial load
duke
parents:
diff changeset
7043 ins_cost(150); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7044 format %{ "addq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7045 opcode(0x01); /* Opcode 01 /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
7046 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7047 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7048 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7049
a61af66fc99e Initial load
duke
parents:
diff changeset
7050 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7051 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7052 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7053 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7054
a61af66fc99e Initial load
duke
parents:
diff changeset
7055 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7056 format %{ "addq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7057 opcode(0x81); /* Opcode 81 /0 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
7058 ins_encode(REX_mem_wide(dst),
a61af66fc99e Initial load
duke
parents:
diff changeset
7059 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7060 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
7061 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7062
a61af66fc99e Initial load
duke
parents:
diff changeset
7063 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7064 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7065 predicate(UseIncDec);
a61af66fc99e Initial load
duke
parents:
diff changeset
7066 match(Set dst (AddL dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7067 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7068
a61af66fc99e Initial load
duke
parents:
diff changeset
7069 format %{ "incq $dst\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7070 opcode(0xFF, 0x00); // FF /0
a61af66fc99e Initial load
duke
parents:
diff changeset
7071 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7072 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7073 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7074
a61af66fc99e Initial load
duke
parents:
diff changeset
7075 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7076 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7077 predicate(UseIncDec);
a61af66fc99e Initial load
duke
parents:
diff changeset
7078 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7079 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7080
a61af66fc99e Initial load
duke
parents:
diff changeset
7081 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7082 format %{ "incq $dst\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7083 opcode(0xFF); /* Opcode FF /0 */
a61af66fc99e Initial load
duke
parents:
diff changeset
7084 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7085 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
7086 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7087
a61af66fc99e Initial load
duke
parents:
diff changeset
7088 // XXX why does that use AddL
a61af66fc99e Initial load
duke
parents:
diff changeset
7089 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7090 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7091 predicate(UseIncDec);
a61af66fc99e Initial load
duke
parents:
diff changeset
7092 match(Set dst (AddL dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7093 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7094
a61af66fc99e Initial load
duke
parents:
diff changeset
7095 format %{ "decq $dst\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7096 opcode(0xFF, 0x01); // FF /1
a61af66fc99e Initial load
duke
parents:
diff changeset
7097 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7098 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7099 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7100
a61af66fc99e Initial load
duke
parents:
diff changeset
7101 // XXX why does that use AddL
a61af66fc99e Initial load
duke
parents:
diff changeset
7102 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7103 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7104 predicate(UseIncDec);
a61af66fc99e Initial load
duke
parents:
diff changeset
7105 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7106 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7107
a61af66fc99e Initial load
duke
parents:
diff changeset
7108 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7109 format %{ "decq $dst\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7110 opcode(0xFF); /* Opcode FF /1 */
a61af66fc99e Initial load
duke
parents:
diff changeset
7111 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7112 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
7113 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7114
a61af66fc99e Initial load
duke
parents:
diff changeset
7115 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1)
a61af66fc99e Initial load
duke
parents:
diff changeset
7116 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7117 match(Set dst (AddL src0 src1));
a61af66fc99e Initial load
duke
parents:
diff changeset
7118
a61af66fc99e Initial load
duke
parents:
diff changeset
7119 ins_cost(110);
a61af66fc99e Initial load
duke
parents:
diff changeset
7120 format %{ "leaq $dst, [$src0 + $src1]\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7121 opcode(0x8D); /* 0x8D /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
7122 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7123 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7124 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7125
a61af66fc99e Initial load
duke
parents:
diff changeset
7126 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7127 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7128 match(Set dst (AddP dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7129 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7130
a61af66fc99e Initial load
duke
parents:
diff changeset
7131 format %{ "addq $dst, $src\t# ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7132 opcode(0x03);
a61af66fc99e Initial load
duke
parents:
diff changeset
7133 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7134 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7135 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7136
a61af66fc99e Initial load
duke
parents:
diff changeset
7137 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7138 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7139 match(Set dst (AddP dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7140 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7141
a61af66fc99e Initial load
duke
parents:
diff changeset
7142 format %{ "addq $dst, $src\t# ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7143 opcode(0x81, 0x00); /* /0 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
7144 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7145 ins_pipe( ialu_reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
7146 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7147
a61af66fc99e Initial load
duke
parents:
diff changeset
7148 // XXX addP mem ops ????
a61af66fc99e Initial load
duke
parents:
diff changeset
7149
a61af66fc99e Initial load
duke
parents:
diff changeset
7150 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1)
a61af66fc99e Initial load
duke
parents:
diff changeset
7151 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7152 match(Set dst (AddP src0 src1));
a61af66fc99e Initial load
duke
parents:
diff changeset
7153
a61af66fc99e Initial load
duke
parents:
diff changeset
7154 ins_cost(110);
a61af66fc99e Initial load
duke
parents:
diff changeset
7155 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7156 opcode(0x8D); /* 0x8D /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
7157 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7158 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7159 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7160
a61af66fc99e Initial load
duke
parents:
diff changeset
7161 instruct checkCastPP(rRegP dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
7162 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7163 match(Set dst (CheckCastPP dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7164
a61af66fc99e Initial load
duke
parents:
diff changeset
7165 size(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
7166 format %{ "# checkcastPP of $dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7167 ins_encode(/* empty encoding */);
a61af66fc99e Initial load
duke
parents:
diff changeset
7168 ins_pipe(empty);
a61af66fc99e Initial load
duke
parents:
diff changeset
7169 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7170
a61af66fc99e Initial load
duke
parents:
diff changeset
7171 instruct castPP(rRegP dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
7172 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7173 match(Set dst (CastPP dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7174
a61af66fc99e Initial load
duke
parents:
diff changeset
7175 size(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
7176 format %{ "# castPP of $dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7177 ins_encode(/* empty encoding */);
a61af66fc99e Initial load
duke
parents:
diff changeset
7178 ins_pipe(empty);
a61af66fc99e Initial load
duke
parents:
diff changeset
7179 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7180
a61af66fc99e Initial load
duke
parents:
diff changeset
7181 instruct castII(rRegI dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
7182 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7183 match(Set dst (CastII dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7184
a61af66fc99e Initial load
duke
parents:
diff changeset
7185 size(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
7186 format %{ "# castII of $dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7187 ins_encode(/* empty encoding */);
a61af66fc99e Initial load
duke
parents:
diff changeset
7188 ins_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
7189 ins_pipe(empty);
a61af66fc99e Initial load
duke
parents:
diff changeset
7190 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7191
a61af66fc99e Initial load
duke
parents:
diff changeset
7192 // LoadP-locked same as a regular LoadP when used with compare-swap
a61af66fc99e Initial load
duke
parents:
diff changeset
7193 instruct loadPLocked(rRegP dst, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
7194 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7195 match(Set dst (LoadPLocked mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
7196
a61af66fc99e Initial load
duke
parents:
diff changeset
7197 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7198 format %{ "movq $dst, $mem\t# ptr locked" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7199 opcode(0x8B);
a61af66fc99e Initial load
duke
parents:
diff changeset
7200 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
7201 ins_pipe(ialu_reg_mem); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7202 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7203
a61af66fc99e Initial load
duke
parents:
diff changeset
7204 // Conditional-store of the updated heap-top.
a61af66fc99e Initial load
duke
parents:
diff changeset
7205 // Used during allocation of the shared heap.
a61af66fc99e Initial load
duke
parents:
diff changeset
7206 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
a61af66fc99e Initial load
duke
parents:
diff changeset
7207
a61af66fc99e Initial load
duke
parents:
diff changeset
7208 instruct storePConditional(memory heap_top_ptr,
a61af66fc99e Initial load
duke
parents:
diff changeset
7209 rax_RegP oldval, rRegP newval,
a61af66fc99e Initial load
duke
parents:
diff changeset
7210 rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7211 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7212 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
7213
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7214 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) "
a61af66fc99e Initial load
duke
parents:
diff changeset
7215 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7216 opcode(0x0F, 0xB1);
a61af66fc99e Initial load
duke
parents:
diff changeset
7217 ins_encode(lock_prefix,
a61af66fc99e Initial load
duke
parents:
diff changeset
7218 REX_reg_mem_wide(newval, heap_top_ptr),
a61af66fc99e Initial load
duke
parents:
diff changeset
7219 OpcP, OpcS,
a61af66fc99e Initial load
duke
parents:
diff changeset
7220 reg_mem(newval, heap_top_ptr));
a61af66fc99e Initial load
duke
parents:
diff changeset
7221 ins_pipe(pipe_cmpxchg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7222 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7223
420
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7224 // Conditional-store of an int value.
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7225 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7226 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr)
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7227 %{
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7228 match(Set cr (StoreIConditional mem (Binary oldval newval)));
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7229 effect(KILL oldval);
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7230
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7231 format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7232 opcode(0x0F, 0xB1);
a61af66fc99e Initial load
duke
parents:
diff changeset
7233 ins_encode(lock_prefix,
420
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7234 REX_reg_mem(newval, mem),
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7235 OpcP, OpcS,
420
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7236 reg_mem(newval, mem));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7237 ins_pipe(pipe_cmpxchg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7238 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7239
420
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7240 // Conditional-store of a long value.
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7241 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7242 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr)
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7243 %{
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7244 match(Set cr (StoreLConditional mem (Binary oldval newval)));
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7245 effect(KILL oldval);
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7246
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7247 format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7248 opcode(0x0F, 0xB1);
a61af66fc99e Initial load
duke
parents:
diff changeset
7249 ins_encode(lock_prefix,
420
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7250 REX_reg_mem_wide(newval, mem),
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7251 OpcP, OpcS,
420
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7252 reg_mem(newval, mem));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7253 ins_pipe(pipe_cmpxchg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7254 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7255
420
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7256
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7257 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7258 instruct compareAndSwapP(rRegI res,
a61af66fc99e Initial load
duke
parents:
diff changeset
7259 memory mem_ptr,
a61af66fc99e Initial load
duke
parents:
diff changeset
7260 rax_RegP oldval, rRegP newval,
a61af66fc99e Initial load
duke
parents:
diff changeset
7261 rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7262 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7263 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7264 effect(KILL cr, KILL oldval);
a61af66fc99e Initial load
duke
parents:
diff changeset
7265
a61af66fc99e Initial load
duke
parents:
diff changeset
7266 format %{ "cmpxchgq $mem_ptr,$newval\t# "
a61af66fc99e Initial load
duke
parents:
diff changeset
7267 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7268 "sete $res\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7269 "movzbl $res, $res" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7270 opcode(0x0F, 0xB1);
a61af66fc99e Initial load
duke
parents:
diff changeset
7271 ins_encode(lock_prefix,
a61af66fc99e Initial load
duke
parents:
diff changeset
7272 REX_reg_mem_wide(newval, mem_ptr),
a61af66fc99e Initial load
duke
parents:
diff changeset
7273 OpcP, OpcS,
a61af66fc99e Initial load
duke
parents:
diff changeset
7274 reg_mem(newval, mem_ptr),
a61af66fc99e Initial load
duke
parents:
diff changeset
7275 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
a61af66fc99e Initial load
duke
parents:
diff changeset
7276 REX_reg_breg(res, res), // movzbl
a61af66fc99e Initial load
duke
parents:
diff changeset
7277 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
a61af66fc99e Initial load
duke
parents:
diff changeset
7278 ins_pipe( pipe_cmpxchg );
a61af66fc99e Initial load
duke
parents:
diff changeset
7279 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7280
a61af66fc99e Initial load
duke
parents:
diff changeset
7281 instruct compareAndSwapL(rRegI res,
a61af66fc99e Initial load
duke
parents:
diff changeset
7282 memory mem_ptr,
a61af66fc99e Initial load
duke
parents:
diff changeset
7283 rax_RegL oldval, rRegL newval,
a61af66fc99e Initial load
duke
parents:
diff changeset
7284 rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7285 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7286 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7287 effect(KILL cr, KILL oldval);
a61af66fc99e Initial load
duke
parents:
diff changeset
7288
a61af66fc99e Initial load
duke
parents:
diff changeset
7289 format %{ "cmpxchgq $mem_ptr,$newval\t# "
a61af66fc99e Initial load
duke
parents:
diff changeset
7290 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7291 "sete $res\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7292 "movzbl $res, $res" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7293 opcode(0x0F, 0xB1);
a61af66fc99e Initial load
duke
parents:
diff changeset
7294 ins_encode(lock_prefix,
a61af66fc99e Initial load
duke
parents:
diff changeset
7295 REX_reg_mem_wide(newval, mem_ptr),
a61af66fc99e Initial load
duke
parents:
diff changeset
7296 OpcP, OpcS,
a61af66fc99e Initial load
duke
parents:
diff changeset
7297 reg_mem(newval, mem_ptr),
a61af66fc99e Initial load
duke
parents:
diff changeset
7298 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
a61af66fc99e Initial load
duke
parents:
diff changeset
7299 REX_reg_breg(res, res), // movzbl
a61af66fc99e Initial load
duke
parents:
diff changeset
7300 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
a61af66fc99e Initial load
duke
parents:
diff changeset
7301 ins_pipe( pipe_cmpxchg );
a61af66fc99e Initial load
duke
parents:
diff changeset
7302 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7303
a61af66fc99e Initial load
duke
parents:
diff changeset
7304 instruct compareAndSwapI(rRegI res,
a61af66fc99e Initial load
duke
parents:
diff changeset
7305 memory mem_ptr,
a61af66fc99e Initial load
duke
parents:
diff changeset
7306 rax_RegI oldval, rRegI newval,
a61af66fc99e Initial load
duke
parents:
diff changeset
7307 rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7308 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7309 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7310 effect(KILL cr, KILL oldval);
a61af66fc99e Initial load
duke
parents:
diff changeset
7311
a61af66fc99e Initial load
duke
parents:
diff changeset
7312 format %{ "cmpxchgl $mem_ptr,$newval\t# "
a61af66fc99e Initial load
duke
parents:
diff changeset
7313 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7314 "sete $res\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7315 "movzbl $res, $res" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7316 opcode(0x0F, 0xB1);
a61af66fc99e Initial load
duke
parents:
diff changeset
7317 ins_encode(lock_prefix,
a61af66fc99e Initial load
duke
parents:
diff changeset
7318 REX_reg_mem(newval, mem_ptr),
a61af66fc99e Initial load
duke
parents:
diff changeset
7319 OpcP, OpcS,
a61af66fc99e Initial load
duke
parents:
diff changeset
7320 reg_mem(newval, mem_ptr),
a61af66fc99e Initial load
duke
parents:
diff changeset
7321 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
a61af66fc99e Initial load
duke
parents:
diff changeset
7322 REX_reg_breg(res, res), // movzbl
a61af66fc99e Initial load
duke
parents:
diff changeset
7323 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
a61af66fc99e Initial load
duke
parents:
diff changeset
7324 ins_pipe( pipe_cmpxchg );
a61af66fc99e Initial load
duke
parents:
diff changeset
7325 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7326
a61af66fc99e Initial load
duke
parents:
diff changeset
7327
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7328 instruct compareAndSwapN(rRegI res,
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7329 memory mem_ptr,
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7330 rax_RegN oldval, rRegN newval,
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7331 rFlagsReg cr) %{
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7332 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7333 effect(KILL cr, KILL oldval);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7334
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7335 format %{ "cmpxchgl $mem_ptr,$newval\t# "
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7336 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7337 "sete $res\n\t"
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7338 "movzbl $res, $res" %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7339 opcode(0x0F, 0xB1);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7340 ins_encode(lock_prefix,
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7341 REX_reg_mem(newval, mem_ptr),
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7342 OpcP, OpcS,
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7343 reg_mem(newval, mem_ptr),
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7344 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7345 REX_reg_breg(res, res), // movzbl
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7346 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7347 ins_pipe( pipe_cmpxchg );
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7348 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7349
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7350 //----------Subtraction Instructions-------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
7351
a61af66fc99e Initial load
duke
parents:
diff changeset
7352 // Integer Subtraction Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
7353 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7354 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7355 match(Set dst (SubI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7356 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7357
a61af66fc99e Initial load
duke
parents:
diff changeset
7358 format %{ "subl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7359 opcode(0x2B);
a61af66fc99e Initial load
duke
parents:
diff changeset
7360 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7361 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7362 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7363
a61af66fc99e Initial load
duke
parents:
diff changeset
7364 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7365 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7366 match(Set dst (SubI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7367 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7368
a61af66fc99e Initial load
duke
parents:
diff changeset
7369 format %{ "subl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7370 opcode(0x81, 0x05); /* Opcode 81 /5 */
a61af66fc99e Initial load
duke
parents:
diff changeset
7371 ins_encode(OpcSErm(dst, src), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7372 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7373 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7374
a61af66fc99e Initial load
duke
parents:
diff changeset
7375 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7376 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7377 match(Set dst (SubI dst (LoadI src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7378 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7379
a61af66fc99e Initial load
duke
parents:
diff changeset
7380 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
7381 format %{ "subl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7382 opcode(0x2B);
a61af66fc99e Initial load
duke
parents:
diff changeset
7383 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7384 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
7385 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7386
a61af66fc99e Initial load
duke
parents:
diff changeset
7387 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7388 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7389 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7390 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7391
a61af66fc99e Initial load
duke
parents:
diff changeset
7392 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
7393 format %{ "subl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7394 opcode(0x29); /* Opcode 29 /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
7395 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7396 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7397 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7398
a61af66fc99e Initial load
duke
parents:
diff changeset
7399 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7400 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7401 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7402 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7403
a61af66fc99e Initial load
duke
parents:
diff changeset
7404 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7405 format %{ "subl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7406 opcode(0x81); /* Opcode 81 /5 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
7407 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7408 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
7409 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7410
a61af66fc99e Initial load
duke
parents:
diff changeset
7411 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7412 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7413 match(Set dst (SubL dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7414 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7415
a61af66fc99e Initial load
duke
parents:
diff changeset
7416 format %{ "subq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7417 opcode(0x2B);
a61af66fc99e Initial load
duke
parents:
diff changeset
7418 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7419 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7420 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7421
a61af66fc99e Initial load
duke
parents:
diff changeset
7422 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7423 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7424 match(Set dst (SubL dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7425 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7426
a61af66fc99e Initial load
duke
parents:
diff changeset
7427 format %{ "subq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7428 opcode(0x81, 0x05); /* Opcode 81 /5 */
a61af66fc99e Initial load
duke
parents:
diff changeset
7429 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7430 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7431 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7432
a61af66fc99e Initial load
duke
parents:
diff changeset
7433 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7434 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7435 match(Set dst (SubL dst (LoadL src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7436 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7437
a61af66fc99e Initial load
duke
parents:
diff changeset
7438 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
7439 format %{ "subq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7440 opcode(0x2B);
a61af66fc99e Initial load
duke
parents:
diff changeset
7441 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7442 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
7443 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7444
a61af66fc99e Initial load
duke
parents:
diff changeset
7445 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7446 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7447 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7448 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7449
a61af66fc99e Initial load
duke
parents:
diff changeset
7450 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
7451 format %{ "subq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7452 opcode(0x29); /* Opcode 29 /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
7453 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7454 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7455 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7456
a61af66fc99e Initial load
duke
parents:
diff changeset
7457 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7458 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7459 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7460 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7461
a61af66fc99e Initial load
duke
parents:
diff changeset
7462 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7463 format %{ "subq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7464 opcode(0x81); /* Opcode 81 /5 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
7465 ins_encode(REX_mem_wide(dst),
a61af66fc99e Initial load
duke
parents:
diff changeset
7466 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7467 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
7468 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7469
a61af66fc99e Initial load
duke
parents:
diff changeset
7470 // Subtract from a pointer
a61af66fc99e Initial load
duke
parents:
diff changeset
7471 // XXX hmpf???
a61af66fc99e Initial load
duke
parents:
diff changeset
7472 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7473 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7474 match(Set dst (AddP dst (SubI zero src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7475 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7476
a61af66fc99e Initial load
duke
parents:
diff changeset
7477 format %{ "subq $dst, $src\t# ptr - int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7478 opcode(0x2B);
a61af66fc99e Initial load
duke
parents:
diff changeset
7479 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7480 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7481 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7482
a61af66fc99e Initial load
duke
parents:
diff changeset
7483 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7484 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7485 match(Set dst (SubI zero dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7486 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7487
a61af66fc99e Initial load
duke
parents:
diff changeset
7488 format %{ "negl $dst\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7489 opcode(0xF7, 0x03); // Opcode F7 /3
a61af66fc99e Initial load
duke
parents:
diff changeset
7490 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7491 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7492 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7493
a61af66fc99e Initial load
duke
parents:
diff changeset
7494 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7495 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7496 match(Set dst (StoreI dst (SubI zero (LoadI dst))));
a61af66fc99e Initial load
duke
parents:
diff changeset
7497 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7498
a61af66fc99e Initial load
duke
parents:
diff changeset
7499 format %{ "negl $dst\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7500 opcode(0xF7, 0x03); // Opcode F7 /3
a61af66fc99e Initial load
duke
parents:
diff changeset
7501 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7502 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7503 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7504
a61af66fc99e Initial load
duke
parents:
diff changeset
7505 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7506 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7507 match(Set dst (SubL zero dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7508 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7509
a61af66fc99e Initial load
duke
parents:
diff changeset
7510 format %{ "negq $dst\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7511 opcode(0xF7, 0x03); // Opcode F7 /3
a61af66fc99e Initial load
duke
parents:
diff changeset
7512 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7513 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7514 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7515
a61af66fc99e Initial load
duke
parents:
diff changeset
7516 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7517 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7518 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
a61af66fc99e Initial load
duke
parents:
diff changeset
7519 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7520
a61af66fc99e Initial load
duke
parents:
diff changeset
7521 format %{ "negq $dst\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7522 opcode(0xF7, 0x03); // Opcode F7 /3
a61af66fc99e Initial load
duke
parents:
diff changeset
7523 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7524 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7525 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7526
a61af66fc99e Initial load
duke
parents:
diff changeset
7527
a61af66fc99e Initial load
duke
parents:
diff changeset
7528 //----------Multiplication/Division Instructions-------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
7529 // Integer Multiplication Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
7530 // Multiply Register
a61af66fc99e Initial load
duke
parents:
diff changeset
7531
a61af66fc99e Initial load
duke
parents:
diff changeset
7532 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7533 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7534 match(Set dst (MulI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7535 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7536
a61af66fc99e Initial load
duke
parents:
diff changeset
7537 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
7538 format %{ "imull $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7539 opcode(0x0F, 0xAF);
a61af66fc99e Initial load
duke
parents:
diff changeset
7540 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7541 ins_pipe(ialu_reg_reg_alu0);
a61af66fc99e Initial load
duke
parents:
diff changeset
7542 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7543
a61af66fc99e Initial load
duke
parents:
diff changeset
7544 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7545 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7546 match(Set dst (MulI src imm));
a61af66fc99e Initial load
duke
parents:
diff changeset
7547 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7548
a61af66fc99e Initial load
duke
parents:
diff changeset
7549 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
7550 format %{ "imull $dst, $src, $imm\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7551 opcode(0x69); /* 69 /r id */
a61af66fc99e Initial load
duke
parents:
diff changeset
7552 ins_encode(REX_reg_reg(dst, src),
a61af66fc99e Initial load
duke
parents:
diff changeset
7553 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
a61af66fc99e Initial load
duke
parents:
diff changeset
7554 ins_pipe(ialu_reg_reg_alu0);
a61af66fc99e Initial load
duke
parents:
diff changeset
7555 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7556
a61af66fc99e Initial load
duke
parents:
diff changeset
7557 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7558 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7559 match(Set dst (MulI dst (LoadI src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7560 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7561
a61af66fc99e Initial load
duke
parents:
diff changeset
7562 ins_cost(350);
a61af66fc99e Initial load
duke
parents:
diff changeset
7563 format %{ "imull $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7564 opcode(0x0F, 0xAF);
a61af66fc99e Initial load
duke
parents:
diff changeset
7565 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7566 ins_pipe(ialu_reg_mem_alu0);
a61af66fc99e Initial load
duke
parents:
diff changeset
7567 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7568
a61af66fc99e Initial load
duke
parents:
diff changeset
7569 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7570 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7571 match(Set dst (MulI (LoadI src) imm));
a61af66fc99e Initial load
duke
parents:
diff changeset
7572 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7573
a61af66fc99e Initial load
duke
parents:
diff changeset
7574 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
7575 format %{ "imull $dst, $src, $imm\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7576 opcode(0x69); /* 69 /r id */
a61af66fc99e Initial load
duke
parents:
diff changeset
7577 ins_encode(REX_reg_mem(dst, src),
a61af66fc99e Initial load
duke
parents:
diff changeset
7578 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
a61af66fc99e Initial load
duke
parents:
diff changeset
7579 ins_pipe(ialu_reg_mem_alu0);
a61af66fc99e Initial load
duke
parents:
diff changeset
7580 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7581
a61af66fc99e Initial load
duke
parents:
diff changeset
7582 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7583 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7584 match(Set dst (MulL dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7585 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7586
a61af66fc99e Initial load
duke
parents:
diff changeset
7587 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
7588 format %{ "imulq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7589 opcode(0x0F, 0xAF);
a61af66fc99e Initial load
duke
parents:
diff changeset
7590 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7591 ins_pipe(ialu_reg_reg_alu0);
a61af66fc99e Initial load
duke
parents:
diff changeset
7592 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7593
a61af66fc99e Initial load
duke
parents:
diff changeset
7594 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7595 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7596 match(Set dst (MulL src imm));
a61af66fc99e Initial load
duke
parents:
diff changeset
7597 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7598
a61af66fc99e Initial load
duke
parents:
diff changeset
7599 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
7600 format %{ "imulq $dst, $src, $imm\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7601 opcode(0x69); /* 69 /r id */
a61af66fc99e Initial load
duke
parents:
diff changeset
7602 ins_encode(REX_reg_reg_wide(dst, src),
a61af66fc99e Initial load
duke
parents:
diff changeset
7603 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
a61af66fc99e Initial load
duke
parents:
diff changeset
7604 ins_pipe(ialu_reg_reg_alu0);
a61af66fc99e Initial load
duke
parents:
diff changeset
7605 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7606
a61af66fc99e Initial load
duke
parents:
diff changeset
7607 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7608 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7609 match(Set dst (MulL dst (LoadL src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7610 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7611
a61af66fc99e Initial load
duke
parents:
diff changeset
7612 ins_cost(350);
a61af66fc99e Initial load
duke
parents:
diff changeset
7613 format %{ "imulq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7614 opcode(0x0F, 0xAF);
a61af66fc99e Initial load
duke
parents:
diff changeset
7615 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7616 ins_pipe(ialu_reg_mem_alu0);
a61af66fc99e Initial load
duke
parents:
diff changeset
7617 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7618
a61af66fc99e Initial load
duke
parents:
diff changeset
7619 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7620 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7621 match(Set dst (MulL (LoadL src) imm));
a61af66fc99e Initial load
duke
parents:
diff changeset
7622 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7623
a61af66fc99e Initial load
duke
parents:
diff changeset
7624 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
7625 format %{ "imulq $dst, $src, $imm\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7626 opcode(0x69); /* 69 /r id */
a61af66fc99e Initial load
duke
parents:
diff changeset
7627 ins_encode(REX_reg_mem_wide(dst, src),
a61af66fc99e Initial load
duke
parents:
diff changeset
7628 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
a61af66fc99e Initial load
duke
parents:
diff changeset
7629 ins_pipe(ialu_reg_mem_alu0);
a61af66fc99e Initial load
duke
parents:
diff changeset
7630 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7631
145
f3de1255b035 6603011: RFE: Optimize long division
rasbold
parents: 124
diff changeset
7632 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
f3de1255b035 6603011: RFE: Optimize long division
rasbold
parents: 124
diff changeset
7633 %{
f3de1255b035 6603011: RFE: Optimize long division
rasbold
parents: 124
diff changeset
7634 match(Set dst (MulHiL src rax));
f3de1255b035 6603011: RFE: Optimize long division
rasbold
parents: 124
diff changeset
7635 effect(USE_KILL rax, KILL cr);
f3de1255b035 6603011: RFE: Optimize long division
rasbold
parents: 124
diff changeset
7636
f3de1255b035 6603011: RFE: Optimize long division
rasbold
parents: 124
diff changeset
7637 ins_cost(300);
f3de1255b035 6603011: RFE: Optimize long division
rasbold
parents: 124
diff changeset
7638 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
f3de1255b035 6603011: RFE: Optimize long division
rasbold
parents: 124
diff changeset
7639 opcode(0xF7, 0x5); /* Opcode F7 /5 */
f3de1255b035 6603011: RFE: Optimize long division
rasbold
parents: 124
diff changeset
7640 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
f3de1255b035 6603011: RFE: Optimize long division
rasbold
parents: 124
diff changeset
7641 ins_pipe(ialu_reg_reg_alu0);
f3de1255b035 6603011: RFE: Optimize long division
rasbold
parents: 124
diff changeset
7642 %}
f3de1255b035 6603011: RFE: Optimize long division
rasbold
parents: 124
diff changeset
7643
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7644 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
a61af66fc99e Initial load
duke
parents:
diff changeset
7645 rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7646 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7647 match(Set rax (DivI rax div));
a61af66fc99e Initial load
duke
parents:
diff changeset
7648 effect(KILL rdx, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7649
a61af66fc99e Initial load
duke
parents:
diff changeset
7650 ins_cost(30*100+10*100); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7651 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7652 "jne,s normal\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7653 "xorl rdx, rdx\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7654 "cmpl $div, -1\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7655 "je,s done\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
7656 "normal: cdql\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7657 "idivl $div\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
7658 "done:" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7659 opcode(0xF7, 0x7); /* Opcode F7 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
7660 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
a61af66fc99e Initial load
duke
parents:
diff changeset
7661 ins_pipe(ialu_reg_reg_alu0);
a61af66fc99e Initial load
duke
parents:
diff changeset
7662 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7663
a61af66fc99e Initial load
duke
parents:
diff changeset
7664 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
a61af66fc99e Initial load
duke
parents:
diff changeset
7665 rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7666 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7667 match(Set rax (DivL rax div));
a61af66fc99e Initial load
duke
parents:
diff changeset
7668 effect(KILL rdx, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7669
a61af66fc99e Initial load
duke
parents:
diff changeset
7670 ins_cost(30*100+10*100); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7671 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7672 "cmpq rax, rdx\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7673 "jne,s normal\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7674 "xorl rdx, rdx\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7675 "cmpq $div, -1\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7676 "je,s done\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
7677 "normal: cdqq\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7678 "idivq $div\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
7679 "done:" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7680 opcode(0xF7, 0x7); /* Opcode F7 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
7681 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
a61af66fc99e Initial load
duke
parents:
diff changeset
7682 ins_pipe(ialu_reg_reg_alu0);
a61af66fc99e Initial load
duke
parents:
diff changeset
7683 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7684
a61af66fc99e Initial load
duke
parents:
diff changeset
7685 // Integer DIVMOD with Register, both quotient and mod results
a61af66fc99e Initial load
duke
parents:
diff changeset
7686 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
a61af66fc99e Initial load
duke
parents:
diff changeset
7687 rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7688 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7689 match(DivModI rax div);
a61af66fc99e Initial load
duke
parents:
diff changeset
7690 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7691
a61af66fc99e Initial load
duke
parents:
diff changeset
7692 ins_cost(30*100+10*100); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7693 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7694 "jne,s normal\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7695 "xorl rdx, rdx\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7696 "cmpl $div, -1\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7697 "je,s done\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
7698 "normal: cdql\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7699 "idivl $div\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
7700 "done:" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7701 opcode(0xF7, 0x7); /* Opcode F7 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
7702 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
a61af66fc99e Initial load
duke
parents:
diff changeset
7703 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
7704 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7705
a61af66fc99e Initial load
duke
parents:
diff changeset
7706 // Long DIVMOD with Register, both quotient and mod results
a61af66fc99e Initial load
duke
parents:
diff changeset
7707 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
a61af66fc99e Initial load
duke
parents:
diff changeset
7708 rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7709 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7710 match(DivModL rax div);
a61af66fc99e Initial load
duke
parents:
diff changeset
7711 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7712
a61af66fc99e Initial load
duke
parents:
diff changeset
7713 ins_cost(30*100+10*100); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7714 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7715 "cmpq rax, rdx\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7716 "jne,s normal\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7717 "xorl rdx, rdx\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7718 "cmpq $div, -1\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7719 "je,s done\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
7720 "normal: cdqq\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7721 "idivq $div\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
7722 "done:" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7723 opcode(0xF7, 0x7); /* Opcode F7 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
7724 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
a61af66fc99e Initial load
duke
parents:
diff changeset
7725 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
7726 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7727
a61af66fc99e Initial load
duke
parents:
diff changeset
7728 //----------- DivL-By-Constant-Expansions--------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
7729 // DivI cases are handled by the compiler
a61af66fc99e Initial load
duke
parents:
diff changeset
7730
605
98cb887364d3 6810672: Comment typos
twisti
parents: 569
diff changeset
7731 // Magic constant, reciprocal of 10
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7732 instruct loadConL_0x6666666666666667(rRegL dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
7733 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7734 effect(DEF dst);
a61af66fc99e Initial load
duke
parents:
diff changeset
7735
a61af66fc99e Initial load
duke
parents:
diff changeset
7736 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7737 ins_encode(load_immL(dst, 0x6666666666666667));
a61af66fc99e Initial load
duke
parents:
diff changeset
7738 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7739 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7740
a61af66fc99e Initial load
duke
parents:
diff changeset
7741 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7742 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7743 effect(DEF dst, USE src, USE_KILL rax, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7744
a61af66fc99e Initial load
duke
parents:
diff changeset
7745 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7746 opcode(0xF7, 0x5); /* Opcode F7 /5 */
a61af66fc99e Initial load
duke
parents:
diff changeset
7747 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7748 ins_pipe(ialu_reg_reg_alu0);
a61af66fc99e Initial load
duke
parents:
diff changeset
7749 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7750
a61af66fc99e Initial load
duke
parents:
diff changeset
7751 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7752 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7753 effect(USE_DEF dst, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7754
a61af66fc99e Initial load
duke
parents:
diff changeset
7755 format %{ "sarq $dst, #63\t# Used in div-by-10" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7756 opcode(0xC1, 0x7); /* C1 /7 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
7757 ins_encode(reg_opc_imm_wide(dst, 0x3F));
a61af66fc99e Initial load
duke
parents:
diff changeset
7758 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7759 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7760
a61af66fc99e Initial load
duke
parents:
diff changeset
7761 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7762 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7763 effect(USE_DEF dst, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7764
a61af66fc99e Initial load
duke
parents:
diff changeset
7765 format %{ "sarq $dst, #2\t# Used in div-by-10" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7766 opcode(0xC1, 0x7); /* C1 /7 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
7767 ins_encode(reg_opc_imm_wide(dst, 0x2));
a61af66fc99e Initial load
duke
parents:
diff changeset
7768 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7769 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7770
a61af66fc99e Initial load
duke
parents:
diff changeset
7771 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div)
a61af66fc99e Initial load
duke
parents:
diff changeset
7772 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7773 match(Set dst (DivL src div));
a61af66fc99e Initial load
duke
parents:
diff changeset
7774
a61af66fc99e Initial load
duke
parents:
diff changeset
7775 ins_cost((5+8)*100);
a61af66fc99e Initial load
duke
parents:
diff changeset
7776 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7777 rax_RegL rax; // Killed temp
a61af66fc99e Initial load
duke
parents:
diff changeset
7778 rFlagsReg cr; // Killed
a61af66fc99e Initial load
duke
parents:
diff changeset
7779 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667
a61af66fc99e Initial load
duke
parents:
diff changeset
7780 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src
a61af66fc99e Initial load
duke
parents:
diff changeset
7781 sarL_rReg_63(src, cr); // sarq src, 63
a61af66fc99e Initial load
duke
parents:
diff changeset
7782 sarL_rReg_2(dst, cr); // sarq rdx, 2
a61af66fc99e Initial load
duke
parents:
diff changeset
7783 subL_rReg(dst, src, cr); // subl rdx, src
a61af66fc99e Initial load
duke
parents:
diff changeset
7784 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7785 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7786
a61af66fc99e Initial load
duke
parents:
diff changeset
7787 //-----------------------------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
7788
a61af66fc99e Initial load
duke
parents:
diff changeset
7789 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
a61af66fc99e Initial load
duke
parents:
diff changeset
7790 rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7791 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7792 match(Set rdx (ModI rax div));
a61af66fc99e Initial load
duke
parents:
diff changeset
7793 effect(KILL rax, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7794
a61af66fc99e Initial load
duke
parents:
diff changeset
7795 ins_cost(300); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7796 format %{ "cmpl rax, 0x80000000\t# irem\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7797 "jne,s normal\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7798 "xorl rdx, rdx\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7799 "cmpl $div, -1\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7800 "je,s done\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
7801 "normal: cdql\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7802 "idivl $div\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
7803 "done:" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7804 opcode(0xF7, 0x7); /* Opcode F7 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
7805 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
a61af66fc99e Initial load
duke
parents:
diff changeset
7806 ins_pipe(ialu_reg_reg_alu0);
a61af66fc99e Initial load
duke
parents:
diff changeset
7807 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7808
a61af66fc99e Initial load
duke
parents:
diff changeset
7809 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
a61af66fc99e Initial load
duke
parents:
diff changeset
7810 rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7811 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7812 match(Set rdx (ModL rax div));
a61af66fc99e Initial load
duke
parents:
diff changeset
7813 effect(KILL rax, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7814
a61af66fc99e Initial load
duke
parents:
diff changeset
7815 ins_cost(300); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7816 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7817 "cmpq rax, rdx\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7818 "jne,s normal\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7819 "xorl rdx, rdx\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7820 "cmpq $div, -1\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7821 "je,s done\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
7822 "normal: cdqq\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7823 "idivq $div\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
7824 "done:" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7825 opcode(0xF7, 0x7); /* Opcode F7 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
7826 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
a61af66fc99e Initial load
duke
parents:
diff changeset
7827 ins_pipe(ialu_reg_reg_alu0);
a61af66fc99e Initial load
duke
parents:
diff changeset
7828 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7829
a61af66fc99e Initial load
duke
parents:
diff changeset
7830 // Integer Shift Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
7831 // Shift Left by one
a61af66fc99e Initial load
duke
parents:
diff changeset
7832 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7833 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7834 match(Set dst (LShiftI dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
7835 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7836
a61af66fc99e Initial load
duke
parents:
diff changeset
7837 format %{ "sall $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7838 opcode(0xD1, 0x4); /* D1 /4 */
a61af66fc99e Initial load
duke
parents:
diff changeset
7839 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7840 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7841 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7842
a61af66fc99e Initial load
duke
parents:
diff changeset
7843 // Shift Left by one
a61af66fc99e Initial load
duke
parents:
diff changeset
7844 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7845 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7846 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7847 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7848
a61af66fc99e Initial load
duke
parents:
diff changeset
7849 format %{ "sall $dst, $shift\t" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7850 opcode(0xD1, 0x4); /* D1 /4 */
a61af66fc99e Initial load
duke
parents:
diff changeset
7851 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7852 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
7853 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7854
a61af66fc99e Initial load
duke
parents:
diff changeset
7855 // Shift Left by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
7856 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7857 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7858 match(Set dst (LShiftI dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
7859 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7860
a61af66fc99e Initial load
duke
parents:
diff changeset
7861 format %{ "sall $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7862 opcode(0xC1, 0x4); /* C1 /4 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
7863 ins_encode(reg_opc_imm(dst, shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
7864 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7865 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7866
a61af66fc99e Initial load
duke
parents:
diff changeset
7867 // Shift Left by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
7868 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7869 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7870 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7871 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7872
a61af66fc99e Initial load
duke
parents:
diff changeset
7873 format %{ "sall $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7874 opcode(0xC1, 0x4); /* C1 /4 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
7875 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
7876 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
7877 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7878
a61af66fc99e Initial load
duke
parents:
diff changeset
7879 // Shift Left by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
7880 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7881 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7882 match(Set dst (LShiftI dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
7883 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7884
a61af66fc99e Initial load
duke
parents:
diff changeset
7885 format %{ "sall $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7886 opcode(0xD3, 0x4); /* D3 /4 */
a61af66fc99e Initial load
duke
parents:
diff changeset
7887 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7888 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7889 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7890
a61af66fc99e Initial load
duke
parents:
diff changeset
7891 // Shift Left by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
7892 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7893 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7894 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7895 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7896
a61af66fc99e Initial load
duke
parents:
diff changeset
7897 format %{ "sall $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7898 opcode(0xD3, 0x4); /* D3 /4 */
a61af66fc99e Initial load
duke
parents:
diff changeset
7899 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7900 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7901 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7902
a61af66fc99e Initial load
duke
parents:
diff changeset
7903 // Arithmetic shift right by one
a61af66fc99e Initial load
duke
parents:
diff changeset
7904 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7905 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7906 match(Set dst (RShiftI dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
7907 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7908
a61af66fc99e Initial load
duke
parents:
diff changeset
7909 format %{ "sarl $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7910 opcode(0xD1, 0x7); /* D1 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
7911 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7912 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7913 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7914
a61af66fc99e Initial load
duke
parents:
diff changeset
7915 // Arithmetic shift right by one
a61af66fc99e Initial load
duke
parents:
diff changeset
7916 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7917 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7918 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7919 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7920
a61af66fc99e Initial load
duke
parents:
diff changeset
7921 format %{ "sarl $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7922 opcode(0xD1, 0x7); /* D1 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
7923 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7924 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
7925 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7926
a61af66fc99e Initial load
duke
parents:
diff changeset
7927 // Arithmetic Shift Right by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
7928 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7929 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7930 match(Set dst (RShiftI dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
7931 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7932
a61af66fc99e Initial load
duke
parents:
diff changeset
7933 format %{ "sarl $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7934 opcode(0xC1, 0x7); /* C1 /7 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
7935 ins_encode(reg_opc_imm(dst, shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
7936 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
7937 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7938
a61af66fc99e Initial load
duke
parents:
diff changeset
7939 // Arithmetic Shift Right by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
7940 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7941 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7942 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7943 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7944
a61af66fc99e Initial load
duke
parents:
diff changeset
7945 format %{ "sarl $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7946 opcode(0xC1, 0x7); /* C1 /7 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
7947 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
7948 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
7949 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7950
a61af66fc99e Initial load
duke
parents:
diff changeset
7951 // Arithmetic Shift Right by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
7952 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7953 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7954 match(Set dst (RShiftI dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
7955 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7956
a61af66fc99e Initial load
duke
parents:
diff changeset
7957 format %{ "sarl $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7958 opcode(0xD3, 0x7); /* D3 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
7959 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7960 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7961 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7962
a61af66fc99e Initial load
duke
parents:
diff changeset
7963 // Arithmetic Shift Right by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
7964 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7965 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7966 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7967 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7968
a61af66fc99e Initial load
duke
parents:
diff changeset
7969 format %{ "sarl $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7970 opcode(0xD3, 0x7); /* D3 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
7971 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7972 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7973 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7974
a61af66fc99e Initial load
duke
parents:
diff changeset
7975 // Logical shift right by one
a61af66fc99e Initial load
duke
parents:
diff changeset
7976 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7977 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7978 match(Set dst (URShiftI dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
7979 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7980
a61af66fc99e Initial load
duke
parents:
diff changeset
7981 format %{ "shrl $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7982 opcode(0xD1, 0x5); /* D1 /5 */
a61af66fc99e Initial load
duke
parents:
diff changeset
7983 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7984 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7985 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7986
a61af66fc99e Initial load
duke
parents:
diff changeset
7987 // Logical shift right by one
a61af66fc99e Initial load
duke
parents:
diff changeset
7988 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7989 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7990 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7991 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7992
a61af66fc99e Initial load
duke
parents:
diff changeset
7993 format %{ "shrl $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7994 opcode(0xD1, 0x5); /* D1 /5 */
a61af66fc99e Initial load
duke
parents:
diff changeset
7995 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7996 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
7997 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7998
a61af66fc99e Initial load
duke
parents:
diff changeset
7999 // Logical Shift Right by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
8000 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8001 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8002 match(Set dst (URShiftI dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8003 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8004
a61af66fc99e Initial load
duke
parents:
diff changeset
8005 format %{ "shrl $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8006 opcode(0xC1, 0x5); /* C1 /5 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
8007 ins_encode(reg_opc_imm(dst, shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8008 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8009 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8010
a61af66fc99e Initial load
duke
parents:
diff changeset
8011 // Logical Shift Right by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
8012 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8013 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8014 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8015 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8016
a61af66fc99e Initial load
duke
parents:
diff changeset
8017 format %{ "shrl $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8018 opcode(0xC1, 0x5); /* C1 /5 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
8019 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8020 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
8021 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8022
a61af66fc99e Initial load
duke
parents:
diff changeset
8023 // Logical Shift Right by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
8024 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8025 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8026 match(Set dst (URShiftI dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8027 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8028
a61af66fc99e Initial load
duke
parents:
diff changeset
8029 format %{ "shrl $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8030 opcode(0xD3, 0x5); /* D3 /5 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8031 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8032 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8033 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8034
a61af66fc99e Initial load
duke
parents:
diff changeset
8035 // Logical Shift Right by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
8036 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8037 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8038 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8039 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8040
a61af66fc99e Initial load
duke
parents:
diff changeset
8041 format %{ "shrl $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8042 opcode(0xD3, 0x5); /* D3 /5 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8043 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8044 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8045 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8046
a61af66fc99e Initial load
duke
parents:
diff changeset
8047 // Long Shift Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
8048 // Shift Left by one
a61af66fc99e Initial load
duke
parents:
diff changeset
8049 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8050 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8051 match(Set dst (LShiftL dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8052 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8053
a61af66fc99e Initial load
duke
parents:
diff changeset
8054 format %{ "salq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8055 opcode(0xD1, 0x4); /* D1 /4 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8056 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8057 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8058 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8059
a61af66fc99e Initial load
duke
parents:
diff changeset
8060 // Shift Left by one
a61af66fc99e Initial load
duke
parents:
diff changeset
8061 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8062 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8063 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8064 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8065
a61af66fc99e Initial load
duke
parents:
diff changeset
8066 format %{ "salq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8067 opcode(0xD1, 0x4); /* D1 /4 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8068 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8069 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
8070 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8071
a61af66fc99e Initial load
duke
parents:
diff changeset
8072 // Shift Left by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
8073 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8074 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8075 match(Set dst (LShiftL dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8076 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8077
a61af66fc99e Initial load
duke
parents:
diff changeset
8078 format %{ "salq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8079 opcode(0xC1, 0x4); /* C1 /4 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
8080 ins_encode(reg_opc_imm_wide(dst, shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8081 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8082 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8083
a61af66fc99e Initial load
duke
parents:
diff changeset
8084 // Shift Left by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
8085 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8086 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8087 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8088 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8089
a61af66fc99e Initial load
duke
parents:
diff changeset
8090 format %{ "salq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8091 opcode(0xC1, 0x4); /* C1 /4 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
8092 ins_encode(REX_mem_wide(dst), OpcP,
a61af66fc99e Initial load
duke
parents:
diff changeset
8093 RM_opc_mem(secondary, dst), Con8or32(shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8094 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
8095 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8096
a61af66fc99e Initial load
duke
parents:
diff changeset
8097 // Shift Left by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
8098 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8099 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8100 match(Set dst (LShiftL dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8101 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8102
a61af66fc99e Initial load
duke
parents:
diff changeset
8103 format %{ "salq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8104 opcode(0xD3, 0x4); /* D3 /4 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8105 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8106 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8107 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8108
a61af66fc99e Initial load
duke
parents:
diff changeset
8109 // Shift Left by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
8110 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8111 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8112 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8113 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8114
a61af66fc99e Initial load
duke
parents:
diff changeset
8115 format %{ "salq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8116 opcode(0xD3, 0x4); /* D3 /4 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8117 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8118 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8119 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8120
a61af66fc99e Initial load
duke
parents:
diff changeset
8121 // Arithmetic shift right by one
a61af66fc99e Initial load
duke
parents:
diff changeset
8122 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8123 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8124 match(Set dst (RShiftL dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8125 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8126
a61af66fc99e Initial load
duke
parents:
diff changeset
8127 format %{ "sarq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8128 opcode(0xD1, 0x7); /* D1 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8129 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8130 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8131 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8132
a61af66fc99e Initial load
duke
parents:
diff changeset
8133 // Arithmetic shift right by one
a61af66fc99e Initial load
duke
parents:
diff changeset
8134 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8135 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8136 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8137 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8138
a61af66fc99e Initial load
duke
parents:
diff changeset
8139 format %{ "sarq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8140 opcode(0xD1, 0x7); /* D1 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8141 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8142 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
8143 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8144
a61af66fc99e Initial load
duke
parents:
diff changeset
8145 // Arithmetic Shift Right by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
8146 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8147 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8148 match(Set dst (RShiftL dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8149 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8150
a61af66fc99e Initial load
duke
parents:
diff changeset
8151 format %{ "sarq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8152 opcode(0xC1, 0x7); /* C1 /7 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
8153 ins_encode(reg_opc_imm_wide(dst, shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8154 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
8155 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8156
a61af66fc99e Initial load
duke
parents:
diff changeset
8157 // Arithmetic Shift Right by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
8158 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8159 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8160 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8161 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8162
a61af66fc99e Initial load
duke
parents:
diff changeset
8163 format %{ "sarq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8164 opcode(0xC1, 0x7); /* C1 /7 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
8165 ins_encode(REX_mem_wide(dst), OpcP,
a61af66fc99e Initial load
duke
parents:
diff changeset
8166 RM_opc_mem(secondary, dst), Con8or32(shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8167 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
8168 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8169
a61af66fc99e Initial load
duke
parents:
diff changeset
8170 // Arithmetic Shift Right by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
8171 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8172 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8173 match(Set dst (RShiftL dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8174 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8175
a61af66fc99e Initial load
duke
parents:
diff changeset
8176 format %{ "sarq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8177 opcode(0xD3, 0x7); /* D3 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8178 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8179 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8180 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8181
a61af66fc99e Initial load
duke
parents:
diff changeset
8182 // Arithmetic Shift Right by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
8183 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8184 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8185 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8186 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8187
a61af66fc99e Initial load
duke
parents:
diff changeset
8188 format %{ "sarq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8189 opcode(0xD3, 0x7); /* D3 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8190 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8191 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8192 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8193
a61af66fc99e Initial load
duke
parents:
diff changeset
8194 // Logical shift right by one
a61af66fc99e Initial load
duke
parents:
diff changeset
8195 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8196 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8197 match(Set dst (URShiftL dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8198 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8199
a61af66fc99e Initial load
duke
parents:
diff changeset
8200 format %{ "shrq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8201 opcode(0xD1, 0x5); /* D1 /5 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8202 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst ));
a61af66fc99e Initial load
duke
parents:
diff changeset
8203 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8204 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8205
a61af66fc99e Initial load
duke
parents:
diff changeset
8206 // Logical shift right by one
a61af66fc99e Initial load
duke
parents:
diff changeset
8207 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8208 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8209 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8210 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8211
a61af66fc99e Initial load
duke
parents:
diff changeset
8212 format %{ "shrq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8213 opcode(0xD1, 0x5); /* D1 /5 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8214 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8215 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
8216 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8217
a61af66fc99e Initial load
duke
parents:
diff changeset
8218 // Logical Shift Right by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
8219 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8220 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8221 match(Set dst (URShiftL dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8222 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8223
a61af66fc99e Initial load
duke
parents:
diff changeset
8224 format %{ "shrq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8225 opcode(0xC1, 0x5); /* C1 /5 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
8226 ins_encode(reg_opc_imm_wide(dst, shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8227 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8228 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8229
420
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
8230
0
a61af66fc99e Initial load
duke
parents:
diff changeset
8231 // Logical Shift Right by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
8232 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8233 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8234 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8235 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8236
a61af66fc99e Initial load
duke
parents:
diff changeset
8237 format %{ "shrq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8238 opcode(0xC1, 0x5); /* C1 /5 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
8239 ins_encode(REX_mem_wide(dst), OpcP,
a61af66fc99e Initial load
duke
parents:
diff changeset
8240 RM_opc_mem(secondary, dst), Con8or32(shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8241 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
8242 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8243
a61af66fc99e Initial load
duke
parents:
diff changeset
8244 // Logical Shift Right by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
8245 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8246 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8247 match(Set dst (URShiftL dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8248 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8249
a61af66fc99e Initial load
duke
parents:
diff changeset
8250 format %{ "shrq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8251 opcode(0xD3, 0x5); /* D3 /5 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8252 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8253 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8254 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8255
a61af66fc99e Initial load
duke
parents:
diff changeset
8256 // Logical Shift Right by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
8257 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8258 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8259 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8260 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8261
a61af66fc99e Initial load
duke
parents:
diff changeset
8262 format %{ "shrq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8263 opcode(0xD3, 0x5); /* D3 /5 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8264 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8265 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8266 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8267
a61af66fc99e Initial load
duke
parents:
diff changeset
8268 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
a61af66fc99e Initial load
duke
parents:
diff changeset
8269 // This idiom is used by the compiler for the i2b bytecode.
a61af66fc99e Initial load
duke
parents:
diff changeset
8270 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
a61af66fc99e Initial load
duke
parents:
diff changeset
8271 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8272 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
a61af66fc99e Initial load
duke
parents:
diff changeset
8273
a61af66fc99e Initial load
duke
parents:
diff changeset
8274 format %{ "movsbl $dst, $src\t# i2b" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8275 opcode(0x0F, 0xBE);
a61af66fc99e Initial load
duke
parents:
diff changeset
8276 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8277 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8278 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8279
a61af66fc99e Initial load
duke
parents:
diff changeset
8280 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
a61af66fc99e Initial load
duke
parents:
diff changeset
8281 // This idiom is used by the compiler the i2s bytecode.
a61af66fc99e Initial load
duke
parents:
diff changeset
8282 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
a61af66fc99e Initial load
duke
parents:
diff changeset
8283 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8284 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
a61af66fc99e Initial load
duke
parents:
diff changeset
8285
a61af66fc99e Initial load
duke
parents:
diff changeset
8286 format %{ "movswl $dst, $src\t# i2s" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8287 opcode(0x0F, 0xBF);
a61af66fc99e Initial load
duke
parents:
diff changeset
8288 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8289 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8290 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8291
a61af66fc99e Initial load
duke
parents:
diff changeset
8292 // ROL/ROR instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
8293
a61af66fc99e Initial load
duke
parents:
diff changeset
8294 // ROL expand
a61af66fc99e Initial load
duke
parents:
diff changeset
8295 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8296 effect(KILL cr, USE_DEF dst);
a61af66fc99e Initial load
duke
parents:
diff changeset
8297
a61af66fc99e Initial load
duke
parents:
diff changeset
8298 format %{ "roll $dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8299 opcode(0xD1, 0x0); /* Opcode D1 /0 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8300 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8301 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8302 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8303
a61af66fc99e Initial load
duke
parents:
diff changeset
8304 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8305 effect(USE_DEF dst, USE shift, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8306
a61af66fc99e Initial load
duke
parents:
diff changeset
8307 format %{ "roll $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8308 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
8309 ins_encode( reg_opc_imm(dst, shift) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8310 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8311 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8312
a61af66fc99e Initial load
duke
parents:
diff changeset
8313 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8314 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8315 effect(USE_DEF dst, USE shift, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8316
a61af66fc99e Initial load
duke
parents:
diff changeset
8317 format %{ "roll $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8318 opcode(0xD3, 0x0); /* Opcode D3 /0 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8319 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8320 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8321 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8322 // end of ROL expand
a61af66fc99e Initial load
duke
parents:
diff changeset
8323
a61af66fc99e Initial load
duke
parents:
diff changeset
8324 // Rotate Left by one
a61af66fc99e Initial load
duke
parents:
diff changeset
8325 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8326 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8327 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8328
a61af66fc99e Initial load
duke
parents:
diff changeset
8329 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8330 rolI_rReg_imm1(dst, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8331 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8332 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8333
a61af66fc99e Initial load
duke
parents:
diff changeset
8334 // Rotate Left by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
8335 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8336 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8337 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
a61af66fc99e Initial load
duke
parents:
diff changeset
8338 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8339
a61af66fc99e Initial load
duke
parents:
diff changeset
8340 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8341 rolI_rReg_imm8(dst, lshift, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8342 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8343 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8344
a61af66fc99e Initial load
duke
parents:
diff changeset
8345 // Rotate Left by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
8346 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8347 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8348 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
a61af66fc99e Initial load
duke
parents:
diff changeset
8349
a61af66fc99e Initial load
duke
parents:
diff changeset
8350 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8351 rolI_rReg_CL(dst, shift, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8352 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8353 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8354
a61af66fc99e Initial load
duke
parents:
diff changeset
8355 // Rotate Left by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
8356 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8357 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8358 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
a61af66fc99e Initial load
duke
parents:
diff changeset
8359
a61af66fc99e Initial load
duke
parents:
diff changeset
8360 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8361 rolI_rReg_CL(dst, shift, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8362 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8363 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8364
a61af66fc99e Initial load
duke
parents:
diff changeset
8365 // ROR expand
a61af66fc99e Initial load
duke
parents:
diff changeset
8366 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8367 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8368 effect(USE_DEF dst, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8369
a61af66fc99e Initial load
duke
parents:
diff changeset
8370 format %{ "rorl $dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8371 opcode(0xD1, 0x1); /* D1 /1 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8372 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8373 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8374 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8375
a61af66fc99e Initial load
duke
parents:
diff changeset
8376 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8377 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8378 effect(USE_DEF dst, USE shift, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8379
a61af66fc99e Initial load
duke
parents:
diff changeset
8380 format %{ "rorl $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8381 opcode(0xC1, 0x1); /* C1 /1 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
8382 ins_encode(reg_opc_imm(dst, shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8383 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8384 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8385
a61af66fc99e Initial load
duke
parents:
diff changeset
8386 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8387 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8388 effect(USE_DEF dst, USE shift, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8389
a61af66fc99e Initial load
duke
parents:
diff changeset
8390 format %{ "rorl $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8391 opcode(0xD3, 0x1); /* D3 /1 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8392 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8393 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8394 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8395 // end of ROR expand
a61af66fc99e Initial load
duke
parents:
diff changeset
8396
a61af66fc99e Initial load
duke
parents:
diff changeset
8397 // Rotate Right by one
a61af66fc99e Initial load
duke
parents:
diff changeset
8398 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8399 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8400 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8401
a61af66fc99e Initial load
duke
parents:
diff changeset
8402 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8403 rorI_rReg_imm1(dst, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8404 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8405 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8406
a61af66fc99e Initial load
duke
parents:
diff changeset
8407 // Rotate Right by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
8408 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8409 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8410 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
a61af66fc99e Initial load
duke
parents:
diff changeset
8411 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8412
a61af66fc99e Initial load
duke
parents:
diff changeset
8413 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8414 rorI_rReg_imm8(dst, rshift, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8415 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8416 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8417
a61af66fc99e Initial load
duke
parents:
diff changeset
8418 // Rotate Right by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
8419 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8420 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8421 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
a61af66fc99e Initial load
duke
parents:
diff changeset
8422
a61af66fc99e Initial load
duke
parents:
diff changeset
8423 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8424 rorI_rReg_CL(dst, shift, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8425 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8426 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8427
a61af66fc99e Initial load
duke
parents:
diff changeset
8428 // Rotate Right by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
8429 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8430 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8431 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
a61af66fc99e Initial load
duke
parents:
diff changeset
8432
a61af66fc99e Initial load
duke
parents:
diff changeset
8433 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8434 rorI_rReg_CL(dst, shift, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8435 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8436 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8437
a61af66fc99e Initial load
duke
parents:
diff changeset
8438 // for long rotate
a61af66fc99e Initial load
duke
parents:
diff changeset
8439 // ROL expand
a61af66fc99e Initial load
duke
parents:
diff changeset
8440 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8441 effect(USE_DEF dst, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8442
a61af66fc99e Initial load
duke
parents:
diff changeset
8443 format %{ "rolq $dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8444 opcode(0xD1, 0x0); /* Opcode D1 /0 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8445 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8446 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8447 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8448
a61af66fc99e Initial load
duke
parents:
diff changeset
8449 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8450 effect(USE_DEF dst, USE shift, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8451
a61af66fc99e Initial load
duke
parents:
diff changeset
8452 format %{ "rolq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8453 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
8454 ins_encode( reg_opc_imm_wide(dst, shift) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8455 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8456 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8457
a61af66fc99e Initial load
duke
parents:
diff changeset
8458 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8459 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8460 effect(USE_DEF dst, USE shift, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8461
a61af66fc99e Initial load
duke
parents:
diff changeset
8462 format %{ "rolq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8463 opcode(0xD3, 0x0); /* Opcode D3 /0 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8464 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8465 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8466 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8467 // end of ROL expand
a61af66fc99e Initial load
duke
parents:
diff changeset
8468
a61af66fc99e Initial load
duke
parents:
diff changeset
8469 // Rotate Left by one
a61af66fc99e Initial load
duke
parents:
diff changeset
8470 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8471 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8472 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8473
a61af66fc99e Initial load
duke
parents:
diff changeset
8474 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8475 rolL_rReg_imm1(dst, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8476 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8477 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8478
a61af66fc99e Initial load
duke
parents:
diff changeset
8479 // Rotate Left by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
8480 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8481 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8482 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
a61af66fc99e Initial load
duke
parents:
diff changeset
8483 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8484
a61af66fc99e Initial load
duke
parents:
diff changeset
8485 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8486 rolL_rReg_imm8(dst, lshift, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8487 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8488 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8489
a61af66fc99e Initial load
duke
parents:
diff changeset
8490 // Rotate Left by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
8491 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8492 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8493 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift))));
a61af66fc99e Initial load
duke
parents:
diff changeset
8494
a61af66fc99e Initial load
duke
parents:
diff changeset
8495 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8496 rolL_rReg_CL(dst, shift, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8497 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8498 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8499
a61af66fc99e Initial load
duke
parents:
diff changeset
8500 // Rotate Left by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
8501 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8502 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8503 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift))));
a61af66fc99e Initial load
duke
parents:
diff changeset
8504
a61af66fc99e Initial load
duke
parents:
diff changeset
8505 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8506 rolL_rReg_CL(dst, shift, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8507 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8508 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8509
a61af66fc99e Initial load
duke
parents:
diff changeset
8510 // ROR expand
a61af66fc99e Initial load
duke
parents:
diff changeset
8511 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8512 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8513 effect(USE_DEF dst, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8514
a61af66fc99e Initial load
duke
parents:
diff changeset
8515 format %{ "rorq $dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8516 opcode(0xD1, 0x1); /* D1 /1 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8517 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8518 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8519 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8520
a61af66fc99e Initial load
duke
parents:
diff changeset
8521 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8522 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8523 effect(USE_DEF dst, USE shift, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8524
a61af66fc99e Initial load
duke
parents:
diff changeset
8525 format %{ "rorq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8526 opcode(0xC1, 0x1); /* C1 /1 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
8527 ins_encode(reg_opc_imm_wide(dst, shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8528 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8529 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8530
a61af66fc99e Initial load
duke
parents:
diff changeset
8531 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8532 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8533 effect(USE_DEF dst, USE shift, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8534
a61af66fc99e Initial load
duke
parents:
diff changeset
8535 format %{ "rorq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8536 opcode(0xD3, 0x1); /* D3 /1 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8537 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8538 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8539 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8540 // end of ROR expand
a61af66fc99e Initial load
duke
parents:
diff changeset
8541
a61af66fc99e Initial load
duke
parents:
diff changeset
8542 // Rotate Right by one
a61af66fc99e Initial load
duke
parents:
diff changeset
8543 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8544 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8545 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8546
a61af66fc99e Initial load
duke
parents:
diff changeset
8547 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8548 rorL_rReg_imm1(dst, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8549 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8550 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8551
a61af66fc99e Initial load
duke
parents:
diff changeset
8552 // Rotate Right by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
8553 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8554 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8555 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
a61af66fc99e Initial load
duke
parents:
diff changeset
8556 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8557
a61af66fc99e Initial load
duke
parents:
diff changeset
8558 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8559 rorL_rReg_imm8(dst, rshift, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8560 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8561 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8562
a61af66fc99e Initial load
duke
parents:
diff changeset
8563 // Rotate Right by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
8564 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8565 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8566 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift))));
a61af66fc99e Initial load
duke
parents:
diff changeset
8567
a61af66fc99e Initial load
duke
parents:
diff changeset
8568 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8569 rorL_rReg_CL(dst, shift, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8570 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8571 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8572
a61af66fc99e Initial load
duke
parents:
diff changeset
8573 // Rotate Right by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
8574 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8575 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8576 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift))));
a61af66fc99e Initial load
duke
parents:
diff changeset
8577
a61af66fc99e Initial load
duke
parents:
diff changeset
8578 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8579 rorL_rReg_CL(dst, shift, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8580 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8581 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8582
a61af66fc99e Initial load
duke
parents:
diff changeset
8583 // Logical Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
8584
a61af66fc99e Initial load
duke
parents:
diff changeset
8585 // Integer Logical Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
8586
a61af66fc99e Initial load
duke
parents:
diff changeset
8587 // And Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
8588 // And Register with Register
a61af66fc99e Initial load
duke
parents:
diff changeset
8589 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8590 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8591 match(Set dst (AndI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8592 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8593
a61af66fc99e Initial load
duke
parents:
diff changeset
8594 format %{ "andl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8595 opcode(0x23);
a61af66fc99e Initial load
duke
parents:
diff changeset
8596 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8597 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8598 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8599
a61af66fc99e Initial load
duke
parents:
diff changeset
8600 // And Register with Immediate 255
a61af66fc99e Initial load
duke
parents:
diff changeset
8601 instruct andI_rReg_imm255(rRegI dst, immI_255 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
8602 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8603 match(Set dst (AndI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8604
a61af66fc99e Initial load
duke
parents:
diff changeset
8605 format %{ "movzbl $dst, $dst\t# int & 0xFF" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8606 opcode(0x0F, 0xB6);
a61af66fc99e Initial load
duke
parents:
diff changeset
8607 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8608 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8609 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8610
a61af66fc99e Initial load
duke
parents:
diff changeset
8611 // And Register with Immediate 255 and promote to long
a61af66fc99e Initial load
duke
parents:
diff changeset
8612 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
a61af66fc99e Initial load
duke
parents:
diff changeset
8613 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8614 match(Set dst (ConvI2L (AndI src mask)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8615
a61af66fc99e Initial load
duke
parents:
diff changeset
8616 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8617 opcode(0x0F, 0xB6);
a61af66fc99e Initial load
duke
parents:
diff changeset
8618 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8619 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8620 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8621
a61af66fc99e Initial load
duke
parents:
diff changeset
8622 // And Register with Immediate 65535
a61af66fc99e Initial load
duke
parents:
diff changeset
8623 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
8624 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8625 match(Set dst (AndI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8626
a61af66fc99e Initial load
duke
parents:
diff changeset
8627 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8628 opcode(0x0F, 0xB7);
a61af66fc99e Initial load
duke
parents:
diff changeset
8629 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8630 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8631 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8632
a61af66fc99e Initial load
duke
parents:
diff changeset
8633 // And Register with Immediate 65535 and promote to long
a61af66fc99e Initial load
duke
parents:
diff changeset
8634 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
a61af66fc99e Initial load
duke
parents:
diff changeset
8635 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8636 match(Set dst (ConvI2L (AndI src mask)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8637
a61af66fc99e Initial load
duke
parents:
diff changeset
8638 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8639 opcode(0x0F, 0xB7);
a61af66fc99e Initial load
duke
parents:
diff changeset
8640 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8641 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8642 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8643
a61af66fc99e Initial load
duke
parents:
diff changeset
8644 // And Register with Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
8645 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8646 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8647 match(Set dst (AndI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8648 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8649
a61af66fc99e Initial load
duke
parents:
diff changeset
8650 format %{ "andl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8651 opcode(0x81, 0x04); /* Opcode 81 /4 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8652 ins_encode(OpcSErm(dst, src), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8653 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8654 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8655
a61af66fc99e Initial load
duke
parents:
diff changeset
8656 // And Register with Memory
a61af66fc99e Initial load
duke
parents:
diff changeset
8657 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8658 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8659 match(Set dst (AndI dst (LoadI src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8660 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8661
a61af66fc99e Initial load
duke
parents:
diff changeset
8662 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
8663 format %{ "andl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8664 opcode(0x23);
a61af66fc99e Initial load
duke
parents:
diff changeset
8665 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8666 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
8667 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8668
a61af66fc99e Initial load
duke
parents:
diff changeset
8669 // And Memory with Register
a61af66fc99e Initial load
duke
parents:
diff changeset
8670 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8671 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8672 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8673 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8674
a61af66fc99e Initial load
duke
parents:
diff changeset
8675 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
8676 format %{ "andl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8677 opcode(0x21); /* Opcode 21 /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
8678 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8679 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8680 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8681
a61af66fc99e Initial load
duke
parents:
diff changeset
8682 // And Memory with Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
8683 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8684 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8685 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8686 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8687
a61af66fc99e Initial load
duke
parents:
diff changeset
8688 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
8689 format %{ "andl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8690 opcode(0x81, 0x4); /* Opcode 81 /4 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
8691 ins_encode(REX_mem(dst), OpcSE(src),
a61af66fc99e Initial load
duke
parents:
diff changeset
8692 RM_opc_mem(secondary, dst), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8693 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
8694 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8695
a61af66fc99e Initial load
duke
parents:
diff changeset
8696 // Or Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
8697 // Or Register with Register
a61af66fc99e Initial load
duke
parents:
diff changeset
8698 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8699 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8700 match(Set dst (OrI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8701 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8702
a61af66fc99e Initial load
duke
parents:
diff changeset
8703 format %{ "orl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8704 opcode(0x0B);
a61af66fc99e Initial load
duke
parents:
diff changeset
8705 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8706 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8707 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8708
a61af66fc99e Initial load
duke
parents:
diff changeset
8709 // Or Register with Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
8710 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8711 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8712 match(Set dst (OrI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8713 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8714
a61af66fc99e Initial load
duke
parents:
diff changeset
8715 format %{ "orl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8716 opcode(0x81, 0x01); /* Opcode 81 /1 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
8717 ins_encode(OpcSErm(dst, src), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8718 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8719 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8720
a61af66fc99e Initial load
duke
parents:
diff changeset
8721 // Or Register with Memory
a61af66fc99e Initial load
duke
parents:
diff changeset
8722 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8723 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8724 match(Set dst (OrI dst (LoadI src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8725 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8726
a61af66fc99e Initial load
duke
parents:
diff changeset
8727 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
8728 format %{ "orl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8729 opcode(0x0B);
a61af66fc99e Initial load
duke
parents:
diff changeset
8730 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8731 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
8732 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8733
a61af66fc99e Initial load
duke
parents:
diff changeset
8734 // Or Memory with Register
a61af66fc99e Initial load
duke
parents:
diff changeset
8735 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8736 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8737 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8738 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8739
a61af66fc99e Initial load
duke
parents:
diff changeset
8740 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
8741 format %{ "orl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8742 opcode(0x09); /* Opcode 09 /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
8743 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8744 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8745 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8746
a61af66fc99e Initial load
duke
parents:
diff changeset
8747 // Or Memory with Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
8748 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8749 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8750 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8751 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8752
a61af66fc99e Initial load
duke
parents:
diff changeset
8753 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
8754 format %{ "orl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8755 opcode(0x81, 0x1); /* Opcode 81 /1 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
8756 ins_encode(REX_mem(dst), OpcSE(src),
a61af66fc99e Initial load
duke
parents:
diff changeset
8757 RM_opc_mem(secondary, dst), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8758 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
8759 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8760
a61af66fc99e Initial load
duke
parents:
diff changeset
8761 // Xor Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
8762 // Xor Register with Register
a61af66fc99e Initial load
duke
parents:
diff changeset
8763 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8764 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8765 match(Set dst (XorI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8766 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8767
a61af66fc99e Initial load
duke
parents:
diff changeset
8768 format %{ "xorl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8769 opcode(0x33);
a61af66fc99e Initial load
duke
parents:
diff changeset
8770 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8771 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8772 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8773
403
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
8774 // Xor Register with Immediate -1
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
8775 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
8776 match(Set dst (XorI dst imm));
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
8777
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
8778 format %{ "not $dst" %}
403
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
8779 ins_encode %{
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
8780 __ notl($dst$$Register);
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
8781 %}
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
8782 ins_pipe(ialu_reg);
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
8783 %}
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
8784
0
a61af66fc99e Initial load
duke
parents:
diff changeset
8785 // Xor Register with Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
8786 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8787 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8788 match(Set dst (XorI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8789 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8790
a61af66fc99e Initial load
duke
parents:
diff changeset
8791 format %{ "xorl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8792 opcode(0x81, 0x06); /* Opcode 81 /6 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
8793 ins_encode(OpcSErm(dst, src), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8794 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8795 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8796
a61af66fc99e Initial load
duke
parents:
diff changeset
8797 // Xor Register with Memory
a61af66fc99e Initial load
duke
parents:
diff changeset
8798 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8799 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8800 match(Set dst (XorI dst (LoadI src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8801 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8802
a61af66fc99e Initial load
duke
parents:
diff changeset
8803 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
8804 format %{ "xorl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8805 opcode(0x33);
a61af66fc99e Initial load
duke
parents:
diff changeset
8806 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8807 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
8808 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8809
a61af66fc99e Initial load
duke
parents:
diff changeset
8810 // Xor Memory with Register
a61af66fc99e Initial load
duke
parents:
diff changeset
8811 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8812 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8813 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8814 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8815
a61af66fc99e Initial load
duke
parents:
diff changeset
8816 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
8817 format %{ "xorl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8818 opcode(0x31); /* Opcode 31 /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
8819 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8820 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8821 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8822
a61af66fc99e Initial load
duke
parents:
diff changeset
8823 // Xor Memory with Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
8824 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8825 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8826 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8827 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8828
a61af66fc99e Initial load
duke
parents:
diff changeset
8829 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
8830 format %{ "xorl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8831 opcode(0x81, 0x6); /* Opcode 81 /6 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
8832 ins_encode(REX_mem(dst), OpcSE(src),
a61af66fc99e Initial load
duke
parents:
diff changeset
8833 RM_opc_mem(secondary, dst), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8834 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
8835 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8836
a61af66fc99e Initial load
duke
parents:
diff changeset
8837
a61af66fc99e Initial load
duke
parents:
diff changeset
8838 // Long Logical Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
8839
a61af66fc99e Initial load
duke
parents:
diff changeset
8840 // And Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
8841 // And Register with Register
a61af66fc99e Initial load
duke
parents:
diff changeset
8842 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8843 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8844 match(Set dst (AndL dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8845 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8846
a61af66fc99e Initial load
duke
parents:
diff changeset
8847 format %{ "andq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8848 opcode(0x23);
a61af66fc99e Initial load
duke
parents:
diff changeset
8849 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8850 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8851 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8852
a61af66fc99e Initial load
duke
parents:
diff changeset
8853 // And Register with Immediate 255
a61af66fc99e Initial load
duke
parents:
diff changeset
8854 instruct andL_rReg_imm255(rRegL dst, immL_255 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
8855 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8856 match(Set dst (AndL dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8857
569
2cacccded90f 6805950: Typos in andL_rReg_imm instructions in x86_64.ad
twisti
parents: 558
diff changeset
8858 format %{ "movzbq $dst, $dst\t# long & 0xFF" %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
8859 opcode(0x0F, 0xB6);
a61af66fc99e Initial load
duke
parents:
diff changeset
8860 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8861 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8862 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8863
a61af66fc99e Initial load
duke
parents:
diff changeset
8864 // And Register with Immediate 65535
569
2cacccded90f 6805950: Typos in andL_rReg_imm instructions in x86_64.ad
twisti
parents: 558
diff changeset
8865 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src)
0
a61af66fc99e Initial load
duke
parents:
diff changeset
8866 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8867 match(Set dst (AndL dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8868
a61af66fc99e Initial load
duke
parents:
diff changeset
8869 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8870 opcode(0x0F, 0xB7);
a61af66fc99e Initial load
duke
parents:
diff changeset
8871 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8872 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8873 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8874
a61af66fc99e Initial load
duke
parents:
diff changeset
8875 // And Register with Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
8876 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8877 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8878 match(Set dst (AndL dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8879 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8880
a61af66fc99e Initial load
duke
parents:
diff changeset
8881 format %{ "andq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8882 opcode(0x81, 0x04); /* Opcode 81 /4 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8883 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8884 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8885 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8886
a61af66fc99e Initial load
duke
parents:
diff changeset
8887 // And Register with Memory
a61af66fc99e Initial load
duke
parents:
diff changeset
8888 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8889 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8890 match(Set dst (AndL dst (LoadL src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8891 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8892
a61af66fc99e Initial load
duke
parents:
diff changeset
8893 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
8894 format %{ "andq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8895 opcode(0x23);
a61af66fc99e Initial load
duke
parents:
diff changeset
8896 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8897 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
8898 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8899
a61af66fc99e Initial load
duke
parents:
diff changeset
8900 // And Memory with Register
a61af66fc99e Initial load
duke
parents:
diff changeset
8901 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8902 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8903 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8904 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8905
a61af66fc99e Initial load
duke
parents:
diff changeset
8906 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
8907 format %{ "andq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8908 opcode(0x21); /* Opcode 21 /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
8909 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8910 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8911 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8912
a61af66fc99e Initial load
duke
parents:
diff changeset
8913 // And Memory with Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
8914 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8915 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8916 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8917 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8918
a61af66fc99e Initial load
duke
parents:
diff changeset
8919 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
8920 format %{ "andq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8921 opcode(0x81, 0x4); /* Opcode 81 /4 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
8922 ins_encode(REX_mem_wide(dst), OpcSE(src),
a61af66fc99e Initial load
duke
parents:
diff changeset
8923 RM_opc_mem(secondary, dst), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8924 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
8925 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8926
a61af66fc99e Initial load
duke
parents:
diff changeset
8927 // Or Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
8928 // Or Register with Register
a61af66fc99e Initial load
duke
parents:
diff changeset
8929 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8930 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8931 match(Set dst (OrL dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8932 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8933
a61af66fc99e Initial load
duke
parents:
diff changeset
8934 format %{ "orq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8935 opcode(0x0B);
a61af66fc99e Initial load
duke
parents:
diff changeset
8936 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8937 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8938 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8939
420
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
8940 // Use any_RegP to match R15 (TLS register) without spilling.
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
8941 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
8942 match(Set dst (OrL dst (CastP2X src)));
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
8943 effect(KILL cr);
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
8944
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
8945 format %{ "orq $dst, $src\t# long" %}
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
8946 opcode(0x0B);
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
8947 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
8948 ins_pipe(ialu_reg_reg);
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
8949 %}
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
8950
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
8951
0
a61af66fc99e Initial load
duke
parents:
diff changeset
8952 // Or Register with Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
8953 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8954 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8955 match(Set dst (OrL dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8956 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8957
a61af66fc99e Initial load
duke
parents:
diff changeset
8958 format %{ "orq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8959 opcode(0x81, 0x01); /* Opcode 81 /1 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
8960 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8961 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8962 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8963
a61af66fc99e Initial load
duke
parents:
diff changeset
8964 // Or Register with Memory
a61af66fc99e Initial load
duke
parents:
diff changeset
8965 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8966 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8967 match(Set dst (OrL dst (LoadL src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8968 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8969
a61af66fc99e Initial load
duke
parents:
diff changeset
8970 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
8971 format %{ "orq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8972 opcode(0x0B);
a61af66fc99e Initial load
duke
parents:
diff changeset
8973 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8974 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
8975 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8976
a61af66fc99e Initial load
duke
parents:
diff changeset
8977 // Or Memory with Register
a61af66fc99e Initial load
duke
parents:
diff changeset
8978 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8979 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8980 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8981 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8982
a61af66fc99e Initial load
duke
parents:
diff changeset
8983 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
8984 format %{ "orq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8985 opcode(0x09); /* Opcode 09 /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
8986 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8987 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8988 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8989
a61af66fc99e Initial load
duke
parents:
diff changeset
8990 // Or Memory with Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
8991 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8992 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8993 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8994 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8995
a61af66fc99e Initial load
duke
parents:
diff changeset
8996 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
8997 format %{ "orq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8998 opcode(0x81, 0x1); /* Opcode 81 /1 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
8999 ins_encode(REX_mem_wide(dst), OpcSE(src),
a61af66fc99e Initial load
duke
parents:
diff changeset
9000 RM_opc_mem(secondary, dst), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9001 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
9002 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9003
a61af66fc99e Initial load
duke
parents:
diff changeset
9004 // Xor Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
9005 // Xor Register with Register
a61af66fc99e Initial load
duke
parents:
diff changeset
9006 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9007 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9008 match(Set dst (XorL dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9009 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9010
a61af66fc99e Initial load
duke
parents:
diff changeset
9011 format %{ "xorq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9012 opcode(0x33);
a61af66fc99e Initial load
duke
parents:
diff changeset
9013 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9014 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9015 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9016
403
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
9017 // Xor Register with Immediate -1
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
9018 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
9019 match(Set dst (XorL dst imm));
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
9020
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
9021 format %{ "notq $dst" %}
403
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
9022 ins_encode %{
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
9023 __ notq($dst$$Register);
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
9024 %}
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
9025 ins_pipe(ialu_reg);
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
9026 %}
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
9027
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9028 // Xor Register with Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
9029 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9030 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9031 match(Set dst (XorL dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9032 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9033
a61af66fc99e Initial load
duke
parents:
diff changeset
9034 format %{ "xorq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9035 opcode(0x81, 0x06); /* Opcode 81 /6 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
9036 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9037 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9038 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9039
a61af66fc99e Initial load
duke
parents:
diff changeset
9040 // Xor Register with Memory
a61af66fc99e Initial load
duke
parents:
diff changeset
9041 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9042 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9043 match(Set dst (XorL dst (LoadL src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9044 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9045
a61af66fc99e Initial load
duke
parents:
diff changeset
9046 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
9047 format %{ "xorq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9048 opcode(0x33);
a61af66fc99e Initial load
duke
parents:
diff changeset
9049 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9050 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
9051 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9052
a61af66fc99e Initial load
duke
parents:
diff changeset
9053 // Xor Memory with Register
a61af66fc99e Initial load
duke
parents:
diff changeset
9054 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9055 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9056 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9057 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9058
a61af66fc99e Initial load
duke
parents:
diff changeset
9059 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
9060 format %{ "xorq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9061 opcode(0x31); /* Opcode 31 /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
9062 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9063 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9064 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9065
a61af66fc99e Initial load
duke
parents:
diff changeset
9066 // Xor Memory with Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
9067 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9068 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9069 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9070 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9071
a61af66fc99e Initial load
duke
parents:
diff changeset
9072 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
9073 format %{ "xorq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9074 opcode(0x81, 0x6); /* Opcode 81 /6 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
9075 ins_encode(REX_mem_wide(dst), OpcSE(src),
a61af66fc99e Initial load
duke
parents:
diff changeset
9076 RM_opc_mem(secondary, dst), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9077 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
9078 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9079
a61af66fc99e Initial load
duke
parents:
diff changeset
9080 // Convert Int to Boolean
a61af66fc99e Initial load
duke
parents:
diff changeset
9081 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9082 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9083 match(Set dst (Conv2B src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9084 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9085
a61af66fc99e Initial load
duke
parents:
diff changeset
9086 format %{ "testl $src, $src\t# ci2b\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9087 "setnz $dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9088 "movzbl $dst, $dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9089 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl
a61af66fc99e Initial load
duke
parents:
diff changeset
9090 setNZ_reg(dst),
a61af66fc99e Initial load
duke
parents:
diff changeset
9091 REX_reg_breg(dst, dst), // movzbl
a61af66fc99e Initial load
duke
parents:
diff changeset
9092 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9093 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
9094 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9095
a61af66fc99e Initial load
duke
parents:
diff changeset
9096 // Convert Pointer to Boolean
a61af66fc99e Initial load
duke
parents:
diff changeset
9097 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9098 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9099 match(Set dst (Conv2B src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9100 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9101
a61af66fc99e Initial load
duke
parents:
diff changeset
9102 format %{ "testq $src, $src\t# cp2b\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9103 "setnz $dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9104 "movzbl $dst, $dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9105 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq
a61af66fc99e Initial load
duke
parents:
diff changeset
9106 setNZ_reg(dst),
a61af66fc99e Initial load
duke
parents:
diff changeset
9107 REX_reg_breg(dst, dst), // movzbl
a61af66fc99e Initial load
duke
parents:
diff changeset
9108 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9109 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
9110 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9111
a61af66fc99e Initial load
duke
parents:
diff changeset
9112 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9113 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9114 match(Set dst (CmpLTMask p q));
a61af66fc99e Initial load
duke
parents:
diff changeset
9115 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9116
a61af66fc99e Initial load
duke
parents:
diff changeset
9117 ins_cost(400); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
9118 format %{ "cmpl $p, $q\t# cmpLTMask\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9119 "setlt $dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9120 "movzbl $dst, $dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9121 "negl $dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9122 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl
a61af66fc99e Initial load
duke
parents:
diff changeset
9123 setLT_reg(dst),
a61af66fc99e Initial load
duke
parents:
diff changeset
9124 REX_reg_breg(dst, dst), // movzbl
a61af66fc99e Initial load
duke
parents:
diff changeset
9125 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst),
a61af66fc99e Initial load
duke
parents:
diff changeset
9126 neg_reg(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9127 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
9128 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9129
a61af66fc99e Initial load
duke
parents:
diff changeset
9130 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9131 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9132 match(Set dst (CmpLTMask dst zero));
a61af66fc99e Initial load
duke
parents:
diff changeset
9133 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9134
a61af66fc99e Initial load
duke
parents:
diff changeset
9135 ins_cost(100); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
9136 format %{ "sarl $dst, #31\t# cmpLTMask0" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9137 opcode(0xC1, 0x7); /* C1 /7 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
9138 ins_encode(reg_opc_imm(dst, 0x1F));
a61af66fc99e Initial load
duke
parents:
diff changeset
9139 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9140 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9141
a61af66fc99e Initial load
duke
parents:
diff changeset
9142
3738
c7c81f18c834 7048332: Cadd_cmpLTMask doesn't handle 64-bit tmp register properly
kvn
parents: 2404
diff changeset
9143 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rRegI tmp, rFlagsReg cr)
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9144 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9145 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9146 effect(TEMP tmp, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9147
a61af66fc99e Initial load
duke
parents:
diff changeset
9148 ins_cost(400); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
9149 format %{ "subl $p, $q\t# cadd_cmpLTMask1\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9150 "sbbl $tmp, $tmp\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9151 "andl $tmp, $y\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9152 "addl $p, $tmp" %}
3738
c7c81f18c834 7048332: Cadd_cmpLTMask doesn't handle 64-bit tmp register properly
kvn
parents: 2404
diff changeset
9153 ins_encode %{
c7c81f18c834 7048332: Cadd_cmpLTMask doesn't handle 64-bit tmp register properly
kvn
parents: 2404
diff changeset
9154 Register Rp = $p$$Register;
c7c81f18c834 7048332: Cadd_cmpLTMask doesn't handle 64-bit tmp register properly
kvn
parents: 2404
diff changeset
9155 Register Rq = $q$$Register;
c7c81f18c834 7048332: Cadd_cmpLTMask doesn't handle 64-bit tmp register properly
kvn
parents: 2404
diff changeset
9156 Register Ry = $y$$Register;
c7c81f18c834 7048332: Cadd_cmpLTMask doesn't handle 64-bit tmp register properly
kvn
parents: 2404
diff changeset
9157 Register Rt = $tmp$$Register;
c7c81f18c834 7048332: Cadd_cmpLTMask doesn't handle 64-bit tmp register properly
kvn
parents: 2404
diff changeset
9158 __ subl(Rp, Rq);
c7c81f18c834 7048332: Cadd_cmpLTMask doesn't handle 64-bit tmp register properly
kvn
parents: 2404
diff changeset
9159 __ sbbl(Rt, Rt);
c7c81f18c834 7048332: Cadd_cmpLTMask doesn't handle 64-bit tmp register properly
kvn
parents: 2404
diff changeset
9160 __ andl(Rt, Ry);
c7c81f18c834 7048332: Cadd_cmpLTMask doesn't handle 64-bit tmp register properly
kvn
parents: 2404
diff changeset
9161 __ addl(Rp, Rt);
c7c81f18c834 7048332: Cadd_cmpLTMask doesn't handle 64-bit tmp register properly
kvn
parents: 2404
diff changeset
9162 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9163 ins_pipe(pipe_cmplt);
a61af66fc99e Initial load
duke
parents:
diff changeset
9164 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9165
a61af66fc99e Initial load
duke
parents:
diff changeset
9166 //---------- FP Instructions------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
9167
a61af66fc99e Initial load
duke
parents:
diff changeset
9168 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
a61af66fc99e Initial load
duke
parents:
diff changeset
9169 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9170 match(Set cr (CmpF src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
9171
a61af66fc99e Initial load
duke
parents:
diff changeset
9172 ins_cost(145);
a61af66fc99e Initial load
duke
parents:
diff changeset
9173 format %{ "ucomiss $src1, $src2\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9174 "jnp,s exit\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9175 "pushfq\t# saw NaN, set CF\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9176 "andq [rsp], #0xffffff2b\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9177 "popfq\n"
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9178 "exit:" %}
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9179 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9180 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9181 emit_cmpfp_fixup(_masm);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9182 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9183 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
9184 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9185
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9186 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9187 match(Set cr (CmpF src1 src2));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9188
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9189 ins_cost(100);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9190 format %{ "ucomiss $src1, $src2" %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9191 ins_encode %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9192 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9193 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9194 ins_pipe(pipe_slow);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9195 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9196
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9197 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2)
a61af66fc99e Initial load
duke
parents:
diff changeset
9198 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9199 match(Set cr (CmpF src1 (LoadF src2)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9200
a61af66fc99e Initial load
duke
parents:
diff changeset
9201 ins_cost(145);
a61af66fc99e Initial load
duke
parents:
diff changeset
9202 format %{ "ucomiss $src1, $src2\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9203 "jnp,s exit\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9204 "pushfq\t# saw NaN, set CF\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9205 "andq [rsp], #0xffffff2b\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9206 "popfq\n"
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9207 "exit:" %}
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9208 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9209 __ ucomiss($src1$$XMMRegister, $src2$$Address);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9210 emit_cmpfp_fixup(_masm);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9211 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9212 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
9213 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9214
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9215 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9216 match(Set cr (CmpF src1 (LoadF src2)));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9217
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9218 ins_cost(100);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9219 format %{ "ucomiss $src1, $src2" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9220 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9221 __ ucomiss($src1$$XMMRegister, $src2$$Address);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9222 %}
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9223 ins_pipe(pipe_slow);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9224 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9225
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9226 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9227 match(Set cr (CmpF src con));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9228
a61af66fc99e Initial load
duke
parents:
diff changeset
9229 ins_cost(145);
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9230 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9231 "jnp,s exit\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9232 "pushfq\t# saw NaN, set CF\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9233 "andq [rsp], #0xffffff2b\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9234 "popfq\n"
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9235 "exit:" %}
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9236 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9237 __ ucomiss($src$$XMMRegister, $constantaddress($con));
3783
de6a837d75cf 7056380: VM crashes with SIGSEGV in compiled code
never
parents: 3738
diff changeset
9238 emit_cmpfp_fixup(_masm);
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9239 %}
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9240 ins_pipe(pipe_slow);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9241 %}
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9242
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9243 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9244 match(Set cr (CmpF src con));
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9245 ins_cost(100);
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9246 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %}
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9247 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9248 __ ucomiss($src$$XMMRegister, $constantaddress($con));
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9249 %}
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9250 ins_pipe(pipe_slow);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9251 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9252
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9253 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
a61af66fc99e Initial load
duke
parents:
diff changeset
9254 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9255 match(Set cr (CmpD src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
9256
a61af66fc99e Initial load
duke
parents:
diff changeset
9257 ins_cost(145);
a61af66fc99e Initial load
duke
parents:
diff changeset
9258 format %{ "ucomisd $src1, $src2\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9259 "jnp,s exit\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9260 "pushfq\t# saw NaN, set CF\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9261 "andq [rsp], #0xffffff2b\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9262 "popfq\n"
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9263 "exit:" %}
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9264 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9265 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9266 emit_cmpfp_fixup(_masm);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9267 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9268 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
9269 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9270
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9271 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9272 match(Set cr (CmpD src1 src2));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9273
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9274 ins_cost(100);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9275 format %{ "ucomisd $src1, $src2 test" %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9276 ins_encode %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9277 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9278 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9279 ins_pipe(pipe_slow);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9280 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9281
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9282 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2)
a61af66fc99e Initial load
duke
parents:
diff changeset
9283 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9284 match(Set cr (CmpD src1 (LoadD src2)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9285
a61af66fc99e Initial load
duke
parents:
diff changeset
9286 ins_cost(145);
a61af66fc99e Initial load
duke
parents:
diff changeset
9287 format %{ "ucomisd $src1, $src2\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9288 "jnp,s exit\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9289 "pushfq\t# saw NaN, set CF\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9290 "andq [rsp], #0xffffff2b\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9291 "popfq\n"
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9292 "exit:" %}
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9293 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9294 __ ucomisd($src1$$XMMRegister, $src2$$Address);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9295 emit_cmpfp_fixup(_masm);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9296 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9297 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
9298 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9299
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9300 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9301 match(Set cr (CmpD src1 (LoadD src2)));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9302
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9303 ins_cost(100);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9304 format %{ "ucomisd $src1, $src2" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9305 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9306 __ ucomisd($src1$$XMMRegister, $src2$$Address);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9307 %}
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9308 ins_pipe(pipe_slow);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9309 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9310
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9311 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9312 match(Set cr (CmpD src con));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9313
a61af66fc99e Initial load
duke
parents:
diff changeset
9314 ins_cost(145);
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9315 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9316 "jnp,s exit\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9317 "pushfq\t# saw NaN, set CF\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9318 "andq [rsp], #0xffffff2b\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9319 "popfq\n"
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9320 "exit:" %}
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9321 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9322 __ ucomisd($src$$XMMRegister, $constantaddress($con));
3783
de6a837d75cf 7056380: VM crashes with SIGSEGV in compiled code
never
parents: 3738
diff changeset
9323 emit_cmpfp_fixup(_masm);
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9324 %}
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9325 ins_pipe(pipe_slow);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9326 %}
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9327
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9328 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9329 match(Set cr (CmpD src con));
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9330 ins_cost(100);
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9331 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %}
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9332 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9333 __ ucomisd($src$$XMMRegister, $constantaddress($con));
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9334 %}
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9335 ins_pipe(pipe_slow);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9336 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9337
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9338 // Compare into -1,0,1
a61af66fc99e Initial load
duke
parents:
diff changeset
9339 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9340 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9341 match(Set dst (CmpF3 src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
9342 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9343
a61af66fc99e Initial load
duke
parents:
diff changeset
9344 ins_cost(275);
a61af66fc99e Initial load
duke
parents:
diff changeset
9345 format %{ "ucomiss $src1, $src2\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9346 "movl $dst, #-1\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9347 "jp,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9348 "jb,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9349 "setne $dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9350 "movzbl $dst, $dst\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
9351 "done:" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9352 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9353 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9354 emit_cmpfp3(_masm, $dst$$Register);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9355 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9356 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
9357 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9358
a61af66fc99e Initial load
duke
parents:
diff changeset
9359 // Compare into -1,0,1
a61af66fc99e Initial load
duke
parents:
diff changeset
9360 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9361 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9362 match(Set dst (CmpF3 src1 (LoadF src2)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9363 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9364
a61af66fc99e Initial load
duke
parents:
diff changeset
9365 ins_cost(275);
a61af66fc99e Initial load
duke
parents:
diff changeset
9366 format %{ "ucomiss $src1, $src2\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9367 "movl $dst, #-1\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9368 "jp,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9369 "jb,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9370 "setne $dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9371 "movzbl $dst, $dst\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
9372 "done:" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9373 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9374 __ ucomiss($src1$$XMMRegister, $src2$$Address);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9375 emit_cmpfp3(_masm, $dst$$Register);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9376 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9377 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
9378 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9379
a61af66fc99e Initial load
duke
parents:
diff changeset
9380 // Compare into -1,0,1
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9381 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9382 match(Set dst (CmpF3 src con));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9383 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9384
a61af66fc99e Initial load
duke
parents:
diff changeset
9385 ins_cost(275);
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9386 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9387 "movl $dst, #-1\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9388 "jp,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9389 "jb,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9390 "setne $dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9391 "movzbl $dst, $dst\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
9392 "done:" %}
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9393 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9394 __ ucomiss($src$$XMMRegister, $constantaddress($con));
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9395 emit_cmpfp3(_masm, $dst$$Register);
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9396 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9397 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
9398 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9399
a61af66fc99e Initial load
duke
parents:
diff changeset
9400 // Compare into -1,0,1
a61af66fc99e Initial load
duke
parents:
diff changeset
9401 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9402 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9403 match(Set dst (CmpD3 src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
9404 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9405
a61af66fc99e Initial load
duke
parents:
diff changeset
9406 ins_cost(275);
a61af66fc99e Initial load
duke
parents:
diff changeset
9407 format %{ "ucomisd $src1, $src2\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9408 "movl $dst, #-1\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9409 "jp,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9410 "jb,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9411 "setne $dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9412 "movzbl $dst, $dst\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
9413 "done:" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9414 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9415 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9416 emit_cmpfp3(_masm, $dst$$Register);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9417 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9418 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
9419 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9420
a61af66fc99e Initial load
duke
parents:
diff changeset
9421 // Compare into -1,0,1
a61af66fc99e Initial load
duke
parents:
diff changeset
9422 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9423 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9424 match(Set dst (CmpD3 src1 (LoadD src2)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9425 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9426
a61af66fc99e Initial load
duke
parents:
diff changeset
9427 ins_cost(275);
a61af66fc99e Initial load
duke
parents:
diff changeset
9428 format %{ "ucomisd $src1, $src2\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9429 "movl $dst, #-1\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9430 "jp,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9431 "jb,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9432 "setne $dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9433 "movzbl $dst, $dst\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
9434 "done:" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9435 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9436 __ ucomisd($src1$$XMMRegister, $src2$$Address);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9437 emit_cmpfp3(_masm, $dst$$Register);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9438 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9439 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
9440 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9441
a61af66fc99e Initial load
duke
parents:
diff changeset
9442 // Compare into -1,0,1
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9443 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9444 match(Set dst (CmpD3 src con));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9445 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9446
a61af66fc99e Initial load
duke
parents:
diff changeset
9447 ins_cost(275);
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9448 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9449 "movl $dst, #-1\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9450 "jp,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9451 "jb,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9452 "setne $dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9453 "movzbl $dst, $dst\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
9454 "done:" %}
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9455 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9456 __ ucomisd($src$$XMMRegister, $constantaddress($con));
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9457 emit_cmpfp3(_masm, $dst$$Register);
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9458 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9459 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
9460 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9461
a61af66fc99e Initial load
duke
parents:
diff changeset
9462 // -----------Trig and Trancendental Instructions------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
9463 instruct cosD_reg(regD dst) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9464 match(Set dst (CosD dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9465
a61af66fc99e Initial load
duke
parents:
diff changeset
9466 format %{ "dcos $dst\n\t" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9467 opcode(0xD9, 0xFF);
a61af66fc99e Initial load
duke
parents:
diff changeset
9468 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
a61af66fc99e Initial load
duke
parents:
diff changeset
9469 ins_pipe( pipe_slow );
a61af66fc99e Initial load
duke
parents:
diff changeset
9470 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9471
a61af66fc99e Initial load
duke
parents:
diff changeset
9472 instruct sinD_reg(regD dst) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9473 match(Set dst (SinD dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9474
a61af66fc99e Initial load
duke
parents:
diff changeset
9475 format %{ "dsin $dst\n\t" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9476 opcode(0xD9, 0xFE);
a61af66fc99e Initial load
duke
parents:
diff changeset
9477 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
a61af66fc99e Initial load
duke
parents:
diff changeset
9478 ins_pipe( pipe_slow );
a61af66fc99e Initial load
duke
parents:
diff changeset
9479 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9480
a61af66fc99e Initial load
duke
parents:
diff changeset
9481 instruct tanD_reg(regD dst) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9482 match(Set dst (TanD dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9483
a61af66fc99e Initial load
duke
parents:
diff changeset
9484 format %{ "dtan $dst\n\t" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9485 ins_encode( Push_SrcXD(dst),
a61af66fc99e Initial load
duke
parents:
diff changeset
9486 Opcode(0xD9), Opcode(0xF2), //fptan
a61af66fc99e Initial load
duke
parents:
diff changeset
9487 Opcode(0xDD), Opcode(0xD8), //fstp st
a61af66fc99e Initial load
duke
parents:
diff changeset
9488 Push_ResultXD(dst) );
a61af66fc99e Initial load
duke
parents:
diff changeset
9489 ins_pipe( pipe_slow );
a61af66fc99e Initial load
duke
parents:
diff changeset
9490 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9491
a61af66fc99e Initial load
duke
parents:
diff changeset
9492 instruct log10D_reg(regD dst) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9493 // The source and result Double operands in XMM registers
a61af66fc99e Initial load
duke
parents:
diff changeset
9494 match(Set dst (Log10D dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9495 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
a61af66fc99e Initial load
duke
parents:
diff changeset
9496 // fyl2x ; compute log_10(2) * log_2(x)
a61af66fc99e Initial load
duke
parents:
diff changeset
9497 format %{ "fldlg2\t\t\t#Log10\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9498 "fyl2x\t\t\t# Q=Log10*Log_2(x)\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9499 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9500 ins_encode(Opcode(0xD9), Opcode(0xEC), // fldlg2
a61af66fc99e Initial load
duke
parents:
diff changeset
9501 Push_SrcXD(dst),
a61af66fc99e Initial load
duke
parents:
diff changeset
9502 Opcode(0xD9), Opcode(0xF1), // fyl2x
a61af66fc99e Initial load
duke
parents:
diff changeset
9503 Push_ResultXD(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9504
a61af66fc99e Initial load
duke
parents:
diff changeset
9505 ins_pipe( pipe_slow );
a61af66fc99e Initial load
duke
parents:
diff changeset
9506 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9507
a61af66fc99e Initial load
duke
parents:
diff changeset
9508 instruct logD_reg(regD dst) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9509 // The source and result Double operands in XMM registers
a61af66fc99e Initial load
duke
parents:
diff changeset
9510 match(Set dst (LogD dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9511 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
a61af66fc99e Initial load
duke
parents:
diff changeset
9512 // fyl2x ; compute log_e(2) * log_2(x)
a61af66fc99e Initial load
duke
parents:
diff changeset
9513 format %{ "fldln2\t\t\t#Log_e\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9514 "fyl2x\t\t\t# Q=Log_e*Log_2(x)\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9515 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9516 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
a61af66fc99e Initial load
duke
parents:
diff changeset
9517 Push_SrcXD(dst),
a61af66fc99e Initial load
duke
parents:
diff changeset
9518 Opcode(0xD9), Opcode(0xF1), // fyl2x
a61af66fc99e Initial load
duke
parents:
diff changeset
9519 Push_ResultXD(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9520 ins_pipe( pipe_slow );
a61af66fc99e Initial load
duke
parents:
diff changeset
9521 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9522
6084
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9523 instruct powD_reg(regD dst, regD src0, regD src1, rax_RegI rax, rdx_RegI rdx, rcx_RegI rcx, rFlagsReg cr) %{
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9524 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9525 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9526 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %}
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9527 ins_encode %{
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9528 __ subptr(rsp, 8);
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9529 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9530 __ fld_d(Address(rsp, 0));
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9531 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9532 __ fld_d(Address(rsp, 0));
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9533 __ fast_pow();
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9534 __ fstp_d(Address(rsp, 0));
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9535 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9536 __ addptr(rsp, 8);
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9537 %}
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9538 ins_pipe( pipe_slow );
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9539 %}
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9540
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9541 instruct expD_reg(regD dst, regD src, rax_RegI rax, rdx_RegI rdx, rcx_RegI rcx, rFlagsReg cr) %{
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9542 match(Set dst (ExpD src));
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9543 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9544 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %}
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9545 ins_encode %{
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9546 __ subptr(rsp, 8);
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9547 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9548 __ fld_d(Address(rsp, 0));
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9549 __ fast_exp();
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9550 __ fstp_d(Address(rsp, 0));
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9551 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9552 __ addptr(rsp, 8);
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9553 %}
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9554 ins_pipe( pipe_slow );
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9555 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9556
a61af66fc99e Initial load
duke
parents:
diff changeset
9557 //----------Arithmetic Conversion Instructions---------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
9558
a61af66fc99e Initial load
duke
parents:
diff changeset
9559 instruct roundFloat_nop(regF dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
9560 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9561 match(Set dst (RoundFloat dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9562
a61af66fc99e Initial load
duke
parents:
diff changeset
9563 ins_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
9564 ins_encode();
a61af66fc99e Initial load
duke
parents:
diff changeset
9565 ins_pipe(empty);
a61af66fc99e Initial load
duke
parents:
diff changeset
9566 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9567
a61af66fc99e Initial load
duke
parents:
diff changeset
9568 instruct roundDouble_nop(regD dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
9569 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9570 match(Set dst (RoundDouble dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9571
a61af66fc99e Initial load
duke
parents:
diff changeset
9572 ins_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
9573 ins_encode();
a61af66fc99e Initial load
duke
parents:
diff changeset
9574 ins_pipe(empty);
a61af66fc99e Initial load
duke
parents:
diff changeset
9575 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9576
a61af66fc99e Initial load
duke
parents:
diff changeset
9577 instruct convF2D_reg_reg(regD dst, regF src)
a61af66fc99e Initial load
duke
parents:
diff changeset
9578 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9579 match(Set dst (ConvF2D src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9580
a61af66fc99e Initial load
duke
parents:
diff changeset
9581 format %{ "cvtss2sd $dst, $src" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9582 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9583 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9584 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9585 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
9586 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9587
a61af66fc99e Initial load
duke
parents:
diff changeset
9588 instruct convF2D_reg_mem(regD dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
9589 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9590 match(Set dst (ConvF2D (LoadF src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9591
a61af66fc99e Initial load
duke
parents:
diff changeset
9592 format %{ "cvtss2sd $dst, $src" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9593 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9594 __ cvtss2sd ($dst$$XMMRegister, $src$$Address);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9595 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9596 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
9597 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9598
a61af66fc99e Initial load
duke
parents:
diff changeset
9599 instruct convD2F_reg_reg(regF dst, regD src)
a61af66fc99e Initial load
duke
parents:
diff changeset
9600 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9601 match(Set dst (ConvD2F src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9602
a61af66fc99e Initial load
duke
parents:
diff changeset
9603 format %{ "cvtsd2ss $dst, $src" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9604 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9605 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9606 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9607 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
9608 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9609
a61af66fc99e Initial load
duke
parents:
diff changeset
9610 instruct convD2F_reg_mem(regF dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
9611 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9612 match(Set dst (ConvD2F (LoadD src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9613
a61af66fc99e Initial load
duke
parents:
diff changeset
9614 format %{ "cvtsd2ss $dst, $src" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9615 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9616 __ cvtsd2ss ($dst$$XMMRegister, $src$$Address);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9617 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9618 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
9619 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9620
a61af66fc99e Initial load
duke
parents:
diff changeset
9621 // XXX do mem variants
a61af66fc99e Initial load
duke
parents:
diff changeset
9622 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9623 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9624 match(Set dst (ConvF2I src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9625 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9626
a61af66fc99e Initial load
duke
parents:
diff changeset
9627 format %{ "cvttss2sil $dst, $src\t# f2i\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9628 "cmpl $dst, #0x80000000\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9629 "jne,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9630 "subq rsp, #8\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9631 "movss [rsp], $src\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9632 "call f2i_fixup\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9633 "popq $dst\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
9634 "done: "%}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9635 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9636 Label done;
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9637 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9638 __ cmpl($dst$$Register, 0x80000000);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9639 __ jccb(Assembler::notEqual, done);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9640 __ subptr(rsp, 8);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9641 __ movflt(Address(rsp, 0), $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9642 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9643 __ pop($dst$$Register);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9644 __ bind(done);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9645 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9646 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
9647 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9648
a61af66fc99e Initial load
duke
parents:
diff changeset
9649 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9650 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9651 match(Set dst (ConvF2L src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9652 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9653
a61af66fc99e Initial load
duke
parents:
diff changeset
9654 format %{ "cvttss2siq $dst, $src\t# f2l\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9655 "cmpq $dst, [0x8000000000000000]\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9656 "jne,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9657 "subq rsp, #8\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9658 "movss [rsp], $src\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9659 "call f2l_fixup\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9660 "popq $dst\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
9661 "done: "%}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9662 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9663 Label done;
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9664 __ cvttss2siq($dst$$Register, $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9665 __ cmp64($dst$$Register,
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9666 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9667 __ jccb(Assembler::notEqual, done);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9668 __ subptr(rsp, 8);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9669 __ movflt(Address(rsp, 0), $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9670 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9671 __ pop($dst$$Register);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9672 __ bind(done);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9673 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9674 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
9675 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9676
a61af66fc99e Initial load
duke
parents:
diff changeset
9677 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9678 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9679 match(Set dst (ConvD2I src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9680 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9681
a61af66fc99e Initial load
duke
parents:
diff changeset
9682 format %{ "cvttsd2sil $dst, $src\t# d2i\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9683 "cmpl $dst, #0x80000000\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9684 "jne,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9685 "subq rsp, #8\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9686 "movsd [rsp], $src\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9687 "call d2i_fixup\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9688 "popq $dst\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
9689 "done: "%}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9690 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9691 Label done;
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9692 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9693 __ cmpl($dst$$Register, 0x80000000);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9694 __ jccb(Assembler::notEqual, done);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9695 __ subptr(rsp, 8);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9696 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9697 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9698 __ pop($dst$$Register);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9699 __ bind(done);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9700 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9701 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
9702 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9703
a61af66fc99e Initial load
duke
parents:
diff changeset
9704 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9705 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9706 match(Set dst (ConvD2L src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9707 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9708
a61af66fc99e Initial load
duke
parents:
diff changeset
9709 format %{ "cvttsd2siq $dst, $src\t# d2l\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9710 "cmpq $dst, [0x8000000000000000]\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9711 "jne,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9712 "subq rsp, #8\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9713 "movsd [rsp], $src\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9714 "call d2l_fixup\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9715 "popq $dst\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
9716 "done: "%}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9717 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9718 Label done;
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9719 __ cvttsd2siq($dst$$Register, $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9720 __ cmp64($dst$$Register,
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9721 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9722 __ jccb(Assembler::notEqual, done);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9723 __ subptr(rsp, 8);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9724 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9725 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9726 __ pop($dst$$Register);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9727 __ bind(done);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9728 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9729 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
9730 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9731
a61af66fc99e Initial load
duke
parents:
diff changeset
9732 instruct convI2F_reg_reg(regF dst, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
9733 %{
71
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
9734 predicate(!UseXmmI2F);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9735 match(Set dst (ConvI2F src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9736
a61af66fc99e Initial load
duke
parents:
diff changeset
9737 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9738 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9739 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9740 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9741 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
9742 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9743
a61af66fc99e Initial load
duke
parents:
diff changeset
9744 instruct convI2F_reg_mem(regF dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
9745 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9746 match(Set dst (ConvI2F (LoadI src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9747
a61af66fc99e Initial load
duke
parents:
diff changeset
9748 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9749 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9750 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9751 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9752 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
9753 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9754
a61af66fc99e Initial load
duke
parents:
diff changeset
9755 instruct convI2D_reg_reg(regD dst, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
9756 %{
71
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
9757 predicate(!UseXmmI2D);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9758 match(Set dst (ConvI2D src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9759
a61af66fc99e Initial load
duke
parents:
diff changeset
9760 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9761 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9762 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9763 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9764 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
9765 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9766
a61af66fc99e Initial load
duke
parents:
diff changeset
9767 instruct convI2D_reg_mem(regD dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
9768 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9769 match(Set dst (ConvI2D (LoadI src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9770
a61af66fc99e Initial load
duke
parents:
diff changeset
9771 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9772 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9773 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9774 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9775 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
9776 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9777
71
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
9778 instruct convXI2F_reg(regF dst, rRegI src)
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
9779 %{
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
9780 predicate(UseXmmI2F);
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
9781 match(Set dst (ConvI2F src));
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
9782
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
9783 format %{ "movdl $dst, $src\n\t"
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
9784 "cvtdq2psl $dst, $dst\t# i2f" %}
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
9785 ins_encode %{
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
9786 __ movdl($dst$$XMMRegister, $src$$Register);
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
9787 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
9788 %}
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
9789 ins_pipe(pipe_slow); // XXX
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
9790 %}
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
9791
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
9792 instruct convXI2D_reg(regD dst, rRegI src)
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
9793 %{
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
9794 predicate(UseXmmI2D);
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
9795 match(Set dst (ConvI2D src));
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
9796
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
9797 format %{ "movdl $dst, $src\n\t"
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
9798 "cvtdq2pdl $dst, $dst\t# i2d" %}
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
9799 ins_encode %{
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
9800 __ movdl($dst$$XMMRegister, $src$$Register);
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
9801 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
9802 %}
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
9803 ins_pipe(pipe_slow); // XXX
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
9804 %}
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
9805
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9806 instruct convL2F_reg_reg(regF dst, rRegL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
9807 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9808 match(Set dst (ConvL2F src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9809
a61af66fc99e Initial load
duke
parents:
diff changeset
9810 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9811 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9812 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9813 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9814 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
9815 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9816
a61af66fc99e Initial load
duke
parents:
diff changeset
9817 instruct convL2F_reg_mem(regF dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
9818 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9819 match(Set dst (ConvL2F (LoadL src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9820
a61af66fc99e Initial load
duke
parents:
diff changeset
9821 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9822 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9823 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9824 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9825 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
9826 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9827
a61af66fc99e Initial load
duke
parents:
diff changeset
9828 instruct convL2D_reg_reg(regD dst, rRegL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
9829 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9830 match(Set dst (ConvL2D src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9831
a61af66fc99e Initial load
duke
parents:
diff changeset
9832 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9833 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9834 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9835 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9836 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
9837 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9838
a61af66fc99e Initial load
duke
parents:
diff changeset
9839 instruct convL2D_reg_mem(regD dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
9840 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9841 match(Set dst (ConvL2D (LoadL src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9842
a61af66fc99e Initial load
duke
parents:
diff changeset
9843 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9844 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9845 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9846 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9847 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
9848 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9849
a61af66fc99e Initial load
duke
parents:
diff changeset
9850 instruct convI2L_reg_reg(rRegL dst, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
9851 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9852 match(Set dst (ConvI2L src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9853
a61af66fc99e Initial load
duke
parents:
diff changeset
9854 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
9855 format %{ "movslq $dst, $src\t# i2l" %}
824
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
9856 ins_encode %{
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
9857 __ movslq($dst$$Register, $src$$Register);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
9858 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9859 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9860 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9861
a61af66fc99e Initial load
duke
parents:
diff changeset
9862 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
9863 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9864 // match(Set dst (ConvI2L src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9865 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 &&
a61af66fc99e Initial load
duke
parents:
diff changeset
9866 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0);
a61af66fc99e Initial load
duke
parents:
diff changeset
9867 // predicate(((const TypeNode*) n)->type()->is_long()->_hi ==
a61af66fc99e Initial load
duke
parents:
diff changeset
9868 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi &&
a61af66fc99e Initial load
duke
parents:
diff changeset
9869 // ((const TypeNode*) n)->type()->is_long()->_lo ==
a61af66fc99e Initial load
duke
parents:
diff changeset
9870 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo);
a61af66fc99e Initial load
duke
parents:
diff changeset
9871
a61af66fc99e Initial load
duke
parents:
diff changeset
9872 // format %{ "movl $dst, $src\t# unsigned i2l" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9873 // ins_encode(enc_copy(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9874 // // opcode(0x63); // needs REX.W
a61af66fc99e Initial load
duke
parents:
diff changeset
9875 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9876 // ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9877 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9878
a61af66fc99e Initial load
duke
parents:
diff changeset
9879 // Zero-extend convert int to long
a61af66fc99e Initial load
duke
parents:
diff changeset
9880 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
a61af66fc99e Initial load
duke
parents:
diff changeset
9881 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9882 match(Set dst (AndL (ConvI2L src) mask));
a61af66fc99e Initial load
duke
parents:
diff changeset
9883
a61af66fc99e Initial load
duke
parents:
diff changeset
9884 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9885 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9886 if ($dst$$reg != $src$$reg) {
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9887 __ movl($dst$$Register, $src$$Register);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9888 }
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9889 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9890 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9891 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9892
a61af66fc99e Initial load
duke
parents:
diff changeset
9893 // Zero-extend convert int to long
a61af66fc99e Initial load
duke
parents:
diff changeset
9894 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
a61af66fc99e Initial load
duke
parents:
diff changeset
9895 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9896 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
a61af66fc99e Initial load
duke
parents:
diff changeset
9897
a61af66fc99e Initial load
duke
parents:
diff changeset
9898 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9899 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9900 __ movl($dst$$Register, $src$$Address);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9901 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9902 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
9903 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9904
a61af66fc99e Initial load
duke
parents:
diff changeset
9905 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
a61af66fc99e Initial load
duke
parents:
diff changeset
9906 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9907 match(Set dst (AndL src mask));
a61af66fc99e Initial load
duke
parents:
diff changeset
9908
a61af66fc99e Initial load
duke
parents:
diff changeset
9909 format %{ "movl $dst, $src\t# zero-extend long" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9910 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9911 __ movl($dst$$Register, $src$$Register);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9912 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9913 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9914 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9915
a61af66fc99e Initial load
duke
parents:
diff changeset
9916 instruct convL2I_reg_reg(rRegI dst, rRegL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
9917 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9918 match(Set dst (ConvL2I src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9919
a61af66fc99e Initial load
duke
parents:
diff changeset
9920 format %{ "movl $dst, $src\t# l2i" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9921 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9922 __ movl($dst$$Register, $src$$Register);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9923 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9924 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9925 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9926
a61af66fc99e Initial load
duke
parents:
diff changeset
9927
a61af66fc99e Initial load
duke
parents:
diff changeset
9928 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9929 match(Set dst (MoveF2I src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9930 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
9931
a61af66fc99e Initial load
duke
parents:
diff changeset
9932 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
9933 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9934 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9935 __ movl($dst$$Register, Address(rsp, $src$$disp));
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9936 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9937 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
9938 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9939
a61af66fc99e Initial load
duke
parents:
diff changeset
9940 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9941 match(Set dst (MoveI2F src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9942 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
9943
a61af66fc99e Initial load
duke
parents:
diff changeset
9944 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
9945 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9946 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9947 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9948 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9949 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
9950 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9951
a61af66fc99e Initial load
duke
parents:
diff changeset
9952 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9953 match(Set dst (MoveD2L src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9954 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
9955
a61af66fc99e Initial load
duke
parents:
diff changeset
9956 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
9957 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9958 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9959 __ movq($dst$$Register, Address(rsp, $src$$disp));
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9960 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9961 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
9962 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9963
a61af66fc99e Initial load
duke
parents:
diff changeset
9964 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9965 predicate(!UseXmmLoadAndClearUpper);
a61af66fc99e Initial load
duke
parents:
diff changeset
9966 match(Set dst (MoveL2D src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9967 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
9968
a61af66fc99e Initial load
duke
parents:
diff changeset
9969 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
9970 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9971 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9972 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9973 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9974 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
9975 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9976
a61af66fc99e Initial load
duke
parents:
diff changeset
9977 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9978 predicate(UseXmmLoadAndClearUpper);
a61af66fc99e Initial load
duke
parents:
diff changeset
9979 match(Set dst (MoveL2D src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9980 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
9981
a61af66fc99e Initial load
duke
parents:
diff changeset
9982 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
9983 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9984 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9985 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9986 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9987 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
9988 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9989
a61af66fc99e Initial load
duke
parents:
diff changeset
9990
a61af66fc99e Initial load
duke
parents:
diff changeset
9991 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9992 match(Set dst (MoveF2I src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9993 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
9994
a61af66fc99e Initial load
duke
parents:
diff changeset
9995 ins_cost(95); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
9996 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9997 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9998 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9999 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10000 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10001 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10002
a61af66fc99e Initial load
duke
parents:
diff changeset
10003 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10004 match(Set dst (MoveI2F src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10005 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
10006
a61af66fc99e Initial load
duke
parents:
diff changeset
10007 ins_cost(100);
a61af66fc99e Initial load
duke
parents:
diff changeset
10008 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10009 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10010 __ movl(Address(rsp, $dst$$disp), $src$$Register);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10011 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10012 ins_pipe( ialu_mem_reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
10013 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10014
a61af66fc99e Initial load
duke
parents:
diff changeset
10015 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10016 match(Set dst (MoveD2L src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10017 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
10018
a61af66fc99e Initial load
duke
parents:
diff changeset
10019 ins_cost(95); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
10020 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10021 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10022 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10023 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10024 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10025 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10026
a61af66fc99e Initial load
duke
parents:
diff changeset
10027 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10028 match(Set dst (MoveL2D src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10029 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
10030
a61af66fc99e Initial load
duke
parents:
diff changeset
10031 ins_cost(100);
a61af66fc99e Initial load
duke
parents:
diff changeset
10032 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10033 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10034 __ movq(Address(rsp, $dst$$disp), $src$$Register);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10035 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10036 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
10037 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10038
a61af66fc99e Initial load
duke
parents:
diff changeset
10039 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10040 match(Set dst (MoveF2I src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10041 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
10042 ins_cost(85);
a61af66fc99e Initial load
duke
parents:
diff changeset
10043 format %{ "movd $dst,$src\t# MoveF2I" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10044 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10045 __ movdl($dst$$Register, $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10046 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10047 ins_pipe( pipe_slow );
a61af66fc99e Initial load
duke
parents:
diff changeset
10048 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10049
a61af66fc99e Initial load
duke
parents:
diff changeset
10050 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10051 match(Set dst (MoveD2L src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10052 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
10053 ins_cost(85);
a61af66fc99e Initial load
duke
parents:
diff changeset
10054 format %{ "movd $dst,$src\t# MoveD2L" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10055 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10056 __ movdq($dst$$Register, $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10057 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10058 ins_pipe( pipe_slow );
a61af66fc99e Initial load
duke
parents:
diff changeset
10059 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10060
a61af66fc99e Initial load
duke
parents:
diff changeset
10061 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10062 match(Set dst (MoveI2F src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10063 effect(DEF dst, USE src);
6614
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
10064 ins_cost(100);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10065 format %{ "movd $dst,$src\t# MoveI2F" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10066 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10067 __ movdl($dst$$XMMRegister, $src$$Register);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10068 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10069 ins_pipe( pipe_slow );
a61af66fc99e Initial load
duke
parents:
diff changeset
10070 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10071
a61af66fc99e Initial load
duke
parents:
diff changeset
10072 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10073 match(Set dst (MoveL2D src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10074 effect(DEF dst, USE src);
6614
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
10075 ins_cost(100);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10076 format %{ "movd $dst,$src\t# MoveL2D" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10077 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10078 __ movdq($dst$$XMMRegister, $src$$Register);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10079 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10080 ins_pipe( pipe_slow );
a61af66fc99e Initial load
duke
parents:
diff changeset
10081 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10082
a61af66fc99e Initial load
duke
parents:
diff changeset
10083
a61af66fc99e Initial load
duke
parents:
diff changeset
10084 // =======================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
10085 // fast clearing of an array
a61af66fc99e Initial load
duke
parents:
diff changeset
10086 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy,
a61af66fc99e Initial load
duke
parents:
diff changeset
10087 rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
10088 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10089 match(Set dummy (ClearArray cnt base));
a61af66fc99e Initial load
duke
parents:
diff changeset
10090 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
10091
a61af66fc99e Initial load
duke
parents:
diff changeset
10092 format %{ "xorl rax, rax\t# ClearArray:\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10093 "rep stosq\t# Store rax to *rdi++ while rcx--" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10094 ins_encode(opc_reg_reg(0x33, RAX, RAX), // xorl %eax, %eax
a61af66fc99e Initial load
duke
parents:
diff changeset
10095 Opcode(0xF3), Opcode(0x48), Opcode(0xAB)); // rep REX_W stos
a61af66fc99e Initial load
duke
parents:
diff changeset
10096 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10097 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10098
2262
6bbaedb03534 7016474: string compare intrinsic improvements
never
parents: 2008
diff changeset
10099 instruct string_compare(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
6bbaedb03534 7016474: string compare intrinsic improvements
never
parents: 2008
diff changeset
10100 rax_RegI result, regD tmp1, rFlagsReg cr)
986
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10101 %{
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10102 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
2262
6bbaedb03534 7016474: string compare intrinsic improvements
never
parents: 2008
diff changeset
10103 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
6bbaedb03534 7016474: string compare intrinsic improvements
never
parents: 2008
diff changeset
10104
6bbaedb03534 7016474: string compare intrinsic improvements
never
parents: 2008
diff changeset
10105 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
986
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10106 ins_encode %{
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10107 __ string_compare($str1$$Register, $str2$$Register,
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10108 $cnt1$$Register, $cnt2$$Register, $result$$Register,
2262
6bbaedb03534 7016474: string compare intrinsic improvements
never
parents: 2008
diff changeset
10109 $tmp1$$XMMRegister);
986
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10110 %}
681
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 671
diff changeset
10111 ins_pipe( pipe_slow );
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 671
diff changeset
10112 %}
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 671
diff changeset
10113
2320
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10114 // fast search of substring with known size.
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10115 instruct string_indexof_con(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10116 rbx_RegI result, regD vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10117 %{
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10118 predicate(UseSSE42Intrinsics);
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10119 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10120 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10121
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10122 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10123 ins_encode %{
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10124 int icnt2 = (int)$int_cnt2$$constant;
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10125 if (icnt2 >= 8) {
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10126 // IndexOf for constant substrings with size >= 8 elements
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10127 // which don't need to be loaded through stack.
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10128 __ string_indexofC8($str1$$Register, $str2$$Register,
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10129 $cnt1$$Register, $cnt2$$Register,
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10130 icnt2, $result$$Register,
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10131 $vec$$XMMRegister, $tmp$$Register);
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10132 } else {
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10133 // Small strings are loaded through stack if they cross page boundary.
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10134 __ string_indexof($str1$$Register, $str2$$Register,
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10135 $cnt1$$Register, $cnt2$$Register,
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10136 icnt2, $result$$Register,
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10137 $vec$$XMMRegister, $tmp$$Register);
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10138 }
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10139 %}
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10140 ins_pipe( pipe_slow );
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10141 %}
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10142
986
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10143 instruct string_indexof(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
2320
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10144 rbx_RegI result, regD vec, rcx_RegI tmp, rFlagsReg cr)
681
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 671
diff changeset
10145 %{
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 671
diff changeset
10146 predicate(UseSSE42Intrinsics);
986
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10147 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
2320
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10148 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10149
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10150 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
986
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10151 ins_encode %{
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10152 __ string_indexof($str1$$Register, $str2$$Register,
2320
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10153 $cnt1$$Register, $cnt2$$Register,
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10154 (-1), $result$$Register,
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10155 $vec$$XMMRegister, $tmp$$Register);
986
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10156 %}
681
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 671
diff changeset
10157 ins_pipe( pipe_slow );
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 671
diff changeset
10158 %}
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 671
diff changeset
10159
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 671
diff changeset
10160 // fast string equals
986
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10161 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10162 regD tmp1, regD tmp2, rbx_RegI tmp3, rFlagsReg cr)
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10163 %{
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10164 match(Set result (StrEquals (Binary str1 str2) cnt));
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10165 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10166
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10167 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10168 ins_encode %{
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10169 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10170 $cnt$$Register, $result$$Register, $tmp3$$Register,
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10171 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10172 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10173 ins_pipe( pipe_slow );
a61af66fc99e Initial load
duke
parents:
diff changeset
10174 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10175
169
9148c65abefc 6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents: 168
diff changeset
10176 // fast array equals
986
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10177 instruct array_equals(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10178 regD tmp1, regD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
681
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 671
diff changeset
10179 %{
169
9148c65abefc 6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents: 168
diff changeset
10180 match(Set result (AryEq ary1 ary2));
681
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 671
diff changeset
10181 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
169
9148c65abefc 6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents: 168
diff changeset
10182 //ins_cost(300);
9148c65abefc 6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents: 168
diff changeset
10183
986
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10184 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10185 ins_encode %{
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10186 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10187 $tmp3$$Register, $result$$Register, $tmp4$$Register,
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10188 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10189 %}
169
9148c65abefc 6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents: 168
diff changeset
10190 ins_pipe( pipe_slow );
9148c65abefc 6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents: 168
diff changeset
10191 %}
9148c65abefc 6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents: 168
diff changeset
10192
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10193 //----------Control Flow Instructions------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
10194 // Signed compare Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
10195
a61af66fc99e Initial load
duke
parents:
diff changeset
10196 // XXX more variants!!
a61af66fc99e Initial load
duke
parents:
diff changeset
10197 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
a61af66fc99e Initial load
duke
parents:
diff changeset
10198 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10199 match(Set cr (CmpI op1 op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10200 effect(DEF cr, USE op1, USE op2);
a61af66fc99e Initial load
duke
parents:
diff changeset
10201
a61af66fc99e Initial load
duke
parents:
diff changeset
10202 format %{ "cmpl $op1, $op2" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10203 opcode(0x3B); /* Opcode 3B /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
10204 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10205 ins_pipe(ialu_cr_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
10206 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10207
a61af66fc99e Initial load
duke
parents:
diff changeset
10208 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
a61af66fc99e Initial load
duke
parents:
diff changeset
10209 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10210 match(Set cr (CmpI op1 op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10211
a61af66fc99e Initial load
duke
parents:
diff changeset
10212 format %{ "cmpl $op1, $op2" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10213 opcode(0x81, 0x07); /* Opcode 81 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
10214 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10215 ins_pipe(ialu_cr_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
10216 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10217
a61af66fc99e Initial load
duke
parents:
diff changeset
10218 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
a61af66fc99e Initial load
duke
parents:
diff changeset
10219 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10220 match(Set cr (CmpI op1 (LoadI op2)));
a61af66fc99e Initial load
duke
parents:
diff changeset
10221
a61af66fc99e Initial load
duke
parents:
diff changeset
10222 ins_cost(500); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
10223 format %{ "cmpl $op1, $op2" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10224 opcode(0x3B); /* Opcode 3B /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
10225 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10226 ins_pipe(ialu_cr_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
10227 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10228
a61af66fc99e Initial load
duke
parents:
diff changeset
10229 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero)
a61af66fc99e Initial load
duke
parents:
diff changeset
10230 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10231 match(Set cr (CmpI src zero));
a61af66fc99e Initial load
duke
parents:
diff changeset
10232
a61af66fc99e Initial load
duke
parents:
diff changeset
10233 format %{ "testl $src, $src" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10234 opcode(0x85);
a61af66fc99e Initial load
duke
parents:
diff changeset
10235 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10236 ins_pipe(ialu_cr_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
10237 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10238
a61af66fc99e Initial load
duke
parents:
diff changeset
10239 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero)
a61af66fc99e Initial load
duke
parents:
diff changeset
10240 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10241 match(Set cr (CmpI (AndI src con) zero));
a61af66fc99e Initial load
duke
parents:
diff changeset
10242
a61af66fc99e Initial load
duke
parents:
diff changeset
10243 format %{ "testl $src, $con" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10244 opcode(0xF7, 0x00);
a61af66fc99e Initial load
duke
parents:
diff changeset
10245 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con));
a61af66fc99e Initial load
duke
parents:
diff changeset
10246 ins_pipe(ialu_cr_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
10247 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10248
a61af66fc99e Initial load
duke
parents:
diff changeset
10249 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero)
a61af66fc99e Initial load
duke
parents:
diff changeset
10250 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10251 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
a61af66fc99e Initial load
duke
parents:
diff changeset
10252
a61af66fc99e Initial load
duke
parents:
diff changeset
10253 format %{ "testl $src, $mem" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10254 opcode(0x85);
a61af66fc99e Initial load
duke
parents:
diff changeset
10255 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
10256 ins_pipe(ialu_cr_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
10257 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10258
a61af66fc99e Initial load
duke
parents:
diff changeset
10259 // Unsigned compare Instructions; really, same as signed except they
a61af66fc99e Initial load
duke
parents:
diff changeset
10260 // produce an rFlagsRegU instead of rFlagsReg.
a61af66fc99e Initial load
duke
parents:
diff changeset
10261 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
a61af66fc99e Initial load
duke
parents:
diff changeset
10262 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10263 match(Set cr (CmpU op1 op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10264
a61af66fc99e Initial load
duke
parents:
diff changeset
10265 format %{ "cmpl $op1, $op2\t# unsigned" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10266 opcode(0x3B); /* Opcode 3B /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
10267 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10268 ins_pipe(ialu_cr_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
10269 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10270
a61af66fc99e Initial load
duke
parents:
diff changeset
10271 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
a61af66fc99e Initial load
duke
parents:
diff changeset
10272 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10273 match(Set cr (CmpU op1 op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10274
a61af66fc99e Initial load
duke
parents:
diff changeset
10275 format %{ "cmpl $op1, $op2\t# unsigned" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10276 opcode(0x81,0x07); /* Opcode 81 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
10277 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10278 ins_pipe(ialu_cr_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
10279 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10280
a61af66fc99e Initial load
duke
parents:
diff changeset
10281 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
a61af66fc99e Initial load
duke
parents:
diff changeset
10282 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10283 match(Set cr (CmpU op1 (LoadI op2)));
a61af66fc99e Initial load
duke
parents:
diff changeset
10284
a61af66fc99e Initial load
duke
parents:
diff changeset
10285 ins_cost(500); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
10286 format %{ "cmpl $op1, $op2\t# unsigned" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10287 opcode(0x3B); /* Opcode 3B /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
10288 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10289 ins_pipe(ialu_cr_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
10290 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10291
a61af66fc99e Initial load
duke
parents:
diff changeset
10292 // // // Cisc-spilled version of cmpU_rReg
a61af66fc99e Initial load
duke
parents:
diff changeset
10293 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2)
a61af66fc99e Initial load
duke
parents:
diff changeset
10294 // //%{
a61af66fc99e Initial load
duke
parents:
diff changeset
10295 // // match(Set cr (CmpU (LoadI op1) op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10296 // //
a61af66fc99e Initial load
duke
parents:
diff changeset
10297 // // format %{ "CMPu $op1,$op2" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10298 // // ins_cost(500);
a61af66fc99e Initial load
duke
parents:
diff changeset
10299 // // opcode(0x39); /* Opcode 39 /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
10300 // // ins_encode( OpcP, reg_mem( op1, op2) );
a61af66fc99e Initial load
duke
parents:
diff changeset
10301 // //%}
a61af66fc99e Initial load
duke
parents:
diff changeset
10302
a61af66fc99e Initial load
duke
parents:
diff changeset
10303 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero)
a61af66fc99e Initial load
duke
parents:
diff changeset
10304 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10305 match(Set cr (CmpU src zero));
a61af66fc99e Initial load
duke
parents:
diff changeset
10306
a61af66fc99e Initial load
duke
parents:
diff changeset
10307 format %{ "testl $src, $src\t# unsigned" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10308 opcode(0x85);
a61af66fc99e Initial load
duke
parents:
diff changeset
10309 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10310 ins_pipe(ialu_cr_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
10311 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10312
a61af66fc99e Initial load
duke
parents:
diff changeset
10313 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
a61af66fc99e Initial load
duke
parents:
diff changeset
10314 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10315 match(Set cr (CmpP op1 op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10316
a61af66fc99e Initial load
duke
parents:
diff changeset
10317 format %{ "cmpq $op1, $op2\t# ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10318 opcode(0x3B); /* Opcode 3B /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
10319 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10320 ins_pipe(ialu_cr_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
10321 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10322
a61af66fc99e Initial load
duke
parents:
diff changeset
10323 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
a61af66fc99e Initial load
duke
parents:
diff changeset
10324 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10325 match(Set cr (CmpP op1 (LoadP op2)));
a61af66fc99e Initial load
duke
parents:
diff changeset
10326
a61af66fc99e Initial load
duke
parents:
diff changeset
10327 ins_cost(500); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
10328 format %{ "cmpq $op1, $op2\t# ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10329 opcode(0x3B); /* Opcode 3B /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
10330 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10331 ins_pipe(ialu_cr_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
10332 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10333
a61af66fc99e Initial load
duke
parents:
diff changeset
10334 // // // Cisc-spilled version of cmpP_rReg
a61af66fc99e Initial load
duke
parents:
diff changeset
10335 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2)
a61af66fc99e Initial load
duke
parents:
diff changeset
10336 // //%{
a61af66fc99e Initial load
duke
parents:
diff changeset
10337 // // match(Set cr (CmpP (LoadP op1) op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10338 // //
a61af66fc99e Initial load
duke
parents:
diff changeset
10339 // // format %{ "CMPu $op1,$op2" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10340 // // ins_cost(500);
a61af66fc99e Initial load
duke
parents:
diff changeset
10341 // // opcode(0x39); /* Opcode 39 /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
10342 // // ins_encode( OpcP, reg_mem( op1, op2) );
a61af66fc99e Initial load
duke
parents:
diff changeset
10343 // //%}
a61af66fc99e Initial load
duke
parents:
diff changeset
10344
a61af66fc99e Initial load
duke
parents:
diff changeset
10345 // XXX this is generalized by compP_rReg_mem???
a61af66fc99e Initial load
duke
parents:
diff changeset
10346 // Compare raw pointer (used in out-of-heap check).
a61af66fc99e Initial load
duke
parents:
diff changeset
10347 // Only works because non-oop pointers must be raw pointers
a61af66fc99e Initial load
duke
parents:
diff changeset
10348 // and raw pointers have no anti-dependencies.
a61af66fc99e Initial load
duke
parents:
diff changeset
10349 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
a61af66fc99e Initial load
duke
parents:
diff changeset
10350 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10351 predicate(!n->in(2)->in(2)->bottom_type()->isa_oop_ptr());
a61af66fc99e Initial load
duke
parents:
diff changeset
10352 match(Set cr (CmpP op1 (LoadP op2)));
a61af66fc99e Initial load
duke
parents:
diff changeset
10353
a61af66fc99e Initial load
duke
parents:
diff changeset
10354 format %{ "cmpq $op1, $op2\t# raw ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10355 opcode(0x3B); /* Opcode 3B /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
10356 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10357 ins_pipe(ialu_cr_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
10358 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10359
a61af66fc99e Initial load
duke
parents:
diff changeset
10360 // This will generate a signed flags result. This should be OK since
a61af66fc99e Initial load
duke
parents:
diff changeset
10361 // any compare to a zero should be eq/neq.
a61af66fc99e Initial load
duke
parents:
diff changeset
10362 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
a61af66fc99e Initial load
duke
parents:
diff changeset
10363 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10364 match(Set cr (CmpP src zero));
a61af66fc99e Initial load
duke
parents:
diff changeset
10365
a61af66fc99e Initial load
duke
parents:
diff changeset
10366 format %{ "testq $src, $src\t# ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10367 opcode(0x85);
a61af66fc99e Initial load
duke
parents:
diff changeset
10368 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10369 ins_pipe(ialu_cr_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
10370 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10371
a61af66fc99e Initial load
duke
parents:
diff changeset
10372 // This will generate a signed flags result. This should be OK since
a61af66fc99e Initial load
duke
parents:
diff changeset
10373 // any compare to a zero should be eq/neq.
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10374 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10375 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10376 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10377 match(Set cr (CmpP (LoadP op) zero));
a61af66fc99e Initial load
duke
parents:
diff changeset
10378
a61af66fc99e Initial load
duke
parents:
diff changeset
10379 ins_cost(500); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
10380 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10381 opcode(0xF7); /* Opcode F7 /0 */
a61af66fc99e Initial load
duke
parents:
diff changeset
10382 ins_encode(REX_mem_wide(op),
a61af66fc99e Initial load
duke
parents:
diff changeset
10383 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF));
a61af66fc99e Initial load
duke
parents:
diff changeset
10384 ins_pipe(ialu_cr_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
10385 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10386
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10387 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10388 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10389 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10390 match(Set cr (CmpP (LoadP mem) zero));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10391
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10392 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10393 ins_encode %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10394 __ cmpq(r12, $mem$$Address);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10395 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10396 ins_pipe(ialu_cr_reg_mem);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10397 %}
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10398
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10399 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10400 %{
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10401 match(Set cr (CmpN op1 op2));
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10402
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10403 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10404 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %}
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10405 ins_pipe(ialu_cr_reg_reg);
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10406 %}
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10407
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10408 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10409 %{
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10410 match(Set cr (CmpN src (LoadN mem)));
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10411
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10412 format %{ "cmpl $src, $mem\t# compressed ptr" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10413 ins_encode %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10414 __ cmpl($src$$Register, $mem$$Address);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10415 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10416 ins_pipe(ialu_cr_reg_mem);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10417 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10418
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10419 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10420 match(Set cr (CmpN op1 op2));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10421
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10422 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10423 ins_encode %{
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10424 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10425 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10426 ins_pipe(ialu_cr_reg_imm);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10427 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10428
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10429 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10430 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10431 match(Set cr (CmpN src (LoadN mem)));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10432
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10433 format %{ "cmpl $mem, $src\t# compressed ptr" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10434 ins_encode %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10435 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant);
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10436 %}
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10437 ins_pipe(ialu_cr_reg_mem);
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10438 %}
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10439
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
10440 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
10441 match(Set cr (CmpN src zero));
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
10442
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10443 format %{ "testl $src, $src\t# compressed ptr" %}
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
10444 ins_encode %{ __ testl($src$$Register, $src$$Register); %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
10445 ins_pipe(ialu_cr_reg_imm);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
10446 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
10447
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10448 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10449 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10450 predicate(Universe::narrow_oop_base() != NULL);
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10451 match(Set cr (CmpN (LoadN mem) zero));
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10452
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10453 ins_cost(500); // XXX
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10454 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %}
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10455 ins_encode %{
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10456 __ cmpl($mem$$Address, (int)0xFFFFFFFF);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10457 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10458 ins_pipe(ialu_cr_reg_mem);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10459 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10460
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10461 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10462 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10463 predicate(Universe::narrow_oop_base() == NULL);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10464 match(Set cr (CmpN (LoadN mem) zero));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10465
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10466 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10467 ins_encode %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10468 __ cmpl(r12, $mem$$Address);
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10469 %}
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10470 ins_pipe(ialu_cr_reg_mem);
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10471 %}
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10472
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10473 // Yanked all unsigned pointer compare operations.
a61af66fc99e Initial load
duke
parents:
diff changeset
10474 // Pointer compares are done with CmpP which is already unsigned.
a61af66fc99e Initial load
duke
parents:
diff changeset
10475
a61af66fc99e Initial load
duke
parents:
diff changeset
10476 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
a61af66fc99e Initial load
duke
parents:
diff changeset
10477 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10478 match(Set cr (CmpL op1 op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10479
a61af66fc99e Initial load
duke
parents:
diff changeset
10480 format %{ "cmpq $op1, $op2" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10481 opcode(0x3B); /* Opcode 3B /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
10482 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10483 ins_pipe(ialu_cr_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
10484 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10485
a61af66fc99e Initial load
duke
parents:
diff changeset
10486 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
a61af66fc99e Initial load
duke
parents:
diff changeset
10487 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10488 match(Set cr (CmpL op1 op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10489
a61af66fc99e Initial load
duke
parents:
diff changeset
10490 format %{ "cmpq $op1, $op2" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10491 opcode(0x81, 0x07); /* Opcode 81 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
10492 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10493 ins_pipe(ialu_cr_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
10494 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10495
a61af66fc99e Initial load
duke
parents:
diff changeset
10496 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
a61af66fc99e Initial load
duke
parents:
diff changeset
10497 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10498 match(Set cr (CmpL op1 (LoadL op2)));
a61af66fc99e Initial load
duke
parents:
diff changeset
10499
a61af66fc99e Initial load
duke
parents:
diff changeset
10500 format %{ "cmpq $op1, $op2" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10501 opcode(0x3B); /* Opcode 3B /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
10502 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10503 ins_pipe(ialu_cr_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
10504 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10505
a61af66fc99e Initial load
duke
parents:
diff changeset
10506 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
a61af66fc99e Initial load
duke
parents:
diff changeset
10507 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10508 match(Set cr (CmpL src zero));
a61af66fc99e Initial load
duke
parents:
diff changeset
10509
a61af66fc99e Initial load
duke
parents:
diff changeset
10510 format %{ "testq $src, $src" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10511 opcode(0x85);
a61af66fc99e Initial load
duke
parents:
diff changeset
10512 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10513 ins_pipe(ialu_cr_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
10514 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10515
a61af66fc99e Initial load
duke
parents:
diff changeset
10516 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
a61af66fc99e Initial load
duke
parents:
diff changeset
10517 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10518 match(Set cr (CmpL (AndL src con) zero));
a61af66fc99e Initial load
duke
parents:
diff changeset
10519
a61af66fc99e Initial load
duke
parents:
diff changeset
10520 format %{ "testq $src, $con\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10521 opcode(0xF7, 0x00);
a61af66fc99e Initial load
duke
parents:
diff changeset
10522 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con));
a61af66fc99e Initial load
duke
parents:
diff changeset
10523 ins_pipe(ialu_cr_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
10524 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10525
a61af66fc99e Initial load
duke
parents:
diff changeset
10526 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
a61af66fc99e Initial load
duke
parents:
diff changeset
10527 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10528 match(Set cr (CmpL (AndL src (LoadL mem)) zero));
a61af66fc99e Initial load
duke
parents:
diff changeset
10529
a61af66fc99e Initial load
duke
parents:
diff changeset
10530 format %{ "testq $src, $mem" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10531 opcode(0x85);
a61af66fc99e Initial load
duke
parents:
diff changeset
10532 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
10533 ins_pipe(ialu_cr_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
10534 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10535
a61af66fc99e Initial load
duke
parents:
diff changeset
10536 // Manifest a CmpL result in an integer register. Very painful.
a61af66fc99e Initial load
duke
parents:
diff changeset
10537 // This is the test to avoid.
a61af66fc99e Initial load
duke
parents:
diff changeset
10538 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
a61af66fc99e Initial load
duke
parents:
diff changeset
10539 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10540 match(Set dst (CmpL3 src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10541 effect(KILL flags);
a61af66fc99e Initial load
duke
parents:
diff changeset
10542
a61af66fc99e Initial load
duke
parents:
diff changeset
10543 ins_cost(275); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
10544 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10545 "movl $dst, -1\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10546 "jl,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10547 "setne $dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10548 "movzbl $dst, $dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10549 "done:" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10550 ins_encode(cmpl3_flag(src1, src2, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
10551 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10552 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10553
a61af66fc99e Initial load
duke
parents:
diff changeset
10554 //----------Max and Min--------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
10555 // Min Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
10556
a61af66fc99e Initial load
duke
parents:
diff changeset
10557 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
10558 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10559 effect(USE_DEF dst, USE src, USE cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
10560
a61af66fc99e Initial load
duke
parents:
diff changeset
10561 format %{ "cmovlgt $dst, $src\t# min" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10562 opcode(0x0F, 0x4F);
a61af66fc99e Initial load
duke
parents:
diff changeset
10563 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10564 ins_pipe(pipe_cmov_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
10565 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10566
a61af66fc99e Initial load
duke
parents:
diff changeset
10567
a61af66fc99e Initial load
duke
parents:
diff changeset
10568 instruct minI_rReg(rRegI dst, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
10569 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10570 match(Set dst (MinI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10571
a61af66fc99e Initial load
duke
parents:
diff changeset
10572 ins_cost(200);
a61af66fc99e Initial load
duke
parents:
diff changeset
10573 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10574 rFlagsReg cr;
a61af66fc99e Initial load
duke
parents:
diff changeset
10575 compI_rReg(cr, dst, src);
a61af66fc99e Initial load
duke
parents:
diff changeset
10576 cmovI_reg_g(dst, src, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
10577 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10578 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10579
a61af66fc99e Initial load
duke
parents:
diff changeset
10580 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
10581 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10582 effect(USE_DEF dst, USE src, USE cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
10583
a61af66fc99e Initial load
duke
parents:
diff changeset
10584 format %{ "cmovllt $dst, $src\t# max" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10585 opcode(0x0F, 0x4C);
a61af66fc99e Initial load
duke
parents:
diff changeset
10586 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10587 ins_pipe(pipe_cmov_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
10588 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10589
a61af66fc99e Initial load
duke
parents:
diff changeset
10590
a61af66fc99e Initial load
duke
parents:
diff changeset
10591 instruct maxI_rReg(rRegI dst, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
10592 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10593 match(Set dst (MaxI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10594
a61af66fc99e Initial load
duke
parents:
diff changeset
10595 ins_cost(200);
a61af66fc99e Initial load
duke
parents:
diff changeset
10596 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10597 rFlagsReg cr;
a61af66fc99e Initial load
duke
parents:
diff changeset
10598 compI_rReg(cr, dst, src);
a61af66fc99e Initial load
duke
parents:
diff changeset
10599 cmovI_reg_l(dst, src, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
10600 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10601 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10602
a61af66fc99e Initial load
duke
parents:
diff changeset
10603 // ============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
10604 // Branch Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
10605
a61af66fc99e Initial load
duke
parents:
diff changeset
10606 // Jump Direct - Label defines a relative address from JMP+1
a61af66fc99e Initial load
duke
parents:
diff changeset
10607 instruct jmpDir(label labl)
a61af66fc99e Initial load
duke
parents:
diff changeset
10608 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10609 match(Goto);
a61af66fc99e Initial load
duke
parents:
diff changeset
10610 effect(USE labl);
a61af66fc99e Initial load
duke
parents:
diff changeset
10611
a61af66fc99e Initial load
duke
parents:
diff changeset
10612 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
10613 format %{ "jmp $labl" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10614 size(5);
3851
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10615 ins_encode %{
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10616 Label* L = $labl$$label;
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10617 __ jmp(*L, false); // Always long jump
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10618 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10619 ins_pipe(pipe_jmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
10620 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10621
a61af66fc99e Initial load
duke
parents:
diff changeset
10622 // Jump Direct Conditional - Label defines a relative address from Jcc+1
a61af66fc99e Initial load
duke
parents:
diff changeset
10623 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
a61af66fc99e Initial load
duke
parents:
diff changeset
10624 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10625 match(If cop cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
10626 effect(USE labl);
a61af66fc99e Initial load
duke
parents:
diff changeset
10627
a61af66fc99e Initial load
duke
parents:
diff changeset
10628 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
10629 format %{ "j$cop $labl" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10630 size(6);
3851
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10631 ins_encode %{
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10632 Label* L = $labl$$label;
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10633 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10634 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10635 ins_pipe(pipe_jcc);
a61af66fc99e Initial load
duke
parents:
diff changeset
10636 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10637
a61af66fc99e Initial load
duke
parents:
diff changeset
10638 // Jump Direct Conditional - Label defines a relative address from Jcc+1
a61af66fc99e Initial load
duke
parents:
diff changeset
10639 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
a61af66fc99e Initial load
duke
parents:
diff changeset
10640 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10641 match(CountedLoopEnd cop cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
10642 effect(USE labl);
a61af66fc99e Initial load
duke
parents:
diff changeset
10643
a61af66fc99e Initial load
duke
parents:
diff changeset
10644 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
10645 format %{ "j$cop $labl\t# loop end" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10646 size(6);
3851
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10647 ins_encode %{
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10648 Label* L = $labl$$label;
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10649 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10650 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10651 ins_pipe(pipe_jcc);
a61af66fc99e Initial load
duke
parents:
diff changeset
10652 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10653
a61af66fc99e Initial load
duke
parents:
diff changeset
10654 // Jump Direct Conditional - Label defines a relative address from Jcc+1
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10655 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10656 match(CountedLoopEnd cop cmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
10657 effect(USE labl);
a61af66fc99e Initial load
duke
parents:
diff changeset
10658
a61af66fc99e Initial load
duke
parents:
diff changeset
10659 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
10660 format %{ "j$cop,u $labl\t# loop end" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10661 size(6);
3851
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10662 ins_encode %{
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10663 Label* L = $labl$$label;
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10664 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10665 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10666 ins_pipe(pipe_jcc);
a61af66fc99e Initial load
duke
parents:
diff changeset
10667 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10668
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10669 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10670 match(CountedLoopEnd cop cmp);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10671 effect(USE labl);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10672
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10673 ins_cost(200);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10674 format %{ "j$cop,u $labl\t# loop end" %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10675 size(6);
3851
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10676 ins_encode %{
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10677 Label* L = $labl$$label;
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10678 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10679 %}
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10680 ins_pipe(pipe_jcc);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10681 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10682
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10683 // Jump Direct Conditional - using unsigned comparison
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10684 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10685 match(If cop cmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
10686 effect(USE labl);
a61af66fc99e Initial load
duke
parents:
diff changeset
10687
a61af66fc99e Initial load
duke
parents:
diff changeset
10688 ins_cost(300);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10689 format %{ "j$cop,u $labl" %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10690 size(6);
3851
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10691 ins_encode %{
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10692 Label* L = $labl$$label;
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10693 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10694 %}
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10695 ins_pipe(pipe_jcc);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10696 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10697
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10698 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10699 match(If cop cmp);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10700 effect(USE labl);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10701
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10702 ins_cost(200);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10703 format %{ "j$cop,u $labl" %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10704 size(6);
3851
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10705 ins_encode %{
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10706 Label* L = $labl$$label;
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10707 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10708 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10709 ins_pipe(pipe_jcc);
a61af66fc99e Initial load
duke
parents:
diff changeset
10710 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10711
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10712 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10713 match(If cop cmp);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10714 effect(USE labl);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10715
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10716 ins_cost(200);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10717 format %{ $$template
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10718 if ($cop$$cmpcode == Assembler::notEqual) {
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10719 $$emit$$"jp,u $labl\n\t"
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10720 $$emit$$"j$cop,u $labl"
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10721 } else {
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10722 $$emit$$"jp,u done\n\t"
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10723 $$emit$$"j$cop,u $labl\n\t"
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10724 $$emit$$"done:"
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10725 }
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10726 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10727 ins_encode %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10728 Label* l = $labl$$label;
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10729 if ($cop$$cmpcode == Assembler::notEqual) {
3851
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10730 __ jcc(Assembler::parity, *l, false);
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10731 __ jcc(Assembler::notEqual, *l, false);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10732 } else if ($cop$$cmpcode == Assembler::equal) {
3851
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10733 Label done;
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10734 __ jccb(Assembler::parity, done);
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10735 __ jcc(Assembler::equal, *l, false);
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10736 __ bind(done);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10737 } else {
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10738 ShouldNotReachHere();
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10739 }
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10740 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10741 ins_pipe(pipe_jcc);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10742 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10743
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10744 // ============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
10745 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary
a61af66fc99e Initial load
duke
parents:
diff changeset
10746 // superklass array for an instance of the superklass. Set a hidden
a61af66fc99e Initial load
duke
parents:
diff changeset
10747 // internal cache on a hit (cache is checked with exposed code in
a61af66fc99e Initial load
duke
parents:
diff changeset
10748 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The
a61af66fc99e Initial load
duke
parents:
diff changeset
10749 // encoding ALSO sets flags.
a61af66fc99e Initial load
duke
parents:
diff changeset
10750
a61af66fc99e Initial load
duke
parents:
diff changeset
10751 instruct partialSubtypeCheck(rdi_RegP result,
a61af66fc99e Initial load
duke
parents:
diff changeset
10752 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
a61af66fc99e Initial load
duke
parents:
diff changeset
10753 rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
10754 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10755 match(Set result (PartialSubtypeCheck sub super));
a61af66fc99e Initial load
duke
parents:
diff changeset
10756 effect(KILL rcx, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
10757
a61af66fc99e Initial load
duke
parents:
diff changeset
10758 ins_cost(1100); // slightly larger than the next version
4762
069ab3f976d3 7118863: Move sizeof(klassOopDesc) into the *Klass::*_offset_in_bytes() functions
stefank
parents: 4761
diff changeset
10759 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10760 "movl rcx, [rdi + arrayOopDesc::length_offset_in_bytes()]\t# length to scan\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10761 "addq rdi, arrayOopDex::base_offset_in_bytes(T_OBJECT)\t# Skip to start of data; set NZ in case count is zero\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10762 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10763 "jne,s miss\t\t# Missed: rdi not-zero\n\t"
4762
069ab3f976d3 7118863: Move sizeof(klassOopDesc) into the *Klass::*_offset_in_bytes() functions
stefank
parents: 4761
diff changeset
10764 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10765 "xorq $result, $result\t\t Hit: rdi zero\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10766 "miss:\t" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10767
a61af66fc99e Initial load
duke
parents:
diff changeset
10768 opcode(0x1); // Force a XOR of RDI
a61af66fc99e Initial load
duke
parents:
diff changeset
10769 ins_encode(enc_PartialSubtypeCheck());
a61af66fc99e Initial load
duke
parents:
diff changeset
10770 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10771 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10772
a61af66fc99e Initial load
duke
parents:
diff changeset
10773 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr,
a61af66fc99e Initial load
duke
parents:
diff changeset
10774 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
a61af66fc99e Initial load
duke
parents:
diff changeset
10775 immP0 zero,
a61af66fc99e Initial load
duke
parents:
diff changeset
10776 rdi_RegP result)
a61af66fc99e Initial load
duke
parents:
diff changeset
10777 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10778 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
a61af66fc99e Initial load
duke
parents:
diff changeset
10779 effect(KILL rcx, KILL result);
a61af66fc99e Initial load
duke
parents:
diff changeset
10780
a61af66fc99e Initial load
duke
parents:
diff changeset
10781 ins_cost(1000);
4762
069ab3f976d3 7118863: Move sizeof(klassOopDesc) into the *Klass::*_offset_in_bytes() functions
stefank
parents: 4761
diff changeset
10782 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10783 "movl rcx, [rdi + arrayOopDesc::length_offset_in_bytes()]\t# length to scan\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10784 "addq rdi, arrayOopDex::base_offset_in_bytes(T_OBJECT)\t# Skip to start of data; set NZ in case count is zero\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10785 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10786 "jne,s miss\t\t# Missed: flags nz\n\t"
4762
069ab3f976d3 7118863: Move sizeof(klassOopDesc) into the *Klass::*_offset_in_bytes() functions
stefank
parents: 4761
diff changeset
10787 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10788 "miss:\t" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10789
a61af66fc99e Initial load
duke
parents:
diff changeset
10790 opcode(0x0); // No need to XOR RDI
a61af66fc99e Initial load
duke
parents:
diff changeset
10791 ins_encode(enc_PartialSubtypeCheck());
a61af66fc99e Initial load
duke
parents:
diff changeset
10792 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10793 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10794
a61af66fc99e Initial load
duke
parents:
diff changeset
10795 // ============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
10796 // Branch Instructions -- short offset versions
a61af66fc99e Initial load
duke
parents:
diff changeset
10797 //
a61af66fc99e Initial load
duke
parents:
diff changeset
10798 // These instructions are used to replace jumps of a long offset (the default
a61af66fc99e Initial load
duke
parents:
diff changeset
10799 // match) with jumps of a shorter offset. These instructions are all tagged
a61af66fc99e Initial load
duke
parents:
diff changeset
10800 // with the ins_short_branch attribute, which causes the ADLC to suppress the
a61af66fc99e Initial load
duke
parents:
diff changeset
10801 // match rules in general matching. Instead, the ADLC generates a conversion
a61af66fc99e Initial load
duke
parents:
diff changeset
10802 // method in the MachNode which can be used to do in-place replacement of the
a61af66fc99e Initial load
duke
parents:
diff changeset
10803 // long variant with the shorter variant. The compiler will determine if a
a61af66fc99e Initial load
duke
parents:
diff changeset
10804 // branch can be taken by the is_short_branch_offset() predicate in the machine
a61af66fc99e Initial load
duke
parents:
diff changeset
10805 // specific code section of the file.
a61af66fc99e Initial load
duke
parents:
diff changeset
10806
a61af66fc99e Initial load
duke
parents:
diff changeset
10807 // Jump Direct - Label defines a relative address from JMP+1
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10808 instruct jmpDir_short(label labl) %{
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10809 match(Goto);
a61af66fc99e Initial load
duke
parents:
diff changeset
10810 effect(USE labl);
a61af66fc99e Initial load
duke
parents:
diff changeset
10811
a61af66fc99e Initial load
duke
parents:
diff changeset
10812 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
10813 format %{ "jmp,s $labl" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10814 size(2);
3851
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10815 ins_encode %{
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10816 Label* L = $labl$$label;
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10817 __ jmpb(*L);
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10818 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10819 ins_pipe(pipe_jmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
10820 ins_short_branch(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
10821 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10822
a61af66fc99e Initial load
duke
parents:
diff changeset
10823 // Jump Direct Conditional - Label defines a relative address from Jcc+1
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10824 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10825 match(If cop cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
10826 effect(USE labl);
a61af66fc99e Initial load
duke
parents:
diff changeset
10827
a61af66fc99e Initial load
duke
parents:
diff changeset
10828 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
10829 format %{ "j$cop,s $labl" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10830 size(2);
3851
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10831 ins_encode %{
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10832 Label* L = $labl$$label;
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10833 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10834 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10835 ins_pipe(pipe_jcc);
a61af66fc99e Initial load
duke
parents:
diff changeset
10836 ins_short_branch(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
10837 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10838
a61af66fc99e Initial load
duke
parents:
diff changeset
10839 // Jump Direct Conditional - Label defines a relative address from Jcc+1
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10840 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10841 match(CountedLoopEnd cop cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
10842 effect(USE labl);
a61af66fc99e Initial load
duke
parents:
diff changeset
10843
a61af66fc99e Initial load
duke
parents:
diff changeset
10844 ins_cost(300);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10845 format %{ "j$cop,s $labl\t# loop end" %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10846 size(2);
3851
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10847 ins_encode %{
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10848 Label* L = $labl$$label;
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10849 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10850 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10851 ins_pipe(pipe_jcc);
a61af66fc99e Initial load
duke
parents:
diff changeset
10852 ins_short_branch(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
10853 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10854
a61af66fc99e Initial load
duke
parents:
diff changeset
10855 // Jump Direct Conditional - Label defines a relative address from Jcc+1
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10856 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10857 match(CountedLoopEnd cop cmp);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10858 effect(USE labl);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10859
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10860 ins_cost(300);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10861 format %{ "j$cop,us $labl\t# loop end" %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10862 size(2);
3851
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10863 ins_encode %{
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10864 Label* L = $labl$$label;
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10865 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10866 %}
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10867 ins_pipe(pipe_jcc);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10868 ins_short_branch(1);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10869 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10870
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10871 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10872 match(CountedLoopEnd cop cmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
10873 effect(USE labl);
a61af66fc99e Initial load
duke
parents:
diff changeset
10874
a61af66fc99e Initial load
duke
parents:
diff changeset
10875 ins_cost(300);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10876 format %{ "j$cop,us $labl\t# loop end" %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10877 size(2);
3851
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10878 ins_encode %{
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10879 Label* L = $labl$$label;
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10880 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10881 %}
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10882 ins_pipe(pipe_jcc);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10883 ins_short_branch(1);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10884 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10885
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10886 // Jump Direct Conditional - using unsigned comparison
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10887 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10888 match(If cop cmp);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10889 effect(USE labl);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10890
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10891 ins_cost(300);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10892 format %{ "j$cop,us $labl" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10893 size(2);
3851
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10894 ins_encode %{
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10895 Label* L = $labl$$label;
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10896 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10897 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10898 ins_pipe(pipe_jcc);
a61af66fc99e Initial load
duke
parents:
diff changeset
10899 ins_short_branch(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
10900 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10901
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10902 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10903 match(If cop cmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
10904 effect(USE labl);
a61af66fc99e Initial load
duke
parents:
diff changeset
10905
a61af66fc99e Initial load
duke
parents:
diff changeset
10906 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
10907 format %{ "j$cop,us $labl" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10908 size(2);
3851
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10909 ins_encode %{
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10910 Label* L = $labl$$label;
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10911 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10912 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10913 ins_pipe(pipe_jcc);
a61af66fc99e Initial load
duke
parents:
diff changeset
10914 ins_short_branch(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
10915 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10916
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10917 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10918 match(If cop cmp);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10919 effect(USE labl);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10920
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10921 ins_cost(300);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10922 format %{ $$template
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10923 if ($cop$$cmpcode == Assembler::notEqual) {
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10924 $$emit$$"jp,u,s $labl\n\t"
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10925 $$emit$$"j$cop,u,s $labl"
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10926 } else {
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10927 $$emit$$"jp,u,s done\n\t"
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10928 $$emit$$"j$cop,u,s $labl\n\t"
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10929 $$emit$$"done:"
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10930 }
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10931 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10932 size(4);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10933 ins_encode %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10934 Label* l = $labl$$label;
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10935 if ($cop$$cmpcode == Assembler::notEqual) {
3851
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10936 __ jccb(Assembler::parity, *l);
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10937 __ jccb(Assembler::notEqual, *l);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10938 } else if ($cop$$cmpcode == Assembler::equal) {
3851
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10939 Label done;
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10940 __ jccb(Assembler::parity, done);
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10941 __ jccb(Assembler::equal, *l);
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10942 __ bind(done);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10943 } else {
3851
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10944 ShouldNotReachHere();
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10945 }
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10946 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10947 ins_pipe(pipe_jcc);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10948 ins_short_branch(1);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10949 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
10950
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10951 // ============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
10952 // inlined locking and unlocking
a61af66fc99e Initial load
duke
parents:
diff changeset
10953
a61af66fc99e Initial load
duke
parents:
diff changeset
10954 instruct cmpFastLock(rFlagsReg cr,
4777
e9a5e0a812c8 7125896: Eliminate nested locks
kvn
parents: 4763
diff changeset
10955 rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr)
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10956 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10957 match(Set cr (FastLock object box));
4777
e9a5e0a812c8 7125896: Eliminate nested locks
kvn
parents: 4763
diff changeset
10958 effect(TEMP tmp, TEMP scr, USE_KILL box);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10959
a61af66fc99e Initial load
duke
parents:
diff changeset
10960 ins_cost(300);
4777
e9a5e0a812c8 7125896: Eliminate nested locks
kvn
parents: 4763
diff changeset
10961 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10962 ins_encode(Fast_Lock(object, box, tmp, scr));
a61af66fc99e Initial load
duke
parents:
diff changeset
10963 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10964 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10965
a61af66fc99e Initial load
duke
parents:
diff changeset
10966 instruct cmpFastUnlock(rFlagsReg cr,
a61af66fc99e Initial load
duke
parents:
diff changeset
10967 rRegP object, rax_RegP box, rRegP tmp)
a61af66fc99e Initial load
duke
parents:
diff changeset
10968 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10969 match(Set cr (FastUnlock object box));
4777
e9a5e0a812c8 7125896: Eliminate nested locks
kvn
parents: 4763
diff changeset
10970 effect(TEMP tmp, USE_KILL box);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10971
a61af66fc99e Initial load
duke
parents:
diff changeset
10972 ins_cost(300);
4777
e9a5e0a812c8 7125896: Eliminate nested locks
kvn
parents: 4763
diff changeset
10973 format %{ "fastunlock $object,$box\t! kills $box,$tmp" %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10974 ins_encode(Fast_Unlock(object, box, tmp));
a61af66fc99e Initial load
duke
parents:
diff changeset
10975 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10976 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10977
a61af66fc99e Initial load
duke
parents:
diff changeset
10978
a61af66fc99e Initial load
duke
parents:
diff changeset
10979 // ============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
10980 // Safepoint Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
10981 instruct safePoint_poll(rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
10982 %{
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
10983 predicate(!Assembler::is_polling_page_far());
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10984 match(SafePoint);
a61af66fc99e Initial load
duke
parents:
diff changeset
10985 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
10986
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
10987 format %{ "testl rax, [rip + #offset_to_poll_page]\t"
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10988 "# Safepoint: poll for GC" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10989 ins_cost(125);
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
10990 ins_encode %{
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
10991 AddressLiteral addr(os::get_polling_page(), relocInfo::poll_type);
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
10992 __ testl(rax, addr);
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
10993 %}
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
10994 ins_pipe(ialu_reg_mem);
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
10995 %}
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
10996
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
10997 instruct safePoint_poll_far(rFlagsReg cr, rRegP poll)
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
10998 %{
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
10999 predicate(Assembler::is_polling_page_far());
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
11000 match(SafePoint poll);
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
11001 effect(KILL cr, USE poll);
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
11002
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
11003 format %{ "testl rax, [$poll]\t"
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
11004 "# Safepoint: poll for GC" %}
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
11005 ins_cost(125);
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
11006 ins_encode %{
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
11007 __ relocate(relocInfo::poll_type);
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
11008 __ testl(rax, Address($poll$$Register, 0));
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
11009 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11010 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
11011 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11012
a61af66fc99e Initial load
duke
parents:
diff changeset
11013 // ============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
11014 // Procedure Call/Return Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
11015 // Call Java Static Instruction
a61af66fc99e Initial load
duke
parents:
diff changeset
11016 // Note: If this code changes, the corresponding ret_addr_offset() and
a61af66fc99e Initial load
duke
parents:
diff changeset
11017 // compute_padding() functions will have to be adjusted.
1137
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
11018 instruct CallStaticJavaDirect(method meth) %{
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11019 match(CallStaticJava);
1137
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
11020 predicate(!((CallStaticJavaNode*) n)->is_method_handle_invoke());
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11021 effect(USE meth);
a61af66fc99e Initial load
duke
parents:
diff changeset
11022
a61af66fc99e Initial load
duke
parents:
diff changeset
11023 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
11024 format %{ "call,static " %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11025 opcode(0xE8); /* E8 cd */
a61af66fc99e Initial load
duke
parents:
diff changeset
11026 ins_encode(Java_Static_Call(meth), call_epilog);
a61af66fc99e Initial load
duke
parents:
diff changeset
11027 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
11028 ins_alignment(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
11029 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11030
1137
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
11031 // Call Java Static Instruction (method handle version)
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
11032 // Note: If this code changes, the corresponding ret_addr_offset() and
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
11033 // compute_padding() functions will have to be adjusted.
1567
110501f54a99 6934104: JSR 292 needs to support SPARC C2
twisti
parents: 1396
diff changeset
11034 instruct CallStaticJavaHandle(method meth, rbp_RegP rbp_mh_SP_save) %{
1137
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
11035 match(CallStaticJava);
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
11036 predicate(((CallStaticJavaNode*) n)->is_method_handle_invoke());
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
11037 effect(USE meth);
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
11038 // RBP is saved by all callees (for interpreter stack correction).
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
11039 // We use it here for a similar purpose, in {preserve,restore}_SP.
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
11040
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
11041 ins_cost(300);
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
11042 format %{ "call,static/MethodHandle " %}
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
11043 opcode(0xE8); /* E8 cd */
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
11044 ins_encode(preserve_SP,
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
11045 Java_Static_Call(meth),
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
11046 restore_SP,
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
11047 call_epilog);
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
11048 ins_pipe(pipe_slow);
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
11049 ins_alignment(4);
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
11050 %}
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
11051
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11052 // Call Java Dynamic Instruction
a61af66fc99e Initial load
duke
parents:
diff changeset
11053 // Note: If this code changes, the corresponding ret_addr_offset() and
a61af66fc99e Initial load
duke
parents:
diff changeset
11054 // compute_padding() functions will have to be adjusted.
a61af66fc99e Initial load
duke
parents:
diff changeset
11055 instruct CallDynamicJavaDirect(method meth)
a61af66fc99e Initial load
duke
parents:
diff changeset
11056 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11057 match(CallDynamicJava);
a61af66fc99e Initial load
duke
parents:
diff changeset
11058 effect(USE meth);
a61af66fc99e Initial load
duke
parents:
diff changeset
11059
a61af66fc99e Initial load
duke
parents:
diff changeset
11060 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
11061 format %{ "movq rax, #Universe::non_oop_word()\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
11062 "call,dynamic " %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11063 opcode(0xE8); /* E8 cd */
a61af66fc99e Initial load
duke
parents:
diff changeset
11064 ins_encode(Java_Dynamic_Call(meth), call_epilog);
a61af66fc99e Initial load
duke
parents:
diff changeset
11065 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
11066 ins_alignment(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
11067 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11068
a61af66fc99e Initial load
duke
parents:
diff changeset
11069 // Call Runtime Instruction
a61af66fc99e Initial load
duke
parents:
diff changeset
11070 instruct CallRuntimeDirect(method meth)
a61af66fc99e Initial load
duke
parents:
diff changeset
11071 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11072 match(CallRuntime);
a61af66fc99e Initial load
duke
parents:
diff changeset
11073 effect(USE meth);
a61af66fc99e Initial load
duke
parents:
diff changeset
11074
a61af66fc99e Initial load
duke
parents:
diff changeset
11075 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
11076 format %{ "call,runtime " %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11077 opcode(0xE8); /* E8 cd */
a61af66fc99e Initial load
duke
parents:
diff changeset
11078 ins_encode(Java_To_Runtime(meth));
a61af66fc99e Initial load
duke
parents:
diff changeset
11079 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
11080 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11081
a61af66fc99e Initial load
duke
parents:
diff changeset
11082 // Call runtime without safepoint
a61af66fc99e Initial load
duke
parents:
diff changeset
11083 instruct CallLeafDirect(method meth)
a61af66fc99e Initial load
duke
parents:
diff changeset
11084 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11085 match(CallLeaf);
a61af66fc99e Initial load
duke
parents:
diff changeset
11086 effect(USE meth);
a61af66fc99e Initial load
duke
parents:
diff changeset
11087
a61af66fc99e Initial load
duke
parents:
diff changeset
11088 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
11089 format %{ "call_leaf,runtime " %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11090 opcode(0xE8); /* E8 cd */
a61af66fc99e Initial load
duke
parents:
diff changeset
11091 ins_encode(Java_To_Runtime(meth));
a61af66fc99e Initial load
duke
parents:
diff changeset
11092 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
11093 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11094
a61af66fc99e Initial load
duke
parents:
diff changeset
11095 // Call runtime without safepoint
a61af66fc99e Initial load
duke
parents:
diff changeset
11096 instruct CallLeafNoFPDirect(method meth)
a61af66fc99e Initial load
duke
parents:
diff changeset
11097 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11098 match(CallLeafNoFP);
a61af66fc99e Initial load
duke
parents:
diff changeset
11099 effect(USE meth);
a61af66fc99e Initial load
duke
parents:
diff changeset
11100
a61af66fc99e Initial load
duke
parents:
diff changeset
11101 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
11102 format %{ "call_leaf_nofp,runtime " %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11103 opcode(0xE8); /* E8 cd */
a61af66fc99e Initial load
duke
parents:
diff changeset
11104 ins_encode(Java_To_Runtime(meth));
a61af66fc99e Initial load
duke
parents:
diff changeset
11105 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
11106 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11107
a61af66fc99e Initial load
duke
parents:
diff changeset
11108 // Return Instruction
a61af66fc99e Initial load
duke
parents:
diff changeset
11109 // Remove the return address & jump to it.
a61af66fc99e Initial load
duke
parents:
diff changeset
11110 // Notice: We always emit a nop after a ret to make sure there is room
a61af66fc99e Initial load
duke
parents:
diff changeset
11111 // for safepoint patching
a61af66fc99e Initial load
duke
parents:
diff changeset
11112 instruct Ret()
a61af66fc99e Initial load
duke
parents:
diff changeset
11113 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11114 match(Return);
a61af66fc99e Initial load
duke
parents:
diff changeset
11115
a61af66fc99e Initial load
duke
parents:
diff changeset
11116 format %{ "ret" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11117 opcode(0xC3);
a61af66fc99e Initial load
duke
parents:
diff changeset
11118 ins_encode(OpcP);
a61af66fc99e Initial load
duke
parents:
diff changeset
11119 ins_pipe(pipe_jmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
11120 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11121
a61af66fc99e Initial load
duke
parents:
diff changeset
11122 // Tail Call; Jump from runtime stub to Java code.
a61af66fc99e Initial load
duke
parents:
diff changeset
11123 // Also known as an 'interprocedural jump'.
a61af66fc99e Initial load
duke
parents:
diff changeset
11124 // Target of jump will eventually return to caller.
a61af66fc99e Initial load
duke
parents:
diff changeset
11125 // TailJump below removes the return address.
a61af66fc99e Initial load
duke
parents:
diff changeset
11126 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop)
a61af66fc99e Initial load
duke
parents:
diff changeset
11127 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11128 match(TailCall jump_target method_oop);
a61af66fc99e Initial load
duke
parents:
diff changeset
11129
a61af66fc99e Initial load
duke
parents:
diff changeset
11130 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
11131 format %{ "jmp $jump_target\t# rbx holds method oop" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11132 opcode(0xFF, 0x4); /* Opcode FF /4 */
a61af66fc99e Initial load
duke
parents:
diff changeset
11133 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target));
a61af66fc99e Initial load
duke
parents:
diff changeset
11134 ins_pipe(pipe_jmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
11135 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11136
a61af66fc99e Initial load
duke
parents:
diff changeset
11137 // Tail Jump; remove the return address; jump to target.
a61af66fc99e Initial load
duke
parents:
diff changeset
11138 // TailCall above leaves the return address around.
a61af66fc99e Initial load
duke
parents:
diff changeset
11139 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
a61af66fc99e Initial load
duke
parents:
diff changeset
11140 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11141 match(TailJump jump_target ex_oop);
a61af66fc99e Initial load
duke
parents:
diff changeset
11142
a61af66fc99e Initial load
duke
parents:
diff changeset
11143 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
11144 format %{ "popq rdx\t# pop return address\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
11145 "jmp $jump_target" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11146 opcode(0xFF, 0x4); /* Opcode FF /4 */
a61af66fc99e Initial load
duke
parents:
diff changeset
11147 ins_encode(Opcode(0x5a), // popq rdx
a61af66fc99e Initial load
duke
parents:
diff changeset
11148 REX_reg(jump_target), OpcP, reg_opc(jump_target));
a61af66fc99e Initial load
duke
parents:
diff changeset
11149 ins_pipe(pipe_jmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
11150 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11151
a61af66fc99e Initial load
duke
parents:
diff changeset
11152 // Create exception oop: created by stack-crawling runtime code.
a61af66fc99e Initial load
duke
parents:
diff changeset
11153 // Created exception is now available to this handler, and is setup
a61af66fc99e Initial load
duke
parents:
diff changeset
11154 // just prior to jumping to this handler. No code emitted.
a61af66fc99e Initial load
duke
parents:
diff changeset
11155 instruct CreateException(rax_RegP ex_oop)
a61af66fc99e Initial load
duke
parents:
diff changeset
11156 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11157 match(Set ex_oop (CreateEx));
a61af66fc99e Initial load
duke
parents:
diff changeset
11158
a61af66fc99e Initial load
duke
parents:
diff changeset
11159 size(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
11160 // use the following format syntax
a61af66fc99e Initial load
duke
parents:
diff changeset
11161 format %{ "# exception oop is in rax; no code emitted" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11162 ins_encode();
a61af66fc99e Initial load
duke
parents:
diff changeset
11163 ins_pipe(empty);
a61af66fc99e Initial load
duke
parents:
diff changeset
11164 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11165
a61af66fc99e Initial load
duke
parents:
diff changeset
11166 // Rethrow exception:
a61af66fc99e Initial load
duke
parents:
diff changeset
11167 // The exception oop will come in the first argument position.
a61af66fc99e Initial load
duke
parents:
diff changeset
11168 // Then JUMP (not call) to the rethrow stub code.
a61af66fc99e Initial load
duke
parents:
diff changeset
11169 instruct RethrowException()
a61af66fc99e Initial load
duke
parents:
diff changeset
11170 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11171 match(Rethrow);
a61af66fc99e Initial load
duke
parents:
diff changeset
11172
a61af66fc99e Initial load
duke
parents:
diff changeset
11173 // use the following format syntax
a61af66fc99e Initial load
duke
parents:
diff changeset
11174 format %{ "jmp rethrow_stub" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11175 ins_encode(enc_rethrow);
a61af66fc99e Initial load
duke
parents:
diff changeset
11176 ins_pipe(pipe_jmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
11177 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11178
a61af66fc99e Initial load
duke
parents:
diff changeset
11179
4950
9b8ce46870df 7145346: VerifyStackAtCalls is broken
kvn
parents: 4947
diff changeset
11180 // ============================================================================
9b8ce46870df 7145346: VerifyStackAtCalls is broken
kvn
parents: 4947
diff changeset
11181 // This name is KNOWN by the ADLC and cannot be changed.
9b8ce46870df 7145346: VerifyStackAtCalls is broken
kvn
parents: 4947
diff changeset
11182 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
9b8ce46870df 7145346: VerifyStackAtCalls is broken
kvn
parents: 4947
diff changeset
11183 // for this guy.
9b8ce46870df 7145346: VerifyStackAtCalls is broken
kvn
parents: 4947
diff changeset
11184 instruct tlsLoadP(r15_RegP dst) %{
9b8ce46870df 7145346: VerifyStackAtCalls is broken
kvn
parents: 4947
diff changeset
11185 match(Set dst (ThreadLocal));
9b8ce46870df 7145346: VerifyStackAtCalls is broken
kvn
parents: 4947
diff changeset
11186 effect(DEF dst);
9b8ce46870df 7145346: VerifyStackAtCalls is broken
kvn
parents: 4947
diff changeset
11187
9b8ce46870df 7145346: VerifyStackAtCalls is broken
kvn
parents: 4947
diff changeset
11188 size(0);
9b8ce46870df 7145346: VerifyStackAtCalls is broken
kvn
parents: 4947
diff changeset
11189 format %{ "# TLS is in R15" %}
9b8ce46870df 7145346: VerifyStackAtCalls is broken
kvn
parents: 4947
diff changeset
11190 ins_encode( /*empty encoding*/ );
9b8ce46870df 7145346: VerifyStackAtCalls is broken
kvn
parents: 4947
diff changeset
11191 ins_pipe(ialu_reg_reg);
9b8ce46870df 7145346: VerifyStackAtCalls is broken
kvn
parents: 4947
diff changeset
11192 %}
9b8ce46870df 7145346: VerifyStackAtCalls is broken
kvn
parents: 4947
diff changeset
11193
9b8ce46870df 7145346: VerifyStackAtCalls is broken
kvn
parents: 4947
diff changeset
11194
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11195 //----------PEEPHOLE RULES-----------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
11196 // These must follow all instruction definitions as they use the names
a61af66fc99e Initial load
duke
parents:
diff changeset
11197 // defined in the instructions definitions.
a61af66fc99e Initial load
duke
parents:
diff changeset
11198 //
605
98cb887364d3 6810672: Comment typos
twisti
parents: 569
diff changeset
11199 // peepmatch ( root_instr_name [preceding_instruction]* );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11200 //
a61af66fc99e Initial load
duke
parents:
diff changeset
11201 // peepconstraint %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11202 // (instruction_number.operand_name relational_op instruction_number.operand_name
a61af66fc99e Initial load
duke
parents:
diff changeset
11203 // [, ...] );
a61af66fc99e Initial load
duke
parents:
diff changeset
11204 // // instruction numbers are zero-based using left to right order in peepmatch
a61af66fc99e Initial load
duke
parents:
diff changeset
11205 //
a61af66fc99e Initial load
duke
parents:
diff changeset
11206 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
11207 // // provide an instruction_number.operand_name for each operand that appears
a61af66fc99e Initial load
duke
parents:
diff changeset
11208 // // in the replacement instruction's match rule
a61af66fc99e Initial load
duke
parents:
diff changeset
11209 //
a61af66fc99e Initial load
duke
parents:
diff changeset
11210 // ---------VM FLAGS---------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
11211 //
a61af66fc99e Initial load
duke
parents:
diff changeset
11212 // All peephole optimizations can be turned off using -XX:-OptoPeephole
a61af66fc99e Initial load
duke
parents:
diff changeset
11213 //
a61af66fc99e Initial load
duke
parents:
diff changeset
11214 // Each peephole rule is given an identifying number starting with zero and
a61af66fc99e Initial load
duke
parents:
diff changeset
11215 // increasing by one in the order seen by the parser. An individual peephole
a61af66fc99e Initial load
duke
parents:
diff changeset
11216 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
a61af66fc99e Initial load
duke
parents:
diff changeset
11217 // on the command-line.
a61af66fc99e Initial load
duke
parents:
diff changeset
11218 //
a61af66fc99e Initial load
duke
parents:
diff changeset
11219 // ---------CURRENT LIMITATIONS----------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
11220 //
a61af66fc99e Initial load
duke
parents:
diff changeset
11221 // Only match adjacent instructions in same basic block
a61af66fc99e Initial load
duke
parents:
diff changeset
11222 // Only equality constraints
a61af66fc99e Initial load
duke
parents:
diff changeset
11223 // Only constraints between operands, not (0.dest_reg == RAX_enc)
a61af66fc99e Initial load
duke
parents:
diff changeset
11224 // Only one replacement instruction
a61af66fc99e Initial load
duke
parents:
diff changeset
11225 //
a61af66fc99e Initial load
duke
parents:
diff changeset
11226 // ---------EXAMPLE----------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
11227 //
a61af66fc99e Initial load
duke
parents:
diff changeset
11228 // // pertinent parts of existing instructions in architecture description
a61af66fc99e Initial load
duke
parents:
diff changeset
11229 // instruct movI(rRegI dst, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
11230 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11231 // match(Set dst (CopyI src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11232 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11233 //
a61af66fc99e Initial load
duke
parents:
diff changeset
11234 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
11235 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11236 // match(Set dst (AddI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11237 // effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
11238 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11239 //
a61af66fc99e Initial load
duke
parents:
diff changeset
11240 // // Change (inc mov) to lea
a61af66fc99e Initial load
duke
parents:
diff changeset
11241 // peephole %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11242 // // increment preceeded by register-register move
a61af66fc99e Initial load
duke
parents:
diff changeset
11243 // peepmatch ( incI_rReg movI );
a61af66fc99e Initial load
duke
parents:
diff changeset
11244 // // require that the destination register of the increment
a61af66fc99e Initial load
duke
parents:
diff changeset
11245 // // match the destination register of the move
a61af66fc99e Initial load
duke
parents:
diff changeset
11246 // peepconstraint ( 0.dst == 1.dst );
a61af66fc99e Initial load
duke
parents:
diff changeset
11247 // // construct a replacement instruction that sets
a61af66fc99e Initial load
duke
parents:
diff changeset
11248 // // the destination to ( move's source register + one )
a61af66fc99e Initial load
duke
parents:
diff changeset
11249 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
11250 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11251 //
a61af66fc99e Initial load
duke
parents:
diff changeset
11252
a61af66fc99e Initial load
duke
parents:
diff changeset
11253 // Implementation no longer uses movX instructions since
a61af66fc99e Initial load
duke
parents:
diff changeset
11254 // machine-independent system no longer uses CopyX nodes.
a61af66fc99e Initial load
duke
parents:
diff changeset
11255 //
a61af66fc99e Initial load
duke
parents:
diff changeset
11256 // peephole
a61af66fc99e Initial load
duke
parents:
diff changeset
11257 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11258 // peepmatch (incI_rReg movI);
a61af66fc99e Initial load
duke
parents:
diff changeset
11259 // peepconstraint (0.dst == 1.dst);
a61af66fc99e Initial load
duke
parents:
diff changeset
11260 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11261 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11262
a61af66fc99e Initial load
duke
parents:
diff changeset
11263 // peephole
a61af66fc99e Initial load
duke
parents:
diff changeset
11264 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11265 // peepmatch (decI_rReg movI);
a61af66fc99e Initial load
duke
parents:
diff changeset
11266 // peepconstraint (0.dst == 1.dst);
a61af66fc99e Initial load
duke
parents:
diff changeset
11267 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11268 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11269
a61af66fc99e Initial load
duke
parents:
diff changeset
11270 // peephole
a61af66fc99e Initial load
duke
parents:
diff changeset
11271 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11272 // peepmatch (addI_rReg_imm movI);
a61af66fc99e Initial load
duke
parents:
diff changeset
11273 // peepconstraint (0.dst == 1.dst);
a61af66fc99e Initial load
duke
parents:
diff changeset
11274 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11275 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11276
a61af66fc99e Initial load
duke
parents:
diff changeset
11277 // peephole
a61af66fc99e Initial load
duke
parents:
diff changeset
11278 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11279 // peepmatch (incL_rReg movL);
a61af66fc99e Initial load
duke
parents:
diff changeset
11280 // peepconstraint (0.dst == 1.dst);
a61af66fc99e Initial load
duke
parents:
diff changeset
11281 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11282 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11283
a61af66fc99e Initial load
duke
parents:
diff changeset
11284 // peephole
a61af66fc99e Initial load
duke
parents:
diff changeset
11285 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11286 // peepmatch (decL_rReg movL);
a61af66fc99e Initial load
duke
parents:
diff changeset
11287 // peepconstraint (0.dst == 1.dst);
a61af66fc99e Initial load
duke
parents:
diff changeset
11288 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11289 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11290
a61af66fc99e Initial load
duke
parents:
diff changeset
11291 // peephole
a61af66fc99e Initial load
duke
parents:
diff changeset
11292 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11293 // peepmatch (addL_rReg_imm movL);
a61af66fc99e Initial load
duke
parents:
diff changeset
11294 // peepconstraint (0.dst == 1.dst);
a61af66fc99e Initial load
duke
parents:
diff changeset
11295 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11296 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11297
a61af66fc99e Initial load
duke
parents:
diff changeset
11298 // peephole
a61af66fc99e Initial load
duke
parents:
diff changeset
11299 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11300 // peepmatch (addP_rReg_imm movP);
a61af66fc99e Initial load
duke
parents:
diff changeset
11301 // peepconstraint (0.dst == 1.dst);
a61af66fc99e Initial load
duke
parents:
diff changeset
11302 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11303 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11304
a61af66fc99e Initial load
duke
parents:
diff changeset
11305 // // Change load of spilled value to only a spill
a61af66fc99e Initial load
duke
parents:
diff changeset
11306 // instruct storeI(memory mem, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
11307 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11308 // match(Set mem (StoreI mem src));
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parents:
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11309 // %}
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11310 //
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diff changeset
11311 // instruct loadI(rRegI dst, memory mem)
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11312 // %{
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parents:
diff changeset
11313 // match(Set dst (LoadI mem));
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11314 // %}
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parents:
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11315 //
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parents:
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11316
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parents:
diff changeset
11317 peephole
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parents:
diff changeset
11318 %{
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parents:
diff changeset
11319 peepmatch (loadI storeI);
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parents:
diff changeset
11320 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
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parents:
diff changeset
11321 peepreplace (storeI(1.mem 1.mem 1.src));
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parents:
diff changeset
11322 %}
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parents:
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11323
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parents:
diff changeset
11324 peephole
a61af66fc99e Initial load
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parents:
diff changeset
11325 %{
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parents:
diff changeset
11326 peepmatch (loadL storeL);
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parents:
diff changeset
11327 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
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parents:
diff changeset
11328 peepreplace (storeL(1.mem 1.mem 1.src));
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parents:
diff changeset
11329 %}
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parents:
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11330
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parents:
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11331 //----------SMARTSPILL RULES---------------------------------------------------
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parents:
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11332 // These must follow all instruction definitions as they use the names
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11333 // defined in the instructions definitions.