Mercurial > hg > truffle
annotate src/cpu/x86/vm/x86_64.ad @ 2401:7e88bdae86ec
7029017: Additional architecture support for c2 compiler
Summary: Enables cross building of a c2 VM. Support masking of shift counts when the processor architecture mandates it.
Reviewed-by: kvn, never
| author | roland |
|---|---|
| date | Fri, 25 Mar 2011 09:35:39 +0100 |
| parents | 41d4973cf100 |
| children | b40d4fa697bf |
| rev | line source |
|---|---|
| 0 | 1 // |
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2 // Copyright (c) 2003, 2011, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 // | |
| 5 // This code is free software; you can redistribute it and/or modify it | |
| 6 // under the terms of the GNU General Public License version 2 only, as | |
| 7 // published by the Free Software Foundation. | |
| 8 // | |
| 9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 // version 2 for more details (a copy is included in the LICENSE file that | |
| 13 // accompanied this code). | |
| 14 // | |
| 15 // You should have received a copy of the GNU General Public License version | |
| 16 // 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 // | |
|
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19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 // or visit www.oracle.com if you need additional information or have any |
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21 // questions. |
| 0 | 22 // |
| 23 // | |
| 24 | |
| 25 // AMD64 Architecture Description File | |
| 26 | |
| 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ | |
| 28 // This information is used by the matcher and the register allocator to | |
| 29 // describe individual registers and classes of registers within the target | |
| 30 // archtecture. | |
| 31 | |
| 32 register %{ | |
| 33 //----------Architecture Description Register Definitions---------------------- | |
| 34 // General Registers | |
| 35 // "reg_def" name ( register save type, C convention save type, | |
| 36 // ideal register type, encoding ); | |
| 37 // Register Save Types: | |
| 38 // | |
| 39 // NS = No-Save: The register allocator assumes that these registers | |
| 40 // can be used without saving upon entry to the method, & | |
| 41 // that they do not need to be saved at call sites. | |
| 42 // | |
| 43 // SOC = Save-On-Call: The register allocator assumes that these registers | |
| 44 // can be used without saving upon entry to the method, | |
| 45 // but that they must be saved at call sites. | |
| 46 // | |
| 47 // SOE = Save-On-Entry: The register allocator assumes that these registers | |
| 48 // must be saved before using them upon entry to the | |
| 49 // method, but they do not need to be saved at call | |
| 50 // sites. | |
| 51 // | |
| 52 // AS = Always-Save: The register allocator assumes that these registers | |
| 53 // must be saved before using them upon entry to the | |
| 54 // method, & that they must be saved at call sites. | |
| 55 // | |
| 56 // Ideal Register Type is used to determine how to save & restore a | |
| 57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get | |
| 58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. | |
| 59 // | |
| 60 // The encoding number is the actual bit-pattern placed into the opcodes. | |
| 61 | |
| 62 // General Registers | |
| 63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when | |
| 64 // used as byte registers) | |
| 65 | |
| 66 // Previously set RBX, RSI, and RDI as save-on-entry for java code | |
| 67 // Turn off SOE in java-code due to frequent use of uncommon-traps. | |
| 68 // Now that allocator is better, turn on RSI and RDI as SOE registers. | |
| 69 | |
| 70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg()); | |
| 71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next()); | |
| 72 | |
| 73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg()); | |
| 74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next()); | |
| 75 | |
| 76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg()); | |
| 77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next()); | |
| 78 | |
| 79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg()); | |
| 80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next()); | |
| 81 | |
| 82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg()); | |
| 83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next()); | |
| 84 | |
| 85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code | |
| 86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg()); | |
| 87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next()); | |
| 88 | |
| 89 #ifdef _WIN64 | |
| 90 | |
| 91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg()); | |
| 92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next()); | |
| 93 | |
| 94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg()); | |
| 95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next()); | |
| 96 | |
| 97 #else | |
| 98 | |
| 99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg()); | |
| 100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next()); | |
| 101 | |
| 102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg()); | |
| 103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next()); | |
| 104 | |
| 105 #endif | |
| 106 | |
| 107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg()); | |
| 108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next()); | |
| 109 | |
| 110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg()); | |
| 111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next()); | |
| 112 | |
| 113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg()); | |
| 114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next()); | |
| 115 | |
| 116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg()); | |
| 117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next()); | |
| 118 | |
| 119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg()); | |
| 120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next()); | |
| 121 | |
| 122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg()); | |
| 123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next()); | |
| 124 | |
| 125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg()); | |
| 126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next()); | |
| 127 | |
| 128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg()); | |
| 129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next()); | |
| 130 | |
| 131 | |
| 132 // Floating Point Registers | |
| 133 | |
| 134 // XMM registers. 128-bit registers or 4 words each, labeled (a)-d. | |
| 135 // Word a in each register holds a Float, words ab hold a Double. We | |
| 136 // currently do not use the SIMD capabilities, so registers cd are | |
| 137 // unused at the moment. | |
| 138 // XMM8-XMM15 must be encoded with REX. | |
| 139 // Linux ABI: No register preserved across function calls | |
| 140 // XMM0-XMM7 might hold parameters | |
| 141 // Windows ABI: XMM6-XMM15 preserved across function calls | |
| 142 // XMM0-XMM3 might hold parameters | |
| 143 | |
| 144 reg_def XMM0 (SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()); | |
| 145 reg_def XMM0_H (SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next()); | |
| 146 | |
| 147 reg_def XMM1 (SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()); | |
| 148 reg_def XMM1_H (SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next()); | |
| 149 | |
| 150 reg_def XMM2 (SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()); | |
| 151 reg_def XMM2_H (SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next()); | |
| 152 | |
| 153 reg_def XMM3 (SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()); | |
| 154 reg_def XMM3_H (SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next()); | |
| 155 | |
| 156 reg_def XMM4 (SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()); | |
| 157 reg_def XMM4_H (SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next()); | |
| 158 | |
| 159 reg_def XMM5 (SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()); | |
| 160 reg_def XMM5_H (SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next()); | |
| 161 | |
| 162 #ifdef _WIN64 | |
| 163 | |
| 164 reg_def XMM6 (SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()); | |
| 165 reg_def XMM6_H (SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next()); | |
| 166 | |
| 167 reg_def XMM7 (SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()); | |
| 168 reg_def XMM7_H (SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next()); | |
| 169 | |
| 170 reg_def XMM8 (SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()); | |
| 171 reg_def XMM8_H (SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next()); | |
| 172 | |
| 173 reg_def XMM9 (SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()); | |
| 174 reg_def XMM9_H (SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next()); | |
| 175 | |
| 176 reg_def XMM10 (SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()); | |
| 177 reg_def XMM10_H(SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next()); | |
| 178 | |
| 179 reg_def XMM11 (SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()); | |
| 180 reg_def XMM11_H(SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next()); | |
| 181 | |
| 182 reg_def XMM12 (SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()); | |
| 183 reg_def XMM12_H(SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next()); | |
| 184 | |
| 185 reg_def XMM13 (SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()); | |
| 186 reg_def XMM13_H(SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next()); | |
| 187 | |
| 188 reg_def XMM14 (SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()); | |
| 189 reg_def XMM14_H(SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next()); | |
| 190 | |
| 191 reg_def XMM15 (SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()); | |
| 192 reg_def XMM15_H(SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next()); | |
| 193 | |
| 194 #else | |
| 195 | |
| 196 reg_def XMM6 (SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()); | |
| 197 reg_def XMM6_H (SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next()); | |
| 198 | |
| 199 reg_def XMM7 (SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()); | |
| 200 reg_def XMM7_H (SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next()); | |
| 201 | |
| 202 reg_def XMM8 (SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()); | |
| 203 reg_def XMM8_H (SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next()); | |
| 204 | |
| 205 reg_def XMM9 (SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()); | |
| 206 reg_def XMM9_H (SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next()); | |
| 207 | |
| 208 reg_def XMM10 (SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()); | |
| 209 reg_def XMM10_H(SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next()); | |
| 210 | |
| 211 reg_def XMM11 (SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()); | |
| 212 reg_def XMM11_H(SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next()); | |
| 213 | |
| 214 reg_def XMM12 (SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()); | |
| 215 reg_def XMM12_H(SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next()); | |
| 216 | |
| 217 reg_def XMM13 (SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()); | |
| 218 reg_def XMM13_H(SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next()); | |
| 219 | |
| 220 reg_def XMM14 (SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()); | |
| 221 reg_def XMM14_H(SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next()); | |
| 222 | |
| 223 reg_def XMM15 (SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()); | |
| 224 reg_def XMM15_H(SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next()); | |
| 225 | |
| 226 #endif // _WIN64 | |
| 227 | |
| 228 reg_def RFLAGS(SOC, SOC, 0, 16, VMRegImpl::Bad()); | |
| 229 | |
| 230 // Specify priority of register selection within phases of register | |
| 231 // allocation. Highest priority is first. A useful heuristic is to | |
| 232 // give registers a low priority when they are required by machine | |
| 233 // instructions, like EAX and EDX on I486, and choose no-save registers | |
| 234 // before save-on-call, & save-on-call before save-on-entry. Registers | |
| 235 // which participate in fixed calling sequences should come last. | |
| 236 // Registers which are used as pairs must fall on an even boundary. | |
| 237 | |
| 238 alloc_class chunk0(R10, R10_H, | |
| 239 R11, R11_H, | |
| 240 R8, R8_H, | |
| 241 R9, R9_H, | |
| 242 R12, R12_H, | |
| 243 RCX, RCX_H, | |
| 244 RBX, RBX_H, | |
| 245 RDI, RDI_H, | |
| 246 RDX, RDX_H, | |
| 247 RSI, RSI_H, | |
| 248 RAX, RAX_H, | |
| 249 RBP, RBP_H, | |
| 250 R13, R13_H, | |
| 251 R14, R14_H, | |
| 252 R15, R15_H, | |
| 253 RSP, RSP_H); | |
| 254 | |
| 255 // XXX probably use 8-15 first on Linux | |
| 256 alloc_class chunk1(XMM0, XMM0_H, | |
| 257 XMM1, XMM1_H, | |
| 258 XMM2, XMM2_H, | |
| 259 XMM3, XMM3_H, | |
| 260 XMM4, XMM4_H, | |
| 261 XMM5, XMM5_H, | |
| 262 XMM6, XMM6_H, | |
| 263 XMM7, XMM7_H, | |
| 264 XMM8, XMM8_H, | |
| 265 XMM9, XMM9_H, | |
| 266 XMM10, XMM10_H, | |
| 267 XMM11, XMM11_H, | |
| 268 XMM12, XMM12_H, | |
| 269 XMM13, XMM13_H, | |
| 270 XMM14, XMM14_H, | |
| 271 XMM15, XMM15_H); | |
| 272 | |
| 273 alloc_class chunk2(RFLAGS); | |
| 274 | |
| 275 | |
| 276 //----------Architecture Description Register Classes-------------------------- | |
| 277 // Several register classes are automatically defined based upon information in | |
| 278 // this architecture description. | |
| 279 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ ) | |
| 280 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ ) | |
| 281 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ ) | |
| 282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) | |
| 283 // | |
| 284 | |
| 285 // Class for all pointer registers (including RSP) | |
| 286 reg_class any_reg(RAX, RAX_H, | |
| 287 RDX, RDX_H, | |
| 288 RBP, RBP_H, | |
| 289 RDI, RDI_H, | |
| 290 RSI, RSI_H, | |
| 291 RCX, RCX_H, | |
| 292 RBX, RBX_H, | |
| 293 RSP, RSP_H, | |
| 294 R8, R8_H, | |
| 295 R9, R9_H, | |
| 296 R10, R10_H, | |
| 297 R11, R11_H, | |
| 298 R12, R12_H, | |
| 299 R13, R13_H, | |
| 300 R14, R14_H, | |
| 301 R15, R15_H); | |
| 302 | |
| 303 // Class for all pointer registers except RSP | |
| 304 reg_class ptr_reg(RAX, RAX_H, | |
| 305 RDX, RDX_H, | |
| 306 RBP, RBP_H, | |
| 307 RDI, RDI_H, | |
| 308 RSI, RSI_H, | |
| 309 RCX, RCX_H, | |
| 310 RBX, RBX_H, | |
| 311 R8, R8_H, | |
| 312 R9, R9_H, | |
| 313 R10, R10_H, | |
| 314 R11, R11_H, | |
| 315 R13, R13_H, | |
| 316 R14, R14_H); | |
| 317 | |
| 318 // Class for all pointer registers except RAX and RSP | |
| 319 reg_class ptr_no_rax_reg(RDX, RDX_H, | |
| 320 RBP, RBP_H, | |
| 321 RDI, RDI_H, | |
| 322 RSI, RSI_H, | |
| 323 RCX, RCX_H, | |
| 324 RBX, RBX_H, | |
| 325 R8, R8_H, | |
| 326 R9, R9_H, | |
| 327 R10, R10_H, | |
| 328 R11, R11_H, | |
| 329 R13, R13_H, | |
| 330 R14, R14_H); | |
| 331 | |
| 332 reg_class ptr_no_rbp_reg(RDX, RDX_H, | |
| 333 RAX, RAX_H, | |
| 334 RDI, RDI_H, | |
| 335 RSI, RSI_H, | |
| 336 RCX, RCX_H, | |
| 337 RBX, RBX_H, | |
| 338 R8, R8_H, | |
| 339 R9, R9_H, | |
| 340 R10, R10_H, | |
| 341 R11, R11_H, | |
| 342 R13, R13_H, | |
| 343 R14, R14_H); | |
| 344 | |
| 345 // Class for all pointer registers except RAX, RBX and RSP | |
| 346 reg_class ptr_no_rax_rbx_reg(RDX, RDX_H, | |
| 347 RBP, RBP_H, | |
| 348 RDI, RDI_H, | |
| 349 RSI, RSI_H, | |
| 350 RCX, RCX_H, | |
| 351 R8, R8_H, | |
| 352 R9, R9_H, | |
| 353 R10, R10_H, | |
| 354 R11, R11_H, | |
| 355 R13, R13_H, | |
| 356 R14, R14_H); | |
| 357 | |
| 358 // Singleton class for RAX pointer register | |
| 359 reg_class ptr_rax_reg(RAX, RAX_H); | |
| 360 | |
| 361 // Singleton class for RBX pointer register | |
| 362 reg_class ptr_rbx_reg(RBX, RBX_H); | |
| 363 | |
| 364 // Singleton class for RSI pointer register | |
| 365 reg_class ptr_rsi_reg(RSI, RSI_H); | |
| 366 | |
| 367 // Singleton class for RDI pointer register | |
| 368 reg_class ptr_rdi_reg(RDI, RDI_H); | |
| 369 | |
| 370 // Singleton class for RBP pointer register | |
| 371 reg_class ptr_rbp_reg(RBP, RBP_H); | |
| 372 | |
| 373 // Singleton class for stack pointer | |
| 374 reg_class ptr_rsp_reg(RSP, RSP_H); | |
| 375 | |
| 376 // Singleton class for TLS pointer | |
| 377 reg_class ptr_r15_reg(R15, R15_H); | |
| 378 | |
| 379 // Class for all long registers (except RSP) | |
| 380 reg_class long_reg(RAX, RAX_H, | |
| 381 RDX, RDX_H, | |
| 382 RBP, RBP_H, | |
| 383 RDI, RDI_H, | |
| 384 RSI, RSI_H, | |
| 385 RCX, RCX_H, | |
| 386 RBX, RBX_H, | |
| 387 R8, R8_H, | |
| 388 R9, R9_H, | |
| 389 R10, R10_H, | |
| 390 R11, R11_H, | |
| 391 R13, R13_H, | |
| 392 R14, R14_H); | |
| 393 | |
| 394 // Class for all long registers except RAX, RDX (and RSP) | |
| 395 reg_class long_no_rax_rdx_reg(RBP, RBP_H, | |
| 396 RDI, RDI_H, | |
| 397 RSI, RSI_H, | |
| 398 RCX, RCX_H, | |
| 399 RBX, RBX_H, | |
| 400 R8, R8_H, | |
| 401 R9, R9_H, | |
| 402 R10, R10_H, | |
| 403 R11, R11_H, | |
| 404 R13, R13_H, | |
| 405 R14, R14_H); | |
| 406 | |
| 407 // Class for all long registers except RCX (and RSP) | |
| 408 reg_class long_no_rcx_reg(RBP, RBP_H, | |
| 409 RDI, RDI_H, | |
| 410 RSI, RSI_H, | |
| 411 RAX, RAX_H, | |
| 412 RDX, RDX_H, | |
| 413 RBX, RBX_H, | |
| 414 R8, R8_H, | |
| 415 R9, R9_H, | |
| 416 R10, R10_H, | |
| 417 R11, R11_H, | |
| 418 R13, R13_H, | |
| 419 R14, R14_H); | |
| 420 | |
| 421 // Class for all long registers except RAX (and RSP) | |
| 422 reg_class long_no_rax_reg(RBP, RBP_H, | |
| 423 RDX, RDX_H, | |
| 424 RDI, RDI_H, | |
| 425 RSI, RSI_H, | |
| 426 RCX, RCX_H, | |
| 427 RBX, RBX_H, | |
| 428 R8, R8_H, | |
| 429 R9, R9_H, | |
| 430 R10, R10_H, | |
| 431 R11, R11_H, | |
| 432 R13, R13_H, | |
| 433 R14, R14_H); | |
| 434 | |
| 435 // Singleton class for RAX long register | |
| 436 reg_class long_rax_reg(RAX, RAX_H); | |
| 437 | |
| 438 // Singleton class for RCX long register | |
| 439 reg_class long_rcx_reg(RCX, RCX_H); | |
| 440 | |
| 441 // Singleton class for RDX long register | |
| 442 reg_class long_rdx_reg(RDX, RDX_H); | |
| 443 | |
| 444 // Class for all int registers (except RSP) | |
| 445 reg_class int_reg(RAX, | |
| 446 RDX, | |
| 447 RBP, | |
| 448 RDI, | |
| 449 RSI, | |
| 450 RCX, | |
| 451 RBX, | |
| 452 R8, | |
| 453 R9, | |
| 454 R10, | |
| 455 R11, | |
| 456 R13, | |
| 457 R14); | |
| 458 | |
| 459 // Class for all int registers except RCX (and RSP) | |
| 460 reg_class int_no_rcx_reg(RAX, | |
| 461 RDX, | |
| 462 RBP, | |
| 463 RDI, | |
| 464 RSI, | |
| 465 RBX, | |
| 466 R8, | |
| 467 R9, | |
| 468 R10, | |
| 469 R11, | |
| 470 R13, | |
| 471 R14); | |
| 472 | |
| 473 // Class for all int registers except RAX, RDX (and RSP) | |
| 474 reg_class int_no_rax_rdx_reg(RBP, | |
| 304 | 475 RDI, |
| 0 | 476 RSI, |
| 477 RCX, | |
| 478 RBX, | |
| 479 R8, | |
| 480 R9, | |
| 481 R10, | |
| 482 R11, | |
| 483 R13, | |
| 484 R14); | |
| 485 | |
| 486 // Singleton class for RAX int register | |
| 487 reg_class int_rax_reg(RAX); | |
| 488 | |
| 489 // Singleton class for RBX int register | |
| 490 reg_class int_rbx_reg(RBX); | |
| 491 | |
| 492 // Singleton class for RCX int register | |
| 493 reg_class int_rcx_reg(RCX); | |
| 494 | |
| 495 // Singleton class for RCX int register | |
| 496 reg_class int_rdx_reg(RDX); | |
| 497 | |
| 498 // Singleton class for RCX int register | |
| 499 reg_class int_rdi_reg(RDI); | |
| 500 | |
| 501 // Singleton class for instruction pointer | |
| 502 // reg_class ip_reg(RIP); | |
| 503 | |
| 504 // Singleton class for condition codes | |
| 505 reg_class int_flags(RFLAGS); | |
| 506 | |
| 507 // Class for all float registers | |
| 508 reg_class float_reg(XMM0, | |
| 509 XMM1, | |
| 510 XMM2, | |
| 511 XMM3, | |
| 512 XMM4, | |
| 513 XMM5, | |
| 514 XMM6, | |
| 515 XMM7, | |
| 516 XMM8, | |
| 517 XMM9, | |
| 518 XMM10, | |
| 519 XMM11, | |
| 520 XMM12, | |
| 521 XMM13, | |
| 522 XMM14, | |
| 523 XMM15); | |
| 524 | |
| 525 // Class for all double registers | |
| 526 reg_class double_reg(XMM0, XMM0_H, | |
| 527 XMM1, XMM1_H, | |
| 528 XMM2, XMM2_H, | |
| 529 XMM3, XMM3_H, | |
| 530 XMM4, XMM4_H, | |
| 531 XMM5, XMM5_H, | |
| 532 XMM6, XMM6_H, | |
| 533 XMM7, XMM7_H, | |
| 534 XMM8, XMM8_H, | |
| 535 XMM9, XMM9_H, | |
| 536 XMM10, XMM10_H, | |
| 537 XMM11, XMM11_H, | |
| 538 XMM12, XMM12_H, | |
| 539 XMM13, XMM13_H, | |
| 540 XMM14, XMM14_H, | |
| 541 XMM15, XMM15_H); | |
| 542 %} | |
| 543 | |
| 544 | |
| 545 //----------SOURCE BLOCK------------------------------------------------------- | |
| 546 // This is a block of C++ code which provides values, functions, and | |
| 547 // definitions necessary in the rest of the architecture description | |
| 548 source %{ | |
| 304 | 549 #define RELOC_IMM64 Assembler::imm_operand |
| 0 | 550 #define RELOC_DISP32 Assembler::disp32_operand |
| 551 | |
| 552 #define __ _masm. | |
| 553 | |
|
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554 static int preserve_SP_size() { |
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555 return LP64_ONLY(1 +) 2; // [rex,] op, rm(reg/reg) |
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556 } |
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557 |
| 0 | 558 // !!!!! Special hack to get all types of calls to specify the byte offset |
| 559 // from the start of the call to the point where the return address | |
| 560 // will point. | |
| 561 int MachCallStaticJavaNode::ret_addr_offset() | |
| 562 { | |
|
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563 int offset = 5; // 5 bytes from start of call to where return address points |
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564 if (_method_handle_invoke) |
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565 offset += preserve_SP_size(); |
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566 return offset; |
| 0 | 567 } |
| 568 | |
| 569 int MachCallDynamicJavaNode::ret_addr_offset() | |
| 570 { | |
| 571 return 15; // 15 bytes from start of call to where return address points | |
| 572 } | |
| 573 | |
| 574 // In os_cpu .ad file | |
| 575 // int MachCallRuntimeNode::ret_addr_offset() | |
| 576 | |
| 577 // Indicate if the safepoint node needs the polling page as an input. | |
| 578 // Since amd64 does not have absolute addressing but RIP-relative | |
| 579 // addressing and the polling page is within 2G, it doesn't. | |
| 580 bool SafePointNode::needs_polling_address_input() | |
| 581 { | |
| 582 return false; | |
| 583 } | |
| 584 | |
| 585 // | |
| 586 // Compute padding required for nodes which need alignment | |
| 587 // | |
| 588 | |
| 589 // The address of the call instruction needs to be 4-byte aligned to | |
| 590 // ensure that it does not span a cache line so that it can be patched. | |
| 591 int CallStaticJavaDirectNode::compute_padding(int current_offset) const | |
| 592 { | |
| 593 current_offset += 1; // skip call opcode byte | |
| 594 return round_to(current_offset, alignment_required()) - current_offset; | |
| 595 } | |
| 596 | |
| 597 // The address of the call instruction needs to be 4-byte aligned to | |
| 598 // ensure that it does not span a cache line so that it can be patched. | |
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599 int CallStaticJavaHandleNode::compute_padding(int current_offset) const |
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600 { |
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601 current_offset += preserve_SP_size(); // skip mov rbp, rsp |
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602 current_offset += 1; // skip call opcode byte |
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603 return round_to(current_offset, alignment_required()) - current_offset; |
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604 } |
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605 |
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606 // The address of the call instruction needs to be 4-byte aligned to |
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607 // ensure that it does not span a cache line so that it can be patched. |
| 0 | 608 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const |
| 609 { | |
| 610 current_offset += 11; // skip movq instruction + call opcode byte | |
| 611 return round_to(current_offset, alignment_required()) - current_offset; | |
| 612 } | |
| 613 | |
| 614 #ifndef PRODUCT | |
| 615 void MachBreakpointNode::format(PhaseRegAlloc*, outputStream* st) const | |
| 616 { | |
| 617 st->print("INT3"); | |
| 618 } | |
| 619 #endif | |
| 620 | |
| 621 // EMIT_RM() | |
| 1748 | 622 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) { |
| 0 | 623 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3); |
| 1748 | 624 cbuf.insts()->emit_int8(c); |
| 0 | 625 } |
| 626 | |
| 627 // EMIT_CC() | |
| 1748 | 628 void emit_cc(CodeBuffer &cbuf, int f1, int f2) { |
| 0 | 629 unsigned char c = (unsigned char) (f1 | f2); |
| 1748 | 630 cbuf.insts()->emit_int8(c); |
| 0 | 631 } |
| 632 | |
| 633 // EMIT_OPCODE() | |
| 1748 | 634 void emit_opcode(CodeBuffer &cbuf, int code) { |
| 635 cbuf.insts()->emit_int8((unsigned char) code); | |
| 0 | 636 } |
| 637 | |
| 638 // EMIT_OPCODE() w/ relocation information | |
| 639 void emit_opcode(CodeBuffer &cbuf, | |
| 640 int code, relocInfo::relocType reloc, int offset, int format) | |
| 641 { | |
| 1748 | 642 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format); |
| 0 | 643 emit_opcode(cbuf, code); |
| 644 } | |
| 645 | |
| 646 // EMIT_D8() | |
| 1748 | 647 void emit_d8(CodeBuffer &cbuf, int d8) { |
| 648 cbuf.insts()->emit_int8((unsigned char) d8); | |
| 0 | 649 } |
| 650 | |
| 651 // EMIT_D16() | |
| 1748 | 652 void emit_d16(CodeBuffer &cbuf, int d16) { |
| 653 cbuf.insts()->emit_int16(d16); | |
| 0 | 654 } |
| 655 | |
| 656 // EMIT_D32() | |
| 1748 | 657 void emit_d32(CodeBuffer &cbuf, int d32) { |
| 658 cbuf.insts()->emit_int32(d32); | |
| 0 | 659 } |
| 660 | |
| 661 // EMIT_D64() | |
| 1748 | 662 void emit_d64(CodeBuffer &cbuf, int64_t d64) { |
| 663 cbuf.insts()->emit_int64(d64); | |
| 0 | 664 } |
| 665 | |
| 666 // emit 32 bit value and construct relocation entry from relocInfo::relocType | |
| 667 void emit_d32_reloc(CodeBuffer& cbuf, | |
| 668 int d32, | |
| 669 relocInfo::relocType reloc, | |
| 670 int format) | |
| 671 { | |
| 672 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc"); | |
| 1748 | 673 cbuf.relocate(cbuf.insts_mark(), reloc, format); |
| 674 cbuf.insts()->emit_int32(d32); | |
| 0 | 675 } |
| 676 | |
| 677 // emit 32 bit value and construct relocation entry from RelocationHolder | |
| 1748 | 678 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) { |
| 0 | 679 #ifdef ASSERT |
| 680 if (rspec.reloc()->type() == relocInfo::oop_type && | |
| 681 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) { | |
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682 assert(oop((intptr_t)d32)->is_oop() && (ScavengeRootsInCode || !oop((intptr_t)d32)->is_scavengable()), "cannot embed scavengable oops in code"); |
| 0 | 683 } |
| 684 #endif | |
| 1748 | 685 cbuf.relocate(cbuf.insts_mark(), rspec, format); |
| 686 cbuf.insts()->emit_int32(d32); | |
| 0 | 687 } |
| 688 | |
| 689 void emit_d32_reloc(CodeBuffer& cbuf, address addr) { | |
| 1748 | 690 address next_ip = cbuf.insts_end() + 4; |
| 0 | 691 emit_d32_reloc(cbuf, (int) (addr - next_ip), |
| 692 external_word_Relocation::spec(addr), | |
| 693 RELOC_DISP32); | |
| 694 } | |
| 695 | |
| 696 | |
| 697 // emit 64 bit value and construct relocation entry from relocInfo::relocType | |
| 1748 | 698 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) { |
| 699 cbuf.relocate(cbuf.insts_mark(), reloc, format); | |
| 700 cbuf.insts()->emit_int64(d64); | |
| 0 | 701 } |
| 702 | |
| 703 // emit 64 bit value and construct relocation entry from RelocationHolder | |
| 1748 | 704 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) { |
| 0 | 705 #ifdef ASSERT |
| 706 if (rspec.reloc()->type() == relocInfo::oop_type && | |
| 707 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) { | |
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708 assert(oop(d64)->is_oop() && (ScavengeRootsInCode || !oop(d64)->is_scavengable()), |
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709 "cannot embed scavengable oops in code"); |
| 0 | 710 } |
| 711 #endif | |
| 1748 | 712 cbuf.relocate(cbuf.insts_mark(), rspec, format); |
| 713 cbuf.insts()->emit_int64(d64); | |
| 0 | 714 } |
| 715 | |
| 716 // Access stack slot for load or store | |
| 717 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) | |
| 718 { | |
| 719 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src]) | |
| 720 if (-0x80 <= disp && disp < 0x80) { | |
| 721 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte | |
| 722 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte | |
| 723 emit_d8(cbuf, disp); // Displacement // R/M byte | |
| 724 } else { | |
| 725 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte | |
| 726 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte | |
| 727 emit_d32(cbuf, disp); // Displacement // R/M byte | |
| 728 } | |
| 729 } | |
| 730 | |
| 731 // rRegI ereg, memory mem) %{ // emit_reg_mem | |
| 732 void encode_RegMem(CodeBuffer &cbuf, | |
| 733 int reg, | |
| 734 int base, int index, int scale, int disp, bool disp_is_oop) | |
| 735 { | |
| 736 assert(!disp_is_oop, "cannot have disp"); | |
| 737 int regenc = reg & 7; | |
| 738 int baseenc = base & 7; | |
| 739 int indexenc = index & 7; | |
| 740 | |
| 741 // There is no index & no scale, use form without SIB byte | |
| 742 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) { | |
| 743 // If no displacement, mode is 0x0; unless base is [RBP] or [R13] | |
| 744 if (disp == 0 && base != RBP_enc && base != R13_enc) { | |
| 745 emit_rm(cbuf, 0x0, regenc, baseenc); // * | |
| 746 } else if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) { | |
| 747 // If 8-bit displacement, mode 0x1 | |
| 748 emit_rm(cbuf, 0x1, regenc, baseenc); // * | |
| 749 emit_d8(cbuf, disp); | |
| 750 } else { | |
| 751 // If 32-bit displacement | |
| 752 if (base == -1) { // Special flag for absolute address | |
| 753 emit_rm(cbuf, 0x0, regenc, 0x5); // * | |
| 754 if (disp_is_oop) { | |
| 755 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32); | |
| 756 } else { | |
| 757 emit_d32(cbuf, disp); | |
| 758 } | |
| 759 } else { | |
| 760 // Normal base + offset | |
| 761 emit_rm(cbuf, 0x2, regenc, baseenc); // * | |
| 762 if (disp_is_oop) { | |
| 763 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32); | |
| 764 } else { | |
| 765 emit_d32(cbuf, disp); | |
| 766 } | |
| 767 } | |
| 768 } | |
| 769 } else { | |
| 770 // Else, encode with the SIB byte | |
| 771 // If no displacement, mode is 0x0; unless base is [RBP] or [R13] | |
| 772 if (disp == 0 && base != RBP_enc && base != R13_enc) { | |
| 773 // If no displacement | |
| 774 emit_rm(cbuf, 0x0, regenc, 0x4); // * | |
| 775 emit_rm(cbuf, scale, indexenc, baseenc); | |
| 776 } else { | |
| 777 if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) { | |
| 778 // If 8-bit displacement, mode 0x1 | |
| 779 emit_rm(cbuf, 0x1, regenc, 0x4); // * | |
| 780 emit_rm(cbuf, scale, indexenc, baseenc); | |
| 781 emit_d8(cbuf, disp); | |
| 782 } else { | |
| 783 // If 32-bit displacement | |
| 784 if (base == 0x04 ) { | |
| 785 emit_rm(cbuf, 0x2, regenc, 0x4); | |
| 786 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid??? | |
| 787 } else { | |
| 788 emit_rm(cbuf, 0x2, regenc, 0x4); | |
| 789 emit_rm(cbuf, scale, indexenc, baseenc); // * | |
| 790 } | |
| 791 if (disp_is_oop) { | |
| 792 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32); | |
| 793 } else { | |
| 794 emit_d32(cbuf, disp); | |
| 795 } | |
| 796 } | |
| 797 } | |
| 798 } | |
| 799 } | |
| 800 | |
| 801 void encode_copy(CodeBuffer &cbuf, int dstenc, int srcenc) | |
| 802 { | |
| 803 if (dstenc != srcenc) { | |
| 804 if (dstenc < 8) { | |
| 805 if (srcenc >= 8) { | |
| 806 emit_opcode(cbuf, Assembler::REX_B); | |
| 807 srcenc -= 8; | |
| 808 } | |
| 809 } else { | |
| 810 if (srcenc < 8) { | |
| 811 emit_opcode(cbuf, Assembler::REX_R); | |
| 812 } else { | |
| 813 emit_opcode(cbuf, Assembler::REX_RB); | |
| 814 srcenc -= 8; | |
| 815 } | |
| 816 dstenc -= 8; | |
| 817 } | |
| 818 | |
| 819 emit_opcode(cbuf, 0x8B); | |
| 820 emit_rm(cbuf, 0x3, dstenc, srcenc); | |
| 821 } | |
| 822 } | |
| 823 | |
| 824 void encode_CopyXD( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) { | |
| 825 if( dst_encoding == src_encoding ) { | |
| 826 // reg-reg copy, use an empty encoding | |
| 827 } else { | |
| 828 MacroAssembler _masm(&cbuf); | |
| 829 | |
| 830 __ movdqa(as_XMMRegister(dst_encoding), as_XMMRegister(src_encoding)); | |
| 831 } | |
| 832 } | |
| 833 | |
| 834 | |
| 835 //============================================================================= | |
| 2008 | 836 const bool Matcher::constant_table_absolute_addressing = true; |
| 837 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty; | |
| 838 | |
| 839 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { | |
| 840 // Empty encoding | |
| 841 } | |
| 842 | |
| 843 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const { | |
| 844 return 0; | |
| 845 } | |
| 846 | |
| 847 #ifndef PRODUCT | |
| 848 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { | |
| 849 st->print("# MachConstantBaseNode (empty encoding)"); | |
| 850 } | |
| 851 #endif | |
| 852 | |
| 853 | |
| 854 //============================================================================= | |
| 0 | 855 #ifndef PRODUCT |
| 856 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const | |
| 857 { | |
| 858 Compile* C = ra_->C; | |
| 859 | |
| 860 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 861 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 862 // Remove wordSize for return adr already pushed | |
| 863 // and another for the RBP we are going to save | |
| 864 framesize -= 2*wordSize; | |
| 865 bool need_nop = true; | |
| 866 | |
| 867 // Calls to C2R adapters often do not accept exceptional returns. | |
| 868 // We require that their callers must bang for them. But be | |
| 869 // careful, because some VM calls (such as call site linkage) can | |
| 870 // use several kilobytes of stack. But the stack safety zone should | |
| 871 // account for that. See bugs 4446381, 4468289, 4497237. | |
| 872 if (C->need_stack_bang(framesize)) { | |
| 873 st->print_cr("# stack bang"); st->print("\t"); | |
| 874 need_nop = false; | |
| 875 } | |
| 876 st->print_cr("pushq rbp"); st->print("\t"); | |
| 877 | |
| 878 if (VerifyStackAtCalls) { | |
| 879 // Majik cookie to verify stack depth | |
| 880 st->print_cr("pushq 0xffffffffbadb100d" | |
| 881 "\t# Majik cookie for stack depth check"); | |
| 882 st->print("\t"); | |
| 883 framesize -= wordSize; // Remove 2 for cookie | |
| 884 need_nop = false; | |
| 885 } | |
| 886 | |
| 887 if (framesize) { | |
| 888 st->print("subq rsp, #%d\t# Create frame", framesize); | |
| 889 if (framesize < 0x80 && need_nop) { | |
| 890 st->print("\n\tnop\t# nop for patch_verified_entry"); | |
| 891 } | |
| 892 } | |
| 893 } | |
| 894 #endif | |
| 895 | |
| 896 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const | |
| 897 { | |
| 898 Compile* C = ra_->C; | |
| 899 | |
| 900 // WARNING: Initial instruction MUST be 5 bytes or longer so that | |
| 901 // NativeJump::patch_verified_entry will be able to patch out the entry | |
| 902 // code safely. The fldcw is ok at 6 bytes, the push to verify stack | |
| 903 // depth is ok at 5 bytes, the frame allocation can be either 3 or | |
| 904 // 6 bytes. So if we don't do the fldcw or the push then we must | |
| 905 // use the 6 byte frame allocation even if we have no frame. :-( | |
| 906 // If method sets FPU control word do it now | |
| 907 | |
| 908 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 909 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 910 // Remove wordSize for return adr already pushed | |
| 911 // and another for the RBP we are going to save | |
| 912 framesize -= 2*wordSize; | |
| 913 bool need_nop = true; | |
| 914 | |
| 915 // Calls to C2R adapters often do not accept exceptional returns. | |
| 916 // We require that their callers must bang for them. But be | |
| 917 // careful, because some VM calls (such as call site linkage) can | |
| 918 // use several kilobytes of stack. But the stack safety zone should | |
| 919 // account for that. See bugs 4446381, 4468289, 4497237. | |
| 920 if (C->need_stack_bang(framesize)) { | |
| 921 MacroAssembler masm(&cbuf); | |
| 922 masm.generate_stack_overflow_check(framesize); | |
| 923 need_nop = false; | |
| 924 } | |
| 925 | |
| 926 // We always push rbp so that on return to interpreter rbp will be | |
| 927 // restored correctly and we can correct the stack. | |
| 928 emit_opcode(cbuf, 0x50 | RBP_enc); | |
| 929 | |
| 930 if (VerifyStackAtCalls) { | |
| 931 // Majik cookie to verify stack depth | |
| 932 emit_opcode(cbuf, 0x68); // pushq (sign-extended) 0xbadb100d | |
| 933 emit_d32(cbuf, 0xbadb100d); | |
| 934 framesize -= wordSize; // Remove 2 for cookie | |
| 935 need_nop = false; | |
| 936 } | |
| 937 | |
| 938 if (framesize) { | |
| 939 emit_opcode(cbuf, Assembler::REX_W); | |
| 940 if (framesize < 0x80) { | |
| 941 emit_opcode(cbuf, 0x83); // sub SP,#framesize | |
| 942 emit_rm(cbuf, 0x3, 0x05, RSP_enc); | |
| 943 emit_d8(cbuf, framesize); | |
| 944 if (need_nop) { | |
| 945 emit_opcode(cbuf, 0x90); // nop | |
| 946 } | |
| 947 } else { | |
| 948 emit_opcode(cbuf, 0x81); // sub SP,#framesize | |
| 949 emit_rm(cbuf, 0x3, 0x05, RSP_enc); | |
| 950 emit_d32(cbuf, framesize); | |
| 951 } | |
| 952 } | |
| 953 | |
| 1748 | 954 C->set_frame_complete(cbuf.insts_size()); |
| 0 | 955 |
| 956 #ifdef ASSERT | |
| 957 if (VerifyStackAtCalls) { | |
| 958 Label L; | |
| 959 MacroAssembler masm(&cbuf); | |
| 304 | 960 masm.push(rax); |
| 961 masm.mov(rax, rsp); | |
| 962 masm.andptr(rax, StackAlignmentInBytes-1); | |
| 963 masm.cmpptr(rax, StackAlignmentInBytes-wordSize); | |
| 964 masm.pop(rax); | |
| 0 | 965 masm.jcc(Assembler::equal, L); |
| 966 masm.stop("Stack is not properly aligned!"); | |
| 967 masm.bind(L); | |
| 968 } | |
| 969 #endif | |
| 970 } | |
| 971 | |
| 972 uint MachPrologNode::size(PhaseRegAlloc* ra_) const | |
| 973 { | |
| 974 return MachNode::size(ra_); // too many variables; just compute it | |
| 975 // the hard way | |
| 976 } | |
| 977 | |
| 978 int MachPrologNode::reloc() const | |
| 979 { | |
| 980 return 0; // a large enough number | |
| 981 } | |
| 982 | |
| 983 //============================================================================= | |
| 984 #ifndef PRODUCT | |
| 985 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const | |
| 986 { | |
| 987 Compile* C = ra_->C; | |
| 988 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 989 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 990 // Remove word for return adr already pushed | |
| 991 // and RBP | |
| 992 framesize -= 2*wordSize; | |
| 993 | |
| 994 if (framesize) { | |
| 995 st->print_cr("addq\trsp, %d\t# Destroy frame", framesize); | |
| 996 st->print("\t"); | |
| 997 } | |
| 998 | |
| 999 st->print_cr("popq\trbp"); | |
| 1000 if (do_polling() && C->is_method_compilation()) { | |
| 1001 st->print_cr("\ttestl\trax, [rip + #offset_to_poll_page]\t" | |
| 1002 "# Safepoint: poll for GC"); | |
| 1003 st->print("\t"); | |
| 1004 } | |
| 1005 } | |
| 1006 #endif | |
| 1007 | |
| 1008 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const | |
| 1009 { | |
| 1010 Compile* C = ra_->C; | |
| 1011 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 1012 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 1013 // Remove word for return adr already pushed | |
| 1014 // and RBP | |
| 1015 framesize -= 2*wordSize; | |
| 1016 | |
| 1017 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here | |
| 1018 | |
| 1019 if (framesize) { | |
| 1020 emit_opcode(cbuf, Assembler::REX_W); | |
| 1021 if (framesize < 0x80) { | |
| 1022 emit_opcode(cbuf, 0x83); // addq rsp, #framesize | |
| 1023 emit_rm(cbuf, 0x3, 0x00, RSP_enc); | |
| 1024 emit_d8(cbuf, framesize); | |
| 1025 } else { | |
| 1026 emit_opcode(cbuf, 0x81); // addq rsp, #framesize | |
| 1027 emit_rm(cbuf, 0x3, 0x00, RSP_enc); | |
| 1028 emit_d32(cbuf, framesize); | |
| 1029 } | |
| 1030 } | |
| 1031 | |
| 1032 // popq rbp | |
| 1033 emit_opcode(cbuf, 0x58 | RBP_enc); | |
| 1034 | |
| 1035 if (do_polling() && C->is_method_compilation()) { | |
| 1036 // testl %rax, off(%rip) // Opcode + ModRM + Disp32 == 6 bytes | |
| 1037 // XXX reg_mem doesn't support RIP-relative addressing yet | |
| 1748 | 1038 cbuf.set_insts_mark(); |
| 1039 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_return_type, 0); // XXX | |
| 0 | 1040 emit_opcode(cbuf, 0x85); // testl |
| 1041 emit_rm(cbuf, 0x0, RAX_enc, 0x5); // 00 rax 101 == 0x5 | |
| 1748 | 1042 // cbuf.insts_mark() is beginning of instruction |
| 0 | 1043 emit_d32_reloc(cbuf, os::get_polling_page()); |
| 1044 // relocInfo::poll_return_type, | |
| 1045 } | |
| 1046 } | |
| 1047 | |
| 1048 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const | |
| 1049 { | |
| 1050 Compile* C = ra_->C; | |
| 1051 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 1052 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 1053 // Remove word for return adr already pushed | |
| 1054 // and RBP | |
| 1055 framesize -= 2*wordSize; | |
| 1056 | |
| 1057 uint size = 0; | |
| 1058 | |
| 1059 if (do_polling() && C->is_method_compilation()) { | |
| 1060 size += 6; | |
| 1061 } | |
| 1062 | |
| 1063 // count popq rbp | |
| 1064 size++; | |
| 1065 | |
| 1066 if (framesize) { | |
| 1067 if (framesize < 0x80) { | |
| 1068 size += 4; | |
| 1069 } else if (framesize) { | |
| 1070 size += 7; | |
| 1071 } | |
| 1072 } | |
| 1073 | |
| 1074 return size; | |
| 1075 } | |
| 1076 | |
| 1077 int MachEpilogNode::reloc() const | |
| 1078 { | |
| 1079 return 2; // a large enough number | |
| 1080 } | |
| 1081 | |
| 1082 const Pipeline* MachEpilogNode::pipeline() const | |
| 1083 { | |
| 1084 return MachNode::pipeline_class(); | |
| 1085 } | |
| 1086 | |
| 1087 int MachEpilogNode::safepoint_offset() const | |
| 1088 { | |
| 1089 return 0; | |
| 1090 } | |
| 1091 | |
| 1092 //============================================================================= | |
| 1093 | |
| 1094 enum RC { | |
| 1095 rc_bad, | |
| 1096 rc_int, | |
| 1097 rc_float, | |
| 1098 rc_stack | |
| 1099 }; | |
| 1100 | |
| 1101 static enum RC rc_class(OptoReg::Name reg) | |
| 1102 { | |
| 1103 if( !OptoReg::is_valid(reg) ) return rc_bad; | |
| 1104 | |
| 1105 if (OptoReg::is_stack(reg)) return rc_stack; | |
| 1106 | |
| 1107 VMReg r = OptoReg::as_VMReg(reg); | |
| 1108 | |
| 1109 if (r->is_Register()) return rc_int; | |
| 1110 | |
| 1111 assert(r->is_XMMRegister(), "must be"); | |
| 1112 return rc_float; | |
| 1113 } | |
| 1114 | |
| 1115 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf, | |
| 1116 PhaseRegAlloc* ra_, | |
| 1117 bool do_size, | |
| 1118 outputStream* st) const | |
| 1119 { | |
| 1120 | |
| 1121 // Get registers to move | |
| 1122 OptoReg::Name src_second = ra_->get_reg_second(in(1)); | |
| 1123 OptoReg::Name src_first = ra_->get_reg_first(in(1)); | |
| 1124 OptoReg::Name dst_second = ra_->get_reg_second(this); | |
| 1125 OptoReg::Name dst_first = ra_->get_reg_first(this); | |
| 1126 | |
| 1127 enum RC src_second_rc = rc_class(src_second); | |
| 1128 enum RC src_first_rc = rc_class(src_first); | |
| 1129 enum RC dst_second_rc = rc_class(dst_second); | |
| 1130 enum RC dst_first_rc = rc_class(dst_first); | |
| 1131 | |
| 1132 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), | |
| 1133 "must move at least 1 register" ); | |
| 1134 | |
| 1135 if (src_first == dst_first && src_second == dst_second) { | |
| 1136 // Self copy, no move | |
| 1137 return 0; | |
| 1138 } else if (src_first_rc == rc_stack) { | |
| 1139 // mem -> | |
| 1140 if (dst_first_rc == rc_stack) { | |
| 1141 // mem -> mem | |
| 1142 assert(src_second != dst_first, "overlap"); | |
| 1143 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1144 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1145 // 64-bit | |
| 1146 int src_offset = ra_->reg2offset(src_first); | |
| 1147 int dst_offset = ra_->reg2offset(dst_first); | |
| 1148 if (cbuf) { | |
| 1149 emit_opcode(*cbuf, 0xFF); | |
| 1150 encode_RegMem(*cbuf, RSI_enc, RSP_enc, 0x4, 0, src_offset, false); | |
| 1151 | |
| 1152 emit_opcode(*cbuf, 0x8F); | |
| 1153 encode_RegMem(*cbuf, RAX_enc, RSP_enc, 0x4, 0, dst_offset, false); | |
| 1154 | |
| 1155 #ifndef PRODUCT | |
| 1156 } else if (!do_size) { | |
| 1157 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t" | |
| 1158 "popq [rsp + #%d]", | |
| 1159 src_offset, | |
| 1160 dst_offset); | |
| 1161 #endif | |
| 1162 } | |
| 1163 return | |
| 1164 3 + ((src_offset == 0) ? 0 : (src_offset < 0x80 ? 1 : 4)) + | |
| 1165 3 + ((dst_offset == 0) ? 0 : (dst_offset < 0x80 ? 1 : 4)); | |
| 1166 } else { | |
| 1167 // 32-bit | |
| 1168 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1169 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1170 // No pushl/popl, so: | |
| 1171 int src_offset = ra_->reg2offset(src_first); | |
| 1172 int dst_offset = ra_->reg2offset(dst_first); | |
| 1173 if (cbuf) { | |
| 1174 emit_opcode(*cbuf, Assembler::REX_W); | |
| 1175 emit_opcode(*cbuf, 0x89); | |
| 1176 emit_opcode(*cbuf, 0x44); | |
| 1177 emit_opcode(*cbuf, 0x24); | |
| 1178 emit_opcode(*cbuf, 0xF8); | |
| 1179 | |
| 1180 emit_opcode(*cbuf, 0x8B); | |
| 1181 encode_RegMem(*cbuf, | |
| 1182 RAX_enc, | |
| 1183 RSP_enc, 0x4, 0, src_offset, | |
| 1184 false); | |
| 1185 | |
| 1186 emit_opcode(*cbuf, 0x89); | |
| 1187 encode_RegMem(*cbuf, | |
| 1188 RAX_enc, | |
| 1189 RSP_enc, 0x4, 0, dst_offset, | |
| 1190 false); | |
| 1191 | |
| 1192 emit_opcode(*cbuf, Assembler::REX_W); | |
| 1193 emit_opcode(*cbuf, 0x8B); | |
| 1194 emit_opcode(*cbuf, 0x44); | |
| 1195 emit_opcode(*cbuf, 0x24); | |
| 1196 emit_opcode(*cbuf, 0xF8); | |
| 1197 | |
| 1198 #ifndef PRODUCT | |
| 1199 } else if (!do_size) { | |
| 1200 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t" | |
| 1201 "movl rax, [rsp + #%d]\n\t" | |
| 1202 "movl [rsp + #%d], rax\n\t" | |
| 1203 "movq rax, [rsp - #8]", | |
| 1204 src_offset, | |
| 1205 dst_offset); | |
| 1206 #endif | |
| 1207 } | |
| 1208 return | |
| 1209 5 + // movq | |
| 1210 3 + ((src_offset == 0) ? 0 : (src_offset < 0x80 ? 1 : 4)) + // movl | |
| 1211 3 + ((dst_offset == 0) ? 0 : (dst_offset < 0x80 ? 1 : 4)) + // movl | |
| 1212 5; // movq | |
| 1213 } | |
| 1214 } else if (dst_first_rc == rc_int) { | |
| 1215 // mem -> gpr | |
| 1216 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1217 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1218 // 64-bit | |
| 1219 int offset = ra_->reg2offset(src_first); | |
| 1220 if (cbuf) { | |
| 1221 if (Matcher::_regEncode[dst_first] < 8) { | |
| 1222 emit_opcode(*cbuf, Assembler::REX_W); | |
| 1223 } else { | |
| 1224 emit_opcode(*cbuf, Assembler::REX_WR); | |
| 1225 } | |
| 1226 emit_opcode(*cbuf, 0x8B); | |
| 1227 encode_RegMem(*cbuf, | |
| 1228 Matcher::_regEncode[dst_first], | |
| 1229 RSP_enc, 0x4, 0, offset, | |
| 1230 false); | |
| 1231 #ifndef PRODUCT | |
| 1232 } else if (!do_size) { | |
| 1233 st->print("movq %s, [rsp + #%d]\t# spill", | |
| 1234 Matcher::regName[dst_first], | |
| 1235 offset); | |
| 1236 #endif | |
| 1237 } | |
| 1238 return | |
| 1239 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + 4; // REX | |
| 1240 } else { | |
| 1241 // 32-bit | |
| 1242 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1243 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1244 int offset = ra_->reg2offset(src_first); | |
| 1245 if (cbuf) { | |
| 1246 if (Matcher::_regEncode[dst_first] >= 8) { | |
| 1247 emit_opcode(*cbuf, Assembler::REX_R); | |
| 1248 } | |
| 1249 emit_opcode(*cbuf, 0x8B); | |
| 1250 encode_RegMem(*cbuf, | |
| 1251 Matcher::_regEncode[dst_first], | |
| 1252 RSP_enc, 0x4, 0, offset, | |
| 1253 false); | |
| 1254 #ifndef PRODUCT | |
| 1255 } else if (!do_size) { | |
| 1256 st->print("movl %s, [rsp + #%d]\t# spill", | |
| 1257 Matcher::regName[dst_first], | |
| 1258 offset); | |
| 1259 #endif | |
| 1260 } | |
| 1261 return | |
| 1262 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + | |
| 1263 ((Matcher::_regEncode[dst_first] < 8) | |
| 1264 ? 3 | |
| 1265 : 4); // REX | |
| 1266 } | |
| 1267 } else if (dst_first_rc == rc_float) { | |
| 1268 // mem-> xmm | |
| 1269 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1270 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1271 // 64-bit | |
| 1272 int offset = ra_->reg2offset(src_first); | |
| 1273 if (cbuf) { | |
| 1274 emit_opcode(*cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66); | |
| 1275 if (Matcher::_regEncode[dst_first] >= 8) { | |
| 1276 emit_opcode(*cbuf, Assembler::REX_R); | |
| 1277 } | |
| 1278 emit_opcode(*cbuf, 0x0F); | |
| 1279 emit_opcode(*cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12); | |
| 1280 encode_RegMem(*cbuf, | |
| 1281 Matcher::_regEncode[dst_first], | |
| 1282 RSP_enc, 0x4, 0, offset, | |
| 1283 false); | |
| 1284 #ifndef PRODUCT | |
| 1285 } else if (!do_size) { | |
| 1286 st->print("%s %s, [rsp + #%d]\t# spill", | |
| 1287 UseXmmLoadAndClearUpper ? "movsd " : "movlpd", | |
| 1288 Matcher::regName[dst_first], | |
| 1289 offset); | |
| 1290 #endif | |
| 1291 } | |
| 1292 return | |
| 1293 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + | |
| 1294 ((Matcher::_regEncode[dst_first] < 8) | |
| 1295 ? 5 | |
| 1296 : 6); // REX | |
| 1297 } else { | |
| 1298 // 32-bit | |
| 1299 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1300 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1301 int offset = ra_->reg2offset(src_first); | |
| 1302 if (cbuf) { | |
| 1303 emit_opcode(*cbuf, 0xF3); | |
| 1304 if (Matcher::_regEncode[dst_first] >= 8) { | |
| 1305 emit_opcode(*cbuf, Assembler::REX_R); | |
| 1306 } | |
| 1307 emit_opcode(*cbuf, 0x0F); | |
| 1308 emit_opcode(*cbuf, 0x10); | |
| 1309 encode_RegMem(*cbuf, | |
| 1310 Matcher::_regEncode[dst_first], | |
| 1311 RSP_enc, 0x4, 0, offset, | |
| 1312 false); | |
| 1313 #ifndef PRODUCT | |
| 1314 } else if (!do_size) { | |
| 1315 st->print("movss %s, [rsp + #%d]\t# spill", | |
| 1316 Matcher::regName[dst_first], | |
| 1317 offset); | |
| 1318 #endif | |
| 1319 } | |
| 1320 return | |
| 1321 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + | |
| 1322 ((Matcher::_regEncode[dst_first] < 8) | |
| 1323 ? 5 | |
| 1324 : 6); // REX | |
| 1325 } | |
| 1326 } | |
| 1327 } else if (src_first_rc == rc_int) { | |
| 1328 // gpr -> | |
| 1329 if (dst_first_rc == rc_stack) { | |
| 1330 // gpr -> mem | |
| 1331 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1332 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1333 // 64-bit | |
| 1334 int offset = ra_->reg2offset(dst_first); | |
| 1335 if (cbuf) { | |
| 1336 if (Matcher::_regEncode[src_first] < 8) { | |
| 1337 emit_opcode(*cbuf, Assembler::REX_W); | |
| 1338 } else { | |
| 1339 emit_opcode(*cbuf, Assembler::REX_WR); | |
| 1340 } | |
| 1341 emit_opcode(*cbuf, 0x89); | |
| 1342 encode_RegMem(*cbuf, | |
| 1343 Matcher::_regEncode[src_first], | |
| 1344 RSP_enc, 0x4, 0, offset, | |
| 1345 false); | |
| 1346 #ifndef PRODUCT | |
| 1347 } else if (!do_size) { | |
| 1348 st->print("movq [rsp + #%d], %s\t# spill", | |
| 1349 offset, | |
| 1350 Matcher::regName[src_first]); | |
| 1351 #endif | |
| 1352 } | |
| 1353 return ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + 4; // REX | |
| 1354 } else { | |
| 1355 // 32-bit | |
| 1356 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1357 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1358 int offset = ra_->reg2offset(dst_first); | |
| 1359 if (cbuf) { | |
| 1360 if (Matcher::_regEncode[src_first] >= 8) { | |
| 1361 emit_opcode(*cbuf, Assembler::REX_R); | |
| 1362 } | |
| 1363 emit_opcode(*cbuf, 0x89); | |
| 1364 encode_RegMem(*cbuf, | |
| 1365 Matcher::_regEncode[src_first], | |
| 1366 RSP_enc, 0x4, 0, offset, | |
| 1367 false); | |
| 1368 #ifndef PRODUCT | |
| 1369 } else if (!do_size) { | |
| 1370 st->print("movl [rsp + #%d], %s\t# spill", | |
| 1371 offset, | |
| 1372 Matcher::regName[src_first]); | |
| 1373 #endif | |
| 1374 } | |
| 1375 return | |
| 1376 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + | |
| 1377 ((Matcher::_regEncode[src_first] < 8) | |
| 1378 ? 3 | |
| 1379 : 4); // REX | |
| 1380 } | |
| 1381 } else if (dst_first_rc == rc_int) { | |
| 1382 // gpr -> gpr | |
| 1383 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1384 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1385 // 64-bit | |
| 1386 if (cbuf) { | |
| 1387 if (Matcher::_regEncode[dst_first] < 8) { | |
| 1388 if (Matcher::_regEncode[src_first] < 8) { | |
| 1389 emit_opcode(*cbuf, Assembler::REX_W); | |
| 1390 } else { | |
| 1391 emit_opcode(*cbuf, Assembler::REX_WB); | |
| 1392 } | |
| 1393 } else { | |
| 1394 if (Matcher::_regEncode[src_first] < 8) { | |
| 1395 emit_opcode(*cbuf, Assembler::REX_WR); | |
| 1396 } else { | |
| 1397 emit_opcode(*cbuf, Assembler::REX_WRB); | |
| 1398 } | |
| 1399 } | |
| 1400 emit_opcode(*cbuf, 0x8B); | |
| 1401 emit_rm(*cbuf, 0x3, | |
| 1402 Matcher::_regEncode[dst_first] & 7, | |
| 1403 Matcher::_regEncode[src_first] & 7); | |
| 1404 #ifndef PRODUCT | |
| 1405 } else if (!do_size) { | |
| 1406 st->print("movq %s, %s\t# spill", | |
| 1407 Matcher::regName[dst_first], | |
| 1408 Matcher::regName[src_first]); | |
| 1409 #endif | |
| 1410 } | |
| 1411 return 3; // REX | |
| 1412 } else { | |
| 1413 // 32-bit | |
| 1414 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1415 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1416 if (cbuf) { | |
| 1417 if (Matcher::_regEncode[dst_first] < 8) { | |
| 1418 if (Matcher::_regEncode[src_first] >= 8) { | |
| 1419 emit_opcode(*cbuf, Assembler::REX_B); | |
| 1420 } | |
| 1421 } else { | |
| 1422 if (Matcher::_regEncode[src_first] < 8) { | |
| 1423 emit_opcode(*cbuf, Assembler::REX_R); | |
| 1424 } else { | |
| 1425 emit_opcode(*cbuf, Assembler::REX_RB); | |
| 1426 } | |
| 1427 } | |
| 1428 emit_opcode(*cbuf, 0x8B); | |
| 1429 emit_rm(*cbuf, 0x3, | |
| 1430 Matcher::_regEncode[dst_first] & 7, | |
| 1431 Matcher::_regEncode[src_first] & 7); | |
| 1432 #ifndef PRODUCT | |
| 1433 } else if (!do_size) { | |
| 1434 st->print("movl %s, %s\t# spill", | |
| 1435 Matcher::regName[dst_first], | |
| 1436 Matcher::regName[src_first]); | |
| 1437 #endif | |
| 1438 } | |
| 1439 return | |
| 1440 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8) | |
| 1441 ? 2 | |
| 1442 : 3; // REX | |
| 1443 } | |
| 1444 } else if (dst_first_rc == rc_float) { | |
| 1445 // gpr -> xmm | |
| 1446 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1447 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1448 // 64-bit | |
| 1449 if (cbuf) { | |
| 1450 emit_opcode(*cbuf, 0x66); | |
| 1451 if (Matcher::_regEncode[dst_first] < 8) { | |
| 1452 if (Matcher::_regEncode[src_first] < 8) { | |
| 1453 emit_opcode(*cbuf, Assembler::REX_W); | |
| 1454 } else { | |
| 1455 emit_opcode(*cbuf, Assembler::REX_WB); | |
| 1456 } | |
| 1457 } else { | |
| 1458 if (Matcher::_regEncode[src_first] < 8) { | |
| 1459 emit_opcode(*cbuf, Assembler::REX_WR); | |
| 1460 } else { | |
| 1461 emit_opcode(*cbuf, Assembler::REX_WRB); | |
| 1462 } | |
| 1463 } | |
| 1464 emit_opcode(*cbuf, 0x0F); | |
| 1465 emit_opcode(*cbuf, 0x6E); | |
| 1466 emit_rm(*cbuf, 0x3, | |
| 1467 Matcher::_regEncode[dst_first] & 7, | |
| 1468 Matcher::_regEncode[src_first] & 7); | |
| 1469 #ifndef PRODUCT | |
| 1470 } else if (!do_size) { | |
| 1471 st->print("movdq %s, %s\t# spill", | |
| 1472 Matcher::regName[dst_first], | |
| 1473 Matcher::regName[src_first]); | |
| 1474 #endif | |
| 1475 } | |
| 1476 return 5; // REX | |
| 1477 } else { | |
| 1478 // 32-bit | |
| 1479 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1480 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1481 if (cbuf) { | |
| 1482 emit_opcode(*cbuf, 0x66); | |
| 1483 if (Matcher::_regEncode[dst_first] < 8) { | |
| 1484 if (Matcher::_regEncode[src_first] >= 8) { | |
| 1485 emit_opcode(*cbuf, Assembler::REX_B); | |
| 1486 } | |
| 1487 } else { | |
| 1488 if (Matcher::_regEncode[src_first] < 8) { | |
| 1489 emit_opcode(*cbuf, Assembler::REX_R); | |
| 1490 } else { | |
| 1491 emit_opcode(*cbuf, Assembler::REX_RB); | |
| 1492 } | |
| 1493 } | |
| 1494 emit_opcode(*cbuf, 0x0F); | |
| 1495 emit_opcode(*cbuf, 0x6E); | |
| 1496 emit_rm(*cbuf, 0x3, | |
| 1497 Matcher::_regEncode[dst_first] & 7, | |
| 1498 Matcher::_regEncode[src_first] & 7); | |
| 1499 #ifndef PRODUCT | |
| 1500 } else if (!do_size) { | |
| 1501 st->print("movdl %s, %s\t# spill", | |
| 1502 Matcher::regName[dst_first], | |
| 1503 Matcher::regName[src_first]); | |
| 1504 #endif | |
| 1505 } | |
| 1506 return | |
| 1507 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8) | |
| 1508 ? 4 | |
| 1509 : 5; // REX | |
| 1510 } | |
| 1511 } | |
| 1512 } else if (src_first_rc == rc_float) { | |
| 1513 // xmm -> | |
| 1514 if (dst_first_rc == rc_stack) { | |
| 1515 // xmm -> mem | |
| 1516 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1517 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1518 // 64-bit | |
| 1519 int offset = ra_->reg2offset(dst_first); | |
| 1520 if (cbuf) { | |
| 1521 emit_opcode(*cbuf, 0xF2); | |
| 1522 if (Matcher::_regEncode[src_first] >= 8) { | |
| 1523 emit_opcode(*cbuf, Assembler::REX_R); | |
| 1524 } | |
| 1525 emit_opcode(*cbuf, 0x0F); | |
| 1526 emit_opcode(*cbuf, 0x11); | |
| 1527 encode_RegMem(*cbuf, | |
| 1528 Matcher::_regEncode[src_first], | |
| 1529 RSP_enc, 0x4, 0, offset, | |
| 1530 false); | |
| 1531 #ifndef PRODUCT | |
| 1532 } else if (!do_size) { | |
| 1533 st->print("movsd [rsp + #%d], %s\t# spill", | |
| 1534 offset, | |
| 1535 Matcher::regName[src_first]); | |
| 1536 #endif | |
| 1537 } | |
| 1538 return | |
| 1539 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + | |
| 1540 ((Matcher::_regEncode[src_first] < 8) | |
| 1541 ? 5 | |
| 1542 : 6); // REX | |
| 1543 } else { | |
| 1544 // 32-bit | |
| 1545 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1546 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1547 int offset = ra_->reg2offset(dst_first); | |
| 1548 if (cbuf) { | |
| 1549 emit_opcode(*cbuf, 0xF3); | |
| 1550 if (Matcher::_regEncode[src_first] >= 8) { | |
| 1551 emit_opcode(*cbuf, Assembler::REX_R); | |
| 1552 } | |
| 1553 emit_opcode(*cbuf, 0x0F); | |
| 1554 emit_opcode(*cbuf, 0x11); | |
| 1555 encode_RegMem(*cbuf, | |
| 1556 Matcher::_regEncode[src_first], | |
| 1557 RSP_enc, 0x4, 0, offset, | |
| 1558 false); | |
| 1559 #ifndef PRODUCT | |
| 1560 } else if (!do_size) { | |
| 1561 st->print("movss [rsp + #%d], %s\t# spill", | |
| 1562 offset, | |
| 1563 Matcher::regName[src_first]); | |
| 1564 #endif | |
| 1565 } | |
| 1566 return | |
| 1567 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + | |
| 1568 ((Matcher::_regEncode[src_first] < 8) | |
| 1569 ? 5 | |
| 1570 : 6); // REX | |
| 1571 } | |
| 1572 } else if (dst_first_rc == rc_int) { | |
| 1573 // xmm -> gpr | |
| 1574 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1575 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1576 // 64-bit | |
| 1577 if (cbuf) { | |
| 1578 emit_opcode(*cbuf, 0x66); | |
| 1579 if (Matcher::_regEncode[dst_first] < 8) { | |
| 1580 if (Matcher::_regEncode[src_first] < 8) { | |
| 1581 emit_opcode(*cbuf, Assembler::REX_W); | |
| 1582 } else { | |
| 1583 emit_opcode(*cbuf, Assembler::REX_WR); // attention! | |
| 1584 } | |
| 1585 } else { | |
| 1586 if (Matcher::_regEncode[src_first] < 8) { | |
| 1587 emit_opcode(*cbuf, Assembler::REX_WB); // attention! | |
| 1588 } else { | |
| 1589 emit_opcode(*cbuf, Assembler::REX_WRB); | |
| 1590 } | |
| 1591 } | |
| 1592 emit_opcode(*cbuf, 0x0F); | |
| 1593 emit_opcode(*cbuf, 0x7E); | |
| 1594 emit_rm(*cbuf, 0x3, | |
|
1730
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1595 Matcher::_regEncode[src_first] & 7, |
|
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|
1596 Matcher::_regEncode[dst_first] & 7); |
| 0 | 1597 #ifndef PRODUCT |
| 1598 } else if (!do_size) { | |
| 1599 st->print("movdq %s, %s\t# spill", | |
| 1600 Matcher::regName[dst_first], | |
| 1601 Matcher::regName[src_first]); | |
| 1602 #endif | |
| 1603 } | |
| 1604 return 5; // REX | |
| 1605 } else { | |
| 1606 // 32-bit | |
| 1607 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1608 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1609 if (cbuf) { | |
| 1610 emit_opcode(*cbuf, 0x66); | |
| 1611 if (Matcher::_regEncode[dst_first] < 8) { | |
| 1612 if (Matcher::_regEncode[src_first] >= 8) { | |
| 1613 emit_opcode(*cbuf, Assembler::REX_R); // attention! | |
| 1614 } | |
| 1615 } else { | |
| 1616 if (Matcher::_regEncode[src_first] < 8) { | |
| 1617 emit_opcode(*cbuf, Assembler::REX_B); // attention! | |
| 1618 } else { | |
| 1619 emit_opcode(*cbuf, Assembler::REX_RB); | |
| 1620 } | |
| 1621 } | |
| 1622 emit_opcode(*cbuf, 0x0F); | |
| 1623 emit_opcode(*cbuf, 0x7E); | |
| 1624 emit_rm(*cbuf, 0x3, | |
|
1730
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1625 Matcher::_regEncode[src_first] & 7, |
|
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|
1626 Matcher::_regEncode[dst_first] & 7); |
| 0 | 1627 #ifndef PRODUCT |
| 1628 } else if (!do_size) { | |
| 1629 st->print("movdl %s, %s\t# spill", | |
| 1630 Matcher::regName[dst_first], | |
| 1631 Matcher::regName[src_first]); | |
| 1632 #endif | |
| 1633 } | |
| 1634 return | |
| 1635 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8) | |
| 1636 ? 4 | |
| 1637 : 5; // REX | |
| 1638 } | |
| 1639 } else if (dst_first_rc == rc_float) { | |
| 1640 // xmm -> xmm | |
| 1641 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1642 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1643 // 64-bit | |
| 1644 if (cbuf) { | |
| 1645 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x66 : 0xF2); | |
| 1646 if (Matcher::_regEncode[dst_first] < 8) { | |
| 1647 if (Matcher::_regEncode[src_first] >= 8) { | |
| 1648 emit_opcode(*cbuf, Assembler::REX_B); | |
| 1649 } | |
| 1650 } else { | |
| 1651 if (Matcher::_regEncode[src_first] < 8) { | |
| 1652 emit_opcode(*cbuf, Assembler::REX_R); | |
| 1653 } else { | |
| 1654 emit_opcode(*cbuf, Assembler::REX_RB); | |
| 1655 } | |
| 1656 } | |
| 1657 emit_opcode(*cbuf, 0x0F); | |
| 1658 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10); | |
| 1659 emit_rm(*cbuf, 0x3, | |
| 1660 Matcher::_regEncode[dst_first] & 7, | |
| 1661 Matcher::_regEncode[src_first] & 7); | |
| 1662 #ifndef PRODUCT | |
| 1663 } else if (!do_size) { | |
| 1664 st->print("%s %s, %s\t# spill", | |
| 1665 UseXmmRegToRegMoveAll ? "movapd" : "movsd ", | |
| 1666 Matcher::regName[dst_first], | |
| 1667 Matcher::regName[src_first]); | |
| 1668 #endif | |
| 1669 } | |
| 1670 return | |
| 1671 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8) | |
| 1672 ? 4 | |
| 1673 : 5; // REX | |
| 1674 } else { | |
| 1675 // 32-bit | |
| 1676 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1677 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1678 if (cbuf) { | |
| 1679 if (!UseXmmRegToRegMoveAll) | |
| 1680 emit_opcode(*cbuf, 0xF3); | |
| 1681 if (Matcher::_regEncode[dst_first] < 8) { | |
| 1682 if (Matcher::_regEncode[src_first] >= 8) { | |
| 1683 emit_opcode(*cbuf, Assembler::REX_B); | |
| 1684 } | |
| 1685 } else { | |
| 1686 if (Matcher::_regEncode[src_first] < 8) { | |
| 1687 emit_opcode(*cbuf, Assembler::REX_R); | |
| 1688 } else { | |
| 1689 emit_opcode(*cbuf, Assembler::REX_RB); | |
| 1690 } | |
| 1691 } | |
| 1692 emit_opcode(*cbuf, 0x0F); | |
| 1693 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10); | |
| 1694 emit_rm(*cbuf, 0x3, | |
| 1695 Matcher::_regEncode[dst_first] & 7, | |
| 1696 Matcher::_regEncode[src_first] & 7); | |
| 1697 #ifndef PRODUCT | |
| 1698 } else if (!do_size) { | |
| 1699 st->print("%s %s, %s\t# spill", | |
| 1700 UseXmmRegToRegMoveAll ? "movaps" : "movss ", | |
| 1701 Matcher::regName[dst_first], | |
| 1702 Matcher::regName[src_first]); | |
| 1703 #endif | |
| 1704 } | |
| 1705 return | |
| 1706 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8) | |
| 1707 ? (UseXmmRegToRegMoveAll ? 3 : 4) | |
| 1708 : (UseXmmRegToRegMoveAll ? 4 : 5); // REX | |
| 1709 } | |
| 1710 } | |
| 1711 } | |
| 1712 | |
| 1713 assert(0," foo "); | |
| 1714 Unimplemented(); | |
| 1715 | |
| 1716 return 0; | |
| 1717 } | |
| 1718 | |
| 1719 #ifndef PRODUCT | |
| 1720 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const | |
| 1721 { | |
| 1722 implementation(NULL, ra_, false, st); | |
| 1723 } | |
| 1724 #endif | |
| 1725 | |
| 1726 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const | |
| 1727 { | |
| 1728 implementation(&cbuf, ra_, false, NULL); | |
| 1729 } | |
| 1730 | |
| 1731 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const | |
| 1732 { | |
| 1733 return implementation(NULL, ra_, true, NULL); | |
| 1734 } | |
| 1735 | |
| 1736 //============================================================================= | |
| 1737 #ifndef PRODUCT | |
| 1738 void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const | |
| 1739 { | |
| 1740 st->print("nop \t# %d bytes pad for loops and calls", _count); | |
| 1741 } | |
| 1742 #endif | |
| 1743 | |
| 1744 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const | |
| 1745 { | |
| 1746 MacroAssembler _masm(&cbuf); | |
| 1747 __ nop(_count); | |
| 1748 } | |
| 1749 | |
| 1750 uint MachNopNode::size(PhaseRegAlloc*) const | |
| 1751 { | |
| 1752 return _count; | |
| 1753 } | |
| 1754 | |
| 1755 | |
| 1756 //============================================================================= | |
| 1757 #ifndef PRODUCT | |
| 1758 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const | |
| 1759 { | |
| 1760 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1761 int reg = ra_->get_reg_first(this); | |
| 1762 st->print("leaq %s, [rsp + #%d]\t# box lock", | |
| 1763 Matcher::regName[reg], offset); | |
| 1764 } | |
| 1765 #endif | |
| 1766 | |
| 1767 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const | |
| 1768 { | |
| 1769 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1770 int reg = ra_->get_encode(this); | |
| 1771 if (offset >= 0x80) { | |
| 1772 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR); | |
| 1773 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1774 emit_rm(cbuf, 0x2, reg & 7, 0x04); | |
| 1775 emit_rm(cbuf, 0x0, 0x04, RSP_enc); | |
| 1776 emit_d32(cbuf, offset); | |
| 1777 } else { | |
| 1778 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR); | |
| 1779 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1780 emit_rm(cbuf, 0x1, reg & 7, 0x04); | |
| 1781 emit_rm(cbuf, 0x0, 0x04, RSP_enc); | |
| 1782 emit_d8(cbuf, offset); | |
| 1783 } | |
| 1784 } | |
| 1785 | |
| 1786 uint BoxLockNode::size(PhaseRegAlloc *ra_) const | |
| 1787 { | |
| 1788 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1789 return (offset < 0x80) ? 5 : 8; // REX | |
| 1790 } | |
| 1791 | |
| 1792 //============================================================================= | |
| 1793 | |
| 1794 // emit call stub, compiled java to interpreter | |
| 1795 void emit_java_to_interp(CodeBuffer& cbuf) | |
| 1796 { | |
| 1797 // Stub is fixed up when the corresponding call is converted from | |
| 1798 // calling compiled code to calling interpreted code. | |
| 1799 // movq rbx, 0 | |
| 1800 // jmp -5 # to self | |
| 1801 | |
| 1748 | 1802 address mark = cbuf.insts_mark(); // get mark within main instrs section |
| 1803 | |
| 1804 // Note that the code buffer's insts_mark is always relative to insts. | |
| 0 | 1805 // That's why we must use the macroassembler to generate a stub. |
| 1806 MacroAssembler _masm(&cbuf); | |
| 1807 | |
| 1808 address base = | |
| 1809 __ start_a_stub(Compile::MAX_stubs_size); | |
| 1810 if (base == NULL) return; // CodeBuffer::expand failed | |
| 1811 // static stub relocation stores the instruction address of the call | |
| 1812 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM64); | |
| 1813 // static stub relocation also tags the methodOop in the code-stream. | |
| 1814 __ movoop(rbx, (jobject) NULL); // method is zapped till fixup time | |
| 304 | 1815 // This is recognized as unresolved by relocs/nativeinst/ic code |
| 0 | 1816 __ jump(RuntimeAddress(__ pc())); |
| 1817 | |
| 1748 | 1818 // Update current stubs pointer and restore insts_end. |
| 0 | 1819 __ end_a_stub(); |
| 1820 } | |
| 1821 | |
| 1822 // size of call stub, compiled java to interpretor | |
| 1823 uint size_java_to_interp() | |
| 1824 { | |
| 1825 return 15; // movq (1+1+8); jmp (1+4) | |
| 1826 } | |
| 1827 | |
| 1828 // relocation entries for call stub, compiled java to interpretor | |
| 1829 uint reloc_java_to_interp() | |
| 1830 { | |
| 1831 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call | |
| 1832 } | |
| 1833 | |
| 1834 //============================================================================= | |
| 1835 #ifndef PRODUCT | |
| 1836 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const | |
| 1837 { | |
|
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1838 if (UseCompressedOops) { |
|
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1839 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass"); |
|
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1840 if (Universe::narrow_oop_shift() != 0) { |
|
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1841 st->print_cr("\tdecode_heap_oop_not_null rscratch1, rscratch1"); |
|
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1842 } |
|
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1843 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check"); |
|
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1844 } else { |
|
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1845 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t" |
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1846 "# Inline cache check"); |
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1847 } |
| 0 | 1848 st->print_cr("\tjne SharedRuntime::_ic_miss_stub"); |
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1849 st->print_cr("\tnop\t# nops to align entry point"); |
| 0 | 1850 } |
| 1851 #endif | |
| 1852 | |
| 1853 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const | |
| 1854 { | |
| 1855 MacroAssembler masm(&cbuf); | |
| 1748 | 1856 uint insts_size = cbuf.insts_size(); |
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1857 if (UseCompressedOops) { |
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1858 masm.load_klass(rscratch1, j_rarg0); |
| 304 | 1859 masm.cmpptr(rax, rscratch1); |
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1860 } else { |
| 304 | 1861 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes())); |
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1862 } |
| 0 | 1863 |
| 1864 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub())); | |
| 1865 | |
| 1866 /* WARNING these NOPs are critical so that verified entry point is properly | |
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1867 4 bytes aligned for patching by NativeJump::patch_verified_entry() */ |
| 1748 | 1868 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3); |
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1869 if (OptoBreakpoint) { |
| 0 | 1870 // Leave space for int3 |
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1871 nops_cnt -= 1; |
| 0 | 1872 } |
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1873 nops_cnt &= 0x3; // Do not add nops if code is aligned. |
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1874 if (nops_cnt > 0) |
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1875 masm.nop(nops_cnt); |
| 0 | 1876 } |
| 1877 | |
| 1878 uint MachUEPNode::size(PhaseRegAlloc* ra_) const | |
| 1879 { | |
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1880 return MachNode::size(ra_); // too many variables; just compute it |
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1881 // the hard way |
| 0 | 1882 } |
| 1883 | |
| 1884 | |
| 1885 //============================================================================= | |
| 1886 uint size_exception_handler() | |
| 1887 { | |
| 1888 // NativeCall instruction size is the same as NativeJump. | |
| 1889 // Note that this value is also credited (in output.cpp) to | |
| 1890 // the size of the code section. | |
| 1891 return NativeJump::instruction_size; | |
| 1892 } | |
| 1893 | |
| 1894 // Emit exception handler code. | |
| 1895 int emit_exception_handler(CodeBuffer& cbuf) | |
| 1896 { | |
| 1897 | |
| 1748 | 1898 // Note that the code buffer's insts_mark is always relative to insts. |
| 0 | 1899 // That's why we must use the macroassembler to generate a handler. |
| 1900 MacroAssembler _masm(&cbuf); | |
| 1901 address base = | |
| 1902 __ start_a_stub(size_exception_handler()); | |
| 1903 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1904 int offset = __ offset(); | |
| 1748 | 1905 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point())); |
| 0 | 1906 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); |
| 1907 __ end_a_stub(); | |
| 1908 return offset; | |
| 1909 } | |
| 1910 | |
| 1911 uint size_deopt_handler() | |
| 1912 { | |
| 1913 // three 5 byte instructions | |
| 1914 return 15; | |
| 1915 } | |
| 1916 | |
| 1917 // Emit deopt handler code. | |
| 1918 int emit_deopt_handler(CodeBuffer& cbuf) | |
| 1919 { | |
| 1920 | |
| 1748 | 1921 // Note that the code buffer's insts_mark is always relative to insts. |
| 0 | 1922 // That's why we must use the macroassembler to generate a handler. |
| 1923 MacroAssembler _masm(&cbuf); | |
| 1924 address base = | |
| 1925 __ start_a_stub(size_deopt_handler()); | |
| 1926 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1927 int offset = __ offset(); | |
| 1928 address the_pc = (address) __ pc(); | |
| 1929 Label next; | |
| 1930 // push a "the_pc" on the stack without destroying any registers | |
| 1931 // as they all may be live. | |
| 1932 | |
| 1933 // push address of "next" | |
| 1934 __ call(next, relocInfo::none); // reloc none is fine since it is a disp32 | |
| 1935 __ bind(next); | |
| 1936 // adjust it so it matches "the_pc" | |
| 304 | 1937 __ subptr(Address(rsp, 0), __ offset() - offset); |
| 0 | 1938 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); |
| 1939 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); | |
| 1940 __ end_a_stub(); | |
| 1941 return offset; | |
| 1942 } | |
| 1943 | |
| 1944 | |
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1945 const bool Matcher::match_rule_supported(int opcode) { |
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1946 if (!has_match_rule(opcode)) |
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1947 return false; |
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1948 |
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1949 return true; // Per default match rules are supported. |
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1950 } |
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1951 |
| 0 | 1952 int Matcher::regnum_to_fpu_offset(int regnum) |
| 1953 { | |
| 1954 return regnum - 32; // The FP registers are in the second chunk | |
| 1955 } | |
| 1956 | |
| 1957 // This is UltraSparc specific, true just means we have fast l2f conversion | |
| 1958 const bool Matcher::convL2FSupported(void) { | |
| 1959 return true; | |
| 1960 } | |
| 1961 | |
| 1962 // Vector width in bytes | |
| 1963 const uint Matcher::vector_width_in_bytes(void) { | |
| 1964 return 8; | |
| 1965 } | |
| 1966 | |
| 1967 // Vector ideal reg | |
| 1968 const uint Matcher::vector_ideal_reg(void) { | |
| 1969 return Op_RegD; | |
| 1970 } | |
| 1971 | |
| 1972 // Is this branch offset short enough that a short branch can be used? | |
| 1973 // | |
| 1974 // NOTE: If the platform does not provide any short branch variants, then | |
| 1975 // this method should return false for offset 0. | |
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1976 bool Matcher::is_short_branch_offset(int rule, int offset) { |
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1977 // the short version of jmpConUCF2 contains multiple branches, |
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1978 // making the reach slightly less |
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1979 if (rule == jmpConUCF2_rule) |
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1980 return (-126 <= offset && offset <= 125); |
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1981 return (-128 <= offset && offset <= 127); |
| 0 | 1982 } |
| 1983 | |
| 1984 const bool Matcher::isSimpleConstant64(jlong value) { | |
| 1985 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. | |
| 1986 //return value == (int) value; // Cf. storeImmL and immL32. | |
| 1987 | |
| 1988 // Probably always true, even if a temp register is required. | |
| 1989 return true; | |
| 1990 } | |
| 1991 | |
| 1992 // The ecx parameter to rep stosq for the ClearArray node is in words. | |
| 1993 const bool Matcher::init_array_count_is_in_bytes = false; | |
| 1994 | |
| 1995 // Threshold size for cleararray. | |
| 1996 const int Matcher::init_array_short_size = 8 * BytesPerLong; | |
| 1997 | |
| 1998 // Should the Matcher clone shifts on addressing modes, expecting them | |
| 1999 // to be subsumed into complex addressing expressions or compute them | |
| 2000 // into registers? True for Intel but false for most RISCs | |
| 2001 const bool Matcher::clone_shift_expressions = true; | |
| 2002 | |
|
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2003 // Do we need to mask the count passed to shift instructions or does |
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2004 // the cpu only look at the lower 5/6 bits anyway? |
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2005 const bool Matcher::need_masked_shift_count = false; |
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2006 |
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2007 bool Matcher::narrow_oop_use_complex_address() { |
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2008 assert(UseCompressedOops, "only for compressed oops code"); |
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2009 return (LogMinObjAlignmentInBytes <= 3); |
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2010 } |
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2011 |
| 0 | 2012 // Is it better to copy float constants, or load them directly from |
| 2013 // memory? Intel can load a float constant from a direct address, | |
| 2014 // requiring no extra registers. Most RISCs will have to materialize | |
| 2015 // an address into a register first, so they would do better to copy | |
| 2016 // the constant from stack. | |
| 2017 const bool Matcher::rematerialize_float_constants = true; // XXX | |
| 2018 | |
| 2019 // If CPU can load and store mis-aligned doubles directly then no | |
| 2020 // fixup is needed. Else we split the double into 2 integer pieces | |
| 2021 // and move it piece-by-piece. Only happens when passing doubles into | |
| 2022 // C code as the Java calling convention forces doubles to be aligned. | |
| 2023 const bool Matcher::misaligned_doubles_ok = true; | |
| 2024 | |
| 2025 // No-op on amd64 | |
| 2026 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {} | |
| 2027 | |
| 2028 // Advertise here if the CPU requires explicit rounding operations to | |
| 2029 // implement the UseStrictFP mode. | |
| 2030 const bool Matcher::strict_fp_requires_explicit_rounding = true; | |
| 2031 | |
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2032 // Are floats conerted to double when stored to stack during deoptimization? |
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2033 // On x64 it is stored without convertion so we can use normal access. |
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2034 bool Matcher::float_in_double() { return false; } |
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2035 |
| 0 | 2036 // Do ints take an entire long register or just half? |
| 2037 const bool Matcher::int_in_long = true; | |
| 2038 | |
| 2039 // Return whether or not this register is ever used as an argument. | |
| 2040 // This function is used on startup to build the trampoline stubs in | |
| 2041 // generateOptoStub. Registers not mentioned will be killed by the VM | |
| 2042 // call in the trampoline, and arguments in those registers not be | |
| 2043 // available to the callee. | |
| 2044 bool Matcher::can_be_java_arg(int reg) | |
| 2045 { | |
| 2046 return | |
| 2047 reg == RDI_num || reg == RDI_H_num || | |
| 2048 reg == RSI_num || reg == RSI_H_num || | |
| 2049 reg == RDX_num || reg == RDX_H_num || | |
| 2050 reg == RCX_num || reg == RCX_H_num || | |
| 2051 reg == R8_num || reg == R8_H_num || | |
| 2052 reg == R9_num || reg == R9_H_num || | |
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2053 reg == R12_num || reg == R12_H_num || |
| 0 | 2054 reg == XMM0_num || reg == XMM0_H_num || |
| 2055 reg == XMM1_num || reg == XMM1_H_num || | |
| 2056 reg == XMM2_num || reg == XMM2_H_num || | |
| 2057 reg == XMM3_num || reg == XMM3_H_num || | |
| 2058 reg == XMM4_num || reg == XMM4_H_num || | |
| 2059 reg == XMM5_num || reg == XMM5_H_num || | |
| 2060 reg == XMM6_num || reg == XMM6_H_num || | |
| 2061 reg == XMM7_num || reg == XMM7_H_num; | |
| 2062 } | |
| 2063 | |
| 2064 bool Matcher::is_spillable_arg(int reg) | |
| 2065 { | |
| 2066 return can_be_java_arg(reg); | |
| 2067 } | |
| 2068 | |
|
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2069 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) { |
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2070 // In 64 bit mode a code which use multiply when |
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2071 // devisor is constant is faster than hardware |
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2072 // DIV instruction (it uses MulHiL). |
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2073 return false; |
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2074 } |
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2075 |
| 0 | 2076 // Register for DIVI projection of divmodI |
| 2077 RegMask Matcher::divI_proj_mask() { | |
| 2078 return INT_RAX_REG_mask; | |
| 2079 } | |
| 2080 | |
| 2081 // Register for MODI projection of divmodI | |
| 2082 RegMask Matcher::modI_proj_mask() { | |
| 2083 return INT_RDX_REG_mask; | |
| 2084 } | |
| 2085 | |
| 2086 // Register for DIVL projection of divmodL | |
| 2087 RegMask Matcher::divL_proj_mask() { | |
| 2088 return LONG_RAX_REG_mask; | |
| 2089 } | |
| 2090 | |
| 2091 // Register for MODL projection of divmodL | |
| 2092 RegMask Matcher::modL_proj_mask() { | |
| 2093 return LONG_RDX_REG_mask; | |
| 2094 } | |
| 2095 | |
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2096 const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
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2097 return PTR_RBP_REG_mask; |
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2098 } |
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2099 |
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2100 static Address build_address(int b, int i, int s, int d) { |
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2101 Register index = as_Register(i); |
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2102 Address::ScaleFactor scale = (Address::ScaleFactor)s; |
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2103 if (index == rsp) { |
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2104 index = noreg; |
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2105 scale = Address::no_scale; |
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2106 } |
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2107 Address addr(as_Register(b), index, scale, d); |
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2108 return addr; |
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2109 } |
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2110 |
| 0 | 2111 %} |
| 2112 | |
| 2113 //----------ENCODING BLOCK----------------------------------------------------- | |
| 2114 // This block specifies the encoding classes used by the compiler to | |
| 2115 // output byte streams. Encoding classes are parameterized macros | |
| 2116 // used by Machine Instruction Nodes in order to generate the bit | |
| 2117 // encoding of the instruction. Operands specify their base encoding | |
| 2118 // interface with the interface keyword. There are currently | |
| 2119 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, & | |
| 2120 // COND_INTER. REG_INTER causes an operand to generate a function | |
| 2121 // which returns its register number when queried. CONST_INTER causes | |
| 2122 // an operand to generate a function which returns the value of the | |
| 2123 // constant when queried. MEMORY_INTER causes an operand to generate | |
| 2124 // four functions which return the Base Register, the Index Register, | |
| 2125 // the Scale Value, and the Offset Value of the operand when queried. | |
| 2126 // COND_INTER causes an operand to generate six functions which return | |
| 2127 // the encoding code (ie - encoding bits for the instruction) | |
| 2128 // associated with each basic boolean condition for a conditional | |
| 2129 // instruction. | |
| 2130 // | |
| 2131 // Instructions specify two basic values for encoding. Again, a | |
| 2132 // function is available to check if the constant displacement is an | |
| 2133 // oop. They use the ins_encode keyword to specify their encoding | |
| 2134 // classes (which must be a sequence of enc_class names, and their | |
| 2135 // parameters, specified in the encoding block), and they use the | |
| 2136 // opcode keyword to specify, in order, their primary, secondary, and | |
| 2137 // tertiary opcode. Only the opcode sections which a particular | |
| 2138 // instruction needs for encoding need to be specified. | |
| 2139 encode %{ | |
| 2140 // Build emit functions for each basic byte or larger field in the | |
| 2141 // intel encoding scheme (opcode, rm, sib, immediate), and call them | |
| 2142 // from C++ code in the enc_class source block. Emit functions will | |
| 2143 // live in the main source block for now. In future, we can | |
| 2144 // generalize this by adding a syntax that specifies the sizes of | |
| 2145 // fields in an order, so that the adlc can build the emit functions | |
| 2146 // automagically | |
| 2147 | |
| 2148 // Emit primary opcode | |
| 2149 enc_class OpcP | |
| 2150 %{ | |
| 2151 emit_opcode(cbuf, $primary); | |
| 2152 %} | |
| 2153 | |
| 2154 // Emit secondary opcode | |
| 2155 enc_class OpcS | |
| 2156 %{ | |
| 2157 emit_opcode(cbuf, $secondary); | |
| 2158 %} | |
| 2159 | |
| 2160 // Emit tertiary opcode | |
| 2161 enc_class OpcT | |
| 2162 %{ | |
| 2163 emit_opcode(cbuf, $tertiary); | |
| 2164 %} | |
| 2165 | |
| 2166 // Emit opcode directly | |
| 2167 enc_class Opcode(immI d8) | |
| 2168 %{ | |
| 2169 emit_opcode(cbuf, $d8$$constant); | |
| 2170 %} | |
| 2171 | |
| 2172 // Emit size prefix | |
| 2173 enc_class SizePrefix | |
| 2174 %{ | |
| 2175 emit_opcode(cbuf, 0x66); | |
| 2176 %} | |
| 2177 | |
| 2178 enc_class reg(rRegI reg) | |
| 2179 %{ | |
| 2180 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7); | |
| 2181 %} | |
| 2182 | |
| 2183 enc_class reg_reg(rRegI dst, rRegI src) | |
| 2184 %{ | |
| 2185 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7); | |
| 2186 %} | |
| 2187 | |
| 2188 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src) | |
| 2189 %{ | |
| 2190 emit_opcode(cbuf, $opcode$$constant); | |
| 2191 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7); | |
| 2192 %} | |
| 2193 | |
| 2194 enc_class cmpfp_fixup() | |
| 2195 %{ | |
| 2196 // jnp,s exit | |
| 2197 emit_opcode(cbuf, 0x7B); | |
| 2198 emit_d8(cbuf, 0x0A); | |
| 2199 | |
| 2200 // pushfq | |
| 2201 emit_opcode(cbuf, 0x9C); | |
| 2202 | |
| 2203 // andq $0xffffff2b, (%rsp) | |
| 2204 emit_opcode(cbuf, Assembler::REX_W); | |
| 2205 emit_opcode(cbuf, 0x81); | |
| 2206 emit_opcode(cbuf, 0x24); | |
| 2207 emit_opcode(cbuf, 0x24); | |
| 2208 emit_d32(cbuf, 0xffffff2b); | |
| 2209 | |
| 2210 // popfq | |
| 2211 emit_opcode(cbuf, 0x9D); | |
| 2212 | |
| 2213 // nop (target for branch to avoid branch to branch) | |
| 2214 emit_opcode(cbuf, 0x90); | |
| 2215 %} | |
| 2216 | |
| 2217 enc_class cmpfp3(rRegI dst) | |
| 2218 %{ | |
| 2219 int dstenc = $dst$$reg; | |
| 2220 | |
| 2221 // movl $dst, -1 | |
| 2222 if (dstenc >= 8) { | |
| 2223 emit_opcode(cbuf, Assembler::REX_B); | |
| 2224 } | |
| 2225 emit_opcode(cbuf, 0xB8 | (dstenc & 7)); | |
| 2226 emit_d32(cbuf, -1); | |
| 2227 | |
| 2228 // jp,s done | |
| 2229 emit_opcode(cbuf, 0x7A); | |
| 2230 emit_d8(cbuf, dstenc < 4 ? 0x08 : 0x0A); | |
| 2231 | |
| 2232 // jb,s done | |
| 2233 emit_opcode(cbuf, 0x72); | |
| 2234 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08); | |
| 2235 | |
| 2236 // setne $dst | |
| 2237 if (dstenc >= 4) { | |
| 2238 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B); | |
| 2239 } | |
| 2240 emit_opcode(cbuf, 0x0F); | |
| 2241 emit_opcode(cbuf, 0x95); | |
| 2242 emit_opcode(cbuf, 0xC0 | (dstenc & 7)); | |
| 2243 | |
| 2244 // movzbl $dst, $dst | |
| 2245 if (dstenc >= 4) { | |
| 2246 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB); | |
| 2247 } | |
| 2248 emit_opcode(cbuf, 0x0F); | |
| 2249 emit_opcode(cbuf, 0xB6); | |
| 2250 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7); | |
| 2251 %} | |
| 2252 | |
| 2253 enc_class cdql_enc(no_rax_rdx_RegI div) | |
| 2254 %{ | |
| 2255 // Full implementation of Java idiv and irem; checks for | |
| 2256 // special case as described in JVM spec., p.243 & p.271. | |
| 2257 // | |
| 2258 // normal case special case | |
| 2259 // | |
| 2260 // input : rax: dividend min_int | |
| 2261 // reg: divisor -1 | |
| 2262 // | |
| 2263 // output: rax: quotient (= rax idiv reg) min_int | |
| 2264 // rdx: remainder (= rax irem reg) 0 | |
| 2265 // | |
| 2266 // Code sequnce: | |
| 2267 // | |
| 2268 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax | |
| 2269 // 5: 75 07/08 jne e <normal> | |
| 2270 // 7: 33 d2 xor %edx,%edx | |
| 2271 // [div >= 8 -> offset + 1] | |
| 2272 // [REX_B] | |
| 2273 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div | |
| 2274 // c: 74 03/04 je 11 <done> | |
| 2275 // 000000000000000e <normal>: | |
| 2276 // e: 99 cltd | |
| 2277 // [div >= 8 -> offset + 1] | |
| 2278 // [REX_B] | |
| 2279 // f: f7 f9 idiv $div | |
| 2280 // 0000000000000011 <done>: | |
| 2281 | |
| 2282 // cmp $0x80000000,%eax | |
| 2283 emit_opcode(cbuf, 0x3d); | |
| 2284 emit_d8(cbuf, 0x00); | |
| 2285 emit_d8(cbuf, 0x00); | |
| 2286 emit_d8(cbuf, 0x00); | |
| 2287 emit_d8(cbuf, 0x80); | |
| 2288 | |
| 2289 // jne e <normal> | |
| 2290 emit_opcode(cbuf, 0x75); | |
| 2291 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08); | |
| 2292 | |
| 2293 // xor %edx,%edx | |
| 2294 emit_opcode(cbuf, 0x33); | |
| 2295 emit_d8(cbuf, 0xD2); | |
| 2296 | |
| 2297 // cmp $0xffffffffffffffff,%ecx | |
| 2298 if ($div$$reg >= 8) { | |
| 2299 emit_opcode(cbuf, Assembler::REX_B); | |
| 2300 } | |
| 2301 emit_opcode(cbuf, 0x83); | |
| 2302 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7); | |
| 2303 emit_d8(cbuf, 0xFF); | |
| 2304 | |
| 2305 // je 11 <done> | |
| 2306 emit_opcode(cbuf, 0x74); | |
| 2307 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04); | |
| 2308 | |
| 2309 // <normal> | |
| 2310 // cltd | |
| 2311 emit_opcode(cbuf, 0x99); | |
| 2312 | |
| 2313 // idivl (note: must be emitted by the user of this rule) | |
| 2314 // <done> | |
| 2315 %} | |
| 2316 | |
| 2317 enc_class cdqq_enc(no_rax_rdx_RegL div) | |
| 2318 %{ | |
| 2319 // Full implementation of Java ldiv and lrem; checks for | |
| 2320 // special case as described in JVM spec., p.243 & p.271. | |
| 2321 // | |
| 2322 // normal case special case | |
| 2323 // | |
| 2324 // input : rax: dividend min_long | |
| 2325 // reg: divisor -1 | |
| 2326 // | |
| 2327 // output: rax: quotient (= rax idiv reg) min_long | |
| 2328 // rdx: remainder (= rax irem reg) 0 | |
| 2329 // | |
| 2330 // Code sequnce: | |
| 2331 // | |
| 2332 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx | |
| 2333 // 7: 00 00 80 | |
| 2334 // a: 48 39 d0 cmp %rdx,%rax | |
| 2335 // d: 75 08 jne 17 <normal> | |
| 2336 // f: 33 d2 xor %edx,%edx | |
| 2337 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div | |
| 2338 // 15: 74 05 je 1c <done> | |
| 2339 // 0000000000000017 <normal>: | |
| 2340 // 17: 48 99 cqto | |
| 2341 // 19: 48 f7 f9 idiv $div | |
| 2342 // 000000000000001c <done>: | |
| 2343 | |
| 2344 // mov $0x8000000000000000,%rdx | |
| 2345 emit_opcode(cbuf, Assembler::REX_W); | |
| 2346 emit_opcode(cbuf, 0xBA); | |
| 2347 emit_d8(cbuf, 0x00); | |
| 2348 emit_d8(cbuf, 0x00); | |
| 2349 emit_d8(cbuf, 0x00); | |
| 2350 emit_d8(cbuf, 0x00); | |
| 2351 emit_d8(cbuf, 0x00); | |
| 2352 emit_d8(cbuf, 0x00); | |
| 2353 emit_d8(cbuf, 0x00); | |
| 2354 emit_d8(cbuf, 0x80); | |
| 2355 | |
| 2356 // cmp %rdx,%rax | |
| 2357 emit_opcode(cbuf, Assembler::REX_W); | |
| 2358 emit_opcode(cbuf, 0x39); | |
| 2359 emit_d8(cbuf, 0xD0); | |
| 2360 | |
| 2361 // jne 17 <normal> | |
| 2362 emit_opcode(cbuf, 0x75); | |
| 2363 emit_d8(cbuf, 0x08); | |
| 2364 | |
| 2365 // xor %edx,%edx | |
| 2366 emit_opcode(cbuf, 0x33); | |
| 2367 emit_d8(cbuf, 0xD2); | |
| 2368 | |
| 2369 // cmp $0xffffffffffffffff,$div | |
| 2370 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB); | |
| 2371 emit_opcode(cbuf, 0x83); | |
| 2372 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7); | |
| 2373 emit_d8(cbuf, 0xFF); | |
| 2374 | |
| 2375 // je 1e <done> | |
| 2376 emit_opcode(cbuf, 0x74); | |
| 2377 emit_d8(cbuf, 0x05); | |
| 2378 | |
| 2379 // <normal> | |
| 2380 // cqto | |
| 2381 emit_opcode(cbuf, Assembler::REX_W); | |
| 2382 emit_opcode(cbuf, 0x99); | |
| 2383 | |
| 2384 // idivq (note: must be emitted by the user of this rule) | |
| 2385 // <done> | |
| 2386 %} | |
| 2387 | |
| 2388 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension | |
| 2389 enc_class OpcSE(immI imm) | |
| 2390 %{ | |
| 2391 // Emit primary opcode and set sign-extend bit | |
| 2392 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 2393 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
| 2394 emit_opcode(cbuf, $primary | 0x02); | |
| 2395 } else { | |
| 2396 // 32-bit immediate | |
| 2397 emit_opcode(cbuf, $primary); | |
| 2398 } | |
| 2399 %} | |
| 2400 | |
| 2401 enc_class OpcSErm(rRegI dst, immI imm) | |
| 2402 %{ | |
| 2403 // OpcSEr/m | |
| 2404 int dstenc = $dst$$reg; | |
| 2405 if (dstenc >= 8) { | |
| 2406 emit_opcode(cbuf, Assembler::REX_B); | |
| 2407 dstenc -= 8; | |
| 2408 } | |
| 2409 // Emit primary opcode and set sign-extend bit | |
| 2410 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 2411 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
| 2412 emit_opcode(cbuf, $primary | 0x02); | |
| 2413 } else { | |
| 2414 // 32-bit immediate | |
| 2415 emit_opcode(cbuf, $primary); | |
| 2416 } | |
| 2417 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 2418 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
| 2419 %} | |
| 2420 | |
| 2421 enc_class OpcSErm_wide(rRegL dst, immI imm) | |
| 2422 %{ | |
| 2423 // OpcSEr/m | |
| 2424 int dstenc = $dst$$reg; | |
| 2425 if (dstenc < 8) { | |
| 2426 emit_opcode(cbuf, Assembler::REX_W); | |
| 2427 } else { | |
| 2428 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2429 dstenc -= 8; | |
| 2430 } | |
| 2431 // Emit primary opcode and set sign-extend bit | |
| 2432 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 2433 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
| 2434 emit_opcode(cbuf, $primary | 0x02); | |
| 2435 } else { | |
| 2436 // 32-bit immediate | |
| 2437 emit_opcode(cbuf, $primary); | |
| 2438 } | |
| 2439 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 2440 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
| 2441 %} | |
| 2442 | |
| 2443 enc_class Con8or32(immI imm) | |
| 2444 %{ | |
| 2445 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 2446 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
| 2447 $$$emit8$imm$$constant; | |
| 2448 } else { | |
| 2449 // 32-bit immediate | |
| 2450 $$$emit32$imm$$constant; | |
| 2451 } | |
| 2452 %} | |
| 2453 | |
| 2454 enc_class Lbl(label labl) | |
| 2455 %{ | |
| 2456 // JMP, CALL | |
| 2457 Label* l = $labl$$label; | |
| 1748 | 2458 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.insts_size() + 4)) : 0); |
| 0 | 2459 %} |
| 2460 | |
| 2461 enc_class LblShort(label labl) | |
| 2462 %{ | |
| 2463 // JMP, CALL | |
| 2464 Label* l = $labl$$label; | |
| 1748 | 2465 int disp = l ? (l->loc_pos() - (cbuf.insts_size() + 1)) : 0; |
| 0 | 2466 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp"); |
| 2467 emit_d8(cbuf, disp); | |
| 2468 %} | |
| 2469 | |
| 2470 enc_class opc2_reg(rRegI dst) | |
| 2471 %{ | |
| 2472 // BSWAP | |
| 2473 emit_cc(cbuf, $secondary, $dst$$reg); | |
| 2474 %} | |
| 2475 | |
| 2476 enc_class opc3_reg(rRegI dst) | |
| 2477 %{ | |
| 2478 // BSWAP | |
| 2479 emit_cc(cbuf, $tertiary, $dst$$reg); | |
| 2480 %} | |
| 2481 | |
| 2482 enc_class reg_opc(rRegI div) | |
| 2483 %{ | |
| 2484 // INC, DEC, IDIV, IMOD, JMP indirect, ... | |
| 2485 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7); | |
| 2486 %} | |
| 2487 | |
| 2488 enc_class Jcc(cmpOp cop, label labl) | |
| 2489 %{ | |
| 2490 // JCC | |
| 2491 Label* l = $labl$$label; | |
| 2492 $$$emit8$primary; | |
| 2493 emit_cc(cbuf, $secondary, $cop$$cmpcode); | |
| 1748 | 2494 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.insts_size() + 4)) : 0); |
| 0 | 2495 %} |
| 2496 | |
| 2497 enc_class JccShort (cmpOp cop, label labl) | |
| 2498 %{ | |
| 2499 // JCC | |
| 2500 Label *l = $labl$$label; | |
| 2501 emit_cc(cbuf, $primary, $cop$$cmpcode); | |
| 1748 | 2502 int disp = l ? (l->loc_pos() - (cbuf.insts_size() + 1)) : 0; |
| 0 | 2503 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp"); |
| 2504 emit_d8(cbuf, disp); | |
| 2505 %} | |
| 2506 | |
| 2507 enc_class enc_cmov(cmpOp cop) | |
| 2508 %{ | |
| 2509 // CMOV | |
| 2510 $$$emit8$primary; | |
| 2511 emit_cc(cbuf, $secondary, $cop$$cmpcode); | |
| 2512 %} | |
| 2513 | |
| 2514 enc_class enc_cmovf_branch(cmpOp cop, regF dst, regF src) | |
| 2515 %{ | |
| 2516 // Invert sense of branch from sense of cmov | |
| 2517 emit_cc(cbuf, 0x70, $cop$$cmpcode ^ 1); | |
| 2518 emit_d8(cbuf, ($dst$$reg < 8 && $src$$reg < 8) | |
| 2519 ? (UseXmmRegToRegMoveAll ? 3 : 4) | |
| 2520 : (UseXmmRegToRegMoveAll ? 4 : 5) ); // REX | |
| 2521 // UseXmmRegToRegMoveAll ? movaps(dst, src) : movss(dst, src) | |
| 2522 if (!UseXmmRegToRegMoveAll) emit_opcode(cbuf, 0xF3); | |
| 2523 if ($dst$$reg < 8) { | |
| 2524 if ($src$$reg >= 8) { | |
| 2525 emit_opcode(cbuf, Assembler::REX_B); | |
| 2526 } | |
| 2527 } else { | |
| 2528 if ($src$$reg < 8) { | |
| 2529 emit_opcode(cbuf, Assembler::REX_R); | |
| 2530 } else { | |
| 2531 emit_opcode(cbuf, Assembler::REX_RB); | |
| 2532 } | |
| 2533 } | |
| 2534 emit_opcode(cbuf, 0x0F); | |
| 2535 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10); | |
| 2536 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7); | |
| 2537 %} | |
| 2538 | |
| 2539 enc_class enc_cmovd_branch(cmpOp cop, regD dst, regD src) | |
| 2540 %{ | |
| 2541 // Invert sense of branch from sense of cmov | |
| 2542 emit_cc(cbuf, 0x70, $cop$$cmpcode ^ 1); | |
| 2543 emit_d8(cbuf, $dst$$reg < 8 && $src$$reg < 8 ? 4 : 5); // REX | |
| 2544 | |
| 2545 // UseXmmRegToRegMoveAll ? movapd(dst, src) : movsd(dst, src) | |
| 2546 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x66 : 0xF2); | |
| 2547 if ($dst$$reg < 8) { | |
| 2548 if ($src$$reg >= 8) { | |
| 2549 emit_opcode(cbuf, Assembler::REX_B); | |
| 2550 } | |
| 2551 } else { | |
| 2552 if ($src$$reg < 8) { | |
| 2553 emit_opcode(cbuf, Assembler::REX_R); | |
| 2554 } else { | |
| 2555 emit_opcode(cbuf, Assembler::REX_RB); | |
| 2556 } | |
| 2557 } | |
| 2558 emit_opcode(cbuf, 0x0F); | |
| 2559 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10); | |
| 2560 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7); | |
| 2561 %} | |
| 2562 | |
| 2563 enc_class enc_PartialSubtypeCheck() | |
| 2564 %{ | |
| 2565 Register Rrdi = as_Register(RDI_enc); // result register | |
| 2566 Register Rrax = as_Register(RAX_enc); // super class | |
| 2567 Register Rrcx = as_Register(RCX_enc); // killed | |
| 2568 Register Rrsi = as_Register(RSI_enc); // sub class | |
|
644
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2569 Label miss; |
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2570 const bool set_cond_codes = true; |
| 0 | 2571 |
| 2572 MacroAssembler _masm(&cbuf); | |
|
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2573 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi, |
|
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2574 NULL, &miss, |
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2575 /*set_cond_codes:*/ true); |
| 0 | 2576 if ($primary) { |
| 304 | 2577 __ xorptr(Rrdi, Rrdi); |
| 0 | 2578 } |
| 2579 __ bind(miss); | |
| 2580 %} | |
| 2581 | |
| 2582 enc_class Java_To_Interpreter(method meth) | |
| 2583 %{ | |
| 2584 // CALL Java_To_Interpreter | |
| 2585 // This is the instruction starting address for relocation info. | |
| 1748 | 2586 cbuf.set_insts_mark(); |
| 0 | 2587 $$$emit8$primary; |
| 2588 // CALL directly to the runtime | |
| 2589 emit_d32_reloc(cbuf, | |
| 1748 | 2590 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4), |
| 0 | 2591 runtime_call_Relocation::spec(), |
| 2592 RELOC_DISP32); | |
| 2593 %} | |
| 2594 | |
|
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2595 enc_class preserve_SP %{ |
| 1748 | 2596 debug_only(int off0 = cbuf.insts_size()); |
|
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2597 MacroAssembler _masm(&cbuf); |
|
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2598 // RBP is preserved across all calls, even compiled calls. |
|
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2599 // Use it to preserve RSP in places where the callee might change the SP. |
| 1567 | 2600 __ movptr(rbp_mh_SP_save, rsp); |
| 1748 | 2601 debug_only(int off1 = cbuf.insts_size()); |
|
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2602 assert(off1 - off0 == preserve_SP_size(), "correct size prediction"); |
|
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2603 %} |
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2604 |
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6829187: compiler optimizations required for JSR 292
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2605 enc_class restore_SP %{ |
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2606 MacroAssembler _masm(&cbuf); |
| 1567 | 2607 __ movptr(rsp, rbp_mh_SP_save); |
|
1137
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6829187: compiler optimizations required for JSR 292
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2608 %} |
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2609 |
| 0 | 2610 enc_class Java_Static_Call(method meth) |
| 2611 %{ | |
| 2612 // JAVA STATIC CALL | |
| 2613 // CALL to fixup routine. Fixup routine uses ScopeDesc info to | |
| 2614 // determine who we intended to call. | |
| 1748 | 2615 cbuf.set_insts_mark(); |
| 0 | 2616 $$$emit8$primary; |
| 2617 | |
| 2618 if (!_method) { | |
| 2619 emit_d32_reloc(cbuf, | |
| 1748 | 2620 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4), |
| 0 | 2621 runtime_call_Relocation::spec(), |
| 2622 RELOC_DISP32); | |
| 2623 } else if (_optimized_virtual) { | |
| 2624 emit_d32_reloc(cbuf, | |
| 1748 | 2625 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4), |
| 0 | 2626 opt_virtual_call_Relocation::spec(), |
| 2627 RELOC_DISP32); | |
| 2628 } else { | |
| 2629 emit_d32_reloc(cbuf, | |
| 1748 | 2630 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4), |
| 0 | 2631 static_call_Relocation::spec(), |
| 2632 RELOC_DISP32); | |
| 2633 } | |
| 2634 if (_method) { | |
| 2635 // Emit stub for static call | |
| 2636 emit_java_to_interp(cbuf); | |
| 2637 } | |
| 2638 %} | |
| 2639 | |
| 2640 enc_class Java_Dynamic_Call(method meth) | |
| 2641 %{ | |
| 2642 // JAVA DYNAMIC CALL | |
| 2643 // !!!!! | |
| 2644 // Generate "movq rax, -1", placeholder instruction to load oop-info | |
| 2645 // emit_call_dynamic_prologue( cbuf ); | |
| 1748 | 2646 cbuf.set_insts_mark(); |
| 0 | 2647 |
| 2648 // movq rax, -1 | |
| 2649 emit_opcode(cbuf, Assembler::REX_W); | |
| 2650 emit_opcode(cbuf, 0xB8 | RAX_enc); | |
| 2651 emit_d64_reloc(cbuf, | |
| 2652 (int64_t) Universe::non_oop_word(), | |
| 2653 oop_Relocation::spec_for_immediate(), RELOC_IMM64); | |
| 1748 | 2654 address virtual_call_oop_addr = cbuf.insts_mark(); |
| 0 | 2655 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine |
| 2656 // who we intended to call. | |
| 1748 | 2657 cbuf.set_insts_mark(); |
| 0 | 2658 $$$emit8$primary; |
| 2659 emit_d32_reloc(cbuf, | |
| 1748 | 2660 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4), |
| 0 | 2661 virtual_call_Relocation::spec(virtual_call_oop_addr), |
| 2662 RELOC_DISP32); | |
| 2663 %} | |
| 2664 | |
| 2665 enc_class Java_Compiled_Call(method meth) | |
| 2666 %{ | |
| 2667 // JAVA COMPILED CALL | |
| 2668 int disp = in_bytes(methodOopDesc:: from_compiled_offset()); | |
| 2669 | |
| 2670 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!! | |
| 2671 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small"); | |
| 2672 | |
| 2673 // callq *disp(%rax) | |
| 1748 | 2674 cbuf.set_insts_mark(); |
| 0 | 2675 $$$emit8$primary; |
| 2676 if (disp < 0x80) { | |
| 2677 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte | |
| 2678 emit_d8(cbuf, disp); // Displacement | |
| 2679 } else { | |
| 2680 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte | |
| 2681 emit_d32(cbuf, disp); // Displacement | |
| 2682 } | |
| 2683 %} | |
| 2684 | |
| 2685 enc_class reg_opc_imm(rRegI dst, immI8 shift) | |
| 2686 %{ | |
| 2687 // SAL, SAR, SHR | |
| 2688 int dstenc = $dst$$reg; | |
| 2689 if (dstenc >= 8) { | |
| 2690 emit_opcode(cbuf, Assembler::REX_B); | |
| 2691 dstenc -= 8; | |
| 2692 } | |
| 2693 $$$emit8$primary; | |
| 2694 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
| 2695 $$$emit8$shift$$constant; | |
| 2696 %} | |
| 2697 | |
| 2698 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift) | |
| 2699 %{ | |
| 2700 // SAL, SAR, SHR | |
| 2701 int dstenc = $dst$$reg; | |
| 2702 if (dstenc < 8) { | |
| 2703 emit_opcode(cbuf, Assembler::REX_W); | |
| 2704 } else { | |
| 2705 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2706 dstenc -= 8; | |
| 2707 } | |
| 2708 $$$emit8$primary; | |
| 2709 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
| 2710 $$$emit8$shift$$constant; | |
| 2711 %} | |
| 2712 | |
| 2713 enc_class load_immI(rRegI dst, immI src) | |
| 2714 %{ | |
| 2715 int dstenc = $dst$$reg; | |
| 2716 if (dstenc >= 8) { | |
| 2717 emit_opcode(cbuf, Assembler::REX_B); | |
| 2718 dstenc -= 8; | |
| 2719 } | |
| 2720 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2721 $$$emit32$src$$constant; | |
| 2722 %} | |
| 2723 | |
| 2724 enc_class load_immL(rRegL dst, immL src) | |
| 2725 %{ | |
| 2726 int dstenc = $dst$$reg; | |
| 2727 if (dstenc < 8) { | |
| 2728 emit_opcode(cbuf, Assembler::REX_W); | |
| 2729 } else { | |
| 2730 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2731 dstenc -= 8; | |
| 2732 } | |
| 2733 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2734 emit_d64(cbuf, $src$$constant); | |
| 2735 %} | |
| 2736 | |
| 2737 enc_class load_immUL32(rRegL dst, immUL32 src) | |
| 2738 %{ | |
| 2739 // same as load_immI, but this time we care about zeroes in the high word | |
| 2740 int dstenc = $dst$$reg; | |
| 2741 if (dstenc >= 8) { | |
| 2742 emit_opcode(cbuf, Assembler::REX_B); | |
| 2743 dstenc -= 8; | |
| 2744 } | |
| 2745 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2746 $$$emit32$src$$constant; | |
| 2747 %} | |
| 2748 | |
| 2749 enc_class load_immL32(rRegL dst, immL32 src) | |
| 2750 %{ | |
| 2751 int dstenc = $dst$$reg; | |
| 2752 if (dstenc < 8) { | |
| 2753 emit_opcode(cbuf, Assembler::REX_W); | |
| 2754 } else { | |
| 2755 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2756 dstenc -= 8; | |
| 2757 } | |
| 2758 emit_opcode(cbuf, 0xC7); | |
| 2759 emit_rm(cbuf, 0x03, 0x00, dstenc); | |
| 2760 $$$emit32$src$$constant; | |
| 2761 %} | |
| 2762 | |
| 2763 enc_class load_immP31(rRegP dst, immP32 src) | |
| 2764 %{ | |
| 2765 // same as load_immI, but this time we care about zeroes in the high word | |
| 2766 int dstenc = $dst$$reg; | |
| 2767 if (dstenc >= 8) { | |
| 2768 emit_opcode(cbuf, Assembler::REX_B); | |
| 2769 dstenc -= 8; | |
| 2770 } | |
| 2771 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2772 $$$emit32$src$$constant; | |
| 2773 %} | |
| 2774 | |
| 2775 enc_class load_immP(rRegP dst, immP src) | |
| 2776 %{ | |
| 2777 int dstenc = $dst$$reg; | |
| 2778 if (dstenc < 8) { | |
| 2779 emit_opcode(cbuf, Assembler::REX_W); | |
| 2780 } else { | |
| 2781 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2782 dstenc -= 8; | |
| 2783 } | |
| 2784 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2785 // This next line should be generated from ADLC | |
| 2786 if ($src->constant_is_oop()) { | |
| 2787 emit_d64_reloc(cbuf, $src$$constant, relocInfo::oop_type, RELOC_IMM64); | |
| 2788 } else { | |
| 2789 emit_d64(cbuf, $src$$constant); | |
| 2790 } | |
| 2791 %} | |
| 2792 | |
| 2793 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 2794 enc_class enc_copy(rRegI dst, rRegI src) | |
| 2795 %{ | |
| 2796 encode_copy(cbuf, $dst$$reg, $src$$reg); | |
| 2797 %} | |
| 2798 | |
| 2799 // Encode xmm reg-reg copy. If it is useless, then empty encoding. | |
| 2800 enc_class enc_CopyXD( RegD dst, RegD src ) %{ | |
| 2801 encode_CopyXD( cbuf, $dst$$reg, $src$$reg ); | |
| 2802 %} | |
| 2803 | |
| 2804 enc_class enc_copy_always(rRegI dst, rRegI src) | |
| 2805 %{ | |
| 2806 int srcenc = $src$$reg; | |
| 2807 int dstenc = $dst$$reg; | |
| 2808 | |
| 2809 if (dstenc < 8) { | |
| 2810 if (srcenc >= 8) { | |
| 2811 emit_opcode(cbuf, Assembler::REX_B); | |
| 2812 srcenc -= 8; | |
| 2813 } | |
| 2814 } else { | |
| 2815 if (srcenc < 8) { | |
| 2816 emit_opcode(cbuf, Assembler::REX_R); | |
| 2817 } else { | |
| 2818 emit_opcode(cbuf, Assembler::REX_RB); | |
| 2819 srcenc -= 8; | |
| 2820 } | |
| 2821 dstenc -= 8; | |
| 2822 } | |
| 2823 | |
| 2824 emit_opcode(cbuf, 0x8B); | |
| 2825 emit_rm(cbuf, 0x3, dstenc, srcenc); | |
| 2826 %} | |
| 2827 | |
| 2828 enc_class enc_copy_wide(rRegL dst, rRegL src) | |
| 2829 %{ | |
| 2830 int srcenc = $src$$reg; | |
| 2831 int dstenc = $dst$$reg; | |
| 2832 | |
| 2833 if (dstenc != srcenc) { | |
| 2834 if (dstenc < 8) { | |
| 2835 if (srcenc < 8) { | |
| 2836 emit_opcode(cbuf, Assembler::REX_W); | |
| 2837 } else { | |
| 2838 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2839 srcenc -= 8; | |
| 2840 } | |
| 2841 } else { | |
| 2842 if (srcenc < 8) { | |
| 2843 emit_opcode(cbuf, Assembler::REX_WR); | |
| 2844 } else { | |
| 2845 emit_opcode(cbuf, Assembler::REX_WRB); | |
| 2846 srcenc -= 8; | |
| 2847 } | |
| 2848 dstenc -= 8; | |
| 2849 } | |
| 2850 emit_opcode(cbuf, 0x8B); | |
| 2851 emit_rm(cbuf, 0x3, dstenc, srcenc); | |
| 2852 } | |
| 2853 %} | |
| 2854 | |
| 2855 enc_class Con32(immI src) | |
| 2856 %{ | |
| 2857 // Output immediate | |
| 2858 $$$emit32$src$$constant; | |
| 2859 %} | |
| 2860 | |
| 2861 enc_class Con64(immL src) | |
| 2862 %{ | |
| 2863 // Output immediate | |
| 2864 emit_d64($src$$constant); | |
| 2865 %} | |
| 2866 | |
| 2867 enc_class Con32F_as_bits(immF src) | |
| 2868 %{ | |
| 2869 // Output Float immediate bits | |
| 2870 jfloat jf = $src$$constant; | |
| 2871 jint jf_as_bits = jint_cast(jf); | |
| 2872 emit_d32(cbuf, jf_as_bits); | |
| 2873 %} | |
| 2874 | |
| 2875 enc_class Con16(immI src) | |
| 2876 %{ | |
| 2877 // Output immediate | |
| 2878 $$$emit16$src$$constant; | |
| 2879 %} | |
| 2880 | |
| 2881 // How is this different from Con32??? XXX | |
| 2882 enc_class Con_d32(immI src) | |
| 2883 %{ | |
| 2884 emit_d32(cbuf,$src$$constant); | |
| 2885 %} | |
| 2886 | |
| 2887 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI) | |
| 2888 // Output immediate memory reference | |
| 2889 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 ); | |
| 2890 emit_d32(cbuf, 0x00); | |
| 2891 %} | |
| 2892 | |
| 2893 enc_class lock_prefix() | |
| 2894 %{ | |
| 2895 if (os::is_MP()) { | |
| 2896 emit_opcode(cbuf, 0xF0); // lock | |
| 2897 } | |
| 2898 %} | |
| 2899 | |
| 2900 enc_class REX_mem(memory mem) | |
| 2901 %{ | |
| 2902 if ($mem$$base >= 8) { | |
| 2903 if ($mem$$index < 8) { | |
| 2904 emit_opcode(cbuf, Assembler::REX_B); | |
| 2905 } else { | |
| 2906 emit_opcode(cbuf, Assembler::REX_XB); | |
| 2907 } | |
| 2908 } else { | |
| 2909 if ($mem$$index >= 8) { | |
| 2910 emit_opcode(cbuf, Assembler::REX_X); | |
| 2911 } | |
| 2912 } | |
| 2913 %} | |
| 2914 | |
| 2915 enc_class REX_mem_wide(memory mem) | |
| 2916 %{ | |
| 2917 if ($mem$$base >= 8) { | |
| 2918 if ($mem$$index < 8) { | |
| 2919 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2920 } else { | |
| 2921 emit_opcode(cbuf, Assembler::REX_WXB); | |
| 2922 } | |
| 2923 } else { | |
| 2924 if ($mem$$index < 8) { | |
| 2925 emit_opcode(cbuf, Assembler::REX_W); | |
| 2926 } else { | |
| 2927 emit_opcode(cbuf, Assembler::REX_WX); | |
| 2928 } | |
| 2929 } | |
| 2930 %} | |
| 2931 | |
| 2932 // for byte regs | |
| 2933 enc_class REX_breg(rRegI reg) | |
| 2934 %{ | |
| 2935 if ($reg$$reg >= 4) { | |
| 2936 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B); | |
| 2937 } | |
| 2938 %} | |
| 2939 | |
| 2940 // for byte regs | |
| 2941 enc_class REX_reg_breg(rRegI dst, rRegI src) | |
| 2942 %{ | |
| 2943 if ($dst$$reg < 8) { | |
| 2944 if ($src$$reg >= 4) { | |
| 2945 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B); | |
| 2946 } | |
| 2947 } else { | |
| 2948 if ($src$$reg < 8) { | |
| 2949 emit_opcode(cbuf, Assembler::REX_R); | |
| 2950 } else { | |
| 2951 emit_opcode(cbuf, Assembler::REX_RB); | |
| 2952 } | |
| 2953 } | |
| 2954 %} | |
| 2955 | |
| 2956 // for byte regs | |
| 2957 enc_class REX_breg_mem(rRegI reg, memory mem) | |
| 2958 %{ | |
| 2959 if ($reg$$reg < 8) { | |
| 2960 if ($mem$$base < 8) { | |
| 2961 if ($mem$$index >= 8) { | |
| 2962 emit_opcode(cbuf, Assembler::REX_X); | |
| 2963 } else if ($reg$$reg >= 4) { | |
| 2964 emit_opcode(cbuf, Assembler::REX); | |
| 2965 } | |
| 2966 } else { | |
| 2967 if ($mem$$index < 8) { | |
| 2968 emit_opcode(cbuf, Assembler::REX_B); | |
| 2969 } else { | |
| 2970 emit_opcode(cbuf, Assembler::REX_XB); | |
| 2971 } | |
| 2972 } | |
| 2973 } else { | |
| 2974 if ($mem$$base < 8) { | |
| 2975 if ($mem$$index < 8) { | |
| 2976 emit_opcode(cbuf, Assembler::REX_R); | |
| 2977 } else { | |
| 2978 emit_opcode(cbuf, Assembler::REX_RX); | |
| 2979 } | |
| 2980 } else { | |
| 2981 if ($mem$$index < 8) { | |
| 2982 emit_opcode(cbuf, Assembler::REX_RB); | |
| 2983 } else { | |
| 2984 emit_opcode(cbuf, Assembler::REX_RXB); | |
| 2985 } | |
| 2986 } | |
| 2987 } | |
| 2988 %} | |
| 2989 | |
| 2990 enc_class REX_reg(rRegI reg) | |
| 2991 %{ | |
| 2992 if ($reg$$reg >= 8) { | |
| 2993 emit_opcode(cbuf, Assembler::REX_B); | |
| 2994 } | |
| 2995 %} | |
| 2996 | |
| 2997 enc_class REX_reg_wide(rRegI reg) | |
| 2998 %{ | |
| 2999 if ($reg$$reg < 8) { | |
| 3000 emit_opcode(cbuf, Assembler::REX_W); | |
| 3001 } else { | |
| 3002 emit_opcode(cbuf, Assembler::REX_WB); | |
| 3003 } | |
| 3004 %} | |
| 3005 | |
| 3006 enc_class REX_reg_reg(rRegI dst, rRegI src) | |
| 3007 %{ | |
| 3008 if ($dst$$reg < 8) { | |
| 3009 if ($src$$reg >= 8) { | |
| 3010 emit_opcode(cbuf, Assembler::REX_B); | |
| 3011 } | |
| 3012 } else { | |
| 3013 if ($src$$reg < 8) { | |
| 3014 emit_opcode(cbuf, Assembler::REX_R); | |
| 3015 } else { | |
| 3016 emit_opcode(cbuf, Assembler::REX_RB); | |
| 3017 } | |
| 3018 } | |
| 3019 %} | |
| 3020 | |
| 3021 enc_class REX_reg_reg_wide(rRegI dst, rRegI src) | |
| 3022 %{ | |
| 3023 if ($dst$$reg < 8) { | |
| 3024 if ($src$$reg < 8) { | |
| 3025 emit_opcode(cbuf, Assembler::REX_W); | |
| 3026 } else { | |
| 3027 emit_opcode(cbuf, Assembler::REX_WB); | |
| 3028 } | |
| 3029 } else { | |
| 3030 if ($src$$reg < 8) { | |
| 3031 emit_opcode(cbuf, Assembler::REX_WR); | |
| 3032 } else { | |
| 3033 emit_opcode(cbuf, Assembler::REX_WRB); | |
| 3034 } | |
| 3035 } | |
| 3036 %} | |
| 3037 | |
| 3038 enc_class REX_reg_mem(rRegI reg, memory mem) | |
| 3039 %{ | |
| 3040 if ($reg$$reg < 8) { | |
| 3041 if ($mem$$base < 8) { | |
| 3042 if ($mem$$index >= 8) { | |
| 3043 emit_opcode(cbuf, Assembler::REX_X); | |
| 3044 } | |
| 3045 } else { | |
| 3046 if ($mem$$index < 8) { | |
| 3047 emit_opcode(cbuf, Assembler::REX_B); | |
| 3048 } else { | |
| 3049 emit_opcode(cbuf, Assembler::REX_XB); | |
| 3050 } | |
| 3051 } | |
| 3052 } else { | |
| 3053 if ($mem$$base < 8) { | |
| 3054 if ($mem$$index < 8) { | |
| 3055 emit_opcode(cbuf, Assembler::REX_R); | |
| 3056 } else { | |
| 3057 emit_opcode(cbuf, Assembler::REX_RX); | |
| 3058 } | |
| 3059 } else { | |
| 3060 if ($mem$$index < 8) { | |
| 3061 emit_opcode(cbuf, Assembler::REX_RB); | |
| 3062 } else { | |
| 3063 emit_opcode(cbuf, Assembler::REX_RXB); | |
| 3064 } | |
| 3065 } | |
| 3066 } | |
| 3067 %} | |
| 3068 | |
| 3069 enc_class REX_reg_mem_wide(rRegL reg, memory mem) | |
| 3070 %{ | |
| 3071 if ($reg$$reg < 8) { | |
| 3072 if ($mem$$base < 8) { | |
| 3073 if ($mem$$index < 8) { | |
| 3074 emit_opcode(cbuf, Assembler::REX_W); | |
| 3075 } else { | |
| 3076 emit_opcode(cbuf, Assembler::REX_WX); | |
| 3077 } | |
| 3078 } else { | |
| 3079 if ($mem$$index < 8) { | |
| 3080 emit_opcode(cbuf, Assembler::REX_WB); | |
| 3081 } else { | |
| 3082 emit_opcode(cbuf, Assembler::REX_WXB); | |
| 3083 } | |
| 3084 } | |
| 3085 } else { | |
| 3086 if ($mem$$base < 8) { | |
| 3087 if ($mem$$index < 8) { | |
| 3088 emit_opcode(cbuf, Assembler::REX_WR); | |
| 3089 } else { | |
| 3090 emit_opcode(cbuf, Assembler::REX_WRX); | |
| 3091 } | |
| 3092 } else { | |
| 3093 if ($mem$$index < 8) { | |
| 3094 emit_opcode(cbuf, Assembler::REX_WRB); | |
| 3095 } else { | |
| 3096 emit_opcode(cbuf, Assembler::REX_WRXB); | |
| 3097 } | |
| 3098 } | |
| 3099 } | |
| 3100 %} | |
| 3101 | |
| 3102 enc_class reg_mem(rRegI ereg, memory mem) | |
| 3103 %{ | |
| 3104 // High registers handle in encode_RegMem | |
| 3105 int reg = $ereg$$reg; | |
| 3106 int base = $mem$$base; | |
| 3107 int index = $mem$$index; | |
| 3108 int scale = $mem$$scale; | |
| 3109 int disp = $mem$$disp; | |
| 3110 bool disp_is_oop = $mem->disp_is_oop(); | |
| 3111 | |
| 3112 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_is_oop); | |
| 3113 %} | |
| 3114 | |
| 3115 enc_class RM_opc_mem(immI rm_opcode, memory mem) | |
| 3116 %{ | |
| 3117 int rm_byte_opcode = $rm_opcode$$constant; | |
| 3118 | |
| 3119 // High registers handle in encode_RegMem | |
| 3120 int base = $mem$$base; | |
| 3121 int index = $mem$$index; | |
| 3122 int scale = $mem$$scale; | |
| 3123 int displace = $mem$$disp; | |
| 3124 | |
| 3125 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when | |
| 3126 // working with static | |
| 3127 // globals | |
| 3128 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, | |
| 3129 disp_is_oop); | |
| 3130 %} | |
| 3131 | |
| 3132 enc_class reg_lea(rRegI dst, rRegI src0, immI src1) | |
| 3133 %{ | |
| 3134 int reg_encoding = $dst$$reg; | |
| 3135 int base = $src0$$reg; // 0xFFFFFFFF indicates no base | |
| 3136 int index = 0x04; // 0x04 indicates no index | |
| 3137 int scale = 0x00; // 0x00 indicates no scale | |
| 3138 int displace = $src1$$constant; // 0x00 indicates no displacement | |
| 3139 bool disp_is_oop = false; | |
| 3140 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, | |
| 3141 disp_is_oop); | |
| 3142 %} | |
| 3143 | |
| 3144 enc_class neg_reg(rRegI dst) | |
| 3145 %{ | |
| 3146 int dstenc = $dst$$reg; | |
| 3147 if (dstenc >= 8) { | |
| 3148 emit_opcode(cbuf, Assembler::REX_B); | |
| 3149 dstenc -= 8; | |
| 3150 } | |
| 3151 // NEG $dst | |
| 3152 emit_opcode(cbuf, 0xF7); | |
| 3153 emit_rm(cbuf, 0x3, 0x03, dstenc); | |
| 3154 %} | |
| 3155 | |
| 3156 enc_class neg_reg_wide(rRegI dst) | |
| 3157 %{ | |
| 3158 int dstenc = $dst$$reg; | |
| 3159 if (dstenc < 8) { | |
| 3160 emit_opcode(cbuf, Assembler::REX_W); | |
| 3161 } else { | |
| 3162 emit_opcode(cbuf, Assembler::REX_WB); | |
| 3163 dstenc -= 8; | |
| 3164 } | |
| 3165 // NEG $dst | |
| 3166 emit_opcode(cbuf, 0xF7); | |
| 3167 emit_rm(cbuf, 0x3, 0x03, dstenc); | |
| 3168 %} | |
| 3169 | |
| 3170 enc_class setLT_reg(rRegI dst) | |
| 3171 %{ | |
| 3172 int dstenc = $dst$$reg; | |
| 3173 if (dstenc >= 8) { | |
| 3174 emit_opcode(cbuf, Assembler::REX_B); | |
| 3175 dstenc -= 8; | |
| 3176 } else if (dstenc >= 4) { | |
| 3177 emit_opcode(cbuf, Assembler::REX); | |
| 3178 } | |
| 3179 // SETLT $dst | |
| 3180 emit_opcode(cbuf, 0x0F); | |
| 3181 emit_opcode(cbuf, 0x9C); | |
| 3182 emit_rm(cbuf, 0x3, 0x0, dstenc); | |
| 3183 %} | |
| 3184 | |
| 3185 enc_class setNZ_reg(rRegI dst) | |
| 3186 %{ | |
| 3187 int dstenc = $dst$$reg; | |
| 3188 if (dstenc >= 8) { | |
| 3189 emit_opcode(cbuf, Assembler::REX_B); | |
| 3190 dstenc -= 8; | |
| 3191 } else if (dstenc >= 4) { | |
| 3192 emit_opcode(cbuf, Assembler::REX); | |
| 3193 } | |
| 3194 // SETNZ $dst | |
| 3195 emit_opcode(cbuf, 0x0F); | |
| 3196 emit_opcode(cbuf, 0x95); | |
| 3197 emit_rm(cbuf, 0x3, 0x0, dstenc); | |
| 3198 %} | |
| 3199 | |
| 3200 enc_class enc_cmpLTP(no_rcx_RegI p, no_rcx_RegI q, no_rcx_RegI y, | |
| 3201 rcx_RegI tmp) | |
| 3202 %{ | |
| 3203 // cadd_cmpLT | |
| 3204 | |
| 3205 int tmpReg = $tmp$$reg; | |
| 3206 | |
| 3207 int penc = $p$$reg; | |
| 3208 int qenc = $q$$reg; | |
| 3209 int yenc = $y$$reg; | |
| 3210 | |
| 3211 // subl $p,$q | |
| 3212 if (penc < 8) { | |
| 3213 if (qenc >= 8) { | |
| 3214 emit_opcode(cbuf, Assembler::REX_B); | |
| 3215 } | |
| 3216 } else { | |
| 3217 if (qenc < 8) { | |
| 3218 emit_opcode(cbuf, Assembler::REX_R); | |
| 3219 } else { | |
| 3220 emit_opcode(cbuf, Assembler::REX_RB); | |
| 3221 } | |
| 3222 } | |
| 3223 emit_opcode(cbuf, 0x2B); | |
| 3224 emit_rm(cbuf, 0x3, penc & 7, qenc & 7); | |
| 3225 | |
| 3226 // sbbl $tmp, $tmp | |
| 3227 emit_opcode(cbuf, 0x1B); | |
| 3228 emit_rm(cbuf, 0x3, tmpReg, tmpReg); | |
| 3229 | |
| 3230 // andl $tmp, $y | |
| 3231 if (yenc >= 8) { | |
| 3232 emit_opcode(cbuf, Assembler::REX_B); | |
| 3233 } | |
| 3234 emit_opcode(cbuf, 0x23); | |
| 3235 emit_rm(cbuf, 0x3, tmpReg, yenc & 7); | |
| 3236 | |
| 3237 // addl $p,$tmp | |
| 3238 if (penc >= 8) { | |
| 3239 emit_opcode(cbuf, Assembler::REX_R); | |
| 3240 } | |
| 3241 emit_opcode(cbuf, 0x03); | |
| 3242 emit_rm(cbuf, 0x3, penc & 7, tmpReg); | |
| 3243 %} | |
| 3244 | |
| 3245 // Compare the lonogs and set -1, 0, or 1 into dst | |
| 3246 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst) | |
| 3247 %{ | |
| 3248 int src1enc = $src1$$reg; | |
| 3249 int src2enc = $src2$$reg; | |
| 3250 int dstenc = $dst$$reg; | |
| 3251 | |
| 3252 // cmpq $src1, $src2 | |
| 3253 if (src1enc < 8) { | |
| 3254 if (src2enc < 8) { | |
| 3255 emit_opcode(cbuf, Assembler::REX_W); | |
| 3256 } else { | |
| 3257 emit_opcode(cbuf, Assembler::REX_WB); | |
| 3258 } | |
| 3259 } else { | |
| 3260 if (src2enc < 8) { | |
| 3261 emit_opcode(cbuf, Assembler::REX_WR); | |
| 3262 } else { | |
| 3263 emit_opcode(cbuf, Assembler::REX_WRB); | |
| 3264 } | |
| 3265 } | |
| 3266 emit_opcode(cbuf, 0x3B); | |
| 3267 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7); | |
| 3268 | |
| 3269 // movl $dst, -1 | |
| 3270 if (dstenc >= 8) { | |
| 3271 emit_opcode(cbuf, Assembler::REX_B); | |
| 3272 } | |
| 3273 emit_opcode(cbuf, 0xB8 | (dstenc & 7)); | |
| 3274 emit_d32(cbuf, -1); | |
| 3275 | |
| 3276 // jl,s done | |
| 3277 emit_opcode(cbuf, 0x7C); | |
| 3278 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08); | |
| 3279 | |
| 3280 // setne $dst | |
| 3281 if (dstenc >= 4) { | |
| 3282 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B); | |
| 3283 } | |
| 3284 emit_opcode(cbuf, 0x0F); | |
| 3285 emit_opcode(cbuf, 0x95); | |
| 3286 emit_opcode(cbuf, 0xC0 | (dstenc & 7)); | |
| 3287 | |
| 3288 // movzbl $dst, $dst | |
| 3289 if (dstenc >= 4) { | |
| 3290 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB); | |
| 3291 } | |
| 3292 emit_opcode(cbuf, 0x0F); | |
| 3293 emit_opcode(cbuf, 0xB6); | |
| 3294 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7); | |
| 3295 %} | |
| 3296 | |
| 3297 enc_class Push_ResultXD(regD dst) %{ | |
| 3298 int dstenc = $dst$$reg; | |
| 3299 | |
| 3300 store_to_stackslot( cbuf, 0xDD, 0x03, 0 ); //FSTP [RSP] | |
| 3301 | |
| 3302 // UseXmmLoadAndClearUpper ? movsd dst,[rsp] : movlpd dst,[rsp] | |
| 3303 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66); | |
| 3304 if (dstenc >= 8) { | |
| 3305 emit_opcode(cbuf, Assembler::REX_R); | |
| 3306 } | |
| 3307 emit_opcode (cbuf, 0x0F ); | |
| 3308 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12 ); | |
| 3309 encode_RegMem(cbuf, dstenc, RSP_enc, 0x4, 0, 0, false); | |
| 3310 | |
| 3311 // add rsp,8 | |
| 3312 emit_opcode(cbuf, Assembler::REX_W); | |
| 3313 emit_opcode(cbuf,0x83); | |
| 3314 emit_rm(cbuf,0x3, 0x0, RSP_enc); | |
| 3315 emit_d8(cbuf,0x08); | |
| 3316 %} | |
| 3317 | |
| 3318 enc_class Push_SrcXD(regD src) %{ | |
| 3319 int srcenc = $src$$reg; | |
| 3320 | |
| 3321 // subq rsp,#8 | |
| 3322 emit_opcode(cbuf, Assembler::REX_W); | |
| 3323 emit_opcode(cbuf, 0x83); | |
| 3324 emit_rm(cbuf, 0x3, 0x5, RSP_enc); | |
| 3325 emit_d8(cbuf, 0x8); | |
| 3326 | |
| 3327 // movsd [rsp],src | |
| 3328 emit_opcode(cbuf, 0xF2); | |
| 3329 if (srcenc >= 8) { | |
| 3330 emit_opcode(cbuf, Assembler::REX_R); | |
| 3331 } | |
| 3332 emit_opcode(cbuf, 0x0F); | |
| 3333 emit_opcode(cbuf, 0x11); | |
| 3334 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); | |
| 3335 | |
| 3336 // fldd [rsp] | |
| 3337 emit_opcode(cbuf, 0x66); | |
| 3338 emit_opcode(cbuf, 0xDD); | |
| 3339 encode_RegMem(cbuf, 0x0, RSP_enc, 0x4, 0, 0, false); | |
| 3340 %} | |
| 3341 | |
| 3342 | |
| 3343 enc_class movq_ld(regD dst, memory mem) %{ | |
| 3344 MacroAssembler _masm(&cbuf); | |
| 624 | 3345 __ movq($dst$$XMMRegister, $mem$$Address); |
| 0 | 3346 %} |
| 3347 | |
| 3348 enc_class movq_st(memory mem, regD src) %{ | |
| 3349 MacroAssembler _masm(&cbuf); | |
| 624 | 3350 __ movq($mem$$Address, $src$$XMMRegister); |
| 0 | 3351 %} |
| 3352 | |
| 3353 enc_class pshufd_8x8(regF dst, regF src) %{ | |
| 3354 MacroAssembler _masm(&cbuf); | |
| 3355 | |
| 3356 encode_CopyXD(cbuf, $dst$$reg, $src$$reg); | |
| 3357 __ punpcklbw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg)); | |
| 3358 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg), 0x00); | |
| 3359 %} | |
| 3360 | |
| 3361 enc_class pshufd_4x16(regF dst, regF src) %{ | |
| 3362 MacroAssembler _masm(&cbuf); | |
| 3363 | |
| 3364 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), 0x00); | |
| 3365 %} | |
| 3366 | |
| 3367 enc_class pshufd(regD dst, regD src, int mode) %{ | |
| 3368 MacroAssembler _masm(&cbuf); | |
| 3369 | |
| 3370 __ pshufd(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), $mode); | |
| 3371 %} | |
| 3372 | |
| 3373 enc_class pxor(regD dst, regD src) %{ | |
| 3374 MacroAssembler _masm(&cbuf); | |
| 3375 | |
| 3376 __ pxor(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg)); | |
| 3377 %} | |
| 3378 | |
| 3379 enc_class mov_i2x(regD dst, rRegI src) %{ | |
| 3380 MacroAssembler _masm(&cbuf); | |
| 3381 | |
| 3382 __ movdl(as_XMMRegister($dst$$reg), as_Register($src$$reg)); | |
| 3383 %} | |
| 3384 | |
| 3385 // obj: object to lock | |
| 3386 // box: box address (header location) -- killed | |
| 3387 // tmp: rax -- killed | |
| 3388 // scr: rbx -- killed | |
| 3389 // | |
| 3390 // What follows is a direct transliteration of fast_lock() and fast_unlock() | |
| 3391 // from i486.ad. See that file for comments. | |
| 3392 // TODO: where possible switch from movq (r, 0) to movl(r,0) and | |
| 3393 // use the shorter encoding. (Movl clears the high-order 32-bits). | |
| 3394 | |
| 3395 | |
| 3396 enc_class Fast_Lock(rRegP obj, rRegP box, rax_RegI tmp, rRegP scr) | |
| 3397 %{ | |
| 3398 Register objReg = as_Register((int)$obj$$reg); | |
| 3399 Register boxReg = as_Register((int)$box$$reg); | |
| 3400 Register tmpReg = as_Register($tmp$$reg); | |
| 3401 Register scrReg = as_Register($scr$$reg); | |
| 3402 MacroAssembler masm(&cbuf); | |
| 3403 | |
| 3404 // Verify uniqueness of register assignments -- necessary but not sufficient | |
| 3405 assert (objReg != boxReg && objReg != tmpReg && | |
| 3406 objReg != scrReg && tmpReg != scrReg, "invariant") ; | |
| 3407 | |
| 3408 if (_counters != NULL) { | |
| 3409 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr())); | |
| 3410 } | |
| 3411 if (EmitSync & 1) { | |
| 304 | 3412 // Without cast to int32_t a movptr will destroy r10 which is typically obj |
| 3413 masm.movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ; | |
| 3414 masm.cmpptr(rsp, (int32_t)NULL_WORD) ; | |
| 0 | 3415 } else |
| 3416 if (EmitSync & 2) { | |
| 3417 Label DONE_LABEL; | |
| 3418 if (UseBiasedLocking) { | |
| 3419 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument. | |
| 3420 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters); | |
| 3421 } | |
| 304 | 3422 // QQQ was movl... |
| 3423 masm.movptr(tmpReg, 0x1); | |
| 3424 masm.orptr(tmpReg, Address(objReg, 0)); | |
| 3425 masm.movptr(Address(boxReg, 0), tmpReg); | |
| 0 | 3426 if (os::is_MP()) { |
| 3427 masm.lock(); | |
| 3428 } | |
| 304 | 3429 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg |
| 0 | 3430 masm.jcc(Assembler::equal, DONE_LABEL); |
| 3431 | |
| 3432 // Recursive locking | |
| 304 | 3433 masm.subptr(tmpReg, rsp); |
| 3434 masm.andptr(tmpReg, 7 - os::vm_page_size()); | |
| 3435 masm.movptr(Address(boxReg, 0), tmpReg); | |
| 0 | 3436 |
| 3437 masm.bind(DONE_LABEL); | |
| 3438 masm.nop(); // avoid branch to branch | |
| 3439 } else { | |
| 3440 Label DONE_LABEL, IsInflated, Egress; | |
| 3441 | |
| 304 | 3442 masm.movptr(tmpReg, Address(objReg, 0)) ; |
| 3443 masm.testl (tmpReg, 0x02) ; // inflated vs stack-locked|neutral|biased | |
| 3444 masm.jcc (Assembler::notZero, IsInflated) ; | |
| 3445 | |
| 0 | 3446 // it's stack-locked, biased or neutral |
| 3447 // TODO: optimize markword triage order to reduce the number of | |
| 3448 // conditional branches in the most common cases. | |
| 3449 // Beware -- there's a subtle invariant that fetch of the markword | |
| 3450 // at [FETCH], below, will never observe a biased encoding (*101b). | |
| 3451 // If this invariant is not held we'll suffer exclusion (safety) failure. | |
| 3452 | |
|
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|
3453 if (UseBiasedLocking && !UseOptoBiasInlining) { |
| 0 | 3454 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, true, DONE_LABEL, NULL, _counters); |
| 304 | 3455 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH] |
| 0 | 3456 } |
| 3457 | |
| 304 | 3458 // was q will it destroy high? |
| 3459 masm.orl (tmpReg, 1) ; | |
| 3460 masm.movptr(Address(boxReg, 0), tmpReg) ; | |
| 3461 if (os::is_MP()) { masm.lock(); } | |
| 3462 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg | |
| 0 | 3463 if (_counters != NULL) { |
| 3464 masm.cond_inc32(Assembler::equal, | |
| 3465 ExternalAddress((address) _counters->fast_path_entry_count_addr())); | |
| 3466 } | |
| 3467 masm.jcc (Assembler::equal, DONE_LABEL); | |
| 3468 | |
| 3469 // Recursive locking | |
| 304 | 3470 masm.subptr(tmpReg, rsp); |
| 3471 masm.andptr(tmpReg, 7 - os::vm_page_size()); | |
| 3472 masm.movptr(Address(boxReg, 0), tmpReg); | |
| 0 | 3473 if (_counters != NULL) { |
| 3474 masm.cond_inc32(Assembler::equal, | |
| 3475 ExternalAddress((address) _counters->fast_path_entry_count_addr())); | |
| 3476 } | |
| 3477 masm.jmp (DONE_LABEL) ; | |
| 3478 | |
| 3479 masm.bind (IsInflated) ; | |
| 3480 // It's inflated | |
| 3481 | |
| 3482 // TODO: someday avoid the ST-before-CAS penalty by | |
| 3483 // relocating (deferring) the following ST. | |
| 3484 // We should also think about trying a CAS without having | |
| 3485 // fetched _owner. If the CAS is successful we may | |
| 3486 // avoid an RTO->RTS upgrade on the $line. | |
| 304 | 3487 // Without cast to int32_t a movptr will destroy r10 which is typically obj |
| 3488 masm.movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ; | |
| 3489 | |
| 3490 masm.mov (boxReg, tmpReg) ; | |
| 3491 masm.movptr (tmpReg, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; | |
| 3492 masm.testptr(tmpReg, tmpReg) ; | |
| 3493 masm.jcc (Assembler::notZero, DONE_LABEL) ; | |
| 0 | 3494 |
| 3495 // It's inflated and appears unlocked | |
| 304 | 3496 if (os::is_MP()) { masm.lock(); } |
| 3497 masm.cmpxchgptr(r15_thread, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; | |
| 0 | 3498 // Intentional fall-through into DONE_LABEL ... |
| 3499 | |
| 3500 masm.bind (DONE_LABEL) ; | |
| 3501 masm.nop () ; // avoid jmp to jmp | |
| 3502 } | |
| 3503 %} | |
| 3504 | |
| 3505 // obj: object to unlock | |
| 3506 // box: box address (displaced header location), killed | |
| 3507 // RBX: killed tmp; cannot be obj nor box | |
| 3508 enc_class Fast_Unlock(rRegP obj, rax_RegP box, rRegP tmp) | |
| 3509 %{ | |
| 3510 | |
| 3511 Register objReg = as_Register($obj$$reg); | |
| 3512 Register boxReg = as_Register($box$$reg); | |
| 3513 Register tmpReg = as_Register($tmp$$reg); | |
| 3514 MacroAssembler masm(&cbuf); | |
| 3515 | |
| 304 | 3516 if (EmitSync & 4) { |
| 3517 masm.cmpptr(rsp, 0) ; | |
| 0 | 3518 } else |
| 3519 if (EmitSync & 8) { | |
| 3520 Label DONE_LABEL; | |
| 3521 if (UseBiasedLocking) { | |
| 3522 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); | |
| 3523 } | |
| 3524 | |
| 3525 // Check whether the displaced header is 0 | |
| 3526 //(=> recursive unlock) | |
| 304 | 3527 masm.movptr(tmpReg, Address(boxReg, 0)); |
| 3528 masm.testptr(tmpReg, tmpReg); | |
| 0 | 3529 masm.jcc(Assembler::zero, DONE_LABEL); |
| 3530 | |
| 3531 // If not recursive lock, reset the header to displaced header | |
| 3532 if (os::is_MP()) { | |
| 3533 masm.lock(); | |
| 3534 } | |
| 304 | 3535 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box |
| 0 | 3536 masm.bind(DONE_LABEL); |
| 3537 masm.nop(); // avoid branch to branch | |
| 3538 } else { | |
| 3539 Label DONE_LABEL, Stacked, CheckSucc ; | |
| 3540 | |
|
420
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parents:
415
diff
changeset
|
3541 if (UseBiasedLocking && !UseOptoBiasInlining) { |
| 0 | 3542 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); |
| 3543 } | |
| 304 | 3544 |
| 3545 masm.movptr(tmpReg, Address(objReg, 0)) ; | |
| 3546 masm.cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD) ; | |
| 3547 masm.jcc (Assembler::zero, DONE_LABEL) ; | |
| 3548 masm.testl (tmpReg, 0x02) ; | |
| 3549 masm.jcc (Assembler::zero, Stacked) ; | |
| 3550 | |
| 0 | 3551 // It's inflated |
| 304 | 3552 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
| 3553 masm.xorptr(boxReg, r15_thread) ; | |
| 3554 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ; | |
| 3555 masm.jcc (Assembler::notZero, DONE_LABEL) ; | |
| 3556 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ; | |
| 3557 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ; | |
| 3558 masm.jcc (Assembler::notZero, CheckSucc) ; | |
| 3559 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ; | |
| 3560 masm.jmp (DONE_LABEL) ; | |
| 3561 | |
| 3562 if ((EmitSync & 65536) == 0) { | |
| 0 | 3563 Label LSuccess, LGoSlowPath ; |
| 3564 masm.bind (CheckSucc) ; | |
| 304 | 3565 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ; |
| 0 | 3566 masm.jcc (Assembler::zero, LGoSlowPath) ; |
| 3567 | |
| 3568 // I'd much rather use lock:andl m->_owner, 0 as it's faster than the | |
| 3569 // the explicit ST;MEMBAR combination, but masm doesn't currently support | |
| 3570 // "ANDQ M,IMM". Don't use MFENCE here. lock:add to TOS, xchg, etc | |
| 3571 // are all faster when the write buffer is populated. | |
| 304 | 3572 masm.movptr (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ; |
| 0 | 3573 if (os::is_MP()) { |
| 304 | 3574 masm.lock () ; masm.addl (Address(rsp, 0), 0) ; |
| 0 | 3575 } |
| 304 | 3576 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ; |
| 0 | 3577 masm.jcc (Assembler::notZero, LSuccess) ; |
| 3578 | |
| 304 | 3579 masm.movptr (boxReg, (int32_t)NULL_WORD) ; // box is really EAX |
| 0 | 3580 if (os::is_MP()) { masm.lock(); } |
| 304 | 3581 masm.cmpxchgptr(r15_thread, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)); |
| 0 | 3582 masm.jcc (Assembler::notEqual, LSuccess) ; |
| 3583 // Intentional fall-through into slow-path | |
| 3584 | |
| 3585 masm.bind (LGoSlowPath) ; | |
| 3586 masm.orl (boxReg, 1) ; // set ICC.ZF=0 to indicate failure | |
| 3587 masm.jmp (DONE_LABEL) ; | |
| 3588 | |
| 3589 masm.bind (LSuccess) ; | |
| 3590 masm.testl (boxReg, 0) ; // set ICC.ZF=1 to indicate success | |
| 3591 masm.jmp (DONE_LABEL) ; | |
| 3592 } | |
| 3593 | |
| 304 | 3594 masm.bind (Stacked) ; |
| 3595 masm.movptr(tmpReg, Address (boxReg, 0)) ; // re-fetch | |
| 3596 if (os::is_MP()) { masm.lock(); } | |
| 3597 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box | |
| 0 | 3598 |
| 3599 if (EmitSync & 65536) { | |
| 3600 masm.bind (CheckSucc) ; | |
| 3601 } | |
| 3602 masm.bind(DONE_LABEL); | |
| 3603 if (EmitSync & 32768) { | |
| 3604 masm.nop(); // avoid branch to branch | |
| 3605 } | |
| 3606 } | |
| 3607 %} | |
| 3608 | |
|
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|
3609 |
| 0 | 3610 enc_class enc_rethrow() |
| 3611 %{ | |
| 1748 | 3612 cbuf.set_insts_mark(); |
| 0 | 3613 emit_opcode(cbuf, 0xE9); // jmp entry |
| 3614 emit_d32_reloc(cbuf, | |
| 1748 | 3615 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4), |
| 0 | 3616 runtime_call_Relocation::spec(), |
| 3617 RELOC_DISP32); | |
| 3618 %} | |
| 3619 | |
| 3620 enc_class absF_encoding(regF dst) | |
| 3621 %{ | |
| 3622 int dstenc = $dst$$reg; | |
| 304 | 3623 address signmask_address = (address) StubRoutines::x86::float_sign_mask(); |
| 0 | 3624 |
| 1748 | 3625 cbuf.set_insts_mark(); |
| 0 | 3626 if (dstenc >= 8) { |
| 3627 emit_opcode(cbuf, Assembler::REX_R); | |
| 3628 dstenc -= 8; | |
| 3629 } | |
| 3630 // XXX reg_mem doesn't support RIP-relative addressing yet | |
| 3631 emit_opcode(cbuf, 0x0F); | |
| 3632 emit_opcode(cbuf, 0x54); | |
| 3633 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101 | |
| 3634 emit_d32_reloc(cbuf, signmask_address); | |
| 3635 %} | |
| 3636 | |
| 3637 enc_class absD_encoding(regD dst) | |
| 3638 %{ | |
| 3639 int dstenc = $dst$$reg; | |
| 304 | 3640 address signmask_address = (address) StubRoutines::x86::double_sign_mask(); |
| 0 | 3641 |
| 1748 | 3642 cbuf.set_insts_mark(); |
| 0 | 3643 emit_opcode(cbuf, 0x66); |
| 3644 if (dstenc >= 8) { | |
| 3645 emit_opcode(cbuf, Assembler::REX_R); | |
| 3646 dstenc -= 8; | |
| 3647 } | |
| 3648 // XXX reg_mem doesn't support RIP-relative addressing yet | |
| 3649 emit_opcode(cbuf, 0x0F); | |
| 3650 emit_opcode(cbuf, 0x54); | |
| 3651 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101 | |
| 3652 emit_d32_reloc(cbuf, signmask_address); | |
| 3653 %} | |
| 3654 | |
| 3655 enc_class negF_encoding(regF dst) | |
| 3656 %{ | |
| 3657 int dstenc = $dst$$reg; | |
| 304 | 3658 address signflip_address = (address) StubRoutines::x86::float_sign_flip(); |
| 0 | 3659 |
| 1748 | 3660 cbuf.set_insts_mark(); |
| 0 | 3661 if (dstenc >= 8) { |
| 3662 emit_opcode(cbuf, Assembler::REX_R); | |
| 3663 dstenc -= 8; | |
| 3664 } | |
| 3665 // XXX reg_mem doesn't support RIP-relative addressing yet | |
| 3666 emit_opcode(cbuf, 0x0F); | |
| 3667 emit_opcode(cbuf, 0x57); | |
| 3668 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101 | |
| 3669 emit_d32_reloc(cbuf, signflip_address); | |
| 3670 %} | |
| 3671 | |
| 3672 enc_class negD_encoding(regD dst) | |
| 3673 %{ | |
| 3674 int dstenc = $dst$$reg; | |
| 304 | 3675 address signflip_address = (address) StubRoutines::x86::double_sign_flip(); |
| 0 | 3676 |
| 1748 | 3677 cbuf.set_insts_mark(); |
| 0 | 3678 emit_opcode(cbuf, 0x66); |
| 3679 if (dstenc >= 8) { | |
| 3680 emit_opcode(cbuf, Assembler::REX_R); | |
| 3681 dstenc -= 8; | |
| 3682 } | |
| 3683 // XXX reg_mem doesn't support RIP-relative addressing yet | |
| 3684 emit_opcode(cbuf, 0x0F); | |
| 3685 emit_opcode(cbuf, 0x57); | |
| 3686 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101 | |
| 3687 emit_d32_reloc(cbuf, signflip_address); | |
| 3688 %} | |
| 3689 | |
| 3690 enc_class f2i_fixup(rRegI dst, regF src) | |
| 3691 %{ | |
| 3692 int dstenc = $dst$$reg; | |
| 3693 int srcenc = $src$$reg; | |
| 3694 | |
| 3695 // cmpl $dst, #0x80000000 | |
| 3696 if (dstenc >= 8) { | |
| 3697 emit_opcode(cbuf, Assembler::REX_B); | |
| 3698 } | |
| 3699 emit_opcode(cbuf, 0x81); | |
| 3700 emit_rm(cbuf, 0x3, 0x7, dstenc & 7); | |
| 3701 emit_d32(cbuf, 0x80000000); | |
| 3702 | |
| 3703 // jne,s done | |
| 3704 emit_opcode(cbuf, 0x75); | |
| 3705 if (srcenc < 8 && dstenc < 8) { | |
| 3706 emit_d8(cbuf, 0xF); | |
| 3707 } else if (srcenc >= 8 && dstenc >= 8) { | |
| 3708 emit_d8(cbuf, 0x11); | |
| 3709 } else { | |
| 3710 emit_d8(cbuf, 0x10); | |
| 3711 } | |
| 3712 | |
| 3713 // subq rsp, #8 | |
| 3714 emit_opcode(cbuf, Assembler::REX_W); | |
| 3715 emit_opcode(cbuf, 0x83); | |
| 3716 emit_rm(cbuf, 0x3, 0x5, RSP_enc); | |
| 3717 emit_d8(cbuf, 8); | |
| 3718 | |
| 3719 // movss [rsp], $src | |
| 3720 emit_opcode(cbuf, 0xF3); | |
| 3721 if (srcenc >= 8) { | |
| 3722 emit_opcode(cbuf, Assembler::REX_R); | |
| 3723 } | |
| 3724 emit_opcode(cbuf, 0x0F); | |
| 3725 emit_opcode(cbuf, 0x11); | |
| 3726 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes | |
| 3727 | |
| 3728 // call f2i_fixup | |
| 1748 | 3729 cbuf.set_insts_mark(); |
| 0 | 3730 emit_opcode(cbuf, 0xE8); |
| 3731 emit_d32_reloc(cbuf, | |
| 3732 (int) | |
| 1748 | 3733 (StubRoutines::x86::f2i_fixup() - cbuf.insts_end() - 4), |
| 0 | 3734 runtime_call_Relocation::spec(), |
| 3735 RELOC_DISP32); | |
| 3736 | |
| 3737 // popq $dst | |
| 3738 if (dstenc >= 8) { | |
| 3739 emit_opcode(cbuf, Assembler::REX_B); | |
| 3740 } | |
| 3741 emit_opcode(cbuf, 0x58 | (dstenc & 7)); | |
| 3742 | |
| 3743 // done: | |
| 3744 %} | |
| 3745 | |
| 3746 enc_class f2l_fixup(rRegL dst, regF src) | |
| 3747 %{ | |
| 3748 int dstenc = $dst$$reg; | |
| 3749 int srcenc = $src$$reg; | |
| 304 | 3750 address const_address = (address) StubRoutines::x86::double_sign_flip(); |
| 0 | 3751 |
| 3752 // cmpq $dst, [0x8000000000000000] | |
| 1748 | 3753 cbuf.set_insts_mark(); |
| 0 | 3754 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX_W : Assembler::REX_WR); |
| 3755 emit_opcode(cbuf, 0x39); | |
| 3756 // XXX reg_mem doesn't support RIP-relative addressing yet | |
| 3757 emit_rm(cbuf, 0x0, dstenc & 7, 0x5); // 00 reg 101 | |
| 3758 emit_d32_reloc(cbuf, const_address); | |
| 3759 | |
| 3760 | |
| 3761 // jne,s done | |
| 3762 emit_opcode(cbuf, 0x75); | |
| 3763 if (srcenc < 8 && dstenc < 8) { | |
| 3764 emit_d8(cbuf, 0xF); | |
| 3765 } else if (srcenc >= 8 && dstenc >= 8) { | |
| 3766 emit_d8(cbuf, 0x11); | |
| 3767 } else { | |
| 3768 emit_d8(cbuf, 0x10); | |
| 3769 } | |
| 3770 | |
| 3771 // subq rsp, #8 | |
| 3772 emit_opcode(cbuf, Assembler::REX_W); | |
| 3773 emit_opcode(cbuf, 0x83); | |
| 3774 emit_rm(cbuf, 0x3, 0x5, RSP_enc); | |
| 3775 emit_d8(cbuf, 8); | |
| 3776 | |
| 3777 // movss [rsp], $src | |
| 3778 emit_opcode(cbuf, 0xF3); | |
| 3779 if (srcenc >= 8) { | |
| 3780 emit_opcode(cbuf, Assembler::REX_R); | |
| 3781 } | |
| 3782 emit_opcode(cbuf, 0x0F); | |
| 3783 emit_opcode(cbuf, 0x11); | |
| 3784 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes | |
| 3785 | |
| 3786 // call f2l_fixup | |
| 1748 | 3787 cbuf.set_insts_mark(); |
| 0 | 3788 emit_opcode(cbuf, 0xE8); |
| 3789 emit_d32_reloc(cbuf, | |
| 3790 (int) | |
| 1748 | 3791 (StubRoutines::x86::f2l_fixup() - cbuf.insts_end() - 4), |
| 0 | 3792 runtime_call_Relocation::spec(), |
| 3793 RELOC_DISP32); | |
| 3794 | |
| 3795 // popq $dst | |
| 3796 if (dstenc >= 8) { | |
| 3797 emit_opcode(cbuf, Assembler::REX_B); | |
| 3798 } | |
| 3799 emit_opcode(cbuf, 0x58 | (dstenc & 7)); | |
| 3800 | |
| 3801 // done: | |
| 3802 %} | |
| 3803 | |
| 3804 enc_class d2i_fixup(rRegI dst, regD src) | |
| 3805 %{ | |
| 3806 int dstenc = $dst$$reg; | |
| 3807 int srcenc = $src$$reg; | |
| 3808 | |
| 3809 // cmpl $dst, #0x80000000 | |
| 3810 if (dstenc >= 8) { | |
| 3811 emit_opcode(cbuf, Assembler::REX_B); | |
| 3812 } | |
| 3813 emit_opcode(cbuf, 0x81); | |
| 3814 emit_rm(cbuf, 0x3, 0x7, dstenc & 7); | |
| 3815 emit_d32(cbuf, 0x80000000); | |
| 3816 | |
| 3817 // jne,s done | |
| 3818 emit_opcode(cbuf, 0x75); | |
| 3819 if (srcenc < 8 && dstenc < 8) { | |
| 3820 emit_d8(cbuf, 0xF); | |
| 3821 } else if (srcenc >= 8 && dstenc >= 8) { | |
| 3822 emit_d8(cbuf, 0x11); | |
| 3823 } else { | |
| 3824 emit_d8(cbuf, 0x10); | |
| 3825 } | |
| 3826 | |
| 3827 // subq rsp, #8 | |
| 3828 emit_opcode(cbuf, Assembler::REX_W); | |
| 3829 emit_opcode(cbuf, 0x83); | |
| 3830 emit_rm(cbuf, 0x3, 0x5, RSP_enc); | |
| 3831 emit_d8(cbuf, 8); | |
| 3832 | |
| 3833 // movsd [rsp], $src | |
| 3834 emit_opcode(cbuf, 0xF2); | |
| 3835 if (srcenc >= 8) { | |
| 3836 emit_opcode(cbuf, Assembler::REX_R); | |
| 3837 } | |
| 3838 emit_opcode(cbuf, 0x0F); | |
| 3839 emit_opcode(cbuf, 0x11); | |
| 3840 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes | |
| 3841 | |
| 3842 // call d2i_fixup | |
| 1748 | 3843 cbuf.set_insts_mark(); |
| 0 | 3844 emit_opcode(cbuf, 0xE8); |
| 3845 emit_d32_reloc(cbuf, | |
| 3846 (int) | |
| 1748 | 3847 (StubRoutines::x86::d2i_fixup() - cbuf.insts_end() - 4), |
| 0 | 3848 runtime_call_Relocation::spec(), |
| 3849 RELOC_DISP32); | |
| 3850 | |
| 3851 // popq $dst | |
| 3852 if (dstenc >= 8) { | |
| 3853 emit_opcode(cbuf, Assembler::REX_B); | |
| 3854 } | |
| 3855 emit_opcode(cbuf, 0x58 | (dstenc & 7)); | |
| 3856 | |
| 3857 // done: | |
| 3858 %} | |
| 3859 | |
| 3860 enc_class d2l_fixup(rRegL dst, regD src) | |
| 3861 %{ | |
| 3862 int dstenc = $dst$$reg; | |
| 3863 int srcenc = $src$$reg; | |
| 304 | 3864 address const_address = (address) StubRoutines::x86::double_sign_flip(); |
| 0 | 3865 |
| 3866 // cmpq $dst, [0x8000000000000000] | |
| 1748 | 3867 cbuf.set_insts_mark(); |
| 0 | 3868 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX_W : Assembler::REX_WR); |
| 3869 emit_opcode(cbuf, 0x39); | |
| 3870 // XXX reg_mem doesn't support RIP-relative addressing yet | |
| 3871 emit_rm(cbuf, 0x0, dstenc & 7, 0x5); // 00 reg 101 | |
| 3872 emit_d32_reloc(cbuf, const_address); | |
| 3873 | |
| 3874 | |
| 3875 // jne,s done | |
| 3876 emit_opcode(cbuf, 0x75); | |
| 3877 if (srcenc < 8 && dstenc < 8) { | |
| 3878 emit_d8(cbuf, 0xF); | |
| 3879 } else if (srcenc >= 8 && dstenc >= 8) { | |
| 3880 emit_d8(cbuf, 0x11); | |
| 3881 } else { | |
| 3882 emit_d8(cbuf, 0x10); | |
| 3883 } | |
| 3884 | |
| 3885 // subq rsp, #8 | |
| 3886 emit_opcode(cbuf, Assembler::REX_W); | |
| 3887 emit_opcode(cbuf, 0x83); | |
| 3888 emit_rm(cbuf, 0x3, 0x5, RSP_enc); | |
| 3889 emit_d8(cbuf, 8); | |
| 3890 | |
| 3891 // movsd [rsp], $src | |
| 3892 emit_opcode(cbuf, 0xF2); | |
| 3893 if (srcenc >= 8) { | |
| 3894 emit_opcode(cbuf, Assembler::REX_R); | |
| 3895 } | |
| 3896 emit_opcode(cbuf, 0x0F); | |
| 3897 emit_opcode(cbuf, 0x11); | |
| 3898 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes | |
| 3899 | |
| 3900 // call d2l_fixup | |
| 1748 | 3901 cbuf.set_insts_mark(); |
| 0 | 3902 emit_opcode(cbuf, 0xE8); |
| 3903 emit_d32_reloc(cbuf, | |
| 3904 (int) | |
| 1748 | 3905 (StubRoutines::x86::d2l_fixup() - cbuf.insts_end() - 4), |
| 0 | 3906 runtime_call_Relocation::spec(), |
| 3907 RELOC_DISP32); | |
| 3908 | |
| 3909 // popq $dst | |
| 3910 if (dstenc >= 8) { | |
| 3911 emit_opcode(cbuf, Assembler::REX_B); | |
| 3912 } | |
| 3913 emit_opcode(cbuf, 0x58 | (dstenc & 7)); | |
| 3914 | |
| 3915 // done: | |
| 3916 %} | |
| 3917 | |
| 3918 // Safepoint Poll. This polls the safepoint page, and causes an | |
| 3919 // exception if it is not readable. Unfortunately, it kills | |
| 3920 // RFLAGS in the process. | |
| 3921 enc_class enc_safepoint_poll | |
| 3922 %{ | |
| 3923 // testl %rax, off(%rip) // Opcode + ModRM + Disp32 == 6 bytes | |
| 3924 // XXX reg_mem doesn't support RIP-relative addressing yet | |
| 1748 | 3925 cbuf.set_insts_mark(); |
| 3926 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0); // XXX | |
| 0 | 3927 emit_opcode(cbuf, 0x85); // testl |
| 3928 emit_rm(cbuf, 0x0, RAX_enc, 0x5); // 00 rax 101 == 0x5 | |
| 1748 | 3929 // cbuf.insts_mark() is beginning of instruction |
| 0 | 3930 emit_d32_reloc(cbuf, os::get_polling_page()); |
| 3931 // relocInfo::poll_type, | |
| 3932 %} | |
| 3933 %} | |
| 3934 | |
| 3935 | |
|
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|
3936 |
| 0 | 3937 //----------FRAME-------------------------------------------------------------- |
| 3938 // Definition of frame structure and management information. | |
| 3939 // | |
| 3940 // S T A C K L A Y O U T Allocators stack-slot number | |
| 3941 // | (to get allocators register number | |
| 3942 // G Owned by | | v add OptoReg::stack0()) | |
| 3943 // r CALLER | | | |
| 3944 // o | +--------+ pad to even-align allocators stack-slot | |
| 3945 // w V | pad0 | numbers; owned by CALLER | |
| 3946 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned | |
| 3947 // h ^ | in | 5 | |
| 3948 // | | args | 4 Holes in incoming args owned by SELF | |
| 3949 // | | | | 3 | |
| 3950 // | | +--------+ | |
| 3951 // V | | old out| Empty on Intel, window on Sparc | |
| 3952 // | old |preserve| Must be even aligned. | |
| 3953 // | SP-+--------+----> Matcher::_old_SP, even aligned | |
| 3954 // | | in | 3 area for Intel ret address | |
| 3955 // Owned by |preserve| Empty on Sparc. | |
| 3956 // SELF +--------+ | |
| 3957 // | | pad2 | 2 pad to align old SP | |
| 3958 // | +--------+ 1 | |
| 3959 // | | locks | 0 | |
| 3960 // | +--------+----> OptoReg::stack0(), even aligned | |
| 3961 // | | pad1 | 11 pad to align new SP | |
| 3962 // | +--------+ | |
| 3963 // | | | 10 | |
| 3964 // | | spills | 9 spills | |
| 3965 // V | | 8 (pad0 slot for callee) | |
| 3966 // -----------+--------+----> Matcher::_out_arg_limit, unaligned | |
| 3967 // ^ | out | 7 | |
| 3968 // | | args | 6 Holes in outgoing args owned by CALLEE | |
| 3969 // Owned by +--------+ | |
| 3970 // CALLEE | new out| 6 Empty on Intel, window on Sparc | |
| 3971 // | new |preserve| Must be even-aligned. | |
| 3972 // | SP-+--------+----> Matcher::_new_SP, even aligned | |
| 3973 // | | | | |
| 3974 // | |
| 3975 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is | |
| 3976 // known from SELF's arguments and the Java calling convention. | |
| 3977 // Region 6-7 is determined per call site. | |
| 3978 // Note 2: If the calling convention leaves holes in the incoming argument | |
| 3979 // area, those holes are owned by SELF. Holes in the outgoing area | |
| 3980 // are owned by the CALLEE. Holes should not be nessecary in the | |
| 3981 // incoming area, as the Java calling convention is completely under | |
| 3982 // the control of the AD file. Doubles can be sorted and packed to | |
| 3983 // avoid holes. Holes in the outgoing arguments may be nessecary for | |
| 3984 // varargs C calling conventions. | |
| 3985 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is | |
| 3986 // even aligned with pad0 as needed. | |
| 3987 // Region 6 is even aligned. Region 6-7 is NOT even aligned; | |
| 3988 // region 6-11 is even aligned; it may be padded out more so that | |
| 3989 // the region from SP to FP meets the minimum stack alignment. | |
| 3990 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack | |
| 3991 // alignment. Region 11, pad1, may be dynamically extended so that | |
| 3992 // SP meets the minimum alignment. | |
| 3993 | |
| 3994 frame | |
| 3995 %{ | |
| 3996 // What direction does stack grow in (assumed to be same for C & Java) | |
| 3997 stack_direction(TOWARDS_LOW); | |
| 3998 | |
| 3999 // These three registers define part of the calling convention | |
| 4000 // between compiled code and the interpreter. | |
| 4001 inline_cache_reg(RAX); // Inline Cache Register | |
| 4002 interpreter_method_oop_reg(RBX); // Method Oop Register when | |
| 4003 // calling interpreter | |
| 4004 | |
| 4005 // Optional: name the operand used by cisc-spilling to access | |
| 4006 // [stack_pointer + offset] | |
| 4007 cisc_spilling_operand_name(indOffset32); | |
| 4008 | |
| 4009 // Number of stack slots consumed by locking an object | |
| 4010 sync_stack_slots(2); | |
| 4011 | |
| 4012 // Compiled code's Frame Pointer | |
| 4013 frame_pointer(RSP); | |
| 4014 | |
| 4015 // Interpreter stores its frame pointer in a register which is | |
| 4016 // stored to the stack by I2CAdaptors. | |
| 4017 // I2CAdaptors convert from interpreted java to compiled java. | |
| 4018 interpreter_frame_pointer(RBP); | |
| 4019 | |
| 4020 // Stack alignment requirement | |
| 4021 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes) | |
| 4022 | |
| 4023 // Number of stack slots between incoming argument block and the start of | |
| 4024 // a new frame. The PROLOG must add this many slots to the stack. The | |
| 4025 // EPILOG must remove this many slots. amd64 needs two slots for | |
| 4026 // return address. | |
| 4027 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls); | |
| 4028 | |
| 4029 // Number of outgoing stack slots killed above the out_preserve_stack_slots | |
| 4030 // for calls to C. Supports the var-args backing area for register parms. | |
| 4031 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt); | |
| 4032 | |
| 4033 // The after-PROLOG location of the return address. Location of | |
| 4034 // return address specifies a type (REG or STACK) and a number | |
| 4035 // representing the register number (i.e. - use a register name) or | |
| 4036 // stack slot. | |
| 4037 // Ret Addr is on stack in slot 0 if no locks or verification or alignment. | |
| 4038 // Otherwise, it is above the locks and verification slot and alignment word | |
| 4039 return_addr(STACK - 2 + | |
| 4040 round_to(2 + 2 * VerifyStackAtCalls + | |
| 4041 Compile::current()->fixed_slots(), | |
| 4042 WordsPerLong * 2)); | |
| 4043 | |
| 4044 // Body of function which returns an integer array locating | |
| 4045 // arguments either in registers or in stack slots. Passed an array | |
| 4046 // of ideal registers called "sig" and a "length" count. Stack-slot | |
| 4047 // offsets are based on outgoing arguments, i.e. a CALLER setting up | |
| 4048 // arguments for a CALLEE. Incoming stack arguments are | |
| 4049 // automatically biased by the preserve_stack_slots field above. | |
| 4050 | |
| 4051 calling_convention | |
| 4052 %{ | |
| 4053 // No difference between ingoing/outgoing just pass false | |
| 4054 SharedRuntime::java_calling_convention(sig_bt, regs, length, false); | |
| 4055 %} | |
| 4056 | |
| 4057 c_calling_convention | |
| 4058 %{ | |
| 4059 // This is obviously always outgoing | |
| 4060 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); | |
| 4061 %} | |
| 4062 | |
| 4063 // Location of compiled Java return values. Same as C for now. | |
| 4064 return_value | |
| 4065 %{ | |
| 4066 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, | |
| 4067 "only return normal values"); | |
| 4068 | |
| 4069 static const int lo[Op_RegL + 1] = { | |
| 4070 0, | |
| 4071 0, | |
|
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4072 RAX_num, // Op_RegN |
| 0 | 4073 RAX_num, // Op_RegI |
| 4074 RAX_num, // Op_RegP | |
| 4075 XMM0_num, // Op_RegF | |
| 4076 XMM0_num, // Op_RegD | |
| 4077 RAX_num // Op_RegL | |
| 4078 }; | |
| 4079 static const int hi[Op_RegL + 1] = { | |
| 4080 0, | |
| 4081 0, | |
|
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4082 OptoReg::Bad, // Op_RegN |
| 0 | 4083 OptoReg::Bad, // Op_RegI |
| 4084 RAX_H_num, // Op_RegP | |
| 4085 OptoReg::Bad, // Op_RegF | |
| 4086 XMM0_H_num, // Op_RegD | |
| 4087 RAX_H_num // Op_RegL | |
| 4088 }; | |
|
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4089 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 1, "missing type"); |
| 0 | 4090 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]); |
| 4091 %} | |
| 4092 %} | |
| 4093 | |
| 4094 //----------ATTRIBUTES--------------------------------------------------------- | |
| 4095 //----------Operand Attributes------------------------------------------------- | |
| 4096 op_attrib op_cost(0); // Required cost attribute | |
| 4097 | |
| 4098 //----------Instruction Attributes--------------------------------------------- | |
| 4099 ins_attrib ins_cost(100); // Required cost attribute | |
| 4100 ins_attrib ins_size(8); // Required size attribute (in bits) | |
| 4101 ins_attrib ins_pc_relative(0); // Required PC Relative flag | |
| 4102 ins_attrib ins_short_branch(0); // Required flag: is this instruction | |
| 4103 // a non-matching short branch variant | |
| 4104 // of some long branch? | |
| 4105 ins_attrib ins_alignment(1); // Required alignment attribute (must | |
| 4106 // be a power of 2) specifies the | |
| 4107 // alignment that some part of the | |
| 4108 // instruction (not necessarily the | |
| 4109 // start) requires. If > 1, a | |
| 4110 // compute_padding() function must be | |
| 4111 // provided for the instruction | |
| 4112 | |
| 4113 //----------OPERANDS----------------------------------------------------------- | |
| 4114 // Operand definitions must precede instruction definitions for correct parsing | |
| 4115 // in the ADLC because operands constitute user defined types which are used in | |
| 4116 // instruction definitions. | |
| 4117 | |
| 4118 //----------Simple Operands---------------------------------------------------- | |
| 4119 // Immediate Operands | |
| 4120 // Integer Immediate | |
| 4121 operand immI() | |
| 4122 %{ | |
| 4123 match(ConI); | |
| 4124 | |
| 4125 op_cost(10); | |
| 4126 format %{ %} | |
| 4127 interface(CONST_INTER); | |
| 4128 %} | |
| 4129 | |
| 4130 // Constant for test vs zero | |
| 4131 operand immI0() | |
| 4132 %{ | |
| 4133 predicate(n->get_int() == 0); | |
| 4134 match(ConI); | |
| 4135 | |
| 4136 op_cost(0); | |
| 4137 format %{ %} | |
| 4138 interface(CONST_INTER); | |
| 4139 %} | |
| 4140 | |
| 4141 // Constant for increment | |
| 4142 operand immI1() | |
| 4143 %{ | |
| 4144 predicate(n->get_int() == 1); | |
| 4145 match(ConI); | |
| 4146 | |
| 4147 op_cost(0); | |
| 4148 format %{ %} | |
| 4149 interface(CONST_INTER); | |
| 4150 %} | |
| 4151 | |
| 4152 // Constant for decrement | |
| 4153 operand immI_M1() | |
| 4154 %{ | |
| 4155 predicate(n->get_int() == -1); | |
| 4156 match(ConI); | |
| 4157 | |
| 4158 op_cost(0); | |
| 4159 format %{ %} | |
| 4160 interface(CONST_INTER); | |
| 4161 %} | |
| 4162 | |
| 4163 // Valid scale values for addressing modes | |
| 4164 operand immI2() | |
| 4165 %{ | |
| 4166 predicate(0 <= n->get_int() && (n->get_int() <= 3)); | |
| 4167 match(ConI); | |
| 4168 | |
| 4169 format %{ %} | |
| 4170 interface(CONST_INTER); | |
| 4171 %} | |
| 4172 | |
| 4173 operand immI8() | |
| 4174 %{ | |
| 4175 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80)); | |
| 4176 match(ConI); | |
| 4177 | |
| 4178 op_cost(5); | |
| 4179 format %{ %} | |
| 4180 interface(CONST_INTER); | |
| 4181 %} | |
| 4182 | |
| 4183 operand immI16() | |
| 4184 %{ | |
| 4185 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767)); | |
| 4186 match(ConI); | |
| 4187 | |
| 4188 op_cost(10); | |
| 4189 format %{ %} | |
| 4190 interface(CONST_INTER); | |
| 4191 %} | |
| 4192 | |
| 4193 // Constant for long shifts | |
| 4194 operand immI_32() | |
| 4195 %{ | |
| 4196 predicate( n->get_int() == 32 ); | |
| 4197 match(ConI); | |
| 4198 | |
| 4199 op_cost(0); | |
| 4200 format %{ %} | |
| 4201 interface(CONST_INTER); | |
| 4202 %} | |
| 4203 | |
| 4204 // Constant for long shifts | |
| 4205 operand immI_64() | |
| 4206 %{ | |
| 4207 predicate( n->get_int() == 64 ); | |
| 4208 match(ConI); | |
| 4209 | |
| 4210 op_cost(0); | |
| 4211 format %{ %} | |
| 4212 interface(CONST_INTER); | |
| 4213 %} | |
| 4214 | |
| 4215 // Pointer Immediate | |
| 4216 operand immP() | |
| 4217 %{ | |
| 4218 match(ConP); | |
| 4219 | |
| 4220 op_cost(10); | |
| 4221 format %{ %} | |
| 4222 interface(CONST_INTER); | |
| 4223 %} | |
| 4224 | |
| 4225 // NULL Pointer Immediate | |
| 4226 operand immP0() | |
| 4227 %{ | |
| 4228 predicate(n->get_ptr() == 0); | |
| 4229 match(ConP); | |
| 4230 | |
| 4231 op_cost(5); | |
| 4232 format %{ %} | |
| 4233 interface(CONST_INTER); | |
| 4234 %} | |
| 4235 | |
|
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4236 // Pointer Immediate |
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4237 operand immN() %{ |
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4238 match(ConN); |
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4239 |
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4240 op_cost(10); |
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4241 format %{ %} |
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4242 interface(CONST_INTER); |
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4243 %} |
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4244 |
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4245 // NULL Pointer Immediate |
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4246 operand immN0() %{ |
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4247 predicate(n->get_narrowcon() == 0); |
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4248 match(ConN); |
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4249 |
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4250 op_cost(5); |
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4251 format %{ %} |
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4252 interface(CONST_INTER); |
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4253 %} |
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4254 |
| 0 | 4255 operand immP31() |
| 4256 %{ | |
| 4257 predicate(!n->as_Type()->type()->isa_oopptr() | |
| 4258 && (n->get_ptr() >> 31) == 0); | |
| 4259 match(ConP); | |
| 4260 | |
| 4261 op_cost(5); | |
| 4262 format %{ %} | |
| 4263 interface(CONST_INTER); | |
| 4264 %} | |
| 4265 | |
|
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4266 |
| 0 | 4267 // Long Immediate |
| 4268 operand immL() | |
| 4269 %{ | |
| 4270 match(ConL); | |
| 4271 | |
| 4272 op_cost(20); | |
| 4273 format %{ %} | |
| 4274 interface(CONST_INTER); | |
| 4275 %} | |
| 4276 | |
| 4277 // Long Immediate 8-bit | |
| 4278 operand immL8() | |
| 4279 %{ | |
| 4280 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L); | |
| 4281 match(ConL); | |
| 4282 | |
| 4283 op_cost(5); | |
| 4284 format %{ %} | |
| 4285 interface(CONST_INTER); | |
| 4286 %} | |
| 4287 | |
| 4288 // Long Immediate 32-bit unsigned | |
| 4289 operand immUL32() | |
| 4290 %{ | |
| 4291 predicate(n->get_long() == (unsigned int) (n->get_long())); | |
| 4292 match(ConL); | |
| 4293 | |
| 4294 op_cost(10); | |
| 4295 format %{ %} | |
| 4296 interface(CONST_INTER); | |
| 4297 %} | |
| 4298 | |
| 4299 // Long Immediate 32-bit signed | |
| 4300 operand immL32() | |
| 4301 %{ | |
| 4302 predicate(n->get_long() == (int) (n->get_long())); | |
| 4303 match(ConL); | |
| 4304 | |
| 4305 op_cost(15); | |
| 4306 format %{ %} | |
| 4307 interface(CONST_INTER); | |
| 4308 %} | |
| 4309 | |
| 4310 // Long Immediate zero | |
| 4311 operand immL0() | |
| 4312 %{ | |
| 4313 predicate(n->get_long() == 0L); | |
| 4314 match(ConL); | |
| 4315 | |
| 4316 op_cost(10); | |
| 4317 format %{ %} | |
| 4318 interface(CONST_INTER); | |
| 4319 %} | |
| 4320 | |
| 4321 // Constant for increment | |
| 4322 operand immL1() | |
| 4323 %{ | |
| 4324 predicate(n->get_long() == 1); | |
| 4325 match(ConL); | |
| 4326 | |
| 4327 format %{ %} | |
| 4328 interface(CONST_INTER); | |
| 4329 %} | |
| 4330 | |
| 4331 // Constant for decrement | |
| 4332 operand immL_M1() | |
| 4333 %{ | |
| 4334 predicate(n->get_long() == -1); | |
| 4335 match(ConL); | |
| 4336 | |
| 4337 format %{ %} | |
| 4338 interface(CONST_INTER); | |
| 4339 %} | |
| 4340 | |
| 4341 // Long Immediate: the value 10 | |
| 4342 operand immL10() | |
| 4343 %{ | |
| 4344 predicate(n->get_long() == 10); | |
| 4345 match(ConL); | |
| 4346 | |
| 4347 format %{ %} | |
| 4348 interface(CONST_INTER); | |
| 4349 %} | |
| 4350 | |
| 4351 // Long immediate from 0 to 127. | |
| 4352 // Used for a shorter form of long mul by 10. | |
| 4353 operand immL_127() | |
| 4354 %{ | |
| 4355 predicate(0 <= n->get_long() && n->get_long() < 0x80); | |
| 4356 match(ConL); | |
| 4357 | |
| 4358 op_cost(10); | |
| 4359 format %{ %} | |
| 4360 interface(CONST_INTER); | |
| 4361 %} | |
| 4362 | |
| 4363 // Long Immediate: low 32-bit mask | |
| 4364 operand immL_32bits() | |
| 4365 %{ | |
| 4366 predicate(n->get_long() == 0xFFFFFFFFL); | |
| 4367 match(ConL); | |
| 4368 op_cost(20); | |
| 4369 | |
| 4370 format %{ %} | |
| 4371 interface(CONST_INTER); | |
| 4372 %} | |
| 4373 | |
| 4374 // Float Immediate zero | |
| 4375 operand immF0() | |
| 4376 %{ | |
| 4377 predicate(jint_cast(n->getf()) == 0); | |
| 4378 match(ConF); | |
| 4379 | |
| 4380 op_cost(5); | |
| 4381 format %{ %} | |
| 4382 interface(CONST_INTER); | |
| 4383 %} | |
| 4384 | |
| 4385 // Float Immediate | |
| 4386 operand immF() | |
| 4387 %{ | |
| 4388 match(ConF); | |
| 4389 | |
| 4390 op_cost(15); | |
| 4391 format %{ %} | |
| 4392 interface(CONST_INTER); | |
| 4393 %} | |
| 4394 | |
| 4395 // Double Immediate zero | |
| 4396 operand immD0() | |
| 4397 %{ | |
| 4398 predicate(jlong_cast(n->getd()) == 0); | |
| 4399 match(ConD); | |
| 4400 | |
| 4401 op_cost(5); | |
| 4402 format %{ %} | |
| 4403 interface(CONST_INTER); | |
| 4404 %} | |
| 4405 | |
| 4406 // Double Immediate | |
| 4407 operand immD() | |
| 4408 %{ | |
| 4409 match(ConD); | |
| 4410 | |
| 4411 op_cost(15); | |
| 4412 format %{ %} | |
| 4413 interface(CONST_INTER); | |
| 4414 %} | |
| 4415 | |
| 4416 // Immediates for special shifts (sign extend) | |
| 4417 | |
| 4418 // Constants for increment | |
| 4419 operand immI_16() | |
| 4420 %{ | |
| 4421 predicate(n->get_int() == 16); | |
| 4422 match(ConI); | |
| 4423 | |
| 4424 format %{ %} | |
| 4425 interface(CONST_INTER); | |
| 4426 %} | |
| 4427 | |
| 4428 operand immI_24() | |
| 4429 %{ | |
| 4430 predicate(n->get_int() == 24); | |
| 4431 match(ConI); | |
| 4432 | |
| 4433 format %{ %} | |
| 4434 interface(CONST_INTER); | |
| 4435 %} | |
| 4436 | |
| 4437 // Constant for byte-wide masking | |
| 4438 operand immI_255() | |
| 4439 %{ | |
| 4440 predicate(n->get_int() == 255); | |
| 4441 match(ConI); | |
| 4442 | |
| 4443 format %{ %} | |
| 4444 interface(CONST_INTER); | |
| 4445 %} | |
| 4446 | |
| 4447 // Constant for short-wide masking | |
| 4448 operand immI_65535() | |
| 4449 %{ | |
| 4450 predicate(n->get_int() == 65535); | |
| 4451 match(ConI); | |
| 4452 | |
| 4453 format %{ %} | |
| 4454 interface(CONST_INTER); | |
| 4455 %} | |
| 4456 | |
| 4457 // Constant for byte-wide masking | |
| 4458 operand immL_255() | |
| 4459 %{ | |
| 4460 predicate(n->get_long() == 255); | |
| 4461 match(ConL); | |
| 4462 | |
| 4463 format %{ %} | |
| 4464 interface(CONST_INTER); | |
| 4465 %} | |
| 4466 | |
| 4467 // Constant for short-wide masking | |
| 4468 operand immL_65535() | |
| 4469 %{ | |
| 4470 predicate(n->get_long() == 65535); | |
| 4471 match(ConL); | |
| 4472 | |
| 4473 format %{ %} | |
| 4474 interface(CONST_INTER); | |
| 4475 %} | |
| 4476 | |
| 4477 // Register Operands | |
| 4478 // Integer Register | |
| 4479 operand rRegI() | |
| 4480 %{ | |
| 4481 constraint(ALLOC_IN_RC(int_reg)); | |
| 4482 match(RegI); | |
| 4483 | |
| 4484 match(rax_RegI); | |
| 4485 match(rbx_RegI); | |
| 4486 match(rcx_RegI); | |
| 4487 match(rdx_RegI); | |
| 4488 match(rdi_RegI); | |
| 4489 | |
| 4490 format %{ %} | |
| 4491 interface(REG_INTER); | |
| 4492 %} | |
| 4493 | |
| 4494 // Special Registers | |
| 4495 operand rax_RegI() | |
| 4496 %{ | |
| 4497 constraint(ALLOC_IN_RC(int_rax_reg)); | |
| 4498 match(RegI); | |
| 4499 match(rRegI); | |
| 4500 | |
| 4501 format %{ "RAX" %} | |
| 4502 interface(REG_INTER); | |
| 4503 %} | |
| 4504 | |
| 4505 // Special Registers | |
| 4506 operand rbx_RegI() | |
| 4507 %{ | |
| 4508 constraint(ALLOC_IN_RC(int_rbx_reg)); | |
| 4509 match(RegI); | |
| 4510 match(rRegI); | |
| 4511 | |
| 4512 format %{ "RBX" %} | |
| 4513 interface(REG_INTER); | |
| 4514 %} | |
| 4515 | |
| 4516 operand rcx_RegI() | |
| 4517 %{ | |
| 4518 constraint(ALLOC_IN_RC(int_rcx_reg)); | |
| 4519 match(RegI); | |
| 4520 match(rRegI); | |
| 4521 | |
| 4522 format %{ "RCX" %} | |
| 4523 interface(REG_INTER); | |
| 4524 %} | |
| 4525 | |
| 4526 operand rdx_RegI() | |
| 4527 %{ | |
| 4528 constraint(ALLOC_IN_RC(int_rdx_reg)); | |
| 4529 match(RegI); | |
| 4530 match(rRegI); | |
| 4531 | |
| 4532 format %{ "RDX" %} | |
| 4533 interface(REG_INTER); | |
| 4534 %} | |
| 4535 | |
| 4536 operand rdi_RegI() | |
| 4537 %{ | |
| 4538 constraint(ALLOC_IN_RC(int_rdi_reg)); | |
| 4539 match(RegI); | |
| 4540 match(rRegI); | |
| 4541 | |
| 4542 format %{ "RDI" %} | |
| 4543 interface(REG_INTER); | |
| 4544 %} | |
| 4545 | |
| 4546 operand no_rcx_RegI() | |
| 4547 %{ | |
| 4548 constraint(ALLOC_IN_RC(int_no_rcx_reg)); | |
| 4549 match(RegI); | |
| 4550 match(rax_RegI); | |
| 4551 match(rbx_RegI); | |
| 4552 match(rdx_RegI); | |
| 4553 match(rdi_RegI); | |
| 4554 | |
| 4555 format %{ %} | |
| 4556 interface(REG_INTER); | |
| 4557 %} | |
| 4558 | |
| 4559 operand no_rax_rdx_RegI() | |
| 4560 %{ | |
| 4561 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg)); | |
| 4562 match(RegI); | |
| 4563 match(rbx_RegI); | |
| 4564 match(rcx_RegI); | |
| 4565 match(rdi_RegI); | |
| 4566 | |
| 4567 format %{ %} | |
| 4568 interface(REG_INTER); | |
| 4569 %} | |
| 4570 | |
| 4571 // Pointer Register | |
| 4572 operand any_RegP() | |
| 4573 %{ | |
| 4574 constraint(ALLOC_IN_RC(any_reg)); | |
| 4575 match(RegP); | |
| 4576 match(rax_RegP); | |
| 4577 match(rbx_RegP); | |
| 4578 match(rdi_RegP); | |
| 4579 match(rsi_RegP); | |
| 4580 match(rbp_RegP); | |
| 4581 match(r15_RegP); | |
| 4582 match(rRegP); | |
| 4583 | |
| 4584 format %{ %} | |
| 4585 interface(REG_INTER); | |
| 4586 %} | |
| 4587 | |
| 4588 operand rRegP() | |
| 4589 %{ | |
| 4590 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 4591 match(RegP); | |
| 4592 match(rax_RegP); | |
| 4593 match(rbx_RegP); | |
| 4594 match(rdi_RegP); | |
| 4595 match(rsi_RegP); | |
| 4596 match(rbp_RegP); | |
| 4597 match(r15_RegP); // See Q&A below about r15_RegP. | |
| 4598 | |
| 4599 format %{ %} | |
| 4600 interface(REG_INTER); | |
| 4601 %} | |
| 4602 | |
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4603 operand rRegN() %{ |
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4604 constraint(ALLOC_IN_RC(int_reg)); |
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4605 match(RegN); |
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4606 |
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|
4607 format %{ %} |
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4608 interface(REG_INTER); |
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4609 %} |
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4610 |
| 0 | 4611 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP? |
| 4612 // Answer: Operand match rules govern the DFA as it processes instruction inputs. | |
| 4613 // It's fine for an instruction input which expects rRegP to match a r15_RegP. | |
| 4614 // The output of an instruction is controlled by the allocator, which respects | |
| 4615 // register class masks, not match rules. Unless an instruction mentions | |
| 4616 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered | |
| 4617 // by the allocator as an input. | |
| 4618 | |
| 4619 operand no_rax_RegP() | |
| 4620 %{ | |
| 4621 constraint(ALLOC_IN_RC(ptr_no_rax_reg)); | |
| 4622 match(RegP); | |
| 4623 match(rbx_RegP); | |
| 4624 match(rsi_RegP); | |
| 4625 match(rdi_RegP); | |
| 4626 | |
| 4627 format %{ %} | |
| 4628 interface(REG_INTER); | |
| 4629 %} | |
| 4630 | |
| 4631 operand no_rbp_RegP() | |
| 4632 %{ | |
| 4633 constraint(ALLOC_IN_RC(ptr_no_rbp_reg)); | |
| 4634 match(RegP); | |
| 4635 match(rbx_RegP); | |
| 4636 match(rsi_RegP); | |
| 4637 match(rdi_RegP); | |
| 4638 | |
| 4639 format %{ %} | |
| 4640 interface(REG_INTER); | |
| 4641 %} | |
| 4642 | |
| 4643 operand no_rax_rbx_RegP() | |
| 4644 %{ | |
| 4645 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg)); | |
| 4646 match(RegP); | |
| 4647 match(rsi_RegP); | |
| 4648 match(rdi_RegP); | |
| 4649 | |
| 4650 format %{ %} | |
| 4651 interface(REG_INTER); | |
| 4652 %} | |
| 4653 | |
| 4654 // Special Registers | |
| 4655 // Return a pointer value | |
| 4656 operand rax_RegP() | |
| 4657 %{ | |
| 4658 constraint(ALLOC_IN_RC(ptr_rax_reg)); | |
| 4659 match(RegP); | |
| 4660 match(rRegP); | |
| 4661 | |
| 4662 format %{ %} | |
| 4663 interface(REG_INTER); | |
| 4664 %} | |
| 4665 | |
|
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4666 // Special Registers |
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4667 // Return a compressed pointer value |
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4668 operand rax_RegN() |
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4669 %{ |
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4670 constraint(ALLOC_IN_RC(int_rax_reg)); |
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4671 match(RegN); |
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4672 match(rRegN); |
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|
4673 |
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|
4674 format %{ %} |
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4675 interface(REG_INTER); |
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4676 %} |
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|
4677 |
| 0 | 4678 // Used in AtomicAdd |
| 4679 operand rbx_RegP() | |
| 4680 %{ | |
| 4681 constraint(ALLOC_IN_RC(ptr_rbx_reg)); | |
| 4682 match(RegP); | |
| 4683 match(rRegP); | |
| 4684 | |
| 4685 format %{ %} | |
| 4686 interface(REG_INTER); | |
| 4687 %} | |
| 4688 | |
| 4689 operand rsi_RegP() | |
| 4690 %{ | |
| 4691 constraint(ALLOC_IN_RC(ptr_rsi_reg)); | |
| 4692 match(RegP); | |
| 4693 match(rRegP); | |
| 4694 | |
| 4695 format %{ %} | |
| 4696 interface(REG_INTER); | |
| 4697 %} | |
| 4698 | |
| 4699 // Used in rep stosq | |
| 4700 operand rdi_RegP() | |
| 4701 %{ | |
| 4702 constraint(ALLOC_IN_RC(ptr_rdi_reg)); | |
| 4703 match(RegP); | |
| 4704 match(rRegP); | |
| 4705 | |
| 4706 format %{ %} | |
| 4707 interface(REG_INTER); | |
| 4708 %} | |
| 4709 | |
| 4710 operand rbp_RegP() | |
| 4711 %{ | |
| 4712 constraint(ALLOC_IN_RC(ptr_rbp_reg)); | |
| 4713 match(RegP); | |
| 4714 match(rRegP); | |
| 4715 | |
| 4716 format %{ %} | |
| 4717 interface(REG_INTER); | |
| 4718 %} | |
| 4719 | |
| 4720 operand r15_RegP() | |
| 4721 %{ | |
| 4722 constraint(ALLOC_IN_RC(ptr_r15_reg)); | |
| 4723 match(RegP); | |
| 4724 match(rRegP); | |
| 4725 | |
| 4726 format %{ %} | |
| 4727 interface(REG_INTER); | |
| 4728 %} | |
| 4729 | |
| 4730 operand rRegL() | |
| 4731 %{ | |
| 4732 constraint(ALLOC_IN_RC(long_reg)); | |
| 4733 match(RegL); | |
| 4734 match(rax_RegL); | |
| 4735 match(rdx_RegL); | |
| 4736 | |
| 4737 format %{ %} | |
| 4738 interface(REG_INTER); | |
| 4739 %} | |
| 4740 | |
| 4741 // Special Registers | |
| 4742 operand no_rax_rdx_RegL() | |
| 4743 %{ | |
| 4744 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg)); | |
| 4745 match(RegL); | |
| 4746 match(rRegL); | |
| 4747 | |
| 4748 format %{ %} | |
| 4749 interface(REG_INTER); | |
| 4750 %} | |
| 4751 | |
| 4752 operand no_rax_RegL() | |
| 4753 %{ | |
| 4754 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg)); | |
| 4755 match(RegL); | |
| 4756 match(rRegL); | |
| 4757 match(rdx_RegL); | |
| 4758 | |
| 4759 format %{ %} | |
| 4760 interface(REG_INTER); | |
| 4761 %} | |
| 4762 | |
| 4763 operand no_rcx_RegL() | |
| 4764 %{ | |
| 4765 constraint(ALLOC_IN_RC(long_no_rcx_reg)); | |
| 4766 match(RegL); | |
| 4767 match(rRegL); | |
| 4768 | |
| 4769 format %{ %} | |
| 4770 interface(REG_INTER); | |
| 4771 %} | |
| 4772 | |
| 4773 operand rax_RegL() | |
| 4774 %{ | |
| 4775 constraint(ALLOC_IN_RC(long_rax_reg)); | |
| 4776 match(RegL); | |
| 4777 match(rRegL); | |
| 4778 | |
| 4779 format %{ "RAX" %} | |
| 4780 interface(REG_INTER); | |
| 4781 %} | |
| 4782 | |
| 4783 operand rcx_RegL() | |
| 4784 %{ | |
| 4785 constraint(ALLOC_IN_RC(long_rcx_reg)); | |
| 4786 match(RegL); | |
| 4787 match(rRegL); | |
| 4788 | |
| 4789 format %{ %} | |
| 4790 interface(REG_INTER); | |
| 4791 %} | |
| 4792 | |
| 4793 operand rdx_RegL() | |
| 4794 %{ | |
| 4795 constraint(ALLOC_IN_RC(long_rdx_reg)); | |
| 4796 match(RegL); | |
| 4797 match(rRegL); | |
| 4798 | |
| 4799 format %{ %} | |
| 4800 interface(REG_INTER); | |
| 4801 %} | |
| 4802 | |
| 4803 // Flags register, used as output of compare instructions | |
| 4804 operand rFlagsReg() | |
| 4805 %{ | |
| 4806 constraint(ALLOC_IN_RC(int_flags)); | |
| 4807 match(RegFlags); | |
| 4808 | |
| 4809 format %{ "RFLAGS" %} | |
| 4810 interface(REG_INTER); | |
| 4811 %} | |
| 4812 | |
| 4813 // Flags register, used as output of FLOATING POINT compare instructions | |
| 4814 operand rFlagsRegU() | |
| 4815 %{ | |
| 4816 constraint(ALLOC_IN_RC(int_flags)); | |
| 4817 match(RegFlags); | |
| 4818 | |
| 4819 format %{ "RFLAGS_U" %} | |
| 4820 interface(REG_INTER); | |
| 4821 %} | |
| 4822 | |
|
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4823 operand rFlagsRegUCF() %{ |
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4824 constraint(ALLOC_IN_RC(int_flags)); |
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4825 match(RegFlags); |
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|
4826 predicate(false); |
|
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|
4827 |
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4828 format %{ "RFLAGS_U_CF" %} |
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4829 interface(REG_INTER); |
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4830 %} |
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4831 |
| 0 | 4832 // Float register operands |
| 4833 operand regF() | |
| 4834 %{ | |
| 4835 constraint(ALLOC_IN_RC(float_reg)); | |
| 4836 match(RegF); | |
| 4837 | |
| 4838 format %{ %} | |
| 4839 interface(REG_INTER); | |
| 4840 %} | |
| 4841 | |
| 4842 // Double register operands | |
| 681 | 4843 operand regD() |
| 0 | 4844 %{ |
| 4845 constraint(ALLOC_IN_RC(double_reg)); | |
| 4846 match(RegD); | |
| 4847 | |
| 4848 format %{ %} | |
| 4849 interface(REG_INTER); | |
| 4850 %} | |
| 4851 | |
| 4852 | |
| 4853 //----------Memory Operands---------------------------------------------------- | |
| 4854 // Direct Memory Operand | |
| 4855 // operand direct(immP addr) | |
| 4856 // %{ | |
| 4857 // match(addr); | |
| 4858 | |
| 4859 // format %{ "[$addr]" %} | |
| 4860 // interface(MEMORY_INTER) %{ | |
| 4861 // base(0xFFFFFFFF); | |
| 4862 // index(0x4); | |
| 4863 // scale(0x0); | |
| 4864 // disp($addr); | |
| 4865 // %} | |
| 4866 // %} | |
| 4867 | |
| 4868 // Indirect Memory Operand | |
| 4869 operand indirect(any_RegP reg) | |
| 4870 %{ | |
| 4871 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 4872 match(reg); | |
| 4873 | |
| 4874 format %{ "[$reg]" %} | |
| 4875 interface(MEMORY_INTER) %{ | |
| 4876 base($reg); | |
| 4877 index(0x4); | |
| 4878 scale(0x0); | |
| 4879 disp(0x0); | |
| 4880 %} | |
| 4881 %} | |
| 4882 | |
| 4883 // Indirect Memory Plus Short Offset Operand | |
| 4884 operand indOffset8(any_RegP reg, immL8 off) | |
| 4885 %{ | |
| 4886 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 4887 match(AddP reg off); | |
| 4888 | |
| 4889 format %{ "[$reg + $off (8-bit)]" %} | |
| 4890 interface(MEMORY_INTER) %{ | |
| 4891 base($reg); | |
| 4892 index(0x4); | |
| 4893 scale(0x0); | |
| 4894 disp($off); | |
| 4895 %} | |
| 4896 %} | |
| 4897 | |
| 4898 // Indirect Memory Plus Long Offset Operand | |
| 4899 operand indOffset32(any_RegP reg, immL32 off) | |
| 4900 %{ | |
| 4901 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 4902 match(AddP reg off); | |
| 4903 | |
| 4904 format %{ "[$reg + $off (32-bit)]" %} | |
| 4905 interface(MEMORY_INTER) %{ | |
| 4906 base($reg); | |
| 4907 index(0x4); | |
| 4908 scale(0x0); | |
| 4909 disp($off); | |
| 4910 %} | |
| 4911 %} | |
| 4912 | |
| 4913 // Indirect Memory Plus Index Register Plus Offset Operand | |
| 4914 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off) | |
| 4915 %{ | |
| 4916 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 4917 match(AddP (AddP reg lreg) off); | |
| 4918 | |
| 4919 op_cost(10); | |
| 4920 format %{"[$reg + $off + $lreg]" %} | |
| 4921 interface(MEMORY_INTER) %{ | |
| 4922 base($reg); | |
| 4923 index($lreg); | |
| 4924 scale(0x0); | |
| 4925 disp($off); | |
| 4926 %} | |
| 4927 %} | |
| 4928 | |
| 4929 // Indirect Memory Plus Index Register Plus Offset Operand | |
| 4930 operand indIndex(any_RegP reg, rRegL lreg) | |
| 4931 %{ | |
| 4932 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 4933 match(AddP reg lreg); | |
| 4934 | |
| 4935 op_cost(10); | |
| 4936 format %{"[$reg + $lreg]" %} | |
| 4937 interface(MEMORY_INTER) %{ | |
| 4938 base($reg); | |
| 4939 index($lreg); | |
| 4940 scale(0x0); | |
| 4941 disp(0x0); | |
| 4942 %} | |
| 4943 %} | |
| 4944 | |
| 4945 // Indirect Memory Times Scale Plus Index Register | |
| 4946 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale) | |
| 4947 %{ | |
| 4948 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 4949 match(AddP reg (LShiftL lreg scale)); | |
| 4950 | |
| 4951 op_cost(10); | |
| 4952 format %{"[$reg + $lreg << $scale]" %} | |
| 4953 interface(MEMORY_INTER) %{ | |
| 4954 base($reg); | |
| 4955 index($lreg); | |
| 4956 scale($scale); | |
| 4957 disp(0x0); | |
| 4958 %} | |
| 4959 %} | |
| 4960 | |
| 4961 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand | |
| 4962 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale) | |
| 4963 %{ | |
| 4964 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 4965 match(AddP (AddP reg (LShiftL lreg scale)) off); | |
| 4966 | |
| 4967 op_cost(10); | |
| 4968 format %{"[$reg + $off + $lreg << $scale]" %} | |
| 4969 interface(MEMORY_INTER) %{ | |
| 4970 base($reg); | |
| 4971 index($lreg); | |
| 4972 scale($scale); | |
| 4973 disp($off); | |
| 4974 %} | |
| 4975 %} | |
| 4976 | |
| 4977 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand | |
| 4978 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale) | |
| 4979 %{ | |
| 4980 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 4981 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0); | |
| 4982 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off); | |
| 4983 | |
| 4984 op_cost(10); | |
| 4985 format %{"[$reg + $off + $idx << $scale]" %} | |
| 4986 interface(MEMORY_INTER) %{ | |
| 4987 base($reg); | |
| 4988 index($idx); | |
| 4989 scale($scale); | |
| 4990 disp($off); | |
| 4991 %} | |
| 4992 %} | |
| 4993 | |
|
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4994 // Indirect Narrow Oop Plus Offset Operand |
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4995 // Note: x86 architecture doesn't support "scale * index + offset" without a base |
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4996 // we can't free r12 even with Universe::narrow_oop_base() == NULL. |
|
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4997 operand indCompressedOopOffset(rRegN reg, immL32 off) %{ |
|
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4998 predicate(UseCompressedOops && (Universe::narrow_oop_shift() == Address::times_8)); |
|
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4999 constraint(ALLOC_IN_RC(ptr_reg)); |
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5000 match(AddP (DecodeN reg) off); |
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5001 |
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5002 op_cost(10); |
|
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5003 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %} |
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5004 interface(MEMORY_INTER) %{ |
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5005 base(0xc); // R12 |
|
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5006 index($reg); |
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5007 scale(0x3); |
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5008 disp($off); |
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5009 %} |
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5010 %} |
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5011 |
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5012 // Indirect Memory Operand |
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5013 operand indirectNarrow(rRegN reg) |
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5014 %{ |
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5015 predicate(Universe::narrow_oop_shift() == 0); |
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5016 constraint(ALLOC_IN_RC(ptr_reg)); |
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5017 match(DecodeN reg); |
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5018 |
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5019 format %{ "[$reg]" %} |
|
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5020 interface(MEMORY_INTER) %{ |
|
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5021 base($reg); |
|
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parents:
624
diff
changeset
|
5022 index(0x4); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5023 scale(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5024 disp(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5025 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5026 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5027 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5028 // Indirect Memory Plus Short Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5029 operand indOffset8Narrow(rRegN reg, immL8 off) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5030 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5031 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5032 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5033 match(AddP (DecodeN reg) off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5034 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5035 format %{ "[$reg + $off (8-bit)]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5036 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5037 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5038 index(0x4); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5039 scale(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5040 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5041 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5042 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5043 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5044 // Indirect Memory Plus Long Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5045 operand indOffset32Narrow(rRegN reg, immL32 off) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5046 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5047 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5048 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5049 match(AddP (DecodeN reg) off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5050 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5051 format %{ "[$reg + $off (32-bit)]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5052 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5053 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5054 index(0x4); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5055 scale(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5056 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5057 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5058 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5059 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5060 // Indirect Memory Plus Index Register Plus Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5061 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5062 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5063 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5064 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5065 match(AddP (AddP (DecodeN reg) lreg) off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5066 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5067 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5068 format %{"[$reg + $off + $lreg]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5069 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5070 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5071 index($lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5072 scale(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5073 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5074 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5075 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5076 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5077 // Indirect Memory Plus Index Register Plus Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5078 operand indIndexNarrow(rRegN reg, rRegL lreg) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5079 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5080 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5081 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5082 match(AddP (DecodeN reg) lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5083 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5084 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5085 format %{"[$reg + $lreg]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5086 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5087 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5088 index($lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5089 scale(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5090 disp(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5091 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5092 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5093 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5094 // Indirect Memory Times Scale Plus Index Register |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5095 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5096 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5097 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5098 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5099 match(AddP (DecodeN reg) (LShiftL lreg scale)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5100 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5101 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5102 format %{"[$reg + $lreg << $scale]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5103 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5104 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5105 index($lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5106 scale($scale); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5107 disp(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5108 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5109 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5110 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5111 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5112 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5113 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5114 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5115 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5116 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5117 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5118 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5119 format %{"[$reg + $off + $lreg << $scale]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5120 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5121 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5122 index($lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5123 scale($scale); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5124 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5125 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5126 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5127 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5128 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5129 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5130 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5131 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5132 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5133 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5134 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5135 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5136 format %{"[$reg + $off + $idx << $scale]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5137 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5138 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5139 index($idx); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5140 scale($scale); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5141 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5142 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5143 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5144 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5145 |
| 0 | 5146 //----------Special Memory Operands-------------------------------------------- |
| 5147 // Stack Slot Operand - This operand is used for loading and storing temporary | |
| 5148 // values on the stack where a match requires a value to | |
| 5149 // flow through memory. | |
| 5150 operand stackSlotP(sRegP reg) | |
| 5151 %{ | |
| 5152 constraint(ALLOC_IN_RC(stack_slots)); | |
| 5153 // No match rule because this operand is only generated in matching | |
| 5154 | |
| 5155 format %{ "[$reg]" %} | |
| 5156 interface(MEMORY_INTER) %{ | |
| 5157 base(0x4); // RSP | |
| 5158 index(0x4); // No Index | |
| 5159 scale(0x0); // No Scale | |
| 5160 disp($reg); // Stack Offset | |
| 5161 %} | |
| 5162 %} | |
| 5163 | |
| 5164 operand stackSlotI(sRegI reg) | |
| 5165 %{ | |
| 5166 constraint(ALLOC_IN_RC(stack_slots)); | |
| 5167 // No match rule because this operand is only generated in matching | |
| 5168 | |
| 5169 format %{ "[$reg]" %} | |
| 5170 interface(MEMORY_INTER) %{ | |
| 5171 base(0x4); // RSP | |
| 5172 index(0x4); // No Index | |
| 5173 scale(0x0); // No Scale | |
| 5174 disp($reg); // Stack Offset | |
| 5175 %} | |
| 5176 %} | |
| 5177 | |
| 5178 operand stackSlotF(sRegF reg) | |
| 5179 %{ | |
| 5180 constraint(ALLOC_IN_RC(stack_slots)); | |
| 5181 // No match rule because this operand is only generated in matching | |
| 5182 | |
| 5183 format %{ "[$reg]" %} | |
| 5184 interface(MEMORY_INTER) %{ | |
| 5185 base(0x4); // RSP | |
| 5186 index(0x4); // No Index | |
| 5187 scale(0x0); // No Scale | |
| 5188 disp($reg); // Stack Offset | |
| 5189 %} | |
| 5190 %} | |
| 5191 | |
| 5192 operand stackSlotD(sRegD reg) | |
| 5193 %{ | |
| 5194 constraint(ALLOC_IN_RC(stack_slots)); | |
| 5195 // No match rule because this operand is only generated in matching | |
| 5196 | |
| 5197 format %{ "[$reg]" %} | |
| 5198 interface(MEMORY_INTER) %{ | |
| 5199 base(0x4); // RSP | |
| 5200 index(0x4); // No Index | |
| 5201 scale(0x0); // No Scale | |
| 5202 disp($reg); // Stack Offset | |
| 5203 %} | |
| 5204 %} | |
| 5205 operand stackSlotL(sRegL reg) | |
| 5206 %{ | |
| 5207 constraint(ALLOC_IN_RC(stack_slots)); | |
| 5208 // No match rule because this operand is only generated in matching | |
| 5209 | |
| 5210 format %{ "[$reg]" %} | |
| 5211 interface(MEMORY_INTER) %{ | |
| 5212 base(0x4); // RSP | |
| 5213 index(0x4); // No Index | |
| 5214 scale(0x0); // No Scale | |
| 5215 disp($reg); // Stack Offset | |
| 5216 %} | |
| 5217 %} | |
| 5218 | |
| 5219 //----------Conditional Branch Operands---------------------------------------- | |
| 5220 // Comparison Op - This is the operation of the comparison, and is limited to | |
| 5221 // the following set of codes: | |
| 5222 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) | |
| 5223 // | |
| 5224 // Other attributes of the comparison, such as unsignedness, are specified | |
| 5225 // by the comparison instruction that sets a condition code flags register. | |
| 5226 // That result is represented by a flags operand whose subtype is appropriate | |
| 5227 // to the unsignedness (etc.) of the comparison. | |
| 5228 // | |
| 5229 // Later, the instruction which matches both the Comparison Op (a Bool) and | |
| 5230 // the flags (produced by the Cmp) specifies the coding of the comparison op | |
| 5231 // by matching a specific subtype of Bool operand below, such as cmpOpU. | |
| 5232 | |
| 5233 // Comparision Code | |
| 5234 operand cmpOp() | |
| 5235 %{ | |
| 5236 match(Bool); | |
| 5237 | |
| 5238 format %{ "" %} | |
| 5239 interface(COND_INTER) %{ | |
|
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|
5240 equal(0x4, "e"); |
|
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|
5241 not_equal(0x5, "ne"); |
|
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|
5242 less(0xC, "l"); |
|
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|
5243 greater_equal(0xD, "ge"); |
|
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|
5244 less_equal(0xE, "le"); |
|
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|
5245 greater(0xF, "g"); |
| 0 | 5246 %} |
| 5247 %} | |
| 5248 | |
| 5249 // Comparison Code, unsigned compare. Used by FP also, with | |
| 5250 // C2 (unordered) turned into GT or LT already. The other bits | |
| 5251 // C0 and C3 are turned into Carry & Zero flags. | |
| 5252 operand cmpOpU() | |
| 5253 %{ | |
| 5254 match(Bool); | |
| 5255 | |
| 5256 format %{ "" %} | |
| 5257 interface(COND_INTER) %{ | |
|
415
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|
5258 equal(0x4, "e"); |
|
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|
5259 not_equal(0x5, "ne"); |
|
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|
5260 less(0x2, "b"); |
|
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|
5261 greater_equal(0x3, "nb"); |
|
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|
5262 less_equal(0x6, "be"); |
|
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|
5263 greater(0x7, "nbe"); |
|
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|
5264 %} |
|
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|
5265 %} |
|
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|
5266 |
|
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changeset
|
5267 |
|
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|
5268 // Floating comparisons that don't require any fixup for the unordered case |
|
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|
5269 operand cmpOpUCF() %{ |
|
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|
5270 match(Bool); |
|
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|
5271 predicate(n->as_Bool()->_test._test == BoolTest::lt || |
|
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|
5272 n->as_Bool()->_test._test == BoolTest::ge || |
|
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|
5273 n->as_Bool()->_test._test == BoolTest::le || |
|
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|
5274 n->as_Bool()->_test._test == BoolTest::gt); |
|
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|
5275 format %{ "" %} |
|
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diff
changeset
|
5276 interface(COND_INTER) %{ |
|
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diff
changeset
|
5277 equal(0x4, "e"); |
|
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diff
changeset
|
5278 not_equal(0x5, "ne"); |
|
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|
5279 less(0x2, "b"); |
|
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diff
changeset
|
5280 greater_equal(0x3, "nb"); |
|
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diff
changeset
|
5281 less_equal(0x6, "be"); |
|
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|
5282 greater(0x7, "nbe"); |
|
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|
5283 %} |
|
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|
5284 %} |
|
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|
5285 |
|
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|
5286 |
|
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changeset
|
5287 // Floating comparisons that can be fixed up with extra conditional jumps |
|
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|
5288 operand cmpOpUCF2() %{ |
|
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|
5289 match(Bool); |
|
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|
5290 predicate(n->as_Bool()->_test._test == BoolTest::ne || |
|
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|
5291 n->as_Bool()->_test._test == BoolTest::eq); |
|
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|
5292 format %{ "" %} |
|
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|
5293 interface(COND_INTER) %{ |
|
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|
5294 equal(0x4, "e"); |
|
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|
5295 not_equal(0x5, "ne"); |
|
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|
5296 less(0x2, "b"); |
|
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|
5297 greater_equal(0x3, "nb"); |
|
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|
5298 less_equal(0x6, "be"); |
|
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|
5299 greater(0x7, "nbe"); |
| 0 | 5300 %} |
| 5301 %} | |
| 5302 | |
| 5303 | |
| 5304 //----------OPERAND CLASSES---------------------------------------------------- | |
| 5305 // Operand Classes are groups of operands that are used as to simplify | |
| 605 | 5306 // instruction definitions by not requiring the AD writer to specify separate |
| 0 | 5307 // instructions for every form of operand when the instruction accepts |
| 5308 // multiple operand types with the same basic encoding and format. The classic | |
| 5309 // case of this is memory operands. | |
| 5310 | |
| 5311 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex, | |
|
113
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|
5312 indIndexScale, indIndexScaleOffset, indPosIndexScaleOffset, |
|
642
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624
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|
5313 indCompressedOopOffset, |
|
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|
5314 indirectNarrow, indOffset8Narrow, indOffset32Narrow, |
|
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|
5315 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow, |
|
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|
5316 indIndexScaleOffsetNarrow, indPosIndexScaleOffsetNarrow); |
| 0 | 5317 |
| 5318 //----------PIPELINE----------------------------------------------------------- | |
| 5319 // Rules which define the behavior of the target architectures pipeline. | |
| 5320 pipeline %{ | |
| 5321 | |
| 5322 //----------ATTRIBUTES--------------------------------------------------------- | |
| 5323 attributes %{ | |
| 5324 variable_size_instructions; // Fixed size instructions | |
| 5325 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle | |
| 5326 instruction_unit_size = 1; // An instruction is 1 bytes long | |
| 5327 instruction_fetch_unit_size = 16; // The processor fetches one line | |
| 5328 instruction_fetch_units = 1; // of 16 bytes | |
| 5329 | |
| 5330 // List of nop instructions | |
| 5331 nops( MachNop ); | |
| 5332 %} | |
| 5333 | |
| 5334 //----------RESOURCES---------------------------------------------------------- | |
| 5335 // Resources are the functional units available to the machine | |
| 5336 | |
| 5337 // Generic P2/P3 pipeline | |
| 5338 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of | |
| 5339 // 3 instructions decoded per cycle. | |
| 5340 // 2 load/store ops per cycle, 1 branch, 1 FPU, | |
| 5341 // 3 ALU op, only ALU0 handles mul instructions. | |
| 5342 resources( D0, D1, D2, DECODE = D0 | D1 | D2, | |
| 5343 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2, | |
| 5344 BR, FPU, | |
| 5345 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2); | |
| 5346 | |
| 5347 //----------PIPELINE DESCRIPTION----------------------------------------------- | |
| 5348 // Pipeline Description specifies the stages in the machine's pipeline | |
| 5349 | |
| 5350 // Generic P2/P3 pipeline | |
| 5351 pipe_desc(S0, S1, S2, S3, S4, S5); | |
| 5352 | |
| 5353 //----------PIPELINE CLASSES--------------------------------------------------- | |
| 5354 // Pipeline Classes describe the stages in which input and output are | |
| 5355 // referenced by the hardware pipeline. | |
| 5356 | |
| 5357 // Naming convention: ialu or fpu | |
| 5358 // Then: _reg | |
| 5359 // Then: _reg if there is a 2nd register | |
| 5360 // Then: _long if it's a pair of instructions implementing a long | |
| 5361 // Then: _fat if it requires the big decoder | |
| 5362 // Or: _mem if it requires the big decoder and a memory unit. | |
| 5363 | |
| 5364 // Integer ALU reg operation | |
| 5365 pipe_class ialu_reg(rRegI dst) | |
| 5366 %{ | |
| 5367 single_instruction; | |
| 5368 dst : S4(write); | |
| 5369 dst : S3(read); | |
| 5370 DECODE : S0; // any decoder | |
| 5371 ALU : S3; // any alu | |
| 5372 %} | |
| 5373 | |
| 5374 // Long ALU reg operation | |
| 5375 pipe_class ialu_reg_long(rRegL dst) | |
| 5376 %{ | |
| 5377 instruction_count(2); | |
| 5378 dst : S4(write); | |
| 5379 dst : S3(read); | |
| 5380 DECODE : S0(2); // any 2 decoders | |
| 5381 ALU : S3(2); // both alus | |
| 5382 %} | |
| 5383 | |
| 5384 // Integer ALU reg operation using big decoder | |
| 5385 pipe_class ialu_reg_fat(rRegI dst) | |
| 5386 %{ | |
| 5387 single_instruction; | |
| 5388 dst : S4(write); | |
| 5389 dst : S3(read); | |
| 5390 D0 : S0; // big decoder only | |
| 5391 ALU : S3; // any alu | |
| 5392 %} | |
| 5393 | |
| 5394 // Long ALU reg operation using big decoder | |
| 5395 pipe_class ialu_reg_long_fat(rRegL dst) | |
| 5396 %{ | |
| 5397 instruction_count(2); | |
| 5398 dst : S4(write); | |
| 5399 dst : S3(read); | |
| 5400 D0 : S0(2); // big decoder only; twice | |
| 5401 ALU : S3(2); // any 2 alus | |
| 5402 %} | |
| 5403 | |
| 5404 // Integer ALU reg-reg operation | |
| 5405 pipe_class ialu_reg_reg(rRegI dst, rRegI src) | |
| 5406 %{ | |
| 5407 single_instruction; | |
| 5408 dst : S4(write); | |
| 5409 src : S3(read); | |
| 5410 DECODE : S0; // any decoder | |
| 5411 ALU : S3; // any alu | |
| 5412 %} | |
| 5413 | |
| 5414 // Long ALU reg-reg operation | |
| 5415 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src) | |
| 5416 %{ | |
| 5417 instruction_count(2); | |
| 5418 dst : S4(write); | |
| 5419 src : S3(read); | |
| 5420 DECODE : S0(2); // any 2 decoders | |
| 5421 ALU : S3(2); // both alus | |
| 5422 %} | |
| 5423 | |
| 5424 // Integer ALU reg-reg operation | |
| 5425 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) | |
| 5426 %{ | |
| 5427 single_instruction; | |
| 5428 dst : S4(write); | |
| 5429 src : S3(read); | |
| 5430 D0 : S0; // big decoder only | |
| 5431 ALU : S3; // any alu | |
| 5432 %} | |
| 5433 | |
| 5434 // Long ALU reg-reg operation | |
| 5435 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src) | |
| 5436 %{ | |
| 5437 instruction_count(2); | |
| 5438 dst : S4(write); | |
| 5439 src : S3(read); | |
| 5440 D0 : S0(2); // big decoder only; twice | |
| 5441 ALU : S3(2); // both alus | |
| 5442 %} | |
| 5443 | |
| 5444 // Integer ALU reg-mem operation | |
| 5445 pipe_class ialu_reg_mem(rRegI dst, memory mem) | |
| 5446 %{ | |
| 5447 single_instruction; | |
| 5448 dst : S5(write); | |
| 5449 mem : S3(read); | |
| 5450 D0 : S0; // big decoder only | |
| 5451 ALU : S4; // any alu | |
| 5452 MEM : S3; // any mem | |
| 5453 %} | |
| 5454 | |
| 5455 // Integer mem operation (prefetch) | |
| 5456 pipe_class ialu_mem(memory mem) | |
| 5457 %{ | |
| 5458 single_instruction; | |
| 5459 mem : S3(read); | |
| 5460 D0 : S0; // big decoder only | |
| 5461 MEM : S3; // any mem | |
| 5462 %} | |
| 5463 | |
| 5464 // Integer Store to Memory | |
| 5465 pipe_class ialu_mem_reg(memory mem, rRegI src) | |
| 5466 %{ | |
| 5467 single_instruction; | |
| 5468 mem : S3(read); | |
| 5469 src : S5(read); | |
| 5470 D0 : S0; // big decoder only | |
| 5471 ALU : S4; // any alu | |
| 5472 MEM : S3; | |
| 5473 %} | |
| 5474 | |
| 5475 // // Long Store to Memory | |
| 5476 // pipe_class ialu_mem_long_reg(memory mem, rRegL src) | |
| 5477 // %{ | |
| 5478 // instruction_count(2); | |
| 5479 // mem : S3(read); | |
| 5480 // src : S5(read); | |
| 5481 // D0 : S0(2); // big decoder only; twice | |
| 5482 // ALU : S4(2); // any 2 alus | |
| 5483 // MEM : S3(2); // Both mems | |
| 5484 // %} | |
| 5485 | |
| 5486 // Integer Store to Memory | |
| 5487 pipe_class ialu_mem_imm(memory mem) | |
| 5488 %{ | |
| 5489 single_instruction; | |
| 5490 mem : S3(read); | |
| 5491 D0 : S0; // big decoder only | |
| 5492 ALU : S4; // any alu | |
| 5493 MEM : S3; | |
| 5494 %} | |
| 5495 | |
| 5496 // Integer ALU0 reg-reg operation | |
| 5497 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) | |
| 5498 %{ | |
| 5499 single_instruction; | |
| 5500 dst : S4(write); | |
| 5501 src : S3(read); | |
| 5502 D0 : S0; // Big decoder only | |
| 5503 ALU0 : S3; // only alu0 | |
| 5504 %} | |
| 5505 | |
| 5506 // Integer ALU0 reg-mem operation | |
| 5507 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) | |
| 5508 %{ | |
| 5509 single_instruction; | |
| 5510 dst : S5(write); | |
| 5511 mem : S3(read); | |
| 5512 D0 : S0; // big decoder only | |
| 5513 ALU0 : S4; // ALU0 only | |
| 5514 MEM : S3; // any mem | |
| 5515 %} | |
| 5516 | |
| 5517 // Integer ALU reg-reg operation | |
| 5518 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2) | |
| 5519 %{ | |
| 5520 single_instruction; | |
| 5521 cr : S4(write); | |
| 5522 src1 : S3(read); | |
| 5523 src2 : S3(read); | |
| 5524 DECODE : S0; // any decoder | |
| 5525 ALU : S3; // any alu | |
| 5526 %} | |
| 5527 | |
| 5528 // Integer ALU reg-imm operation | |
| 5529 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1) | |
| 5530 %{ | |
| 5531 single_instruction; | |
| 5532 cr : S4(write); | |
| 5533 src1 : S3(read); | |
| 5534 DECODE : S0; // any decoder | |
| 5535 ALU : S3; // any alu | |
| 5536 %} | |
| 5537 | |
| 5538 // Integer ALU reg-mem operation | |
| 5539 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2) | |
| 5540 %{ | |
| 5541 single_instruction; | |
| 5542 cr : S4(write); | |
| 5543 src1 : S3(read); | |
| 5544 src2 : S3(read); | |
| 5545 D0 : S0; // big decoder only | |
| 5546 ALU : S4; // any alu | |
| 5547 MEM : S3; | |
| 5548 %} | |
| 5549 | |
| 5550 // Conditional move reg-reg | |
| 5551 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y) | |
| 5552 %{ | |
| 5553 instruction_count(4); | |
| 5554 y : S4(read); | |
| 5555 q : S3(read); | |
| 5556 p : S3(read); | |
| 5557 DECODE : S0(4); // any decoder | |
| 5558 %} | |
| 5559 | |
| 5560 // Conditional move reg-reg | |
| 5561 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr) | |
| 5562 %{ | |
| 5563 single_instruction; | |
| 5564 dst : S4(write); | |
| 5565 src : S3(read); | |
| 5566 cr : S3(read); | |
| 5567 DECODE : S0; // any decoder | |
| 5568 %} | |
| 5569 | |
| 5570 // Conditional move reg-mem | |
| 5571 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src) | |
| 5572 %{ | |
| 5573 single_instruction; | |
| 5574 dst : S4(write); | |
| 5575 src : S3(read); | |
| 5576 cr : S3(read); | |
| 5577 DECODE : S0; // any decoder | |
| 5578 MEM : S3; | |
| 5579 %} | |
| 5580 | |
| 5581 // Conditional move reg-reg long | |
| 5582 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src) | |
| 5583 %{ | |
| 5584 single_instruction; | |
| 5585 dst : S4(write); | |
| 5586 src : S3(read); | |
| 5587 cr : S3(read); | |
| 5588 DECODE : S0(2); // any 2 decoders | |
| 5589 %} | |
| 5590 | |
| 5591 // XXX | |
| 5592 // // Conditional move double reg-reg | |
| 5593 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src) | |
| 5594 // %{ | |
| 5595 // single_instruction; | |
| 5596 // dst : S4(write); | |
| 5597 // src : S3(read); | |
| 5598 // cr : S3(read); | |
| 5599 // DECODE : S0; // any decoder | |
| 5600 // %} | |
| 5601 | |
| 5602 // Float reg-reg operation | |
| 5603 pipe_class fpu_reg(regD dst) | |
| 5604 %{ | |
| 5605 instruction_count(2); | |
| 5606 dst : S3(read); | |
| 5607 DECODE : S0(2); // any 2 decoders | |
| 5608 FPU : S3; | |
| 5609 %} | |
| 5610 | |
| 5611 // Float reg-reg operation | |
| 5612 pipe_class fpu_reg_reg(regD dst, regD src) | |
| 5613 %{ | |
| 5614 instruction_count(2); | |
| 5615 dst : S4(write); | |
| 5616 src : S3(read); | |
| 5617 DECODE : S0(2); // any 2 decoders | |
| 5618 FPU : S3; | |
| 5619 %} | |
| 5620 | |
| 5621 // Float reg-reg operation | |
| 5622 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2) | |
| 5623 %{ | |
| 5624 instruction_count(3); | |
| 5625 dst : S4(write); | |
| 5626 src1 : S3(read); | |
| 5627 src2 : S3(read); | |
| 5628 DECODE : S0(3); // any 3 decoders | |
| 5629 FPU : S3(2); | |
| 5630 %} | |
| 5631 | |
| 5632 // Float reg-reg operation | |
| 5633 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3) | |
| 5634 %{ | |
| 5635 instruction_count(4); | |
| 5636 dst : S4(write); | |
| 5637 src1 : S3(read); | |
| 5638 src2 : S3(read); | |
| 5639 src3 : S3(read); | |
| 5640 DECODE : S0(4); // any 3 decoders | |
| 5641 FPU : S3(2); | |
| 5642 %} | |
| 5643 | |
| 5644 // Float reg-reg operation | |
| 5645 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3) | |
| 5646 %{ | |
| 5647 instruction_count(4); | |
| 5648 dst : S4(write); | |
| 5649 src1 : S3(read); | |
| 5650 src2 : S3(read); | |
| 5651 src3 : S3(read); | |
| 5652 DECODE : S1(3); // any 3 decoders | |
| 5653 D0 : S0; // Big decoder only | |
| 5654 FPU : S3(2); | |
| 5655 MEM : S3; | |
| 5656 %} | |
| 5657 | |
| 5658 // Float reg-mem operation | |
| 5659 pipe_class fpu_reg_mem(regD dst, memory mem) | |
| 5660 %{ | |
| 5661 instruction_count(2); | |
| 5662 dst : S5(write); | |
| 5663 mem : S3(read); | |
| 5664 D0 : S0; // big decoder only | |
| 5665 DECODE : S1; // any decoder for FPU POP | |
| 5666 FPU : S4; | |
| 5667 MEM : S3; // any mem | |
| 5668 %} | |
| 5669 | |
| 5670 // Float reg-mem operation | |
| 5671 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem) | |
| 5672 %{ | |
| 5673 instruction_count(3); | |
| 5674 dst : S5(write); | |
| 5675 src1 : S3(read); | |
| 5676 mem : S3(read); | |
| 5677 D0 : S0; // big decoder only | |
| 5678 DECODE : S1(2); // any decoder for FPU POP | |
| 5679 FPU : S4; | |
| 5680 MEM : S3; // any mem | |
| 5681 %} | |
| 5682 | |
| 5683 // Float mem-reg operation | |
| 5684 pipe_class fpu_mem_reg(memory mem, regD src) | |
| 5685 %{ | |
| 5686 instruction_count(2); | |
| 5687 src : S5(read); | |
| 5688 mem : S3(read); | |
| 5689 DECODE : S0; // any decoder for FPU PUSH | |
| 5690 D0 : S1; // big decoder only | |
| 5691 FPU : S4; | |
| 5692 MEM : S3; // any mem | |
| 5693 %} | |
| 5694 | |
| 5695 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2) | |
| 5696 %{ | |
| 5697 instruction_count(3); | |
| 5698 src1 : S3(read); | |
| 5699 src2 : S3(read); | |
| 5700 mem : S3(read); | |
| 5701 DECODE : S0(2); // any decoder for FPU PUSH | |
| 5702 D0 : S1; // big decoder only | |
| 5703 FPU : S4; | |
| 5704 MEM : S3; // any mem | |
| 5705 %} | |
| 5706 | |
| 5707 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2) | |
| 5708 %{ | |
| 5709 instruction_count(3); | |
| 5710 src1 : S3(read); | |
| 5711 src2 : S3(read); | |
| 5712 mem : S4(read); | |
| 5713 DECODE : S0; // any decoder for FPU PUSH | |
| 5714 D0 : S0(2); // big decoder only | |
| 5715 FPU : S4; | |
| 5716 MEM : S3(2); // any mem | |
| 5717 %} | |
| 5718 | |
| 5719 pipe_class fpu_mem_mem(memory dst, memory src1) | |
| 5720 %{ | |
| 5721 instruction_count(2); | |
| 5722 src1 : S3(read); | |
| 5723 dst : S4(read); | |
| 5724 D0 : S0(2); // big decoder only | |
| 5725 MEM : S3(2); // any mem | |
| 5726 %} | |
| 5727 | |
| 5728 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) | |
| 5729 %{ | |
| 5730 instruction_count(3); | |
| 5731 src1 : S3(read); | |
| 5732 src2 : S3(read); | |
| 5733 dst : S4(read); | |
| 5734 D0 : S0(3); // big decoder only | |
| 5735 FPU : S4; | |
| 5736 MEM : S3(3); // any mem | |
| 5737 %} | |
| 5738 | |
| 5739 pipe_class fpu_mem_reg_con(memory mem, regD src1) | |
| 5740 %{ | |
| 5741 instruction_count(3); | |
| 5742 src1 : S4(read); | |
| 5743 mem : S4(read); | |
| 5744 DECODE : S0; // any decoder for FPU PUSH | |
| 5745 D0 : S0(2); // big decoder only | |
| 5746 FPU : S4; | |
| 5747 MEM : S3(2); // any mem | |
| 5748 %} | |
| 5749 | |
| 5750 // Float load constant | |
| 5751 pipe_class fpu_reg_con(regD dst) | |
| 5752 %{ | |
| 5753 instruction_count(2); | |
| 5754 dst : S5(write); | |
| 5755 D0 : S0; // big decoder only for the load | |
| 5756 DECODE : S1; // any decoder for FPU POP | |
| 5757 FPU : S4; | |
| 5758 MEM : S3; // any mem | |
| 5759 %} | |
| 5760 | |
| 5761 // Float load constant | |
| 5762 pipe_class fpu_reg_reg_con(regD dst, regD src) | |
| 5763 %{ | |
| 5764 instruction_count(3); | |
| 5765 dst : S5(write); | |
| 5766 src : S3(read); | |
| 5767 D0 : S0; // big decoder only for the load | |
| 5768 DECODE : S1(2); // any decoder for FPU POP | |
| 5769 FPU : S4; | |
| 5770 MEM : S3; // any mem | |
| 5771 %} | |
| 5772 | |
| 5773 // UnConditional branch | |
| 5774 pipe_class pipe_jmp(label labl) | |
| 5775 %{ | |
| 5776 single_instruction; | |
| 5777 BR : S3; | |
| 5778 %} | |
| 5779 | |
| 5780 // Conditional branch | |
| 5781 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl) | |
| 5782 %{ | |
| 5783 single_instruction; | |
| 5784 cr : S1(read); | |
| 5785 BR : S3; | |
| 5786 %} | |
| 5787 | |
| 5788 // Allocation idiom | |
| 5789 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr) | |
| 5790 %{ | |
| 5791 instruction_count(1); force_serialization; | |
| 5792 fixed_latency(6); | |
| 5793 heap_ptr : S3(read); | |
| 5794 DECODE : S0(3); | |
| 5795 D0 : S2; | |
| 5796 MEM : S3; | |
| 5797 ALU : S3(2); | |
| 5798 dst : S5(write); | |
| 5799 BR : S5; | |
| 5800 %} | |
| 5801 | |
| 5802 // Generic big/slow expanded idiom | |
| 5803 pipe_class pipe_slow() | |
| 5804 %{ | |
| 5805 instruction_count(10); multiple_bundles; force_serialization; | |
| 5806 fixed_latency(100); | |
| 5807 D0 : S0(2); | |
| 5808 MEM : S3(2); | |
| 5809 %} | |
| 5810 | |
| 5811 // The real do-nothing guy | |
| 5812 pipe_class empty() | |
| 5813 %{ | |
| 5814 instruction_count(0); | |
| 5815 %} | |
| 5816 | |
| 5817 // Define the class for the Nop node | |
| 5818 define | |
| 5819 %{ | |
| 5820 MachNop = empty; | |
| 5821 %} | |
| 5822 | |
| 5823 %} | |
| 5824 | |
| 5825 //----------INSTRUCTIONS------------------------------------------------------- | |
| 5826 // | |
| 5827 // match -- States which machine-independent subtree may be replaced | |
| 5828 // by this instruction. | |
| 5829 // ins_cost -- The estimated cost of this instruction is used by instruction | |
| 5830 // selection to identify a minimum cost tree of machine | |
| 5831 // instructions that matches a tree of machine-independent | |
| 5832 // instructions. | |
| 5833 // format -- A string providing the disassembly for this instruction. | |
| 5834 // The value of an instruction's operand may be inserted | |
| 5835 // by referring to it with a '$' prefix. | |
| 5836 // opcode -- Three instruction opcodes may be provided. These are referred | |
| 5837 // to within an encode class as $primary, $secondary, and $tertiary | |
| 5838 // rrspectively. The primary opcode is commonly used to | |
| 5839 // indicate the type of machine instruction, while secondary | |
| 5840 // and tertiary are often used for prefix options or addressing | |
| 5841 // modes. | |
| 5842 // ins_encode -- A list of encode classes with parameters. The encode class | |
| 5843 // name must have been defined in an 'enc_class' specification | |
| 5844 // in the encode section of the architecture description. | |
| 5845 | |
| 5846 | |
| 5847 //----------Load/Store/Move Instructions--------------------------------------- | |
| 5848 //----------Load Instructions-------------------------------------------------- | |
| 5849 | |
| 5850 // Load Byte (8 bit signed) | |
| 5851 instruct loadB(rRegI dst, memory mem) | |
| 5852 %{ | |
| 5853 match(Set dst (LoadB mem)); | |
| 5854 | |
| 5855 ins_cost(125); | |
| 5856 format %{ "movsbl $dst, $mem\t# byte" %} | |
| 624 | 5857 |
| 5858 ins_encode %{ | |
| 5859 __ movsbl($dst$$Register, $mem$$Address); | |
| 5860 %} | |
| 5861 | |
| 0 | 5862 ins_pipe(ialu_reg_mem); |
| 5863 %} | |
| 5864 | |
| 624 | 5865 // Load Byte (8 bit signed) into Long Register |
| 5866 instruct loadB2L(rRegL dst, memory mem) | |
| 5867 %{ | |
| 5868 match(Set dst (ConvI2L (LoadB mem))); | |
| 5869 | |
| 5870 ins_cost(125); | |
| 5871 format %{ "movsbq $dst, $mem\t# byte -> long" %} | |
| 5872 | |
| 5873 ins_encode %{ | |
| 5874 __ movsbq($dst$$Register, $mem$$Address); | |
| 5875 %} | |
| 5876 | |
| 5877 ins_pipe(ialu_reg_mem); | |
| 5878 %} | |
| 5879 | |
| 5880 // Load Unsigned Byte (8 bit UNsigned) | |
| 5881 instruct loadUB(rRegI dst, memory mem) | |
| 5882 %{ | |
| 5883 match(Set dst (LoadUB mem)); | |
| 0 | 5884 |
| 5885 ins_cost(125); | |
| 5886 format %{ "movzbl $dst, $mem\t# ubyte" %} | |
| 624 | 5887 |
| 5888 ins_encode %{ | |
| 5889 __ movzbl($dst$$Register, $mem$$Address); | |
| 5890 %} | |
| 5891 | |
| 0 | 5892 ins_pipe(ialu_reg_mem); |
| 5893 %} | |
| 5894 | |
| 624 | 5895 // Load Unsigned Byte (8 bit UNsigned) into Long Register |
| 5896 instruct loadUB2L(rRegL dst, memory mem) | |
| 5897 %{ | |
| 5898 match(Set dst (ConvI2L (LoadUB mem))); | |
| 5899 | |
| 5900 ins_cost(125); | |
| 5901 format %{ "movzbq $dst, $mem\t# ubyte -> long" %} | |
| 5902 | |
| 5903 ins_encode %{ | |
| 5904 __ movzbq($dst$$Register, $mem$$Address); | |
| 5905 %} | |
| 5906 | |
| 5907 ins_pipe(ialu_reg_mem); | |
| 5908 %} | |
| 0 | 5909 |
| 824 | 5910 // Load Unsigned Byte (8 bit UNsigned) with a 8-bit mask into Long Register |
| 5911 instruct loadUB2L_immI8(rRegL dst, memory mem, immI8 mask, rFlagsReg cr) %{ | |
| 5912 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); | |
| 5913 effect(KILL cr); | |
| 5914 | |
| 5915 format %{ "movzbq $dst, $mem\t# ubyte & 8-bit mask -> long\n\t" | |
| 5916 "andl $dst, $mask" %} | |
| 5917 ins_encode %{ | |
| 5918 Register Rdst = $dst$$Register; | |
| 5919 __ movzbq(Rdst, $mem$$Address); | |
| 5920 __ andl(Rdst, $mask$$constant); | |
| 5921 %} | |
| 5922 ins_pipe(ialu_reg_mem); | |
| 5923 %} | |
| 5924 | |
| 0 | 5925 // Load Short (16 bit signed) |
| 5926 instruct loadS(rRegI dst, memory mem) | |
| 5927 %{ | |
| 5928 match(Set dst (LoadS mem)); | |
| 5929 | |
| 624 | 5930 ins_cost(125); |
| 0 | 5931 format %{ "movswl $dst, $mem\t# short" %} |
| 624 | 5932 |
| 5933 ins_encode %{ | |
| 5934 __ movswl($dst$$Register, $mem$$Address); | |
| 5935 %} | |
| 5936 | |
| 0 | 5937 ins_pipe(ialu_reg_mem); |
| 5938 %} | |
| 5939 | |
| 785 | 5940 // Load Short (16 bit signed) to Byte (8 bit signed) |
| 5941 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{ | |
| 5942 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); | |
| 5943 | |
| 5944 ins_cost(125); | |
| 5945 format %{ "movsbl $dst, $mem\t# short -> byte" %} | |
| 5946 ins_encode %{ | |
| 5947 __ movsbl($dst$$Register, $mem$$Address); | |
| 5948 %} | |
| 5949 ins_pipe(ialu_reg_mem); | |
| 5950 %} | |
| 5951 | |
| 624 | 5952 // Load Short (16 bit signed) into Long Register |
| 5953 instruct loadS2L(rRegL dst, memory mem) | |
| 5954 %{ | |
| 5955 match(Set dst (ConvI2L (LoadS mem))); | |
| 5956 | |
| 5957 ins_cost(125); | |
| 5958 format %{ "movswq $dst, $mem\t# short -> long" %} | |
| 5959 | |
| 5960 ins_encode %{ | |
| 5961 __ movswq($dst$$Register, $mem$$Address); | |
| 5962 %} | |
| 5963 | |
| 5964 ins_pipe(ialu_reg_mem); | |
| 5965 %} | |
| 0 | 5966 |
|
558
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
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parents:
420
diff
changeset
|
5967 // Load Unsigned Short/Char (16 bit UNsigned) |
|
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents:
420
diff
changeset
|
5968 instruct loadUS(rRegI dst, memory mem) |
|
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents:
420
diff
changeset
|
5969 %{ |
|
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents:
420
diff
changeset
|
5970 match(Set dst (LoadUS mem)); |
| 0 | 5971 |
| 5972 ins_cost(125); | |
|
558
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents:
420
diff
changeset
|
5973 format %{ "movzwl $dst, $mem\t# ushort/char" %} |
| 624 | 5974 |
| 5975 ins_encode %{ | |
| 5976 __ movzwl($dst$$Register, $mem$$Address); | |
| 5977 %} | |
| 5978 | |
| 0 | 5979 ins_pipe(ialu_reg_mem); |
| 5980 %} | |
| 5981 | |
| 785 | 5982 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) |
| 5983 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{ | |
| 5984 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); | |
| 5985 | |
| 5986 ins_cost(125); | |
| 5987 format %{ "movsbl $dst, $mem\t# ushort -> byte" %} | |
| 5988 ins_encode %{ | |
| 5989 __ movsbl($dst$$Register, $mem$$Address); | |
| 5990 %} | |
| 5991 ins_pipe(ialu_reg_mem); | |
| 5992 %} | |
| 5993 | |
| 624 | 5994 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register |
| 5995 instruct loadUS2L(rRegL dst, memory mem) | |
| 5996 %{ | |
| 5997 match(Set dst (ConvI2L (LoadUS mem))); | |
| 5998 | |
| 5999 ins_cost(125); | |
| 6000 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %} | |
| 6001 | |
| 6002 ins_encode %{ | |
| 6003 __ movzwq($dst$$Register, $mem$$Address); | |
| 6004 %} | |
| 6005 | |
| 6006 ins_pipe(ialu_reg_mem); | |
| 6007 %} | |
| 0 | 6008 |
| 824 | 6009 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register |
| 6010 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{ | |
| 6011 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 6012 | |
| 6013 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %} | |
| 6014 ins_encode %{ | |
| 6015 __ movzbq($dst$$Register, $mem$$Address); | |
| 6016 %} | |
| 6017 ins_pipe(ialu_reg_mem); | |
| 6018 %} | |
| 6019 | |
| 6020 // Load Unsigned Short/Char (16 bit UNsigned) with mask into Long Register | |
| 6021 instruct loadUS2L_immI16(rRegL dst, memory mem, immI16 mask, rFlagsReg cr) %{ | |
| 6022 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 6023 effect(KILL cr); | |
| 6024 | |
| 6025 format %{ "movzwq $dst, $mem\t# ushort/char & 16-bit mask -> long\n\t" | |
| 6026 "andl $dst, $mask" %} | |
| 6027 ins_encode %{ | |
| 6028 Register Rdst = $dst$$Register; | |
| 6029 __ movzwq(Rdst, $mem$$Address); | |
| 6030 __ andl(Rdst, $mask$$constant); | |
| 6031 %} | |
| 6032 ins_pipe(ialu_reg_mem); | |
| 6033 %} | |
| 6034 | |
| 0 | 6035 // Load Integer |
| 6036 instruct loadI(rRegI dst, memory mem) | |
| 6037 %{ | |
| 6038 match(Set dst (LoadI mem)); | |
| 6039 | |
| 624 | 6040 ins_cost(125); |
| 0 | 6041 format %{ "movl $dst, $mem\t# int" %} |
| 624 | 6042 |
| 6043 ins_encode %{ | |
| 6044 __ movl($dst$$Register, $mem$$Address); | |
| 6045 %} | |
| 6046 | |
| 6047 ins_pipe(ialu_reg_mem); | |
| 6048 %} | |
| 6049 | |
| 785 | 6050 // Load Integer (32 bit signed) to Byte (8 bit signed) |
| 6051 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{ | |
| 6052 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); | |
| 6053 | |
| 6054 ins_cost(125); | |
| 6055 format %{ "movsbl $dst, $mem\t# int -> byte" %} | |
| 6056 ins_encode %{ | |
| 6057 __ movsbl($dst$$Register, $mem$$Address); | |
| 6058 %} | |
| 6059 ins_pipe(ialu_reg_mem); | |
| 6060 %} | |
| 6061 | |
| 6062 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned) | |
| 6063 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{ | |
| 6064 match(Set dst (AndI (LoadI mem) mask)); | |
| 6065 | |
| 6066 ins_cost(125); | |
| 6067 format %{ "movzbl $dst, $mem\t# int -> ubyte" %} | |
| 6068 ins_encode %{ | |
| 6069 __ movzbl($dst$$Register, $mem$$Address); | |
| 6070 %} | |
| 6071 ins_pipe(ialu_reg_mem); | |
| 6072 %} | |
| 6073 | |
| 6074 // Load Integer (32 bit signed) to Short (16 bit signed) | |
| 6075 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{ | |
| 6076 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); | |
| 6077 | |
| 6078 ins_cost(125); | |
| 6079 format %{ "movswl $dst, $mem\t# int -> short" %} | |
| 6080 ins_encode %{ | |
| 6081 __ movswl($dst$$Register, $mem$$Address); | |
| 6082 %} | |
| 6083 ins_pipe(ialu_reg_mem); | |
| 6084 %} | |
| 6085 | |
| 6086 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned) | |
| 6087 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{ | |
| 6088 match(Set dst (AndI (LoadI mem) mask)); | |
| 6089 | |
| 6090 ins_cost(125); | |
| 6091 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %} | |
| 6092 ins_encode %{ | |
| 6093 __ movzwl($dst$$Register, $mem$$Address); | |
| 6094 %} | |
| 6095 ins_pipe(ialu_reg_mem); | |
| 6096 %} | |
| 6097 | |
| 624 | 6098 // Load Integer into Long Register |
| 6099 instruct loadI2L(rRegL dst, memory mem) | |
| 6100 %{ | |
| 6101 match(Set dst (ConvI2L (LoadI mem))); | |
| 6102 | |
| 6103 ins_cost(125); | |
| 6104 format %{ "movslq $dst, $mem\t# int -> long" %} | |
| 6105 | |
| 6106 ins_encode %{ | |
| 6107 __ movslq($dst$$Register, $mem$$Address); | |
| 6108 %} | |
| 6109 | |
| 6110 ins_pipe(ialu_reg_mem); | |
| 6111 %} | |
| 6112 | |
| 824 | 6113 // Load Integer with mask 0xFF into Long Register |
| 6114 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{ | |
| 6115 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 6116 | |
| 6117 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %} | |
| 6118 ins_encode %{ | |
| 6119 __ movzbq($dst$$Register, $mem$$Address); | |
| 6120 %} | |
| 6121 ins_pipe(ialu_reg_mem); | |
| 6122 %} | |
| 6123 | |
| 6124 // Load Integer with mask 0xFFFF into Long Register | |
| 6125 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{ | |
| 6126 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 6127 | |
| 6128 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %} | |
| 6129 ins_encode %{ | |
| 6130 __ movzwq($dst$$Register, $mem$$Address); | |
| 6131 %} | |
| 6132 ins_pipe(ialu_reg_mem); | |
| 6133 %} | |
| 6134 | |
| 6135 // Load Integer with a 32-bit mask into Long Register | |
| 6136 instruct loadI2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{ | |
| 6137 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 6138 effect(KILL cr); | |
| 6139 | |
| 6140 format %{ "movl $dst, $mem\t# int & 32-bit mask -> long\n\t" | |
| 6141 "andl $dst, $mask" %} | |
| 6142 ins_encode %{ | |
| 6143 Register Rdst = $dst$$Register; | |
| 6144 __ movl(Rdst, $mem$$Address); | |
| 6145 __ andl(Rdst, $mask$$constant); | |
| 6146 %} | |
| 6147 ins_pipe(ialu_reg_mem); | |
| 6148 %} | |
| 6149 | |
| 624 | 6150 // Load Unsigned Integer into Long Register |
| 6151 instruct loadUI2L(rRegL dst, memory mem) | |
| 6152 %{ | |
| 6153 match(Set dst (LoadUI2L mem)); | |
| 6154 | |
| 6155 ins_cost(125); | |
| 6156 format %{ "movl $dst, $mem\t# uint -> long" %} | |
| 6157 | |
| 6158 ins_encode %{ | |
| 6159 __ movl($dst$$Register, $mem$$Address); | |
| 6160 %} | |
| 6161 | |
| 0 | 6162 ins_pipe(ialu_reg_mem); |
| 6163 %} | |
| 6164 | |
| 6165 // Load Long | |
| 6166 instruct loadL(rRegL dst, memory mem) | |
| 6167 %{ | |
| 6168 match(Set dst (LoadL mem)); | |
| 6169 | |
| 624 | 6170 ins_cost(125); |
| 0 | 6171 format %{ "movq $dst, $mem\t# long" %} |
| 624 | 6172 |
| 6173 ins_encode %{ | |
| 6174 __ movq($dst$$Register, $mem$$Address); | |
| 6175 %} | |
| 6176 | |
| 0 | 6177 ins_pipe(ialu_reg_mem); // XXX |
| 6178 %} | |
| 6179 | |
| 6180 // Load Range | |
| 6181 instruct loadRange(rRegI dst, memory mem) | |
| 6182 %{ | |
| 6183 match(Set dst (LoadRange mem)); | |
| 6184 | |
| 6185 ins_cost(125); // XXX | |
| 6186 format %{ "movl $dst, $mem\t# range" %} | |
| 6187 opcode(0x8B); | |
| 6188 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 6189 ins_pipe(ialu_reg_mem); | |
| 6190 %} | |
| 6191 | |
| 6192 // Load Pointer | |
| 6193 instruct loadP(rRegP dst, memory mem) | |
| 6194 %{ | |
| 6195 match(Set dst (LoadP mem)); | |
| 6196 | |
| 6197 ins_cost(125); // XXX | |
| 6198 format %{ "movq $dst, $mem\t# ptr" %} | |
| 6199 opcode(0x8B); | |
| 6200 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 6201 ins_pipe(ialu_reg_mem); // XXX | |
| 6202 %} | |
| 6203 | |
|
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6204 // Load Compressed Pointer |
| 163 | 6205 instruct loadN(rRegN dst, memory mem) |
|
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6206 %{ |
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6207 match(Set dst (LoadN mem)); |
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6208 |
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6209 ins_cost(125); // XXX |
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6210 format %{ "movl $dst, $mem\t# compressed ptr" %} |
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6211 ins_encode %{ |
|
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6212 __ movl($dst$$Register, $mem$$Address); |
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6213 %} |
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6214 ins_pipe(ialu_reg_mem); // XXX |
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6215 %} |
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6216 |
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6217 |
| 0 | 6218 // Load Klass Pointer |
| 6219 instruct loadKlass(rRegP dst, memory mem) | |
| 6220 %{ | |
| 6221 match(Set dst (LoadKlass mem)); | |
| 6222 | |
| 6223 ins_cost(125); // XXX | |
| 6224 format %{ "movq $dst, $mem\t# class" %} | |
| 6225 opcode(0x8B); | |
| 6226 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 6227 ins_pipe(ialu_reg_mem); // XXX | |
| 6228 %} | |
| 6229 | |
|
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6230 // Load narrow Klass Pointer |
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6231 instruct loadNKlass(rRegN dst, memory mem) |
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6232 %{ |
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6233 match(Set dst (LoadNKlass mem)); |
|
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6234 |
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6235 ins_cost(125); // XXX |
|
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6236 format %{ "movl $dst, $mem\t# compressed klass ptr" %} |
|
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6237 ins_encode %{ |
|
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6238 __ movl($dst$$Register, $mem$$Address); |
|
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6239 %} |
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6240 ins_pipe(ialu_reg_mem); // XXX |
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6241 %} |
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6242 |
| 0 | 6243 // Load Float |
| 6244 instruct loadF(regF dst, memory mem) | |
| 6245 %{ | |
| 6246 match(Set dst (LoadF mem)); | |
| 6247 | |
| 6248 ins_cost(145); // XXX | |
| 6249 format %{ "movss $dst, $mem\t# float" %} | |
| 6250 opcode(0xF3, 0x0F, 0x10); | |
| 6251 ins_encode(OpcP, REX_reg_mem(dst, mem), OpcS, OpcT, reg_mem(dst, mem)); | |
| 6252 ins_pipe(pipe_slow); // XXX | |
| 6253 %} | |
| 6254 | |
| 6255 // Load Double | |
| 6256 instruct loadD_partial(regD dst, memory mem) | |
| 6257 %{ | |
| 6258 predicate(!UseXmmLoadAndClearUpper); | |
| 6259 match(Set dst (LoadD mem)); | |
| 6260 | |
| 6261 ins_cost(145); // XXX | |
| 6262 format %{ "movlpd $dst, $mem\t# double" %} | |
| 6263 opcode(0x66, 0x0F, 0x12); | |
| 6264 ins_encode(OpcP, REX_reg_mem(dst, mem), OpcS, OpcT, reg_mem(dst, mem)); | |
| 6265 ins_pipe(pipe_slow); // XXX | |
| 6266 %} | |
| 6267 | |
| 6268 instruct loadD(regD dst, memory mem) | |
| 6269 %{ | |
| 6270 predicate(UseXmmLoadAndClearUpper); | |
| 6271 match(Set dst (LoadD mem)); | |
| 6272 | |
| 6273 ins_cost(145); // XXX | |
| 6274 format %{ "movsd $dst, $mem\t# double" %} | |
| 6275 opcode(0xF2, 0x0F, 0x10); | |
| 6276 ins_encode(OpcP, REX_reg_mem(dst, mem), OpcS, OpcT, reg_mem(dst, mem)); | |
| 6277 ins_pipe(pipe_slow); // XXX | |
| 6278 %} | |
| 6279 | |
| 6280 // Load Aligned Packed Byte to XMM register | |
| 6281 instruct loadA8B(regD dst, memory mem) %{ | |
| 6282 match(Set dst (Load8B mem)); | |
| 6283 ins_cost(125); | |
| 6284 format %{ "MOVQ $dst,$mem\t! packed8B" %} | |
| 6285 ins_encode( movq_ld(dst, mem)); | |
| 6286 ins_pipe( pipe_slow ); | |
| 6287 %} | |
| 6288 | |
| 6289 // Load Aligned Packed Short to XMM register | |
| 6290 instruct loadA4S(regD dst, memory mem) %{ | |
| 6291 match(Set dst (Load4S mem)); | |
| 6292 ins_cost(125); | |
| 6293 format %{ "MOVQ $dst,$mem\t! packed4S" %} | |
| 6294 ins_encode( movq_ld(dst, mem)); | |
| 6295 ins_pipe( pipe_slow ); | |
| 6296 %} | |
| 6297 | |
| 6298 // Load Aligned Packed Char to XMM register | |
| 6299 instruct loadA4C(regD dst, memory mem) %{ | |
| 6300 match(Set dst (Load4C mem)); | |
| 6301 ins_cost(125); | |
| 6302 format %{ "MOVQ $dst,$mem\t! packed4C" %} | |
| 6303 ins_encode( movq_ld(dst, mem)); | |
| 6304 ins_pipe( pipe_slow ); | |
| 6305 %} | |
| 6306 | |
| 6307 // Load Aligned Packed Integer to XMM register | |
| 6308 instruct load2IU(regD dst, memory mem) %{ | |
| 6309 match(Set dst (Load2I mem)); | |
| 6310 ins_cost(125); | |
| 6311 format %{ "MOVQ $dst,$mem\t! packed2I" %} | |
| 6312 ins_encode( movq_ld(dst, mem)); | |
| 6313 ins_pipe( pipe_slow ); | |
| 6314 %} | |
| 6315 | |
| 6316 // Load Aligned Packed Single to XMM | |
| 6317 instruct loadA2F(regD dst, memory mem) %{ | |
| 6318 match(Set dst (Load2F mem)); | |
| 6319 ins_cost(145); | |
| 6320 format %{ "MOVQ $dst,$mem\t! packed2F" %} | |
| 6321 ins_encode( movq_ld(dst, mem)); | |
| 6322 ins_pipe( pipe_slow ); | |
| 6323 %} | |
| 6324 | |
| 6325 // Load Effective Address | |
| 6326 instruct leaP8(rRegP dst, indOffset8 mem) | |
| 6327 %{ | |
| 6328 match(Set dst mem); | |
| 6329 | |
| 6330 ins_cost(110); // XXX | |
| 6331 format %{ "leaq $dst, $mem\t# ptr 8" %} | |
| 6332 opcode(0x8D); | |
| 6333 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 6334 ins_pipe(ialu_reg_reg_fat); | |
| 6335 %} | |
| 6336 | |
| 6337 instruct leaP32(rRegP dst, indOffset32 mem) | |
| 6338 %{ | |
| 6339 match(Set dst mem); | |
| 6340 | |
| 6341 ins_cost(110); | |
| 6342 format %{ "leaq $dst, $mem\t# ptr 32" %} | |
| 6343 opcode(0x8D); | |
| 6344 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 6345 ins_pipe(ialu_reg_reg_fat); | |
| 6346 %} | |
| 6347 | |
| 6348 // instruct leaPIdx(rRegP dst, indIndex mem) | |
| 6349 // %{ | |
| 6350 // match(Set dst mem); | |
| 6351 | |
| 6352 // ins_cost(110); | |
| 6353 // format %{ "leaq $dst, $mem\t# ptr idx" %} | |
| 6354 // opcode(0x8D); | |
| 6355 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 6356 // ins_pipe(ialu_reg_reg_fat); | |
| 6357 // %} | |
| 6358 | |
| 6359 instruct leaPIdxOff(rRegP dst, indIndexOffset mem) | |
| 6360 %{ | |
| 6361 match(Set dst mem); | |
| 6362 | |
| 6363 ins_cost(110); | |
| 6364 format %{ "leaq $dst, $mem\t# ptr idxoff" %} | |
| 6365 opcode(0x8D); | |
| 6366 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 6367 ins_pipe(ialu_reg_reg_fat); | |
| 6368 %} | |
| 6369 | |
| 6370 instruct leaPIdxScale(rRegP dst, indIndexScale mem) | |
| 6371 %{ | |
| 6372 match(Set dst mem); | |
| 6373 | |
| 6374 ins_cost(110); | |
| 6375 format %{ "leaq $dst, $mem\t# ptr idxscale" %} | |
| 6376 opcode(0x8D); | |
| 6377 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 6378 ins_pipe(ialu_reg_reg_fat); | |
| 6379 %} | |
| 6380 | |
| 6381 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem) | |
| 6382 %{ | |
| 6383 match(Set dst mem); | |
| 6384 | |
| 6385 ins_cost(110); | |
| 6386 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %} | |
| 6387 opcode(0x8D); | |
| 6388 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 6389 ins_pipe(ialu_reg_reg_fat); | |
| 6390 %} | |
| 6391 | |
|
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6392 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem) |
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6393 %{ |
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6394 match(Set dst mem); |
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6395 |
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6396 ins_cost(110); |
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6397 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %} |
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6398 opcode(0x8D); |
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6399 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
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6400 ins_pipe(ialu_reg_reg_fat); |
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6401 %} |
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6402 |
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6403 // Load Effective Address which uses Narrow (32-bits) oop |
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6404 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem) |
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6405 %{ |
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6406 predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0)); |
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6407 match(Set dst mem); |
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6408 |
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6409 ins_cost(110); |
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6410 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %} |
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6411 opcode(0x8D); |
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6412 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
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6413 ins_pipe(ialu_reg_reg_fat); |
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6414 %} |
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6415 |
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kvn
parents:
624
diff
changeset
|
6416 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6417 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6418 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6419 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6420 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6421 ins_cost(110); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6422 format %{ "leaq $dst, $mem\t# ptr off8narrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6423 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6424 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6425 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6426 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6427 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6428 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6429 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6430 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6431 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6432 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6433 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6434 format %{ "leaq $dst, $mem\t# ptr off32narrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6435 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6436 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6437 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6438 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6439 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6440 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6441 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6442 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6443 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6444 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6445 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6446 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6447 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6448 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6449 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6450 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6451 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6452 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6453 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6454 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6455 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6456 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6457 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6458 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6459 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6460 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6461 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6462 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6463 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
6464 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem) |
|
660978a2a31a
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kvn
parents:
624
diff
changeset
|
6465 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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parents:
624
diff
changeset
|
6466 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6467 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6468 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6469 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6470 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6471 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6472 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6473 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6474 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6475 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6476 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6477 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6478 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6479 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6480 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6481 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6482 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6483 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6484 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6485 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6486 %} |
|
660978a2a31a
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kvn
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624
diff
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|
6487 |
| 0 | 6488 instruct loadConI(rRegI dst, immI src) |
| 6489 %{ | |
| 6490 match(Set dst src); | |
| 6491 | |
| 6492 format %{ "movl $dst, $src\t# int" %} | |
| 6493 ins_encode(load_immI(dst, src)); | |
| 6494 ins_pipe(ialu_reg_fat); // XXX | |
| 6495 %} | |
| 6496 | |
| 6497 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr) | |
| 6498 %{ | |
| 6499 match(Set dst src); | |
| 6500 effect(KILL cr); | |
| 6501 | |
| 6502 ins_cost(50); | |
| 6503 format %{ "xorl $dst, $dst\t# int" %} | |
| 6504 opcode(0x33); /* + rd */ | |
| 6505 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst)); | |
| 6506 ins_pipe(ialu_reg); | |
| 6507 %} | |
| 6508 | |
| 6509 instruct loadConL(rRegL dst, immL src) | |
| 6510 %{ | |
| 6511 match(Set dst src); | |
| 6512 | |
| 6513 ins_cost(150); | |
| 6514 format %{ "movq $dst, $src\t# long" %} | |
| 6515 ins_encode(load_immL(dst, src)); | |
| 6516 ins_pipe(ialu_reg); | |
| 6517 %} | |
| 6518 | |
| 6519 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr) | |
| 6520 %{ | |
| 6521 match(Set dst src); | |
| 6522 effect(KILL cr); | |
| 6523 | |
| 6524 ins_cost(50); | |
| 6525 format %{ "xorl $dst, $dst\t# long" %} | |
| 6526 opcode(0x33); /* + rd */ | |
| 6527 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst)); | |
| 6528 ins_pipe(ialu_reg); // XXX | |
| 6529 %} | |
| 6530 | |
| 6531 instruct loadConUL32(rRegL dst, immUL32 src) | |
| 6532 %{ | |
| 6533 match(Set dst src); | |
| 6534 | |
| 6535 ins_cost(60); | |
| 6536 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %} | |
| 6537 ins_encode(load_immUL32(dst, src)); | |
| 6538 ins_pipe(ialu_reg); | |
| 6539 %} | |
| 6540 | |
| 6541 instruct loadConL32(rRegL dst, immL32 src) | |
| 6542 %{ | |
| 6543 match(Set dst src); | |
| 6544 | |
| 6545 ins_cost(70); | |
| 6546 format %{ "movq $dst, $src\t# long (32-bit)" %} | |
| 6547 ins_encode(load_immL32(dst, src)); | |
| 6548 ins_pipe(ialu_reg); | |
| 6549 %} | |
| 6550 | |
| 2008 | 6551 instruct loadConP(rRegP dst, immP con) %{ |
| 6552 match(Set dst con); | |
| 6553 | |
| 6554 format %{ "movq $dst, $con\t# ptr" %} | |
| 6555 ins_encode(load_immP(dst, con)); | |
| 0 | 6556 ins_pipe(ialu_reg_fat); // XXX |
| 6557 %} | |
| 6558 | |
| 6559 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr) | |
| 6560 %{ | |
| 6561 match(Set dst src); | |
| 6562 effect(KILL cr); | |
| 6563 | |
| 6564 ins_cost(50); | |
| 6565 format %{ "xorl $dst, $dst\t# ptr" %} | |
| 6566 opcode(0x33); /* + rd */ | |
| 6567 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst)); | |
| 6568 ins_pipe(ialu_reg); | |
| 6569 %} | |
| 6570 | |
| 6571 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr) | |
| 6572 %{ | |
| 6573 match(Set dst src); | |
| 6574 effect(KILL cr); | |
| 6575 | |
| 6576 ins_cost(60); | |
| 6577 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %} | |
| 6578 ins_encode(load_immP31(dst, src)); | |
| 6579 ins_pipe(ialu_reg); | |
| 6580 %} | |
| 6581 | |
| 2008 | 6582 instruct loadConF(regF dst, immF con) %{ |
| 6583 match(Set dst con); | |
| 0 | 6584 ins_cost(125); |
| 2008 | 6585 format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %} |
| 6586 ins_encode %{ | |
| 6587 __ movflt($dst$$XMMRegister, $constantaddress($con)); | |
| 6588 %} | |
| 0 | 6589 ins_pipe(pipe_slow); |
| 6590 %} | |
| 6591 | |
|
113
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|
6592 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{ |
|
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|
6593 match(Set dst src); |
|
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|
6594 effect(KILL cr); |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
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diff
changeset
|
6595 format %{ "xorq $dst, $src\t# compressed NULL ptr" %} |
|
113
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|
6596 ins_encode %{ |
|
642
660978a2a31a
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changeset
|
6597 __ xorq($dst$$Register, $dst$$Register); |
|
113
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|
6598 %} |
|
ba764ed4b6f2
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changeset
|
6599 ins_pipe(ialu_reg); |
|
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|
6600 %} |
|
ba764ed4b6f2
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|
6601 |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6602 instruct loadConN(rRegN dst, immN src) %{ |
|
113
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|
6603 match(Set dst src); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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|
6604 |
|
ba764ed4b6f2
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coleenp
parents:
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diff
changeset
|
6605 ins_cost(125); |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
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parents:
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|
6606 format %{ "movl $dst, $src\t# compressed ptr" %} |
|
113
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|
6607 ins_encode %{ |
|
ba764ed4b6f2
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|
6608 address con = (address)$src$$constant; |
|
ba764ed4b6f2
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|
6609 if (con == NULL) { |
|
ba764ed4b6f2
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|
6610 ShouldNotReachHere(); |
|
ba764ed4b6f2
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|
6611 } else { |
|
642
660978a2a31a
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parents:
624
diff
changeset
|
6612 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant); |
|
113
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|
6613 } |
|
ba764ed4b6f2
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|
6614 %} |
|
ba764ed4b6f2
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|
6615 ins_pipe(ialu_reg_fat); // XXX |
|
ba764ed4b6f2
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|
6616 %} |
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6617 |
| 0 | 6618 instruct loadConF0(regF dst, immF0 src) |
| 6619 %{ | |
| 6620 match(Set dst src); | |
| 6621 ins_cost(100); | |
| 6622 | |
| 6623 format %{ "xorps $dst, $dst\t# float 0.0" %} | |
| 6624 opcode(0x0F, 0x57); | |
| 6625 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 6626 ins_pipe(pipe_slow); | |
| 6627 %} | |
| 6628 | |
| 6629 // Use the same format since predicate() can not be used here. | |
| 2008 | 6630 instruct loadConD(regD dst, immD con) %{ |
| 6631 match(Set dst con); | |
| 0 | 6632 ins_cost(125); |
| 2008 | 6633 format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %} |
| 6634 ins_encode %{ | |
| 6635 __ movdbl($dst$$XMMRegister, $constantaddress($con)); | |
| 6636 %} | |
| 0 | 6637 ins_pipe(pipe_slow); |
| 6638 %} | |
| 6639 | |
| 6640 instruct loadConD0(regD dst, immD0 src) | |
| 6641 %{ | |
| 6642 match(Set dst src); | |
| 6643 ins_cost(100); | |
| 6644 | |
| 6645 format %{ "xorpd $dst, $dst\t# double 0.0" %} | |
| 6646 opcode(0x66, 0x0F, 0x57); | |
| 6647 ins_encode(OpcP, REX_reg_reg(dst, dst), OpcS, OpcT, reg_reg(dst, dst)); | |
| 6648 ins_pipe(pipe_slow); | |
| 6649 %} | |
| 6650 | |
| 6651 instruct loadSSI(rRegI dst, stackSlotI src) | |
| 6652 %{ | |
| 6653 match(Set dst src); | |
| 6654 | |
| 6655 ins_cost(125); | |
| 6656 format %{ "movl $dst, $src\t# int stk" %} | |
| 6657 opcode(0x8B); | |
| 6658 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 6659 ins_pipe(ialu_reg_mem); | |
| 6660 %} | |
| 6661 | |
| 6662 instruct loadSSL(rRegL dst, stackSlotL src) | |
| 6663 %{ | |
| 6664 match(Set dst src); | |
| 6665 | |
| 6666 ins_cost(125); | |
| 6667 format %{ "movq $dst, $src\t# long stk" %} | |
| 6668 opcode(0x8B); | |
| 6669 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 6670 ins_pipe(ialu_reg_mem); | |
| 6671 %} | |
| 6672 | |
| 6673 instruct loadSSP(rRegP dst, stackSlotP src) | |
| 6674 %{ | |
| 6675 match(Set dst src); | |
| 6676 | |
| 6677 ins_cost(125); | |
| 6678 format %{ "movq $dst, $src\t# ptr stk" %} | |
| 6679 opcode(0x8B); | |
| 6680 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 6681 ins_pipe(ialu_reg_mem); | |
| 6682 %} | |
| 6683 | |
| 6684 instruct loadSSF(regF dst, stackSlotF src) | |
| 6685 %{ | |
| 6686 match(Set dst src); | |
| 6687 | |
| 6688 ins_cost(125); | |
| 6689 format %{ "movss $dst, $src\t# float stk" %} | |
| 6690 opcode(0xF3, 0x0F, 0x10); | |
| 6691 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 6692 ins_pipe(pipe_slow); // XXX | |
| 6693 %} | |
| 6694 | |
| 6695 // Use the same format since predicate() can not be used here. | |
| 6696 instruct loadSSD(regD dst, stackSlotD src) | |
| 6697 %{ | |
| 6698 match(Set dst src); | |
| 6699 | |
| 6700 ins_cost(125); | |
| 6701 format %{ "movsd $dst, $src\t# double stk" %} | |
| 6702 ins_encode %{ | |
| 6703 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 6704 %} | |
| 6705 ins_pipe(pipe_slow); // XXX | |
| 6706 %} | |
| 6707 | |
| 6708 // Prefetch instructions. | |
| 6709 // Must be safe to execute with invalid address (cannot fault). | |
| 6710 | |
| 6711 instruct prefetchr( memory mem ) %{ | |
| 6712 predicate(ReadPrefetchInstr==3); | |
| 6713 match(PrefetchRead mem); | |
| 6714 ins_cost(125); | |
| 6715 | |
| 6716 format %{ "PREFETCHR $mem\t# Prefetch into level 1 cache" %} | |
| 6717 opcode(0x0F, 0x0D); /* Opcode 0F 0D /0 */ | |
| 6718 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x00, mem)); | |
| 6719 ins_pipe(ialu_mem); | |
| 6720 %} | |
| 6721 | |
| 6722 instruct prefetchrNTA( memory mem ) %{ | |
| 6723 predicate(ReadPrefetchInstr==0); | |
| 6724 match(PrefetchRead mem); | |
| 6725 ins_cost(125); | |
| 6726 | |
| 6727 format %{ "PREFETCHNTA $mem\t# Prefetch into non-temporal cache for read" %} | |
| 6728 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */ | |
| 6729 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x00, mem)); | |
| 6730 ins_pipe(ialu_mem); | |
| 6731 %} | |
| 6732 | |
| 6733 instruct prefetchrT0( memory mem ) %{ | |
| 6734 predicate(ReadPrefetchInstr==1); | |
| 6735 match(PrefetchRead mem); | |
| 6736 ins_cost(125); | |
| 6737 | |
| 6738 format %{ "PREFETCHT0 $mem\t# prefetch into L1 and L2 caches for read" %} | |
| 6739 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */ | |
| 6740 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x01, mem)); | |
| 6741 ins_pipe(ialu_mem); | |
| 6742 %} | |
| 6743 | |
| 6744 instruct prefetchrT2( memory mem ) %{ | |
| 6745 predicate(ReadPrefetchInstr==2); | |
| 6746 match(PrefetchRead mem); | |
| 6747 ins_cost(125); | |
| 6748 | |
| 6749 format %{ "PREFETCHT2 $mem\t# prefetch into L2 caches for read" %} | |
| 6750 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */ | |
| 6751 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x03, mem)); | |
| 6752 ins_pipe(ialu_mem); | |
| 6753 %} | |
| 6754 | |
| 6755 instruct prefetchw( memory mem ) %{ | |
| 6756 predicate(AllocatePrefetchInstr==3); | |
| 6757 match(PrefetchWrite mem); | |
| 6758 ins_cost(125); | |
| 6759 | |
| 6760 format %{ "PREFETCHW $mem\t# Prefetch into level 1 cache and mark modified" %} | |
| 6761 opcode(0x0F, 0x0D); /* Opcode 0F 0D /1 */ | |
| 6762 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x01, mem)); | |
| 6763 ins_pipe(ialu_mem); | |
| 6764 %} | |
| 6765 | |
| 6766 instruct prefetchwNTA( memory mem ) %{ | |
| 6767 predicate(AllocatePrefetchInstr==0); | |
| 6768 match(PrefetchWrite mem); | |
| 6769 ins_cost(125); | |
| 6770 | |
| 6771 format %{ "PREFETCHNTA $mem\t# Prefetch to non-temporal cache for write" %} | |
| 6772 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */ | |
| 6773 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x00, mem)); | |
| 6774 ins_pipe(ialu_mem); | |
| 6775 %} | |
| 6776 | |
| 6777 instruct prefetchwT0( memory mem ) %{ | |
| 6778 predicate(AllocatePrefetchInstr==1); | |
| 6779 match(PrefetchWrite mem); | |
| 6780 ins_cost(125); | |
| 6781 | |
| 6782 format %{ "PREFETCHT0 $mem\t# Prefetch to level 1 and 2 caches for write" %} | |
| 6783 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */ | |
| 6784 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x01, mem)); | |
| 6785 ins_pipe(ialu_mem); | |
| 6786 %} | |
| 6787 | |
| 6788 instruct prefetchwT2( memory mem ) %{ | |
| 6789 predicate(AllocatePrefetchInstr==2); | |
| 6790 match(PrefetchWrite mem); | |
| 6791 ins_cost(125); | |
| 6792 | |
| 6793 format %{ "PREFETCHT2 $mem\t# Prefetch to level 2 cache for write" %} | |
| 6794 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */ | |
| 6795 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x03, mem)); | |
| 6796 ins_pipe(ialu_mem); | |
| 6797 %} | |
| 6798 | |
| 6799 //----------Store Instructions------------------------------------------------- | |
| 6800 | |
| 6801 // Store Byte | |
| 6802 instruct storeB(memory mem, rRegI src) | |
| 6803 %{ | |
| 6804 match(Set mem (StoreB mem src)); | |
| 6805 | |
| 6806 ins_cost(125); // XXX | |
| 6807 format %{ "movb $mem, $src\t# byte" %} | |
| 6808 opcode(0x88); | |
| 6809 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
| 6810 ins_pipe(ialu_mem_reg); | |
| 6811 %} | |
| 6812 | |
| 6813 // Store Char/Short | |
| 6814 instruct storeC(memory mem, rRegI src) | |
| 6815 %{ | |
| 6816 match(Set mem (StoreC mem src)); | |
| 6817 | |
| 6818 ins_cost(125); // XXX | |
| 6819 format %{ "movw $mem, $src\t# char/short" %} | |
| 6820 opcode(0x89); | |
| 6821 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
| 6822 ins_pipe(ialu_mem_reg); | |
| 6823 %} | |
| 6824 | |
| 6825 // Store Integer | |
| 6826 instruct storeI(memory mem, rRegI src) | |
| 6827 %{ | |
| 6828 match(Set mem (StoreI mem src)); | |
| 6829 | |
| 6830 ins_cost(125); // XXX | |
| 6831 format %{ "movl $mem, $src\t# int" %} | |
| 6832 opcode(0x89); | |
| 6833 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
| 6834 ins_pipe(ialu_mem_reg); | |
| 6835 %} | |
| 6836 | |
| 6837 // Store Long | |
| 6838 instruct storeL(memory mem, rRegL src) | |
| 6839 %{ | |
| 6840 match(Set mem (StoreL mem src)); | |
| 6841 | |
| 6842 ins_cost(125); // XXX | |
| 6843 format %{ "movq $mem, $src\t# long" %} | |
| 6844 opcode(0x89); | |
| 6845 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem)); | |
| 6846 ins_pipe(ialu_mem_reg); // XXX | |
| 6847 %} | |
| 6848 | |
| 6849 // Store Pointer | |
| 6850 instruct storeP(memory mem, any_RegP src) | |
| 6851 %{ | |
| 6852 match(Set mem (StoreP mem src)); | |
| 6853 | |
| 6854 ins_cost(125); // XXX | |
| 6855 format %{ "movq $mem, $src\t# ptr" %} | |
| 6856 opcode(0x89); | |
| 6857 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem)); | |
| 6858 ins_pipe(ialu_mem_reg); | |
| 6859 %} | |
| 6860 | |
|
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6861 instruct storeImmP0(memory mem, immP0 zero) |
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6862 %{ |
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6863 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
|
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6864 match(Set mem (StoreP mem zero)); |
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6865 |
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6866 ins_cost(125); // XXX |
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6867 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %} |
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6868 ins_encode %{ |
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6869 __ movq($mem$$Address, r12); |
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6870 %} |
|
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6871 ins_pipe(ialu_mem_reg); |
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6872 %} |
|
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6873 |
| 0 | 6874 // Store NULL Pointer, mark word, or other simple pointer constant. |
| 6875 instruct storeImmP(memory mem, immP31 src) | |
| 6876 %{ | |
| 6877 match(Set mem (StoreP mem src)); | |
| 6878 | |
|
642
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6879 ins_cost(150); // XXX |
| 0 | 6880 format %{ "movq $mem, $src\t# ptr" %} |
| 6881 opcode(0xC7); /* C7 /0 */ | |
| 6882 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); | |
| 6883 ins_pipe(ialu_mem_imm); | |
| 6884 %} | |
| 6885 | |
|
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6886 // Store Compressed Pointer |
| 163 | 6887 instruct storeN(memory mem, rRegN src) |
|
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6888 %{ |
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6889 match(Set mem (StoreN mem src)); |
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6890 |
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6891 ins_cost(125); // XXX |
|
164
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6892 format %{ "movl $mem, $src\t# compressed ptr" %} |
|
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6893 ins_encode %{ |
|
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6894 __ movl($mem$$Address, $src$$Register); |
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6895 %} |
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6896 ins_pipe(ialu_mem_reg); |
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6897 %} |
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6898 |
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6899 instruct storeImmN0(memory mem, immN0 zero) |
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6900 %{ |
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6901 predicate(Universe::narrow_oop_base() == NULL); |
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6902 match(Set mem (StoreN mem zero)); |
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6903 |
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6904 ins_cost(125); // XXX |
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6905 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %} |
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6906 ins_encode %{ |
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6907 __ movl($mem$$Address, r12); |
|
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6908 %} |
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6909 ins_pipe(ialu_mem_reg); |
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6910 %} |
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6911 |
|
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6912 instruct storeImmN(memory mem, immN src) |
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6913 %{ |
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6914 match(Set mem (StoreN mem src)); |
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6915 |
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6916 ins_cost(150); // XXX |
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6917 format %{ "movl $mem, $src\t# compressed ptr" %} |
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6918 ins_encode %{ |
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6919 address con = (address)$src$$constant; |
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6920 if (con == NULL) { |
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6921 __ movl($mem$$Address, (int32_t)0); |
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6922 } else { |
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6923 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant); |
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6924 } |
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6925 %} |
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6926 ins_pipe(ialu_mem_imm); |
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6927 %} |
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6928 |
| 0 | 6929 // Store Integer Immediate |
|
642
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6930 instruct storeImmI0(memory mem, immI0 zero) |
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6931 %{ |
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changeset
|
6932 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6933 match(Set mem (StoreI mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6934 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6935 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6936 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6937 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6938 __ movl($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6939 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6940 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6941 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6942 |
| 0 | 6943 instruct storeImmI(memory mem, immI src) |
| 6944 %{ | |
| 6945 match(Set mem (StoreI mem src)); | |
| 6946 | |
| 6947 ins_cost(150); | |
| 6948 format %{ "movl $mem, $src\t# int" %} | |
| 6949 opcode(0xC7); /* C7 /0 */ | |
| 6950 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); | |
| 6951 ins_pipe(ialu_mem_imm); | |
| 6952 %} | |
| 6953 | |
| 6954 // Store Long Immediate | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6955 instruct storeImmL0(memory mem, immL0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6956 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6957 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6958 match(Set mem (StoreL mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6959 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6960 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6961 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6962 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6963 __ movq($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6964 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6965 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6966 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6967 |
| 0 | 6968 instruct storeImmL(memory mem, immL32 src) |
| 6969 %{ | |
| 6970 match(Set mem (StoreL mem src)); | |
| 6971 | |
| 6972 ins_cost(150); | |
| 6973 format %{ "movq $mem, $src\t# long" %} | |
| 6974 opcode(0xC7); /* C7 /0 */ | |
| 6975 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); | |
| 6976 ins_pipe(ialu_mem_imm); | |
| 6977 %} | |
| 6978 | |
| 6979 // Store Short/Char Immediate | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6980 instruct storeImmC0(memory mem, immI0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6981 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6982 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6983 match(Set mem (StoreC mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6984 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6985 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6986 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6987 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6988 __ movw($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6989 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6990 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6991 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6992 |
| 0 | 6993 instruct storeImmI16(memory mem, immI16 src) |
| 6994 %{ | |
| 6995 predicate(UseStoreImmI16); | |
| 6996 match(Set mem (StoreC mem src)); | |
| 6997 | |
| 6998 ins_cost(150); | |
| 6999 format %{ "movw $mem, $src\t# short/char" %} | |
| 7000 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */ | |
| 7001 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src)); | |
| 7002 ins_pipe(ialu_mem_imm); | |
| 7003 %} | |
| 7004 | |
| 7005 // Store Byte Immediate | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7006 instruct storeImmB0(memory mem, immI0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7007 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7008 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7009 match(Set mem (StoreB mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7010 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7011 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7012 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7013 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7014 __ movb($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7015 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7016 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7017 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7018 |
| 0 | 7019 instruct storeImmB(memory mem, immI8 src) |
| 7020 %{ | |
| 7021 match(Set mem (StoreB mem src)); | |
| 7022 | |
| 7023 ins_cost(150); // XXX | |
| 7024 format %{ "movb $mem, $src\t# byte" %} | |
| 7025 opcode(0xC6); /* C6 /0 */ | |
| 7026 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src)); | |
| 7027 ins_pipe(ialu_mem_imm); | |
| 7028 %} | |
| 7029 | |
| 7030 // Store Aligned Packed Byte XMM register to memory | |
| 7031 instruct storeA8B(memory mem, regD src) %{ | |
| 7032 match(Set mem (Store8B mem src)); | |
| 7033 ins_cost(145); | |
| 7034 format %{ "MOVQ $mem,$src\t! packed8B" %} | |
| 7035 ins_encode( movq_st(mem, src)); | |
| 7036 ins_pipe( pipe_slow ); | |
| 7037 %} | |
| 7038 | |
| 7039 // Store Aligned Packed Char/Short XMM register to memory | |
| 7040 instruct storeA4C(memory mem, regD src) %{ | |
| 7041 match(Set mem (Store4C mem src)); | |
| 7042 ins_cost(145); | |
| 7043 format %{ "MOVQ $mem,$src\t! packed4C" %} | |
| 7044 ins_encode( movq_st(mem, src)); | |
| 7045 ins_pipe( pipe_slow ); | |
| 7046 %} | |
| 7047 | |
| 7048 // Store Aligned Packed Integer XMM register to memory | |
| 7049 instruct storeA2I(memory mem, regD src) %{ | |
| 7050 match(Set mem (Store2I mem src)); | |
| 7051 ins_cost(145); | |
| 7052 format %{ "MOVQ $mem,$src\t! packed2I" %} | |
| 7053 ins_encode( movq_st(mem, src)); | |
| 7054 ins_pipe( pipe_slow ); | |
| 7055 %} | |
| 7056 | |
| 7057 // Store CMS card-mark Immediate | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7058 instruct storeImmCM0_reg(memory mem, immI0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7059 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7060 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7061 match(Set mem (StoreCM mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7062 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7063 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7064 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7065 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7066 __ movb($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7067 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7068 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7069 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7070 |
| 0 | 7071 instruct storeImmCM0(memory mem, immI0 src) |
| 7072 %{ | |
| 7073 match(Set mem (StoreCM mem src)); | |
| 7074 | |
| 7075 ins_cost(150); // XXX | |
| 7076 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %} | |
| 7077 opcode(0xC6); /* C6 /0 */ | |
| 7078 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src)); | |
| 7079 ins_pipe(ialu_mem_imm); | |
| 7080 %} | |
| 7081 | |
| 7082 // Store Aligned Packed Single Float XMM register to memory | |
| 7083 instruct storeA2F(memory mem, regD src) %{ | |
| 7084 match(Set mem (Store2F mem src)); | |
| 7085 ins_cost(145); | |
| 7086 format %{ "MOVQ $mem,$src\t! packed2F" %} | |
| 7087 ins_encode( movq_st(mem, src)); | |
| 7088 ins_pipe( pipe_slow ); | |
| 7089 %} | |
| 7090 | |
| 7091 // Store Float | |
| 7092 instruct storeF(memory mem, regF src) | |
| 7093 %{ | |
| 7094 match(Set mem (StoreF mem src)); | |
| 7095 | |
| 7096 ins_cost(95); // XXX | |
| 7097 format %{ "movss $mem, $src\t# float" %} | |
| 7098 opcode(0xF3, 0x0F, 0x11); | |
| 7099 ins_encode(OpcP, REX_reg_mem(src, mem), OpcS, OpcT, reg_mem(src, mem)); | |
| 7100 ins_pipe(pipe_slow); // XXX | |
| 7101 %} | |
| 7102 | |
| 7103 // Store immediate Float value (it is faster than store from XMM register) | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7104 instruct storeF0(memory mem, immF0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7105 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7106 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7107 match(Set mem (StoreF mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7108 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7109 ins_cost(25); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7110 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7111 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7112 __ movl($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7113 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7114 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7115 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7116 |
| 0 | 7117 instruct storeF_imm(memory mem, immF src) |
| 7118 %{ | |
| 7119 match(Set mem (StoreF mem src)); | |
| 7120 | |
| 7121 ins_cost(50); | |
| 7122 format %{ "movl $mem, $src\t# float" %} | |
| 7123 opcode(0xC7); /* C7 /0 */ | |
| 7124 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src)); | |
| 7125 ins_pipe(ialu_mem_imm); | |
| 7126 %} | |
| 7127 | |
| 7128 // Store Double | |
| 7129 instruct storeD(memory mem, regD src) | |
| 7130 %{ | |
| 7131 match(Set mem (StoreD mem src)); | |
| 7132 | |
| 7133 ins_cost(95); // XXX | |
| 7134 format %{ "movsd $mem, $src\t# double" %} | |
| 7135 opcode(0xF2, 0x0F, 0x11); | |
| 7136 ins_encode(OpcP, REX_reg_mem(src, mem), OpcS, OpcT, reg_mem(src, mem)); | |
| 7137 ins_pipe(pipe_slow); // XXX | |
| 7138 %} | |
| 7139 | |
| 7140 // Store immediate double 0.0 (it is faster than store from XMM register) | |
| 7141 instruct storeD0_imm(memory mem, immD0 src) | |
| 7142 %{ | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7143 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL)); |
| 0 | 7144 match(Set mem (StoreD mem src)); |
| 7145 | |
| 7146 ins_cost(50); | |
| 7147 format %{ "movq $mem, $src\t# double 0." %} | |
| 7148 opcode(0xC7); /* C7 /0 */ | |
| 7149 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src)); | |
| 7150 ins_pipe(ialu_mem_imm); | |
| 7151 %} | |
| 7152 | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7153 instruct storeD0(memory mem, immD0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7154 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7155 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7156 match(Set mem (StoreD mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7157 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7158 ins_cost(25); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7159 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7160 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7161 __ movq($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7162 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7163 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7164 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7165 |
| 0 | 7166 instruct storeSSI(stackSlotI dst, rRegI src) |
| 7167 %{ | |
| 7168 match(Set dst src); | |
| 7169 | |
| 7170 ins_cost(100); | |
| 7171 format %{ "movl $dst, $src\t# int stk" %} | |
| 7172 opcode(0x89); | |
| 7173 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 7174 ins_pipe( ialu_mem_reg ); | |
| 7175 %} | |
| 7176 | |
| 7177 instruct storeSSL(stackSlotL dst, rRegL src) | |
| 7178 %{ | |
| 7179 match(Set dst src); | |
| 7180 | |
| 7181 ins_cost(100); | |
| 7182 format %{ "movq $dst, $src\t# long stk" %} | |
| 7183 opcode(0x89); | |
| 7184 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 7185 ins_pipe(ialu_mem_reg); | |
| 7186 %} | |
| 7187 | |
| 7188 instruct storeSSP(stackSlotP dst, rRegP src) | |
| 7189 %{ | |
| 7190 match(Set dst src); | |
| 7191 | |
| 7192 ins_cost(100); | |
| 7193 format %{ "movq $dst, $src\t# ptr stk" %} | |
| 7194 opcode(0x89); | |
| 7195 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 7196 ins_pipe(ialu_mem_reg); | |
| 7197 %} | |
| 7198 | |
| 7199 instruct storeSSF(stackSlotF dst, regF src) | |
| 7200 %{ | |
| 7201 match(Set dst src); | |
| 7202 | |
| 7203 ins_cost(95); // XXX | |
| 7204 format %{ "movss $dst, $src\t# float stk" %} | |
| 7205 opcode(0xF3, 0x0F, 0x11); | |
| 7206 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst)); | |
| 7207 ins_pipe(pipe_slow); // XXX | |
| 7208 %} | |
| 7209 | |
| 7210 instruct storeSSD(stackSlotD dst, regD src) | |
| 7211 %{ | |
| 7212 match(Set dst src); | |
| 7213 | |
| 7214 ins_cost(95); // XXX | |
| 7215 format %{ "movsd $dst, $src\t# double stk" %} | |
| 7216 opcode(0xF2, 0x0F, 0x11); | |
| 7217 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst)); | |
| 7218 ins_pipe(pipe_slow); // XXX | |
| 7219 %} | |
| 7220 | |
| 7221 //----------BSWAP Instructions------------------------------------------------- | |
| 7222 instruct bytes_reverse_int(rRegI dst) %{ | |
| 7223 match(Set dst (ReverseBytesI dst)); | |
| 7224 | |
| 7225 format %{ "bswapl $dst" %} | |
| 7226 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */ | |
| 7227 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) ); | |
| 7228 ins_pipe( ialu_reg ); | |
| 7229 %} | |
| 7230 | |
| 7231 instruct bytes_reverse_long(rRegL dst) %{ | |
| 7232 match(Set dst (ReverseBytesL dst)); | |
| 7233 | |
| 7234 format %{ "bswapq $dst" %} | |
| 7235 | |
| 7236 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */ | |
| 7237 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) ); | |
| 7238 ins_pipe( ialu_reg); | |
| 7239 %} | |
| 7240 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7241 instruct bytes_reverse_unsigned_short(rRegI dst) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7242 match(Set dst (ReverseBytesUS dst)); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7243 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7244 format %{ "bswapl $dst\n\t" |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7245 "shrl $dst,16\n\t" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7246 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7247 __ bswapl($dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7248 __ shrl($dst$$Register, 16); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7249 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7250 ins_pipe( ialu_reg ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7251 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7252 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7253 instruct bytes_reverse_short(rRegI dst) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7254 match(Set dst (ReverseBytesS dst)); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7255 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7256 format %{ "bswapl $dst\n\t" |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7257 "sar $dst,16\n\t" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7258 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7259 __ bswapl($dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7260 __ sarl($dst$$Register, 16); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7261 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7262 ins_pipe( ialu_reg ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7263 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7264 |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7265 //---------- Zeros Count Instructions ------------------------------------------ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7266 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7267 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7268 predicate(UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7269 match(Set dst (CountLeadingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7270 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7271 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7272 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7273 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7274 __ lzcntl($dst$$Register, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7275 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7276 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7277 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7278 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7279 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7280 predicate(!UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7281 match(Set dst (CountLeadingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7282 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7283 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7284 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7285 "jnz skip\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7286 "movl $dst, -1\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7287 "skip:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7288 "negl $dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7289 "addl $dst, 31" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7290 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7291 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7292 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7293 Label skip; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7294 __ bsrl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7295 __ jccb(Assembler::notZero, skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7296 __ movl(Rdst, -1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7297 __ bind(skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7298 __ negl(Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7299 __ addl(Rdst, BitsPerInt - 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7300 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7301 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7302 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7303 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7304 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7305 predicate(UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7306 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7307 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7308 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7309 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7310 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7311 __ lzcntq($dst$$Register, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7312 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7313 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7314 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7315 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7316 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7317 predicate(!UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7318 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7319 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7320 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7321 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7322 "jnz skip\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7323 "movl $dst, -1\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7324 "skip:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7325 "negl $dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7326 "addl $dst, 63" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7327 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7328 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7329 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7330 Label skip; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7331 __ bsrq(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7332 __ jccb(Assembler::notZero, skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7333 __ movl(Rdst, -1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7334 __ bind(skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7335 __ negl(Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7336 __ addl(Rdst, BitsPerLong - 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7337 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7338 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7339 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7340 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7341 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7342 match(Set dst (CountTrailingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7343 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7344 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7345 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7346 "jnz done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7347 "movl $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7348 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7349 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7350 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7351 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7352 __ bsfl(Rdst, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7353 __ jccb(Assembler::notZero, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7354 __ movl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7355 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7356 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7357 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7358 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7359 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7360 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7361 match(Set dst (CountTrailingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7362 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7363 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7364 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7365 "jnz done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7366 "movl $dst, 64\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7367 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7368 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7369 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7370 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7371 __ bsfq(Rdst, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7372 __ jccb(Assembler::notZero, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7373 __ movl(Rdst, BitsPerLong); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7374 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7375 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7376 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7377 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7378 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7379 |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7380 //---------- Population Count Instructions ------------------------------------- |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7381 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7382 instruct popCountI(rRegI dst, rRegI src) %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7383 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7384 match(Set dst (PopCountI src)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7385 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7386 format %{ "popcnt $dst, $src" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7387 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7388 __ popcntl($dst$$Register, $src$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7389 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7390 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7391 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7392 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7393 instruct popCountI_mem(rRegI dst, memory mem) %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7394 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7395 match(Set dst (PopCountI (LoadI mem))); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7396 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7397 format %{ "popcnt $dst, $mem" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7398 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7399 __ popcntl($dst$$Register, $mem$$Address); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7400 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7401 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7402 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7403 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7404 // Note: Long.bitCount(long) returns an int. |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7405 instruct popCountL(rRegI dst, rRegL src) %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7406 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7407 match(Set dst (PopCountL src)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7408 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7409 format %{ "popcnt $dst, $src" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7410 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7411 __ popcntq($dst$$Register, $src$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7412 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7413 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7414 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7415 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7416 // Note: Long.bitCount(long) returns an int. |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7417 instruct popCountL_mem(rRegI dst, memory mem) %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7418 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7419 match(Set dst (PopCountL (LoadL mem))); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7420 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7421 format %{ "popcnt $dst, $mem" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7422 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7423 __ popcntq($dst$$Register, $mem$$Address); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7424 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7425 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7426 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7427 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7428 |
| 0 | 7429 //----------MemBar Instructions----------------------------------------------- |
| 7430 // Memory barrier flavors | |
| 7431 | |
| 7432 instruct membar_acquire() | |
| 7433 %{ | |
| 7434 match(MemBarAcquire); | |
| 7435 ins_cost(0); | |
| 7436 | |
| 7437 size(0); | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7438 format %{ "MEMBAR-acquire ! (empty encoding)" %} |
| 0 | 7439 ins_encode(); |
| 7440 ins_pipe(empty); | |
| 7441 %} | |
| 7442 | |
| 7443 instruct membar_acquire_lock() | |
| 7444 %{ | |
| 7445 match(MemBarAcquire); | |
| 7446 predicate(Matcher::prior_fast_lock(n)); | |
| 7447 ins_cost(0); | |
| 7448 | |
| 7449 size(0); | |
| 7450 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %} | |
| 7451 ins_encode(); | |
| 7452 ins_pipe(empty); | |
| 7453 %} | |
| 7454 | |
| 7455 instruct membar_release() | |
| 7456 %{ | |
| 7457 match(MemBarRelease); | |
| 7458 ins_cost(0); | |
| 7459 | |
| 7460 size(0); | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7461 format %{ "MEMBAR-release ! (empty encoding)" %} |
| 0 | 7462 ins_encode(); |
| 7463 ins_pipe(empty); | |
| 7464 %} | |
| 7465 | |
| 7466 instruct membar_release_lock() | |
| 7467 %{ | |
| 7468 match(MemBarRelease); | |
| 7469 predicate(Matcher::post_fast_unlock(n)); | |
| 7470 ins_cost(0); | |
| 7471 | |
| 7472 size(0); | |
| 7473 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %} | |
| 7474 ins_encode(); | |
| 7475 ins_pipe(empty); | |
| 7476 %} | |
| 7477 | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7478 instruct membar_volatile(rFlagsReg cr) %{ |
| 0 | 7479 match(MemBarVolatile); |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7480 effect(KILL cr); |
| 0 | 7481 ins_cost(400); |
| 7482 | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7483 format %{ |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7484 $$template |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7485 if (os::is_MP()) { |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7486 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile" |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7487 } else { |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7488 $$emit$$"MEMBAR-volatile ! (empty encoding)" |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7489 } |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7490 %} |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7491 ins_encode %{ |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7492 __ membar(Assembler::StoreLoad); |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
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parents:
647
diff
changeset
|
7493 %} |
| 0 | 7494 ins_pipe(pipe_slow); |
| 7495 %} | |
| 7496 | |
| 7497 instruct unnecessary_membar_volatile() | |
| 7498 %{ | |
| 7499 match(MemBarVolatile); | |
| 7500 predicate(Matcher::post_store_load_barrier(n)); | |
| 7501 ins_cost(0); | |
| 7502 | |
| 7503 size(0); | |
| 7504 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %} | |
| 7505 ins_encode(); | |
| 7506 ins_pipe(empty); | |
| 7507 %} | |
| 7508 | |
| 7509 //----------Move Instructions-------------------------------------------------- | |
| 7510 | |
| 7511 instruct castX2P(rRegP dst, rRegL src) | |
| 7512 %{ | |
| 7513 match(Set dst (CastX2P src)); | |
| 7514 | |
| 7515 format %{ "movq $dst, $src\t# long->ptr" %} | |
| 7516 ins_encode(enc_copy_wide(dst, src)); | |
| 7517 ins_pipe(ialu_reg_reg); // XXX | |
| 7518 %} | |
| 7519 | |
| 7520 instruct castP2X(rRegL dst, rRegP src) | |
| 7521 %{ | |
| 7522 match(Set dst (CastP2X src)); | |
| 7523 | |
| 7524 format %{ "movq $dst, $src\t# ptr -> long" %} | |
| 7525 ins_encode(enc_copy_wide(dst, src)); | |
| 7526 ins_pipe(ialu_reg_reg); // XXX | |
| 7527 %} | |
| 7528 | |
|
113
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|
7529 |
|
ba764ed4b6f2
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diff
changeset
|
7530 // Convert oop pointer into compressed form |
|
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|
7531 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{ |
|
221
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|
7532 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); |
|
113
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|
7533 match(Set dst (EncodeP src)); |
|
ba764ed4b6f2
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71
diff
changeset
|
7534 effect(KILL cr); |
|
ba764ed4b6f2
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71
diff
changeset
|
7535 format %{ "encode_heap_oop $dst,$src" %} |
|
ba764ed4b6f2
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changeset
|
7536 ins_encode %{ |
|
ba764ed4b6f2
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diff
changeset
|
7537 Register s = $src$$Register; |
|
ba764ed4b6f2
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diff
changeset
|
7538 Register d = $dst$$Register; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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71
diff
changeset
|
7539 if (s != d) { |
|
ba764ed4b6f2
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coleenp
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71
diff
changeset
|
7540 __ movq(d, s); |
|
ba764ed4b6f2
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diff
changeset
|
7541 } |
|
ba764ed4b6f2
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changeset
|
7542 __ encode_heap_oop(d); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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changeset
|
7543 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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71
diff
changeset
|
7544 ins_pipe(ialu_reg_long); |
|
ba764ed4b6f2
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71
diff
changeset
|
7545 %} |
|
ba764ed4b6f2
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diff
changeset
|
7546 |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
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113
diff
changeset
|
7547 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{ |
|
221
1e026f8da827
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changeset
|
7548 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); |
|
124
b130b98db9cf
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kvn
parents:
113
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changeset
|
7549 match(Set dst (EncodeP src)); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
7550 effect(KILL cr); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
7551 format %{ "encode_heap_oop_not_null $dst,$src" %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
7552 ins_encode %{ |
|
642
660978a2a31a
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changeset
|
7553 __ encode_heap_oop_not_null($dst$$Register, $src$$Register); |
|
124
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|
7554 %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
7555 ins_pipe(ialu_reg_long); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
7556 %} |
|
b130b98db9cf
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kvn
parents:
113
diff
changeset
|
7557 |
|
113
ba764ed4b6f2
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71
diff
changeset
|
7558 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{ |
|
182
44abbb0d4c18
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parents:
169
diff
changeset
|
7559 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && |
|
44abbb0d4c18
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kvn
parents:
169
diff
changeset
|
7560 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant); |
|
113
ba764ed4b6f2
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71
diff
changeset
|
7561 match(Set dst (DecodeN src)); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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71
diff
changeset
|
7562 effect(KILL cr); |
|
ba764ed4b6f2
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71
diff
changeset
|
7563 format %{ "decode_heap_oop $dst,$src" %} |
|
ba764ed4b6f2
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71
diff
changeset
|
7564 ins_encode %{ |
|
ba764ed4b6f2
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71
diff
changeset
|
7565 Register s = $src$$Register; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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71
diff
changeset
|
7566 Register d = $dst$$Register; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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71
diff
changeset
|
7567 if (s != d) { |
|
ba764ed4b6f2
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parents:
71
diff
changeset
|
7568 __ movq(d, s); |
|
ba764ed4b6f2
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coleenp
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71
diff
changeset
|
7569 } |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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71
diff
changeset
|
7570 __ decode_heap_oop(d); |
|
ba764ed4b6f2
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71
diff
changeset
|
7571 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
7572 ins_pipe(ialu_reg_long); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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71
diff
changeset
|
7573 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
7574 |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1567
diff
changeset
|
7575 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{ |
|
182
44abbb0d4c18
6709093: Compressed Oops: reduce size of compiled methods
kvn
parents:
169
diff
changeset
|
7576 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || |
|
44abbb0d4c18
6709093: Compressed Oops: reduce size of compiled methods
kvn
parents:
169
diff
changeset
|
7577 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant); |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
7578 match(Set dst (DecodeN src)); |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1567
diff
changeset
|
7579 effect(KILL cr); |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
7580 format %{ "decode_heap_oop_not_null $dst,$src" %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
7581 ins_encode %{ |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
7582 Register s = $src$$Register; |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
7583 Register d = $dst$$Register; |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7584 if (s != d) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7585 __ decode_heap_oop_not_null(d, s); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7586 } else { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7587 __ decode_heap_oop_not_null(d); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7588 } |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
7589 %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
7590 ins_pipe(ialu_reg_long); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
7591 %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
7592 |
|
113
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coleenp
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71
diff
changeset
|
7593 |
| 0 | 7594 //----------Conditional Move--------------------------------------------------- |
| 7595 // Jump | |
| 7596 // dummy instruction for generating temp registers | |
| 7597 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{ | |
| 7598 match(Jump (LShiftL switch_val shift)); | |
| 7599 ins_cost(350); | |
| 7600 predicate(false); | |
| 7601 effect(TEMP dest); | |
| 7602 | |
| 2008 | 7603 format %{ "leaq $dest, [$constantaddress]\n\t" |
| 0 | 7604 "jmp [$dest + $switch_val << $shift]\n\t" %} |
| 2008 | 7605 ins_encode %{ |
| 7606 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10 | |
| 7607 // to do that and the compiler is using that register as one it can allocate. | |
| 7608 // So we build it all by hand. | |
| 7609 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant); | |
| 7610 // ArrayAddress dispatch(table, index); | |
| 7611 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant); | |
| 7612 __ lea($dest$$Register, $constantaddress); | |
| 7613 __ jmp(dispatch); | |
| 7614 %} | |
| 0 | 7615 ins_pipe(pipe_jmp); |
| 7616 ins_pc_relative(1); | |
| 7617 %} | |
| 7618 | |
| 7619 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{ | |
| 7620 match(Jump (AddL (LShiftL switch_val shift) offset)); | |
| 7621 ins_cost(350); | |
| 7622 effect(TEMP dest); | |
| 7623 | |
| 2008 | 7624 format %{ "leaq $dest, [$constantaddress]\n\t" |
| 0 | 7625 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %} |
| 2008 | 7626 ins_encode %{ |
| 7627 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10 | |
| 7628 // to do that and the compiler is using that register as one it can allocate. | |
| 7629 // So we build it all by hand. | |
| 7630 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant); | |
| 7631 // ArrayAddress dispatch(table, index); | |
| 7632 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant); | |
| 7633 __ lea($dest$$Register, $constantaddress); | |
| 7634 __ jmp(dispatch); | |
| 7635 %} | |
| 0 | 7636 ins_pipe(pipe_jmp); |
| 7637 ins_pc_relative(1); | |
| 7638 %} | |
| 7639 | |
| 7640 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{ | |
| 7641 match(Jump switch_val); | |
| 7642 ins_cost(350); | |
| 7643 effect(TEMP dest); | |
| 7644 | |
| 2008 | 7645 format %{ "leaq $dest, [$constantaddress]\n\t" |
| 0 | 7646 "jmp [$dest + $switch_val]\n\t" %} |
| 2008 | 7647 ins_encode %{ |
| 7648 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10 | |
| 7649 // to do that and the compiler is using that register as one it can allocate. | |
| 7650 // So we build it all by hand. | |
| 7651 // Address index(noreg, switch_reg, Address::times_1); | |
| 7652 // ArrayAddress dispatch(table, index); | |
| 7653 Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1); | |
| 7654 __ lea($dest$$Register, $constantaddress); | |
| 7655 __ jmp(dispatch); | |
| 7656 %} | |
| 0 | 7657 ins_pipe(pipe_jmp); |
| 7658 ins_pc_relative(1); | |
| 7659 %} | |
| 7660 | |
| 7661 // Conditional move | |
| 7662 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop) | |
| 7663 %{ | |
| 7664 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 7665 | |
| 7666 ins_cost(200); // XXX | |
| 7667 format %{ "cmovl$cop $dst, $src\t# signed, int" %} | |
| 7668 opcode(0x0F, 0x40); | |
| 7669 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 7670 ins_pipe(pipe_cmov_reg); | |
| 7671 %} | |
| 7672 | |
|
415
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403
diff
changeset
|
7673 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{ |
| 0 | 7674 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); |
| 7675 | |
| 7676 ins_cost(200); // XXX | |
| 7677 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %} | |
| 7678 opcode(0x0F, 0x40); | |
| 7679 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 7680 ins_pipe(pipe_cmov_reg); | |
| 7681 %} | |
| 7682 | |
|
415
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7683 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7684 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7685 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7686 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7687 cmovI_regU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7688 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7689 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7690 |
| 0 | 7691 // Conditional move |
|
415
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parents:
403
diff
changeset
|
7692 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{ |
| 0 | 7693 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); |
| 7694 | |
| 7695 ins_cost(250); // XXX | |
| 7696 format %{ "cmovl$cop $dst, $src\t# signed, int" %} | |
| 7697 opcode(0x0F, 0x40); | |
| 7698 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
| 7699 ins_pipe(pipe_cmov_mem); | |
| 7700 %} | |
| 7701 | |
| 7702 // Conditional move | |
| 7703 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src) | |
| 7704 %{ | |
| 7705 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); | |
| 7706 | |
| 7707 ins_cost(250); // XXX | |
| 7708 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %} | |
| 7709 opcode(0x0F, 0x40); | |
| 7710 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
| 7711 ins_pipe(pipe_cmov_mem); | |
| 7712 %} | |
| 7713 | |
|
415
4d9884b01ba6
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|
7714 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{ |
|
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|
7715 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); |
|
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diff
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|
7716 ins_cost(250); |
|
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6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
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403
diff
changeset
|
7717 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
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403
diff
changeset
|
7718 cmovI_memU(cop, cr, dst, src); |
|
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never
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403
diff
changeset
|
7719 %} |
|
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never
parents:
403
diff
changeset
|
7720 %} |
|
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diff
changeset
|
7721 |
| 0 | 7722 // Conditional move |
|
164
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|
7723 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop) |
|
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|
7724 %{ |
|
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|
7725 match(Set dst (CMoveN (Binary cop cr) (Binary dst src))); |
|
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|
7726 |
|
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|
7727 ins_cost(200); // XXX |
|
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|
7728 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %} |
|
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|
7729 opcode(0x0F, 0x40); |
|
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|
7730 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); |
|
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|
7731 ins_pipe(pipe_cmov_reg); |
|
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changeset
|
7732 %} |
|
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kvn
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changeset
|
7733 |
|
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changeset
|
7734 // Conditional move |
|
415
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|
7735 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src) |
|
164
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|
7736 %{ |
|
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|
7737 match(Set dst (CMoveN (Binary cop cr) (Binary dst src))); |
|
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|
7738 |
|
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changeset
|
7739 ins_cost(200); // XXX |
|
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|
7740 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %} |
|
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|
7741 opcode(0x0F, 0x40); |
|
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changeset
|
7742 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); |
|
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changeset
|
7743 ins_pipe(pipe_cmov_reg); |
|
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changeset
|
7744 %} |
|
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163
diff
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|
7745 |
|
415
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changeset
|
7746 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{ |
|
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diff
changeset
|
7747 match(Set dst (CMoveN (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7748 ins_cost(200); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7749 expand %{ |
|
4d9884b01ba6
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403
diff
changeset
|
7750 cmovN_regU(cop, cr, dst, src); |
|
4d9884b01ba6
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403
diff
changeset
|
7751 %} |
|
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never
parents:
403
diff
changeset
|
7752 %} |
|
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never
parents:
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diff
changeset
|
7753 |
|
164
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|
7754 // Conditional move |
| 0 | 7755 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop) |
| 7756 %{ | |
| 7757 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 7758 | |
| 7759 ins_cost(200); // XXX | |
| 7760 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %} | |
| 7761 opcode(0x0F, 0x40); | |
| 7762 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 7763 ins_pipe(pipe_cmov_reg); // XXX | |
| 7764 %} | |
| 7765 | |
| 7766 // Conditional move | |
|
415
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diff
changeset
|
7767 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src) |
| 0 | 7768 %{ |
| 7769 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 7770 | |
| 7771 ins_cost(200); // XXX | |
| 7772 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %} | |
| 7773 opcode(0x0F, 0x40); | |
| 7774 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 7775 ins_pipe(pipe_cmov_reg); // XXX | |
| 7776 %} | |
| 7777 | |
|
415
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changeset
|
7778 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{ |
|
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diff
changeset
|
7779 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
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never
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403
diff
changeset
|
7780 ins_cost(200); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7781 expand %{ |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
7782 cmovP_regU(cop, cr, dst, src); |
|
4d9884b01ba6
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403
diff
changeset
|
7783 %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7784 %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7785 |
| 0 | 7786 // DISABLED: Requires the ADLC to emit a bottom_type call that |
| 7787 // correctly meets the two pointer arguments; one is an incoming | |
| 7788 // register but the other is a memory operand. ALSO appears to | |
| 7789 // be buggy with implicit null checks. | |
| 7790 // | |
| 7791 //// Conditional move | |
| 7792 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src) | |
| 7793 //%{ | |
| 7794 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 7795 // ins_cost(250); | |
| 7796 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 7797 // opcode(0x0F,0x40); | |
| 7798 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) ); | |
| 7799 // ins_pipe( pipe_cmov_mem ); | |
| 7800 //%} | |
| 7801 // | |
| 7802 //// Conditional move | |
| 7803 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src) | |
| 7804 //%{ | |
| 7805 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 7806 // ins_cost(250); | |
| 7807 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 7808 // opcode(0x0F,0x40); | |
| 7809 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) ); | |
| 7810 // ins_pipe( pipe_cmov_mem ); | |
| 7811 //%} | |
| 7812 | |
| 7813 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src) | |
| 7814 %{ | |
| 7815 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 7816 | |
| 7817 ins_cost(200); // XXX | |
| 7818 format %{ "cmovq$cop $dst, $src\t# signed, long" %} | |
| 7819 opcode(0x0F, 0x40); | |
| 7820 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 7821 ins_pipe(pipe_cmov_reg); // XXX | |
| 7822 %} | |
| 7823 | |
| 7824 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src) | |
| 7825 %{ | |
| 7826 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src)))); | |
| 7827 | |
| 7828 ins_cost(200); // XXX | |
| 7829 format %{ "cmovq$cop $dst, $src\t# signed, long" %} | |
| 7830 opcode(0x0F, 0x40); | |
| 7831 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
| 7832 ins_pipe(pipe_cmov_mem); // XXX | |
| 7833 %} | |
| 7834 | |
| 7835 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src) | |
| 7836 %{ | |
| 7837 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 7838 | |
| 7839 ins_cost(200); // XXX | |
| 7840 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %} | |
| 7841 opcode(0x0F, 0x40); | |
| 7842 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 7843 ins_pipe(pipe_cmov_reg); // XXX | |
| 7844 %} | |
| 7845 | |
|
415
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changeset
|
7846 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{ |
|
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403
diff
changeset
|
7847 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7848 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7849 expand %{ |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7850 cmovL_regU(cop, cr, dst, src); |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
7851 %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7852 %} |
|
4d9884b01ba6
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never
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403
diff
changeset
|
7853 |
| 0 | 7854 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src) |
| 7855 %{ | |
| 7856 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src)))); | |
| 7857 | |
| 7858 ins_cost(200); // XXX | |
| 7859 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %} | |
| 7860 opcode(0x0F, 0x40); | |
| 7861 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
| 7862 ins_pipe(pipe_cmov_mem); // XXX | |
| 7863 %} | |
| 7864 | |
|
415
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changeset
|
7865 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{ |
|
4d9884b01ba6
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changeset
|
7866 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src)))); |
|
4d9884b01ba6
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diff
changeset
|
7867 ins_cost(200); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7868 expand %{ |
|
4d9884b01ba6
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403
diff
changeset
|
7869 cmovL_memU(cop, cr, dst, src); |
|
4d9884b01ba6
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403
diff
changeset
|
7870 %} |
|
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parents:
403
diff
changeset
|
7871 %} |
|
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diff
changeset
|
7872 |
| 0 | 7873 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src) |
| 7874 %{ | |
| 7875 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 7876 | |
| 7877 ins_cost(200); // XXX | |
| 7878 format %{ "jn$cop skip\t# signed cmove float\n\t" | |
| 7879 "movss $dst, $src\n" | |
| 7880 "skip:" %} | |
| 7881 ins_encode(enc_cmovf_branch(cop, dst, src)); | |
| 7882 ins_pipe(pipe_slow); | |
| 7883 %} | |
| 7884 | |
| 7885 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src) | |
| 7886 // %{ | |
| 7887 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src)))); | |
| 7888 | |
| 7889 // ins_cost(200); // XXX | |
| 7890 // format %{ "jn$cop skip\t# signed cmove float\n\t" | |
| 7891 // "movss $dst, $src\n" | |
| 7892 // "skip:" %} | |
| 7893 // ins_encode(enc_cmovf_mem_branch(cop, dst, src)); | |
| 7894 // ins_pipe(pipe_slow); | |
| 7895 // %} | |
| 7896 | |
| 7897 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src) | |
| 7898 %{ | |
| 7899 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 7900 | |
| 7901 ins_cost(200); // XXX | |
| 7902 format %{ "jn$cop skip\t# unsigned cmove float\n\t" | |
| 7903 "movss $dst, $src\n" | |
| 7904 "skip:" %} | |
| 7905 ins_encode(enc_cmovf_branch(cop, dst, src)); | |
| 7906 ins_pipe(pipe_slow); | |
| 7907 %} | |
| 7908 | |
|
415
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diff
changeset
|
7909 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{ |
|
4d9884b01ba6
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diff
changeset
|
7910 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7911 ins_cost(200); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7912 expand %{ |
|
4d9884b01ba6
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403
diff
changeset
|
7913 cmovF_regU(cop, cr, dst, src); |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
7914 %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7915 %} |
|
4d9884b01ba6
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diff
changeset
|
7916 |
| 0 | 7917 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src) |
| 7918 %{ | |
| 7919 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 7920 | |
| 7921 ins_cost(200); // XXX | |
| 7922 format %{ "jn$cop skip\t# signed cmove double\n\t" | |
| 7923 "movsd $dst, $src\n" | |
| 7924 "skip:" %} | |
| 7925 ins_encode(enc_cmovd_branch(cop, dst, src)); | |
| 7926 ins_pipe(pipe_slow); | |
| 7927 %} | |
| 7928 | |
| 7929 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src) | |
| 7930 %{ | |
| 7931 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 7932 | |
| 7933 ins_cost(200); // XXX | |
| 7934 format %{ "jn$cop skip\t# unsigned cmove double\n\t" | |
| 7935 "movsd $dst, $src\n" | |
| 7936 "skip:" %} | |
| 7937 ins_encode(enc_cmovd_branch(cop, dst, src)); | |
| 7938 ins_pipe(pipe_slow); | |
| 7939 %} | |
| 7940 | |
|
415
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diff
changeset
|
7941 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{ |
|
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|
7942 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); |
|
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403
diff
changeset
|
7943 ins_cost(200); |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
7944 expand %{ |
|
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diff
changeset
|
7945 cmovD_regU(cop, cr, dst, src); |
|
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parents:
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diff
changeset
|
7946 %} |
|
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never
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diff
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|
7947 %} |
|
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|
7948 |
| 0 | 7949 //----------Arithmetic Instructions-------------------------------------------- |
| 7950 //----------Addition Instructions---------------------------------------------- | |
| 7951 | |
| 7952 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 7953 %{ | |
| 7954 match(Set dst (AddI dst src)); | |
| 7955 effect(KILL cr); | |
| 7956 | |
| 7957 format %{ "addl $dst, $src\t# int" %} | |
| 7958 opcode(0x03); | |
| 7959 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 7960 ins_pipe(ialu_reg_reg); | |
| 7961 %} | |
| 7962 | |
| 7963 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 7964 %{ | |
| 7965 match(Set dst (AddI dst src)); | |
| 7966 effect(KILL cr); | |
| 7967 | |
| 7968 format %{ "addl $dst, $src\t# int" %} | |
| 7969 opcode(0x81, 0x00); /* /0 id */ | |
| 7970 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 7971 ins_pipe( ialu_reg ); | |
| 7972 %} | |
| 7973 | |
| 7974 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 7975 %{ | |
| 7976 match(Set dst (AddI dst (LoadI src))); | |
| 7977 effect(KILL cr); | |
| 7978 | |
| 7979 ins_cost(125); // XXX | |
| 7980 format %{ "addl $dst, $src\t# int" %} | |
| 7981 opcode(0x03); | |
| 7982 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 7983 ins_pipe(ialu_reg_mem); | |
| 7984 %} | |
| 7985 | |
| 7986 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 7987 %{ | |
| 7988 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7989 effect(KILL cr); | |
| 7990 | |
| 7991 ins_cost(150); // XXX | |
| 7992 format %{ "addl $dst, $src\t# int" %} | |
| 7993 opcode(0x01); /* Opcode 01 /r */ | |
| 7994 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 7995 ins_pipe(ialu_mem_reg); | |
| 7996 %} | |
| 7997 | |
| 7998 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 7999 %{ | |
| 8000 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 8001 effect(KILL cr); | |
| 8002 | |
| 8003 ins_cost(125); // XXX | |
| 8004 format %{ "addl $dst, $src\t# int" %} | |
| 8005 opcode(0x81); /* Opcode 81 /0 id */ | |
| 8006 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src)); | |
| 8007 ins_pipe(ialu_mem_imm); | |
| 8008 %} | |
| 8009 | |
| 8010 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr) | |
| 8011 %{ | |
| 8012 predicate(UseIncDec); | |
| 8013 match(Set dst (AddI dst src)); | |
| 8014 effect(KILL cr); | |
| 8015 | |
| 8016 format %{ "incl $dst\t# int" %} | |
| 8017 opcode(0xFF, 0x00); // FF /0 | |
| 8018 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8019 ins_pipe(ialu_reg); | |
| 8020 %} | |
| 8021 | |
| 8022 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr) | |
| 8023 %{ | |
| 8024 predicate(UseIncDec); | |
| 8025 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 8026 effect(KILL cr); | |
| 8027 | |
| 8028 ins_cost(125); // XXX | |
| 8029 format %{ "incl $dst\t# int" %} | |
| 8030 opcode(0xFF); /* Opcode FF /0 */ | |
| 8031 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst)); | |
| 8032 ins_pipe(ialu_mem_imm); | |
| 8033 %} | |
| 8034 | |
| 8035 // XXX why does that use AddI | |
| 8036 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr) | |
| 8037 %{ | |
| 8038 predicate(UseIncDec); | |
| 8039 match(Set dst (AddI dst src)); | |
| 8040 effect(KILL cr); | |
| 8041 | |
| 8042 format %{ "decl $dst\t# int" %} | |
| 8043 opcode(0xFF, 0x01); // FF /1 | |
| 8044 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8045 ins_pipe(ialu_reg); | |
| 8046 %} | |
| 8047 | |
| 8048 // XXX why does that use AddI | |
| 8049 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr) | |
| 8050 %{ | |
| 8051 predicate(UseIncDec); | |
| 8052 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 8053 effect(KILL cr); | |
| 8054 | |
| 8055 ins_cost(125); // XXX | |
| 8056 format %{ "decl $dst\t# int" %} | |
| 8057 opcode(0xFF); /* Opcode FF /1 */ | |
| 8058 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst)); | |
| 8059 ins_pipe(ialu_mem_imm); | |
| 8060 %} | |
| 8061 | |
| 8062 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1) | |
| 8063 %{ | |
| 8064 match(Set dst (AddI src0 src1)); | |
| 8065 | |
| 8066 ins_cost(110); | |
| 8067 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %} | |
| 8068 opcode(0x8D); /* 0x8D /r */ | |
| 8069 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX | |
| 8070 ins_pipe(ialu_reg_reg); | |
| 8071 %} | |
| 8072 | |
| 8073 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 8074 %{ | |
| 8075 match(Set dst (AddL dst src)); | |
| 8076 effect(KILL cr); | |
| 8077 | |
| 8078 format %{ "addq $dst, $src\t# long" %} | |
| 8079 opcode(0x03); | |
| 8080 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 8081 ins_pipe(ialu_reg_reg); | |
| 8082 %} | |
| 8083 | |
| 8084 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
| 8085 %{ | |
| 8086 match(Set dst (AddL dst src)); | |
| 8087 effect(KILL cr); | |
| 8088 | |
| 8089 format %{ "addq $dst, $src\t# long" %} | |
| 8090 opcode(0x81, 0x00); /* /0 id */ | |
| 8091 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 8092 ins_pipe( ialu_reg ); | |
| 8093 %} | |
| 8094 | |
| 8095 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 8096 %{ | |
| 8097 match(Set dst (AddL dst (LoadL src))); | |
| 8098 effect(KILL cr); | |
| 8099 | |
| 8100 ins_cost(125); // XXX | |
| 8101 format %{ "addq $dst, $src\t# long" %} | |
| 8102 opcode(0x03); | |
| 8103 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 8104 ins_pipe(ialu_reg_mem); | |
| 8105 %} | |
| 8106 | |
| 8107 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 8108 %{ | |
| 8109 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
| 8110 effect(KILL cr); | |
| 8111 | |
| 8112 ins_cost(150); // XXX | |
| 8113 format %{ "addq $dst, $src\t# long" %} | |
| 8114 opcode(0x01); /* Opcode 01 /r */ | |
| 8115 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 8116 ins_pipe(ialu_mem_reg); | |
| 8117 %} | |
| 8118 | |
| 8119 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 8120 %{ | |
| 8121 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
| 8122 effect(KILL cr); | |
| 8123 | |
| 8124 ins_cost(125); // XXX | |
| 8125 format %{ "addq $dst, $src\t# long" %} | |
| 8126 opcode(0x81); /* Opcode 81 /0 id */ | |
| 8127 ins_encode(REX_mem_wide(dst), | |
| 8128 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src)); | |
| 8129 ins_pipe(ialu_mem_imm); | |
| 8130 %} | |
| 8131 | |
| 8132 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr) | |
| 8133 %{ | |
| 8134 predicate(UseIncDec); | |
| 8135 match(Set dst (AddL dst src)); | |
| 8136 effect(KILL cr); | |
| 8137 | |
| 8138 format %{ "incq $dst\t# long" %} | |
| 8139 opcode(0xFF, 0x00); // FF /0 | |
| 8140 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8141 ins_pipe(ialu_reg); | |
| 8142 %} | |
| 8143 | |
| 8144 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr) | |
| 8145 %{ | |
| 8146 predicate(UseIncDec); | |
| 8147 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
| 8148 effect(KILL cr); | |
| 8149 | |
| 8150 ins_cost(125); // XXX | |
| 8151 format %{ "incq $dst\t# long" %} | |
| 8152 opcode(0xFF); /* Opcode FF /0 */ | |
| 8153 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst)); | |
| 8154 ins_pipe(ialu_mem_imm); | |
| 8155 %} | |
| 8156 | |
| 8157 // XXX why does that use AddL | |
| 8158 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr) | |
| 8159 %{ | |
| 8160 predicate(UseIncDec); | |
| 8161 match(Set dst (AddL dst src)); | |
| 8162 effect(KILL cr); | |
| 8163 | |
| 8164 format %{ "decq $dst\t# long" %} | |
| 8165 opcode(0xFF, 0x01); // FF /1 | |
| 8166 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8167 ins_pipe(ialu_reg); | |
| 8168 %} | |
| 8169 | |
| 8170 // XXX why does that use AddL | |
| 8171 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr) | |
| 8172 %{ | |
| 8173 predicate(UseIncDec); | |
| 8174 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
| 8175 effect(KILL cr); | |
| 8176 | |
| 8177 ins_cost(125); // XXX | |
| 8178 format %{ "decq $dst\t# long" %} | |
| 8179 opcode(0xFF); /* Opcode FF /1 */ | |
| 8180 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst)); | |
| 8181 ins_pipe(ialu_mem_imm); | |
| 8182 %} | |
| 8183 | |
| 8184 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1) | |
| 8185 %{ | |
| 8186 match(Set dst (AddL src0 src1)); | |
| 8187 | |
| 8188 ins_cost(110); | |
| 8189 format %{ "leaq $dst, [$src0 + $src1]\t# long" %} | |
| 8190 opcode(0x8D); /* 0x8D /r */ | |
| 8191 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX | |
| 8192 ins_pipe(ialu_reg_reg); | |
| 8193 %} | |
| 8194 | |
| 8195 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr) | |
| 8196 %{ | |
| 8197 match(Set dst (AddP dst src)); | |
| 8198 effect(KILL cr); | |
| 8199 | |
| 8200 format %{ "addq $dst, $src\t# ptr" %} | |
| 8201 opcode(0x03); | |
| 8202 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 8203 ins_pipe(ialu_reg_reg); | |
| 8204 %} | |
| 8205 | |
| 8206 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr) | |
| 8207 %{ | |
| 8208 match(Set dst (AddP dst src)); | |
| 8209 effect(KILL cr); | |
| 8210 | |
| 8211 format %{ "addq $dst, $src\t# ptr" %} | |
| 8212 opcode(0x81, 0x00); /* /0 id */ | |
| 8213 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 8214 ins_pipe( ialu_reg ); | |
| 8215 %} | |
| 8216 | |
| 8217 // XXX addP mem ops ???? | |
| 8218 | |
| 8219 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1) | |
| 8220 %{ | |
| 8221 match(Set dst (AddP src0 src1)); | |
| 8222 | |
| 8223 ins_cost(110); | |
| 8224 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %} | |
| 8225 opcode(0x8D); /* 0x8D /r */ | |
| 8226 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX | |
| 8227 ins_pipe(ialu_reg_reg); | |
| 8228 %} | |
| 8229 | |
| 8230 instruct checkCastPP(rRegP dst) | |
| 8231 %{ | |
| 8232 match(Set dst (CheckCastPP dst)); | |
| 8233 | |
| 8234 size(0); | |
| 8235 format %{ "# checkcastPP of $dst" %} | |
| 8236 ins_encode(/* empty encoding */); | |
| 8237 ins_pipe(empty); | |
| 8238 %} | |
| 8239 | |
| 8240 instruct castPP(rRegP dst) | |
| 8241 %{ | |
| 8242 match(Set dst (CastPP dst)); | |
| 8243 | |
| 8244 size(0); | |
| 8245 format %{ "# castPP of $dst" %} | |
| 8246 ins_encode(/* empty encoding */); | |
| 8247 ins_pipe(empty); | |
| 8248 %} | |
| 8249 | |
| 8250 instruct castII(rRegI dst) | |
| 8251 %{ | |
| 8252 match(Set dst (CastII dst)); | |
| 8253 | |
| 8254 size(0); | |
| 8255 format %{ "# castII of $dst" %} | |
| 8256 ins_encode(/* empty encoding */); | |
| 8257 ins_cost(0); | |
| 8258 ins_pipe(empty); | |
| 8259 %} | |
| 8260 | |
| 8261 // LoadP-locked same as a regular LoadP when used with compare-swap | |
| 8262 instruct loadPLocked(rRegP dst, memory mem) | |
| 8263 %{ | |
| 8264 match(Set dst (LoadPLocked mem)); | |
| 8265 | |
| 8266 ins_cost(125); // XXX | |
| 8267 format %{ "movq $dst, $mem\t# ptr locked" %} | |
| 8268 opcode(0x8B); | |
| 8269 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 8270 ins_pipe(ialu_reg_mem); // XXX | |
| 8271 %} | |
| 8272 | |
| 8273 // LoadL-locked - same as a regular LoadL when used with compare-swap | |
| 8274 instruct loadLLocked(rRegL dst, memory mem) | |
| 8275 %{ | |
| 8276 match(Set dst (LoadLLocked mem)); | |
| 8277 | |
| 8278 ins_cost(125); // XXX | |
| 8279 format %{ "movq $dst, $mem\t# long locked" %} | |
| 8280 opcode(0x8B); | |
| 8281 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 8282 ins_pipe(ialu_reg_mem); // XXX | |
| 8283 %} | |
| 8284 | |
| 8285 // Conditional-store of the updated heap-top. | |
| 8286 // Used during allocation of the shared heap. | |
| 8287 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel. | |
| 8288 | |
| 8289 instruct storePConditional(memory heap_top_ptr, | |
| 8290 rax_RegP oldval, rRegP newval, | |
| 8291 rFlagsReg cr) | |
| 8292 %{ | |
| 8293 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval))); | |
|
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|
8294 |
| 0 | 8295 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) " |
| 8296 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %} | |
| 8297 opcode(0x0F, 0xB1); | |
| 8298 ins_encode(lock_prefix, | |
| 8299 REX_reg_mem_wide(newval, heap_top_ptr), | |
| 8300 OpcP, OpcS, | |
| 8301 reg_mem(newval, heap_top_ptr)); | |
| 8302 ins_pipe(pipe_cmpxchg); | |
| 8303 %} | |
| 8304 | |
|
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|
8305 // Conditional-store of an int value. |
|
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8306 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG. |
|
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8307 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr) |
|
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8308 %{ |
|
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8309 match(Set cr (StoreIConditional mem (Binary oldval newval))); |
|
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8310 effect(KILL oldval); |
|
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|
8311 |
|
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8312 format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %} |
| 0 | 8313 opcode(0x0F, 0xB1); |
| 8314 ins_encode(lock_prefix, | |
|
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8315 REX_reg_mem(newval, mem), |
| 0 | 8316 OpcP, OpcS, |
|
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8317 reg_mem(newval, mem)); |
| 0 | 8318 ins_pipe(pipe_cmpxchg); |
| 8319 %} | |
| 8320 | |
|
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8321 // Conditional-store of a long value. |
|
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8322 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG. |
|
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8323 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr) |
|
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8324 %{ |
|
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8325 match(Set cr (StoreLConditional mem (Binary oldval newval))); |
|
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8326 effect(KILL oldval); |
|
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8327 |
|
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8328 format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %} |
| 0 | 8329 opcode(0x0F, 0xB1); |
| 8330 ins_encode(lock_prefix, | |
|
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8331 REX_reg_mem_wide(newval, mem), |
| 0 | 8332 OpcP, OpcS, |
|
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8333 reg_mem(newval, mem)); |
| 0 | 8334 ins_pipe(pipe_cmpxchg); |
| 8335 %} | |
| 8336 | |
|
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8337 |
|
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8338 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them |
| 0 | 8339 instruct compareAndSwapP(rRegI res, |
| 8340 memory mem_ptr, | |
| 8341 rax_RegP oldval, rRegP newval, | |
| 8342 rFlagsReg cr) | |
| 8343 %{ | |
| 8344 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); | |
| 8345 effect(KILL cr, KILL oldval); | |
| 8346 | |
| 8347 format %{ "cmpxchgq $mem_ptr,$newval\t# " | |
| 8348 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" | |
| 8349 "sete $res\n\t" | |
| 8350 "movzbl $res, $res" %} | |
| 8351 opcode(0x0F, 0xB1); | |
| 8352 ins_encode(lock_prefix, | |
| 8353 REX_reg_mem_wide(newval, mem_ptr), | |
| 8354 OpcP, OpcS, | |
| 8355 reg_mem(newval, mem_ptr), | |
| 8356 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete | |
| 8357 REX_reg_breg(res, res), // movzbl | |
| 8358 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); | |
| 8359 ins_pipe( pipe_cmpxchg ); | |
| 8360 %} | |
| 8361 | |
| 8362 instruct compareAndSwapL(rRegI res, | |
| 8363 memory mem_ptr, | |
| 8364 rax_RegL oldval, rRegL newval, | |
| 8365 rFlagsReg cr) | |
| 8366 %{ | |
| 8367 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); | |
| 8368 effect(KILL cr, KILL oldval); | |
| 8369 | |
| 8370 format %{ "cmpxchgq $mem_ptr,$newval\t# " | |
| 8371 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" | |
| 8372 "sete $res\n\t" | |
| 8373 "movzbl $res, $res" %} | |
| 8374 opcode(0x0F, 0xB1); | |
| 8375 ins_encode(lock_prefix, | |
| 8376 REX_reg_mem_wide(newval, mem_ptr), | |
| 8377 OpcP, OpcS, | |
| 8378 reg_mem(newval, mem_ptr), | |
| 8379 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete | |
| 8380 REX_reg_breg(res, res), // movzbl | |
| 8381 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); | |
| 8382 ins_pipe( pipe_cmpxchg ); | |
| 8383 %} | |
| 8384 | |
| 8385 instruct compareAndSwapI(rRegI res, | |
| 8386 memory mem_ptr, | |
| 8387 rax_RegI oldval, rRegI newval, | |
| 8388 rFlagsReg cr) | |
| 8389 %{ | |
| 8390 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); | |
| 8391 effect(KILL cr, KILL oldval); | |
| 8392 | |
| 8393 format %{ "cmpxchgl $mem_ptr,$newval\t# " | |
| 8394 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" | |
| 8395 "sete $res\n\t" | |
| 8396 "movzbl $res, $res" %} | |
| 8397 opcode(0x0F, 0xB1); | |
| 8398 ins_encode(lock_prefix, | |
| 8399 REX_reg_mem(newval, mem_ptr), | |
| 8400 OpcP, OpcS, | |
| 8401 reg_mem(newval, mem_ptr), | |
| 8402 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete | |
| 8403 REX_reg_breg(res, res), // movzbl | |
| 8404 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); | |
| 8405 ins_pipe( pipe_cmpxchg ); | |
| 8406 %} | |
| 8407 | |
| 8408 | |
|
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8409 instruct compareAndSwapN(rRegI res, |
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8410 memory mem_ptr, |
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8411 rax_RegN oldval, rRegN newval, |
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8412 rFlagsReg cr) %{ |
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8413 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); |
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8414 effect(KILL cr, KILL oldval); |
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8415 |
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8416 format %{ "cmpxchgl $mem_ptr,$newval\t# " |
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8417 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" |
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8418 "sete $res\n\t" |
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8419 "movzbl $res, $res" %} |
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8420 opcode(0x0F, 0xB1); |
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8421 ins_encode(lock_prefix, |
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8422 REX_reg_mem(newval, mem_ptr), |
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8423 OpcP, OpcS, |
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8424 reg_mem(newval, mem_ptr), |
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8425 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete |
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8426 REX_reg_breg(res, res), // movzbl |
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8427 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); |
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8428 ins_pipe( pipe_cmpxchg ); |
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8429 %} |
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8430 |
| 0 | 8431 //----------Subtraction Instructions------------------------------------------- |
| 8432 | |
| 8433 // Integer Subtraction Instructions | |
| 8434 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 8435 %{ | |
| 8436 match(Set dst (SubI dst src)); | |
| 8437 effect(KILL cr); | |
| 8438 | |
| 8439 format %{ "subl $dst, $src\t# int" %} | |
| 8440 opcode(0x2B); | |
| 8441 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 8442 ins_pipe(ialu_reg_reg); | |
| 8443 %} | |
| 8444 | |
| 8445 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 8446 %{ | |
| 8447 match(Set dst (SubI dst src)); | |
| 8448 effect(KILL cr); | |
| 8449 | |
| 8450 format %{ "subl $dst, $src\t# int" %} | |
| 8451 opcode(0x81, 0x05); /* Opcode 81 /5 */ | |
| 8452 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 8453 ins_pipe(ialu_reg); | |
| 8454 %} | |
| 8455 | |
| 8456 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 8457 %{ | |
| 8458 match(Set dst (SubI dst (LoadI src))); | |
| 8459 effect(KILL cr); | |
| 8460 | |
| 8461 ins_cost(125); | |
| 8462 format %{ "subl $dst, $src\t# int" %} | |
| 8463 opcode(0x2B); | |
| 8464 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 8465 ins_pipe(ialu_reg_mem); | |
| 8466 %} | |
| 8467 | |
| 8468 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 8469 %{ | |
| 8470 match(Set dst (StoreI dst (SubI (LoadI dst) src))); | |
| 8471 effect(KILL cr); | |
| 8472 | |
| 8473 ins_cost(150); | |
| 8474 format %{ "subl $dst, $src\t# int" %} | |
| 8475 opcode(0x29); /* Opcode 29 /r */ | |
| 8476 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 8477 ins_pipe(ialu_mem_reg); | |
| 8478 %} | |
| 8479 | |
| 8480 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 8481 %{ | |
| 8482 match(Set dst (StoreI dst (SubI (LoadI dst) src))); | |
| 8483 effect(KILL cr); | |
| 8484 | |
| 8485 ins_cost(125); // XXX | |
| 8486 format %{ "subl $dst, $src\t# int" %} | |
| 8487 opcode(0x81); /* Opcode 81 /5 id */ | |
| 8488 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src)); | |
| 8489 ins_pipe(ialu_mem_imm); | |
| 8490 %} | |
| 8491 | |
| 8492 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 8493 %{ | |
| 8494 match(Set dst (SubL dst src)); | |
| 8495 effect(KILL cr); | |
| 8496 | |
| 8497 format %{ "subq $dst, $src\t# long" %} | |
| 8498 opcode(0x2B); | |
| 8499 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 8500 ins_pipe(ialu_reg_reg); | |
| 8501 %} | |
| 8502 | |
| 8503 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr) | |
| 8504 %{ | |
| 8505 match(Set dst (SubL dst src)); | |
| 8506 effect(KILL cr); | |
| 8507 | |
| 8508 format %{ "subq $dst, $src\t# long" %} | |
| 8509 opcode(0x81, 0x05); /* Opcode 81 /5 */ | |
| 8510 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 8511 ins_pipe(ialu_reg); | |
| 8512 %} | |
| 8513 | |
| 8514 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 8515 %{ | |
| 8516 match(Set dst (SubL dst (LoadL src))); | |
| 8517 effect(KILL cr); | |
| 8518 | |
| 8519 ins_cost(125); | |
| 8520 format %{ "subq $dst, $src\t# long" %} | |
| 8521 opcode(0x2B); | |
| 8522 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 8523 ins_pipe(ialu_reg_mem); | |
| 8524 %} | |
| 8525 | |
| 8526 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 8527 %{ | |
| 8528 match(Set dst (StoreL dst (SubL (LoadL dst) src))); | |
| 8529 effect(KILL cr); | |
| 8530 | |
| 8531 ins_cost(150); | |
| 8532 format %{ "subq $dst, $src\t# long" %} | |
| 8533 opcode(0x29); /* Opcode 29 /r */ | |
| 8534 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 8535 ins_pipe(ialu_mem_reg); | |
| 8536 %} | |
| 8537 | |
| 8538 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 8539 %{ | |
| 8540 match(Set dst (StoreL dst (SubL (LoadL dst) src))); | |
| 8541 effect(KILL cr); | |
| 8542 | |
| 8543 ins_cost(125); // XXX | |
| 8544 format %{ "subq $dst, $src\t# long" %} | |
| 8545 opcode(0x81); /* Opcode 81 /5 id */ | |
| 8546 ins_encode(REX_mem_wide(dst), | |
| 8547 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src)); | |
| 8548 ins_pipe(ialu_mem_imm); | |
| 8549 %} | |
| 8550 | |
| 8551 // Subtract from a pointer | |
| 8552 // XXX hmpf??? | |
| 8553 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr) | |
| 8554 %{ | |
| 8555 match(Set dst (AddP dst (SubI zero src))); | |
| 8556 effect(KILL cr); | |
| 8557 | |
| 8558 format %{ "subq $dst, $src\t# ptr - int" %} | |
| 8559 opcode(0x2B); | |
| 8560 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 8561 ins_pipe(ialu_reg_reg); | |
| 8562 %} | |
| 8563 | |
| 8564 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr) | |
| 8565 %{ | |
| 8566 match(Set dst (SubI zero dst)); | |
| 8567 effect(KILL cr); | |
| 8568 | |
| 8569 format %{ "negl $dst\t# int" %} | |
| 8570 opcode(0xF7, 0x03); // Opcode F7 /3 | |
| 8571 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8572 ins_pipe(ialu_reg); | |
| 8573 %} | |
| 8574 | |
| 8575 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr) | |
| 8576 %{ | |
| 8577 match(Set dst (StoreI dst (SubI zero (LoadI dst)))); | |
| 8578 effect(KILL cr); | |
| 8579 | |
| 8580 format %{ "negl $dst\t# int" %} | |
| 8581 opcode(0xF7, 0x03); // Opcode F7 /3 | |
| 8582 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8583 ins_pipe(ialu_reg); | |
| 8584 %} | |
| 8585 | |
| 8586 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr) | |
| 8587 %{ | |
| 8588 match(Set dst (SubL zero dst)); | |
| 8589 effect(KILL cr); | |
| 8590 | |
| 8591 format %{ "negq $dst\t# long" %} | |
| 8592 opcode(0xF7, 0x03); // Opcode F7 /3 | |
| 8593 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8594 ins_pipe(ialu_reg); | |
| 8595 %} | |
| 8596 | |
| 8597 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr) | |
| 8598 %{ | |
| 8599 match(Set dst (StoreL dst (SubL zero (LoadL dst)))); | |
| 8600 effect(KILL cr); | |
| 8601 | |
| 8602 format %{ "negq $dst\t# long" %} | |
| 8603 opcode(0xF7, 0x03); // Opcode F7 /3 | |
| 8604 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8605 ins_pipe(ialu_reg); | |
| 8606 %} | |
| 8607 | |
| 8608 | |
| 8609 //----------Multiplication/Division Instructions------------------------------- | |
| 8610 // Integer Multiplication Instructions | |
| 8611 // Multiply Register | |
| 8612 | |
| 8613 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 8614 %{ | |
| 8615 match(Set dst (MulI dst src)); | |
| 8616 effect(KILL cr); | |
| 8617 | |
| 8618 ins_cost(300); | |
| 8619 format %{ "imull $dst, $src\t# int" %} | |
| 8620 opcode(0x0F, 0xAF); | |
| 8621 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 8622 ins_pipe(ialu_reg_reg_alu0); | |
| 8623 %} | |
| 8624 | |
| 8625 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr) | |
| 8626 %{ | |
| 8627 match(Set dst (MulI src imm)); | |
| 8628 effect(KILL cr); | |
| 8629 | |
| 8630 ins_cost(300); | |
| 8631 format %{ "imull $dst, $src, $imm\t# int" %} | |
| 8632 opcode(0x69); /* 69 /r id */ | |
| 8633 ins_encode(REX_reg_reg(dst, src), | |
| 8634 OpcSE(imm), reg_reg(dst, src), Con8or32(imm)); | |
| 8635 ins_pipe(ialu_reg_reg_alu0); | |
| 8636 %} | |
| 8637 | |
| 8638 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 8639 %{ | |
| 8640 match(Set dst (MulI dst (LoadI src))); | |
| 8641 effect(KILL cr); | |
| 8642 | |
| 8643 ins_cost(350); | |
| 8644 format %{ "imull $dst, $src\t# int" %} | |
| 8645 opcode(0x0F, 0xAF); | |
| 8646 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src)); | |
| 8647 ins_pipe(ialu_reg_mem_alu0); | |
| 8648 %} | |
| 8649 | |
| 8650 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr) | |
| 8651 %{ | |
| 8652 match(Set dst (MulI (LoadI src) imm)); | |
| 8653 effect(KILL cr); | |
| 8654 | |
| 8655 ins_cost(300); | |
| 8656 format %{ "imull $dst, $src, $imm\t# int" %} | |
| 8657 opcode(0x69); /* 69 /r id */ | |
| 8658 ins_encode(REX_reg_mem(dst, src), | |
| 8659 OpcSE(imm), reg_mem(dst, src), Con8or32(imm)); | |
| 8660 ins_pipe(ialu_reg_mem_alu0); | |
| 8661 %} | |
| 8662 | |
| 8663 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 8664 %{ | |
| 8665 match(Set dst (MulL dst src)); | |
| 8666 effect(KILL cr); | |
| 8667 | |
| 8668 ins_cost(300); | |
| 8669 format %{ "imulq $dst, $src\t# long" %} | |
| 8670 opcode(0x0F, 0xAF); | |
| 8671 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 8672 ins_pipe(ialu_reg_reg_alu0); | |
| 8673 %} | |
| 8674 | |
| 8675 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr) | |
| 8676 %{ | |
| 8677 match(Set dst (MulL src imm)); | |
| 8678 effect(KILL cr); | |
| 8679 | |
| 8680 ins_cost(300); | |
| 8681 format %{ "imulq $dst, $src, $imm\t# long" %} | |
| 8682 opcode(0x69); /* 69 /r id */ | |
| 8683 ins_encode(REX_reg_reg_wide(dst, src), | |
| 8684 OpcSE(imm), reg_reg(dst, src), Con8or32(imm)); | |
| 8685 ins_pipe(ialu_reg_reg_alu0); | |
| 8686 %} | |
| 8687 | |
| 8688 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 8689 %{ | |
| 8690 match(Set dst (MulL dst (LoadL src))); | |
| 8691 effect(KILL cr); | |
| 8692 | |
| 8693 ins_cost(350); | |
| 8694 format %{ "imulq $dst, $src\t# long" %} | |
| 8695 opcode(0x0F, 0xAF); | |
| 8696 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src)); | |
| 8697 ins_pipe(ialu_reg_mem_alu0); | |
| 8698 %} | |
| 8699 | |
| 8700 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr) | |
| 8701 %{ | |
| 8702 match(Set dst (MulL (LoadL src) imm)); | |
| 8703 effect(KILL cr); | |
| 8704 | |
| 8705 ins_cost(300); | |
| 8706 format %{ "imulq $dst, $src, $imm\t# long" %} | |
| 8707 opcode(0x69); /* 69 /r id */ | |
| 8708 ins_encode(REX_reg_mem_wide(dst, src), | |
| 8709 OpcSE(imm), reg_mem(dst, src), Con8or32(imm)); | |
| 8710 ins_pipe(ialu_reg_mem_alu0); | |
| 8711 %} | |
| 8712 | |
| 145 | 8713 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr) |
| 8714 %{ | |
| 8715 match(Set dst (MulHiL src rax)); | |
| 8716 effect(USE_KILL rax, KILL cr); | |
| 8717 | |
| 8718 ins_cost(300); | |
| 8719 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %} | |
| 8720 opcode(0xF7, 0x5); /* Opcode F7 /5 */ | |
| 8721 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src)); | |
| 8722 ins_pipe(ialu_reg_reg_alu0); | |
| 8723 %} | |
| 8724 | |
| 0 | 8725 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div, |
| 8726 rFlagsReg cr) | |
| 8727 %{ | |
| 8728 match(Set rax (DivI rax div)); | |
| 8729 effect(KILL rdx, KILL cr); | |
| 8730 | |
| 8731 ins_cost(30*100+10*100); // XXX | |
| 8732 format %{ "cmpl rax, 0x80000000\t# idiv\n\t" | |
| 8733 "jne,s normal\n\t" | |
| 8734 "xorl rdx, rdx\n\t" | |
| 8735 "cmpl $div, -1\n\t" | |
| 8736 "je,s done\n" | |
| 8737 "normal: cdql\n\t" | |
| 8738 "idivl $div\n" | |
| 8739 "done:" %} | |
| 8740 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8741 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div)); | |
| 8742 ins_pipe(ialu_reg_reg_alu0); | |
| 8743 %} | |
| 8744 | |
| 8745 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div, | |
| 8746 rFlagsReg cr) | |
| 8747 %{ | |
| 8748 match(Set rax (DivL rax div)); | |
| 8749 effect(KILL rdx, KILL cr); | |
| 8750 | |
| 8751 ins_cost(30*100+10*100); // XXX | |
| 8752 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t" | |
| 8753 "cmpq rax, rdx\n\t" | |
| 8754 "jne,s normal\n\t" | |
| 8755 "xorl rdx, rdx\n\t" | |
| 8756 "cmpq $div, -1\n\t" | |
| 8757 "je,s done\n" | |
| 8758 "normal: cdqq\n\t" | |
| 8759 "idivq $div\n" | |
| 8760 "done:" %} | |
| 8761 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8762 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div)); | |
| 8763 ins_pipe(ialu_reg_reg_alu0); | |
| 8764 %} | |
| 8765 | |
| 8766 // Integer DIVMOD with Register, both quotient and mod results | |
| 8767 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div, | |
| 8768 rFlagsReg cr) | |
| 8769 %{ | |
| 8770 match(DivModI rax div); | |
| 8771 effect(KILL cr); | |
| 8772 | |
| 8773 ins_cost(30*100+10*100); // XXX | |
| 8774 format %{ "cmpl rax, 0x80000000\t# idiv\n\t" | |
| 8775 "jne,s normal\n\t" | |
| 8776 "xorl rdx, rdx\n\t" | |
| 8777 "cmpl $div, -1\n\t" | |
| 8778 "je,s done\n" | |
| 8779 "normal: cdql\n\t" | |
| 8780 "idivl $div\n" | |
| 8781 "done:" %} | |
| 8782 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8783 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div)); | |
| 8784 ins_pipe(pipe_slow); | |
| 8785 %} | |
| 8786 | |
| 8787 // Long DIVMOD with Register, both quotient and mod results | |
| 8788 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div, | |
| 8789 rFlagsReg cr) | |
| 8790 %{ | |
| 8791 match(DivModL rax div); | |
| 8792 effect(KILL cr); | |
| 8793 | |
| 8794 ins_cost(30*100+10*100); // XXX | |
| 8795 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t" | |
| 8796 "cmpq rax, rdx\n\t" | |
| 8797 "jne,s normal\n\t" | |
| 8798 "xorl rdx, rdx\n\t" | |
| 8799 "cmpq $div, -1\n\t" | |
| 8800 "je,s done\n" | |
| 8801 "normal: cdqq\n\t" | |
| 8802 "idivq $div\n" | |
| 8803 "done:" %} | |
| 8804 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8805 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div)); | |
| 8806 ins_pipe(pipe_slow); | |
| 8807 %} | |
| 8808 | |
| 8809 //----------- DivL-By-Constant-Expansions-------------------------------------- | |
| 8810 // DivI cases are handled by the compiler | |
| 8811 | |
| 605 | 8812 // Magic constant, reciprocal of 10 |
| 0 | 8813 instruct loadConL_0x6666666666666667(rRegL dst) |
| 8814 %{ | |
| 8815 effect(DEF dst); | |
| 8816 | |
| 8817 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %} | |
| 8818 ins_encode(load_immL(dst, 0x6666666666666667)); | |
| 8819 ins_pipe(ialu_reg); | |
| 8820 %} | |
| 8821 | |
| 8822 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr) | |
| 8823 %{ | |
| 8824 effect(DEF dst, USE src, USE_KILL rax, KILL cr); | |
| 8825 | |
| 8826 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %} | |
| 8827 opcode(0xF7, 0x5); /* Opcode F7 /5 */ | |
| 8828 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src)); | |
| 8829 ins_pipe(ialu_reg_reg_alu0); | |
| 8830 %} | |
| 8831 | |
| 8832 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr) | |
| 8833 %{ | |
| 8834 effect(USE_DEF dst, KILL cr); | |
| 8835 | |
| 8836 format %{ "sarq $dst, #63\t# Used in div-by-10" %} | |
| 8837 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8838 ins_encode(reg_opc_imm_wide(dst, 0x3F)); | |
| 8839 ins_pipe(ialu_reg); | |
| 8840 %} | |
| 8841 | |
| 8842 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr) | |
| 8843 %{ | |
| 8844 effect(USE_DEF dst, KILL cr); | |
| 8845 | |
| 8846 format %{ "sarq $dst, #2\t# Used in div-by-10" %} | |
| 8847 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8848 ins_encode(reg_opc_imm_wide(dst, 0x2)); | |
| 8849 ins_pipe(ialu_reg); | |
| 8850 %} | |
| 8851 | |
| 8852 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div) | |
| 8853 %{ | |
| 8854 match(Set dst (DivL src div)); | |
| 8855 | |
| 8856 ins_cost((5+8)*100); | |
| 8857 expand %{ | |
| 8858 rax_RegL rax; // Killed temp | |
| 8859 rFlagsReg cr; // Killed | |
| 8860 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667 | |
| 8861 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src | |
| 8862 sarL_rReg_63(src, cr); // sarq src, 63 | |
| 8863 sarL_rReg_2(dst, cr); // sarq rdx, 2 | |
| 8864 subL_rReg(dst, src, cr); // subl rdx, src | |
| 8865 %} | |
| 8866 %} | |
| 8867 | |
| 8868 //----------------------------------------------------------------------------- | |
| 8869 | |
| 8870 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div, | |
| 8871 rFlagsReg cr) | |
| 8872 %{ | |
| 8873 match(Set rdx (ModI rax div)); | |
| 8874 effect(KILL rax, KILL cr); | |
| 8875 | |
| 8876 ins_cost(300); // XXX | |
| 8877 format %{ "cmpl rax, 0x80000000\t# irem\n\t" | |
| 8878 "jne,s normal\n\t" | |
| 8879 "xorl rdx, rdx\n\t" | |
| 8880 "cmpl $div, -1\n\t" | |
| 8881 "je,s done\n" | |
| 8882 "normal: cdql\n\t" | |
| 8883 "idivl $div\n" | |
| 8884 "done:" %} | |
| 8885 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8886 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div)); | |
| 8887 ins_pipe(ialu_reg_reg_alu0); | |
| 8888 %} | |
| 8889 | |
| 8890 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div, | |
| 8891 rFlagsReg cr) | |
| 8892 %{ | |
| 8893 match(Set rdx (ModL rax div)); | |
| 8894 effect(KILL rax, KILL cr); | |
| 8895 | |
| 8896 ins_cost(300); // XXX | |
| 8897 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t" | |
| 8898 "cmpq rax, rdx\n\t" | |
| 8899 "jne,s normal\n\t" | |
| 8900 "xorl rdx, rdx\n\t" | |
| 8901 "cmpq $div, -1\n\t" | |
| 8902 "je,s done\n" | |
| 8903 "normal: cdqq\n\t" | |
| 8904 "idivq $div\n" | |
| 8905 "done:" %} | |
| 8906 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8907 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div)); | |
| 8908 ins_pipe(ialu_reg_reg_alu0); | |
| 8909 %} | |
| 8910 | |
| 8911 // Integer Shift Instructions | |
| 8912 // Shift Left by one | |
| 8913 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr) | |
| 8914 %{ | |
| 8915 match(Set dst (LShiftI dst shift)); | |
| 8916 effect(KILL cr); | |
| 8917 | |
| 8918 format %{ "sall $dst, $shift" %} | |
| 8919 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 8920 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8921 ins_pipe(ialu_reg); | |
| 8922 %} | |
| 8923 | |
| 8924 // Shift Left by one | |
| 8925 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 8926 %{ | |
| 8927 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift))); | |
| 8928 effect(KILL cr); | |
| 8929 | |
| 8930 format %{ "sall $dst, $shift\t" %} | |
| 8931 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 8932 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8933 ins_pipe(ialu_mem_imm); | |
| 8934 %} | |
| 8935 | |
| 8936 // Shift Left by 8-bit immediate | |
| 8937 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) | |
| 8938 %{ | |
| 8939 match(Set dst (LShiftI dst shift)); | |
| 8940 effect(KILL cr); | |
| 8941 | |
| 8942 format %{ "sall $dst, $shift" %} | |
| 8943 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 8944 ins_encode(reg_opc_imm(dst, shift)); | |
| 8945 ins_pipe(ialu_reg); | |
| 8946 %} | |
| 8947 | |
| 8948 // Shift Left by 8-bit immediate | |
| 8949 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 8950 %{ | |
| 8951 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift))); | |
| 8952 effect(KILL cr); | |
| 8953 | |
| 8954 format %{ "sall $dst, $shift" %} | |
| 8955 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 8956 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 8957 ins_pipe(ialu_mem_imm); | |
| 8958 %} | |
| 8959 | |
| 8960 // Shift Left by variable | |
| 8961 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 8962 %{ | |
| 8963 match(Set dst (LShiftI dst shift)); | |
| 8964 effect(KILL cr); | |
| 8965 | |
| 8966 format %{ "sall $dst, $shift" %} | |
| 8967 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 8968 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8969 ins_pipe(ialu_reg_reg); | |
| 8970 %} | |
| 8971 | |
| 8972 // Shift Left by variable | |
| 8973 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 8974 %{ | |
| 8975 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift))); | |
| 8976 effect(KILL cr); | |
| 8977 | |
| 8978 format %{ "sall $dst, $shift" %} | |
| 8979 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 8980 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8981 ins_pipe(ialu_mem_reg); | |
| 8982 %} | |
| 8983 | |
| 8984 // Arithmetic shift right by one | |
| 8985 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr) | |
| 8986 %{ | |
| 8987 match(Set dst (RShiftI dst shift)); | |
| 8988 effect(KILL cr); | |
| 8989 | |
| 8990 format %{ "sarl $dst, $shift" %} | |
| 8991 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 8992 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8993 ins_pipe(ialu_reg); | |
| 8994 %} | |
| 8995 | |
| 8996 // Arithmetic shift right by one | |
| 8997 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 8998 %{ | |
| 8999 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 9000 effect(KILL cr); | |
| 9001 | |
| 9002 format %{ "sarl $dst, $shift" %} | |
| 9003 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 9004 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 9005 ins_pipe(ialu_mem_imm); | |
| 9006 %} | |
| 9007 | |
| 9008 // Arithmetic Shift Right by 8-bit immediate | |
| 9009 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) | |
| 9010 %{ | |
| 9011 match(Set dst (RShiftI dst shift)); | |
| 9012 effect(KILL cr); | |
| 9013 | |
| 9014 format %{ "sarl $dst, $shift" %} | |
| 9015 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 9016 ins_encode(reg_opc_imm(dst, shift)); | |
| 9017 ins_pipe(ialu_mem_imm); | |
| 9018 %} | |
| 9019 | |
| 9020 // Arithmetic Shift Right by 8-bit immediate | |
| 9021 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 9022 %{ | |
| 9023 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 9024 effect(KILL cr); | |
| 9025 | |
| 9026 format %{ "sarl $dst, $shift" %} | |
| 9027 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 9028 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 9029 ins_pipe(ialu_mem_imm); | |
| 9030 %} | |
| 9031 | |
| 9032 // Arithmetic Shift Right by variable | |
| 9033 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 9034 %{ | |
| 9035 match(Set dst (RShiftI dst shift)); | |
| 9036 effect(KILL cr); | |
| 9037 | |
| 9038 format %{ "sarl $dst, $shift" %} | |
| 9039 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 9040 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 9041 ins_pipe(ialu_reg_reg); | |
| 9042 %} | |
| 9043 | |
| 9044 // Arithmetic Shift Right by variable | |
| 9045 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 9046 %{ | |
| 9047 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 9048 effect(KILL cr); | |
| 9049 | |
| 9050 format %{ "sarl $dst, $shift" %} | |
| 9051 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 9052 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 9053 ins_pipe(ialu_mem_reg); | |
| 9054 %} | |
| 9055 | |
| 9056 // Logical shift right by one | |
| 9057 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr) | |
| 9058 %{ | |
| 9059 match(Set dst (URShiftI dst shift)); | |
| 9060 effect(KILL cr); | |
| 9061 | |
| 9062 format %{ "shrl $dst, $shift" %} | |
| 9063 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 9064 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 9065 ins_pipe(ialu_reg); | |
| 9066 %} | |
| 9067 | |
| 9068 // Logical shift right by one | |
| 9069 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 9070 %{ | |
| 9071 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift))); | |
| 9072 effect(KILL cr); | |
| 9073 | |
| 9074 format %{ "shrl $dst, $shift" %} | |
| 9075 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 9076 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 9077 ins_pipe(ialu_mem_imm); | |
| 9078 %} | |
| 9079 | |
| 9080 // Logical Shift Right by 8-bit immediate | |
| 9081 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) | |
| 9082 %{ | |
| 9083 match(Set dst (URShiftI dst shift)); | |
| 9084 effect(KILL cr); | |
| 9085 | |
| 9086 format %{ "shrl $dst, $shift" %} | |
| 9087 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 9088 ins_encode(reg_opc_imm(dst, shift)); | |
| 9089 ins_pipe(ialu_reg); | |
| 9090 %} | |
| 9091 | |
| 9092 // Logical Shift Right by 8-bit immediate | |
| 9093 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 9094 %{ | |
| 9095 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift))); | |
| 9096 effect(KILL cr); | |
| 9097 | |
| 9098 format %{ "shrl $dst, $shift" %} | |
| 9099 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 9100 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 9101 ins_pipe(ialu_mem_imm); | |
| 9102 %} | |
| 9103 | |
| 9104 // Logical Shift Right by variable | |
| 9105 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 9106 %{ | |
| 9107 match(Set dst (URShiftI dst shift)); | |
| 9108 effect(KILL cr); | |
| 9109 | |
| 9110 format %{ "shrl $dst, $shift" %} | |
| 9111 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 9112 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 9113 ins_pipe(ialu_reg_reg); | |
| 9114 %} | |
| 9115 | |
| 9116 // Logical Shift Right by variable | |
| 9117 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 9118 %{ | |
| 9119 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift))); | |
| 9120 effect(KILL cr); | |
| 9121 | |
| 9122 format %{ "shrl $dst, $shift" %} | |
| 9123 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 9124 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 9125 ins_pipe(ialu_mem_reg); | |
| 9126 %} | |
| 9127 | |
| 9128 // Long Shift Instructions | |
| 9129 // Shift Left by one | |
| 9130 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr) | |
| 9131 %{ | |
| 9132 match(Set dst (LShiftL dst shift)); | |
| 9133 effect(KILL cr); | |
| 9134 | |
| 9135 format %{ "salq $dst, $shift" %} | |
| 9136 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 9137 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 9138 ins_pipe(ialu_reg); | |
| 9139 %} | |
| 9140 | |
| 9141 // Shift Left by one | |
| 9142 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 9143 %{ | |
| 9144 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift))); | |
| 9145 effect(KILL cr); | |
| 9146 | |
| 9147 format %{ "salq $dst, $shift" %} | |
| 9148 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 9149 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 9150 ins_pipe(ialu_mem_imm); | |
| 9151 %} | |
| 9152 | |
| 9153 // Shift Left by 8-bit immediate | |
| 9154 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr) | |
| 9155 %{ | |
| 9156 match(Set dst (LShiftL dst shift)); | |
| 9157 effect(KILL cr); | |
| 9158 | |
| 9159 format %{ "salq $dst, $shift" %} | |
| 9160 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 9161 ins_encode(reg_opc_imm_wide(dst, shift)); | |
| 9162 ins_pipe(ialu_reg); | |
| 9163 %} | |
| 9164 | |
| 9165 // Shift Left by 8-bit immediate | |
| 9166 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 9167 %{ | |
| 9168 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift))); | |
| 9169 effect(KILL cr); | |
| 9170 | |
| 9171 format %{ "salq $dst, $shift" %} | |
| 9172 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 9173 ins_encode(REX_mem_wide(dst), OpcP, | |
| 9174 RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 9175 ins_pipe(ialu_mem_imm); | |
| 9176 %} | |
| 9177 | |
| 9178 // Shift Left by variable | |
| 9179 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 9180 %{ | |
| 9181 match(Set dst (LShiftL dst shift)); | |
| 9182 effect(KILL cr); | |
| 9183 | |
| 9184 format %{ "salq $dst, $shift" %} | |
| 9185 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 9186 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 9187 ins_pipe(ialu_reg_reg); | |
| 9188 %} | |
| 9189 | |
| 9190 // Shift Left by variable | |
| 9191 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 9192 %{ | |
| 9193 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift))); | |
| 9194 effect(KILL cr); | |
| 9195 | |
| 9196 format %{ "salq $dst, $shift" %} | |
| 9197 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 9198 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 9199 ins_pipe(ialu_mem_reg); | |
| 9200 %} | |
| 9201 | |
| 9202 // Arithmetic shift right by one | |
| 9203 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr) | |
| 9204 %{ | |
| 9205 match(Set dst (RShiftL dst shift)); | |
| 9206 effect(KILL cr); | |
| 9207 | |
| 9208 format %{ "sarq $dst, $shift" %} | |
| 9209 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 9210 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 9211 ins_pipe(ialu_reg); | |
| 9212 %} | |
| 9213 | |
| 9214 // Arithmetic shift right by one | |
| 9215 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 9216 %{ | |
| 9217 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift))); | |
| 9218 effect(KILL cr); | |
| 9219 | |
| 9220 format %{ "sarq $dst, $shift" %} | |
| 9221 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 9222 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 9223 ins_pipe(ialu_mem_imm); | |
| 9224 %} | |
| 9225 | |
| 9226 // Arithmetic Shift Right by 8-bit immediate | |
| 9227 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr) | |
| 9228 %{ | |
| 9229 match(Set dst (RShiftL dst shift)); | |
| 9230 effect(KILL cr); | |
| 9231 | |
| 9232 format %{ "sarq $dst, $shift" %} | |
| 9233 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 9234 ins_encode(reg_opc_imm_wide(dst, shift)); | |
| 9235 ins_pipe(ialu_mem_imm); | |
| 9236 %} | |
| 9237 | |
| 9238 // Arithmetic Shift Right by 8-bit immediate | |
| 9239 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 9240 %{ | |
| 9241 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift))); | |
| 9242 effect(KILL cr); | |
| 9243 | |
| 9244 format %{ "sarq $dst, $shift" %} | |
| 9245 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 9246 ins_encode(REX_mem_wide(dst), OpcP, | |
| 9247 RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 9248 ins_pipe(ialu_mem_imm); | |
| 9249 %} | |
| 9250 | |
| 9251 // Arithmetic Shift Right by variable | |
| 9252 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 9253 %{ | |
| 9254 match(Set dst (RShiftL dst shift)); | |
| 9255 effect(KILL cr); | |
| 9256 | |
| 9257 format %{ "sarq $dst, $shift" %} | |
| 9258 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 9259 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 9260 ins_pipe(ialu_reg_reg); | |
| 9261 %} | |
| 9262 | |
| 9263 // Arithmetic Shift Right by variable | |
| 9264 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 9265 %{ | |
| 9266 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift))); | |
| 9267 effect(KILL cr); | |
| 9268 | |
| 9269 format %{ "sarq $dst, $shift" %} | |
| 9270 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 9271 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 9272 ins_pipe(ialu_mem_reg); | |
| 9273 %} | |
| 9274 | |
| 9275 // Logical shift right by one | |
| 9276 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr) | |
| 9277 %{ | |
| 9278 match(Set dst (URShiftL dst shift)); | |
| 9279 effect(KILL cr); | |
| 9280 | |
| 9281 format %{ "shrq $dst, $shift" %} | |
| 9282 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 9283 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst )); | |
| 9284 ins_pipe(ialu_reg); | |
| 9285 %} | |
| 9286 | |
| 9287 // Logical shift right by one | |
| 9288 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 9289 %{ | |
| 9290 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift))); | |
| 9291 effect(KILL cr); | |
| 9292 | |
| 9293 format %{ "shrq $dst, $shift" %} | |
| 9294 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 9295 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 9296 ins_pipe(ialu_mem_imm); | |
| 9297 %} | |
| 9298 | |
| 9299 // Logical Shift Right by 8-bit immediate | |
| 9300 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr) | |
| 9301 %{ | |
| 9302 match(Set dst (URShiftL dst shift)); | |
| 9303 effect(KILL cr); | |
| 9304 | |
| 9305 format %{ "shrq $dst, $shift" %} | |
| 9306 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 9307 ins_encode(reg_opc_imm_wide(dst, shift)); | |
| 9308 ins_pipe(ialu_reg); | |
| 9309 %} | |
| 9310 | |
|
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|
9311 |
| 0 | 9312 // Logical Shift Right by 8-bit immediate |
| 9313 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 9314 %{ | |
| 9315 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift))); | |
| 9316 effect(KILL cr); | |
| 9317 | |
| 9318 format %{ "shrq $dst, $shift" %} | |
| 9319 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 9320 ins_encode(REX_mem_wide(dst), OpcP, | |
| 9321 RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 9322 ins_pipe(ialu_mem_imm); | |
| 9323 %} | |
| 9324 | |
| 9325 // Logical Shift Right by variable | |
| 9326 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 9327 %{ | |
| 9328 match(Set dst (URShiftL dst shift)); | |
| 9329 effect(KILL cr); | |
| 9330 | |
| 9331 format %{ "shrq $dst, $shift" %} | |
| 9332 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 9333 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 9334 ins_pipe(ialu_reg_reg); | |
| 9335 %} | |
| 9336 | |
| 9337 // Logical Shift Right by variable | |
| 9338 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 9339 %{ | |
| 9340 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift))); | |
| 9341 effect(KILL cr); | |
| 9342 | |
| 9343 format %{ "shrq $dst, $shift" %} | |
| 9344 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 9345 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 9346 ins_pipe(ialu_mem_reg); | |
| 9347 %} | |
| 9348 | |
| 9349 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24. | |
| 9350 // This idiom is used by the compiler for the i2b bytecode. | |
| 9351 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour) | |
| 9352 %{ | |
| 9353 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour)); | |
| 9354 | |
| 9355 format %{ "movsbl $dst, $src\t# i2b" %} | |
| 9356 opcode(0x0F, 0xBE); | |
| 9357 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 9358 ins_pipe(ialu_reg_reg); | |
| 9359 %} | |
| 9360 | |
| 9361 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16. | |
| 9362 // This idiom is used by the compiler the i2s bytecode. | |
| 9363 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen) | |
| 9364 %{ | |
| 9365 match(Set dst (RShiftI (LShiftI src sixteen) sixteen)); | |
| 9366 | |
| 9367 format %{ "movswl $dst, $src\t# i2s" %} | |
| 9368 opcode(0x0F, 0xBF); | |
| 9369 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 9370 ins_pipe(ialu_reg_reg); | |
| 9371 %} | |
| 9372 | |
| 9373 // ROL/ROR instructions | |
| 9374 | |
| 9375 // ROL expand | |
| 9376 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{ | |
| 9377 effect(KILL cr, USE_DEF dst); | |
| 9378 | |
| 9379 format %{ "roll $dst" %} | |
| 9380 opcode(0xD1, 0x0); /* Opcode D1 /0 */ | |
| 9381 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 9382 ins_pipe(ialu_reg); | |
| 9383 %} | |
| 9384 | |
| 9385 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{ | |
| 9386 effect(USE_DEF dst, USE shift, KILL cr); | |
| 9387 | |
| 9388 format %{ "roll $dst, $shift" %} | |
| 9389 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */ | |
| 9390 ins_encode( reg_opc_imm(dst, shift) ); | |
| 9391 ins_pipe(ialu_reg); | |
| 9392 %} | |
| 9393 | |
| 9394 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 9395 %{ | |
| 9396 effect(USE_DEF dst, USE shift, KILL cr); | |
| 9397 | |
| 9398 format %{ "roll $dst, $shift" %} | |
| 9399 opcode(0xD3, 0x0); /* Opcode D3 /0 */ | |
| 9400 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 9401 ins_pipe(ialu_reg_reg); | |
| 9402 %} | |
| 9403 // end of ROL expand | |
| 9404 | |
| 9405 // Rotate Left by one | |
| 9406 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr) | |
| 9407 %{ | |
| 9408 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift))); | |
| 9409 | |
| 9410 expand %{ | |
| 9411 rolI_rReg_imm1(dst, cr); | |
| 9412 %} | |
| 9413 %} | |
| 9414 | |
| 9415 // Rotate Left by 8-bit immediate | |
| 9416 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr) | |
| 9417 %{ | |
| 9418 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); | |
| 9419 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift))); | |
| 9420 | |
| 9421 expand %{ | |
| 9422 rolI_rReg_imm8(dst, lshift, cr); | |
| 9423 %} | |
| 9424 %} | |
| 9425 | |
| 9426 // Rotate Left by variable | |
| 9427 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
| 9428 %{ | |
| 9429 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift)))); | |
| 9430 | |
| 9431 expand %{ | |
| 9432 rolI_rReg_CL(dst, shift, cr); | |
| 9433 %} | |
| 9434 %} | |
| 9435 | |
| 9436 // Rotate Left by variable | |
| 9437 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr) | |
| 9438 %{ | |
| 9439 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift)))); | |
| 9440 | |
| 9441 expand %{ | |
| 9442 rolI_rReg_CL(dst, shift, cr); | |
| 9443 %} | |
| 9444 %} | |
| 9445 | |
| 9446 // ROR expand | |
| 9447 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr) | |
| 9448 %{ | |
| 9449 effect(USE_DEF dst, KILL cr); | |
| 9450 | |
| 9451 format %{ "rorl $dst" %} | |
| 9452 opcode(0xD1, 0x1); /* D1 /1 */ | |
| 9453 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 9454 ins_pipe(ialu_reg); | |
| 9455 %} | |
| 9456 | |
| 9457 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) | |
| 9458 %{ | |
| 9459 effect(USE_DEF dst, USE shift, KILL cr); | |
| 9460 | |
| 9461 format %{ "rorl $dst, $shift" %} | |
| 9462 opcode(0xC1, 0x1); /* C1 /1 ib */ | |
| 9463 ins_encode(reg_opc_imm(dst, shift)); | |
| 9464 ins_pipe(ialu_reg); | |
| 9465 %} | |
| 9466 | |
| 9467 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 9468 %{ | |
| 9469 effect(USE_DEF dst, USE shift, KILL cr); | |
| 9470 | |
| 9471 format %{ "rorl $dst, $shift" %} | |
| 9472 opcode(0xD3, 0x1); /* D3 /1 */ | |
| 9473 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 9474 ins_pipe(ialu_reg_reg); | |
| 9475 %} | |
| 9476 // end of ROR expand | |
| 9477 | |
| 9478 // Rotate Right by one | |
| 9479 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr) | |
| 9480 %{ | |
| 9481 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift))); | |
| 9482 | |
| 9483 expand %{ | |
| 9484 rorI_rReg_imm1(dst, cr); | |
| 9485 %} | |
| 9486 %} | |
| 9487 | |
| 9488 // Rotate Right by 8-bit immediate | |
| 9489 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr) | |
| 9490 %{ | |
| 9491 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); | |
| 9492 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift))); | |
| 9493 | |
| 9494 expand %{ | |
| 9495 rorI_rReg_imm8(dst, rshift, cr); | |
| 9496 %} | |
| 9497 %} | |
| 9498 | |
| 9499 // Rotate Right by variable | |
| 9500 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
| 9501 %{ | |
| 9502 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift)))); | |
| 9503 | |
| 9504 expand %{ | |
| 9505 rorI_rReg_CL(dst, shift, cr); | |
| 9506 %} | |
| 9507 %} | |
| 9508 | |
| 9509 // Rotate Right by variable | |
| 9510 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr) | |
| 9511 %{ | |
| 9512 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift)))); | |
| 9513 | |
| 9514 expand %{ | |
| 9515 rorI_rReg_CL(dst, shift, cr); | |
| 9516 %} | |
| 9517 %} | |
| 9518 | |
| 9519 // for long rotate | |
| 9520 // ROL expand | |
| 9521 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{ | |
| 9522 effect(USE_DEF dst, KILL cr); | |
| 9523 | |
| 9524 format %{ "rolq $dst" %} | |
| 9525 opcode(0xD1, 0x0); /* Opcode D1 /0 */ | |
| 9526 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 9527 ins_pipe(ialu_reg); | |
| 9528 %} | |
| 9529 | |
| 9530 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{ | |
| 9531 effect(USE_DEF dst, USE shift, KILL cr); | |
| 9532 | |
| 9533 format %{ "rolq $dst, $shift" %} | |
| 9534 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */ | |
| 9535 ins_encode( reg_opc_imm_wide(dst, shift) ); | |
| 9536 ins_pipe(ialu_reg); | |
| 9537 %} | |
| 9538 | |
| 9539 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 9540 %{ | |
| 9541 effect(USE_DEF dst, USE shift, KILL cr); | |
| 9542 | |
| 9543 format %{ "rolq $dst, $shift" %} | |
| 9544 opcode(0xD3, 0x0); /* Opcode D3 /0 */ | |
| 9545 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 9546 ins_pipe(ialu_reg_reg); | |
| 9547 %} | |
| 9548 // end of ROL expand | |
| 9549 | |
| 9550 // Rotate Left by one | |
| 9551 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr) | |
| 9552 %{ | |
| 9553 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift))); | |
| 9554 | |
| 9555 expand %{ | |
| 9556 rolL_rReg_imm1(dst, cr); | |
| 9557 %} | |
| 9558 %} | |
| 9559 | |
| 9560 // Rotate Left by 8-bit immediate | |
| 9561 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr) | |
| 9562 %{ | |
| 9563 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f)); | |
| 9564 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift))); | |
| 9565 | |
| 9566 expand %{ | |
| 9567 rolL_rReg_imm8(dst, lshift, cr); | |
| 9568 %} | |
| 9569 %} | |
| 9570 | |
| 9571 // Rotate Left by variable | |
| 9572 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
| 9573 %{ | |
| 9574 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift)))); | |
| 9575 | |
| 9576 expand %{ | |
| 9577 rolL_rReg_CL(dst, shift, cr); | |
| 9578 %} | |
| 9579 %} | |
| 9580 | |
| 9581 // Rotate Left by variable | |
| 9582 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr) | |
| 9583 %{ | |
| 9584 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift)))); | |
| 9585 | |
| 9586 expand %{ | |
| 9587 rolL_rReg_CL(dst, shift, cr); | |
| 9588 %} | |
| 9589 %} | |
| 9590 | |
| 9591 // ROR expand | |
| 9592 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr) | |
| 9593 %{ | |
| 9594 effect(USE_DEF dst, KILL cr); | |
| 9595 | |
| 9596 format %{ "rorq $dst" %} | |
| 9597 opcode(0xD1, 0x1); /* D1 /1 */ | |
| 9598 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 9599 ins_pipe(ialu_reg); | |
| 9600 %} | |
| 9601 | |
| 9602 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) | |
| 9603 %{ | |
| 9604 effect(USE_DEF dst, USE shift, KILL cr); | |
| 9605 | |
| 9606 format %{ "rorq $dst, $shift" %} | |
| 9607 opcode(0xC1, 0x1); /* C1 /1 ib */ | |
| 9608 ins_encode(reg_opc_imm_wide(dst, shift)); | |
| 9609 ins_pipe(ialu_reg); | |
| 9610 %} | |
| 9611 | |
| 9612 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 9613 %{ | |
| 9614 effect(USE_DEF dst, USE shift, KILL cr); | |
| 9615 | |
| 9616 format %{ "rorq $dst, $shift" %} | |
| 9617 opcode(0xD3, 0x1); /* D3 /1 */ | |
| 9618 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 9619 ins_pipe(ialu_reg_reg); | |
| 9620 %} | |
| 9621 // end of ROR expand | |
| 9622 | |
| 9623 // Rotate Right by one | |
| 9624 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr) | |
| 9625 %{ | |
| 9626 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift))); | |
| 9627 | |
| 9628 expand %{ | |
| 9629 rorL_rReg_imm1(dst, cr); | |
| 9630 %} | |
| 9631 %} | |
| 9632 | |
| 9633 // Rotate Right by 8-bit immediate | |
| 9634 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr) | |
| 9635 %{ | |
| 9636 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f)); | |
| 9637 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift))); | |
| 9638 | |
| 9639 expand %{ | |
| 9640 rorL_rReg_imm8(dst, rshift, cr); | |
| 9641 %} | |
| 9642 %} | |
| 9643 | |
| 9644 // Rotate Right by variable | |
| 9645 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
| 9646 %{ | |
| 9647 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift)))); | |
| 9648 | |
| 9649 expand %{ | |
| 9650 rorL_rReg_CL(dst, shift, cr); | |
| 9651 %} | |
| 9652 %} | |
| 9653 | |
| 9654 // Rotate Right by variable | |
| 9655 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr) | |
| 9656 %{ | |
| 9657 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift)))); | |
| 9658 | |
| 9659 expand %{ | |
| 9660 rorL_rReg_CL(dst, shift, cr); | |
| 9661 %} | |
| 9662 %} | |
| 9663 | |
| 9664 // Logical Instructions | |
| 9665 | |
| 9666 // Integer Logical Instructions | |
| 9667 | |
| 9668 // And Instructions | |
| 9669 // And Register with Register | |
| 9670 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 9671 %{ | |
| 9672 match(Set dst (AndI dst src)); | |
| 9673 effect(KILL cr); | |
| 9674 | |
| 9675 format %{ "andl $dst, $src\t# int" %} | |
| 9676 opcode(0x23); | |
| 9677 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 9678 ins_pipe(ialu_reg_reg); | |
| 9679 %} | |
| 9680 | |
| 9681 // And Register with Immediate 255 | |
| 9682 instruct andI_rReg_imm255(rRegI dst, immI_255 src) | |
| 9683 %{ | |
| 9684 match(Set dst (AndI dst src)); | |
| 9685 | |
| 9686 format %{ "movzbl $dst, $dst\t# int & 0xFF" %} | |
| 9687 opcode(0x0F, 0xB6); | |
| 9688 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 9689 ins_pipe(ialu_reg); | |
| 9690 %} | |
| 9691 | |
| 9692 // And Register with Immediate 255 and promote to long | |
| 9693 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask) | |
| 9694 %{ | |
| 9695 match(Set dst (ConvI2L (AndI src mask))); | |
| 9696 | |
| 9697 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %} | |
| 9698 opcode(0x0F, 0xB6); | |
| 9699 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 9700 ins_pipe(ialu_reg); | |
| 9701 %} | |
| 9702 | |
| 9703 // And Register with Immediate 65535 | |
| 9704 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src) | |
| 9705 %{ | |
| 9706 match(Set dst (AndI dst src)); | |
| 9707 | |
| 9708 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %} | |
| 9709 opcode(0x0F, 0xB7); | |
| 9710 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 9711 ins_pipe(ialu_reg); | |
| 9712 %} | |
| 9713 | |
| 9714 // And Register with Immediate 65535 and promote to long | |
| 9715 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask) | |
| 9716 %{ | |
| 9717 match(Set dst (ConvI2L (AndI src mask))); | |
| 9718 | |
| 9719 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %} | |
| 9720 opcode(0x0F, 0xB7); | |
| 9721 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 9722 ins_pipe(ialu_reg); | |
| 9723 %} | |
| 9724 | |
| 9725 // And Register with Immediate | |
| 9726 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 9727 %{ | |
| 9728 match(Set dst (AndI dst src)); | |
| 9729 effect(KILL cr); | |
| 9730 | |
| 9731 format %{ "andl $dst, $src\t# int" %} | |
| 9732 opcode(0x81, 0x04); /* Opcode 81 /4 */ | |
| 9733 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 9734 ins_pipe(ialu_reg); | |
| 9735 %} | |
| 9736 | |
| 9737 // And Register with Memory | |
| 9738 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 9739 %{ | |
| 9740 match(Set dst (AndI dst (LoadI src))); | |
| 9741 effect(KILL cr); | |
| 9742 | |
| 9743 ins_cost(125); | |
| 9744 format %{ "andl $dst, $src\t# int" %} | |
| 9745 opcode(0x23); | |
| 9746 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 9747 ins_pipe(ialu_reg_mem); | |
| 9748 %} | |
| 9749 | |
| 9750 // And Memory with Register | |
| 9751 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 9752 %{ | |
| 9753 match(Set dst (StoreI dst (AndI (LoadI dst) src))); | |
| 9754 effect(KILL cr); | |
| 9755 | |
| 9756 ins_cost(150); | |
| 9757 format %{ "andl $dst, $src\t# int" %} | |
| 9758 opcode(0x21); /* Opcode 21 /r */ | |
| 9759 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 9760 ins_pipe(ialu_mem_reg); | |
| 9761 %} | |
| 9762 | |
| 9763 // And Memory with Immediate | |
| 9764 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 9765 %{ | |
| 9766 match(Set dst (StoreI dst (AndI (LoadI dst) src))); | |
| 9767 effect(KILL cr); | |
| 9768 | |
| 9769 ins_cost(125); | |
| 9770 format %{ "andl $dst, $src\t# int" %} | |
| 9771 opcode(0x81, 0x4); /* Opcode 81 /4 id */ | |
| 9772 ins_encode(REX_mem(dst), OpcSE(src), | |
| 9773 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 9774 ins_pipe(ialu_mem_imm); | |
| 9775 %} | |
| 9776 | |
| 9777 // Or Instructions | |
| 9778 // Or Register with Register | |
| 9779 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 9780 %{ | |
| 9781 match(Set dst (OrI dst src)); | |
| 9782 effect(KILL cr); | |
| 9783 | |
| 9784 format %{ "orl $dst, $src\t# int" %} | |
| 9785 opcode(0x0B); | |
| 9786 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 9787 ins_pipe(ialu_reg_reg); | |
| 9788 %} | |
| 9789 | |
| 9790 // Or Register with Immediate | |
| 9791 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 9792 %{ | |
| 9793 match(Set dst (OrI dst src)); | |
| 9794 effect(KILL cr); | |
| 9795 | |
| 9796 format %{ "orl $dst, $src\t# int" %} | |
| 9797 opcode(0x81, 0x01); /* Opcode 81 /1 id */ | |
| 9798 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 9799 ins_pipe(ialu_reg); | |
| 9800 %} | |
| 9801 | |
| 9802 // Or Register with Memory | |
| 9803 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 9804 %{ | |
| 9805 match(Set dst (OrI dst (LoadI src))); | |
| 9806 effect(KILL cr); | |
| 9807 | |
| 9808 ins_cost(125); | |
| 9809 format %{ "orl $dst, $src\t# int" %} | |
| 9810 opcode(0x0B); | |
| 9811 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 9812 ins_pipe(ialu_reg_mem); | |
| 9813 %} | |
| 9814 | |
| 9815 // Or Memory with Register | |
| 9816 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 9817 %{ | |
| 9818 match(Set dst (StoreI dst (OrI (LoadI dst) src))); | |
| 9819 effect(KILL cr); | |
| 9820 | |
| 9821 ins_cost(150); | |
| 9822 format %{ "orl $dst, $src\t# int" %} | |
| 9823 opcode(0x09); /* Opcode 09 /r */ | |
| 9824 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 9825 ins_pipe(ialu_mem_reg); | |
| 9826 %} | |
| 9827 | |
| 9828 // Or Memory with Immediate | |
| 9829 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 9830 %{ | |
| 9831 match(Set dst (StoreI dst (OrI (LoadI dst) src))); | |
| 9832 effect(KILL cr); | |
| 9833 | |
| 9834 ins_cost(125); | |
| 9835 format %{ "orl $dst, $src\t# int" %} | |
| 9836 opcode(0x81, 0x1); /* Opcode 81 /1 id */ | |
| 9837 ins_encode(REX_mem(dst), OpcSE(src), | |
| 9838 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 9839 ins_pipe(ialu_mem_imm); | |
| 9840 %} | |
| 9841 | |
| 9842 // Xor Instructions | |
| 9843 // Xor Register with Register | |
| 9844 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 9845 %{ | |
| 9846 match(Set dst (XorI dst src)); | |
| 9847 effect(KILL cr); | |
| 9848 | |
| 9849 format %{ "xorl $dst, $src\t# int" %} | |
| 9850 opcode(0x33); | |
| 9851 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 9852 ins_pipe(ialu_reg_reg); | |
| 9853 %} | |
| 9854 | |
| 403 | 9855 // Xor Register with Immediate -1 |
| 9856 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{ | |
| 9857 match(Set dst (XorI dst imm)); | |
| 9858 | |
| 9859 format %{ "not $dst" %} | |
| 9860 ins_encode %{ | |
| 9861 __ notl($dst$$Register); | |
| 9862 %} | |
| 9863 ins_pipe(ialu_reg); | |
| 9864 %} | |
| 9865 | |
| 0 | 9866 // Xor Register with Immediate |
| 9867 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 9868 %{ | |
| 9869 match(Set dst (XorI dst src)); | |
| 9870 effect(KILL cr); | |
| 9871 | |
| 9872 format %{ "xorl $dst, $src\t# int" %} | |
| 9873 opcode(0x81, 0x06); /* Opcode 81 /6 id */ | |
| 9874 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 9875 ins_pipe(ialu_reg); | |
| 9876 %} | |
| 9877 | |
| 9878 // Xor Register with Memory | |
| 9879 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 9880 %{ | |
| 9881 match(Set dst (XorI dst (LoadI src))); | |
| 9882 effect(KILL cr); | |
| 9883 | |
| 9884 ins_cost(125); | |
| 9885 format %{ "xorl $dst, $src\t# int" %} | |
| 9886 opcode(0x33); | |
| 9887 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 9888 ins_pipe(ialu_reg_mem); | |
| 9889 %} | |
| 9890 | |
| 9891 // Xor Memory with Register | |
| 9892 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 9893 %{ | |
| 9894 match(Set dst (StoreI dst (XorI (LoadI dst) src))); | |
| 9895 effect(KILL cr); | |
| 9896 | |
| 9897 ins_cost(150); | |
| 9898 format %{ "xorl $dst, $src\t# int" %} | |
| 9899 opcode(0x31); /* Opcode 31 /r */ | |
| 9900 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 9901 ins_pipe(ialu_mem_reg); | |
| 9902 %} | |
| 9903 | |
| 9904 // Xor Memory with Immediate | |
| 9905 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 9906 %{ | |
| 9907 match(Set dst (StoreI dst (XorI (LoadI dst) src))); | |
| 9908 effect(KILL cr); | |
| 9909 | |
| 9910 ins_cost(125); | |
| 9911 format %{ "xorl $dst, $src\t# int" %} | |
| 9912 opcode(0x81, 0x6); /* Opcode 81 /6 id */ | |
| 9913 ins_encode(REX_mem(dst), OpcSE(src), | |
| 9914 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 9915 ins_pipe(ialu_mem_imm); | |
| 9916 %} | |
| 9917 | |
| 9918 | |
| 9919 // Long Logical Instructions | |
| 9920 | |
| 9921 // And Instructions | |
| 9922 // And Register with Register | |
| 9923 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 9924 %{ | |
| 9925 match(Set dst (AndL dst src)); | |
| 9926 effect(KILL cr); | |
| 9927 | |
| 9928 format %{ "andq $dst, $src\t# long" %} | |
| 9929 opcode(0x23); | |
| 9930 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 9931 ins_pipe(ialu_reg_reg); | |
| 9932 %} | |
| 9933 | |
| 9934 // And Register with Immediate 255 | |
| 9935 instruct andL_rReg_imm255(rRegL dst, immL_255 src) | |
| 9936 %{ | |
| 9937 match(Set dst (AndL dst src)); | |
| 9938 | |
|
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9939 format %{ "movzbq $dst, $dst\t# long & 0xFF" %} |
| 0 | 9940 opcode(0x0F, 0xB6); |
| 9941 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 9942 ins_pipe(ialu_reg); | |
| 9943 %} | |
| 9944 | |
| 9945 // And Register with Immediate 65535 | |
|
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9946 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src) |
| 0 | 9947 %{ |
| 9948 match(Set dst (AndL dst src)); | |
| 9949 | |
| 9950 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %} | |
| 9951 opcode(0x0F, 0xB7); | |
| 9952 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 9953 ins_pipe(ialu_reg); | |
| 9954 %} | |
| 9955 | |
| 9956 // And Register with Immediate | |
| 9957 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
| 9958 %{ | |
| 9959 match(Set dst (AndL dst src)); | |
| 9960 effect(KILL cr); | |
| 9961 | |
| 9962 format %{ "andq $dst, $src\t# long" %} | |
| 9963 opcode(0x81, 0x04); /* Opcode 81 /4 */ | |
| 9964 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 9965 ins_pipe(ialu_reg); | |
| 9966 %} | |
| 9967 | |
| 9968 // And Register with Memory | |
| 9969 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 9970 %{ | |
| 9971 match(Set dst (AndL dst (LoadL src))); | |
| 9972 effect(KILL cr); | |
| 9973 | |
| 9974 ins_cost(125); | |
| 9975 format %{ "andq $dst, $src\t# long" %} | |
| 9976 opcode(0x23); | |
| 9977 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 9978 ins_pipe(ialu_reg_mem); | |
| 9979 %} | |
| 9980 | |
| 9981 // And Memory with Register | |
| 9982 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 9983 %{ | |
| 9984 match(Set dst (StoreL dst (AndL (LoadL dst) src))); | |
| 9985 effect(KILL cr); | |
| 9986 | |
| 9987 ins_cost(150); | |
| 9988 format %{ "andq $dst, $src\t# long" %} | |
| 9989 opcode(0x21); /* Opcode 21 /r */ | |
| 9990 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 9991 ins_pipe(ialu_mem_reg); | |
| 9992 %} | |
| 9993 | |
| 9994 // And Memory with Immediate | |
| 9995 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 9996 %{ | |
| 9997 match(Set dst (StoreL dst (AndL (LoadL dst) src))); | |
| 9998 effect(KILL cr); | |
| 9999 | |
| 10000 ins_cost(125); | |
| 10001 format %{ "andq $dst, $src\t# long" %} | |
| 10002 opcode(0x81, 0x4); /* Opcode 81 /4 id */ | |
| 10003 ins_encode(REX_mem_wide(dst), OpcSE(src), | |
| 10004 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 10005 ins_pipe(ialu_mem_imm); | |
| 10006 %} | |
| 10007 | |
| 10008 // Or Instructions | |
| 10009 // Or Register with Register | |
| 10010 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 10011 %{ | |
| 10012 match(Set dst (OrL dst src)); | |
| 10013 effect(KILL cr); | |
| 10014 | |
| 10015 format %{ "orq $dst, $src\t# long" %} | |
| 10016 opcode(0x0B); | |
| 10017 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 10018 ins_pipe(ialu_reg_reg); | |
| 10019 %} | |
| 10020 | |
|
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10021 // Use any_RegP to match R15 (TLS register) without spilling. |
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10022 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{ |
|
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10023 match(Set dst (OrL dst (CastP2X src))); |
|
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10024 effect(KILL cr); |
|
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10025 |
|
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10026 format %{ "orq $dst, $src\t# long" %} |
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10027 opcode(0x0B); |
|
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10028 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); |
|
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10029 ins_pipe(ialu_reg_reg); |
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10030 %} |
|
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10031 |
|
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10032 |
| 0 | 10033 // Or Register with Immediate |
| 10034 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
| 10035 %{ | |
| 10036 match(Set dst (OrL dst src)); | |
| 10037 effect(KILL cr); | |
| 10038 | |
| 10039 format %{ "orq $dst, $src\t# long" %} | |
| 10040 opcode(0x81, 0x01); /* Opcode 81 /1 id */ | |
| 10041 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 10042 ins_pipe(ialu_reg); | |
| 10043 %} | |
| 10044 | |
| 10045 // Or Register with Memory | |
| 10046 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 10047 %{ | |
| 10048 match(Set dst (OrL dst (LoadL src))); | |
| 10049 effect(KILL cr); | |
| 10050 | |
| 10051 ins_cost(125); | |
| 10052 format %{ "orq $dst, $src\t# long" %} | |
| 10053 opcode(0x0B); | |
| 10054 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 10055 ins_pipe(ialu_reg_mem); | |
| 10056 %} | |
| 10057 | |
| 10058 // Or Memory with Register | |
| 10059 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 10060 %{ | |
| 10061 match(Set dst (StoreL dst (OrL (LoadL dst) src))); | |
| 10062 effect(KILL cr); | |
| 10063 | |
| 10064 ins_cost(150); | |
| 10065 format %{ "orq $dst, $src\t# long" %} | |
| 10066 opcode(0x09); /* Opcode 09 /r */ | |
| 10067 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 10068 ins_pipe(ialu_mem_reg); | |
| 10069 %} | |
| 10070 | |
| 10071 // Or Memory with Immediate | |
| 10072 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 10073 %{ | |
| 10074 match(Set dst (StoreL dst (OrL (LoadL dst) src))); | |
| 10075 effect(KILL cr); | |
| 10076 | |
| 10077 ins_cost(125); | |
| 10078 format %{ "orq $dst, $src\t# long" %} | |
| 10079 opcode(0x81, 0x1); /* Opcode 81 /1 id */ | |
| 10080 ins_encode(REX_mem_wide(dst), OpcSE(src), | |
| 10081 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 10082 ins_pipe(ialu_mem_imm); | |
| 10083 %} | |
| 10084 | |
| 10085 // Xor Instructions | |
| 10086 // Xor Register with Register | |
| 10087 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 10088 %{ | |
| 10089 match(Set dst (XorL dst src)); | |
| 10090 effect(KILL cr); | |
| 10091 | |
| 10092 format %{ "xorq $dst, $src\t# long" %} | |
| 10093 opcode(0x33); | |
| 10094 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 10095 ins_pipe(ialu_reg_reg); | |
| 10096 %} | |
| 10097 | |
| 403 | 10098 // Xor Register with Immediate -1 |
| 10099 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{ | |
| 10100 match(Set dst (XorL dst imm)); | |
| 10101 | |
| 10102 format %{ "notq $dst" %} | |
| 10103 ins_encode %{ | |
| 10104 __ notq($dst$$Register); | |
| 10105 %} | |
| 10106 ins_pipe(ialu_reg); | |
| 10107 %} | |
| 10108 | |
| 0 | 10109 // Xor Register with Immediate |
| 10110 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
| 10111 %{ | |
| 10112 match(Set dst (XorL dst src)); | |
| 10113 effect(KILL cr); | |
| 10114 | |
| 10115 format %{ "xorq $dst, $src\t# long" %} | |
| 10116 opcode(0x81, 0x06); /* Opcode 81 /6 id */ | |
| 10117 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 10118 ins_pipe(ialu_reg); | |
| 10119 %} | |
| 10120 | |
| 10121 // Xor Register with Memory | |
| 10122 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 10123 %{ | |
| 10124 match(Set dst (XorL dst (LoadL src))); | |
| 10125 effect(KILL cr); | |
| 10126 | |
| 10127 ins_cost(125); | |
| 10128 format %{ "xorq $dst, $src\t# long" %} | |
| 10129 opcode(0x33); | |
| 10130 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 10131 ins_pipe(ialu_reg_mem); | |
| 10132 %} | |
| 10133 | |
| 10134 // Xor Memory with Register | |
| 10135 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 10136 %{ | |
| 10137 match(Set dst (StoreL dst (XorL (LoadL dst) src))); | |
| 10138 effect(KILL cr); | |
| 10139 | |
| 10140 ins_cost(150); | |
| 10141 format %{ "xorq $dst, $src\t# long" %} | |
| 10142 opcode(0x31); /* Opcode 31 /r */ | |
| 10143 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 10144 ins_pipe(ialu_mem_reg); | |
| 10145 %} | |
| 10146 | |
| 10147 // Xor Memory with Immediate | |
| 10148 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 10149 %{ | |
| 10150 match(Set dst (StoreL dst (XorL (LoadL dst) src))); | |
| 10151 effect(KILL cr); | |
| 10152 | |
| 10153 ins_cost(125); | |
| 10154 format %{ "xorq $dst, $src\t# long" %} | |
| 10155 opcode(0x81, 0x6); /* Opcode 81 /6 id */ | |
| 10156 ins_encode(REX_mem_wide(dst), OpcSE(src), | |
| 10157 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 10158 ins_pipe(ialu_mem_imm); | |
| 10159 %} | |
| 10160 | |
| 10161 // Convert Int to Boolean | |
| 10162 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr) | |
| 10163 %{ | |
| 10164 match(Set dst (Conv2B src)); | |
| 10165 effect(KILL cr); | |
| 10166 | |
| 10167 format %{ "testl $src, $src\t# ci2b\n\t" | |
| 10168 "setnz $dst\n\t" | |
| 10169 "movzbl $dst, $dst" %} | |
| 10170 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl | |
| 10171 setNZ_reg(dst), | |
| 10172 REX_reg_breg(dst, dst), // movzbl | |
| 10173 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst)); | |
| 10174 ins_pipe(pipe_slow); // XXX | |
| 10175 %} | |
| 10176 | |
| 10177 // Convert Pointer to Boolean | |
| 10178 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr) | |
| 10179 %{ | |
| 10180 match(Set dst (Conv2B src)); | |
| 10181 effect(KILL cr); | |
| 10182 | |
| 10183 format %{ "testq $src, $src\t# cp2b\n\t" | |
| 10184 "setnz $dst\n\t" | |
| 10185 "movzbl $dst, $dst" %} | |
| 10186 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq | |
| 10187 setNZ_reg(dst), | |
| 10188 REX_reg_breg(dst, dst), // movzbl | |
| 10189 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst)); | |
| 10190 ins_pipe(pipe_slow); // XXX | |
| 10191 %} | |
| 10192 | |
| 10193 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr) | |
| 10194 %{ | |
| 10195 match(Set dst (CmpLTMask p q)); | |
| 10196 effect(KILL cr); | |
| 10197 | |
| 10198 ins_cost(400); // XXX | |
| 10199 format %{ "cmpl $p, $q\t# cmpLTMask\n\t" | |
| 10200 "setlt $dst\n\t" | |
| 10201 "movzbl $dst, $dst\n\t" | |
| 10202 "negl $dst" %} | |
| 10203 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl | |
| 10204 setLT_reg(dst), | |
| 10205 REX_reg_breg(dst, dst), // movzbl | |
| 10206 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst), | |
| 10207 neg_reg(dst)); | |
| 10208 ins_pipe(pipe_slow); | |
| 10209 %} | |
| 10210 | |
| 10211 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr) | |
| 10212 %{ | |
| 10213 match(Set dst (CmpLTMask dst zero)); | |
| 10214 effect(KILL cr); | |
| 10215 | |
| 10216 ins_cost(100); // XXX | |
| 10217 format %{ "sarl $dst, #31\t# cmpLTMask0" %} | |
| 10218 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 10219 ins_encode(reg_opc_imm(dst, 0x1F)); | |
| 10220 ins_pipe(ialu_reg); | |
| 10221 %} | |
| 10222 | |
| 10223 | |
| 10224 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, | |
| 10225 rRegI tmp, | |
| 10226 rFlagsReg cr) | |
| 10227 %{ | |
| 10228 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); | |
| 10229 effect(TEMP tmp, KILL cr); | |
| 10230 | |
| 10231 ins_cost(400); // XXX | |
| 10232 format %{ "subl $p, $q\t# cadd_cmpLTMask1\n\t" | |
| 10233 "sbbl $tmp, $tmp\n\t" | |
| 10234 "andl $tmp, $y\n\t" | |
| 10235 "addl $p, $tmp" %} | |
| 10236 ins_encode(enc_cmpLTP(p, q, y, tmp)); | |
| 10237 ins_pipe(pipe_cmplt); | |
| 10238 %} | |
| 10239 | |
| 10240 /* If I enable this, I encourage spilling in the inner loop of compress. | |
| 10241 instruct cadd_cmpLTMask_mem( rRegI p, rRegI q, memory y, rRegI tmp, rFlagsReg cr ) | |
| 10242 %{ | |
| 10243 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q))); | |
| 10244 effect( TEMP tmp, KILL cr ); | |
| 10245 ins_cost(400); | |
| 10246 | |
| 10247 format %{ "SUB $p,$q\n\t" | |
| 10248 "SBB RCX,RCX\n\t" | |
| 10249 "AND RCX,$y\n\t" | |
| 10250 "ADD $p,RCX" %} | |
| 10251 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) ); | |
| 10252 %} | |
| 10253 */ | |
| 10254 | |
| 10255 //---------- FP Instructions------------------------------------------------ | |
| 10256 | |
| 10257 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2) | |
| 10258 %{ | |
| 10259 match(Set cr (CmpF src1 src2)); | |
| 10260 | |
| 10261 ins_cost(145); | |
| 10262 format %{ "ucomiss $src1, $src2\n\t" | |
| 10263 "jnp,s exit\n\t" | |
| 10264 "pushfq\t# saw NaN, set CF\n\t" | |
| 10265 "andq [rsp], #0xffffff2b\n\t" | |
| 10266 "popfq\n" | |
| 10267 "exit: nop\t# avoid branch to branch" %} | |
| 10268 opcode(0x0F, 0x2E); | |
| 10269 ins_encode(REX_reg_reg(src1, src2), OpcP, OpcS, reg_reg(src1, src2), | |
| 10270 cmpfp_fixup); | |
| 10271 ins_pipe(pipe_slow); | |
| 10272 %} | |
| 10273 | |
|
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10274 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{ |
|
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|
10275 match(Set cr (CmpF src1 src2)); |
|
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|
10276 |
|
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|
10277 ins_cost(145); |
|
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|
10278 format %{ "ucomiss $src1, $src2" %} |
|
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|
10279 ins_encode %{ |
|
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|
10280 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); |
|
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|
10281 %} |
|
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|
10282 ins_pipe(pipe_slow); |
|
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|
10283 %} |
|
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|
10284 |
| 0 | 10285 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2) |
| 10286 %{ | |
| 10287 match(Set cr (CmpF src1 (LoadF src2))); | |
| 10288 | |
| 10289 ins_cost(145); | |
| 10290 format %{ "ucomiss $src1, $src2\n\t" | |
| 10291 "jnp,s exit\n\t" | |
| 10292 "pushfq\t# saw NaN, set CF\n\t" | |
| 10293 "andq [rsp], #0xffffff2b\n\t" | |
| 10294 "popfq\n" | |
| 10295 "exit: nop\t# avoid branch to branch" %} | |
| 10296 opcode(0x0F, 0x2E); | |
| 10297 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, reg_mem(src1, src2), | |
| 10298 cmpfp_fixup); | |
| 10299 ins_pipe(pipe_slow); | |
| 10300 %} | |
| 10301 | |
|
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|
10302 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{ |
|
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|
10303 match(Set cr (CmpF src1 (LoadF src2))); |
|
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|
10304 |
|
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|
10305 ins_cost(100); |
|
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|
10306 format %{ "ucomiss $src1, $src2" %} |
|
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|
10307 opcode(0x0F, 0x2E); |
|
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|
10308 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, reg_mem(src1, src2)); |
|
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|
10309 ins_pipe(pipe_slow); |
|
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|
10310 %} |
|
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|
10311 |
| 2008 | 10312 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{ |
| 10313 match(Set cr (CmpF src con)); | |
| 0 | 10314 |
| 10315 ins_cost(145); | |
| 2008 | 10316 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t" |
| 0 | 10317 "jnp,s exit\n\t" |
| 10318 "pushfq\t# saw NaN, set CF\n\t" | |
| 10319 "andq [rsp], #0xffffff2b\n\t" | |
| 10320 "popfq\n" | |
| 10321 "exit: nop\t# avoid branch to branch" %} | |
| 2008 | 10322 ins_encode %{ |
| 10323 Label L_exit; | |
| 10324 __ ucomiss($src$$XMMRegister, $constantaddress($con)); | |
| 10325 __ jcc(Assembler::noParity, L_exit); | |
| 10326 __ pushf(); | |
| 10327 __ andq(rsp, 0xffffff2b); | |
| 10328 __ popf(); | |
| 10329 __ bind(L_exit); | |
| 10330 __ nop(); | |
| 10331 %} | |
| 10332 ins_pipe(pipe_slow); | |
| 10333 %} | |
| 10334 | |
| 10335 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{ | |
| 10336 match(Set cr (CmpF src con)); | |
|
415
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|
10337 ins_cost(100); |
| 2008 | 10338 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %} |
| 10339 ins_encode %{ | |
| 10340 __ ucomiss($src$$XMMRegister, $constantaddress($con)); | |
| 10341 %} | |
|
415
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|
10342 ins_pipe(pipe_slow); |
|
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|
10343 %} |
|
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|
10344 |
| 0 | 10345 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2) |
| 10346 %{ | |
| 10347 match(Set cr (CmpD src1 src2)); | |
| 10348 | |
| 10349 ins_cost(145); | |
| 10350 format %{ "ucomisd $src1, $src2\n\t" | |
| 10351 "jnp,s exit\n\t" | |
| 10352 "pushfq\t# saw NaN, set CF\n\t" | |
| 10353 "andq [rsp], #0xffffff2b\n\t" | |
| 10354 "popfq\n" | |
| 10355 "exit: nop\t# avoid branch to branch" %} | |
| 10356 opcode(0x66, 0x0F, 0x2E); | |
| 10357 ins_encode(OpcP, REX_reg_reg(src1, src2), OpcS, OpcT, reg_reg(src1, src2), | |
| 10358 cmpfp_fixup); | |
| 10359 ins_pipe(pipe_slow); | |
| 10360 %} | |
| 10361 | |
|
415
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|
10362 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{ |
|
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|
10363 match(Set cr (CmpD src1 src2)); |
|
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|
10364 |
|
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|
10365 ins_cost(100); |
|
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|
10366 format %{ "ucomisd $src1, $src2 test" %} |
|
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|
10367 ins_encode %{ |
|
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|
10368 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); |
|
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|
10369 %} |
|
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|
10370 ins_pipe(pipe_slow); |
|
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|
10371 %} |
|
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|
10372 |
| 0 | 10373 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2) |
| 10374 %{ | |
| 10375 match(Set cr (CmpD src1 (LoadD src2))); | |
| 10376 | |
| 10377 ins_cost(145); | |
| 10378 format %{ "ucomisd $src1, $src2\n\t" | |
| 10379 "jnp,s exit\n\t" | |
| 10380 "pushfq\t# saw NaN, set CF\n\t" | |
| 10381 "andq [rsp], #0xffffff2b\n\t" | |
| 10382 "popfq\n" | |
| 10383 "exit: nop\t# avoid branch to branch" %} | |
| 10384 opcode(0x66, 0x0F, 0x2E); | |
| 10385 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, reg_mem(src1, src2), | |
| 10386 cmpfp_fixup); | |
| 10387 ins_pipe(pipe_slow); | |
| 10388 %} | |
| 10389 | |
|
415
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|
10390 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{ |
|
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|
10391 match(Set cr (CmpD src1 (LoadD src2))); |
|
4d9884b01ba6
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|
10392 |
|
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|
10393 ins_cost(100); |
|
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|
10394 format %{ "ucomisd $src1, $src2" %} |
|
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|
10395 opcode(0x66, 0x0F, 0x2E); |
|
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|
10396 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, reg_mem(src1, src2)); |
|
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|
10397 ins_pipe(pipe_slow); |
|
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|
10398 %} |
|
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|
10399 |
| 2008 | 10400 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{ |
| 10401 match(Set cr (CmpD src con)); | |
| 0 | 10402 |
| 10403 ins_cost(145); | |
| 2008 | 10404 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 10405 "jnp,s exit\n\t" |
| 10406 "pushfq\t# saw NaN, set CF\n\t" | |
| 10407 "andq [rsp], #0xffffff2b\n\t" | |
| 10408 "popfq\n" | |
| 10409 "exit: nop\t# avoid branch to branch" %} | |
| 2008 | 10410 ins_encode %{ |
| 10411 Label L_exit; | |
| 10412 __ ucomisd($src$$XMMRegister, $constantaddress($con)); | |
| 10413 __ jcc(Assembler::noParity, L_exit); | |
| 10414 __ pushf(); | |
| 10415 __ andq(rsp, 0xffffff2b); | |
| 10416 __ popf(); | |
| 10417 __ bind(L_exit); | |
| 10418 __ nop(); | |
| 10419 %} | |
| 10420 ins_pipe(pipe_slow); | |
| 10421 %} | |
| 10422 | |
| 10423 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{ | |
| 10424 match(Set cr (CmpD src con)); | |
|
415
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|
10425 ins_cost(100); |
| 2008 | 10426 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %} |
| 10427 ins_encode %{ | |
| 10428 __ ucomisd($src$$XMMRegister, $constantaddress($con)); | |
| 10429 %} | |
|
415
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|
10430 ins_pipe(pipe_slow); |
|
4d9884b01ba6
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diff
changeset
|
10431 %} |
|
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changeset
|
10432 |
| 0 | 10433 // Compare into -1,0,1 |
| 10434 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr) | |
| 10435 %{ | |
| 10436 match(Set dst (CmpF3 src1 src2)); | |
| 10437 effect(KILL cr); | |
| 10438 | |
| 10439 ins_cost(275); | |
| 10440 format %{ "ucomiss $src1, $src2\n\t" | |
| 10441 "movl $dst, #-1\n\t" | |
| 10442 "jp,s done\n\t" | |
| 10443 "jb,s done\n\t" | |
| 10444 "setne $dst\n\t" | |
| 10445 "movzbl $dst, $dst\n" | |
| 10446 "done:" %} | |
| 10447 | |
| 10448 opcode(0x0F, 0x2E); | |
| 10449 ins_encode(REX_reg_reg(src1, src2), OpcP, OpcS, reg_reg(src1, src2), | |
| 10450 cmpfp3(dst)); | |
| 10451 ins_pipe(pipe_slow); | |
| 10452 %} | |
| 10453 | |
| 10454 // Compare into -1,0,1 | |
| 10455 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr) | |
| 10456 %{ | |
| 10457 match(Set dst (CmpF3 src1 (LoadF src2))); | |
| 10458 effect(KILL cr); | |
| 10459 | |
| 10460 ins_cost(275); | |
| 10461 format %{ "ucomiss $src1, $src2\n\t" | |
| 10462 "movl $dst, #-1\n\t" | |
| 10463 "jp,s done\n\t" | |
| 10464 "jb,s done\n\t" | |
| 10465 "setne $dst\n\t" | |
| 10466 "movzbl $dst, $dst\n" | |
| 10467 "done:" %} | |
| 10468 | |
| 10469 opcode(0x0F, 0x2E); | |
| 10470 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, reg_mem(src1, src2), | |
| 10471 cmpfp3(dst)); | |
| 10472 ins_pipe(pipe_slow); | |
| 10473 %} | |
| 10474 | |
| 10475 // Compare into -1,0,1 | |
| 2008 | 10476 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{ |
| 10477 match(Set dst (CmpF3 src con)); | |
| 0 | 10478 effect(KILL cr); |
| 10479 | |
| 10480 ins_cost(275); | |
| 2008 | 10481 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t" |
| 0 | 10482 "movl $dst, #-1\n\t" |
| 10483 "jp,s done\n\t" | |
| 10484 "jb,s done\n\t" | |
| 10485 "setne $dst\n\t" | |
| 10486 "movzbl $dst, $dst\n" | |
| 10487 "done:" %} | |
| 2008 | 10488 ins_encode %{ |
| 10489 Label L_done; | |
| 10490 Register Rdst = $dst$$Register; | |
| 10491 __ ucomiss($src$$XMMRegister, $constantaddress($con)); | |
| 10492 __ movl(Rdst, -1); | |
| 10493 __ jcc(Assembler::parity, L_done); | |
| 10494 __ jcc(Assembler::below, L_done); | |
| 10495 __ setb(Assembler::notEqual, Rdst); | |
| 10496 __ movzbl(Rdst, Rdst); | |
| 10497 __ bind(L_done); | |
| 10498 %} | |
| 0 | 10499 ins_pipe(pipe_slow); |
| 10500 %} | |
| 10501 | |
| 10502 // Compare into -1,0,1 | |
| 10503 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr) | |
| 10504 %{ | |
| 10505 match(Set dst (CmpD3 src1 src2)); | |
| 10506 effect(KILL cr); | |
| 10507 | |
| 10508 ins_cost(275); | |
| 10509 format %{ "ucomisd $src1, $src2\n\t" | |
| 10510 "movl $dst, #-1\n\t" | |
| 10511 "jp,s done\n\t" | |
| 10512 "jb,s done\n\t" | |
| 10513 "setne $dst\n\t" | |
| 10514 "movzbl $dst, $dst\n" | |
| 10515 "done:" %} | |
| 10516 | |
| 10517 opcode(0x66, 0x0F, 0x2E); | |
| 10518 ins_encode(OpcP, REX_reg_reg(src1, src2), OpcS, OpcT, reg_reg(src1, src2), | |
| 10519 cmpfp3(dst)); | |
| 10520 ins_pipe(pipe_slow); | |
| 10521 %} | |
| 10522 | |
| 10523 // Compare into -1,0,1 | |
| 10524 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr) | |
| 10525 %{ | |
| 10526 match(Set dst (CmpD3 src1 (LoadD src2))); | |
| 10527 effect(KILL cr); | |
| 10528 | |
| 10529 ins_cost(275); | |
| 10530 format %{ "ucomisd $src1, $src2\n\t" | |
| 10531 "movl $dst, #-1\n\t" | |
| 10532 "jp,s done\n\t" | |
| 10533 "jb,s done\n\t" | |
| 10534 "setne $dst\n\t" | |
| 10535 "movzbl $dst, $dst\n" | |
| 10536 "done:" %} | |
| 10537 | |
| 10538 opcode(0x66, 0x0F, 0x2E); | |
| 10539 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, reg_mem(src1, src2), | |
| 10540 cmpfp3(dst)); | |
| 10541 ins_pipe(pipe_slow); | |
| 10542 %} | |
| 10543 | |
| 10544 // Compare into -1,0,1 | |
| 2008 | 10545 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{ |
| 10546 match(Set dst (CmpD3 src con)); | |
| 0 | 10547 effect(KILL cr); |
| 10548 | |
| 10549 ins_cost(275); | |
| 2008 | 10550 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 10551 "movl $dst, #-1\n\t" |
| 10552 "jp,s done\n\t" | |
| 10553 "jb,s done\n\t" | |
| 10554 "setne $dst\n\t" | |
| 10555 "movzbl $dst, $dst\n" | |
| 10556 "done:" %} | |
| 2008 | 10557 ins_encode %{ |
| 10558 Register Rdst = $dst$$Register; | |
| 10559 Label L_done; | |
| 10560 __ ucomisd($src$$XMMRegister, $constantaddress($con)); | |
| 10561 __ movl(Rdst, -1); | |
| 10562 __ jcc(Assembler::parity, L_done); | |
| 10563 __ jcc(Assembler::below, L_done); | |
| 10564 __ setb(Assembler::notEqual, Rdst); | |
| 10565 __ movzbl(Rdst, Rdst); | |
| 10566 __ bind(L_done); | |
| 10567 %} | |
| 0 | 10568 ins_pipe(pipe_slow); |
| 10569 %} | |
| 10570 | |
| 10571 instruct addF_reg(regF dst, regF src) | |
| 10572 %{ | |
| 10573 match(Set dst (AddF dst src)); | |
| 10574 | |
| 10575 format %{ "addss $dst, $src" %} | |
| 10576 ins_cost(150); // XXX | |
| 10577 opcode(0xF3, 0x0F, 0x58); | |
| 10578 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10579 ins_pipe(pipe_slow); | |
| 10580 %} | |
| 10581 | |
| 10582 instruct addF_mem(regF dst, memory src) | |
| 10583 %{ | |
| 10584 match(Set dst (AddF dst (LoadF src))); | |
| 10585 | |
| 10586 format %{ "addss $dst, $src" %} | |
| 10587 ins_cost(150); // XXX | |
| 10588 opcode(0xF3, 0x0F, 0x58); | |
| 10589 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10590 ins_pipe(pipe_slow); | |
| 10591 %} | |
| 10592 | |
| 2008 | 10593 instruct addF_imm(regF dst, immF con) %{ |
| 10594 match(Set dst (AddF dst con)); | |
| 10595 format %{ "addss $dst, [$constantaddress]\t# load from constant table: float=$con" %} | |
| 0 | 10596 ins_cost(150); // XXX |
| 2008 | 10597 ins_encode %{ |
| 10598 __ addss($dst$$XMMRegister, $constantaddress($con)); | |
| 10599 %} | |
| 0 | 10600 ins_pipe(pipe_slow); |
| 10601 %} | |
| 10602 | |
| 10603 instruct addD_reg(regD dst, regD src) | |
| 10604 %{ | |
| 10605 match(Set dst (AddD dst src)); | |
| 10606 | |
| 10607 format %{ "addsd $dst, $src" %} | |
| 10608 ins_cost(150); // XXX | |
| 10609 opcode(0xF2, 0x0F, 0x58); | |
| 10610 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10611 ins_pipe(pipe_slow); | |
| 10612 %} | |
| 10613 | |
| 10614 instruct addD_mem(regD dst, memory src) | |
| 10615 %{ | |
| 10616 match(Set dst (AddD dst (LoadD src))); | |
| 10617 | |
| 10618 format %{ "addsd $dst, $src" %} | |
| 10619 ins_cost(150); // XXX | |
| 10620 opcode(0xF2, 0x0F, 0x58); | |
| 10621 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10622 ins_pipe(pipe_slow); | |
| 10623 %} | |
| 10624 | |
| 2008 | 10625 instruct addD_imm(regD dst, immD con) %{ |
| 10626 match(Set dst (AddD dst con)); | |
| 10627 format %{ "addsd $dst, [$constantaddress]\t# load from constant table: double=$con" %} | |
| 0 | 10628 ins_cost(150); // XXX |
| 2008 | 10629 ins_encode %{ |
| 10630 __ addsd($dst$$XMMRegister, $constantaddress($con)); | |
| 10631 %} | |
| 0 | 10632 ins_pipe(pipe_slow); |
| 10633 %} | |
| 10634 | |
| 10635 instruct subF_reg(regF dst, regF src) | |
| 10636 %{ | |
| 10637 match(Set dst (SubF dst src)); | |
| 10638 | |
| 10639 format %{ "subss $dst, $src" %} | |
| 10640 ins_cost(150); // XXX | |
| 10641 opcode(0xF3, 0x0F, 0x5C); | |
| 10642 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10643 ins_pipe(pipe_slow); | |
| 10644 %} | |
| 10645 | |
| 10646 instruct subF_mem(regF dst, memory src) | |
| 10647 %{ | |
| 10648 match(Set dst (SubF dst (LoadF src))); | |
| 10649 | |
| 10650 format %{ "subss $dst, $src" %} | |
| 10651 ins_cost(150); // XXX | |
| 10652 opcode(0xF3, 0x0F, 0x5C); | |
| 10653 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10654 ins_pipe(pipe_slow); | |
| 10655 %} | |
| 10656 | |
| 2008 | 10657 instruct subF_imm(regF dst, immF con) %{ |
| 10658 match(Set dst (SubF dst con)); | |
| 10659 format %{ "subss $dst, [$constantaddress]\t# load from constant table: float=$con" %} | |
| 0 | 10660 ins_cost(150); // XXX |
| 2008 | 10661 ins_encode %{ |
| 10662 __ subss($dst$$XMMRegister, $constantaddress($con)); | |
| 10663 %} | |
| 0 | 10664 ins_pipe(pipe_slow); |
| 10665 %} | |
| 10666 | |
| 10667 instruct subD_reg(regD dst, regD src) | |
| 10668 %{ | |
| 10669 match(Set dst (SubD dst src)); | |
| 10670 | |
| 10671 format %{ "subsd $dst, $src" %} | |
| 10672 ins_cost(150); // XXX | |
| 10673 opcode(0xF2, 0x0F, 0x5C); | |
| 10674 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10675 ins_pipe(pipe_slow); | |
| 10676 %} | |
| 10677 | |
| 10678 instruct subD_mem(regD dst, memory src) | |
| 10679 %{ | |
| 10680 match(Set dst (SubD dst (LoadD src))); | |
| 10681 | |
| 10682 format %{ "subsd $dst, $src" %} | |
| 10683 ins_cost(150); // XXX | |
| 10684 opcode(0xF2, 0x0F, 0x5C); | |
| 10685 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10686 ins_pipe(pipe_slow); | |
| 10687 %} | |
| 10688 | |
| 2008 | 10689 instruct subD_imm(regD dst, immD con) %{ |
| 10690 match(Set dst (SubD dst con)); | |
| 10691 format %{ "subsd $dst, [$constantaddress]\t# load from constant table: double=$con" %} | |
| 0 | 10692 ins_cost(150); // XXX |
| 2008 | 10693 ins_encode %{ |
| 10694 __ subsd($dst$$XMMRegister, $constantaddress($con)); | |
| 10695 %} | |
| 0 | 10696 ins_pipe(pipe_slow); |
| 10697 %} | |
| 10698 | |
| 10699 instruct mulF_reg(regF dst, regF src) | |
| 10700 %{ | |
| 10701 match(Set dst (MulF dst src)); | |
| 10702 | |
| 10703 format %{ "mulss $dst, $src" %} | |
| 10704 ins_cost(150); // XXX | |
| 10705 opcode(0xF3, 0x0F, 0x59); | |
| 10706 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10707 ins_pipe(pipe_slow); | |
| 10708 %} | |
| 10709 | |
| 10710 instruct mulF_mem(regF dst, memory src) | |
| 10711 %{ | |
| 10712 match(Set dst (MulF dst (LoadF src))); | |
| 10713 | |
| 10714 format %{ "mulss $dst, $src" %} | |
| 10715 ins_cost(150); // XXX | |
| 10716 opcode(0xF3, 0x0F, 0x59); | |
| 10717 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10718 ins_pipe(pipe_slow); | |
| 10719 %} | |
| 10720 | |
| 2008 | 10721 instruct mulF_imm(regF dst, immF con) %{ |
| 10722 match(Set dst (MulF dst con)); | |
| 10723 format %{ "mulss $dst, [$constantaddress]\t# load from constant table: float=$con" %} | |
| 0 | 10724 ins_cost(150); // XXX |
| 2008 | 10725 ins_encode %{ |
| 10726 __ mulss($dst$$XMMRegister, $constantaddress($con)); | |
| 10727 %} | |
| 0 | 10728 ins_pipe(pipe_slow); |
| 10729 %} | |
| 10730 | |
| 10731 instruct mulD_reg(regD dst, regD src) | |
| 10732 %{ | |
| 10733 match(Set dst (MulD dst src)); | |
| 10734 | |
| 10735 format %{ "mulsd $dst, $src" %} | |
| 10736 ins_cost(150); // XXX | |
| 10737 opcode(0xF2, 0x0F, 0x59); | |
| 10738 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10739 ins_pipe(pipe_slow); | |
| 10740 %} | |
| 10741 | |
| 10742 instruct mulD_mem(regD dst, memory src) | |
| 10743 %{ | |
| 10744 match(Set dst (MulD dst (LoadD src))); | |
| 10745 | |
| 10746 format %{ "mulsd $dst, $src" %} | |
| 10747 ins_cost(150); // XXX | |
| 10748 opcode(0xF2, 0x0F, 0x59); | |
| 10749 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10750 ins_pipe(pipe_slow); | |
| 10751 %} | |
| 10752 | |
| 2008 | 10753 instruct mulD_imm(regD dst, immD con) %{ |
| 10754 match(Set dst (MulD dst con)); | |
| 10755 format %{ "mulsd $dst, [$constantaddress]\t# load from constant table: double=$con" %} | |
| 0 | 10756 ins_cost(150); // XXX |
| 2008 | 10757 ins_encode %{ |
| 10758 __ mulsd($dst$$XMMRegister, $constantaddress($con)); | |
| 10759 %} | |
| 0 | 10760 ins_pipe(pipe_slow); |
| 10761 %} | |
| 10762 | |
| 10763 instruct divF_reg(regF dst, regF src) | |
| 10764 %{ | |
| 10765 match(Set dst (DivF dst src)); | |
| 10766 | |
| 10767 format %{ "divss $dst, $src" %} | |
| 10768 ins_cost(150); // XXX | |
| 10769 opcode(0xF3, 0x0F, 0x5E); | |
| 10770 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10771 ins_pipe(pipe_slow); | |
| 10772 %} | |
| 10773 | |
| 10774 instruct divF_mem(regF dst, memory src) | |
| 10775 %{ | |
| 10776 match(Set dst (DivF dst (LoadF src))); | |
| 10777 | |
| 10778 format %{ "divss $dst, $src" %} | |
| 10779 ins_cost(150); // XXX | |
| 10780 opcode(0xF3, 0x0F, 0x5E); | |
| 10781 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10782 ins_pipe(pipe_slow); | |
| 10783 %} | |
| 10784 | |
| 2008 | 10785 instruct divF_imm(regF dst, immF con) %{ |
| 10786 match(Set dst (DivF dst con)); | |
| 10787 format %{ "divss $dst, [$constantaddress]\t# load from constant table: float=$con" %} | |
| 0 | 10788 ins_cost(150); // XXX |
| 2008 | 10789 ins_encode %{ |
| 10790 __ divss($dst$$XMMRegister, $constantaddress($con)); | |
| 10791 %} | |
| 0 | 10792 ins_pipe(pipe_slow); |
| 10793 %} | |
| 10794 | |
| 10795 instruct divD_reg(regD dst, regD src) | |
| 10796 %{ | |
| 10797 match(Set dst (DivD dst src)); | |
| 10798 | |
| 10799 format %{ "divsd $dst, $src" %} | |
| 10800 ins_cost(150); // XXX | |
| 10801 opcode(0xF2, 0x0F, 0x5E); | |
| 10802 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10803 ins_pipe(pipe_slow); | |
| 10804 %} | |
| 10805 | |
| 10806 instruct divD_mem(regD dst, memory src) | |
| 10807 %{ | |
| 10808 match(Set dst (DivD dst (LoadD src))); | |
| 10809 | |
| 10810 format %{ "divsd $dst, $src" %} | |
| 10811 ins_cost(150); // XXX | |
| 10812 opcode(0xF2, 0x0F, 0x5E); | |
| 10813 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10814 ins_pipe(pipe_slow); | |
| 10815 %} | |
| 10816 | |
| 2008 | 10817 instruct divD_imm(regD dst, immD con) %{ |
| 10818 match(Set dst (DivD dst con)); | |
| 10819 format %{ "divsd $dst, [$constantaddress]\t# load from constant table: double=$con" %} | |
| 0 | 10820 ins_cost(150); // XXX |
| 2008 | 10821 ins_encode %{ |
| 10822 __ divsd($dst$$XMMRegister, $constantaddress($con)); | |
| 10823 %} | |
| 0 | 10824 ins_pipe(pipe_slow); |
| 10825 %} | |
| 10826 | |
| 10827 instruct sqrtF_reg(regF dst, regF src) | |
| 10828 %{ | |
| 10829 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); | |
| 10830 | |
| 10831 format %{ "sqrtss $dst, $src" %} | |
| 10832 ins_cost(150); // XXX | |
| 10833 opcode(0xF3, 0x0F, 0x51); | |
| 10834 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10835 ins_pipe(pipe_slow); | |
| 10836 %} | |
| 10837 | |
| 10838 instruct sqrtF_mem(regF dst, memory src) | |
| 10839 %{ | |
| 10840 match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF src))))); | |
| 10841 | |
| 10842 format %{ "sqrtss $dst, $src" %} | |
| 10843 ins_cost(150); // XXX | |
| 10844 opcode(0xF3, 0x0F, 0x51); | |
| 10845 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10846 ins_pipe(pipe_slow); | |
| 10847 %} | |
| 10848 | |
| 2008 | 10849 instruct sqrtF_imm(regF dst, immF con) %{ |
| 10850 match(Set dst (ConvD2F (SqrtD (ConvF2D con)))); | |
| 10851 format %{ "sqrtss $dst, [$constantaddress]\t# load from constant table: float=$con" %} | |
| 0 | 10852 ins_cost(150); // XXX |
| 2008 | 10853 ins_encode %{ |
| 10854 __ sqrtss($dst$$XMMRegister, $constantaddress($con)); | |
| 10855 %} | |
| 0 | 10856 ins_pipe(pipe_slow); |
| 10857 %} | |
| 10858 | |
| 10859 instruct sqrtD_reg(regD dst, regD src) | |
| 10860 %{ | |
| 10861 match(Set dst (SqrtD src)); | |
| 10862 | |
| 10863 format %{ "sqrtsd $dst, $src" %} | |
| 10864 ins_cost(150); // XXX | |
| 10865 opcode(0xF2, 0x0F, 0x51); | |
| 10866 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10867 ins_pipe(pipe_slow); | |
| 10868 %} | |
| 10869 | |
| 10870 instruct sqrtD_mem(regD dst, memory src) | |
| 10871 %{ | |
| 10872 match(Set dst (SqrtD (LoadD src))); | |
| 10873 | |
| 10874 format %{ "sqrtsd $dst, $src" %} | |
| 10875 ins_cost(150); // XXX | |
| 10876 opcode(0xF2, 0x0F, 0x51); | |
| 10877 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10878 ins_pipe(pipe_slow); | |
| 10879 %} | |
| 10880 | |
| 2008 | 10881 instruct sqrtD_imm(regD dst, immD con) %{ |
| 10882 match(Set dst (SqrtD con)); | |
| 10883 format %{ "sqrtsd $dst, [$constantaddress]\t# load from constant table: double=$con" %} | |
| 0 | 10884 ins_cost(150); // XXX |
| 2008 | 10885 ins_encode %{ |
| 10886 __ sqrtsd($dst$$XMMRegister, $constantaddress($con)); | |
| 10887 %} | |
| 0 | 10888 ins_pipe(pipe_slow); |
| 10889 %} | |
| 10890 | |
| 10891 instruct absF_reg(regF dst) | |
| 10892 %{ | |
| 10893 match(Set dst (AbsF dst)); | |
| 10894 | |
| 10895 format %{ "andps $dst, [0x7fffffff]\t# abs float by sign masking" %} | |
| 10896 ins_encode(absF_encoding(dst)); | |
| 10897 ins_pipe(pipe_slow); | |
| 10898 %} | |
| 10899 | |
| 10900 instruct absD_reg(regD dst) | |
| 10901 %{ | |
| 10902 match(Set dst (AbsD dst)); | |
| 10903 | |
| 10904 format %{ "andpd $dst, [0x7fffffffffffffff]\t" | |
| 10905 "# abs double by sign masking" %} | |
| 10906 ins_encode(absD_encoding(dst)); | |
| 10907 ins_pipe(pipe_slow); | |
| 10908 %} | |
| 10909 | |
| 10910 instruct negF_reg(regF dst) | |
| 10911 %{ | |
| 10912 match(Set dst (NegF dst)); | |
| 10913 | |
| 10914 format %{ "xorps $dst, [0x80000000]\t# neg float by sign flipping" %} | |
| 10915 ins_encode(negF_encoding(dst)); | |
| 10916 ins_pipe(pipe_slow); | |
| 10917 %} | |
| 10918 | |
| 10919 instruct negD_reg(regD dst) | |
| 10920 %{ | |
| 10921 match(Set dst (NegD dst)); | |
| 10922 | |
| 10923 format %{ "xorpd $dst, [0x8000000000000000]\t" | |
| 10924 "# neg double by sign flipping" %} | |
| 10925 ins_encode(negD_encoding(dst)); | |
| 10926 ins_pipe(pipe_slow); | |
| 10927 %} | |
| 10928 | |
| 10929 // -----------Trig and Trancendental Instructions------------------------------ | |
| 10930 instruct cosD_reg(regD dst) %{ | |
| 10931 match(Set dst (CosD dst)); | |
| 10932 | |
| 10933 format %{ "dcos $dst\n\t" %} | |
| 10934 opcode(0xD9, 0xFF); | |
| 10935 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) ); | |
| 10936 ins_pipe( pipe_slow ); | |
| 10937 %} | |
| 10938 | |
| 10939 instruct sinD_reg(regD dst) %{ | |
| 10940 match(Set dst (SinD dst)); | |
| 10941 | |
| 10942 format %{ "dsin $dst\n\t" %} | |
| 10943 opcode(0xD9, 0xFE); | |
| 10944 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) ); | |
| 10945 ins_pipe( pipe_slow ); | |
| 10946 %} | |
| 10947 | |
| 10948 instruct tanD_reg(regD dst) %{ | |
| 10949 match(Set dst (TanD dst)); | |
| 10950 | |
| 10951 format %{ "dtan $dst\n\t" %} | |
| 10952 ins_encode( Push_SrcXD(dst), | |
| 10953 Opcode(0xD9), Opcode(0xF2), //fptan | |
| 10954 Opcode(0xDD), Opcode(0xD8), //fstp st | |
| 10955 Push_ResultXD(dst) ); | |
| 10956 ins_pipe( pipe_slow ); | |
| 10957 %} | |
| 10958 | |
| 10959 instruct log10D_reg(regD dst) %{ | |
| 10960 // The source and result Double operands in XMM registers | |
| 10961 match(Set dst (Log10D dst)); | |
| 10962 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number | |
| 10963 // fyl2x ; compute log_10(2) * log_2(x) | |
| 10964 format %{ "fldlg2\t\t\t#Log10\n\t" | |
| 10965 "fyl2x\t\t\t# Q=Log10*Log_2(x)\n\t" | |
| 10966 %} | |
| 10967 ins_encode(Opcode(0xD9), Opcode(0xEC), // fldlg2 | |
| 10968 Push_SrcXD(dst), | |
| 10969 Opcode(0xD9), Opcode(0xF1), // fyl2x | |
| 10970 Push_ResultXD(dst)); | |
| 10971 | |
| 10972 ins_pipe( pipe_slow ); | |
| 10973 %} | |
| 10974 | |
| 10975 instruct logD_reg(regD dst) %{ | |
| 10976 // The source and result Double operands in XMM registers | |
| 10977 match(Set dst (LogD dst)); | |
| 10978 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number | |
| 10979 // fyl2x ; compute log_e(2) * log_2(x) | |
| 10980 format %{ "fldln2\t\t\t#Log_e\n\t" | |
| 10981 "fyl2x\t\t\t# Q=Log_e*Log_2(x)\n\t" | |
| 10982 %} | |
| 10983 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 | |
| 10984 Push_SrcXD(dst), | |
| 10985 Opcode(0xD9), Opcode(0xF1), // fyl2x | |
| 10986 Push_ResultXD(dst)); | |
| 10987 ins_pipe( pipe_slow ); | |
| 10988 %} | |
| 10989 | |
| 10990 | |
| 10991 | |
| 10992 //----------Arithmetic Conversion Instructions--------------------------------- | |
| 10993 | |
| 10994 instruct roundFloat_nop(regF dst) | |
| 10995 %{ | |
| 10996 match(Set dst (RoundFloat dst)); | |
| 10997 | |
| 10998 ins_cost(0); | |
| 10999 ins_encode(); | |
| 11000 ins_pipe(empty); | |
| 11001 %} | |
| 11002 | |
| 11003 instruct roundDouble_nop(regD dst) | |
| 11004 %{ | |
| 11005 match(Set dst (RoundDouble dst)); | |
| 11006 | |
| 11007 ins_cost(0); | |
| 11008 ins_encode(); | |
| 11009 ins_pipe(empty); | |
| 11010 %} | |
| 11011 | |
| 11012 instruct convF2D_reg_reg(regD dst, regF src) | |
| 11013 %{ | |
| 11014 match(Set dst (ConvF2D src)); | |
| 11015 | |
| 11016 format %{ "cvtss2sd $dst, $src" %} | |
| 11017 opcode(0xF3, 0x0F, 0x5A); | |
| 11018 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 11019 ins_pipe(pipe_slow); // XXX | |
| 11020 %} | |
| 11021 | |
| 11022 instruct convF2D_reg_mem(regD dst, memory src) | |
| 11023 %{ | |
| 11024 match(Set dst (ConvF2D (LoadF src))); | |
| 11025 | |
| 11026 format %{ "cvtss2sd $dst, $src" %} | |
| 11027 opcode(0xF3, 0x0F, 0x5A); | |
| 11028 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 11029 ins_pipe(pipe_slow); // XXX | |
| 11030 %} | |
| 11031 | |
| 11032 instruct convD2F_reg_reg(regF dst, regD src) | |
| 11033 %{ | |
| 11034 match(Set dst (ConvD2F src)); | |
| 11035 | |
| 11036 format %{ "cvtsd2ss $dst, $src" %} | |
| 11037 opcode(0xF2, 0x0F, 0x5A); | |
| 11038 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 11039 ins_pipe(pipe_slow); // XXX | |
| 11040 %} | |
| 11041 | |
| 11042 instruct convD2F_reg_mem(regF dst, memory src) | |
| 11043 %{ | |
| 11044 match(Set dst (ConvD2F (LoadD src))); | |
| 11045 | |
| 11046 format %{ "cvtsd2ss $dst, $src" %} | |
| 11047 opcode(0xF2, 0x0F, 0x5A); | |
| 11048 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 11049 ins_pipe(pipe_slow); // XXX | |
| 11050 %} | |
| 11051 | |
| 11052 // XXX do mem variants | |
| 11053 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr) | |
| 11054 %{ | |
| 11055 match(Set dst (ConvF2I src)); | |
| 11056 effect(KILL cr); | |
| 11057 | |
| 11058 format %{ "cvttss2sil $dst, $src\t# f2i\n\t" | |
| 11059 "cmpl $dst, #0x80000000\n\t" | |
| 11060 "jne,s done\n\t" | |
| 11061 "subq rsp, #8\n\t" | |
| 11062 "movss [rsp], $src\n\t" | |
| 11063 "call f2i_fixup\n\t" | |
| 11064 "popq $dst\n" | |
| 11065 "done: "%} | |
| 11066 opcode(0xF3, 0x0F, 0x2C); | |
| 11067 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src), | |
| 11068 f2i_fixup(dst, src)); | |
| 11069 ins_pipe(pipe_slow); | |
| 11070 %} | |
| 11071 | |
| 11072 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr) | |
| 11073 %{ | |
| 11074 match(Set dst (ConvF2L src)); | |
| 11075 effect(KILL cr); | |
| 11076 | |
| 11077 format %{ "cvttss2siq $dst, $src\t# f2l\n\t" | |
| 11078 "cmpq $dst, [0x8000000000000000]\n\t" | |
| 11079 "jne,s done\n\t" | |
| 11080 "subq rsp, #8\n\t" | |
| 11081 "movss [rsp], $src\n\t" | |
| 11082 "call f2l_fixup\n\t" | |
| 11083 "popq $dst\n" | |
| 11084 "done: "%} | |
| 11085 opcode(0xF3, 0x0F, 0x2C); | |
| 11086 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src), | |
| 11087 f2l_fixup(dst, src)); | |
| 11088 ins_pipe(pipe_slow); | |
| 11089 %} | |
| 11090 | |
| 11091 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr) | |
| 11092 %{ | |
| 11093 match(Set dst (ConvD2I src)); | |
| 11094 effect(KILL cr); | |
| 11095 | |
| 11096 format %{ "cvttsd2sil $dst, $src\t# d2i\n\t" | |
| 11097 "cmpl $dst, #0x80000000\n\t" | |
| 11098 "jne,s done\n\t" | |
| 11099 "subq rsp, #8\n\t" | |
| 11100 "movsd [rsp], $src\n\t" | |
| 11101 "call d2i_fixup\n\t" | |
| 11102 "popq $dst\n" | |
| 11103 "done: "%} | |
| 11104 opcode(0xF2, 0x0F, 0x2C); | |
| 11105 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src), | |
| 11106 d2i_fixup(dst, src)); | |
| 11107 ins_pipe(pipe_slow); | |
| 11108 %} | |
| 11109 | |
| 11110 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr) | |
| 11111 %{ | |
| 11112 match(Set dst (ConvD2L src)); | |
| 11113 effect(KILL cr); | |
| 11114 | |
| 11115 format %{ "cvttsd2siq $dst, $src\t# d2l\n\t" | |
| 11116 "cmpq $dst, [0x8000000000000000]\n\t" | |
| 11117 "jne,s done\n\t" | |
| 11118 "subq rsp, #8\n\t" | |
| 11119 "movsd [rsp], $src\n\t" | |
| 11120 "call d2l_fixup\n\t" | |
| 11121 "popq $dst\n" | |
| 11122 "done: "%} | |
| 11123 opcode(0xF2, 0x0F, 0x2C); | |
| 11124 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src), | |
| 11125 d2l_fixup(dst, src)); | |
| 11126 ins_pipe(pipe_slow); | |
| 11127 %} | |
| 11128 | |
| 11129 instruct convI2F_reg_reg(regF dst, rRegI src) | |
| 11130 %{ | |
| 71 | 11131 predicate(!UseXmmI2F); |
| 0 | 11132 match(Set dst (ConvI2F src)); |
| 11133 | |
| 11134 format %{ "cvtsi2ssl $dst, $src\t# i2f" %} | |
| 11135 opcode(0xF3, 0x0F, 0x2A); | |
| 11136 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 11137 ins_pipe(pipe_slow); // XXX | |
| 11138 %} | |
| 11139 | |
| 11140 instruct convI2F_reg_mem(regF dst, memory src) | |
| 11141 %{ | |
| 11142 match(Set dst (ConvI2F (LoadI src))); | |
| 11143 | |
| 11144 format %{ "cvtsi2ssl $dst, $src\t# i2f" %} | |
| 11145 opcode(0xF3, 0x0F, 0x2A); | |
| 11146 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 11147 ins_pipe(pipe_slow); // XXX | |
| 11148 %} | |
| 11149 | |
| 11150 instruct convI2D_reg_reg(regD dst, rRegI src) | |
| 11151 %{ | |
| 71 | 11152 predicate(!UseXmmI2D); |
| 0 | 11153 match(Set dst (ConvI2D src)); |
| 11154 | |
| 11155 format %{ "cvtsi2sdl $dst, $src\t# i2d" %} | |
| 11156 opcode(0xF2, 0x0F, 0x2A); | |
| 11157 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 11158 ins_pipe(pipe_slow); // XXX | |
| 11159 %} | |
| 11160 | |
| 11161 instruct convI2D_reg_mem(regD dst, memory src) | |
| 11162 %{ | |
| 11163 match(Set dst (ConvI2D (LoadI src))); | |
| 11164 | |
| 11165 format %{ "cvtsi2sdl $dst, $src\t# i2d" %} | |
| 11166 opcode(0xF2, 0x0F, 0x2A); | |
| 11167 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 11168 ins_pipe(pipe_slow); // XXX | |
| 11169 %} | |
| 11170 | |
| 71 | 11171 instruct convXI2F_reg(regF dst, rRegI src) |
| 11172 %{ | |
| 11173 predicate(UseXmmI2F); | |
| 11174 match(Set dst (ConvI2F src)); | |
| 11175 | |
| 11176 format %{ "movdl $dst, $src\n\t" | |
| 11177 "cvtdq2psl $dst, $dst\t# i2f" %} | |
| 11178 ins_encode %{ | |
| 11179 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 11180 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister); | |
| 11181 %} | |
| 11182 ins_pipe(pipe_slow); // XXX | |
| 11183 %} | |
| 11184 | |
| 11185 instruct convXI2D_reg(regD dst, rRegI src) | |
| 11186 %{ | |
| 11187 predicate(UseXmmI2D); | |
| 11188 match(Set dst (ConvI2D src)); | |
| 11189 | |
| 11190 format %{ "movdl $dst, $src\n\t" | |
| 11191 "cvtdq2pdl $dst, $dst\t# i2d" %} | |
| 11192 ins_encode %{ | |
| 11193 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 11194 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister); | |
| 11195 %} | |
| 11196 ins_pipe(pipe_slow); // XXX | |
| 11197 %} | |
| 11198 | |
| 0 | 11199 instruct convL2F_reg_reg(regF dst, rRegL src) |
| 11200 %{ | |
| 11201 match(Set dst (ConvL2F src)); | |
| 11202 | |
| 11203 format %{ "cvtsi2ssq $dst, $src\t# l2f" %} | |
| 11204 opcode(0xF3, 0x0F, 0x2A); | |
| 11205 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 11206 ins_pipe(pipe_slow); // XXX | |
| 11207 %} | |
| 11208 | |
| 11209 instruct convL2F_reg_mem(regF dst, memory src) | |
| 11210 %{ | |
| 11211 match(Set dst (ConvL2F (LoadL src))); | |
| 11212 | |
| 11213 format %{ "cvtsi2ssq $dst, $src\t# l2f" %} | |
| 11214 opcode(0xF3, 0x0F, 0x2A); | |
| 11215 ins_encode(OpcP, REX_reg_mem_wide(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 11216 ins_pipe(pipe_slow); // XXX | |
| 11217 %} | |
| 11218 | |
| 11219 instruct convL2D_reg_reg(regD dst, rRegL src) | |
| 11220 %{ | |
| 11221 match(Set dst (ConvL2D src)); | |
| 11222 | |
| 11223 format %{ "cvtsi2sdq $dst, $src\t# l2d" %} | |
| 11224 opcode(0xF2, 0x0F, 0x2A); | |
| 11225 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 11226 ins_pipe(pipe_slow); // XXX | |
| 11227 %} | |
| 11228 | |
| 11229 instruct convL2D_reg_mem(regD dst, memory src) | |
| 11230 %{ | |
| 11231 match(Set dst (ConvL2D (LoadL src))); | |
| 11232 | |
| 11233 format %{ "cvtsi2sdq $dst, $src\t# l2d" %} | |
| 11234 opcode(0xF2, 0x0F, 0x2A); | |
| 11235 ins_encode(OpcP, REX_reg_mem_wide(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 11236 ins_pipe(pipe_slow); // XXX | |
| 11237 %} | |
| 11238 | |
| 11239 instruct convI2L_reg_reg(rRegL dst, rRegI src) | |
| 11240 %{ | |
| 11241 match(Set dst (ConvI2L src)); | |
| 11242 | |
| 11243 ins_cost(125); | |
| 11244 format %{ "movslq $dst, $src\t# i2l" %} | |
| 824 | 11245 ins_encode %{ |
| 11246 __ movslq($dst$$Register, $src$$Register); | |
| 11247 %} | |
| 0 | 11248 ins_pipe(ialu_reg_reg); |
| 11249 %} | |
| 11250 | |
| 11251 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src) | |
| 11252 // %{ | |
| 11253 // match(Set dst (ConvI2L src)); | |
| 11254 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 && | |
| 11255 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0); | |
| 11256 // predicate(((const TypeNode*) n)->type()->is_long()->_hi == | |
| 11257 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi && | |
| 11258 // ((const TypeNode*) n)->type()->is_long()->_lo == | |
| 11259 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo); | |
| 11260 | |
| 11261 // format %{ "movl $dst, $src\t# unsigned i2l" %} | |
| 11262 // ins_encode(enc_copy(dst, src)); | |
| 11263 // // opcode(0x63); // needs REX.W | |
| 11264 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src)); | |
| 11265 // ins_pipe(ialu_reg_reg); | |
| 11266 // %} | |
| 11267 | |
| 11268 // Zero-extend convert int to long | |
| 11269 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask) | |
| 11270 %{ | |
| 11271 match(Set dst (AndL (ConvI2L src) mask)); | |
| 11272 | |
| 11273 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %} | |
| 11274 ins_encode(enc_copy(dst, src)); | |
| 11275 ins_pipe(ialu_reg_reg); | |
| 11276 %} | |
| 11277 | |
| 11278 // Zero-extend convert int to long | |
| 11279 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask) | |
| 11280 %{ | |
| 11281 match(Set dst (AndL (ConvI2L (LoadI src)) mask)); | |
| 11282 | |
| 11283 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %} | |
| 11284 opcode(0x8B); | |
| 11285 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 11286 ins_pipe(ialu_reg_mem); | |
| 11287 %} | |
| 11288 | |
| 11289 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask) | |
| 11290 %{ | |
| 11291 match(Set dst (AndL src mask)); | |
| 11292 | |
| 11293 format %{ "movl $dst, $src\t# zero-extend long" %} | |
| 11294 ins_encode(enc_copy_always(dst, src)); | |
| 11295 ins_pipe(ialu_reg_reg); | |
| 11296 %} | |
| 11297 | |
| 11298 instruct convL2I_reg_reg(rRegI dst, rRegL src) | |
| 11299 %{ | |
| 11300 match(Set dst (ConvL2I src)); | |
| 11301 | |
| 11302 format %{ "movl $dst, $src\t# l2i" %} | |
| 11303 ins_encode(enc_copy_always(dst, src)); | |
| 11304 ins_pipe(ialu_reg_reg); | |
| 11305 %} | |
| 11306 | |
| 11307 | |
| 11308 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{ | |
| 11309 match(Set dst (MoveF2I src)); | |
| 11310 effect(DEF dst, USE src); | |
| 11311 | |
| 11312 ins_cost(125); | |
| 11313 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %} | |
| 11314 opcode(0x8B); | |
| 11315 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 11316 ins_pipe(ialu_reg_mem); | |
| 11317 %} | |
| 11318 | |
| 11319 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ | |
| 11320 match(Set dst (MoveI2F src)); | |
| 11321 effect(DEF dst, USE src); | |
| 11322 | |
| 11323 ins_cost(125); | |
| 11324 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %} | |
| 11325 opcode(0xF3, 0x0F, 0x10); | |
| 11326 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 11327 ins_pipe(pipe_slow); | |
| 11328 %} | |
| 11329 | |
| 11330 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{ | |
| 11331 match(Set dst (MoveD2L src)); | |
| 11332 effect(DEF dst, USE src); | |
| 11333 | |
| 11334 ins_cost(125); | |
| 11335 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %} | |
| 11336 opcode(0x8B); | |
| 11337 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 11338 ins_pipe(ialu_reg_mem); | |
| 11339 %} | |
| 11340 | |
| 11341 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{ | |
| 11342 predicate(!UseXmmLoadAndClearUpper); | |
| 11343 match(Set dst (MoveL2D src)); | |
| 11344 effect(DEF dst, USE src); | |
| 11345 | |
| 11346 ins_cost(125); | |
| 11347 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %} | |
| 11348 opcode(0x66, 0x0F, 0x12); | |
| 11349 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 11350 ins_pipe(pipe_slow); | |
| 11351 %} | |
| 11352 | |
| 11353 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ | |
| 11354 predicate(UseXmmLoadAndClearUpper); | |
| 11355 match(Set dst (MoveL2D src)); | |
| 11356 effect(DEF dst, USE src); | |
| 11357 | |
| 11358 ins_cost(125); | |
| 11359 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %} | |
| 11360 opcode(0xF2, 0x0F, 0x10); | |
| 11361 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 11362 ins_pipe(pipe_slow); | |
| 11363 %} | |
| 11364 | |
| 11365 | |
| 11366 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ | |
| 11367 match(Set dst (MoveF2I src)); | |
| 11368 effect(DEF dst, USE src); | |
| 11369 | |
| 11370 ins_cost(95); // XXX | |
| 11371 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %} | |
| 11372 opcode(0xF3, 0x0F, 0x11); | |
| 11373 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst)); | |
| 11374 ins_pipe(pipe_slow); | |
| 11375 %} | |
| 11376 | |
| 11377 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{ | |
| 11378 match(Set dst (MoveI2F src)); | |
| 11379 effect(DEF dst, USE src); | |
| 11380 | |
| 11381 ins_cost(100); | |
| 11382 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %} | |
| 11383 opcode(0x89); | |
| 11384 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 11385 ins_pipe( ialu_mem_reg ); | |
| 11386 %} | |
| 11387 | |
| 11388 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ | |
| 11389 match(Set dst (MoveD2L src)); | |
| 11390 effect(DEF dst, USE src); | |
| 11391 | |
| 11392 ins_cost(95); // XXX | |
| 11393 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %} | |
| 11394 opcode(0xF2, 0x0F, 0x11); | |
| 11395 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst)); | |
| 11396 ins_pipe(pipe_slow); | |
| 11397 %} | |
| 11398 | |
| 11399 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{ | |
| 11400 match(Set dst (MoveL2D src)); | |
| 11401 effect(DEF dst, USE src); | |
| 11402 | |
| 11403 ins_cost(100); | |
| 11404 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %} | |
| 11405 opcode(0x89); | |
| 11406 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 11407 ins_pipe(ialu_mem_reg); | |
| 11408 %} | |
| 11409 | |
| 11410 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{ | |
| 11411 match(Set dst (MoveF2I src)); | |
| 11412 effect(DEF dst, USE src); | |
| 11413 ins_cost(85); | |
| 11414 format %{ "movd $dst,$src\t# MoveF2I" %} | |
| 11415 ins_encode %{ __ movdl($dst$$Register, $src$$XMMRegister); %} | |
| 11416 ins_pipe( pipe_slow ); | |
| 11417 %} | |
| 11418 | |
| 11419 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{ | |
| 11420 match(Set dst (MoveD2L src)); | |
| 11421 effect(DEF dst, USE src); | |
| 11422 ins_cost(85); | |
| 11423 format %{ "movd $dst,$src\t# MoveD2L" %} | |
| 11424 ins_encode %{ __ movdq($dst$$Register, $src$$XMMRegister); %} | |
| 11425 ins_pipe( pipe_slow ); | |
| 11426 %} | |
| 11427 | |
| 11428 // The next instructions have long latency and use Int unit. Set high cost. | |
| 11429 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{ | |
| 11430 match(Set dst (MoveI2F src)); | |
| 11431 effect(DEF dst, USE src); | |
| 11432 ins_cost(300); | |
| 11433 format %{ "movd $dst,$src\t# MoveI2F" %} | |
| 11434 ins_encode %{ __ movdl($dst$$XMMRegister, $src$$Register); %} | |
| 11435 ins_pipe( pipe_slow ); | |
| 11436 %} | |
| 11437 | |
| 11438 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{ | |
| 11439 match(Set dst (MoveL2D src)); | |
| 11440 effect(DEF dst, USE src); | |
| 11441 ins_cost(300); | |
| 11442 format %{ "movd $dst,$src\t# MoveL2D" %} | |
| 11443 ins_encode %{ __ movdq($dst$$XMMRegister, $src$$Register); %} | |
| 11444 ins_pipe( pipe_slow ); | |
| 11445 %} | |
| 11446 | |
| 11447 // Replicate scalar to packed byte (1 byte) values in xmm | |
| 11448 instruct Repl8B_reg(regD dst, regD src) %{ | |
| 11449 match(Set dst (Replicate8B src)); | |
| 11450 format %{ "MOVDQA $dst,$src\n\t" | |
| 11451 "PUNPCKLBW $dst,$dst\n\t" | |
| 11452 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %} | |
| 11453 ins_encode( pshufd_8x8(dst, src)); | |
| 11454 ins_pipe( pipe_slow ); | |
| 11455 %} | |
| 11456 | |
| 11457 // Replicate scalar to packed byte (1 byte) values in xmm | |
| 11458 instruct Repl8B_rRegI(regD dst, rRegI src) %{ | |
| 11459 match(Set dst (Replicate8B src)); | |
| 11460 format %{ "MOVD $dst,$src\n\t" | |
| 11461 "PUNPCKLBW $dst,$dst\n\t" | |
| 11462 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %} | |
| 11463 ins_encode( mov_i2x(dst, src), pshufd_8x8(dst, dst)); | |
| 11464 ins_pipe( pipe_slow ); | |
| 11465 %} | |
| 11466 | |
| 11467 // Replicate scalar zero to packed byte (1 byte) values in xmm | |
| 11468 instruct Repl8B_immI0(regD dst, immI0 zero) %{ | |
| 11469 match(Set dst (Replicate8B zero)); | |
| 11470 format %{ "PXOR $dst,$dst\t! replicate8B" %} | |
| 11471 ins_encode( pxor(dst, dst)); | |
| 11472 ins_pipe( fpu_reg_reg ); | |
| 11473 %} | |
| 11474 | |
| 11475 // Replicate scalar to packed shore (2 byte) values in xmm | |
| 11476 instruct Repl4S_reg(regD dst, regD src) %{ | |
| 11477 match(Set dst (Replicate4S src)); | |
| 11478 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %} | |
| 11479 ins_encode( pshufd_4x16(dst, src)); | |
| 11480 ins_pipe( fpu_reg_reg ); | |
| 11481 %} | |
| 11482 | |
| 11483 // Replicate scalar to packed shore (2 byte) values in xmm | |
| 11484 instruct Repl4S_rRegI(regD dst, rRegI src) %{ | |
| 11485 match(Set dst (Replicate4S src)); | |
| 11486 format %{ "MOVD $dst,$src\n\t" | |
| 11487 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %} | |
| 11488 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst)); | |
| 11489 ins_pipe( fpu_reg_reg ); | |
| 11490 %} | |
| 11491 | |
| 11492 // Replicate scalar zero to packed short (2 byte) values in xmm | |
| 11493 instruct Repl4S_immI0(regD dst, immI0 zero) %{ | |
| 11494 match(Set dst (Replicate4S zero)); | |
| 11495 format %{ "PXOR $dst,$dst\t! replicate4S" %} | |
| 11496 ins_encode( pxor(dst, dst)); | |
| 11497 ins_pipe( fpu_reg_reg ); | |
| 11498 %} | |
| 11499 | |
| 11500 // Replicate scalar to packed char (2 byte) values in xmm | |
| 11501 instruct Repl4C_reg(regD dst, regD src) %{ | |
| 11502 match(Set dst (Replicate4C src)); | |
| 11503 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %} | |
| 11504 ins_encode( pshufd_4x16(dst, src)); | |
| 11505 ins_pipe( fpu_reg_reg ); | |
| 11506 %} | |
| 11507 | |
| 11508 // Replicate scalar to packed char (2 byte) values in xmm | |
| 11509 instruct Repl4C_rRegI(regD dst, rRegI src) %{ | |
| 11510 match(Set dst (Replicate4C src)); | |
| 11511 format %{ "MOVD $dst,$src\n\t" | |
| 11512 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %} | |
| 11513 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst)); | |
| 11514 ins_pipe( fpu_reg_reg ); | |
| 11515 %} | |
| 11516 | |
| 11517 // Replicate scalar zero to packed char (2 byte) values in xmm | |
| 11518 instruct Repl4C_immI0(regD dst, immI0 zero) %{ | |
| 11519 match(Set dst (Replicate4C zero)); | |
| 11520 format %{ "PXOR $dst,$dst\t! replicate4C" %} | |
| 11521 ins_encode( pxor(dst, dst)); | |
| 11522 ins_pipe( fpu_reg_reg ); | |
| 11523 %} | |
| 11524 | |
| 11525 // Replicate scalar to packed integer (4 byte) values in xmm | |
| 11526 instruct Repl2I_reg(regD dst, regD src) %{ | |
| 11527 match(Set dst (Replicate2I src)); | |
| 11528 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %} | |
| 11529 ins_encode( pshufd(dst, src, 0x00)); | |
| 11530 ins_pipe( fpu_reg_reg ); | |
| 11531 %} | |
| 11532 | |
| 11533 // Replicate scalar to packed integer (4 byte) values in xmm | |
| 11534 instruct Repl2I_rRegI(regD dst, rRegI src) %{ | |
| 11535 match(Set dst (Replicate2I src)); | |
| 11536 format %{ "MOVD $dst,$src\n\t" | |
| 11537 "PSHUFD $dst,$dst,0x00\t! replicate2I" %} | |
| 11538 ins_encode( mov_i2x(dst, src), pshufd(dst, dst, 0x00)); | |
| 11539 ins_pipe( fpu_reg_reg ); | |
| 11540 %} | |
| 11541 | |
| 11542 // Replicate scalar zero to packed integer (2 byte) values in xmm | |
| 11543 instruct Repl2I_immI0(regD dst, immI0 zero) %{ | |
| 11544 match(Set dst (Replicate2I zero)); | |
| 11545 format %{ "PXOR $dst,$dst\t! replicate2I" %} | |
| 11546 ins_encode( pxor(dst, dst)); | |
| 11547 ins_pipe( fpu_reg_reg ); | |
| 11548 %} | |
| 11549 | |
| 11550 // Replicate scalar to packed single precision floating point values in xmm | |
| 11551 instruct Repl2F_reg(regD dst, regD src) %{ | |
| 11552 match(Set dst (Replicate2F src)); | |
| 11553 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %} | |
| 11554 ins_encode( pshufd(dst, src, 0xe0)); | |
| 11555 ins_pipe( fpu_reg_reg ); | |
| 11556 %} | |
| 11557 | |
| 11558 // Replicate scalar to packed single precision floating point values in xmm | |
| 11559 instruct Repl2F_regF(regD dst, regF src) %{ | |
| 11560 match(Set dst (Replicate2F src)); | |
| 11561 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %} | |
| 11562 ins_encode( pshufd(dst, src, 0xe0)); | |
| 11563 ins_pipe( fpu_reg_reg ); | |
| 11564 %} | |
| 11565 | |
| 11566 // Replicate scalar to packed single precision floating point values in xmm | |
| 11567 instruct Repl2F_immF0(regD dst, immF0 zero) %{ | |
| 11568 match(Set dst (Replicate2F zero)); | |
| 11569 format %{ "PXOR $dst,$dst\t! replicate2F" %} | |
| 11570 ins_encode( pxor(dst, dst)); | |
| 11571 ins_pipe( fpu_reg_reg ); | |
| 11572 %} | |
| 11573 | |
| 11574 | |
| 11575 // ======================================================================= | |
| 11576 // fast clearing of an array | |
| 11577 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy, | |
| 11578 rFlagsReg cr) | |
| 11579 %{ | |
| 11580 match(Set dummy (ClearArray cnt base)); | |
| 11581 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr); | |
| 11582 | |
| 11583 format %{ "xorl rax, rax\t# ClearArray:\n\t" | |
| 11584 "rep stosq\t# Store rax to *rdi++ while rcx--" %} | |
| 11585 ins_encode(opc_reg_reg(0x33, RAX, RAX), // xorl %eax, %eax | |
| 11586 Opcode(0xF3), Opcode(0x48), Opcode(0xAB)); // rep REX_W stos | |
| 11587 ins_pipe(pipe_slow); | |
| 11588 %} | |
| 11589 | |
| 2262 | 11590 instruct string_compare(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2, |
| 11591 rax_RegI result, regD tmp1, rFlagsReg cr) | |
|
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11592 %{ |
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11593 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); |
| 2262 | 11594 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr); |
| 11595 | |
| 11596 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %} | |
|
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11597 ins_encode %{ |
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11598 __ string_compare($str1$$Register, $str2$$Register, |
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11599 $cnt1$$Register, $cnt2$$Register, $result$$Register, |
| 2262 | 11600 $tmp1$$XMMRegister); |
|
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11601 %} |
| 681 | 11602 ins_pipe( pipe_slow ); |
| 11603 %} | |
| 11604 | |
|
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11605 // fast search of substring with known size. |
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11606 instruct string_indexof_con(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2, |
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11607 rbx_RegI result, regD vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr) |
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11608 %{ |
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11609 predicate(UseSSE42Intrinsics); |
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11610 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2))); |
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11611 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr); |
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11612 |
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11613 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %} |
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11614 ins_encode %{ |
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11615 int icnt2 = (int)$int_cnt2$$constant; |
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11616 if (icnt2 >= 8) { |
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11617 // IndexOf for constant substrings with size >= 8 elements |
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11618 // which don't need to be loaded through stack. |
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11619 __ string_indexofC8($str1$$Register, $str2$$Register, |
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11620 $cnt1$$Register, $cnt2$$Register, |
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11621 icnt2, $result$$Register, |
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11622 $vec$$XMMRegister, $tmp$$Register); |
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11623 } else { |
|
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11624 // Small strings are loaded through stack if they cross page boundary. |
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11625 __ string_indexof($str1$$Register, $str2$$Register, |
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11626 $cnt1$$Register, $cnt2$$Register, |
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11627 icnt2, $result$$Register, |
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11628 $vec$$XMMRegister, $tmp$$Register); |
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11629 } |
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11630 %} |
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11631 ins_pipe( pipe_slow ); |
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11632 %} |
|
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11633 |
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11634 instruct string_indexof(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2, |
|
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11635 rbx_RegI result, regD vec, rcx_RegI tmp, rFlagsReg cr) |
| 681 | 11636 %{ |
| 11637 predicate(UseSSE42Intrinsics); | |
|
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11638 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2))); |
|
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11639 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr); |
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11640 |
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11641 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %} |
|
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11642 ins_encode %{ |
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11643 __ string_indexof($str1$$Register, $str2$$Register, |
|
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11644 $cnt1$$Register, $cnt2$$Register, |
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11645 (-1), $result$$Register, |
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11646 $vec$$XMMRegister, $tmp$$Register); |
|
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11647 %} |
| 681 | 11648 ins_pipe( pipe_slow ); |
| 11649 %} | |
| 11650 | |
| 11651 // fast string equals | |
|
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11652 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result, |
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11653 regD tmp1, regD tmp2, rbx_RegI tmp3, rFlagsReg cr) |
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11654 %{ |
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11655 match(Set result (StrEquals (Binary str1 str2) cnt)); |
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11656 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr); |
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11657 |
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11658 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %} |
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11659 ins_encode %{ |
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11660 __ char_arrays_equals(false, $str1$$Register, $str2$$Register, |
|
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11661 $cnt$$Register, $result$$Register, $tmp3$$Register, |
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11662 $tmp1$$XMMRegister, $tmp2$$XMMRegister); |
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11663 %} |
| 0 | 11664 ins_pipe( pipe_slow ); |
| 11665 %} | |
| 11666 | |
|
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11667 // fast array equals |
|
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11668 instruct array_equals(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result, |
|
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11669 regD tmp1, regD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr) |
| 681 | 11670 %{ |
|
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11671 match(Set result (AryEq ary1 ary2)); |
| 681 | 11672 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr); |
|
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11673 //ins_cost(300); |
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11674 |
|
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11675 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %} |
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11676 ins_encode %{ |
|
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11677 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register, |
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11678 $tmp3$$Register, $result$$Register, $tmp4$$Register, |
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11679 $tmp1$$XMMRegister, $tmp2$$XMMRegister); |
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11680 %} |
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11681 ins_pipe( pipe_slow ); |
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11682 %} |
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11683 |
| 0 | 11684 //----------Control Flow Instructions------------------------------------------ |
| 11685 // Signed compare Instructions | |
| 11686 | |
| 11687 // XXX more variants!! | |
| 11688 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2) | |
| 11689 %{ | |
| 11690 match(Set cr (CmpI op1 op2)); | |
| 11691 effect(DEF cr, USE op1, USE op2); | |
| 11692 | |
| 11693 format %{ "cmpl $op1, $op2" %} | |
| 11694 opcode(0x3B); /* Opcode 3B /r */ | |
| 11695 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2)); | |
| 11696 ins_pipe(ialu_cr_reg_reg); | |
| 11697 %} | |
| 11698 | |
| 11699 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2) | |
| 11700 %{ | |
| 11701 match(Set cr (CmpI op1 op2)); | |
| 11702 | |
| 11703 format %{ "cmpl $op1, $op2" %} | |
| 11704 opcode(0x81, 0x07); /* Opcode 81 /7 */ | |
| 11705 ins_encode(OpcSErm(op1, op2), Con8or32(op2)); | |
| 11706 ins_pipe(ialu_cr_reg_imm); | |
| 11707 %} | |
| 11708 | |
| 11709 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2) | |
| 11710 %{ | |
| 11711 match(Set cr (CmpI op1 (LoadI op2))); | |
| 11712 | |
| 11713 ins_cost(500); // XXX | |
| 11714 format %{ "cmpl $op1, $op2" %} | |
| 11715 opcode(0x3B); /* Opcode 3B /r */ | |
| 11716 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 11717 ins_pipe(ialu_cr_reg_mem); | |
| 11718 %} | |
| 11719 | |
| 11720 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero) | |
| 11721 %{ | |
| 11722 match(Set cr (CmpI src zero)); | |
| 11723 | |
| 11724 format %{ "testl $src, $src" %} | |
| 11725 opcode(0x85); | |
| 11726 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src)); | |
| 11727 ins_pipe(ialu_cr_reg_imm); | |
| 11728 %} | |
| 11729 | |
| 11730 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero) | |
| 11731 %{ | |
| 11732 match(Set cr (CmpI (AndI src con) zero)); | |
| 11733 | |
| 11734 format %{ "testl $src, $con" %} | |
| 11735 opcode(0xF7, 0x00); | |
| 11736 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con)); | |
| 11737 ins_pipe(ialu_cr_reg_imm); | |
| 11738 %} | |
| 11739 | |
| 11740 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero) | |
| 11741 %{ | |
| 11742 match(Set cr (CmpI (AndI src (LoadI mem)) zero)); | |
| 11743 | |
| 11744 format %{ "testl $src, $mem" %} | |
| 11745 opcode(0x85); | |
| 11746 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
| 11747 ins_pipe(ialu_cr_reg_mem); | |
| 11748 %} | |
| 11749 | |
| 11750 // Unsigned compare Instructions; really, same as signed except they | |
| 11751 // produce an rFlagsRegU instead of rFlagsReg. | |
| 11752 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2) | |
| 11753 %{ | |
| 11754 match(Set cr (CmpU op1 op2)); | |
| 11755 | |
| 11756 format %{ "cmpl $op1, $op2\t# unsigned" %} | |
| 11757 opcode(0x3B); /* Opcode 3B /r */ | |
| 11758 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2)); | |
| 11759 ins_pipe(ialu_cr_reg_reg); | |
| 11760 %} | |
| 11761 | |
| 11762 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2) | |
| 11763 %{ | |
| 11764 match(Set cr (CmpU op1 op2)); | |
| 11765 | |
| 11766 format %{ "cmpl $op1, $op2\t# unsigned" %} | |
| 11767 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 11768 ins_encode(OpcSErm(op1, op2), Con8or32(op2)); | |
| 11769 ins_pipe(ialu_cr_reg_imm); | |
| 11770 %} | |
| 11771 | |
| 11772 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2) | |
| 11773 %{ | |
| 11774 match(Set cr (CmpU op1 (LoadI op2))); | |
| 11775 | |
| 11776 ins_cost(500); // XXX | |
| 11777 format %{ "cmpl $op1, $op2\t# unsigned" %} | |
| 11778 opcode(0x3B); /* Opcode 3B /r */ | |
| 11779 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 11780 ins_pipe(ialu_cr_reg_mem); | |
| 11781 %} | |
| 11782 | |
| 11783 // // // Cisc-spilled version of cmpU_rReg | |
| 11784 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2) | |
| 11785 // //%{ | |
| 11786 // // match(Set cr (CmpU (LoadI op1) op2)); | |
| 11787 // // | |
| 11788 // // format %{ "CMPu $op1,$op2" %} | |
| 11789 // // ins_cost(500); | |
| 11790 // // opcode(0x39); /* Opcode 39 /r */ | |
| 11791 // // ins_encode( OpcP, reg_mem( op1, op2) ); | |
| 11792 // //%} | |
| 11793 | |
| 11794 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero) | |
| 11795 %{ | |
| 11796 match(Set cr (CmpU src zero)); | |
| 11797 | |
| 11798 format %{ "testl $src, $src\t# unsigned" %} | |
| 11799 opcode(0x85); | |
| 11800 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src)); | |
| 11801 ins_pipe(ialu_cr_reg_imm); | |
| 11802 %} | |
| 11803 | |
| 11804 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2) | |
| 11805 %{ | |
| 11806 match(Set cr (CmpP op1 op2)); | |
| 11807 | |
| 11808 format %{ "cmpq $op1, $op2\t# ptr" %} | |
| 11809 opcode(0x3B); /* Opcode 3B /r */ | |
| 11810 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2)); | |
| 11811 ins_pipe(ialu_cr_reg_reg); | |
| 11812 %} | |
| 11813 | |
| 11814 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2) | |
| 11815 %{ | |
| 11816 match(Set cr (CmpP op1 (LoadP op2))); | |
| 11817 | |
| 11818 ins_cost(500); // XXX | |
| 11819 format %{ "cmpq $op1, $op2\t# ptr" %} | |
| 11820 opcode(0x3B); /* Opcode 3B /r */ | |
| 11821 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 11822 ins_pipe(ialu_cr_reg_mem); | |
| 11823 %} | |
| 11824 | |
| 11825 // // // Cisc-spilled version of cmpP_rReg | |
| 11826 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2) | |
| 11827 // //%{ | |
| 11828 // // match(Set cr (CmpP (LoadP op1) op2)); | |
| 11829 // // | |
| 11830 // // format %{ "CMPu $op1,$op2" %} | |
| 11831 // // ins_cost(500); | |
| 11832 // // opcode(0x39); /* Opcode 39 /r */ | |
| 11833 // // ins_encode( OpcP, reg_mem( op1, op2) ); | |
| 11834 // //%} | |
| 11835 | |
| 11836 // XXX this is generalized by compP_rReg_mem??? | |
| 11837 // Compare raw pointer (used in out-of-heap check). | |
| 11838 // Only works because non-oop pointers must be raw pointers | |
| 11839 // and raw pointers have no anti-dependencies. | |
| 11840 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2) | |
| 11841 %{ | |
| 11842 predicate(!n->in(2)->in(2)->bottom_type()->isa_oop_ptr()); | |
| 11843 match(Set cr (CmpP op1 (LoadP op2))); | |
| 11844 | |
| 11845 format %{ "cmpq $op1, $op2\t# raw ptr" %} | |
| 11846 opcode(0x3B); /* Opcode 3B /r */ | |
| 11847 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 11848 ins_pipe(ialu_cr_reg_mem); | |
| 11849 %} | |
| 11850 | |
| 11851 // This will generate a signed flags result. This should be OK since | |
| 11852 // any compare to a zero should be eq/neq. | |
| 11853 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero) | |
| 11854 %{ | |
| 11855 match(Set cr (CmpP src zero)); | |
| 11856 | |
| 11857 format %{ "testq $src, $src\t# ptr" %} | |
| 11858 opcode(0x85); | |
| 11859 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src)); | |
| 11860 ins_pipe(ialu_cr_reg_imm); | |
| 11861 %} | |
| 11862 | |
| 11863 // This will generate a signed flags result. This should be OK since | |
| 11864 // any compare to a zero should be eq/neq. | |
|
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11865 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero) |
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11866 %{ |
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11867 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL)); |
| 0 | 11868 match(Set cr (CmpP (LoadP op) zero)); |
| 11869 | |
| 11870 ins_cost(500); // XXX | |
| 11871 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %} | |
| 11872 opcode(0xF7); /* Opcode F7 /0 */ | |
| 11873 ins_encode(REX_mem_wide(op), | |
| 11874 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF)); | |
| 11875 ins_pipe(ialu_cr_reg_imm); | |
| 11876 %} | |
| 11877 | |
|
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11878 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero) |
|
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11879 %{ |
|
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11880 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
|
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11881 match(Set cr (CmpP (LoadP mem) zero)); |
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11882 |
|
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11883 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %} |
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11884 ins_encode %{ |
|
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|
11885 __ cmpq(r12, $mem$$Address); |
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11886 %} |
|
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11887 ins_pipe(ialu_cr_reg_mem); |
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11888 %} |
|
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11889 |
|
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11890 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2) |
|
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11891 %{ |
|
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11892 match(Set cr (CmpN op1 op2)); |
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11893 |
|
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11894 format %{ "cmpl $op1, $op2\t# compressed ptr" %} |
|
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11895 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %} |
|
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11896 ins_pipe(ialu_cr_reg_reg); |
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11897 %} |
|
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11898 |
|
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11899 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem) |
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11900 %{ |
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11901 match(Set cr (CmpN src (LoadN mem))); |
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11902 |
|
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11903 format %{ "cmpl $src, $mem\t# compressed ptr" %} |
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11904 ins_encode %{ |
|
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11905 __ cmpl($src$$Register, $mem$$Address); |
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11906 %} |
|
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11907 ins_pipe(ialu_cr_reg_mem); |
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11908 %} |
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11909 |
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11910 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{ |
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11911 match(Set cr (CmpN op1 op2)); |
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11912 |
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11913 format %{ "cmpl $op1, $op2\t# compressed ptr" %} |
|
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11914 ins_encode %{ |
|
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11915 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant); |
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11916 %} |
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11917 ins_pipe(ialu_cr_reg_imm); |
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11918 %} |
|
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11919 |
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11920 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src) |
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11921 %{ |
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11922 match(Set cr (CmpN src (LoadN mem))); |
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11923 |
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11924 format %{ "cmpl $mem, $src\t# compressed ptr" %} |
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11925 ins_encode %{ |
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11926 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant); |
|
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11927 %} |
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11928 ins_pipe(ialu_cr_reg_mem); |
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11929 %} |
|
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11930 |
|
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11931 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{ |
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11932 match(Set cr (CmpN src zero)); |
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|
11933 |
|
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11934 format %{ "testl $src, $src\t# compressed ptr" %} |
|
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11935 ins_encode %{ __ testl($src$$Register, $src$$Register); %} |
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11936 ins_pipe(ialu_cr_reg_imm); |
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|
11937 %} |
|
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|
11938 |
|
642
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|
11939 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero) |
|
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|
11940 %{ |
|
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|
11941 predicate(Universe::narrow_oop_base() != NULL); |
|
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11942 match(Set cr (CmpN (LoadN mem) zero)); |
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|
11943 |
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|
11944 ins_cost(500); // XXX |
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11945 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %} |
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11946 ins_encode %{ |
|
642
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|
11947 __ cmpl($mem$$Address, (int)0xFFFFFFFF); |
|
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|
11948 %} |
|
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|
11949 ins_pipe(ialu_cr_reg_mem); |
|
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|
11950 %} |
|
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|
11951 |
|
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|
11952 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero) |
|
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|
11953 %{ |
|
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|
11954 predicate(Universe::narrow_oop_base() == NULL); |
|
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|
11955 match(Set cr (CmpN (LoadN mem) zero)); |
|
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|
11956 |
|
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|
11957 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %} |
|
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|
11958 ins_encode %{ |
|
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|
11959 __ cmpl(r12, $mem$$Address); |
|
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11960 %} |
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|
11961 ins_pipe(ialu_cr_reg_mem); |
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|
11962 %} |
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|
11963 |
| 0 | 11964 // Yanked all unsigned pointer compare operations. |
| 11965 // Pointer compares are done with CmpP which is already unsigned. | |
| 11966 | |
| 11967 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2) | |
| 11968 %{ | |
| 11969 match(Set cr (CmpL op1 op2)); | |
| 11970 | |
| 11971 format %{ "cmpq $op1, $op2" %} | |
| 11972 opcode(0x3B); /* Opcode 3B /r */ | |
| 11973 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2)); | |
| 11974 ins_pipe(ialu_cr_reg_reg); | |
| 11975 %} | |
| 11976 | |
| 11977 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2) | |
| 11978 %{ | |
| 11979 match(Set cr (CmpL op1 op2)); | |
| 11980 | |
| 11981 format %{ "cmpq $op1, $op2" %} | |
| 11982 opcode(0x81, 0x07); /* Opcode 81 /7 */ | |
| 11983 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2)); | |
| 11984 ins_pipe(ialu_cr_reg_imm); | |
| 11985 %} | |
| 11986 | |
| 11987 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2) | |
| 11988 %{ | |
| 11989 match(Set cr (CmpL op1 (LoadL op2))); | |
| 11990 | |
| 11991 format %{ "cmpq $op1, $op2" %} | |
| 11992 opcode(0x3B); /* Opcode 3B /r */ | |
| 11993 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 11994 ins_pipe(ialu_cr_reg_mem); | |
| 11995 %} | |
| 11996 | |
| 11997 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero) | |
| 11998 %{ | |
| 11999 match(Set cr (CmpL src zero)); | |
| 12000 | |
| 12001 format %{ "testq $src, $src" %} | |
| 12002 opcode(0x85); | |
| 12003 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src)); | |
| 12004 ins_pipe(ialu_cr_reg_imm); | |
| 12005 %} | |
| 12006 | |
| 12007 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero) | |
| 12008 %{ | |
| 12009 match(Set cr (CmpL (AndL src con) zero)); | |
| 12010 | |
| 12011 format %{ "testq $src, $con\t# long" %} | |
| 12012 opcode(0xF7, 0x00); | |
| 12013 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con)); | |
| 12014 ins_pipe(ialu_cr_reg_imm); | |
| 12015 %} | |
| 12016 | |
| 12017 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero) | |
| 12018 %{ | |
| 12019 match(Set cr (CmpL (AndL src (LoadL mem)) zero)); | |
| 12020 | |
| 12021 format %{ "testq $src, $mem" %} | |
| 12022 opcode(0x85); | |
| 12023 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem)); | |
| 12024 ins_pipe(ialu_cr_reg_mem); | |
| 12025 %} | |
| 12026 | |
| 12027 // Manifest a CmpL result in an integer register. Very painful. | |
| 12028 // This is the test to avoid. | |
| 12029 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags) | |
| 12030 %{ | |
| 12031 match(Set dst (CmpL3 src1 src2)); | |
| 12032 effect(KILL flags); | |
| 12033 | |
| 12034 ins_cost(275); // XXX | |
| 12035 format %{ "cmpq $src1, $src2\t# CmpL3\n\t" | |
| 12036 "movl $dst, -1\n\t" | |
| 12037 "jl,s done\n\t" | |
| 12038 "setne $dst\n\t" | |
| 12039 "movzbl $dst, $dst\n\t" | |
| 12040 "done:" %} | |
| 12041 ins_encode(cmpl3_flag(src1, src2, dst)); | |
| 12042 ins_pipe(pipe_slow); | |
| 12043 %} | |
| 12044 | |
| 12045 //----------Max and Min-------------------------------------------------------- | |
| 12046 // Min Instructions | |
| 12047 | |
| 12048 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr) | |
| 12049 %{ | |
| 12050 effect(USE_DEF dst, USE src, USE cr); | |
| 12051 | |
| 12052 format %{ "cmovlgt $dst, $src\t# min" %} | |
| 12053 opcode(0x0F, 0x4F); | |
| 12054 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 12055 ins_pipe(pipe_cmov_reg); | |
| 12056 %} | |
| 12057 | |
| 12058 | |
| 12059 instruct minI_rReg(rRegI dst, rRegI src) | |
| 12060 %{ | |
| 12061 match(Set dst (MinI dst src)); | |
| 12062 | |
| 12063 ins_cost(200); | |
| 12064 expand %{ | |
| 12065 rFlagsReg cr; | |
| 12066 compI_rReg(cr, dst, src); | |
| 12067 cmovI_reg_g(dst, src, cr); | |
| 12068 %} | |
| 12069 %} | |
| 12070 | |
| 12071 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr) | |
| 12072 %{ | |
| 12073 effect(USE_DEF dst, USE src, USE cr); | |
| 12074 | |
| 12075 format %{ "cmovllt $dst, $src\t# max" %} | |
| 12076 opcode(0x0F, 0x4C); | |
| 12077 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 12078 ins_pipe(pipe_cmov_reg); | |
| 12079 %} | |
| 12080 | |
| 12081 | |
| 12082 instruct maxI_rReg(rRegI dst, rRegI src) | |
| 12083 %{ | |
| 12084 match(Set dst (MaxI dst src)); | |
| 12085 | |
| 12086 ins_cost(200); | |
| 12087 expand %{ | |
| 12088 rFlagsReg cr; | |
| 12089 compI_rReg(cr, dst, src); | |
| 12090 cmovI_reg_l(dst, src, cr); | |
| 12091 %} | |
| 12092 %} | |
| 12093 | |
| 12094 // ============================================================================ | |
| 12095 // Branch Instructions | |
| 12096 | |
| 12097 // Jump Direct - Label defines a relative address from JMP+1 | |
| 12098 instruct jmpDir(label labl) | |
| 12099 %{ | |
| 12100 match(Goto); | |
| 12101 effect(USE labl); | |
| 12102 | |
| 12103 ins_cost(300); | |
| 12104 format %{ "jmp $labl" %} | |
| 12105 size(5); | |
| 12106 opcode(0xE9); | |
| 12107 ins_encode(OpcP, Lbl(labl)); | |
| 12108 ins_pipe(pipe_jmp); | |
| 12109 ins_pc_relative(1); | |
| 12110 %} | |
| 12111 | |
| 12112 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12113 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl) | |
| 12114 %{ | |
| 12115 match(If cop cr); | |
| 12116 effect(USE labl); | |
| 12117 | |
| 12118 ins_cost(300); | |
| 12119 format %{ "j$cop $labl" %} | |
| 12120 size(6); | |
| 12121 opcode(0x0F, 0x80); | |
| 12122 ins_encode(Jcc(cop, labl)); | |
| 12123 ins_pipe(pipe_jcc); | |
| 12124 ins_pc_relative(1); | |
| 12125 %} | |
| 12126 | |
| 12127 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12128 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl) | |
| 12129 %{ | |
| 12130 match(CountedLoopEnd cop cr); | |
| 12131 effect(USE labl); | |
| 12132 | |
| 12133 ins_cost(300); | |
| 12134 format %{ "j$cop $labl\t# loop end" %} | |
| 12135 size(6); | |
| 12136 opcode(0x0F, 0x80); | |
| 12137 ins_encode(Jcc(cop, labl)); | |
| 12138 ins_pipe(pipe_jcc); | |
| 12139 ins_pc_relative(1); | |
| 12140 %} | |
| 12141 | |
| 12142 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
|
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|
12143 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
| 0 | 12144 match(CountedLoopEnd cop cmp); |
| 12145 effect(USE labl); | |
| 12146 | |
| 12147 ins_cost(300); | |
| 12148 format %{ "j$cop,u $labl\t# loop end" %} | |
| 12149 size(6); | |
| 12150 opcode(0x0F, 0x80); | |
| 12151 ins_encode(Jcc(cop, labl)); | |
| 12152 ins_pipe(pipe_jcc); | |
| 12153 ins_pc_relative(1); | |
| 12154 %} | |
| 12155 | |
|
415
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|
12156 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
|
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|
12157 match(CountedLoopEnd cop cmp); |
|
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|
12158 effect(USE labl); |
|
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|
12159 |
|
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|
12160 ins_cost(200); |
|
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|
12161 format %{ "j$cop,u $labl\t# loop end" %} |
|
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|
12162 size(6); |
|
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|
12163 opcode(0x0F, 0x80); |
|
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|
12164 ins_encode(Jcc(cop, labl)); |
|
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|
12165 ins_pipe(pipe_jcc); |
|
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|
12166 ins_pc_relative(1); |
|
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diff
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|
12167 %} |
|
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|
12168 |
| 0 | 12169 // Jump Direct Conditional - using unsigned comparison |
|
415
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|
12170 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
| 0 | 12171 match(If cop cmp); |
| 12172 effect(USE labl); | |
| 12173 | |
| 12174 ins_cost(300); | |
|
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|
12175 format %{ "j$cop,u $labl" %} |
|
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diff
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|
12176 size(6); |
|
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|
12177 opcode(0x0F, 0x80); |
|
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|
12178 ins_encode(Jcc(cop, labl)); |
|
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|
12179 ins_pipe(pipe_jcc); |
|
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|
12180 ins_pc_relative(1); |
|
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diff
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|
12181 %} |
|
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changeset
|
12182 |
|
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|
12183 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
|
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|
12184 match(If cop cmp); |
|
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|
12185 effect(USE labl); |
|
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changeset
|
12186 |
|
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|
12187 ins_cost(200); |
|
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|
12188 format %{ "j$cop,u $labl" %} |
| 0 | 12189 size(6); |
| 12190 opcode(0x0F, 0x80); | |
| 12191 ins_encode(Jcc(cop, labl)); | |
| 12192 ins_pipe(pipe_jcc); | |
| 12193 ins_pc_relative(1); | |
| 12194 %} | |
| 12195 | |
|
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|
12196 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{ |
|
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|
12197 match(If cop cmp); |
|
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|
12198 effect(USE labl); |
|
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changeset
|
12199 |
|
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|
12200 ins_cost(200); |
|
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|
12201 format %{ $$template |
|
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diff
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|
12202 if ($cop$$cmpcode == Assembler::notEqual) { |
|
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|
12203 $$emit$$"jp,u $labl\n\t" |
|
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12204 $$emit$$"j$cop,u $labl" |
|
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|
12205 } else { |
|
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|
12206 $$emit$$"jp,u done\n\t" |
|
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12207 $$emit$$"j$cop,u $labl\n\t" |
|
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12208 $$emit$$"done:" |
|
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|
12209 } |
|
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|
12210 %} |
|
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|
12211 size(12); |
|
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|
12212 opcode(0x0F, 0x80); |
|
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|
12213 ins_encode %{ |
|
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|
12214 Label* l = $labl$$label; |
|
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12215 $$$emit8$primary; |
|
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12216 emit_cc(cbuf, $secondary, Assembler::parity); |
|
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12217 int parity_disp = -1; |
|
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|
12218 if ($cop$$cmpcode == Assembler::notEqual) { |
|
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12219 // the two jumps 6 bytes apart so the jump distances are too |
| 1748 | 12220 parity_disp = l ? (l->loc_pos() - (cbuf.insts_size() + 4)) : 0; |
|
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12221 } else if ($cop$$cmpcode == Assembler::equal) { |
|
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|
12222 parity_disp = 6; |
|
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|
12223 } else { |
|
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|
12224 ShouldNotReachHere(); |
|
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|
12225 } |
|
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|
12226 emit_d32(cbuf, parity_disp); |
|
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12227 $$$emit8$primary; |
|
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|
12228 emit_cc(cbuf, $secondary, $cop$$cmpcode); |
| 1748 | 12229 int disp = l ? (l->loc_pos() - (cbuf.insts_size() + 4)) : 0; |
|
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|
12230 emit_d32(cbuf, disp); |
|
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|
12231 %} |
|
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|
12232 ins_pipe(pipe_jcc); |
|
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12233 ins_pc_relative(1); |
|
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|
12234 %} |
|
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|
12235 |
| 0 | 12236 // ============================================================================ |
| 12237 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary | |
| 12238 // superklass array for an instance of the superklass. Set a hidden | |
| 12239 // internal cache on a hit (cache is checked with exposed code in | |
| 12240 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The | |
| 12241 // encoding ALSO sets flags. | |
| 12242 | |
| 12243 instruct partialSubtypeCheck(rdi_RegP result, | |
| 12244 rsi_RegP sub, rax_RegP super, rcx_RegI rcx, | |
| 12245 rFlagsReg cr) | |
| 12246 %{ | |
| 12247 match(Set result (PartialSubtypeCheck sub super)); | |
| 12248 effect(KILL rcx, KILL cr); | |
| 12249 | |
| 12250 ins_cost(1100); // slightly larger than the next version | |
|
644
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|
12251 format %{ "movq rdi, [$sub + (sizeof(oopDesc) + Klass::secondary_supers_offset_in_bytes())]\n\t" |
| 0 | 12252 "movl rcx, [rdi + arrayOopDesc::length_offset_in_bytes()]\t# length to scan\n\t" |
| 12253 "addq rdi, arrayOopDex::base_offset_in_bytes(T_OBJECT)\t# Skip to start of data; set NZ in case count is zero\n\t" | |
| 12254 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t" | |
| 12255 "jne,s miss\t\t# Missed: rdi not-zero\n\t" | |
| 12256 "movq [$sub + (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes())], $super\t# Hit: update cache\n\t" | |
| 12257 "xorq $result, $result\t\t Hit: rdi zero\n\t" | |
| 12258 "miss:\t" %} | |
| 12259 | |
| 12260 opcode(0x1); // Force a XOR of RDI | |
| 12261 ins_encode(enc_PartialSubtypeCheck()); | |
| 12262 ins_pipe(pipe_slow); | |
| 12263 %} | |
| 12264 | |
| 12265 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr, | |
| 12266 rsi_RegP sub, rax_RegP super, rcx_RegI rcx, | |
| 12267 immP0 zero, | |
| 12268 rdi_RegP result) | |
| 12269 %{ | |
| 12270 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero)); | |
| 12271 effect(KILL rcx, KILL result); | |
| 12272 | |
| 12273 ins_cost(1000); | |
|
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|
12274 format %{ "movq rdi, [$sub + (sizeof(oopDesc) + Klass::secondary_supers_offset_in_bytes())]\n\t" |
| 0 | 12275 "movl rcx, [rdi + arrayOopDesc::length_offset_in_bytes()]\t# length to scan\n\t" |
| 12276 "addq rdi, arrayOopDex::base_offset_in_bytes(T_OBJECT)\t# Skip to start of data; set NZ in case count is zero\n\t" | |
| 12277 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t" | |
| 12278 "jne,s miss\t\t# Missed: flags nz\n\t" | |
| 12279 "movq [$sub + (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes())], $super\t# Hit: update cache\n\t" | |
| 12280 "miss:\t" %} | |
| 12281 | |
| 12282 opcode(0x0); // No need to XOR RDI | |
| 12283 ins_encode(enc_PartialSubtypeCheck()); | |
| 12284 ins_pipe(pipe_slow); | |
| 12285 %} | |
| 12286 | |
| 12287 // ============================================================================ | |
| 12288 // Branch Instructions -- short offset versions | |
| 12289 // | |
| 12290 // These instructions are used to replace jumps of a long offset (the default | |
| 12291 // match) with jumps of a shorter offset. These instructions are all tagged | |
| 12292 // with the ins_short_branch attribute, which causes the ADLC to suppress the | |
| 12293 // match rules in general matching. Instead, the ADLC generates a conversion | |
| 12294 // method in the MachNode which can be used to do in-place replacement of the | |
| 12295 // long variant with the shorter variant. The compiler will determine if a | |
| 12296 // branch can be taken by the is_short_branch_offset() predicate in the machine | |
| 12297 // specific code section of the file. | |
| 12298 | |
| 12299 // Jump Direct - Label defines a relative address from JMP+1 | |
|
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|
12300 instruct jmpDir_short(label labl) %{ |
| 0 | 12301 match(Goto); |
| 12302 effect(USE labl); | |
| 12303 | |
| 12304 ins_cost(300); | |
| 12305 format %{ "jmp,s $labl" %} | |
| 12306 size(2); | |
| 12307 opcode(0xEB); | |
| 12308 ins_encode(OpcP, LblShort(labl)); | |
| 12309 ins_pipe(pipe_jmp); | |
| 12310 ins_pc_relative(1); | |
| 12311 ins_short_branch(1); | |
| 12312 %} | |
| 12313 | |
| 12314 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
|
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|
12315 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{ |
| 0 | 12316 match(If cop cr); |
| 12317 effect(USE labl); | |
| 12318 | |
| 12319 ins_cost(300); | |
| 12320 format %{ "j$cop,s $labl" %} | |
| 12321 size(2); | |
| 12322 opcode(0x70); | |
| 12323 ins_encode(JccShort(cop, labl)); | |
| 12324 ins_pipe(pipe_jcc); | |
| 12325 ins_pc_relative(1); | |
| 12326 ins_short_branch(1); | |
| 12327 %} | |
| 12328 | |
| 12329 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
|
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|
12330 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{ |
| 0 | 12331 match(CountedLoopEnd cop cr); |
| 12332 effect(USE labl); | |
| 12333 | |
| 12334 ins_cost(300); | |
|
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|
12335 format %{ "j$cop,s $labl\t# loop end" %} |
| 0 | 12336 size(2); |
| 12337 opcode(0x70); | |
| 12338 ins_encode(JccShort(cop, labl)); | |
| 12339 ins_pipe(pipe_jcc); | |
| 12340 ins_pc_relative(1); | |
| 12341 ins_short_branch(1); | |
| 12342 %} | |
| 12343 | |
| 12344 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
|
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|
12345 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
|
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|
12346 match(CountedLoopEnd cop cmp); |
|
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|
12347 effect(USE labl); |
|
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|
12348 |
|
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|
12349 ins_cost(300); |
|
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|
12350 format %{ "j$cop,us $labl\t# loop end" %} |
|
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|
12351 size(2); |
|
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|
12352 opcode(0x70); |
|
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|
12353 ins_encode(JccShort(cop, labl)); |
|
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|
12354 ins_pipe(pipe_jcc); |
|
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|
12355 ins_pc_relative(1); |
|
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|
12356 ins_short_branch(1); |
|
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|
12357 %} |
|
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changeset
|
12358 |
|
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|
12359 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
| 0 | 12360 match(CountedLoopEnd cop cmp); |
| 12361 effect(USE labl); | |
| 12362 | |
| 12363 ins_cost(300); | |
|
415
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|
12364 format %{ "j$cop,us $labl\t# loop end" %} |
|
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|
12365 size(2); |
|
4d9884b01ba6
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changeset
|
12366 opcode(0x70); |
|
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|
12367 ins_encode(JccShort(cop, labl)); |
|
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|
12368 ins_pipe(pipe_jcc); |
|
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|
12369 ins_pc_relative(1); |
|
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|
12370 ins_short_branch(1); |
|
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|
12371 %} |
|
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|
12372 |
|
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|
12373 // Jump Direct Conditional - using unsigned comparison |
|
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|
12374 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
|
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|
12375 match(If cop cmp); |
|
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|
12376 effect(USE labl); |
|
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|
12377 |
|
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|
12378 ins_cost(300); |
| 0 | 12379 format %{ "j$cop,us $labl" %} |
| 12380 size(2); | |
| 12381 opcode(0x70); | |
| 12382 ins_encode(JccShort(cop, labl)); | |
| 12383 ins_pipe(pipe_jcc); | |
| 12384 ins_pc_relative(1); | |
| 12385 ins_short_branch(1); | |
| 12386 %} | |
| 12387 | |
|
415
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|
12388 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
| 0 | 12389 match(If cop cmp); |
| 12390 effect(USE labl); | |
| 12391 | |
| 12392 ins_cost(300); | |
| 12393 format %{ "j$cop,us $labl" %} | |
| 12394 size(2); | |
| 12395 opcode(0x70); | |
| 12396 ins_encode(JccShort(cop, labl)); | |
| 12397 ins_pipe(pipe_jcc); | |
| 12398 ins_pc_relative(1); | |
| 12399 ins_short_branch(1); | |
| 12400 %} | |
| 12401 | |
|
415
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|
12402 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{ |
|
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|
12403 match(If cop cmp); |
|
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|
12404 effect(USE labl); |
|
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|
12405 |
|
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changeset
|
12406 ins_cost(300); |
|
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|
12407 format %{ $$template |
|
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|
12408 if ($cop$$cmpcode == Assembler::notEqual) { |
|
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|
12409 $$emit$$"jp,u,s $labl\n\t" |
|
4d9884b01ba6
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|
12410 $$emit$$"j$cop,u,s $labl" |
|
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|
12411 } else { |
|
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|
12412 $$emit$$"jp,u,s done\n\t" |
|
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|
12413 $$emit$$"j$cop,u,s $labl\n\t" |
|
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|
12414 $$emit$$"done:" |
|
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|
12415 } |
|
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|
12416 %} |
|
4d9884b01ba6
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|
12417 size(4); |
|
4d9884b01ba6
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|
12418 opcode(0x70); |
|
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|
12419 ins_encode %{ |
|
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|
12420 Label* l = $labl$$label; |
|
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12421 emit_cc(cbuf, $primary, Assembler::parity); |
|
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12422 int parity_disp = -1; |
|
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|
12423 if ($cop$$cmpcode == Assembler::notEqual) { |
| 1748 | 12424 parity_disp = l ? (l->loc_pos() - (cbuf.insts_size() + 1)) : 0; |
|
415
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12425 } else if ($cop$$cmpcode == Assembler::equal) { |
|
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|
12426 parity_disp = 2; |
|
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|
12427 } else { |
|
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|
12428 ShouldNotReachHere(); |
|
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|
12429 } |
|
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|
12430 emit_d8(cbuf, parity_disp); |
|
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|
12431 emit_cc(cbuf, $primary, $cop$$cmpcode); |
| 1748 | 12432 int disp = l ? (l->loc_pos() - (cbuf.insts_size() + 1)) : 0; |
|
415
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12433 emit_d8(cbuf, disp); |
|
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|
12434 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp"); |
|
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|
12435 assert(-128 <= parity_disp && parity_disp <= 127, "Displacement too large for short jmp"); |
|
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|
12436 %} |
|
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|
12437 ins_pipe(pipe_jcc); |
|
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|
12438 ins_pc_relative(1); |
|
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|
12439 ins_short_branch(1); |
|
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|
12440 %} |
|
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|
12441 |
| 0 | 12442 // ============================================================================ |
| 12443 // inlined locking and unlocking | |
| 12444 | |
| 12445 instruct cmpFastLock(rFlagsReg cr, | |
| 12446 rRegP object, rRegP box, rax_RegI tmp, rRegP scr) | |
| 12447 %{ | |
| 12448 match(Set cr (FastLock object box)); | |
| 12449 effect(TEMP tmp, TEMP scr); | |
| 12450 | |
| 12451 ins_cost(300); | |
| 12452 format %{ "fastlock $object,$box,$tmp,$scr" %} | |
| 12453 ins_encode(Fast_Lock(object, box, tmp, scr)); | |
| 12454 ins_pipe(pipe_slow); | |
| 12455 ins_pc_relative(1); | |
| 12456 %} | |
| 12457 | |
| 12458 instruct cmpFastUnlock(rFlagsReg cr, | |
| 12459 rRegP object, rax_RegP box, rRegP tmp) | |
| 12460 %{ | |
| 12461 match(Set cr (FastUnlock object box)); | |
| 12462 effect(TEMP tmp); | |
| 12463 | |
| 12464 ins_cost(300); | |
| 12465 format %{ "fastunlock $object, $box, $tmp" %} | |
| 12466 ins_encode(Fast_Unlock(object, box, tmp)); | |
| 12467 ins_pipe(pipe_slow); | |
| 12468 ins_pc_relative(1); | |
| 12469 %} | |
| 12470 | |
| 12471 | |
| 12472 // ============================================================================ | |
| 12473 // Safepoint Instructions | |
| 12474 instruct safePoint_poll(rFlagsReg cr) | |
| 12475 %{ | |
| 12476 match(SafePoint); | |
| 12477 effect(KILL cr); | |
| 12478 | |
| 12479 format %{ "testl rax, [rip + #offset_to_poll_page]\t" | |
| 12480 "# Safepoint: poll for GC" %} | |
| 12481 size(6); // Opcode + ModRM + Disp32 == 6 bytes | |
| 12482 ins_cost(125); | |
| 12483 ins_encode(enc_safepoint_poll); | |
| 12484 ins_pipe(ialu_reg_mem); | |
| 12485 %} | |
| 12486 | |
| 12487 // ============================================================================ | |
| 12488 // Procedure Call/Return Instructions | |
| 12489 // Call Java Static Instruction | |
| 12490 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 12491 // compute_padding() functions will have to be adjusted. | |
|
1137
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|
12492 instruct CallStaticJavaDirect(method meth) %{ |
| 0 | 12493 match(CallStaticJava); |
|
1137
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12494 predicate(!((CallStaticJavaNode*) n)->is_method_handle_invoke()); |
| 0 | 12495 effect(USE meth); |
| 12496 | |
| 12497 ins_cost(300); | |
| 12498 format %{ "call,static " %} | |
| 12499 opcode(0xE8); /* E8 cd */ | |
| 12500 ins_encode(Java_Static_Call(meth), call_epilog); | |
| 12501 ins_pipe(pipe_slow); | |
| 12502 ins_pc_relative(1); | |
| 12503 ins_alignment(4); | |
| 12504 %} | |
| 12505 | |
|
1137
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|
12506 // Call Java Static Instruction (method handle version) |
|
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|
12507 // Note: If this code changes, the corresponding ret_addr_offset() and |
|
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|
12508 // compute_padding() functions will have to be adjusted. |
| 1567 | 12509 instruct CallStaticJavaHandle(method meth, rbp_RegP rbp_mh_SP_save) %{ |
|
1137
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|
12510 match(CallStaticJava); |
|
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|
12511 predicate(((CallStaticJavaNode*) n)->is_method_handle_invoke()); |
|
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|
12512 effect(USE meth); |
|
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|
12513 // RBP is saved by all callees (for interpreter stack correction). |
|
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|
12514 // We use it here for a similar purpose, in {preserve,restore}_SP. |
|
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|
12515 |
|
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|
12516 ins_cost(300); |
|
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|
12517 format %{ "call,static/MethodHandle " %} |
|
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|
12518 opcode(0xE8); /* E8 cd */ |
|
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|
12519 ins_encode(preserve_SP, |
|
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|
12520 Java_Static_Call(meth), |
|
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|
12521 restore_SP, |
|
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|
12522 call_epilog); |
|
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|
12523 ins_pipe(pipe_slow); |
|
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|
12524 ins_pc_relative(1); |
|
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|
12525 ins_alignment(4); |
|
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|
12526 %} |
|
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|
12527 |
| 0 | 12528 // Call Java Dynamic Instruction |
| 12529 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 12530 // compute_padding() functions will have to be adjusted. | |
| 12531 instruct CallDynamicJavaDirect(method meth) | |
| 12532 %{ | |
| 12533 match(CallDynamicJava); | |
| 12534 effect(USE meth); | |
| 12535 | |
| 12536 ins_cost(300); | |
| 12537 format %{ "movq rax, #Universe::non_oop_word()\n\t" | |
| 12538 "call,dynamic " %} | |
| 12539 opcode(0xE8); /* E8 cd */ | |
| 12540 ins_encode(Java_Dynamic_Call(meth), call_epilog); | |
| 12541 ins_pipe(pipe_slow); | |
| 12542 ins_pc_relative(1); | |
| 12543 ins_alignment(4); | |
| 12544 %} | |
| 12545 | |
| 12546 // Call Runtime Instruction | |
| 12547 instruct CallRuntimeDirect(method meth) | |
| 12548 %{ | |
| 12549 match(CallRuntime); | |
| 12550 effect(USE meth); | |
| 12551 | |
| 12552 ins_cost(300); | |
| 12553 format %{ "call,runtime " %} | |
| 12554 opcode(0xE8); /* E8 cd */ | |
| 12555 ins_encode(Java_To_Runtime(meth)); | |
| 12556 ins_pipe(pipe_slow); | |
| 12557 ins_pc_relative(1); | |
| 12558 %} | |
| 12559 | |
| 12560 // Call runtime without safepoint | |
| 12561 instruct CallLeafDirect(method meth) | |
| 12562 %{ | |
| 12563 match(CallLeaf); | |
| 12564 effect(USE meth); | |
| 12565 | |
| 12566 ins_cost(300); | |
| 12567 format %{ "call_leaf,runtime " %} | |
| 12568 opcode(0xE8); /* E8 cd */ | |
| 12569 ins_encode(Java_To_Runtime(meth)); | |
| 12570 ins_pipe(pipe_slow); | |
| 12571 ins_pc_relative(1); | |
| 12572 %} | |
| 12573 | |
| 12574 // Call runtime without safepoint | |
| 12575 instruct CallLeafNoFPDirect(method meth) | |
| 12576 %{ | |
| 12577 match(CallLeafNoFP); | |
| 12578 effect(USE meth); | |
| 12579 | |
| 12580 ins_cost(300); | |
| 12581 format %{ "call_leaf_nofp,runtime " %} | |
| 12582 opcode(0xE8); /* E8 cd */ | |
| 12583 ins_encode(Java_To_Runtime(meth)); | |
| 12584 ins_pipe(pipe_slow); | |
| 12585 ins_pc_relative(1); | |
| 12586 %} | |
| 12587 | |
| 12588 // Return Instruction | |
| 12589 // Remove the return address & jump to it. | |
| 12590 // Notice: We always emit a nop after a ret to make sure there is room | |
| 12591 // for safepoint patching | |
| 12592 instruct Ret() | |
| 12593 %{ | |
| 12594 match(Return); | |
| 12595 | |
| 12596 format %{ "ret" %} | |
| 12597 opcode(0xC3); | |
| 12598 ins_encode(OpcP); | |
| 12599 ins_pipe(pipe_jmp); | |
| 12600 %} | |
| 12601 | |
| 12602 // Tail Call; Jump from runtime stub to Java code. | |
| 12603 // Also known as an 'interprocedural jump'. | |
| 12604 // Target of jump will eventually return to caller. | |
| 12605 // TailJump below removes the return address. | |
| 12606 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop) | |
| 12607 %{ | |
| 12608 match(TailCall jump_target method_oop); | |
| 12609 | |
| 12610 ins_cost(300); | |
| 12611 format %{ "jmp $jump_target\t# rbx holds method oop" %} | |
| 12612 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 12613 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target)); | |
| 12614 ins_pipe(pipe_jmp); | |
| 12615 %} | |
| 12616 | |
| 12617 // Tail Jump; remove the return address; jump to target. | |
| 12618 // TailCall above leaves the return address around. | |
| 12619 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop) | |
| 12620 %{ | |
| 12621 match(TailJump jump_target ex_oop); | |
| 12622 | |
| 12623 ins_cost(300); | |
| 12624 format %{ "popq rdx\t# pop return address\n\t" | |
| 12625 "jmp $jump_target" %} | |
| 12626 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 12627 ins_encode(Opcode(0x5a), // popq rdx | |
| 12628 REX_reg(jump_target), OpcP, reg_opc(jump_target)); | |
| 12629 ins_pipe(pipe_jmp); | |
| 12630 %} | |
| 12631 | |
| 12632 // Create exception oop: created by stack-crawling runtime code. | |
| 12633 // Created exception is now available to this handler, and is setup | |
| 12634 // just prior to jumping to this handler. No code emitted. | |
| 12635 instruct CreateException(rax_RegP ex_oop) | |
| 12636 %{ | |
| 12637 match(Set ex_oop (CreateEx)); | |
| 12638 | |
| 12639 size(0); | |
| 12640 // use the following format syntax | |
| 12641 format %{ "# exception oop is in rax; no code emitted" %} | |
| 12642 ins_encode(); | |
| 12643 ins_pipe(empty); | |
| 12644 %} | |
| 12645 | |
| 12646 // Rethrow exception: | |
| 12647 // The exception oop will come in the first argument position. | |
| 12648 // Then JUMP (not call) to the rethrow stub code. | |
| 12649 instruct RethrowException() | |
| 12650 %{ | |
| 12651 match(Rethrow); | |
| 12652 | |
| 12653 // use the following format syntax | |
| 12654 format %{ "jmp rethrow_stub" %} | |
| 12655 ins_encode(enc_rethrow); | |
| 12656 ins_pipe(pipe_jmp); | |
| 12657 %} | |
| 12658 | |
| 12659 | |
| 12660 //----------PEEPHOLE RULES----------------------------------------------------- | |
| 12661 // These must follow all instruction definitions as they use the names | |
| 12662 // defined in the instructions definitions. | |
| 12663 // | |
| 605 | 12664 // peepmatch ( root_instr_name [preceding_instruction]* ); |
| 0 | 12665 // |
| 12666 // peepconstraint %{ | |
| 12667 // (instruction_number.operand_name relational_op instruction_number.operand_name | |
| 12668 // [, ...] ); | |
| 12669 // // instruction numbers are zero-based using left to right order in peepmatch | |
| 12670 // | |
| 12671 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); | |
| 12672 // // provide an instruction_number.operand_name for each operand that appears | |
| 12673 // // in the replacement instruction's match rule | |
| 12674 // | |
| 12675 // ---------VM FLAGS--------------------------------------------------------- | |
| 12676 // | |
| 12677 // All peephole optimizations can be turned off using -XX:-OptoPeephole | |
| 12678 // | |
| 12679 // Each peephole rule is given an identifying number starting with zero and | |
| 12680 // increasing by one in the order seen by the parser. An individual peephole | |
| 12681 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# | |
| 12682 // on the command-line. | |
| 12683 // | |
| 12684 // ---------CURRENT LIMITATIONS---------------------------------------------- | |
| 12685 // | |
| 12686 // Only match adjacent instructions in same basic block | |
| 12687 // Only equality constraints | |
| 12688 // Only constraints between operands, not (0.dest_reg == RAX_enc) | |
| 12689 // Only one replacement instruction | |
| 12690 // | |
| 12691 // ---------EXAMPLE---------------------------------------------------------- | |
| 12692 // | |
| 12693 // // pertinent parts of existing instructions in architecture description | |
| 12694 // instruct movI(rRegI dst, rRegI src) | |
| 12695 // %{ | |
| 12696 // match(Set dst (CopyI src)); | |
| 12697 // %} | |
| 12698 // | |
| 12699 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr) | |
| 12700 // %{ | |
| 12701 // match(Set dst (AddI dst src)); | |
| 12702 // effect(KILL cr); | |
| 12703 // %} | |
| 12704 // | |
| 12705 // // Change (inc mov) to lea | |
| 12706 // peephole %{ | |
| 12707 // // increment preceeded by register-register move | |
| 12708 // peepmatch ( incI_rReg movI ); | |
| 12709 // // require that the destination register of the increment | |
| 12710 // // match the destination register of the move | |
| 12711 // peepconstraint ( 0.dst == 1.dst ); | |
| 12712 // // construct a replacement instruction that sets | |
| 12713 // // the destination to ( move's source register + one ) | |
| 12714 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) ); | |
| 12715 // %} | |
| 12716 // | |
| 12717 | |
| 12718 // Implementation no longer uses movX instructions since | |
| 12719 // machine-independent system no longer uses CopyX nodes. | |
| 12720 // | |
| 12721 // peephole | |
| 12722 // %{ | |
| 12723 // peepmatch (incI_rReg movI); | |
| 12724 // peepconstraint (0.dst == 1.dst); | |
| 12725 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src)); | |
| 12726 // %} | |
| 12727 | |
| 12728 // peephole | |
| 12729 // %{ | |
| 12730 // peepmatch (decI_rReg movI); | |
| 12731 // peepconstraint (0.dst == 1.dst); | |
| 12732 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src)); | |
| 12733 // %} | |
| 12734 | |
| 12735 // peephole | |
| 12736 // %{ | |
| 12737 // peepmatch (addI_rReg_imm movI); | |
| 12738 // peepconstraint (0.dst == 1.dst); | |
| 12739 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src)); | |
| 12740 // %} | |
| 12741 | |
| 12742 // peephole | |
| 12743 // %{ | |
| 12744 // peepmatch (incL_rReg movL); | |
| 12745 // peepconstraint (0.dst == 1.dst); | |
| 12746 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src)); | |
| 12747 // %} | |
| 12748 | |
| 12749 // peephole | |
| 12750 // %{ | |
| 12751 // peepmatch (decL_rReg movL); | |
| 12752 // peepconstraint (0.dst == 1.dst); | |
| 12753 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src)); | |
| 12754 // %} | |
| 12755 | |
| 12756 // peephole | |
| 12757 // %{ | |
| 12758 // peepmatch (addL_rReg_imm movL); | |
| 12759 // peepconstraint (0.dst == 1.dst); | |
| 12760 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src)); | |
| 12761 // %} | |
| 12762 | |
| 12763 // peephole | |
| 12764 // %{ | |
| 12765 // peepmatch (addP_rReg_imm movP); | |
| 12766 // peepconstraint (0.dst == 1.dst); | |
| 12767 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src)); | |
| 12768 // %} | |
| 12769 | |
| 12770 // // Change load of spilled value to only a spill | |
| 12771 // instruct storeI(memory mem, rRegI src) | |
| 12772 // %{ | |
| 12773 // match(Set mem (StoreI mem src)); | |
| 12774 // %} | |
| 12775 // | |
| 12776 // instruct loadI(rRegI dst, memory mem) | |
| 12777 // %{ | |
| 12778 // match(Set dst (LoadI mem)); | |
| 12779 // %} | |
| 12780 // | |
| 12781 | |
| 12782 peephole | |
| 12783 %{ | |
| 12784 peepmatch (loadI storeI); | |
| 12785 peepconstraint (1.src == 0.dst, 1.mem == 0.mem); | |
| 12786 peepreplace (storeI(1.mem 1.mem 1.src)); | |
| 12787 %} | |
| 12788 | |
| 12789 peephole | |
| 12790 %{ | |
| 12791 peepmatch (loadL storeL); | |
| 12792 peepconstraint (1.src == 0.dst, 1.mem == 0.mem); | |
| 12793 peepreplace (storeL(1.mem 1.mem 1.src)); | |
| 12794 %} | |
| 12795 | |
| 12796 //----------SMARTSPILL RULES--------------------------------------------------- | |
| 12797 // These must follow all instruction definitions as they use the names | |
| 12798 // defined in the instructions definitions. |