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diff src/cpu/x86/vm/x86_64.ad @ 2401:7e88bdae86ec

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7029017: Additional architecture support for c2 compiler Summary: Enables cross building of a c2 VM. Support masking of shift counts when the processor architecture mandates it. Reviewed-by: kvn, never
author roland
date Fri, 25 Mar 2011 09:35:39 +0100
parents 41d4973cf100
children b40d4fa697bf
line wrap: on
line diff
--- a/src/cpu/x86/vm/x86_64.ad	Fri Mar 25 18:19:22 2011 -0400
+++ b/src/cpu/x86/vm/x86_64.ad	Fri Mar 25 09:35:39 2011 +0100
@@ -2000,6 +2000,10 @@
 // into registers?  True for Intel but false for most RISCs
 const bool Matcher::clone_shift_expressions = true;
 
+// Do we need to mask the count passed to shift instructions or does
+// the cpu only look at the lower 5/6 bits anyway?
+const bool Matcher::need_masked_shift_count = false;
+
 bool Matcher::narrow_oop_use_complex_address() {
   assert(UseCompressedOops, "only for compressed oops code");
   return (LogMinObjAlignmentInBytes <= 3);