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7029017: Additional architecture support for c2 compiler Summary: Enables cross building of a c2 VM. Support masking of shift counts when the processor architecture mandates it. Reviewed-by: kvn, never
author roland
date Fri, 25 Mar 2011 09:35:39 +0100
parents 41d4973cf100
children b40d4fa697bf
comparison
equal deleted inserted replaced
2399:b2949bf39900 2401:7e88bdae86ec
1998 // Should the Matcher clone shifts on addressing modes, expecting them 1998 // Should the Matcher clone shifts on addressing modes, expecting them
1999 // to be subsumed into complex addressing expressions or compute them 1999 // to be subsumed into complex addressing expressions or compute them
2000 // into registers? True for Intel but false for most RISCs 2000 // into registers? True for Intel but false for most RISCs
2001 const bool Matcher::clone_shift_expressions = true; 2001 const bool Matcher::clone_shift_expressions = true;
2002 2002
2003 // Do we need to mask the count passed to shift instructions or does
2004 // the cpu only look at the lower 5/6 bits anyway?
2005 const bool Matcher::need_masked_shift_count = false;
2006
2003 bool Matcher::narrow_oop_use_complex_address() { 2007 bool Matcher::narrow_oop_use_complex_address() {
2004 assert(UseCompressedOops, "only for compressed oops code"); 2008 assert(UseCompressedOops, "only for compressed oops code");
2005 return (LogMinObjAlignmentInBytes <= 3); 2009 return (LogMinObjAlignmentInBytes <= 3);
2006 } 2010 }
2007 2011