Mercurial > hg > truffle
annotate src/cpu/x86/vm/x86_64.ad @ 624:337400e7a5dd
6797305: Add LoadUB and LoadUI opcode class
Summary: Add a LoadUB (unsigned byte) and LoadUI (unsigned int) opcode class so we have these load optimizations in the first place and do not need to handle them in the matcher.
Reviewed-by: never, kvn
| author | twisti |
|---|---|
| date | Mon, 09 Mar 2009 03:17:11 -0700 |
| parents | 56aae7be60d4 |
| children | 7bb995fbd3c0 660978a2a31a |
| rev | line source |
|---|---|
| 0 | 1 // |
| 624 | 2 // Copyright 2003-2009 Sun Microsystems, Inc. All Rights Reserved. |
| 0 | 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 // | |
| 5 // This code is free software; you can redistribute it and/or modify it | |
| 6 // under the terms of the GNU General Public License version 2 only, as | |
| 7 // published by the Free Software Foundation. | |
| 8 // | |
| 9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 // version 2 for more details (a copy is included in the LICENSE file that | |
| 13 // accompanied this code). | |
| 14 // | |
| 15 // You should have received a copy of the GNU General Public License version | |
| 16 // 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 // | |
| 19 // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 20 // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 21 // have any questions. | |
| 22 // | |
| 23 // | |
| 24 | |
| 25 // AMD64 Architecture Description File | |
| 26 | |
| 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ | |
| 28 // This information is used by the matcher and the register allocator to | |
| 29 // describe individual registers and classes of registers within the target | |
| 30 // archtecture. | |
| 31 | |
| 32 register %{ | |
| 33 //----------Architecture Description Register Definitions---------------------- | |
| 34 // General Registers | |
| 35 // "reg_def" name ( register save type, C convention save type, | |
| 36 // ideal register type, encoding ); | |
| 37 // Register Save Types: | |
| 38 // | |
| 39 // NS = No-Save: The register allocator assumes that these registers | |
| 40 // can be used without saving upon entry to the method, & | |
| 41 // that they do not need to be saved at call sites. | |
| 42 // | |
| 43 // SOC = Save-On-Call: The register allocator assumes that these registers | |
| 44 // can be used without saving upon entry to the method, | |
| 45 // but that they must be saved at call sites. | |
| 46 // | |
| 47 // SOE = Save-On-Entry: The register allocator assumes that these registers | |
| 48 // must be saved before using them upon entry to the | |
| 49 // method, but they do not need to be saved at call | |
| 50 // sites. | |
| 51 // | |
| 52 // AS = Always-Save: The register allocator assumes that these registers | |
| 53 // must be saved before using them upon entry to the | |
| 54 // method, & that they must be saved at call sites. | |
| 55 // | |
| 56 // Ideal Register Type is used to determine how to save & restore a | |
| 57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get | |
| 58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. | |
| 59 // | |
| 60 // The encoding number is the actual bit-pattern placed into the opcodes. | |
| 61 | |
| 62 // General Registers | |
| 63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when | |
| 64 // used as byte registers) | |
| 65 | |
| 66 // Previously set RBX, RSI, and RDI as save-on-entry for java code | |
| 67 // Turn off SOE in java-code due to frequent use of uncommon-traps. | |
| 68 // Now that allocator is better, turn on RSI and RDI as SOE registers. | |
| 69 | |
| 70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg()); | |
| 71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next()); | |
| 72 | |
| 73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg()); | |
| 74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next()); | |
| 75 | |
| 76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg()); | |
| 77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next()); | |
| 78 | |
| 79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg()); | |
| 80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next()); | |
| 81 | |
| 82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg()); | |
| 83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next()); | |
| 84 | |
| 85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code | |
| 86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg()); | |
| 87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next()); | |
| 88 | |
| 89 #ifdef _WIN64 | |
| 90 | |
| 91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg()); | |
| 92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next()); | |
| 93 | |
| 94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg()); | |
| 95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next()); | |
| 96 | |
| 97 #else | |
| 98 | |
| 99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg()); | |
| 100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next()); | |
| 101 | |
| 102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg()); | |
| 103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next()); | |
| 104 | |
| 105 #endif | |
| 106 | |
| 107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg()); | |
| 108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next()); | |
| 109 | |
| 110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg()); | |
| 111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next()); | |
| 112 | |
| 113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg()); | |
| 114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next()); | |
| 115 | |
| 116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg()); | |
| 117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next()); | |
| 118 | |
| 119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg()); | |
| 120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next()); | |
| 121 | |
| 122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg()); | |
| 123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next()); | |
| 124 | |
| 125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg()); | |
| 126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next()); | |
| 127 | |
| 128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg()); | |
| 129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next()); | |
| 130 | |
| 131 | |
| 132 // Floating Point Registers | |
| 133 | |
| 134 // XMM registers. 128-bit registers or 4 words each, labeled (a)-d. | |
| 135 // Word a in each register holds a Float, words ab hold a Double. We | |
| 136 // currently do not use the SIMD capabilities, so registers cd are | |
| 137 // unused at the moment. | |
| 138 // XMM8-XMM15 must be encoded with REX. | |
| 139 // Linux ABI: No register preserved across function calls | |
| 140 // XMM0-XMM7 might hold parameters | |
| 141 // Windows ABI: XMM6-XMM15 preserved across function calls | |
| 142 // XMM0-XMM3 might hold parameters | |
| 143 | |
| 144 reg_def XMM0 (SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()); | |
| 145 reg_def XMM0_H (SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next()); | |
| 146 | |
| 147 reg_def XMM1 (SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()); | |
| 148 reg_def XMM1_H (SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next()); | |
| 149 | |
| 150 reg_def XMM2 (SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()); | |
| 151 reg_def XMM2_H (SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next()); | |
| 152 | |
| 153 reg_def XMM3 (SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()); | |
| 154 reg_def XMM3_H (SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next()); | |
| 155 | |
| 156 reg_def XMM4 (SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()); | |
| 157 reg_def XMM4_H (SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next()); | |
| 158 | |
| 159 reg_def XMM5 (SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()); | |
| 160 reg_def XMM5_H (SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next()); | |
| 161 | |
| 162 #ifdef _WIN64 | |
| 163 | |
| 164 reg_def XMM6 (SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()); | |
| 165 reg_def XMM6_H (SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next()); | |
| 166 | |
| 167 reg_def XMM7 (SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()); | |
| 168 reg_def XMM7_H (SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next()); | |
| 169 | |
| 170 reg_def XMM8 (SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()); | |
| 171 reg_def XMM8_H (SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next()); | |
| 172 | |
| 173 reg_def XMM9 (SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()); | |
| 174 reg_def XMM9_H (SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next()); | |
| 175 | |
| 176 reg_def XMM10 (SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()); | |
| 177 reg_def XMM10_H(SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next()); | |
| 178 | |
| 179 reg_def XMM11 (SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()); | |
| 180 reg_def XMM11_H(SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next()); | |
| 181 | |
| 182 reg_def XMM12 (SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()); | |
| 183 reg_def XMM12_H(SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next()); | |
| 184 | |
| 185 reg_def XMM13 (SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()); | |
| 186 reg_def XMM13_H(SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next()); | |
| 187 | |
| 188 reg_def XMM14 (SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()); | |
| 189 reg_def XMM14_H(SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next()); | |
| 190 | |
| 191 reg_def XMM15 (SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()); | |
| 192 reg_def XMM15_H(SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next()); | |
| 193 | |
| 194 #else | |
| 195 | |
| 196 reg_def XMM6 (SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()); | |
| 197 reg_def XMM6_H (SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next()); | |
| 198 | |
| 199 reg_def XMM7 (SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()); | |
| 200 reg_def XMM7_H (SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next()); | |
| 201 | |
| 202 reg_def XMM8 (SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()); | |
| 203 reg_def XMM8_H (SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next()); | |
| 204 | |
| 205 reg_def XMM9 (SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()); | |
| 206 reg_def XMM9_H (SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next()); | |
| 207 | |
| 208 reg_def XMM10 (SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()); | |
| 209 reg_def XMM10_H(SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next()); | |
| 210 | |
| 211 reg_def XMM11 (SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()); | |
| 212 reg_def XMM11_H(SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next()); | |
| 213 | |
| 214 reg_def XMM12 (SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()); | |
| 215 reg_def XMM12_H(SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next()); | |
| 216 | |
| 217 reg_def XMM13 (SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()); | |
| 218 reg_def XMM13_H(SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next()); | |
| 219 | |
| 220 reg_def XMM14 (SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()); | |
| 221 reg_def XMM14_H(SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next()); | |
| 222 | |
| 223 reg_def XMM15 (SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()); | |
| 224 reg_def XMM15_H(SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next()); | |
| 225 | |
| 226 #endif // _WIN64 | |
| 227 | |
| 228 reg_def RFLAGS(SOC, SOC, 0, 16, VMRegImpl::Bad()); | |
| 229 | |
| 230 // Specify priority of register selection within phases of register | |
| 231 // allocation. Highest priority is first. A useful heuristic is to | |
| 232 // give registers a low priority when they are required by machine | |
| 233 // instructions, like EAX and EDX on I486, and choose no-save registers | |
| 234 // before save-on-call, & save-on-call before save-on-entry. Registers | |
| 235 // which participate in fixed calling sequences should come last. | |
| 236 // Registers which are used as pairs must fall on an even boundary. | |
| 237 | |
| 238 alloc_class chunk0(R10, R10_H, | |
| 239 R11, R11_H, | |
| 240 R8, R8_H, | |
| 241 R9, R9_H, | |
| 242 R12, R12_H, | |
| 243 RCX, RCX_H, | |
| 244 RBX, RBX_H, | |
| 245 RDI, RDI_H, | |
| 246 RDX, RDX_H, | |
| 247 RSI, RSI_H, | |
| 248 RAX, RAX_H, | |
| 249 RBP, RBP_H, | |
| 250 R13, R13_H, | |
| 251 R14, R14_H, | |
| 252 R15, R15_H, | |
| 253 RSP, RSP_H); | |
| 254 | |
| 255 // XXX probably use 8-15 first on Linux | |
| 256 alloc_class chunk1(XMM0, XMM0_H, | |
| 257 XMM1, XMM1_H, | |
| 258 XMM2, XMM2_H, | |
| 259 XMM3, XMM3_H, | |
| 260 XMM4, XMM4_H, | |
| 261 XMM5, XMM5_H, | |
| 262 XMM6, XMM6_H, | |
| 263 XMM7, XMM7_H, | |
| 264 XMM8, XMM8_H, | |
| 265 XMM9, XMM9_H, | |
| 266 XMM10, XMM10_H, | |
| 267 XMM11, XMM11_H, | |
| 268 XMM12, XMM12_H, | |
| 269 XMM13, XMM13_H, | |
| 270 XMM14, XMM14_H, | |
| 271 XMM15, XMM15_H); | |
| 272 | |
| 273 alloc_class chunk2(RFLAGS); | |
| 274 | |
| 275 | |
| 276 //----------Architecture Description Register Classes-------------------------- | |
| 277 // Several register classes are automatically defined based upon information in | |
| 278 // this architecture description. | |
| 279 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ ) | |
| 280 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ ) | |
| 281 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ ) | |
| 282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) | |
| 283 // | |
| 284 | |
| 285 // Class for all pointer registers (including RSP) | |
| 286 reg_class any_reg(RAX, RAX_H, | |
| 287 RDX, RDX_H, | |
| 288 RBP, RBP_H, | |
| 289 RDI, RDI_H, | |
| 290 RSI, RSI_H, | |
| 291 RCX, RCX_H, | |
| 292 RBX, RBX_H, | |
| 293 RSP, RSP_H, | |
| 294 R8, R8_H, | |
| 295 R9, R9_H, | |
| 296 R10, R10_H, | |
| 297 R11, R11_H, | |
| 298 R12, R12_H, | |
| 299 R13, R13_H, | |
| 300 R14, R14_H, | |
| 301 R15, R15_H); | |
| 302 | |
| 303 // Class for all pointer registers except RSP | |
| 304 reg_class ptr_reg(RAX, RAX_H, | |
| 305 RDX, RDX_H, | |
| 306 RBP, RBP_H, | |
| 307 RDI, RDI_H, | |
| 308 RSI, RSI_H, | |
| 309 RCX, RCX_H, | |
| 310 RBX, RBX_H, | |
| 311 R8, R8_H, | |
| 312 R9, R9_H, | |
| 313 R10, R10_H, | |
| 314 R11, R11_H, | |
| 315 R13, R13_H, | |
| 316 R14, R14_H); | |
| 317 | |
| 318 // Class for all pointer registers except RAX and RSP | |
| 319 reg_class ptr_no_rax_reg(RDX, RDX_H, | |
| 320 RBP, RBP_H, | |
| 321 RDI, RDI_H, | |
| 322 RSI, RSI_H, | |
| 323 RCX, RCX_H, | |
| 324 RBX, RBX_H, | |
| 325 R8, R8_H, | |
| 326 R9, R9_H, | |
| 327 R10, R10_H, | |
| 328 R11, R11_H, | |
| 329 R12, R12_H, | |
| 330 R13, R13_H, | |
| 331 R14, R14_H); | |
| 332 | |
| 333 reg_class ptr_no_rbp_reg(RDX, RDX_H, | |
| 334 RAX, RAX_H, | |
| 335 RDI, RDI_H, | |
| 336 RSI, RSI_H, | |
| 337 RCX, RCX_H, | |
| 338 RBX, RBX_H, | |
| 339 R8, R8_H, | |
| 340 R9, R9_H, | |
| 341 R10, R10_H, | |
| 342 R11, R11_H, | |
| 343 R12, R12_H, | |
| 344 R13, R13_H, | |
| 345 R14, R14_H); | |
| 346 | |
| 347 // Class for all pointer registers except RAX, RBX and RSP | |
| 348 reg_class ptr_no_rax_rbx_reg(RDX, RDX_H, | |
| 349 RBP, RBP_H, | |
| 350 RDI, RDI_H, | |
| 351 RSI, RSI_H, | |
| 352 RCX, RCX_H, | |
| 353 R8, R8_H, | |
| 354 R9, R9_H, | |
| 355 R10, R10_H, | |
| 356 R11, R11_H, | |
| 357 R12, R12_H, | |
| 358 R13, R13_H, | |
| 359 R14, R14_H); | |
| 360 | |
| 361 // Singleton class for RAX pointer register | |
| 362 reg_class ptr_rax_reg(RAX, RAX_H); | |
| 363 | |
| 364 // Singleton class for RBX pointer register | |
| 365 reg_class ptr_rbx_reg(RBX, RBX_H); | |
| 366 | |
| 367 // Singleton class for RSI pointer register | |
| 368 reg_class ptr_rsi_reg(RSI, RSI_H); | |
| 369 | |
| 370 // Singleton class for RDI pointer register | |
| 371 reg_class ptr_rdi_reg(RDI, RDI_H); | |
| 372 | |
| 373 // Singleton class for RBP pointer register | |
| 374 reg_class ptr_rbp_reg(RBP, RBP_H); | |
| 375 | |
| 376 // Singleton class for stack pointer | |
| 377 reg_class ptr_rsp_reg(RSP, RSP_H); | |
| 378 | |
| 379 // Singleton class for TLS pointer | |
| 380 reg_class ptr_r15_reg(R15, R15_H); | |
| 381 | |
| 382 // Class for all long registers (except RSP) | |
| 383 reg_class long_reg(RAX, RAX_H, | |
| 384 RDX, RDX_H, | |
| 385 RBP, RBP_H, | |
| 386 RDI, RDI_H, | |
| 387 RSI, RSI_H, | |
| 388 RCX, RCX_H, | |
| 389 RBX, RBX_H, | |
| 390 R8, R8_H, | |
| 391 R9, R9_H, | |
| 392 R10, R10_H, | |
| 393 R11, R11_H, | |
| 394 R13, R13_H, | |
| 395 R14, R14_H); | |
| 396 | |
| 397 // Class for all long registers except RAX, RDX (and RSP) | |
| 398 reg_class long_no_rax_rdx_reg(RBP, RBP_H, | |
| 399 RDI, RDI_H, | |
| 400 RSI, RSI_H, | |
| 401 RCX, RCX_H, | |
| 402 RBX, RBX_H, | |
| 403 R8, R8_H, | |
| 404 R9, R9_H, | |
| 405 R10, R10_H, | |
| 406 R11, R11_H, | |
| 407 R13, R13_H, | |
| 408 R14, R14_H); | |
| 409 | |
| 410 // Class for all long registers except RCX (and RSP) | |
| 411 reg_class long_no_rcx_reg(RBP, RBP_H, | |
| 412 RDI, RDI_H, | |
| 413 RSI, RSI_H, | |
| 414 RAX, RAX_H, | |
| 415 RDX, RDX_H, | |
| 416 RBX, RBX_H, | |
| 417 R8, R8_H, | |
| 418 R9, R9_H, | |
| 419 R10, R10_H, | |
| 420 R11, R11_H, | |
| 421 R13, R13_H, | |
| 422 R14, R14_H); | |
| 423 | |
| 424 // Class for all long registers except RAX (and RSP) | |
| 425 reg_class long_no_rax_reg(RBP, RBP_H, | |
| 426 RDX, RDX_H, | |
| 427 RDI, RDI_H, | |
| 428 RSI, RSI_H, | |
| 429 RCX, RCX_H, | |
| 430 RBX, RBX_H, | |
| 431 R8, R8_H, | |
| 432 R9, R9_H, | |
| 433 R10, R10_H, | |
| 434 R11, R11_H, | |
| 435 R13, R13_H, | |
| 436 R14, R14_H); | |
| 437 | |
| 438 // Singleton class for RAX long register | |
| 439 reg_class long_rax_reg(RAX, RAX_H); | |
| 440 | |
| 441 // Singleton class for RCX long register | |
| 442 reg_class long_rcx_reg(RCX, RCX_H); | |
| 443 | |
| 444 // Singleton class for RDX long register | |
| 445 reg_class long_rdx_reg(RDX, RDX_H); | |
| 446 | |
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447 // Singleton class for R12 long register |
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ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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changeset
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448 reg_class long_r12_reg(R12, R12_H); |
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ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
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changeset
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449 |
| 0 | 450 // Class for all int registers (except RSP) |
| 451 reg_class int_reg(RAX, | |
| 452 RDX, | |
| 453 RBP, | |
| 454 RDI, | |
| 455 RSI, | |
| 456 RCX, | |
| 457 RBX, | |
| 458 R8, | |
| 459 R9, | |
| 460 R10, | |
| 461 R11, | |
| 462 R13, | |
| 463 R14); | |
| 464 | |
| 465 // Class for all int registers except RCX (and RSP) | |
| 466 reg_class int_no_rcx_reg(RAX, | |
| 467 RDX, | |
| 468 RBP, | |
| 469 RDI, | |
| 470 RSI, | |
| 471 RBX, | |
| 472 R8, | |
| 473 R9, | |
| 474 R10, | |
| 475 R11, | |
| 476 R13, | |
| 477 R14); | |
| 478 | |
| 479 // Class for all int registers except RAX, RDX (and RSP) | |
| 480 reg_class int_no_rax_rdx_reg(RBP, | |
| 304 | 481 RDI, |
| 0 | 482 RSI, |
| 483 RCX, | |
| 484 RBX, | |
| 485 R8, | |
| 486 R9, | |
| 487 R10, | |
| 488 R11, | |
| 489 R13, | |
| 490 R14); | |
| 491 | |
| 492 // Singleton class for RAX int register | |
| 493 reg_class int_rax_reg(RAX); | |
| 494 | |
| 495 // Singleton class for RBX int register | |
| 496 reg_class int_rbx_reg(RBX); | |
| 497 | |
| 498 // Singleton class for RCX int register | |
| 499 reg_class int_rcx_reg(RCX); | |
| 500 | |
| 501 // Singleton class for RCX int register | |
| 502 reg_class int_rdx_reg(RDX); | |
| 503 | |
| 504 // Singleton class for RCX int register | |
| 505 reg_class int_rdi_reg(RDI); | |
| 506 | |
| 507 // Singleton class for instruction pointer | |
| 508 // reg_class ip_reg(RIP); | |
| 509 | |
| 510 // Singleton class for condition codes | |
| 511 reg_class int_flags(RFLAGS); | |
| 512 | |
| 513 // Class for all float registers | |
| 514 reg_class float_reg(XMM0, | |
| 515 XMM1, | |
| 516 XMM2, | |
| 517 XMM3, | |
| 518 XMM4, | |
| 519 XMM5, | |
| 520 XMM6, | |
| 521 XMM7, | |
| 522 XMM8, | |
| 523 XMM9, | |
| 524 XMM10, | |
| 525 XMM11, | |
| 526 XMM12, | |
| 527 XMM13, | |
| 528 XMM14, | |
| 529 XMM15); | |
| 530 | |
| 531 // Class for all double registers | |
| 532 reg_class double_reg(XMM0, XMM0_H, | |
| 533 XMM1, XMM1_H, | |
| 534 XMM2, XMM2_H, | |
| 535 XMM3, XMM3_H, | |
| 536 XMM4, XMM4_H, | |
| 537 XMM5, XMM5_H, | |
| 538 XMM6, XMM6_H, | |
| 539 XMM7, XMM7_H, | |
| 540 XMM8, XMM8_H, | |
| 541 XMM9, XMM9_H, | |
| 542 XMM10, XMM10_H, | |
| 543 XMM11, XMM11_H, | |
| 544 XMM12, XMM12_H, | |
| 545 XMM13, XMM13_H, | |
| 546 XMM14, XMM14_H, | |
| 547 XMM15, XMM15_H); | |
| 548 %} | |
| 549 | |
| 550 | |
| 551 //----------SOURCE BLOCK------------------------------------------------------- | |
| 552 // This is a block of C++ code which provides values, functions, and | |
| 553 // definitions necessary in the rest of the architecture description | |
| 554 source %{ | |
| 304 | 555 #define RELOC_IMM64 Assembler::imm_operand |
| 0 | 556 #define RELOC_DISP32 Assembler::disp32_operand |
| 557 | |
| 558 #define __ _masm. | |
| 559 | |
| 560 // !!!!! Special hack to get all types of calls to specify the byte offset | |
| 561 // from the start of the call to the point where the return address | |
| 562 // will point. | |
| 563 int MachCallStaticJavaNode::ret_addr_offset() | |
| 564 { | |
| 565 return 5; // 5 bytes from start of call to where return address points | |
| 566 } | |
| 567 | |
| 568 int MachCallDynamicJavaNode::ret_addr_offset() | |
| 569 { | |
| 570 return 15; // 15 bytes from start of call to where return address points | |
| 571 } | |
| 572 | |
| 573 // In os_cpu .ad file | |
| 574 // int MachCallRuntimeNode::ret_addr_offset() | |
| 575 | |
| 576 // Indicate if the safepoint node needs the polling page as an input. | |
| 577 // Since amd64 does not have absolute addressing but RIP-relative | |
| 578 // addressing and the polling page is within 2G, it doesn't. | |
| 579 bool SafePointNode::needs_polling_address_input() | |
| 580 { | |
| 581 return false; | |
| 582 } | |
| 583 | |
| 584 // | |
| 585 // Compute padding required for nodes which need alignment | |
| 586 // | |
| 587 | |
| 588 // The address of the call instruction needs to be 4-byte aligned to | |
| 589 // ensure that it does not span a cache line so that it can be patched. | |
| 590 int CallStaticJavaDirectNode::compute_padding(int current_offset) const | |
| 591 { | |
| 592 current_offset += 1; // skip call opcode byte | |
| 593 return round_to(current_offset, alignment_required()) - current_offset; | |
| 594 } | |
| 595 | |
| 596 // The address of the call instruction needs to be 4-byte aligned to | |
| 597 // ensure that it does not span a cache line so that it can be patched. | |
| 598 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const | |
| 599 { | |
| 600 current_offset += 11; // skip movq instruction + call opcode byte | |
| 601 return round_to(current_offset, alignment_required()) - current_offset; | |
| 602 } | |
| 603 | |
| 604 #ifndef PRODUCT | |
| 605 void MachBreakpointNode::format(PhaseRegAlloc*, outputStream* st) const | |
| 606 { | |
| 607 st->print("INT3"); | |
| 608 } | |
| 609 #endif | |
| 610 | |
| 611 // EMIT_RM() | |
| 612 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) | |
| 613 { | |
| 614 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3); | |
| 615 *(cbuf.code_end()) = c; | |
| 616 cbuf.set_code_end(cbuf.code_end() + 1); | |
| 617 } | |
| 618 | |
| 619 // EMIT_CC() | |
| 620 void emit_cc(CodeBuffer &cbuf, int f1, int f2) | |
| 621 { | |
| 622 unsigned char c = (unsigned char) (f1 | f2); | |
| 623 *(cbuf.code_end()) = c; | |
| 624 cbuf.set_code_end(cbuf.code_end() + 1); | |
| 625 } | |
| 626 | |
| 627 // EMIT_OPCODE() | |
| 628 void emit_opcode(CodeBuffer &cbuf, int code) | |
| 629 { | |
| 630 *(cbuf.code_end()) = (unsigned char) code; | |
| 631 cbuf.set_code_end(cbuf.code_end() + 1); | |
| 632 } | |
| 633 | |
| 634 // EMIT_OPCODE() w/ relocation information | |
| 635 void emit_opcode(CodeBuffer &cbuf, | |
| 636 int code, relocInfo::relocType reloc, int offset, int format) | |
| 637 { | |
| 638 cbuf.relocate(cbuf.inst_mark() + offset, reloc, format); | |
| 639 emit_opcode(cbuf, code); | |
| 640 } | |
| 641 | |
| 642 // EMIT_D8() | |
| 643 void emit_d8(CodeBuffer &cbuf, int d8) | |
| 644 { | |
| 645 *(cbuf.code_end()) = (unsigned char) d8; | |
| 646 cbuf.set_code_end(cbuf.code_end() + 1); | |
| 647 } | |
| 648 | |
| 649 // EMIT_D16() | |
| 650 void emit_d16(CodeBuffer &cbuf, int d16) | |
| 651 { | |
| 652 *((short *)(cbuf.code_end())) = d16; | |
| 653 cbuf.set_code_end(cbuf.code_end() + 2); | |
| 654 } | |
| 655 | |
| 656 // EMIT_D32() | |
| 657 void emit_d32(CodeBuffer &cbuf, int d32) | |
| 658 { | |
| 659 *((int *)(cbuf.code_end())) = d32; | |
| 660 cbuf.set_code_end(cbuf.code_end() + 4); | |
| 661 } | |
| 662 | |
| 663 // EMIT_D64() | |
| 664 void emit_d64(CodeBuffer &cbuf, int64_t d64) | |
| 665 { | |
| 666 *((int64_t*) (cbuf.code_end())) = d64; | |
| 667 cbuf.set_code_end(cbuf.code_end() + 8); | |
| 668 } | |
| 669 | |
| 670 // emit 32 bit value and construct relocation entry from relocInfo::relocType | |
| 671 void emit_d32_reloc(CodeBuffer& cbuf, | |
| 672 int d32, | |
| 673 relocInfo::relocType reloc, | |
| 674 int format) | |
| 675 { | |
| 676 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc"); | |
| 677 cbuf.relocate(cbuf.inst_mark(), reloc, format); | |
| 678 | |
| 679 *((int*) (cbuf.code_end())) = d32; | |
| 680 cbuf.set_code_end(cbuf.code_end() + 4); | |
| 681 } | |
| 682 | |
| 683 // emit 32 bit value and construct relocation entry from RelocationHolder | |
| 684 void emit_d32_reloc(CodeBuffer& cbuf, | |
| 685 int d32, | |
| 686 RelocationHolder const& rspec, | |
| 687 int format) | |
| 688 { | |
| 689 #ifdef ASSERT | |
| 690 if (rspec.reloc()->type() == relocInfo::oop_type && | |
| 691 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) { | |
| 692 assert(oop((intptr_t)d32)->is_oop() && oop((intptr_t)d32)->is_perm(), "cannot embed non-perm oops in code"); | |
| 693 } | |
| 694 #endif | |
| 695 cbuf.relocate(cbuf.inst_mark(), rspec, format); | |
| 696 | |
| 697 *((int* )(cbuf.code_end())) = d32; | |
| 698 cbuf.set_code_end(cbuf.code_end() + 4); | |
| 699 } | |
| 700 | |
| 701 void emit_d32_reloc(CodeBuffer& cbuf, address addr) { | |
| 702 address next_ip = cbuf.code_end() + 4; | |
| 703 emit_d32_reloc(cbuf, (int) (addr - next_ip), | |
| 704 external_word_Relocation::spec(addr), | |
| 705 RELOC_DISP32); | |
| 706 } | |
| 707 | |
| 708 | |
| 709 // emit 64 bit value and construct relocation entry from relocInfo::relocType | |
| 710 void emit_d64_reloc(CodeBuffer& cbuf, | |
| 711 int64_t d64, | |
| 712 relocInfo::relocType reloc, | |
| 713 int format) | |
| 714 { | |
| 715 cbuf.relocate(cbuf.inst_mark(), reloc, format); | |
| 716 | |
| 717 *((int64_t*) (cbuf.code_end())) = d64; | |
| 718 cbuf.set_code_end(cbuf.code_end() + 8); | |
| 719 } | |
| 720 | |
| 721 // emit 64 bit value and construct relocation entry from RelocationHolder | |
| 722 void emit_d64_reloc(CodeBuffer& cbuf, | |
| 723 int64_t d64, | |
| 724 RelocationHolder const& rspec, | |
| 725 int format) | |
| 726 { | |
| 727 #ifdef ASSERT | |
| 728 if (rspec.reloc()->type() == relocInfo::oop_type && | |
| 729 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) { | |
| 730 assert(oop(d64)->is_oop() && oop(d64)->is_perm(), | |
| 731 "cannot embed non-perm oops in code"); | |
| 732 } | |
| 733 #endif | |
| 734 cbuf.relocate(cbuf.inst_mark(), rspec, format); | |
| 735 | |
| 736 *((int64_t*) (cbuf.code_end())) = d64; | |
| 737 cbuf.set_code_end(cbuf.code_end() + 8); | |
| 738 } | |
| 739 | |
| 740 // Access stack slot for load or store | |
| 741 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) | |
| 742 { | |
| 743 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src]) | |
| 744 if (-0x80 <= disp && disp < 0x80) { | |
| 745 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte | |
| 746 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte | |
| 747 emit_d8(cbuf, disp); // Displacement // R/M byte | |
| 748 } else { | |
| 749 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte | |
| 750 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte | |
| 751 emit_d32(cbuf, disp); // Displacement // R/M byte | |
| 752 } | |
| 753 } | |
| 754 | |
| 755 // rRegI ereg, memory mem) %{ // emit_reg_mem | |
| 756 void encode_RegMem(CodeBuffer &cbuf, | |
| 757 int reg, | |
| 758 int base, int index, int scale, int disp, bool disp_is_oop) | |
| 759 { | |
| 760 assert(!disp_is_oop, "cannot have disp"); | |
| 761 int regenc = reg & 7; | |
| 762 int baseenc = base & 7; | |
| 763 int indexenc = index & 7; | |
| 764 | |
| 765 // There is no index & no scale, use form without SIB byte | |
| 766 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) { | |
| 767 // If no displacement, mode is 0x0; unless base is [RBP] or [R13] | |
| 768 if (disp == 0 && base != RBP_enc && base != R13_enc) { | |
| 769 emit_rm(cbuf, 0x0, regenc, baseenc); // * | |
| 770 } else if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) { | |
| 771 // If 8-bit displacement, mode 0x1 | |
| 772 emit_rm(cbuf, 0x1, regenc, baseenc); // * | |
| 773 emit_d8(cbuf, disp); | |
| 774 } else { | |
| 775 // If 32-bit displacement | |
| 776 if (base == -1) { // Special flag for absolute address | |
| 777 emit_rm(cbuf, 0x0, regenc, 0x5); // * | |
| 778 if (disp_is_oop) { | |
| 779 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32); | |
| 780 } else { | |
| 781 emit_d32(cbuf, disp); | |
| 782 } | |
| 783 } else { | |
| 784 // Normal base + offset | |
| 785 emit_rm(cbuf, 0x2, regenc, baseenc); // * | |
| 786 if (disp_is_oop) { | |
| 787 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32); | |
| 788 } else { | |
| 789 emit_d32(cbuf, disp); | |
| 790 } | |
| 791 } | |
| 792 } | |
| 793 } else { | |
| 794 // Else, encode with the SIB byte | |
| 795 // If no displacement, mode is 0x0; unless base is [RBP] or [R13] | |
| 796 if (disp == 0 && base != RBP_enc && base != R13_enc) { | |
| 797 // If no displacement | |
| 798 emit_rm(cbuf, 0x0, regenc, 0x4); // * | |
| 799 emit_rm(cbuf, scale, indexenc, baseenc); | |
| 800 } else { | |
| 801 if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) { | |
| 802 // If 8-bit displacement, mode 0x1 | |
| 803 emit_rm(cbuf, 0x1, regenc, 0x4); // * | |
| 804 emit_rm(cbuf, scale, indexenc, baseenc); | |
| 805 emit_d8(cbuf, disp); | |
| 806 } else { | |
| 807 // If 32-bit displacement | |
| 808 if (base == 0x04 ) { | |
| 809 emit_rm(cbuf, 0x2, regenc, 0x4); | |
| 810 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid??? | |
| 811 } else { | |
| 812 emit_rm(cbuf, 0x2, regenc, 0x4); | |
| 813 emit_rm(cbuf, scale, indexenc, baseenc); // * | |
| 814 } | |
| 815 if (disp_is_oop) { | |
| 816 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32); | |
| 817 } else { | |
| 818 emit_d32(cbuf, disp); | |
| 819 } | |
| 820 } | |
| 821 } | |
| 822 } | |
| 823 } | |
| 824 | |
| 825 void encode_copy(CodeBuffer &cbuf, int dstenc, int srcenc) | |
| 826 { | |
| 827 if (dstenc != srcenc) { | |
| 828 if (dstenc < 8) { | |
| 829 if (srcenc >= 8) { | |
| 830 emit_opcode(cbuf, Assembler::REX_B); | |
| 831 srcenc -= 8; | |
| 832 } | |
| 833 } else { | |
| 834 if (srcenc < 8) { | |
| 835 emit_opcode(cbuf, Assembler::REX_R); | |
| 836 } else { | |
| 837 emit_opcode(cbuf, Assembler::REX_RB); | |
| 838 srcenc -= 8; | |
| 839 } | |
| 840 dstenc -= 8; | |
| 841 } | |
| 842 | |
| 843 emit_opcode(cbuf, 0x8B); | |
| 844 emit_rm(cbuf, 0x3, dstenc, srcenc); | |
| 845 } | |
| 846 } | |
| 847 | |
| 848 void encode_CopyXD( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) { | |
| 849 if( dst_encoding == src_encoding ) { | |
| 850 // reg-reg copy, use an empty encoding | |
| 851 } else { | |
| 852 MacroAssembler _masm(&cbuf); | |
| 853 | |
| 854 __ movdqa(as_XMMRegister(dst_encoding), as_XMMRegister(src_encoding)); | |
| 855 } | |
| 856 } | |
| 857 | |
| 858 | |
| 859 //============================================================================= | |
| 860 #ifndef PRODUCT | |
| 861 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const | |
| 862 { | |
| 863 Compile* C = ra_->C; | |
| 864 | |
| 865 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 866 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 867 // Remove wordSize for return adr already pushed | |
| 868 // and another for the RBP we are going to save | |
| 869 framesize -= 2*wordSize; | |
| 870 bool need_nop = true; | |
| 871 | |
| 872 // Calls to C2R adapters often do not accept exceptional returns. | |
| 873 // We require that their callers must bang for them. But be | |
| 874 // careful, because some VM calls (such as call site linkage) can | |
| 875 // use several kilobytes of stack. But the stack safety zone should | |
| 876 // account for that. See bugs 4446381, 4468289, 4497237. | |
| 877 if (C->need_stack_bang(framesize)) { | |
| 878 st->print_cr("# stack bang"); st->print("\t"); | |
| 879 need_nop = false; | |
| 880 } | |
| 881 st->print_cr("pushq rbp"); st->print("\t"); | |
| 882 | |
| 883 if (VerifyStackAtCalls) { | |
| 884 // Majik cookie to verify stack depth | |
| 885 st->print_cr("pushq 0xffffffffbadb100d" | |
| 886 "\t# Majik cookie for stack depth check"); | |
| 887 st->print("\t"); | |
| 888 framesize -= wordSize; // Remove 2 for cookie | |
| 889 need_nop = false; | |
| 890 } | |
| 891 | |
| 892 if (framesize) { | |
| 893 st->print("subq rsp, #%d\t# Create frame", framesize); | |
| 894 if (framesize < 0x80 && need_nop) { | |
| 895 st->print("\n\tnop\t# nop for patch_verified_entry"); | |
| 896 } | |
| 897 } | |
| 898 } | |
| 899 #endif | |
| 900 | |
| 901 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const | |
| 902 { | |
| 903 Compile* C = ra_->C; | |
| 904 | |
| 905 // WARNING: Initial instruction MUST be 5 bytes or longer so that | |
| 906 // NativeJump::patch_verified_entry will be able to patch out the entry | |
| 907 // code safely. The fldcw is ok at 6 bytes, the push to verify stack | |
| 908 // depth is ok at 5 bytes, the frame allocation can be either 3 or | |
| 909 // 6 bytes. So if we don't do the fldcw or the push then we must | |
| 910 // use the 6 byte frame allocation even if we have no frame. :-( | |
| 911 // If method sets FPU control word do it now | |
| 912 | |
| 913 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 914 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 915 // Remove wordSize for return adr already pushed | |
| 916 // and another for the RBP we are going to save | |
| 917 framesize -= 2*wordSize; | |
| 918 bool need_nop = true; | |
| 919 | |
| 920 // Calls to C2R adapters often do not accept exceptional returns. | |
| 921 // We require that their callers must bang for them. But be | |
| 922 // careful, because some VM calls (such as call site linkage) can | |
| 923 // use several kilobytes of stack. But the stack safety zone should | |
| 924 // account for that. See bugs 4446381, 4468289, 4497237. | |
| 925 if (C->need_stack_bang(framesize)) { | |
| 926 MacroAssembler masm(&cbuf); | |
| 927 masm.generate_stack_overflow_check(framesize); | |
| 928 need_nop = false; | |
| 929 } | |
| 930 | |
| 931 // We always push rbp so that on return to interpreter rbp will be | |
| 932 // restored correctly and we can correct the stack. | |
| 933 emit_opcode(cbuf, 0x50 | RBP_enc); | |
| 934 | |
| 935 if (VerifyStackAtCalls) { | |
| 936 // Majik cookie to verify stack depth | |
| 937 emit_opcode(cbuf, 0x68); // pushq (sign-extended) 0xbadb100d | |
| 938 emit_d32(cbuf, 0xbadb100d); | |
| 939 framesize -= wordSize; // Remove 2 for cookie | |
| 940 need_nop = false; | |
| 941 } | |
| 942 | |
| 943 if (framesize) { | |
| 944 emit_opcode(cbuf, Assembler::REX_W); | |
| 945 if (framesize < 0x80) { | |
| 946 emit_opcode(cbuf, 0x83); // sub SP,#framesize | |
| 947 emit_rm(cbuf, 0x3, 0x05, RSP_enc); | |
| 948 emit_d8(cbuf, framesize); | |
| 949 if (need_nop) { | |
| 950 emit_opcode(cbuf, 0x90); // nop | |
| 951 } | |
| 952 } else { | |
| 953 emit_opcode(cbuf, 0x81); // sub SP,#framesize | |
| 954 emit_rm(cbuf, 0x3, 0x05, RSP_enc); | |
| 955 emit_d32(cbuf, framesize); | |
| 956 } | |
| 957 } | |
| 958 | |
| 959 C->set_frame_complete(cbuf.code_end() - cbuf.code_begin()); | |
| 960 | |
| 961 #ifdef ASSERT | |
| 962 if (VerifyStackAtCalls) { | |
| 963 Label L; | |
| 964 MacroAssembler masm(&cbuf); | |
| 304 | 965 masm.push(rax); |
| 966 masm.mov(rax, rsp); | |
| 967 masm.andptr(rax, StackAlignmentInBytes-1); | |
| 968 masm.cmpptr(rax, StackAlignmentInBytes-wordSize); | |
| 969 masm.pop(rax); | |
| 0 | 970 masm.jcc(Assembler::equal, L); |
| 971 masm.stop("Stack is not properly aligned!"); | |
| 972 masm.bind(L); | |
| 973 } | |
| 974 #endif | |
| 975 } | |
| 976 | |
| 977 uint MachPrologNode::size(PhaseRegAlloc* ra_) const | |
| 978 { | |
| 979 return MachNode::size(ra_); // too many variables; just compute it | |
| 980 // the hard way | |
| 981 } | |
| 982 | |
| 983 int MachPrologNode::reloc() const | |
| 984 { | |
| 985 return 0; // a large enough number | |
| 986 } | |
| 987 | |
| 988 //============================================================================= | |
| 989 #ifndef PRODUCT | |
| 990 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const | |
| 991 { | |
| 992 Compile* C = ra_->C; | |
| 993 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 994 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 995 // Remove word for return adr already pushed | |
| 996 // and RBP | |
| 997 framesize -= 2*wordSize; | |
| 998 | |
| 999 if (framesize) { | |
| 1000 st->print_cr("addq\trsp, %d\t# Destroy frame", framesize); | |
| 1001 st->print("\t"); | |
| 1002 } | |
| 1003 | |
| 1004 st->print_cr("popq\trbp"); | |
| 1005 if (do_polling() && C->is_method_compilation()) { | |
| 1006 st->print_cr("\ttestl\trax, [rip + #offset_to_poll_page]\t" | |
| 1007 "# Safepoint: poll for GC"); | |
| 1008 st->print("\t"); | |
| 1009 } | |
| 1010 } | |
| 1011 #endif | |
| 1012 | |
| 1013 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const | |
| 1014 { | |
| 1015 Compile* C = ra_->C; | |
| 1016 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 1017 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 1018 // Remove word for return adr already pushed | |
| 1019 // and RBP | |
| 1020 framesize -= 2*wordSize; | |
| 1021 | |
| 1022 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here | |
| 1023 | |
| 1024 if (framesize) { | |
| 1025 emit_opcode(cbuf, Assembler::REX_W); | |
| 1026 if (framesize < 0x80) { | |
| 1027 emit_opcode(cbuf, 0x83); // addq rsp, #framesize | |
| 1028 emit_rm(cbuf, 0x3, 0x00, RSP_enc); | |
| 1029 emit_d8(cbuf, framesize); | |
| 1030 } else { | |
| 1031 emit_opcode(cbuf, 0x81); // addq rsp, #framesize | |
| 1032 emit_rm(cbuf, 0x3, 0x00, RSP_enc); | |
| 1033 emit_d32(cbuf, framesize); | |
| 1034 } | |
| 1035 } | |
| 1036 | |
| 1037 // popq rbp | |
| 1038 emit_opcode(cbuf, 0x58 | RBP_enc); | |
| 1039 | |
| 1040 if (do_polling() && C->is_method_compilation()) { | |
| 1041 // testl %rax, off(%rip) // Opcode + ModRM + Disp32 == 6 bytes | |
| 1042 // XXX reg_mem doesn't support RIP-relative addressing yet | |
| 1043 cbuf.set_inst_mark(); | |
| 1044 cbuf.relocate(cbuf.inst_mark(), relocInfo::poll_return_type, 0); // XXX | |
| 1045 emit_opcode(cbuf, 0x85); // testl | |
| 1046 emit_rm(cbuf, 0x0, RAX_enc, 0x5); // 00 rax 101 == 0x5 | |
| 1047 // cbuf.inst_mark() is beginning of instruction | |
| 1048 emit_d32_reloc(cbuf, os::get_polling_page()); | |
| 1049 // relocInfo::poll_return_type, | |
| 1050 } | |
| 1051 } | |
| 1052 | |
| 1053 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const | |
| 1054 { | |
| 1055 Compile* C = ra_->C; | |
| 1056 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 1057 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 1058 // Remove word for return adr already pushed | |
| 1059 // and RBP | |
| 1060 framesize -= 2*wordSize; | |
| 1061 | |
| 1062 uint size = 0; | |
| 1063 | |
| 1064 if (do_polling() && C->is_method_compilation()) { | |
| 1065 size += 6; | |
| 1066 } | |
| 1067 | |
| 1068 // count popq rbp | |
| 1069 size++; | |
| 1070 | |
| 1071 if (framesize) { | |
| 1072 if (framesize < 0x80) { | |
| 1073 size += 4; | |
| 1074 } else if (framesize) { | |
| 1075 size += 7; | |
| 1076 } | |
| 1077 } | |
| 1078 | |
| 1079 return size; | |
| 1080 } | |
| 1081 | |
| 1082 int MachEpilogNode::reloc() const | |
| 1083 { | |
| 1084 return 2; // a large enough number | |
| 1085 } | |
| 1086 | |
| 1087 const Pipeline* MachEpilogNode::pipeline() const | |
| 1088 { | |
| 1089 return MachNode::pipeline_class(); | |
| 1090 } | |
| 1091 | |
| 1092 int MachEpilogNode::safepoint_offset() const | |
| 1093 { | |
| 1094 return 0; | |
| 1095 } | |
| 1096 | |
| 1097 //============================================================================= | |
| 1098 | |
| 1099 enum RC { | |
| 1100 rc_bad, | |
| 1101 rc_int, | |
| 1102 rc_float, | |
| 1103 rc_stack | |
| 1104 }; | |
| 1105 | |
| 1106 static enum RC rc_class(OptoReg::Name reg) | |
| 1107 { | |
| 1108 if( !OptoReg::is_valid(reg) ) return rc_bad; | |
| 1109 | |
| 1110 if (OptoReg::is_stack(reg)) return rc_stack; | |
| 1111 | |
| 1112 VMReg r = OptoReg::as_VMReg(reg); | |
| 1113 | |
| 1114 if (r->is_Register()) return rc_int; | |
| 1115 | |
| 1116 assert(r->is_XMMRegister(), "must be"); | |
| 1117 return rc_float; | |
| 1118 } | |
| 1119 | |
| 1120 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf, | |
| 1121 PhaseRegAlloc* ra_, | |
| 1122 bool do_size, | |
| 1123 outputStream* st) const | |
| 1124 { | |
| 1125 | |
| 1126 // Get registers to move | |
| 1127 OptoReg::Name src_second = ra_->get_reg_second(in(1)); | |
| 1128 OptoReg::Name src_first = ra_->get_reg_first(in(1)); | |
| 1129 OptoReg::Name dst_second = ra_->get_reg_second(this); | |
| 1130 OptoReg::Name dst_first = ra_->get_reg_first(this); | |
| 1131 | |
| 1132 enum RC src_second_rc = rc_class(src_second); | |
| 1133 enum RC src_first_rc = rc_class(src_first); | |
| 1134 enum RC dst_second_rc = rc_class(dst_second); | |
| 1135 enum RC dst_first_rc = rc_class(dst_first); | |
| 1136 | |
| 1137 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), | |
| 1138 "must move at least 1 register" ); | |
| 1139 | |
| 1140 if (src_first == dst_first && src_second == dst_second) { | |
| 1141 // Self copy, no move | |
| 1142 return 0; | |
| 1143 } else if (src_first_rc == rc_stack) { | |
| 1144 // mem -> | |
| 1145 if (dst_first_rc == rc_stack) { | |
| 1146 // mem -> mem | |
| 1147 assert(src_second != dst_first, "overlap"); | |
| 1148 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1149 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1150 // 64-bit | |
| 1151 int src_offset = ra_->reg2offset(src_first); | |
| 1152 int dst_offset = ra_->reg2offset(dst_first); | |
| 1153 if (cbuf) { | |
| 1154 emit_opcode(*cbuf, 0xFF); | |
| 1155 encode_RegMem(*cbuf, RSI_enc, RSP_enc, 0x4, 0, src_offset, false); | |
| 1156 | |
| 1157 emit_opcode(*cbuf, 0x8F); | |
| 1158 encode_RegMem(*cbuf, RAX_enc, RSP_enc, 0x4, 0, dst_offset, false); | |
| 1159 | |
| 1160 #ifndef PRODUCT | |
| 1161 } else if (!do_size) { | |
| 1162 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t" | |
| 1163 "popq [rsp + #%d]", | |
| 1164 src_offset, | |
| 1165 dst_offset); | |
| 1166 #endif | |
| 1167 } | |
| 1168 return | |
| 1169 3 + ((src_offset == 0) ? 0 : (src_offset < 0x80 ? 1 : 4)) + | |
| 1170 3 + ((dst_offset == 0) ? 0 : (dst_offset < 0x80 ? 1 : 4)); | |
| 1171 } else { | |
| 1172 // 32-bit | |
| 1173 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1174 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1175 // No pushl/popl, so: | |
| 1176 int src_offset = ra_->reg2offset(src_first); | |
| 1177 int dst_offset = ra_->reg2offset(dst_first); | |
| 1178 if (cbuf) { | |
| 1179 emit_opcode(*cbuf, Assembler::REX_W); | |
| 1180 emit_opcode(*cbuf, 0x89); | |
| 1181 emit_opcode(*cbuf, 0x44); | |
| 1182 emit_opcode(*cbuf, 0x24); | |
| 1183 emit_opcode(*cbuf, 0xF8); | |
| 1184 | |
| 1185 emit_opcode(*cbuf, 0x8B); | |
| 1186 encode_RegMem(*cbuf, | |
| 1187 RAX_enc, | |
| 1188 RSP_enc, 0x4, 0, src_offset, | |
| 1189 false); | |
| 1190 | |
| 1191 emit_opcode(*cbuf, 0x89); | |
| 1192 encode_RegMem(*cbuf, | |
| 1193 RAX_enc, | |
| 1194 RSP_enc, 0x4, 0, dst_offset, | |
| 1195 false); | |
| 1196 | |
| 1197 emit_opcode(*cbuf, Assembler::REX_W); | |
| 1198 emit_opcode(*cbuf, 0x8B); | |
| 1199 emit_opcode(*cbuf, 0x44); | |
| 1200 emit_opcode(*cbuf, 0x24); | |
| 1201 emit_opcode(*cbuf, 0xF8); | |
| 1202 | |
| 1203 #ifndef PRODUCT | |
| 1204 } else if (!do_size) { | |
| 1205 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t" | |
| 1206 "movl rax, [rsp + #%d]\n\t" | |
| 1207 "movl [rsp + #%d], rax\n\t" | |
| 1208 "movq rax, [rsp - #8]", | |
| 1209 src_offset, | |
| 1210 dst_offset); | |
| 1211 #endif | |
| 1212 } | |
| 1213 return | |
| 1214 5 + // movq | |
| 1215 3 + ((src_offset == 0) ? 0 : (src_offset < 0x80 ? 1 : 4)) + // movl | |
| 1216 3 + ((dst_offset == 0) ? 0 : (dst_offset < 0x80 ? 1 : 4)) + // movl | |
| 1217 5; // movq | |
| 1218 } | |
| 1219 } else if (dst_first_rc == rc_int) { | |
| 1220 // mem -> gpr | |
| 1221 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1222 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1223 // 64-bit | |
| 1224 int offset = ra_->reg2offset(src_first); | |
| 1225 if (cbuf) { | |
| 1226 if (Matcher::_regEncode[dst_first] < 8) { | |
| 1227 emit_opcode(*cbuf, Assembler::REX_W); | |
| 1228 } else { | |
| 1229 emit_opcode(*cbuf, Assembler::REX_WR); | |
| 1230 } | |
| 1231 emit_opcode(*cbuf, 0x8B); | |
| 1232 encode_RegMem(*cbuf, | |
| 1233 Matcher::_regEncode[dst_first], | |
| 1234 RSP_enc, 0x4, 0, offset, | |
| 1235 false); | |
| 1236 #ifndef PRODUCT | |
| 1237 } else if (!do_size) { | |
| 1238 st->print("movq %s, [rsp + #%d]\t# spill", | |
| 1239 Matcher::regName[dst_first], | |
| 1240 offset); | |
| 1241 #endif | |
| 1242 } | |
| 1243 return | |
| 1244 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + 4; // REX | |
| 1245 } else { | |
| 1246 // 32-bit | |
| 1247 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1248 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1249 int offset = ra_->reg2offset(src_first); | |
| 1250 if (cbuf) { | |
| 1251 if (Matcher::_regEncode[dst_first] >= 8) { | |
| 1252 emit_opcode(*cbuf, Assembler::REX_R); | |
| 1253 } | |
| 1254 emit_opcode(*cbuf, 0x8B); | |
| 1255 encode_RegMem(*cbuf, | |
| 1256 Matcher::_regEncode[dst_first], | |
| 1257 RSP_enc, 0x4, 0, offset, | |
| 1258 false); | |
| 1259 #ifndef PRODUCT | |
| 1260 } else if (!do_size) { | |
| 1261 st->print("movl %s, [rsp + #%d]\t# spill", | |
| 1262 Matcher::regName[dst_first], | |
| 1263 offset); | |
| 1264 #endif | |
| 1265 } | |
| 1266 return | |
| 1267 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + | |
| 1268 ((Matcher::_regEncode[dst_first] < 8) | |
| 1269 ? 3 | |
| 1270 : 4); // REX | |
| 1271 } | |
| 1272 } else if (dst_first_rc == rc_float) { | |
| 1273 // mem-> xmm | |
| 1274 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1275 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1276 // 64-bit | |
| 1277 int offset = ra_->reg2offset(src_first); | |
| 1278 if (cbuf) { | |
| 1279 emit_opcode(*cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66); | |
| 1280 if (Matcher::_regEncode[dst_first] >= 8) { | |
| 1281 emit_opcode(*cbuf, Assembler::REX_R); | |
| 1282 } | |
| 1283 emit_opcode(*cbuf, 0x0F); | |
| 1284 emit_opcode(*cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12); | |
| 1285 encode_RegMem(*cbuf, | |
| 1286 Matcher::_regEncode[dst_first], | |
| 1287 RSP_enc, 0x4, 0, offset, | |
| 1288 false); | |
| 1289 #ifndef PRODUCT | |
| 1290 } else if (!do_size) { | |
| 1291 st->print("%s %s, [rsp + #%d]\t# spill", | |
| 1292 UseXmmLoadAndClearUpper ? "movsd " : "movlpd", | |
| 1293 Matcher::regName[dst_first], | |
| 1294 offset); | |
| 1295 #endif | |
| 1296 } | |
| 1297 return | |
| 1298 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + | |
| 1299 ((Matcher::_regEncode[dst_first] < 8) | |
| 1300 ? 5 | |
| 1301 : 6); // REX | |
| 1302 } else { | |
| 1303 // 32-bit | |
| 1304 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1305 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1306 int offset = ra_->reg2offset(src_first); | |
| 1307 if (cbuf) { | |
| 1308 emit_opcode(*cbuf, 0xF3); | |
| 1309 if (Matcher::_regEncode[dst_first] >= 8) { | |
| 1310 emit_opcode(*cbuf, Assembler::REX_R); | |
| 1311 } | |
| 1312 emit_opcode(*cbuf, 0x0F); | |
| 1313 emit_opcode(*cbuf, 0x10); | |
| 1314 encode_RegMem(*cbuf, | |
| 1315 Matcher::_regEncode[dst_first], | |
| 1316 RSP_enc, 0x4, 0, offset, | |
| 1317 false); | |
| 1318 #ifndef PRODUCT | |
| 1319 } else if (!do_size) { | |
| 1320 st->print("movss %s, [rsp + #%d]\t# spill", | |
| 1321 Matcher::regName[dst_first], | |
| 1322 offset); | |
| 1323 #endif | |
| 1324 } | |
| 1325 return | |
| 1326 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + | |
| 1327 ((Matcher::_regEncode[dst_first] < 8) | |
| 1328 ? 5 | |
| 1329 : 6); // REX | |
| 1330 } | |
| 1331 } | |
| 1332 } else if (src_first_rc == rc_int) { | |
| 1333 // gpr -> | |
| 1334 if (dst_first_rc == rc_stack) { | |
| 1335 // gpr -> mem | |
| 1336 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1337 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1338 // 64-bit | |
| 1339 int offset = ra_->reg2offset(dst_first); | |
| 1340 if (cbuf) { | |
| 1341 if (Matcher::_regEncode[src_first] < 8) { | |
| 1342 emit_opcode(*cbuf, Assembler::REX_W); | |
| 1343 } else { | |
| 1344 emit_opcode(*cbuf, Assembler::REX_WR); | |
| 1345 } | |
| 1346 emit_opcode(*cbuf, 0x89); | |
| 1347 encode_RegMem(*cbuf, | |
| 1348 Matcher::_regEncode[src_first], | |
| 1349 RSP_enc, 0x4, 0, offset, | |
| 1350 false); | |
| 1351 #ifndef PRODUCT | |
| 1352 } else if (!do_size) { | |
| 1353 st->print("movq [rsp + #%d], %s\t# spill", | |
| 1354 offset, | |
| 1355 Matcher::regName[src_first]); | |
| 1356 #endif | |
| 1357 } | |
| 1358 return ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + 4; // REX | |
| 1359 } else { | |
| 1360 // 32-bit | |
| 1361 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1362 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1363 int offset = ra_->reg2offset(dst_first); | |
| 1364 if (cbuf) { | |
| 1365 if (Matcher::_regEncode[src_first] >= 8) { | |
| 1366 emit_opcode(*cbuf, Assembler::REX_R); | |
| 1367 } | |
| 1368 emit_opcode(*cbuf, 0x89); | |
| 1369 encode_RegMem(*cbuf, | |
| 1370 Matcher::_regEncode[src_first], | |
| 1371 RSP_enc, 0x4, 0, offset, | |
| 1372 false); | |
| 1373 #ifndef PRODUCT | |
| 1374 } else if (!do_size) { | |
| 1375 st->print("movl [rsp + #%d], %s\t# spill", | |
| 1376 offset, | |
| 1377 Matcher::regName[src_first]); | |
| 1378 #endif | |
| 1379 } | |
| 1380 return | |
| 1381 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + | |
| 1382 ((Matcher::_regEncode[src_first] < 8) | |
| 1383 ? 3 | |
| 1384 : 4); // REX | |
| 1385 } | |
| 1386 } else if (dst_first_rc == rc_int) { | |
| 1387 // gpr -> gpr | |
| 1388 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1389 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1390 // 64-bit | |
| 1391 if (cbuf) { | |
| 1392 if (Matcher::_regEncode[dst_first] < 8) { | |
| 1393 if (Matcher::_regEncode[src_first] < 8) { | |
| 1394 emit_opcode(*cbuf, Assembler::REX_W); | |
| 1395 } else { | |
| 1396 emit_opcode(*cbuf, Assembler::REX_WB); | |
| 1397 } | |
| 1398 } else { | |
| 1399 if (Matcher::_regEncode[src_first] < 8) { | |
| 1400 emit_opcode(*cbuf, Assembler::REX_WR); | |
| 1401 } else { | |
| 1402 emit_opcode(*cbuf, Assembler::REX_WRB); | |
| 1403 } | |
| 1404 } | |
| 1405 emit_opcode(*cbuf, 0x8B); | |
| 1406 emit_rm(*cbuf, 0x3, | |
| 1407 Matcher::_regEncode[dst_first] & 7, | |
| 1408 Matcher::_regEncode[src_first] & 7); | |
| 1409 #ifndef PRODUCT | |
| 1410 } else if (!do_size) { | |
| 1411 st->print("movq %s, %s\t# spill", | |
| 1412 Matcher::regName[dst_first], | |
| 1413 Matcher::regName[src_first]); | |
| 1414 #endif | |
| 1415 } | |
| 1416 return 3; // REX | |
| 1417 } else { | |
| 1418 // 32-bit | |
| 1419 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1420 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1421 if (cbuf) { | |
| 1422 if (Matcher::_regEncode[dst_first] < 8) { | |
| 1423 if (Matcher::_regEncode[src_first] >= 8) { | |
| 1424 emit_opcode(*cbuf, Assembler::REX_B); | |
| 1425 } | |
| 1426 } else { | |
| 1427 if (Matcher::_regEncode[src_first] < 8) { | |
| 1428 emit_opcode(*cbuf, Assembler::REX_R); | |
| 1429 } else { | |
| 1430 emit_opcode(*cbuf, Assembler::REX_RB); | |
| 1431 } | |
| 1432 } | |
| 1433 emit_opcode(*cbuf, 0x8B); | |
| 1434 emit_rm(*cbuf, 0x3, | |
| 1435 Matcher::_regEncode[dst_first] & 7, | |
| 1436 Matcher::_regEncode[src_first] & 7); | |
| 1437 #ifndef PRODUCT | |
| 1438 } else if (!do_size) { | |
| 1439 st->print("movl %s, %s\t# spill", | |
| 1440 Matcher::regName[dst_first], | |
| 1441 Matcher::regName[src_first]); | |
| 1442 #endif | |
| 1443 } | |
| 1444 return | |
| 1445 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8) | |
| 1446 ? 2 | |
| 1447 : 3; // REX | |
| 1448 } | |
| 1449 } else if (dst_first_rc == rc_float) { | |
| 1450 // gpr -> xmm | |
| 1451 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1452 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1453 // 64-bit | |
| 1454 if (cbuf) { | |
| 1455 emit_opcode(*cbuf, 0x66); | |
| 1456 if (Matcher::_regEncode[dst_first] < 8) { | |
| 1457 if (Matcher::_regEncode[src_first] < 8) { | |
| 1458 emit_opcode(*cbuf, Assembler::REX_W); | |
| 1459 } else { | |
| 1460 emit_opcode(*cbuf, Assembler::REX_WB); | |
| 1461 } | |
| 1462 } else { | |
| 1463 if (Matcher::_regEncode[src_first] < 8) { | |
| 1464 emit_opcode(*cbuf, Assembler::REX_WR); | |
| 1465 } else { | |
| 1466 emit_opcode(*cbuf, Assembler::REX_WRB); | |
| 1467 } | |
| 1468 } | |
| 1469 emit_opcode(*cbuf, 0x0F); | |
| 1470 emit_opcode(*cbuf, 0x6E); | |
| 1471 emit_rm(*cbuf, 0x3, | |
| 1472 Matcher::_regEncode[dst_first] & 7, | |
| 1473 Matcher::_regEncode[src_first] & 7); | |
| 1474 #ifndef PRODUCT | |
| 1475 } else if (!do_size) { | |
| 1476 st->print("movdq %s, %s\t# spill", | |
| 1477 Matcher::regName[dst_first], | |
| 1478 Matcher::regName[src_first]); | |
| 1479 #endif | |
| 1480 } | |
| 1481 return 5; // REX | |
| 1482 } else { | |
| 1483 // 32-bit | |
| 1484 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1485 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1486 if (cbuf) { | |
| 1487 emit_opcode(*cbuf, 0x66); | |
| 1488 if (Matcher::_regEncode[dst_first] < 8) { | |
| 1489 if (Matcher::_regEncode[src_first] >= 8) { | |
| 1490 emit_opcode(*cbuf, Assembler::REX_B); | |
| 1491 } | |
| 1492 } else { | |
| 1493 if (Matcher::_regEncode[src_first] < 8) { | |
| 1494 emit_opcode(*cbuf, Assembler::REX_R); | |
| 1495 } else { | |
| 1496 emit_opcode(*cbuf, Assembler::REX_RB); | |
| 1497 } | |
| 1498 } | |
| 1499 emit_opcode(*cbuf, 0x0F); | |
| 1500 emit_opcode(*cbuf, 0x6E); | |
| 1501 emit_rm(*cbuf, 0x3, | |
| 1502 Matcher::_regEncode[dst_first] & 7, | |
| 1503 Matcher::_regEncode[src_first] & 7); | |
| 1504 #ifndef PRODUCT | |
| 1505 } else if (!do_size) { | |
| 1506 st->print("movdl %s, %s\t# spill", | |
| 1507 Matcher::regName[dst_first], | |
| 1508 Matcher::regName[src_first]); | |
| 1509 #endif | |
| 1510 } | |
| 1511 return | |
| 1512 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8) | |
| 1513 ? 4 | |
| 1514 : 5; // REX | |
| 1515 } | |
| 1516 } | |
| 1517 } else if (src_first_rc == rc_float) { | |
| 1518 // xmm -> | |
| 1519 if (dst_first_rc == rc_stack) { | |
| 1520 // xmm -> mem | |
| 1521 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1522 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1523 // 64-bit | |
| 1524 int offset = ra_->reg2offset(dst_first); | |
| 1525 if (cbuf) { | |
| 1526 emit_opcode(*cbuf, 0xF2); | |
| 1527 if (Matcher::_regEncode[src_first] >= 8) { | |
| 1528 emit_opcode(*cbuf, Assembler::REX_R); | |
| 1529 } | |
| 1530 emit_opcode(*cbuf, 0x0F); | |
| 1531 emit_opcode(*cbuf, 0x11); | |
| 1532 encode_RegMem(*cbuf, | |
| 1533 Matcher::_regEncode[src_first], | |
| 1534 RSP_enc, 0x4, 0, offset, | |
| 1535 false); | |
| 1536 #ifndef PRODUCT | |
| 1537 } else if (!do_size) { | |
| 1538 st->print("movsd [rsp + #%d], %s\t# spill", | |
| 1539 offset, | |
| 1540 Matcher::regName[src_first]); | |
| 1541 #endif | |
| 1542 } | |
| 1543 return | |
| 1544 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + | |
| 1545 ((Matcher::_regEncode[src_first] < 8) | |
| 1546 ? 5 | |
| 1547 : 6); // REX | |
| 1548 } else { | |
| 1549 // 32-bit | |
| 1550 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1551 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1552 int offset = ra_->reg2offset(dst_first); | |
| 1553 if (cbuf) { | |
| 1554 emit_opcode(*cbuf, 0xF3); | |
| 1555 if (Matcher::_regEncode[src_first] >= 8) { | |
| 1556 emit_opcode(*cbuf, Assembler::REX_R); | |
| 1557 } | |
| 1558 emit_opcode(*cbuf, 0x0F); | |
| 1559 emit_opcode(*cbuf, 0x11); | |
| 1560 encode_RegMem(*cbuf, | |
| 1561 Matcher::_regEncode[src_first], | |
| 1562 RSP_enc, 0x4, 0, offset, | |
| 1563 false); | |
| 1564 #ifndef PRODUCT | |
| 1565 } else if (!do_size) { | |
| 1566 st->print("movss [rsp + #%d], %s\t# spill", | |
| 1567 offset, | |
| 1568 Matcher::regName[src_first]); | |
| 1569 #endif | |
| 1570 } | |
| 1571 return | |
| 1572 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + | |
| 1573 ((Matcher::_regEncode[src_first] < 8) | |
| 1574 ? 5 | |
| 1575 : 6); // REX | |
| 1576 } | |
| 1577 } else if (dst_first_rc == rc_int) { | |
| 1578 // xmm -> gpr | |
| 1579 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1580 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1581 // 64-bit | |
| 1582 if (cbuf) { | |
| 1583 emit_opcode(*cbuf, 0x66); | |
| 1584 if (Matcher::_regEncode[dst_first] < 8) { | |
| 1585 if (Matcher::_regEncode[src_first] < 8) { | |
| 1586 emit_opcode(*cbuf, Assembler::REX_W); | |
| 1587 } else { | |
| 1588 emit_opcode(*cbuf, Assembler::REX_WR); // attention! | |
| 1589 } | |
| 1590 } else { | |
| 1591 if (Matcher::_regEncode[src_first] < 8) { | |
| 1592 emit_opcode(*cbuf, Assembler::REX_WB); // attention! | |
| 1593 } else { | |
| 1594 emit_opcode(*cbuf, Assembler::REX_WRB); | |
| 1595 } | |
| 1596 } | |
| 1597 emit_opcode(*cbuf, 0x0F); | |
| 1598 emit_opcode(*cbuf, 0x7E); | |
| 1599 emit_rm(*cbuf, 0x3, | |
| 1600 Matcher::_regEncode[dst_first] & 7, | |
| 1601 Matcher::_regEncode[src_first] & 7); | |
| 1602 #ifndef PRODUCT | |
| 1603 } else if (!do_size) { | |
| 1604 st->print("movdq %s, %s\t# spill", | |
| 1605 Matcher::regName[dst_first], | |
| 1606 Matcher::regName[src_first]); | |
| 1607 #endif | |
| 1608 } | |
| 1609 return 5; // REX | |
| 1610 } else { | |
| 1611 // 32-bit | |
| 1612 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1613 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1614 if (cbuf) { | |
| 1615 emit_opcode(*cbuf, 0x66); | |
| 1616 if (Matcher::_regEncode[dst_first] < 8) { | |
| 1617 if (Matcher::_regEncode[src_first] >= 8) { | |
| 1618 emit_opcode(*cbuf, Assembler::REX_R); // attention! | |
| 1619 } | |
| 1620 } else { | |
| 1621 if (Matcher::_regEncode[src_first] < 8) { | |
| 1622 emit_opcode(*cbuf, Assembler::REX_B); // attention! | |
| 1623 } else { | |
| 1624 emit_opcode(*cbuf, Assembler::REX_RB); | |
| 1625 } | |
| 1626 } | |
| 1627 emit_opcode(*cbuf, 0x0F); | |
| 1628 emit_opcode(*cbuf, 0x7E); | |
| 1629 emit_rm(*cbuf, 0x3, | |
| 1630 Matcher::_regEncode[dst_first] & 7, | |
| 1631 Matcher::_regEncode[src_first] & 7); | |
| 1632 #ifndef PRODUCT | |
| 1633 } else if (!do_size) { | |
| 1634 st->print("movdl %s, %s\t# spill", | |
| 1635 Matcher::regName[dst_first], | |
| 1636 Matcher::regName[src_first]); | |
| 1637 #endif | |
| 1638 } | |
| 1639 return | |
| 1640 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8) | |
| 1641 ? 4 | |
| 1642 : 5; // REX | |
| 1643 } | |
| 1644 } else if (dst_first_rc == rc_float) { | |
| 1645 // xmm -> xmm | |
| 1646 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1647 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1648 // 64-bit | |
| 1649 if (cbuf) { | |
| 1650 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x66 : 0xF2); | |
| 1651 if (Matcher::_regEncode[dst_first] < 8) { | |
| 1652 if (Matcher::_regEncode[src_first] >= 8) { | |
| 1653 emit_opcode(*cbuf, Assembler::REX_B); | |
| 1654 } | |
| 1655 } else { | |
| 1656 if (Matcher::_regEncode[src_first] < 8) { | |
| 1657 emit_opcode(*cbuf, Assembler::REX_R); | |
| 1658 } else { | |
| 1659 emit_opcode(*cbuf, Assembler::REX_RB); | |
| 1660 } | |
| 1661 } | |
| 1662 emit_opcode(*cbuf, 0x0F); | |
| 1663 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10); | |
| 1664 emit_rm(*cbuf, 0x3, | |
| 1665 Matcher::_regEncode[dst_first] & 7, | |
| 1666 Matcher::_regEncode[src_first] & 7); | |
| 1667 #ifndef PRODUCT | |
| 1668 } else if (!do_size) { | |
| 1669 st->print("%s %s, %s\t# spill", | |
| 1670 UseXmmRegToRegMoveAll ? "movapd" : "movsd ", | |
| 1671 Matcher::regName[dst_first], | |
| 1672 Matcher::regName[src_first]); | |
| 1673 #endif | |
| 1674 } | |
| 1675 return | |
| 1676 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8) | |
| 1677 ? 4 | |
| 1678 : 5; // REX | |
| 1679 } else { | |
| 1680 // 32-bit | |
| 1681 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1682 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1683 if (cbuf) { | |
| 1684 if (!UseXmmRegToRegMoveAll) | |
| 1685 emit_opcode(*cbuf, 0xF3); | |
| 1686 if (Matcher::_regEncode[dst_first] < 8) { | |
| 1687 if (Matcher::_regEncode[src_first] >= 8) { | |
| 1688 emit_opcode(*cbuf, Assembler::REX_B); | |
| 1689 } | |
| 1690 } else { | |
| 1691 if (Matcher::_regEncode[src_first] < 8) { | |
| 1692 emit_opcode(*cbuf, Assembler::REX_R); | |
| 1693 } else { | |
| 1694 emit_opcode(*cbuf, Assembler::REX_RB); | |
| 1695 } | |
| 1696 } | |
| 1697 emit_opcode(*cbuf, 0x0F); | |
| 1698 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10); | |
| 1699 emit_rm(*cbuf, 0x3, | |
| 1700 Matcher::_regEncode[dst_first] & 7, | |
| 1701 Matcher::_regEncode[src_first] & 7); | |
| 1702 #ifndef PRODUCT | |
| 1703 } else if (!do_size) { | |
| 1704 st->print("%s %s, %s\t# spill", | |
| 1705 UseXmmRegToRegMoveAll ? "movaps" : "movss ", | |
| 1706 Matcher::regName[dst_first], | |
| 1707 Matcher::regName[src_first]); | |
| 1708 #endif | |
| 1709 } | |
| 1710 return | |
| 1711 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8) | |
| 1712 ? (UseXmmRegToRegMoveAll ? 3 : 4) | |
| 1713 : (UseXmmRegToRegMoveAll ? 4 : 5); // REX | |
| 1714 } | |
| 1715 } | |
| 1716 } | |
| 1717 | |
| 1718 assert(0," foo "); | |
| 1719 Unimplemented(); | |
| 1720 | |
| 1721 return 0; | |
| 1722 } | |
| 1723 | |
| 1724 #ifndef PRODUCT | |
| 1725 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const | |
| 1726 { | |
| 1727 implementation(NULL, ra_, false, st); | |
| 1728 } | |
| 1729 #endif | |
| 1730 | |
| 1731 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const | |
| 1732 { | |
| 1733 implementation(&cbuf, ra_, false, NULL); | |
| 1734 } | |
| 1735 | |
| 1736 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const | |
| 1737 { | |
| 1738 return implementation(NULL, ra_, true, NULL); | |
| 1739 } | |
| 1740 | |
| 1741 //============================================================================= | |
| 1742 #ifndef PRODUCT | |
| 1743 void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const | |
| 1744 { | |
| 1745 st->print("nop \t# %d bytes pad for loops and calls", _count); | |
| 1746 } | |
| 1747 #endif | |
| 1748 | |
| 1749 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const | |
| 1750 { | |
| 1751 MacroAssembler _masm(&cbuf); | |
| 1752 __ nop(_count); | |
| 1753 } | |
| 1754 | |
| 1755 uint MachNopNode::size(PhaseRegAlloc*) const | |
| 1756 { | |
| 1757 return _count; | |
| 1758 } | |
| 1759 | |
| 1760 | |
| 1761 //============================================================================= | |
| 1762 #ifndef PRODUCT | |
| 1763 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const | |
| 1764 { | |
| 1765 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1766 int reg = ra_->get_reg_first(this); | |
| 1767 st->print("leaq %s, [rsp + #%d]\t# box lock", | |
| 1768 Matcher::regName[reg], offset); | |
| 1769 } | |
| 1770 #endif | |
| 1771 | |
| 1772 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const | |
| 1773 { | |
| 1774 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1775 int reg = ra_->get_encode(this); | |
| 1776 if (offset >= 0x80) { | |
| 1777 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR); | |
| 1778 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1779 emit_rm(cbuf, 0x2, reg & 7, 0x04); | |
| 1780 emit_rm(cbuf, 0x0, 0x04, RSP_enc); | |
| 1781 emit_d32(cbuf, offset); | |
| 1782 } else { | |
| 1783 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR); | |
| 1784 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1785 emit_rm(cbuf, 0x1, reg & 7, 0x04); | |
| 1786 emit_rm(cbuf, 0x0, 0x04, RSP_enc); | |
| 1787 emit_d8(cbuf, offset); | |
| 1788 } | |
| 1789 } | |
| 1790 | |
| 1791 uint BoxLockNode::size(PhaseRegAlloc *ra_) const | |
| 1792 { | |
| 1793 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1794 return (offset < 0x80) ? 5 : 8; // REX | |
| 1795 } | |
| 1796 | |
| 1797 //============================================================================= | |
| 1798 | |
| 1799 // emit call stub, compiled java to interpreter | |
| 1800 void emit_java_to_interp(CodeBuffer& cbuf) | |
| 1801 { | |
| 1802 // Stub is fixed up when the corresponding call is converted from | |
| 1803 // calling compiled code to calling interpreted code. | |
| 1804 // movq rbx, 0 | |
| 1805 // jmp -5 # to self | |
| 1806 | |
| 1807 address mark = cbuf.inst_mark(); // get mark within main instrs section | |
| 1808 | |
| 1809 // Note that the code buffer's inst_mark is always relative to insts. | |
| 1810 // That's why we must use the macroassembler to generate a stub. | |
| 1811 MacroAssembler _masm(&cbuf); | |
| 1812 | |
| 1813 address base = | |
| 1814 __ start_a_stub(Compile::MAX_stubs_size); | |
| 1815 if (base == NULL) return; // CodeBuffer::expand failed | |
| 1816 // static stub relocation stores the instruction address of the call | |
| 1817 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM64); | |
| 1818 // static stub relocation also tags the methodOop in the code-stream. | |
| 1819 __ movoop(rbx, (jobject) NULL); // method is zapped till fixup time | |
| 304 | 1820 // This is recognized as unresolved by relocs/nativeinst/ic code |
| 0 | 1821 __ jump(RuntimeAddress(__ pc())); |
| 1822 | |
| 1823 // Update current stubs pointer and restore code_end. | |
| 1824 __ end_a_stub(); | |
| 1825 } | |
| 1826 | |
| 1827 // size of call stub, compiled java to interpretor | |
| 1828 uint size_java_to_interp() | |
| 1829 { | |
| 1830 return 15; // movq (1+1+8); jmp (1+4) | |
| 1831 } | |
| 1832 | |
| 1833 // relocation entries for call stub, compiled java to interpretor | |
| 1834 uint reloc_java_to_interp() | |
| 1835 { | |
| 1836 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call | |
| 1837 } | |
| 1838 | |
| 1839 //============================================================================= | |
| 1840 #ifndef PRODUCT | |
| 1841 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const | |
| 1842 { | |
|
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1843 if (UseCompressedOops) { |
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1844 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes() #%d]\t", oopDesc::klass_offset_in_bytes()); |
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1845 st->print_cr("leaq rscratch1, [r12_heapbase, r, Address::times_8, 0]"); |
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1846 st->print_cr("cmpq rax, rscratch1\t # Inline cache check"); |
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1847 } else { |
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1848 st->print_cr("cmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes() #%d]\t" |
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1849 "# Inline cache check", oopDesc::klass_offset_in_bytes()); |
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1850 } |
| 0 | 1851 st->print_cr("\tjne SharedRuntime::_ic_miss_stub"); |
| 1852 st->print_cr("\tnop"); | |
| 1853 if (!OptoBreakpoint) { | |
| 1854 st->print_cr("\tnop"); | |
| 1855 } | |
| 1856 } | |
| 1857 #endif | |
| 1858 | |
| 1859 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const | |
| 1860 { | |
| 1861 MacroAssembler masm(&cbuf); | |
| 1862 #ifdef ASSERT | |
| 1863 uint code_size = cbuf.code_size(); | |
| 1864 #endif | |
|
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1865 if (UseCompressedOops) { |
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1866 masm.load_klass(rscratch1, j_rarg0); |
| 304 | 1867 masm.cmpptr(rax, rscratch1); |
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1868 } else { |
| 304 | 1869 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes())); |
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1870 } |
| 0 | 1871 |
| 1872 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub())); | |
| 1873 | |
| 1874 /* WARNING these NOPs are critical so that verified entry point is properly | |
| 1875 aligned for patching by NativeJump::patch_verified_entry() */ | |
| 1876 int nops_cnt = 1; | |
| 1877 if (!OptoBreakpoint) { | |
| 1878 // Leave space for int3 | |
| 1879 nops_cnt += 1; | |
| 1880 } | |
|
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1881 if (UseCompressedOops) { |
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1882 // ??? divisible by 4 is aligned? |
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1883 nops_cnt += 1; |
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1884 } |
| 0 | 1885 masm.nop(nops_cnt); |
| 1886 | |
| 1887 assert(cbuf.code_size() - code_size == size(ra_), | |
| 1888 "checking code size of inline cache node"); | |
| 1889 } | |
| 1890 | |
| 1891 uint MachUEPNode::size(PhaseRegAlloc* ra_) const | |
| 1892 { | |
|
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1893 if (UseCompressedOops) { |
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1894 return OptoBreakpoint ? 19 : 20; |
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1895 } else { |
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1896 return OptoBreakpoint ? 11 : 12; |
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1897 } |
| 0 | 1898 } |
| 1899 | |
| 1900 | |
| 1901 //============================================================================= | |
| 1902 uint size_exception_handler() | |
| 1903 { | |
| 1904 // NativeCall instruction size is the same as NativeJump. | |
| 1905 // Note that this value is also credited (in output.cpp) to | |
| 1906 // the size of the code section. | |
| 1907 return NativeJump::instruction_size; | |
| 1908 } | |
| 1909 | |
| 1910 // Emit exception handler code. | |
| 1911 int emit_exception_handler(CodeBuffer& cbuf) | |
| 1912 { | |
| 1913 | |
| 1914 // Note that the code buffer's inst_mark is always relative to insts. | |
| 1915 // That's why we must use the macroassembler to generate a handler. | |
| 1916 MacroAssembler _masm(&cbuf); | |
| 1917 address base = | |
| 1918 __ start_a_stub(size_exception_handler()); | |
| 1919 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1920 int offset = __ offset(); | |
| 1921 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->instructions_begin())); | |
| 1922 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); | |
| 1923 __ end_a_stub(); | |
| 1924 return offset; | |
| 1925 } | |
| 1926 | |
| 1927 uint size_deopt_handler() | |
| 1928 { | |
| 1929 // three 5 byte instructions | |
| 1930 return 15; | |
| 1931 } | |
| 1932 | |
| 1933 // Emit deopt handler code. | |
| 1934 int emit_deopt_handler(CodeBuffer& cbuf) | |
| 1935 { | |
| 1936 | |
| 1937 // Note that the code buffer's inst_mark is always relative to insts. | |
| 1938 // That's why we must use the macroassembler to generate a handler. | |
| 1939 MacroAssembler _masm(&cbuf); | |
| 1940 address base = | |
| 1941 __ start_a_stub(size_deopt_handler()); | |
| 1942 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1943 int offset = __ offset(); | |
| 1944 address the_pc = (address) __ pc(); | |
| 1945 Label next; | |
| 1946 // push a "the_pc" on the stack without destroying any registers | |
| 1947 // as they all may be live. | |
| 1948 | |
| 1949 // push address of "next" | |
| 1950 __ call(next, relocInfo::none); // reloc none is fine since it is a disp32 | |
| 1951 __ bind(next); | |
| 1952 // adjust it so it matches "the_pc" | |
| 304 | 1953 __ subptr(Address(rsp, 0), __ offset() - offset); |
| 0 | 1954 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); |
| 1955 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); | |
| 1956 __ end_a_stub(); | |
| 1957 return offset; | |
| 1958 } | |
| 1959 | |
| 1960 static void emit_double_constant(CodeBuffer& cbuf, double x) { | |
| 1961 int mark = cbuf.insts()->mark_off(); | |
| 1962 MacroAssembler _masm(&cbuf); | |
| 1963 address double_address = __ double_constant(x); | |
| 1964 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift | |
| 1965 emit_d32_reloc(cbuf, | |
| 1966 (int) (double_address - cbuf.code_end() - 4), | |
| 1967 internal_word_Relocation::spec(double_address), | |
| 1968 RELOC_DISP32); | |
| 1969 } | |
| 1970 | |
| 1971 static void emit_float_constant(CodeBuffer& cbuf, float x) { | |
| 1972 int mark = cbuf.insts()->mark_off(); | |
| 1973 MacroAssembler _masm(&cbuf); | |
| 1974 address float_address = __ float_constant(x); | |
| 1975 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift | |
| 1976 emit_d32_reloc(cbuf, | |
| 1977 (int) (float_address - cbuf.code_end() - 4), | |
| 1978 internal_word_Relocation::spec(float_address), | |
| 1979 RELOC_DISP32); | |
| 1980 } | |
| 1981 | |
| 1982 | |
| 1983 int Matcher::regnum_to_fpu_offset(int regnum) | |
| 1984 { | |
| 1985 return regnum - 32; // The FP registers are in the second chunk | |
| 1986 } | |
| 1987 | |
| 1988 // This is UltraSparc specific, true just means we have fast l2f conversion | |
| 1989 const bool Matcher::convL2FSupported(void) { | |
| 1990 return true; | |
| 1991 } | |
| 1992 | |
| 1993 // Vector width in bytes | |
| 1994 const uint Matcher::vector_width_in_bytes(void) { | |
| 1995 return 8; | |
| 1996 } | |
| 1997 | |
| 1998 // Vector ideal reg | |
| 1999 const uint Matcher::vector_ideal_reg(void) { | |
| 2000 return Op_RegD; | |
| 2001 } | |
| 2002 | |
| 2003 // Is this branch offset short enough that a short branch can be used? | |
| 2004 // | |
| 2005 // NOTE: If the platform does not provide any short branch variants, then | |
| 2006 // this method should return false for offset 0. | |
|
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2007 bool Matcher::is_short_branch_offset(int rule, int offset) { |
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2008 // the short version of jmpConUCF2 contains multiple branches, |
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2009 // making the reach slightly less |
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2010 if (rule == jmpConUCF2_rule) |
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2011 return (-126 <= offset && offset <= 125); |
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2012 return (-128 <= offset && offset <= 127); |
| 0 | 2013 } |
| 2014 | |
| 2015 const bool Matcher::isSimpleConstant64(jlong value) { | |
| 2016 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. | |
| 2017 //return value == (int) value; // Cf. storeImmL and immL32. | |
| 2018 | |
| 2019 // Probably always true, even if a temp register is required. | |
| 2020 return true; | |
| 2021 } | |
| 2022 | |
| 2023 // The ecx parameter to rep stosq for the ClearArray node is in words. | |
| 2024 const bool Matcher::init_array_count_is_in_bytes = false; | |
| 2025 | |
| 2026 // Threshold size for cleararray. | |
| 2027 const int Matcher::init_array_short_size = 8 * BytesPerLong; | |
| 2028 | |
| 2029 // Should the Matcher clone shifts on addressing modes, expecting them | |
| 2030 // to be subsumed into complex addressing expressions or compute them | |
| 2031 // into registers? True for Intel but false for most RISCs | |
| 2032 const bool Matcher::clone_shift_expressions = true; | |
| 2033 | |
| 2034 // Is it better to copy float constants, or load them directly from | |
| 2035 // memory? Intel can load a float constant from a direct address, | |
| 2036 // requiring no extra registers. Most RISCs will have to materialize | |
| 2037 // an address into a register first, so they would do better to copy | |
| 2038 // the constant from stack. | |
| 2039 const bool Matcher::rematerialize_float_constants = true; // XXX | |
| 2040 | |
| 2041 // If CPU can load and store mis-aligned doubles directly then no | |
| 2042 // fixup is needed. Else we split the double into 2 integer pieces | |
| 2043 // and move it piece-by-piece. Only happens when passing doubles into | |
| 2044 // C code as the Java calling convention forces doubles to be aligned. | |
| 2045 const bool Matcher::misaligned_doubles_ok = true; | |
| 2046 | |
| 2047 // No-op on amd64 | |
| 2048 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {} | |
| 2049 | |
| 2050 // Advertise here if the CPU requires explicit rounding operations to | |
| 2051 // implement the UseStrictFP mode. | |
| 2052 const bool Matcher::strict_fp_requires_explicit_rounding = true; | |
| 2053 | |
| 2054 // Do floats take an entire double register or just half? | |
| 2055 const bool Matcher::float_in_double = true; | |
| 2056 // Do ints take an entire long register or just half? | |
| 2057 const bool Matcher::int_in_long = true; | |
| 2058 | |
| 2059 // Return whether or not this register is ever used as an argument. | |
| 2060 // This function is used on startup to build the trampoline stubs in | |
| 2061 // generateOptoStub. Registers not mentioned will be killed by the VM | |
| 2062 // call in the trampoline, and arguments in those registers not be | |
| 2063 // available to the callee. | |
| 2064 bool Matcher::can_be_java_arg(int reg) | |
| 2065 { | |
| 2066 return | |
| 2067 reg == RDI_num || reg == RDI_H_num || | |
| 2068 reg == RSI_num || reg == RSI_H_num || | |
| 2069 reg == RDX_num || reg == RDX_H_num || | |
| 2070 reg == RCX_num || reg == RCX_H_num || | |
| 2071 reg == R8_num || reg == R8_H_num || | |
| 2072 reg == R9_num || reg == R9_H_num || | |
|
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2073 reg == R12_num || reg == R12_H_num || |
| 0 | 2074 reg == XMM0_num || reg == XMM0_H_num || |
| 2075 reg == XMM1_num || reg == XMM1_H_num || | |
| 2076 reg == XMM2_num || reg == XMM2_H_num || | |
| 2077 reg == XMM3_num || reg == XMM3_H_num || | |
| 2078 reg == XMM4_num || reg == XMM4_H_num || | |
| 2079 reg == XMM5_num || reg == XMM5_H_num || | |
| 2080 reg == XMM6_num || reg == XMM6_H_num || | |
| 2081 reg == XMM7_num || reg == XMM7_H_num; | |
| 2082 } | |
| 2083 | |
| 2084 bool Matcher::is_spillable_arg(int reg) | |
| 2085 { | |
| 2086 return can_be_java_arg(reg); | |
| 2087 } | |
| 2088 | |
| 2089 // Register for DIVI projection of divmodI | |
| 2090 RegMask Matcher::divI_proj_mask() { | |
| 2091 return INT_RAX_REG_mask; | |
| 2092 } | |
| 2093 | |
| 2094 // Register for MODI projection of divmodI | |
| 2095 RegMask Matcher::modI_proj_mask() { | |
| 2096 return INT_RDX_REG_mask; | |
| 2097 } | |
| 2098 | |
| 2099 // Register for DIVL projection of divmodL | |
| 2100 RegMask Matcher::divL_proj_mask() { | |
| 2101 return LONG_RAX_REG_mask; | |
| 2102 } | |
| 2103 | |
| 2104 // Register for MODL projection of divmodL | |
| 2105 RegMask Matcher::modL_proj_mask() { | |
| 2106 return LONG_RDX_REG_mask; | |
| 2107 } | |
| 2108 | |
|
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2109 static Address build_address(int b, int i, int s, int d) { |
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2110 Register index = as_Register(i); |
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2111 Address::ScaleFactor scale = (Address::ScaleFactor)s; |
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2112 if (index == rsp) { |
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2113 index = noreg; |
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2114 scale = Address::no_scale; |
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2115 } |
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2116 Address addr(as_Register(b), index, scale, d); |
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2117 return addr; |
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2118 } |
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2119 |
| 0 | 2120 %} |
| 2121 | |
| 2122 //----------ENCODING BLOCK----------------------------------------------------- | |
| 2123 // This block specifies the encoding classes used by the compiler to | |
| 2124 // output byte streams. Encoding classes are parameterized macros | |
| 2125 // used by Machine Instruction Nodes in order to generate the bit | |
| 2126 // encoding of the instruction. Operands specify their base encoding | |
| 2127 // interface with the interface keyword. There are currently | |
| 2128 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, & | |
| 2129 // COND_INTER. REG_INTER causes an operand to generate a function | |
| 2130 // which returns its register number when queried. CONST_INTER causes | |
| 2131 // an operand to generate a function which returns the value of the | |
| 2132 // constant when queried. MEMORY_INTER causes an operand to generate | |
| 2133 // four functions which return the Base Register, the Index Register, | |
| 2134 // the Scale Value, and the Offset Value of the operand when queried. | |
| 2135 // COND_INTER causes an operand to generate six functions which return | |
| 2136 // the encoding code (ie - encoding bits for the instruction) | |
| 2137 // associated with each basic boolean condition for a conditional | |
| 2138 // instruction. | |
| 2139 // | |
| 2140 // Instructions specify two basic values for encoding. Again, a | |
| 2141 // function is available to check if the constant displacement is an | |
| 2142 // oop. They use the ins_encode keyword to specify their encoding | |
| 2143 // classes (which must be a sequence of enc_class names, and their | |
| 2144 // parameters, specified in the encoding block), and they use the | |
| 2145 // opcode keyword to specify, in order, their primary, secondary, and | |
| 2146 // tertiary opcode. Only the opcode sections which a particular | |
| 2147 // instruction needs for encoding need to be specified. | |
| 2148 encode %{ | |
| 2149 // Build emit functions for each basic byte or larger field in the | |
| 2150 // intel encoding scheme (opcode, rm, sib, immediate), and call them | |
| 2151 // from C++ code in the enc_class source block. Emit functions will | |
| 2152 // live in the main source block for now. In future, we can | |
| 2153 // generalize this by adding a syntax that specifies the sizes of | |
| 2154 // fields in an order, so that the adlc can build the emit functions | |
| 2155 // automagically | |
| 2156 | |
| 2157 // Emit primary opcode | |
| 2158 enc_class OpcP | |
| 2159 %{ | |
| 2160 emit_opcode(cbuf, $primary); | |
| 2161 %} | |
| 2162 | |
| 2163 // Emit secondary opcode | |
| 2164 enc_class OpcS | |
| 2165 %{ | |
| 2166 emit_opcode(cbuf, $secondary); | |
| 2167 %} | |
| 2168 | |
| 2169 // Emit tertiary opcode | |
| 2170 enc_class OpcT | |
| 2171 %{ | |
| 2172 emit_opcode(cbuf, $tertiary); | |
| 2173 %} | |
| 2174 | |
| 2175 // Emit opcode directly | |
| 2176 enc_class Opcode(immI d8) | |
| 2177 %{ | |
| 2178 emit_opcode(cbuf, $d8$$constant); | |
| 2179 %} | |
| 2180 | |
| 2181 // Emit size prefix | |
| 2182 enc_class SizePrefix | |
| 2183 %{ | |
| 2184 emit_opcode(cbuf, 0x66); | |
| 2185 %} | |
| 2186 | |
| 2187 enc_class reg(rRegI reg) | |
| 2188 %{ | |
| 2189 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7); | |
| 2190 %} | |
| 2191 | |
| 2192 enc_class reg_reg(rRegI dst, rRegI src) | |
| 2193 %{ | |
| 2194 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7); | |
| 2195 %} | |
| 2196 | |
| 2197 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src) | |
| 2198 %{ | |
| 2199 emit_opcode(cbuf, $opcode$$constant); | |
| 2200 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7); | |
| 2201 %} | |
| 2202 | |
| 2203 enc_class cmpfp_fixup() | |
| 2204 %{ | |
| 2205 // jnp,s exit | |
| 2206 emit_opcode(cbuf, 0x7B); | |
| 2207 emit_d8(cbuf, 0x0A); | |
| 2208 | |
| 2209 // pushfq | |
| 2210 emit_opcode(cbuf, 0x9C); | |
| 2211 | |
| 2212 // andq $0xffffff2b, (%rsp) | |
| 2213 emit_opcode(cbuf, Assembler::REX_W); | |
| 2214 emit_opcode(cbuf, 0x81); | |
| 2215 emit_opcode(cbuf, 0x24); | |
| 2216 emit_opcode(cbuf, 0x24); | |
| 2217 emit_d32(cbuf, 0xffffff2b); | |
| 2218 | |
| 2219 // popfq | |
| 2220 emit_opcode(cbuf, 0x9D); | |
| 2221 | |
| 2222 // nop (target for branch to avoid branch to branch) | |
| 2223 emit_opcode(cbuf, 0x90); | |
| 2224 %} | |
| 2225 | |
| 2226 enc_class cmpfp3(rRegI dst) | |
| 2227 %{ | |
| 2228 int dstenc = $dst$$reg; | |
| 2229 | |
| 2230 // movl $dst, -1 | |
| 2231 if (dstenc >= 8) { | |
| 2232 emit_opcode(cbuf, Assembler::REX_B); | |
| 2233 } | |
| 2234 emit_opcode(cbuf, 0xB8 | (dstenc & 7)); | |
| 2235 emit_d32(cbuf, -1); | |
| 2236 | |
| 2237 // jp,s done | |
| 2238 emit_opcode(cbuf, 0x7A); | |
| 2239 emit_d8(cbuf, dstenc < 4 ? 0x08 : 0x0A); | |
| 2240 | |
| 2241 // jb,s done | |
| 2242 emit_opcode(cbuf, 0x72); | |
| 2243 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08); | |
| 2244 | |
| 2245 // setne $dst | |
| 2246 if (dstenc >= 4) { | |
| 2247 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B); | |
| 2248 } | |
| 2249 emit_opcode(cbuf, 0x0F); | |
| 2250 emit_opcode(cbuf, 0x95); | |
| 2251 emit_opcode(cbuf, 0xC0 | (dstenc & 7)); | |
| 2252 | |
| 2253 // movzbl $dst, $dst | |
| 2254 if (dstenc >= 4) { | |
| 2255 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB); | |
| 2256 } | |
| 2257 emit_opcode(cbuf, 0x0F); | |
| 2258 emit_opcode(cbuf, 0xB6); | |
| 2259 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7); | |
| 2260 %} | |
| 2261 | |
| 2262 enc_class cdql_enc(no_rax_rdx_RegI div) | |
| 2263 %{ | |
| 2264 // Full implementation of Java idiv and irem; checks for | |
| 2265 // special case as described in JVM spec., p.243 & p.271. | |
| 2266 // | |
| 2267 // normal case special case | |
| 2268 // | |
| 2269 // input : rax: dividend min_int | |
| 2270 // reg: divisor -1 | |
| 2271 // | |
| 2272 // output: rax: quotient (= rax idiv reg) min_int | |
| 2273 // rdx: remainder (= rax irem reg) 0 | |
| 2274 // | |
| 2275 // Code sequnce: | |
| 2276 // | |
| 2277 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax | |
| 2278 // 5: 75 07/08 jne e <normal> | |
| 2279 // 7: 33 d2 xor %edx,%edx | |
| 2280 // [div >= 8 -> offset + 1] | |
| 2281 // [REX_B] | |
| 2282 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div | |
| 2283 // c: 74 03/04 je 11 <done> | |
| 2284 // 000000000000000e <normal>: | |
| 2285 // e: 99 cltd | |
| 2286 // [div >= 8 -> offset + 1] | |
| 2287 // [REX_B] | |
| 2288 // f: f7 f9 idiv $div | |
| 2289 // 0000000000000011 <done>: | |
| 2290 | |
| 2291 // cmp $0x80000000,%eax | |
| 2292 emit_opcode(cbuf, 0x3d); | |
| 2293 emit_d8(cbuf, 0x00); | |
| 2294 emit_d8(cbuf, 0x00); | |
| 2295 emit_d8(cbuf, 0x00); | |
| 2296 emit_d8(cbuf, 0x80); | |
| 2297 | |
| 2298 // jne e <normal> | |
| 2299 emit_opcode(cbuf, 0x75); | |
| 2300 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08); | |
| 2301 | |
| 2302 // xor %edx,%edx | |
| 2303 emit_opcode(cbuf, 0x33); | |
| 2304 emit_d8(cbuf, 0xD2); | |
| 2305 | |
| 2306 // cmp $0xffffffffffffffff,%ecx | |
| 2307 if ($div$$reg >= 8) { | |
| 2308 emit_opcode(cbuf, Assembler::REX_B); | |
| 2309 } | |
| 2310 emit_opcode(cbuf, 0x83); | |
| 2311 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7); | |
| 2312 emit_d8(cbuf, 0xFF); | |
| 2313 | |
| 2314 // je 11 <done> | |
| 2315 emit_opcode(cbuf, 0x74); | |
| 2316 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04); | |
| 2317 | |
| 2318 // <normal> | |
| 2319 // cltd | |
| 2320 emit_opcode(cbuf, 0x99); | |
| 2321 | |
| 2322 // idivl (note: must be emitted by the user of this rule) | |
| 2323 // <done> | |
| 2324 %} | |
| 2325 | |
| 2326 enc_class cdqq_enc(no_rax_rdx_RegL div) | |
| 2327 %{ | |
| 2328 // Full implementation of Java ldiv and lrem; checks for | |
| 2329 // special case as described in JVM spec., p.243 & p.271. | |
| 2330 // | |
| 2331 // normal case special case | |
| 2332 // | |
| 2333 // input : rax: dividend min_long | |
| 2334 // reg: divisor -1 | |
| 2335 // | |
| 2336 // output: rax: quotient (= rax idiv reg) min_long | |
| 2337 // rdx: remainder (= rax irem reg) 0 | |
| 2338 // | |
| 2339 // Code sequnce: | |
| 2340 // | |
| 2341 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx | |
| 2342 // 7: 00 00 80 | |
| 2343 // a: 48 39 d0 cmp %rdx,%rax | |
| 2344 // d: 75 08 jne 17 <normal> | |
| 2345 // f: 33 d2 xor %edx,%edx | |
| 2346 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div | |
| 2347 // 15: 74 05 je 1c <done> | |
| 2348 // 0000000000000017 <normal>: | |
| 2349 // 17: 48 99 cqto | |
| 2350 // 19: 48 f7 f9 idiv $div | |
| 2351 // 000000000000001c <done>: | |
| 2352 | |
| 2353 // mov $0x8000000000000000,%rdx | |
| 2354 emit_opcode(cbuf, Assembler::REX_W); | |
| 2355 emit_opcode(cbuf, 0xBA); | |
| 2356 emit_d8(cbuf, 0x00); | |
| 2357 emit_d8(cbuf, 0x00); | |
| 2358 emit_d8(cbuf, 0x00); | |
| 2359 emit_d8(cbuf, 0x00); | |
| 2360 emit_d8(cbuf, 0x00); | |
| 2361 emit_d8(cbuf, 0x00); | |
| 2362 emit_d8(cbuf, 0x00); | |
| 2363 emit_d8(cbuf, 0x80); | |
| 2364 | |
| 2365 // cmp %rdx,%rax | |
| 2366 emit_opcode(cbuf, Assembler::REX_W); | |
| 2367 emit_opcode(cbuf, 0x39); | |
| 2368 emit_d8(cbuf, 0xD0); | |
| 2369 | |
| 2370 // jne 17 <normal> | |
| 2371 emit_opcode(cbuf, 0x75); | |
| 2372 emit_d8(cbuf, 0x08); | |
| 2373 | |
| 2374 // xor %edx,%edx | |
| 2375 emit_opcode(cbuf, 0x33); | |
| 2376 emit_d8(cbuf, 0xD2); | |
| 2377 | |
| 2378 // cmp $0xffffffffffffffff,$div | |
| 2379 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB); | |
| 2380 emit_opcode(cbuf, 0x83); | |
| 2381 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7); | |
| 2382 emit_d8(cbuf, 0xFF); | |
| 2383 | |
| 2384 // je 1e <done> | |
| 2385 emit_opcode(cbuf, 0x74); | |
| 2386 emit_d8(cbuf, 0x05); | |
| 2387 | |
| 2388 // <normal> | |
| 2389 // cqto | |
| 2390 emit_opcode(cbuf, Assembler::REX_W); | |
| 2391 emit_opcode(cbuf, 0x99); | |
| 2392 | |
| 2393 // idivq (note: must be emitted by the user of this rule) | |
| 2394 // <done> | |
| 2395 %} | |
| 2396 | |
| 2397 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension | |
| 2398 enc_class OpcSE(immI imm) | |
| 2399 %{ | |
| 2400 // Emit primary opcode and set sign-extend bit | |
| 2401 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 2402 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
| 2403 emit_opcode(cbuf, $primary | 0x02); | |
| 2404 } else { | |
| 2405 // 32-bit immediate | |
| 2406 emit_opcode(cbuf, $primary); | |
| 2407 } | |
| 2408 %} | |
| 2409 | |
| 2410 enc_class OpcSErm(rRegI dst, immI imm) | |
| 2411 %{ | |
| 2412 // OpcSEr/m | |
| 2413 int dstenc = $dst$$reg; | |
| 2414 if (dstenc >= 8) { | |
| 2415 emit_opcode(cbuf, Assembler::REX_B); | |
| 2416 dstenc -= 8; | |
| 2417 } | |
| 2418 // Emit primary opcode and set sign-extend bit | |
| 2419 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 2420 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
| 2421 emit_opcode(cbuf, $primary | 0x02); | |
| 2422 } else { | |
| 2423 // 32-bit immediate | |
| 2424 emit_opcode(cbuf, $primary); | |
| 2425 } | |
| 2426 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 2427 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
| 2428 %} | |
| 2429 | |
| 2430 enc_class OpcSErm_wide(rRegL dst, immI imm) | |
| 2431 %{ | |
| 2432 // OpcSEr/m | |
| 2433 int dstenc = $dst$$reg; | |
| 2434 if (dstenc < 8) { | |
| 2435 emit_opcode(cbuf, Assembler::REX_W); | |
| 2436 } else { | |
| 2437 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2438 dstenc -= 8; | |
| 2439 } | |
| 2440 // Emit primary opcode and set sign-extend bit | |
| 2441 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 2442 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
| 2443 emit_opcode(cbuf, $primary | 0x02); | |
| 2444 } else { | |
| 2445 // 32-bit immediate | |
| 2446 emit_opcode(cbuf, $primary); | |
| 2447 } | |
| 2448 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 2449 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
| 2450 %} | |
| 2451 | |
| 2452 enc_class Con8or32(immI imm) | |
| 2453 %{ | |
| 2454 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 2455 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
| 2456 $$$emit8$imm$$constant; | |
| 2457 } else { | |
| 2458 // 32-bit immediate | |
| 2459 $$$emit32$imm$$constant; | |
| 2460 } | |
| 2461 %} | |
| 2462 | |
| 2463 enc_class Lbl(label labl) | |
| 2464 %{ | |
| 2465 // JMP, CALL | |
| 2466 Label* l = $labl$$label; | |
| 2467 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0); | |
| 2468 %} | |
| 2469 | |
| 2470 enc_class LblShort(label labl) | |
| 2471 %{ | |
| 2472 // JMP, CALL | |
| 2473 Label* l = $labl$$label; | |
| 2474 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0; | |
| 2475 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp"); | |
| 2476 emit_d8(cbuf, disp); | |
| 2477 %} | |
| 2478 | |
| 2479 enc_class opc2_reg(rRegI dst) | |
| 2480 %{ | |
| 2481 // BSWAP | |
| 2482 emit_cc(cbuf, $secondary, $dst$$reg); | |
| 2483 %} | |
| 2484 | |
| 2485 enc_class opc3_reg(rRegI dst) | |
| 2486 %{ | |
| 2487 // BSWAP | |
| 2488 emit_cc(cbuf, $tertiary, $dst$$reg); | |
| 2489 %} | |
| 2490 | |
| 2491 enc_class reg_opc(rRegI div) | |
| 2492 %{ | |
| 2493 // INC, DEC, IDIV, IMOD, JMP indirect, ... | |
| 2494 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7); | |
| 2495 %} | |
| 2496 | |
| 2497 enc_class Jcc(cmpOp cop, label labl) | |
| 2498 %{ | |
| 2499 // JCC | |
| 2500 Label* l = $labl$$label; | |
| 2501 $$$emit8$primary; | |
| 2502 emit_cc(cbuf, $secondary, $cop$$cmpcode); | |
| 2503 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0); | |
| 2504 %} | |
| 2505 | |
| 2506 enc_class JccShort (cmpOp cop, label labl) | |
| 2507 %{ | |
| 2508 // JCC | |
| 2509 Label *l = $labl$$label; | |
| 2510 emit_cc(cbuf, $primary, $cop$$cmpcode); | |
| 2511 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0; | |
| 2512 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp"); | |
| 2513 emit_d8(cbuf, disp); | |
| 2514 %} | |
| 2515 | |
| 2516 enc_class enc_cmov(cmpOp cop) | |
| 2517 %{ | |
| 2518 // CMOV | |
| 2519 $$$emit8$primary; | |
| 2520 emit_cc(cbuf, $secondary, $cop$$cmpcode); | |
| 2521 %} | |
| 2522 | |
| 2523 enc_class enc_cmovf_branch(cmpOp cop, regF dst, regF src) | |
| 2524 %{ | |
| 2525 // Invert sense of branch from sense of cmov | |
| 2526 emit_cc(cbuf, 0x70, $cop$$cmpcode ^ 1); | |
| 2527 emit_d8(cbuf, ($dst$$reg < 8 && $src$$reg < 8) | |
| 2528 ? (UseXmmRegToRegMoveAll ? 3 : 4) | |
| 2529 : (UseXmmRegToRegMoveAll ? 4 : 5) ); // REX | |
| 2530 // UseXmmRegToRegMoveAll ? movaps(dst, src) : movss(dst, src) | |
| 2531 if (!UseXmmRegToRegMoveAll) emit_opcode(cbuf, 0xF3); | |
| 2532 if ($dst$$reg < 8) { | |
| 2533 if ($src$$reg >= 8) { | |
| 2534 emit_opcode(cbuf, Assembler::REX_B); | |
| 2535 } | |
| 2536 } else { | |
| 2537 if ($src$$reg < 8) { | |
| 2538 emit_opcode(cbuf, Assembler::REX_R); | |
| 2539 } else { | |
| 2540 emit_opcode(cbuf, Assembler::REX_RB); | |
| 2541 } | |
| 2542 } | |
| 2543 emit_opcode(cbuf, 0x0F); | |
| 2544 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10); | |
| 2545 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7); | |
| 2546 %} | |
| 2547 | |
| 2548 enc_class enc_cmovd_branch(cmpOp cop, regD dst, regD src) | |
| 2549 %{ | |
| 2550 // Invert sense of branch from sense of cmov | |
| 2551 emit_cc(cbuf, 0x70, $cop$$cmpcode ^ 1); | |
| 2552 emit_d8(cbuf, $dst$$reg < 8 && $src$$reg < 8 ? 4 : 5); // REX | |
| 2553 | |
| 2554 // UseXmmRegToRegMoveAll ? movapd(dst, src) : movsd(dst, src) | |
| 2555 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x66 : 0xF2); | |
| 2556 if ($dst$$reg < 8) { | |
| 2557 if ($src$$reg >= 8) { | |
| 2558 emit_opcode(cbuf, Assembler::REX_B); | |
| 2559 } | |
| 2560 } else { | |
| 2561 if ($src$$reg < 8) { | |
| 2562 emit_opcode(cbuf, Assembler::REX_R); | |
| 2563 } else { | |
| 2564 emit_opcode(cbuf, Assembler::REX_RB); | |
| 2565 } | |
| 2566 } | |
| 2567 emit_opcode(cbuf, 0x0F); | |
| 2568 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10); | |
| 2569 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7); | |
| 2570 %} | |
| 2571 | |
| 2572 enc_class enc_PartialSubtypeCheck() | |
| 2573 %{ | |
| 2574 Register Rrdi = as_Register(RDI_enc); // result register | |
| 2575 Register Rrax = as_Register(RAX_enc); // super class | |
| 2576 Register Rrcx = as_Register(RCX_enc); // killed | |
| 2577 Register Rrsi = as_Register(RSI_enc); // sub class | |
|
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2578 Label hit, miss, cmiss; |
| 0 | 2579 |
| 2580 MacroAssembler _masm(&cbuf); | |
| 2581 // Compare super with sub directly, since super is not in its own SSA. | |
| 2582 // The compiler used to emit this test, but we fold it in here, | |
| 2583 // to allow platform-specific tweaking on sparc. | |
| 304 | 2584 __ cmpptr(Rrax, Rrsi); |
| 0 | 2585 __ jcc(Assembler::equal, hit); |
| 2586 #ifndef PRODUCT | |
| 2587 __ lea(Rrcx, ExternalAddress((address)&SharedRuntime::_partial_subtype_ctr)); | |
| 2588 __ incrementl(Address(Rrcx, 0)); | |
| 2589 #endif //PRODUCT | |
| 304 | 2590 __ movptr(Rrdi, Address(Rrsi, |
| 2591 sizeof(oopDesc) + | |
| 0 | 2592 Klass::secondary_supers_offset_in_bytes())); |
| 2593 __ movl(Rrcx, Address(Rrdi, arrayOopDesc::length_offset_in_bytes())); | |
| 304 | 2594 __ addptr(Rrdi, arrayOopDesc::base_offset_in_bytes(T_OBJECT)); |
|
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2595 if (UseCompressedOops) { |
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2596 __ encode_heap_oop(Rrax); |
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2597 __ repne_scanl(); |
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2598 __ jcc(Assembler::notEqual, cmiss); |
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2599 __ decode_heap_oop(Rrax); |
| 304 | 2600 __ movptr(Address(Rrsi, |
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2601 sizeof(oopDesc) + |
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2602 Klass::secondary_super_cache_offset_in_bytes()), |
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2603 Rrax); |
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2604 __ jmp(hit); |
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2605 __ bind(cmiss); |
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2606 __ decode_heap_oop(Rrax); |
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2607 __ jmp(miss); |
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2608 } else { |
| 304 | 2609 __ repne_scan(); |
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2610 __ jcc(Assembler::notEqual, miss); |
| 304 | 2611 __ movptr(Address(Rrsi, |
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2612 sizeof(oopDesc) + |
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2613 Klass::secondary_super_cache_offset_in_bytes()), |
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2614 Rrax); |
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2615 } |
| 0 | 2616 __ bind(hit); |
| 2617 if ($primary) { | |
| 304 | 2618 __ xorptr(Rrdi, Rrdi); |
| 0 | 2619 } |
| 2620 __ bind(miss); | |
| 2621 %} | |
| 2622 | |
| 2623 enc_class Java_To_Interpreter(method meth) | |
| 2624 %{ | |
| 2625 // CALL Java_To_Interpreter | |
| 2626 // This is the instruction starting address for relocation info. | |
| 2627 cbuf.set_inst_mark(); | |
| 2628 $$$emit8$primary; | |
| 2629 // CALL directly to the runtime | |
| 2630 emit_d32_reloc(cbuf, | |
| 2631 (int) ($meth$$method - ((intptr_t) cbuf.code_end()) - 4), | |
| 2632 runtime_call_Relocation::spec(), | |
| 2633 RELOC_DISP32); | |
| 2634 %} | |
| 2635 | |
| 2636 enc_class Java_Static_Call(method meth) | |
| 2637 %{ | |
| 2638 // JAVA STATIC CALL | |
| 2639 // CALL to fixup routine. Fixup routine uses ScopeDesc info to | |
| 2640 // determine who we intended to call. | |
| 2641 cbuf.set_inst_mark(); | |
| 2642 $$$emit8$primary; | |
| 2643 | |
| 2644 if (!_method) { | |
| 2645 emit_d32_reloc(cbuf, | |
| 2646 (int) ($meth$$method - ((intptr_t) cbuf.code_end()) - 4), | |
| 2647 runtime_call_Relocation::spec(), | |
| 2648 RELOC_DISP32); | |
| 2649 } else if (_optimized_virtual) { | |
| 2650 emit_d32_reloc(cbuf, | |
| 2651 (int) ($meth$$method - ((intptr_t) cbuf.code_end()) - 4), | |
| 2652 opt_virtual_call_Relocation::spec(), | |
| 2653 RELOC_DISP32); | |
| 2654 } else { | |
| 2655 emit_d32_reloc(cbuf, | |
| 2656 (int) ($meth$$method - ((intptr_t) cbuf.code_end()) - 4), | |
| 2657 static_call_Relocation::spec(), | |
| 2658 RELOC_DISP32); | |
| 2659 } | |
| 2660 if (_method) { | |
| 2661 // Emit stub for static call | |
| 2662 emit_java_to_interp(cbuf); | |
| 2663 } | |
| 2664 %} | |
| 2665 | |
| 2666 enc_class Java_Dynamic_Call(method meth) | |
| 2667 %{ | |
| 2668 // JAVA DYNAMIC CALL | |
| 2669 // !!!!! | |
| 2670 // Generate "movq rax, -1", placeholder instruction to load oop-info | |
| 2671 // emit_call_dynamic_prologue( cbuf ); | |
| 2672 cbuf.set_inst_mark(); | |
| 2673 | |
| 2674 // movq rax, -1 | |
| 2675 emit_opcode(cbuf, Assembler::REX_W); | |
| 2676 emit_opcode(cbuf, 0xB8 | RAX_enc); | |
| 2677 emit_d64_reloc(cbuf, | |
| 2678 (int64_t) Universe::non_oop_word(), | |
| 2679 oop_Relocation::spec_for_immediate(), RELOC_IMM64); | |
| 2680 address virtual_call_oop_addr = cbuf.inst_mark(); | |
| 2681 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
| 2682 // who we intended to call. | |
| 2683 cbuf.set_inst_mark(); | |
| 2684 $$$emit8$primary; | |
| 2685 emit_d32_reloc(cbuf, | |
| 2686 (int) ($meth$$method - ((intptr_t) cbuf.code_end()) - 4), | |
| 2687 virtual_call_Relocation::spec(virtual_call_oop_addr), | |
| 2688 RELOC_DISP32); | |
| 2689 %} | |
| 2690 | |
| 2691 enc_class Java_Compiled_Call(method meth) | |
| 2692 %{ | |
| 2693 // JAVA COMPILED CALL | |
| 2694 int disp = in_bytes(methodOopDesc:: from_compiled_offset()); | |
| 2695 | |
| 2696 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!! | |
| 2697 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small"); | |
| 2698 | |
| 2699 // callq *disp(%rax) | |
| 2700 cbuf.set_inst_mark(); | |
| 2701 $$$emit8$primary; | |
| 2702 if (disp < 0x80) { | |
| 2703 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte | |
| 2704 emit_d8(cbuf, disp); // Displacement | |
| 2705 } else { | |
| 2706 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte | |
| 2707 emit_d32(cbuf, disp); // Displacement | |
| 2708 } | |
| 2709 %} | |
| 2710 | |
| 2711 enc_class reg_opc_imm(rRegI dst, immI8 shift) | |
| 2712 %{ | |
| 2713 // SAL, SAR, SHR | |
| 2714 int dstenc = $dst$$reg; | |
| 2715 if (dstenc >= 8) { | |
| 2716 emit_opcode(cbuf, Assembler::REX_B); | |
| 2717 dstenc -= 8; | |
| 2718 } | |
| 2719 $$$emit8$primary; | |
| 2720 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
| 2721 $$$emit8$shift$$constant; | |
| 2722 %} | |
| 2723 | |
| 2724 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift) | |
| 2725 %{ | |
| 2726 // SAL, SAR, SHR | |
| 2727 int dstenc = $dst$$reg; | |
| 2728 if (dstenc < 8) { | |
| 2729 emit_opcode(cbuf, Assembler::REX_W); | |
| 2730 } else { | |
| 2731 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2732 dstenc -= 8; | |
| 2733 } | |
| 2734 $$$emit8$primary; | |
| 2735 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
| 2736 $$$emit8$shift$$constant; | |
| 2737 %} | |
| 2738 | |
| 2739 enc_class load_immI(rRegI dst, immI src) | |
| 2740 %{ | |
| 2741 int dstenc = $dst$$reg; | |
| 2742 if (dstenc >= 8) { | |
| 2743 emit_opcode(cbuf, Assembler::REX_B); | |
| 2744 dstenc -= 8; | |
| 2745 } | |
| 2746 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2747 $$$emit32$src$$constant; | |
| 2748 %} | |
| 2749 | |
| 2750 enc_class load_immL(rRegL dst, immL src) | |
| 2751 %{ | |
| 2752 int dstenc = $dst$$reg; | |
| 2753 if (dstenc < 8) { | |
| 2754 emit_opcode(cbuf, Assembler::REX_W); | |
| 2755 } else { | |
| 2756 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2757 dstenc -= 8; | |
| 2758 } | |
| 2759 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2760 emit_d64(cbuf, $src$$constant); | |
| 2761 %} | |
| 2762 | |
| 2763 enc_class load_immUL32(rRegL dst, immUL32 src) | |
| 2764 %{ | |
| 2765 // same as load_immI, but this time we care about zeroes in the high word | |
| 2766 int dstenc = $dst$$reg; | |
| 2767 if (dstenc >= 8) { | |
| 2768 emit_opcode(cbuf, Assembler::REX_B); | |
| 2769 dstenc -= 8; | |
| 2770 } | |
| 2771 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2772 $$$emit32$src$$constant; | |
| 2773 %} | |
| 2774 | |
| 2775 enc_class load_immL32(rRegL dst, immL32 src) | |
| 2776 %{ | |
| 2777 int dstenc = $dst$$reg; | |
| 2778 if (dstenc < 8) { | |
| 2779 emit_opcode(cbuf, Assembler::REX_W); | |
| 2780 } else { | |
| 2781 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2782 dstenc -= 8; | |
| 2783 } | |
| 2784 emit_opcode(cbuf, 0xC7); | |
| 2785 emit_rm(cbuf, 0x03, 0x00, dstenc); | |
| 2786 $$$emit32$src$$constant; | |
| 2787 %} | |
| 2788 | |
| 2789 enc_class load_immP31(rRegP dst, immP32 src) | |
| 2790 %{ | |
| 2791 // same as load_immI, but this time we care about zeroes in the high word | |
| 2792 int dstenc = $dst$$reg; | |
| 2793 if (dstenc >= 8) { | |
| 2794 emit_opcode(cbuf, Assembler::REX_B); | |
| 2795 dstenc -= 8; | |
| 2796 } | |
| 2797 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2798 $$$emit32$src$$constant; | |
| 2799 %} | |
| 2800 | |
| 2801 enc_class load_immP(rRegP dst, immP src) | |
| 2802 %{ | |
| 2803 int dstenc = $dst$$reg; | |
| 2804 if (dstenc < 8) { | |
| 2805 emit_opcode(cbuf, Assembler::REX_W); | |
| 2806 } else { | |
| 2807 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2808 dstenc -= 8; | |
| 2809 } | |
| 2810 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2811 // This next line should be generated from ADLC | |
| 2812 if ($src->constant_is_oop()) { | |
| 2813 emit_d64_reloc(cbuf, $src$$constant, relocInfo::oop_type, RELOC_IMM64); | |
| 2814 } else { | |
| 2815 emit_d64(cbuf, $src$$constant); | |
| 2816 } | |
| 2817 %} | |
| 2818 | |
| 2819 enc_class load_immF(regF dst, immF con) | |
| 2820 %{ | |
| 2821 // XXX reg_mem doesn't support RIP-relative addressing yet | |
| 2822 emit_rm(cbuf, 0x0, $dst$$reg & 7, 0x5); // 00 reg 101 | |
| 2823 emit_float_constant(cbuf, $con$$constant); | |
| 2824 %} | |
| 2825 | |
| 2826 enc_class load_immD(regD dst, immD con) | |
| 2827 %{ | |
| 2828 // XXX reg_mem doesn't support RIP-relative addressing yet | |
| 2829 emit_rm(cbuf, 0x0, $dst$$reg & 7, 0x5); // 00 reg 101 | |
| 2830 emit_double_constant(cbuf, $con$$constant); | |
| 2831 %} | |
| 2832 | |
| 2833 enc_class load_conF (regF dst, immF con) %{ // Load float constant | |
| 2834 emit_opcode(cbuf, 0xF3); | |
| 2835 if ($dst$$reg >= 8) { | |
| 2836 emit_opcode(cbuf, Assembler::REX_R); | |
| 2837 } | |
| 2838 emit_opcode(cbuf, 0x0F); | |
| 2839 emit_opcode(cbuf, 0x10); | |
| 2840 emit_rm(cbuf, 0x0, $dst$$reg & 7, 0x5); // 00 reg 101 | |
| 2841 emit_float_constant(cbuf, $con$$constant); | |
| 2842 %} | |
| 2843 | |
| 2844 enc_class load_conD (regD dst, immD con) %{ // Load double constant | |
| 2845 // UseXmmLoadAndClearUpper ? movsd(dst, con) : movlpd(dst, con) | |
| 2846 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66); | |
| 2847 if ($dst$$reg >= 8) { | |
| 2848 emit_opcode(cbuf, Assembler::REX_R); | |
| 2849 } | |
| 2850 emit_opcode(cbuf, 0x0F); | |
| 2851 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12); | |
| 2852 emit_rm(cbuf, 0x0, $dst$$reg & 7, 0x5); // 00 reg 101 | |
| 2853 emit_double_constant(cbuf, $con$$constant); | |
| 2854 %} | |
| 2855 | |
| 2856 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 2857 enc_class enc_copy(rRegI dst, rRegI src) | |
| 2858 %{ | |
| 2859 encode_copy(cbuf, $dst$$reg, $src$$reg); | |
| 2860 %} | |
| 2861 | |
| 2862 // Encode xmm reg-reg copy. If it is useless, then empty encoding. | |
| 2863 enc_class enc_CopyXD( RegD dst, RegD src ) %{ | |
| 2864 encode_CopyXD( cbuf, $dst$$reg, $src$$reg ); | |
| 2865 %} | |
| 2866 | |
| 2867 enc_class enc_copy_always(rRegI dst, rRegI src) | |
| 2868 %{ | |
| 2869 int srcenc = $src$$reg; | |
| 2870 int dstenc = $dst$$reg; | |
| 2871 | |
| 2872 if (dstenc < 8) { | |
| 2873 if (srcenc >= 8) { | |
| 2874 emit_opcode(cbuf, Assembler::REX_B); | |
| 2875 srcenc -= 8; | |
| 2876 } | |
| 2877 } else { | |
| 2878 if (srcenc < 8) { | |
| 2879 emit_opcode(cbuf, Assembler::REX_R); | |
| 2880 } else { | |
| 2881 emit_opcode(cbuf, Assembler::REX_RB); | |
| 2882 srcenc -= 8; | |
| 2883 } | |
| 2884 dstenc -= 8; | |
| 2885 } | |
| 2886 | |
| 2887 emit_opcode(cbuf, 0x8B); | |
| 2888 emit_rm(cbuf, 0x3, dstenc, srcenc); | |
| 2889 %} | |
| 2890 | |
| 2891 enc_class enc_copy_wide(rRegL dst, rRegL src) | |
| 2892 %{ | |
| 2893 int srcenc = $src$$reg; | |
| 2894 int dstenc = $dst$$reg; | |
| 2895 | |
| 2896 if (dstenc != srcenc) { | |
| 2897 if (dstenc < 8) { | |
| 2898 if (srcenc < 8) { | |
| 2899 emit_opcode(cbuf, Assembler::REX_W); | |
| 2900 } else { | |
| 2901 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2902 srcenc -= 8; | |
| 2903 } | |
| 2904 } else { | |
| 2905 if (srcenc < 8) { | |
| 2906 emit_opcode(cbuf, Assembler::REX_WR); | |
| 2907 } else { | |
| 2908 emit_opcode(cbuf, Assembler::REX_WRB); | |
| 2909 srcenc -= 8; | |
| 2910 } | |
| 2911 dstenc -= 8; | |
| 2912 } | |
| 2913 emit_opcode(cbuf, 0x8B); | |
| 2914 emit_rm(cbuf, 0x3, dstenc, srcenc); | |
| 2915 } | |
| 2916 %} | |
| 2917 | |
| 2918 enc_class Con32(immI src) | |
| 2919 %{ | |
| 2920 // Output immediate | |
| 2921 $$$emit32$src$$constant; | |
| 2922 %} | |
| 2923 | |
| 2924 enc_class Con64(immL src) | |
| 2925 %{ | |
| 2926 // Output immediate | |
| 2927 emit_d64($src$$constant); | |
| 2928 %} | |
| 2929 | |
| 2930 enc_class Con32F_as_bits(immF src) | |
| 2931 %{ | |
| 2932 // Output Float immediate bits | |
| 2933 jfloat jf = $src$$constant; | |
| 2934 jint jf_as_bits = jint_cast(jf); | |
| 2935 emit_d32(cbuf, jf_as_bits); | |
| 2936 %} | |
| 2937 | |
| 2938 enc_class Con16(immI src) | |
| 2939 %{ | |
| 2940 // Output immediate | |
| 2941 $$$emit16$src$$constant; | |
| 2942 %} | |
| 2943 | |
| 2944 // How is this different from Con32??? XXX | |
| 2945 enc_class Con_d32(immI src) | |
| 2946 %{ | |
| 2947 emit_d32(cbuf,$src$$constant); | |
| 2948 %} | |
| 2949 | |
| 2950 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI) | |
| 2951 // Output immediate memory reference | |
| 2952 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 ); | |
| 2953 emit_d32(cbuf, 0x00); | |
| 2954 %} | |
| 2955 | |
| 2956 enc_class jump_enc(rRegL switch_val, rRegI dest) %{ | |
| 2957 MacroAssembler masm(&cbuf); | |
| 2958 | |
| 2959 Register switch_reg = as_Register($switch_val$$reg); | |
| 2960 Register dest_reg = as_Register($dest$$reg); | |
| 2961 address table_base = masm.address_table_constant(_index2label); | |
| 2962 | |
| 2963 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10 | |
| 2964 // to do that and the compiler is using that register as one it can allocate. | |
| 2965 // So we build it all by hand. | |
| 2966 // Address index(noreg, switch_reg, Address::times_1); | |
| 2967 // ArrayAddress dispatch(table, index); | |
| 2968 | |
| 2969 Address dispatch(dest_reg, switch_reg, Address::times_1); | |
| 2970 | |
| 2971 masm.lea(dest_reg, InternalAddress(table_base)); | |
| 2972 masm.jmp(dispatch); | |
| 2973 %} | |
| 2974 | |
| 2975 enc_class jump_enc_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{ | |
| 2976 MacroAssembler masm(&cbuf); | |
| 2977 | |
| 2978 Register switch_reg = as_Register($switch_val$$reg); | |
| 2979 Register dest_reg = as_Register($dest$$reg); | |
| 2980 address table_base = masm.address_table_constant(_index2label); | |
| 2981 | |
| 2982 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10 | |
| 2983 // to do that and the compiler is using that register as one it can allocate. | |
| 2984 // So we build it all by hand. | |
| 2985 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant, (int)$offset$$constant); | |
| 2986 // ArrayAddress dispatch(table, index); | |
| 2987 | |
| 2988 Address dispatch(dest_reg, switch_reg, (Address::ScaleFactor)$shift$$constant, (int)$offset$$constant); | |
| 2989 | |
| 2990 masm.lea(dest_reg, InternalAddress(table_base)); | |
| 2991 masm.jmp(dispatch); | |
| 2992 %} | |
| 2993 | |
| 2994 enc_class jump_enc_offset(rRegL switch_val, immI2 shift, rRegI dest) %{ | |
| 2995 MacroAssembler masm(&cbuf); | |
| 2996 | |
| 2997 Register switch_reg = as_Register($switch_val$$reg); | |
| 2998 Register dest_reg = as_Register($dest$$reg); | |
| 2999 address table_base = masm.address_table_constant(_index2label); | |
| 3000 | |
| 3001 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10 | |
| 3002 // to do that and the compiler is using that register as one it can allocate. | |
| 3003 // So we build it all by hand. | |
| 3004 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant); | |
| 3005 // ArrayAddress dispatch(table, index); | |
| 3006 | |
| 3007 Address dispatch(dest_reg, switch_reg, (Address::ScaleFactor)$shift$$constant); | |
| 3008 masm.lea(dest_reg, InternalAddress(table_base)); | |
| 3009 masm.jmp(dispatch); | |
| 3010 | |
| 3011 %} | |
| 3012 | |
| 3013 enc_class lock_prefix() | |
| 3014 %{ | |
| 3015 if (os::is_MP()) { | |
| 3016 emit_opcode(cbuf, 0xF0); // lock | |
| 3017 } | |
| 3018 %} | |
| 3019 | |
| 3020 enc_class REX_mem(memory mem) | |
| 3021 %{ | |
| 3022 if ($mem$$base >= 8) { | |
| 3023 if ($mem$$index < 8) { | |
| 3024 emit_opcode(cbuf, Assembler::REX_B); | |
| 3025 } else { | |
| 3026 emit_opcode(cbuf, Assembler::REX_XB); | |
| 3027 } | |
| 3028 } else { | |
| 3029 if ($mem$$index >= 8) { | |
| 3030 emit_opcode(cbuf, Assembler::REX_X); | |
| 3031 } | |
| 3032 } | |
| 3033 %} | |
| 3034 | |
| 3035 enc_class REX_mem_wide(memory mem) | |
| 3036 %{ | |
| 3037 if ($mem$$base >= 8) { | |
| 3038 if ($mem$$index < 8) { | |
| 3039 emit_opcode(cbuf, Assembler::REX_WB); | |
| 3040 } else { | |
| 3041 emit_opcode(cbuf, Assembler::REX_WXB); | |
| 3042 } | |
| 3043 } else { | |
| 3044 if ($mem$$index < 8) { | |
| 3045 emit_opcode(cbuf, Assembler::REX_W); | |
| 3046 } else { | |
| 3047 emit_opcode(cbuf, Assembler::REX_WX); | |
| 3048 } | |
| 3049 } | |
| 3050 %} | |
| 3051 | |
| 3052 // for byte regs | |
| 3053 enc_class REX_breg(rRegI reg) | |
| 3054 %{ | |
| 3055 if ($reg$$reg >= 4) { | |
| 3056 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B); | |
| 3057 } | |
| 3058 %} | |
| 3059 | |
| 3060 // for byte regs | |
| 3061 enc_class REX_reg_breg(rRegI dst, rRegI src) | |
| 3062 %{ | |
| 3063 if ($dst$$reg < 8) { | |
| 3064 if ($src$$reg >= 4) { | |
| 3065 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B); | |
| 3066 } | |
| 3067 } else { | |
| 3068 if ($src$$reg < 8) { | |
| 3069 emit_opcode(cbuf, Assembler::REX_R); | |
| 3070 } else { | |
| 3071 emit_opcode(cbuf, Assembler::REX_RB); | |
| 3072 } | |
| 3073 } | |
| 3074 %} | |
| 3075 | |
| 3076 // for byte regs | |
| 3077 enc_class REX_breg_mem(rRegI reg, memory mem) | |
| 3078 %{ | |
| 3079 if ($reg$$reg < 8) { | |
| 3080 if ($mem$$base < 8) { | |
| 3081 if ($mem$$index >= 8) { | |
| 3082 emit_opcode(cbuf, Assembler::REX_X); | |
| 3083 } else if ($reg$$reg >= 4) { | |
| 3084 emit_opcode(cbuf, Assembler::REX); | |
| 3085 } | |
| 3086 } else { | |
| 3087 if ($mem$$index < 8) { | |
| 3088 emit_opcode(cbuf, Assembler::REX_B); | |
| 3089 } else { | |
| 3090 emit_opcode(cbuf, Assembler::REX_XB); | |
| 3091 } | |
| 3092 } | |
| 3093 } else { | |
| 3094 if ($mem$$base < 8) { | |
| 3095 if ($mem$$index < 8) { | |
| 3096 emit_opcode(cbuf, Assembler::REX_R); | |
| 3097 } else { | |
| 3098 emit_opcode(cbuf, Assembler::REX_RX); | |
| 3099 } | |
| 3100 } else { | |
| 3101 if ($mem$$index < 8) { | |
| 3102 emit_opcode(cbuf, Assembler::REX_RB); | |
| 3103 } else { | |
| 3104 emit_opcode(cbuf, Assembler::REX_RXB); | |
| 3105 } | |
| 3106 } | |
| 3107 } | |
| 3108 %} | |
| 3109 | |
| 3110 enc_class REX_reg(rRegI reg) | |
| 3111 %{ | |
| 3112 if ($reg$$reg >= 8) { | |
| 3113 emit_opcode(cbuf, Assembler::REX_B); | |
| 3114 } | |
| 3115 %} | |
| 3116 | |
| 3117 enc_class REX_reg_wide(rRegI reg) | |
| 3118 %{ | |
| 3119 if ($reg$$reg < 8) { | |
| 3120 emit_opcode(cbuf, Assembler::REX_W); | |
| 3121 } else { | |
| 3122 emit_opcode(cbuf, Assembler::REX_WB); | |
| 3123 } | |
| 3124 %} | |
| 3125 | |
| 3126 enc_class REX_reg_reg(rRegI dst, rRegI src) | |
| 3127 %{ | |
| 3128 if ($dst$$reg < 8) { | |
| 3129 if ($src$$reg >= 8) { | |
| 3130 emit_opcode(cbuf, Assembler::REX_B); | |
| 3131 } | |
| 3132 } else { | |
| 3133 if ($src$$reg < 8) { | |
| 3134 emit_opcode(cbuf, Assembler::REX_R); | |
| 3135 } else { | |
| 3136 emit_opcode(cbuf, Assembler::REX_RB); | |
| 3137 } | |
| 3138 } | |
| 3139 %} | |
| 3140 | |
| 3141 enc_class REX_reg_reg_wide(rRegI dst, rRegI src) | |
| 3142 %{ | |
| 3143 if ($dst$$reg < 8) { | |
| 3144 if ($src$$reg < 8) { | |
| 3145 emit_opcode(cbuf, Assembler::REX_W); | |
| 3146 } else { | |
| 3147 emit_opcode(cbuf, Assembler::REX_WB); | |
| 3148 } | |
| 3149 } else { | |
| 3150 if ($src$$reg < 8) { | |
| 3151 emit_opcode(cbuf, Assembler::REX_WR); | |
| 3152 } else { | |
| 3153 emit_opcode(cbuf, Assembler::REX_WRB); | |
| 3154 } | |
| 3155 } | |
| 3156 %} | |
| 3157 | |
| 3158 enc_class REX_reg_mem(rRegI reg, memory mem) | |
| 3159 %{ | |
| 3160 if ($reg$$reg < 8) { | |
| 3161 if ($mem$$base < 8) { | |
| 3162 if ($mem$$index >= 8) { | |
| 3163 emit_opcode(cbuf, Assembler::REX_X); | |
| 3164 } | |
| 3165 } else { | |
| 3166 if ($mem$$index < 8) { | |
| 3167 emit_opcode(cbuf, Assembler::REX_B); | |
| 3168 } else { | |
| 3169 emit_opcode(cbuf, Assembler::REX_XB); | |
| 3170 } | |
| 3171 } | |
| 3172 } else { | |
| 3173 if ($mem$$base < 8) { | |
| 3174 if ($mem$$index < 8) { | |
| 3175 emit_opcode(cbuf, Assembler::REX_R); | |
| 3176 } else { | |
| 3177 emit_opcode(cbuf, Assembler::REX_RX); | |
| 3178 } | |
| 3179 } else { | |
| 3180 if ($mem$$index < 8) { | |
| 3181 emit_opcode(cbuf, Assembler::REX_RB); | |
| 3182 } else { | |
| 3183 emit_opcode(cbuf, Assembler::REX_RXB); | |
| 3184 } | |
| 3185 } | |
| 3186 } | |
| 3187 %} | |
| 3188 | |
| 3189 enc_class REX_reg_mem_wide(rRegL reg, memory mem) | |
| 3190 %{ | |
| 3191 if ($reg$$reg < 8) { | |
| 3192 if ($mem$$base < 8) { | |
| 3193 if ($mem$$index < 8) { | |
| 3194 emit_opcode(cbuf, Assembler::REX_W); | |
| 3195 } else { | |
| 3196 emit_opcode(cbuf, Assembler::REX_WX); | |
| 3197 } | |
| 3198 } else { | |
| 3199 if ($mem$$index < 8) { | |
| 3200 emit_opcode(cbuf, Assembler::REX_WB); | |
| 3201 } else { | |
| 3202 emit_opcode(cbuf, Assembler::REX_WXB); | |
| 3203 } | |
| 3204 } | |
| 3205 } else { | |
| 3206 if ($mem$$base < 8) { | |
| 3207 if ($mem$$index < 8) { | |
| 3208 emit_opcode(cbuf, Assembler::REX_WR); | |
| 3209 } else { | |
| 3210 emit_opcode(cbuf, Assembler::REX_WRX); | |
| 3211 } | |
| 3212 } else { | |
| 3213 if ($mem$$index < 8) { | |
| 3214 emit_opcode(cbuf, Assembler::REX_WRB); | |
| 3215 } else { | |
| 3216 emit_opcode(cbuf, Assembler::REX_WRXB); | |
| 3217 } | |
| 3218 } | |
| 3219 } | |
| 3220 %} | |
| 3221 | |
| 3222 enc_class reg_mem(rRegI ereg, memory mem) | |
| 3223 %{ | |
| 3224 // High registers handle in encode_RegMem | |
| 3225 int reg = $ereg$$reg; | |
| 3226 int base = $mem$$base; | |
| 3227 int index = $mem$$index; | |
| 3228 int scale = $mem$$scale; | |
| 3229 int disp = $mem$$disp; | |
| 3230 bool disp_is_oop = $mem->disp_is_oop(); | |
| 3231 | |
| 3232 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_is_oop); | |
| 3233 %} | |
| 3234 | |
| 3235 enc_class RM_opc_mem(immI rm_opcode, memory mem) | |
| 3236 %{ | |
| 3237 int rm_byte_opcode = $rm_opcode$$constant; | |
| 3238 | |
| 3239 // High registers handle in encode_RegMem | |
| 3240 int base = $mem$$base; | |
| 3241 int index = $mem$$index; | |
| 3242 int scale = $mem$$scale; | |
| 3243 int displace = $mem$$disp; | |
| 3244 | |
| 3245 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when | |
| 3246 // working with static | |
| 3247 // globals | |
| 3248 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, | |
| 3249 disp_is_oop); | |
| 3250 %} | |
| 3251 | |
| 3252 enc_class reg_lea(rRegI dst, rRegI src0, immI src1) | |
| 3253 %{ | |
| 3254 int reg_encoding = $dst$$reg; | |
| 3255 int base = $src0$$reg; // 0xFFFFFFFF indicates no base | |
| 3256 int index = 0x04; // 0x04 indicates no index | |
| 3257 int scale = 0x00; // 0x00 indicates no scale | |
| 3258 int displace = $src1$$constant; // 0x00 indicates no displacement | |
| 3259 bool disp_is_oop = false; | |
| 3260 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, | |
| 3261 disp_is_oop); | |
| 3262 %} | |
| 3263 | |
| 3264 enc_class neg_reg(rRegI dst) | |
| 3265 %{ | |
| 3266 int dstenc = $dst$$reg; | |
| 3267 if (dstenc >= 8) { | |
| 3268 emit_opcode(cbuf, Assembler::REX_B); | |
| 3269 dstenc -= 8; | |
| 3270 } | |
| 3271 // NEG $dst | |
| 3272 emit_opcode(cbuf, 0xF7); | |
| 3273 emit_rm(cbuf, 0x3, 0x03, dstenc); | |
| 3274 %} | |
| 3275 | |
| 3276 enc_class neg_reg_wide(rRegI dst) | |
| 3277 %{ | |
| 3278 int dstenc = $dst$$reg; | |
| 3279 if (dstenc < 8) { | |
| 3280 emit_opcode(cbuf, Assembler::REX_W); | |
| 3281 } else { | |
| 3282 emit_opcode(cbuf, Assembler::REX_WB); | |
| 3283 dstenc -= 8; | |
| 3284 } | |
| 3285 // NEG $dst | |
| 3286 emit_opcode(cbuf, 0xF7); | |
| 3287 emit_rm(cbuf, 0x3, 0x03, dstenc); | |
| 3288 %} | |
| 3289 | |
| 3290 enc_class setLT_reg(rRegI dst) | |
| 3291 %{ | |
| 3292 int dstenc = $dst$$reg; | |
| 3293 if (dstenc >= 8) { | |
| 3294 emit_opcode(cbuf, Assembler::REX_B); | |
| 3295 dstenc -= 8; | |
| 3296 } else if (dstenc >= 4) { | |
| 3297 emit_opcode(cbuf, Assembler::REX); | |
| 3298 } | |
| 3299 // SETLT $dst | |
| 3300 emit_opcode(cbuf, 0x0F); | |
| 3301 emit_opcode(cbuf, 0x9C); | |
| 3302 emit_rm(cbuf, 0x3, 0x0, dstenc); | |
| 3303 %} | |
| 3304 | |
| 3305 enc_class setNZ_reg(rRegI dst) | |
| 3306 %{ | |
| 3307 int dstenc = $dst$$reg; | |
| 3308 if (dstenc >= 8) { | |
| 3309 emit_opcode(cbuf, Assembler::REX_B); | |
| 3310 dstenc -= 8; | |
| 3311 } else if (dstenc >= 4) { | |
| 3312 emit_opcode(cbuf, Assembler::REX); | |
| 3313 } | |
| 3314 // SETNZ $dst | |
| 3315 emit_opcode(cbuf, 0x0F); | |
| 3316 emit_opcode(cbuf, 0x95); | |
| 3317 emit_rm(cbuf, 0x3, 0x0, dstenc); | |
| 3318 %} | |
| 3319 | |
| 3320 enc_class enc_cmpLTP(no_rcx_RegI p, no_rcx_RegI q, no_rcx_RegI y, | |
| 3321 rcx_RegI tmp) | |
| 3322 %{ | |
| 3323 // cadd_cmpLT | |
| 3324 | |
| 3325 int tmpReg = $tmp$$reg; | |
| 3326 | |
| 3327 int penc = $p$$reg; | |
| 3328 int qenc = $q$$reg; | |
| 3329 int yenc = $y$$reg; | |
| 3330 | |
| 3331 // subl $p,$q | |
| 3332 if (penc < 8) { | |
| 3333 if (qenc >= 8) { | |
| 3334 emit_opcode(cbuf, Assembler::REX_B); | |
| 3335 } | |
| 3336 } else { | |
| 3337 if (qenc < 8) { | |
| 3338 emit_opcode(cbuf, Assembler::REX_R); | |
| 3339 } else { | |
| 3340 emit_opcode(cbuf, Assembler::REX_RB); | |
| 3341 } | |
| 3342 } | |
| 3343 emit_opcode(cbuf, 0x2B); | |
| 3344 emit_rm(cbuf, 0x3, penc & 7, qenc & 7); | |
| 3345 | |
| 3346 // sbbl $tmp, $tmp | |
| 3347 emit_opcode(cbuf, 0x1B); | |
| 3348 emit_rm(cbuf, 0x3, tmpReg, tmpReg); | |
| 3349 | |
| 3350 // andl $tmp, $y | |
| 3351 if (yenc >= 8) { | |
| 3352 emit_opcode(cbuf, Assembler::REX_B); | |
| 3353 } | |
| 3354 emit_opcode(cbuf, 0x23); | |
| 3355 emit_rm(cbuf, 0x3, tmpReg, yenc & 7); | |
| 3356 | |
| 3357 // addl $p,$tmp | |
| 3358 if (penc >= 8) { | |
| 3359 emit_opcode(cbuf, Assembler::REX_R); | |
| 3360 } | |
| 3361 emit_opcode(cbuf, 0x03); | |
| 3362 emit_rm(cbuf, 0x3, penc & 7, tmpReg); | |
| 3363 %} | |
| 3364 | |
| 3365 // Compare the lonogs and set -1, 0, or 1 into dst | |
| 3366 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst) | |
| 3367 %{ | |
| 3368 int src1enc = $src1$$reg; | |
| 3369 int src2enc = $src2$$reg; | |
| 3370 int dstenc = $dst$$reg; | |
| 3371 | |
| 3372 // cmpq $src1, $src2 | |
| 3373 if (src1enc < 8) { | |
| 3374 if (src2enc < 8) { | |
| 3375 emit_opcode(cbuf, Assembler::REX_W); | |
| 3376 } else { | |
| 3377 emit_opcode(cbuf, Assembler::REX_WB); | |
| 3378 } | |
| 3379 } else { | |
| 3380 if (src2enc < 8) { | |
| 3381 emit_opcode(cbuf, Assembler::REX_WR); | |
| 3382 } else { | |
| 3383 emit_opcode(cbuf, Assembler::REX_WRB); | |
| 3384 } | |
| 3385 } | |
| 3386 emit_opcode(cbuf, 0x3B); | |
| 3387 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7); | |
| 3388 | |
| 3389 // movl $dst, -1 | |
| 3390 if (dstenc >= 8) { | |
| 3391 emit_opcode(cbuf, Assembler::REX_B); | |
| 3392 } | |
| 3393 emit_opcode(cbuf, 0xB8 | (dstenc & 7)); | |
| 3394 emit_d32(cbuf, -1); | |
| 3395 | |
| 3396 // jl,s done | |
| 3397 emit_opcode(cbuf, 0x7C); | |
| 3398 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08); | |
| 3399 | |
| 3400 // setne $dst | |
| 3401 if (dstenc >= 4) { | |
| 3402 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B); | |
| 3403 } | |
| 3404 emit_opcode(cbuf, 0x0F); | |
| 3405 emit_opcode(cbuf, 0x95); | |
| 3406 emit_opcode(cbuf, 0xC0 | (dstenc & 7)); | |
| 3407 | |
| 3408 // movzbl $dst, $dst | |
| 3409 if (dstenc >= 4) { | |
| 3410 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB); | |
| 3411 } | |
| 3412 emit_opcode(cbuf, 0x0F); | |
| 3413 emit_opcode(cbuf, 0xB6); | |
| 3414 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7); | |
| 3415 %} | |
| 3416 | |
| 3417 enc_class Push_ResultXD(regD dst) %{ | |
| 3418 int dstenc = $dst$$reg; | |
| 3419 | |
| 3420 store_to_stackslot( cbuf, 0xDD, 0x03, 0 ); //FSTP [RSP] | |
| 3421 | |
| 3422 // UseXmmLoadAndClearUpper ? movsd dst,[rsp] : movlpd dst,[rsp] | |
| 3423 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66); | |
| 3424 if (dstenc >= 8) { | |
| 3425 emit_opcode(cbuf, Assembler::REX_R); | |
| 3426 } | |
| 3427 emit_opcode (cbuf, 0x0F ); | |
| 3428 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12 ); | |
| 3429 encode_RegMem(cbuf, dstenc, RSP_enc, 0x4, 0, 0, false); | |
| 3430 | |
| 3431 // add rsp,8 | |
| 3432 emit_opcode(cbuf, Assembler::REX_W); | |
| 3433 emit_opcode(cbuf,0x83); | |
| 3434 emit_rm(cbuf,0x3, 0x0, RSP_enc); | |
| 3435 emit_d8(cbuf,0x08); | |
| 3436 %} | |
| 3437 | |
| 3438 enc_class Push_SrcXD(regD src) %{ | |
| 3439 int srcenc = $src$$reg; | |
| 3440 | |
| 3441 // subq rsp,#8 | |
| 3442 emit_opcode(cbuf, Assembler::REX_W); | |
| 3443 emit_opcode(cbuf, 0x83); | |
| 3444 emit_rm(cbuf, 0x3, 0x5, RSP_enc); | |
| 3445 emit_d8(cbuf, 0x8); | |
| 3446 | |
| 3447 // movsd [rsp],src | |
| 3448 emit_opcode(cbuf, 0xF2); | |
| 3449 if (srcenc >= 8) { | |
| 3450 emit_opcode(cbuf, Assembler::REX_R); | |
| 3451 } | |
| 3452 emit_opcode(cbuf, 0x0F); | |
| 3453 emit_opcode(cbuf, 0x11); | |
| 3454 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); | |
| 3455 | |
| 3456 // fldd [rsp] | |
| 3457 emit_opcode(cbuf, 0x66); | |
| 3458 emit_opcode(cbuf, 0xDD); | |
| 3459 encode_RegMem(cbuf, 0x0, RSP_enc, 0x4, 0, 0, false); | |
| 3460 %} | |
| 3461 | |
| 3462 | |
| 3463 enc_class movq_ld(regD dst, memory mem) %{ | |
| 3464 MacroAssembler _masm(&cbuf); | |
| 624 | 3465 __ movq($dst$$XMMRegister, $mem$$Address); |
| 0 | 3466 %} |
| 3467 | |
| 3468 enc_class movq_st(memory mem, regD src) %{ | |
| 3469 MacroAssembler _masm(&cbuf); | |
| 624 | 3470 __ movq($mem$$Address, $src$$XMMRegister); |
| 0 | 3471 %} |
| 3472 | |
| 3473 enc_class pshufd_8x8(regF dst, regF src) %{ | |
| 3474 MacroAssembler _masm(&cbuf); | |
| 3475 | |
| 3476 encode_CopyXD(cbuf, $dst$$reg, $src$$reg); | |
| 3477 __ punpcklbw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg)); | |
| 3478 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg), 0x00); | |
| 3479 %} | |
| 3480 | |
| 3481 enc_class pshufd_4x16(regF dst, regF src) %{ | |
| 3482 MacroAssembler _masm(&cbuf); | |
| 3483 | |
| 3484 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), 0x00); | |
| 3485 %} | |
| 3486 | |
| 3487 enc_class pshufd(regD dst, regD src, int mode) %{ | |
| 3488 MacroAssembler _masm(&cbuf); | |
| 3489 | |
| 3490 __ pshufd(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), $mode); | |
| 3491 %} | |
| 3492 | |
| 3493 enc_class pxor(regD dst, regD src) %{ | |
| 3494 MacroAssembler _masm(&cbuf); | |
| 3495 | |
| 3496 __ pxor(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg)); | |
| 3497 %} | |
| 3498 | |
| 3499 enc_class mov_i2x(regD dst, rRegI src) %{ | |
| 3500 MacroAssembler _masm(&cbuf); | |
| 3501 | |
| 3502 __ movdl(as_XMMRegister($dst$$reg), as_Register($src$$reg)); | |
| 3503 %} | |
| 3504 | |
| 3505 // obj: object to lock | |
| 3506 // box: box address (header location) -- killed | |
| 3507 // tmp: rax -- killed | |
| 3508 // scr: rbx -- killed | |
| 3509 // | |
| 3510 // What follows is a direct transliteration of fast_lock() and fast_unlock() | |
| 3511 // from i486.ad. See that file for comments. | |
| 3512 // TODO: where possible switch from movq (r, 0) to movl(r,0) and | |
| 3513 // use the shorter encoding. (Movl clears the high-order 32-bits). | |
| 3514 | |
| 3515 | |
| 3516 enc_class Fast_Lock(rRegP obj, rRegP box, rax_RegI tmp, rRegP scr) | |
| 3517 %{ | |
| 3518 Register objReg = as_Register((int)$obj$$reg); | |
| 3519 Register boxReg = as_Register((int)$box$$reg); | |
| 3520 Register tmpReg = as_Register($tmp$$reg); | |
| 3521 Register scrReg = as_Register($scr$$reg); | |
| 3522 MacroAssembler masm(&cbuf); | |
| 3523 | |
| 3524 // Verify uniqueness of register assignments -- necessary but not sufficient | |
| 3525 assert (objReg != boxReg && objReg != tmpReg && | |
| 3526 objReg != scrReg && tmpReg != scrReg, "invariant") ; | |
| 3527 | |
| 3528 if (_counters != NULL) { | |
| 3529 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr())); | |
| 3530 } | |
| 3531 if (EmitSync & 1) { | |
| 304 | 3532 // Without cast to int32_t a movptr will destroy r10 which is typically obj |
| 3533 masm.movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ; | |
| 3534 masm.cmpptr(rsp, (int32_t)NULL_WORD) ; | |
| 0 | 3535 } else |
| 3536 if (EmitSync & 2) { | |
| 3537 Label DONE_LABEL; | |
| 3538 if (UseBiasedLocking) { | |
| 3539 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument. | |
| 3540 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters); | |
| 3541 } | |
| 304 | 3542 // QQQ was movl... |
| 3543 masm.movptr(tmpReg, 0x1); | |
| 3544 masm.orptr(tmpReg, Address(objReg, 0)); | |
| 3545 masm.movptr(Address(boxReg, 0), tmpReg); | |
| 0 | 3546 if (os::is_MP()) { |
| 3547 masm.lock(); | |
| 3548 } | |
| 304 | 3549 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg |
| 0 | 3550 masm.jcc(Assembler::equal, DONE_LABEL); |
| 3551 | |
| 3552 // Recursive locking | |
| 304 | 3553 masm.subptr(tmpReg, rsp); |
| 3554 masm.andptr(tmpReg, 7 - os::vm_page_size()); | |
| 3555 masm.movptr(Address(boxReg, 0), tmpReg); | |
| 0 | 3556 |
| 3557 masm.bind(DONE_LABEL); | |
| 3558 masm.nop(); // avoid branch to branch | |
| 3559 } else { | |
| 3560 Label DONE_LABEL, IsInflated, Egress; | |
| 3561 | |
| 304 | 3562 masm.movptr(tmpReg, Address(objReg, 0)) ; |
| 3563 masm.testl (tmpReg, 0x02) ; // inflated vs stack-locked|neutral|biased | |
| 3564 masm.jcc (Assembler::notZero, IsInflated) ; | |
| 3565 | |
| 0 | 3566 // it's stack-locked, biased or neutral |
| 3567 // TODO: optimize markword triage order to reduce the number of | |
| 3568 // conditional branches in the most common cases. | |
| 3569 // Beware -- there's a subtle invariant that fetch of the markword | |
| 3570 // at [FETCH], below, will never observe a biased encoding (*101b). | |
| 3571 // If this invariant is not held we'll suffer exclusion (safety) failure. | |
| 3572 | |
|
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|
3573 if (UseBiasedLocking && !UseOptoBiasInlining) { |
| 0 | 3574 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, true, DONE_LABEL, NULL, _counters); |
| 304 | 3575 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH] |
| 0 | 3576 } |
| 3577 | |
| 304 | 3578 // was q will it destroy high? |
| 3579 masm.orl (tmpReg, 1) ; | |
| 3580 masm.movptr(Address(boxReg, 0), tmpReg) ; | |
| 3581 if (os::is_MP()) { masm.lock(); } | |
| 3582 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg | |
| 0 | 3583 if (_counters != NULL) { |
| 3584 masm.cond_inc32(Assembler::equal, | |
| 3585 ExternalAddress((address) _counters->fast_path_entry_count_addr())); | |
| 3586 } | |
| 3587 masm.jcc (Assembler::equal, DONE_LABEL); | |
| 3588 | |
| 3589 // Recursive locking | |
| 304 | 3590 masm.subptr(tmpReg, rsp); |
| 3591 masm.andptr(tmpReg, 7 - os::vm_page_size()); | |
| 3592 masm.movptr(Address(boxReg, 0), tmpReg); | |
| 0 | 3593 if (_counters != NULL) { |
| 3594 masm.cond_inc32(Assembler::equal, | |
| 3595 ExternalAddress((address) _counters->fast_path_entry_count_addr())); | |
| 3596 } | |
| 3597 masm.jmp (DONE_LABEL) ; | |
| 3598 | |
| 3599 masm.bind (IsInflated) ; | |
| 3600 // It's inflated | |
| 3601 | |
| 3602 // TODO: someday avoid the ST-before-CAS penalty by | |
| 3603 // relocating (deferring) the following ST. | |
| 3604 // We should also think about trying a CAS without having | |
| 3605 // fetched _owner. If the CAS is successful we may | |
| 3606 // avoid an RTO->RTS upgrade on the $line. | |
| 304 | 3607 // Without cast to int32_t a movptr will destroy r10 which is typically obj |
| 3608 masm.movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ; | |
| 3609 | |
| 3610 masm.mov (boxReg, tmpReg) ; | |
| 3611 masm.movptr (tmpReg, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; | |
| 3612 masm.testptr(tmpReg, tmpReg) ; | |
| 3613 masm.jcc (Assembler::notZero, DONE_LABEL) ; | |
| 0 | 3614 |
| 3615 // It's inflated and appears unlocked | |
| 304 | 3616 if (os::is_MP()) { masm.lock(); } |
| 3617 masm.cmpxchgptr(r15_thread, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; | |
| 0 | 3618 // Intentional fall-through into DONE_LABEL ... |
| 3619 | |
| 3620 masm.bind (DONE_LABEL) ; | |
| 3621 masm.nop () ; // avoid jmp to jmp | |
| 3622 } | |
| 3623 %} | |
| 3624 | |
| 3625 // obj: object to unlock | |
| 3626 // box: box address (displaced header location), killed | |
| 3627 // RBX: killed tmp; cannot be obj nor box | |
| 3628 enc_class Fast_Unlock(rRegP obj, rax_RegP box, rRegP tmp) | |
| 3629 %{ | |
| 3630 | |
| 3631 Register objReg = as_Register($obj$$reg); | |
| 3632 Register boxReg = as_Register($box$$reg); | |
| 3633 Register tmpReg = as_Register($tmp$$reg); | |
| 3634 MacroAssembler masm(&cbuf); | |
| 3635 | |
| 304 | 3636 if (EmitSync & 4) { |
| 3637 masm.cmpptr(rsp, 0) ; | |
| 0 | 3638 } else |
| 3639 if (EmitSync & 8) { | |
| 3640 Label DONE_LABEL; | |
| 3641 if (UseBiasedLocking) { | |
| 3642 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); | |
| 3643 } | |
| 3644 | |
| 3645 // Check whether the displaced header is 0 | |
| 3646 //(=> recursive unlock) | |
| 304 | 3647 masm.movptr(tmpReg, Address(boxReg, 0)); |
| 3648 masm.testptr(tmpReg, tmpReg); | |
| 0 | 3649 masm.jcc(Assembler::zero, DONE_LABEL); |
| 3650 | |
| 3651 // If not recursive lock, reset the header to displaced header | |
| 3652 if (os::is_MP()) { | |
| 3653 masm.lock(); | |
| 3654 } | |
| 304 | 3655 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box |
| 0 | 3656 masm.bind(DONE_LABEL); |
| 3657 masm.nop(); // avoid branch to branch | |
| 3658 } else { | |
| 3659 Label DONE_LABEL, Stacked, CheckSucc ; | |
| 3660 | |
|
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parents:
415
diff
changeset
|
3661 if (UseBiasedLocking && !UseOptoBiasInlining) { |
| 0 | 3662 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); |
| 3663 } | |
| 304 | 3664 |
| 3665 masm.movptr(tmpReg, Address(objReg, 0)) ; | |
| 3666 masm.cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD) ; | |
| 3667 masm.jcc (Assembler::zero, DONE_LABEL) ; | |
| 3668 masm.testl (tmpReg, 0x02) ; | |
| 3669 masm.jcc (Assembler::zero, Stacked) ; | |
| 3670 | |
| 0 | 3671 // It's inflated |
| 304 | 3672 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
| 3673 masm.xorptr(boxReg, r15_thread) ; | |
| 3674 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ; | |
| 3675 masm.jcc (Assembler::notZero, DONE_LABEL) ; | |
| 3676 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ; | |
| 3677 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ; | |
| 3678 masm.jcc (Assembler::notZero, CheckSucc) ; | |
| 3679 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ; | |
| 3680 masm.jmp (DONE_LABEL) ; | |
| 3681 | |
| 3682 if ((EmitSync & 65536) == 0) { | |
| 0 | 3683 Label LSuccess, LGoSlowPath ; |
| 3684 masm.bind (CheckSucc) ; | |
| 304 | 3685 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ; |
| 0 | 3686 masm.jcc (Assembler::zero, LGoSlowPath) ; |
| 3687 | |
| 3688 // I'd much rather use lock:andl m->_owner, 0 as it's faster than the | |
| 3689 // the explicit ST;MEMBAR combination, but masm doesn't currently support | |
| 3690 // "ANDQ M,IMM". Don't use MFENCE here. lock:add to TOS, xchg, etc | |
| 3691 // are all faster when the write buffer is populated. | |
| 304 | 3692 masm.movptr (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ; |
| 0 | 3693 if (os::is_MP()) { |
| 304 | 3694 masm.lock () ; masm.addl (Address(rsp, 0), 0) ; |
| 0 | 3695 } |
| 304 | 3696 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ; |
| 0 | 3697 masm.jcc (Assembler::notZero, LSuccess) ; |
| 3698 | |
| 304 | 3699 masm.movptr (boxReg, (int32_t)NULL_WORD) ; // box is really EAX |
| 0 | 3700 if (os::is_MP()) { masm.lock(); } |
| 304 | 3701 masm.cmpxchgptr(r15_thread, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)); |
| 0 | 3702 masm.jcc (Assembler::notEqual, LSuccess) ; |
| 3703 // Intentional fall-through into slow-path | |
| 3704 | |
| 3705 masm.bind (LGoSlowPath) ; | |
| 3706 masm.orl (boxReg, 1) ; // set ICC.ZF=0 to indicate failure | |
| 3707 masm.jmp (DONE_LABEL) ; | |
| 3708 | |
| 3709 masm.bind (LSuccess) ; | |
| 3710 masm.testl (boxReg, 0) ; // set ICC.ZF=1 to indicate success | |
| 3711 masm.jmp (DONE_LABEL) ; | |
| 3712 } | |
| 3713 | |
| 304 | 3714 masm.bind (Stacked) ; |
| 3715 masm.movptr(tmpReg, Address (boxReg, 0)) ; // re-fetch | |
| 3716 if (os::is_MP()) { masm.lock(); } | |
| 3717 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box | |
| 0 | 3718 |
| 3719 if (EmitSync & 65536) { | |
| 3720 masm.bind (CheckSucc) ; | |
| 3721 } | |
| 3722 masm.bind(DONE_LABEL); | |
| 3723 if (EmitSync & 32768) { | |
| 3724 masm.nop(); // avoid branch to branch | |
| 3725 } | |
| 3726 } | |
| 3727 %} | |
| 3728 | |
| 3729 enc_class enc_String_Compare() | |
| 3730 %{ | |
| 3731 Label RCX_GOOD_LABEL, LENGTH_DIFF_LABEL, | |
| 3732 POP_LABEL, DONE_LABEL, CONT_LABEL, | |
| 3733 WHILE_HEAD_LABEL; | |
| 3734 MacroAssembler masm(&cbuf); | |
| 3735 | |
| 3736 // Get the first character position in both strings | |
| 3737 // [8] char array, [12] offset, [16] count | |
| 3738 int value_offset = java_lang_String::value_offset_in_bytes(); | |
| 3739 int offset_offset = java_lang_String::offset_offset_in_bytes(); | |
| 3740 int count_offset = java_lang_String::count_offset_in_bytes(); | |
| 3741 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); | |
| 3742 | |
|
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3743 masm.load_heap_oop(rax, Address(rsi, value_offset)); |
| 0 | 3744 masm.movl(rcx, Address(rsi, offset_offset)); |
| 304 | 3745 masm.lea(rax, Address(rax, rcx, Address::times_2, base_offset)); |
|
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3746 masm.load_heap_oop(rbx, Address(rdi, value_offset)); |
| 0 | 3747 masm.movl(rcx, Address(rdi, offset_offset)); |
| 304 | 3748 masm.lea(rbx, Address(rbx, rcx, Address::times_2, base_offset)); |
| 0 | 3749 |
| 3750 // Compute the minimum of the string lengths(rsi) and the | |
| 3751 // difference of the string lengths (stack) | |
| 3752 | |
| 3753 masm.movl(rdi, Address(rdi, count_offset)); | |
| 3754 masm.movl(rsi, Address(rsi, count_offset)); | |
| 3755 masm.movl(rcx, rdi); | |
| 3756 masm.subl(rdi, rsi); | |
| 304 | 3757 masm.push(rdi); |
| 3758 masm.cmov(Assembler::lessEqual, rsi, rcx); | |
| 0 | 3759 |
| 3760 // Is the minimum length zero? | |
| 3761 masm.bind(RCX_GOOD_LABEL); | |
| 3762 masm.testl(rsi, rsi); | |
| 3763 masm.jcc(Assembler::zero, LENGTH_DIFF_LABEL); | |
| 3764 | |
| 3765 // Load first characters | |
|
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3766 masm.load_unsigned_short(rcx, Address(rbx, 0)); |
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3767 masm.load_unsigned_short(rdi, Address(rax, 0)); |
| 0 | 3768 |
| 3769 // Compare first characters | |
| 3770 masm.subl(rcx, rdi); | |
| 3771 masm.jcc(Assembler::notZero, POP_LABEL); | |
| 3772 masm.decrementl(rsi); | |
| 3773 masm.jcc(Assembler::zero, LENGTH_DIFF_LABEL); | |
| 3774 | |
| 3775 { | |
| 3776 // Check after comparing first character to see if strings are equivalent | |
| 3777 Label LSkip2; | |
| 3778 // Check if the strings start at same location | |
| 304 | 3779 masm.cmpptr(rbx, rax); |
| 0 | 3780 masm.jcc(Assembler::notEqual, LSkip2); |
| 3781 | |
| 3782 // Check if the length difference is zero (from stack) | |
| 3783 masm.cmpl(Address(rsp, 0), 0x0); | |
| 3784 masm.jcc(Assembler::equal, LENGTH_DIFF_LABEL); | |
| 3785 | |
| 3786 // Strings might not be equivalent | |
| 3787 masm.bind(LSkip2); | |
| 3788 } | |
| 3789 | |
| 3790 // Shift RAX and RBX to the end of the arrays, negate min | |
| 304 | 3791 masm.lea(rax, Address(rax, rsi, Address::times_2, 2)); |
| 3792 masm.lea(rbx, Address(rbx, rsi, Address::times_2, 2)); | |
| 3793 masm.negptr(rsi); | |
| 0 | 3794 |
| 3795 // Compare the rest of the characters | |
| 3796 masm.bind(WHILE_HEAD_LABEL); | |
|
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3797 masm.load_unsigned_short(rcx, Address(rbx, rsi, Address::times_2, 0)); |
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3798 masm.load_unsigned_short(rdi, Address(rax, rsi, Address::times_2, 0)); |
| 0 | 3799 masm.subl(rcx, rdi); |
| 3800 masm.jcc(Assembler::notZero, POP_LABEL); | |
| 304 | 3801 masm.increment(rsi); |
| 0 | 3802 masm.jcc(Assembler::notZero, WHILE_HEAD_LABEL); |
| 3803 | |
| 3804 // Strings are equal up to min length. Return the length difference. | |
| 3805 masm.bind(LENGTH_DIFF_LABEL); | |
| 304 | 3806 masm.pop(rcx); |
| 0 | 3807 masm.jmp(DONE_LABEL); |
| 3808 | |
| 3809 // Discard the stored length difference | |
| 3810 masm.bind(POP_LABEL); | |
| 304 | 3811 masm.addptr(rsp, 8); |
| 3812 | |
| 0 | 3813 // That's it |
| 3814 masm.bind(DONE_LABEL); | |
| 3815 %} | |
| 3816 | |
|
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3817 enc_class enc_Array_Equals(rdi_RegP ary1, rsi_RegP ary2, rax_RegI tmp1, rbx_RegI tmp2, rcx_RegI result) %{ |
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3818 Label TRUE_LABEL, FALSE_LABEL, DONE_LABEL, COMPARE_LOOP_HDR, COMPARE_LOOP; |
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3819 MacroAssembler masm(&cbuf); |
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3820 |
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3821 Register ary1Reg = as_Register($ary1$$reg); |
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3822 Register ary2Reg = as_Register($ary2$$reg); |
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3823 Register tmp1Reg = as_Register($tmp1$$reg); |
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3824 Register tmp2Reg = as_Register($tmp2$$reg); |
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3825 Register resultReg = as_Register($result$$reg); |
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3826 |
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3827 int length_offset = arrayOopDesc::length_offset_in_bytes(); |
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3828 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); |
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3829 |
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3830 // Check the input args |
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3831 masm.cmpq(ary1Reg, ary2Reg); |
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3832 masm.jcc(Assembler::equal, TRUE_LABEL); |
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3833 masm.testq(ary1Reg, ary1Reg); |
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3834 masm.jcc(Assembler::zero, FALSE_LABEL); |
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3835 masm.testq(ary2Reg, ary2Reg); |
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3836 masm.jcc(Assembler::zero, FALSE_LABEL); |
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3837 |
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3838 // Check the lengths |
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3839 masm.movl(tmp2Reg, Address(ary1Reg, length_offset)); |
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3840 masm.movl(resultReg, Address(ary2Reg, length_offset)); |
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3841 masm.cmpl(tmp2Reg, resultReg); |
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3842 masm.jcc(Assembler::notEqual, FALSE_LABEL); |
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3843 masm.testl(resultReg, resultReg); |
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3844 masm.jcc(Assembler::zero, TRUE_LABEL); |
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3845 |
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3846 // Get the number of 4 byte vectors to compare |
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3847 masm.shrl(resultReg, 1); |
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3848 |
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3849 // Check for odd-length arrays |
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3850 masm.andl(tmp2Reg, 1); |
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3851 masm.testl(tmp2Reg, tmp2Reg); |
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3852 masm.jcc(Assembler::zero, COMPARE_LOOP_HDR); |
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3853 |
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3854 // Compare 2-byte "tail" at end of arrays |
|
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3855 masm.load_unsigned_short(tmp1Reg, Address(ary1Reg, resultReg, Address::times_4, base_offset)); |
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3856 masm.load_unsigned_short(tmp2Reg, Address(ary2Reg, resultReg, Address::times_4, base_offset)); |
|
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3857 masm.cmpl(tmp1Reg, tmp2Reg); |
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3858 masm.jcc(Assembler::notEqual, FALSE_LABEL); |
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3859 masm.testl(resultReg, resultReg); |
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3860 masm.jcc(Assembler::zero, TRUE_LABEL); |
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3861 |
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3862 // Setup compare loop |
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3863 masm.bind(COMPARE_LOOP_HDR); |
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3864 // Shift tmp1Reg and tmp2Reg to the last 4-byte boundary of the arrays |
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3865 masm.leaq(tmp1Reg, Address(ary1Reg, resultReg, Address::times_4, base_offset)); |
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3866 masm.leaq(tmp2Reg, Address(ary2Reg, resultReg, Address::times_4, base_offset)); |
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3867 masm.negq(resultReg); |
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3868 |
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3869 // 4-byte-wide compare loop |
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3870 masm.bind(COMPARE_LOOP); |
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3871 masm.movl(ary1Reg, Address(tmp1Reg, resultReg, Address::times_4, 0)); |
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3872 masm.movl(ary2Reg, Address(tmp2Reg, resultReg, Address::times_4, 0)); |
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3873 masm.cmpl(ary1Reg, ary2Reg); |
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3874 masm.jcc(Assembler::notEqual, FALSE_LABEL); |
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3875 masm.incrementq(resultReg); |
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3876 masm.jcc(Assembler::notZero, COMPARE_LOOP); |
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3877 |
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3878 masm.bind(TRUE_LABEL); |
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3879 masm.movl(resultReg, 1); // return true |
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3880 masm.jmp(DONE_LABEL); |
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3881 |
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3882 masm.bind(FALSE_LABEL); |
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3883 masm.xorl(resultReg, resultReg); // return false |
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3884 |
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3885 // That's it |
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3886 masm.bind(DONE_LABEL); |
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3887 %} |
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3888 |
| 0 | 3889 enc_class enc_rethrow() |
| 3890 %{ | |
| 3891 cbuf.set_inst_mark(); | |
| 3892 emit_opcode(cbuf, 0xE9); // jmp entry | |
| 3893 emit_d32_reloc(cbuf, | |
| 3894 (int) (OptoRuntime::rethrow_stub() - cbuf.code_end() - 4), | |
| 3895 runtime_call_Relocation::spec(), | |
| 3896 RELOC_DISP32); | |
| 3897 %} | |
| 3898 | |
| 3899 enc_class absF_encoding(regF dst) | |
| 3900 %{ | |
| 3901 int dstenc = $dst$$reg; | |
| 304 | 3902 address signmask_address = (address) StubRoutines::x86::float_sign_mask(); |
| 0 | 3903 |
| 3904 cbuf.set_inst_mark(); | |
| 3905 if (dstenc >= 8) { | |
| 3906 emit_opcode(cbuf, Assembler::REX_R); | |
| 3907 dstenc -= 8; | |
| 3908 } | |
| 3909 // XXX reg_mem doesn't support RIP-relative addressing yet | |
| 3910 emit_opcode(cbuf, 0x0F); | |
| 3911 emit_opcode(cbuf, 0x54); | |
| 3912 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101 | |
| 3913 emit_d32_reloc(cbuf, signmask_address); | |
| 3914 %} | |
| 3915 | |
| 3916 enc_class absD_encoding(regD dst) | |
| 3917 %{ | |
| 3918 int dstenc = $dst$$reg; | |
| 304 | 3919 address signmask_address = (address) StubRoutines::x86::double_sign_mask(); |
| 0 | 3920 |
| 3921 cbuf.set_inst_mark(); | |
| 3922 emit_opcode(cbuf, 0x66); | |
| 3923 if (dstenc >= 8) { | |
| 3924 emit_opcode(cbuf, Assembler::REX_R); | |
| 3925 dstenc -= 8; | |
| 3926 } | |
| 3927 // XXX reg_mem doesn't support RIP-relative addressing yet | |
| 3928 emit_opcode(cbuf, 0x0F); | |
| 3929 emit_opcode(cbuf, 0x54); | |
| 3930 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101 | |
| 3931 emit_d32_reloc(cbuf, signmask_address); | |
| 3932 %} | |
| 3933 | |
| 3934 enc_class negF_encoding(regF dst) | |
| 3935 %{ | |
| 3936 int dstenc = $dst$$reg; | |
| 304 | 3937 address signflip_address = (address) StubRoutines::x86::float_sign_flip(); |
| 0 | 3938 |
| 3939 cbuf.set_inst_mark(); | |
| 3940 if (dstenc >= 8) { | |
| 3941 emit_opcode(cbuf, Assembler::REX_R); | |
| 3942 dstenc -= 8; | |
| 3943 } | |
| 3944 // XXX reg_mem doesn't support RIP-relative addressing yet | |
| 3945 emit_opcode(cbuf, 0x0F); | |
| 3946 emit_opcode(cbuf, 0x57); | |
| 3947 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101 | |
| 3948 emit_d32_reloc(cbuf, signflip_address); | |
| 3949 %} | |
| 3950 | |
| 3951 enc_class negD_encoding(regD dst) | |
| 3952 %{ | |
| 3953 int dstenc = $dst$$reg; | |
| 304 | 3954 address signflip_address = (address) StubRoutines::x86::double_sign_flip(); |
| 0 | 3955 |
| 3956 cbuf.set_inst_mark(); | |
| 3957 emit_opcode(cbuf, 0x66); | |
| 3958 if (dstenc >= 8) { | |
| 3959 emit_opcode(cbuf, Assembler::REX_R); | |
| 3960 dstenc -= 8; | |
| 3961 } | |
| 3962 // XXX reg_mem doesn't support RIP-relative addressing yet | |
| 3963 emit_opcode(cbuf, 0x0F); | |
| 3964 emit_opcode(cbuf, 0x57); | |
| 3965 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101 | |
| 3966 emit_d32_reloc(cbuf, signflip_address); | |
| 3967 %} | |
| 3968 | |
| 3969 enc_class f2i_fixup(rRegI dst, regF src) | |
| 3970 %{ | |
| 3971 int dstenc = $dst$$reg; | |
| 3972 int srcenc = $src$$reg; | |
| 3973 | |
| 3974 // cmpl $dst, #0x80000000 | |
| 3975 if (dstenc >= 8) { | |
| 3976 emit_opcode(cbuf, Assembler::REX_B); | |
| 3977 } | |
| 3978 emit_opcode(cbuf, 0x81); | |
| 3979 emit_rm(cbuf, 0x3, 0x7, dstenc & 7); | |
| 3980 emit_d32(cbuf, 0x80000000); | |
| 3981 | |
| 3982 // jne,s done | |
| 3983 emit_opcode(cbuf, 0x75); | |
| 3984 if (srcenc < 8 && dstenc < 8) { | |
| 3985 emit_d8(cbuf, 0xF); | |
| 3986 } else if (srcenc >= 8 && dstenc >= 8) { | |
| 3987 emit_d8(cbuf, 0x11); | |
| 3988 } else { | |
| 3989 emit_d8(cbuf, 0x10); | |
| 3990 } | |
| 3991 | |
| 3992 // subq rsp, #8 | |
| 3993 emit_opcode(cbuf, Assembler::REX_W); | |
| 3994 emit_opcode(cbuf, 0x83); | |
| 3995 emit_rm(cbuf, 0x3, 0x5, RSP_enc); | |
| 3996 emit_d8(cbuf, 8); | |
| 3997 | |
| 3998 // movss [rsp], $src | |
| 3999 emit_opcode(cbuf, 0xF3); | |
| 4000 if (srcenc >= 8) { | |
| 4001 emit_opcode(cbuf, Assembler::REX_R); | |
| 4002 } | |
| 4003 emit_opcode(cbuf, 0x0F); | |
| 4004 emit_opcode(cbuf, 0x11); | |
| 4005 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes | |
| 4006 | |
| 4007 // call f2i_fixup | |
| 4008 cbuf.set_inst_mark(); | |
| 4009 emit_opcode(cbuf, 0xE8); | |
| 4010 emit_d32_reloc(cbuf, | |
| 4011 (int) | |
| 304 | 4012 (StubRoutines::x86::f2i_fixup() - cbuf.code_end() - 4), |
| 0 | 4013 runtime_call_Relocation::spec(), |
| 4014 RELOC_DISP32); | |
| 4015 | |
| 4016 // popq $dst | |
| 4017 if (dstenc >= 8) { | |
| 4018 emit_opcode(cbuf, Assembler::REX_B); | |
| 4019 } | |
| 4020 emit_opcode(cbuf, 0x58 | (dstenc & 7)); | |
| 4021 | |
| 4022 // done: | |
| 4023 %} | |
| 4024 | |
| 4025 enc_class f2l_fixup(rRegL dst, regF src) | |
| 4026 %{ | |
| 4027 int dstenc = $dst$$reg; | |
| 4028 int srcenc = $src$$reg; | |
| 304 | 4029 address const_address = (address) StubRoutines::x86::double_sign_flip(); |
| 0 | 4030 |
| 4031 // cmpq $dst, [0x8000000000000000] | |
| 4032 cbuf.set_inst_mark(); | |
| 4033 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX_W : Assembler::REX_WR); | |
| 4034 emit_opcode(cbuf, 0x39); | |
| 4035 // XXX reg_mem doesn't support RIP-relative addressing yet | |
| 4036 emit_rm(cbuf, 0x0, dstenc & 7, 0x5); // 00 reg 101 | |
| 4037 emit_d32_reloc(cbuf, const_address); | |
| 4038 | |
| 4039 | |
| 4040 // jne,s done | |
| 4041 emit_opcode(cbuf, 0x75); | |
| 4042 if (srcenc < 8 && dstenc < 8) { | |
| 4043 emit_d8(cbuf, 0xF); | |
| 4044 } else if (srcenc >= 8 && dstenc >= 8) { | |
| 4045 emit_d8(cbuf, 0x11); | |
| 4046 } else { | |
| 4047 emit_d8(cbuf, 0x10); | |
| 4048 } | |
| 4049 | |
| 4050 // subq rsp, #8 | |
| 4051 emit_opcode(cbuf, Assembler::REX_W); | |
| 4052 emit_opcode(cbuf, 0x83); | |
| 4053 emit_rm(cbuf, 0x3, 0x5, RSP_enc); | |
| 4054 emit_d8(cbuf, 8); | |
| 4055 | |
| 4056 // movss [rsp], $src | |
| 4057 emit_opcode(cbuf, 0xF3); | |
| 4058 if (srcenc >= 8) { | |
| 4059 emit_opcode(cbuf, Assembler::REX_R); | |
| 4060 } | |
| 4061 emit_opcode(cbuf, 0x0F); | |
| 4062 emit_opcode(cbuf, 0x11); | |
| 4063 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes | |
| 4064 | |
| 4065 // call f2l_fixup | |
| 4066 cbuf.set_inst_mark(); | |
| 4067 emit_opcode(cbuf, 0xE8); | |
| 4068 emit_d32_reloc(cbuf, | |
| 4069 (int) | |
| 304 | 4070 (StubRoutines::x86::f2l_fixup() - cbuf.code_end() - 4), |
| 0 | 4071 runtime_call_Relocation::spec(), |
| 4072 RELOC_DISP32); | |
| 4073 | |
| 4074 // popq $dst | |
| 4075 if (dstenc >= 8) { | |
| 4076 emit_opcode(cbuf, Assembler::REX_B); | |
| 4077 } | |
| 4078 emit_opcode(cbuf, 0x58 | (dstenc & 7)); | |
| 4079 | |
| 4080 // done: | |
| 4081 %} | |
| 4082 | |
| 4083 enc_class d2i_fixup(rRegI dst, regD src) | |
| 4084 %{ | |
| 4085 int dstenc = $dst$$reg; | |
| 4086 int srcenc = $src$$reg; | |
| 4087 | |
| 4088 // cmpl $dst, #0x80000000 | |
| 4089 if (dstenc >= 8) { | |
| 4090 emit_opcode(cbuf, Assembler::REX_B); | |
| 4091 } | |
| 4092 emit_opcode(cbuf, 0x81); | |
| 4093 emit_rm(cbuf, 0x3, 0x7, dstenc & 7); | |
| 4094 emit_d32(cbuf, 0x80000000); | |
| 4095 | |
| 4096 // jne,s done | |
| 4097 emit_opcode(cbuf, 0x75); | |
| 4098 if (srcenc < 8 && dstenc < 8) { | |
| 4099 emit_d8(cbuf, 0xF); | |
| 4100 } else if (srcenc >= 8 && dstenc >= 8) { | |
| 4101 emit_d8(cbuf, 0x11); | |
| 4102 } else { | |
| 4103 emit_d8(cbuf, 0x10); | |
| 4104 } | |
| 4105 | |
| 4106 // subq rsp, #8 | |
| 4107 emit_opcode(cbuf, Assembler::REX_W); | |
| 4108 emit_opcode(cbuf, 0x83); | |
| 4109 emit_rm(cbuf, 0x3, 0x5, RSP_enc); | |
| 4110 emit_d8(cbuf, 8); | |
| 4111 | |
| 4112 // movsd [rsp], $src | |
| 4113 emit_opcode(cbuf, 0xF2); | |
| 4114 if (srcenc >= 8) { | |
| 4115 emit_opcode(cbuf, Assembler::REX_R); | |
| 4116 } | |
| 4117 emit_opcode(cbuf, 0x0F); | |
| 4118 emit_opcode(cbuf, 0x11); | |
| 4119 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes | |
| 4120 | |
| 4121 // call d2i_fixup | |
| 4122 cbuf.set_inst_mark(); | |
| 4123 emit_opcode(cbuf, 0xE8); | |
| 4124 emit_d32_reloc(cbuf, | |
| 4125 (int) | |
| 304 | 4126 (StubRoutines::x86::d2i_fixup() - cbuf.code_end() - 4), |
| 0 | 4127 runtime_call_Relocation::spec(), |
| 4128 RELOC_DISP32); | |
| 4129 | |
| 4130 // popq $dst | |
| 4131 if (dstenc >= 8) { | |
| 4132 emit_opcode(cbuf, Assembler::REX_B); | |
| 4133 } | |
| 4134 emit_opcode(cbuf, 0x58 | (dstenc & 7)); | |
| 4135 | |
| 4136 // done: | |
| 4137 %} | |
| 4138 | |
| 4139 enc_class d2l_fixup(rRegL dst, regD src) | |
| 4140 %{ | |
| 4141 int dstenc = $dst$$reg; | |
| 4142 int srcenc = $src$$reg; | |
| 304 | 4143 address const_address = (address) StubRoutines::x86::double_sign_flip(); |
| 0 | 4144 |
| 4145 // cmpq $dst, [0x8000000000000000] | |
| 4146 cbuf.set_inst_mark(); | |
| 4147 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX_W : Assembler::REX_WR); | |
| 4148 emit_opcode(cbuf, 0x39); | |
| 4149 // XXX reg_mem doesn't support RIP-relative addressing yet | |
| 4150 emit_rm(cbuf, 0x0, dstenc & 7, 0x5); // 00 reg 101 | |
| 4151 emit_d32_reloc(cbuf, const_address); | |
| 4152 | |
| 4153 | |
| 4154 // jne,s done | |
| 4155 emit_opcode(cbuf, 0x75); | |
| 4156 if (srcenc < 8 && dstenc < 8) { | |
| 4157 emit_d8(cbuf, 0xF); | |
| 4158 } else if (srcenc >= 8 && dstenc >= 8) { | |
| 4159 emit_d8(cbuf, 0x11); | |
| 4160 } else { | |
| 4161 emit_d8(cbuf, 0x10); | |
| 4162 } | |
| 4163 | |
| 4164 // subq rsp, #8 | |
| 4165 emit_opcode(cbuf, Assembler::REX_W); | |
| 4166 emit_opcode(cbuf, 0x83); | |
| 4167 emit_rm(cbuf, 0x3, 0x5, RSP_enc); | |
| 4168 emit_d8(cbuf, 8); | |
| 4169 | |
| 4170 // movsd [rsp], $src | |
| 4171 emit_opcode(cbuf, 0xF2); | |
| 4172 if (srcenc >= 8) { | |
| 4173 emit_opcode(cbuf, Assembler::REX_R); | |
| 4174 } | |
| 4175 emit_opcode(cbuf, 0x0F); | |
| 4176 emit_opcode(cbuf, 0x11); | |
| 4177 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes | |
| 4178 | |
| 4179 // call d2l_fixup | |
| 4180 cbuf.set_inst_mark(); | |
| 4181 emit_opcode(cbuf, 0xE8); | |
| 4182 emit_d32_reloc(cbuf, | |
| 4183 (int) | |
| 304 | 4184 (StubRoutines::x86::d2l_fixup() - cbuf.code_end() - 4), |
| 0 | 4185 runtime_call_Relocation::spec(), |
| 4186 RELOC_DISP32); | |
| 4187 | |
| 4188 // popq $dst | |
| 4189 if (dstenc >= 8) { | |
| 4190 emit_opcode(cbuf, Assembler::REX_B); | |
| 4191 } | |
| 4192 emit_opcode(cbuf, 0x58 | (dstenc & 7)); | |
| 4193 | |
| 4194 // done: | |
| 4195 %} | |
| 4196 | |
| 4197 enc_class enc_membar_acquire | |
| 4198 %{ | |
| 4199 // [jk] not needed currently, if you enable this and it really | |
| 4200 // emits code don't forget to the remove the "size(0)" line in | |
| 4201 // membar_acquire() | |
| 4202 // MacroAssembler masm(&cbuf); | |
| 4203 // masm.membar(Assembler::Membar_mask_bits(Assembler::LoadStore | | |
| 4204 // Assembler::LoadLoad)); | |
| 4205 %} | |
| 4206 | |
| 4207 enc_class enc_membar_release | |
| 4208 %{ | |
| 4209 // [jk] not needed currently, if you enable this and it really | |
| 4210 // emits code don't forget to the remove the "size(0)" line in | |
| 4211 // membar_release() | |
| 4212 // MacroAssembler masm(&cbuf); | |
| 4213 // masm.membar(Assembler::Membar_mask_bits(Assembler::LoadStore | | |
| 4214 // Assembler::StoreStore)); | |
| 4215 %} | |
| 4216 | |
| 4217 enc_class enc_membar_volatile | |
| 4218 %{ | |
| 4219 MacroAssembler masm(&cbuf); | |
| 4220 masm.membar(Assembler::Membar_mask_bits(Assembler::StoreLoad | | |
| 4221 Assembler::StoreStore)); | |
| 4222 %} | |
| 4223 | |
| 4224 // Safepoint Poll. This polls the safepoint page, and causes an | |
| 4225 // exception if it is not readable. Unfortunately, it kills | |
| 4226 // RFLAGS in the process. | |
| 4227 enc_class enc_safepoint_poll | |
| 4228 %{ | |
| 4229 // testl %rax, off(%rip) // Opcode + ModRM + Disp32 == 6 bytes | |
| 4230 // XXX reg_mem doesn't support RIP-relative addressing yet | |
| 4231 cbuf.set_inst_mark(); | |
| 4232 cbuf.relocate(cbuf.inst_mark(), relocInfo::poll_type, 0); // XXX | |
| 4233 emit_opcode(cbuf, 0x85); // testl | |
| 4234 emit_rm(cbuf, 0x0, RAX_enc, 0x5); // 00 rax 101 == 0x5 | |
| 4235 // cbuf.inst_mark() is beginning of instruction | |
| 4236 emit_d32_reloc(cbuf, os::get_polling_page()); | |
| 4237 // relocInfo::poll_type, | |
| 4238 %} | |
| 4239 %} | |
| 4240 | |
| 4241 | |
|
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|
4242 |
| 0 | 4243 //----------FRAME-------------------------------------------------------------- |
| 4244 // Definition of frame structure and management information. | |
| 4245 // | |
| 4246 // S T A C K L A Y O U T Allocators stack-slot number | |
| 4247 // | (to get allocators register number | |
| 4248 // G Owned by | | v add OptoReg::stack0()) | |
| 4249 // r CALLER | | | |
| 4250 // o | +--------+ pad to even-align allocators stack-slot | |
| 4251 // w V | pad0 | numbers; owned by CALLER | |
| 4252 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned | |
| 4253 // h ^ | in | 5 | |
| 4254 // | | args | 4 Holes in incoming args owned by SELF | |
| 4255 // | | | | 3 | |
| 4256 // | | +--------+ | |
| 4257 // V | | old out| Empty on Intel, window on Sparc | |
| 4258 // | old |preserve| Must be even aligned. | |
| 4259 // | SP-+--------+----> Matcher::_old_SP, even aligned | |
| 4260 // | | in | 3 area for Intel ret address | |
| 4261 // Owned by |preserve| Empty on Sparc. | |
| 4262 // SELF +--------+ | |
| 4263 // | | pad2 | 2 pad to align old SP | |
| 4264 // | +--------+ 1 | |
| 4265 // | | locks | 0 | |
| 4266 // | +--------+----> OptoReg::stack0(), even aligned | |
| 4267 // | | pad1 | 11 pad to align new SP | |
| 4268 // | +--------+ | |
| 4269 // | | | 10 | |
| 4270 // | | spills | 9 spills | |
| 4271 // V | | 8 (pad0 slot for callee) | |
| 4272 // -----------+--------+----> Matcher::_out_arg_limit, unaligned | |
| 4273 // ^ | out | 7 | |
| 4274 // | | args | 6 Holes in outgoing args owned by CALLEE | |
| 4275 // Owned by +--------+ | |
| 4276 // CALLEE | new out| 6 Empty on Intel, window on Sparc | |
| 4277 // | new |preserve| Must be even-aligned. | |
| 4278 // | SP-+--------+----> Matcher::_new_SP, even aligned | |
| 4279 // | | | | |
| 4280 // | |
| 4281 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is | |
| 4282 // known from SELF's arguments and the Java calling convention. | |
| 4283 // Region 6-7 is determined per call site. | |
| 4284 // Note 2: If the calling convention leaves holes in the incoming argument | |
| 4285 // area, those holes are owned by SELF. Holes in the outgoing area | |
| 4286 // are owned by the CALLEE. Holes should not be nessecary in the | |
| 4287 // incoming area, as the Java calling convention is completely under | |
| 4288 // the control of the AD file. Doubles can be sorted and packed to | |
| 4289 // avoid holes. Holes in the outgoing arguments may be nessecary for | |
| 4290 // varargs C calling conventions. | |
| 4291 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is | |
| 4292 // even aligned with pad0 as needed. | |
| 4293 // Region 6 is even aligned. Region 6-7 is NOT even aligned; | |
| 4294 // region 6-11 is even aligned; it may be padded out more so that | |
| 4295 // the region from SP to FP meets the minimum stack alignment. | |
| 4296 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack | |
| 4297 // alignment. Region 11, pad1, may be dynamically extended so that | |
| 4298 // SP meets the minimum alignment. | |
| 4299 | |
| 4300 frame | |
| 4301 %{ | |
| 4302 // What direction does stack grow in (assumed to be same for C & Java) | |
| 4303 stack_direction(TOWARDS_LOW); | |
| 4304 | |
| 4305 // These three registers define part of the calling convention | |
| 4306 // between compiled code and the interpreter. | |
| 4307 inline_cache_reg(RAX); // Inline Cache Register | |
| 4308 interpreter_method_oop_reg(RBX); // Method Oop Register when | |
| 4309 // calling interpreter | |
| 4310 | |
| 4311 // Optional: name the operand used by cisc-spilling to access | |
| 4312 // [stack_pointer + offset] | |
| 4313 cisc_spilling_operand_name(indOffset32); | |
| 4314 | |
| 4315 // Number of stack slots consumed by locking an object | |
| 4316 sync_stack_slots(2); | |
| 4317 | |
| 4318 // Compiled code's Frame Pointer | |
| 4319 frame_pointer(RSP); | |
| 4320 | |
| 4321 // Interpreter stores its frame pointer in a register which is | |
| 4322 // stored to the stack by I2CAdaptors. | |
| 4323 // I2CAdaptors convert from interpreted java to compiled java. | |
| 4324 interpreter_frame_pointer(RBP); | |
| 4325 | |
| 4326 // Stack alignment requirement | |
| 4327 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes) | |
| 4328 | |
| 4329 // Number of stack slots between incoming argument block and the start of | |
| 4330 // a new frame. The PROLOG must add this many slots to the stack. The | |
| 4331 // EPILOG must remove this many slots. amd64 needs two slots for | |
| 4332 // return address. | |
| 4333 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls); | |
| 4334 | |
| 4335 // Number of outgoing stack slots killed above the out_preserve_stack_slots | |
| 4336 // for calls to C. Supports the var-args backing area for register parms. | |
| 4337 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt); | |
| 4338 | |
| 4339 // The after-PROLOG location of the return address. Location of | |
| 4340 // return address specifies a type (REG or STACK) and a number | |
| 4341 // representing the register number (i.e. - use a register name) or | |
| 4342 // stack slot. | |
| 4343 // Ret Addr is on stack in slot 0 if no locks or verification or alignment. | |
| 4344 // Otherwise, it is above the locks and verification slot and alignment word | |
| 4345 return_addr(STACK - 2 + | |
| 4346 round_to(2 + 2 * VerifyStackAtCalls + | |
| 4347 Compile::current()->fixed_slots(), | |
| 4348 WordsPerLong * 2)); | |
| 4349 | |
| 4350 // Body of function which returns an integer array locating | |
| 4351 // arguments either in registers or in stack slots. Passed an array | |
| 4352 // of ideal registers called "sig" and a "length" count. Stack-slot | |
| 4353 // offsets are based on outgoing arguments, i.e. a CALLER setting up | |
| 4354 // arguments for a CALLEE. Incoming stack arguments are | |
| 4355 // automatically biased by the preserve_stack_slots field above. | |
| 4356 | |
| 4357 calling_convention | |
| 4358 %{ | |
| 4359 // No difference between ingoing/outgoing just pass false | |
| 4360 SharedRuntime::java_calling_convention(sig_bt, regs, length, false); | |
| 4361 %} | |
| 4362 | |
| 4363 c_calling_convention | |
| 4364 %{ | |
| 4365 // This is obviously always outgoing | |
| 4366 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); | |
| 4367 %} | |
| 4368 | |
| 4369 // Location of compiled Java return values. Same as C for now. | |
| 4370 return_value | |
| 4371 %{ | |
| 4372 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, | |
| 4373 "only return normal values"); | |
| 4374 | |
| 4375 static const int lo[Op_RegL + 1] = { | |
| 4376 0, | |
| 4377 0, | |
|
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|
4378 RAX_num, // Op_RegN |
| 0 | 4379 RAX_num, // Op_RegI |
| 4380 RAX_num, // Op_RegP | |
| 4381 XMM0_num, // Op_RegF | |
| 4382 XMM0_num, // Op_RegD | |
| 4383 RAX_num // Op_RegL | |
| 4384 }; | |
| 4385 static const int hi[Op_RegL + 1] = { | |
| 4386 0, | |
| 4387 0, | |
|
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|
4388 OptoReg::Bad, // Op_RegN |
| 0 | 4389 OptoReg::Bad, // Op_RegI |
| 4390 RAX_H_num, // Op_RegP | |
| 4391 OptoReg::Bad, // Op_RegF | |
| 4392 XMM0_H_num, // Op_RegD | |
| 4393 RAX_H_num // Op_RegL | |
| 4394 }; | |
|
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|
4395 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 1, "missing type"); |
| 0 | 4396 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]); |
| 4397 %} | |
| 4398 %} | |
| 4399 | |
| 4400 //----------ATTRIBUTES--------------------------------------------------------- | |
| 4401 //----------Operand Attributes------------------------------------------------- | |
| 4402 op_attrib op_cost(0); // Required cost attribute | |
| 4403 | |
| 4404 //----------Instruction Attributes--------------------------------------------- | |
| 4405 ins_attrib ins_cost(100); // Required cost attribute | |
| 4406 ins_attrib ins_size(8); // Required size attribute (in bits) | |
| 4407 ins_attrib ins_pc_relative(0); // Required PC Relative flag | |
| 4408 ins_attrib ins_short_branch(0); // Required flag: is this instruction | |
| 4409 // a non-matching short branch variant | |
| 4410 // of some long branch? | |
| 4411 ins_attrib ins_alignment(1); // Required alignment attribute (must | |
| 4412 // be a power of 2) specifies the | |
| 4413 // alignment that some part of the | |
| 4414 // instruction (not necessarily the | |
| 4415 // start) requires. If > 1, a | |
| 4416 // compute_padding() function must be | |
| 4417 // provided for the instruction | |
| 4418 | |
| 4419 //----------OPERANDS----------------------------------------------------------- | |
| 4420 // Operand definitions must precede instruction definitions for correct parsing | |
| 4421 // in the ADLC because operands constitute user defined types which are used in | |
| 4422 // instruction definitions. | |
| 4423 | |
| 4424 //----------Simple Operands---------------------------------------------------- | |
| 4425 // Immediate Operands | |
| 4426 // Integer Immediate | |
| 4427 operand immI() | |
| 4428 %{ | |
| 4429 match(ConI); | |
| 4430 | |
| 4431 op_cost(10); | |
| 4432 format %{ %} | |
| 4433 interface(CONST_INTER); | |
| 4434 %} | |
| 4435 | |
| 4436 // Constant for test vs zero | |
| 4437 operand immI0() | |
| 4438 %{ | |
| 4439 predicate(n->get_int() == 0); | |
| 4440 match(ConI); | |
| 4441 | |
| 4442 op_cost(0); | |
| 4443 format %{ %} | |
| 4444 interface(CONST_INTER); | |
| 4445 %} | |
| 4446 | |
| 4447 // Constant for increment | |
| 4448 operand immI1() | |
| 4449 %{ | |
| 4450 predicate(n->get_int() == 1); | |
| 4451 match(ConI); | |
| 4452 | |
| 4453 op_cost(0); | |
| 4454 format %{ %} | |
| 4455 interface(CONST_INTER); | |
| 4456 %} | |
| 4457 | |
| 4458 // Constant for decrement | |
| 4459 operand immI_M1() | |
| 4460 %{ | |
| 4461 predicate(n->get_int() == -1); | |
| 4462 match(ConI); | |
| 4463 | |
| 4464 op_cost(0); | |
| 4465 format %{ %} | |
| 4466 interface(CONST_INTER); | |
| 4467 %} | |
| 4468 | |
| 4469 // Valid scale values for addressing modes | |
| 4470 operand immI2() | |
| 4471 %{ | |
| 4472 predicate(0 <= n->get_int() && (n->get_int() <= 3)); | |
| 4473 match(ConI); | |
| 4474 | |
| 4475 format %{ %} | |
| 4476 interface(CONST_INTER); | |
| 4477 %} | |
| 4478 | |
| 4479 operand immI8() | |
| 4480 %{ | |
| 4481 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80)); | |
| 4482 match(ConI); | |
| 4483 | |
| 4484 op_cost(5); | |
| 4485 format %{ %} | |
| 4486 interface(CONST_INTER); | |
| 4487 %} | |
| 4488 | |
| 4489 operand immI16() | |
| 4490 %{ | |
| 4491 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767)); | |
| 4492 match(ConI); | |
| 4493 | |
| 4494 op_cost(10); | |
| 4495 format %{ %} | |
| 4496 interface(CONST_INTER); | |
| 4497 %} | |
| 4498 | |
| 4499 // Constant for long shifts | |
| 4500 operand immI_32() | |
| 4501 %{ | |
| 4502 predicate( n->get_int() == 32 ); | |
| 4503 match(ConI); | |
| 4504 | |
| 4505 op_cost(0); | |
| 4506 format %{ %} | |
| 4507 interface(CONST_INTER); | |
| 4508 %} | |
| 4509 | |
| 4510 // Constant for long shifts | |
| 4511 operand immI_64() | |
| 4512 %{ | |
| 4513 predicate( n->get_int() == 64 ); | |
| 4514 match(ConI); | |
| 4515 | |
| 4516 op_cost(0); | |
| 4517 format %{ %} | |
| 4518 interface(CONST_INTER); | |
| 4519 %} | |
| 4520 | |
| 4521 // Pointer Immediate | |
| 4522 operand immP() | |
| 4523 %{ | |
| 4524 match(ConP); | |
| 4525 | |
| 4526 op_cost(10); | |
| 4527 format %{ %} | |
| 4528 interface(CONST_INTER); | |
| 4529 %} | |
| 4530 | |
| 4531 // NULL Pointer Immediate | |
| 4532 operand immP0() | |
| 4533 %{ | |
| 4534 predicate(n->get_ptr() == 0); | |
| 4535 match(ConP); | |
| 4536 | |
| 4537 op_cost(5); | |
| 4538 format %{ %} | |
| 4539 interface(CONST_INTER); | |
| 4540 %} | |
| 4541 | |
|
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4542 // Pointer Immediate |
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4543 operand immN() %{ |
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4544 match(ConN); |
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4545 |
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4546 op_cost(10); |
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4547 format %{ %} |
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4548 interface(CONST_INTER); |
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4549 %} |
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4550 |
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4551 // NULL Pointer Immediate |
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4552 operand immN0() %{ |
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4553 predicate(n->get_narrowcon() == 0); |
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4554 match(ConN); |
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4555 |
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4556 op_cost(5); |
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4557 format %{ %} |
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4558 interface(CONST_INTER); |
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4559 %} |
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4560 |
| 0 | 4561 operand immP31() |
| 4562 %{ | |
| 4563 predicate(!n->as_Type()->type()->isa_oopptr() | |
| 4564 && (n->get_ptr() >> 31) == 0); | |
| 4565 match(ConP); | |
| 4566 | |
| 4567 op_cost(5); | |
| 4568 format %{ %} | |
| 4569 interface(CONST_INTER); | |
| 4570 %} | |
| 4571 | |
|
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4572 |
| 0 | 4573 // Long Immediate |
| 4574 operand immL() | |
| 4575 %{ | |
| 4576 match(ConL); | |
| 4577 | |
| 4578 op_cost(20); | |
| 4579 format %{ %} | |
| 4580 interface(CONST_INTER); | |
| 4581 %} | |
| 4582 | |
| 4583 // Long Immediate 8-bit | |
| 4584 operand immL8() | |
| 4585 %{ | |
| 4586 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L); | |
| 4587 match(ConL); | |
| 4588 | |
| 4589 op_cost(5); | |
| 4590 format %{ %} | |
| 4591 interface(CONST_INTER); | |
| 4592 %} | |
| 4593 | |
| 4594 // Long Immediate 32-bit unsigned | |
| 4595 operand immUL32() | |
| 4596 %{ | |
| 4597 predicate(n->get_long() == (unsigned int) (n->get_long())); | |
| 4598 match(ConL); | |
| 4599 | |
| 4600 op_cost(10); | |
| 4601 format %{ %} | |
| 4602 interface(CONST_INTER); | |
| 4603 %} | |
| 4604 | |
| 4605 // Long Immediate 32-bit signed | |
| 4606 operand immL32() | |
| 4607 %{ | |
| 4608 predicate(n->get_long() == (int) (n->get_long())); | |
| 4609 match(ConL); | |
| 4610 | |
| 4611 op_cost(15); | |
| 4612 format %{ %} | |
| 4613 interface(CONST_INTER); | |
| 4614 %} | |
| 4615 | |
| 4616 // Long Immediate zero | |
| 4617 operand immL0() | |
| 4618 %{ | |
| 4619 predicate(n->get_long() == 0L); | |
| 4620 match(ConL); | |
| 4621 | |
| 4622 op_cost(10); | |
| 4623 format %{ %} | |
| 4624 interface(CONST_INTER); | |
| 4625 %} | |
| 4626 | |
| 4627 // Constant for increment | |
| 4628 operand immL1() | |
| 4629 %{ | |
| 4630 predicate(n->get_long() == 1); | |
| 4631 match(ConL); | |
| 4632 | |
| 4633 format %{ %} | |
| 4634 interface(CONST_INTER); | |
| 4635 %} | |
| 4636 | |
| 4637 // Constant for decrement | |
| 4638 operand immL_M1() | |
| 4639 %{ | |
| 4640 predicate(n->get_long() == -1); | |
| 4641 match(ConL); | |
| 4642 | |
| 4643 format %{ %} | |
| 4644 interface(CONST_INTER); | |
| 4645 %} | |
| 4646 | |
| 4647 // Long Immediate: the value 10 | |
| 4648 operand immL10() | |
| 4649 %{ | |
| 4650 predicate(n->get_long() == 10); | |
| 4651 match(ConL); | |
| 4652 | |
| 4653 format %{ %} | |
| 4654 interface(CONST_INTER); | |
| 4655 %} | |
| 4656 | |
| 4657 // Long immediate from 0 to 127. | |
| 4658 // Used for a shorter form of long mul by 10. | |
| 4659 operand immL_127() | |
| 4660 %{ | |
| 4661 predicate(0 <= n->get_long() && n->get_long() < 0x80); | |
| 4662 match(ConL); | |
| 4663 | |
| 4664 op_cost(10); | |
| 4665 format %{ %} | |
| 4666 interface(CONST_INTER); | |
| 4667 %} | |
| 4668 | |
| 4669 // Long Immediate: low 32-bit mask | |
| 4670 operand immL_32bits() | |
| 4671 %{ | |
| 4672 predicate(n->get_long() == 0xFFFFFFFFL); | |
| 4673 match(ConL); | |
| 4674 op_cost(20); | |
| 4675 | |
| 4676 format %{ %} | |
| 4677 interface(CONST_INTER); | |
| 4678 %} | |
| 4679 | |
| 4680 // Float Immediate zero | |
| 4681 operand immF0() | |
| 4682 %{ | |
| 4683 predicate(jint_cast(n->getf()) == 0); | |
| 4684 match(ConF); | |
| 4685 | |
| 4686 op_cost(5); | |
| 4687 format %{ %} | |
| 4688 interface(CONST_INTER); | |
| 4689 %} | |
| 4690 | |
| 4691 // Float Immediate | |
| 4692 operand immF() | |
| 4693 %{ | |
| 4694 match(ConF); | |
| 4695 | |
| 4696 op_cost(15); | |
| 4697 format %{ %} | |
| 4698 interface(CONST_INTER); | |
| 4699 %} | |
| 4700 | |
| 4701 // Double Immediate zero | |
| 4702 operand immD0() | |
| 4703 %{ | |
| 4704 predicate(jlong_cast(n->getd()) == 0); | |
| 4705 match(ConD); | |
| 4706 | |
| 4707 op_cost(5); | |
| 4708 format %{ %} | |
| 4709 interface(CONST_INTER); | |
| 4710 %} | |
| 4711 | |
| 4712 // Double Immediate | |
| 4713 operand immD() | |
| 4714 %{ | |
| 4715 match(ConD); | |
| 4716 | |
| 4717 op_cost(15); | |
| 4718 format %{ %} | |
| 4719 interface(CONST_INTER); | |
| 4720 %} | |
| 4721 | |
| 4722 // Immediates for special shifts (sign extend) | |
| 4723 | |
| 4724 // Constants for increment | |
| 4725 operand immI_16() | |
| 4726 %{ | |
| 4727 predicate(n->get_int() == 16); | |
| 4728 match(ConI); | |
| 4729 | |
| 4730 format %{ %} | |
| 4731 interface(CONST_INTER); | |
| 4732 %} | |
| 4733 | |
| 4734 operand immI_24() | |
| 4735 %{ | |
| 4736 predicate(n->get_int() == 24); | |
| 4737 match(ConI); | |
| 4738 | |
| 4739 format %{ %} | |
| 4740 interface(CONST_INTER); | |
| 4741 %} | |
| 4742 | |
| 4743 // Constant for byte-wide masking | |
| 4744 operand immI_255() | |
| 4745 %{ | |
| 4746 predicate(n->get_int() == 255); | |
| 4747 match(ConI); | |
| 4748 | |
| 4749 format %{ %} | |
| 4750 interface(CONST_INTER); | |
| 4751 %} | |
| 4752 | |
| 4753 // Constant for short-wide masking | |
| 4754 operand immI_65535() | |
| 4755 %{ | |
| 4756 predicate(n->get_int() == 65535); | |
| 4757 match(ConI); | |
| 4758 | |
| 4759 format %{ %} | |
| 4760 interface(CONST_INTER); | |
| 4761 %} | |
| 4762 | |
| 4763 // Constant for byte-wide masking | |
| 4764 operand immL_255() | |
| 4765 %{ | |
| 4766 predicate(n->get_long() == 255); | |
| 4767 match(ConL); | |
| 4768 | |
| 4769 format %{ %} | |
| 4770 interface(CONST_INTER); | |
| 4771 %} | |
| 4772 | |
| 4773 // Constant for short-wide masking | |
| 4774 operand immL_65535() | |
| 4775 %{ | |
| 4776 predicate(n->get_long() == 65535); | |
| 4777 match(ConL); | |
| 4778 | |
| 4779 format %{ %} | |
| 4780 interface(CONST_INTER); | |
| 4781 %} | |
| 4782 | |
| 4783 // Register Operands | |
| 4784 // Integer Register | |
| 4785 operand rRegI() | |
| 4786 %{ | |
| 4787 constraint(ALLOC_IN_RC(int_reg)); | |
| 4788 match(RegI); | |
| 4789 | |
| 4790 match(rax_RegI); | |
| 4791 match(rbx_RegI); | |
| 4792 match(rcx_RegI); | |
| 4793 match(rdx_RegI); | |
| 4794 match(rdi_RegI); | |
| 4795 | |
| 4796 format %{ %} | |
| 4797 interface(REG_INTER); | |
| 4798 %} | |
| 4799 | |
| 4800 // Special Registers | |
| 4801 operand rax_RegI() | |
| 4802 %{ | |
| 4803 constraint(ALLOC_IN_RC(int_rax_reg)); | |
| 4804 match(RegI); | |
| 4805 match(rRegI); | |
| 4806 | |
| 4807 format %{ "RAX" %} | |
| 4808 interface(REG_INTER); | |
| 4809 %} | |
| 4810 | |
| 4811 // Special Registers | |
| 4812 operand rbx_RegI() | |
| 4813 %{ | |
| 4814 constraint(ALLOC_IN_RC(int_rbx_reg)); | |
| 4815 match(RegI); | |
| 4816 match(rRegI); | |
| 4817 | |
| 4818 format %{ "RBX" %} | |
| 4819 interface(REG_INTER); | |
| 4820 %} | |
| 4821 | |
| 4822 operand rcx_RegI() | |
| 4823 %{ | |
| 4824 constraint(ALLOC_IN_RC(int_rcx_reg)); | |
| 4825 match(RegI); | |
| 4826 match(rRegI); | |
| 4827 | |
| 4828 format %{ "RCX" %} | |
| 4829 interface(REG_INTER); | |
| 4830 %} | |
| 4831 | |
| 4832 operand rdx_RegI() | |
| 4833 %{ | |
| 4834 constraint(ALLOC_IN_RC(int_rdx_reg)); | |
| 4835 match(RegI); | |
| 4836 match(rRegI); | |
| 4837 | |
| 4838 format %{ "RDX" %} | |
| 4839 interface(REG_INTER); | |
| 4840 %} | |
| 4841 | |
| 4842 operand rdi_RegI() | |
| 4843 %{ | |
| 4844 constraint(ALLOC_IN_RC(int_rdi_reg)); | |
| 4845 match(RegI); | |
| 4846 match(rRegI); | |
| 4847 | |
| 4848 format %{ "RDI" %} | |
| 4849 interface(REG_INTER); | |
| 4850 %} | |
| 4851 | |
| 4852 operand no_rcx_RegI() | |
| 4853 %{ | |
| 4854 constraint(ALLOC_IN_RC(int_no_rcx_reg)); | |
| 4855 match(RegI); | |
| 4856 match(rax_RegI); | |
| 4857 match(rbx_RegI); | |
| 4858 match(rdx_RegI); | |
| 4859 match(rdi_RegI); | |
| 4860 | |
| 4861 format %{ %} | |
| 4862 interface(REG_INTER); | |
| 4863 %} | |
| 4864 | |
| 4865 operand no_rax_rdx_RegI() | |
| 4866 %{ | |
| 4867 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg)); | |
| 4868 match(RegI); | |
| 4869 match(rbx_RegI); | |
| 4870 match(rcx_RegI); | |
| 4871 match(rdi_RegI); | |
| 4872 | |
| 4873 format %{ %} | |
| 4874 interface(REG_INTER); | |
| 4875 %} | |
| 4876 | |
| 4877 // Pointer Register | |
| 4878 operand any_RegP() | |
| 4879 %{ | |
| 4880 constraint(ALLOC_IN_RC(any_reg)); | |
| 4881 match(RegP); | |
| 4882 match(rax_RegP); | |
| 4883 match(rbx_RegP); | |
| 4884 match(rdi_RegP); | |
| 4885 match(rsi_RegP); | |
| 4886 match(rbp_RegP); | |
| 4887 match(r15_RegP); | |
| 4888 match(rRegP); | |
| 4889 | |
| 4890 format %{ %} | |
| 4891 interface(REG_INTER); | |
| 4892 %} | |
| 4893 | |
| 4894 operand rRegP() | |
| 4895 %{ | |
| 4896 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 4897 match(RegP); | |
| 4898 match(rax_RegP); | |
| 4899 match(rbx_RegP); | |
| 4900 match(rdi_RegP); | |
| 4901 match(rsi_RegP); | |
| 4902 match(rbp_RegP); | |
| 4903 match(r15_RegP); // See Q&A below about r15_RegP. | |
| 4904 | |
| 4905 format %{ %} | |
| 4906 interface(REG_INTER); | |
| 4907 %} | |
| 4908 | |
|
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4909 |
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4910 operand r12RegL() %{ |
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4911 constraint(ALLOC_IN_RC(long_r12_reg)); |
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4912 match(RegL); |
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4913 |
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4914 format %{ %} |
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4915 interface(REG_INTER); |
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4916 %} |
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4917 |
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4918 operand rRegN() %{ |
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4919 constraint(ALLOC_IN_RC(int_reg)); |
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4920 match(RegN); |
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4921 |
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4922 format %{ %} |
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4923 interface(REG_INTER); |
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4924 %} |
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4925 |
| 0 | 4926 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP? |
| 4927 // Answer: Operand match rules govern the DFA as it processes instruction inputs. | |
| 4928 // It's fine for an instruction input which expects rRegP to match a r15_RegP. | |
| 4929 // The output of an instruction is controlled by the allocator, which respects | |
| 4930 // register class masks, not match rules. Unless an instruction mentions | |
| 4931 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered | |
| 4932 // by the allocator as an input. | |
| 4933 | |
| 4934 operand no_rax_RegP() | |
| 4935 %{ | |
| 4936 constraint(ALLOC_IN_RC(ptr_no_rax_reg)); | |
| 4937 match(RegP); | |
| 4938 match(rbx_RegP); | |
| 4939 match(rsi_RegP); | |
| 4940 match(rdi_RegP); | |
| 4941 | |
| 4942 format %{ %} | |
| 4943 interface(REG_INTER); | |
| 4944 %} | |
| 4945 | |
| 4946 operand no_rbp_RegP() | |
| 4947 %{ | |
| 4948 constraint(ALLOC_IN_RC(ptr_no_rbp_reg)); | |
| 4949 match(RegP); | |
| 4950 match(rbx_RegP); | |
| 4951 match(rsi_RegP); | |
| 4952 match(rdi_RegP); | |
| 4953 | |
| 4954 format %{ %} | |
| 4955 interface(REG_INTER); | |
| 4956 %} | |
| 4957 | |
| 4958 operand no_rax_rbx_RegP() | |
| 4959 %{ | |
| 4960 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg)); | |
| 4961 match(RegP); | |
| 4962 match(rsi_RegP); | |
| 4963 match(rdi_RegP); | |
| 4964 | |
| 4965 format %{ %} | |
| 4966 interface(REG_INTER); | |
| 4967 %} | |
| 4968 | |
| 4969 // Special Registers | |
| 4970 // Return a pointer value | |
| 4971 operand rax_RegP() | |
| 4972 %{ | |
| 4973 constraint(ALLOC_IN_RC(ptr_rax_reg)); | |
| 4974 match(RegP); | |
| 4975 match(rRegP); | |
| 4976 | |
| 4977 format %{ %} | |
| 4978 interface(REG_INTER); | |
| 4979 %} | |
| 4980 | |
|
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4981 // Special Registers |
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4982 // Return a compressed pointer value |
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4983 operand rax_RegN() |
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4984 %{ |
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4985 constraint(ALLOC_IN_RC(int_rax_reg)); |
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4986 match(RegN); |
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4987 match(rRegN); |
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4988 |
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4989 format %{ %} |
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4990 interface(REG_INTER); |
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4991 %} |
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4992 |
| 0 | 4993 // Used in AtomicAdd |
| 4994 operand rbx_RegP() | |
| 4995 %{ | |
| 4996 constraint(ALLOC_IN_RC(ptr_rbx_reg)); | |
| 4997 match(RegP); | |
| 4998 match(rRegP); | |
| 4999 | |
| 5000 format %{ %} | |
| 5001 interface(REG_INTER); | |
| 5002 %} | |
| 5003 | |
| 5004 operand rsi_RegP() | |
| 5005 %{ | |
| 5006 constraint(ALLOC_IN_RC(ptr_rsi_reg)); | |
| 5007 match(RegP); | |
| 5008 match(rRegP); | |
| 5009 | |
| 5010 format %{ %} | |
| 5011 interface(REG_INTER); | |
| 5012 %} | |
| 5013 | |
| 5014 // Used in rep stosq | |
| 5015 operand rdi_RegP() | |
| 5016 %{ | |
| 5017 constraint(ALLOC_IN_RC(ptr_rdi_reg)); | |
| 5018 match(RegP); | |
| 5019 match(rRegP); | |
| 5020 | |
| 5021 format %{ %} | |
| 5022 interface(REG_INTER); | |
| 5023 %} | |
| 5024 | |
| 5025 operand rbp_RegP() | |
| 5026 %{ | |
| 5027 constraint(ALLOC_IN_RC(ptr_rbp_reg)); | |
| 5028 match(RegP); | |
| 5029 match(rRegP); | |
| 5030 | |
| 5031 format %{ %} | |
| 5032 interface(REG_INTER); | |
| 5033 %} | |
| 5034 | |
| 5035 operand r15_RegP() | |
| 5036 %{ | |
| 5037 constraint(ALLOC_IN_RC(ptr_r15_reg)); | |
| 5038 match(RegP); | |
| 5039 match(rRegP); | |
| 5040 | |
| 5041 format %{ %} | |
| 5042 interface(REG_INTER); | |
| 5043 %} | |
| 5044 | |
| 5045 operand rRegL() | |
| 5046 %{ | |
| 5047 constraint(ALLOC_IN_RC(long_reg)); | |
| 5048 match(RegL); | |
| 5049 match(rax_RegL); | |
| 5050 match(rdx_RegL); | |
| 5051 | |
| 5052 format %{ %} | |
| 5053 interface(REG_INTER); | |
| 5054 %} | |
| 5055 | |
| 5056 // Special Registers | |
| 5057 operand no_rax_rdx_RegL() | |
| 5058 %{ | |
| 5059 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg)); | |
| 5060 match(RegL); | |
| 5061 match(rRegL); | |
| 5062 | |
| 5063 format %{ %} | |
| 5064 interface(REG_INTER); | |
| 5065 %} | |
| 5066 | |
| 5067 operand no_rax_RegL() | |
| 5068 %{ | |
| 5069 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg)); | |
| 5070 match(RegL); | |
| 5071 match(rRegL); | |
| 5072 match(rdx_RegL); | |
| 5073 | |
| 5074 format %{ %} | |
| 5075 interface(REG_INTER); | |
| 5076 %} | |
| 5077 | |
| 5078 operand no_rcx_RegL() | |
| 5079 %{ | |
| 5080 constraint(ALLOC_IN_RC(long_no_rcx_reg)); | |
| 5081 match(RegL); | |
| 5082 match(rRegL); | |
| 5083 | |
| 5084 format %{ %} | |
| 5085 interface(REG_INTER); | |
| 5086 %} | |
| 5087 | |
| 5088 operand rax_RegL() | |
| 5089 %{ | |
| 5090 constraint(ALLOC_IN_RC(long_rax_reg)); | |
| 5091 match(RegL); | |
| 5092 match(rRegL); | |
| 5093 | |
| 5094 format %{ "RAX" %} | |
| 5095 interface(REG_INTER); | |
| 5096 %} | |
| 5097 | |
| 5098 operand rcx_RegL() | |
| 5099 %{ | |
| 5100 constraint(ALLOC_IN_RC(long_rcx_reg)); | |
| 5101 match(RegL); | |
| 5102 match(rRegL); | |
| 5103 | |
| 5104 format %{ %} | |
| 5105 interface(REG_INTER); | |
| 5106 %} | |
| 5107 | |
| 5108 operand rdx_RegL() | |
| 5109 %{ | |
| 5110 constraint(ALLOC_IN_RC(long_rdx_reg)); | |
| 5111 match(RegL); | |
| 5112 match(rRegL); | |
| 5113 | |
| 5114 format %{ %} | |
| 5115 interface(REG_INTER); | |
| 5116 %} | |
| 5117 | |
| 5118 // Flags register, used as output of compare instructions | |
| 5119 operand rFlagsReg() | |
| 5120 %{ | |
| 5121 constraint(ALLOC_IN_RC(int_flags)); | |
| 5122 match(RegFlags); | |
| 5123 | |
| 5124 format %{ "RFLAGS" %} | |
| 5125 interface(REG_INTER); | |
| 5126 %} | |
| 5127 | |
| 5128 // Flags register, used as output of FLOATING POINT compare instructions | |
| 5129 operand rFlagsRegU() | |
| 5130 %{ | |
| 5131 constraint(ALLOC_IN_RC(int_flags)); | |
| 5132 match(RegFlags); | |
| 5133 | |
| 5134 format %{ "RFLAGS_U" %} | |
| 5135 interface(REG_INTER); | |
| 5136 %} | |
| 5137 | |
|
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5138 operand rFlagsRegUCF() %{ |
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5139 constraint(ALLOC_IN_RC(int_flags)); |
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5140 match(RegFlags); |
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5141 predicate(false); |
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|
5142 |
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5143 format %{ "RFLAGS_U_CF" %} |
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5144 interface(REG_INTER); |
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5145 %} |
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5146 |
| 0 | 5147 // Float register operands |
| 5148 operand regF() | |
| 5149 %{ | |
| 5150 constraint(ALLOC_IN_RC(float_reg)); | |
| 5151 match(RegF); | |
| 5152 | |
| 5153 format %{ %} | |
| 5154 interface(REG_INTER); | |
| 5155 %} | |
| 5156 | |
| 5157 // Double register operands | |
| 5158 operand regD() | |
| 5159 %{ | |
| 5160 constraint(ALLOC_IN_RC(double_reg)); | |
| 5161 match(RegD); | |
| 5162 | |
| 5163 format %{ %} | |
| 5164 interface(REG_INTER); | |
| 5165 %} | |
| 5166 | |
| 5167 | |
| 5168 //----------Memory Operands---------------------------------------------------- | |
| 5169 // Direct Memory Operand | |
| 5170 // operand direct(immP addr) | |
| 5171 // %{ | |
| 5172 // match(addr); | |
| 5173 | |
| 5174 // format %{ "[$addr]" %} | |
| 5175 // interface(MEMORY_INTER) %{ | |
| 5176 // base(0xFFFFFFFF); | |
| 5177 // index(0x4); | |
| 5178 // scale(0x0); | |
| 5179 // disp($addr); | |
| 5180 // %} | |
| 5181 // %} | |
| 5182 | |
| 5183 // Indirect Memory Operand | |
| 5184 operand indirect(any_RegP reg) | |
| 5185 %{ | |
| 5186 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 5187 match(reg); | |
| 5188 | |
| 5189 format %{ "[$reg]" %} | |
| 5190 interface(MEMORY_INTER) %{ | |
| 5191 base($reg); | |
| 5192 index(0x4); | |
| 5193 scale(0x0); | |
| 5194 disp(0x0); | |
| 5195 %} | |
| 5196 %} | |
| 5197 | |
| 5198 // Indirect Memory Plus Short Offset Operand | |
| 5199 operand indOffset8(any_RegP reg, immL8 off) | |
| 5200 %{ | |
| 5201 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 5202 match(AddP reg off); | |
| 5203 | |
| 5204 format %{ "[$reg + $off (8-bit)]" %} | |
| 5205 interface(MEMORY_INTER) %{ | |
| 5206 base($reg); | |
| 5207 index(0x4); | |
| 5208 scale(0x0); | |
| 5209 disp($off); | |
| 5210 %} | |
| 5211 %} | |
| 5212 | |
| 5213 // Indirect Memory Plus Long Offset Operand | |
| 5214 operand indOffset32(any_RegP reg, immL32 off) | |
| 5215 %{ | |
| 5216 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 5217 match(AddP reg off); | |
| 5218 | |
| 5219 format %{ "[$reg + $off (32-bit)]" %} | |
| 5220 interface(MEMORY_INTER) %{ | |
| 5221 base($reg); | |
| 5222 index(0x4); | |
| 5223 scale(0x0); | |
| 5224 disp($off); | |
| 5225 %} | |
| 5226 %} | |
| 5227 | |
| 5228 // Indirect Memory Plus Index Register Plus Offset Operand | |
| 5229 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off) | |
| 5230 %{ | |
| 5231 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 5232 match(AddP (AddP reg lreg) off); | |
| 5233 | |
| 5234 op_cost(10); | |
| 5235 format %{"[$reg + $off + $lreg]" %} | |
| 5236 interface(MEMORY_INTER) %{ | |
| 5237 base($reg); | |
| 5238 index($lreg); | |
| 5239 scale(0x0); | |
| 5240 disp($off); | |
| 5241 %} | |
| 5242 %} | |
| 5243 | |
| 5244 // Indirect Memory Plus Index Register Plus Offset Operand | |
| 5245 operand indIndex(any_RegP reg, rRegL lreg) | |
| 5246 %{ | |
| 5247 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 5248 match(AddP reg lreg); | |
| 5249 | |
| 5250 op_cost(10); | |
| 5251 format %{"[$reg + $lreg]" %} | |
| 5252 interface(MEMORY_INTER) %{ | |
| 5253 base($reg); | |
| 5254 index($lreg); | |
| 5255 scale(0x0); | |
| 5256 disp(0x0); | |
| 5257 %} | |
| 5258 %} | |
| 5259 | |
| 5260 // Indirect Memory Times Scale Plus Index Register | |
| 5261 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale) | |
| 5262 %{ | |
| 5263 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 5264 match(AddP reg (LShiftL lreg scale)); | |
| 5265 | |
| 5266 op_cost(10); | |
| 5267 format %{"[$reg + $lreg << $scale]" %} | |
| 5268 interface(MEMORY_INTER) %{ | |
| 5269 base($reg); | |
| 5270 index($lreg); | |
| 5271 scale($scale); | |
| 5272 disp(0x0); | |
| 5273 %} | |
| 5274 %} | |
| 5275 | |
| 5276 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand | |
| 5277 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale) | |
| 5278 %{ | |
| 5279 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 5280 match(AddP (AddP reg (LShiftL lreg scale)) off); | |
| 5281 | |
| 5282 op_cost(10); | |
| 5283 format %{"[$reg + $off + $lreg << $scale]" %} | |
| 5284 interface(MEMORY_INTER) %{ | |
| 5285 base($reg); | |
| 5286 index($lreg); | |
| 5287 scale($scale); | |
| 5288 disp($off); | |
| 5289 %} | |
| 5290 %} | |
| 5291 | |
|
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5292 // Indirect Narrow Oop Plus Offset Operand |
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5293 operand indNarrowOopOffset(rRegN src, immL32 off) %{ |
|
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5294 constraint(ALLOC_IN_RC(ptr_reg)); |
|
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5295 match(AddP (DecodeN src) off); |
|
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5296 |
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5297 op_cost(10); |
|
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5298 format %{"[R12 + $src << 3 + $off] (compressed oop addressing)" %} |
|
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5299 interface(MEMORY_INTER) %{ |
|
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5300 base(0xc); // R12 |
|
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5301 index($src); |
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5302 scale(0x3); |
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5303 disp($off); |
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5304 %} |
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5305 %} |
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5306 |
| 0 | 5307 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand |
| 5308 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale) | |
| 5309 %{ | |
| 5310 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 5311 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0); | |
| 5312 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off); | |
| 5313 | |
| 5314 op_cost(10); | |
| 5315 format %{"[$reg + $off + $idx << $scale]" %} | |
| 5316 interface(MEMORY_INTER) %{ | |
| 5317 base($reg); | |
| 5318 index($idx); | |
| 5319 scale($scale); | |
| 5320 disp($off); | |
| 5321 %} | |
| 5322 %} | |
| 5323 | |
| 5324 //----------Special Memory Operands-------------------------------------------- | |
| 5325 // Stack Slot Operand - This operand is used for loading and storing temporary | |
| 5326 // values on the stack where a match requires a value to | |
| 5327 // flow through memory. | |
| 5328 operand stackSlotP(sRegP reg) | |
| 5329 %{ | |
| 5330 constraint(ALLOC_IN_RC(stack_slots)); | |
| 5331 // No match rule because this operand is only generated in matching | |
| 5332 | |
| 5333 format %{ "[$reg]" %} | |
| 5334 interface(MEMORY_INTER) %{ | |
| 5335 base(0x4); // RSP | |
| 5336 index(0x4); // No Index | |
| 5337 scale(0x0); // No Scale | |
| 5338 disp($reg); // Stack Offset | |
| 5339 %} | |
| 5340 %} | |
| 5341 | |
| 5342 operand stackSlotI(sRegI reg) | |
| 5343 %{ | |
| 5344 constraint(ALLOC_IN_RC(stack_slots)); | |
| 5345 // No match rule because this operand is only generated in matching | |
| 5346 | |
| 5347 format %{ "[$reg]" %} | |
| 5348 interface(MEMORY_INTER) %{ | |
| 5349 base(0x4); // RSP | |
| 5350 index(0x4); // No Index | |
| 5351 scale(0x0); // No Scale | |
| 5352 disp($reg); // Stack Offset | |
| 5353 %} | |
| 5354 %} | |
| 5355 | |
| 5356 operand stackSlotF(sRegF reg) | |
| 5357 %{ | |
| 5358 constraint(ALLOC_IN_RC(stack_slots)); | |
| 5359 // No match rule because this operand is only generated in matching | |
| 5360 | |
| 5361 format %{ "[$reg]" %} | |
| 5362 interface(MEMORY_INTER) %{ | |
| 5363 base(0x4); // RSP | |
| 5364 index(0x4); // No Index | |
| 5365 scale(0x0); // No Scale | |
| 5366 disp($reg); // Stack Offset | |
| 5367 %} | |
| 5368 %} | |
| 5369 | |
| 5370 operand stackSlotD(sRegD reg) | |
| 5371 %{ | |
| 5372 constraint(ALLOC_IN_RC(stack_slots)); | |
| 5373 // No match rule because this operand is only generated in matching | |
| 5374 | |
| 5375 format %{ "[$reg]" %} | |
| 5376 interface(MEMORY_INTER) %{ | |
| 5377 base(0x4); // RSP | |
| 5378 index(0x4); // No Index | |
| 5379 scale(0x0); // No Scale | |
| 5380 disp($reg); // Stack Offset | |
| 5381 %} | |
| 5382 %} | |
| 5383 operand stackSlotL(sRegL reg) | |
| 5384 %{ | |
| 5385 constraint(ALLOC_IN_RC(stack_slots)); | |
| 5386 // No match rule because this operand is only generated in matching | |
| 5387 | |
| 5388 format %{ "[$reg]" %} | |
| 5389 interface(MEMORY_INTER) %{ | |
| 5390 base(0x4); // RSP | |
| 5391 index(0x4); // No Index | |
| 5392 scale(0x0); // No Scale | |
| 5393 disp($reg); // Stack Offset | |
| 5394 %} | |
| 5395 %} | |
| 5396 | |
| 5397 //----------Conditional Branch Operands---------------------------------------- | |
| 5398 // Comparison Op - This is the operation of the comparison, and is limited to | |
| 5399 // the following set of codes: | |
| 5400 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) | |
| 5401 // | |
| 5402 // Other attributes of the comparison, such as unsignedness, are specified | |
| 5403 // by the comparison instruction that sets a condition code flags register. | |
| 5404 // That result is represented by a flags operand whose subtype is appropriate | |
| 5405 // to the unsignedness (etc.) of the comparison. | |
| 5406 // | |
| 5407 // Later, the instruction which matches both the Comparison Op (a Bool) and | |
| 5408 // the flags (produced by the Cmp) specifies the coding of the comparison op | |
| 5409 // by matching a specific subtype of Bool operand below, such as cmpOpU. | |
| 5410 | |
| 5411 // Comparision Code | |
| 5412 operand cmpOp() | |
| 5413 %{ | |
| 5414 match(Bool); | |
| 5415 | |
| 5416 format %{ "" %} | |
| 5417 interface(COND_INTER) %{ | |
|
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5418 equal(0x4, "e"); |
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5419 not_equal(0x5, "ne"); |
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5420 less(0xC, "l"); |
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5421 greater_equal(0xD, "ge"); |
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|
5422 less_equal(0xE, "le"); |
|
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|
5423 greater(0xF, "g"); |
| 0 | 5424 %} |
| 5425 %} | |
| 5426 | |
| 5427 // Comparison Code, unsigned compare. Used by FP also, with | |
| 5428 // C2 (unordered) turned into GT or LT already. The other bits | |
| 5429 // C0 and C3 are turned into Carry & Zero flags. | |
| 5430 operand cmpOpU() | |
| 5431 %{ | |
| 5432 match(Bool); | |
| 5433 | |
| 5434 format %{ "" %} | |
| 5435 interface(COND_INTER) %{ | |
|
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|
5436 equal(0x4, "e"); |
|
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|
5437 not_equal(0x5, "ne"); |
|
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|
5438 less(0x2, "b"); |
|
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|
5439 greater_equal(0x3, "nb"); |
|
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|
5440 less_equal(0x6, "be"); |
|
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|
5441 greater(0x7, "nbe"); |
|
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|
5442 %} |
|
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|
5443 %} |
|
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|
5444 |
|
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|
5445 |
|
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|
5446 // Floating comparisons that don't require any fixup for the unordered case |
|
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|
5447 operand cmpOpUCF() %{ |
|
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|
5448 match(Bool); |
|
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|
5449 predicate(n->as_Bool()->_test._test == BoolTest::lt || |
|
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|
5450 n->as_Bool()->_test._test == BoolTest::ge || |
|
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|
5451 n->as_Bool()->_test._test == BoolTest::le || |
|
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|
5452 n->as_Bool()->_test._test == BoolTest::gt); |
|
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|
5453 format %{ "" %} |
|
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|
5454 interface(COND_INTER) %{ |
|
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|
5455 equal(0x4, "e"); |
|
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|
5456 not_equal(0x5, "ne"); |
|
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|
5457 less(0x2, "b"); |
|
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|
5458 greater_equal(0x3, "nb"); |
|
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|
5459 less_equal(0x6, "be"); |
|
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|
5460 greater(0x7, "nbe"); |
|
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|
5461 %} |
|
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|
5462 %} |
|
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|
5463 |
|
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|
5464 |
|
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|
5465 // Floating comparisons that can be fixed up with extra conditional jumps |
|
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|
5466 operand cmpOpUCF2() %{ |
|
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|
5467 match(Bool); |
|
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|
5468 predicate(n->as_Bool()->_test._test == BoolTest::ne || |
|
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|
5469 n->as_Bool()->_test._test == BoolTest::eq); |
|
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|
5470 format %{ "" %} |
|
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|
5471 interface(COND_INTER) %{ |
|
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|
5472 equal(0x4, "e"); |
|
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|
5473 not_equal(0x5, "ne"); |
|
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|
5474 less(0x2, "b"); |
|
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|
5475 greater_equal(0x3, "nb"); |
|
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|
5476 less_equal(0x6, "be"); |
|
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|
5477 greater(0x7, "nbe"); |
| 0 | 5478 %} |
| 5479 %} | |
| 5480 | |
| 5481 | |
| 5482 //----------OPERAND CLASSES---------------------------------------------------- | |
| 5483 // Operand Classes are groups of operands that are used as to simplify | |
| 605 | 5484 // instruction definitions by not requiring the AD writer to specify separate |
| 0 | 5485 // instructions for every form of operand when the instruction accepts |
| 5486 // multiple operand types with the same basic encoding and format. The classic | |
| 5487 // case of this is memory operands. | |
| 5488 | |
| 5489 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex, | |
|
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|
5490 indIndexScale, indIndexScaleOffset, indPosIndexScaleOffset, |
|
168
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|
5491 indNarrowOopOffset); |
| 0 | 5492 |
| 5493 //----------PIPELINE----------------------------------------------------------- | |
| 5494 // Rules which define the behavior of the target architectures pipeline. | |
| 5495 pipeline %{ | |
| 5496 | |
| 5497 //----------ATTRIBUTES--------------------------------------------------------- | |
| 5498 attributes %{ | |
| 5499 variable_size_instructions; // Fixed size instructions | |
| 5500 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle | |
| 5501 instruction_unit_size = 1; // An instruction is 1 bytes long | |
| 5502 instruction_fetch_unit_size = 16; // The processor fetches one line | |
| 5503 instruction_fetch_units = 1; // of 16 bytes | |
| 5504 | |
| 5505 // List of nop instructions | |
| 5506 nops( MachNop ); | |
| 5507 %} | |
| 5508 | |
| 5509 //----------RESOURCES---------------------------------------------------------- | |
| 5510 // Resources are the functional units available to the machine | |
| 5511 | |
| 5512 // Generic P2/P3 pipeline | |
| 5513 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of | |
| 5514 // 3 instructions decoded per cycle. | |
| 5515 // 2 load/store ops per cycle, 1 branch, 1 FPU, | |
| 5516 // 3 ALU op, only ALU0 handles mul instructions. | |
| 5517 resources( D0, D1, D2, DECODE = D0 | D1 | D2, | |
| 5518 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2, | |
| 5519 BR, FPU, | |
| 5520 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2); | |
| 5521 | |
| 5522 //----------PIPELINE DESCRIPTION----------------------------------------------- | |
| 5523 // Pipeline Description specifies the stages in the machine's pipeline | |
| 5524 | |
| 5525 // Generic P2/P3 pipeline | |
| 5526 pipe_desc(S0, S1, S2, S3, S4, S5); | |
| 5527 | |
| 5528 //----------PIPELINE CLASSES--------------------------------------------------- | |
| 5529 // Pipeline Classes describe the stages in which input and output are | |
| 5530 // referenced by the hardware pipeline. | |
| 5531 | |
| 5532 // Naming convention: ialu or fpu | |
| 5533 // Then: _reg | |
| 5534 // Then: _reg if there is a 2nd register | |
| 5535 // Then: _long if it's a pair of instructions implementing a long | |
| 5536 // Then: _fat if it requires the big decoder | |
| 5537 // Or: _mem if it requires the big decoder and a memory unit. | |
| 5538 | |
| 5539 // Integer ALU reg operation | |
| 5540 pipe_class ialu_reg(rRegI dst) | |
| 5541 %{ | |
| 5542 single_instruction; | |
| 5543 dst : S4(write); | |
| 5544 dst : S3(read); | |
| 5545 DECODE : S0; // any decoder | |
| 5546 ALU : S3; // any alu | |
| 5547 %} | |
| 5548 | |
| 5549 // Long ALU reg operation | |
| 5550 pipe_class ialu_reg_long(rRegL dst) | |
| 5551 %{ | |
| 5552 instruction_count(2); | |
| 5553 dst : S4(write); | |
| 5554 dst : S3(read); | |
| 5555 DECODE : S0(2); // any 2 decoders | |
| 5556 ALU : S3(2); // both alus | |
| 5557 %} | |
| 5558 | |
| 5559 // Integer ALU reg operation using big decoder | |
| 5560 pipe_class ialu_reg_fat(rRegI dst) | |
| 5561 %{ | |
| 5562 single_instruction; | |
| 5563 dst : S4(write); | |
| 5564 dst : S3(read); | |
| 5565 D0 : S0; // big decoder only | |
| 5566 ALU : S3; // any alu | |
| 5567 %} | |
| 5568 | |
| 5569 // Long ALU reg operation using big decoder | |
| 5570 pipe_class ialu_reg_long_fat(rRegL dst) | |
| 5571 %{ | |
| 5572 instruction_count(2); | |
| 5573 dst : S4(write); | |
| 5574 dst : S3(read); | |
| 5575 D0 : S0(2); // big decoder only; twice | |
| 5576 ALU : S3(2); // any 2 alus | |
| 5577 %} | |
| 5578 | |
| 5579 // Integer ALU reg-reg operation | |
| 5580 pipe_class ialu_reg_reg(rRegI dst, rRegI src) | |
| 5581 %{ | |
| 5582 single_instruction; | |
| 5583 dst : S4(write); | |
| 5584 src : S3(read); | |
| 5585 DECODE : S0; // any decoder | |
| 5586 ALU : S3; // any alu | |
| 5587 %} | |
| 5588 | |
| 5589 // Long ALU reg-reg operation | |
| 5590 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src) | |
| 5591 %{ | |
| 5592 instruction_count(2); | |
| 5593 dst : S4(write); | |
| 5594 src : S3(read); | |
| 5595 DECODE : S0(2); // any 2 decoders | |
| 5596 ALU : S3(2); // both alus | |
| 5597 %} | |
| 5598 | |
| 5599 // Integer ALU reg-reg operation | |
| 5600 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) | |
| 5601 %{ | |
| 5602 single_instruction; | |
| 5603 dst : S4(write); | |
| 5604 src : S3(read); | |
| 5605 D0 : S0; // big decoder only | |
| 5606 ALU : S3; // any alu | |
| 5607 %} | |
| 5608 | |
| 5609 // Long ALU reg-reg operation | |
| 5610 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src) | |
| 5611 %{ | |
| 5612 instruction_count(2); | |
| 5613 dst : S4(write); | |
| 5614 src : S3(read); | |
| 5615 D0 : S0(2); // big decoder only; twice | |
| 5616 ALU : S3(2); // both alus | |
| 5617 %} | |
| 5618 | |
| 5619 // Integer ALU reg-mem operation | |
| 5620 pipe_class ialu_reg_mem(rRegI dst, memory mem) | |
| 5621 %{ | |
| 5622 single_instruction; | |
| 5623 dst : S5(write); | |
| 5624 mem : S3(read); | |
| 5625 D0 : S0; // big decoder only | |
| 5626 ALU : S4; // any alu | |
| 5627 MEM : S3; // any mem | |
| 5628 %} | |
| 5629 | |
| 5630 // Integer mem operation (prefetch) | |
| 5631 pipe_class ialu_mem(memory mem) | |
| 5632 %{ | |
| 5633 single_instruction; | |
| 5634 mem : S3(read); | |
| 5635 D0 : S0; // big decoder only | |
| 5636 MEM : S3; // any mem | |
| 5637 %} | |
| 5638 | |
| 5639 // Integer Store to Memory | |
| 5640 pipe_class ialu_mem_reg(memory mem, rRegI src) | |
| 5641 %{ | |
| 5642 single_instruction; | |
| 5643 mem : S3(read); | |
| 5644 src : S5(read); | |
| 5645 D0 : S0; // big decoder only | |
| 5646 ALU : S4; // any alu | |
| 5647 MEM : S3; | |
| 5648 %} | |
| 5649 | |
| 5650 // // Long Store to Memory | |
| 5651 // pipe_class ialu_mem_long_reg(memory mem, rRegL src) | |
| 5652 // %{ | |
| 5653 // instruction_count(2); | |
| 5654 // mem : S3(read); | |
| 5655 // src : S5(read); | |
| 5656 // D0 : S0(2); // big decoder only; twice | |
| 5657 // ALU : S4(2); // any 2 alus | |
| 5658 // MEM : S3(2); // Both mems | |
| 5659 // %} | |
| 5660 | |
| 5661 // Integer Store to Memory | |
| 5662 pipe_class ialu_mem_imm(memory mem) | |
| 5663 %{ | |
| 5664 single_instruction; | |
| 5665 mem : S3(read); | |
| 5666 D0 : S0; // big decoder only | |
| 5667 ALU : S4; // any alu | |
| 5668 MEM : S3; | |
| 5669 %} | |
| 5670 | |
| 5671 // Integer ALU0 reg-reg operation | |
| 5672 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) | |
| 5673 %{ | |
| 5674 single_instruction; | |
| 5675 dst : S4(write); | |
| 5676 src : S3(read); | |
| 5677 D0 : S0; // Big decoder only | |
| 5678 ALU0 : S3; // only alu0 | |
| 5679 %} | |
| 5680 | |
| 5681 // Integer ALU0 reg-mem operation | |
| 5682 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) | |
| 5683 %{ | |
| 5684 single_instruction; | |
| 5685 dst : S5(write); | |
| 5686 mem : S3(read); | |
| 5687 D0 : S0; // big decoder only | |
| 5688 ALU0 : S4; // ALU0 only | |
| 5689 MEM : S3; // any mem | |
| 5690 %} | |
| 5691 | |
| 5692 // Integer ALU reg-reg operation | |
| 5693 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2) | |
| 5694 %{ | |
| 5695 single_instruction; | |
| 5696 cr : S4(write); | |
| 5697 src1 : S3(read); | |
| 5698 src2 : S3(read); | |
| 5699 DECODE : S0; // any decoder | |
| 5700 ALU : S3; // any alu | |
| 5701 %} | |
| 5702 | |
| 5703 // Integer ALU reg-imm operation | |
| 5704 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1) | |
| 5705 %{ | |
| 5706 single_instruction; | |
| 5707 cr : S4(write); | |
| 5708 src1 : S3(read); | |
| 5709 DECODE : S0; // any decoder | |
| 5710 ALU : S3; // any alu | |
| 5711 %} | |
| 5712 | |
| 5713 // Integer ALU reg-mem operation | |
| 5714 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2) | |
| 5715 %{ | |
| 5716 single_instruction; | |
| 5717 cr : S4(write); | |
| 5718 src1 : S3(read); | |
| 5719 src2 : S3(read); | |
| 5720 D0 : S0; // big decoder only | |
| 5721 ALU : S4; // any alu | |
| 5722 MEM : S3; | |
| 5723 %} | |
| 5724 | |
| 5725 // Conditional move reg-reg | |
| 5726 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y) | |
| 5727 %{ | |
| 5728 instruction_count(4); | |
| 5729 y : S4(read); | |
| 5730 q : S3(read); | |
| 5731 p : S3(read); | |
| 5732 DECODE : S0(4); // any decoder | |
| 5733 %} | |
| 5734 | |
| 5735 // Conditional move reg-reg | |
| 5736 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr) | |
| 5737 %{ | |
| 5738 single_instruction; | |
| 5739 dst : S4(write); | |
| 5740 src : S3(read); | |
| 5741 cr : S3(read); | |
| 5742 DECODE : S0; // any decoder | |
| 5743 %} | |
| 5744 | |
| 5745 // Conditional move reg-mem | |
| 5746 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src) | |
| 5747 %{ | |
| 5748 single_instruction; | |
| 5749 dst : S4(write); | |
| 5750 src : S3(read); | |
| 5751 cr : S3(read); | |
| 5752 DECODE : S0; // any decoder | |
| 5753 MEM : S3; | |
| 5754 %} | |
| 5755 | |
| 5756 // Conditional move reg-reg long | |
| 5757 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src) | |
| 5758 %{ | |
| 5759 single_instruction; | |
| 5760 dst : S4(write); | |
| 5761 src : S3(read); | |
| 5762 cr : S3(read); | |
| 5763 DECODE : S0(2); // any 2 decoders | |
| 5764 %} | |
| 5765 | |
| 5766 // XXX | |
| 5767 // // Conditional move double reg-reg | |
| 5768 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src) | |
| 5769 // %{ | |
| 5770 // single_instruction; | |
| 5771 // dst : S4(write); | |
| 5772 // src : S3(read); | |
| 5773 // cr : S3(read); | |
| 5774 // DECODE : S0; // any decoder | |
| 5775 // %} | |
| 5776 | |
| 5777 // Float reg-reg operation | |
| 5778 pipe_class fpu_reg(regD dst) | |
| 5779 %{ | |
| 5780 instruction_count(2); | |
| 5781 dst : S3(read); | |
| 5782 DECODE : S0(2); // any 2 decoders | |
| 5783 FPU : S3; | |
| 5784 %} | |
| 5785 | |
| 5786 // Float reg-reg operation | |
| 5787 pipe_class fpu_reg_reg(regD dst, regD src) | |
| 5788 %{ | |
| 5789 instruction_count(2); | |
| 5790 dst : S4(write); | |
| 5791 src : S3(read); | |
| 5792 DECODE : S0(2); // any 2 decoders | |
| 5793 FPU : S3; | |
| 5794 %} | |
| 5795 | |
| 5796 // Float reg-reg operation | |
| 5797 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2) | |
| 5798 %{ | |
| 5799 instruction_count(3); | |
| 5800 dst : S4(write); | |
| 5801 src1 : S3(read); | |
| 5802 src2 : S3(read); | |
| 5803 DECODE : S0(3); // any 3 decoders | |
| 5804 FPU : S3(2); | |
| 5805 %} | |
| 5806 | |
| 5807 // Float reg-reg operation | |
| 5808 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3) | |
| 5809 %{ | |
| 5810 instruction_count(4); | |
| 5811 dst : S4(write); | |
| 5812 src1 : S3(read); | |
| 5813 src2 : S3(read); | |
| 5814 src3 : S3(read); | |
| 5815 DECODE : S0(4); // any 3 decoders | |
| 5816 FPU : S3(2); | |
| 5817 %} | |
| 5818 | |
| 5819 // Float reg-reg operation | |
| 5820 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3) | |
| 5821 %{ | |
| 5822 instruction_count(4); | |
| 5823 dst : S4(write); | |
| 5824 src1 : S3(read); | |
| 5825 src2 : S3(read); | |
| 5826 src3 : S3(read); | |
| 5827 DECODE : S1(3); // any 3 decoders | |
| 5828 D0 : S0; // Big decoder only | |
| 5829 FPU : S3(2); | |
| 5830 MEM : S3; | |
| 5831 %} | |
| 5832 | |
| 5833 // Float reg-mem operation | |
| 5834 pipe_class fpu_reg_mem(regD dst, memory mem) | |
| 5835 %{ | |
| 5836 instruction_count(2); | |
| 5837 dst : S5(write); | |
| 5838 mem : S3(read); | |
| 5839 D0 : S0; // big decoder only | |
| 5840 DECODE : S1; // any decoder for FPU POP | |
| 5841 FPU : S4; | |
| 5842 MEM : S3; // any mem | |
| 5843 %} | |
| 5844 | |
| 5845 // Float reg-mem operation | |
| 5846 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem) | |
| 5847 %{ | |
| 5848 instruction_count(3); | |
| 5849 dst : S5(write); | |
| 5850 src1 : S3(read); | |
| 5851 mem : S3(read); | |
| 5852 D0 : S0; // big decoder only | |
| 5853 DECODE : S1(2); // any decoder for FPU POP | |
| 5854 FPU : S4; | |
| 5855 MEM : S3; // any mem | |
| 5856 %} | |
| 5857 | |
| 5858 // Float mem-reg operation | |
| 5859 pipe_class fpu_mem_reg(memory mem, regD src) | |
| 5860 %{ | |
| 5861 instruction_count(2); | |
| 5862 src : S5(read); | |
| 5863 mem : S3(read); | |
| 5864 DECODE : S0; // any decoder for FPU PUSH | |
| 5865 D0 : S1; // big decoder only | |
| 5866 FPU : S4; | |
| 5867 MEM : S3; // any mem | |
| 5868 %} | |
| 5869 | |
| 5870 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2) | |
| 5871 %{ | |
| 5872 instruction_count(3); | |
| 5873 src1 : S3(read); | |
| 5874 src2 : S3(read); | |
| 5875 mem : S3(read); | |
| 5876 DECODE : S0(2); // any decoder for FPU PUSH | |
| 5877 D0 : S1; // big decoder only | |
| 5878 FPU : S4; | |
| 5879 MEM : S3; // any mem | |
| 5880 %} | |
| 5881 | |
| 5882 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2) | |
| 5883 %{ | |
| 5884 instruction_count(3); | |
| 5885 src1 : S3(read); | |
| 5886 src2 : S3(read); | |
| 5887 mem : S4(read); | |
| 5888 DECODE : S0; // any decoder for FPU PUSH | |
| 5889 D0 : S0(2); // big decoder only | |
| 5890 FPU : S4; | |
| 5891 MEM : S3(2); // any mem | |
| 5892 %} | |
| 5893 | |
| 5894 pipe_class fpu_mem_mem(memory dst, memory src1) | |
| 5895 %{ | |
| 5896 instruction_count(2); | |
| 5897 src1 : S3(read); | |
| 5898 dst : S4(read); | |
| 5899 D0 : S0(2); // big decoder only | |
| 5900 MEM : S3(2); // any mem | |
| 5901 %} | |
| 5902 | |
| 5903 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) | |
| 5904 %{ | |
| 5905 instruction_count(3); | |
| 5906 src1 : S3(read); | |
| 5907 src2 : S3(read); | |
| 5908 dst : S4(read); | |
| 5909 D0 : S0(3); // big decoder only | |
| 5910 FPU : S4; | |
| 5911 MEM : S3(3); // any mem | |
| 5912 %} | |
| 5913 | |
| 5914 pipe_class fpu_mem_reg_con(memory mem, regD src1) | |
| 5915 %{ | |
| 5916 instruction_count(3); | |
| 5917 src1 : S4(read); | |
| 5918 mem : S4(read); | |
| 5919 DECODE : S0; // any decoder for FPU PUSH | |
| 5920 D0 : S0(2); // big decoder only | |
| 5921 FPU : S4; | |
| 5922 MEM : S3(2); // any mem | |
| 5923 %} | |
| 5924 | |
| 5925 // Float load constant | |
| 5926 pipe_class fpu_reg_con(regD dst) | |
| 5927 %{ | |
| 5928 instruction_count(2); | |
| 5929 dst : S5(write); | |
| 5930 D0 : S0; // big decoder only for the load | |
| 5931 DECODE : S1; // any decoder for FPU POP | |
| 5932 FPU : S4; | |
| 5933 MEM : S3; // any mem | |
| 5934 %} | |
| 5935 | |
| 5936 // Float load constant | |
| 5937 pipe_class fpu_reg_reg_con(regD dst, regD src) | |
| 5938 %{ | |
| 5939 instruction_count(3); | |
| 5940 dst : S5(write); | |
| 5941 src : S3(read); | |
| 5942 D0 : S0; // big decoder only for the load | |
| 5943 DECODE : S1(2); // any decoder for FPU POP | |
| 5944 FPU : S4; | |
| 5945 MEM : S3; // any mem | |
| 5946 %} | |
| 5947 | |
| 5948 // UnConditional branch | |
| 5949 pipe_class pipe_jmp(label labl) | |
| 5950 %{ | |
| 5951 single_instruction; | |
| 5952 BR : S3; | |
| 5953 %} | |
| 5954 | |
| 5955 // Conditional branch | |
| 5956 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl) | |
| 5957 %{ | |
| 5958 single_instruction; | |
| 5959 cr : S1(read); | |
| 5960 BR : S3; | |
| 5961 %} | |
| 5962 | |
| 5963 // Allocation idiom | |
| 5964 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr) | |
| 5965 %{ | |
| 5966 instruction_count(1); force_serialization; | |
| 5967 fixed_latency(6); | |
| 5968 heap_ptr : S3(read); | |
| 5969 DECODE : S0(3); | |
| 5970 D0 : S2; | |
| 5971 MEM : S3; | |
| 5972 ALU : S3(2); | |
| 5973 dst : S5(write); | |
| 5974 BR : S5; | |
| 5975 %} | |
| 5976 | |
| 5977 // Generic big/slow expanded idiom | |
| 5978 pipe_class pipe_slow() | |
| 5979 %{ | |
| 5980 instruction_count(10); multiple_bundles; force_serialization; | |
| 5981 fixed_latency(100); | |
| 5982 D0 : S0(2); | |
| 5983 MEM : S3(2); | |
| 5984 %} | |
| 5985 | |
| 5986 // The real do-nothing guy | |
| 5987 pipe_class empty() | |
| 5988 %{ | |
| 5989 instruction_count(0); | |
| 5990 %} | |
| 5991 | |
| 5992 // Define the class for the Nop node | |
| 5993 define | |
| 5994 %{ | |
| 5995 MachNop = empty; | |
| 5996 %} | |
| 5997 | |
| 5998 %} | |
| 5999 | |
| 6000 //----------INSTRUCTIONS------------------------------------------------------- | |
| 6001 // | |
| 6002 // match -- States which machine-independent subtree may be replaced | |
| 6003 // by this instruction. | |
| 6004 // ins_cost -- The estimated cost of this instruction is used by instruction | |
| 6005 // selection to identify a minimum cost tree of machine | |
| 6006 // instructions that matches a tree of machine-independent | |
| 6007 // instructions. | |
| 6008 // format -- A string providing the disassembly for this instruction. | |
| 6009 // The value of an instruction's operand may be inserted | |
| 6010 // by referring to it with a '$' prefix. | |
| 6011 // opcode -- Three instruction opcodes may be provided. These are referred | |
| 6012 // to within an encode class as $primary, $secondary, and $tertiary | |
| 6013 // rrspectively. The primary opcode is commonly used to | |
| 6014 // indicate the type of machine instruction, while secondary | |
| 6015 // and tertiary are often used for prefix options or addressing | |
| 6016 // modes. | |
| 6017 // ins_encode -- A list of encode classes with parameters. The encode class | |
| 6018 // name must have been defined in an 'enc_class' specification | |
| 6019 // in the encode section of the architecture description. | |
| 6020 | |
| 6021 | |
| 6022 //----------Load/Store/Move Instructions--------------------------------------- | |
| 6023 //----------Load Instructions-------------------------------------------------- | |
| 6024 | |
| 6025 // Load Byte (8 bit signed) | |
| 6026 instruct loadB(rRegI dst, memory mem) | |
| 6027 %{ | |
| 6028 match(Set dst (LoadB mem)); | |
| 6029 | |
| 6030 ins_cost(125); | |
| 6031 format %{ "movsbl $dst, $mem\t# byte" %} | |
| 624 | 6032 |
| 6033 ins_encode %{ | |
| 6034 __ movsbl($dst$$Register, $mem$$Address); | |
| 6035 %} | |
| 6036 | |
| 0 | 6037 ins_pipe(ialu_reg_mem); |
| 6038 %} | |
| 6039 | |
| 624 | 6040 // Load Byte (8 bit signed) into Long Register |
| 6041 instruct loadB2L(rRegL dst, memory mem) | |
| 6042 %{ | |
| 6043 match(Set dst (ConvI2L (LoadB mem))); | |
| 6044 | |
| 6045 ins_cost(125); | |
| 6046 format %{ "movsbq $dst, $mem\t# byte -> long" %} | |
| 6047 | |
| 6048 ins_encode %{ | |
| 6049 __ movsbq($dst$$Register, $mem$$Address); | |
| 6050 %} | |
| 6051 | |
| 6052 ins_pipe(ialu_reg_mem); | |
| 6053 %} | |
| 6054 | |
| 6055 // Load Unsigned Byte (8 bit UNsigned) | |
| 6056 instruct loadUB(rRegI dst, memory mem) | |
| 6057 %{ | |
| 6058 match(Set dst (LoadUB mem)); | |
| 0 | 6059 |
| 6060 ins_cost(125); | |
| 6061 format %{ "movzbl $dst, $mem\t# ubyte" %} | |
| 624 | 6062 |
| 6063 ins_encode %{ | |
| 6064 __ movzbl($dst$$Register, $mem$$Address); | |
| 6065 %} | |
| 6066 | |
| 0 | 6067 ins_pipe(ialu_reg_mem); |
| 6068 %} | |
| 6069 | |
| 624 | 6070 // Load Unsigned Byte (8 bit UNsigned) into Long Register |
| 6071 instruct loadUB2L(rRegL dst, memory mem) | |
| 6072 %{ | |
| 6073 match(Set dst (ConvI2L (LoadUB mem))); | |
| 6074 | |
| 6075 ins_cost(125); | |
| 6076 format %{ "movzbq $dst, $mem\t# ubyte -> long" %} | |
| 6077 | |
| 6078 ins_encode %{ | |
| 6079 __ movzbq($dst$$Register, $mem$$Address); | |
| 6080 %} | |
| 6081 | |
| 6082 ins_pipe(ialu_reg_mem); | |
| 6083 %} | |
| 0 | 6084 |
| 6085 // Load Short (16 bit signed) | |
| 6086 instruct loadS(rRegI dst, memory mem) | |
| 6087 %{ | |
| 6088 match(Set dst (LoadS mem)); | |
| 6089 | |
| 624 | 6090 ins_cost(125); |
| 0 | 6091 format %{ "movswl $dst, $mem\t# short" %} |
| 624 | 6092 |
| 6093 ins_encode %{ | |
| 6094 __ movswl($dst$$Register, $mem$$Address); | |
| 6095 %} | |
| 6096 | |
| 0 | 6097 ins_pipe(ialu_reg_mem); |
| 6098 %} | |
| 6099 | |
| 624 | 6100 // Load Short (16 bit signed) into Long Register |
| 6101 instruct loadS2L(rRegL dst, memory mem) | |
| 6102 %{ | |
| 6103 match(Set dst (ConvI2L (LoadS mem))); | |
| 6104 | |
| 6105 ins_cost(125); | |
| 6106 format %{ "movswq $dst, $mem\t# short -> long" %} | |
| 6107 | |
| 6108 ins_encode %{ | |
| 6109 __ movswq($dst$$Register, $mem$$Address); | |
| 6110 %} | |
| 6111 | |
| 6112 ins_pipe(ialu_reg_mem); | |
| 6113 %} | |
| 0 | 6114 |
|
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6115 // Load Unsigned Short/Char (16 bit UNsigned) |
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6116 instruct loadUS(rRegI dst, memory mem) |
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6117 %{ |
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6118 match(Set dst (LoadUS mem)); |
| 0 | 6119 |
| 6120 ins_cost(125); | |
|
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6121 format %{ "movzwl $dst, $mem\t# ushort/char" %} |
| 624 | 6122 |
| 6123 ins_encode %{ | |
| 6124 __ movzwl($dst$$Register, $mem$$Address); | |
| 6125 %} | |
| 6126 | |
| 0 | 6127 ins_pipe(ialu_reg_mem); |
| 6128 %} | |
| 6129 | |
| 624 | 6130 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register |
| 6131 instruct loadUS2L(rRegL dst, memory mem) | |
| 6132 %{ | |
| 6133 match(Set dst (ConvI2L (LoadUS mem))); | |
| 6134 | |
| 6135 ins_cost(125); | |
| 6136 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %} | |
| 6137 | |
| 6138 ins_encode %{ | |
| 6139 __ movzwq($dst$$Register, $mem$$Address); | |
| 6140 %} | |
| 6141 | |
| 6142 ins_pipe(ialu_reg_mem); | |
| 6143 %} | |
| 0 | 6144 |
| 6145 // Load Integer | |
| 6146 instruct loadI(rRegI dst, memory mem) | |
| 6147 %{ | |
| 6148 match(Set dst (LoadI mem)); | |
| 6149 | |
| 624 | 6150 ins_cost(125); |
| 0 | 6151 format %{ "movl $dst, $mem\t# int" %} |
| 624 | 6152 |
| 6153 ins_encode %{ | |
| 6154 __ movl($dst$$Register, $mem$$Address); | |
| 6155 %} | |
| 6156 | |
| 6157 ins_pipe(ialu_reg_mem); | |
| 6158 %} | |
| 6159 | |
| 6160 // Load Integer into Long Register | |
| 6161 instruct loadI2L(rRegL dst, memory mem) | |
| 6162 %{ | |
| 6163 match(Set dst (ConvI2L (LoadI mem))); | |
| 6164 | |
| 6165 ins_cost(125); | |
| 6166 format %{ "movslq $dst, $mem\t# int -> long" %} | |
| 6167 | |
| 6168 ins_encode %{ | |
| 6169 __ movslq($dst$$Register, $mem$$Address); | |
| 6170 %} | |
| 6171 | |
| 6172 ins_pipe(ialu_reg_mem); | |
| 6173 %} | |
| 6174 | |
| 6175 // Load Unsigned Integer into Long Register | |
| 6176 instruct loadUI2L(rRegL dst, memory mem) | |
| 6177 %{ | |
| 6178 match(Set dst (LoadUI2L mem)); | |
| 6179 | |
| 6180 ins_cost(125); | |
| 6181 format %{ "movl $dst, $mem\t# uint -> long" %} | |
| 6182 | |
| 6183 ins_encode %{ | |
| 6184 __ movl($dst$$Register, $mem$$Address); | |
| 6185 %} | |
| 6186 | |
| 0 | 6187 ins_pipe(ialu_reg_mem); |
| 6188 %} | |
| 6189 | |
| 6190 // Load Long | |
| 6191 instruct loadL(rRegL dst, memory mem) | |
| 6192 %{ | |
| 6193 match(Set dst (LoadL mem)); | |
| 6194 | |
| 624 | 6195 ins_cost(125); |
| 0 | 6196 format %{ "movq $dst, $mem\t# long" %} |
| 624 | 6197 |
| 6198 ins_encode %{ | |
| 6199 __ movq($dst$$Register, $mem$$Address); | |
| 6200 %} | |
| 6201 | |
| 0 | 6202 ins_pipe(ialu_reg_mem); // XXX |
| 6203 %} | |
| 6204 | |
| 6205 // Load Range | |
| 6206 instruct loadRange(rRegI dst, memory mem) | |
| 6207 %{ | |
| 6208 match(Set dst (LoadRange mem)); | |
| 6209 | |
| 6210 ins_cost(125); // XXX | |
| 6211 format %{ "movl $dst, $mem\t# range" %} | |
| 6212 opcode(0x8B); | |
| 6213 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 6214 ins_pipe(ialu_reg_mem); | |
| 6215 %} | |
| 6216 | |
| 6217 // Load Pointer | |
| 6218 instruct loadP(rRegP dst, memory mem) | |
| 6219 %{ | |
| 6220 match(Set dst (LoadP mem)); | |
| 6221 | |
| 6222 ins_cost(125); // XXX | |
| 6223 format %{ "movq $dst, $mem\t# ptr" %} | |
| 6224 opcode(0x8B); | |
| 6225 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 6226 ins_pipe(ialu_reg_mem); // XXX | |
| 6227 %} | |
| 6228 | |
|
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6229 // Load Compressed Pointer |
| 163 | 6230 instruct loadN(rRegN dst, memory mem) |
|
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6231 %{ |
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6232 match(Set dst (LoadN mem)); |
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6233 |
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6234 ins_cost(125); // XXX |
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6235 format %{ "movl $dst, $mem\t# compressed ptr" %} |
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6236 ins_encode %{ |
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6237 Address addr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp); |
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6238 Register dst = as_Register($dst$$reg); |
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6239 __ movl(dst, addr); |
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6240 %} |
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6241 ins_pipe(ialu_reg_mem); // XXX |
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6242 %} |
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6243 |
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6244 |
| 0 | 6245 // Load Klass Pointer |
| 6246 instruct loadKlass(rRegP dst, memory mem) | |
| 6247 %{ | |
| 6248 match(Set dst (LoadKlass mem)); | |
| 6249 | |
| 6250 ins_cost(125); // XXX | |
| 6251 format %{ "movq $dst, $mem\t# class" %} | |
| 6252 opcode(0x8B); | |
| 6253 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 6254 ins_pipe(ialu_reg_mem); // XXX | |
| 6255 %} | |
| 6256 | |
|
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6257 // Load narrow Klass Pointer |
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6258 instruct loadNKlass(rRegN dst, memory mem) |
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6259 %{ |
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6260 match(Set dst (LoadNKlass mem)); |
|
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6261 |
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6262 ins_cost(125); // XXX |
|
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6263 format %{ "movl $dst, $mem\t# compressed klass ptr" %} |
|
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6264 ins_encode %{ |
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6265 Address addr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp); |
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6266 Register dst = as_Register($dst$$reg); |
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6267 __ movl(dst, addr); |
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6268 %} |
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6269 ins_pipe(ialu_reg_mem); // XXX |
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6270 %} |
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6271 |
| 0 | 6272 // Load Float |
| 6273 instruct loadF(regF dst, memory mem) | |
| 6274 %{ | |
| 6275 match(Set dst (LoadF mem)); | |
| 6276 | |
| 6277 ins_cost(145); // XXX | |
| 6278 format %{ "movss $dst, $mem\t# float" %} | |
| 6279 opcode(0xF3, 0x0F, 0x10); | |
| 6280 ins_encode(OpcP, REX_reg_mem(dst, mem), OpcS, OpcT, reg_mem(dst, mem)); | |
| 6281 ins_pipe(pipe_slow); // XXX | |
| 6282 %} | |
| 6283 | |
| 6284 // Load Double | |
| 6285 instruct loadD_partial(regD dst, memory mem) | |
| 6286 %{ | |
| 6287 predicate(!UseXmmLoadAndClearUpper); | |
| 6288 match(Set dst (LoadD mem)); | |
| 6289 | |
| 6290 ins_cost(145); // XXX | |
| 6291 format %{ "movlpd $dst, $mem\t# double" %} | |
| 6292 opcode(0x66, 0x0F, 0x12); | |
| 6293 ins_encode(OpcP, REX_reg_mem(dst, mem), OpcS, OpcT, reg_mem(dst, mem)); | |
| 6294 ins_pipe(pipe_slow); // XXX | |
| 6295 %} | |
| 6296 | |
| 6297 instruct loadD(regD dst, memory mem) | |
| 6298 %{ | |
| 6299 predicate(UseXmmLoadAndClearUpper); | |
| 6300 match(Set dst (LoadD mem)); | |
| 6301 | |
| 6302 ins_cost(145); // XXX | |
| 6303 format %{ "movsd $dst, $mem\t# double" %} | |
| 6304 opcode(0xF2, 0x0F, 0x10); | |
| 6305 ins_encode(OpcP, REX_reg_mem(dst, mem), OpcS, OpcT, reg_mem(dst, mem)); | |
| 6306 ins_pipe(pipe_slow); // XXX | |
| 6307 %} | |
| 6308 | |
| 6309 // Load Aligned Packed Byte to XMM register | |
| 6310 instruct loadA8B(regD dst, memory mem) %{ | |
| 6311 match(Set dst (Load8B mem)); | |
| 6312 ins_cost(125); | |
| 6313 format %{ "MOVQ $dst,$mem\t! packed8B" %} | |
| 6314 ins_encode( movq_ld(dst, mem)); | |
| 6315 ins_pipe( pipe_slow ); | |
| 6316 %} | |
| 6317 | |
| 6318 // Load Aligned Packed Short to XMM register | |
| 6319 instruct loadA4S(regD dst, memory mem) %{ | |
| 6320 match(Set dst (Load4S mem)); | |
| 6321 ins_cost(125); | |
| 6322 format %{ "MOVQ $dst,$mem\t! packed4S" %} | |
| 6323 ins_encode( movq_ld(dst, mem)); | |
| 6324 ins_pipe( pipe_slow ); | |
| 6325 %} | |
| 6326 | |
| 6327 // Load Aligned Packed Char to XMM register | |
| 6328 instruct loadA4C(regD dst, memory mem) %{ | |
| 6329 match(Set dst (Load4C mem)); | |
| 6330 ins_cost(125); | |
| 6331 format %{ "MOVQ $dst,$mem\t! packed4C" %} | |
| 6332 ins_encode( movq_ld(dst, mem)); | |
| 6333 ins_pipe( pipe_slow ); | |
| 6334 %} | |
| 6335 | |
| 6336 // Load Aligned Packed Integer to XMM register | |
| 6337 instruct load2IU(regD dst, memory mem) %{ | |
| 6338 match(Set dst (Load2I mem)); | |
| 6339 ins_cost(125); | |
| 6340 format %{ "MOVQ $dst,$mem\t! packed2I" %} | |
| 6341 ins_encode( movq_ld(dst, mem)); | |
| 6342 ins_pipe( pipe_slow ); | |
| 6343 %} | |
| 6344 | |
| 6345 // Load Aligned Packed Single to XMM | |
| 6346 instruct loadA2F(regD dst, memory mem) %{ | |
| 6347 match(Set dst (Load2F mem)); | |
| 6348 ins_cost(145); | |
| 6349 format %{ "MOVQ $dst,$mem\t! packed2F" %} | |
| 6350 ins_encode( movq_ld(dst, mem)); | |
| 6351 ins_pipe( pipe_slow ); | |
| 6352 %} | |
| 6353 | |
| 6354 // Load Effective Address | |
| 6355 instruct leaP8(rRegP dst, indOffset8 mem) | |
| 6356 %{ | |
| 6357 match(Set dst mem); | |
| 6358 | |
| 6359 ins_cost(110); // XXX | |
| 6360 format %{ "leaq $dst, $mem\t# ptr 8" %} | |
| 6361 opcode(0x8D); | |
| 6362 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 6363 ins_pipe(ialu_reg_reg_fat); | |
| 6364 %} | |
| 6365 | |
| 6366 instruct leaP32(rRegP dst, indOffset32 mem) | |
| 6367 %{ | |
| 6368 match(Set dst mem); | |
| 6369 | |
| 6370 ins_cost(110); | |
| 6371 format %{ "leaq $dst, $mem\t# ptr 32" %} | |
| 6372 opcode(0x8D); | |
| 6373 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 6374 ins_pipe(ialu_reg_reg_fat); | |
| 6375 %} | |
| 6376 | |
| 6377 // instruct leaPIdx(rRegP dst, indIndex mem) | |
| 6378 // %{ | |
| 6379 // match(Set dst mem); | |
| 6380 | |
| 6381 // ins_cost(110); | |
| 6382 // format %{ "leaq $dst, $mem\t# ptr idx" %} | |
| 6383 // opcode(0x8D); | |
| 6384 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 6385 // ins_pipe(ialu_reg_reg_fat); | |
| 6386 // %} | |
| 6387 | |
| 6388 instruct leaPIdxOff(rRegP dst, indIndexOffset mem) | |
| 6389 %{ | |
| 6390 match(Set dst mem); | |
| 6391 | |
| 6392 ins_cost(110); | |
| 6393 format %{ "leaq $dst, $mem\t# ptr idxoff" %} | |
| 6394 opcode(0x8D); | |
| 6395 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 6396 ins_pipe(ialu_reg_reg_fat); | |
| 6397 %} | |
| 6398 | |
| 6399 instruct leaPIdxScale(rRegP dst, indIndexScale mem) | |
| 6400 %{ | |
| 6401 match(Set dst mem); | |
| 6402 | |
| 6403 ins_cost(110); | |
| 6404 format %{ "leaq $dst, $mem\t# ptr idxscale" %} | |
| 6405 opcode(0x8D); | |
| 6406 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 6407 ins_pipe(ialu_reg_reg_fat); | |
| 6408 %} | |
| 6409 | |
| 6410 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem) | |
| 6411 %{ | |
| 6412 match(Set dst mem); | |
| 6413 | |
| 6414 ins_cost(110); | |
| 6415 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %} | |
| 6416 opcode(0x8D); | |
| 6417 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 6418 ins_pipe(ialu_reg_reg_fat); | |
| 6419 %} | |
| 6420 | |
| 6421 instruct loadConI(rRegI dst, immI src) | |
| 6422 %{ | |
| 6423 match(Set dst src); | |
| 6424 | |
| 6425 format %{ "movl $dst, $src\t# int" %} | |
| 6426 ins_encode(load_immI(dst, src)); | |
| 6427 ins_pipe(ialu_reg_fat); // XXX | |
| 6428 %} | |
| 6429 | |
| 6430 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr) | |
| 6431 %{ | |
| 6432 match(Set dst src); | |
| 6433 effect(KILL cr); | |
| 6434 | |
| 6435 ins_cost(50); | |
| 6436 format %{ "xorl $dst, $dst\t# int" %} | |
| 6437 opcode(0x33); /* + rd */ | |
| 6438 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst)); | |
| 6439 ins_pipe(ialu_reg); | |
| 6440 %} | |
| 6441 | |
| 6442 instruct loadConL(rRegL dst, immL src) | |
| 6443 %{ | |
| 6444 match(Set dst src); | |
| 6445 | |
| 6446 ins_cost(150); | |
| 6447 format %{ "movq $dst, $src\t# long" %} | |
| 6448 ins_encode(load_immL(dst, src)); | |
| 6449 ins_pipe(ialu_reg); | |
| 6450 %} | |
| 6451 | |
| 6452 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr) | |
| 6453 %{ | |
| 6454 match(Set dst src); | |
| 6455 effect(KILL cr); | |
| 6456 | |
| 6457 ins_cost(50); | |
| 6458 format %{ "xorl $dst, $dst\t# long" %} | |
| 6459 opcode(0x33); /* + rd */ | |
| 6460 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst)); | |
| 6461 ins_pipe(ialu_reg); // XXX | |
| 6462 %} | |
| 6463 | |
| 6464 instruct loadConUL32(rRegL dst, immUL32 src) | |
| 6465 %{ | |
| 6466 match(Set dst src); | |
| 6467 | |
| 6468 ins_cost(60); | |
| 6469 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %} | |
| 6470 ins_encode(load_immUL32(dst, src)); | |
| 6471 ins_pipe(ialu_reg); | |
| 6472 %} | |
| 6473 | |
| 6474 instruct loadConL32(rRegL dst, immL32 src) | |
| 6475 %{ | |
| 6476 match(Set dst src); | |
| 6477 | |
| 6478 ins_cost(70); | |
| 6479 format %{ "movq $dst, $src\t# long (32-bit)" %} | |
| 6480 ins_encode(load_immL32(dst, src)); | |
| 6481 ins_pipe(ialu_reg); | |
| 6482 %} | |
| 6483 | |
| 6484 instruct loadConP(rRegP dst, immP src) | |
| 6485 %{ | |
| 6486 match(Set dst src); | |
| 6487 | |
| 6488 format %{ "movq $dst, $src\t# ptr" %} | |
| 6489 ins_encode(load_immP(dst, src)); | |
| 6490 ins_pipe(ialu_reg_fat); // XXX | |
| 6491 %} | |
| 6492 | |
| 6493 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr) | |
| 6494 %{ | |
| 6495 match(Set dst src); | |
| 6496 effect(KILL cr); | |
| 6497 | |
| 6498 ins_cost(50); | |
| 6499 format %{ "xorl $dst, $dst\t# ptr" %} | |
| 6500 opcode(0x33); /* + rd */ | |
| 6501 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst)); | |
| 6502 ins_pipe(ialu_reg); | |
| 6503 %} | |
| 6504 | |
| 6505 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr) | |
| 6506 %{ | |
| 6507 match(Set dst src); | |
| 6508 effect(KILL cr); | |
| 6509 | |
| 6510 ins_cost(60); | |
| 6511 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %} | |
| 6512 ins_encode(load_immP31(dst, src)); | |
| 6513 ins_pipe(ialu_reg); | |
| 6514 %} | |
| 6515 | |
| 6516 instruct loadConF(regF dst, immF src) | |
| 6517 %{ | |
| 6518 match(Set dst src); | |
| 6519 ins_cost(125); | |
| 6520 | |
| 6521 format %{ "movss $dst, [$src]" %} | |
| 6522 ins_encode(load_conF(dst, src)); | |
| 6523 ins_pipe(pipe_slow); | |
| 6524 %} | |
| 6525 | |
|
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6526 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{ |
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6527 match(Set dst src); |
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6528 effect(KILL cr); |
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6529 format %{ "xorq $dst, $src\t# compressed NULL ptr" %} |
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6530 ins_encode %{ |
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6531 Register dst = $dst$$Register; |
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6532 __ xorq(dst, dst); |
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6533 %} |
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6534 ins_pipe(ialu_reg); |
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6535 %} |
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6536 |
|
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6537 instruct loadConN(rRegN dst, immN src) %{ |
|
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6538 match(Set dst src); |
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6539 |
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6540 ins_cost(125); |
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6541 format %{ "movl $dst, $src\t# compressed ptr" %} |
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6542 ins_encode %{ |
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6543 address con = (address)$src$$constant; |
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6544 Register dst = $dst$$Register; |
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6545 if (con == NULL) { |
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6546 ShouldNotReachHere(); |
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6547 } else { |
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6548 __ set_narrow_oop(dst, (jobject)$src$$constant); |
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6549 } |
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6550 %} |
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6551 ins_pipe(ialu_reg_fat); // XXX |
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6552 %} |
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6553 |
| 0 | 6554 instruct loadConF0(regF dst, immF0 src) |
| 6555 %{ | |
| 6556 match(Set dst src); | |
| 6557 ins_cost(100); | |
| 6558 | |
| 6559 format %{ "xorps $dst, $dst\t# float 0.0" %} | |
| 6560 opcode(0x0F, 0x57); | |
| 6561 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 6562 ins_pipe(pipe_slow); | |
| 6563 %} | |
| 6564 | |
| 6565 // Use the same format since predicate() can not be used here. | |
| 6566 instruct loadConD(regD dst, immD src) | |
| 6567 %{ | |
| 6568 match(Set dst src); | |
| 6569 ins_cost(125); | |
| 6570 | |
| 6571 format %{ "movsd $dst, [$src]" %} | |
| 6572 ins_encode(load_conD(dst, src)); | |
| 6573 ins_pipe(pipe_slow); | |
| 6574 %} | |
| 6575 | |
| 6576 instruct loadConD0(regD dst, immD0 src) | |
| 6577 %{ | |
| 6578 match(Set dst src); | |
| 6579 ins_cost(100); | |
| 6580 | |
| 6581 format %{ "xorpd $dst, $dst\t# double 0.0" %} | |
| 6582 opcode(0x66, 0x0F, 0x57); | |
| 6583 ins_encode(OpcP, REX_reg_reg(dst, dst), OpcS, OpcT, reg_reg(dst, dst)); | |
| 6584 ins_pipe(pipe_slow); | |
| 6585 %} | |
| 6586 | |
| 6587 instruct loadSSI(rRegI dst, stackSlotI src) | |
| 6588 %{ | |
| 6589 match(Set dst src); | |
| 6590 | |
| 6591 ins_cost(125); | |
| 6592 format %{ "movl $dst, $src\t# int stk" %} | |
| 6593 opcode(0x8B); | |
| 6594 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 6595 ins_pipe(ialu_reg_mem); | |
| 6596 %} | |
| 6597 | |
| 6598 instruct loadSSL(rRegL dst, stackSlotL src) | |
| 6599 %{ | |
| 6600 match(Set dst src); | |
| 6601 | |
| 6602 ins_cost(125); | |
| 6603 format %{ "movq $dst, $src\t# long stk" %} | |
| 6604 opcode(0x8B); | |
| 6605 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 6606 ins_pipe(ialu_reg_mem); | |
| 6607 %} | |
| 6608 | |
| 6609 instruct loadSSP(rRegP dst, stackSlotP src) | |
| 6610 %{ | |
| 6611 match(Set dst src); | |
| 6612 | |
| 6613 ins_cost(125); | |
| 6614 format %{ "movq $dst, $src\t# ptr stk" %} | |
| 6615 opcode(0x8B); | |
| 6616 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 6617 ins_pipe(ialu_reg_mem); | |
| 6618 %} | |
| 6619 | |
| 6620 instruct loadSSF(regF dst, stackSlotF src) | |
| 6621 %{ | |
| 6622 match(Set dst src); | |
| 6623 | |
| 6624 ins_cost(125); | |
| 6625 format %{ "movss $dst, $src\t# float stk" %} | |
| 6626 opcode(0xF3, 0x0F, 0x10); | |
| 6627 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 6628 ins_pipe(pipe_slow); // XXX | |
| 6629 %} | |
| 6630 | |
| 6631 // Use the same format since predicate() can not be used here. | |
| 6632 instruct loadSSD(regD dst, stackSlotD src) | |
| 6633 %{ | |
| 6634 match(Set dst src); | |
| 6635 | |
| 6636 ins_cost(125); | |
| 6637 format %{ "movsd $dst, $src\t# double stk" %} | |
| 6638 ins_encode %{ | |
| 6639 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 6640 %} | |
| 6641 ins_pipe(pipe_slow); // XXX | |
| 6642 %} | |
| 6643 | |
| 6644 // Prefetch instructions. | |
| 6645 // Must be safe to execute with invalid address (cannot fault). | |
| 6646 | |
| 6647 instruct prefetchr( memory mem ) %{ | |
| 6648 predicate(ReadPrefetchInstr==3); | |
| 6649 match(PrefetchRead mem); | |
| 6650 ins_cost(125); | |
| 6651 | |
| 6652 format %{ "PREFETCHR $mem\t# Prefetch into level 1 cache" %} | |
| 6653 opcode(0x0F, 0x0D); /* Opcode 0F 0D /0 */ | |
| 6654 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x00, mem)); | |
| 6655 ins_pipe(ialu_mem); | |
| 6656 %} | |
| 6657 | |
| 6658 instruct prefetchrNTA( memory mem ) %{ | |
| 6659 predicate(ReadPrefetchInstr==0); | |
| 6660 match(PrefetchRead mem); | |
| 6661 ins_cost(125); | |
| 6662 | |
| 6663 format %{ "PREFETCHNTA $mem\t# Prefetch into non-temporal cache for read" %} | |
| 6664 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */ | |
| 6665 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x00, mem)); | |
| 6666 ins_pipe(ialu_mem); | |
| 6667 %} | |
| 6668 | |
| 6669 instruct prefetchrT0( memory mem ) %{ | |
| 6670 predicate(ReadPrefetchInstr==1); | |
| 6671 match(PrefetchRead mem); | |
| 6672 ins_cost(125); | |
| 6673 | |
| 6674 format %{ "PREFETCHT0 $mem\t# prefetch into L1 and L2 caches for read" %} | |
| 6675 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */ | |
| 6676 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x01, mem)); | |
| 6677 ins_pipe(ialu_mem); | |
| 6678 %} | |
| 6679 | |
| 6680 instruct prefetchrT2( memory mem ) %{ | |
| 6681 predicate(ReadPrefetchInstr==2); | |
| 6682 match(PrefetchRead mem); | |
| 6683 ins_cost(125); | |
| 6684 | |
| 6685 format %{ "PREFETCHT2 $mem\t# prefetch into L2 caches for read" %} | |
| 6686 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */ | |
| 6687 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x03, mem)); | |
| 6688 ins_pipe(ialu_mem); | |
| 6689 %} | |
| 6690 | |
| 6691 instruct prefetchw( memory mem ) %{ | |
| 6692 predicate(AllocatePrefetchInstr==3); | |
| 6693 match(PrefetchWrite mem); | |
| 6694 ins_cost(125); | |
| 6695 | |
| 6696 format %{ "PREFETCHW $mem\t# Prefetch into level 1 cache and mark modified" %} | |
| 6697 opcode(0x0F, 0x0D); /* Opcode 0F 0D /1 */ | |
| 6698 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x01, mem)); | |
| 6699 ins_pipe(ialu_mem); | |
| 6700 %} | |
| 6701 | |
| 6702 instruct prefetchwNTA( memory mem ) %{ | |
| 6703 predicate(AllocatePrefetchInstr==0); | |
| 6704 match(PrefetchWrite mem); | |
| 6705 ins_cost(125); | |
| 6706 | |
| 6707 format %{ "PREFETCHNTA $mem\t# Prefetch to non-temporal cache for write" %} | |
| 6708 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */ | |
| 6709 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x00, mem)); | |
| 6710 ins_pipe(ialu_mem); | |
| 6711 %} | |
| 6712 | |
| 6713 instruct prefetchwT0( memory mem ) %{ | |
| 6714 predicate(AllocatePrefetchInstr==1); | |
| 6715 match(PrefetchWrite mem); | |
| 6716 ins_cost(125); | |
| 6717 | |
| 6718 format %{ "PREFETCHT0 $mem\t# Prefetch to level 1 and 2 caches for write" %} | |
| 6719 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */ | |
| 6720 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x01, mem)); | |
| 6721 ins_pipe(ialu_mem); | |
| 6722 %} | |
| 6723 | |
| 6724 instruct prefetchwT2( memory mem ) %{ | |
| 6725 predicate(AllocatePrefetchInstr==2); | |
| 6726 match(PrefetchWrite mem); | |
| 6727 ins_cost(125); | |
| 6728 | |
| 6729 format %{ "PREFETCHT2 $mem\t# Prefetch to level 2 cache for write" %} | |
| 6730 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */ | |
| 6731 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x03, mem)); | |
| 6732 ins_pipe(ialu_mem); | |
| 6733 %} | |
| 6734 | |
| 6735 //----------Store Instructions------------------------------------------------- | |
| 6736 | |
| 6737 // Store Byte | |
| 6738 instruct storeB(memory mem, rRegI src) | |
| 6739 %{ | |
| 6740 match(Set mem (StoreB mem src)); | |
| 6741 | |
| 6742 ins_cost(125); // XXX | |
| 6743 format %{ "movb $mem, $src\t# byte" %} | |
| 6744 opcode(0x88); | |
| 6745 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
| 6746 ins_pipe(ialu_mem_reg); | |
| 6747 %} | |
| 6748 | |
| 6749 // Store Char/Short | |
| 6750 instruct storeC(memory mem, rRegI src) | |
| 6751 %{ | |
| 6752 match(Set mem (StoreC mem src)); | |
| 6753 | |
| 6754 ins_cost(125); // XXX | |
| 6755 format %{ "movw $mem, $src\t# char/short" %} | |
| 6756 opcode(0x89); | |
| 6757 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
| 6758 ins_pipe(ialu_mem_reg); | |
| 6759 %} | |
| 6760 | |
| 6761 // Store Integer | |
| 6762 instruct storeI(memory mem, rRegI src) | |
| 6763 %{ | |
| 6764 match(Set mem (StoreI mem src)); | |
| 6765 | |
| 6766 ins_cost(125); // XXX | |
| 6767 format %{ "movl $mem, $src\t# int" %} | |
| 6768 opcode(0x89); | |
| 6769 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
| 6770 ins_pipe(ialu_mem_reg); | |
| 6771 %} | |
| 6772 | |
| 6773 // Store Long | |
| 6774 instruct storeL(memory mem, rRegL src) | |
| 6775 %{ | |
| 6776 match(Set mem (StoreL mem src)); | |
| 6777 | |
| 6778 ins_cost(125); // XXX | |
| 6779 format %{ "movq $mem, $src\t# long" %} | |
| 6780 opcode(0x89); | |
| 6781 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem)); | |
| 6782 ins_pipe(ialu_mem_reg); // XXX | |
| 6783 %} | |
| 6784 | |
| 6785 // Store Pointer | |
| 6786 instruct storeP(memory mem, any_RegP src) | |
| 6787 %{ | |
| 6788 match(Set mem (StoreP mem src)); | |
| 6789 | |
| 6790 ins_cost(125); // XXX | |
| 6791 format %{ "movq $mem, $src\t# ptr" %} | |
| 6792 opcode(0x89); | |
| 6793 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem)); | |
| 6794 ins_pipe(ialu_mem_reg); | |
| 6795 %} | |
| 6796 | |
| 6797 // Store NULL Pointer, mark word, or other simple pointer constant. | |
| 6798 instruct storeImmP(memory mem, immP31 src) | |
| 6799 %{ | |
| 6800 match(Set mem (StoreP mem src)); | |
| 6801 | |
| 6802 ins_cost(125); // XXX | |
| 6803 format %{ "movq $mem, $src\t# ptr" %} | |
| 6804 opcode(0xC7); /* C7 /0 */ | |
| 6805 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); | |
| 6806 ins_pipe(ialu_mem_imm); | |
| 6807 %} | |
| 6808 | |
|
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6809 // Store Compressed Pointer |
| 163 | 6810 instruct storeN(memory mem, rRegN src) |
|
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6811 %{ |
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6812 match(Set mem (StoreN mem src)); |
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6813 |
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6814 ins_cost(125); // XXX |
|
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6815 format %{ "movl $mem, $src\t# compressed ptr" %} |
|
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6816 ins_encode %{ |
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6817 Address addr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp); |
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6818 Register src = as_Register($src$$reg); |
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6819 __ movl(addr, src); |
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6820 %} |
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6821 ins_pipe(ialu_mem_reg); |
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6822 %} |
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6823 |
| 0 | 6824 // Store Integer Immediate |
| 6825 instruct storeImmI(memory mem, immI src) | |
| 6826 %{ | |
| 6827 match(Set mem (StoreI mem src)); | |
| 6828 | |
| 6829 ins_cost(150); | |
| 6830 format %{ "movl $mem, $src\t# int" %} | |
| 6831 opcode(0xC7); /* C7 /0 */ | |
| 6832 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); | |
| 6833 ins_pipe(ialu_mem_imm); | |
| 6834 %} | |
| 6835 | |
| 6836 // Store Long Immediate | |
| 6837 instruct storeImmL(memory mem, immL32 src) | |
| 6838 %{ | |
| 6839 match(Set mem (StoreL mem src)); | |
| 6840 | |
| 6841 ins_cost(150); | |
| 6842 format %{ "movq $mem, $src\t# long" %} | |
| 6843 opcode(0xC7); /* C7 /0 */ | |
| 6844 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); | |
| 6845 ins_pipe(ialu_mem_imm); | |
| 6846 %} | |
| 6847 | |
| 6848 // Store Short/Char Immediate | |
| 6849 instruct storeImmI16(memory mem, immI16 src) | |
| 6850 %{ | |
| 6851 predicate(UseStoreImmI16); | |
| 6852 match(Set mem (StoreC mem src)); | |
| 6853 | |
| 6854 ins_cost(150); | |
| 6855 format %{ "movw $mem, $src\t# short/char" %} | |
| 6856 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */ | |
| 6857 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src)); | |
| 6858 ins_pipe(ialu_mem_imm); | |
| 6859 %} | |
| 6860 | |
| 6861 // Store Byte Immediate | |
| 6862 instruct storeImmB(memory mem, immI8 src) | |
| 6863 %{ | |
| 6864 match(Set mem (StoreB mem src)); | |
| 6865 | |
| 6866 ins_cost(150); // XXX | |
| 6867 format %{ "movb $mem, $src\t# byte" %} | |
| 6868 opcode(0xC6); /* C6 /0 */ | |
| 6869 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src)); | |
| 6870 ins_pipe(ialu_mem_imm); | |
| 6871 %} | |
| 6872 | |
| 6873 // Store Aligned Packed Byte XMM register to memory | |
| 6874 instruct storeA8B(memory mem, regD src) %{ | |
| 6875 match(Set mem (Store8B mem src)); | |
| 6876 ins_cost(145); | |
| 6877 format %{ "MOVQ $mem,$src\t! packed8B" %} | |
| 6878 ins_encode( movq_st(mem, src)); | |
| 6879 ins_pipe( pipe_slow ); | |
| 6880 %} | |
| 6881 | |
| 6882 // Store Aligned Packed Char/Short XMM register to memory | |
| 6883 instruct storeA4C(memory mem, regD src) %{ | |
| 6884 match(Set mem (Store4C mem src)); | |
| 6885 ins_cost(145); | |
| 6886 format %{ "MOVQ $mem,$src\t! packed4C" %} | |
| 6887 ins_encode( movq_st(mem, src)); | |
| 6888 ins_pipe( pipe_slow ); | |
| 6889 %} | |
| 6890 | |
| 6891 // Store Aligned Packed Integer XMM register to memory | |
| 6892 instruct storeA2I(memory mem, regD src) %{ | |
| 6893 match(Set mem (Store2I mem src)); | |
| 6894 ins_cost(145); | |
| 6895 format %{ "MOVQ $mem,$src\t! packed2I" %} | |
| 6896 ins_encode( movq_st(mem, src)); | |
| 6897 ins_pipe( pipe_slow ); | |
| 6898 %} | |
| 6899 | |
| 6900 // Store CMS card-mark Immediate | |
| 6901 instruct storeImmCM0(memory mem, immI0 src) | |
| 6902 %{ | |
| 6903 match(Set mem (StoreCM mem src)); | |
| 6904 | |
| 6905 ins_cost(150); // XXX | |
| 6906 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %} | |
| 6907 opcode(0xC6); /* C6 /0 */ | |
| 6908 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src)); | |
| 6909 ins_pipe(ialu_mem_imm); | |
| 6910 %} | |
| 6911 | |
| 6912 // Store Aligned Packed Single Float XMM register to memory | |
| 6913 instruct storeA2F(memory mem, regD src) %{ | |
| 6914 match(Set mem (Store2F mem src)); | |
| 6915 ins_cost(145); | |
| 6916 format %{ "MOVQ $mem,$src\t! packed2F" %} | |
| 6917 ins_encode( movq_st(mem, src)); | |
| 6918 ins_pipe( pipe_slow ); | |
| 6919 %} | |
| 6920 | |
| 6921 // Store Float | |
| 6922 instruct storeF(memory mem, regF src) | |
| 6923 %{ | |
| 6924 match(Set mem (StoreF mem src)); | |
| 6925 | |
| 6926 ins_cost(95); // XXX | |
| 6927 format %{ "movss $mem, $src\t# float" %} | |
| 6928 opcode(0xF3, 0x0F, 0x11); | |
| 6929 ins_encode(OpcP, REX_reg_mem(src, mem), OpcS, OpcT, reg_mem(src, mem)); | |
| 6930 ins_pipe(pipe_slow); // XXX | |
| 6931 %} | |
| 6932 | |
| 6933 // Store immediate Float value (it is faster than store from XMM register) | |
| 6934 instruct storeF_imm(memory mem, immF src) | |
| 6935 %{ | |
| 6936 match(Set mem (StoreF mem src)); | |
| 6937 | |
| 6938 ins_cost(50); | |
| 6939 format %{ "movl $mem, $src\t# float" %} | |
| 6940 opcode(0xC7); /* C7 /0 */ | |
| 6941 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src)); | |
| 6942 ins_pipe(ialu_mem_imm); | |
| 6943 %} | |
| 6944 | |
| 6945 // Store Double | |
| 6946 instruct storeD(memory mem, regD src) | |
| 6947 %{ | |
| 6948 match(Set mem (StoreD mem src)); | |
| 6949 | |
| 6950 ins_cost(95); // XXX | |
| 6951 format %{ "movsd $mem, $src\t# double" %} | |
| 6952 opcode(0xF2, 0x0F, 0x11); | |
| 6953 ins_encode(OpcP, REX_reg_mem(src, mem), OpcS, OpcT, reg_mem(src, mem)); | |
| 6954 ins_pipe(pipe_slow); // XXX | |
| 6955 %} | |
| 6956 | |
| 6957 // Store immediate double 0.0 (it is faster than store from XMM register) | |
| 6958 instruct storeD0_imm(memory mem, immD0 src) | |
| 6959 %{ | |
| 6960 match(Set mem (StoreD mem src)); | |
| 6961 | |
| 6962 ins_cost(50); | |
| 6963 format %{ "movq $mem, $src\t# double 0." %} | |
| 6964 opcode(0xC7); /* C7 /0 */ | |
| 6965 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src)); | |
| 6966 ins_pipe(ialu_mem_imm); | |
| 6967 %} | |
| 6968 | |
| 6969 instruct storeSSI(stackSlotI dst, rRegI src) | |
| 6970 %{ | |
| 6971 match(Set dst src); | |
| 6972 | |
| 6973 ins_cost(100); | |
| 6974 format %{ "movl $dst, $src\t# int stk" %} | |
| 6975 opcode(0x89); | |
| 6976 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 6977 ins_pipe( ialu_mem_reg ); | |
| 6978 %} | |
| 6979 | |
| 6980 instruct storeSSL(stackSlotL dst, rRegL src) | |
| 6981 %{ | |
| 6982 match(Set dst src); | |
| 6983 | |
| 6984 ins_cost(100); | |
| 6985 format %{ "movq $dst, $src\t# long stk" %} | |
| 6986 opcode(0x89); | |
| 6987 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 6988 ins_pipe(ialu_mem_reg); | |
| 6989 %} | |
| 6990 | |
| 6991 instruct storeSSP(stackSlotP dst, rRegP src) | |
| 6992 %{ | |
| 6993 match(Set dst src); | |
| 6994 | |
| 6995 ins_cost(100); | |
| 6996 format %{ "movq $dst, $src\t# ptr stk" %} | |
| 6997 opcode(0x89); | |
| 6998 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 6999 ins_pipe(ialu_mem_reg); | |
| 7000 %} | |
| 7001 | |
| 7002 instruct storeSSF(stackSlotF dst, regF src) | |
| 7003 %{ | |
| 7004 match(Set dst src); | |
| 7005 | |
| 7006 ins_cost(95); // XXX | |
| 7007 format %{ "movss $dst, $src\t# float stk" %} | |
| 7008 opcode(0xF3, 0x0F, 0x11); | |
| 7009 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst)); | |
| 7010 ins_pipe(pipe_slow); // XXX | |
| 7011 %} | |
| 7012 | |
| 7013 instruct storeSSD(stackSlotD dst, regD src) | |
| 7014 %{ | |
| 7015 match(Set dst src); | |
| 7016 | |
| 7017 ins_cost(95); // XXX | |
| 7018 format %{ "movsd $dst, $src\t# double stk" %} | |
| 7019 opcode(0xF2, 0x0F, 0x11); | |
| 7020 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst)); | |
| 7021 ins_pipe(pipe_slow); // XXX | |
| 7022 %} | |
| 7023 | |
| 7024 //----------BSWAP Instructions------------------------------------------------- | |
| 7025 instruct bytes_reverse_int(rRegI dst) %{ | |
| 7026 match(Set dst (ReverseBytesI dst)); | |
| 7027 | |
| 7028 format %{ "bswapl $dst" %} | |
| 7029 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */ | |
| 7030 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) ); | |
| 7031 ins_pipe( ialu_reg ); | |
| 7032 %} | |
| 7033 | |
| 7034 instruct bytes_reverse_long(rRegL dst) %{ | |
| 7035 match(Set dst (ReverseBytesL dst)); | |
| 7036 | |
| 7037 format %{ "bswapq $dst" %} | |
| 7038 | |
| 7039 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */ | |
| 7040 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) ); | |
| 7041 ins_pipe( ialu_reg); | |
| 7042 %} | |
| 7043 | |
| 7044 instruct loadI_reversed(rRegI dst, memory src) %{ | |
| 7045 match(Set dst (ReverseBytesI (LoadI src))); | |
| 7046 | |
| 7047 format %{ "bswap_movl $dst, $src" %} | |
| 7048 opcode(0x8B, 0x0F, 0xC8); /* Opcode 8B 0F C8 */ | |
| 7049 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src), REX_reg(dst), OpcS, opc3_reg(dst)); | |
| 7050 ins_pipe( ialu_reg_mem ); | |
| 7051 %} | |
| 7052 | |
| 7053 instruct loadL_reversed(rRegL dst, memory src) %{ | |
| 7054 match(Set dst (ReverseBytesL (LoadL src))); | |
| 7055 | |
| 7056 format %{ "bswap_movq $dst, $src" %} | |
| 7057 opcode(0x8B, 0x0F, 0xC8); /* Opcode 8B 0F C8 */ | |
| 7058 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src), REX_reg_wide(dst), OpcS, opc3_reg(dst)); | |
| 7059 ins_pipe( ialu_reg_mem ); | |
| 7060 %} | |
| 7061 | |
| 7062 instruct storeI_reversed(memory dst, rRegI src) %{ | |
| 7063 match(Set dst (StoreI dst (ReverseBytesI src))); | |
| 7064 | |
| 7065 format %{ "movl_bswap $dst, $src" %} | |
| 7066 opcode(0x0F, 0xC8, 0x89); /* Opcode 0F C8 89 */ | |
| 7067 ins_encode( REX_reg(src), OpcP, opc2_reg(src), REX_reg_mem(src, dst), OpcT, reg_mem(src, dst) ); | |
| 7068 ins_pipe( ialu_mem_reg ); | |
| 7069 %} | |
| 7070 | |
| 7071 instruct storeL_reversed(memory dst, rRegL src) %{ | |
| 7072 match(Set dst (StoreL dst (ReverseBytesL src))); | |
| 7073 | |
| 7074 format %{ "movq_bswap $dst, $src" %} | |
| 7075 opcode(0x0F, 0xC8, 0x89); /* Opcode 0F C8 89 */ | |
| 7076 ins_encode( REX_reg_wide(src), OpcP, opc2_reg(src), REX_reg_mem_wide(src, dst), OpcT, reg_mem(src, dst) ); | |
| 7077 ins_pipe( ialu_mem_reg ); | |
| 7078 %} | |
| 7079 | |
| 7080 //----------MemBar Instructions----------------------------------------------- | |
| 7081 // Memory barrier flavors | |
| 7082 | |
| 7083 instruct membar_acquire() | |
| 7084 %{ | |
| 7085 match(MemBarAcquire); | |
| 7086 ins_cost(0); | |
| 7087 | |
| 7088 size(0); | |
| 7089 format %{ "MEMBAR-acquire" %} | |
| 7090 ins_encode(); | |
| 7091 ins_pipe(empty); | |
| 7092 %} | |
| 7093 | |
| 7094 instruct membar_acquire_lock() | |
| 7095 %{ | |
| 7096 match(MemBarAcquire); | |
| 7097 predicate(Matcher::prior_fast_lock(n)); | |
| 7098 ins_cost(0); | |
| 7099 | |
| 7100 size(0); | |
| 7101 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %} | |
| 7102 ins_encode(); | |
| 7103 ins_pipe(empty); | |
| 7104 %} | |
| 7105 | |
| 7106 instruct membar_release() | |
| 7107 %{ | |
| 7108 match(MemBarRelease); | |
| 7109 ins_cost(0); | |
| 7110 | |
| 7111 size(0); | |
| 7112 format %{ "MEMBAR-release" %} | |
| 7113 ins_encode(); | |
| 7114 ins_pipe(empty); | |
| 7115 %} | |
| 7116 | |
| 7117 instruct membar_release_lock() | |
| 7118 %{ | |
| 7119 match(MemBarRelease); | |
| 7120 predicate(Matcher::post_fast_unlock(n)); | |
| 7121 ins_cost(0); | |
| 7122 | |
| 7123 size(0); | |
| 7124 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %} | |
| 7125 ins_encode(); | |
| 7126 ins_pipe(empty); | |
| 7127 %} | |
| 7128 | |
| 7129 instruct membar_volatile() | |
| 7130 %{ | |
| 7131 match(MemBarVolatile); | |
| 7132 ins_cost(400); | |
| 7133 | |
| 7134 format %{ "MEMBAR-volatile" %} | |
| 7135 ins_encode(enc_membar_volatile); | |
| 7136 ins_pipe(pipe_slow); | |
| 7137 %} | |
| 7138 | |
| 7139 instruct unnecessary_membar_volatile() | |
| 7140 %{ | |
| 7141 match(MemBarVolatile); | |
| 7142 predicate(Matcher::post_store_load_barrier(n)); | |
| 7143 ins_cost(0); | |
| 7144 | |
| 7145 size(0); | |
| 7146 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %} | |
| 7147 ins_encode(); | |
| 7148 ins_pipe(empty); | |
| 7149 %} | |
| 7150 | |
| 7151 //----------Move Instructions-------------------------------------------------- | |
| 7152 | |
| 7153 instruct castX2P(rRegP dst, rRegL src) | |
| 7154 %{ | |
| 7155 match(Set dst (CastX2P src)); | |
| 7156 | |
| 7157 format %{ "movq $dst, $src\t# long->ptr" %} | |
| 7158 ins_encode(enc_copy_wide(dst, src)); | |
| 7159 ins_pipe(ialu_reg_reg); // XXX | |
| 7160 %} | |
| 7161 | |
| 7162 instruct castP2X(rRegL dst, rRegP src) | |
| 7163 %{ | |
| 7164 match(Set dst (CastP2X src)); | |
| 7165 | |
| 7166 format %{ "movq $dst, $src\t# ptr -> long" %} | |
| 7167 ins_encode(enc_copy_wide(dst, src)); | |
| 7168 ins_pipe(ialu_reg_reg); // XXX | |
| 7169 %} | |
| 7170 | |
|
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7171 |
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|
7172 // Convert oop pointer into compressed form |
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7173 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{ |
|
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7174 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); |
|
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7175 match(Set dst (EncodeP src)); |
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7176 effect(KILL cr); |
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7177 format %{ "encode_heap_oop $dst,$src" %} |
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7178 ins_encode %{ |
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7179 Register s = $src$$Register; |
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7180 Register d = $dst$$Register; |
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7181 if (s != d) { |
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7182 __ movq(d, s); |
|
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7183 } |
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7184 __ encode_heap_oop(d); |
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7185 %} |
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7186 ins_pipe(ialu_reg_long); |
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7187 %} |
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|
7188 |
|
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7189 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{ |
|
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7190 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); |
|
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7191 match(Set dst (EncodeP src)); |
|
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|
7192 effect(KILL cr); |
|
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|
7193 format %{ "encode_heap_oop_not_null $dst,$src" %} |
|
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7194 ins_encode %{ |
|
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|
7195 Register s = $src$$Register; |
|
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|
7196 Register d = $dst$$Register; |
|
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|
7197 __ encode_heap_oop_not_null(d, s); |
|
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|
7198 %} |
|
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|
7199 ins_pipe(ialu_reg_long); |
|
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|
7200 %} |
|
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|
7201 |
|
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7202 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{ |
|
182
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7203 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && |
|
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7204 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant); |
|
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7205 match(Set dst (DecodeN src)); |
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|
7206 effect(KILL cr); |
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7207 format %{ "decode_heap_oop $dst,$src" %} |
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7208 ins_encode %{ |
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7209 Register s = $src$$Register; |
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7210 Register d = $dst$$Register; |
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7211 if (s != d) { |
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|
7212 __ movq(d, s); |
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7213 } |
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7214 __ decode_heap_oop(d); |
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7215 %} |
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|
7216 ins_pipe(ialu_reg_long); |
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|
7217 %} |
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|
7218 |
|
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7219 instruct decodeHeapOop_not_null(rRegP dst, rRegN src) %{ |
|
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|
7220 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || |
|
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|
7221 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant); |
|
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|
7222 match(Set dst (DecodeN src)); |
|
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|
7223 format %{ "decode_heap_oop_not_null $dst,$src" %} |
|
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|
7224 ins_encode %{ |
|
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|
7225 Register s = $src$$Register; |
|
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|
7226 Register d = $dst$$Register; |
|
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|
7227 __ decode_heap_oop_not_null(d, s); |
|
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|
7228 %} |
|
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|
7229 ins_pipe(ialu_reg_long); |
|
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|
7230 %} |
|
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|
7231 |
|
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|
7232 |
| 0 | 7233 //----------Conditional Move--------------------------------------------------- |
| 7234 // Jump | |
| 7235 // dummy instruction for generating temp registers | |
| 7236 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{ | |
| 7237 match(Jump (LShiftL switch_val shift)); | |
| 7238 ins_cost(350); | |
| 7239 predicate(false); | |
| 7240 effect(TEMP dest); | |
| 7241 | |
| 7242 format %{ "leaq $dest, table_base\n\t" | |
| 7243 "jmp [$dest + $switch_val << $shift]\n\t" %} | |
| 7244 ins_encode(jump_enc_offset(switch_val, shift, dest)); | |
| 7245 ins_pipe(pipe_jmp); | |
| 7246 ins_pc_relative(1); | |
| 7247 %} | |
| 7248 | |
| 7249 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{ | |
| 7250 match(Jump (AddL (LShiftL switch_val shift) offset)); | |
| 7251 ins_cost(350); | |
| 7252 effect(TEMP dest); | |
| 7253 | |
| 7254 format %{ "leaq $dest, table_base\n\t" | |
| 7255 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %} | |
| 7256 ins_encode(jump_enc_addr(switch_val, shift, offset, dest)); | |
| 7257 ins_pipe(pipe_jmp); | |
| 7258 ins_pc_relative(1); | |
| 7259 %} | |
| 7260 | |
| 7261 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{ | |
| 7262 match(Jump switch_val); | |
| 7263 ins_cost(350); | |
| 7264 effect(TEMP dest); | |
| 7265 | |
| 7266 format %{ "leaq $dest, table_base\n\t" | |
| 7267 "jmp [$dest + $switch_val]\n\t" %} | |
| 7268 ins_encode(jump_enc(switch_val, dest)); | |
| 7269 ins_pipe(pipe_jmp); | |
| 7270 ins_pc_relative(1); | |
| 7271 %} | |
| 7272 | |
| 7273 // Conditional move | |
| 7274 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop) | |
| 7275 %{ | |
| 7276 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 7277 | |
| 7278 ins_cost(200); // XXX | |
| 7279 format %{ "cmovl$cop $dst, $src\t# signed, int" %} | |
| 7280 opcode(0x0F, 0x40); | |
| 7281 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 7282 ins_pipe(pipe_cmov_reg); | |
| 7283 %} | |
| 7284 | |
|
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|
7285 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{ |
| 0 | 7286 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); |
| 7287 | |
| 7288 ins_cost(200); // XXX | |
| 7289 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %} | |
| 7290 opcode(0x0F, 0x40); | |
| 7291 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 7292 ins_pipe(pipe_cmov_reg); | |
| 7293 %} | |
| 7294 | |
|
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|
7295 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{ |
|
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|
7296 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); |
|
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|
7297 ins_cost(200); |
|
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changeset
|
7298 expand %{ |
|
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|
7299 cmovI_regU(cop, cr, dst, src); |
|
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|
7300 %} |
|
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|
7301 %} |
|
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|
7302 |
| 0 | 7303 // Conditional move |
|
415
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|
7304 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{ |
| 0 | 7305 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); |
| 7306 | |
| 7307 ins_cost(250); // XXX | |
| 7308 format %{ "cmovl$cop $dst, $src\t# signed, int" %} | |
| 7309 opcode(0x0F, 0x40); | |
| 7310 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
| 7311 ins_pipe(pipe_cmov_mem); | |
| 7312 %} | |
| 7313 | |
| 7314 // Conditional move | |
| 7315 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src) | |
| 7316 %{ | |
| 7317 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); | |
| 7318 | |
| 7319 ins_cost(250); // XXX | |
| 7320 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %} | |
| 7321 opcode(0x0F, 0x40); | |
| 7322 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
| 7323 ins_pipe(pipe_cmov_mem); | |
| 7324 %} | |
| 7325 | |
|
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|
7326 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{ |
|
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|
7327 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); |
|
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|
7328 ins_cost(250); |
|
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diff
changeset
|
7329 expand %{ |
|
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changeset
|
7330 cmovI_memU(cop, cr, dst, src); |
|
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changeset
|
7331 %} |
|
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changeset
|
7332 %} |
|
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|
7333 |
| 0 | 7334 // Conditional move |
|
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7335 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop) |
|
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|
7336 %{ |
|
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|
7337 match(Set dst (CMoveN (Binary cop cr) (Binary dst src))); |
|
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|
7338 |
|
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|
7339 ins_cost(200); // XXX |
|
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7340 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %} |
|
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7341 opcode(0x0F, 0x40); |
|
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7342 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); |
|
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|
7343 ins_pipe(pipe_cmov_reg); |
|
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|
7344 %} |
|
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|
7345 |
|
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|
7346 // Conditional move |
|
415
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|
7347 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src) |
|
164
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|
7348 %{ |
|
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|
7349 match(Set dst (CMoveN (Binary cop cr) (Binary dst src))); |
|
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|
7350 |
|
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|
7351 ins_cost(200); // XXX |
|
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|
7352 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %} |
|
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|
7353 opcode(0x0F, 0x40); |
|
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|
7354 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); |
|
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|
7355 ins_pipe(pipe_cmov_reg); |
|
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|
7356 %} |
|
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|
7357 |
|
415
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diff
changeset
|
7358 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{ |
|
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changeset
|
7359 match(Set dst (CMoveN (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
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never
parents:
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diff
changeset
|
7360 ins_cost(200); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7361 expand %{ |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
7362 cmovN_regU(cop, cr, dst, src); |
|
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diff
changeset
|
7363 %} |
|
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never
parents:
403
diff
changeset
|
7364 %} |
|
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never
parents:
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diff
changeset
|
7365 |
|
164
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|
7366 // Conditional move |
| 0 | 7367 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop) |
| 7368 %{ | |
| 7369 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 7370 | |
| 7371 ins_cost(200); // XXX | |
| 7372 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %} | |
| 7373 opcode(0x0F, 0x40); | |
| 7374 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 7375 ins_pipe(pipe_cmov_reg); // XXX | |
| 7376 %} | |
| 7377 | |
| 7378 // Conditional move | |
|
415
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changeset
|
7379 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src) |
| 0 | 7380 %{ |
| 7381 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 7382 | |
| 7383 ins_cost(200); // XXX | |
| 7384 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %} | |
| 7385 opcode(0x0F, 0x40); | |
| 7386 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 7387 ins_pipe(pipe_cmov_reg); // XXX | |
| 7388 %} | |
| 7389 | |
|
415
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changeset
|
7390 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{ |
|
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parents:
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diff
changeset
|
7391 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7392 ins_cost(200); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7393 expand %{ |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
7394 cmovP_regU(cop, cr, dst, src); |
|
4d9884b01ba6
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diff
changeset
|
7395 %} |
|
4d9884b01ba6
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never
parents:
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diff
changeset
|
7396 %} |
|
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never
parents:
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diff
changeset
|
7397 |
| 0 | 7398 // DISABLED: Requires the ADLC to emit a bottom_type call that |
| 7399 // correctly meets the two pointer arguments; one is an incoming | |
| 7400 // register but the other is a memory operand. ALSO appears to | |
| 7401 // be buggy with implicit null checks. | |
| 7402 // | |
| 7403 //// Conditional move | |
| 7404 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src) | |
| 7405 //%{ | |
| 7406 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 7407 // ins_cost(250); | |
| 7408 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 7409 // opcode(0x0F,0x40); | |
| 7410 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) ); | |
| 7411 // ins_pipe( pipe_cmov_mem ); | |
| 7412 //%} | |
| 7413 // | |
| 7414 //// Conditional move | |
| 7415 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src) | |
| 7416 //%{ | |
| 7417 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 7418 // ins_cost(250); | |
| 7419 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 7420 // opcode(0x0F,0x40); | |
| 7421 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) ); | |
| 7422 // ins_pipe( pipe_cmov_mem ); | |
| 7423 //%} | |
| 7424 | |
| 7425 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src) | |
| 7426 %{ | |
| 7427 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 7428 | |
| 7429 ins_cost(200); // XXX | |
| 7430 format %{ "cmovq$cop $dst, $src\t# signed, long" %} | |
| 7431 opcode(0x0F, 0x40); | |
| 7432 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 7433 ins_pipe(pipe_cmov_reg); // XXX | |
| 7434 %} | |
| 7435 | |
| 7436 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src) | |
| 7437 %{ | |
| 7438 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src)))); | |
| 7439 | |
| 7440 ins_cost(200); // XXX | |
| 7441 format %{ "cmovq$cop $dst, $src\t# signed, long" %} | |
| 7442 opcode(0x0F, 0x40); | |
| 7443 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
| 7444 ins_pipe(pipe_cmov_mem); // XXX | |
| 7445 %} | |
| 7446 | |
| 7447 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src) | |
| 7448 %{ | |
| 7449 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 7450 | |
| 7451 ins_cost(200); // XXX | |
| 7452 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %} | |
| 7453 opcode(0x0F, 0x40); | |
| 7454 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 7455 ins_pipe(pipe_cmov_reg); // XXX | |
| 7456 %} | |
| 7457 | |
|
415
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parents:
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diff
changeset
|
7458 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{ |
|
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parents:
403
diff
changeset
|
7459 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7460 ins_cost(200); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7461 expand %{ |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
7462 cmovL_regU(cop, cr, dst, src); |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
7463 %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7464 %} |
|
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never
parents:
403
diff
changeset
|
7465 |
| 0 | 7466 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src) |
| 7467 %{ | |
| 7468 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src)))); | |
| 7469 | |
| 7470 ins_cost(200); // XXX | |
| 7471 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %} | |
| 7472 opcode(0x0F, 0x40); | |
| 7473 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
| 7474 ins_pipe(pipe_cmov_mem); // XXX | |
| 7475 %} | |
| 7476 | |
|
415
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diff
changeset
|
7477 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{ |
|
4d9884b01ba6
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parents:
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diff
changeset
|
7478 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src)))); |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
7479 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7480 expand %{ |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
7481 cmovL_memU(cop, cr, dst, src); |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
7482 %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7483 %} |
|
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parents:
403
diff
changeset
|
7484 |
| 0 | 7485 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src) |
| 7486 %{ | |
| 7487 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 7488 | |
| 7489 ins_cost(200); // XXX | |
| 7490 format %{ "jn$cop skip\t# signed cmove float\n\t" | |
| 7491 "movss $dst, $src\n" | |
| 7492 "skip:" %} | |
| 7493 ins_encode(enc_cmovf_branch(cop, dst, src)); | |
| 7494 ins_pipe(pipe_slow); | |
| 7495 %} | |
| 7496 | |
| 7497 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src) | |
| 7498 // %{ | |
| 7499 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src)))); | |
| 7500 | |
| 7501 // ins_cost(200); // XXX | |
| 7502 // format %{ "jn$cop skip\t# signed cmove float\n\t" | |
| 7503 // "movss $dst, $src\n" | |
| 7504 // "skip:" %} | |
| 7505 // ins_encode(enc_cmovf_mem_branch(cop, dst, src)); | |
| 7506 // ins_pipe(pipe_slow); | |
| 7507 // %} | |
| 7508 | |
| 7509 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src) | |
| 7510 %{ | |
| 7511 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 7512 | |
| 7513 ins_cost(200); // XXX | |
| 7514 format %{ "jn$cop skip\t# unsigned cmove float\n\t" | |
| 7515 "movss $dst, $src\n" | |
| 7516 "skip:" %} | |
| 7517 ins_encode(enc_cmovf_branch(cop, dst, src)); | |
| 7518 ins_pipe(pipe_slow); | |
| 7519 %} | |
| 7520 | |
|
415
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diff
changeset
|
7521 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{ |
|
4d9884b01ba6
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parents:
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diff
changeset
|
7522 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7523 ins_cost(200); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7524 expand %{ |
|
4d9884b01ba6
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403
diff
changeset
|
7525 cmovF_regU(cop, cr, dst, src); |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
7526 %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7527 %} |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
7528 |
| 0 | 7529 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src) |
| 7530 %{ | |
| 7531 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 7532 | |
| 7533 ins_cost(200); // XXX | |
| 7534 format %{ "jn$cop skip\t# signed cmove double\n\t" | |
| 7535 "movsd $dst, $src\n" | |
| 7536 "skip:" %} | |
| 7537 ins_encode(enc_cmovd_branch(cop, dst, src)); | |
| 7538 ins_pipe(pipe_slow); | |
| 7539 %} | |
| 7540 | |
| 7541 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src) | |
| 7542 %{ | |
| 7543 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 7544 | |
| 7545 ins_cost(200); // XXX | |
| 7546 format %{ "jn$cop skip\t# unsigned cmove double\n\t" | |
| 7547 "movsd $dst, $src\n" | |
| 7548 "skip:" %} | |
| 7549 ins_encode(enc_cmovd_branch(cop, dst, src)); | |
| 7550 ins_pipe(pipe_slow); | |
| 7551 %} | |
| 7552 | |
|
415
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diff
changeset
|
7553 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
7554 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7555 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7556 expand %{ |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7557 cmovD_regU(cop, cr, dst, src); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7558 %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7559 %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7560 |
| 0 | 7561 //----------Arithmetic Instructions-------------------------------------------- |
| 7562 //----------Addition Instructions---------------------------------------------- | |
| 7563 | |
| 7564 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 7565 %{ | |
| 7566 match(Set dst (AddI dst src)); | |
| 7567 effect(KILL cr); | |
| 7568 | |
| 7569 format %{ "addl $dst, $src\t# int" %} | |
| 7570 opcode(0x03); | |
| 7571 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 7572 ins_pipe(ialu_reg_reg); | |
| 7573 %} | |
| 7574 | |
| 7575 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 7576 %{ | |
| 7577 match(Set dst (AddI dst src)); | |
| 7578 effect(KILL cr); | |
| 7579 | |
| 7580 format %{ "addl $dst, $src\t# int" %} | |
| 7581 opcode(0x81, 0x00); /* /0 id */ | |
| 7582 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 7583 ins_pipe( ialu_reg ); | |
| 7584 %} | |
| 7585 | |
| 7586 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 7587 %{ | |
| 7588 match(Set dst (AddI dst (LoadI src))); | |
| 7589 effect(KILL cr); | |
| 7590 | |
| 7591 ins_cost(125); // XXX | |
| 7592 format %{ "addl $dst, $src\t# int" %} | |
| 7593 opcode(0x03); | |
| 7594 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 7595 ins_pipe(ialu_reg_mem); | |
| 7596 %} | |
| 7597 | |
| 7598 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 7599 %{ | |
| 7600 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7601 effect(KILL cr); | |
| 7602 | |
| 7603 ins_cost(150); // XXX | |
| 7604 format %{ "addl $dst, $src\t# int" %} | |
| 7605 opcode(0x01); /* Opcode 01 /r */ | |
| 7606 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 7607 ins_pipe(ialu_mem_reg); | |
| 7608 %} | |
| 7609 | |
| 7610 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 7611 %{ | |
| 7612 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7613 effect(KILL cr); | |
| 7614 | |
| 7615 ins_cost(125); // XXX | |
| 7616 format %{ "addl $dst, $src\t# int" %} | |
| 7617 opcode(0x81); /* Opcode 81 /0 id */ | |
| 7618 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src)); | |
| 7619 ins_pipe(ialu_mem_imm); | |
| 7620 %} | |
| 7621 | |
| 7622 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr) | |
| 7623 %{ | |
| 7624 predicate(UseIncDec); | |
| 7625 match(Set dst (AddI dst src)); | |
| 7626 effect(KILL cr); | |
| 7627 | |
| 7628 format %{ "incl $dst\t# int" %} | |
| 7629 opcode(0xFF, 0x00); // FF /0 | |
| 7630 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 7631 ins_pipe(ialu_reg); | |
| 7632 %} | |
| 7633 | |
| 7634 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr) | |
| 7635 %{ | |
| 7636 predicate(UseIncDec); | |
| 7637 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7638 effect(KILL cr); | |
| 7639 | |
| 7640 ins_cost(125); // XXX | |
| 7641 format %{ "incl $dst\t# int" %} | |
| 7642 opcode(0xFF); /* Opcode FF /0 */ | |
| 7643 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst)); | |
| 7644 ins_pipe(ialu_mem_imm); | |
| 7645 %} | |
| 7646 | |
| 7647 // XXX why does that use AddI | |
| 7648 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr) | |
| 7649 %{ | |
| 7650 predicate(UseIncDec); | |
| 7651 match(Set dst (AddI dst src)); | |
| 7652 effect(KILL cr); | |
| 7653 | |
| 7654 format %{ "decl $dst\t# int" %} | |
| 7655 opcode(0xFF, 0x01); // FF /1 | |
| 7656 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 7657 ins_pipe(ialu_reg); | |
| 7658 %} | |
| 7659 | |
| 7660 // XXX why does that use AddI | |
| 7661 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr) | |
| 7662 %{ | |
| 7663 predicate(UseIncDec); | |
| 7664 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7665 effect(KILL cr); | |
| 7666 | |
| 7667 ins_cost(125); // XXX | |
| 7668 format %{ "decl $dst\t# int" %} | |
| 7669 opcode(0xFF); /* Opcode FF /1 */ | |
| 7670 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst)); | |
| 7671 ins_pipe(ialu_mem_imm); | |
| 7672 %} | |
| 7673 | |
| 7674 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1) | |
| 7675 %{ | |
| 7676 match(Set dst (AddI src0 src1)); | |
| 7677 | |
| 7678 ins_cost(110); | |
| 7679 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %} | |
| 7680 opcode(0x8D); /* 0x8D /r */ | |
| 7681 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX | |
| 7682 ins_pipe(ialu_reg_reg); | |
| 7683 %} | |
| 7684 | |
| 7685 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 7686 %{ | |
| 7687 match(Set dst (AddL dst src)); | |
| 7688 effect(KILL cr); | |
| 7689 | |
| 7690 format %{ "addq $dst, $src\t# long" %} | |
| 7691 opcode(0x03); | |
| 7692 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 7693 ins_pipe(ialu_reg_reg); | |
| 7694 %} | |
| 7695 | |
| 7696 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
| 7697 %{ | |
| 7698 match(Set dst (AddL dst src)); | |
| 7699 effect(KILL cr); | |
| 7700 | |
| 7701 format %{ "addq $dst, $src\t# long" %} | |
| 7702 opcode(0x81, 0x00); /* /0 id */ | |
| 7703 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 7704 ins_pipe( ialu_reg ); | |
| 7705 %} | |
| 7706 | |
| 7707 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 7708 %{ | |
| 7709 match(Set dst (AddL dst (LoadL src))); | |
| 7710 effect(KILL cr); | |
| 7711 | |
| 7712 ins_cost(125); // XXX | |
| 7713 format %{ "addq $dst, $src\t# long" %} | |
| 7714 opcode(0x03); | |
| 7715 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 7716 ins_pipe(ialu_reg_mem); | |
| 7717 %} | |
| 7718 | |
| 7719 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 7720 %{ | |
| 7721 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
| 7722 effect(KILL cr); | |
| 7723 | |
| 7724 ins_cost(150); // XXX | |
| 7725 format %{ "addq $dst, $src\t# long" %} | |
| 7726 opcode(0x01); /* Opcode 01 /r */ | |
| 7727 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 7728 ins_pipe(ialu_mem_reg); | |
| 7729 %} | |
| 7730 | |
| 7731 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 7732 %{ | |
| 7733 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
| 7734 effect(KILL cr); | |
| 7735 | |
| 7736 ins_cost(125); // XXX | |
| 7737 format %{ "addq $dst, $src\t# long" %} | |
| 7738 opcode(0x81); /* Opcode 81 /0 id */ | |
| 7739 ins_encode(REX_mem_wide(dst), | |
| 7740 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src)); | |
| 7741 ins_pipe(ialu_mem_imm); | |
| 7742 %} | |
| 7743 | |
| 7744 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr) | |
| 7745 %{ | |
| 7746 predicate(UseIncDec); | |
| 7747 match(Set dst (AddL dst src)); | |
| 7748 effect(KILL cr); | |
| 7749 | |
| 7750 format %{ "incq $dst\t# long" %} | |
| 7751 opcode(0xFF, 0x00); // FF /0 | |
| 7752 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 7753 ins_pipe(ialu_reg); | |
| 7754 %} | |
| 7755 | |
| 7756 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr) | |
| 7757 %{ | |
| 7758 predicate(UseIncDec); | |
| 7759 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
| 7760 effect(KILL cr); | |
| 7761 | |
| 7762 ins_cost(125); // XXX | |
| 7763 format %{ "incq $dst\t# long" %} | |
| 7764 opcode(0xFF); /* Opcode FF /0 */ | |
| 7765 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst)); | |
| 7766 ins_pipe(ialu_mem_imm); | |
| 7767 %} | |
| 7768 | |
| 7769 // XXX why does that use AddL | |
| 7770 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr) | |
| 7771 %{ | |
| 7772 predicate(UseIncDec); | |
| 7773 match(Set dst (AddL dst src)); | |
| 7774 effect(KILL cr); | |
| 7775 | |
| 7776 format %{ "decq $dst\t# long" %} | |
| 7777 opcode(0xFF, 0x01); // FF /1 | |
| 7778 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 7779 ins_pipe(ialu_reg); | |
| 7780 %} | |
| 7781 | |
| 7782 // XXX why does that use AddL | |
| 7783 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr) | |
| 7784 %{ | |
| 7785 predicate(UseIncDec); | |
| 7786 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
| 7787 effect(KILL cr); | |
| 7788 | |
| 7789 ins_cost(125); // XXX | |
| 7790 format %{ "decq $dst\t# long" %} | |
| 7791 opcode(0xFF); /* Opcode FF /1 */ | |
| 7792 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst)); | |
| 7793 ins_pipe(ialu_mem_imm); | |
| 7794 %} | |
| 7795 | |
| 7796 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1) | |
| 7797 %{ | |
| 7798 match(Set dst (AddL src0 src1)); | |
| 7799 | |
| 7800 ins_cost(110); | |
| 7801 format %{ "leaq $dst, [$src0 + $src1]\t# long" %} | |
| 7802 opcode(0x8D); /* 0x8D /r */ | |
| 7803 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX | |
| 7804 ins_pipe(ialu_reg_reg); | |
| 7805 %} | |
| 7806 | |
| 7807 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr) | |
| 7808 %{ | |
| 7809 match(Set dst (AddP dst src)); | |
| 7810 effect(KILL cr); | |
| 7811 | |
| 7812 format %{ "addq $dst, $src\t# ptr" %} | |
| 7813 opcode(0x03); | |
| 7814 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 7815 ins_pipe(ialu_reg_reg); | |
| 7816 %} | |
| 7817 | |
| 7818 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr) | |
| 7819 %{ | |
| 7820 match(Set dst (AddP dst src)); | |
| 7821 effect(KILL cr); | |
| 7822 | |
| 7823 format %{ "addq $dst, $src\t# ptr" %} | |
| 7824 opcode(0x81, 0x00); /* /0 id */ | |
| 7825 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 7826 ins_pipe( ialu_reg ); | |
| 7827 %} | |
| 7828 | |
| 7829 // XXX addP mem ops ???? | |
| 7830 | |
| 7831 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1) | |
| 7832 %{ | |
| 7833 match(Set dst (AddP src0 src1)); | |
| 7834 | |
| 7835 ins_cost(110); | |
| 7836 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %} | |
| 7837 opcode(0x8D); /* 0x8D /r */ | |
| 7838 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX | |
| 7839 ins_pipe(ialu_reg_reg); | |
| 7840 %} | |
| 7841 | |
| 7842 instruct checkCastPP(rRegP dst) | |
| 7843 %{ | |
| 7844 match(Set dst (CheckCastPP dst)); | |
| 7845 | |
| 7846 size(0); | |
| 7847 format %{ "# checkcastPP of $dst" %} | |
| 7848 ins_encode(/* empty encoding */); | |
| 7849 ins_pipe(empty); | |
| 7850 %} | |
| 7851 | |
| 7852 instruct castPP(rRegP dst) | |
| 7853 %{ | |
| 7854 match(Set dst (CastPP dst)); | |
| 7855 | |
| 7856 size(0); | |
| 7857 format %{ "# castPP of $dst" %} | |
| 7858 ins_encode(/* empty encoding */); | |
| 7859 ins_pipe(empty); | |
| 7860 %} | |
| 7861 | |
| 7862 instruct castII(rRegI dst) | |
| 7863 %{ | |
| 7864 match(Set dst (CastII dst)); | |
| 7865 | |
| 7866 size(0); | |
| 7867 format %{ "# castII of $dst" %} | |
| 7868 ins_encode(/* empty encoding */); | |
| 7869 ins_cost(0); | |
| 7870 ins_pipe(empty); | |
| 7871 %} | |
| 7872 | |
| 7873 // LoadP-locked same as a regular LoadP when used with compare-swap | |
| 7874 instruct loadPLocked(rRegP dst, memory mem) | |
| 7875 %{ | |
| 7876 match(Set dst (LoadPLocked mem)); | |
| 7877 | |
| 7878 ins_cost(125); // XXX | |
| 7879 format %{ "movq $dst, $mem\t# ptr locked" %} | |
| 7880 opcode(0x8B); | |
| 7881 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 7882 ins_pipe(ialu_reg_mem); // XXX | |
| 7883 %} | |
| 7884 | |
| 7885 // LoadL-locked - same as a regular LoadL when used with compare-swap | |
| 7886 instruct loadLLocked(rRegL dst, memory mem) | |
| 7887 %{ | |
| 7888 match(Set dst (LoadLLocked mem)); | |
| 7889 | |
| 7890 ins_cost(125); // XXX | |
| 7891 format %{ "movq $dst, $mem\t# long locked" %} | |
| 7892 opcode(0x8B); | |
| 7893 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 7894 ins_pipe(ialu_reg_mem); // XXX | |
| 7895 %} | |
| 7896 | |
| 7897 // Conditional-store of the updated heap-top. | |
| 7898 // Used during allocation of the shared heap. | |
| 7899 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel. | |
| 7900 | |
| 7901 instruct storePConditional(memory heap_top_ptr, | |
| 7902 rax_RegP oldval, rRegP newval, | |
| 7903 rFlagsReg cr) | |
| 7904 %{ | |
| 7905 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval))); | |
|
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7906 |
| 0 | 7907 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) " |
| 7908 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %} | |
| 7909 opcode(0x0F, 0xB1); | |
| 7910 ins_encode(lock_prefix, | |
| 7911 REX_reg_mem_wide(newval, heap_top_ptr), | |
| 7912 OpcP, OpcS, | |
| 7913 reg_mem(newval, heap_top_ptr)); | |
| 7914 ins_pipe(pipe_cmpxchg); | |
| 7915 %} | |
| 7916 | |
|
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7917 // Conditional-store of an int value. |
|
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7918 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG. |
|
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7919 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr) |
|
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7920 %{ |
|
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7921 match(Set cr (StoreIConditional mem (Binary oldval newval))); |
|
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7922 effect(KILL oldval); |
|
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7923 |
|
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7924 format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %} |
| 0 | 7925 opcode(0x0F, 0xB1); |
| 7926 ins_encode(lock_prefix, | |
|
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7927 REX_reg_mem(newval, mem), |
| 0 | 7928 OpcP, OpcS, |
|
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7929 reg_mem(newval, mem)); |
| 0 | 7930 ins_pipe(pipe_cmpxchg); |
| 7931 %} | |
| 7932 | |
|
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7933 // Conditional-store of a long value. |
|
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7934 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG. |
|
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7935 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr) |
|
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7936 %{ |
|
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7937 match(Set cr (StoreLConditional mem (Binary oldval newval))); |
|
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7938 effect(KILL oldval); |
|
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7939 |
|
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7940 format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %} |
| 0 | 7941 opcode(0x0F, 0xB1); |
| 7942 ins_encode(lock_prefix, | |
|
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7943 REX_reg_mem_wide(newval, mem), |
| 0 | 7944 OpcP, OpcS, |
|
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7945 reg_mem(newval, mem)); |
| 0 | 7946 ins_pipe(pipe_cmpxchg); |
| 7947 %} | |
| 7948 | |
|
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7949 |
|
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7950 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them |
| 0 | 7951 instruct compareAndSwapP(rRegI res, |
| 7952 memory mem_ptr, | |
| 7953 rax_RegP oldval, rRegP newval, | |
| 7954 rFlagsReg cr) | |
| 7955 %{ | |
| 7956 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); | |
| 7957 effect(KILL cr, KILL oldval); | |
| 7958 | |
| 7959 format %{ "cmpxchgq $mem_ptr,$newval\t# " | |
| 7960 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" | |
| 7961 "sete $res\n\t" | |
| 7962 "movzbl $res, $res" %} | |
| 7963 opcode(0x0F, 0xB1); | |
| 7964 ins_encode(lock_prefix, | |
| 7965 REX_reg_mem_wide(newval, mem_ptr), | |
| 7966 OpcP, OpcS, | |
| 7967 reg_mem(newval, mem_ptr), | |
| 7968 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete | |
| 7969 REX_reg_breg(res, res), // movzbl | |
| 7970 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); | |
| 7971 ins_pipe( pipe_cmpxchg ); | |
| 7972 %} | |
| 7973 | |
| 7974 instruct compareAndSwapL(rRegI res, | |
| 7975 memory mem_ptr, | |
| 7976 rax_RegL oldval, rRegL newval, | |
| 7977 rFlagsReg cr) | |
| 7978 %{ | |
| 7979 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); | |
| 7980 effect(KILL cr, KILL oldval); | |
| 7981 | |
| 7982 format %{ "cmpxchgq $mem_ptr,$newval\t# " | |
| 7983 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" | |
| 7984 "sete $res\n\t" | |
| 7985 "movzbl $res, $res" %} | |
| 7986 opcode(0x0F, 0xB1); | |
| 7987 ins_encode(lock_prefix, | |
| 7988 REX_reg_mem_wide(newval, mem_ptr), | |
| 7989 OpcP, OpcS, | |
| 7990 reg_mem(newval, mem_ptr), | |
| 7991 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete | |
| 7992 REX_reg_breg(res, res), // movzbl | |
| 7993 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); | |
| 7994 ins_pipe( pipe_cmpxchg ); | |
| 7995 %} | |
| 7996 | |
| 7997 instruct compareAndSwapI(rRegI res, | |
| 7998 memory mem_ptr, | |
| 7999 rax_RegI oldval, rRegI newval, | |
| 8000 rFlagsReg cr) | |
| 8001 %{ | |
| 8002 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); | |
| 8003 effect(KILL cr, KILL oldval); | |
| 8004 | |
| 8005 format %{ "cmpxchgl $mem_ptr,$newval\t# " | |
| 8006 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" | |
| 8007 "sete $res\n\t" | |
| 8008 "movzbl $res, $res" %} | |
| 8009 opcode(0x0F, 0xB1); | |
| 8010 ins_encode(lock_prefix, | |
| 8011 REX_reg_mem(newval, mem_ptr), | |
| 8012 OpcP, OpcS, | |
| 8013 reg_mem(newval, mem_ptr), | |
| 8014 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete | |
| 8015 REX_reg_breg(res, res), // movzbl | |
| 8016 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); | |
| 8017 ins_pipe( pipe_cmpxchg ); | |
| 8018 %} | |
| 8019 | |
| 8020 | |
|
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8021 instruct compareAndSwapN(rRegI res, |
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8022 memory mem_ptr, |
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8023 rax_RegN oldval, rRegN newval, |
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8024 rFlagsReg cr) %{ |
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8025 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); |
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8026 effect(KILL cr, KILL oldval); |
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8027 |
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8028 format %{ "cmpxchgl $mem_ptr,$newval\t# " |
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8029 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" |
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8030 "sete $res\n\t" |
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8031 "movzbl $res, $res" %} |
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8032 opcode(0x0F, 0xB1); |
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8033 ins_encode(lock_prefix, |
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8034 REX_reg_mem(newval, mem_ptr), |
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8035 OpcP, OpcS, |
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8036 reg_mem(newval, mem_ptr), |
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8037 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete |
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8038 REX_reg_breg(res, res), // movzbl |
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8039 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); |
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8040 ins_pipe( pipe_cmpxchg ); |
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8041 %} |
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8042 |
| 0 | 8043 //----------Subtraction Instructions------------------------------------------- |
| 8044 | |
| 8045 // Integer Subtraction Instructions | |
| 8046 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 8047 %{ | |
| 8048 match(Set dst (SubI dst src)); | |
| 8049 effect(KILL cr); | |
| 8050 | |
| 8051 format %{ "subl $dst, $src\t# int" %} | |
| 8052 opcode(0x2B); | |
| 8053 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 8054 ins_pipe(ialu_reg_reg); | |
| 8055 %} | |
| 8056 | |
| 8057 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 8058 %{ | |
| 8059 match(Set dst (SubI dst src)); | |
| 8060 effect(KILL cr); | |
| 8061 | |
| 8062 format %{ "subl $dst, $src\t# int" %} | |
| 8063 opcode(0x81, 0x05); /* Opcode 81 /5 */ | |
| 8064 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 8065 ins_pipe(ialu_reg); | |
| 8066 %} | |
| 8067 | |
| 8068 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 8069 %{ | |
| 8070 match(Set dst (SubI dst (LoadI src))); | |
| 8071 effect(KILL cr); | |
| 8072 | |
| 8073 ins_cost(125); | |
| 8074 format %{ "subl $dst, $src\t# int" %} | |
| 8075 opcode(0x2B); | |
| 8076 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 8077 ins_pipe(ialu_reg_mem); | |
| 8078 %} | |
| 8079 | |
| 8080 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 8081 %{ | |
| 8082 match(Set dst (StoreI dst (SubI (LoadI dst) src))); | |
| 8083 effect(KILL cr); | |
| 8084 | |
| 8085 ins_cost(150); | |
| 8086 format %{ "subl $dst, $src\t# int" %} | |
| 8087 opcode(0x29); /* Opcode 29 /r */ | |
| 8088 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 8089 ins_pipe(ialu_mem_reg); | |
| 8090 %} | |
| 8091 | |
| 8092 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 8093 %{ | |
| 8094 match(Set dst (StoreI dst (SubI (LoadI dst) src))); | |
| 8095 effect(KILL cr); | |
| 8096 | |
| 8097 ins_cost(125); // XXX | |
| 8098 format %{ "subl $dst, $src\t# int" %} | |
| 8099 opcode(0x81); /* Opcode 81 /5 id */ | |
| 8100 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src)); | |
| 8101 ins_pipe(ialu_mem_imm); | |
| 8102 %} | |
| 8103 | |
| 8104 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 8105 %{ | |
| 8106 match(Set dst (SubL dst src)); | |
| 8107 effect(KILL cr); | |
| 8108 | |
| 8109 format %{ "subq $dst, $src\t# long" %} | |
| 8110 opcode(0x2B); | |
| 8111 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 8112 ins_pipe(ialu_reg_reg); | |
| 8113 %} | |
| 8114 | |
| 8115 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr) | |
| 8116 %{ | |
| 8117 match(Set dst (SubL dst src)); | |
| 8118 effect(KILL cr); | |
| 8119 | |
| 8120 format %{ "subq $dst, $src\t# long" %} | |
| 8121 opcode(0x81, 0x05); /* Opcode 81 /5 */ | |
| 8122 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 8123 ins_pipe(ialu_reg); | |
| 8124 %} | |
| 8125 | |
| 8126 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 8127 %{ | |
| 8128 match(Set dst (SubL dst (LoadL src))); | |
| 8129 effect(KILL cr); | |
| 8130 | |
| 8131 ins_cost(125); | |
| 8132 format %{ "subq $dst, $src\t# long" %} | |
| 8133 opcode(0x2B); | |
| 8134 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 8135 ins_pipe(ialu_reg_mem); | |
| 8136 %} | |
| 8137 | |
| 8138 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 8139 %{ | |
| 8140 match(Set dst (StoreL dst (SubL (LoadL dst) src))); | |
| 8141 effect(KILL cr); | |
| 8142 | |
| 8143 ins_cost(150); | |
| 8144 format %{ "subq $dst, $src\t# long" %} | |
| 8145 opcode(0x29); /* Opcode 29 /r */ | |
| 8146 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 8147 ins_pipe(ialu_mem_reg); | |
| 8148 %} | |
| 8149 | |
| 8150 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 8151 %{ | |
| 8152 match(Set dst (StoreL dst (SubL (LoadL dst) src))); | |
| 8153 effect(KILL cr); | |
| 8154 | |
| 8155 ins_cost(125); // XXX | |
| 8156 format %{ "subq $dst, $src\t# long" %} | |
| 8157 opcode(0x81); /* Opcode 81 /5 id */ | |
| 8158 ins_encode(REX_mem_wide(dst), | |
| 8159 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src)); | |
| 8160 ins_pipe(ialu_mem_imm); | |
| 8161 %} | |
| 8162 | |
| 8163 // Subtract from a pointer | |
| 8164 // XXX hmpf??? | |
| 8165 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr) | |
| 8166 %{ | |
| 8167 match(Set dst (AddP dst (SubI zero src))); | |
| 8168 effect(KILL cr); | |
| 8169 | |
| 8170 format %{ "subq $dst, $src\t# ptr - int" %} | |
| 8171 opcode(0x2B); | |
| 8172 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 8173 ins_pipe(ialu_reg_reg); | |
| 8174 %} | |
| 8175 | |
| 8176 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr) | |
| 8177 %{ | |
| 8178 match(Set dst (SubI zero dst)); | |
| 8179 effect(KILL cr); | |
| 8180 | |
| 8181 format %{ "negl $dst\t# int" %} | |
| 8182 opcode(0xF7, 0x03); // Opcode F7 /3 | |
| 8183 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8184 ins_pipe(ialu_reg); | |
| 8185 %} | |
| 8186 | |
| 8187 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr) | |
| 8188 %{ | |
| 8189 match(Set dst (StoreI dst (SubI zero (LoadI dst)))); | |
| 8190 effect(KILL cr); | |
| 8191 | |
| 8192 format %{ "negl $dst\t# int" %} | |
| 8193 opcode(0xF7, 0x03); // Opcode F7 /3 | |
| 8194 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8195 ins_pipe(ialu_reg); | |
| 8196 %} | |
| 8197 | |
| 8198 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr) | |
| 8199 %{ | |
| 8200 match(Set dst (SubL zero dst)); | |
| 8201 effect(KILL cr); | |
| 8202 | |
| 8203 format %{ "negq $dst\t# long" %} | |
| 8204 opcode(0xF7, 0x03); // Opcode F7 /3 | |
| 8205 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8206 ins_pipe(ialu_reg); | |
| 8207 %} | |
| 8208 | |
| 8209 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr) | |
| 8210 %{ | |
| 8211 match(Set dst (StoreL dst (SubL zero (LoadL dst)))); | |
| 8212 effect(KILL cr); | |
| 8213 | |
| 8214 format %{ "negq $dst\t# long" %} | |
| 8215 opcode(0xF7, 0x03); // Opcode F7 /3 | |
| 8216 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8217 ins_pipe(ialu_reg); | |
| 8218 %} | |
| 8219 | |
| 8220 | |
| 8221 //----------Multiplication/Division Instructions------------------------------- | |
| 8222 // Integer Multiplication Instructions | |
| 8223 // Multiply Register | |
| 8224 | |
| 8225 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 8226 %{ | |
| 8227 match(Set dst (MulI dst src)); | |
| 8228 effect(KILL cr); | |
| 8229 | |
| 8230 ins_cost(300); | |
| 8231 format %{ "imull $dst, $src\t# int" %} | |
| 8232 opcode(0x0F, 0xAF); | |
| 8233 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 8234 ins_pipe(ialu_reg_reg_alu0); | |
| 8235 %} | |
| 8236 | |
| 8237 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr) | |
| 8238 %{ | |
| 8239 match(Set dst (MulI src imm)); | |
| 8240 effect(KILL cr); | |
| 8241 | |
| 8242 ins_cost(300); | |
| 8243 format %{ "imull $dst, $src, $imm\t# int" %} | |
| 8244 opcode(0x69); /* 69 /r id */ | |
| 8245 ins_encode(REX_reg_reg(dst, src), | |
| 8246 OpcSE(imm), reg_reg(dst, src), Con8or32(imm)); | |
| 8247 ins_pipe(ialu_reg_reg_alu0); | |
| 8248 %} | |
| 8249 | |
| 8250 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 8251 %{ | |
| 8252 match(Set dst (MulI dst (LoadI src))); | |
| 8253 effect(KILL cr); | |
| 8254 | |
| 8255 ins_cost(350); | |
| 8256 format %{ "imull $dst, $src\t# int" %} | |
| 8257 opcode(0x0F, 0xAF); | |
| 8258 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src)); | |
| 8259 ins_pipe(ialu_reg_mem_alu0); | |
| 8260 %} | |
| 8261 | |
| 8262 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr) | |
| 8263 %{ | |
| 8264 match(Set dst (MulI (LoadI src) imm)); | |
| 8265 effect(KILL cr); | |
| 8266 | |
| 8267 ins_cost(300); | |
| 8268 format %{ "imull $dst, $src, $imm\t# int" %} | |
| 8269 opcode(0x69); /* 69 /r id */ | |
| 8270 ins_encode(REX_reg_mem(dst, src), | |
| 8271 OpcSE(imm), reg_mem(dst, src), Con8or32(imm)); | |
| 8272 ins_pipe(ialu_reg_mem_alu0); | |
| 8273 %} | |
| 8274 | |
| 8275 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 8276 %{ | |
| 8277 match(Set dst (MulL dst src)); | |
| 8278 effect(KILL cr); | |
| 8279 | |
| 8280 ins_cost(300); | |
| 8281 format %{ "imulq $dst, $src\t# long" %} | |
| 8282 opcode(0x0F, 0xAF); | |
| 8283 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 8284 ins_pipe(ialu_reg_reg_alu0); | |
| 8285 %} | |
| 8286 | |
| 8287 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr) | |
| 8288 %{ | |
| 8289 match(Set dst (MulL src imm)); | |
| 8290 effect(KILL cr); | |
| 8291 | |
| 8292 ins_cost(300); | |
| 8293 format %{ "imulq $dst, $src, $imm\t# long" %} | |
| 8294 opcode(0x69); /* 69 /r id */ | |
| 8295 ins_encode(REX_reg_reg_wide(dst, src), | |
| 8296 OpcSE(imm), reg_reg(dst, src), Con8or32(imm)); | |
| 8297 ins_pipe(ialu_reg_reg_alu0); | |
| 8298 %} | |
| 8299 | |
| 8300 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 8301 %{ | |
| 8302 match(Set dst (MulL dst (LoadL src))); | |
| 8303 effect(KILL cr); | |
| 8304 | |
| 8305 ins_cost(350); | |
| 8306 format %{ "imulq $dst, $src\t# long" %} | |
| 8307 opcode(0x0F, 0xAF); | |
| 8308 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src)); | |
| 8309 ins_pipe(ialu_reg_mem_alu0); | |
| 8310 %} | |
| 8311 | |
| 8312 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr) | |
| 8313 %{ | |
| 8314 match(Set dst (MulL (LoadL src) imm)); | |
| 8315 effect(KILL cr); | |
| 8316 | |
| 8317 ins_cost(300); | |
| 8318 format %{ "imulq $dst, $src, $imm\t# long" %} | |
| 8319 opcode(0x69); /* 69 /r id */ | |
| 8320 ins_encode(REX_reg_mem_wide(dst, src), | |
| 8321 OpcSE(imm), reg_mem(dst, src), Con8or32(imm)); | |
| 8322 ins_pipe(ialu_reg_mem_alu0); | |
| 8323 %} | |
| 8324 | |
| 145 | 8325 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr) |
| 8326 %{ | |
| 8327 match(Set dst (MulHiL src rax)); | |
| 8328 effect(USE_KILL rax, KILL cr); | |
| 8329 | |
| 8330 ins_cost(300); | |
| 8331 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %} | |
| 8332 opcode(0xF7, 0x5); /* Opcode F7 /5 */ | |
| 8333 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src)); | |
| 8334 ins_pipe(ialu_reg_reg_alu0); | |
| 8335 %} | |
| 8336 | |
| 0 | 8337 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div, |
| 8338 rFlagsReg cr) | |
| 8339 %{ | |
| 8340 match(Set rax (DivI rax div)); | |
| 8341 effect(KILL rdx, KILL cr); | |
| 8342 | |
| 8343 ins_cost(30*100+10*100); // XXX | |
| 8344 format %{ "cmpl rax, 0x80000000\t# idiv\n\t" | |
| 8345 "jne,s normal\n\t" | |
| 8346 "xorl rdx, rdx\n\t" | |
| 8347 "cmpl $div, -1\n\t" | |
| 8348 "je,s done\n" | |
| 8349 "normal: cdql\n\t" | |
| 8350 "idivl $div\n" | |
| 8351 "done:" %} | |
| 8352 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8353 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div)); | |
| 8354 ins_pipe(ialu_reg_reg_alu0); | |
| 8355 %} | |
| 8356 | |
| 8357 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div, | |
| 8358 rFlagsReg cr) | |
| 8359 %{ | |
| 8360 match(Set rax (DivL rax div)); | |
| 8361 effect(KILL rdx, KILL cr); | |
| 8362 | |
| 8363 ins_cost(30*100+10*100); // XXX | |
| 8364 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t" | |
| 8365 "cmpq rax, rdx\n\t" | |
| 8366 "jne,s normal\n\t" | |
| 8367 "xorl rdx, rdx\n\t" | |
| 8368 "cmpq $div, -1\n\t" | |
| 8369 "je,s done\n" | |
| 8370 "normal: cdqq\n\t" | |
| 8371 "idivq $div\n" | |
| 8372 "done:" %} | |
| 8373 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8374 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div)); | |
| 8375 ins_pipe(ialu_reg_reg_alu0); | |
| 8376 %} | |
| 8377 | |
| 8378 // Integer DIVMOD with Register, both quotient and mod results | |
| 8379 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div, | |
| 8380 rFlagsReg cr) | |
| 8381 %{ | |
| 8382 match(DivModI rax div); | |
| 8383 effect(KILL cr); | |
| 8384 | |
| 8385 ins_cost(30*100+10*100); // XXX | |
| 8386 format %{ "cmpl rax, 0x80000000\t# idiv\n\t" | |
| 8387 "jne,s normal\n\t" | |
| 8388 "xorl rdx, rdx\n\t" | |
| 8389 "cmpl $div, -1\n\t" | |
| 8390 "je,s done\n" | |
| 8391 "normal: cdql\n\t" | |
| 8392 "idivl $div\n" | |
| 8393 "done:" %} | |
| 8394 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8395 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div)); | |
| 8396 ins_pipe(pipe_slow); | |
| 8397 %} | |
| 8398 | |
| 8399 // Long DIVMOD with Register, both quotient and mod results | |
| 8400 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div, | |
| 8401 rFlagsReg cr) | |
| 8402 %{ | |
| 8403 match(DivModL rax div); | |
| 8404 effect(KILL cr); | |
| 8405 | |
| 8406 ins_cost(30*100+10*100); // XXX | |
| 8407 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t" | |
| 8408 "cmpq rax, rdx\n\t" | |
| 8409 "jne,s normal\n\t" | |
| 8410 "xorl rdx, rdx\n\t" | |
| 8411 "cmpq $div, -1\n\t" | |
| 8412 "je,s done\n" | |
| 8413 "normal: cdqq\n\t" | |
| 8414 "idivq $div\n" | |
| 8415 "done:" %} | |
| 8416 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8417 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div)); | |
| 8418 ins_pipe(pipe_slow); | |
| 8419 %} | |
| 8420 | |
| 8421 //----------- DivL-By-Constant-Expansions-------------------------------------- | |
| 8422 // DivI cases are handled by the compiler | |
| 8423 | |
| 605 | 8424 // Magic constant, reciprocal of 10 |
| 0 | 8425 instruct loadConL_0x6666666666666667(rRegL dst) |
| 8426 %{ | |
| 8427 effect(DEF dst); | |
| 8428 | |
| 8429 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %} | |
| 8430 ins_encode(load_immL(dst, 0x6666666666666667)); | |
| 8431 ins_pipe(ialu_reg); | |
| 8432 %} | |
| 8433 | |
| 8434 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr) | |
| 8435 %{ | |
| 8436 effect(DEF dst, USE src, USE_KILL rax, KILL cr); | |
| 8437 | |
| 8438 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %} | |
| 8439 opcode(0xF7, 0x5); /* Opcode F7 /5 */ | |
| 8440 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src)); | |
| 8441 ins_pipe(ialu_reg_reg_alu0); | |
| 8442 %} | |
| 8443 | |
| 8444 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr) | |
| 8445 %{ | |
| 8446 effect(USE_DEF dst, KILL cr); | |
| 8447 | |
| 8448 format %{ "sarq $dst, #63\t# Used in div-by-10" %} | |
| 8449 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8450 ins_encode(reg_opc_imm_wide(dst, 0x3F)); | |
| 8451 ins_pipe(ialu_reg); | |
| 8452 %} | |
| 8453 | |
| 8454 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr) | |
| 8455 %{ | |
| 8456 effect(USE_DEF dst, KILL cr); | |
| 8457 | |
| 8458 format %{ "sarq $dst, #2\t# Used in div-by-10" %} | |
| 8459 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8460 ins_encode(reg_opc_imm_wide(dst, 0x2)); | |
| 8461 ins_pipe(ialu_reg); | |
| 8462 %} | |
| 8463 | |
| 8464 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div) | |
| 8465 %{ | |
| 8466 match(Set dst (DivL src div)); | |
| 8467 | |
| 8468 ins_cost((5+8)*100); | |
| 8469 expand %{ | |
| 8470 rax_RegL rax; // Killed temp | |
| 8471 rFlagsReg cr; // Killed | |
| 8472 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667 | |
| 8473 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src | |
| 8474 sarL_rReg_63(src, cr); // sarq src, 63 | |
| 8475 sarL_rReg_2(dst, cr); // sarq rdx, 2 | |
| 8476 subL_rReg(dst, src, cr); // subl rdx, src | |
| 8477 %} | |
| 8478 %} | |
| 8479 | |
| 8480 //----------------------------------------------------------------------------- | |
| 8481 | |
| 8482 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div, | |
| 8483 rFlagsReg cr) | |
| 8484 %{ | |
| 8485 match(Set rdx (ModI rax div)); | |
| 8486 effect(KILL rax, KILL cr); | |
| 8487 | |
| 8488 ins_cost(300); // XXX | |
| 8489 format %{ "cmpl rax, 0x80000000\t# irem\n\t" | |
| 8490 "jne,s normal\n\t" | |
| 8491 "xorl rdx, rdx\n\t" | |
| 8492 "cmpl $div, -1\n\t" | |
| 8493 "je,s done\n" | |
| 8494 "normal: cdql\n\t" | |
| 8495 "idivl $div\n" | |
| 8496 "done:" %} | |
| 8497 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8498 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div)); | |
| 8499 ins_pipe(ialu_reg_reg_alu0); | |
| 8500 %} | |
| 8501 | |
| 8502 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div, | |
| 8503 rFlagsReg cr) | |
| 8504 %{ | |
| 8505 match(Set rdx (ModL rax div)); | |
| 8506 effect(KILL rax, KILL cr); | |
| 8507 | |
| 8508 ins_cost(300); // XXX | |
| 8509 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t" | |
| 8510 "cmpq rax, rdx\n\t" | |
| 8511 "jne,s normal\n\t" | |
| 8512 "xorl rdx, rdx\n\t" | |
| 8513 "cmpq $div, -1\n\t" | |
| 8514 "je,s done\n" | |
| 8515 "normal: cdqq\n\t" | |
| 8516 "idivq $div\n" | |
| 8517 "done:" %} | |
| 8518 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8519 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div)); | |
| 8520 ins_pipe(ialu_reg_reg_alu0); | |
| 8521 %} | |
| 8522 | |
| 8523 // Integer Shift Instructions | |
| 8524 // Shift Left by one | |
| 8525 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr) | |
| 8526 %{ | |
| 8527 match(Set dst (LShiftI dst shift)); | |
| 8528 effect(KILL cr); | |
| 8529 | |
| 8530 format %{ "sall $dst, $shift" %} | |
| 8531 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 8532 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8533 ins_pipe(ialu_reg); | |
| 8534 %} | |
| 8535 | |
| 8536 // Shift Left by one | |
| 8537 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 8538 %{ | |
| 8539 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift))); | |
| 8540 effect(KILL cr); | |
| 8541 | |
| 8542 format %{ "sall $dst, $shift\t" %} | |
| 8543 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 8544 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8545 ins_pipe(ialu_mem_imm); | |
| 8546 %} | |
| 8547 | |
| 8548 // Shift Left by 8-bit immediate | |
| 8549 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) | |
| 8550 %{ | |
| 8551 match(Set dst (LShiftI dst shift)); | |
| 8552 effect(KILL cr); | |
| 8553 | |
| 8554 format %{ "sall $dst, $shift" %} | |
| 8555 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 8556 ins_encode(reg_opc_imm(dst, shift)); | |
| 8557 ins_pipe(ialu_reg); | |
| 8558 %} | |
| 8559 | |
| 8560 // Shift Left by 8-bit immediate | |
| 8561 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 8562 %{ | |
| 8563 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift))); | |
| 8564 effect(KILL cr); | |
| 8565 | |
| 8566 format %{ "sall $dst, $shift" %} | |
| 8567 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 8568 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 8569 ins_pipe(ialu_mem_imm); | |
| 8570 %} | |
| 8571 | |
| 8572 // Shift Left by variable | |
| 8573 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 8574 %{ | |
| 8575 match(Set dst (LShiftI dst shift)); | |
| 8576 effect(KILL cr); | |
| 8577 | |
| 8578 format %{ "sall $dst, $shift" %} | |
| 8579 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 8580 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8581 ins_pipe(ialu_reg_reg); | |
| 8582 %} | |
| 8583 | |
| 8584 // Shift Left by variable | |
| 8585 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 8586 %{ | |
| 8587 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift))); | |
| 8588 effect(KILL cr); | |
| 8589 | |
| 8590 format %{ "sall $dst, $shift" %} | |
| 8591 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 8592 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8593 ins_pipe(ialu_mem_reg); | |
| 8594 %} | |
| 8595 | |
| 8596 // Arithmetic shift right by one | |
| 8597 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr) | |
| 8598 %{ | |
| 8599 match(Set dst (RShiftI dst shift)); | |
| 8600 effect(KILL cr); | |
| 8601 | |
| 8602 format %{ "sarl $dst, $shift" %} | |
| 8603 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 8604 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8605 ins_pipe(ialu_reg); | |
| 8606 %} | |
| 8607 | |
| 8608 // Arithmetic shift right by one | |
| 8609 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 8610 %{ | |
| 8611 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 8612 effect(KILL cr); | |
| 8613 | |
| 8614 format %{ "sarl $dst, $shift" %} | |
| 8615 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 8616 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8617 ins_pipe(ialu_mem_imm); | |
| 8618 %} | |
| 8619 | |
| 8620 // Arithmetic Shift Right by 8-bit immediate | |
| 8621 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) | |
| 8622 %{ | |
| 8623 match(Set dst (RShiftI dst shift)); | |
| 8624 effect(KILL cr); | |
| 8625 | |
| 8626 format %{ "sarl $dst, $shift" %} | |
| 8627 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8628 ins_encode(reg_opc_imm(dst, shift)); | |
| 8629 ins_pipe(ialu_mem_imm); | |
| 8630 %} | |
| 8631 | |
| 8632 // Arithmetic Shift Right by 8-bit immediate | |
| 8633 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 8634 %{ | |
| 8635 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 8636 effect(KILL cr); | |
| 8637 | |
| 8638 format %{ "sarl $dst, $shift" %} | |
| 8639 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8640 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 8641 ins_pipe(ialu_mem_imm); | |
| 8642 %} | |
| 8643 | |
| 8644 // Arithmetic Shift Right by variable | |
| 8645 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 8646 %{ | |
| 8647 match(Set dst (RShiftI dst shift)); | |
| 8648 effect(KILL cr); | |
| 8649 | |
| 8650 format %{ "sarl $dst, $shift" %} | |
| 8651 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 8652 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8653 ins_pipe(ialu_reg_reg); | |
| 8654 %} | |
| 8655 | |
| 8656 // Arithmetic Shift Right by variable | |
| 8657 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 8658 %{ | |
| 8659 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 8660 effect(KILL cr); | |
| 8661 | |
| 8662 format %{ "sarl $dst, $shift" %} | |
| 8663 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 8664 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8665 ins_pipe(ialu_mem_reg); | |
| 8666 %} | |
| 8667 | |
| 8668 // Logical shift right by one | |
| 8669 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr) | |
| 8670 %{ | |
| 8671 match(Set dst (URShiftI dst shift)); | |
| 8672 effect(KILL cr); | |
| 8673 | |
| 8674 format %{ "shrl $dst, $shift" %} | |
| 8675 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 8676 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8677 ins_pipe(ialu_reg); | |
| 8678 %} | |
| 8679 | |
| 8680 // Logical shift right by one | |
| 8681 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 8682 %{ | |
| 8683 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift))); | |
| 8684 effect(KILL cr); | |
| 8685 | |
| 8686 format %{ "shrl $dst, $shift" %} | |
| 8687 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 8688 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8689 ins_pipe(ialu_mem_imm); | |
| 8690 %} | |
| 8691 | |
| 8692 // Logical Shift Right by 8-bit immediate | |
| 8693 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) | |
| 8694 %{ | |
| 8695 match(Set dst (URShiftI dst shift)); | |
| 8696 effect(KILL cr); | |
| 8697 | |
| 8698 format %{ "shrl $dst, $shift" %} | |
| 8699 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 8700 ins_encode(reg_opc_imm(dst, shift)); | |
| 8701 ins_pipe(ialu_reg); | |
| 8702 %} | |
| 8703 | |
| 8704 // Logical Shift Right by 8-bit immediate | |
| 8705 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 8706 %{ | |
| 8707 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift))); | |
| 8708 effect(KILL cr); | |
| 8709 | |
| 8710 format %{ "shrl $dst, $shift" %} | |
| 8711 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 8712 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 8713 ins_pipe(ialu_mem_imm); | |
| 8714 %} | |
| 8715 | |
| 8716 // Logical Shift Right by variable | |
| 8717 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 8718 %{ | |
| 8719 match(Set dst (URShiftI dst shift)); | |
| 8720 effect(KILL cr); | |
| 8721 | |
| 8722 format %{ "shrl $dst, $shift" %} | |
| 8723 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 8724 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8725 ins_pipe(ialu_reg_reg); | |
| 8726 %} | |
| 8727 | |
| 8728 // Logical Shift Right by variable | |
| 8729 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 8730 %{ | |
| 8731 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift))); | |
| 8732 effect(KILL cr); | |
| 8733 | |
| 8734 format %{ "shrl $dst, $shift" %} | |
| 8735 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 8736 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8737 ins_pipe(ialu_mem_reg); | |
| 8738 %} | |
| 8739 | |
| 8740 // Long Shift Instructions | |
| 8741 // Shift Left by one | |
| 8742 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr) | |
| 8743 %{ | |
| 8744 match(Set dst (LShiftL dst shift)); | |
| 8745 effect(KILL cr); | |
| 8746 | |
| 8747 format %{ "salq $dst, $shift" %} | |
| 8748 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 8749 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8750 ins_pipe(ialu_reg); | |
| 8751 %} | |
| 8752 | |
| 8753 // Shift Left by one | |
| 8754 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 8755 %{ | |
| 8756 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift))); | |
| 8757 effect(KILL cr); | |
| 8758 | |
| 8759 format %{ "salq $dst, $shift" %} | |
| 8760 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 8761 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8762 ins_pipe(ialu_mem_imm); | |
| 8763 %} | |
| 8764 | |
| 8765 // Shift Left by 8-bit immediate | |
| 8766 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr) | |
| 8767 %{ | |
| 8768 match(Set dst (LShiftL dst shift)); | |
| 8769 effect(KILL cr); | |
| 8770 | |
| 8771 format %{ "salq $dst, $shift" %} | |
| 8772 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 8773 ins_encode(reg_opc_imm_wide(dst, shift)); | |
| 8774 ins_pipe(ialu_reg); | |
| 8775 %} | |
| 8776 | |
| 8777 // Shift Left by 8-bit immediate | |
| 8778 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 8779 %{ | |
| 8780 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift))); | |
| 8781 effect(KILL cr); | |
| 8782 | |
| 8783 format %{ "salq $dst, $shift" %} | |
| 8784 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 8785 ins_encode(REX_mem_wide(dst), OpcP, | |
| 8786 RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 8787 ins_pipe(ialu_mem_imm); | |
| 8788 %} | |
| 8789 | |
| 8790 // Shift Left by variable | |
| 8791 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 8792 %{ | |
| 8793 match(Set dst (LShiftL dst shift)); | |
| 8794 effect(KILL cr); | |
| 8795 | |
| 8796 format %{ "salq $dst, $shift" %} | |
| 8797 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 8798 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8799 ins_pipe(ialu_reg_reg); | |
| 8800 %} | |
| 8801 | |
| 8802 // Shift Left by variable | |
| 8803 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 8804 %{ | |
| 8805 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift))); | |
| 8806 effect(KILL cr); | |
| 8807 | |
| 8808 format %{ "salq $dst, $shift" %} | |
| 8809 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 8810 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8811 ins_pipe(ialu_mem_reg); | |
| 8812 %} | |
| 8813 | |
| 8814 // Arithmetic shift right by one | |
| 8815 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr) | |
| 8816 %{ | |
| 8817 match(Set dst (RShiftL dst shift)); | |
| 8818 effect(KILL cr); | |
| 8819 | |
| 8820 format %{ "sarq $dst, $shift" %} | |
| 8821 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 8822 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8823 ins_pipe(ialu_reg); | |
| 8824 %} | |
| 8825 | |
| 8826 // Arithmetic shift right by one | |
| 8827 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 8828 %{ | |
| 8829 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift))); | |
| 8830 effect(KILL cr); | |
| 8831 | |
| 8832 format %{ "sarq $dst, $shift" %} | |
| 8833 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 8834 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8835 ins_pipe(ialu_mem_imm); | |
| 8836 %} | |
| 8837 | |
| 8838 // Arithmetic Shift Right by 8-bit immediate | |
| 8839 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr) | |
| 8840 %{ | |
| 8841 match(Set dst (RShiftL dst shift)); | |
| 8842 effect(KILL cr); | |
| 8843 | |
| 8844 format %{ "sarq $dst, $shift" %} | |
| 8845 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8846 ins_encode(reg_opc_imm_wide(dst, shift)); | |
| 8847 ins_pipe(ialu_mem_imm); | |
| 8848 %} | |
| 8849 | |
| 8850 // Arithmetic Shift Right by 8-bit immediate | |
| 8851 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 8852 %{ | |
| 8853 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift))); | |
| 8854 effect(KILL cr); | |
| 8855 | |
| 8856 format %{ "sarq $dst, $shift" %} | |
| 8857 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8858 ins_encode(REX_mem_wide(dst), OpcP, | |
| 8859 RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 8860 ins_pipe(ialu_mem_imm); | |
| 8861 %} | |
| 8862 | |
| 8863 // Arithmetic Shift Right by variable | |
| 8864 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 8865 %{ | |
| 8866 match(Set dst (RShiftL dst shift)); | |
| 8867 effect(KILL cr); | |
| 8868 | |
| 8869 format %{ "sarq $dst, $shift" %} | |
| 8870 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 8871 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8872 ins_pipe(ialu_reg_reg); | |
| 8873 %} | |
| 8874 | |
| 8875 // Arithmetic Shift Right by variable | |
| 8876 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 8877 %{ | |
| 8878 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift))); | |
| 8879 effect(KILL cr); | |
| 8880 | |
| 8881 format %{ "sarq $dst, $shift" %} | |
| 8882 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 8883 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8884 ins_pipe(ialu_mem_reg); | |
| 8885 %} | |
| 8886 | |
| 8887 // Logical shift right by one | |
| 8888 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr) | |
| 8889 %{ | |
| 8890 match(Set dst (URShiftL dst shift)); | |
| 8891 effect(KILL cr); | |
| 8892 | |
| 8893 format %{ "shrq $dst, $shift" %} | |
| 8894 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 8895 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst )); | |
| 8896 ins_pipe(ialu_reg); | |
| 8897 %} | |
| 8898 | |
| 8899 // Logical shift right by one | |
| 8900 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 8901 %{ | |
| 8902 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift))); | |
| 8903 effect(KILL cr); | |
| 8904 | |
| 8905 format %{ "shrq $dst, $shift" %} | |
| 8906 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 8907 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8908 ins_pipe(ialu_mem_imm); | |
| 8909 %} | |
| 8910 | |
| 8911 // Logical Shift Right by 8-bit immediate | |
| 8912 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr) | |
| 8913 %{ | |
| 8914 match(Set dst (URShiftL dst shift)); | |
| 8915 effect(KILL cr); | |
| 8916 | |
| 8917 format %{ "shrq $dst, $shift" %} | |
| 8918 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 8919 ins_encode(reg_opc_imm_wide(dst, shift)); | |
| 8920 ins_pipe(ialu_reg); | |
| 8921 %} | |
| 8922 | |
|
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|
8923 |
| 0 | 8924 // Logical Shift Right by 8-bit immediate |
| 8925 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 8926 %{ | |
| 8927 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift))); | |
| 8928 effect(KILL cr); | |
| 8929 | |
| 8930 format %{ "shrq $dst, $shift" %} | |
| 8931 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 8932 ins_encode(REX_mem_wide(dst), OpcP, | |
| 8933 RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 8934 ins_pipe(ialu_mem_imm); | |
| 8935 %} | |
| 8936 | |
| 8937 // Logical Shift Right by variable | |
| 8938 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 8939 %{ | |
| 8940 match(Set dst (URShiftL dst shift)); | |
| 8941 effect(KILL cr); | |
| 8942 | |
| 8943 format %{ "shrq $dst, $shift" %} | |
| 8944 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 8945 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8946 ins_pipe(ialu_reg_reg); | |
| 8947 %} | |
| 8948 | |
| 8949 // Logical Shift Right by variable | |
| 8950 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 8951 %{ | |
| 8952 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift))); | |
| 8953 effect(KILL cr); | |
| 8954 | |
| 8955 format %{ "shrq $dst, $shift" %} | |
| 8956 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 8957 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8958 ins_pipe(ialu_mem_reg); | |
| 8959 %} | |
| 8960 | |
| 8961 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24. | |
| 8962 // This idiom is used by the compiler for the i2b bytecode. | |
| 8963 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour) | |
| 8964 %{ | |
| 8965 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour)); | |
| 8966 | |
| 8967 format %{ "movsbl $dst, $src\t# i2b" %} | |
| 8968 opcode(0x0F, 0xBE); | |
| 8969 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 8970 ins_pipe(ialu_reg_reg); | |
| 8971 %} | |
| 8972 | |
| 8973 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16. | |
| 8974 // This idiom is used by the compiler the i2s bytecode. | |
| 8975 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen) | |
| 8976 %{ | |
| 8977 match(Set dst (RShiftI (LShiftI src sixteen) sixteen)); | |
| 8978 | |
| 8979 format %{ "movswl $dst, $src\t# i2s" %} | |
| 8980 opcode(0x0F, 0xBF); | |
| 8981 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 8982 ins_pipe(ialu_reg_reg); | |
| 8983 %} | |
| 8984 | |
| 8985 // ROL/ROR instructions | |
| 8986 | |
| 8987 // ROL expand | |
| 8988 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{ | |
| 8989 effect(KILL cr, USE_DEF dst); | |
| 8990 | |
| 8991 format %{ "roll $dst" %} | |
| 8992 opcode(0xD1, 0x0); /* Opcode D1 /0 */ | |
| 8993 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8994 ins_pipe(ialu_reg); | |
| 8995 %} | |
| 8996 | |
| 8997 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{ | |
| 8998 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8999 | |
| 9000 format %{ "roll $dst, $shift" %} | |
| 9001 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */ | |
| 9002 ins_encode( reg_opc_imm(dst, shift) ); | |
| 9003 ins_pipe(ialu_reg); | |
| 9004 %} | |
| 9005 | |
| 9006 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 9007 %{ | |
| 9008 effect(USE_DEF dst, USE shift, KILL cr); | |
| 9009 | |
| 9010 format %{ "roll $dst, $shift" %} | |
| 9011 opcode(0xD3, 0x0); /* Opcode D3 /0 */ | |
| 9012 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 9013 ins_pipe(ialu_reg_reg); | |
| 9014 %} | |
| 9015 // end of ROL expand | |
| 9016 | |
| 9017 // Rotate Left by one | |
| 9018 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr) | |
| 9019 %{ | |
| 9020 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift))); | |
| 9021 | |
| 9022 expand %{ | |
| 9023 rolI_rReg_imm1(dst, cr); | |
| 9024 %} | |
| 9025 %} | |
| 9026 | |
| 9027 // Rotate Left by 8-bit immediate | |
| 9028 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr) | |
| 9029 %{ | |
| 9030 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); | |
| 9031 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift))); | |
| 9032 | |
| 9033 expand %{ | |
| 9034 rolI_rReg_imm8(dst, lshift, cr); | |
| 9035 %} | |
| 9036 %} | |
| 9037 | |
| 9038 // Rotate Left by variable | |
| 9039 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
| 9040 %{ | |
| 9041 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift)))); | |
| 9042 | |
| 9043 expand %{ | |
| 9044 rolI_rReg_CL(dst, shift, cr); | |
| 9045 %} | |
| 9046 %} | |
| 9047 | |
| 9048 // Rotate Left by variable | |
| 9049 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr) | |
| 9050 %{ | |
| 9051 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift)))); | |
| 9052 | |
| 9053 expand %{ | |
| 9054 rolI_rReg_CL(dst, shift, cr); | |
| 9055 %} | |
| 9056 %} | |
| 9057 | |
| 9058 // ROR expand | |
| 9059 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr) | |
| 9060 %{ | |
| 9061 effect(USE_DEF dst, KILL cr); | |
| 9062 | |
| 9063 format %{ "rorl $dst" %} | |
| 9064 opcode(0xD1, 0x1); /* D1 /1 */ | |
| 9065 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 9066 ins_pipe(ialu_reg); | |
| 9067 %} | |
| 9068 | |
| 9069 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) | |
| 9070 %{ | |
| 9071 effect(USE_DEF dst, USE shift, KILL cr); | |
| 9072 | |
| 9073 format %{ "rorl $dst, $shift" %} | |
| 9074 opcode(0xC1, 0x1); /* C1 /1 ib */ | |
| 9075 ins_encode(reg_opc_imm(dst, shift)); | |
| 9076 ins_pipe(ialu_reg); | |
| 9077 %} | |
| 9078 | |
| 9079 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 9080 %{ | |
| 9081 effect(USE_DEF dst, USE shift, KILL cr); | |
| 9082 | |
| 9083 format %{ "rorl $dst, $shift" %} | |
| 9084 opcode(0xD3, 0x1); /* D3 /1 */ | |
| 9085 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 9086 ins_pipe(ialu_reg_reg); | |
| 9087 %} | |
| 9088 // end of ROR expand | |
| 9089 | |
| 9090 // Rotate Right by one | |
| 9091 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr) | |
| 9092 %{ | |
| 9093 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift))); | |
| 9094 | |
| 9095 expand %{ | |
| 9096 rorI_rReg_imm1(dst, cr); | |
| 9097 %} | |
| 9098 %} | |
| 9099 | |
| 9100 // Rotate Right by 8-bit immediate | |
| 9101 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr) | |
| 9102 %{ | |
| 9103 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); | |
| 9104 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift))); | |
| 9105 | |
| 9106 expand %{ | |
| 9107 rorI_rReg_imm8(dst, rshift, cr); | |
| 9108 %} | |
| 9109 %} | |
| 9110 | |
| 9111 // Rotate Right by variable | |
| 9112 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
| 9113 %{ | |
| 9114 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift)))); | |
| 9115 | |
| 9116 expand %{ | |
| 9117 rorI_rReg_CL(dst, shift, cr); | |
| 9118 %} | |
| 9119 %} | |
| 9120 | |
| 9121 // Rotate Right by variable | |
| 9122 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr) | |
| 9123 %{ | |
| 9124 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift)))); | |
| 9125 | |
| 9126 expand %{ | |
| 9127 rorI_rReg_CL(dst, shift, cr); | |
| 9128 %} | |
| 9129 %} | |
| 9130 | |
| 9131 // for long rotate | |
| 9132 // ROL expand | |
| 9133 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{ | |
| 9134 effect(USE_DEF dst, KILL cr); | |
| 9135 | |
| 9136 format %{ "rolq $dst" %} | |
| 9137 opcode(0xD1, 0x0); /* Opcode D1 /0 */ | |
| 9138 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 9139 ins_pipe(ialu_reg); | |
| 9140 %} | |
| 9141 | |
| 9142 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{ | |
| 9143 effect(USE_DEF dst, USE shift, KILL cr); | |
| 9144 | |
| 9145 format %{ "rolq $dst, $shift" %} | |
| 9146 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */ | |
| 9147 ins_encode( reg_opc_imm_wide(dst, shift) ); | |
| 9148 ins_pipe(ialu_reg); | |
| 9149 %} | |
| 9150 | |
| 9151 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 9152 %{ | |
| 9153 effect(USE_DEF dst, USE shift, KILL cr); | |
| 9154 | |
| 9155 format %{ "rolq $dst, $shift" %} | |
| 9156 opcode(0xD3, 0x0); /* Opcode D3 /0 */ | |
| 9157 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 9158 ins_pipe(ialu_reg_reg); | |
| 9159 %} | |
| 9160 // end of ROL expand | |
| 9161 | |
| 9162 // Rotate Left by one | |
| 9163 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr) | |
| 9164 %{ | |
| 9165 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift))); | |
| 9166 | |
| 9167 expand %{ | |
| 9168 rolL_rReg_imm1(dst, cr); | |
| 9169 %} | |
| 9170 %} | |
| 9171 | |
| 9172 // Rotate Left by 8-bit immediate | |
| 9173 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr) | |
| 9174 %{ | |
| 9175 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f)); | |
| 9176 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift))); | |
| 9177 | |
| 9178 expand %{ | |
| 9179 rolL_rReg_imm8(dst, lshift, cr); | |
| 9180 %} | |
| 9181 %} | |
| 9182 | |
| 9183 // Rotate Left by variable | |
| 9184 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
| 9185 %{ | |
| 9186 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift)))); | |
| 9187 | |
| 9188 expand %{ | |
| 9189 rolL_rReg_CL(dst, shift, cr); | |
| 9190 %} | |
| 9191 %} | |
| 9192 | |
| 9193 // Rotate Left by variable | |
| 9194 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr) | |
| 9195 %{ | |
| 9196 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift)))); | |
| 9197 | |
| 9198 expand %{ | |
| 9199 rolL_rReg_CL(dst, shift, cr); | |
| 9200 %} | |
| 9201 %} | |
| 9202 | |
| 9203 // ROR expand | |
| 9204 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr) | |
| 9205 %{ | |
| 9206 effect(USE_DEF dst, KILL cr); | |
| 9207 | |
| 9208 format %{ "rorq $dst" %} | |
| 9209 opcode(0xD1, 0x1); /* D1 /1 */ | |
| 9210 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 9211 ins_pipe(ialu_reg); | |
| 9212 %} | |
| 9213 | |
| 9214 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) | |
| 9215 %{ | |
| 9216 effect(USE_DEF dst, USE shift, KILL cr); | |
| 9217 | |
| 9218 format %{ "rorq $dst, $shift" %} | |
| 9219 opcode(0xC1, 0x1); /* C1 /1 ib */ | |
| 9220 ins_encode(reg_opc_imm_wide(dst, shift)); | |
| 9221 ins_pipe(ialu_reg); | |
| 9222 %} | |
| 9223 | |
| 9224 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 9225 %{ | |
| 9226 effect(USE_DEF dst, USE shift, KILL cr); | |
| 9227 | |
| 9228 format %{ "rorq $dst, $shift" %} | |
| 9229 opcode(0xD3, 0x1); /* D3 /1 */ | |
| 9230 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 9231 ins_pipe(ialu_reg_reg); | |
| 9232 %} | |
| 9233 // end of ROR expand | |
| 9234 | |
| 9235 // Rotate Right by one | |
| 9236 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr) | |
| 9237 %{ | |
| 9238 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift))); | |
| 9239 | |
| 9240 expand %{ | |
| 9241 rorL_rReg_imm1(dst, cr); | |
| 9242 %} | |
| 9243 %} | |
| 9244 | |
| 9245 // Rotate Right by 8-bit immediate | |
| 9246 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr) | |
| 9247 %{ | |
| 9248 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f)); | |
| 9249 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift))); | |
| 9250 | |
| 9251 expand %{ | |
| 9252 rorL_rReg_imm8(dst, rshift, cr); | |
| 9253 %} | |
| 9254 %} | |
| 9255 | |
| 9256 // Rotate Right by variable | |
| 9257 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
| 9258 %{ | |
| 9259 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift)))); | |
| 9260 | |
| 9261 expand %{ | |
| 9262 rorL_rReg_CL(dst, shift, cr); | |
| 9263 %} | |
| 9264 %} | |
| 9265 | |
| 9266 // Rotate Right by variable | |
| 9267 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr) | |
| 9268 %{ | |
| 9269 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift)))); | |
| 9270 | |
| 9271 expand %{ | |
| 9272 rorL_rReg_CL(dst, shift, cr); | |
| 9273 %} | |
| 9274 %} | |
| 9275 | |
| 9276 // Logical Instructions | |
| 9277 | |
| 9278 // Integer Logical Instructions | |
| 9279 | |
| 9280 // And Instructions | |
| 9281 // And Register with Register | |
| 9282 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 9283 %{ | |
| 9284 match(Set dst (AndI dst src)); | |
| 9285 effect(KILL cr); | |
| 9286 | |
| 9287 format %{ "andl $dst, $src\t# int" %} | |
| 9288 opcode(0x23); | |
| 9289 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 9290 ins_pipe(ialu_reg_reg); | |
| 9291 %} | |
| 9292 | |
| 9293 // And Register with Immediate 255 | |
| 9294 instruct andI_rReg_imm255(rRegI dst, immI_255 src) | |
| 9295 %{ | |
| 9296 match(Set dst (AndI dst src)); | |
| 9297 | |
| 9298 format %{ "movzbl $dst, $dst\t# int & 0xFF" %} | |
| 9299 opcode(0x0F, 0xB6); | |
| 9300 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 9301 ins_pipe(ialu_reg); | |
| 9302 %} | |
| 9303 | |
| 9304 // And Register with Immediate 255 and promote to long | |
| 9305 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask) | |
| 9306 %{ | |
| 9307 match(Set dst (ConvI2L (AndI src mask))); | |
| 9308 | |
| 9309 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %} | |
| 9310 opcode(0x0F, 0xB6); | |
| 9311 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 9312 ins_pipe(ialu_reg); | |
| 9313 %} | |
| 9314 | |
| 9315 // And Register with Immediate 65535 | |
| 9316 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src) | |
| 9317 %{ | |
| 9318 match(Set dst (AndI dst src)); | |
| 9319 | |
| 9320 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %} | |
| 9321 opcode(0x0F, 0xB7); | |
| 9322 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 9323 ins_pipe(ialu_reg); | |
| 9324 %} | |
| 9325 | |
| 9326 // And Register with Immediate 65535 and promote to long | |
| 9327 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask) | |
| 9328 %{ | |
| 9329 match(Set dst (ConvI2L (AndI src mask))); | |
| 9330 | |
| 9331 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %} | |
| 9332 opcode(0x0F, 0xB7); | |
| 9333 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 9334 ins_pipe(ialu_reg); | |
| 9335 %} | |
| 9336 | |
| 9337 // And Register with Immediate | |
| 9338 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 9339 %{ | |
| 9340 match(Set dst (AndI dst src)); | |
| 9341 effect(KILL cr); | |
| 9342 | |
| 9343 format %{ "andl $dst, $src\t# int" %} | |
| 9344 opcode(0x81, 0x04); /* Opcode 81 /4 */ | |
| 9345 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 9346 ins_pipe(ialu_reg); | |
| 9347 %} | |
| 9348 | |
| 9349 // And Register with Memory | |
| 9350 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 9351 %{ | |
| 9352 match(Set dst (AndI dst (LoadI src))); | |
| 9353 effect(KILL cr); | |
| 9354 | |
| 9355 ins_cost(125); | |
| 9356 format %{ "andl $dst, $src\t# int" %} | |
| 9357 opcode(0x23); | |
| 9358 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 9359 ins_pipe(ialu_reg_mem); | |
| 9360 %} | |
| 9361 | |
| 9362 // And Memory with Register | |
| 9363 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 9364 %{ | |
| 9365 match(Set dst (StoreI dst (AndI (LoadI dst) src))); | |
| 9366 effect(KILL cr); | |
| 9367 | |
| 9368 ins_cost(150); | |
| 9369 format %{ "andl $dst, $src\t# int" %} | |
| 9370 opcode(0x21); /* Opcode 21 /r */ | |
| 9371 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 9372 ins_pipe(ialu_mem_reg); | |
| 9373 %} | |
| 9374 | |
| 9375 // And Memory with Immediate | |
| 9376 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 9377 %{ | |
| 9378 match(Set dst (StoreI dst (AndI (LoadI dst) src))); | |
| 9379 effect(KILL cr); | |
| 9380 | |
| 9381 ins_cost(125); | |
| 9382 format %{ "andl $dst, $src\t# int" %} | |
| 9383 opcode(0x81, 0x4); /* Opcode 81 /4 id */ | |
| 9384 ins_encode(REX_mem(dst), OpcSE(src), | |
| 9385 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 9386 ins_pipe(ialu_mem_imm); | |
| 9387 %} | |
| 9388 | |
| 9389 // Or Instructions | |
| 9390 // Or Register with Register | |
| 9391 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 9392 %{ | |
| 9393 match(Set dst (OrI dst src)); | |
| 9394 effect(KILL cr); | |
| 9395 | |
| 9396 format %{ "orl $dst, $src\t# int" %} | |
| 9397 opcode(0x0B); | |
| 9398 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 9399 ins_pipe(ialu_reg_reg); | |
| 9400 %} | |
| 9401 | |
| 9402 // Or Register with Immediate | |
| 9403 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 9404 %{ | |
| 9405 match(Set dst (OrI dst src)); | |
| 9406 effect(KILL cr); | |
| 9407 | |
| 9408 format %{ "orl $dst, $src\t# int" %} | |
| 9409 opcode(0x81, 0x01); /* Opcode 81 /1 id */ | |
| 9410 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 9411 ins_pipe(ialu_reg); | |
| 9412 %} | |
| 9413 | |
| 9414 // Or Register with Memory | |
| 9415 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 9416 %{ | |
| 9417 match(Set dst (OrI dst (LoadI src))); | |
| 9418 effect(KILL cr); | |
| 9419 | |
| 9420 ins_cost(125); | |
| 9421 format %{ "orl $dst, $src\t# int" %} | |
| 9422 opcode(0x0B); | |
| 9423 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 9424 ins_pipe(ialu_reg_mem); | |
| 9425 %} | |
| 9426 | |
| 9427 // Or Memory with Register | |
| 9428 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 9429 %{ | |
| 9430 match(Set dst (StoreI dst (OrI (LoadI dst) src))); | |
| 9431 effect(KILL cr); | |
| 9432 | |
| 9433 ins_cost(150); | |
| 9434 format %{ "orl $dst, $src\t# int" %} | |
| 9435 opcode(0x09); /* Opcode 09 /r */ | |
| 9436 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 9437 ins_pipe(ialu_mem_reg); | |
| 9438 %} | |
| 9439 | |
| 9440 // Or Memory with Immediate | |
| 9441 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 9442 %{ | |
| 9443 match(Set dst (StoreI dst (OrI (LoadI dst) src))); | |
| 9444 effect(KILL cr); | |
| 9445 | |
| 9446 ins_cost(125); | |
| 9447 format %{ "orl $dst, $src\t# int" %} | |
| 9448 opcode(0x81, 0x1); /* Opcode 81 /1 id */ | |
| 9449 ins_encode(REX_mem(dst), OpcSE(src), | |
| 9450 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 9451 ins_pipe(ialu_mem_imm); | |
| 9452 %} | |
| 9453 | |
| 9454 // Xor Instructions | |
| 9455 // Xor Register with Register | |
| 9456 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 9457 %{ | |
| 9458 match(Set dst (XorI dst src)); | |
| 9459 effect(KILL cr); | |
| 9460 | |
| 9461 format %{ "xorl $dst, $src\t# int" %} | |
| 9462 opcode(0x33); | |
| 9463 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 9464 ins_pipe(ialu_reg_reg); | |
| 9465 %} | |
| 9466 | |
| 403 | 9467 // Xor Register with Immediate -1 |
| 9468 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{ | |
| 9469 match(Set dst (XorI dst imm)); | |
| 9470 | |
| 9471 format %{ "not $dst" %} | |
| 9472 ins_encode %{ | |
| 9473 __ notl($dst$$Register); | |
| 9474 %} | |
| 9475 ins_pipe(ialu_reg); | |
| 9476 %} | |
| 9477 | |
| 0 | 9478 // Xor Register with Immediate |
| 9479 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 9480 %{ | |
| 9481 match(Set dst (XorI dst src)); | |
| 9482 effect(KILL cr); | |
| 9483 | |
| 9484 format %{ "xorl $dst, $src\t# int" %} | |
| 9485 opcode(0x81, 0x06); /* Opcode 81 /6 id */ | |
| 9486 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 9487 ins_pipe(ialu_reg); | |
| 9488 %} | |
| 9489 | |
| 9490 // Xor Register with Memory | |
| 9491 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 9492 %{ | |
| 9493 match(Set dst (XorI dst (LoadI src))); | |
| 9494 effect(KILL cr); | |
| 9495 | |
| 9496 ins_cost(125); | |
| 9497 format %{ "xorl $dst, $src\t# int" %} | |
| 9498 opcode(0x33); | |
| 9499 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 9500 ins_pipe(ialu_reg_mem); | |
| 9501 %} | |
| 9502 | |
| 9503 // Xor Memory with Register | |
| 9504 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 9505 %{ | |
| 9506 match(Set dst (StoreI dst (XorI (LoadI dst) src))); | |
| 9507 effect(KILL cr); | |
| 9508 | |
| 9509 ins_cost(150); | |
| 9510 format %{ "xorl $dst, $src\t# int" %} | |
| 9511 opcode(0x31); /* Opcode 31 /r */ | |
| 9512 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 9513 ins_pipe(ialu_mem_reg); | |
| 9514 %} | |
| 9515 | |
| 9516 // Xor Memory with Immediate | |
| 9517 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 9518 %{ | |
| 9519 match(Set dst (StoreI dst (XorI (LoadI dst) src))); | |
| 9520 effect(KILL cr); | |
| 9521 | |
| 9522 ins_cost(125); | |
| 9523 format %{ "xorl $dst, $src\t# int" %} | |
| 9524 opcode(0x81, 0x6); /* Opcode 81 /6 id */ | |
| 9525 ins_encode(REX_mem(dst), OpcSE(src), | |
| 9526 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 9527 ins_pipe(ialu_mem_imm); | |
| 9528 %} | |
| 9529 | |
| 9530 | |
| 9531 // Long Logical Instructions | |
| 9532 | |
| 9533 // And Instructions | |
| 9534 // And Register with Register | |
| 9535 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 9536 %{ | |
| 9537 match(Set dst (AndL dst src)); | |
| 9538 effect(KILL cr); | |
| 9539 | |
| 9540 format %{ "andq $dst, $src\t# long" %} | |
| 9541 opcode(0x23); | |
| 9542 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 9543 ins_pipe(ialu_reg_reg); | |
| 9544 %} | |
| 9545 | |
| 9546 // And Register with Immediate 255 | |
| 9547 instruct andL_rReg_imm255(rRegL dst, immL_255 src) | |
| 9548 %{ | |
| 9549 match(Set dst (AndL dst src)); | |
| 9550 | |
|
569
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9551 format %{ "movzbq $dst, $dst\t# long & 0xFF" %} |
| 0 | 9552 opcode(0x0F, 0xB6); |
| 9553 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 9554 ins_pipe(ialu_reg); | |
| 9555 %} | |
| 9556 | |
| 9557 // And Register with Immediate 65535 | |
|
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9558 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src) |
| 0 | 9559 %{ |
| 9560 match(Set dst (AndL dst src)); | |
| 9561 | |
| 9562 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %} | |
| 9563 opcode(0x0F, 0xB7); | |
| 9564 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 9565 ins_pipe(ialu_reg); | |
| 9566 %} | |
| 9567 | |
| 9568 // And Register with Immediate | |
| 9569 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
| 9570 %{ | |
| 9571 match(Set dst (AndL dst src)); | |
| 9572 effect(KILL cr); | |
| 9573 | |
| 9574 format %{ "andq $dst, $src\t# long" %} | |
| 9575 opcode(0x81, 0x04); /* Opcode 81 /4 */ | |
| 9576 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 9577 ins_pipe(ialu_reg); | |
| 9578 %} | |
| 9579 | |
| 9580 // And Register with Memory | |
| 9581 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 9582 %{ | |
| 9583 match(Set dst (AndL dst (LoadL src))); | |
| 9584 effect(KILL cr); | |
| 9585 | |
| 9586 ins_cost(125); | |
| 9587 format %{ "andq $dst, $src\t# long" %} | |
| 9588 opcode(0x23); | |
| 9589 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 9590 ins_pipe(ialu_reg_mem); | |
| 9591 %} | |
| 9592 | |
| 9593 // And Memory with Register | |
| 9594 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 9595 %{ | |
| 9596 match(Set dst (StoreL dst (AndL (LoadL dst) src))); | |
| 9597 effect(KILL cr); | |
| 9598 | |
| 9599 ins_cost(150); | |
| 9600 format %{ "andq $dst, $src\t# long" %} | |
| 9601 opcode(0x21); /* Opcode 21 /r */ | |
| 9602 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 9603 ins_pipe(ialu_mem_reg); | |
| 9604 %} | |
| 9605 | |
| 9606 // And Memory with Immediate | |
| 9607 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 9608 %{ | |
| 9609 match(Set dst (StoreL dst (AndL (LoadL dst) src))); | |
| 9610 effect(KILL cr); | |
| 9611 | |
| 9612 ins_cost(125); | |
| 9613 format %{ "andq $dst, $src\t# long" %} | |
| 9614 opcode(0x81, 0x4); /* Opcode 81 /4 id */ | |
| 9615 ins_encode(REX_mem_wide(dst), OpcSE(src), | |
| 9616 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 9617 ins_pipe(ialu_mem_imm); | |
| 9618 %} | |
| 9619 | |
| 9620 // Or Instructions | |
| 9621 // Or Register with Register | |
| 9622 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 9623 %{ | |
| 9624 match(Set dst (OrL dst src)); | |
| 9625 effect(KILL cr); | |
| 9626 | |
| 9627 format %{ "orq $dst, $src\t# long" %} | |
| 9628 opcode(0x0B); | |
| 9629 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 9630 ins_pipe(ialu_reg_reg); | |
| 9631 %} | |
| 9632 | |
|
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9633 // Use any_RegP to match R15 (TLS register) without spilling. |
|
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9634 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{ |
|
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9635 match(Set dst (OrL dst (CastP2X src))); |
|
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9636 effect(KILL cr); |
|
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9637 |
|
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9638 format %{ "orq $dst, $src\t# long" %} |
|
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9639 opcode(0x0B); |
|
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9640 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); |
|
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9641 ins_pipe(ialu_reg_reg); |
|
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9642 %} |
|
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9643 |
|
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9644 |
| 0 | 9645 // Or Register with Immediate |
| 9646 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
| 9647 %{ | |
| 9648 match(Set dst (OrL dst src)); | |
| 9649 effect(KILL cr); | |
| 9650 | |
| 9651 format %{ "orq $dst, $src\t# long" %} | |
| 9652 opcode(0x81, 0x01); /* Opcode 81 /1 id */ | |
| 9653 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 9654 ins_pipe(ialu_reg); | |
| 9655 %} | |
| 9656 | |
| 9657 // Or Register with Memory | |
| 9658 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 9659 %{ | |
| 9660 match(Set dst (OrL dst (LoadL src))); | |
| 9661 effect(KILL cr); | |
| 9662 | |
| 9663 ins_cost(125); | |
| 9664 format %{ "orq $dst, $src\t# long" %} | |
| 9665 opcode(0x0B); | |
| 9666 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 9667 ins_pipe(ialu_reg_mem); | |
| 9668 %} | |
| 9669 | |
| 9670 // Or Memory with Register | |
| 9671 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 9672 %{ | |
| 9673 match(Set dst (StoreL dst (OrL (LoadL dst) src))); | |
| 9674 effect(KILL cr); | |
| 9675 | |
| 9676 ins_cost(150); | |
| 9677 format %{ "orq $dst, $src\t# long" %} | |
| 9678 opcode(0x09); /* Opcode 09 /r */ | |
| 9679 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 9680 ins_pipe(ialu_mem_reg); | |
| 9681 %} | |
| 9682 | |
| 9683 // Or Memory with Immediate | |
| 9684 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 9685 %{ | |
| 9686 match(Set dst (StoreL dst (OrL (LoadL dst) src))); | |
| 9687 effect(KILL cr); | |
| 9688 | |
| 9689 ins_cost(125); | |
| 9690 format %{ "orq $dst, $src\t# long" %} | |
| 9691 opcode(0x81, 0x1); /* Opcode 81 /1 id */ | |
| 9692 ins_encode(REX_mem_wide(dst), OpcSE(src), | |
| 9693 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 9694 ins_pipe(ialu_mem_imm); | |
| 9695 %} | |
| 9696 | |
| 9697 // Xor Instructions | |
| 9698 // Xor Register with Register | |
| 9699 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 9700 %{ | |
| 9701 match(Set dst (XorL dst src)); | |
| 9702 effect(KILL cr); | |
| 9703 | |
| 9704 format %{ "xorq $dst, $src\t# long" %} | |
| 9705 opcode(0x33); | |
| 9706 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 9707 ins_pipe(ialu_reg_reg); | |
| 9708 %} | |
| 9709 | |
| 403 | 9710 // Xor Register with Immediate -1 |
| 9711 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{ | |
| 9712 match(Set dst (XorL dst imm)); | |
| 9713 | |
| 9714 format %{ "notq $dst" %} | |
| 9715 ins_encode %{ | |
| 9716 __ notq($dst$$Register); | |
| 9717 %} | |
| 9718 ins_pipe(ialu_reg); | |
| 9719 %} | |
| 9720 | |
| 0 | 9721 // Xor Register with Immediate |
| 9722 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
| 9723 %{ | |
| 9724 match(Set dst (XorL dst src)); | |
| 9725 effect(KILL cr); | |
| 9726 | |
| 9727 format %{ "xorq $dst, $src\t# long" %} | |
| 9728 opcode(0x81, 0x06); /* Opcode 81 /6 id */ | |
| 9729 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 9730 ins_pipe(ialu_reg); | |
| 9731 %} | |
| 9732 | |
| 9733 // Xor Register with Memory | |
| 9734 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 9735 %{ | |
| 9736 match(Set dst (XorL dst (LoadL src))); | |
| 9737 effect(KILL cr); | |
| 9738 | |
| 9739 ins_cost(125); | |
| 9740 format %{ "xorq $dst, $src\t# long" %} | |
| 9741 opcode(0x33); | |
| 9742 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 9743 ins_pipe(ialu_reg_mem); | |
| 9744 %} | |
| 9745 | |
| 9746 // Xor Memory with Register | |
| 9747 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 9748 %{ | |
| 9749 match(Set dst (StoreL dst (XorL (LoadL dst) src))); | |
| 9750 effect(KILL cr); | |
| 9751 | |
| 9752 ins_cost(150); | |
| 9753 format %{ "xorq $dst, $src\t# long" %} | |
| 9754 opcode(0x31); /* Opcode 31 /r */ | |
| 9755 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 9756 ins_pipe(ialu_mem_reg); | |
| 9757 %} | |
| 9758 | |
| 9759 // Xor Memory with Immediate | |
| 9760 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 9761 %{ | |
| 9762 match(Set dst (StoreL dst (XorL (LoadL dst) src))); | |
| 9763 effect(KILL cr); | |
| 9764 | |
| 9765 ins_cost(125); | |
| 9766 format %{ "xorq $dst, $src\t# long" %} | |
| 9767 opcode(0x81, 0x6); /* Opcode 81 /6 id */ | |
| 9768 ins_encode(REX_mem_wide(dst), OpcSE(src), | |
| 9769 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 9770 ins_pipe(ialu_mem_imm); | |
| 9771 %} | |
| 9772 | |
| 9773 // Convert Int to Boolean | |
| 9774 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr) | |
| 9775 %{ | |
| 9776 match(Set dst (Conv2B src)); | |
| 9777 effect(KILL cr); | |
| 9778 | |
| 9779 format %{ "testl $src, $src\t# ci2b\n\t" | |
| 9780 "setnz $dst\n\t" | |
| 9781 "movzbl $dst, $dst" %} | |
| 9782 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl | |
| 9783 setNZ_reg(dst), | |
| 9784 REX_reg_breg(dst, dst), // movzbl | |
| 9785 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst)); | |
| 9786 ins_pipe(pipe_slow); // XXX | |
| 9787 %} | |
| 9788 | |
| 9789 // Convert Pointer to Boolean | |
| 9790 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr) | |
| 9791 %{ | |
| 9792 match(Set dst (Conv2B src)); | |
| 9793 effect(KILL cr); | |
| 9794 | |
| 9795 format %{ "testq $src, $src\t# cp2b\n\t" | |
| 9796 "setnz $dst\n\t" | |
| 9797 "movzbl $dst, $dst" %} | |
| 9798 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq | |
| 9799 setNZ_reg(dst), | |
| 9800 REX_reg_breg(dst, dst), // movzbl | |
| 9801 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst)); | |
| 9802 ins_pipe(pipe_slow); // XXX | |
| 9803 %} | |
| 9804 | |
| 9805 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr) | |
| 9806 %{ | |
| 9807 match(Set dst (CmpLTMask p q)); | |
| 9808 effect(KILL cr); | |
| 9809 | |
| 9810 ins_cost(400); // XXX | |
| 9811 format %{ "cmpl $p, $q\t# cmpLTMask\n\t" | |
| 9812 "setlt $dst\n\t" | |
| 9813 "movzbl $dst, $dst\n\t" | |
| 9814 "negl $dst" %} | |
| 9815 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl | |
| 9816 setLT_reg(dst), | |
| 9817 REX_reg_breg(dst, dst), // movzbl | |
| 9818 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst), | |
| 9819 neg_reg(dst)); | |
| 9820 ins_pipe(pipe_slow); | |
| 9821 %} | |
| 9822 | |
| 9823 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr) | |
| 9824 %{ | |
| 9825 match(Set dst (CmpLTMask dst zero)); | |
| 9826 effect(KILL cr); | |
| 9827 | |
| 9828 ins_cost(100); // XXX | |
| 9829 format %{ "sarl $dst, #31\t# cmpLTMask0" %} | |
| 9830 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 9831 ins_encode(reg_opc_imm(dst, 0x1F)); | |
| 9832 ins_pipe(ialu_reg); | |
| 9833 %} | |
| 9834 | |
| 9835 | |
| 9836 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, | |
| 9837 rRegI tmp, | |
| 9838 rFlagsReg cr) | |
| 9839 %{ | |
| 9840 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); | |
| 9841 effect(TEMP tmp, KILL cr); | |
| 9842 | |
| 9843 ins_cost(400); // XXX | |
| 9844 format %{ "subl $p, $q\t# cadd_cmpLTMask1\n\t" | |
| 9845 "sbbl $tmp, $tmp\n\t" | |
| 9846 "andl $tmp, $y\n\t" | |
| 9847 "addl $p, $tmp" %} | |
| 9848 ins_encode(enc_cmpLTP(p, q, y, tmp)); | |
| 9849 ins_pipe(pipe_cmplt); | |
| 9850 %} | |
| 9851 | |
| 9852 /* If I enable this, I encourage spilling in the inner loop of compress. | |
| 9853 instruct cadd_cmpLTMask_mem( rRegI p, rRegI q, memory y, rRegI tmp, rFlagsReg cr ) | |
| 9854 %{ | |
| 9855 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q))); | |
| 9856 effect( TEMP tmp, KILL cr ); | |
| 9857 ins_cost(400); | |
| 9858 | |
| 9859 format %{ "SUB $p,$q\n\t" | |
| 9860 "SBB RCX,RCX\n\t" | |
| 9861 "AND RCX,$y\n\t" | |
| 9862 "ADD $p,RCX" %} | |
| 9863 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) ); | |
| 9864 %} | |
| 9865 */ | |
| 9866 | |
| 9867 //---------- FP Instructions------------------------------------------------ | |
| 9868 | |
| 9869 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2) | |
| 9870 %{ | |
| 9871 match(Set cr (CmpF src1 src2)); | |
| 9872 | |
| 9873 ins_cost(145); | |
| 9874 format %{ "ucomiss $src1, $src2\n\t" | |
| 9875 "jnp,s exit\n\t" | |
| 9876 "pushfq\t# saw NaN, set CF\n\t" | |
| 9877 "andq [rsp], #0xffffff2b\n\t" | |
| 9878 "popfq\n" | |
| 9879 "exit: nop\t# avoid branch to branch" %} | |
| 9880 opcode(0x0F, 0x2E); | |
| 9881 ins_encode(REX_reg_reg(src1, src2), OpcP, OpcS, reg_reg(src1, src2), | |
| 9882 cmpfp_fixup); | |
| 9883 ins_pipe(pipe_slow); | |
| 9884 %} | |
| 9885 | |
|
415
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|
9886 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{ |
|
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|
9887 match(Set cr (CmpF src1 src2)); |
|
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403
diff
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|
9888 |
|
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diff
changeset
|
9889 ins_cost(145); |
|
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diff
changeset
|
9890 format %{ "ucomiss $src1, $src2" %} |
|
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403
diff
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|
9891 ins_encode %{ |
|
4d9884b01ba6
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diff
changeset
|
9892 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); |
|
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403
diff
changeset
|
9893 %} |
|
4d9884b01ba6
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diff
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|
9894 ins_pipe(pipe_slow); |
|
4d9884b01ba6
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403
diff
changeset
|
9895 %} |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
9896 |
| 0 | 9897 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2) |
| 9898 %{ | |
| 9899 match(Set cr (CmpF src1 (LoadF src2))); | |
| 9900 | |
| 9901 ins_cost(145); | |
| 9902 format %{ "ucomiss $src1, $src2\n\t" | |
| 9903 "jnp,s exit\n\t" | |
| 9904 "pushfq\t# saw NaN, set CF\n\t" | |
| 9905 "andq [rsp], #0xffffff2b\n\t" | |
| 9906 "popfq\n" | |
| 9907 "exit: nop\t# avoid branch to branch" %} | |
| 9908 opcode(0x0F, 0x2E); | |
| 9909 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, reg_mem(src1, src2), | |
| 9910 cmpfp_fixup); | |
| 9911 ins_pipe(pipe_slow); | |
| 9912 %} | |
| 9913 | |
|
415
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|
9914 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{ |
|
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diff
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|
9915 match(Set cr (CmpF src1 (LoadF src2))); |
|
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parents:
403
diff
changeset
|
9916 |
|
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diff
changeset
|
9917 ins_cost(100); |
|
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diff
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|
9918 format %{ "ucomiss $src1, $src2" %} |
|
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403
diff
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|
9919 opcode(0x0F, 0x2E); |
|
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diff
changeset
|
9920 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, reg_mem(src1, src2)); |
|
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diff
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|
9921 ins_pipe(pipe_slow); |
|
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diff
changeset
|
9922 %} |
|
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diff
changeset
|
9923 |
| 0 | 9924 instruct cmpF_cc_imm(rFlagsRegU cr, regF src1, immF src2) |
| 9925 %{ | |
| 9926 match(Set cr (CmpF src1 src2)); | |
| 9927 | |
| 9928 ins_cost(145); | |
| 9929 format %{ "ucomiss $src1, $src2\n\t" | |
| 9930 "jnp,s exit\n\t" | |
| 9931 "pushfq\t# saw NaN, set CF\n\t" | |
| 9932 "andq [rsp], #0xffffff2b\n\t" | |
| 9933 "popfq\n" | |
| 9934 "exit: nop\t# avoid branch to branch" %} | |
| 9935 opcode(0x0F, 0x2E); | |
| 9936 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, load_immF(src1, src2), | |
| 9937 cmpfp_fixup); | |
| 9938 ins_pipe(pipe_slow); | |
| 9939 %} | |
| 9940 | |
|
415
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|
9941 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src1, immF src2) %{ |
|
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diff
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|
9942 match(Set cr (CmpF src1 src2)); |
|
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diff
changeset
|
9943 |
|
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diff
changeset
|
9944 ins_cost(100); |
|
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diff
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|
9945 format %{ "ucomiss $src1, $src2" %} |
|
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parents:
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diff
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|
9946 opcode(0x0F, 0x2E); |
|
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diff
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|
9947 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, load_immF(src1, src2)); |
|
4d9884b01ba6
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|
9948 ins_pipe(pipe_slow); |
|
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diff
changeset
|
9949 %} |
|
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diff
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|
9950 |
| 0 | 9951 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2) |
| 9952 %{ | |
| 9953 match(Set cr (CmpD src1 src2)); | |
| 9954 | |
| 9955 ins_cost(145); | |
| 9956 format %{ "ucomisd $src1, $src2\n\t" | |
| 9957 "jnp,s exit\n\t" | |
| 9958 "pushfq\t# saw NaN, set CF\n\t" | |
| 9959 "andq [rsp], #0xffffff2b\n\t" | |
| 9960 "popfq\n" | |
| 9961 "exit: nop\t# avoid branch to branch" %} | |
| 9962 opcode(0x66, 0x0F, 0x2E); | |
| 9963 ins_encode(OpcP, REX_reg_reg(src1, src2), OpcS, OpcT, reg_reg(src1, src2), | |
| 9964 cmpfp_fixup); | |
| 9965 ins_pipe(pipe_slow); | |
| 9966 %} | |
| 9967 | |
|
415
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|
9968 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{ |
|
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|
9969 match(Set cr (CmpD src1 src2)); |
|
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403
diff
changeset
|
9970 |
|
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diff
changeset
|
9971 ins_cost(100); |
|
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diff
changeset
|
9972 format %{ "ucomisd $src1, $src2 test" %} |
|
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403
diff
changeset
|
9973 ins_encode %{ |
|
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changeset
|
9974 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); |
|
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changeset
|
9975 %} |
|
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|
9976 ins_pipe(pipe_slow); |
|
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diff
changeset
|
9977 %} |
|
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diff
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|
9978 |
| 0 | 9979 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2) |
| 9980 %{ | |
| 9981 match(Set cr (CmpD src1 (LoadD src2))); | |
| 9982 | |
| 9983 ins_cost(145); | |
| 9984 format %{ "ucomisd $src1, $src2\n\t" | |
| 9985 "jnp,s exit\n\t" | |
| 9986 "pushfq\t# saw NaN, set CF\n\t" | |
| 9987 "andq [rsp], #0xffffff2b\n\t" | |
| 9988 "popfq\n" | |
| 9989 "exit: nop\t# avoid branch to branch" %} | |
| 9990 opcode(0x66, 0x0F, 0x2E); | |
| 9991 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, reg_mem(src1, src2), | |
| 9992 cmpfp_fixup); | |
| 9993 ins_pipe(pipe_slow); | |
| 9994 %} | |
| 9995 | |
|
415
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|
9996 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{ |
|
4d9884b01ba6
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diff
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|
9997 match(Set cr (CmpD src1 (LoadD src2))); |
|
4d9884b01ba6
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diff
changeset
|
9998 |
|
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diff
changeset
|
9999 ins_cost(100); |
|
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diff
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|
10000 format %{ "ucomisd $src1, $src2" %} |
|
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diff
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|
10001 opcode(0x66, 0x0F, 0x2E); |
|
4d9884b01ba6
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diff
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|
10002 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, reg_mem(src1, src2)); |
|
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|
10003 ins_pipe(pipe_slow); |
|
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diff
changeset
|
10004 %} |
|
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diff
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|
10005 |
| 0 | 10006 instruct cmpD_cc_imm(rFlagsRegU cr, regD src1, immD src2) |
| 10007 %{ | |
| 10008 match(Set cr (CmpD src1 src2)); | |
| 10009 | |
| 10010 ins_cost(145); | |
| 10011 format %{ "ucomisd $src1, [$src2]\n\t" | |
| 10012 "jnp,s exit\n\t" | |
| 10013 "pushfq\t# saw NaN, set CF\n\t" | |
| 10014 "andq [rsp], #0xffffff2b\n\t" | |
| 10015 "popfq\n" | |
| 10016 "exit: nop\t# avoid branch to branch" %} | |
| 10017 opcode(0x66, 0x0F, 0x2E); | |
| 10018 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, load_immD(src1, src2), | |
| 10019 cmpfp_fixup); | |
| 10020 ins_pipe(pipe_slow); | |
| 10021 %} | |
| 10022 | |
|
415
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changeset
|
10023 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src1, immD src2) %{ |
|
4d9884b01ba6
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diff
changeset
|
10024 match(Set cr (CmpD src1 src2)); |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
10025 |
|
4d9884b01ba6
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diff
changeset
|
10026 ins_cost(100); |
|
4d9884b01ba6
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parents:
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diff
changeset
|
10027 format %{ "ucomisd $src1, [$src2]" %} |
|
4d9884b01ba6
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parents:
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diff
changeset
|
10028 opcode(0x66, 0x0F, 0x2E); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
10029 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, load_immD(src1, src2)); |
|
4d9884b01ba6
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diff
changeset
|
10030 ins_pipe(pipe_slow); |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
10031 %} |
|
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diff
changeset
|
10032 |
| 0 | 10033 // Compare into -1,0,1 |
| 10034 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr) | |
| 10035 %{ | |
| 10036 match(Set dst (CmpF3 src1 src2)); | |
| 10037 effect(KILL cr); | |
| 10038 | |
| 10039 ins_cost(275); | |
| 10040 format %{ "ucomiss $src1, $src2\n\t" | |
| 10041 "movl $dst, #-1\n\t" | |
| 10042 "jp,s done\n\t" | |
| 10043 "jb,s done\n\t" | |
| 10044 "setne $dst\n\t" | |
| 10045 "movzbl $dst, $dst\n" | |
| 10046 "done:" %} | |
| 10047 | |
| 10048 opcode(0x0F, 0x2E); | |
| 10049 ins_encode(REX_reg_reg(src1, src2), OpcP, OpcS, reg_reg(src1, src2), | |
| 10050 cmpfp3(dst)); | |
| 10051 ins_pipe(pipe_slow); | |
| 10052 %} | |
| 10053 | |
| 10054 // Compare into -1,0,1 | |
| 10055 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr) | |
| 10056 %{ | |
| 10057 match(Set dst (CmpF3 src1 (LoadF src2))); | |
| 10058 effect(KILL cr); | |
| 10059 | |
| 10060 ins_cost(275); | |
| 10061 format %{ "ucomiss $src1, $src2\n\t" | |
| 10062 "movl $dst, #-1\n\t" | |
| 10063 "jp,s done\n\t" | |
| 10064 "jb,s done\n\t" | |
| 10065 "setne $dst\n\t" | |
| 10066 "movzbl $dst, $dst\n" | |
| 10067 "done:" %} | |
| 10068 | |
| 10069 opcode(0x0F, 0x2E); | |
| 10070 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, reg_mem(src1, src2), | |
| 10071 cmpfp3(dst)); | |
| 10072 ins_pipe(pipe_slow); | |
| 10073 %} | |
| 10074 | |
| 10075 // Compare into -1,0,1 | |
| 10076 instruct cmpF_imm(rRegI dst, regF src1, immF src2, rFlagsReg cr) | |
| 10077 %{ | |
| 10078 match(Set dst (CmpF3 src1 src2)); | |
| 10079 effect(KILL cr); | |
| 10080 | |
| 10081 ins_cost(275); | |
| 10082 format %{ "ucomiss $src1, [$src2]\n\t" | |
| 10083 "movl $dst, #-1\n\t" | |
| 10084 "jp,s done\n\t" | |
| 10085 "jb,s done\n\t" | |
| 10086 "setne $dst\n\t" | |
| 10087 "movzbl $dst, $dst\n" | |
| 10088 "done:" %} | |
| 10089 | |
| 10090 opcode(0x0F, 0x2E); | |
| 10091 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, load_immF(src1, src2), | |
| 10092 cmpfp3(dst)); | |
| 10093 ins_pipe(pipe_slow); | |
| 10094 %} | |
| 10095 | |
| 10096 // Compare into -1,0,1 | |
| 10097 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr) | |
| 10098 %{ | |
| 10099 match(Set dst (CmpD3 src1 src2)); | |
| 10100 effect(KILL cr); | |
| 10101 | |
| 10102 ins_cost(275); | |
| 10103 format %{ "ucomisd $src1, $src2\n\t" | |
| 10104 "movl $dst, #-1\n\t" | |
| 10105 "jp,s done\n\t" | |
| 10106 "jb,s done\n\t" | |
| 10107 "setne $dst\n\t" | |
| 10108 "movzbl $dst, $dst\n" | |
| 10109 "done:" %} | |
| 10110 | |
| 10111 opcode(0x66, 0x0F, 0x2E); | |
| 10112 ins_encode(OpcP, REX_reg_reg(src1, src2), OpcS, OpcT, reg_reg(src1, src2), | |
| 10113 cmpfp3(dst)); | |
| 10114 ins_pipe(pipe_slow); | |
| 10115 %} | |
| 10116 | |
| 10117 // Compare into -1,0,1 | |
| 10118 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr) | |
| 10119 %{ | |
| 10120 match(Set dst (CmpD3 src1 (LoadD src2))); | |
| 10121 effect(KILL cr); | |
| 10122 | |
| 10123 ins_cost(275); | |
| 10124 format %{ "ucomisd $src1, $src2\n\t" | |
| 10125 "movl $dst, #-1\n\t" | |
| 10126 "jp,s done\n\t" | |
| 10127 "jb,s done\n\t" | |
| 10128 "setne $dst\n\t" | |
| 10129 "movzbl $dst, $dst\n" | |
| 10130 "done:" %} | |
| 10131 | |
| 10132 opcode(0x66, 0x0F, 0x2E); | |
| 10133 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, reg_mem(src1, src2), | |
| 10134 cmpfp3(dst)); | |
| 10135 ins_pipe(pipe_slow); | |
| 10136 %} | |
| 10137 | |
| 10138 // Compare into -1,0,1 | |
| 10139 instruct cmpD_imm(rRegI dst, regD src1, immD src2, rFlagsReg cr) | |
| 10140 %{ | |
| 10141 match(Set dst (CmpD3 src1 src2)); | |
| 10142 effect(KILL cr); | |
| 10143 | |
| 10144 ins_cost(275); | |
| 10145 format %{ "ucomisd $src1, [$src2]\n\t" | |
| 10146 "movl $dst, #-1\n\t" | |
| 10147 "jp,s done\n\t" | |
| 10148 "jb,s done\n\t" | |
| 10149 "setne $dst\n\t" | |
| 10150 "movzbl $dst, $dst\n" | |
| 10151 "done:" %} | |
| 10152 | |
| 10153 opcode(0x66, 0x0F, 0x2E); | |
| 10154 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, load_immD(src1, src2), | |
| 10155 cmpfp3(dst)); | |
| 10156 ins_pipe(pipe_slow); | |
| 10157 %} | |
| 10158 | |
| 10159 instruct addF_reg(regF dst, regF src) | |
| 10160 %{ | |
| 10161 match(Set dst (AddF dst src)); | |
| 10162 | |
| 10163 format %{ "addss $dst, $src" %} | |
| 10164 ins_cost(150); // XXX | |
| 10165 opcode(0xF3, 0x0F, 0x58); | |
| 10166 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10167 ins_pipe(pipe_slow); | |
| 10168 %} | |
| 10169 | |
| 10170 instruct addF_mem(regF dst, memory src) | |
| 10171 %{ | |
| 10172 match(Set dst (AddF dst (LoadF src))); | |
| 10173 | |
| 10174 format %{ "addss $dst, $src" %} | |
| 10175 ins_cost(150); // XXX | |
| 10176 opcode(0xF3, 0x0F, 0x58); | |
| 10177 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10178 ins_pipe(pipe_slow); | |
| 10179 %} | |
| 10180 | |
| 10181 instruct addF_imm(regF dst, immF src) | |
| 10182 %{ | |
| 10183 match(Set dst (AddF dst src)); | |
| 10184 | |
| 10185 format %{ "addss $dst, [$src]" %} | |
| 10186 ins_cost(150); // XXX | |
| 10187 opcode(0xF3, 0x0F, 0x58); | |
| 10188 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immF(dst, src)); | |
| 10189 ins_pipe(pipe_slow); | |
| 10190 %} | |
| 10191 | |
| 10192 instruct addD_reg(regD dst, regD src) | |
| 10193 %{ | |
| 10194 match(Set dst (AddD dst src)); | |
| 10195 | |
| 10196 format %{ "addsd $dst, $src" %} | |
| 10197 ins_cost(150); // XXX | |
| 10198 opcode(0xF2, 0x0F, 0x58); | |
| 10199 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10200 ins_pipe(pipe_slow); | |
| 10201 %} | |
| 10202 | |
| 10203 instruct addD_mem(regD dst, memory src) | |
| 10204 %{ | |
| 10205 match(Set dst (AddD dst (LoadD src))); | |
| 10206 | |
| 10207 format %{ "addsd $dst, $src" %} | |
| 10208 ins_cost(150); // XXX | |
| 10209 opcode(0xF2, 0x0F, 0x58); | |
| 10210 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10211 ins_pipe(pipe_slow); | |
| 10212 %} | |
| 10213 | |
| 10214 instruct addD_imm(regD dst, immD src) | |
| 10215 %{ | |
| 10216 match(Set dst (AddD dst src)); | |
| 10217 | |
| 10218 format %{ "addsd $dst, [$src]" %} | |
| 10219 ins_cost(150); // XXX | |
| 10220 opcode(0xF2, 0x0F, 0x58); | |
| 10221 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immD(dst, src)); | |
| 10222 ins_pipe(pipe_slow); | |
| 10223 %} | |
| 10224 | |
| 10225 instruct subF_reg(regF dst, regF src) | |
| 10226 %{ | |
| 10227 match(Set dst (SubF dst src)); | |
| 10228 | |
| 10229 format %{ "subss $dst, $src" %} | |
| 10230 ins_cost(150); // XXX | |
| 10231 opcode(0xF3, 0x0F, 0x5C); | |
| 10232 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10233 ins_pipe(pipe_slow); | |
| 10234 %} | |
| 10235 | |
| 10236 instruct subF_mem(regF dst, memory src) | |
| 10237 %{ | |
| 10238 match(Set dst (SubF dst (LoadF src))); | |
| 10239 | |
| 10240 format %{ "subss $dst, $src" %} | |
| 10241 ins_cost(150); // XXX | |
| 10242 opcode(0xF3, 0x0F, 0x5C); | |
| 10243 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10244 ins_pipe(pipe_slow); | |
| 10245 %} | |
| 10246 | |
| 10247 instruct subF_imm(regF dst, immF src) | |
| 10248 %{ | |
| 10249 match(Set dst (SubF dst src)); | |
| 10250 | |
| 10251 format %{ "subss $dst, [$src]" %} | |
| 10252 ins_cost(150); // XXX | |
| 10253 opcode(0xF3, 0x0F, 0x5C); | |
| 10254 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immF(dst, src)); | |
| 10255 ins_pipe(pipe_slow); | |
| 10256 %} | |
| 10257 | |
| 10258 instruct subD_reg(regD dst, regD src) | |
| 10259 %{ | |
| 10260 match(Set dst (SubD dst src)); | |
| 10261 | |
| 10262 format %{ "subsd $dst, $src" %} | |
| 10263 ins_cost(150); // XXX | |
| 10264 opcode(0xF2, 0x0F, 0x5C); | |
| 10265 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10266 ins_pipe(pipe_slow); | |
| 10267 %} | |
| 10268 | |
| 10269 instruct subD_mem(regD dst, memory src) | |
| 10270 %{ | |
| 10271 match(Set dst (SubD dst (LoadD src))); | |
| 10272 | |
| 10273 format %{ "subsd $dst, $src" %} | |
| 10274 ins_cost(150); // XXX | |
| 10275 opcode(0xF2, 0x0F, 0x5C); | |
| 10276 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10277 ins_pipe(pipe_slow); | |
| 10278 %} | |
| 10279 | |
| 10280 instruct subD_imm(regD dst, immD src) | |
| 10281 %{ | |
| 10282 match(Set dst (SubD dst src)); | |
| 10283 | |
| 10284 format %{ "subsd $dst, [$src]" %} | |
| 10285 ins_cost(150); // XXX | |
| 10286 opcode(0xF2, 0x0F, 0x5C); | |
| 10287 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immD(dst, src)); | |
| 10288 ins_pipe(pipe_slow); | |
| 10289 %} | |
| 10290 | |
| 10291 instruct mulF_reg(regF dst, regF src) | |
| 10292 %{ | |
| 10293 match(Set dst (MulF dst src)); | |
| 10294 | |
| 10295 format %{ "mulss $dst, $src" %} | |
| 10296 ins_cost(150); // XXX | |
| 10297 opcode(0xF3, 0x0F, 0x59); | |
| 10298 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10299 ins_pipe(pipe_slow); | |
| 10300 %} | |
| 10301 | |
| 10302 instruct mulF_mem(regF dst, memory src) | |
| 10303 %{ | |
| 10304 match(Set dst (MulF dst (LoadF src))); | |
| 10305 | |
| 10306 format %{ "mulss $dst, $src" %} | |
| 10307 ins_cost(150); // XXX | |
| 10308 opcode(0xF3, 0x0F, 0x59); | |
| 10309 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10310 ins_pipe(pipe_slow); | |
| 10311 %} | |
| 10312 | |
| 10313 instruct mulF_imm(regF dst, immF src) | |
| 10314 %{ | |
| 10315 match(Set dst (MulF dst src)); | |
| 10316 | |
| 10317 format %{ "mulss $dst, [$src]" %} | |
| 10318 ins_cost(150); // XXX | |
| 10319 opcode(0xF3, 0x0F, 0x59); | |
| 10320 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immF(dst, src)); | |
| 10321 ins_pipe(pipe_slow); | |
| 10322 %} | |
| 10323 | |
| 10324 instruct mulD_reg(regD dst, regD src) | |
| 10325 %{ | |
| 10326 match(Set dst (MulD dst src)); | |
| 10327 | |
| 10328 format %{ "mulsd $dst, $src" %} | |
| 10329 ins_cost(150); // XXX | |
| 10330 opcode(0xF2, 0x0F, 0x59); | |
| 10331 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10332 ins_pipe(pipe_slow); | |
| 10333 %} | |
| 10334 | |
| 10335 instruct mulD_mem(regD dst, memory src) | |
| 10336 %{ | |
| 10337 match(Set dst (MulD dst (LoadD src))); | |
| 10338 | |
| 10339 format %{ "mulsd $dst, $src" %} | |
| 10340 ins_cost(150); // XXX | |
| 10341 opcode(0xF2, 0x0F, 0x59); | |
| 10342 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10343 ins_pipe(pipe_slow); | |
| 10344 %} | |
| 10345 | |
| 10346 instruct mulD_imm(regD dst, immD src) | |
| 10347 %{ | |
| 10348 match(Set dst (MulD dst src)); | |
| 10349 | |
| 10350 format %{ "mulsd $dst, [$src]" %} | |
| 10351 ins_cost(150); // XXX | |
| 10352 opcode(0xF2, 0x0F, 0x59); | |
| 10353 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immD(dst, src)); | |
| 10354 ins_pipe(pipe_slow); | |
| 10355 %} | |
| 10356 | |
| 10357 instruct divF_reg(regF dst, regF src) | |
| 10358 %{ | |
| 10359 match(Set dst (DivF dst src)); | |
| 10360 | |
| 10361 format %{ "divss $dst, $src" %} | |
| 10362 ins_cost(150); // XXX | |
| 10363 opcode(0xF3, 0x0F, 0x5E); | |
| 10364 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10365 ins_pipe(pipe_slow); | |
| 10366 %} | |
| 10367 | |
| 10368 instruct divF_mem(regF dst, memory src) | |
| 10369 %{ | |
| 10370 match(Set dst (DivF dst (LoadF src))); | |
| 10371 | |
| 10372 format %{ "divss $dst, $src" %} | |
| 10373 ins_cost(150); // XXX | |
| 10374 opcode(0xF3, 0x0F, 0x5E); | |
| 10375 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10376 ins_pipe(pipe_slow); | |
| 10377 %} | |
| 10378 | |
| 10379 instruct divF_imm(regF dst, immF src) | |
| 10380 %{ | |
| 10381 match(Set dst (DivF dst src)); | |
| 10382 | |
| 10383 format %{ "divss $dst, [$src]" %} | |
| 10384 ins_cost(150); // XXX | |
| 10385 opcode(0xF3, 0x0F, 0x5E); | |
| 10386 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immF(dst, src)); | |
| 10387 ins_pipe(pipe_slow); | |
| 10388 %} | |
| 10389 | |
| 10390 instruct divD_reg(regD dst, regD src) | |
| 10391 %{ | |
| 10392 match(Set dst (DivD dst src)); | |
| 10393 | |
| 10394 format %{ "divsd $dst, $src" %} | |
| 10395 ins_cost(150); // XXX | |
| 10396 opcode(0xF2, 0x0F, 0x5E); | |
| 10397 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10398 ins_pipe(pipe_slow); | |
| 10399 %} | |
| 10400 | |
| 10401 instruct divD_mem(regD dst, memory src) | |
| 10402 %{ | |
| 10403 match(Set dst (DivD dst (LoadD src))); | |
| 10404 | |
| 10405 format %{ "divsd $dst, $src" %} | |
| 10406 ins_cost(150); // XXX | |
| 10407 opcode(0xF2, 0x0F, 0x5E); | |
| 10408 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10409 ins_pipe(pipe_slow); | |
| 10410 %} | |
| 10411 | |
| 10412 instruct divD_imm(regD dst, immD src) | |
| 10413 %{ | |
| 10414 match(Set dst (DivD dst src)); | |
| 10415 | |
| 10416 format %{ "divsd $dst, [$src]" %} | |
| 10417 ins_cost(150); // XXX | |
| 10418 opcode(0xF2, 0x0F, 0x5E); | |
| 10419 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immD(dst, src)); | |
| 10420 ins_pipe(pipe_slow); | |
| 10421 %} | |
| 10422 | |
| 10423 instruct sqrtF_reg(regF dst, regF src) | |
| 10424 %{ | |
| 10425 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); | |
| 10426 | |
| 10427 format %{ "sqrtss $dst, $src" %} | |
| 10428 ins_cost(150); // XXX | |
| 10429 opcode(0xF3, 0x0F, 0x51); | |
| 10430 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10431 ins_pipe(pipe_slow); | |
| 10432 %} | |
| 10433 | |
| 10434 instruct sqrtF_mem(regF dst, memory src) | |
| 10435 %{ | |
| 10436 match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF src))))); | |
| 10437 | |
| 10438 format %{ "sqrtss $dst, $src" %} | |
| 10439 ins_cost(150); // XXX | |
| 10440 opcode(0xF3, 0x0F, 0x51); | |
| 10441 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10442 ins_pipe(pipe_slow); | |
| 10443 %} | |
| 10444 | |
| 10445 instruct sqrtF_imm(regF dst, immF src) | |
| 10446 %{ | |
| 10447 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); | |
| 10448 | |
| 10449 format %{ "sqrtss $dst, [$src]" %} | |
| 10450 ins_cost(150); // XXX | |
| 10451 opcode(0xF3, 0x0F, 0x51); | |
| 10452 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immF(dst, src)); | |
| 10453 ins_pipe(pipe_slow); | |
| 10454 %} | |
| 10455 | |
| 10456 instruct sqrtD_reg(regD dst, regD src) | |
| 10457 %{ | |
| 10458 match(Set dst (SqrtD src)); | |
| 10459 | |
| 10460 format %{ "sqrtsd $dst, $src" %} | |
| 10461 ins_cost(150); // XXX | |
| 10462 opcode(0xF2, 0x0F, 0x51); | |
| 10463 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10464 ins_pipe(pipe_slow); | |
| 10465 %} | |
| 10466 | |
| 10467 instruct sqrtD_mem(regD dst, memory src) | |
| 10468 %{ | |
| 10469 match(Set dst (SqrtD (LoadD src))); | |
| 10470 | |
| 10471 format %{ "sqrtsd $dst, $src" %} | |
| 10472 ins_cost(150); // XXX | |
| 10473 opcode(0xF2, 0x0F, 0x51); | |
| 10474 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10475 ins_pipe(pipe_slow); | |
| 10476 %} | |
| 10477 | |
| 10478 instruct sqrtD_imm(regD dst, immD src) | |
| 10479 %{ | |
| 10480 match(Set dst (SqrtD src)); | |
| 10481 | |
| 10482 format %{ "sqrtsd $dst, [$src]" %} | |
| 10483 ins_cost(150); // XXX | |
| 10484 opcode(0xF2, 0x0F, 0x51); | |
| 10485 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immD(dst, src)); | |
| 10486 ins_pipe(pipe_slow); | |
| 10487 %} | |
| 10488 | |
| 10489 instruct absF_reg(regF dst) | |
| 10490 %{ | |
| 10491 match(Set dst (AbsF dst)); | |
| 10492 | |
| 10493 format %{ "andps $dst, [0x7fffffff]\t# abs float by sign masking" %} | |
| 10494 ins_encode(absF_encoding(dst)); | |
| 10495 ins_pipe(pipe_slow); | |
| 10496 %} | |
| 10497 | |
| 10498 instruct absD_reg(regD dst) | |
| 10499 %{ | |
| 10500 match(Set dst (AbsD dst)); | |
| 10501 | |
| 10502 format %{ "andpd $dst, [0x7fffffffffffffff]\t" | |
| 10503 "# abs double by sign masking" %} | |
| 10504 ins_encode(absD_encoding(dst)); | |
| 10505 ins_pipe(pipe_slow); | |
| 10506 %} | |
| 10507 | |
| 10508 instruct negF_reg(regF dst) | |
| 10509 %{ | |
| 10510 match(Set dst (NegF dst)); | |
| 10511 | |
| 10512 format %{ "xorps $dst, [0x80000000]\t# neg float by sign flipping" %} | |
| 10513 ins_encode(negF_encoding(dst)); | |
| 10514 ins_pipe(pipe_slow); | |
| 10515 %} | |
| 10516 | |
| 10517 instruct negD_reg(regD dst) | |
| 10518 %{ | |
| 10519 match(Set dst (NegD dst)); | |
| 10520 | |
| 10521 format %{ "xorpd $dst, [0x8000000000000000]\t" | |
| 10522 "# neg double by sign flipping" %} | |
| 10523 ins_encode(negD_encoding(dst)); | |
| 10524 ins_pipe(pipe_slow); | |
| 10525 %} | |
| 10526 | |
| 10527 // -----------Trig and Trancendental Instructions------------------------------ | |
| 10528 instruct cosD_reg(regD dst) %{ | |
| 10529 match(Set dst (CosD dst)); | |
| 10530 | |
| 10531 format %{ "dcos $dst\n\t" %} | |
| 10532 opcode(0xD9, 0xFF); | |
| 10533 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) ); | |
| 10534 ins_pipe( pipe_slow ); | |
| 10535 %} | |
| 10536 | |
| 10537 instruct sinD_reg(regD dst) %{ | |
| 10538 match(Set dst (SinD dst)); | |
| 10539 | |
| 10540 format %{ "dsin $dst\n\t" %} | |
| 10541 opcode(0xD9, 0xFE); | |
| 10542 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) ); | |
| 10543 ins_pipe( pipe_slow ); | |
| 10544 %} | |
| 10545 | |
| 10546 instruct tanD_reg(regD dst) %{ | |
| 10547 match(Set dst (TanD dst)); | |
| 10548 | |
| 10549 format %{ "dtan $dst\n\t" %} | |
| 10550 ins_encode( Push_SrcXD(dst), | |
| 10551 Opcode(0xD9), Opcode(0xF2), //fptan | |
| 10552 Opcode(0xDD), Opcode(0xD8), //fstp st | |
| 10553 Push_ResultXD(dst) ); | |
| 10554 ins_pipe( pipe_slow ); | |
| 10555 %} | |
| 10556 | |
| 10557 instruct log10D_reg(regD dst) %{ | |
| 10558 // The source and result Double operands in XMM registers | |
| 10559 match(Set dst (Log10D dst)); | |
| 10560 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number | |
| 10561 // fyl2x ; compute log_10(2) * log_2(x) | |
| 10562 format %{ "fldlg2\t\t\t#Log10\n\t" | |
| 10563 "fyl2x\t\t\t# Q=Log10*Log_2(x)\n\t" | |
| 10564 %} | |
| 10565 ins_encode(Opcode(0xD9), Opcode(0xEC), // fldlg2 | |
| 10566 Push_SrcXD(dst), | |
| 10567 Opcode(0xD9), Opcode(0xF1), // fyl2x | |
| 10568 Push_ResultXD(dst)); | |
| 10569 | |
| 10570 ins_pipe( pipe_slow ); | |
| 10571 %} | |
| 10572 | |
| 10573 instruct logD_reg(regD dst) %{ | |
| 10574 // The source and result Double operands in XMM registers | |
| 10575 match(Set dst (LogD dst)); | |
| 10576 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number | |
| 10577 // fyl2x ; compute log_e(2) * log_2(x) | |
| 10578 format %{ "fldln2\t\t\t#Log_e\n\t" | |
| 10579 "fyl2x\t\t\t# Q=Log_e*Log_2(x)\n\t" | |
| 10580 %} | |
| 10581 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 | |
| 10582 Push_SrcXD(dst), | |
| 10583 Opcode(0xD9), Opcode(0xF1), // fyl2x | |
| 10584 Push_ResultXD(dst)); | |
| 10585 ins_pipe( pipe_slow ); | |
| 10586 %} | |
| 10587 | |
| 10588 | |
| 10589 | |
| 10590 //----------Arithmetic Conversion Instructions--------------------------------- | |
| 10591 | |
| 10592 instruct roundFloat_nop(regF dst) | |
| 10593 %{ | |
| 10594 match(Set dst (RoundFloat dst)); | |
| 10595 | |
| 10596 ins_cost(0); | |
| 10597 ins_encode(); | |
| 10598 ins_pipe(empty); | |
| 10599 %} | |
| 10600 | |
| 10601 instruct roundDouble_nop(regD dst) | |
| 10602 %{ | |
| 10603 match(Set dst (RoundDouble dst)); | |
| 10604 | |
| 10605 ins_cost(0); | |
| 10606 ins_encode(); | |
| 10607 ins_pipe(empty); | |
| 10608 %} | |
| 10609 | |
| 10610 instruct convF2D_reg_reg(regD dst, regF src) | |
| 10611 %{ | |
| 10612 match(Set dst (ConvF2D src)); | |
| 10613 | |
| 10614 format %{ "cvtss2sd $dst, $src" %} | |
| 10615 opcode(0xF3, 0x0F, 0x5A); | |
| 10616 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10617 ins_pipe(pipe_slow); // XXX | |
| 10618 %} | |
| 10619 | |
| 10620 instruct convF2D_reg_mem(regD dst, memory src) | |
| 10621 %{ | |
| 10622 match(Set dst (ConvF2D (LoadF src))); | |
| 10623 | |
| 10624 format %{ "cvtss2sd $dst, $src" %} | |
| 10625 opcode(0xF3, 0x0F, 0x5A); | |
| 10626 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10627 ins_pipe(pipe_slow); // XXX | |
| 10628 %} | |
| 10629 | |
| 10630 instruct convD2F_reg_reg(regF dst, regD src) | |
| 10631 %{ | |
| 10632 match(Set dst (ConvD2F src)); | |
| 10633 | |
| 10634 format %{ "cvtsd2ss $dst, $src" %} | |
| 10635 opcode(0xF2, 0x0F, 0x5A); | |
| 10636 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10637 ins_pipe(pipe_slow); // XXX | |
| 10638 %} | |
| 10639 | |
| 10640 instruct convD2F_reg_mem(regF dst, memory src) | |
| 10641 %{ | |
| 10642 match(Set dst (ConvD2F (LoadD src))); | |
| 10643 | |
| 10644 format %{ "cvtsd2ss $dst, $src" %} | |
| 10645 opcode(0xF2, 0x0F, 0x5A); | |
| 10646 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10647 ins_pipe(pipe_slow); // XXX | |
| 10648 %} | |
| 10649 | |
| 10650 // XXX do mem variants | |
| 10651 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr) | |
| 10652 %{ | |
| 10653 match(Set dst (ConvF2I src)); | |
| 10654 effect(KILL cr); | |
| 10655 | |
| 10656 format %{ "cvttss2sil $dst, $src\t# f2i\n\t" | |
| 10657 "cmpl $dst, #0x80000000\n\t" | |
| 10658 "jne,s done\n\t" | |
| 10659 "subq rsp, #8\n\t" | |
| 10660 "movss [rsp], $src\n\t" | |
| 10661 "call f2i_fixup\n\t" | |
| 10662 "popq $dst\n" | |
| 10663 "done: "%} | |
| 10664 opcode(0xF3, 0x0F, 0x2C); | |
| 10665 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src), | |
| 10666 f2i_fixup(dst, src)); | |
| 10667 ins_pipe(pipe_slow); | |
| 10668 %} | |
| 10669 | |
| 10670 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr) | |
| 10671 %{ | |
| 10672 match(Set dst (ConvF2L src)); | |
| 10673 effect(KILL cr); | |
| 10674 | |
| 10675 format %{ "cvttss2siq $dst, $src\t# f2l\n\t" | |
| 10676 "cmpq $dst, [0x8000000000000000]\n\t" | |
| 10677 "jne,s done\n\t" | |
| 10678 "subq rsp, #8\n\t" | |
| 10679 "movss [rsp], $src\n\t" | |
| 10680 "call f2l_fixup\n\t" | |
| 10681 "popq $dst\n" | |
| 10682 "done: "%} | |
| 10683 opcode(0xF3, 0x0F, 0x2C); | |
| 10684 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src), | |
| 10685 f2l_fixup(dst, src)); | |
| 10686 ins_pipe(pipe_slow); | |
| 10687 %} | |
| 10688 | |
| 10689 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr) | |
| 10690 %{ | |
| 10691 match(Set dst (ConvD2I src)); | |
| 10692 effect(KILL cr); | |
| 10693 | |
| 10694 format %{ "cvttsd2sil $dst, $src\t# d2i\n\t" | |
| 10695 "cmpl $dst, #0x80000000\n\t" | |
| 10696 "jne,s done\n\t" | |
| 10697 "subq rsp, #8\n\t" | |
| 10698 "movsd [rsp], $src\n\t" | |
| 10699 "call d2i_fixup\n\t" | |
| 10700 "popq $dst\n" | |
| 10701 "done: "%} | |
| 10702 opcode(0xF2, 0x0F, 0x2C); | |
| 10703 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src), | |
| 10704 d2i_fixup(dst, src)); | |
| 10705 ins_pipe(pipe_slow); | |
| 10706 %} | |
| 10707 | |
| 10708 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr) | |
| 10709 %{ | |
| 10710 match(Set dst (ConvD2L src)); | |
| 10711 effect(KILL cr); | |
| 10712 | |
| 10713 format %{ "cvttsd2siq $dst, $src\t# d2l\n\t" | |
| 10714 "cmpq $dst, [0x8000000000000000]\n\t" | |
| 10715 "jne,s done\n\t" | |
| 10716 "subq rsp, #8\n\t" | |
| 10717 "movsd [rsp], $src\n\t" | |
| 10718 "call d2l_fixup\n\t" | |
| 10719 "popq $dst\n" | |
| 10720 "done: "%} | |
| 10721 opcode(0xF2, 0x0F, 0x2C); | |
| 10722 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src), | |
| 10723 d2l_fixup(dst, src)); | |
| 10724 ins_pipe(pipe_slow); | |
| 10725 %} | |
| 10726 | |
| 10727 instruct convI2F_reg_reg(regF dst, rRegI src) | |
| 10728 %{ | |
| 71 | 10729 predicate(!UseXmmI2F); |
| 0 | 10730 match(Set dst (ConvI2F src)); |
| 10731 | |
| 10732 format %{ "cvtsi2ssl $dst, $src\t# i2f" %} | |
| 10733 opcode(0xF3, 0x0F, 0x2A); | |
| 10734 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10735 ins_pipe(pipe_slow); // XXX | |
| 10736 %} | |
| 10737 | |
| 10738 instruct convI2F_reg_mem(regF dst, memory src) | |
| 10739 %{ | |
| 10740 match(Set dst (ConvI2F (LoadI src))); | |
| 10741 | |
| 10742 format %{ "cvtsi2ssl $dst, $src\t# i2f" %} | |
| 10743 opcode(0xF3, 0x0F, 0x2A); | |
| 10744 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10745 ins_pipe(pipe_slow); // XXX | |
| 10746 %} | |
| 10747 | |
| 10748 instruct convI2D_reg_reg(regD dst, rRegI src) | |
| 10749 %{ | |
| 71 | 10750 predicate(!UseXmmI2D); |
| 0 | 10751 match(Set dst (ConvI2D src)); |
| 10752 | |
| 10753 format %{ "cvtsi2sdl $dst, $src\t# i2d" %} | |
| 10754 opcode(0xF2, 0x0F, 0x2A); | |
| 10755 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10756 ins_pipe(pipe_slow); // XXX | |
| 10757 %} | |
| 10758 | |
| 10759 instruct convI2D_reg_mem(regD dst, memory src) | |
| 10760 %{ | |
| 10761 match(Set dst (ConvI2D (LoadI src))); | |
| 10762 | |
| 10763 format %{ "cvtsi2sdl $dst, $src\t# i2d" %} | |
| 10764 opcode(0xF2, 0x0F, 0x2A); | |
| 10765 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10766 ins_pipe(pipe_slow); // XXX | |
| 10767 %} | |
| 10768 | |
| 71 | 10769 instruct convXI2F_reg(regF dst, rRegI src) |
| 10770 %{ | |
| 10771 predicate(UseXmmI2F); | |
| 10772 match(Set dst (ConvI2F src)); | |
| 10773 | |
| 10774 format %{ "movdl $dst, $src\n\t" | |
| 10775 "cvtdq2psl $dst, $dst\t# i2f" %} | |
| 10776 ins_encode %{ | |
| 10777 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 10778 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister); | |
| 10779 %} | |
| 10780 ins_pipe(pipe_slow); // XXX | |
| 10781 %} | |
| 10782 | |
| 10783 instruct convXI2D_reg(regD dst, rRegI src) | |
| 10784 %{ | |
| 10785 predicate(UseXmmI2D); | |
| 10786 match(Set dst (ConvI2D src)); | |
| 10787 | |
| 10788 format %{ "movdl $dst, $src\n\t" | |
| 10789 "cvtdq2pdl $dst, $dst\t# i2d" %} | |
| 10790 ins_encode %{ | |
| 10791 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 10792 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister); | |
| 10793 %} | |
| 10794 ins_pipe(pipe_slow); // XXX | |
| 10795 %} | |
| 10796 | |
| 0 | 10797 instruct convL2F_reg_reg(regF dst, rRegL src) |
| 10798 %{ | |
| 10799 match(Set dst (ConvL2F src)); | |
| 10800 | |
| 10801 format %{ "cvtsi2ssq $dst, $src\t# l2f" %} | |
| 10802 opcode(0xF3, 0x0F, 0x2A); | |
| 10803 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10804 ins_pipe(pipe_slow); // XXX | |
| 10805 %} | |
| 10806 | |
| 10807 instruct convL2F_reg_mem(regF dst, memory src) | |
| 10808 %{ | |
| 10809 match(Set dst (ConvL2F (LoadL src))); | |
| 10810 | |
| 10811 format %{ "cvtsi2ssq $dst, $src\t# l2f" %} | |
| 10812 opcode(0xF3, 0x0F, 0x2A); | |
| 10813 ins_encode(OpcP, REX_reg_mem_wide(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10814 ins_pipe(pipe_slow); // XXX | |
| 10815 %} | |
| 10816 | |
| 10817 instruct convL2D_reg_reg(regD dst, rRegL src) | |
| 10818 %{ | |
| 10819 match(Set dst (ConvL2D src)); | |
| 10820 | |
| 10821 format %{ "cvtsi2sdq $dst, $src\t# l2d" %} | |
| 10822 opcode(0xF2, 0x0F, 0x2A); | |
| 10823 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10824 ins_pipe(pipe_slow); // XXX | |
| 10825 %} | |
| 10826 | |
| 10827 instruct convL2D_reg_mem(regD dst, memory src) | |
| 10828 %{ | |
| 10829 match(Set dst (ConvL2D (LoadL src))); | |
| 10830 | |
| 10831 format %{ "cvtsi2sdq $dst, $src\t# l2d" %} | |
| 10832 opcode(0xF2, 0x0F, 0x2A); | |
| 10833 ins_encode(OpcP, REX_reg_mem_wide(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10834 ins_pipe(pipe_slow); // XXX | |
| 10835 %} | |
| 10836 | |
| 10837 instruct convI2L_reg_reg(rRegL dst, rRegI src) | |
| 10838 %{ | |
| 10839 match(Set dst (ConvI2L src)); | |
| 10840 | |
| 10841 ins_cost(125); | |
| 10842 format %{ "movslq $dst, $src\t# i2l" %} | |
| 10843 opcode(0x63); // needs REX.W | |
| 10844 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src)); | |
| 10845 ins_pipe(ialu_reg_reg); | |
| 10846 %} | |
| 10847 | |
| 10848 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src) | |
| 10849 // %{ | |
| 10850 // match(Set dst (ConvI2L src)); | |
| 10851 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 && | |
| 10852 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0); | |
| 10853 // predicate(((const TypeNode*) n)->type()->is_long()->_hi == | |
| 10854 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi && | |
| 10855 // ((const TypeNode*) n)->type()->is_long()->_lo == | |
| 10856 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo); | |
| 10857 | |
| 10858 // format %{ "movl $dst, $src\t# unsigned i2l" %} | |
| 10859 // ins_encode(enc_copy(dst, src)); | |
| 10860 // // opcode(0x63); // needs REX.W | |
| 10861 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src)); | |
| 10862 // ins_pipe(ialu_reg_reg); | |
| 10863 // %} | |
| 10864 | |
| 10865 // Zero-extend convert int to long | |
| 10866 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask) | |
| 10867 %{ | |
| 10868 match(Set dst (AndL (ConvI2L src) mask)); | |
| 10869 | |
| 10870 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %} | |
| 10871 ins_encode(enc_copy(dst, src)); | |
| 10872 ins_pipe(ialu_reg_reg); | |
| 10873 %} | |
| 10874 | |
| 10875 // Zero-extend convert int to long | |
| 10876 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask) | |
| 10877 %{ | |
| 10878 match(Set dst (AndL (ConvI2L (LoadI src)) mask)); | |
| 10879 | |
| 10880 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %} | |
| 10881 opcode(0x8B); | |
| 10882 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 10883 ins_pipe(ialu_reg_mem); | |
| 10884 %} | |
| 10885 | |
| 10886 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask) | |
| 10887 %{ | |
| 10888 match(Set dst (AndL src mask)); | |
| 10889 | |
| 10890 format %{ "movl $dst, $src\t# zero-extend long" %} | |
| 10891 ins_encode(enc_copy_always(dst, src)); | |
| 10892 ins_pipe(ialu_reg_reg); | |
| 10893 %} | |
| 10894 | |
| 10895 instruct convL2I_reg_reg(rRegI dst, rRegL src) | |
| 10896 %{ | |
| 10897 match(Set dst (ConvL2I src)); | |
| 10898 | |
| 10899 format %{ "movl $dst, $src\t# l2i" %} | |
| 10900 ins_encode(enc_copy_always(dst, src)); | |
| 10901 ins_pipe(ialu_reg_reg); | |
| 10902 %} | |
| 10903 | |
| 10904 | |
| 10905 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{ | |
| 10906 match(Set dst (MoveF2I src)); | |
| 10907 effect(DEF dst, USE src); | |
| 10908 | |
| 10909 ins_cost(125); | |
| 10910 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %} | |
| 10911 opcode(0x8B); | |
| 10912 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 10913 ins_pipe(ialu_reg_mem); | |
| 10914 %} | |
| 10915 | |
| 10916 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ | |
| 10917 match(Set dst (MoveI2F src)); | |
| 10918 effect(DEF dst, USE src); | |
| 10919 | |
| 10920 ins_cost(125); | |
| 10921 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %} | |
| 10922 opcode(0xF3, 0x0F, 0x10); | |
| 10923 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10924 ins_pipe(pipe_slow); | |
| 10925 %} | |
| 10926 | |
| 10927 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{ | |
| 10928 match(Set dst (MoveD2L src)); | |
| 10929 effect(DEF dst, USE src); | |
| 10930 | |
| 10931 ins_cost(125); | |
| 10932 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %} | |
| 10933 opcode(0x8B); | |
| 10934 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 10935 ins_pipe(ialu_reg_mem); | |
| 10936 %} | |
| 10937 | |
| 10938 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{ | |
| 10939 predicate(!UseXmmLoadAndClearUpper); | |
| 10940 match(Set dst (MoveL2D src)); | |
| 10941 effect(DEF dst, USE src); | |
| 10942 | |
| 10943 ins_cost(125); | |
| 10944 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %} | |
| 10945 opcode(0x66, 0x0F, 0x12); | |
| 10946 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10947 ins_pipe(pipe_slow); | |
| 10948 %} | |
| 10949 | |
| 10950 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ | |
| 10951 predicate(UseXmmLoadAndClearUpper); | |
| 10952 match(Set dst (MoveL2D src)); | |
| 10953 effect(DEF dst, USE src); | |
| 10954 | |
| 10955 ins_cost(125); | |
| 10956 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %} | |
| 10957 opcode(0xF2, 0x0F, 0x10); | |
| 10958 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10959 ins_pipe(pipe_slow); | |
| 10960 %} | |
| 10961 | |
| 10962 | |
| 10963 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ | |
| 10964 match(Set dst (MoveF2I src)); | |
| 10965 effect(DEF dst, USE src); | |
| 10966 | |
| 10967 ins_cost(95); // XXX | |
| 10968 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %} | |
| 10969 opcode(0xF3, 0x0F, 0x11); | |
| 10970 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst)); | |
| 10971 ins_pipe(pipe_slow); | |
| 10972 %} | |
| 10973 | |
| 10974 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{ | |
| 10975 match(Set dst (MoveI2F src)); | |
| 10976 effect(DEF dst, USE src); | |
| 10977 | |
| 10978 ins_cost(100); | |
| 10979 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %} | |
| 10980 opcode(0x89); | |
| 10981 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 10982 ins_pipe( ialu_mem_reg ); | |
| 10983 %} | |
| 10984 | |
| 10985 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ | |
| 10986 match(Set dst (MoveD2L src)); | |
| 10987 effect(DEF dst, USE src); | |
| 10988 | |
| 10989 ins_cost(95); // XXX | |
| 10990 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %} | |
| 10991 opcode(0xF2, 0x0F, 0x11); | |
| 10992 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst)); | |
| 10993 ins_pipe(pipe_slow); | |
| 10994 %} | |
| 10995 | |
| 10996 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{ | |
| 10997 match(Set dst (MoveL2D src)); | |
| 10998 effect(DEF dst, USE src); | |
| 10999 | |
| 11000 ins_cost(100); | |
| 11001 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %} | |
| 11002 opcode(0x89); | |
| 11003 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 11004 ins_pipe(ialu_mem_reg); | |
| 11005 %} | |
| 11006 | |
| 11007 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{ | |
| 11008 match(Set dst (MoveF2I src)); | |
| 11009 effect(DEF dst, USE src); | |
| 11010 ins_cost(85); | |
| 11011 format %{ "movd $dst,$src\t# MoveF2I" %} | |
| 11012 ins_encode %{ __ movdl($dst$$Register, $src$$XMMRegister); %} | |
| 11013 ins_pipe( pipe_slow ); | |
| 11014 %} | |
| 11015 | |
| 11016 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{ | |
| 11017 match(Set dst (MoveD2L src)); | |
| 11018 effect(DEF dst, USE src); | |
| 11019 ins_cost(85); | |
| 11020 format %{ "movd $dst,$src\t# MoveD2L" %} | |
| 11021 ins_encode %{ __ movdq($dst$$Register, $src$$XMMRegister); %} | |
| 11022 ins_pipe( pipe_slow ); | |
| 11023 %} | |
| 11024 | |
| 11025 // The next instructions have long latency and use Int unit. Set high cost. | |
| 11026 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{ | |
| 11027 match(Set dst (MoveI2F src)); | |
| 11028 effect(DEF dst, USE src); | |
| 11029 ins_cost(300); | |
| 11030 format %{ "movd $dst,$src\t# MoveI2F" %} | |
| 11031 ins_encode %{ __ movdl($dst$$XMMRegister, $src$$Register); %} | |
| 11032 ins_pipe( pipe_slow ); | |
| 11033 %} | |
| 11034 | |
| 11035 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{ | |
| 11036 match(Set dst (MoveL2D src)); | |
| 11037 effect(DEF dst, USE src); | |
| 11038 ins_cost(300); | |
| 11039 format %{ "movd $dst,$src\t# MoveL2D" %} | |
| 11040 ins_encode %{ __ movdq($dst$$XMMRegister, $src$$Register); %} | |
| 11041 ins_pipe( pipe_slow ); | |
| 11042 %} | |
| 11043 | |
| 11044 // Replicate scalar to packed byte (1 byte) values in xmm | |
| 11045 instruct Repl8B_reg(regD dst, regD src) %{ | |
| 11046 match(Set dst (Replicate8B src)); | |
| 11047 format %{ "MOVDQA $dst,$src\n\t" | |
| 11048 "PUNPCKLBW $dst,$dst\n\t" | |
| 11049 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %} | |
| 11050 ins_encode( pshufd_8x8(dst, src)); | |
| 11051 ins_pipe( pipe_slow ); | |
| 11052 %} | |
| 11053 | |
| 11054 // Replicate scalar to packed byte (1 byte) values in xmm | |
| 11055 instruct Repl8B_rRegI(regD dst, rRegI src) %{ | |
| 11056 match(Set dst (Replicate8B src)); | |
| 11057 format %{ "MOVD $dst,$src\n\t" | |
| 11058 "PUNPCKLBW $dst,$dst\n\t" | |
| 11059 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %} | |
| 11060 ins_encode( mov_i2x(dst, src), pshufd_8x8(dst, dst)); | |
| 11061 ins_pipe( pipe_slow ); | |
| 11062 %} | |
| 11063 | |
| 11064 // Replicate scalar zero to packed byte (1 byte) values in xmm | |
| 11065 instruct Repl8B_immI0(regD dst, immI0 zero) %{ | |
| 11066 match(Set dst (Replicate8B zero)); | |
| 11067 format %{ "PXOR $dst,$dst\t! replicate8B" %} | |
| 11068 ins_encode( pxor(dst, dst)); | |
| 11069 ins_pipe( fpu_reg_reg ); | |
| 11070 %} | |
| 11071 | |
| 11072 // Replicate scalar to packed shore (2 byte) values in xmm | |
| 11073 instruct Repl4S_reg(regD dst, regD src) %{ | |
| 11074 match(Set dst (Replicate4S src)); | |
| 11075 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %} | |
| 11076 ins_encode( pshufd_4x16(dst, src)); | |
| 11077 ins_pipe( fpu_reg_reg ); | |
| 11078 %} | |
| 11079 | |
| 11080 // Replicate scalar to packed shore (2 byte) values in xmm | |
| 11081 instruct Repl4S_rRegI(regD dst, rRegI src) %{ | |
| 11082 match(Set dst (Replicate4S src)); | |
| 11083 format %{ "MOVD $dst,$src\n\t" | |
| 11084 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %} | |
| 11085 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst)); | |
| 11086 ins_pipe( fpu_reg_reg ); | |
| 11087 %} | |
| 11088 | |
| 11089 // Replicate scalar zero to packed short (2 byte) values in xmm | |
| 11090 instruct Repl4S_immI0(regD dst, immI0 zero) %{ | |
| 11091 match(Set dst (Replicate4S zero)); | |
| 11092 format %{ "PXOR $dst,$dst\t! replicate4S" %} | |
| 11093 ins_encode( pxor(dst, dst)); | |
| 11094 ins_pipe( fpu_reg_reg ); | |
| 11095 %} | |
| 11096 | |
| 11097 // Replicate scalar to packed char (2 byte) values in xmm | |
| 11098 instruct Repl4C_reg(regD dst, regD src) %{ | |
| 11099 match(Set dst (Replicate4C src)); | |
| 11100 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %} | |
| 11101 ins_encode( pshufd_4x16(dst, src)); | |
| 11102 ins_pipe( fpu_reg_reg ); | |
| 11103 %} | |
| 11104 | |
| 11105 // Replicate scalar to packed char (2 byte) values in xmm | |
| 11106 instruct Repl4C_rRegI(regD dst, rRegI src) %{ | |
| 11107 match(Set dst (Replicate4C src)); | |
| 11108 format %{ "MOVD $dst,$src\n\t" | |
| 11109 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %} | |
| 11110 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst)); | |
| 11111 ins_pipe( fpu_reg_reg ); | |
| 11112 %} | |
| 11113 | |
| 11114 // Replicate scalar zero to packed char (2 byte) values in xmm | |
| 11115 instruct Repl4C_immI0(regD dst, immI0 zero) %{ | |
| 11116 match(Set dst (Replicate4C zero)); | |
| 11117 format %{ "PXOR $dst,$dst\t! replicate4C" %} | |
| 11118 ins_encode( pxor(dst, dst)); | |
| 11119 ins_pipe( fpu_reg_reg ); | |
| 11120 %} | |
| 11121 | |
| 11122 // Replicate scalar to packed integer (4 byte) values in xmm | |
| 11123 instruct Repl2I_reg(regD dst, regD src) %{ | |
| 11124 match(Set dst (Replicate2I src)); | |
| 11125 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %} | |
| 11126 ins_encode( pshufd(dst, src, 0x00)); | |
| 11127 ins_pipe( fpu_reg_reg ); | |
| 11128 %} | |
| 11129 | |
| 11130 // Replicate scalar to packed integer (4 byte) values in xmm | |
| 11131 instruct Repl2I_rRegI(regD dst, rRegI src) %{ | |
| 11132 match(Set dst (Replicate2I src)); | |
| 11133 format %{ "MOVD $dst,$src\n\t" | |
| 11134 "PSHUFD $dst,$dst,0x00\t! replicate2I" %} | |
| 11135 ins_encode( mov_i2x(dst, src), pshufd(dst, dst, 0x00)); | |
| 11136 ins_pipe( fpu_reg_reg ); | |
| 11137 %} | |
| 11138 | |
| 11139 // Replicate scalar zero to packed integer (2 byte) values in xmm | |
| 11140 instruct Repl2I_immI0(regD dst, immI0 zero) %{ | |
| 11141 match(Set dst (Replicate2I zero)); | |
| 11142 format %{ "PXOR $dst,$dst\t! replicate2I" %} | |
| 11143 ins_encode( pxor(dst, dst)); | |
| 11144 ins_pipe( fpu_reg_reg ); | |
| 11145 %} | |
| 11146 | |
| 11147 // Replicate scalar to packed single precision floating point values in xmm | |
| 11148 instruct Repl2F_reg(regD dst, regD src) %{ | |
| 11149 match(Set dst (Replicate2F src)); | |
| 11150 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %} | |
| 11151 ins_encode( pshufd(dst, src, 0xe0)); | |
| 11152 ins_pipe( fpu_reg_reg ); | |
| 11153 %} | |
| 11154 | |
| 11155 // Replicate scalar to packed single precision floating point values in xmm | |
| 11156 instruct Repl2F_regF(regD dst, regF src) %{ | |
| 11157 match(Set dst (Replicate2F src)); | |
| 11158 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %} | |
| 11159 ins_encode( pshufd(dst, src, 0xe0)); | |
| 11160 ins_pipe( fpu_reg_reg ); | |
| 11161 %} | |
| 11162 | |
| 11163 // Replicate scalar to packed single precision floating point values in xmm | |
| 11164 instruct Repl2F_immF0(regD dst, immF0 zero) %{ | |
| 11165 match(Set dst (Replicate2F zero)); | |
| 11166 format %{ "PXOR $dst,$dst\t! replicate2F" %} | |
| 11167 ins_encode( pxor(dst, dst)); | |
| 11168 ins_pipe( fpu_reg_reg ); | |
| 11169 %} | |
| 11170 | |
| 11171 | |
| 11172 // ======================================================================= | |
| 11173 // fast clearing of an array | |
| 11174 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy, | |
| 11175 rFlagsReg cr) | |
| 11176 %{ | |
| 11177 match(Set dummy (ClearArray cnt base)); | |
| 11178 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr); | |
| 11179 | |
| 11180 format %{ "xorl rax, rax\t# ClearArray:\n\t" | |
| 11181 "rep stosq\t# Store rax to *rdi++ while rcx--" %} | |
| 11182 ins_encode(opc_reg_reg(0x33, RAX, RAX), // xorl %eax, %eax | |
| 11183 Opcode(0xF3), Opcode(0x48), Opcode(0xAB)); // rep REX_W stos | |
| 11184 ins_pipe(pipe_slow); | |
| 11185 %} | |
| 11186 | |
| 11187 instruct string_compare(rdi_RegP str1, rsi_RegP str2, rax_RegI tmp1, | |
| 11188 rbx_RegI tmp2, rcx_RegI result, rFlagsReg cr) | |
| 11189 %{ | |
| 11190 match(Set result (StrComp str1 str2)); | |
| 11191 effect(USE_KILL str1, USE_KILL str2, KILL tmp1, KILL tmp2, KILL cr); | |
| 11192 //ins_cost(300); | |
| 11193 | |
| 11194 format %{ "String Compare $str1, $str2 -> $result // XXX KILL RAX, RBX" %} | |
| 11195 ins_encode( enc_String_Compare() ); | |
| 11196 ins_pipe( pipe_slow ); | |
| 11197 %} | |
| 11198 | |
|
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11199 // fast array equals |
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11200 instruct array_equals(rdi_RegP ary1, rsi_RegP ary2, rax_RegI tmp1, |
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11201 rbx_RegI tmp2, rcx_RegI result, rFlagsReg cr) %{ |
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11202 match(Set result (AryEq ary1 ary2)); |
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11203 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL cr); |
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11204 //ins_cost(300); |
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11205 |
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11206 format %{ "Array Equals $ary1,$ary2 -> $result // KILL RAX, RBX" %} |
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11207 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, tmp2, result) ); |
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11208 ins_pipe( pipe_slow ); |
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11209 %} |
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11210 |
| 0 | 11211 //----------Control Flow Instructions------------------------------------------ |
| 11212 // Signed compare Instructions | |
| 11213 | |
| 11214 // XXX more variants!! | |
| 11215 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2) | |
| 11216 %{ | |
| 11217 match(Set cr (CmpI op1 op2)); | |
| 11218 effect(DEF cr, USE op1, USE op2); | |
| 11219 | |
| 11220 format %{ "cmpl $op1, $op2" %} | |
| 11221 opcode(0x3B); /* Opcode 3B /r */ | |
| 11222 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2)); | |
| 11223 ins_pipe(ialu_cr_reg_reg); | |
| 11224 %} | |
| 11225 | |
| 11226 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2) | |
| 11227 %{ | |
| 11228 match(Set cr (CmpI op1 op2)); | |
| 11229 | |
| 11230 format %{ "cmpl $op1, $op2" %} | |
| 11231 opcode(0x81, 0x07); /* Opcode 81 /7 */ | |
| 11232 ins_encode(OpcSErm(op1, op2), Con8or32(op2)); | |
| 11233 ins_pipe(ialu_cr_reg_imm); | |
| 11234 %} | |
| 11235 | |
| 11236 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2) | |
| 11237 %{ | |
| 11238 match(Set cr (CmpI op1 (LoadI op2))); | |
| 11239 | |
| 11240 ins_cost(500); // XXX | |
| 11241 format %{ "cmpl $op1, $op2" %} | |
| 11242 opcode(0x3B); /* Opcode 3B /r */ | |
| 11243 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 11244 ins_pipe(ialu_cr_reg_mem); | |
| 11245 %} | |
| 11246 | |
| 11247 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero) | |
| 11248 %{ | |
| 11249 match(Set cr (CmpI src zero)); | |
| 11250 | |
| 11251 format %{ "testl $src, $src" %} | |
| 11252 opcode(0x85); | |
| 11253 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src)); | |
| 11254 ins_pipe(ialu_cr_reg_imm); | |
| 11255 %} | |
| 11256 | |
| 11257 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero) | |
| 11258 %{ | |
| 11259 match(Set cr (CmpI (AndI src con) zero)); | |
| 11260 | |
| 11261 format %{ "testl $src, $con" %} | |
| 11262 opcode(0xF7, 0x00); | |
| 11263 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con)); | |
| 11264 ins_pipe(ialu_cr_reg_imm); | |
| 11265 %} | |
| 11266 | |
| 11267 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero) | |
| 11268 %{ | |
| 11269 match(Set cr (CmpI (AndI src (LoadI mem)) zero)); | |
| 11270 | |
| 11271 format %{ "testl $src, $mem" %} | |
| 11272 opcode(0x85); | |
| 11273 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
| 11274 ins_pipe(ialu_cr_reg_mem); | |
| 11275 %} | |
| 11276 | |
| 11277 // Unsigned compare Instructions; really, same as signed except they | |
| 11278 // produce an rFlagsRegU instead of rFlagsReg. | |
| 11279 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2) | |
| 11280 %{ | |
| 11281 match(Set cr (CmpU op1 op2)); | |
| 11282 | |
| 11283 format %{ "cmpl $op1, $op2\t# unsigned" %} | |
| 11284 opcode(0x3B); /* Opcode 3B /r */ | |
| 11285 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2)); | |
| 11286 ins_pipe(ialu_cr_reg_reg); | |
| 11287 %} | |
| 11288 | |
| 11289 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2) | |
| 11290 %{ | |
| 11291 match(Set cr (CmpU op1 op2)); | |
| 11292 | |
| 11293 format %{ "cmpl $op1, $op2\t# unsigned" %} | |
| 11294 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 11295 ins_encode(OpcSErm(op1, op2), Con8or32(op2)); | |
| 11296 ins_pipe(ialu_cr_reg_imm); | |
| 11297 %} | |
| 11298 | |
| 11299 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2) | |
| 11300 %{ | |
| 11301 match(Set cr (CmpU op1 (LoadI op2))); | |
| 11302 | |
| 11303 ins_cost(500); // XXX | |
| 11304 format %{ "cmpl $op1, $op2\t# unsigned" %} | |
| 11305 opcode(0x3B); /* Opcode 3B /r */ | |
| 11306 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 11307 ins_pipe(ialu_cr_reg_mem); | |
| 11308 %} | |
| 11309 | |
| 11310 // // // Cisc-spilled version of cmpU_rReg | |
| 11311 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2) | |
| 11312 // //%{ | |
| 11313 // // match(Set cr (CmpU (LoadI op1) op2)); | |
| 11314 // // | |
| 11315 // // format %{ "CMPu $op1,$op2" %} | |
| 11316 // // ins_cost(500); | |
| 11317 // // opcode(0x39); /* Opcode 39 /r */ | |
| 11318 // // ins_encode( OpcP, reg_mem( op1, op2) ); | |
| 11319 // //%} | |
| 11320 | |
| 11321 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero) | |
| 11322 %{ | |
| 11323 match(Set cr (CmpU src zero)); | |
| 11324 | |
| 11325 format %{ "testl $src, $src\t# unsigned" %} | |
| 11326 opcode(0x85); | |
| 11327 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src)); | |
| 11328 ins_pipe(ialu_cr_reg_imm); | |
| 11329 %} | |
| 11330 | |
| 11331 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2) | |
| 11332 %{ | |
| 11333 match(Set cr (CmpP op1 op2)); | |
| 11334 | |
| 11335 format %{ "cmpq $op1, $op2\t# ptr" %} | |
| 11336 opcode(0x3B); /* Opcode 3B /r */ | |
| 11337 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2)); | |
| 11338 ins_pipe(ialu_cr_reg_reg); | |
| 11339 %} | |
| 11340 | |
| 11341 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2) | |
| 11342 %{ | |
| 11343 match(Set cr (CmpP op1 (LoadP op2))); | |
| 11344 | |
| 11345 ins_cost(500); // XXX | |
| 11346 format %{ "cmpq $op1, $op2\t# ptr" %} | |
| 11347 opcode(0x3B); /* Opcode 3B /r */ | |
| 11348 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 11349 ins_pipe(ialu_cr_reg_mem); | |
| 11350 %} | |
| 11351 | |
| 11352 // // // Cisc-spilled version of cmpP_rReg | |
| 11353 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2) | |
| 11354 // //%{ | |
| 11355 // // match(Set cr (CmpP (LoadP op1) op2)); | |
| 11356 // // | |
| 11357 // // format %{ "CMPu $op1,$op2" %} | |
| 11358 // // ins_cost(500); | |
| 11359 // // opcode(0x39); /* Opcode 39 /r */ | |
| 11360 // // ins_encode( OpcP, reg_mem( op1, op2) ); | |
| 11361 // //%} | |
| 11362 | |
| 11363 // XXX this is generalized by compP_rReg_mem??? | |
| 11364 // Compare raw pointer (used in out-of-heap check). | |
| 11365 // Only works because non-oop pointers must be raw pointers | |
| 11366 // and raw pointers have no anti-dependencies. | |
| 11367 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2) | |
| 11368 %{ | |
| 11369 predicate(!n->in(2)->in(2)->bottom_type()->isa_oop_ptr()); | |
| 11370 match(Set cr (CmpP op1 (LoadP op2))); | |
| 11371 | |
| 11372 format %{ "cmpq $op1, $op2\t# raw ptr" %} | |
| 11373 opcode(0x3B); /* Opcode 3B /r */ | |
| 11374 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 11375 ins_pipe(ialu_cr_reg_mem); | |
| 11376 %} | |
| 11377 | |
| 11378 // This will generate a signed flags result. This should be OK since | |
| 11379 // any compare to a zero should be eq/neq. | |
| 11380 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero) | |
| 11381 %{ | |
| 11382 match(Set cr (CmpP src zero)); | |
| 11383 | |
| 11384 format %{ "testq $src, $src\t# ptr" %} | |
| 11385 opcode(0x85); | |
| 11386 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src)); | |
| 11387 ins_pipe(ialu_cr_reg_imm); | |
| 11388 %} | |
| 11389 | |
| 11390 // This will generate a signed flags result. This should be OK since | |
| 11391 // any compare to a zero should be eq/neq. | |
| 11392 instruct testP_reg_mem(rFlagsReg cr, memory op, immP0 zero) | |
| 11393 %{ | |
| 11394 match(Set cr (CmpP (LoadP op) zero)); | |
| 11395 | |
| 11396 ins_cost(500); // XXX | |
| 11397 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %} | |
| 11398 opcode(0xF7); /* Opcode F7 /0 */ | |
| 11399 ins_encode(REX_mem_wide(op), | |
| 11400 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF)); | |
| 11401 ins_pipe(ialu_cr_reg_imm); | |
| 11402 %} | |
| 11403 | |
|
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11404 |
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11405 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2) |
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11406 %{ |
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11407 match(Set cr (CmpN op1 op2)); |
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11408 |
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11409 format %{ "cmpl $op1, $op2\t# compressed ptr" %} |
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11410 ins_encode %{ __ cmpl(as_Register($op1$$reg), as_Register($op2$$reg)); %} |
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11411 ins_pipe(ialu_cr_reg_reg); |
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11412 %} |
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11413 |
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11414 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem) |
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11415 %{ |
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11416 match(Set cr (CmpN src (LoadN mem))); |
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11417 |
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11418 ins_cost(500); // XXX |
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11419 format %{ "cmpl $src, mem\t# compressed ptr" %} |
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11420 ins_encode %{ |
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11421 Address adr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp); |
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11422 __ cmpl(as_Register($src$$reg), adr); |
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11423 %} |
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11424 ins_pipe(ialu_cr_reg_mem); |
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11425 %} |
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|
11426 |
|
113
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11427 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{ |
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11428 match(Set cr (CmpN src zero)); |
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|
11429 |
|
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11430 format %{ "testl $src, $src\t# compressed ptr" %} |
|
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11431 ins_encode %{ __ testl($src$$Register, $src$$Register); %} |
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11432 ins_pipe(ialu_cr_reg_imm); |
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11433 %} |
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|
11434 |
|
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11435 instruct testN_reg_mem(rFlagsReg cr, memory mem, immN0 zero) |
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|
11436 %{ |
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|
11437 match(Set cr (CmpN (LoadN mem) zero)); |
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|
11438 |
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|
11439 ins_cost(500); // XXX |
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|
11440 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %} |
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|
11441 ins_encode %{ |
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11442 Address addr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp); |
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|
11443 __ cmpl(addr, (int)0xFFFFFFFF); |
|
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|
11444 %} |
|
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|
11445 ins_pipe(ialu_cr_reg_mem); |
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|
11446 %} |
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|
11447 |
| 0 | 11448 // Yanked all unsigned pointer compare operations. |
| 11449 // Pointer compares are done with CmpP which is already unsigned. | |
| 11450 | |
| 11451 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2) | |
| 11452 %{ | |
| 11453 match(Set cr (CmpL op1 op2)); | |
| 11454 | |
| 11455 format %{ "cmpq $op1, $op2" %} | |
| 11456 opcode(0x3B); /* Opcode 3B /r */ | |
| 11457 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2)); | |
| 11458 ins_pipe(ialu_cr_reg_reg); | |
| 11459 %} | |
| 11460 | |
| 11461 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2) | |
| 11462 %{ | |
| 11463 match(Set cr (CmpL op1 op2)); | |
| 11464 | |
| 11465 format %{ "cmpq $op1, $op2" %} | |
| 11466 opcode(0x81, 0x07); /* Opcode 81 /7 */ | |
| 11467 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2)); | |
| 11468 ins_pipe(ialu_cr_reg_imm); | |
| 11469 %} | |
| 11470 | |
| 11471 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2) | |
| 11472 %{ | |
| 11473 match(Set cr (CmpL op1 (LoadL op2))); | |
| 11474 | |
| 11475 ins_cost(500); // XXX | |
| 11476 format %{ "cmpq $op1, $op2" %} | |
| 11477 opcode(0x3B); /* Opcode 3B /r */ | |
| 11478 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 11479 ins_pipe(ialu_cr_reg_mem); | |
| 11480 %} | |
| 11481 | |
| 11482 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero) | |
| 11483 %{ | |
| 11484 match(Set cr (CmpL src zero)); | |
| 11485 | |
| 11486 format %{ "testq $src, $src" %} | |
| 11487 opcode(0x85); | |
| 11488 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src)); | |
| 11489 ins_pipe(ialu_cr_reg_imm); | |
| 11490 %} | |
| 11491 | |
| 11492 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero) | |
| 11493 %{ | |
| 11494 match(Set cr (CmpL (AndL src con) zero)); | |
| 11495 | |
| 11496 format %{ "testq $src, $con\t# long" %} | |
| 11497 opcode(0xF7, 0x00); | |
| 11498 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con)); | |
| 11499 ins_pipe(ialu_cr_reg_imm); | |
| 11500 %} | |
| 11501 | |
| 11502 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero) | |
| 11503 %{ | |
| 11504 match(Set cr (CmpL (AndL src (LoadL mem)) zero)); | |
| 11505 | |
| 11506 format %{ "testq $src, $mem" %} | |
| 11507 opcode(0x85); | |
| 11508 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem)); | |
| 11509 ins_pipe(ialu_cr_reg_mem); | |
| 11510 %} | |
| 11511 | |
| 11512 // Manifest a CmpL result in an integer register. Very painful. | |
| 11513 // This is the test to avoid. | |
| 11514 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags) | |
| 11515 %{ | |
| 11516 match(Set dst (CmpL3 src1 src2)); | |
| 11517 effect(KILL flags); | |
| 11518 | |
| 11519 ins_cost(275); // XXX | |
| 11520 format %{ "cmpq $src1, $src2\t# CmpL3\n\t" | |
| 11521 "movl $dst, -1\n\t" | |
| 11522 "jl,s done\n\t" | |
| 11523 "setne $dst\n\t" | |
| 11524 "movzbl $dst, $dst\n\t" | |
| 11525 "done:" %} | |
| 11526 ins_encode(cmpl3_flag(src1, src2, dst)); | |
| 11527 ins_pipe(pipe_slow); | |
| 11528 %} | |
| 11529 | |
| 11530 //----------Max and Min-------------------------------------------------------- | |
| 11531 // Min Instructions | |
| 11532 | |
| 11533 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr) | |
| 11534 %{ | |
| 11535 effect(USE_DEF dst, USE src, USE cr); | |
| 11536 | |
| 11537 format %{ "cmovlgt $dst, $src\t# min" %} | |
| 11538 opcode(0x0F, 0x4F); | |
| 11539 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 11540 ins_pipe(pipe_cmov_reg); | |
| 11541 %} | |
| 11542 | |
| 11543 | |
| 11544 instruct minI_rReg(rRegI dst, rRegI src) | |
| 11545 %{ | |
| 11546 match(Set dst (MinI dst src)); | |
| 11547 | |
| 11548 ins_cost(200); | |
| 11549 expand %{ | |
| 11550 rFlagsReg cr; | |
| 11551 compI_rReg(cr, dst, src); | |
| 11552 cmovI_reg_g(dst, src, cr); | |
| 11553 %} | |
| 11554 %} | |
| 11555 | |
| 11556 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr) | |
| 11557 %{ | |
| 11558 effect(USE_DEF dst, USE src, USE cr); | |
| 11559 | |
| 11560 format %{ "cmovllt $dst, $src\t# max" %} | |
| 11561 opcode(0x0F, 0x4C); | |
| 11562 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 11563 ins_pipe(pipe_cmov_reg); | |
| 11564 %} | |
| 11565 | |
| 11566 | |
| 11567 instruct maxI_rReg(rRegI dst, rRegI src) | |
| 11568 %{ | |
| 11569 match(Set dst (MaxI dst src)); | |
| 11570 | |
| 11571 ins_cost(200); | |
| 11572 expand %{ | |
| 11573 rFlagsReg cr; | |
| 11574 compI_rReg(cr, dst, src); | |
| 11575 cmovI_reg_l(dst, src, cr); | |
| 11576 %} | |
| 11577 %} | |
| 11578 | |
| 11579 // ============================================================================ | |
| 11580 // Branch Instructions | |
| 11581 | |
| 11582 // Jump Direct - Label defines a relative address from JMP+1 | |
| 11583 instruct jmpDir(label labl) | |
| 11584 %{ | |
| 11585 match(Goto); | |
| 11586 effect(USE labl); | |
| 11587 | |
| 11588 ins_cost(300); | |
| 11589 format %{ "jmp $labl" %} | |
| 11590 size(5); | |
| 11591 opcode(0xE9); | |
| 11592 ins_encode(OpcP, Lbl(labl)); | |
| 11593 ins_pipe(pipe_jmp); | |
| 11594 ins_pc_relative(1); | |
| 11595 %} | |
| 11596 | |
| 11597 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 11598 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl) | |
| 11599 %{ | |
| 11600 match(If cop cr); | |
| 11601 effect(USE labl); | |
| 11602 | |
| 11603 ins_cost(300); | |
| 11604 format %{ "j$cop $labl" %} | |
| 11605 size(6); | |
| 11606 opcode(0x0F, 0x80); | |
| 11607 ins_encode(Jcc(cop, labl)); | |
| 11608 ins_pipe(pipe_jcc); | |
| 11609 ins_pc_relative(1); | |
| 11610 %} | |
| 11611 | |
| 11612 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 11613 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl) | |
| 11614 %{ | |
| 11615 match(CountedLoopEnd cop cr); | |
| 11616 effect(USE labl); | |
| 11617 | |
| 11618 ins_cost(300); | |
| 11619 format %{ "j$cop $labl\t# loop end" %} | |
| 11620 size(6); | |
| 11621 opcode(0x0F, 0x80); | |
| 11622 ins_encode(Jcc(cop, labl)); | |
| 11623 ins_pipe(pipe_jcc); | |
| 11624 ins_pc_relative(1); | |
| 11625 %} | |
| 11626 | |
| 11627 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
|
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|
11628 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
| 0 | 11629 match(CountedLoopEnd cop cmp); |
| 11630 effect(USE labl); | |
| 11631 | |
| 11632 ins_cost(300); | |
| 11633 format %{ "j$cop,u $labl\t# loop end" %} | |
| 11634 size(6); | |
| 11635 opcode(0x0F, 0x80); | |
| 11636 ins_encode(Jcc(cop, labl)); | |
| 11637 ins_pipe(pipe_jcc); | |
| 11638 ins_pc_relative(1); | |
| 11639 %} | |
| 11640 | |
|
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|
11641 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
|
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|
11642 match(CountedLoopEnd cop cmp); |
|
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|
11643 effect(USE labl); |
|
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|
11644 |
|
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|
11645 ins_cost(200); |
|
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|
11646 format %{ "j$cop,u $labl\t# loop end" %} |
|
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|
11647 size(6); |
|
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|
11648 opcode(0x0F, 0x80); |
|
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|
11649 ins_encode(Jcc(cop, labl)); |
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|
11650 ins_pipe(pipe_jcc); |
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|
11651 ins_pc_relative(1); |
|
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|
11652 %} |
|
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|
11653 |
| 0 | 11654 // Jump Direct Conditional - using unsigned comparison |
|
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|
11655 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
| 0 | 11656 match(If cop cmp); |
| 11657 effect(USE labl); | |
| 11658 | |
| 11659 ins_cost(300); | |
|
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|
11660 format %{ "j$cop,u $labl" %} |
|
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|
11661 size(6); |
|
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|
11662 opcode(0x0F, 0x80); |
|
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|
11663 ins_encode(Jcc(cop, labl)); |
|
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|
11664 ins_pipe(pipe_jcc); |
|
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|
11665 ins_pc_relative(1); |
|
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|
11666 %} |
|
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changeset
|
11667 |
|
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|
11668 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
|
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|
11669 match(If cop cmp); |
|
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|
11670 effect(USE labl); |
|
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changeset
|
11671 |
|
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|
11672 ins_cost(200); |
|
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|
11673 format %{ "j$cop,u $labl" %} |
| 0 | 11674 size(6); |
| 11675 opcode(0x0F, 0x80); | |
| 11676 ins_encode(Jcc(cop, labl)); | |
| 11677 ins_pipe(pipe_jcc); | |
| 11678 ins_pc_relative(1); | |
| 11679 %} | |
| 11680 | |
|
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|
11681 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{ |
|
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diff
changeset
|
11682 match(If cop cmp); |
|
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diff
changeset
|
11683 effect(USE labl); |
|
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diff
changeset
|
11684 |
|
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changeset
|
11685 ins_cost(200); |
|
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|
11686 format %{ $$template |
|
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|
11687 if ($cop$$cmpcode == Assembler::notEqual) { |
|
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11688 $$emit$$"jp,u $labl\n\t" |
|
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11689 $$emit$$"j$cop,u $labl" |
|
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|
11690 } else { |
|
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|
11691 $$emit$$"jp,u done\n\t" |
|
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11692 $$emit$$"j$cop,u $labl\n\t" |
|
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11693 $$emit$$"done:" |
|
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|
11694 } |
|
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|
11695 %} |
|
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|
11696 size(12); |
|
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|
11697 opcode(0x0F, 0x80); |
|
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|
11698 ins_encode %{ |
|
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|
11699 Label* l = $labl$$label; |
|
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11700 $$$emit8$primary; |
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11701 emit_cc(cbuf, $secondary, Assembler::parity); |
|
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11702 int parity_disp = -1; |
|
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11703 if ($cop$$cmpcode == Assembler::notEqual) { |
|
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11704 // the two jumps 6 bytes apart so the jump distances are too |
|
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11705 parity_disp = l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0; |
|
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|
11706 } else if ($cop$$cmpcode == Assembler::equal) { |
|
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11707 parity_disp = 6; |
|
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|
11708 } else { |
|
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|
11709 ShouldNotReachHere(); |
|
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|
11710 } |
|
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|
11711 emit_d32(cbuf, parity_disp); |
|
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11712 $$$emit8$primary; |
|
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11713 emit_cc(cbuf, $secondary, $cop$$cmpcode); |
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11714 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0; |
|
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11715 emit_d32(cbuf, disp); |
|
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|
11716 %} |
|
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|
11717 ins_pipe(pipe_jcc); |
|
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11718 ins_pc_relative(1); |
|
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11719 %} |
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|
11720 |
| 0 | 11721 // ============================================================================ |
| 11722 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary | |
| 11723 // superklass array for an instance of the superklass. Set a hidden | |
| 11724 // internal cache on a hit (cache is checked with exposed code in | |
| 11725 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The | |
| 11726 // encoding ALSO sets flags. | |
| 11727 | |
| 11728 instruct partialSubtypeCheck(rdi_RegP result, | |
| 11729 rsi_RegP sub, rax_RegP super, rcx_RegI rcx, | |
| 11730 rFlagsReg cr) | |
| 11731 %{ | |
| 11732 match(Set result (PartialSubtypeCheck sub super)); | |
| 11733 effect(KILL rcx, KILL cr); | |
| 11734 | |
| 11735 ins_cost(1100); // slightly larger than the next version | |
| 11736 format %{ "cmpq rax, rsi\n\t" | |
| 11737 "jeq,s hit\n\t" | |
| 11738 "movq rdi, [$sub + (sizeof(oopDesc) + Klass::secondary_supers_offset_in_bytes())]\n\t" | |
| 11739 "movl rcx, [rdi + arrayOopDesc::length_offset_in_bytes()]\t# length to scan\n\t" | |
| 11740 "addq rdi, arrayOopDex::base_offset_in_bytes(T_OBJECT)\t# Skip to start of data; set NZ in case count is zero\n\t" | |
| 11741 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t" | |
| 11742 "jne,s miss\t\t# Missed: rdi not-zero\n\t" | |
| 11743 "movq [$sub + (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes())], $super\t# Hit: update cache\n\t" | |
| 11744 "hit:\n\t" | |
| 11745 "xorq $result, $result\t\t Hit: rdi zero\n\t" | |
| 11746 "miss:\t" %} | |
| 11747 | |
| 11748 opcode(0x1); // Force a XOR of RDI | |
| 11749 ins_encode(enc_PartialSubtypeCheck()); | |
| 11750 ins_pipe(pipe_slow); | |
| 11751 %} | |
| 11752 | |
| 11753 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr, | |
| 11754 rsi_RegP sub, rax_RegP super, rcx_RegI rcx, | |
| 11755 immP0 zero, | |
| 11756 rdi_RegP result) | |
| 11757 %{ | |
| 11758 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero)); | |
|
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|
11759 predicate(!UseCompressedOops); // decoding oop kills condition codes |
| 0 | 11760 effect(KILL rcx, KILL result); |
| 11761 | |
| 11762 ins_cost(1000); | |
| 11763 format %{ "cmpq rax, rsi\n\t" | |
| 11764 "jeq,s miss\t# Actually a hit; we are done.\n\t" | |
| 11765 "movq rdi, [$sub + (sizeof(oopDesc) + Klass::secondary_supers_offset_in_bytes())]\n\t" | |
| 11766 "movl rcx, [rdi + arrayOopDesc::length_offset_in_bytes()]\t# length to scan\n\t" | |
| 11767 "addq rdi, arrayOopDex::base_offset_in_bytes(T_OBJECT)\t# Skip to start of data; set NZ in case count is zero\n\t" | |
| 11768 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t" | |
| 11769 "jne,s miss\t\t# Missed: flags nz\n\t" | |
| 11770 "movq [$sub + (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes())], $super\t# Hit: update cache\n\t" | |
| 11771 "miss:\t" %} | |
| 11772 | |
| 11773 opcode(0x0); // No need to XOR RDI | |
| 11774 ins_encode(enc_PartialSubtypeCheck()); | |
| 11775 ins_pipe(pipe_slow); | |
| 11776 %} | |
| 11777 | |
| 11778 // ============================================================================ | |
| 11779 // Branch Instructions -- short offset versions | |
| 11780 // | |
| 11781 // These instructions are used to replace jumps of a long offset (the default | |
| 11782 // match) with jumps of a shorter offset. These instructions are all tagged | |
| 11783 // with the ins_short_branch attribute, which causes the ADLC to suppress the | |
| 11784 // match rules in general matching. Instead, the ADLC generates a conversion | |
| 11785 // method in the MachNode which can be used to do in-place replacement of the | |
| 11786 // long variant with the shorter variant. The compiler will determine if a | |
| 11787 // branch can be taken by the is_short_branch_offset() predicate in the machine | |
| 11788 // specific code section of the file. | |
| 11789 | |
| 11790 // Jump Direct - Label defines a relative address from JMP+1 | |
|
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|
11791 instruct jmpDir_short(label labl) %{ |
| 0 | 11792 match(Goto); |
| 11793 effect(USE labl); | |
| 11794 | |
| 11795 ins_cost(300); | |
| 11796 format %{ "jmp,s $labl" %} | |
| 11797 size(2); | |
| 11798 opcode(0xEB); | |
| 11799 ins_encode(OpcP, LblShort(labl)); | |
| 11800 ins_pipe(pipe_jmp); | |
| 11801 ins_pc_relative(1); | |
| 11802 ins_short_branch(1); | |
| 11803 %} | |
| 11804 | |
| 11805 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
|
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|
11806 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{ |
| 0 | 11807 match(If cop cr); |
| 11808 effect(USE labl); | |
| 11809 | |
| 11810 ins_cost(300); | |
| 11811 format %{ "j$cop,s $labl" %} | |
| 11812 size(2); | |
| 11813 opcode(0x70); | |
| 11814 ins_encode(JccShort(cop, labl)); | |
| 11815 ins_pipe(pipe_jcc); | |
| 11816 ins_pc_relative(1); | |
| 11817 ins_short_branch(1); | |
| 11818 %} | |
| 11819 | |
| 11820 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
|
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|
11821 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{ |
| 0 | 11822 match(CountedLoopEnd cop cr); |
| 11823 effect(USE labl); | |
| 11824 | |
| 11825 ins_cost(300); | |
|
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|
11826 format %{ "j$cop,s $labl\t# loop end" %} |
| 0 | 11827 size(2); |
| 11828 opcode(0x70); | |
| 11829 ins_encode(JccShort(cop, labl)); | |
| 11830 ins_pipe(pipe_jcc); | |
| 11831 ins_pc_relative(1); | |
| 11832 ins_short_branch(1); | |
| 11833 %} | |
| 11834 | |
| 11835 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
|
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|
11836 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
|
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|
11837 match(CountedLoopEnd cop cmp); |
|
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|
11838 effect(USE labl); |
|
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|
11839 |
|
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|
11840 ins_cost(300); |
|
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|
11841 format %{ "j$cop,us $labl\t# loop end" %} |
|
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|
11842 size(2); |
|
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|
11843 opcode(0x70); |
|
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|
11844 ins_encode(JccShort(cop, labl)); |
|
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|
11845 ins_pipe(pipe_jcc); |
|
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|
11846 ins_pc_relative(1); |
|
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|
11847 ins_short_branch(1); |
|
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|
11848 %} |
|
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|
11849 |
|
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|
11850 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
| 0 | 11851 match(CountedLoopEnd cop cmp); |
| 11852 effect(USE labl); | |
| 11853 | |
| 11854 ins_cost(300); | |
|
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|
11855 format %{ "j$cop,us $labl\t# loop end" %} |
|
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403
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|
11856 size(2); |
|
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|
11857 opcode(0x70); |
|
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|
11858 ins_encode(JccShort(cop, labl)); |
|
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|
11859 ins_pipe(pipe_jcc); |
|
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|
11860 ins_pc_relative(1); |
|
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|
11861 ins_short_branch(1); |
|
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|
11862 %} |
|
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|
11863 |
|
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|
11864 // Jump Direct Conditional - using unsigned comparison |
|
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|
11865 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
|
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|
11866 match(If cop cmp); |
|
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|
11867 effect(USE labl); |
|
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|
11868 |
|
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|
11869 ins_cost(300); |
| 0 | 11870 format %{ "j$cop,us $labl" %} |
| 11871 size(2); | |
| 11872 opcode(0x70); | |
| 11873 ins_encode(JccShort(cop, labl)); | |
| 11874 ins_pipe(pipe_jcc); | |
| 11875 ins_pc_relative(1); | |
| 11876 ins_short_branch(1); | |
| 11877 %} | |
| 11878 | |
|
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|
11879 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
| 0 | 11880 match(If cop cmp); |
| 11881 effect(USE labl); | |
| 11882 | |
| 11883 ins_cost(300); | |
| 11884 format %{ "j$cop,us $labl" %} | |
| 11885 size(2); | |
| 11886 opcode(0x70); | |
| 11887 ins_encode(JccShort(cop, labl)); | |
| 11888 ins_pipe(pipe_jcc); | |
| 11889 ins_pc_relative(1); | |
| 11890 ins_short_branch(1); | |
| 11891 %} | |
| 11892 | |
|
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|
11893 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{ |
|
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|
11894 match(If cop cmp); |
|
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|
11895 effect(USE labl); |
|
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|
11896 |
|
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|
11897 ins_cost(300); |
|
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|
11898 format %{ $$template |
|
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|
11899 if ($cop$$cmpcode == Assembler::notEqual) { |
|
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|
11900 $$emit$$"jp,u,s $labl\n\t" |
|
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|
11901 $$emit$$"j$cop,u,s $labl" |
|
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|
11902 } else { |
|
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|
11903 $$emit$$"jp,u,s done\n\t" |
|
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11904 $$emit$$"j$cop,u,s $labl\n\t" |
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11905 $$emit$$"done:" |
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11906 } |
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11907 %} |
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11908 size(4); |
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11909 opcode(0x70); |
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11910 ins_encode %{ |
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11911 Label* l = $labl$$label; |
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11912 emit_cc(cbuf, $primary, Assembler::parity); |
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11913 int parity_disp = -1; |
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11914 if ($cop$$cmpcode == Assembler::notEqual) { |
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11915 parity_disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0; |
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11916 } else if ($cop$$cmpcode == Assembler::equal) { |
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11917 parity_disp = 2; |
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11918 } else { |
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11919 ShouldNotReachHere(); |
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11920 } |
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11921 emit_d8(cbuf, parity_disp); |
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11922 emit_cc(cbuf, $primary, $cop$$cmpcode); |
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11923 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0; |
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11924 emit_d8(cbuf, disp); |
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11925 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp"); |
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11926 assert(-128 <= parity_disp && parity_disp <= 127, "Displacement too large for short jmp"); |
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11927 %} |
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11928 ins_pipe(pipe_jcc); |
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11929 ins_pc_relative(1); |
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11930 ins_short_branch(1); |
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11931 %} |
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11932 |
| 0 | 11933 // ============================================================================ |
| 11934 // inlined locking and unlocking | |
| 11935 | |
| 11936 instruct cmpFastLock(rFlagsReg cr, | |
| 11937 rRegP object, rRegP box, rax_RegI tmp, rRegP scr) | |
| 11938 %{ | |
| 11939 match(Set cr (FastLock object box)); | |
| 11940 effect(TEMP tmp, TEMP scr); | |
| 11941 | |
| 11942 ins_cost(300); | |
| 11943 format %{ "fastlock $object,$box,$tmp,$scr" %} | |
| 11944 ins_encode(Fast_Lock(object, box, tmp, scr)); | |
| 11945 ins_pipe(pipe_slow); | |
| 11946 ins_pc_relative(1); | |
| 11947 %} | |
| 11948 | |
| 11949 instruct cmpFastUnlock(rFlagsReg cr, | |
| 11950 rRegP object, rax_RegP box, rRegP tmp) | |
| 11951 %{ | |
| 11952 match(Set cr (FastUnlock object box)); | |
| 11953 effect(TEMP tmp); | |
| 11954 | |
| 11955 ins_cost(300); | |
| 11956 format %{ "fastunlock $object, $box, $tmp" %} | |
| 11957 ins_encode(Fast_Unlock(object, box, tmp)); | |
| 11958 ins_pipe(pipe_slow); | |
| 11959 ins_pc_relative(1); | |
| 11960 %} | |
| 11961 | |
| 11962 | |
| 11963 // ============================================================================ | |
| 11964 // Safepoint Instructions | |
| 11965 instruct safePoint_poll(rFlagsReg cr) | |
| 11966 %{ | |
| 11967 match(SafePoint); | |
| 11968 effect(KILL cr); | |
| 11969 | |
| 11970 format %{ "testl rax, [rip + #offset_to_poll_page]\t" | |
| 11971 "# Safepoint: poll for GC" %} | |
| 11972 size(6); // Opcode + ModRM + Disp32 == 6 bytes | |
| 11973 ins_cost(125); | |
| 11974 ins_encode(enc_safepoint_poll); | |
| 11975 ins_pipe(ialu_reg_mem); | |
| 11976 %} | |
| 11977 | |
| 11978 // ============================================================================ | |
| 11979 // Procedure Call/Return Instructions | |
| 11980 // Call Java Static Instruction | |
| 11981 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 11982 // compute_padding() functions will have to be adjusted. | |
| 11983 instruct CallStaticJavaDirect(method meth) | |
| 11984 %{ | |
| 11985 match(CallStaticJava); | |
| 11986 effect(USE meth); | |
| 11987 | |
| 11988 ins_cost(300); | |
| 11989 format %{ "call,static " %} | |
| 11990 opcode(0xE8); /* E8 cd */ | |
| 11991 ins_encode(Java_Static_Call(meth), call_epilog); | |
| 11992 ins_pipe(pipe_slow); | |
| 11993 ins_pc_relative(1); | |
| 11994 ins_alignment(4); | |
| 11995 %} | |
| 11996 | |
| 11997 // Call Java Dynamic Instruction | |
| 11998 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 11999 // compute_padding() functions will have to be adjusted. | |
| 12000 instruct CallDynamicJavaDirect(method meth) | |
| 12001 %{ | |
| 12002 match(CallDynamicJava); | |
| 12003 effect(USE meth); | |
| 12004 | |
| 12005 ins_cost(300); | |
| 12006 format %{ "movq rax, #Universe::non_oop_word()\n\t" | |
| 12007 "call,dynamic " %} | |
| 12008 opcode(0xE8); /* E8 cd */ | |
| 12009 ins_encode(Java_Dynamic_Call(meth), call_epilog); | |
| 12010 ins_pipe(pipe_slow); | |
| 12011 ins_pc_relative(1); | |
| 12012 ins_alignment(4); | |
| 12013 %} | |
| 12014 | |
| 12015 // Call Runtime Instruction | |
| 12016 instruct CallRuntimeDirect(method meth) | |
| 12017 %{ | |
| 12018 match(CallRuntime); | |
| 12019 effect(USE meth); | |
| 12020 | |
| 12021 ins_cost(300); | |
| 12022 format %{ "call,runtime " %} | |
| 12023 opcode(0xE8); /* E8 cd */ | |
| 12024 ins_encode(Java_To_Runtime(meth)); | |
| 12025 ins_pipe(pipe_slow); | |
| 12026 ins_pc_relative(1); | |
| 12027 %} | |
| 12028 | |
| 12029 // Call runtime without safepoint | |
| 12030 instruct CallLeafDirect(method meth) | |
| 12031 %{ | |
| 12032 match(CallLeaf); | |
| 12033 effect(USE meth); | |
| 12034 | |
| 12035 ins_cost(300); | |
| 12036 format %{ "call_leaf,runtime " %} | |
| 12037 opcode(0xE8); /* E8 cd */ | |
| 12038 ins_encode(Java_To_Runtime(meth)); | |
| 12039 ins_pipe(pipe_slow); | |
| 12040 ins_pc_relative(1); | |
| 12041 %} | |
| 12042 | |
| 12043 // Call runtime without safepoint | |
| 12044 instruct CallLeafNoFPDirect(method meth) | |
| 12045 %{ | |
| 12046 match(CallLeafNoFP); | |
| 12047 effect(USE meth); | |
| 12048 | |
| 12049 ins_cost(300); | |
| 12050 format %{ "call_leaf_nofp,runtime " %} | |
| 12051 opcode(0xE8); /* E8 cd */ | |
| 12052 ins_encode(Java_To_Runtime(meth)); | |
| 12053 ins_pipe(pipe_slow); | |
| 12054 ins_pc_relative(1); | |
| 12055 %} | |
| 12056 | |
| 12057 // Return Instruction | |
| 12058 // Remove the return address & jump to it. | |
| 12059 // Notice: We always emit a nop after a ret to make sure there is room | |
| 12060 // for safepoint patching | |
| 12061 instruct Ret() | |
| 12062 %{ | |
| 12063 match(Return); | |
| 12064 | |
| 12065 format %{ "ret" %} | |
| 12066 opcode(0xC3); | |
| 12067 ins_encode(OpcP); | |
| 12068 ins_pipe(pipe_jmp); | |
| 12069 %} | |
| 12070 | |
| 12071 // Tail Call; Jump from runtime stub to Java code. | |
| 12072 // Also known as an 'interprocedural jump'. | |
| 12073 // Target of jump will eventually return to caller. | |
| 12074 // TailJump below removes the return address. | |
| 12075 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop) | |
| 12076 %{ | |
| 12077 match(TailCall jump_target method_oop); | |
| 12078 | |
| 12079 ins_cost(300); | |
| 12080 format %{ "jmp $jump_target\t# rbx holds method oop" %} | |
| 12081 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 12082 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target)); | |
| 12083 ins_pipe(pipe_jmp); | |
| 12084 %} | |
| 12085 | |
| 12086 // Tail Jump; remove the return address; jump to target. | |
| 12087 // TailCall above leaves the return address around. | |
| 12088 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop) | |
| 12089 %{ | |
| 12090 match(TailJump jump_target ex_oop); | |
| 12091 | |
| 12092 ins_cost(300); | |
| 12093 format %{ "popq rdx\t# pop return address\n\t" | |
| 12094 "jmp $jump_target" %} | |
| 12095 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 12096 ins_encode(Opcode(0x5a), // popq rdx | |
| 12097 REX_reg(jump_target), OpcP, reg_opc(jump_target)); | |
| 12098 ins_pipe(pipe_jmp); | |
| 12099 %} | |
| 12100 | |
| 12101 // Create exception oop: created by stack-crawling runtime code. | |
| 12102 // Created exception is now available to this handler, and is setup | |
| 12103 // just prior to jumping to this handler. No code emitted. | |
| 12104 instruct CreateException(rax_RegP ex_oop) | |
| 12105 %{ | |
| 12106 match(Set ex_oop (CreateEx)); | |
| 12107 | |
| 12108 size(0); | |
| 12109 // use the following format syntax | |
| 12110 format %{ "# exception oop is in rax; no code emitted" %} | |
| 12111 ins_encode(); | |
| 12112 ins_pipe(empty); | |
| 12113 %} | |
| 12114 | |
| 12115 // Rethrow exception: | |
| 12116 // The exception oop will come in the first argument position. | |
| 12117 // Then JUMP (not call) to the rethrow stub code. | |
| 12118 instruct RethrowException() | |
| 12119 %{ | |
| 12120 match(Rethrow); | |
| 12121 | |
| 12122 // use the following format syntax | |
| 12123 format %{ "jmp rethrow_stub" %} | |
| 12124 ins_encode(enc_rethrow); | |
| 12125 ins_pipe(pipe_jmp); | |
| 12126 %} | |
| 12127 | |
| 12128 | |
| 12129 //----------PEEPHOLE RULES----------------------------------------------------- | |
| 12130 // These must follow all instruction definitions as they use the names | |
| 12131 // defined in the instructions definitions. | |
| 12132 // | |
| 605 | 12133 // peepmatch ( root_instr_name [preceding_instruction]* ); |
| 0 | 12134 // |
| 12135 // peepconstraint %{ | |
| 12136 // (instruction_number.operand_name relational_op instruction_number.operand_name | |
| 12137 // [, ...] ); | |
| 12138 // // instruction numbers are zero-based using left to right order in peepmatch | |
| 12139 // | |
| 12140 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); | |
| 12141 // // provide an instruction_number.operand_name for each operand that appears | |
| 12142 // // in the replacement instruction's match rule | |
| 12143 // | |
| 12144 // ---------VM FLAGS--------------------------------------------------------- | |
| 12145 // | |
| 12146 // All peephole optimizations can be turned off using -XX:-OptoPeephole | |
| 12147 // | |
| 12148 // Each peephole rule is given an identifying number starting with zero and | |
| 12149 // increasing by one in the order seen by the parser. An individual peephole | |
| 12150 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# | |
| 12151 // on the command-line. | |
| 12152 // | |
| 12153 // ---------CURRENT LIMITATIONS---------------------------------------------- | |
| 12154 // | |
| 12155 // Only match adjacent instructions in same basic block | |
| 12156 // Only equality constraints | |
| 12157 // Only constraints between operands, not (0.dest_reg == RAX_enc) | |
| 12158 // Only one replacement instruction | |
| 12159 // | |
| 12160 // ---------EXAMPLE---------------------------------------------------------- | |
| 12161 // | |
| 12162 // // pertinent parts of existing instructions in architecture description | |
| 12163 // instruct movI(rRegI dst, rRegI src) | |
| 12164 // %{ | |
| 12165 // match(Set dst (CopyI src)); | |
| 12166 // %} | |
| 12167 // | |
| 12168 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr) | |
| 12169 // %{ | |
| 12170 // match(Set dst (AddI dst src)); | |
| 12171 // effect(KILL cr); | |
| 12172 // %} | |
| 12173 // | |
| 12174 // // Change (inc mov) to lea | |
| 12175 // peephole %{ | |
| 12176 // // increment preceeded by register-register move | |
| 12177 // peepmatch ( incI_rReg movI ); | |
| 12178 // // require that the destination register of the increment | |
| 12179 // // match the destination register of the move | |
| 12180 // peepconstraint ( 0.dst == 1.dst ); | |
| 12181 // // construct a replacement instruction that sets | |
| 12182 // // the destination to ( move's source register + one ) | |
| 12183 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) ); | |
| 12184 // %} | |
| 12185 // | |
| 12186 | |
| 12187 // Implementation no longer uses movX instructions since | |
| 12188 // machine-independent system no longer uses CopyX nodes. | |
| 12189 // | |
| 12190 // peephole | |
| 12191 // %{ | |
| 12192 // peepmatch (incI_rReg movI); | |
| 12193 // peepconstraint (0.dst == 1.dst); | |
| 12194 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src)); | |
| 12195 // %} | |
| 12196 | |
| 12197 // peephole | |
| 12198 // %{ | |
| 12199 // peepmatch (decI_rReg movI); | |
| 12200 // peepconstraint (0.dst == 1.dst); | |
| 12201 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src)); | |
| 12202 // %} | |
| 12203 | |
| 12204 // peephole | |
| 12205 // %{ | |
| 12206 // peepmatch (addI_rReg_imm movI); | |
| 12207 // peepconstraint (0.dst == 1.dst); | |
| 12208 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src)); | |
| 12209 // %} | |
| 12210 | |
| 12211 // peephole | |
| 12212 // %{ | |
| 12213 // peepmatch (incL_rReg movL); | |
| 12214 // peepconstraint (0.dst == 1.dst); | |
| 12215 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src)); | |
| 12216 // %} | |
| 12217 | |
| 12218 // peephole | |
| 12219 // %{ | |
| 12220 // peepmatch (decL_rReg movL); | |
| 12221 // peepconstraint (0.dst == 1.dst); | |
| 12222 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src)); | |
| 12223 // %} | |
| 12224 | |
| 12225 // peephole | |
| 12226 // %{ | |
| 12227 // peepmatch (addL_rReg_imm movL); | |
| 12228 // peepconstraint (0.dst == 1.dst); | |
| 12229 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src)); | |
| 12230 // %} | |
| 12231 | |
| 12232 // peephole | |
| 12233 // %{ | |
| 12234 // peepmatch (addP_rReg_imm movP); | |
| 12235 // peepconstraint (0.dst == 1.dst); | |
| 12236 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src)); | |
| 12237 // %} | |
| 12238 | |
| 12239 // // Change load of spilled value to only a spill | |
| 12240 // instruct storeI(memory mem, rRegI src) | |
| 12241 // %{ | |
| 12242 // match(Set mem (StoreI mem src)); | |
| 12243 // %} | |
| 12244 // | |
| 12245 // instruct loadI(rRegI dst, memory mem) | |
| 12246 // %{ | |
| 12247 // match(Set dst (LoadI mem)); | |
| 12248 // %} | |
| 12249 // | |
| 12250 | |
| 12251 peephole | |
| 12252 %{ | |
| 12253 peepmatch (loadI storeI); | |
| 12254 peepconstraint (1.src == 0.dst, 1.mem == 0.mem); | |
| 12255 peepreplace (storeI(1.mem 1.mem 1.src)); | |
| 12256 %} | |
| 12257 | |
| 12258 peephole | |
| 12259 %{ | |
| 12260 peepmatch (loadL storeL); | |
| 12261 peepconstraint (1.src == 0.dst, 1.mem == 0.mem); | |
| 12262 peepreplace (storeL(1.mem 1.mem 1.src)); | |
| 12263 %} | |
| 12264 | |
| 12265 //----------SMARTSPILL RULES--------------------------------------------------- | |
| 12266 // These must follow all instruction definitions as they use the names | |
| 12267 // defined in the instructions definitions. |