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6797305: Add LoadUB and LoadUI opcode class Summary: Add a LoadUB (unsigned byte) and LoadUI (unsigned int) opcode class so we have these load optimizations in the first place and do not need to handle them in the matcher. Reviewed-by: never, kvn
author twisti
date Mon, 09 Mar 2009 03:17:11 -0700
parents 56aae7be60d4
children 7bb995fbd3c0 660978a2a31a
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623:9adddb8c0fc8 624:337400e7a5dd
1 // 1 //
2 // Copyright 2003-2008 Sun Microsystems, Inc. All Rights Reserved. 2 // Copyright 2003-2009 Sun Microsystems, Inc. All Rights Reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 // 4 //
5 // This code is free software; you can redistribute it and/or modify it 5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as 6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation. 7 // published by the Free Software Foundation.
3460 %} 3460 %}
3461 3461
3462 3462
3463 enc_class movq_ld(regD dst, memory mem) %{ 3463 enc_class movq_ld(regD dst, memory mem) %{
3464 MacroAssembler _masm(&cbuf); 3464 MacroAssembler _masm(&cbuf);
3465 Address madr = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp); 3465 __ movq($dst$$XMMRegister, $mem$$Address);
3466 __ movq(as_XMMRegister($dst$$reg), madr);
3467 %} 3466 %}
3468 3467
3469 enc_class movq_st(memory mem, regD src) %{ 3468 enc_class movq_st(memory mem, regD src) %{
3470 MacroAssembler _masm(&cbuf); 3469 MacroAssembler _masm(&cbuf);
3471 Address madr = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp); 3470 __ movq($mem$$Address, $src$$XMMRegister);
3472 __ movq(madr, as_XMMRegister($src$$reg));
3473 %} 3471 %}
3474 3472
3475 enc_class pshufd_8x8(regF dst, regF src) %{ 3473 enc_class pshufd_8x8(regF dst, regF src) %{
3476 MacroAssembler _masm(&cbuf); 3474 MacroAssembler _masm(&cbuf);
3477 3475
6029 %{ 6027 %{
6030 match(Set dst (LoadB mem)); 6028 match(Set dst (LoadB mem));
6031 6029
6032 ins_cost(125); 6030 ins_cost(125);
6033 format %{ "movsbl $dst, $mem\t# byte" %} 6031 format %{ "movsbl $dst, $mem\t# byte" %}
6034 opcode(0x0F, 0xBE); 6032
6035 ins_encode(REX_reg_mem(dst, mem), OpcP, OpcS, reg_mem(dst, mem)); 6033 ins_encode %{
6034 __ movsbl($dst$$Register, $mem$$Address);
6035 %}
6036
6036 ins_pipe(ialu_reg_mem); 6037 ins_pipe(ialu_reg_mem);
6037 %} 6038 %}
6038 6039
6039 // Load Byte (8 bit signed) into long 6040 // Load Byte (8 bit signed) into Long Register
6040 // instruct loadB2L(rRegL dst, memory mem) 6041 instruct loadB2L(rRegL dst, memory mem)
6041 // %{ 6042 %{
6042 // match(Set dst (ConvI2L (LoadB mem))); 6043 match(Set dst (ConvI2L (LoadB mem)));
6043 6044
6044 // ins_cost(125); 6045 ins_cost(125);
6045 // format %{ "movsbq $dst, $mem\t# byte -> long" %} 6046 format %{ "movsbq $dst, $mem\t# byte -> long" %}
6046 // opcode(0x0F, 0xBE); 6047
6047 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, OpcS, reg_mem(dst, mem)); 6048 ins_encode %{
6048 // ins_pipe(ialu_reg_mem); 6049 __ movsbq($dst$$Register, $mem$$Address);
6049 // %} 6050 %}
6050 6051
6051 // Load Byte (8 bit UNsigned) 6052 ins_pipe(ialu_reg_mem);
6052 instruct loadUB(rRegI dst, memory mem, immI_255 bytemask) 6053 %}
6053 %{ 6054
6054 match(Set dst (AndI (LoadB mem) bytemask)); 6055 // Load Unsigned Byte (8 bit UNsigned)
6056 instruct loadUB(rRegI dst, memory mem)
6057 %{
6058 match(Set dst (LoadUB mem));
6055 6059
6056 ins_cost(125); 6060 ins_cost(125);
6057 format %{ "movzbl $dst, $mem\t# ubyte" %} 6061 format %{ "movzbl $dst, $mem\t# ubyte" %}
6058 opcode(0x0F, 0xB6); 6062
6059 ins_encode(REX_reg_mem(dst, mem), OpcP, OpcS, reg_mem(dst, mem)); 6063 ins_encode %{
6064 __ movzbl($dst$$Register, $mem$$Address);
6065 %}
6066
6060 ins_pipe(ialu_reg_mem); 6067 ins_pipe(ialu_reg_mem);
6061 %} 6068 %}
6062 6069
6063 // Load Byte (8 bit UNsigned) into long 6070 // Load Unsigned Byte (8 bit UNsigned) into Long Register
6064 // instruct loadUB2L(rRegL dst, memory mem, immI_255 bytemask) 6071 instruct loadUB2L(rRegL dst, memory mem)
6065 // %{ 6072 %{
6066 // match(Set dst (ConvI2L (AndI (LoadB mem) bytemask))); 6073 match(Set dst (ConvI2L (LoadUB mem)));
6067 6074
6068 // ins_cost(125); 6075 ins_cost(125);
6069 // format %{ "movzbl $dst, $mem\t# ubyte -> long" %} 6076 format %{ "movzbq $dst, $mem\t# ubyte -> long" %}
6070 // opcode(0x0F, 0xB6); 6077
6071 // ins_encode(REX_reg_mem(dst, mem), OpcP, OpcS, reg_mem(dst, mem)); 6078 ins_encode %{
6072 // ins_pipe(ialu_reg_mem); 6079 __ movzbq($dst$$Register, $mem$$Address);
6073 // %} 6080 %}
6081
6082 ins_pipe(ialu_reg_mem);
6083 %}
6074 6084
6075 // Load Short (16 bit signed) 6085 // Load Short (16 bit signed)
6076 instruct loadS(rRegI dst, memory mem) 6086 instruct loadS(rRegI dst, memory mem)
6077 %{ 6087 %{
6078 match(Set dst (LoadS mem)); 6088 match(Set dst (LoadS mem));
6079 6089
6080 ins_cost(125); // XXX 6090 ins_cost(125);
6081 format %{ "movswl $dst, $mem\t# short" %} 6091 format %{ "movswl $dst, $mem\t# short" %}
6082 opcode(0x0F, 0xBF); 6092
6083 ins_encode(REX_reg_mem(dst, mem), OpcP, OpcS, reg_mem(dst, mem)); 6093 ins_encode %{
6094 __ movswl($dst$$Register, $mem$$Address);
6095 %}
6096
6084 ins_pipe(ialu_reg_mem); 6097 ins_pipe(ialu_reg_mem);
6085 %} 6098 %}
6086 6099
6087 // Load Short (16 bit signed) into long 6100 // Load Short (16 bit signed) into Long Register
6088 // instruct loadS2L(rRegL dst, memory mem) 6101 instruct loadS2L(rRegL dst, memory mem)
6089 // %{ 6102 %{
6090 // match(Set dst (ConvI2L (LoadS mem))); 6103 match(Set dst (ConvI2L (LoadS mem)));
6091 6104
6092 // ins_cost(125); // XXX 6105 ins_cost(125);
6093 // format %{ "movswq $dst, $mem\t# short -> long" %} 6106 format %{ "movswq $dst, $mem\t# short -> long" %}
6094 // opcode(0x0F, 0xBF); 6107
6095 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, OpcS, reg_mem(dst, mem)); 6108 ins_encode %{
6096 // ins_pipe(ialu_reg_mem); 6109 __ movswq($dst$$Register, $mem$$Address);
6097 // %} 6110 %}
6111
6112 ins_pipe(ialu_reg_mem);
6113 %}
6098 6114
6099 // Load Unsigned Short/Char (16 bit UNsigned) 6115 // Load Unsigned Short/Char (16 bit UNsigned)
6100 instruct loadUS(rRegI dst, memory mem) 6116 instruct loadUS(rRegI dst, memory mem)
6101 %{ 6117 %{
6102 match(Set dst (LoadUS mem)); 6118 match(Set dst (LoadUS mem));
6103 6119
6104 ins_cost(125); 6120 ins_cost(125);
6105 format %{ "movzwl $dst, $mem\t# ushort/char" %} 6121 format %{ "movzwl $dst, $mem\t# ushort/char" %}
6106 opcode(0x0F, 0xB7); 6122
6107 ins_encode(REX_reg_mem(dst, mem), OpcP, OpcS, reg_mem(dst, mem)); 6123 ins_encode %{
6124 __ movzwl($dst$$Register, $mem$$Address);
6125 %}
6126
6108 ins_pipe(ialu_reg_mem); 6127 ins_pipe(ialu_reg_mem);
6109 %} 6128 %}
6110 6129
6111 // Load Unsigned Short/Char (16 bit UNsigned) into long 6130 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
6112 // instruct loadUS2L(rRegL dst, memory mem) 6131 instruct loadUS2L(rRegL dst, memory mem)
6113 // %{ 6132 %{
6114 // match(Set dst (ConvI2L (LoadUS mem))); 6133 match(Set dst (ConvI2L (LoadUS mem)));
6115 6134
6116 // ins_cost(125); 6135 ins_cost(125);
6117 // format %{ "movzwl $dst, $mem\t# ushort/char -> long" %} 6136 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %}
6118 // opcode(0x0F, 0xB7); 6137
6119 // ins_encode(REX_reg_mem(dst, mem), OpcP, OpcS, reg_mem(dst, mem)); 6138 ins_encode %{
6120 // ins_pipe(ialu_reg_mem); 6139 __ movzwq($dst$$Register, $mem$$Address);
6121 // %} 6140 %}
6141
6142 ins_pipe(ialu_reg_mem);
6143 %}
6122 6144
6123 // Load Integer 6145 // Load Integer
6124 instruct loadI(rRegI dst, memory mem) 6146 instruct loadI(rRegI dst, memory mem)
6125 %{ 6147 %{
6126 match(Set dst (LoadI mem)); 6148 match(Set dst (LoadI mem));
6127 6149
6128 ins_cost(125); // XXX 6150 ins_cost(125);
6129 format %{ "movl $dst, $mem\t# int" %} 6151 format %{ "movl $dst, $mem\t# int" %}
6130 opcode(0x8B); 6152
6131 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem)); 6153 ins_encode %{
6154 __ movl($dst$$Register, $mem$$Address);
6155 %}
6156
6157 ins_pipe(ialu_reg_mem);
6158 %}
6159
6160 // Load Integer into Long Register
6161 instruct loadI2L(rRegL dst, memory mem)
6162 %{
6163 match(Set dst (ConvI2L (LoadI mem)));
6164
6165 ins_cost(125);
6166 format %{ "movslq $dst, $mem\t# int -> long" %}
6167
6168 ins_encode %{
6169 __ movslq($dst$$Register, $mem$$Address);
6170 %}
6171
6172 ins_pipe(ialu_reg_mem);
6173 %}
6174
6175 // Load Unsigned Integer into Long Register
6176 instruct loadUI2L(rRegL dst, memory mem)
6177 %{
6178 match(Set dst (LoadUI2L mem));
6179
6180 ins_cost(125);
6181 format %{ "movl $dst, $mem\t# uint -> long" %}
6182
6183 ins_encode %{
6184 __ movl($dst$$Register, $mem$$Address);
6185 %}
6186
6132 ins_pipe(ialu_reg_mem); 6187 ins_pipe(ialu_reg_mem);
6133 %} 6188 %}
6134 6189
6135 // Load Long 6190 // Load Long
6136 instruct loadL(rRegL dst, memory mem) 6191 instruct loadL(rRegL dst, memory mem)
6137 %{ 6192 %{
6138 match(Set dst (LoadL mem)); 6193 match(Set dst (LoadL mem));
6139 6194
6140 ins_cost(125); // XXX 6195 ins_cost(125);
6141 format %{ "movq $dst, $mem\t# long" %} 6196 format %{ "movq $dst, $mem\t# long" %}
6142 opcode(0x8B); 6197
6143 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); 6198 ins_encode %{
6199 __ movq($dst$$Register, $mem$$Address);
6200 %}
6201
6144 ins_pipe(ialu_reg_mem); // XXX 6202 ins_pipe(ialu_reg_mem); // XXX
6145 %} 6203 %}
6146 6204
6147 // Load Range 6205 // Load Range
6148 instruct loadRange(rRegI dst, memory mem) 6206 instruct loadRange(rRegI dst, memory mem)
10801 // ins_encode(enc_copy(dst, src)); 10859 // ins_encode(enc_copy(dst, src));
10802 // // opcode(0x63); // needs REX.W 10860 // // opcode(0x63); // needs REX.W
10803 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src)); 10861 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
10804 // ins_pipe(ialu_reg_reg); 10862 // ins_pipe(ialu_reg_reg);
10805 // %} 10863 // %}
10806
10807 instruct convI2L_reg_mem(rRegL dst, memory src)
10808 %{
10809 match(Set dst (ConvI2L (LoadI src)));
10810
10811 format %{ "movslq $dst, $src\t# i2l" %}
10812 opcode(0x63); // needs REX.W
10813 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst,src));
10814 ins_pipe(ialu_reg_mem);
10815 %}
10816 10864
10817 // Zero-extend convert int to long 10865 // Zero-extend convert int to long
10818 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask) 10866 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
10819 %{ 10867 %{
10820 match(Set dst (AndL (ConvI2L src) mask)); 10868 match(Set dst (AndL (ConvI2L src) mask));