Mercurial > hg > truffle
annotate src/cpu/x86/vm/x86_64.ad @ 671:d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
Reviewed-by: kvn, phh
| author | never |
|---|---|
| date | Thu, 26 Mar 2009 14:31:45 -0700 |
| parents | bd441136a5ce |
| children | fbde8ec322d0 |
| rev | line source |
|---|---|
| 0 | 1 // |
| 624 | 2 // Copyright 2003-2009 Sun Microsystems, Inc. All Rights Reserved. |
| 0 | 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 // | |
| 5 // This code is free software; you can redistribute it and/or modify it | |
| 6 // under the terms of the GNU General Public License version 2 only, as | |
| 7 // published by the Free Software Foundation. | |
| 8 // | |
| 9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 // version 2 for more details (a copy is included in the LICENSE file that | |
| 13 // accompanied this code). | |
| 14 // | |
| 15 // You should have received a copy of the GNU General Public License version | |
| 16 // 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 // | |
| 19 // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 20 // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 21 // have any questions. | |
| 22 // | |
| 23 // | |
| 24 | |
| 25 // AMD64 Architecture Description File | |
| 26 | |
| 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ | |
| 28 // This information is used by the matcher and the register allocator to | |
| 29 // describe individual registers and classes of registers within the target | |
| 30 // archtecture. | |
| 31 | |
| 32 register %{ | |
| 33 //----------Architecture Description Register Definitions---------------------- | |
| 34 // General Registers | |
| 35 // "reg_def" name ( register save type, C convention save type, | |
| 36 // ideal register type, encoding ); | |
| 37 // Register Save Types: | |
| 38 // | |
| 39 // NS = No-Save: The register allocator assumes that these registers | |
| 40 // can be used without saving upon entry to the method, & | |
| 41 // that they do not need to be saved at call sites. | |
| 42 // | |
| 43 // SOC = Save-On-Call: The register allocator assumes that these registers | |
| 44 // can be used without saving upon entry to the method, | |
| 45 // but that they must be saved at call sites. | |
| 46 // | |
| 47 // SOE = Save-On-Entry: The register allocator assumes that these registers | |
| 48 // must be saved before using them upon entry to the | |
| 49 // method, but they do not need to be saved at call | |
| 50 // sites. | |
| 51 // | |
| 52 // AS = Always-Save: The register allocator assumes that these registers | |
| 53 // must be saved before using them upon entry to the | |
| 54 // method, & that they must be saved at call sites. | |
| 55 // | |
| 56 // Ideal Register Type is used to determine how to save & restore a | |
| 57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get | |
| 58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. | |
| 59 // | |
| 60 // The encoding number is the actual bit-pattern placed into the opcodes. | |
| 61 | |
| 62 // General Registers | |
| 63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when | |
| 64 // used as byte registers) | |
| 65 | |
| 66 // Previously set RBX, RSI, and RDI as save-on-entry for java code | |
| 67 // Turn off SOE in java-code due to frequent use of uncommon-traps. | |
| 68 // Now that allocator is better, turn on RSI and RDI as SOE registers. | |
| 69 | |
| 70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg()); | |
| 71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next()); | |
| 72 | |
| 73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg()); | |
| 74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next()); | |
| 75 | |
| 76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg()); | |
| 77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next()); | |
| 78 | |
| 79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg()); | |
| 80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next()); | |
| 81 | |
| 82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg()); | |
| 83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next()); | |
| 84 | |
| 85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code | |
| 86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg()); | |
| 87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next()); | |
| 88 | |
| 89 #ifdef _WIN64 | |
| 90 | |
| 91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg()); | |
| 92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next()); | |
| 93 | |
| 94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg()); | |
| 95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next()); | |
| 96 | |
| 97 #else | |
| 98 | |
| 99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg()); | |
| 100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next()); | |
| 101 | |
| 102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg()); | |
| 103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next()); | |
| 104 | |
| 105 #endif | |
| 106 | |
| 107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg()); | |
| 108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next()); | |
| 109 | |
| 110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg()); | |
| 111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next()); | |
| 112 | |
| 113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg()); | |
| 114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next()); | |
| 115 | |
| 116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg()); | |
| 117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next()); | |
| 118 | |
| 119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg()); | |
| 120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next()); | |
| 121 | |
| 122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg()); | |
| 123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next()); | |
| 124 | |
| 125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg()); | |
| 126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next()); | |
| 127 | |
| 128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg()); | |
| 129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next()); | |
| 130 | |
| 131 | |
| 132 // Floating Point Registers | |
| 133 | |
| 134 // XMM registers. 128-bit registers or 4 words each, labeled (a)-d. | |
| 135 // Word a in each register holds a Float, words ab hold a Double. We | |
| 136 // currently do not use the SIMD capabilities, so registers cd are | |
| 137 // unused at the moment. | |
| 138 // XMM8-XMM15 must be encoded with REX. | |
| 139 // Linux ABI: No register preserved across function calls | |
| 140 // XMM0-XMM7 might hold parameters | |
| 141 // Windows ABI: XMM6-XMM15 preserved across function calls | |
| 142 // XMM0-XMM3 might hold parameters | |
| 143 | |
| 144 reg_def XMM0 (SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()); | |
| 145 reg_def XMM0_H (SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next()); | |
| 146 | |
| 147 reg_def XMM1 (SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()); | |
| 148 reg_def XMM1_H (SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next()); | |
| 149 | |
| 150 reg_def XMM2 (SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()); | |
| 151 reg_def XMM2_H (SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next()); | |
| 152 | |
| 153 reg_def XMM3 (SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()); | |
| 154 reg_def XMM3_H (SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next()); | |
| 155 | |
| 156 reg_def XMM4 (SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()); | |
| 157 reg_def XMM4_H (SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next()); | |
| 158 | |
| 159 reg_def XMM5 (SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()); | |
| 160 reg_def XMM5_H (SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next()); | |
| 161 | |
| 162 #ifdef _WIN64 | |
| 163 | |
| 164 reg_def XMM6 (SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()); | |
| 165 reg_def XMM6_H (SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next()); | |
| 166 | |
| 167 reg_def XMM7 (SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()); | |
| 168 reg_def XMM7_H (SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next()); | |
| 169 | |
| 170 reg_def XMM8 (SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()); | |
| 171 reg_def XMM8_H (SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next()); | |
| 172 | |
| 173 reg_def XMM9 (SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()); | |
| 174 reg_def XMM9_H (SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next()); | |
| 175 | |
| 176 reg_def XMM10 (SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()); | |
| 177 reg_def XMM10_H(SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next()); | |
| 178 | |
| 179 reg_def XMM11 (SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()); | |
| 180 reg_def XMM11_H(SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next()); | |
| 181 | |
| 182 reg_def XMM12 (SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()); | |
| 183 reg_def XMM12_H(SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next()); | |
| 184 | |
| 185 reg_def XMM13 (SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()); | |
| 186 reg_def XMM13_H(SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next()); | |
| 187 | |
| 188 reg_def XMM14 (SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()); | |
| 189 reg_def XMM14_H(SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next()); | |
| 190 | |
| 191 reg_def XMM15 (SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()); | |
| 192 reg_def XMM15_H(SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next()); | |
| 193 | |
| 194 #else | |
| 195 | |
| 196 reg_def XMM6 (SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()); | |
| 197 reg_def XMM6_H (SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next()); | |
| 198 | |
| 199 reg_def XMM7 (SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()); | |
| 200 reg_def XMM7_H (SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next()); | |
| 201 | |
| 202 reg_def XMM8 (SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()); | |
| 203 reg_def XMM8_H (SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next()); | |
| 204 | |
| 205 reg_def XMM9 (SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()); | |
| 206 reg_def XMM9_H (SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next()); | |
| 207 | |
| 208 reg_def XMM10 (SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()); | |
| 209 reg_def XMM10_H(SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next()); | |
| 210 | |
| 211 reg_def XMM11 (SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()); | |
| 212 reg_def XMM11_H(SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next()); | |
| 213 | |
| 214 reg_def XMM12 (SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()); | |
| 215 reg_def XMM12_H(SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next()); | |
| 216 | |
| 217 reg_def XMM13 (SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()); | |
| 218 reg_def XMM13_H(SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next()); | |
| 219 | |
| 220 reg_def XMM14 (SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()); | |
| 221 reg_def XMM14_H(SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next()); | |
| 222 | |
| 223 reg_def XMM15 (SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()); | |
| 224 reg_def XMM15_H(SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next()); | |
| 225 | |
| 226 #endif // _WIN64 | |
| 227 | |
| 228 reg_def RFLAGS(SOC, SOC, 0, 16, VMRegImpl::Bad()); | |
| 229 | |
| 230 // Specify priority of register selection within phases of register | |
| 231 // allocation. Highest priority is first. A useful heuristic is to | |
| 232 // give registers a low priority when they are required by machine | |
| 233 // instructions, like EAX and EDX on I486, and choose no-save registers | |
| 234 // before save-on-call, & save-on-call before save-on-entry. Registers | |
| 235 // which participate in fixed calling sequences should come last. | |
| 236 // Registers which are used as pairs must fall on an even boundary. | |
| 237 | |
| 238 alloc_class chunk0(R10, R10_H, | |
| 239 R11, R11_H, | |
| 240 R8, R8_H, | |
| 241 R9, R9_H, | |
| 242 R12, R12_H, | |
| 243 RCX, RCX_H, | |
| 244 RBX, RBX_H, | |
| 245 RDI, RDI_H, | |
| 246 RDX, RDX_H, | |
| 247 RSI, RSI_H, | |
| 248 RAX, RAX_H, | |
| 249 RBP, RBP_H, | |
| 250 R13, R13_H, | |
| 251 R14, R14_H, | |
| 252 R15, R15_H, | |
| 253 RSP, RSP_H); | |
| 254 | |
| 255 // XXX probably use 8-15 first on Linux | |
| 256 alloc_class chunk1(XMM0, XMM0_H, | |
| 257 XMM1, XMM1_H, | |
| 258 XMM2, XMM2_H, | |
| 259 XMM3, XMM3_H, | |
| 260 XMM4, XMM4_H, | |
| 261 XMM5, XMM5_H, | |
| 262 XMM6, XMM6_H, | |
| 263 XMM7, XMM7_H, | |
| 264 XMM8, XMM8_H, | |
| 265 XMM9, XMM9_H, | |
| 266 XMM10, XMM10_H, | |
| 267 XMM11, XMM11_H, | |
| 268 XMM12, XMM12_H, | |
| 269 XMM13, XMM13_H, | |
| 270 XMM14, XMM14_H, | |
| 271 XMM15, XMM15_H); | |
| 272 | |
| 273 alloc_class chunk2(RFLAGS); | |
| 274 | |
| 275 | |
| 276 //----------Architecture Description Register Classes-------------------------- | |
| 277 // Several register classes are automatically defined based upon information in | |
| 278 // this architecture description. | |
| 279 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ ) | |
| 280 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ ) | |
| 281 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ ) | |
| 282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) | |
| 283 // | |
| 284 | |
| 285 // Class for all pointer registers (including RSP) | |
| 286 reg_class any_reg(RAX, RAX_H, | |
| 287 RDX, RDX_H, | |
| 288 RBP, RBP_H, | |
| 289 RDI, RDI_H, | |
| 290 RSI, RSI_H, | |
| 291 RCX, RCX_H, | |
| 292 RBX, RBX_H, | |
| 293 RSP, RSP_H, | |
| 294 R8, R8_H, | |
| 295 R9, R9_H, | |
| 296 R10, R10_H, | |
| 297 R11, R11_H, | |
| 298 R12, R12_H, | |
| 299 R13, R13_H, | |
| 300 R14, R14_H, | |
| 301 R15, R15_H); | |
| 302 | |
| 303 // Class for all pointer registers except RSP | |
| 304 reg_class ptr_reg(RAX, RAX_H, | |
| 305 RDX, RDX_H, | |
| 306 RBP, RBP_H, | |
| 307 RDI, RDI_H, | |
| 308 RSI, RSI_H, | |
| 309 RCX, RCX_H, | |
| 310 RBX, RBX_H, | |
| 311 R8, R8_H, | |
| 312 R9, R9_H, | |
| 313 R10, R10_H, | |
| 314 R11, R11_H, | |
| 315 R13, R13_H, | |
| 316 R14, R14_H); | |
| 317 | |
| 318 // Class for all pointer registers except RAX and RSP | |
| 319 reg_class ptr_no_rax_reg(RDX, RDX_H, | |
| 320 RBP, RBP_H, | |
| 321 RDI, RDI_H, | |
| 322 RSI, RSI_H, | |
| 323 RCX, RCX_H, | |
| 324 RBX, RBX_H, | |
| 325 R8, R8_H, | |
| 326 R9, R9_H, | |
| 327 R10, R10_H, | |
| 328 R11, R11_H, | |
| 329 R13, R13_H, | |
| 330 R14, R14_H); | |
| 331 | |
| 332 reg_class ptr_no_rbp_reg(RDX, RDX_H, | |
| 333 RAX, RAX_H, | |
| 334 RDI, RDI_H, | |
| 335 RSI, RSI_H, | |
| 336 RCX, RCX_H, | |
| 337 RBX, RBX_H, | |
| 338 R8, R8_H, | |
| 339 R9, R9_H, | |
| 340 R10, R10_H, | |
| 341 R11, R11_H, | |
| 342 R13, R13_H, | |
| 343 R14, R14_H); | |
| 344 | |
| 345 // Class for all pointer registers except RAX, RBX and RSP | |
| 346 reg_class ptr_no_rax_rbx_reg(RDX, RDX_H, | |
| 347 RBP, RBP_H, | |
| 348 RDI, RDI_H, | |
| 349 RSI, RSI_H, | |
| 350 RCX, RCX_H, | |
| 351 R8, R8_H, | |
| 352 R9, R9_H, | |
| 353 R10, R10_H, | |
| 354 R11, R11_H, | |
| 355 R13, R13_H, | |
| 356 R14, R14_H); | |
| 357 | |
| 358 // Singleton class for RAX pointer register | |
| 359 reg_class ptr_rax_reg(RAX, RAX_H); | |
| 360 | |
| 361 // Singleton class for RBX pointer register | |
| 362 reg_class ptr_rbx_reg(RBX, RBX_H); | |
| 363 | |
| 364 // Singleton class for RSI pointer register | |
| 365 reg_class ptr_rsi_reg(RSI, RSI_H); | |
| 366 | |
| 367 // Singleton class for RDI pointer register | |
| 368 reg_class ptr_rdi_reg(RDI, RDI_H); | |
| 369 | |
| 370 // Singleton class for RBP pointer register | |
| 371 reg_class ptr_rbp_reg(RBP, RBP_H); | |
| 372 | |
| 373 // Singleton class for stack pointer | |
| 374 reg_class ptr_rsp_reg(RSP, RSP_H); | |
| 375 | |
| 376 // Singleton class for TLS pointer | |
| 377 reg_class ptr_r15_reg(R15, R15_H); | |
| 378 | |
| 379 // Class for all long registers (except RSP) | |
| 380 reg_class long_reg(RAX, RAX_H, | |
| 381 RDX, RDX_H, | |
| 382 RBP, RBP_H, | |
| 383 RDI, RDI_H, | |
| 384 RSI, RSI_H, | |
| 385 RCX, RCX_H, | |
| 386 RBX, RBX_H, | |
| 387 R8, R8_H, | |
| 388 R9, R9_H, | |
| 389 R10, R10_H, | |
| 390 R11, R11_H, | |
| 391 R13, R13_H, | |
| 392 R14, R14_H); | |
| 393 | |
| 394 // Class for all long registers except RAX, RDX (and RSP) | |
| 395 reg_class long_no_rax_rdx_reg(RBP, RBP_H, | |
| 396 RDI, RDI_H, | |
| 397 RSI, RSI_H, | |
| 398 RCX, RCX_H, | |
| 399 RBX, RBX_H, | |
| 400 R8, R8_H, | |
| 401 R9, R9_H, | |
| 402 R10, R10_H, | |
| 403 R11, R11_H, | |
| 404 R13, R13_H, | |
| 405 R14, R14_H); | |
| 406 | |
| 407 // Class for all long registers except RCX (and RSP) | |
| 408 reg_class long_no_rcx_reg(RBP, RBP_H, | |
| 409 RDI, RDI_H, | |
| 410 RSI, RSI_H, | |
| 411 RAX, RAX_H, | |
| 412 RDX, RDX_H, | |
| 413 RBX, RBX_H, | |
| 414 R8, R8_H, | |
| 415 R9, R9_H, | |
| 416 R10, R10_H, | |
| 417 R11, R11_H, | |
| 418 R13, R13_H, | |
| 419 R14, R14_H); | |
| 420 | |
| 421 // Class for all long registers except RAX (and RSP) | |
| 422 reg_class long_no_rax_reg(RBP, RBP_H, | |
| 423 RDX, RDX_H, | |
| 424 RDI, RDI_H, | |
| 425 RSI, RSI_H, | |
| 426 RCX, RCX_H, | |
| 427 RBX, RBX_H, | |
| 428 R8, R8_H, | |
| 429 R9, R9_H, | |
| 430 R10, R10_H, | |
| 431 R11, R11_H, | |
| 432 R13, R13_H, | |
| 433 R14, R14_H); | |
| 434 | |
| 435 // Singleton class for RAX long register | |
| 436 reg_class long_rax_reg(RAX, RAX_H); | |
| 437 | |
| 438 // Singleton class for RCX long register | |
| 439 reg_class long_rcx_reg(RCX, RCX_H); | |
| 440 | |
| 441 // Singleton class for RDX long register | |
| 442 reg_class long_rdx_reg(RDX, RDX_H); | |
| 443 | |
| 444 // Class for all int registers (except RSP) | |
| 445 reg_class int_reg(RAX, | |
| 446 RDX, | |
| 447 RBP, | |
| 448 RDI, | |
| 449 RSI, | |
| 450 RCX, | |
| 451 RBX, | |
| 452 R8, | |
| 453 R9, | |
| 454 R10, | |
| 455 R11, | |
| 456 R13, | |
| 457 R14); | |
| 458 | |
| 459 // Class for all int registers except RCX (and RSP) | |
| 460 reg_class int_no_rcx_reg(RAX, | |
| 461 RDX, | |
| 462 RBP, | |
| 463 RDI, | |
| 464 RSI, | |
| 465 RBX, | |
| 466 R8, | |
| 467 R9, | |
| 468 R10, | |
| 469 R11, | |
| 470 R13, | |
| 471 R14); | |
| 472 | |
| 473 // Class for all int registers except RAX, RDX (and RSP) | |
| 474 reg_class int_no_rax_rdx_reg(RBP, | |
| 304 | 475 RDI, |
| 0 | 476 RSI, |
| 477 RCX, | |
| 478 RBX, | |
| 479 R8, | |
| 480 R9, | |
| 481 R10, | |
| 482 R11, | |
| 483 R13, | |
| 484 R14); | |
| 485 | |
| 486 // Singleton class for RAX int register | |
| 487 reg_class int_rax_reg(RAX); | |
| 488 | |
| 489 // Singleton class for RBX int register | |
| 490 reg_class int_rbx_reg(RBX); | |
| 491 | |
| 492 // Singleton class for RCX int register | |
| 493 reg_class int_rcx_reg(RCX); | |
| 494 | |
| 495 // Singleton class for RCX int register | |
| 496 reg_class int_rdx_reg(RDX); | |
| 497 | |
| 498 // Singleton class for RCX int register | |
| 499 reg_class int_rdi_reg(RDI); | |
| 500 | |
| 501 // Singleton class for instruction pointer | |
| 502 // reg_class ip_reg(RIP); | |
| 503 | |
| 504 // Singleton class for condition codes | |
| 505 reg_class int_flags(RFLAGS); | |
| 506 | |
| 507 // Class for all float registers | |
| 508 reg_class float_reg(XMM0, | |
| 509 XMM1, | |
| 510 XMM2, | |
| 511 XMM3, | |
| 512 XMM4, | |
| 513 XMM5, | |
| 514 XMM6, | |
| 515 XMM7, | |
| 516 XMM8, | |
| 517 XMM9, | |
| 518 XMM10, | |
| 519 XMM11, | |
| 520 XMM12, | |
| 521 XMM13, | |
| 522 XMM14, | |
| 523 XMM15); | |
| 524 | |
| 525 // Class for all double registers | |
| 526 reg_class double_reg(XMM0, XMM0_H, | |
| 527 XMM1, XMM1_H, | |
| 528 XMM2, XMM2_H, | |
| 529 XMM3, XMM3_H, | |
| 530 XMM4, XMM4_H, | |
| 531 XMM5, XMM5_H, | |
| 532 XMM6, XMM6_H, | |
| 533 XMM7, XMM7_H, | |
| 534 XMM8, XMM8_H, | |
| 535 XMM9, XMM9_H, | |
| 536 XMM10, XMM10_H, | |
| 537 XMM11, XMM11_H, | |
| 538 XMM12, XMM12_H, | |
| 539 XMM13, XMM13_H, | |
| 540 XMM14, XMM14_H, | |
| 541 XMM15, XMM15_H); | |
| 542 %} | |
| 543 | |
| 544 | |
| 545 //----------SOURCE BLOCK------------------------------------------------------- | |
| 546 // This is a block of C++ code which provides values, functions, and | |
| 547 // definitions necessary in the rest of the architecture description | |
| 548 source %{ | |
| 304 | 549 #define RELOC_IMM64 Assembler::imm_operand |
| 0 | 550 #define RELOC_DISP32 Assembler::disp32_operand |
| 551 | |
| 552 #define __ _masm. | |
| 553 | |
| 554 // !!!!! Special hack to get all types of calls to specify the byte offset | |
| 555 // from the start of the call to the point where the return address | |
| 556 // will point. | |
| 557 int MachCallStaticJavaNode::ret_addr_offset() | |
| 558 { | |
| 559 return 5; // 5 bytes from start of call to where return address points | |
| 560 } | |
| 561 | |
| 562 int MachCallDynamicJavaNode::ret_addr_offset() | |
| 563 { | |
| 564 return 15; // 15 bytes from start of call to where return address points | |
| 565 } | |
| 566 | |
| 567 // In os_cpu .ad file | |
| 568 // int MachCallRuntimeNode::ret_addr_offset() | |
| 569 | |
| 570 // Indicate if the safepoint node needs the polling page as an input. | |
| 571 // Since amd64 does not have absolute addressing but RIP-relative | |
| 572 // addressing and the polling page is within 2G, it doesn't. | |
| 573 bool SafePointNode::needs_polling_address_input() | |
| 574 { | |
| 575 return false; | |
| 576 } | |
| 577 | |
| 578 // | |
| 579 // Compute padding required for nodes which need alignment | |
| 580 // | |
| 581 | |
| 582 // The address of the call instruction needs to be 4-byte aligned to | |
| 583 // ensure that it does not span a cache line so that it can be patched. | |
| 584 int CallStaticJavaDirectNode::compute_padding(int current_offset) const | |
| 585 { | |
| 586 current_offset += 1; // skip call opcode byte | |
| 587 return round_to(current_offset, alignment_required()) - current_offset; | |
| 588 } | |
| 589 | |
| 590 // The address of the call instruction needs to be 4-byte aligned to | |
| 591 // ensure that it does not span a cache line so that it can be patched. | |
| 592 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const | |
| 593 { | |
| 594 current_offset += 11; // skip movq instruction + call opcode byte | |
| 595 return round_to(current_offset, alignment_required()) - current_offset; | |
| 596 } | |
| 597 | |
| 598 #ifndef PRODUCT | |
| 599 void MachBreakpointNode::format(PhaseRegAlloc*, outputStream* st) const | |
| 600 { | |
| 601 st->print("INT3"); | |
| 602 } | |
| 603 #endif | |
| 604 | |
| 605 // EMIT_RM() | |
| 606 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) | |
| 607 { | |
| 608 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3); | |
| 609 *(cbuf.code_end()) = c; | |
| 610 cbuf.set_code_end(cbuf.code_end() + 1); | |
| 611 } | |
| 612 | |
| 613 // EMIT_CC() | |
| 614 void emit_cc(CodeBuffer &cbuf, int f1, int f2) | |
| 615 { | |
| 616 unsigned char c = (unsigned char) (f1 | f2); | |
| 617 *(cbuf.code_end()) = c; | |
| 618 cbuf.set_code_end(cbuf.code_end() + 1); | |
| 619 } | |
| 620 | |
| 621 // EMIT_OPCODE() | |
| 622 void emit_opcode(CodeBuffer &cbuf, int code) | |
| 623 { | |
| 624 *(cbuf.code_end()) = (unsigned char) code; | |
| 625 cbuf.set_code_end(cbuf.code_end() + 1); | |
| 626 } | |
| 627 | |
| 628 // EMIT_OPCODE() w/ relocation information | |
| 629 void emit_opcode(CodeBuffer &cbuf, | |
| 630 int code, relocInfo::relocType reloc, int offset, int format) | |
| 631 { | |
| 632 cbuf.relocate(cbuf.inst_mark() + offset, reloc, format); | |
| 633 emit_opcode(cbuf, code); | |
| 634 } | |
| 635 | |
| 636 // EMIT_D8() | |
| 637 void emit_d8(CodeBuffer &cbuf, int d8) | |
| 638 { | |
| 639 *(cbuf.code_end()) = (unsigned char) d8; | |
| 640 cbuf.set_code_end(cbuf.code_end() + 1); | |
| 641 } | |
| 642 | |
| 643 // EMIT_D16() | |
| 644 void emit_d16(CodeBuffer &cbuf, int d16) | |
| 645 { | |
| 646 *((short *)(cbuf.code_end())) = d16; | |
| 647 cbuf.set_code_end(cbuf.code_end() + 2); | |
| 648 } | |
| 649 | |
| 650 // EMIT_D32() | |
| 651 void emit_d32(CodeBuffer &cbuf, int d32) | |
| 652 { | |
| 653 *((int *)(cbuf.code_end())) = d32; | |
| 654 cbuf.set_code_end(cbuf.code_end() + 4); | |
| 655 } | |
| 656 | |
| 657 // EMIT_D64() | |
| 658 void emit_d64(CodeBuffer &cbuf, int64_t d64) | |
| 659 { | |
| 660 *((int64_t*) (cbuf.code_end())) = d64; | |
| 661 cbuf.set_code_end(cbuf.code_end() + 8); | |
| 662 } | |
| 663 | |
| 664 // emit 32 bit value and construct relocation entry from relocInfo::relocType | |
| 665 void emit_d32_reloc(CodeBuffer& cbuf, | |
| 666 int d32, | |
| 667 relocInfo::relocType reloc, | |
| 668 int format) | |
| 669 { | |
| 670 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc"); | |
| 671 cbuf.relocate(cbuf.inst_mark(), reloc, format); | |
| 672 | |
| 673 *((int*) (cbuf.code_end())) = d32; | |
| 674 cbuf.set_code_end(cbuf.code_end() + 4); | |
| 675 } | |
| 676 | |
| 677 // emit 32 bit value and construct relocation entry from RelocationHolder | |
| 678 void emit_d32_reloc(CodeBuffer& cbuf, | |
| 679 int d32, | |
| 680 RelocationHolder const& rspec, | |
| 681 int format) | |
| 682 { | |
| 683 #ifdef ASSERT | |
| 684 if (rspec.reloc()->type() == relocInfo::oop_type && | |
| 685 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) { | |
| 686 assert(oop((intptr_t)d32)->is_oop() && oop((intptr_t)d32)->is_perm(), "cannot embed non-perm oops in code"); | |
| 687 } | |
| 688 #endif | |
| 689 cbuf.relocate(cbuf.inst_mark(), rspec, format); | |
| 690 | |
| 691 *((int* )(cbuf.code_end())) = d32; | |
| 692 cbuf.set_code_end(cbuf.code_end() + 4); | |
| 693 } | |
| 694 | |
| 695 void emit_d32_reloc(CodeBuffer& cbuf, address addr) { | |
| 696 address next_ip = cbuf.code_end() + 4; | |
| 697 emit_d32_reloc(cbuf, (int) (addr - next_ip), | |
| 698 external_word_Relocation::spec(addr), | |
| 699 RELOC_DISP32); | |
| 700 } | |
| 701 | |
| 702 | |
| 703 // emit 64 bit value and construct relocation entry from relocInfo::relocType | |
| 704 void emit_d64_reloc(CodeBuffer& cbuf, | |
| 705 int64_t d64, | |
| 706 relocInfo::relocType reloc, | |
| 707 int format) | |
| 708 { | |
| 709 cbuf.relocate(cbuf.inst_mark(), reloc, format); | |
| 710 | |
| 711 *((int64_t*) (cbuf.code_end())) = d64; | |
| 712 cbuf.set_code_end(cbuf.code_end() + 8); | |
| 713 } | |
| 714 | |
| 715 // emit 64 bit value and construct relocation entry from RelocationHolder | |
| 716 void emit_d64_reloc(CodeBuffer& cbuf, | |
| 717 int64_t d64, | |
| 718 RelocationHolder const& rspec, | |
| 719 int format) | |
| 720 { | |
| 721 #ifdef ASSERT | |
| 722 if (rspec.reloc()->type() == relocInfo::oop_type && | |
| 723 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) { | |
| 724 assert(oop(d64)->is_oop() && oop(d64)->is_perm(), | |
| 725 "cannot embed non-perm oops in code"); | |
| 726 } | |
| 727 #endif | |
| 728 cbuf.relocate(cbuf.inst_mark(), rspec, format); | |
| 729 | |
| 730 *((int64_t*) (cbuf.code_end())) = d64; | |
| 731 cbuf.set_code_end(cbuf.code_end() + 8); | |
| 732 } | |
| 733 | |
| 734 // Access stack slot for load or store | |
| 735 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) | |
| 736 { | |
| 737 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src]) | |
| 738 if (-0x80 <= disp && disp < 0x80) { | |
| 739 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte | |
| 740 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte | |
| 741 emit_d8(cbuf, disp); // Displacement // R/M byte | |
| 742 } else { | |
| 743 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte | |
| 744 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte | |
| 745 emit_d32(cbuf, disp); // Displacement // R/M byte | |
| 746 } | |
| 747 } | |
| 748 | |
| 749 // rRegI ereg, memory mem) %{ // emit_reg_mem | |
| 750 void encode_RegMem(CodeBuffer &cbuf, | |
| 751 int reg, | |
| 752 int base, int index, int scale, int disp, bool disp_is_oop) | |
| 753 { | |
| 754 assert(!disp_is_oop, "cannot have disp"); | |
| 755 int regenc = reg & 7; | |
| 756 int baseenc = base & 7; | |
| 757 int indexenc = index & 7; | |
| 758 | |
| 759 // There is no index & no scale, use form without SIB byte | |
| 760 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) { | |
| 761 // If no displacement, mode is 0x0; unless base is [RBP] or [R13] | |
| 762 if (disp == 0 && base != RBP_enc && base != R13_enc) { | |
| 763 emit_rm(cbuf, 0x0, regenc, baseenc); // * | |
| 764 } else if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) { | |
| 765 // If 8-bit displacement, mode 0x1 | |
| 766 emit_rm(cbuf, 0x1, regenc, baseenc); // * | |
| 767 emit_d8(cbuf, disp); | |
| 768 } else { | |
| 769 // If 32-bit displacement | |
| 770 if (base == -1) { // Special flag for absolute address | |
| 771 emit_rm(cbuf, 0x0, regenc, 0x5); // * | |
| 772 if (disp_is_oop) { | |
| 773 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32); | |
| 774 } else { | |
| 775 emit_d32(cbuf, disp); | |
| 776 } | |
| 777 } else { | |
| 778 // Normal base + offset | |
| 779 emit_rm(cbuf, 0x2, regenc, baseenc); // * | |
| 780 if (disp_is_oop) { | |
| 781 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32); | |
| 782 } else { | |
| 783 emit_d32(cbuf, disp); | |
| 784 } | |
| 785 } | |
| 786 } | |
| 787 } else { | |
| 788 // Else, encode with the SIB byte | |
| 789 // If no displacement, mode is 0x0; unless base is [RBP] or [R13] | |
| 790 if (disp == 0 && base != RBP_enc && base != R13_enc) { | |
| 791 // If no displacement | |
| 792 emit_rm(cbuf, 0x0, regenc, 0x4); // * | |
| 793 emit_rm(cbuf, scale, indexenc, baseenc); | |
| 794 } else { | |
| 795 if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) { | |
| 796 // If 8-bit displacement, mode 0x1 | |
| 797 emit_rm(cbuf, 0x1, regenc, 0x4); // * | |
| 798 emit_rm(cbuf, scale, indexenc, baseenc); | |
| 799 emit_d8(cbuf, disp); | |
| 800 } else { | |
| 801 // If 32-bit displacement | |
| 802 if (base == 0x04 ) { | |
| 803 emit_rm(cbuf, 0x2, regenc, 0x4); | |
| 804 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid??? | |
| 805 } else { | |
| 806 emit_rm(cbuf, 0x2, regenc, 0x4); | |
| 807 emit_rm(cbuf, scale, indexenc, baseenc); // * | |
| 808 } | |
| 809 if (disp_is_oop) { | |
| 810 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32); | |
| 811 } else { | |
| 812 emit_d32(cbuf, disp); | |
| 813 } | |
| 814 } | |
| 815 } | |
| 816 } | |
| 817 } | |
| 818 | |
| 819 void encode_copy(CodeBuffer &cbuf, int dstenc, int srcenc) | |
| 820 { | |
| 821 if (dstenc != srcenc) { | |
| 822 if (dstenc < 8) { | |
| 823 if (srcenc >= 8) { | |
| 824 emit_opcode(cbuf, Assembler::REX_B); | |
| 825 srcenc -= 8; | |
| 826 } | |
| 827 } else { | |
| 828 if (srcenc < 8) { | |
| 829 emit_opcode(cbuf, Assembler::REX_R); | |
| 830 } else { | |
| 831 emit_opcode(cbuf, Assembler::REX_RB); | |
| 832 srcenc -= 8; | |
| 833 } | |
| 834 dstenc -= 8; | |
| 835 } | |
| 836 | |
| 837 emit_opcode(cbuf, 0x8B); | |
| 838 emit_rm(cbuf, 0x3, dstenc, srcenc); | |
| 839 } | |
| 840 } | |
| 841 | |
| 842 void encode_CopyXD( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) { | |
| 843 if( dst_encoding == src_encoding ) { | |
| 844 // reg-reg copy, use an empty encoding | |
| 845 } else { | |
| 846 MacroAssembler _masm(&cbuf); | |
| 847 | |
| 848 __ movdqa(as_XMMRegister(dst_encoding), as_XMMRegister(src_encoding)); | |
| 849 } | |
| 850 } | |
| 851 | |
| 852 | |
| 853 //============================================================================= | |
| 854 #ifndef PRODUCT | |
| 855 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const | |
| 856 { | |
| 857 Compile* C = ra_->C; | |
| 858 | |
| 859 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 860 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 861 // Remove wordSize for return adr already pushed | |
| 862 // and another for the RBP we are going to save | |
| 863 framesize -= 2*wordSize; | |
| 864 bool need_nop = true; | |
| 865 | |
| 866 // Calls to C2R adapters often do not accept exceptional returns. | |
| 867 // We require that their callers must bang for them. But be | |
| 868 // careful, because some VM calls (such as call site linkage) can | |
| 869 // use several kilobytes of stack. But the stack safety zone should | |
| 870 // account for that. See bugs 4446381, 4468289, 4497237. | |
| 871 if (C->need_stack_bang(framesize)) { | |
| 872 st->print_cr("# stack bang"); st->print("\t"); | |
| 873 need_nop = false; | |
| 874 } | |
| 875 st->print_cr("pushq rbp"); st->print("\t"); | |
| 876 | |
| 877 if (VerifyStackAtCalls) { | |
| 878 // Majik cookie to verify stack depth | |
| 879 st->print_cr("pushq 0xffffffffbadb100d" | |
| 880 "\t# Majik cookie for stack depth check"); | |
| 881 st->print("\t"); | |
| 882 framesize -= wordSize; // Remove 2 for cookie | |
| 883 need_nop = false; | |
| 884 } | |
| 885 | |
| 886 if (framesize) { | |
| 887 st->print("subq rsp, #%d\t# Create frame", framesize); | |
| 888 if (framesize < 0x80 && need_nop) { | |
| 889 st->print("\n\tnop\t# nop for patch_verified_entry"); | |
| 890 } | |
| 891 } | |
| 892 } | |
| 893 #endif | |
| 894 | |
| 895 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const | |
| 896 { | |
| 897 Compile* C = ra_->C; | |
| 898 | |
| 899 // WARNING: Initial instruction MUST be 5 bytes or longer so that | |
| 900 // NativeJump::patch_verified_entry will be able to patch out the entry | |
| 901 // code safely. The fldcw is ok at 6 bytes, the push to verify stack | |
| 902 // depth is ok at 5 bytes, the frame allocation can be either 3 or | |
| 903 // 6 bytes. So if we don't do the fldcw or the push then we must | |
| 904 // use the 6 byte frame allocation even if we have no frame. :-( | |
| 905 // If method sets FPU control word do it now | |
| 906 | |
| 907 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 908 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 909 // Remove wordSize for return adr already pushed | |
| 910 // and another for the RBP we are going to save | |
| 911 framesize -= 2*wordSize; | |
| 912 bool need_nop = true; | |
| 913 | |
| 914 // Calls to C2R adapters often do not accept exceptional returns. | |
| 915 // We require that their callers must bang for them. But be | |
| 916 // careful, because some VM calls (such as call site linkage) can | |
| 917 // use several kilobytes of stack. But the stack safety zone should | |
| 918 // account for that. See bugs 4446381, 4468289, 4497237. | |
| 919 if (C->need_stack_bang(framesize)) { | |
| 920 MacroAssembler masm(&cbuf); | |
| 921 masm.generate_stack_overflow_check(framesize); | |
| 922 need_nop = false; | |
| 923 } | |
| 924 | |
| 925 // We always push rbp so that on return to interpreter rbp will be | |
| 926 // restored correctly and we can correct the stack. | |
| 927 emit_opcode(cbuf, 0x50 | RBP_enc); | |
| 928 | |
| 929 if (VerifyStackAtCalls) { | |
| 930 // Majik cookie to verify stack depth | |
| 931 emit_opcode(cbuf, 0x68); // pushq (sign-extended) 0xbadb100d | |
| 932 emit_d32(cbuf, 0xbadb100d); | |
| 933 framesize -= wordSize; // Remove 2 for cookie | |
| 934 need_nop = false; | |
| 935 } | |
| 936 | |
| 937 if (framesize) { | |
| 938 emit_opcode(cbuf, Assembler::REX_W); | |
| 939 if (framesize < 0x80) { | |
| 940 emit_opcode(cbuf, 0x83); // sub SP,#framesize | |
| 941 emit_rm(cbuf, 0x3, 0x05, RSP_enc); | |
| 942 emit_d8(cbuf, framesize); | |
| 943 if (need_nop) { | |
| 944 emit_opcode(cbuf, 0x90); // nop | |
| 945 } | |
| 946 } else { | |
| 947 emit_opcode(cbuf, 0x81); // sub SP,#framesize | |
| 948 emit_rm(cbuf, 0x3, 0x05, RSP_enc); | |
| 949 emit_d32(cbuf, framesize); | |
| 950 } | |
| 951 } | |
| 952 | |
| 953 C->set_frame_complete(cbuf.code_end() - cbuf.code_begin()); | |
| 954 | |
| 955 #ifdef ASSERT | |
| 956 if (VerifyStackAtCalls) { | |
| 957 Label L; | |
| 958 MacroAssembler masm(&cbuf); | |
| 304 | 959 masm.push(rax); |
| 960 masm.mov(rax, rsp); | |
| 961 masm.andptr(rax, StackAlignmentInBytes-1); | |
| 962 masm.cmpptr(rax, StackAlignmentInBytes-wordSize); | |
| 963 masm.pop(rax); | |
| 0 | 964 masm.jcc(Assembler::equal, L); |
| 965 masm.stop("Stack is not properly aligned!"); | |
| 966 masm.bind(L); | |
| 967 } | |
| 968 #endif | |
| 969 } | |
| 970 | |
| 971 uint MachPrologNode::size(PhaseRegAlloc* ra_) const | |
| 972 { | |
| 973 return MachNode::size(ra_); // too many variables; just compute it | |
| 974 // the hard way | |
| 975 } | |
| 976 | |
| 977 int MachPrologNode::reloc() const | |
| 978 { | |
| 979 return 0; // a large enough number | |
| 980 } | |
| 981 | |
| 982 //============================================================================= | |
| 983 #ifndef PRODUCT | |
| 984 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const | |
| 985 { | |
| 986 Compile* C = ra_->C; | |
| 987 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 988 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 989 // Remove word for return adr already pushed | |
| 990 // and RBP | |
| 991 framesize -= 2*wordSize; | |
| 992 | |
| 993 if (framesize) { | |
| 994 st->print_cr("addq\trsp, %d\t# Destroy frame", framesize); | |
| 995 st->print("\t"); | |
| 996 } | |
| 997 | |
| 998 st->print_cr("popq\trbp"); | |
| 999 if (do_polling() && C->is_method_compilation()) { | |
| 1000 st->print_cr("\ttestl\trax, [rip + #offset_to_poll_page]\t" | |
| 1001 "# Safepoint: poll for GC"); | |
| 1002 st->print("\t"); | |
| 1003 } | |
| 1004 } | |
| 1005 #endif | |
| 1006 | |
| 1007 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const | |
| 1008 { | |
| 1009 Compile* C = ra_->C; | |
| 1010 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 1011 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 1012 // Remove word for return adr already pushed | |
| 1013 // and RBP | |
| 1014 framesize -= 2*wordSize; | |
| 1015 | |
| 1016 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here | |
| 1017 | |
| 1018 if (framesize) { | |
| 1019 emit_opcode(cbuf, Assembler::REX_W); | |
| 1020 if (framesize < 0x80) { | |
| 1021 emit_opcode(cbuf, 0x83); // addq rsp, #framesize | |
| 1022 emit_rm(cbuf, 0x3, 0x00, RSP_enc); | |
| 1023 emit_d8(cbuf, framesize); | |
| 1024 } else { | |
| 1025 emit_opcode(cbuf, 0x81); // addq rsp, #framesize | |
| 1026 emit_rm(cbuf, 0x3, 0x00, RSP_enc); | |
| 1027 emit_d32(cbuf, framesize); | |
| 1028 } | |
| 1029 } | |
| 1030 | |
| 1031 // popq rbp | |
| 1032 emit_opcode(cbuf, 0x58 | RBP_enc); | |
| 1033 | |
| 1034 if (do_polling() && C->is_method_compilation()) { | |
| 1035 // testl %rax, off(%rip) // Opcode + ModRM + Disp32 == 6 bytes | |
| 1036 // XXX reg_mem doesn't support RIP-relative addressing yet | |
| 1037 cbuf.set_inst_mark(); | |
| 1038 cbuf.relocate(cbuf.inst_mark(), relocInfo::poll_return_type, 0); // XXX | |
| 1039 emit_opcode(cbuf, 0x85); // testl | |
| 1040 emit_rm(cbuf, 0x0, RAX_enc, 0x5); // 00 rax 101 == 0x5 | |
| 1041 // cbuf.inst_mark() is beginning of instruction | |
| 1042 emit_d32_reloc(cbuf, os::get_polling_page()); | |
| 1043 // relocInfo::poll_return_type, | |
| 1044 } | |
| 1045 } | |
| 1046 | |
| 1047 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const | |
| 1048 { | |
| 1049 Compile* C = ra_->C; | |
| 1050 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 1051 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 1052 // Remove word for return adr already pushed | |
| 1053 // and RBP | |
| 1054 framesize -= 2*wordSize; | |
| 1055 | |
| 1056 uint size = 0; | |
| 1057 | |
| 1058 if (do_polling() && C->is_method_compilation()) { | |
| 1059 size += 6; | |
| 1060 } | |
| 1061 | |
| 1062 // count popq rbp | |
| 1063 size++; | |
| 1064 | |
| 1065 if (framesize) { | |
| 1066 if (framesize < 0x80) { | |
| 1067 size += 4; | |
| 1068 } else if (framesize) { | |
| 1069 size += 7; | |
| 1070 } | |
| 1071 } | |
| 1072 | |
| 1073 return size; | |
| 1074 } | |
| 1075 | |
| 1076 int MachEpilogNode::reloc() const | |
| 1077 { | |
| 1078 return 2; // a large enough number | |
| 1079 } | |
| 1080 | |
| 1081 const Pipeline* MachEpilogNode::pipeline() const | |
| 1082 { | |
| 1083 return MachNode::pipeline_class(); | |
| 1084 } | |
| 1085 | |
| 1086 int MachEpilogNode::safepoint_offset() const | |
| 1087 { | |
| 1088 return 0; | |
| 1089 } | |
| 1090 | |
| 1091 //============================================================================= | |
| 1092 | |
| 1093 enum RC { | |
| 1094 rc_bad, | |
| 1095 rc_int, | |
| 1096 rc_float, | |
| 1097 rc_stack | |
| 1098 }; | |
| 1099 | |
| 1100 static enum RC rc_class(OptoReg::Name reg) | |
| 1101 { | |
| 1102 if( !OptoReg::is_valid(reg) ) return rc_bad; | |
| 1103 | |
| 1104 if (OptoReg::is_stack(reg)) return rc_stack; | |
| 1105 | |
| 1106 VMReg r = OptoReg::as_VMReg(reg); | |
| 1107 | |
| 1108 if (r->is_Register()) return rc_int; | |
| 1109 | |
| 1110 assert(r->is_XMMRegister(), "must be"); | |
| 1111 return rc_float; | |
| 1112 } | |
| 1113 | |
| 1114 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf, | |
| 1115 PhaseRegAlloc* ra_, | |
| 1116 bool do_size, | |
| 1117 outputStream* st) const | |
| 1118 { | |
| 1119 | |
| 1120 // Get registers to move | |
| 1121 OptoReg::Name src_second = ra_->get_reg_second(in(1)); | |
| 1122 OptoReg::Name src_first = ra_->get_reg_first(in(1)); | |
| 1123 OptoReg::Name dst_second = ra_->get_reg_second(this); | |
| 1124 OptoReg::Name dst_first = ra_->get_reg_first(this); | |
| 1125 | |
| 1126 enum RC src_second_rc = rc_class(src_second); | |
| 1127 enum RC src_first_rc = rc_class(src_first); | |
| 1128 enum RC dst_second_rc = rc_class(dst_second); | |
| 1129 enum RC dst_first_rc = rc_class(dst_first); | |
| 1130 | |
| 1131 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), | |
| 1132 "must move at least 1 register" ); | |
| 1133 | |
| 1134 if (src_first == dst_first && src_second == dst_second) { | |
| 1135 // Self copy, no move | |
| 1136 return 0; | |
| 1137 } else if (src_first_rc == rc_stack) { | |
| 1138 // mem -> | |
| 1139 if (dst_first_rc == rc_stack) { | |
| 1140 // mem -> mem | |
| 1141 assert(src_second != dst_first, "overlap"); | |
| 1142 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1143 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1144 // 64-bit | |
| 1145 int src_offset = ra_->reg2offset(src_first); | |
| 1146 int dst_offset = ra_->reg2offset(dst_first); | |
| 1147 if (cbuf) { | |
| 1148 emit_opcode(*cbuf, 0xFF); | |
| 1149 encode_RegMem(*cbuf, RSI_enc, RSP_enc, 0x4, 0, src_offset, false); | |
| 1150 | |
| 1151 emit_opcode(*cbuf, 0x8F); | |
| 1152 encode_RegMem(*cbuf, RAX_enc, RSP_enc, 0x4, 0, dst_offset, false); | |
| 1153 | |
| 1154 #ifndef PRODUCT | |
| 1155 } else if (!do_size) { | |
| 1156 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t" | |
| 1157 "popq [rsp + #%d]", | |
| 1158 src_offset, | |
| 1159 dst_offset); | |
| 1160 #endif | |
| 1161 } | |
| 1162 return | |
| 1163 3 + ((src_offset == 0) ? 0 : (src_offset < 0x80 ? 1 : 4)) + | |
| 1164 3 + ((dst_offset == 0) ? 0 : (dst_offset < 0x80 ? 1 : 4)); | |
| 1165 } else { | |
| 1166 // 32-bit | |
| 1167 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1168 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1169 // No pushl/popl, so: | |
| 1170 int src_offset = ra_->reg2offset(src_first); | |
| 1171 int dst_offset = ra_->reg2offset(dst_first); | |
| 1172 if (cbuf) { | |
| 1173 emit_opcode(*cbuf, Assembler::REX_W); | |
| 1174 emit_opcode(*cbuf, 0x89); | |
| 1175 emit_opcode(*cbuf, 0x44); | |
| 1176 emit_opcode(*cbuf, 0x24); | |
| 1177 emit_opcode(*cbuf, 0xF8); | |
| 1178 | |
| 1179 emit_opcode(*cbuf, 0x8B); | |
| 1180 encode_RegMem(*cbuf, | |
| 1181 RAX_enc, | |
| 1182 RSP_enc, 0x4, 0, src_offset, | |
| 1183 false); | |
| 1184 | |
| 1185 emit_opcode(*cbuf, 0x89); | |
| 1186 encode_RegMem(*cbuf, | |
| 1187 RAX_enc, | |
| 1188 RSP_enc, 0x4, 0, dst_offset, | |
| 1189 false); | |
| 1190 | |
| 1191 emit_opcode(*cbuf, Assembler::REX_W); | |
| 1192 emit_opcode(*cbuf, 0x8B); | |
| 1193 emit_opcode(*cbuf, 0x44); | |
| 1194 emit_opcode(*cbuf, 0x24); | |
| 1195 emit_opcode(*cbuf, 0xF8); | |
| 1196 | |
| 1197 #ifndef PRODUCT | |
| 1198 } else if (!do_size) { | |
| 1199 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t" | |
| 1200 "movl rax, [rsp + #%d]\n\t" | |
| 1201 "movl [rsp + #%d], rax\n\t" | |
| 1202 "movq rax, [rsp - #8]", | |
| 1203 src_offset, | |
| 1204 dst_offset); | |
| 1205 #endif | |
| 1206 } | |
| 1207 return | |
| 1208 5 + // movq | |
| 1209 3 + ((src_offset == 0) ? 0 : (src_offset < 0x80 ? 1 : 4)) + // movl | |
| 1210 3 + ((dst_offset == 0) ? 0 : (dst_offset < 0x80 ? 1 : 4)) + // movl | |
| 1211 5; // movq | |
| 1212 } | |
| 1213 } else if (dst_first_rc == rc_int) { | |
| 1214 // mem -> gpr | |
| 1215 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1216 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1217 // 64-bit | |
| 1218 int offset = ra_->reg2offset(src_first); | |
| 1219 if (cbuf) { | |
| 1220 if (Matcher::_regEncode[dst_first] < 8) { | |
| 1221 emit_opcode(*cbuf, Assembler::REX_W); | |
| 1222 } else { | |
| 1223 emit_opcode(*cbuf, Assembler::REX_WR); | |
| 1224 } | |
| 1225 emit_opcode(*cbuf, 0x8B); | |
| 1226 encode_RegMem(*cbuf, | |
| 1227 Matcher::_regEncode[dst_first], | |
| 1228 RSP_enc, 0x4, 0, offset, | |
| 1229 false); | |
| 1230 #ifndef PRODUCT | |
| 1231 } else if (!do_size) { | |
| 1232 st->print("movq %s, [rsp + #%d]\t# spill", | |
| 1233 Matcher::regName[dst_first], | |
| 1234 offset); | |
| 1235 #endif | |
| 1236 } | |
| 1237 return | |
| 1238 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + 4; // REX | |
| 1239 } else { | |
| 1240 // 32-bit | |
| 1241 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1242 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1243 int offset = ra_->reg2offset(src_first); | |
| 1244 if (cbuf) { | |
| 1245 if (Matcher::_regEncode[dst_first] >= 8) { | |
| 1246 emit_opcode(*cbuf, Assembler::REX_R); | |
| 1247 } | |
| 1248 emit_opcode(*cbuf, 0x8B); | |
| 1249 encode_RegMem(*cbuf, | |
| 1250 Matcher::_regEncode[dst_first], | |
| 1251 RSP_enc, 0x4, 0, offset, | |
| 1252 false); | |
| 1253 #ifndef PRODUCT | |
| 1254 } else if (!do_size) { | |
| 1255 st->print("movl %s, [rsp + #%d]\t# spill", | |
| 1256 Matcher::regName[dst_first], | |
| 1257 offset); | |
| 1258 #endif | |
| 1259 } | |
| 1260 return | |
| 1261 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + | |
| 1262 ((Matcher::_regEncode[dst_first] < 8) | |
| 1263 ? 3 | |
| 1264 : 4); // REX | |
| 1265 } | |
| 1266 } else if (dst_first_rc == rc_float) { | |
| 1267 // mem-> xmm | |
| 1268 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1269 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1270 // 64-bit | |
| 1271 int offset = ra_->reg2offset(src_first); | |
| 1272 if (cbuf) { | |
| 1273 emit_opcode(*cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66); | |
| 1274 if (Matcher::_regEncode[dst_first] >= 8) { | |
| 1275 emit_opcode(*cbuf, Assembler::REX_R); | |
| 1276 } | |
| 1277 emit_opcode(*cbuf, 0x0F); | |
| 1278 emit_opcode(*cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12); | |
| 1279 encode_RegMem(*cbuf, | |
| 1280 Matcher::_regEncode[dst_first], | |
| 1281 RSP_enc, 0x4, 0, offset, | |
| 1282 false); | |
| 1283 #ifndef PRODUCT | |
| 1284 } else if (!do_size) { | |
| 1285 st->print("%s %s, [rsp + #%d]\t# spill", | |
| 1286 UseXmmLoadAndClearUpper ? "movsd " : "movlpd", | |
| 1287 Matcher::regName[dst_first], | |
| 1288 offset); | |
| 1289 #endif | |
| 1290 } | |
| 1291 return | |
| 1292 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + | |
| 1293 ((Matcher::_regEncode[dst_first] < 8) | |
| 1294 ? 5 | |
| 1295 : 6); // REX | |
| 1296 } else { | |
| 1297 // 32-bit | |
| 1298 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1299 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1300 int offset = ra_->reg2offset(src_first); | |
| 1301 if (cbuf) { | |
| 1302 emit_opcode(*cbuf, 0xF3); | |
| 1303 if (Matcher::_regEncode[dst_first] >= 8) { | |
| 1304 emit_opcode(*cbuf, Assembler::REX_R); | |
| 1305 } | |
| 1306 emit_opcode(*cbuf, 0x0F); | |
| 1307 emit_opcode(*cbuf, 0x10); | |
| 1308 encode_RegMem(*cbuf, | |
| 1309 Matcher::_regEncode[dst_first], | |
| 1310 RSP_enc, 0x4, 0, offset, | |
| 1311 false); | |
| 1312 #ifndef PRODUCT | |
| 1313 } else if (!do_size) { | |
| 1314 st->print("movss %s, [rsp + #%d]\t# spill", | |
| 1315 Matcher::regName[dst_first], | |
| 1316 offset); | |
| 1317 #endif | |
| 1318 } | |
| 1319 return | |
| 1320 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + | |
| 1321 ((Matcher::_regEncode[dst_first] < 8) | |
| 1322 ? 5 | |
| 1323 : 6); // REX | |
| 1324 } | |
| 1325 } | |
| 1326 } else if (src_first_rc == rc_int) { | |
| 1327 // gpr -> | |
| 1328 if (dst_first_rc == rc_stack) { | |
| 1329 // gpr -> mem | |
| 1330 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1331 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1332 // 64-bit | |
| 1333 int offset = ra_->reg2offset(dst_first); | |
| 1334 if (cbuf) { | |
| 1335 if (Matcher::_regEncode[src_first] < 8) { | |
| 1336 emit_opcode(*cbuf, Assembler::REX_W); | |
| 1337 } else { | |
| 1338 emit_opcode(*cbuf, Assembler::REX_WR); | |
| 1339 } | |
| 1340 emit_opcode(*cbuf, 0x89); | |
| 1341 encode_RegMem(*cbuf, | |
| 1342 Matcher::_regEncode[src_first], | |
| 1343 RSP_enc, 0x4, 0, offset, | |
| 1344 false); | |
| 1345 #ifndef PRODUCT | |
| 1346 } else if (!do_size) { | |
| 1347 st->print("movq [rsp + #%d], %s\t# spill", | |
| 1348 offset, | |
| 1349 Matcher::regName[src_first]); | |
| 1350 #endif | |
| 1351 } | |
| 1352 return ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + 4; // REX | |
| 1353 } else { | |
| 1354 // 32-bit | |
| 1355 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1356 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1357 int offset = ra_->reg2offset(dst_first); | |
| 1358 if (cbuf) { | |
| 1359 if (Matcher::_regEncode[src_first] >= 8) { | |
| 1360 emit_opcode(*cbuf, Assembler::REX_R); | |
| 1361 } | |
| 1362 emit_opcode(*cbuf, 0x89); | |
| 1363 encode_RegMem(*cbuf, | |
| 1364 Matcher::_regEncode[src_first], | |
| 1365 RSP_enc, 0x4, 0, offset, | |
| 1366 false); | |
| 1367 #ifndef PRODUCT | |
| 1368 } else if (!do_size) { | |
| 1369 st->print("movl [rsp + #%d], %s\t# spill", | |
| 1370 offset, | |
| 1371 Matcher::regName[src_first]); | |
| 1372 #endif | |
| 1373 } | |
| 1374 return | |
| 1375 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + | |
| 1376 ((Matcher::_regEncode[src_first] < 8) | |
| 1377 ? 3 | |
| 1378 : 4); // REX | |
| 1379 } | |
| 1380 } else if (dst_first_rc == rc_int) { | |
| 1381 // gpr -> gpr | |
| 1382 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1383 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1384 // 64-bit | |
| 1385 if (cbuf) { | |
| 1386 if (Matcher::_regEncode[dst_first] < 8) { | |
| 1387 if (Matcher::_regEncode[src_first] < 8) { | |
| 1388 emit_opcode(*cbuf, Assembler::REX_W); | |
| 1389 } else { | |
| 1390 emit_opcode(*cbuf, Assembler::REX_WB); | |
| 1391 } | |
| 1392 } else { | |
| 1393 if (Matcher::_regEncode[src_first] < 8) { | |
| 1394 emit_opcode(*cbuf, Assembler::REX_WR); | |
| 1395 } else { | |
| 1396 emit_opcode(*cbuf, Assembler::REX_WRB); | |
| 1397 } | |
| 1398 } | |
| 1399 emit_opcode(*cbuf, 0x8B); | |
| 1400 emit_rm(*cbuf, 0x3, | |
| 1401 Matcher::_regEncode[dst_first] & 7, | |
| 1402 Matcher::_regEncode[src_first] & 7); | |
| 1403 #ifndef PRODUCT | |
| 1404 } else if (!do_size) { | |
| 1405 st->print("movq %s, %s\t# spill", | |
| 1406 Matcher::regName[dst_first], | |
| 1407 Matcher::regName[src_first]); | |
| 1408 #endif | |
| 1409 } | |
| 1410 return 3; // REX | |
| 1411 } else { | |
| 1412 // 32-bit | |
| 1413 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1414 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1415 if (cbuf) { | |
| 1416 if (Matcher::_regEncode[dst_first] < 8) { | |
| 1417 if (Matcher::_regEncode[src_first] >= 8) { | |
| 1418 emit_opcode(*cbuf, Assembler::REX_B); | |
| 1419 } | |
| 1420 } else { | |
| 1421 if (Matcher::_regEncode[src_first] < 8) { | |
| 1422 emit_opcode(*cbuf, Assembler::REX_R); | |
| 1423 } else { | |
| 1424 emit_opcode(*cbuf, Assembler::REX_RB); | |
| 1425 } | |
| 1426 } | |
| 1427 emit_opcode(*cbuf, 0x8B); | |
| 1428 emit_rm(*cbuf, 0x3, | |
| 1429 Matcher::_regEncode[dst_first] & 7, | |
| 1430 Matcher::_regEncode[src_first] & 7); | |
| 1431 #ifndef PRODUCT | |
| 1432 } else if (!do_size) { | |
| 1433 st->print("movl %s, %s\t# spill", | |
| 1434 Matcher::regName[dst_first], | |
| 1435 Matcher::regName[src_first]); | |
| 1436 #endif | |
| 1437 } | |
| 1438 return | |
| 1439 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8) | |
| 1440 ? 2 | |
| 1441 : 3; // REX | |
| 1442 } | |
| 1443 } else if (dst_first_rc == rc_float) { | |
| 1444 // gpr -> xmm | |
| 1445 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1446 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1447 // 64-bit | |
| 1448 if (cbuf) { | |
| 1449 emit_opcode(*cbuf, 0x66); | |
| 1450 if (Matcher::_regEncode[dst_first] < 8) { | |
| 1451 if (Matcher::_regEncode[src_first] < 8) { | |
| 1452 emit_opcode(*cbuf, Assembler::REX_W); | |
| 1453 } else { | |
| 1454 emit_opcode(*cbuf, Assembler::REX_WB); | |
| 1455 } | |
| 1456 } else { | |
| 1457 if (Matcher::_regEncode[src_first] < 8) { | |
| 1458 emit_opcode(*cbuf, Assembler::REX_WR); | |
| 1459 } else { | |
| 1460 emit_opcode(*cbuf, Assembler::REX_WRB); | |
| 1461 } | |
| 1462 } | |
| 1463 emit_opcode(*cbuf, 0x0F); | |
| 1464 emit_opcode(*cbuf, 0x6E); | |
| 1465 emit_rm(*cbuf, 0x3, | |
| 1466 Matcher::_regEncode[dst_first] & 7, | |
| 1467 Matcher::_regEncode[src_first] & 7); | |
| 1468 #ifndef PRODUCT | |
| 1469 } else if (!do_size) { | |
| 1470 st->print("movdq %s, %s\t# spill", | |
| 1471 Matcher::regName[dst_first], | |
| 1472 Matcher::regName[src_first]); | |
| 1473 #endif | |
| 1474 } | |
| 1475 return 5; // REX | |
| 1476 } else { | |
| 1477 // 32-bit | |
| 1478 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1479 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1480 if (cbuf) { | |
| 1481 emit_opcode(*cbuf, 0x66); | |
| 1482 if (Matcher::_regEncode[dst_first] < 8) { | |
| 1483 if (Matcher::_regEncode[src_first] >= 8) { | |
| 1484 emit_opcode(*cbuf, Assembler::REX_B); | |
| 1485 } | |
| 1486 } else { | |
| 1487 if (Matcher::_regEncode[src_first] < 8) { | |
| 1488 emit_opcode(*cbuf, Assembler::REX_R); | |
| 1489 } else { | |
| 1490 emit_opcode(*cbuf, Assembler::REX_RB); | |
| 1491 } | |
| 1492 } | |
| 1493 emit_opcode(*cbuf, 0x0F); | |
| 1494 emit_opcode(*cbuf, 0x6E); | |
| 1495 emit_rm(*cbuf, 0x3, | |
| 1496 Matcher::_regEncode[dst_first] & 7, | |
| 1497 Matcher::_regEncode[src_first] & 7); | |
| 1498 #ifndef PRODUCT | |
| 1499 } else if (!do_size) { | |
| 1500 st->print("movdl %s, %s\t# spill", | |
| 1501 Matcher::regName[dst_first], | |
| 1502 Matcher::regName[src_first]); | |
| 1503 #endif | |
| 1504 } | |
| 1505 return | |
| 1506 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8) | |
| 1507 ? 4 | |
| 1508 : 5; // REX | |
| 1509 } | |
| 1510 } | |
| 1511 } else if (src_first_rc == rc_float) { | |
| 1512 // xmm -> | |
| 1513 if (dst_first_rc == rc_stack) { | |
| 1514 // xmm -> mem | |
| 1515 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1516 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1517 // 64-bit | |
| 1518 int offset = ra_->reg2offset(dst_first); | |
| 1519 if (cbuf) { | |
| 1520 emit_opcode(*cbuf, 0xF2); | |
| 1521 if (Matcher::_regEncode[src_first] >= 8) { | |
| 1522 emit_opcode(*cbuf, Assembler::REX_R); | |
| 1523 } | |
| 1524 emit_opcode(*cbuf, 0x0F); | |
| 1525 emit_opcode(*cbuf, 0x11); | |
| 1526 encode_RegMem(*cbuf, | |
| 1527 Matcher::_regEncode[src_first], | |
| 1528 RSP_enc, 0x4, 0, offset, | |
| 1529 false); | |
| 1530 #ifndef PRODUCT | |
| 1531 } else if (!do_size) { | |
| 1532 st->print("movsd [rsp + #%d], %s\t# spill", | |
| 1533 offset, | |
| 1534 Matcher::regName[src_first]); | |
| 1535 #endif | |
| 1536 } | |
| 1537 return | |
| 1538 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + | |
| 1539 ((Matcher::_regEncode[src_first] < 8) | |
| 1540 ? 5 | |
| 1541 : 6); // REX | |
| 1542 } else { | |
| 1543 // 32-bit | |
| 1544 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1545 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1546 int offset = ra_->reg2offset(dst_first); | |
| 1547 if (cbuf) { | |
| 1548 emit_opcode(*cbuf, 0xF3); | |
| 1549 if (Matcher::_regEncode[src_first] >= 8) { | |
| 1550 emit_opcode(*cbuf, Assembler::REX_R); | |
| 1551 } | |
| 1552 emit_opcode(*cbuf, 0x0F); | |
| 1553 emit_opcode(*cbuf, 0x11); | |
| 1554 encode_RegMem(*cbuf, | |
| 1555 Matcher::_regEncode[src_first], | |
| 1556 RSP_enc, 0x4, 0, offset, | |
| 1557 false); | |
| 1558 #ifndef PRODUCT | |
| 1559 } else if (!do_size) { | |
| 1560 st->print("movss [rsp + #%d], %s\t# spill", | |
| 1561 offset, | |
| 1562 Matcher::regName[src_first]); | |
| 1563 #endif | |
| 1564 } | |
| 1565 return | |
| 1566 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + | |
| 1567 ((Matcher::_regEncode[src_first] < 8) | |
| 1568 ? 5 | |
| 1569 : 6); // REX | |
| 1570 } | |
| 1571 } else if (dst_first_rc == rc_int) { | |
| 1572 // xmm -> gpr | |
| 1573 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1574 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1575 // 64-bit | |
| 1576 if (cbuf) { | |
| 1577 emit_opcode(*cbuf, 0x66); | |
| 1578 if (Matcher::_regEncode[dst_first] < 8) { | |
| 1579 if (Matcher::_regEncode[src_first] < 8) { | |
| 1580 emit_opcode(*cbuf, Assembler::REX_W); | |
| 1581 } else { | |
| 1582 emit_opcode(*cbuf, Assembler::REX_WR); // attention! | |
| 1583 } | |
| 1584 } else { | |
| 1585 if (Matcher::_regEncode[src_first] < 8) { | |
| 1586 emit_opcode(*cbuf, Assembler::REX_WB); // attention! | |
| 1587 } else { | |
| 1588 emit_opcode(*cbuf, Assembler::REX_WRB); | |
| 1589 } | |
| 1590 } | |
| 1591 emit_opcode(*cbuf, 0x0F); | |
| 1592 emit_opcode(*cbuf, 0x7E); | |
| 1593 emit_rm(*cbuf, 0x3, | |
| 1594 Matcher::_regEncode[dst_first] & 7, | |
| 1595 Matcher::_regEncode[src_first] & 7); | |
| 1596 #ifndef PRODUCT | |
| 1597 } else if (!do_size) { | |
| 1598 st->print("movdq %s, %s\t# spill", | |
| 1599 Matcher::regName[dst_first], | |
| 1600 Matcher::regName[src_first]); | |
| 1601 #endif | |
| 1602 } | |
| 1603 return 5; // REX | |
| 1604 } else { | |
| 1605 // 32-bit | |
| 1606 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1607 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1608 if (cbuf) { | |
| 1609 emit_opcode(*cbuf, 0x66); | |
| 1610 if (Matcher::_regEncode[dst_first] < 8) { | |
| 1611 if (Matcher::_regEncode[src_first] >= 8) { | |
| 1612 emit_opcode(*cbuf, Assembler::REX_R); // attention! | |
| 1613 } | |
| 1614 } else { | |
| 1615 if (Matcher::_regEncode[src_first] < 8) { | |
| 1616 emit_opcode(*cbuf, Assembler::REX_B); // attention! | |
| 1617 } else { | |
| 1618 emit_opcode(*cbuf, Assembler::REX_RB); | |
| 1619 } | |
| 1620 } | |
| 1621 emit_opcode(*cbuf, 0x0F); | |
| 1622 emit_opcode(*cbuf, 0x7E); | |
| 1623 emit_rm(*cbuf, 0x3, | |
| 1624 Matcher::_regEncode[dst_first] & 7, | |
| 1625 Matcher::_regEncode[src_first] & 7); | |
| 1626 #ifndef PRODUCT | |
| 1627 } else if (!do_size) { | |
| 1628 st->print("movdl %s, %s\t# spill", | |
| 1629 Matcher::regName[dst_first], | |
| 1630 Matcher::regName[src_first]); | |
| 1631 #endif | |
| 1632 } | |
| 1633 return | |
| 1634 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8) | |
| 1635 ? 4 | |
| 1636 : 5; // REX | |
| 1637 } | |
| 1638 } else if (dst_first_rc == rc_float) { | |
| 1639 // xmm -> xmm | |
| 1640 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1641 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1642 // 64-bit | |
| 1643 if (cbuf) { | |
| 1644 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x66 : 0xF2); | |
| 1645 if (Matcher::_regEncode[dst_first] < 8) { | |
| 1646 if (Matcher::_regEncode[src_first] >= 8) { | |
| 1647 emit_opcode(*cbuf, Assembler::REX_B); | |
| 1648 } | |
| 1649 } else { | |
| 1650 if (Matcher::_regEncode[src_first] < 8) { | |
| 1651 emit_opcode(*cbuf, Assembler::REX_R); | |
| 1652 } else { | |
| 1653 emit_opcode(*cbuf, Assembler::REX_RB); | |
| 1654 } | |
| 1655 } | |
| 1656 emit_opcode(*cbuf, 0x0F); | |
| 1657 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10); | |
| 1658 emit_rm(*cbuf, 0x3, | |
| 1659 Matcher::_regEncode[dst_first] & 7, | |
| 1660 Matcher::_regEncode[src_first] & 7); | |
| 1661 #ifndef PRODUCT | |
| 1662 } else if (!do_size) { | |
| 1663 st->print("%s %s, %s\t# spill", | |
| 1664 UseXmmRegToRegMoveAll ? "movapd" : "movsd ", | |
| 1665 Matcher::regName[dst_first], | |
| 1666 Matcher::regName[src_first]); | |
| 1667 #endif | |
| 1668 } | |
| 1669 return | |
| 1670 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8) | |
| 1671 ? 4 | |
| 1672 : 5; // REX | |
| 1673 } else { | |
| 1674 // 32-bit | |
| 1675 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1676 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1677 if (cbuf) { | |
| 1678 if (!UseXmmRegToRegMoveAll) | |
| 1679 emit_opcode(*cbuf, 0xF3); | |
| 1680 if (Matcher::_regEncode[dst_first] < 8) { | |
| 1681 if (Matcher::_regEncode[src_first] >= 8) { | |
| 1682 emit_opcode(*cbuf, Assembler::REX_B); | |
| 1683 } | |
| 1684 } else { | |
| 1685 if (Matcher::_regEncode[src_first] < 8) { | |
| 1686 emit_opcode(*cbuf, Assembler::REX_R); | |
| 1687 } else { | |
| 1688 emit_opcode(*cbuf, Assembler::REX_RB); | |
| 1689 } | |
| 1690 } | |
| 1691 emit_opcode(*cbuf, 0x0F); | |
| 1692 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10); | |
| 1693 emit_rm(*cbuf, 0x3, | |
| 1694 Matcher::_regEncode[dst_first] & 7, | |
| 1695 Matcher::_regEncode[src_first] & 7); | |
| 1696 #ifndef PRODUCT | |
| 1697 } else if (!do_size) { | |
| 1698 st->print("%s %s, %s\t# spill", | |
| 1699 UseXmmRegToRegMoveAll ? "movaps" : "movss ", | |
| 1700 Matcher::regName[dst_first], | |
| 1701 Matcher::regName[src_first]); | |
| 1702 #endif | |
| 1703 } | |
| 1704 return | |
| 1705 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8) | |
| 1706 ? (UseXmmRegToRegMoveAll ? 3 : 4) | |
| 1707 : (UseXmmRegToRegMoveAll ? 4 : 5); // REX | |
| 1708 } | |
| 1709 } | |
| 1710 } | |
| 1711 | |
| 1712 assert(0," foo "); | |
| 1713 Unimplemented(); | |
| 1714 | |
| 1715 return 0; | |
| 1716 } | |
| 1717 | |
| 1718 #ifndef PRODUCT | |
| 1719 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const | |
| 1720 { | |
| 1721 implementation(NULL, ra_, false, st); | |
| 1722 } | |
| 1723 #endif | |
| 1724 | |
| 1725 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const | |
| 1726 { | |
| 1727 implementation(&cbuf, ra_, false, NULL); | |
| 1728 } | |
| 1729 | |
| 1730 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const | |
| 1731 { | |
| 1732 return implementation(NULL, ra_, true, NULL); | |
| 1733 } | |
| 1734 | |
| 1735 //============================================================================= | |
| 1736 #ifndef PRODUCT | |
| 1737 void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const | |
| 1738 { | |
| 1739 st->print("nop \t# %d bytes pad for loops and calls", _count); | |
| 1740 } | |
| 1741 #endif | |
| 1742 | |
| 1743 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const | |
| 1744 { | |
| 1745 MacroAssembler _masm(&cbuf); | |
| 1746 __ nop(_count); | |
| 1747 } | |
| 1748 | |
| 1749 uint MachNopNode::size(PhaseRegAlloc*) const | |
| 1750 { | |
| 1751 return _count; | |
| 1752 } | |
| 1753 | |
| 1754 | |
| 1755 //============================================================================= | |
| 1756 #ifndef PRODUCT | |
| 1757 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const | |
| 1758 { | |
| 1759 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1760 int reg = ra_->get_reg_first(this); | |
| 1761 st->print("leaq %s, [rsp + #%d]\t# box lock", | |
| 1762 Matcher::regName[reg], offset); | |
| 1763 } | |
| 1764 #endif | |
| 1765 | |
| 1766 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const | |
| 1767 { | |
| 1768 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1769 int reg = ra_->get_encode(this); | |
| 1770 if (offset >= 0x80) { | |
| 1771 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR); | |
| 1772 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1773 emit_rm(cbuf, 0x2, reg & 7, 0x04); | |
| 1774 emit_rm(cbuf, 0x0, 0x04, RSP_enc); | |
| 1775 emit_d32(cbuf, offset); | |
| 1776 } else { | |
| 1777 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR); | |
| 1778 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1779 emit_rm(cbuf, 0x1, reg & 7, 0x04); | |
| 1780 emit_rm(cbuf, 0x0, 0x04, RSP_enc); | |
| 1781 emit_d8(cbuf, offset); | |
| 1782 } | |
| 1783 } | |
| 1784 | |
| 1785 uint BoxLockNode::size(PhaseRegAlloc *ra_) const | |
| 1786 { | |
| 1787 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1788 return (offset < 0x80) ? 5 : 8; // REX | |
| 1789 } | |
| 1790 | |
| 1791 //============================================================================= | |
| 1792 | |
| 1793 // emit call stub, compiled java to interpreter | |
| 1794 void emit_java_to_interp(CodeBuffer& cbuf) | |
| 1795 { | |
| 1796 // Stub is fixed up when the corresponding call is converted from | |
| 1797 // calling compiled code to calling interpreted code. | |
| 1798 // movq rbx, 0 | |
| 1799 // jmp -5 # to self | |
| 1800 | |
| 1801 address mark = cbuf.inst_mark(); // get mark within main instrs section | |
| 1802 | |
| 1803 // Note that the code buffer's inst_mark is always relative to insts. | |
| 1804 // That's why we must use the macroassembler to generate a stub. | |
| 1805 MacroAssembler _masm(&cbuf); | |
| 1806 | |
| 1807 address base = | |
| 1808 __ start_a_stub(Compile::MAX_stubs_size); | |
| 1809 if (base == NULL) return; // CodeBuffer::expand failed | |
| 1810 // static stub relocation stores the instruction address of the call | |
| 1811 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM64); | |
| 1812 // static stub relocation also tags the methodOop in the code-stream. | |
| 1813 __ movoop(rbx, (jobject) NULL); // method is zapped till fixup time | |
| 304 | 1814 // This is recognized as unresolved by relocs/nativeinst/ic code |
| 0 | 1815 __ jump(RuntimeAddress(__ pc())); |
| 1816 | |
| 1817 // Update current stubs pointer and restore code_end. | |
| 1818 __ end_a_stub(); | |
| 1819 } | |
| 1820 | |
| 1821 // size of call stub, compiled java to interpretor | |
| 1822 uint size_java_to_interp() | |
| 1823 { | |
| 1824 return 15; // movq (1+1+8); jmp (1+4) | |
| 1825 } | |
| 1826 | |
| 1827 // relocation entries for call stub, compiled java to interpretor | |
| 1828 uint reloc_java_to_interp() | |
| 1829 { | |
| 1830 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call | |
| 1831 } | |
| 1832 | |
| 1833 //============================================================================= | |
| 1834 #ifndef PRODUCT | |
| 1835 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const | |
| 1836 { | |
|
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1837 if (UseCompressedOops) { |
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1838 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes() #%d]\t", oopDesc::klass_offset_in_bytes()); |
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1839 if (Universe::narrow_oop_shift() != 0) { |
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1840 st->print_cr("leaq rscratch1, [r12_heapbase, r, Address::times_8, 0]"); |
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1841 } |
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1842 st->print_cr("cmpq rax, rscratch1\t # Inline cache check"); |
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1843 } else { |
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1844 st->print_cr("cmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes() #%d]\t" |
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1845 "# Inline cache check", oopDesc::klass_offset_in_bytes()); |
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1846 } |
| 0 | 1847 st->print_cr("\tjne SharedRuntime::_ic_miss_stub"); |
| 1848 st->print_cr("\tnop"); | |
| 1849 if (!OptoBreakpoint) { | |
| 1850 st->print_cr("\tnop"); | |
| 1851 } | |
| 1852 } | |
| 1853 #endif | |
| 1854 | |
| 1855 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const | |
| 1856 { | |
| 1857 MacroAssembler masm(&cbuf); | |
| 1858 #ifdef ASSERT | |
| 1859 uint code_size = cbuf.code_size(); | |
| 1860 #endif | |
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1861 if (UseCompressedOops) { |
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1862 masm.load_klass(rscratch1, j_rarg0); |
| 304 | 1863 masm.cmpptr(rax, rscratch1); |
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1864 } else { |
| 304 | 1865 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes())); |
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1866 } |
| 0 | 1867 |
| 1868 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub())); | |
| 1869 | |
| 1870 /* WARNING these NOPs are critical so that verified entry point is properly | |
| 1871 aligned for patching by NativeJump::patch_verified_entry() */ | |
| 1872 int nops_cnt = 1; | |
| 1873 if (!OptoBreakpoint) { | |
| 1874 // Leave space for int3 | |
| 1875 nops_cnt += 1; | |
| 1876 } | |
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1877 if (UseCompressedOops) { |
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1878 // ??? divisible by 4 is aligned? |
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1879 nops_cnt += 1; |
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1880 } |
| 0 | 1881 masm.nop(nops_cnt); |
| 1882 | |
| 1883 assert(cbuf.code_size() - code_size == size(ra_), | |
| 1884 "checking code size of inline cache node"); | |
| 1885 } | |
| 1886 | |
| 1887 uint MachUEPNode::size(PhaseRegAlloc* ra_) const | |
| 1888 { | |
|
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1889 if (UseCompressedOops) { |
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1890 if (Universe::narrow_oop_shift() == 0) { |
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1891 return OptoBreakpoint ? 15 : 16; |
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1892 } else { |
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1893 return OptoBreakpoint ? 19 : 20; |
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1894 } |
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1895 } else { |
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1896 return OptoBreakpoint ? 11 : 12; |
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1897 } |
| 0 | 1898 } |
| 1899 | |
| 1900 | |
| 1901 //============================================================================= | |
| 1902 uint size_exception_handler() | |
| 1903 { | |
| 1904 // NativeCall instruction size is the same as NativeJump. | |
| 1905 // Note that this value is also credited (in output.cpp) to | |
| 1906 // the size of the code section. | |
| 1907 return NativeJump::instruction_size; | |
| 1908 } | |
| 1909 | |
| 1910 // Emit exception handler code. | |
| 1911 int emit_exception_handler(CodeBuffer& cbuf) | |
| 1912 { | |
| 1913 | |
| 1914 // Note that the code buffer's inst_mark is always relative to insts. | |
| 1915 // That's why we must use the macroassembler to generate a handler. | |
| 1916 MacroAssembler _masm(&cbuf); | |
| 1917 address base = | |
| 1918 __ start_a_stub(size_exception_handler()); | |
| 1919 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1920 int offset = __ offset(); | |
| 1921 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->instructions_begin())); | |
| 1922 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); | |
| 1923 __ end_a_stub(); | |
| 1924 return offset; | |
| 1925 } | |
| 1926 | |
| 1927 uint size_deopt_handler() | |
| 1928 { | |
| 1929 // three 5 byte instructions | |
| 1930 return 15; | |
| 1931 } | |
| 1932 | |
| 1933 // Emit deopt handler code. | |
| 1934 int emit_deopt_handler(CodeBuffer& cbuf) | |
| 1935 { | |
| 1936 | |
| 1937 // Note that the code buffer's inst_mark is always relative to insts. | |
| 1938 // That's why we must use the macroassembler to generate a handler. | |
| 1939 MacroAssembler _masm(&cbuf); | |
| 1940 address base = | |
| 1941 __ start_a_stub(size_deopt_handler()); | |
| 1942 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1943 int offset = __ offset(); | |
| 1944 address the_pc = (address) __ pc(); | |
| 1945 Label next; | |
| 1946 // push a "the_pc" on the stack without destroying any registers | |
| 1947 // as they all may be live. | |
| 1948 | |
| 1949 // push address of "next" | |
| 1950 __ call(next, relocInfo::none); // reloc none is fine since it is a disp32 | |
| 1951 __ bind(next); | |
| 1952 // adjust it so it matches "the_pc" | |
| 304 | 1953 __ subptr(Address(rsp, 0), __ offset() - offset); |
| 0 | 1954 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); |
| 1955 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); | |
| 1956 __ end_a_stub(); | |
| 1957 return offset; | |
| 1958 } | |
| 1959 | |
| 1960 static void emit_double_constant(CodeBuffer& cbuf, double x) { | |
| 1961 int mark = cbuf.insts()->mark_off(); | |
| 1962 MacroAssembler _masm(&cbuf); | |
| 1963 address double_address = __ double_constant(x); | |
| 1964 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift | |
| 1965 emit_d32_reloc(cbuf, | |
| 1966 (int) (double_address - cbuf.code_end() - 4), | |
| 1967 internal_word_Relocation::spec(double_address), | |
| 1968 RELOC_DISP32); | |
| 1969 } | |
| 1970 | |
| 1971 static void emit_float_constant(CodeBuffer& cbuf, float x) { | |
| 1972 int mark = cbuf.insts()->mark_off(); | |
| 1973 MacroAssembler _masm(&cbuf); | |
| 1974 address float_address = __ float_constant(x); | |
| 1975 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift | |
| 1976 emit_d32_reloc(cbuf, | |
| 1977 (int) (float_address - cbuf.code_end() - 4), | |
| 1978 internal_word_Relocation::spec(float_address), | |
| 1979 RELOC_DISP32); | |
| 1980 } | |
| 1981 | |
| 1982 | |
| 1983 int Matcher::regnum_to_fpu_offset(int regnum) | |
| 1984 { | |
| 1985 return regnum - 32; // The FP registers are in the second chunk | |
| 1986 } | |
| 1987 | |
| 1988 // This is UltraSparc specific, true just means we have fast l2f conversion | |
| 1989 const bool Matcher::convL2FSupported(void) { | |
| 1990 return true; | |
| 1991 } | |
| 1992 | |
| 1993 // Vector width in bytes | |
| 1994 const uint Matcher::vector_width_in_bytes(void) { | |
| 1995 return 8; | |
| 1996 } | |
| 1997 | |
| 1998 // Vector ideal reg | |
| 1999 const uint Matcher::vector_ideal_reg(void) { | |
| 2000 return Op_RegD; | |
| 2001 } | |
| 2002 | |
| 2003 // Is this branch offset short enough that a short branch can be used? | |
| 2004 // | |
| 2005 // NOTE: If the platform does not provide any short branch variants, then | |
| 2006 // this method should return false for offset 0. | |
|
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2007 bool Matcher::is_short_branch_offset(int rule, int offset) { |
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2008 // the short version of jmpConUCF2 contains multiple branches, |
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2009 // making the reach slightly less |
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2010 if (rule == jmpConUCF2_rule) |
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2011 return (-126 <= offset && offset <= 125); |
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2012 return (-128 <= offset && offset <= 127); |
| 0 | 2013 } |
| 2014 | |
| 2015 const bool Matcher::isSimpleConstant64(jlong value) { | |
| 2016 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. | |
| 2017 //return value == (int) value; // Cf. storeImmL and immL32. | |
| 2018 | |
| 2019 // Probably always true, even if a temp register is required. | |
| 2020 return true; | |
| 2021 } | |
| 2022 | |
| 2023 // The ecx parameter to rep stosq for the ClearArray node is in words. | |
| 2024 const bool Matcher::init_array_count_is_in_bytes = false; | |
| 2025 | |
| 2026 // Threshold size for cleararray. | |
| 2027 const int Matcher::init_array_short_size = 8 * BytesPerLong; | |
| 2028 | |
| 2029 // Should the Matcher clone shifts on addressing modes, expecting them | |
| 2030 // to be subsumed into complex addressing expressions or compute them | |
| 2031 // into registers? True for Intel but false for most RISCs | |
| 2032 const bool Matcher::clone_shift_expressions = true; | |
| 2033 | |
| 2034 // Is it better to copy float constants, or load them directly from | |
| 2035 // memory? Intel can load a float constant from a direct address, | |
| 2036 // requiring no extra registers. Most RISCs will have to materialize | |
| 2037 // an address into a register first, so they would do better to copy | |
| 2038 // the constant from stack. | |
| 2039 const bool Matcher::rematerialize_float_constants = true; // XXX | |
| 2040 | |
| 2041 // If CPU can load and store mis-aligned doubles directly then no | |
| 2042 // fixup is needed. Else we split the double into 2 integer pieces | |
| 2043 // and move it piece-by-piece. Only happens when passing doubles into | |
| 2044 // C code as the Java calling convention forces doubles to be aligned. | |
| 2045 const bool Matcher::misaligned_doubles_ok = true; | |
| 2046 | |
| 2047 // No-op on amd64 | |
| 2048 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {} | |
| 2049 | |
| 2050 // Advertise here if the CPU requires explicit rounding operations to | |
| 2051 // implement the UseStrictFP mode. | |
| 2052 const bool Matcher::strict_fp_requires_explicit_rounding = true; | |
| 2053 | |
| 2054 // Do floats take an entire double register or just half? | |
| 2055 const bool Matcher::float_in_double = true; | |
| 2056 // Do ints take an entire long register or just half? | |
| 2057 const bool Matcher::int_in_long = true; | |
| 2058 | |
| 2059 // Return whether or not this register is ever used as an argument. | |
| 2060 // This function is used on startup to build the trampoline stubs in | |
| 2061 // generateOptoStub. Registers not mentioned will be killed by the VM | |
| 2062 // call in the trampoline, and arguments in those registers not be | |
| 2063 // available to the callee. | |
| 2064 bool Matcher::can_be_java_arg(int reg) | |
| 2065 { | |
| 2066 return | |
| 2067 reg == RDI_num || reg == RDI_H_num || | |
| 2068 reg == RSI_num || reg == RSI_H_num || | |
| 2069 reg == RDX_num || reg == RDX_H_num || | |
| 2070 reg == RCX_num || reg == RCX_H_num || | |
| 2071 reg == R8_num || reg == R8_H_num || | |
| 2072 reg == R9_num || reg == R9_H_num || | |
|
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2073 reg == R12_num || reg == R12_H_num || |
| 0 | 2074 reg == XMM0_num || reg == XMM0_H_num || |
| 2075 reg == XMM1_num || reg == XMM1_H_num || | |
| 2076 reg == XMM2_num || reg == XMM2_H_num || | |
| 2077 reg == XMM3_num || reg == XMM3_H_num || | |
| 2078 reg == XMM4_num || reg == XMM4_H_num || | |
| 2079 reg == XMM5_num || reg == XMM5_H_num || | |
| 2080 reg == XMM6_num || reg == XMM6_H_num || | |
| 2081 reg == XMM7_num || reg == XMM7_H_num; | |
| 2082 } | |
| 2083 | |
| 2084 bool Matcher::is_spillable_arg(int reg) | |
| 2085 { | |
| 2086 return can_be_java_arg(reg); | |
| 2087 } | |
| 2088 | |
| 2089 // Register for DIVI projection of divmodI | |
| 2090 RegMask Matcher::divI_proj_mask() { | |
| 2091 return INT_RAX_REG_mask; | |
| 2092 } | |
| 2093 | |
| 2094 // Register for MODI projection of divmodI | |
| 2095 RegMask Matcher::modI_proj_mask() { | |
| 2096 return INT_RDX_REG_mask; | |
| 2097 } | |
| 2098 | |
| 2099 // Register for DIVL projection of divmodL | |
| 2100 RegMask Matcher::divL_proj_mask() { | |
| 2101 return LONG_RAX_REG_mask; | |
| 2102 } | |
| 2103 | |
| 2104 // Register for MODL projection of divmodL | |
| 2105 RegMask Matcher::modL_proj_mask() { | |
| 2106 return LONG_RDX_REG_mask; | |
| 2107 } | |
| 2108 | |
|
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2109 static Address build_address(int b, int i, int s, int d) { |
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2110 Register index = as_Register(i); |
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2111 Address::ScaleFactor scale = (Address::ScaleFactor)s; |
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2112 if (index == rsp) { |
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2113 index = noreg; |
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2114 scale = Address::no_scale; |
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2115 } |
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2116 Address addr(as_Register(b), index, scale, d); |
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2117 return addr; |
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2118 } |
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2119 |
| 0 | 2120 %} |
| 2121 | |
| 2122 //----------ENCODING BLOCK----------------------------------------------------- | |
| 2123 // This block specifies the encoding classes used by the compiler to | |
| 2124 // output byte streams. Encoding classes are parameterized macros | |
| 2125 // used by Machine Instruction Nodes in order to generate the bit | |
| 2126 // encoding of the instruction. Operands specify their base encoding | |
| 2127 // interface with the interface keyword. There are currently | |
| 2128 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, & | |
| 2129 // COND_INTER. REG_INTER causes an operand to generate a function | |
| 2130 // which returns its register number when queried. CONST_INTER causes | |
| 2131 // an operand to generate a function which returns the value of the | |
| 2132 // constant when queried. MEMORY_INTER causes an operand to generate | |
| 2133 // four functions which return the Base Register, the Index Register, | |
| 2134 // the Scale Value, and the Offset Value of the operand when queried. | |
| 2135 // COND_INTER causes an operand to generate six functions which return | |
| 2136 // the encoding code (ie - encoding bits for the instruction) | |
| 2137 // associated with each basic boolean condition for a conditional | |
| 2138 // instruction. | |
| 2139 // | |
| 2140 // Instructions specify two basic values for encoding. Again, a | |
| 2141 // function is available to check if the constant displacement is an | |
| 2142 // oop. They use the ins_encode keyword to specify their encoding | |
| 2143 // classes (which must be a sequence of enc_class names, and their | |
| 2144 // parameters, specified in the encoding block), and they use the | |
| 2145 // opcode keyword to specify, in order, their primary, secondary, and | |
| 2146 // tertiary opcode. Only the opcode sections which a particular | |
| 2147 // instruction needs for encoding need to be specified. | |
| 2148 encode %{ | |
| 2149 // Build emit functions for each basic byte or larger field in the | |
| 2150 // intel encoding scheme (opcode, rm, sib, immediate), and call them | |
| 2151 // from C++ code in the enc_class source block. Emit functions will | |
| 2152 // live in the main source block for now. In future, we can | |
| 2153 // generalize this by adding a syntax that specifies the sizes of | |
| 2154 // fields in an order, so that the adlc can build the emit functions | |
| 2155 // automagically | |
| 2156 | |
| 2157 // Emit primary opcode | |
| 2158 enc_class OpcP | |
| 2159 %{ | |
| 2160 emit_opcode(cbuf, $primary); | |
| 2161 %} | |
| 2162 | |
| 2163 // Emit secondary opcode | |
| 2164 enc_class OpcS | |
| 2165 %{ | |
| 2166 emit_opcode(cbuf, $secondary); | |
| 2167 %} | |
| 2168 | |
| 2169 // Emit tertiary opcode | |
| 2170 enc_class OpcT | |
| 2171 %{ | |
| 2172 emit_opcode(cbuf, $tertiary); | |
| 2173 %} | |
| 2174 | |
| 2175 // Emit opcode directly | |
| 2176 enc_class Opcode(immI d8) | |
| 2177 %{ | |
| 2178 emit_opcode(cbuf, $d8$$constant); | |
| 2179 %} | |
| 2180 | |
| 2181 // Emit size prefix | |
| 2182 enc_class SizePrefix | |
| 2183 %{ | |
| 2184 emit_opcode(cbuf, 0x66); | |
| 2185 %} | |
| 2186 | |
| 2187 enc_class reg(rRegI reg) | |
| 2188 %{ | |
| 2189 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7); | |
| 2190 %} | |
| 2191 | |
| 2192 enc_class reg_reg(rRegI dst, rRegI src) | |
| 2193 %{ | |
| 2194 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7); | |
| 2195 %} | |
| 2196 | |
| 2197 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src) | |
| 2198 %{ | |
| 2199 emit_opcode(cbuf, $opcode$$constant); | |
| 2200 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7); | |
| 2201 %} | |
| 2202 | |
| 2203 enc_class cmpfp_fixup() | |
| 2204 %{ | |
| 2205 // jnp,s exit | |
| 2206 emit_opcode(cbuf, 0x7B); | |
| 2207 emit_d8(cbuf, 0x0A); | |
| 2208 | |
| 2209 // pushfq | |
| 2210 emit_opcode(cbuf, 0x9C); | |
| 2211 | |
| 2212 // andq $0xffffff2b, (%rsp) | |
| 2213 emit_opcode(cbuf, Assembler::REX_W); | |
| 2214 emit_opcode(cbuf, 0x81); | |
| 2215 emit_opcode(cbuf, 0x24); | |
| 2216 emit_opcode(cbuf, 0x24); | |
| 2217 emit_d32(cbuf, 0xffffff2b); | |
| 2218 | |
| 2219 // popfq | |
| 2220 emit_opcode(cbuf, 0x9D); | |
| 2221 | |
| 2222 // nop (target for branch to avoid branch to branch) | |
| 2223 emit_opcode(cbuf, 0x90); | |
| 2224 %} | |
| 2225 | |
| 2226 enc_class cmpfp3(rRegI dst) | |
| 2227 %{ | |
| 2228 int dstenc = $dst$$reg; | |
| 2229 | |
| 2230 // movl $dst, -1 | |
| 2231 if (dstenc >= 8) { | |
| 2232 emit_opcode(cbuf, Assembler::REX_B); | |
| 2233 } | |
| 2234 emit_opcode(cbuf, 0xB8 | (dstenc & 7)); | |
| 2235 emit_d32(cbuf, -1); | |
| 2236 | |
| 2237 // jp,s done | |
| 2238 emit_opcode(cbuf, 0x7A); | |
| 2239 emit_d8(cbuf, dstenc < 4 ? 0x08 : 0x0A); | |
| 2240 | |
| 2241 // jb,s done | |
| 2242 emit_opcode(cbuf, 0x72); | |
| 2243 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08); | |
| 2244 | |
| 2245 // setne $dst | |
| 2246 if (dstenc >= 4) { | |
| 2247 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B); | |
| 2248 } | |
| 2249 emit_opcode(cbuf, 0x0F); | |
| 2250 emit_opcode(cbuf, 0x95); | |
| 2251 emit_opcode(cbuf, 0xC0 | (dstenc & 7)); | |
| 2252 | |
| 2253 // movzbl $dst, $dst | |
| 2254 if (dstenc >= 4) { | |
| 2255 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB); | |
| 2256 } | |
| 2257 emit_opcode(cbuf, 0x0F); | |
| 2258 emit_opcode(cbuf, 0xB6); | |
| 2259 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7); | |
| 2260 %} | |
| 2261 | |
| 2262 enc_class cdql_enc(no_rax_rdx_RegI div) | |
| 2263 %{ | |
| 2264 // Full implementation of Java idiv and irem; checks for | |
| 2265 // special case as described in JVM spec., p.243 & p.271. | |
| 2266 // | |
| 2267 // normal case special case | |
| 2268 // | |
| 2269 // input : rax: dividend min_int | |
| 2270 // reg: divisor -1 | |
| 2271 // | |
| 2272 // output: rax: quotient (= rax idiv reg) min_int | |
| 2273 // rdx: remainder (= rax irem reg) 0 | |
| 2274 // | |
| 2275 // Code sequnce: | |
| 2276 // | |
| 2277 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax | |
| 2278 // 5: 75 07/08 jne e <normal> | |
| 2279 // 7: 33 d2 xor %edx,%edx | |
| 2280 // [div >= 8 -> offset + 1] | |
| 2281 // [REX_B] | |
| 2282 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div | |
| 2283 // c: 74 03/04 je 11 <done> | |
| 2284 // 000000000000000e <normal>: | |
| 2285 // e: 99 cltd | |
| 2286 // [div >= 8 -> offset + 1] | |
| 2287 // [REX_B] | |
| 2288 // f: f7 f9 idiv $div | |
| 2289 // 0000000000000011 <done>: | |
| 2290 | |
| 2291 // cmp $0x80000000,%eax | |
| 2292 emit_opcode(cbuf, 0x3d); | |
| 2293 emit_d8(cbuf, 0x00); | |
| 2294 emit_d8(cbuf, 0x00); | |
| 2295 emit_d8(cbuf, 0x00); | |
| 2296 emit_d8(cbuf, 0x80); | |
| 2297 | |
| 2298 // jne e <normal> | |
| 2299 emit_opcode(cbuf, 0x75); | |
| 2300 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08); | |
| 2301 | |
| 2302 // xor %edx,%edx | |
| 2303 emit_opcode(cbuf, 0x33); | |
| 2304 emit_d8(cbuf, 0xD2); | |
| 2305 | |
| 2306 // cmp $0xffffffffffffffff,%ecx | |
| 2307 if ($div$$reg >= 8) { | |
| 2308 emit_opcode(cbuf, Assembler::REX_B); | |
| 2309 } | |
| 2310 emit_opcode(cbuf, 0x83); | |
| 2311 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7); | |
| 2312 emit_d8(cbuf, 0xFF); | |
| 2313 | |
| 2314 // je 11 <done> | |
| 2315 emit_opcode(cbuf, 0x74); | |
| 2316 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04); | |
| 2317 | |
| 2318 // <normal> | |
| 2319 // cltd | |
| 2320 emit_opcode(cbuf, 0x99); | |
| 2321 | |
| 2322 // idivl (note: must be emitted by the user of this rule) | |
| 2323 // <done> | |
| 2324 %} | |
| 2325 | |
| 2326 enc_class cdqq_enc(no_rax_rdx_RegL div) | |
| 2327 %{ | |
| 2328 // Full implementation of Java ldiv and lrem; checks for | |
| 2329 // special case as described in JVM spec., p.243 & p.271. | |
| 2330 // | |
| 2331 // normal case special case | |
| 2332 // | |
| 2333 // input : rax: dividend min_long | |
| 2334 // reg: divisor -1 | |
| 2335 // | |
| 2336 // output: rax: quotient (= rax idiv reg) min_long | |
| 2337 // rdx: remainder (= rax irem reg) 0 | |
| 2338 // | |
| 2339 // Code sequnce: | |
| 2340 // | |
| 2341 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx | |
| 2342 // 7: 00 00 80 | |
| 2343 // a: 48 39 d0 cmp %rdx,%rax | |
| 2344 // d: 75 08 jne 17 <normal> | |
| 2345 // f: 33 d2 xor %edx,%edx | |
| 2346 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div | |
| 2347 // 15: 74 05 je 1c <done> | |
| 2348 // 0000000000000017 <normal>: | |
| 2349 // 17: 48 99 cqto | |
| 2350 // 19: 48 f7 f9 idiv $div | |
| 2351 // 000000000000001c <done>: | |
| 2352 | |
| 2353 // mov $0x8000000000000000,%rdx | |
| 2354 emit_opcode(cbuf, Assembler::REX_W); | |
| 2355 emit_opcode(cbuf, 0xBA); | |
| 2356 emit_d8(cbuf, 0x00); | |
| 2357 emit_d8(cbuf, 0x00); | |
| 2358 emit_d8(cbuf, 0x00); | |
| 2359 emit_d8(cbuf, 0x00); | |
| 2360 emit_d8(cbuf, 0x00); | |
| 2361 emit_d8(cbuf, 0x00); | |
| 2362 emit_d8(cbuf, 0x00); | |
| 2363 emit_d8(cbuf, 0x80); | |
| 2364 | |
| 2365 // cmp %rdx,%rax | |
| 2366 emit_opcode(cbuf, Assembler::REX_W); | |
| 2367 emit_opcode(cbuf, 0x39); | |
| 2368 emit_d8(cbuf, 0xD0); | |
| 2369 | |
| 2370 // jne 17 <normal> | |
| 2371 emit_opcode(cbuf, 0x75); | |
| 2372 emit_d8(cbuf, 0x08); | |
| 2373 | |
| 2374 // xor %edx,%edx | |
| 2375 emit_opcode(cbuf, 0x33); | |
| 2376 emit_d8(cbuf, 0xD2); | |
| 2377 | |
| 2378 // cmp $0xffffffffffffffff,$div | |
| 2379 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB); | |
| 2380 emit_opcode(cbuf, 0x83); | |
| 2381 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7); | |
| 2382 emit_d8(cbuf, 0xFF); | |
| 2383 | |
| 2384 // je 1e <done> | |
| 2385 emit_opcode(cbuf, 0x74); | |
| 2386 emit_d8(cbuf, 0x05); | |
| 2387 | |
| 2388 // <normal> | |
| 2389 // cqto | |
| 2390 emit_opcode(cbuf, Assembler::REX_W); | |
| 2391 emit_opcode(cbuf, 0x99); | |
| 2392 | |
| 2393 // idivq (note: must be emitted by the user of this rule) | |
| 2394 // <done> | |
| 2395 %} | |
| 2396 | |
| 2397 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension | |
| 2398 enc_class OpcSE(immI imm) | |
| 2399 %{ | |
| 2400 // Emit primary opcode and set sign-extend bit | |
| 2401 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 2402 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
| 2403 emit_opcode(cbuf, $primary | 0x02); | |
| 2404 } else { | |
| 2405 // 32-bit immediate | |
| 2406 emit_opcode(cbuf, $primary); | |
| 2407 } | |
| 2408 %} | |
| 2409 | |
| 2410 enc_class OpcSErm(rRegI dst, immI imm) | |
| 2411 %{ | |
| 2412 // OpcSEr/m | |
| 2413 int dstenc = $dst$$reg; | |
| 2414 if (dstenc >= 8) { | |
| 2415 emit_opcode(cbuf, Assembler::REX_B); | |
| 2416 dstenc -= 8; | |
| 2417 } | |
| 2418 // Emit primary opcode and set sign-extend bit | |
| 2419 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 2420 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
| 2421 emit_opcode(cbuf, $primary | 0x02); | |
| 2422 } else { | |
| 2423 // 32-bit immediate | |
| 2424 emit_opcode(cbuf, $primary); | |
| 2425 } | |
| 2426 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 2427 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
| 2428 %} | |
| 2429 | |
| 2430 enc_class OpcSErm_wide(rRegL dst, immI imm) | |
| 2431 %{ | |
| 2432 // OpcSEr/m | |
| 2433 int dstenc = $dst$$reg; | |
| 2434 if (dstenc < 8) { | |
| 2435 emit_opcode(cbuf, Assembler::REX_W); | |
| 2436 } else { | |
| 2437 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2438 dstenc -= 8; | |
| 2439 } | |
| 2440 // Emit primary opcode and set sign-extend bit | |
| 2441 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 2442 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
| 2443 emit_opcode(cbuf, $primary | 0x02); | |
| 2444 } else { | |
| 2445 // 32-bit immediate | |
| 2446 emit_opcode(cbuf, $primary); | |
| 2447 } | |
| 2448 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 2449 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
| 2450 %} | |
| 2451 | |
| 2452 enc_class Con8or32(immI imm) | |
| 2453 %{ | |
| 2454 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 2455 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
| 2456 $$$emit8$imm$$constant; | |
| 2457 } else { | |
| 2458 // 32-bit immediate | |
| 2459 $$$emit32$imm$$constant; | |
| 2460 } | |
| 2461 %} | |
| 2462 | |
| 2463 enc_class Lbl(label labl) | |
| 2464 %{ | |
| 2465 // JMP, CALL | |
| 2466 Label* l = $labl$$label; | |
| 2467 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0); | |
| 2468 %} | |
| 2469 | |
| 2470 enc_class LblShort(label labl) | |
| 2471 %{ | |
| 2472 // JMP, CALL | |
| 2473 Label* l = $labl$$label; | |
| 2474 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0; | |
| 2475 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp"); | |
| 2476 emit_d8(cbuf, disp); | |
| 2477 %} | |
| 2478 | |
| 2479 enc_class opc2_reg(rRegI dst) | |
| 2480 %{ | |
| 2481 // BSWAP | |
| 2482 emit_cc(cbuf, $secondary, $dst$$reg); | |
| 2483 %} | |
| 2484 | |
| 2485 enc_class opc3_reg(rRegI dst) | |
| 2486 %{ | |
| 2487 // BSWAP | |
| 2488 emit_cc(cbuf, $tertiary, $dst$$reg); | |
| 2489 %} | |
| 2490 | |
| 2491 enc_class reg_opc(rRegI div) | |
| 2492 %{ | |
| 2493 // INC, DEC, IDIV, IMOD, JMP indirect, ... | |
| 2494 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7); | |
| 2495 %} | |
| 2496 | |
| 2497 enc_class Jcc(cmpOp cop, label labl) | |
| 2498 %{ | |
| 2499 // JCC | |
| 2500 Label* l = $labl$$label; | |
| 2501 $$$emit8$primary; | |
| 2502 emit_cc(cbuf, $secondary, $cop$$cmpcode); | |
| 2503 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0); | |
| 2504 %} | |
| 2505 | |
| 2506 enc_class JccShort (cmpOp cop, label labl) | |
| 2507 %{ | |
| 2508 // JCC | |
| 2509 Label *l = $labl$$label; | |
| 2510 emit_cc(cbuf, $primary, $cop$$cmpcode); | |
| 2511 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0; | |
| 2512 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp"); | |
| 2513 emit_d8(cbuf, disp); | |
| 2514 %} | |
| 2515 | |
| 2516 enc_class enc_cmov(cmpOp cop) | |
| 2517 %{ | |
| 2518 // CMOV | |
| 2519 $$$emit8$primary; | |
| 2520 emit_cc(cbuf, $secondary, $cop$$cmpcode); | |
| 2521 %} | |
| 2522 | |
| 2523 enc_class enc_cmovf_branch(cmpOp cop, regF dst, regF src) | |
| 2524 %{ | |
| 2525 // Invert sense of branch from sense of cmov | |
| 2526 emit_cc(cbuf, 0x70, $cop$$cmpcode ^ 1); | |
| 2527 emit_d8(cbuf, ($dst$$reg < 8 && $src$$reg < 8) | |
| 2528 ? (UseXmmRegToRegMoveAll ? 3 : 4) | |
| 2529 : (UseXmmRegToRegMoveAll ? 4 : 5) ); // REX | |
| 2530 // UseXmmRegToRegMoveAll ? movaps(dst, src) : movss(dst, src) | |
| 2531 if (!UseXmmRegToRegMoveAll) emit_opcode(cbuf, 0xF3); | |
| 2532 if ($dst$$reg < 8) { | |
| 2533 if ($src$$reg >= 8) { | |
| 2534 emit_opcode(cbuf, Assembler::REX_B); | |
| 2535 } | |
| 2536 } else { | |
| 2537 if ($src$$reg < 8) { | |
| 2538 emit_opcode(cbuf, Assembler::REX_R); | |
| 2539 } else { | |
| 2540 emit_opcode(cbuf, Assembler::REX_RB); | |
| 2541 } | |
| 2542 } | |
| 2543 emit_opcode(cbuf, 0x0F); | |
| 2544 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10); | |
| 2545 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7); | |
| 2546 %} | |
| 2547 | |
| 2548 enc_class enc_cmovd_branch(cmpOp cop, regD dst, regD src) | |
| 2549 %{ | |
| 2550 // Invert sense of branch from sense of cmov | |
| 2551 emit_cc(cbuf, 0x70, $cop$$cmpcode ^ 1); | |
| 2552 emit_d8(cbuf, $dst$$reg < 8 && $src$$reg < 8 ? 4 : 5); // REX | |
| 2553 | |
| 2554 // UseXmmRegToRegMoveAll ? movapd(dst, src) : movsd(dst, src) | |
| 2555 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x66 : 0xF2); | |
| 2556 if ($dst$$reg < 8) { | |
| 2557 if ($src$$reg >= 8) { | |
| 2558 emit_opcode(cbuf, Assembler::REX_B); | |
| 2559 } | |
| 2560 } else { | |
| 2561 if ($src$$reg < 8) { | |
| 2562 emit_opcode(cbuf, Assembler::REX_R); | |
| 2563 } else { | |
| 2564 emit_opcode(cbuf, Assembler::REX_RB); | |
| 2565 } | |
| 2566 } | |
| 2567 emit_opcode(cbuf, 0x0F); | |
| 2568 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10); | |
| 2569 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7); | |
| 2570 %} | |
| 2571 | |
| 2572 enc_class enc_PartialSubtypeCheck() | |
| 2573 %{ | |
| 2574 Register Rrdi = as_Register(RDI_enc); // result register | |
| 2575 Register Rrax = as_Register(RAX_enc); // super class | |
| 2576 Register Rrcx = as_Register(RCX_enc); // killed | |
| 2577 Register Rrsi = as_Register(RSI_enc); // sub class | |
|
644
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|
2578 Label miss; |
|
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|
2579 const bool set_cond_codes = true; |
| 0 | 2580 |
| 2581 MacroAssembler _masm(&cbuf); | |
|
644
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diff
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|
2582 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi, |
|
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|
2583 NULL, &miss, |
|
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|
2584 /*set_cond_codes:*/ true); |
| 0 | 2585 if ($primary) { |
| 304 | 2586 __ xorptr(Rrdi, Rrdi); |
| 0 | 2587 } |
| 2588 __ bind(miss); | |
| 2589 %} | |
| 2590 | |
| 2591 enc_class Java_To_Interpreter(method meth) | |
| 2592 %{ | |
| 2593 // CALL Java_To_Interpreter | |
| 2594 // This is the instruction starting address for relocation info. | |
| 2595 cbuf.set_inst_mark(); | |
| 2596 $$$emit8$primary; | |
| 2597 // CALL directly to the runtime | |
| 2598 emit_d32_reloc(cbuf, | |
| 2599 (int) ($meth$$method - ((intptr_t) cbuf.code_end()) - 4), | |
| 2600 runtime_call_Relocation::spec(), | |
| 2601 RELOC_DISP32); | |
| 2602 %} | |
| 2603 | |
| 2604 enc_class Java_Static_Call(method meth) | |
| 2605 %{ | |
| 2606 // JAVA STATIC CALL | |
| 2607 // CALL to fixup routine. Fixup routine uses ScopeDesc info to | |
| 2608 // determine who we intended to call. | |
| 2609 cbuf.set_inst_mark(); | |
| 2610 $$$emit8$primary; | |
| 2611 | |
| 2612 if (!_method) { | |
| 2613 emit_d32_reloc(cbuf, | |
| 2614 (int) ($meth$$method - ((intptr_t) cbuf.code_end()) - 4), | |
| 2615 runtime_call_Relocation::spec(), | |
| 2616 RELOC_DISP32); | |
| 2617 } else if (_optimized_virtual) { | |
| 2618 emit_d32_reloc(cbuf, | |
| 2619 (int) ($meth$$method - ((intptr_t) cbuf.code_end()) - 4), | |
| 2620 opt_virtual_call_Relocation::spec(), | |
| 2621 RELOC_DISP32); | |
| 2622 } else { | |
| 2623 emit_d32_reloc(cbuf, | |
| 2624 (int) ($meth$$method - ((intptr_t) cbuf.code_end()) - 4), | |
| 2625 static_call_Relocation::spec(), | |
| 2626 RELOC_DISP32); | |
| 2627 } | |
| 2628 if (_method) { | |
| 2629 // Emit stub for static call | |
| 2630 emit_java_to_interp(cbuf); | |
| 2631 } | |
| 2632 %} | |
| 2633 | |
| 2634 enc_class Java_Dynamic_Call(method meth) | |
| 2635 %{ | |
| 2636 // JAVA DYNAMIC CALL | |
| 2637 // !!!!! | |
| 2638 // Generate "movq rax, -1", placeholder instruction to load oop-info | |
| 2639 // emit_call_dynamic_prologue( cbuf ); | |
| 2640 cbuf.set_inst_mark(); | |
| 2641 | |
| 2642 // movq rax, -1 | |
| 2643 emit_opcode(cbuf, Assembler::REX_W); | |
| 2644 emit_opcode(cbuf, 0xB8 | RAX_enc); | |
| 2645 emit_d64_reloc(cbuf, | |
| 2646 (int64_t) Universe::non_oop_word(), | |
| 2647 oop_Relocation::spec_for_immediate(), RELOC_IMM64); | |
| 2648 address virtual_call_oop_addr = cbuf.inst_mark(); | |
| 2649 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
| 2650 // who we intended to call. | |
| 2651 cbuf.set_inst_mark(); | |
| 2652 $$$emit8$primary; | |
| 2653 emit_d32_reloc(cbuf, | |
| 2654 (int) ($meth$$method - ((intptr_t) cbuf.code_end()) - 4), | |
| 2655 virtual_call_Relocation::spec(virtual_call_oop_addr), | |
| 2656 RELOC_DISP32); | |
| 2657 %} | |
| 2658 | |
| 2659 enc_class Java_Compiled_Call(method meth) | |
| 2660 %{ | |
| 2661 // JAVA COMPILED CALL | |
| 2662 int disp = in_bytes(methodOopDesc:: from_compiled_offset()); | |
| 2663 | |
| 2664 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!! | |
| 2665 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small"); | |
| 2666 | |
| 2667 // callq *disp(%rax) | |
| 2668 cbuf.set_inst_mark(); | |
| 2669 $$$emit8$primary; | |
| 2670 if (disp < 0x80) { | |
| 2671 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte | |
| 2672 emit_d8(cbuf, disp); // Displacement | |
| 2673 } else { | |
| 2674 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte | |
| 2675 emit_d32(cbuf, disp); // Displacement | |
| 2676 } | |
| 2677 %} | |
| 2678 | |
| 2679 enc_class reg_opc_imm(rRegI dst, immI8 shift) | |
| 2680 %{ | |
| 2681 // SAL, SAR, SHR | |
| 2682 int dstenc = $dst$$reg; | |
| 2683 if (dstenc >= 8) { | |
| 2684 emit_opcode(cbuf, Assembler::REX_B); | |
| 2685 dstenc -= 8; | |
| 2686 } | |
| 2687 $$$emit8$primary; | |
| 2688 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
| 2689 $$$emit8$shift$$constant; | |
| 2690 %} | |
| 2691 | |
| 2692 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift) | |
| 2693 %{ | |
| 2694 // SAL, SAR, SHR | |
| 2695 int dstenc = $dst$$reg; | |
| 2696 if (dstenc < 8) { | |
| 2697 emit_opcode(cbuf, Assembler::REX_W); | |
| 2698 } else { | |
| 2699 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2700 dstenc -= 8; | |
| 2701 } | |
| 2702 $$$emit8$primary; | |
| 2703 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
| 2704 $$$emit8$shift$$constant; | |
| 2705 %} | |
| 2706 | |
| 2707 enc_class load_immI(rRegI dst, immI src) | |
| 2708 %{ | |
| 2709 int dstenc = $dst$$reg; | |
| 2710 if (dstenc >= 8) { | |
| 2711 emit_opcode(cbuf, Assembler::REX_B); | |
| 2712 dstenc -= 8; | |
| 2713 } | |
| 2714 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2715 $$$emit32$src$$constant; | |
| 2716 %} | |
| 2717 | |
| 2718 enc_class load_immL(rRegL dst, immL src) | |
| 2719 %{ | |
| 2720 int dstenc = $dst$$reg; | |
| 2721 if (dstenc < 8) { | |
| 2722 emit_opcode(cbuf, Assembler::REX_W); | |
| 2723 } else { | |
| 2724 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2725 dstenc -= 8; | |
| 2726 } | |
| 2727 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2728 emit_d64(cbuf, $src$$constant); | |
| 2729 %} | |
| 2730 | |
| 2731 enc_class load_immUL32(rRegL dst, immUL32 src) | |
| 2732 %{ | |
| 2733 // same as load_immI, but this time we care about zeroes in the high word | |
| 2734 int dstenc = $dst$$reg; | |
| 2735 if (dstenc >= 8) { | |
| 2736 emit_opcode(cbuf, Assembler::REX_B); | |
| 2737 dstenc -= 8; | |
| 2738 } | |
| 2739 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2740 $$$emit32$src$$constant; | |
| 2741 %} | |
| 2742 | |
| 2743 enc_class load_immL32(rRegL dst, immL32 src) | |
| 2744 %{ | |
| 2745 int dstenc = $dst$$reg; | |
| 2746 if (dstenc < 8) { | |
| 2747 emit_opcode(cbuf, Assembler::REX_W); | |
| 2748 } else { | |
| 2749 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2750 dstenc -= 8; | |
| 2751 } | |
| 2752 emit_opcode(cbuf, 0xC7); | |
| 2753 emit_rm(cbuf, 0x03, 0x00, dstenc); | |
| 2754 $$$emit32$src$$constant; | |
| 2755 %} | |
| 2756 | |
| 2757 enc_class load_immP31(rRegP dst, immP32 src) | |
| 2758 %{ | |
| 2759 // same as load_immI, but this time we care about zeroes in the high word | |
| 2760 int dstenc = $dst$$reg; | |
| 2761 if (dstenc >= 8) { | |
| 2762 emit_opcode(cbuf, Assembler::REX_B); | |
| 2763 dstenc -= 8; | |
| 2764 } | |
| 2765 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2766 $$$emit32$src$$constant; | |
| 2767 %} | |
| 2768 | |
| 2769 enc_class load_immP(rRegP dst, immP src) | |
| 2770 %{ | |
| 2771 int dstenc = $dst$$reg; | |
| 2772 if (dstenc < 8) { | |
| 2773 emit_opcode(cbuf, Assembler::REX_W); | |
| 2774 } else { | |
| 2775 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2776 dstenc -= 8; | |
| 2777 } | |
| 2778 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2779 // This next line should be generated from ADLC | |
| 2780 if ($src->constant_is_oop()) { | |
| 2781 emit_d64_reloc(cbuf, $src$$constant, relocInfo::oop_type, RELOC_IMM64); | |
| 2782 } else { | |
| 2783 emit_d64(cbuf, $src$$constant); | |
| 2784 } | |
| 2785 %} | |
| 2786 | |
| 2787 enc_class load_immF(regF dst, immF con) | |
| 2788 %{ | |
| 2789 // XXX reg_mem doesn't support RIP-relative addressing yet | |
| 2790 emit_rm(cbuf, 0x0, $dst$$reg & 7, 0x5); // 00 reg 101 | |
| 2791 emit_float_constant(cbuf, $con$$constant); | |
| 2792 %} | |
| 2793 | |
| 2794 enc_class load_immD(regD dst, immD con) | |
| 2795 %{ | |
| 2796 // XXX reg_mem doesn't support RIP-relative addressing yet | |
| 2797 emit_rm(cbuf, 0x0, $dst$$reg & 7, 0x5); // 00 reg 101 | |
| 2798 emit_double_constant(cbuf, $con$$constant); | |
| 2799 %} | |
| 2800 | |
| 2801 enc_class load_conF (regF dst, immF con) %{ // Load float constant | |
| 2802 emit_opcode(cbuf, 0xF3); | |
| 2803 if ($dst$$reg >= 8) { | |
| 2804 emit_opcode(cbuf, Assembler::REX_R); | |
| 2805 } | |
| 2806 emit_opcode(cbuf, 0x0F); | |
| 2807 emit_opcode(cbuf, 0x10); | |
| 2808 emit_rm(cbuf, 0x0, $dst$$reg & 7, 0x5); // 00 reg 101 | |
| 2809 emit_float_constant(cbuf, $con$$constant); | |
| 2810 %} | |
| 2811 | |
| 2812 enc_class load_conD (regD dst, immD con) %{ // Load double constant | |
| 2813 // UseXmmLoadAndClearUpper ? movsd(dst, con) : movlpd(dst, con) | |
| 2814 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66); | |
| 2815 if ($dst$$reg >= 8) { | |
| 2816 emit_opcode(cbuf, Assembler::REX_R); | |
| 2817 } | |
| 2818 emit_opcode(cbuf, 0x0F); | |
| 2819 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12); | |
| 2820 emit_rm(cbuf, 0x0, $dst$$reg & 7, 0x5); // 00 reg 101 | |
| 2821 emit_double_constant(cbuf, $con$$constant); | |
| 2822 %} | |
| 2823 | |
| 2824 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 2825 enc_class enc_copy(rRegI dst, rRegI src) | |
| 2826 %{ | |
| 2827 encode_copy(cbuf, $dst$$reg, $src$$reg); | |
| 2828 %} | |
| 2829 | |
| 2830 // Encode xmm reg-reg copy. If it is useless, then empty encoding. | |
| 2831 enc_class enc_CopyXD( RegD dst, RegD src ) %{ | |
| 2832 encode_CopyXD( cbuf, $dst$$reg, $src$$reg ); | |
| 2833 %} | |
| 2834 | |
| 2835 enc_class enc_copy_always(rRegI dst, rRegI src) | |
| 2836 %{ | |
| 2837 int srcenc = $src$$reg; | |
| 2838 int dstenc = $dst$$reg; | |
| 2839 | |
| 2840 if (dstenc < 8) { | |
| 2841 if (srcenc >= 8) { | |
| 2842 emit_opcode(cbuf, Assembler::REX_B); | |
| 2843 srcenc -= 8; | |
| 2844 } | |
| 2845 } else { | |
| 2846 if (srcenc < 8) { | |
| 2847 emit_opcode(cbuf, Assembler::REX_R); | |
| 2848 } else { | |
| 2849 emit_opcode(cbuf, Assembler::REX_RB); | |
| 2850 srcenc -= 8; | |
| 2851 } | |
| 2852 dstenc -= 8; | |
| 2853 } | |
| 2854 | |
| 2855 emit_opcode(cbuf, 0x8B); | |
| 2856 emit_rm(cbuf, 0x3, dstenc, srcenc); | |
| 2857 %} | |
| 2858 | |
| 2859 enc_class enc_copy_wide(rRegL dst, rRegL src) | |
| 2860 %{ | |
| 2861 int srcenc = $src$$reg; | |
| 2862 int dstenc = $dst$$reg; | |
| 2863 | |
| 2864 if (dstenc != srcenc) { | |
| 2865 if (dstenc < 8) { | |
| 2866 if (srcenc < 8) { | |
| 2867 emit_opcode(cbuf, Assembler::REX_W); | |
| 2868 } else { | |
| 2869 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2870 srcenc -= 8; | |
| 2871 } | |
| 2872 } else { | |
| 2873 if (srcenc < 8) { | |
| 2874 emit_opcode(cbuf, Assembler::REX_WR); | |
| 2875 } else { | |
| 2876 emit_opcode(cbuf, Assembler::REX_WRB); | |
| 2877 srcenc -= 8; | |
| 2878 } | |
| 2879 dstenc -= 8; | |
| 2880 } | |
| 2881 emit_opcode(cbuf, 0x8B); | |
| 2882 emit_rm(cbuf, 0x3, dstenc, srcenc); | |
| 2883 } | |
| 2884 %} | |
| 2885 | |
| 2886 enc_class Con32(immI src) | |
| 2887 %{ | |
| 2888 // Output immediate | |
| 2889 $$$emit32$src$$constant; | |
| 2890 %} | |
| 2891 | |
| 2892 enc_class Con64(immL src) | |
| 2893 %{ | |
| 2894 // Output immediate | |
| 2895 emit_d64($src$$constant); | |
| 2896 %} | |
| 2897 | |
| 2898 enc_class Con32F_as_bits(immF src) | |
| 2899 %{ | |
| 2900 // Output Float immediate bits | |
| 2901 jfloat jf = $src$$constant; | |
| 2902 jint jf_as_bits = jint_cast(jf); | |
| 2903 emit_d32(cbuf, jf_as_bits); | |
| 2904 %} | |
| 2905 | |
| 2906 enc_class Con16(immI src) | |
| 2907 %{ | |
| 2908 // Output immediate | |
| 2909 $$$emit16$src$$constant; | |
| 2910 %} | |
| 2911 | |
| 2912 // How is this different from Con32??? XXX | |
| 2913 enc_class Con_d32(immI src) | |
| 2914 %{ | |
| 2915 emit_d32(cbuf,$src$$constant); | |
| 2916 %} | |
| 2917 | |
| 2918 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI) | |
| 2919 // Output immediate memory reference | |
| 2920 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 ); | |
| 2921 emit_d32(cbuf, 0x00); | |
| 2922 %} | |
| 2923 | |
| 2924 enc_class jump_enc(rRegL switch_val, rRegI dest) %{ | |
| 2925 MacroAssembler masm(&cbuf); | |
| 2926 | |
| 2927 Register switch_reg = as_Register($switch_val$$reg); | |
| 2928 Register dest_reg = as_Register($dest$$reg); | |
| 2929 address table_base = masm.address_table_constant(_index2label); | |
| 2930 | |
| 2931 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10 | |
| 2932 // to do that and the compiler is using that register as one it can allocate. | |
| 2933 // So we build it all by hand. | |
| 2934 // Address index(noreg, switch_reg, Address::times_1); | |
| 2935 // ArrayAddress dispatch(table, index); | |
| 2936 | |
| 2937 Address dispatch(dest_reg, switch_reg, Address::times_1); | |
| 2938 | |
| 2939 masm.lea(dest_reg, InternalAddress(table_base)); | |
| 2940 masm.jmp(dispatch); | |
| 2941 %} | |
| 2942 | |
| 2943 enc_class jump_enc_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{ | |
| 2944 MacroAssembler masm(&cbuf); | |
| 2945 | |
| 2946 Register switch_reg = as_Register($switch_val$$reg); | |
| 2947 Register dest_reg = as_Register($dest$$reg); | |
| 2948 address table_base = masm.address_table_constant(_index2label); | |
| 2949 | |
| 2950 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10 | |
| 2951 // to do that and the compiler is using that register as one it can allocate. | |
| 2952 // So we build it all by hand. | |
| 2953 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant, (int)$offset$$constant); | |
| 2954 // ArrayAddress dispatch(table, index); | |
| 2955 | |
| 2956 Address dispatch(dest_reg, switch_reg, (Address::ScaleFactor)$shift$$constant, (int)$offset$$constant); | |
| 2957 | |
| 2958 masm.lea(dest_reg, InternalAddress(table_base)); | |
| 2959 masm.jmp(dispatch); | |
| 2960 %} | |
| 2961 | |
| 2962 enc_class jump_enc_offset(rRegL switch_val, immI2 shift, rRegI dest) %{ | |
| 2963 MacroAssembler masm(&cbuf); | |
| 2964 | |
| 2965 Register switch_reg = as_Register($switch_val$$reg); | |
| 2966 Register dest_reg = as_Register($dest$$reg); | |
| 2967 address table_base = masm.address_table_constant(_index2label); | |
| 2968 | |
| 2969 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10 | |
| 2970 // to do that and the compiler is using that register as one it can allocate. | |
| 2971 // So we build it all by hand. | |
| 2972 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant); | |
| 2973 // ArrayAddress dispatch(table, index); | |
| 2974 | |
| 2975 Address dispatch(dest_reg, switch_reg, (Address::ScaleFactor)$shift$$constant); | |
| 2976 masm.lea(dest_reg, InternalAddress(table_base)); | |
| 2977 masm.jmp(dispatch); | |
| 2978 | |
| 2979 %} | |
| 2980 | |
| 2981 enc_class lock_prefix() | |
| 2982 %{ | |
| 2983 if (os::is_MP()) { | |
| 2984 emit_opcode(cbuf, 0xF0); // lock | |
| 2985 } | |
| 2986 %} | |
| 2987 | |
| 2988 enc_class REX_mem(memory mem) | |
| 2989 %{ | |
| 2990 if ($mem$$base >= 8) { | |
| 2991 if ($mem$$index < 8) { | |
| 2992 emit_opcode(cbuf, Assembler::REX_B); | |
| 2993 } else { | |
| 2994 emit_opcode(cbuf, Assembler::REX_XB); | |
| 2995 } | |
| 2996 } else { | |
| 2997 if ($mem$$index >= 8) { | |
| 2998 emit_opcode(cbuf, Assembler::REX_X); | |
| 2999 } | |
| 3000 } | |
| 3001 %} | |
| 3002 | |
| 3003 enc_class REX_mem_wide(memory mem) | |
| 3004 %{ | |
| 3005 if ($mem$$base >= 8) { | |
| 3006 if ($mem$$index < 8) { | |
| 3007 emit_opcode(cbuf, Assembler::REX_WB); | |
| 3008 } else { | |
| 3009 emit_opcode(cbuf, Assembler::REX_WXB); | |
| 3010 } | |
| 3011 } else { | |
| 3012 if ($mem$$index < 8) { | |
| 3013 emit_opcode(cbuf, Assembler::REX_W); | |
| 3014 } else { | |
| 3015 emit_opcode(cbuf, Assembler::REX_WX); | |
| 3016 } | |
| 3017 } | |
| 3018 %} | |
| 3019 | |
| 3020 // for byte regs | |
| 3021 enc_class REX_breg(rRegI reg) | |
| 3022 %{ | |
| 3023 if ($reg$$reg >= 4) { | |
| 3024 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B); | |
| 3025 } | |
| 3026 %} | |
| 3027 | |
| 3028 // for byte regs | |
| 3029 enc_class REX_reg_breg(rRegI dst, rRegI src) | |
| 3030 %{ | |
| 3031 if ($dst$$reg < 8) { | |
| 3032 if ($src$$reg >= 4) { | |
| 3033 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B); | |
| 3034 } | |
| 3035 } else { | |
| 3036 if ($src$$reg < 8) { | |
| 3037 emit_opcode(cbuf, Assembler::REX_R); | |
| 3038 } else { | |
| 3039 emit_opcode(cbuf, Assembler::REX_RB); | |
| 3040 } | |
| 3041 } | |
| 3042 %} | |
| 3043 | |
| 3044 // for byte regs | |
| 3045 enc_class REX_breg_mem(rRegI reg, memory mem) | |
| 3046 %{ | |
| 3047 if ($reg$$reg < 8) { | |
| 3048 if ($mem$$base < 8) { | |
| 3049 if ($mem$$index >= 8) { | |
| 3050 emit_opcode(cbuf, Assembler::REX_X); | |
| 3051 } else if ($reg$$reg >= 4) { | |
| 3052 emit_opcode(cbuf, Assembler::REX); | |
| 3053 } | |
| 3054 } else { | |
| 3055 if ($mem$$index < 8) { | |
| 3056 emit_opcode(cbuf, Assembler::REX_B); | |
| 3057 } else { | |
| 3058 emit_opcode(cbuf, Assembler::REX_XB); | |
| 3059 } | |
| 3060 } | |
| 3061 } else { | |
| 3062 if ($mem$$base < 8) { | |
| 3063 if ($mem$$index < 8) { | |
| 3064 emit_opcode(cbuf, Assembler::REX_R); | |
| 3065 } else { | |
| 3066 emit_opcode(cbuf, Assembler::REX_RX); | |
| 3067 } | |
| 3068 } else { | |
| 3069 if ($mem$$index < 8) { | |
| 3070 emit_opcode(cbuf, Assembler::REX_RB); | |
| 3071 } else { | |
| 3072 emit_opcode(cbuf, Assembler::REX_RXB); | |
| 3073 } | |
| 3074 } | |
| 3075 } | |
| 3076 %} | |
| 3077 | |
| 3078 enc_class REX_reg(rRegI reg) | |
| 3079 %{ | |
| 3080 if ($reg$$reg >= 8) { | |
| 3081 emit_opcode(cbuf, Assembler::REX_B); | |
| 3082 } | |
| 3083 %} | |
| 3084 | |
| 3085 enc_class REX_reg_wide(rRegI reg) | |
| 3086 %{ | |
| 3087 if ($reg$$reg < 8) { | |
| 3088 emit_opcode(cbuf, Assembler::REX_W); | |
| 3089 } else { | |
| 3090 emit_opcode(cbuf, Assembler::REX_WB); | |
| 3091 } | |
| 3092 %} | |
| 3093 | |
| 3094 enc_class REX_reg_reg(rRegI dst, rRegI src) | |
| 3095 %{ | |
| 3096 if ($dst$$reg < 8) { | |
| 3097 if ($src$$reg >= 8) { | |
| 3098 emit_opcode(cbuf, Assembler::REX_B); | |
| 3099 } | |
| 3100 } else { | |
| 3101 if ($src$$reg < 8) { | |
| 3102 emit_opcode(cbuf, Assembler::REX_R); | |
| 3103 } else { | |
| 3104 emit_opcode(cbuf, Assembler::REX_RB); | |
| 3105 } | |
| 3106 } | |
| 3107 %} | |
| 3108 | |
| 3109 enc_class REX_reg_reg_wide(rRegI dst, rRegI src) | |
| 3110 %{ | |
| 3111 if ($dst$$reg < 8) { | |
| 3112 if ($src$$reg < 8) { | |
| 3113 emit_opcode(cbuf, Assembler::REX_W); | |
| 3114 } else { | |
| 3115 emit_opcode(cbuf, Assembler::REX_WB); | |
| 3116 } | |
| 3117 } else { | |
| 3118 if ($src$$reg < 8) { | |
| 3119 emit_opcode(cbuf, Assembler::REX_WR); | |
| 3120 } else { | |
| 3121 emit_opcode(cbuf, Assembler::REX_WRB); | |
| 3122 } | |
| 3123 } | |
| 3124 %} | |
| 3125 | |
| 3126 enc_class REX_reg_mem(rRegI reg, memory mem) | |
| 3127 %{ | |
| 3128 if ($reg$$reg < 8) { | |
| 3129 if ($mem$$base < 8) { | |
| 3130 if ($mem$$index >= 8) { | |
| 3131 emit_opcode(cbuf, Assembler::REX_X); | |
| 3132 } | |
| 3133 } else { | |
| 3134 if ($mem$$index < 8) { | |
| 3135 emit_opcode(cbuf, Assembler::REX_B); | |
| 3136 } else { | |
| 3137 emit_opcode(cbuf, Assembler::REX_XB); | |
| 3138 } | |
| 3139 } | |
| 3140 } else { | |
| 3141 if ($mem$$base < 8) { | |
| 3142 if ($mem$$index < 8) { | |
| 3143 emit_opcode(cbuf, Assembler::REX_R); | |
| 3144 } else { | |
| 3145 emit_opcode(cbuf, Assembler::REX_RX); | |
| 3146 } | |
| 3147 } else { | |
| 3148 if ($mem$$index < 8) { | |
| 3149 emit_opcode(cbuf, Assembler::REX_RB); | |
| 3150 } else { | |
| 3151 emit_opcode(cbuf, Assembler::REX_RXB); | |
| 3152 } | |
| 3153 } | |
| 3154 } | |
| 3155 %} | |
| 3156 | |
| 3157 enc_class REX_reg_mem_wide(rRegL reg, memory mem) | |
| 3158 %{ | |
| 3159 if ($reg$$reg < 8) { | |
| 3160 if ($mem$$base < 8) { | |
| 3161 if ($mem$$index < 8) { | |
| 3162 emit_opcode(cbuf, Assembler::REX_W); | |
| 3163 } else { | |
| 3164 emit_opcode(cbuf, Assembler::REX_WX); | |
| 3165 } | |
| 3166 } else { | |
| 3167 if ($mem$$index < 8) { | |
| 3168 emit_opcode(cbuf, Assembler::REX_WB); | |
| 3169 } else { | |
| 3170 emit_opcode(cbuf, Assembler::REX_WXB); | |
| 3171 } | |
| 3172 } | |
| 3173 } else { | |
| 3174 if ($mem$$base < 8) { | |
| 3175 if ($mem$$index < 8) { | |
| 3176 emit_opcode(cbuf, Assembler::REX_WR); | |
| 3177 } else { | |
| 3178 emit_opcode(cbuf, Assembler::REX_WRX); | |
| 3179 } | |
| 3180 } else { | |
| 3181 if ($mem$$index < 8) { | |
| 3182 emit_opcode(cbuf, Assembler::REX_WRB); | |
| 3183 } else { | |
| 3184 emit_opcode(cbuf, Assembler::REX_WRXB); | |
| 3185 } | |
| 3186 } | |
| 3187 } | |
| 3188 %} | |
| 3189 | |
| 3190 enc_class reg_mem(rRegI ereg, memory mem) | |
| 3191 %{ | |
| 3192 // High registers handle in encode_RegMem | |
| 3193 int reg = $ereg$$reg; | |
| 3194 int base = $mem$$base; | |
| 3195 int index = $mem$$index; | |
| 3196 int scale = $mem$$scale; | |
| 3197 int disp = $mem$$disp; | |
| 3198 bool disp_is_oop = $mem->disp_is_oop(); | |
| 3199 | |
| 3200 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_is_oop); | |
| 3201 %} | |
| 3202 | |
| 3203 enc_class RM_opc_mem(immI rm_opcode, memory mem) | |
| 3204 %{ | |
| 3205 int rm_byte_opcode = $rm_opcode$$constant; | |
| 3206 | |
| 3207 // High registers handle in encode_RegMem | |
| 3208 int base = $mem$$base; | |
| 3209 int index = $mem$$index; | |
| 3210 int scale = $mem$$scale; | |
| 3211 int displace = $mem$$disp; | |
| 3212 | |
| 3213 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when | |
| 3214 // working with static | |
| 3215 // globals | |
| 3216 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, | |
| 3217 disp_is_oop); | |
| 3218 %} | |
| 3219 | |
| 3220 enc_class reg_lea(rRegI dst, rRegI src0, immI src1) | |
| 3221 %{ | |
| 3222 int reg_encoding = $dst$$reg; | |
| 3223 int base = $src0$$reg; // 0xFFFFFFFF indicates no base | |
| 3224 int index = 0x04; // 0x04 indicates no index | |
| 3225 int scale = 0x00; // 0x00 indicates no scale | |
| 3226 int displace = $src1$$constant; // 0x00 indicates no displacement | |
| 3227 bool disp_is_oop = false; | |
| 3228 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, | |
| 3229 disp_is_oop); | |
| 3230 %} | |
| 3231 | |
| 3232 enc_class neg_reg(rRegI dst) | |
| 3233 %{ | |
| 3234 int dstenc = $dst$$reg; | |
| 3235 if (dstenc >= 8) { | |
| 3236 emit_opcode(cbuf, Assembler::REX_B); | |
| 3237 dstenc -= 8; | |
| 3238 } | |
| 3239 // NEG $dst | |
| 3240 emit_opcode(cbuf, 0xF7); | |
| 3241 emit_rm(cbuf, 0x3, 0x03, dstenc); | |
| 3242 %} | |
| 3243 | |
| 3244 enc_class neg_reg_wide(rRegI dst) | |
| 3245 %{ | |
| 3246 int dstenc = $dst$$reg; | |
| 3247 if (dstenc < 8) { | |
| 3248 emit_opcode(cbuf, Assembler::REX_W); | |
| 3249 } else { | |
| 3250 emit_opcode(cbuf, Assembler::REX_WB); | |
| 3251 dstenc -= 8; | |
| 3252 } | |
| 3253 // NEG $dst | |
| 3254 emit_opcode(cbuf, 0xF7); | |
| 3255 emit_rm(cbuf, 0x3, 0x03, dstenc); | |
| 3256 %} | |
| 3257 | |
| 3258 enc_class setLT_reg(rRegI dst) | |
| 3259 %{ | |
| 3260 int dstenc = $dst$$reg; | |
| 3261 if (dstenc >= 8) { | |
| 3262 emit_opcode(cbuf, Assembler::REX_B); | |
| 3263 dstenc -= 8; | |
| 3264 } else if (dstenc >= 4) { | |
| 3265 emit_opcode(cbuf, Assembler::REX); | |
| 3266 } | |
| 3267 // SETLT $dst | |
| 3268 emit_opcode(cbuf, 0x0F); | |
| 3269 emit_opcode(cbuf, 0x9C); | |
| 3270 emit_rm(cbuf, 0x3, 0x0, dstenc); | |
| 3271 %} | |
| 3272 | |
| 3273 enc_class setNZ_reg(rRegI dst) | |
| 3274 %{ | |
| 3275 int dstenc = $dst$$reg; | |
| 3276 if (dstenc >= 8) { | |
| 3277 emit_opcode(cbuf, Assembler::REX_B); | |
| 3278 dstenc -= 8; | |
| 3279 } else if (dstenc >= 4) { | |
| 3280 emit_opcode(cbuf, Assembler::REX); | |
| 3281 } | |
| 3282 // SETNZ $dst | |
| 3283 emit_opcode(cbuf, 0x0F); | |
| 3284 emit_opcode(cbuf, 0x95); | |
| 3285 emit_rm(cbuf, 0x3, 0x0, dstenc); | |
| 3286 %} | |
| 3287 | |
| 3288 enc_class enc_cmpLTP(no_rcx_RegI p, no_rcx_RegI q, no_rcx_RegI y, | |
| 3289 rcx_RegI tmp) | |
| 3290 %{ | |
| 3291 // cadd_cmpLT | |
| 3292 | |
| 3293 int tmpReg = $tmp$$reg; | |
| 3294 | |
| 3295 int penc = $p$$reg; | |
| 3296 int qenc = $q$$reg; | |
| 3297 int yenc = $y$$reg; | |
| 3298 | |
| 3299 // subl $p,$q | |
| 3300 if (penc < 8) { | |
| 3301 if (qenc >= 8) { | |
| 3302 emit_opcode(cbuf, Assembler::REX_B); | |
| 3303 } | |
| 3304 } else { | |
| 3305 if (qenc < 8) { | |
| 3306 emit_opcode(cbuf, Assembler::REX_R); | |
| 3307 } else { | |
| 3308 emit_opcode(cbuf, Assembler::REX_RB); | |
| 3309 } | |
| 3310 } | |
| 3311 emit_opcode(cbuf, 0x2B); | |
| 3312 emit_rm(cbuf, 0x3, penc & 7, qenc & 7); | |
| 3313 | |
| 3314 // sbbl $tmp, $tmp | |
| 3315 emit_opcode(cbuf, 0x1B); | |
| 3316 emit_rm(cbuf, 0x3, tmpReg, tmpReg); | |
| 3317 | |
| 3318 // andl $tmp, $y | |
| 3319 if (yenc >= 8) { | |
| 3320 emit_opcode(cbuf, Assembler::REX_B); | |
| 3321 } | |
| 3322 emit_opcode(cbuf, 0x23); | |
| 3323 emit_rm(cbuf, 0x3, tmpReg, yenc & 7); | |
| 3324 | |
| 3325 // addl $p,$tmp | |
| 3326 if (penc >= 8) { | |
| 3327 emit_opcode(cbuf, Assembler::REX_R); | |
| 3328 } | |
| 3329 emit_opcode(cbuf, 0x03); | |
| 3330 emit_rm(cbuf, 0x3, penc & 7, tmpReg); | |
| 3331 %} | |
| 3332 | |
| 3333 // Compare the lonogs and set -1, 0, or 1 into dst | |
| 3334 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst) | |
| 3335 %{ | |
| 3336 int src1enc = $src1$$reg; | |
| 3337 int src2enc = $src2$$reg; | |
| 3338 int dstenc = $dst$$reg; | |
| 3339 | |
| 3340 // cmpq $src1, $src2 | |
| 3341 if (src1enc < 8) { | |
| 3342 if (src2enc < 8) { | |
| 3343 emit_opcode(cbuf, Assembler::REX_W); | |
| 3344 } else { | |
| 3345 emit_opcode(cbuf, Assembler::REX_WB); | |
| 3346 } | |
| 3347 } else { | |
| 3348 if (src2enc < 8) { | |
| 3349 emit_opcode(cbuf, Assembler::REX_WR); | |
| 3350 } else { | |
| 3351 emit_opcode(cbuf, Assembler::REX_WRB); | |
| 3352 } | |
| 3353 } | |
| 3354 emit_opcode(cbuf, 0x3B); | |
| 3355 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7); | |
| 3356 | |
| 3357 // movl $dst, -1 | |
| 3358 if (dstenc >= 8) { | |
| 3359 emit_opcode(cbuf, Assembler::REX_B); | |
| 3360 } | |
| 3361 emit_opcode(cbuf, 0xB8 | (dstenc & 7)); | |
| 3362 emit_d32(cbuf, -1); | |
| 3363 | |
| 3364 // jl,s done | |
| 3365 emit_opcode(cbuf, 0x7C); | |
| 3366 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08); | |
| 3367 | |
| 3368 // setne $dst | |
| 3369 if (dstenc >= 4) { | |
| 3370 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B); | |
| 3371 } | |
| 3372 emit_opcode(cbuf, 0x0F); | |
| 3373 emit_opcode(cbuf, 0x95); | |
| 3374 emit_opcode(cbuf, 0xC0 | (dstenc & 7)); | |
| 3375 | |
| 3376 // movzbl $dst, $dst | |
| 3377 if (dstenc >= 4) { | |
| 3378 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB); | |
| 3379 } | |
| 3380 emit_opcode(cbuf, 0x0F); | |
| 3381 emit_opcode(cbuf, 0xB6); | |
| 3382 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7); | |
| 3383 %} | |
| 3384 | |
| 3385 enc_class Push_ResultXD(regD dst) %{ | |
| 3386 int dstenc = $dst$$reg; | |
| 3387 | |
| 3388 store_to_stackslot( cbuf, 0xDD, 0x03, 0 ); //FSTP [RSP] | |
| 3389 | |
| 3390 // UseXmmLoadAndClearUpper ? movsd dst,[rsp] : movlpd dst,[rsp] | |
| 3391 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66); | |
| 3392 if (dstenc >= 8) { | |
| 3393 emit_opcode(cbuf, Assembler::REX_R); | |
| 3394 } | |
| 3395 emit_opcode (cbuf, 0x0F ); | |
| 3396 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12 ); | |
| 3397 encode_RegMem(cbuf, dstenc, RSP_enc, 0x4, 0, 0, false); | |
| 3398 | |
| 3399 // add rsp,8 | |
| 3400 emit_opcode(cbuf, Assembler::REX_W); | |
| 3401 emit_opcode(cbuf,0x83); | |
| 3402 emit_rm(cbuf,0x3, 0x0, RSP_enc); | |
| 3403 emit_d8(cbuf,0x08); | |
| 3404 %} | |
| 3405 | |
| 3406 enc_class Push_SrcXD(regD src) %{ | |
| 3407 int srcenc = $src$$reg; | |
| 3408 | |
| 3409 // subq rsp,#8 | |
| 3410 emit_opcode(cbuf, Assembler::REX_W); | |
| 3411 emit_opcode(cbuf, 0x83); | |
| 3412 emit_rm(cbuf, 0x3, 0x5, RSP_enc); | |
| 3413 emit_d8(cbuf, 0x8); | |
| 3414 | |
| 3415 // movsd [rsp],src | |
| 3416 emit_opcode(cbuf, 0xF2); | |
| 3417 if (srcenc >= 8) { | |
| 3418 emit_opcode(cbuf, Assembler::REX_R); | |
| 3419 } | |
| 3420 emit_opcode(cbuf, 0x0F); | |
| 3421 emit_opcode(cbuf, 0x11); | |
| 3422 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); | |
| 3423 | |
| 3424 // fldd [rsp] | |
| 3425 emit_opcode(cbuf, 0x66); | |
| 3426 emit_opcode(cbuf, 0xDD); | |
| 3427 encode_RegMem(cbuf, 0x0, RSP_enc, 0x4, 0, 0, false); | |
| 3428 %} | |
| 3429 | |
| 3430 | |
| 3431 enc_class movq_ld(regD dst, memory mem) %{ | |
| 3432 MacroAssembler _masm(&cbuf); | |
| 624 | 3433 __ movq($dst$$XMMRegister, $mem$$Address); |
| 0 | 3434 %} |
| 3435 | |
| 3436 enc_class movq_st(memory mem, regD src) %{ | |
| 3437 MacroAssembler _masm(&cbuf); | |
| 624 | 3438 __ movq($mem$$Address, $src$$XMMRegister); |
| 0 | 3439 %} |
| 3440 | |
| 3441 enc_class pshufd_8x8(regF dst, regF src) %{ | |
| 3442 MacroAssembler _masm(&cbuf); | |
| 3443 | |
| 3444 encode_CopyXD(cbuf, $dst$$reg, $src$$reg); | |
| 3445 __ punpcklbw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg)); | |
| 3446 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg), 0x00); | |
| 3447 %} | |
| 3448 | |
| 3449 enc_class pshufd_4x16(regF dst, regF src) %{ | |
| 3450 MacroAssembler _masm(&cbuf); | |
| 3451 | |
| 3452 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), 0x00); | |
| 3453 %} | |
| 3454 | |
| 3455 enc_class pshufd(regD dst, regD src, int mode) %{ | |
| 3456 MacroAssembler _masm(&cbuf); | |
| 3457 | |
| 3458 __ pshufd(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), $mode); | |
| 3459 %} | |
| 3460 | |
| 3461 enc_class pxor(regD dst, regD src) %{ | |
| 3462 MacroAssembler _masm(&cbuf); | |
| 3463 | |
| 3464 __ pxor(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg)); | |
| 3465 %} | |
| 3466 | |
| 3467 enc_class mov_i2x(regD dst, rRegI src) %{ | |
| 3468 MacroAssembler _masm(&cbuf); | |
| 3469 | |
| 3470 __ movdl(as_XMMRegister($dst$$reg), as_Register($src$$reg)); | |
| 3471 %} | |
| 3472 | |
| 3473 // obj: object to lock | |
| 3474 // box: box address (header location) -- killed | |
| 3475 // tmp: rax -- killed | |
| 3476 // scr: rbx -- killed | |
| 3477 // | |
| 3478 // What follows is a direct transliteration of fast_lock() and fast_unlock() | |
| 3479 // from i486.ad. See that file for comments. | |
| 3480 // TODO: where possible switch from movq (r, 0) to movl(r,0) and | |
| 3481 // use the shorter encoding. (Movl clears the high-order 32-bits). | |
| 3482 | |
| 3483 | |
| 3484 enc_class Fast_Lock(rRegP obj, rRegP box, rax_RegI tmp, rRegP scr) | |
| 3485 %{ | |
| 3486 Register objReg = as_Register((int)$obj$$reg); | |
| 3487 Register boxReg = as_Register((int)$box$$reg); | |
| 3488 Register tmpReg = as_Register($tmp$$reg); | |
| 3489 Register scrReg = as_Register($scr$$reg); | |
| 3490 MacroAssembler masm(&cbuf); | |
| 3491 | |
| 3492 // Verify uniqueness of register assignments -- necessary but not sufficient | |
| 3493 assert (objReg != boxReg && objReg != tmpReg && | |
| 3494 objReg != scrReg && tmpReg != scrReg, "invariant") ; | |
| 3495 | |
| 3496 if (_counters != NULL) { | |
| 3497 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr())); | |
| 3498 } | |
| 3499 if (EmitSync & 1) { | |
| 304 | 3500 // Without cast to int32_t a movptr will destroy r10 which is typically obj |
| 3501 masm.movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ; | |
| 3502 masm.cmpptr(rsp, (int32_t)NULL_WORD) ; | |
| 0 | 3503 } else |
| 3504 if (EmitSync & 2) { | |
| 3505 Label DONE_LABEL; | |
| 3506 if (UseBiasedLocking) { | |
| 3507 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument. | |
| 3508 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters); | |
| 3509 } | |
| 304 | 3510 // QQQ was movl... |
| 3511 masm.movptr(tmpReg, 0x1); | |
| 3512 masm.orptr(tmpReg, Address(objReg, 0)); | |
| 3513 masm.movptr(Address(boxReg, 0), tmpReg); | |
| 0 | 3514 if (os::is_MP()) { |
| 3515 masm.lock(); | |
| 3516 } | |
| 304 | 3517 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg |
| 0 | 3518 masm.jcc(Assembler::equal, DONE_LABEL); |
| 3519 | |
| 3520 // Recursive locking | |
| 304 | 3521 masm.subptr(tmpReg, rsp); |
| 3522 masm.andptr(tmpReg, 7 - os::vm_page_size()); | |
| 3523 masm.movptr(Address(boxReg, 0), tmpReg); | |
| 0 | 3524 |
| 3525 masm.bind(DONE_LABEL); | |
| 3526 masm.nop(); // avoid branch to branch | |
| 3527 } else { | |
| 3528 Label DONE_LABEL, IsInflated, Egress; | |
| 3529 | |
| 304 | 3530 masm.movptr(tmpReg, Address(objReg, 0)) ; |
| 3531 masm.testl (tmpReg, 0x02) ; // inflated vs stack-locked|neutral|biased | |
| 3532 masm.jcc (Assembler::notZero, IsInflated) ; | |
| 3533 | |
| 0 | 3534 // it's stack-locked, biased or neutral |
| 3535 // TODO: optimize markword triage order to reduce the number of | |
| 3536 // conditional branches in the most common cases. | |
| 3537 // Beware -- there's a subtle invariant that fetch of the markword | |
| 3538 // at [FETCH], below, will never observe a biased encoding (*101b). | |
| 3539 // If this invariant is not held we'll suffer exclusion (safety) failure. | |
| 3540 | |
|
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|
3541 if (UseBiasedLocking && !UseOptoBiasInlining) { |
| 0 | 3542 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, true, DONE_LABEL, NULL, _counters); |
| 304 | 3543 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH] |
| 0 | 3544 } |
| 3545 | |
| 304 | 3546 // was q will it destroy high? |
| 3547 masm.orl (tmpReg, 1) ; | |
| 3548 masm.movptr(Address(boxReg, 0), tmpReg) ; | |
| 3549 if (os::is_MP()) { masm.lock(); } | |
| 3550 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg | |
| 0 | 3551 if (_counters != NULL) { |
| 3552 masm.cond_inc32(Assembler::equal, | |
| 3553 ExternalAddress((address) _counters->fast_path_entry_count_addr())); | |
| 3554 } | |
| 3555 masm.jcc (Assembler::equal, DONE_LABEL); | |
| 3556 | |
| 3557 // Recursive locking | |
| 304 | 3558 masm.subptr(tmpReg, rsp); |
| 3559 masm.andptr(tmpReg, 7 - os::vm_page_size()); | |
| 3560 masm.movptr(Address(boxReg, 0), tmpReg); | |
| 0 | 3561 if (_counters != NULL) { |
| 3562 masm.cond_inc32(Assembler::equal, | |
| 3563 ExternalAddress((address) _counters->fast_path_entry_count_addr())); | |
| 3564 } | |
| 3565 masm.jmp (DONE_LABEL) ; | |
| 3566 | |
| 3567 masm.bind (IsInflated) ; | |
| 3568 // It's inflated | |
| 3569 | |
| 3570 // TODO: someday avoid the ST-before-CAS penalty by | |
| 3571 // relocating (deferring) the following ST. | |
| 3572 // We should also think about trying a CAS without having | |
| 3573 // fetched _owner. If the CAS is successful we may | |
| 3574 // avoid an RTO->RTS upgrade on the $line. | |
| 304 | 3575 // Without cast to int32_t a movptr will destroy r10 which is typically obj |
| 3576 masm.movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ; | |
| 3577 | |
| 3578 masm.mov (boxReg, tmpReg) ; | |
| 3579 masm.movptr (tmpReg, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; | |
| 3580 masm.testptr(tmpReg, tmpReg) ; | |
| 3581 masm.jcc (Assembler::notZero, DONE_LABEL) ; | |
| 0 | 3582 |
| 3583 // It's inflated and appears unlocked | |
| 304 | 3584 if (os::is_MP()) { masm.lock(); } |
| 3585 masm.cmpxchgptr(r15_thread, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; | |
| 0 | 3586 // Intentional fall-through into DONE_LABEL ... |
| 3587 | |
| 3588 masm.bind (DONE_LABEL) ; | |
| 3589 masm.nop () ; // avoid jmp to jmp | |
| 3590 } | |
| 3591 %} | |
| 3592 | |
| 3593 // obj: object to unlock | |
| 3594 // box: box address (displaced header location), killed | |
| 3595 // RBX: killed tmp; cannot be obj nor box | |
| 3596 enc_class Fast_Unlock(rRegP obj, rax_RegP box, rRegP tmp) | |
| 3597 %{ | |
| 3598 | |
| 3599 Register objReg = as_Register($obj$$reg); | |
| 3600 Register boxReg = as_Register($box$$reg); | |
| 3601 Register tmpReg = as_Register($tmp$$reg); | |
| 3602 MacroAssembler masm(&cbuf); | |
| 3603 | |
| 304 | 3604 if (EmitSync & 4) { |
| 3605 masm.cmpptr(rsp, 0) ; | |
| 0 | 3606 } else |
| 3607 if (EmitSync & 8) { | |
| 3608 Label DONE_LABEL; | |
| 3609 if (UseBiasedLocking) { | |
| 3610 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); | |
| 3611 } | |
| 3612 | |
| 3613 // Check whether the displaced header is 0 | |
| 3614 //(=> recursive unlock) | |
| 304 | 3615 masm.movptr(tmpReg, Address(boxReg, 0)); |
| 3616 masm.testptr(tmpReg, tmpReg); | |
| 0 | 3617 masm.jcc(Assembler::zero, DONE_LABEL); |
| 3618 | |
| 3619 // If not recursive lock, reset the header to displaced header | |
| 3620 if (os::is_MP()) { | |
| 3621 masm.lock(); | |
| 3622 } | |
| 304 | 3623 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box |
| 0 | 3624 masm.bind(DONE_LABEL); |
| 3625 masm.nop(); // avoid branch to branch | |
| 3626 } else { | |
| 3627 Label DONE_LABEL, Stacked, CheckSucc ; | |
| 3628 | |
|
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diff
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|
3629 if (UseBiasedLocking && !UseOptoBiasInlining) { |
| 0 | 3630 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); |
| 3631 } | |
| 304 | 3632 |
| 3633 masm.movptr(tmpReg, Address(objReg, 0)) ; | |
| 3634 masm.cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD) ; | |
| 3635 masm.jcc (Assembler::zero, DONE_LABEL) ; | |
| 3636 masm.testl (tmpReg, 0x02) ; | |
| 3637 masm.jcc (Assembler::zero, Stacked) ; | |
| 3638 | |
| 0 | 3639 // It's inflated |
| 304 | 3640 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
| 3641 masm.xorptr(boxReg, r15_thread) ; | |
| 3642 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ; | |
| 3643 masm.jcc (Assembler::notZero, DONE_LABEL) ; | |
| 3644 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ; | |
| 3645 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ; | |
| 3646 masm.jcc (Assembler::notZero, CheckSucc) ; | |
| 3647 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ; | |
| 3648 masm.jmp (DONE_LABEL) ; | |
| 3649 | |
| 3650 if ((EmitSync & 65536) == 0) { | |
| 0 | 3651 Label LSuccess, LGoSlowPath ; |
| 3652 masm.bind (CheckSucc) ; | |
| 304 | 3653 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ; |
| 0 | 3654 masm.jcc (Assembler::zero, LGoSlowPath) ; |
| 3655 | |
| 3656 // I'd much rather use lock:andl m->_owner, 0 as it's faster than the | |
| 3657 // the explicit ST;MEMBAR combination, but masm doesn't currently support | |
| 3658 // "ANDQ M,IMM". Don't use MFENCE here. lock:add to TOS, xchg, etc | |
| 3659 // are all faster when the write buffer is populated. | |
| 304 | 3660 masm.movptr (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ; |
| 0 | 3661 if (os::is_MP()) { |
| 304 | 3662 masm.lock () ; masm.addl (Address(rsp, 0), 0) ; |
| 0 | 3663 } |
| 304 | 3664 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ; |
| 0 | 3665 masm.jcc (Assembler::notZero, LSuccess) ; |
| 3666 | |
| 304 | 3667 masm.movptr (boxReg, (int32_t)NULL_WORD) ; // box is really EAX |
| 0 | 3668 if (os::is_MP()) { masm.lock(); } |
| 304 | 3669 masm.cmpxchgptr(r15_thread, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)); |
| 0 | 3670 masm.jcc (Assembler::notEqual, LSuccess) ; |
| 3671 // Intentional fall-through into slow-path | |
| 3672 | |
| 3673 masm.bind (LGoSlowPath) ; | |
| 3674 masm.orl (boxReg, 1) ; // set ICC.ZF=0 to indicate failure | |
| 3675 masm.jmp (DONE_LABEL) ; | |
| 3676 | |
| 3677 masm.bind (LSuccess) ; | |
| 3678 masm.testl (boxReg, 0) ; // set ICC.ZF=1 to indicate success | |
| 3679 masm.jmp (DONE_LABEL) ; | |
| 3680 } | |
| 3681 | |
| 304 | 3682 masm.bind (Stacked) ; |
| 3683 masm.movptr(tmpReg, Address (boxReg, 0)) ; // re-fetch | |
| 3684 if (os::is_MP()) { masm.lock(); } | |
| 3685 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box | |
| 0 | 3686 |
| 3687 if (EmitSync & 65536) { | |
| 3688 masm.bind (CheckSucc) ; | |
| 3689 } | |
| 3690 masm.bind(DONE_LABEL); | |
| 3691 if (EmitSync & 32768) { | |
| 3692 masm.nop(); // avoid branch to branch | |
| 3693 } | |
| 3694 } | |
| 3695 %} | |
| 3696 | |
| 3697 enc_class enc_String_Compare() | |
| 3698 %{ | |
| 3699 Label RCX_GOOD_LABEL, LENGTH_DIFF_LABEL, | |
| 3700 POP_LABEL, DONE_LABEL, CONT_LABEL, | |
| 3701 WHILE_HEAD_LABEL; | |
| 3702 MacroAssembler masm(&cbuf); | |
| 3703 | |
| 3704 // Get the first character position in both strings | |
| 3705 // [8] char array, [12] offset, [16] count | |
| 3706 int value_offset = java_lang_String::value_offset_in_bytes(); | |
| 3707 int offset_offset = java_lang_String::offset_offset_in_bytes(); | |
| 3708 int count_offset = java_lang_String::count_offset_in_bytes(); | |
| 3709 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); | |
| 3710 | |
|
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|
3711 masm.load_heap_oop(rax, Address(rsi, value_offset)); |
| 0 | 3712 masm.movl(rcx, Address(rsi, offset_offset)); |
| 304 | 3713 masm.lea(rax, Address(rax, rcx, Address::times_2, base_offset)); |
|
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|
3714 masm.load_heap_oop(rbx, Address(rdi, value_offset)); |
| 0 | 3715 masm.movl(rcx, Address(rdi, offset_offset)); |
| 304 | 3716 masm.lea(rbx, Address(rbx, rcx, Address::times_2, base_offset)); |
| 0 | 3717 |
| 3718 // Compute the minimum of the string lengths(rsi) and the | |
| 3719 // difference of the string lengths (stack) | |
| 3720 | |
| 3721 masm.movl(rdi, Address(rdi, count_offset)); | |
| 3722 masm.movl(rsi, Address(rsi, count_offset)); | |
| 3723 masm.movl(rcx, rdi); | |
| 3724 masm.subl(rdi, rsi); | |
| 304 | 3725 masm.push(rdi); |
| 3726 masm.cmov(Assembler::lessEqual, rsi, rcx); | |
| 0 | 3727 |
| 3728 // Is the minimum length zero? | |
| 3729 masm.bind(RCX_GOOD_LABEL); | |
| 3730 masm.testl(rsi, rsi); | |
| 3731 masm.jcc(Assembler::zero, LENGTH_DIFF_LABEL); | |
| 3732 | |
| 3733 // Load first characters | |
|
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|
3734 masm.load_unsigned_short(rcx, Address(rbx, 0)); |
|
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|
3735 masm.load_unsigned_short(rdi, Address(rax, 0)); |
| 0 | 3736 |
| 3737 // Compare first characters | |
| 3738 masm.subl(rcx, rdi); | |
| 3739 masm.jcc(Assembler::notZero, POP_LABEL); | |
| 3740 masm.decrementl(rsi); | |
| 3741 masm.jcc(Assembler::zero, LENGTH_DIFF_LABEL); | |
| 3742 | |
| 3743 { | |
| 3744 // Check after comparing first character to see if strings are equivalent | |
| 3745 Label LSkip2; | |
| 3746 // Check if the strings start at same location | |
| 304 | 3747 masm.cmpptr(rbx, rax); |
| 0 | 3748 masm.jcc(Assembler::notEqual, LSkip2); |
| 3749 | |
| 3750 // Check if the length difference is zero (from stack) | |
| 3751 masm.cmpl(Address(rsp, 0), 0x0); | |
| 3752 masm.jcc(Assembler::equal, LENGTH_DIFF_LABEL); | |
| 3753 | |
| 3754 // Strings might not be equivalent | |
| 3755 masm.bind(LSkip2); | |
| 3756 } | |
| 3757 | |
| 3758 // Shift RAX and RBX to the end of the arrays, negate min | |
| 304 | 3759 masm.lea(rax, Address(rax, rsi, Address::times_2, 2)); |
| 3760 masm.lea(rbx, Address(rbx, rsi, Address::times_2, 2)); | |
| 3761 masm.negptr(rsi); | |
| 0 | 3762 |
| 3763 // Compare the rest of the characters | |
| 3764 masm.bind(WHILE_HEAD_LABEL); | |
|
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|
3765 masm.load_unsigned_short(rcx, Address(rbx, rsi, Address::times_2, 0)); |
|
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|
3766 masm.load_unsigned_short(rdi, Address(rax, rsi, Address::times_2, 0)); |
| 0 | 3767 masm.subl(rcx, rdi); |
| 3768 masm.jcc(Assembler::notZero, POP_LABEL); | |
| 304 | 3769 masm.increment(rsi); |
| 0 | 3770 masm.jcc(Assembler::notZero, WHILE_HEAD_LABEL); |
| 3771 | |
| 3772 // Strings are equal up to min length. Return the length difference. | |
| 3773 masm.bind(LENGTH_DIFF_LABEL); | |
| 304 | 3774 masm.pop(rcx); |
| 0 | 3775 masm.jmp(DONE_LABEL); |
| 3776 | |
| 3777 // Discard the stored length difference | |
| 3778 masm.bind(POP_LABEL); | |
| 304 | 3779 masm.addptr(rsp, 8); |
| 3780 | |
| 0 | 3781 // That's it |
| 3782 masm.bind(DONE_LABEL); | |
| 3783 %} | |
| 3784 | |
|
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3785 enc_class enc_Array_Equals(rdi_RegP ary1, rsi_RegP ary2, rax_RegI tmp1, rbx_RegI tmp2, rcx_RegI result) %{ |
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3786 Label TRUE_LABEL, FALSE_LABEL, DONE_LABEL, COMPARE_LOOP_HDR, COMPARE_LOOP; |
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3787 MacroAssembler masm(&cbuf); |
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3788 |
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3789 Register ary1Reg = as_Register($ary1$$reg); |
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3790 Register ary2Reg = as_Register($ary2$$reg); |
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3791 Register tmp1Reg = as_Register($tmp1$$reg); |
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3792 Register tmp2Reg = as_Register($tmp2$$reg); |
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3793 Register resultReg = as_Register($result$$reg); |
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3794 |
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3795 int length_offset = arrayOopDesc::length_offset_in_bytes(); |
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3796 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); |
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3797 |
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3798 // Check the input args |
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3799 masm.cmpq(ary1Reg, ary2Reg); |
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3800 masm.jcc(Assembler::equal, TRUE_LABEL); |
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3801 masm.testq(ary1Reg, ary1Reg); |
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3802 masm.jcc(Assembler::zero, FALSE_LABEL); |
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3803 masm.testq(ary2Reg, ary2Reg); |
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3804 masm.jcc(Assembler::zero, FALSE_LABEL); |
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3805 |
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3806 // Check the lengths |
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3807 masm.movl(tmp2Reg, Address(ary1Reg, length_offset)); |
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3808 masm.movl(resultReg, Address(ary2Reg, length_offset)); |
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3809 masm.cmpl(tmp2Reg, resultReg); |
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3810 masm.jcc(Assembler::notEqual, FALSE_LABEL); |
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3811 masm.testl(resultReg, resultReg); |
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3812 masm.jcc(Assembler::zero, TRUE_LABEL); |
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3813 |
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3814 // Get the number of 4 byte vectors to compare |
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3815 masm.shrl(resultReg, 1); |
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3816 |
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3817 // Check for odd-length arrays |
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3818 masm.andl(tmp2Reg, 1); |
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3819 masm.testl(tmp2Reg, tmp2Reg); |
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3820 masm.jcc(Assembler::zero, COMPARE_LOOP_HDR); |
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3821 |
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3822 // Compare 2-byte "tail" at end of arrays |
|
622
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3823 masm.load_unsigned_short(tmp1Reg, Address(ary1Reg, resultReg, Address::times_4, base_offset)); |
|
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3824 masm.load_unsigned_short(tmp2Reg, Address(ary2Reg, resultReg, Address::times_4, base_offset)); |
|
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3825 masm.cmpl(tmp1Reg, tmp2Reg); |
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3826 masm.jcc(Assembler::notEqual, FALSE_LABEL); |
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3827 masm.testl(resultReg, resultReg); |
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3828 masm.jcc(Assembler::zero, TRUE_LABEL); |
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3829 |
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3830 // Setup compare loop |
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3831 masm.bind(COMPARE_LOOP_HDR); |
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3832 // Shift tmp1Reg and tmp2Reg to the last 4-byte boundary of the arrays |
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3833 masm.leaq(tmp1Reg, Address(ary1Reg, resultReg, Address::times_4, base_offset)); |
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3834 masm.leaq(tmp2Reg, Address(ary2Reg, resultReg, Address::times_4, base_offset)); |
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3835 masm.negq(resultReg); |
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3836 |
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3837 // 4-byte-wide compare loop |
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3838 masm.bind(COMPARE_LOOP); |
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3839 masm.movl(ary1Reg, Address(tmp1Reg, resultReg, Address::times_4, 0)); |
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3840 masm.movl(ary2Reg, Address(tmp2Reg, resultReg, Address::times_4, 0)); |
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3841 masm.cmpl(ary1Reg, ary2Reg); |
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3842 masm.jcc(Assembler::notEqual, FALSE_LABEL); |
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3843 masm.incrementq(resultReg); |
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3844 masm.jcc(Assembler::notZero, COMPARE_LOOP); |
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3845 |
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3846 masm.bind(TRUE_LABEL); |
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3847 masm.movl(resultReg, 1); // return true |
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3848 masm.jmp(DONE_LABEL); |
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3849 |
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3850 masm.bind(FALSE_LABEL); |
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3851 masm.xorl(resultReg, resultReg); // return false |
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3852 |
|
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3853 // That's it |
|
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3854 masm.bind(DONE_LABEL); |
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3855 %} |
|
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3856 |
| 0 | 3857 enc_class enc_rethrow() |
| 3858 %{ | |
| 3859 cbuf.set_inst_mark(); | |
| 3860 emit_opcode(cbuf, 0xE9); // jmp entry | |
| 3861 emit_d32_reloc(cbuf, | |
| 3862 (int) (OptoRuntime::rethrow_stub() - cbuf.code_end() - 4), | |
| 3863 runtime_call_Relocation::spec(), | |
| 3864 RELOC_DISP32); | |
| 3865 %} | |
| 3866 | |
| 3867 enc_class absF_encoding(regF dst) | |
| 3868 %{ | |
| 3869 int dstenc = $dst$$reg; | |
| 304 | 3870 address signmask_address = (address) StubRoutines::x86::float_sign_mask(); |
| 0 | 3871 |
| 3872 cbuf.set_inst_mark(); | |
| 3873 if (dstenc >= 8) { | |
| 3874 emit_opcode(cbuf, Assembler::REX_R); | |
| 3875 dstenc -= 8; | |
| 3876 } | |
| 3877 // XXX reg_mem doesn't support RIP-relative addressing yet | |
| 3878 emit_opcode(cbuf, 0x0F); | |
| 3879 emit_opcode(cbuf, 0x54); | |
| 3880 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101 | |
| 3881 emit_d32_reloc(cbuf, signmask_address); | |
| 3882 %} | |
| 3883 | |
| 3884 enc_class absD_encoding(regD dst) | |
| 3885 %{ | |
| 3886 int dstenc = $dst$$reg; | |
| 304 | 3887 address signmask_address = (address) StubRoutines::x86::double_sign_mask(); |
| 0 | 3888 |
| 3889 cbuf.set_inst_mark(); | |
| 3890 emit_opcode(cbuf, 0x66); | |
| 3891 if (dstenc >= 8) { | |
| 3892 emit_opcode(cbuf, Assembler::REX_R); | |
| 3893 dstenc -= 8; | |
| 3894 } | |
| 3895 // XXX reg_mem doesn't support RIP-relative addressing yet | |
| 3896 emit_opcode(cbuf, 0x0F); | |
| 3897 emit_opcode(cbuf, 0x54); | |
| 3898 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101 | |
| 3899 emit_d32_reloc(cbuf, signmask_address); | |
| 3900 %} | |
| 3901 | |
| 3902 enc_class negF_encoding(regF dst) | |
| 3903 %{ | |
| 3904 int dstenc = $dst$$reg; | |
| 304 | 3905 address signflip_address = (address) StubRoutines::x86::float_sign_flip(); |
| 0 | 3906 |
| 3907 cbuf.set_inst_mark(); | |
| 3908 if (dstenc >= 8) { | |
| 3909 emit_opcode(cbuf, Assembler::REX_R); | |
| 3910 dstenc -= 8; | |
| 3911 } | |
| 3912 // XXX reg_mem doesn't support RIP-relative addressing yet | |
| 3913 emit_opcode(cbuf, 0x0F); | |
| 3914 emit_opcode(cbuf, 0x57); | |
| 3915 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101 | |
| 3916 emit_d32_reloc(cbuf, signflip_address); | |
| 3917 %} | |
| 3918 | |
| 3919 enc_class negD_encoding(regD dst) | |
| 3920 %{ | |
| 3921 int dstenc = $dst$$reg; | |
| 304 | 3922 address signflip_address = (address) StubRoutines::x86::double_sign_flip(); |
| 0 | 3923 |
| 3924 cbuf.set_inst_mark(); | |
| 3925 emit_opcode(cbuf, 0x66); | |
| 3926 if (dstenc >= 8) { | |
| 3927 emit_opcode(cbuf, Assembler::REX_R); | |
| 3928 dstenc -= 8; | |
| 3929 } | |
| 3930 // XXX reg_mem doesn't support RIP-relative addressing yet | |
| 3931 emit_opcode(cbuf, 0x0F); | |
| 3932 emit_opcode(cbuf, 0x57); | |
| 3933 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101 | |
| 3934 emit_d32_reloc(cbuf, signflip_address); | |
| 3935 %} | |
| 3936 | |
| 3937 enc_class f2i_fixup(rRegI dst, regF src) | |
| 3938 %{ | |
| 3939 int dstenc = $dst$$reg; | |
| 3940 int srcenc = $src$$reg; | |
| 3941 | |
| 3942 // cmpl $dst, #0x80000000 | |
| 3943 if (dstenc >= 8) { | |
| 3944 emit_opcode(cbuf, Assembler::REX_B); | |
| 3945 } | |
| 3946 emit_opcode(cbuf, 0x81); | |
| 3947 emit_rm(cbuf, 0x3, 0x7, dstenc & 7); | |
| 3948 emit_d32(cbuf, 0x80000000); | |
| 3949 | |
| 3950 // jne,s done | |
| 3951 emit_opcode(cbuf, 0x75); | |
| 3952 if (srcenc < 8 && dstenc < 8) { | |
| 3953 emit_d8(cbuf, 0xF); | |
| 3954 } else if (srcenc >= 8 && dstenc >= 8) { | |
| 3955 emit_d8(cbuf, 0x11); | |
| 3956 } else { | |
| 3957 emit_d8(cbuf, 0x10); | |
| 3958 } | |
| 3959 | |
| 3960 // subq rsp, #8 | |
| 3961 emit_opcode(cbuf, Assembler::REX_W); | |
| 3962 emit_opcode(cbuf, 0x83); | |
| 3963 emit_rm(cbuf, 0x3, 0x5, RSP_enc); | |
| 3964 emit_d8(cbuf, 8); | |
| 3965 | |
| 3966 // movss [rsp], $src | |
| 3967 emit_opcode(cbuf, 0xF3); | |
| 3968 if (srcenc >= 8) { | |
| 3969 emit_opcode(cbuf, Assembler::REX_R); | |
| 3970 } | |
| 3971 emit_opcode(cbuf, 0x0F); | |
| 3972 emit_opcode(cbuf, 0x11); | |
| 3973 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes | |
| 3974 | |
| 3975 // call f2i_fixup | |
| 3976 cbuf.set_inst_mark(); | |
| 3977 emit_opcode(cbuf, 0xE8); | |
| 3978 emit_d32_reloc(cbuf, | |
| 3979 (int) | |
| 304 | 3980 (StubRoutines::x86::f2i_fixup() - cbuf.code_end() - 4), |
| 0 | 3981 runtime_call_Relocation::spec(), |
| 3982 RELOC_DISP32); | |
| 3983 | |
| 3984 // popq $dst | |
| 3985 if (dstenc >= 8) { | |
| 3986 emit_opcode(cbuf, Assembler::REX_B); | |
| 3987 } | |
| 3988 emit_opcode(cbuf, 0x58 | (dstenc & 7)); | |
| 3989 | |
| 3990 // done: | |
| 3991 %} | |
| 3992 | |
| 3993 enc_class f2l_fixup(rRegL dst, regF src) | |
| 3994 %{ | |
| 3995 int dstenc = $dst$$reg; | |
| 3996 int srcenc = $src$$reg; | |
| 304 | 3997 address const_address = (address) StubRoutines::x86::double_sign_flip(); |
| 0 | 3998 |
| 3999 // cmpq $dst, [0x8000000000000000] | |
| 4000 cbuf.set_inst_mark(); | |
| 4001 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX_W : Assembler::REX_WR); | |
| 4002 emit_opcode(cbuf, 0x39); | |
| 4003 // XXX reg_mem doesn't support RIP-relative addressing yet | |
| 4004 emit_rm(cbuf, 0x0, dstenc & 7, 0x5); // 00 reg 101 | |
| 4005 emit_d32_reloc(cbuf, const_address); | |
| 4006 | |
| 4007 | |
| 4008 // jne,s done | |
| 4009 emit_opcode(cbuf, 0x75); | |
| 4010 if (srcenc < 8 && dstenc < 8) { | |
| 4011 emit_d8(cbuf, 0xF); | |
| 4012 } else if (srcenc >= 8 && dstenc >= 8) { | |
| 4013 emit_d8(cbuf, 0x11); | |
| 4014 } else { | |
| 4015 emit_d8(cbuf, 0x10); | |
| 4016 } | |
| 4017 | |
| 4018 // subq rsp, #8 | |
| 4019 emit_opcode(cbuf, Assembler::REX_W); | |
| 4020 emit_opcode(cbuf, 0x83); | |
| 4021 emit_rm(cbuf, 0x3, 0x5, RSP_enc); | |
| 4022 emit_d8(cbuf, 8); | |
| 4023 | |
| 4024 // movss [rsp], $src | |
| 4025 emit_opcode(cbuf, 0xF3); | |
| 4026 if (srcenc >= 8) { | |
| 4027 emit_opcode(cbuf, Assembler::REX_R); | |
| 4028 } | |
| 4029 emit_opcode(cbuf, 0x0F); | |
| 4030 emit_opcode(cbuf, 0x11); | |
| 4031 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes | |
| 4032 | |
| 4033 // call f2l_fixup | |
| 4034 cbuf.set_inst_mark(); | |
| 4035 emit_opcode(cbuf, 0xE8); | |
| 4036 emit_d32_reloc(cbuf, | |
| 4037 (int) | |
| 304 | 4038 (StubRoutines::x86::f2l_fixup() - cbuf.code_end() - 4), |
| 0 | 4039 runtime_call_Relocation::spec(), |
| 4040 RELOC_DISP32); | |
| 4041 | |
| 4042 // popq $dst | |
| 4043 if (dstenc >= 8) { | |
| 4044 emit_opcode(cbuf, Assembler::REX_B); | |
| 4045 } | |
| 4046 emit_opcode(cbuf, 0x58 | (dstenc & 7)); | |
| 4047 | |
| 4048 // done: | |
| 4049 %} | |
| 4050 | |
| 4051 enc_class d2i_fixup(rRegI dst, regD src) | |
| 4052 %{ | |
| 4053 int dstenc = $dst$$reg; | |
| 4054 int srcenc = $src$$reg; | |
| 4055 | |
| 4056 // cmpl $dst, #0x80000000 | |
| 4057 if (dstenc >= 8) { | |
| 4058 emit_opcode(cbuf, Assembler::REX_B); | |
| 4059 } | |
| 4060 emit_opcode(cbuf, 0x81); | |
| 4061 emit_rm(cbuf, 0x3, 0x7, dstenc & 7); | |
| 4062 emit_d32(cbuf, 0x80000000); | |
| 4063 | |
| 4064 // jne,s done | |
| 4065 emit_opcode(cbuf, 0x75); | |
| 4066 if (srcenc < 8 && dstenc < 8) { | |
| 4067 emit_d8(cbuf, 0xF); | |
| 4068 } else if (srcenc >= 8 && dstenc >= 8) { | |
| 4069 emit_d8(cbuf, 0x11); | |
| 4070 } else { | |
| 4071 emit_d8(cbuf, 0x10); | |
| 4072 } | |
| 4073 | |
| 4074 // subq rsp, #8 | |
| 4075 emit_opcode(cbuf, Assembler::REX_W); | |
| 4076 emit_opcode(cbuf, 0x83); | |
| 4077 emit_rm(cbuf, 0x3, 0x5, RSP_enc); | |
| 4078 emit_d8(cbuf, 8); | |
| 4079 | |
| 4080 // movsd [rsp], $src | |
| 4081 emit_opcode(cbuf, 0xF2); | |
| 4082 if (srcenc >= 8) { | |
| 4083 emit_opcode(cbuf, Assembler::REX_R); | |
| 4084 } | |
| 4085 emit_opcode(cbuf, 0x0F); | |
| 4086 emit_opcode(cbuf, 0x11); | |
| 4087 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes | |
| 4088 | |
| 4089 // call d2i_fixup | |
| 4090 cbuf.set_inst_mark(); | |
| 4091 emit_opcode(cbuf, 0xE8); | |
| 4092 emit_d32_reloc(cbuf, | |
| 4093 (int) | |
| 304 | 4094 (StubRoutines::x86::d2i_fixup() - cbuf.code_end() - 4), |
| 0 | 4095 runtime_call_Relocation::spec(), |
| 4096 RELOC_DISP32); | |
| 4097 | |
| 4098 // popq $dst | |
| 4099 if (dstenc >= 8) { | |
| 4100 emit_opcode(cbuf, Assembler::REX_B); | |
| 4101 } | |
| 4102 emit_opcode(cbuf, 0x58 | (dstenc & 7)); | |
| 4103 | |
| 4104 // done: | |
| 4105 %} | |
| 4106 | |
| 4107 enc_class d2l_fixup(rRegL dst, regD src) | |
| 4108 %{ | |
| 4109 int dstenc = $dst$$reg; | |
| 4110 int srcenc = $src$$reg; | |
| 304 | 4111 address const_address = (address) StubRoutines::x86::double_sign_flip(); |
| 0 | 4112 |
| 4113 // cmpq $dst, [0x8000000000000000] | |
| 4114 cbuf.set_inst_mark(); | |
| 4115 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX_W : Assembler::REX_WR); | |
| 4116 emit_opcode(cbuf, 0x39); | |
| 4117 // XXX reg_mem doesn't support RIP-relative addressing yet | |
| 4118 emit_rm(cbuf, 0x0, dstenc & 7, 0x5); // 00 reg 101 | |
| 4119 emit_d32_reloc(cbuf, const_address); | |
| 4120 | |
| 4121 | |
| 4122 // jne,s done | |
| 4123 emit_opcode(cbuf, 0x75); | |
| 4124 if (srcenc < 8 && dstenc < 8) { | |
| 4125 emit_d8(cbuf, 0xF); | |
| 4126 } else if (srcenc >= 8 && dstenc >= 8) { | |
| 4127 emit_d8(cbuf, 0x11); | |
| 4128 } else { | |
| 4129 emit_d8(cbuf, 0x10); | |
| 4130 } | |
| 4131 | |
| 4132 // subq rsp, #8 | |
| 4133 emit_opcode(cbuf, Assembler::REX_W); | |
| 4134 emit_opcode(cbuf, 0x83); | |
| 4135 emit_rm(cbuf, 0x3, 0x5, RSP_enc); | |
| 4136 emit_d8(cbuf, 8); | |
| 4137 | |
| 4138 // movsd [rsp], $src | |
| 4139 emit_opcode(cbuf, 0xF2); | |
| 4140 if (srcenc >= 8) { | |
| 4141 emit_opcode(cbuf, Assembler::REX_R); | |
| 4142 } | |
| 4143 emit_opcode(cbuf, 0x0F); | |
| 4144 emit_opcode(cbuf, 0x11); | |
| 4145 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes | |
| 4146 | |
| 4147 // call d2l_fixup | |
| 4148 cbuf.set_inst_mark(); | |
| 4149 emit_opcode(cbuf, 0xE8); | |
| 4150 emit_d32_reloc(cbuf, | |
| 4151 (int) | |
| 304 | 4152 (StubRoutines::x86::d2l_fixup() - cbuf.code_end() - 4), |
| 0 | 4153 runtime_call_Relocation::spec(), |
| 4154 RELOC_DISP32); | |
| 4155 | |
| 4156 // popq $dst | |
| 4157 if (dstenc >= 8) { | |
| 4158 emit_opcode(cbuf, Assembler::REX_B); | |
| 4159 } | |
| 4160 emit_opcode(cbuf, 0x58 | (dstenc & 7)); | |
| 4161 | |
| 4162 // done: | |
| 4163 %} | |
| 4164 | |
| 4165 // Safepoint Poll. This polls the safepoint page, and causes an | |
| 4166 // exception if it is not readable. Unfortunately, it kills | |
| 4167 // RFLAGS in the process. | |
| 4168 enc_class enc_safepoint_poll | |
| 4169 %{ | |
| 4170 // testl %rax, off(%rip) // Opcode + ModRM + Disp32 == 6 bytes | |
| 4171 // XXX reg_mem doesn't support RIP-relative addressing yet | |
| 4172 cbuf.set_inst_mark(); | |
| 4173 cbuf.relocate(cbuf.inst_mark(), relocInfo::poll_type, 0); // XXX | |
| 4174 emit_opcode(cbuf, 0x85); // testl | |
| 4175 emit_rm(cbuf, 0x0, RAX_enc, 0x5); // 00 rax 101 == 0x5 | |
| 4176 // cbuf.inst_mark() is beginning of instruction | |
| 4177 emit_d32_reloc(cbuf, os::get_polling_page()); | |
| 4178 // relocInfo::poll_type, | |
| 4179 %} | |
| 4180 %} | |
| 4181 | |
| 4182 | |
|
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4183 |
| 0 | 4184 //----------FRAME-------------------------------------------------------------- |
| 4185 // Definition of frame structure and management information. | |
| 4186 // | |
| 4187 // S T A C K L A Y O U T Allocators stack-slot number | |
| 4188 // | (to get allocators register number | |
| 4189 // G Owned by | | v add OptoReg::stack0()) | |
| 4190 // r CALLER | | | |
| 4191 // o | +--------+ pad to even-align allocators stack-slot | |
| 4192 // w V | pad0 | numbers; owned by CALLER | |
| 4193 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned | |
| 4194 // h ^ | in | 5 | |
| 4195 // | | args | 4 Holes in incoming args owned by SELF | |
| 4196 // | | | | 3 | |
| 4197 // | | +--------+ | |
| 4198 // V | | old out| Empty on Intel, window on Sparc | |
| 4199 // | old |preserve| Must be even aligned. | |
| 4200 // | SP-+--------+----> Matcher::_old_SP, even aligned | |
| 4201 // | | in | 3 area for Intel ret address | |
| 4202 // Owned by |preserve| Empty on Sparc. | |
| 4203 // SELF +--------+ | |
| 4204 // | | pad2 | 2 pad to align old SP | |
| 4205 // | +--------+ 1 | |
| 4206 // | | locks | 0 | |
| 4207 // | +--------+----> OptoReg::stack0(), even aligned | |
| 4208 // | | pad1 | 11 pad to align new SP | |
| 4209 // | +--------+ | |
| 4210 // | | | 10 | |
| 4211 // | | spills | 9 spills | |
| 4212 // V | | 8 (pad0 slot for callee) | |
| 4213 // -----------+--------+----> Matcher::_out_arg_limit, unaligned | |
| 4214 // ^ | out | 7 | |
| 4215 // | | args | 6 Holes in outgoing args owned by CALLEE | |
| 4216 // Owned by +--------+ | |
| 4217 // CALLEE | new out| 6 Empty on Intel, window on Sparc | |
| 4218 // | new |preserve| Must be even-aligned. | |
| 4219 // | SP-+--------+----> Matcher::_new_SP, even aligned | |
| 4220 // | | | | |
| 4221 // | |
| 4222 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is | |
| 4223 // known from SELF's arguments and the Java calling convention. | |
| 4224 // Region 6-7 is determined per call site. | |
| 4225 // Note 2: If the calling convention leaves holes in the incoming argument | |
| 4226 // area, those holes are owned by SELF. Holes in the outgoing area | |
| 4227 // are owned by the CALLEE. Holes should not be nessecary in the | |
| 4228 // incoming area, as the Java calling convention is completely under | |
| 4229 // the control of the AD file. Doubles can be sorted and packed to | |
| 4230 // avoid holes. Holes in the outgoing arguments may be nessecary for | |
| 4231 // varargs C calling conventions. | |
| 4232 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is | |
| 4233 // even aligned with pad0 as needed. | |
| 4234 // Region 6 is even aligned. Region 6-7 is NOT even aligned; | |
| 4235 // region 6-11 is even aligned; it may be padded out more so that | |
| 4236 // the region from SP to FP meets the minimum stack alignment. | |
| 4237 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack | |
| 4238 // alignment. Region 11, pad1, may be dynamically extended so that | |
| 4239 // SP meets the minimum alignment. | |
| 4240 | |
| 4241 frame | |
| 4242 %{ | |
| 4243 // What direction does stack grow in (assumed to be same for C & Java) | |
| 4244 stack_direction(TOWARDS_LOW); | |
| 4245 | |
| 4246 // These three registers define part of the calling convention | |
| 4247 // between compiled code and the interpreter. | |
| 4248 inline_cache_reg(RAX); // Inline Cache Register | |
| 4249 interpreter_method_oop_reg(RBX); // Method Oop Register when | |
| 4250 // calling interpreter | |
| 4251 | |
| 4252 // Optional: name the operand used by cisc-spilling to access | |
| 4253 // [stack_pointer + offset] | |
| 4254 cisc_spilling_operand_name(indOffset32); | |
| 4255 | |
| 4256 // Number of stack slots consumed by locking an object | |
| 4257 sync_stack_slots(2); | |
| 4258 | |
| 4259 // Compiled code's Frame Pointer | |
| 4260 frame_pointer(RSP); | |
| 4261 | |
| 4262 // Interpreter stores its frame pointer in a register which is | |
| 4263 // stored to the stack by I2CAdaptors. | |
| 4264 // I2CAdaptors convert from interpreted java to compiled java. | |
| 4265 interpreter_frame_pointer(RBP); | |
| 4266 | |
| 4267 // Stack alignment requirement | |
| 4268 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes) | |
| 4269 | |
| 4270 // Number of stack slots between incoming argument block and the start of | |
| 4271 // a new frame. The PROLOG must add this many slots to the stack. The | |
| 4272 // EPILOG must remove this many slots. amd64 needs two slots for | |
| 4273 // return address. | |
| 4274 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls); | |
| 4275 | |
| 4276 // Number of outgoing stack slots killed above the out_preserve_stack_slots | |
| 4277 // for calls to C. Supports the var-args backing area for register parms. | |
| 4278 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt); | |
| 4279 | |
| 4280 // The after-PROLOG location of the return address. Location of | |
| 4281 // return address specifies a type (REG or STACK) and a number | |
| 4282 // representing the register number (i.e. - use a register name) or | |
| 4283 // stack slot. | |
| 4284 // Ret Addr is on stack in slot 0 if no locks or verification or alignment. | |
| 4285 // Otherwise, it is above the locks and verification slot and alignment word | |
| 4286 return_addr(STACK - 2 + | |
| 4287 round_to(2 + 2 * VerifyStackAtCalls + | |
| 4288 Compile::current()->fixed_slots(), | |
| 4289 WordsPerLong * 2)); | |
| 4290 | |
| 4291 // Body of function which returns an integer array locating | |
| 4292 // arguments either in registers or in stack slots. Passed an array | |
| 4293 // of ideal registers called "sig" and a "length" count. Stack-slot | |
| 4294 // offsets are based on outgoing arguments, i.e. a CALLER setting up | |
| 4295 // arguments for a CALLEE. Incoming stack arguments are | |
| 4296 // automatically biased by the preserve_stack_slots field above. | |
| 4297 | |
| 4298 calling_convention | |
| 4299 %{ | |
| 4300 // No difference between ingoing/outgoing just pass false | |
| 4301 SharedRuntime::java_calling_convention(sig_bt, regs, length, false); | |
| 4302 %} | |
| 4303 | |
| 4304 c_calling_convention | |
| 4305 %{ | |
| 4306 // This is obviously always outgoing | |
| 4307 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); | |
| 4308 %} | |
| 4309 | |
| 4310 // Location of compiled Java return values. Same as C for now. | |
| 4311 return_value | |
| 4312 %{ | |
| 4313 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, | |
| 4314 "only return normal values"); | |
| 4315 | |
| 4316 static const int lo[Op_RegL + 1] = { | |
| 4317 0, | |
| 4318 0, | |
|
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4319 RAX_num, // Op_RegN |
| 0 | 4320 RAX_num, // Op_RegI |
| 4321 RAX_num, // Op_RegP | |
| 4322 XMM0_num, // Op_RegF | |
| 4323 XMM0_num, // Op_RegD | |
| 4324 RAX_num // Op_RegL | |
| 4325 }; | |
| 4326 static const int hi[Op_RegL + 1] = { | |
| 4327 0, | |
| 4328 0, | |
|
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4329 OptoReg::Bad, // Op_RegN |
| 0 | 4330 OptoReg::Bad, // Op_RegI |
| 4331 RAX_H_num, // Op_RegP | |
| 4332 OptoReg::Bad, // Op_RegF | |
| 4333 XMM0_H_num, // Op_RegD | |
| 4334 RAX_H_num // Op_RegL | |
| 4335 }; | |
|
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4336 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 1, "missing type"); |
| 0 | 4337 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]); |
| 4338 %} | |
| 4339 %} | |
| 4340 | |
| 4341 //----------ATTRIBUTES--------------------------------------------------------- | |
| 4342 //----------Operand Attributes------------------------------------------------- | |
| 4343 op_attrib op_cost(0); // Required cost attribute | |
| 4344 | |
| 4345 //----------Instruction Attributes--------------------------------------------- | |
| 4346 ins_attrib ins_cost(100); // Required cost attribute | |
| 4347 ins_attrib ins_size(8); // Required size attribute (in bits) | |
| 4348 ins_attrib ins_pc_relative(0); // Required PC Relative flag | |
| 4349 ins_attrib ins_short_branch(0); // Required flag: is this instruction | |
| 4350 // a non-matching short branch variant | |
| 4351 // of some long branch? | |
| 4352 ins_attrib ins_alignment(1); // Required alignment attribute (must | |
| 4353 // be a power of 2) specifies the | |
| 4354 // alignment that some part of the | |
| 4355 // instruction (not necessarily the | |
| 4356 // start) requires. If > 1, a | |
| 4357 // compute_padding() function must be | |
| 4358 // provided for the instruction | |
| 4359 | |
| 4360 //----------OPERANDS----------------------------------------------------------- | |
| 4361 // Operand definitions must precede instruction definitions for correct parsing | |
| 4362 // in the ADLC because operands constitute user defined types which are used in | |
| 4363 // instruction definitions. | |
| 4364 | |
| 4365 //----------Simple Operands---------------------------------------------------- | |
| 4366 // Immediate Operands | |
| 4367 // Integer Immediate | |
| 4368 operand immI() | |
| 4369 %{ | |
| 4370 match(ConI); | |
| 4371 | |
| 4372 op_cost(10); | |
| 4373 format %{ %} | |
| 4374 interface(CONST_INTER); | |
| 4375 %} | |
| 4376 | |
| 4377 // Constant for test vs zero | |
| 4378 operand immI0() | |
| 4379 %{ | |
| 4380 predicate(n->get_int() == 0); | |
| 4381 match(ConI); | |
| 4382 | |
| 4383 op_cost(0); | |
| 4384 format %{ %} | |
| 4385 interface(CONST_INTER); | |
| 4386 %} | |
| 4387 | |
| 4388 // Constant for increment | |
| 4389 operand immI1() | |
| 4390 %{ | |
| 4391 predicate(n->get_int() == 1); | |
| 4392 match(ConI); | |
| 4393 | |
| 4394 op_cost(0); | |
| 4395 format %{ %} | |
| 4396 interface(CONST_INTER); | |
| 4397 %} | |
| 4398 | |
| 4399 // Constant for decrement | |
| 4400 operand immI_M1() | |
| 4401 %{ | |
| 4402 predicate(n->get_int() == -1); | |
| 4403 match(ConI); | |
| 4404 | |
| 4405 op_cost(0); | |
| 4406 format %{ %} | |
| 4407 interface(CONST_INTER); | |
| 4408 %} | |
| 4409 | |
| 4410 // Valid scale values for addressing modes | |
| 4411 operand immI2() | |
| 4412 %{ | |
| 4413 predicate(0 <= n->get_int() && (n->get_int() <= 3)); | |
| 4414 match(ConI); | |
| 4415 | |
| 4416 format %{ %} | |
| 4417 interface(CONST_INTER); | |
| 4418 %} | |
| 4419 | |
| 4420 operand immI8() | |
| 4421 %{ | |
| 4422 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80)); | |
| 4423 match(ConI); | |
| 4424 | |
| 4425 op_cost(5); | |
| 4426 format %{ %} | |
| 4427 interface(CONST_INTER); | |
| 4428 %} | |
| 4429 | |
| 4430 operand immI16() | |
| 4431 %{ | |
| 4432 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767)); | |
| 4433 match(ConI); | |
| 4434 | |
| 4435 op_cost(10); | |
| 4436 format %{ %} | |
| 4437 interface(CONST_INTER); | |
| 4438 %} | |
| 4439 | |
| 4440 // Constant for long shifts | |
| 4441 operand immI_32() | |
| 4442 %{ | |
| 4443 predicate( n->get_int() == 32 ); | |
| 4444 match(ConI); | |
| 4445 | |
| 4446 op_cost(0); | |
| 4447 format %{ %} | |
| 4448 interface(CONST_INTER); | |
| 4449 %} | |
| 4450 | |
| 4451 // Constant for long shifts | |
| 4452 operand immI_64() | |
| 4453 %{ | |
| 4454 predicate( n->get_int() == 64 ); | |
| 4455 match(ConI); | |
| 4456 | |
| 4457 op_cost(0); | |
| 4458 format %{ %} | |
| 4459 interface(CONST_INTER); | |
| 4460 %} | |
| 4461 | |
| 4462 // Pointer Immediate | |
| 4463 operand immP() | |
| 4464 %{ | |
| 4465 match(ConP); | |
| 4466 | |
| 4467 op_cost(10); | |
| 4468 format %{ %} | |
| 4469 interface(CONST_INTER); | |
| 4470 %} | |
| 4471 | |
| 4472 // NULL Pointer Immediate | |
| 4473 operand immP0() | |
| 4474 %{ | |
| 4475 predicate(n->get_ptr() == 0); | |
| 4476 match(ConP); | |
| 4477 | |
| 4478 op_cost(5); | |
| 4479 format %{ %} | |
| 4480 interface(CONST_INTER); | |
| 4481 %} | |
| 4482 | |
|
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4483 // Pointer Immediate |
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4484 operand immN() %{ |
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4485 match(ConN); |
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4486 |
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4487 op_cost(10); |
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4488 format %{ %} |
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4489 interface(CONST_INTER); |
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4490 %} |
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4491 |
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4492 // NULL Pointer Immediate |
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4493 operand immN0() %{ |
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4494 predicate(n->get_narrowcon() == 0); |
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4495 match(ConN); |
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4496 |
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4497 op_cost(5); |
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4498 format %{ %} |
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4499 interface(CONST_INTER); |
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4500 %} |
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4501 |
| 0 | 4502 operand immP31() |
| 4503 %{ | |
| 4504 predicate(!n->as_Type()->type()->isa_oopptr() | |
| 4505 && (n->get_ptr() >> 31) == 0); | |
| 4506 match(ConP); | |
| 4507 | |
| 4508 op_cost(5); | |
| 4509 format %{ %} | |
| 4510 interface(CONST_INTER); | |
| 4511 %} | |
| 4512 | |
|
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4513 |
| 0 | 4514 // Long Immediate |
| 4515 operand immL() | |
| 4516 %{ | |
| 4517 match(ConL); | |
| 4518 | |
| 4519 op_cost(20); | |
| 4520 format %{ %} | |
| 4521 interface(CONST_INTER); | |
| 4522 %} | |
| 4523 | |
| 4524 // Long Immediate 8-bit | |
| 4525 operand immL8() | |
| 4526 %{ | |
| 4527 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L); | |
| 4528 match(ConL); | |
| 4529 | |
| 4530 op_cost(5); | |
| 4531 format %{ %} | |
| 4532 interface(CONST_INTER); | |
| 4533 %} | |
| 4534 | |
| 4535 // Long Immediate 32-bit unsigned | |
| 4536 operand immUL32() | |
| 4537 %{ | |
| 4538 predicate(n->get_long() == (unsigned int) (n->get_long())); | |
| 4539 match(ConL); | |
| 4540 | |
| 4541 op_cost(10); | |
| 4542 format %{ %} | |
| 4543 interface(CONST_INTER); | |
| 4544 %} | |
| 4545 | |
| 4546 // Long Immediate 32-bit signed | |
| 4547 operand immL32() | |
| 4548 %{ | |
| 4549 predicate(n->get_long() == (int) (n->get_long())); | |
| 4550 match(ConL); | |
| 4551 | |
| 4552 op_cost(15); | |
| 4553 format %{ %} | |
| 4554 interface(CONST_INTER); | |
| 4555 %} | |
| 4556 | |
| 4557 // Long Immediate zero | |
| 4558 operand immL0() | |
| 4559 %{ | |
| 4560 predicate(n->get_long() == 0L); | |
| 4561 match(ConL); | |
| 4562 | |
| 4563 op_cost(10); | |
| 4564 format %{ %} | |
| 4565 interface(CONST_INTER); | |
| 4566 %} | |
| 4567 | |
| 4568 // Constant for increment | |
| 4569 operand immL1() | |
| 4570 %{ | |
| 4571 predicate(n->get_long() == 1); | |
| 4572 match(ConL); | |
| 4573 | |
| 4574 format %{ %} | |
| 4575 interface(CONST_INTER); | |
| 4576 %} | |
| 4577 | |
| 4578 // Constant for decrement | |
| 4579 operand immL_M1() | |
| 4580 %{ | |
| 4581 predicate(n->get_long() == -1); | |
| 4582 match(ConL); | |
| 4583 | |
| 4584 format %{ %} | |
| 4585 interface(CONST_INTER); | |
| 4586 %} | |
| 4587 | |
| 4588 // Long Immediate: the value 10 | |
| 4589 operand immL10() | |
| 4590 %{ | |
| 4591 predicate(n->get_long() == 10); | |
| 4592 match(ConL); | |
| 4593 | |
| 4594 format %{ %} | |
| 4595 interface(CONST_INTER); | |
| 4596 %} | |
| 4597 | |
| 4598 // Long immediate from 0 to 127. | |
| 4599 // Used for a shorter form of long mul by 10. | |
| 4600 operand immL_127() | |
| 4601 %{ | |
| 4602 predicate(0 <= n->get_long() && n->get_long() < 0x80); | |
| 4603 match(ConL); | |
| 4604 | |
| 4605 op_cost(10); | |
| 4606 format %{ %} | |
| 4607 interface(CONST_INTER); | |
| 4608 %} | |
| 4609 | |
| 4610 // Long Immediate: low 32-bit mask | |
| 4611 operand immL_32bits() | |
| 4612 %{ | |
| 4613 predicate(n->get_long() == 0xFFFFFFFFL); | |
| 4614 match(ConL); | |
| 4615 op_cost(20); | |
| 4616 | |
| 4617 format %{ %} | |
| 4618 interface(CONST_INTER); | |
| 4619 %} | |
| 4620 | |
| 4621 // Float Immediate zero | |
| 4622 operand immF0() | |
| 4623 %{ | |
| 4624 predicate(jint_cast(n->getf()) == 0); | |
| 4625 match(ConF); | |
| 4626 | |
| 4627 op_cost(5); | |
| 4628 format %{ %} | |
| 4629 interface(CONST_INTER); | |
| 4630 %} | |
| 4631 | |
| 4632 // Float Immediate | |
| 4633 operand immF() | |
| 4634 %{ | |
| 4635 match(ConF); | |
| 4636 | |
| 4637 op_cost(15); | |
| 4638 format %{ %} | |
| 4639 interface(CONST_INTER); | |
| 4640 %} | |
| 4641 | |
| 4642 // Double Immediate zero | |
| 4643 operand immD0() | |
| 4644 %{ | |
| 4645 predicate(jlong_cast(n->getd()) == 0); | |
| 4646 match(ConD); | |
| 4647 | |
| 4648 op_cost(5); | |
| 4649 format %{ %} | |
| 4650 interface(CONST_INTER); | |
| 4651 %} | |
| 4652 | |
| 4653 // Double Immediate | |
| 4654 operand immD() | |
| 4655 %{ | |
| 4656 match(ConD); | |
| 4657 | |
| 4658 op_cost(15); | |
| 4659 format %{ %} | |
| 4660 interface(CONST_INTER); | |
| 4661 %} | |
| 4662 | |
| 4663 // Immediates for special shifts (sign extend) | |
| 4664 | |
| 4665 // Constants for increment | |
| 4666 operand immI_16() | |
| 4667 %{ | |
| 4668 predicate(n->get_int() == 16); | |
| 4669 match(ConI); | |
| 4670 | |
| 4671 format %{ %} | |
| 4672 interface(CONST_INTER); | |
| 4673 %} | |
| 4674 | |
| 4675 operand immI_24() | |
| 4676 %{ | |
| 4677 predicate(n->get_int() == 24); | |
| 4678 match(ConI); | |
| 4679 | |
| 4680 format %{ %} | |
| 4681 interface(CONST_INTER); | |
| 4682 %} | |
| 4683 | |
| 4684 // Constant for byte-wide masking | |
| 4685 operand immI_255() | |
| 4686 %{ | |
| 4687 predicate(n->get_int() == 255); | |
| 4688 match(ConI); | |
| 4689 | |
| 4690 format %{ %} | |
| 4691 interface(CONST_INTER); | |
| 4692 %} | |
| 4693 | |
| 4694 // Constant for short-wide masking | |
| 4695 operand immI_65535() | |
| 4696 %{ | |
| 4697 predicate(n->get_int() == 65535); | |
| 4698 match(ConI); | |
| 4699 | |
| 4700 format %{ %} | |
| 4701 interface(CONST_INTER); | |
| 4702 %} | |
| 4703 | |
| 4704 // Constant for byte-wide masking | |
| 4705 operand immL_255() | |
| 4706 %{ | |
| 4707 predicate(n->get_long() == 255); | |
| 4708 match(ConL); | |
| 4709 | |
| 4710 format %{ %} | |
| 4711 interface(CONST_INTER); | |
| 4712 %} | |
| 4713 | |
| 4714 // Constant for short-wide masking | |
| 4715 operand immL_65535() | |
| 4716 %{ | |
| 4717 predicate(n->get_long() == 65535); | |
| 4718 match(ConL); | |
| 4719 | |
| 4720 format %{ %} | |
| 4721 interface(CONST_INTER); | |
| 4722 %} | |
| 4723 | |
| 4724 // Register Operands | |
| 4725 // Integer Register | |
| 4726 operand rRegI() | |
| 4727 %{ | |
| 4728 constraint(ALLOC_IN_RC(int_reg)); | |
| 4729 match(RegI); | |
| 4730 | |
| 4731 match(rax_RegI); | |
| 4732 match(rbx_RegI); | |
| 4733 match(rcx_RegI); | |
| 4734 match(rdx_RegI); | |
| 4735 match(rdi_RegI); | |
| 4736 | |
| 4737 format %{ %} | |
| 4738 interface(REG_INTER); | |
| 4739 %} | |
| 4740 | |
| 4741 // Special Registers | |
| 4742 operand rax_RegI() | |
| 4743 %{ | |
| 4744 constraint(ALLOC_IN_RC(int_rax_reg)); | |
| 4745 match(RegI); | |
| 4746 match(rRegI); | |
| 4747 | |
| 4748 format %{ "RAX" %} | |
| 4749 interface(REG_INTER); | |
| 4750 %} | |
| 4751 | |
| 4752 // Special Registers | |
| 4753 operand rbx_RegI() | |
| 4754 %{ | |
| 4755 constraint(ALLOC_IN_RC(int_rbx_reg)); | |
| 4756 match(RegI); | |
| 4757 match(rRegI); | |
| 4758 | |
| 4759 format %{ "RBX" %} | |
| 4760 interface(REG_INTER); | |
| 4761 %} | |
| 4762 | |
| 4763 operand rcx_RegI() | |
| 4764 %{ | |
| 4765 constraint(ALLOC_IN_RC(int_rcx_reg)); | |
| 4766 match(RegI); | |
| 4767 match(rRegI); | |
| 4768 | |
| 4769 format %{ "RCX" %} | |
| 4770 interface(REG_INTER); | |
| 4771 %} | |
| 4772 | |
| 4773 operand rdx_RegI() | |
| 4774 %{ | |
| 4775 constraint(ALLOC_IN_RC(int_rdx_reg)); | |
| 4776 match(RegI); | |
| 4777 match(rRegI); | |
| 4778 | |
| 4779 format %{ "RDX" %} | |
| 4780 interface(REG_INTER); | |
| 4781 %} | |
| 4782 | |
| 4783 operand rdi_RegI() | |
| 4784 %{ | |
| 4785 constraint(ALLOC_IN_RC(int_rdi_reg)); | |
| 4786 match(RegI); | |
| 4787 match(rRegI); | |
| 4788 | |
| 4789 format %{ "RDI" %} | |
| 4790 interface(REG_INTER); | |
| 4791 %} | |
| 4792 | |
| 4793 operand no_rcx_RegI() | |
| 4794 %{ | |
| 4795 constraint(ALLOC_IN_RC(int_no_rcx_reg)); | |
| 4796 match(RegI); | |
| 4797 match(rax_RegI); | |
| 4798 match(rbx_RegI); | |
| 4799 match(rdx_RegI); | |
| 4800 match(rdi_RegI); | |
| 4801 | |
| 4802 format %{ %} | |
| 4803 interface(REG_INTER); | |
| 4804 %} | |
| 4805 | |
| 4806 operand no_rax_rdx_RegI() | |
| 4807 %{ | |
| 4808 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg)); | |
| 4809 match(RegI); | |
| 4810 match(rbx_RegI); | |
| 4811 match(rcx_RegI); | |
| 4812 match(rdi_RegI); | |
| 4813 | |
| 4814 format %{ %} | |
| 4815 interface(REG_INTER); | |
| 4816 %} | |
| 4817 | |
| 4818 // Pointer Register | |
| 4819 operand any_RegP() | |
| 4820 %{ | |
| 4821 constraint(ALLOC_IN_RC(any_reg)); | |
| 4822 match(RegP); | |
| 4823 match(rax_RegP); | |
| 4824 match(rbx_RegP); | |
| 4825 match(rdi_RegP); | |
| 4826 match(rsi_RegP); | |
| 4827 match(rbp_RegP); | |
| 4828 match(r15_RegP); | |
| 4829 match(rRegP); | |
| 4830 | |
| 4831 format %{ %} | |
| 4832 interface(REG_INTER); | |
| 4833 %} | |
| 4834 | |
| 4835 operand rRegP() | |
| 4836 %{ | |
| 4837 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 4838 match(RegP); | |
| 4839 match(rax_RegP); | |
| 4840 match(rbx_RegP); | |
| 4841 match(rdi_RegP); | |
| 4842 match(rsi_RegP); | |
| 4843 match(rbp_RegP); | |
| 4844 match(r15_RegP); // See Q&A below about r15_RegP. | |
| 4845 | |
| 4846 format %{ %} | |
| 4847 interface(REG_INTER); | |
| 4848 %} | |
| 4849 | |
|
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4850 operand rRegN() %{ |
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4851 constraint(ALLOC_IN_RC(int_reg)); |
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4852 match(RegN); |
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4853 |
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4854 format %{ %} |
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4855 interface(REG_INTER); |
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4856 %} |
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4857 |
| 0 | 4858 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP? |
| 4859 // Answer: Operand match rules govern the DFA as it processes instruction inputs. | |
| 4860 // It's fine for an instruction input which expects rRegP to match a r15_RegP. | |
| 4861 // The output of an instruction is controlled by the allocator, which respects | |
| 4862 // register class masks, not match rules. Unless an instruction mentions | |
| 4863 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered | |
| 4864 // by the allocator as an input. | |
| 4865 | |
| 4866 operand no_rax_RegP() | |
| 4867 %{ | |
| 4868 constraint(ALLOC_IN_RC(ptr_no_rax_reg)); | |
| 4869 match(RegP); | |
| 4870 match(rbx_RegP); | |
| 4871 match(rsi_RegP); | |
| 4872 match(rdi_RegP); | |
| 4873 | |
| 4874 format %{ %} | |
| 4875 interface(REG_INTER); | |
| 4876 %} | |
| 4877 | |
| 4878 operand no_rbp_RegP() | |
| 4879 %{ | |
| 4880 constraint(ALLOC_IN_RC(ptr_no_rbp_reg)); | |
| 4881 match(RegP); | |
| 4882 match(rbx_RegP); | |
| 4883 match(rsi_RegP); | |
| 4884 match(rdi_RegP); | |
| 4885 | |
| 4886 format %{ %} | |
| 4887 interface(REG_INTER); | |
| 4888 %} | |
| 4889 | |
| 4890 operand no_rax_rbx_RegP() | |
| 4891 %{ | |
| 4892 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg)); | |
| 4893 match(RegP); | |
| 4894 match(rsi_RegP); | |
| 4895 match(rdi_RegP); | |
| 4896 | |
| 4897 format %{ %} | |
| 4898 interface(REG_INTER); | |
| 4899 %} | |
| 4900 | |
| 4901 // Special Registers | |
| 4902 // Return a pointer value | |
| 4903 operand rax_RegP() | |
| 4904 %{ | |
| 4905 constraint(ALLOC_IN_RC(ptr_rax_reg)); | |
| 4906 match(RegP); | |
| 4907 match(rRegP); | |
| 4908 | |
| 4909 format %{ %} | |
| 4910 interface(REG_INTER); | |
| 4911 %} | |
| 4912 | |
|
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4913 // Special Registers |
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4914 // Return a compressed pointer value |
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4915 operand rax_RegN() |
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4916 %{ |
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4917 constraint(ALLOC_IN_RC(int_rax_reg)); |
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4918 match(RegN); |
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4919 match(rRegN); |
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4920 |
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4921 format %{ %} |
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4922 interface(REG_INTER); |
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4923 %} |
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4924 |
| 0 | 4925 // Used in AtomicAdd |
| 4926 operand rbx_RegP() | |
| 4927 %{ | |
| 4928 constraint(ALLOC_IN_RC(ptr_rbx_reg)); | |
| 4929 match(RegP); | |
| 4930 match(rRegP); | |
| 4931 | |
| 4932 format %{ %} | |
| 4933 interface(REG_INTER); | |
| 4934 %} | |
| 4935 | |
| 4936 operand rsi_RegP() | |
| 4937 %{ | |
| 4938 constraint(ALLOC_IN_RC(ptr_rsi_reg)); | |
| 4939 match(RegP); | |
| 4940 match(rRegP); | |
| 4941 | |
| 4942 format %{ %} | |
| 4943 interface(REG_INTER); | |
| 4944 %} | |
| 4945 | |
| 4946 // Used in rep stosq | |
| 4947 operand rdi_RegP() | |
| 4948 %{ | |
| 4949 constraint(ALLOC_IN_RC(ptr_rdi_reg)); | |
| 4950 match(RegP); | |
| 4951 match(rRegP); | |
| 4952 | |
| 4953 format %{ %} | |
| 4954 interface(REG_INTER); | |
| 4955 %} | |
| 4956 | |
| 4957 operand rbp_RegP() | |
| 4958 %{ | |
| 4959 constraint(ALLOC_IN_RC(ptr_rbp_reg)); | |
| 4960 match(RegP); | |
| 4961 match(rRegP); | |
| 4962 | |
| 4963 format %{ %} | |
| 4964 interface(REG_INTER); | |
| 4965 %} | |
| 4966 | |
| 4967 operand r15_RegP() | |
| 4968 %{ | |
| 4969 constraint(ALLOC_IN_RC(ptr_r15_reg)); | |
| 4970 match(RegP); | |
| 4971 match(rRegP); | |
| 4972 | |
| 4973 format %{ %} | |
| 4974 interface(REG_INTER); | |
| 4975 %} | |
| 4976 | |
| 4977 operand rRegL() | |
| 4978 %{ | |
| 4979 constraint(ALLOC_IN_RC(long_reg)); | |
| 4980 match(RegL); | |
| 4981 match(rax_RegL); | |
| 4982 match(rdx_RegL); | |
| 4983 | |
| 4984 format %{ %} | |
| 4985 interface(REG_INTER); | |
| 4986 %} | |
| 4987 | |
| 4988 // Special Registers | |
| 4989 operand no_rax_rdx_RegL() | |
| 4990 %{ | |
| 4991 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg)); | |
| 4992 match(RegL); | |
| 4993 match(rRegL); | |
| 4994 | |
| 4995 format %{ %} | |
| 4996 interface(REG_INTER); | |
| 4997 %} | |
| 4998 | |
| 4999 operand no_rax_RegL() | |
| 5000 %{ | |
| 5001 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg)); | |
| 5002 match(RegL); | |
| 5003 match(rRegL); | |
| 5004 match(rdx_RegL); | |
| 5005 | |
| 5006 format %{ %} | |
| 5007 interface(REG_INTER); | |
| 5008 %} | |
| 5009 | |
| 5010 operand no_rcx_RegL() | |
| 5011 %{ | |
| 5012 constraint(ALLOC_IN_RC(long_no_rcx_reg)); | |
| 5013 match(RegL); | |
| 5014 match(rRegL); | |
| 5015 | |
| 5016 format %{ %} | |
| 5017 interface(REG_INTER); | |
| 5018 %} | |
| 5019 | |
| 5020 operand rax_RegL() | |
| 5021 %{ | |
| 5022 constraint(ALLOC_IN_RC(long_rax_reg)); | |
| 5023 match(RegL); | |
| 5024 match(rRegL); | |
| 5025 | |
| 5026 format %{ "RAX" %} | |
| 5027 interface(REG_INTER); | |
| 5028 %} | |
| 5029 | |
| 5030 operand rcx_RegL() | |
| 5031 %{ | |
| 5032 constraint(ALLOC_IN_RC(long_rcx_reg)); | |
| 5033 match(RegL); | |
| 5034 match(rRegL); | |
| 5035 | |
| 5036 format %{ %} | |
| 5037 interface(REG_INTER); | |
| 5038 %} | |
| 5039 | |
| 5040 operand rdx_RegL() | |
| 5041 %{ | |
| 5042 constraint(ALLOC_IN_RC(long_rdx_reg)); | |
| 5043 match(RegL); | |
| 5044 match(rRegL); | |
| 5045 | |
| 5046 format %{ %} | |
| 5047 interface(REG_INTER); | |
| 5048 %} | |
| 5049 | |
| 5050 // Flags register, used as output of compare instructions | |
| 5051 operand rFlagsReg() | |
| 5052 %{ | |
| 5053 constraint(ALLOC_IN_RC(int_flags)); | |
| 5054 match(RegFlags); | |
| 5055 | |
| 5056 format %{ "RFLAGS" %} | |
| 5057 interface(REG_INTER); | |
| 5058 %} | |
| 5059 | |
| 5060 // Flags register, used as output of FLOATING POINT compare instructions | |
| 5061 operand rFlagsRegU() | |
| 5062 %{ | |
| 5063 constraint(ALLOC_IN_RC(int_flags)); | |
| 5064 match(RegFlags); | |
| 5065 | |
| 5066 format %{ "RFLAGS_U" %} | |
| 5067 interface(REG_INTER); | |
| 5068 %} | |
| 5069 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5070 operand rFlagsRegUCF() %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5071 constraint(ALLOC_IN_RC(int_flags)); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5072 match(RegFlags); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5073 predicate(false); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5074 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5075 format %{ "RFLAGS_U_CF" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5076 interface(REG_INTER); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5077 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5078 |
| 0 | 5079 // Float register operands |
| 5080 operand regF() | |
| 5081 %{ | |
| 5082 constraint(ALLOC_IN_RC(float_reg)); | |
| 5083 match(RegF); | |
| 5084 | |
| 5085 format %{ %} | |
| 5086 interface(REG_INTER); | |
| 5087 %} | |
| 5088 | |
| 5089 // Double register operands | |
| 5090 operand regD() | |
| 5091 %{ | |
| 5092 constraint(ALLOC_IN_RC(double_reg)); | |
| 5093 match(RegD); | |
| 5094 | |
| 5095 format %{ %} | |
| 5096 interface(REG_INTER); | |
| 5097 %} | |
| 5098 | |
| 5099 | |
| 5100 //----------Memory Operands---------------------------------------------------- | |
| 5101 // Direct Memory Operand | |
| 5102 // operand direct(immP addr) | |
| 5103 // %{ | |
| 5104 // match(addr); | |
| 5105 | |
| 5106 // format %{ "[$addr]" %} | |
| 5107 // interface(MEMORY_INTER) %{ | |
| 5108 // base(0xFFFFFFFF); | |
| 5109 // index(0x4); | |
| 5110 // scale(0x0); | |
| 5111 // disp($addr); | |
| 5112 // %} | |
| 5113 // %} | |
| 5114 | |
| 5115 // Indirect Memory Operand | |
| 5116 operand indirect(any_RegP reg) | |
| 5117 %{ | |
| 5118 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 5119 match(reg); | |
| 5120 | |
| 5121 format %{ "[$reg]" %} | |
| 5122 interface(MEMORY_INTER) %{ | |
| 5123 base($reg); | |
| 5124 index(0x4); | |
| 5125 scale(0x0); | |
| 5126 disp(0x0); | |
| 5127 %} | |
| 5128 %} | |
| 5129 | |
| 5130 // Indirect Memory Plus Short Offset Operand | |
| 5131 operand indOffset8(any_RegP reg, immL8 off) | |
| 5132 %{ | |
| 5133 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 5134 match(AddP reg off); | |
| 5135 | |
| 5136 format %{ "[$reg + $off (8-bit)]" %} | |
| 5137 interface(MEMORY_INTER) %{ | |
| 5138 base($reg); | |
| 5139 index(0x4); | |
| 5140 scale(0x0); | |
| 5141 disp($off); | |
| 5142 %} | |
| 5143 %} | |
| 5144 | |
| 5145 // Indirect Memory Plus Long Offset Operand | |
| 5146 operand indOffset32(any_RegP reg, immL32 off) | |
| 5147 %{ | |
| 5148 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 5149 match(AddP reg off); | |
| 5150 | |
| 5151 format %{ "[$reg + $off (32-bit)]" %} | |
| 5152 interface(MEMORY_INTER) %{ | |
| 5153 base($reg); | |
| 5154 index(0x4); | |
| 5155 scale(0x0); | |
| 5156 disp($off); | |
| 5157 %} | |
| 5158 %} | |
| 5159 | |
| 5160 // Indirect Memory Plus Index Register Plus Offset Operand | |
| 5161 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off) | |
| 5162 %{ | |
| 5163 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 5164 match(AddP (AddP reg lreg) off); | |
| 5165 | |
| 5166 op_cost(10); | |
| 5167 format %{"[$reg + $off + $lreg]" %} | |
| 5168 interface(MEMORY_INTER) %{ | |
| 5169 base($reg); | |
| 5170 index($lreg); | |
| 5171 scale(0x0); | |
| 5172 disp($off); | |
| 5173 %} | |
| 5174 %} | |
| 5175 | |
| 5176 // Indirect Memory Plus Index Register Plus Offset Operand | |
| 5177 operand indIndex(any_RegP reg, rRegL lreg) | |
| 5178 %{ | |
| 5179 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 5180 match(AddP reg lreg); | |
| 5181 | |
| 5182 op_cost(10); | |
| 5183 format %{"[$reg + $lreg]" %} | |
| 5184 interface(MEMORY_INTER) %{ | |
| 5185 base($reg); | |
| 5186 index($lreg); | |
| 5187 scale(0x0); | |
| 5188 disp(0x0); | |
| 5189 %} | |
| 5190 %} | |
| 5191 | |
| 5192 // Indirect Memory Times Scale Plus Index Register | |
| 5193 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale) | |
| 5194 %{ | |
| 5195 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 5196 match(AddP reg (LShiftL lreg scale)); | |
| 5197 | |
| 5198 op_cost(10); | |
| 5199 format %{"[$reg + $lreg << $scale]" %} | |
| 5200 interface(MEMORY_INTER) %{ | |
| 5201 base($reg); | |
| 5202 index($lreg); | |
| 5203 scale($scale); | |
| 5204 disp(0x0); | |
| 5205 %} | |
| 5206 %} | |
| 5207 | |
| 5208 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand | |
| 5209 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale) | |
| 5210 %{ | |
| 5211 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 5212 match(AddP (AddP reg (LShiftL lreg scale)) off); | |
| 5213 | |
| 5214 op_cost(10); | |
| 5215 format %{"[$reg + $off + $lreg << $scale]" %} | |
| 5216 interface(MEMORY_INTER) %{ | |
| 5217 base($reg); | |
| 5218 index($lreg); | |
| 5219 scale($scale); | |
| 5220 disp($off); | |
| 5221 %} | |
| 5222 %} | |
| 5223 | |
| 5224 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand | |
| 5225 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale) | |
| 5226 %{ | |
| 5227 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 5228 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0); | |
| 5229 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off); | |
| 5230 | |
| 5231 op_cost(10); | |
| 5232 format %{"[$reg + $off + $idx << $scale]" %} | |
| 5233 interface(MEMORY_INTER) %{ | |
| 5234 base($reg); | |
| 5235 index($idx); | |
| 5236 scale($scale); | |
| 5237 disp($off); | |
| 5238 %} | |
| 5239 %} | |
| 5240 | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5241 // Indirect Narrow Oop Plus Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5242 // Note: x86 architecture doesn't support "scale * index + offset" without a base |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5243 // we can't free r12 even with Universe::narrow_oop_base() == NULL. |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5244 operand indCompressedOopOffset(rRegN reg, immL32 off) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5245 predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5246 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5247 match(AddP (DecodeN reg) off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5248 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5249 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5250 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5251 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5252 base(0xc); // R12 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5253 index($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5254 scale(0x3); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5255 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5256 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5257 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5258 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5259 // Indirect Memory Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5260 operand indirectNarrow(rRegN reg) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5261 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5262 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5263 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5264 match(DecodeN reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5265 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5266 format %{ "[$reg]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5267 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5268 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5269 index(0x4); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5270 scale(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5271 disp(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5272 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5273 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5274 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5275 // Indirect Memory Plus Short Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5276 operand indOffset8Narrow(rRegN reg, immL8 off) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5277 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5278 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5279 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5280 match(AddP (DecodeN reg) off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5281 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5282 format %{ "[$reg + $off (8-bit)]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5283 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5284 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5285 index(0x4); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5286 scale(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5287 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5288 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5289 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5290 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5291 // Indirect Memory Plus Long Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5292 operand indOffset32Narrow(rRegN reg, immL32 off) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5293 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5294 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5295 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5296 match(AddP (DecodeN reg) off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5297 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5298 format %{ "[$reg + $off (32-bit)]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5299 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5300 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5301 index(0x4); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5302 scale(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5303 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5304 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5305 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5306 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5307 // Indirect Memory Plus Index Register Plus Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5308 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5309 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5310 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5311 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5312 match(AddP (AddP (DecodeN reg) lreg) off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5313 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5314 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5315 format %{"[$reg + $off + $lreg]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5316 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5317 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5318 index($lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5319 scale(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5320 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5321 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5322 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5323 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5324 // Indirect Memory Plus Index Register Plus Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5325 operand indIndexNarrow(rRegN reg, rRegL lreg) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5326 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5327 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5328 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5329 match(AddP (DecodeN reg) lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5330 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5331 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5332 format %{"[$reg + $lreg]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5333 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5334 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5335 index($lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5336 scale(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5337 disp(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5338 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5339 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5340 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5341 // Indirect Memory Times Scale Plus Index Register |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5342 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5343 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5344 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5345 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5346 match(AddP (DecodeN reg) (LShiftL lreg scale)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5347 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5348 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5349 format %{"[$reg + $lreg << $scale]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5350 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5351 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5352 index($lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5353 scale($scale); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5354 disp(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5355 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5356 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5357 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5358 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5359 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5360 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5361 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5362 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5363 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5364 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5365 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5366 format %{"[$reg + $off + $lreg << $scale]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5367 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5368 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5369 index($lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5370 scale($scale); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5371 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5372 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5373 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5374 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5375 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5376 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5377 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5378 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5379 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5380 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5381 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5382 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5383 format %{"[$reg + $off + $idx << $scale]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5384 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5385 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5386 index($idx); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5387 scale($scale); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5388 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5389 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5390 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5391 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5392 |
| 0 | 5393 //----------Special Memory Operands-------------------------------------------- |
| 5394 // Stack Slot Operand - This operand is used for loading and storing temporary | |
| 5395 // values on the stack where a match requires a value to | |
| 5396 // flow through memory. | |
| 5397 operand stackSlotP(sRegP reg) | |
| 5398 %{ | |
| 5399 constraint(ALLOC_IN_RC(stack_slots)); | |
| 5400 // No match rule because this operand is only generated in matching | |
| 5401 | |
| 5402 format %{ "[$reg]" %} | |
| 5403 interface(MEMORY_INTER) %{ | |
| 5404 base(0x4); // RSP | |
| 5405 index(0x4); // No Index | |
| 5406 scale(0x0); // No Scale | |
| 5407 disp($reg); // Stack Offset | |
| 5408 %} | |
| 5409 %} | |
| 5410 | |
| 5411 operand stackSlotI(sRegI reg) | |
| 5412 %{ | |
| 5413 constraint(ALLOC_IN_RC(stack_slots)); | |
| 5414 // No match rule because this operand is only generated in matching | |
| 5415 | |
| 5416 format %{ "[$reg]" %} | |
| 5417 interface(MEMORY_INTER) %{ | |
| 5418 base(0x4); // RSP | |
| 5419 index(0x4); // No Index | |
| 5420 scale(0x0); // No Scale | |
| 5421 disp($reg); // Stack Offset | |
| 5422 %} | |
| 5423 %} | |
| 5424 | |
| 5425 operand stackSlotF(sRegF reg) | |
| 5426 %{ | |
| 5427 constraint(ALLOC_IN_RC(stack_slots)); | |
| 5428 // No match rule because this operand is only generated in matching | |
| 5429 | |
| 5430 format %{ "[$reg]" %} | |
| 5431 interface(MEMORY_INTER) %{ | |
| 5432 base(0x4); // RSP | |
| 5433 index(0x4); // No Index | |
| 5434 scale(0x0); // No Scale | |
| 5435 disp($reg); // Stack Offset | |
| 5436 %} | |
| 5437 %} | |
| 5438 | |
| 5439 operand stackSlotD(sRegD reg) | |
| 5440 %{ | |
| 5441 constraint(ALLOC_IN_RC(stack_slots)); | |
| 5442 // No match rule because this operand is only generated in matching | |
| 5443 | |
| 5444 format %{ "[$reg]" %} | |
| 5445 interface(MEMORY_INTER) %{ | |
| 5446 base(0x4); // RSP | |
| 5447 index(0x4); // No Index | |
| 5448 scale(0x0); // No Scale | |
| 5449 disp($reg); // Stack Offset | |
| 5450 %} | |
| 5451 %} | |
| 5452 operand stackSlotL(sRegL reg) | |
| 5453 %{ | |
| 5454 constraint(ALLOC_IN_RC(stack_slots)); | |
| 5455 // No match rule because this operand is only generated in matching | |
| 5456 | |
| 5457 format %{ "[$reg]" %} | |
| 5458 interface(MEMORY_INTER) %{ | |
| 5459 base(0x4); // RSP | |
| 5460 index(0x4); // No Index | |
| 5461 scale(0x0); // No Scale | |
| 5462 disp($reg); // Stack Offset | |
| 5463 %} | |
| 5464 %} | |
| 5465 | |
| 5466 //----------Conditional Branch Operands---------------------------------------- | |
| 5467 // Comparison Op - This is the operation of the comparison, and is limited to | |
| 5468 // the following set of codes: | |
| 5469 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) | |
| 5470 // | |
| 5471 // Other attributes of the comparison, such as unsignedness, are specified | |
| 5472 // by the comparison instruction that sets a condition code flags register. | |
| 5473 // That result is represented by a flags operand whose subtype is appropriate | |
| 5474 // to the unsignedness (etc.) of the comparison. | |
| 5475 // | |
| 5476 // Later, the instruction which matches both the Comparison Op (a Bool) and | |
| 5477 // the flags (produced by the Cmp) specifies the coding of the comparison op | |
| 5478 // by matching a specific subtype of Bool operand below, such as cmpOpU. | |
| 5479 | |
| 5480 // Comparision Code | |
| 5481 operand cmpOp() | |
| 5482 %{ | |
| 5483 match(Bool); | |
| 5484 | |
| 5485 format %{ "" %} | |
| 5486 interface(COND_INTER) %{ | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5487 equal(0x4, "e"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5488 not_equal(0x5, "ne"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5489 less(0xC, "l"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5490 greater_equal(0xD, "ge"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5491 less_equal(0xE, "le"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5492 greater(0xF, "g"); |
| 0 | 5493 %} |
| 5494 %} | |
| 5495 | |
| 5496 // Comparison Code, unsigned compare. Used by FP also, with | |
| 5497 // C2 (unordered) turned into GT or LT already. The other bits | |
| 5498 // C0 and C3 are turned into Carry & Zero flags. | |
| 5499 operand cmpOpU() | |
| 5500 %{ | |
| 5501 match(Bool); | |
| 5502 | |
| 5503 format %{ "" %} | |
| 5504 interface(COND_INTER) %{ | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5505 equal(0x4, "e"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5506 not_equal(0x5, "ne"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5507 less(0x2, "b"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5508 greater_equal(0x3, "nb"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5509 less_equal(0x6, "be"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5510 greater(0x7, "nbe"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5511 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5512 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5513 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5514 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5515 // Floating comparisons that don't require any fixup for the unordered case |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5516 operand cmpOpUCF() %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5517 match(Bool); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5518 predicate(n->as_Bool()->_test._test == BoolTest::lt || |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5519 n->as_Bool()->_test._test == BoolTest::ge || |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5520 n->as_Bool()->_test._test == BoolTest::le || |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5521 n->as_Bool()->_test._test == BoolTest::gt); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5522 format %{ "" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5523 interface(COND_INTER) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5524 equal(0x4, "e"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5525 not_equal(0x5, "ne"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5526 less(0x2, "b"); |
|
4d9884b01ba6
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changeset
|
5527 greater_equal(0x3, "nb"); |
|
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403
diff
changeset
|
5528 less_equal(0x6, "be"); |
|
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403
diff
changeset
|
5529 greater(0x7, "nbe"); |
|
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parents:
403
diff
changeset
|
5530 %} |
|
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diff
changeset
|
5531 %} |
|
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parents:
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diff
changeset
|
5532 |
|
4d9884b01ba6
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parents:
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diff
changeset
|
5533 |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
5534 // Floating comparisons that can be fixed up with extra conditional jumps |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
5535 operand cmpOpUCF2() %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
5536 match(Bool); |
|
4d9884b01ba6
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parents:
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diff
changeset
|
5537 predicate(n->as_Bool()->_test._test == BoolTest::ne || |
|
4d9884b01ba6
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parents:
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diff
changeset
|
5538 n->as_Bool()->_test._test == BoolTest::eq); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
5539 format %{ "" %} |
|
4d9884b01ba6
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diff
changeset
|
5540 interface(COND_INTER) %{ |
|
4d9884b01ba6
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parents:
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diff
changeset
|
5541 equal(0x4, "e"); |
|
4d9884b01ba6
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parents:
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diff
changeset
|
5542 not_equal(0x5, "ne"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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403
diff
changeset
|
5543 less(0x2, "b"); |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
5544 greater_equal(0x3, "nb"); |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
5545 less_equal(0x6, "be"); |
|
4d9884b01ba6
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diff
changeset
|
5546 greater(0x7, "nbe"); |
| 0 | 5547 %} |
| 5548 %} | |
| 5549 | |
| 5550 | |
| 5551 //----------OPERAND CLASSES---------------------------------------------------- | |
| 5552 // Operand Classes are groups of operands that are used as to simplify | |
| 605 | 5553 // instruction definitions by not requiring the AD writer to specify separate |
| 0 | 5554 // instructions for every form of operand when the instruction accepts |
| 5555 // multiple operand types with the same basic encoding and format. The classic | |
| 5556 // case of this is memory operands. | |
| 5557 | |
| 5558 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex, | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5559 indIndexScale, indIndexScaleOffset, indPosIndexScaleOffset, |
|
642
660978a2a31a
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kvn
parents:
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|
5560 indCompressedOopOffset, |
|
660978a2a31a
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kvn
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624
diff
changeset
|
5561 indirectNarrow, indOffset8Narrow, indOffset32Narrow, |
|
660978a2a31a
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kvn
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diff
changeset
|
5562 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow, |
|
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diff
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|
5563 indIndexScaleOffsetNarrow, indPosIndexScaleOffsetNarrow); |
| 0 | 5564 |
| 5565 //----------PIPELINE----------------------------------------------------------- | |
| 5566 // Rules which define the behavior of the target architectures pipeline. | |
| 5567 pipeline %{ | |
| 5568 | |
| 5569 //----------ATTRIBUTES--------------------------------------------------------- | |
| 5570 attributes %{ | |
| 5571 variable_size_instructions; // Fixed size instructions | |
| 5572 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle | |
| 5573 instruction_unit_size = 1; // An instruction is 1 bytes long | |
| 5574 instruction_fetch_unit_size = 16; // The processor fetches one line | |
| 5575 instruction_fetch_units = 1; // of 16 bytes | |
| 5576 | |
| 5577 // List of nop instructions | |
| 5578 nops( MachNop ); | |
| 5579 %} | |
| 5580 | |
| 5581 //----------RESOURCES---------------------------------------------------------- | |
| 5582 // Resources are the functional units available to the machine | |
| 5583 | |
| 5584 // Generic P2/P3 pipeline | |
| 5585 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of | |
| 5586 // 3 instructions decoded per cycle. | |
| 5587 // 2 load/store ops per cycle, 1 branch, 1 FPU, | |
| 5588 // 3 ALU op, only ALU0 handles mul instructions. | |
| 5589 resources( D0, D1, D2, DECODE = D0 | D1 | D2, | |
| 5590 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2, | |
| 5591 BR, FPU, | |
| 5592 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2); | |
| 5593 | |
| 5594 //----------PIPELINE DESCRIPTION----------------------------------------------- | |
| 5595 // Pipeline Description specifies the stages in the machine's pipeline | |
| 5596 | |
| 5597 // Generic P2/P3 pipeline | |
| 5598 pipe_desc(S0, S1, S2, S3, S4, S5); | |
| 5599 | |
| 5600 //----------PIPELINE CLASSES--------------------------------------------------- | |
| 5601 // Pipeline Classes describe the stages in which input and output are | |
| 5602 // referenced by the hardware pipeline. | |
| 5603 | |
| 5604 // Naming convention: ialu or fpu | |
| 5605 // Then: _reg | |
| 5606 // Then: _reg if there is a 2nd register | |
| 5607 // Then: _long if it's a pair of instructions implementing a long | |
| 5608 // Then: _fat if it requires the big decoder | |
| 5609 // Or: _mem if it requires the big decoder and a memory unit. | |
| 5610 | |
| 5611 // Integer ALU reg operation | |
| 5612 pipe_class ialu_reg(rRegI dst) | |
| 5613 %{ | |
| 5614 single_instruction; | |
| 5615 dst : S4(write); | |
| 5616 dst : S3(read); | |
| 5617 DECODE : S0; // any decoder | |
| 5618 ALU : S3; // any alu | |
| 5619 %} | |
| 5620 | |
| 5621 // Long ALU reg operation | |
| 5622 pipe_class ialu_reg_long(rRegL dst) | |
| 5623 %{ | |
| 5624 instruction_count(2); | |
| 5625 dst : S4(write); | |
| 5626 dst : S3(read); | |
| 5627 DECODE : S0(2); // any 2 decoders | |
| 5628 ALU : S3(2); // both alus | |
| 5629 %} | |
| 5630 | |
| 5631 // Integer ALU reg operation using big decoder | |
| 5632 pipe_class ialu_reg_fat(rRegI dst) | |
| 5633 %{ | |
| 5634 single_instruction; | |
| 5635 dst : S4(write); | |
| 5636 dst : S3(read); | |
| 5637 D0 : S0; // big decoder only | |
| 5638 ALU : S3; // any alu | |
| 5639 %} | |
| 5640 | |
| 5641 // Long ALU reg operation using big decoder | |
| 5642 pipe_class ialu_reg_long_fat(rRegL dst) | |
| 5643 %{ | |
| 5644 instruction_count(2); | |
| 5645 dst : S4(write); | |
| 5646 dst : S3(read); | |
| 5647 D0 : S0(2); // big decoder only; twice | |
| 5648 ALU : S3(2); // any 2 alus | |
| 5649 %} | |
| 5650 | |
| 5651 // Integer ALU reg-reg operation | |
| 5652 pipe_class ialu_reg_reg(rRegI dst, rRegI src) | |
| 5653 %{ | |
| 5654 single_instruction; | |
| 5655 dst : S4(write); | |
| 5656 src : S3(read); | |
| 5657 DECODE : S0; // any decoder | |
| 5658 ALU : S3; // any alu | |
| 5659 %} | |
| 5660 | |
| 5661 // Long ALU reg-reg operation | |
| 5662 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src) | |
| 5663 %{ | |
| 5664 instruction_count(2); | |
| 5665 dst : S4(write); | |
| 5666 src : S3(read); | |
| 5667 DECODE : S0(2); // any 2 decoders | |
| 5668 ALU : S3(2); // both alus | |
| 5669 %} | |
| 5670 | |
| 5671 // Integer ALU reg-reg operation | |
| 5672 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) | |
| 5673 %{ | |
| 5674 single_instruction; | |
| 5675 dst : S4(write); | |
| 5676 src : S3(read); | |
| 5677 D0 : S0; // big decoder only | |
| 5678 ALU : S3; // any alu | |
| 5679 %} | |
| 5680 | |
| 5681 // Long ALU reg-reg operation | |
| 5682 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src) | |
| 5683 %{ | |
| 5684 instruction_count(2); | |
| 5685 dst : S4(write); | |
| 5686 src : S3(read); | |
| 5687 D0 : S0(2); // big decoder only; twice | |
| 5688 ALU : S3(2); // both alus | |
| 5689 %} | |
| 5690 | |
| 5691 // Integer ALU reg-mem operation | |
| 5692 pipe_class ialu_reg_mem(rRegI dst, memory mem) | |
| 5693 %{ | |
| 5694 single_instruction; | |
| 5695 dst : S5(write); | |
| 5696 mem : S3(read); | |
| 5697 D0 : S0; // big decoder only | |
| 5698 ALU : S4; // any alu | |
| 5699 MEM : S3; // any mem | |
| 5700 %} | |
| 5701 | |
| 5702 // Integer mem operation (prefetch) | |
| 5703 pipe_class ialu_mem(memory mem) | |
| 5704 %{ | |
| 5705 single_instruction; | |
| 5706 mem : S3(read); | |
| 5707 D0 : S0; // big decoder only | |
| 5708 MEM : S3; // any mem | |
| 5709 %} | |
| 5710 | |
| 5711 // Integer Store to Memory | |
| 5712 pipe_class ialu_mem_reg(memory mem, rRegI src) | |
| 5713 %{ | |
| 5714 single_instruction; | |
| 5715 mem : S3(read); | |
| 5716 src : S5(read); | |
| 5717 D0 : S0; // big decoder only | |
| 5718 ALU : S4; // any alu | |
| 5719 MEM : S3; | |
| 5720 %} | |
| 5721 | |
| 5722 // // Long Store to Memory | |
| 5723 // pipe_class ialu_mem_long_reg(memory mem, rRegL src) | |
| 5724 // %{ | |
| 5725 // instruction_count(2); | |
| 5726 // mem : S3(read); | |
| 5727 // src : S5(read); | |
| 5728 // D0 : S0(2); // big decoder only; twice | |
| 5729 // ALU : S4(2); // any 2 alus | |
| 5730 // MEM : S3(2); // Both mems | |
| 5731 // %} | |
| 5732 | |
| 5733 // Integer Store to Memory | |
| 5734 pipe_class ialu_mem_imm(memory mem) | |
| 5735 %{ | |
| 5736 single_instruction; | |
| 5737 mem : S3(read); | |
| 5738 D0 : S0; // big decoder only | |
| 5739 ALU : S4; // any alu | |
| 5740 MEM : S3; | |
| 5741 %} | |
| 5742 | |
| 5743 // Integer ALU0 reg-reg operation | |
| 5744 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) | |
| 5745 %{ | |
| 5746 single_instruction; | |
| 5747 dst : S4(write); | |
| 5748 src : S3(read); | |
| 5749 D0 : S0; // Big decoder only | |
| 5750 ALU0 : S3; // only alu0 | |
| 5751 %} | |
| 5752 | |
| 5753 // Integer ALU0 reg-mem operation | |
| 5754 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) | |
| 5755 %{ | |
| 5756 single_instruction; | |
| 5757 dst : S5(write); | |
| 5758 mem : S3(read); | |
| 5759 D0 : S0; // big decoder only | |
| 5760 ALU0 : S4; // ALU0 only | |
| 5761 MEM : S3; // any mem | |
| 5762 %} | |
| 5763 | |
| 5764 // Integer ALU reg-reg operation | |
| 5765 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2) | |
| 5766 %{ | |
| 5767 single_instruction; | |
| 5768 cr : S4(write); | |
| 5769 src1 : S3(read); | |
| 5770 src2 : S3(read); | |
| 5771 DECODE : S0; // any decoder | |
| 5772 ALU : S3; // any alu | |
| 5773 %} | |
| 5774 | |
| 5775 // Integer ALU reg-imm operation | |
| 5776 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1) | |
| 5777 %{ | |
| 5778 single_instruction; | |
| 5779 cr : S4(write); | |
| 5780 src1 : S3(read); | |
| 5781 DECODE : S0; // any decoder | |
| 5782 ALU : S3; // any alu | |
| 5783 %} | |
| 5784 | |
| 5785 // Integer ALU reg-mem operation | |
| 5786 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2) | |
| 5787 %{ | |
| 5788 single_instruction; | |
| 5789 cr : S4(write); | |
| 5790 src1 : S3(read); | |
| 5791 src2 : S3(read); | |
| 5792 D0 : S0; // big decoder only | |
| 5793 ALU : S4; // any alu | |
| 5794 MEM : S3; | |
| 5795 %} | |
| 5796 | |
| 5797 // Conditional move reg-reg | |
| 5798 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y) | |
| 5799 %{ | |
| 5800 instruction_count(4); | |
| 5801 y : S4(read); | |
| 5802 q : S3(read); | |
| 5803 p : S3(read); | |
| 5804 DECODE : S0(4); // any decoder | |
| 5805 %} | |
| 5806 | |
| 5807 // Conditional move reg-reg | |
| 5808 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr) | |
| 5809 %{ | |
| 5810 single_instruction; | |
| 5811 dst : S4(write); | |
| 5812 src : S3(read); | |
| 5813 cr : S3(read); | |
| 5814 DECODE : S0; // any decoder | |
| 5815 %} | |
| 5816 | |
| 5817 // Conditional move reg-mem | |
| 5818 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src) | |
| 5819 %{ | |
| 5820 single_instruction; | |
| 5821 dst : S4(write); | |
| 5822 src : S3(read); | |
| 5823 cr : S3(read); | |
| 5824 DECODE : S0; // any decoder | |
| 5825 MEM : S3; | |
| 5826 %} | |
| 5827 | |
| 5828 // Conditional move reg-reg long | |
| 5829 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src) | |
| 5830 %{ | |
| 5831 single_instruction; | |
| 5832 dst : S4(write); | |
| 5833 src : S3(read); | |
| 5834 cr : S3(read); | |
| 5835 DECODE : S0(2); // any 2 decoders | |
| 5836 %} | |
| 5837 | |
| 5838 // XXX | |
| 5839 // // Conditional move double reg-reg | |
| 5840 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src) | |
| 5841 // %{ | |
| 5842 // single_instruction; | |
| 5843 // dst : S4(write); | |
| 5844 // src : S3(read); | |
| 5845 // cr : S3(read); | |
| 5846 // DECODE : S0; // any decoder | |
| 5847 // %} | |
| 5848 | |
| 5849 // Float reg-reg operation | |
| 5850 pipe_class fpu_reg(regD dst) | |
| 5851 %{ | |
| 5852 instruction_count(2); | |
| 5853 dst : S3(read); | |
| 5854 DECODE : S0(2); // any 2 decoders | |
| 5855 FPU : S3; | |
| 5856 %} | |
| 5857 | |
| 5858 // Float reg-reg operation | |
| 5859 pipe_class fpu_reg_reg(regD dst, regD src) | |
| 5860 %{ | |
| 5861 instruction_count(2); | |
| 5862 dst : S4(write); | |
| 5863 src : S3(read); | |
| 5864 DECODE : S0(2); // any 2 decoders | |
| 5865 FPU : S3; | |
| 5866 %} | |
| 5867 | |
| 5868 // Float reg-reg operation | |
| 5869 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2) | |
| 5870 %{ | |
| 5871 instruction_count(3); | |
| 5872 dst : S4(write); | |
| 5873 src1 : S3(read); | |
| 5874 src2 : S3(read); | |
| 5875 DECODE : S0(3); // any 3 decoders | |
| 5876 FPU : S3(2); | |
| 5877 %} | |
| 5878 | |
| 5879 // Float reg-reg operation | |
| 5880 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3) | |
| 5881 %{ | |
| 5882 instruction_count(4); | |
| 5883 dst : S4(write); | |
| 5884 src1 : S3(read); | |
| 5885 src2 : S3(read); | |
| 5886 src3 : S3(read); | |
| 5887 DECODE : S0(4); // any 3 decoders | |
| 5888 FPU : S3(2); | |
| 5889 %} | |
| 5890 | |
| 5891 // Float reg-reg operation | |
| 5892 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3) | |
| 5893 %{ | |
| 5894 instruction_count(4); | |
| 5895 dst : S4(write); | |
| 5896 src1 : S3(read); | |
| 5897 src2 : S3(read); | |
| 5898 src3 : S3(read); | |
| 5899 DECODE : S1(3); // any 3 decoders | |
| 5900 D0 : S0; // Big decoder only | |
| 5901 FPU : S3(2); | |
| 5902 MEM : S3; | |
| 5903 %} | |
| 5904 | |
| 5905 // Float reg-mem operation | |
| 5906 pipe_class fpu_reg_mem(regD dst, memory mem) | |
| 5907 %{ | |
| 5908 instruction_count(2); | |
| 5909 dst : S5(write); | |
| 5910 mem : S3(read); | |
| 5911 D0 : S0; // big decoder only | |
| 5912 DECODE : S1; // any decoder for FPU POP | |
| 5913 FPU : S4; | |
| 5914 MEM : S3; // any mem | |
| 5915 %} | |
| 5916 | |
| 5917 // Float reg-mem operation | |
| 5918 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem) | |
| 5919 %{ | |
| 5920 instruction_count(3); | |
| 5921 dst : S5(write); | |
| 5922 src1 : S3(read); | |
| 5923 mem : S3(read); | |
| 5924 D0 : S0; // big decoder only | |
| 5925 DECODE : S1(2); // any decoder for FPU POP | |
| 5926 FPU : S4; | |
| 5927 MEM : S3; // any mem | |
| 5928 %} | |
| 5929 | |
| 5930 // Float mem-reg operation | |
| 5931 pipe_class fpu_mem_reg(memory mem, regD src) | |
| 5932 %{ | |
| 5933 instruction_count(2); | |
| 5934 src : S5(read); | |
| 5935 mem : S3(read); | |
| 5936 DECODE : S0; // any decoder for FPU PUSH | |
| 5937 D0 : S1; // big decoder only | |
| 5938 FPU : S4; | |
| 5939 MEM : S3; // any mem | |
| 5940 %} | |
| 5941 | |
| 5942 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2) | |
| 5943 %{ | |
| 5944 instruction_count(3); | |
| 5945 src1 : S3(read); | |
| 5946 src2 : S3(read); | |
| 5947 mem : S3(read); | |
| 5948 DECODE : S0(2); // any decoder for FPU PUSH | |
| 5949 D0 : S1; // big decoder only | |
| 5950 FPU : S4; | |
| 5951 MEM : S3; // any mem | |
| 5952 %} | |
| 5953 | |
| 5954 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2) | |
| 5955 %{ | |
| 5956 instruction_count(3); | |
| 5957 src1 : S3(read); | |
| 5958 src2 : S3(read); | |
| 5959 mem : S4(read); | |
| 5960 DECODE : S0; // any decoder for FPU PUSH | |
| 5961 D0 : S0(2); // big decoder only | |
| 5962 FPU : S4; | |
| 5963 MEM : S3(2); // any mem | |
| 5964 %} | |
| 5965 | |
| 5966 pipe_class fpu_mem_mem(memory dst, memory src1) | |
| 5967 %{ | |
| 5968 instruction_count(2); | |
| 5969 src1 : S3(read); | |
| 5970 dst : S4(read); | |
| 5971 D0 : S0(2); // big decoder only | |
| 5972 MEM : S3(2); // any mem | |
| 5973 %} | |
| 5974 | |
| 5975 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) | |
| 5976 %{ | |
| 5977 instruction_count(3); | |
| 5978 src1 : S3(read); | |
| 5979 src2 : S3(read); | |
| 5980 dst : S4(read); | |
| 5981 D0 : S0(3); // big decoder only | |
| 5982 FPU : S4; | |
| 5983 MEM : S3(3); // any mem | |
| 5984 %} | |
| 5985 | |
| 5986 pipe_class fpu_mem_reg_con(memory mem, regD src1) | |
| 5987 %{ | |
| 5988 instruction_count(3); | |
| 5989 src1 : S4(read); | |
| 5990 mem : S4(read); | |
| 5991 DECODE : S0; // any decoder for FPU PUSH | |
| 5992 D0 : S0(2); // big decoder only | |
| 5993 FPU : S4; | |
| 5994 MEM : S3(2); // any mem | |
| 5995 %} | |
| 5996 | |
| 5997 // Float load constant | |
| 5998 pipe_class fpu_reg_con(regD dst) | |
| 5999 %{ | |
| 6000 instruction_count(2); | |
| 6001 dst : S5(write); | |
| 6002 D0 : S0; // big decoder only for the load | |
| 6003 DECODE : S1; // any decoder for FPU POP | |
| 6004 FPU : S4; | |
| 6005 MEM : S3; // any mem | |
| 6006 %} | |
| 6007 | |
| 6008 // Float load constant | |
| 6009 pipe_class fpu_reg_reg_con(regD dst, regD src) | |
| 6010 %{ | |
| 6011 instruction_count(3); | |
| 6012 dst : S5(write); | |
| 6013 src : S3(read); | |
| 6014 D0 : S0; // big decoder only for the load | |
| 6015 DECODE : S1(2); // any decoder for FPU POP | |
| 6016 FPU : S4; | |
| 6017 MEM : S3; // any mem | |
| 6018 %} | |
| 6019 | |
| 6020 // UnConditional branch | |
| 6021 pipe_class pipe_jmp(label labl) | |
| 6022 %{ | |
| 6023 single_instruction; | |
| 6024 BR : S3; | |
| 6025 %} | |
| 6026 | |
| 6027 // Conditional branch | |
| 6028 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl) | |
| 6029 %{ | |
| 6030 single_instruction; | |
| 6031 cr : S1(read); | |
| 6032 BR : S3; | |
| 6033 %} | |
| 6034 | |
| 6035 // Allocation idiom | |
| 6036 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr) | |
| 6037 %{ | |
| 6038 instruction_count(1); force_serialization; | |
| 6039 fixed_latency(6); | |
| 6040 heap_ptr : S3(read); | |
| 6041 DECODE : S0(3); | |
| 6042 D0 : S2; | |
| 6043 MEM : S3; | |
| 6044 ALU : S3(2); | |
| 6045 dst : S5(write); | |
| 6046 BR : S5; | |
| 6047 %} | |
| 6048 | |
| 6049 // Generic big/slow expanded idiom | |
| 6050 pipe_class pipe_slow() | |
| 6051 %{ | |
| 6052 instruction_count(10); multiple_bundles; force_serialization; | |
| 6053 fixed_latency(100); | |
| 6054 D0 : S0(2); | |
| 6055 MEM : S3(2); | |
| 6056 %} | |
| 6057 | |
| 6058 // The real do-nothing guy | |
| 6059 pipe_class empty() | |
| 6060 %{ | |
| 6061 instruction_count(0); | |
| 6062 %} | |
| 6063 | |
| 6064 // Define the class for the Nop node | |
| 6065 define | |
| 6066 %{ | |
| 6067 MachNop = empty; | |
| 6068 %} | |
| 6069 | |
| 6070 %} | |
| 6071 | |
| 6072 //----------INSTRUCTIONS------------------------------------------------------- | |
| 6073 // | |
| 6074 // match -- States which machine-independent subtree may be replaced | |
| 6075 // by this instruction. | |
| 6076 // ins_cost -- The estimated cost of this instruction is used by instruction | |
| 6077 // selection to identify a minimum cost tree of machine | |
| 6078 // instructions that matches a tree of machine-independent | |
| 6079 // instructions. | |
| 6080 // format -- A string providing the disassembly for this instruction. | |
| 6081 // The value of an instruction's operand may be inserted | |
| 6082 // by referring to it with a '$' prefix. | |
| 6083 // opcode -- Three instruction opcodes may be provided. These are referred | |
| 6084 // to within an encode class as $primary, $secondary, and $tertiary | |
| 6085 // rrspectively. The primary opcode is commonly used to | |
| 6086 // indicate the type of machine instruction, while secondary | |
| 6087 // and tertiary are often used for prefix options or addressing | |
| 6088 // modes. | |
| 6089 // ins_encode -- A list of encode classes with parameters. The encode class | |
| 6090 // name must have been defined in an 'enc_class' specification | |
| 6091 // in the encode section of the architecture description. | |
| 6092 | |
| 6093 | |
| 6094 //----------Load/Store/Move Instructions--------------------------------------- | |
| 6095 //----------Load Instructions-------------------------------------------------- | |
| 6096 | |
| 6097 // Load Byte (8 bit signed) | |
| 6098 instruct loadB(rRegI dst, memory mem) | |
| 6099 %{ | |
| 6100 match(Set dst (LoadB mem)); | |
| 6101 | |
| 6102 ins_cost(125); | |
| 6103 format %{ "movsbl $dst, $mem\t# byte" %} | |
| 624 | 6104 |
| 6105 ins_encode %{ | |
| 6106 __ movsbl($dst$$Register, $mem$$Address); | |
| 6107 %} | |
| 6108 | |
| 0 | 6109 ins_pipe(ialu_reg_mem); |
| 6110 %} | |
| 6111 | |
| 624 | 6112 // Load Byte (8 bit signed) into Long Register |
| 6113 instruct loadB2L(rRegL dst, memory mem) | |
| 6114 %{ | |
| 6115 match(Set dst (ConvI2L (LoadB mem))); | |
| 6116 | |
| 6117 ins_cost(125); | |
| 6118 format %{ "movsbq $dst, $mem\t# byte -> long" %} | |
| 6119 | |
| 6120 ins_encode %{ | |
| 6121 __ movsbq($dst$$Register, $mem$$Address); | |
| 6122 %} | |
| 6123 | |
| 6124 ins_pipe(ialu_reg_mem); | |
| 6125 %} | |
| 6126 | |
| 6127 // Load Unsigned Byte (8 bit UNsigned) | |
| 6128 instruct loadUB(rRegI dst, memory mem) | |
| 6129 %{ | |
| 6130 match(Set dst (LoadUB mem)); | |
| 0 | 6131 |
| 6132 ins_cost(125); | |
| 6133 format %{ "movzbl $dst, $mem\t# ubyte" %} | |
| 624 | 6134 |
| 6135 ins_encode %{ | |
| 6136 __ movzbl($dst$$Register, $mem$$Address); | |
| 6137 %} | |
| 6138 | |
| 0 | 6139 ins_pipe(ialu_reg_mem); |
| 6140 %} | |
| 6141 | |
| 624 | 6142 // Load Unsigned Byte (8 bit UNsigned) into Long Register |
| 6143 instruct loadUB2L(rRegL dst, memory mem) | |
| 6144 %{ | |
| 6145 match(Set dst (ConvI2L (LoadUB mem))); | |
| 6146 | |
| 6147 ins_cost(125); | |
| 6148 format %{ "movzbq $dst, $mem\t# ubyte -> long" %} | |
| 6149 | |
| 6150 ins_encode %{ | |
| 6151 __ movzbq($dst$$Register, $mem$$Address); | |
| 6152 %} | |
| 6153 | |
| 6154 ins_pipe(ialu_reg_mem); | |
| 6155 %} | |
| 0 | 6156 |
| 6157 // Load Short (16 bit signed) | |
| 6158 instruct loadS(rRegI dst, memory mem) | |
| 6159 %{ | |
| 6160 match(Set dst (LoadS mem)); | |
| 6161 | |
| 624 | 6162 ins_cost(125); |
| 0 | 6163 format %{ "movswl $dst, $mem\t# short" %} |
| 624 | 6164 |
| 6165 ins_encode %{ | |
| 6166 __ movswl($dst$$Register, $mem$$Address); | |
| 6167 %} | |
| 6168 | |
| 0 | 6169 ins_pipe(ialu_reg_mem); |
| 6170 %} | |
| 6171 | |
| 624 | 6172 // Load Short (16 bit signed) into Long Register |
| 6173 instruct loadS2L(rRegL dst, memory mem) | |
| 6174 %{ | |
| 6175 match(Set dst (ConvI2L (LoadS mem))); | |
| 6176 | |
| 6177 ins_cost(125); | |
| 6178 format %{ "movswq $dst, $mem\t# short -> long" %} | |
| 6179 | |
| 6180 ins_encode %{ | |
| 6181 __ movswq($dst$$Register, $mem$$Address); | |
| 6182 %} | |
| 6183 | |
| 6184 ins_pipe(ialu_reg_mem); | |
| 6185 %} | |
| 0 | 6186 |
|
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6187 // Load Unsigned Short/Char (16 bit UNsigned) |
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6188 instruct loadUS(rRegI dst, memory mem) |
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6189 %{ |
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6190 match(Set dst (LoadUS mem)); |
| 0 | 6191 |
| 6192 ins_cost(125); | |
|
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6193 format %{ "movzwl $dst, $mem\t# ushort/char" %} |
| 624 | 6194 |
| 6195 ins_encode %{ | |
| 6196 __ movzwl($dst$$Register, $mem$$Address); | |
| 6197 %} | |
| 6198 | |
| 0 | 6199 ins_pipe(ialu_reg_mem); |
| 6200 %} | |
| 6201 | |
| 624 | 6202 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register |
| 6203 instruct loadUS2L(rRegL dst, memory mem) | |
| 6204 %{ | |
| 6205 match(Set dst (ConvI2L (LoadUS mem))); | |
| 6206 | |
| 6207 ins_cost(125); | |
| 6208 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %} | |
| 6209 | |
| 6210 ins_encode %{ | |
| 6211 __ movzwq($dst$$Register, $mem$$Address); | |
| 6212 %} | |
| 6213 | |
| 6214 ins_pipe(ialu_reg_mem); | |
| 6215 %} | |
| 0 | 6216 |
| 6217 // Load Integer | |
| 6218 instruct loadI(rRegI dst, memory mem) | |
| 6219 %{ | |
| 6220 match(Set dst (LoadI mem)); | |
| 6221 | |
| 624 | 6222 ins_cost(125); |
| 0 | 6223 format %{ "movl $dst, $mem\t# int" %} |
| 624 | 6224 |
| 6225 ins_encode %{ | |
| 6226 __ movl($dst$$Register, $mem$$Address); | |
| 6227 %} | |
| 6228 | |
| 6229 ins_pipe(ialu_reg_mem); | |
| 6230 %} | |
| 6231 | |
| 6232 // Load Integer into Long Register | |
| 6233 instruct loadI2L(rRegL dst, memory mem) | |
| 6234 %{ | |
| 6235 match(Set dst (ConvI2L (LoadI mem))); | |
| 6236 | |
| 6237 ins_cost(125); | |
| 6238 format %{ "movslq $dst, $mem\t# int -> long" %} | |
| 6239 | |
| 6240 ins_encode %{ | |
| 6241 __ movslq($dst$$Register, $mem$$Address); | |
| 6242 %} | |
| 6243 | |
| 6244 ins_pipe(ialu_reg_mem); | |
| 6245 %} | |
| 6246 | |
| 6247 // Load Unsigned Integer into Long Register | |
| 6248 instruct loadUI2L(rRegL dst, memory mem) | |
| 6249 %{ | |
| 6250 match(Set dst (LoadUI2L mem)); | |
| 6251 | |
| 6252 ins_cost(125); | |
| 6253 format %{ "movl $dst, $mem\t# uint -> long" %} | |
| 6254 | |
| 6255 ins_encode %{ | |
| 6256 __ movl($dst$$Register, $mem$$Address); | |
| 6257 %} | |
| 6258 | |
| 0 | 6259 ins_pipe(ialu_reg_mem); |
| 6260 %} | |
| 6261 | |
| 6262 // Load Long | |
| 6263 instruct loadL(rRegL dst, memory mem) | |
| 6264 %{ | |
| 6265 match(Set dst (LoadL mem)); | |
| 6266 | |
| 624 | 6267 ins_cost(125); |
| 0 | 6268 format %{ "movq $dst, $mem\t# long" %} |
| 624 | 6269 |
| 6270 ins_encode %{ | |
| 6271 __ movq($dst$$Register, $mem$$Address); | |
| 6272 %} | |
| 6273 | |
| 0 | 6274 ins_pipe(ialu_reg_mem); // XXX |
| 6275 %} | |
| 6276 | |
| 6277 // Load Range | |
| 6278 instruct loadRange(rRegI dst, memory mem) | |
| 6279 %{ | |
| 6280 match(Set dst (LoadRange mem)); | |
| 6281 | |
| 6282 ins_cost(125); // XXX | |
| 6283 format %{ "movl $dst, $mem\t# range" %} | |
| 6284 opcode(0x8B); | |
| 6285 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 6286 ins_pipe(ialu_reg_mem); | |
| 6287 %} | |
| 6288 | |
| 6289 // Load Pointer | |
| 6290 instruct loadP(rRegP dst, memory mem) | |
| 6291 %{ | |
| 6292 match(Set dst (LoadP mem)); | |
| 6293 | |
| 6294 ins_cost(125); // XXX | |
| 6295 format %{ "movq $dst, $mem\t# ptr" %} | |
| 6296 opcode(0x8B); | |
| 6297 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 6298 ins_pipe(ialu_reg_mem); // XXX | |
| 6299 %} | |
| 6300 | |
|
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6301 // Load Compressed Pointer |
| 163 | 6302 instruct loadN(rRegN dst, memory mem) |
|
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6303 %{ |
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6304 match(Set dst (LoadN mem)); |
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6305 |
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6306 ins_cost(125); // XXX |
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6307 format %{ "movl $dst, $mem\t# compressed ptr" %} |
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6308 ins_encode %{ |
|
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6309 __ movl($dst$$Register, $mem$$Address); |
|
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6310 %} |
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6311 ins_pipe(ialu_reg_mem); // XXX |
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6312 %} |
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6313 |
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6314 |
| 0 | 6315 // Load Klass Pointer |
| 6316 instruct loadKlass(rRegP dst, memory mem) | |
| 6317 %{ | |
| 6318 match(Set dst (LoadKlass mem)); | |
| 6319 | |
| 6320 ins_cost(125); // XXX | |
| 6321 format %{ "movq $dst, $mem\t# class" %} | |
| 6322 opcode(0x8B); | |
| 6323 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 6324 ins_pipe(ialu_reg_mem); // XXX | |
| 6325 %} | |
| 6326 | |
|
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6327 // Load narrow Klass Pointer |
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|
6328 instruct loadNKlass(rRegN dst, memory mem) |
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6329 %{ |
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|
6330 match(Set dst (LoadNKlass mem)); |
|
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6331 |
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6332 ins_cost(125); // XXX |
|
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6333 format %{ "movl $dst, $mem\t# compressed klass ptr" %} |
|
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6334 ins_encode %{ |
|
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6335 __ movl($dst$$Register, $mem$$Address); |
|
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6336 %} |
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6337 ins_pipe(ialu_reg_mem); // XXX |
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6338 %} |
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6339 |
| 0 | 6340 // Load Float |
| 6341 instruct loadF(regF dst, memory mem) | |
| 6342 %{ | |
| 6343 match(Set dst (LoadF mem)); | |
| 6344 | |
| 6345 ins_cost(145); // XXX | |
| 6346 format %{ "movss $dst, $mem\t# float" %} | |
| 6347 opcode(0xF3, 0x0F, 0x10); | |
| 6348 ins_encode(OpcP, REX_reg_mem(dst, mem), OpcS, OpcT, reg_mem(dst, mem)); | |
| 6349 ins_pipe(pipe_slow); // XXX | |
| 6350 %} | |
| 6351 | |
| 6352 // Load Double | |
| 6353 instruct loadD_partial(regD dst, memory mem) | |
| 6354 %{ | |
| 6355 predicate(!UseXmmLoadAndClearUpper); | |
| 6356 match(Set dst (LoadD mem)); | |
| 6357 | |
| 6358 ins_cost(145); // XXX | |
| 6359 format %{ "movlpd $dst, $mem\t# double" %} | |
| 6360 opcode(0x66, 0x0F, 0x12); | |
| 6361 ins_encode(OpcP, REX_reg_mem(dst, mem), OpcS, OpcT, reg_mem(dst, mem)); | |
| 6362 ins_pipe(pipe_slow); // XXX | |
| 6363 %} | |
| 6364 | |
| 6365 instruct loadD(regD dst, memory mem) | |
| 6366 %{ | |
| 6367 predicate(UseXmmLoadAndClearUpper); | |
| 6368 match(Set dst (LoadD mem)); | |
| 6369 | |
| 6370 ins_cost(145); // XXX | |
| 6371 format %{ "movsd $dst, $mem\t# double" %} | |
| 6372 opcode(0xF2, 0x0F, 0x10); | |
| 6373 ins_encode(OpcP, REX_reg_mem(dst, mem), OpcS, OpcT, reg_mem(dst, mem)); | |
| 6374 ins_pipe(pipe_slow); // XXX | |
| 6375 %} | |
| 6376 | |
| 6377 // Load Aligned Packed Byte to XMM register | |
| 6378 instruct loadA8B(regD dst, memory mem) %{ | |
| 6379 match(Set dst (Load8B mem)); | |
| 6380 ins_cost(125); | |
| 6381 format %{ "MOVQ $dst,$mem\t! packed8B" %} | |
| 6382 ins_encode( movq_ld(dst, mem)); | |
| 6383 ins_pipe( pipe_slow ); | |
| 6384 %} | |
| 6385 | |
| 6386 // Load Aligned Packed Short to XMM register | |
| 6387 instruct loadA4S(regD dst, memory mem) %{ | |
| 6388 match(Set dst (Load4S mem)); | |
| 6389 ins_cost(125); | |
| 6390 format %{ "MOVQ $dst,$mem\t! packed4S" %} | |
| 6391 ins_encode( movq_ld(dst, mem)); | |
| 6392 ins_pipe( pipe_slow ); | |
| 6393 %} | |
| 6394 | |
| 6395 // Load Aligned Packed Char to XMM register | |
| 6396 instruct loadA4C(regD dst, memory mem) %{ | |
| 6397 match(Set dst (Load4C mem)); | |
| 6398 ins_cost(125); | |
| 6399 format %{ "MOVQ $dst,$mem\t! packed4C" %} | |
| 6400 ins_encode( movq_ld(dst, mem)); | |
| 6401 ins_pipe( pipe_slow ); | |
| 6402 %} | |
| 6403 | |
| 6404 // Load Aligned Packed Integer to XMM register | |
| 6405 instruct load2IU(regD dst, memory mem) %{ | |
| 6406 match(Set dst (Load2I mem)); | |
| 6407 ins_cost(125); | |
| 6408 format %{ "MOVQ $dst,$mem\t! packed2I" %} | |
| 6409 ins_encode( movq_ld(dst, mem)); | |
| 6410 ins_pipe( pipe_slow ); | |
| 6411 %} | |
| 6412 | |
| 6413 // Load Aligned Packed Single to XMM | |
| 6414 instruct loadA2F(regD dst, memory mem) %{ | |
| 6415 match(Set dst (Load2F mem)); | |
| 6416 ins_cost(145); | |
| 6417 format %{ "MOVQ $dst,$mem\t! packed2F" %} | |
| 6418 ins_encode( movq_ld(dst, mem)); | |
| 6419 ins_pipe( pipe_slow ); | |
| 6420 %} | |
| 6421 | |
| 6422 // Load Effective Address | |
| 6423 instruct leaP8(rRegP dst, indOffset8 mem) | |
| 6424 %{ | |
| 6425 match(Set dst mem); | |
| 6426 | |
| 6427 ins_cost(110); // XXX | |
| 6428 format %{ "leaq $dst, $mem\t# ptr 8" %} | |
| 6429 opcode(0x8D); | |
| 6430 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 6431 ins_pipe(ialu_reg_reg_fat); | |
| 6432 %} | |
| 6433 | |
| 6434 instruct leaP32(rRegP dst, indOffset32 mem) | |
| 6435 %{ | |
| 6436 match(Set dst mem); | |
| 6437 | |
| 6438 ins_cost(110); | |
| 6439 format %{ "leaq $dst, $mem\t# ptr 32" %} | |
| 6440 opcode(0x8D); | |
| 6441 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 6442 ins_pipe(ialu_reg_reg_fat); | |
| 6443 %} | |
| 6444 | |
| 6445 // instruct leaPIdx(rRegP dst, indIndex mem) | |
| 6446 // %{ | |
| 6447 // match(Set dst mem); | |
| 6448 | |
| 6449 // ins_cost(110); | |
| 6450 // format %{ "leaq $dst, $mem\t# ptr idx" %} | |
| 6451 // opcode(0x8D); | |
| 6452 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 6453 // ins_pipe(ialu_reg_reg_fat); | |
| 6454 // %} | |
| 6455 | |
| 6456 instruct leaPIdxOff(rRegP dst, indIndexOffset mem) | |
| 6457 %{ | |
| 6458 match(Set dst mem); | |
| 6459 | |
| 6460 ins_cost(110); | |
| 6461 format %{ "leaq $dst, $mem\t# ptr idxoff" %} | |
| 6462 opcode(0x8D); | |
| 6463 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 6464 ins_pipe(ialu_reg_reg_fat); | |
| 6465 %} | |
| 6466 | |
| 6467 instruct leaPIdxScale(rRegP dst, indIndexScale mem) | |
| 6468 %{ | |
| 6469 match(Set dst mem); | |
| 6470 | |
| 6471 ins_cost(110); | |
| 6472 format %{ "leaq $dst, $mem\t# ptr idxscale" %} | |
| 6473 opcode(0x8D); | |
| 6474 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 6475 ins_pipe(ialu_reg_reg_fat); | |
| 6476 %} | |
| 6477 | |
| 6478 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem) | |
| 6479 %{ | |
| 6480 match(Set dst mem); | |
| 6481 | |
| 6482 ins_cost(110); | |
| 6483 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %} | |
| 6484 opcode(0x8D); | |
| 6485 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 6486 ins_pipe(ialu_reg_reg_fat); | |
| 6487 %} | |
| 6488 | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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parents:
624
diff
changeset
|
6489 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6490 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6491 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6492 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6493 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6494 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6495 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6496 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6497 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6498 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6499 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6500 // Load Effective Address which uses Narrow (32-bits) oop |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6501 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6502 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6503 predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6504 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6505 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6506 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6507 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6508 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6509 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6510 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6511 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6512 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6513 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6514 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6515 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6516 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6517 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6518 ins_cost(110); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6519 format %{ "leaq $dst, $mem\t# ptr off8narrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6520 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6521 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6522 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6523 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6524 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6525 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6526 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6527 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6528 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6529 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6530 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6531 format %{ "leaq $dst, $mem\t# ptr off32narrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6532 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6533 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6534 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6535 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6536 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6537 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6538 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6539 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6540 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6541 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6542 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6543 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6544 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6545 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6546 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6547 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6548 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6549 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6550 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6551 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6552 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6553 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6554 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6555 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6556 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6557 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6558 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6559 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6560 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6561 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6562 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6563 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6564 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6565 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6566 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6567 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6568 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6569 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6570 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6571 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6572 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6573 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6574 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6575 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6576 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6577 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6578 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6579 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6580 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6581 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6582 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6583 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6584 |
| 0 | 6585 instruct loadConI(rRegI dst, immI src) |
| 6586 %{ | |
| 6587 match(Set dst src); | |
| 6588 | |
| 6589 format %{ "movl $dst, $src\t# int" %} | |
| 6590 ins_encode(load_immI(dst, src)); | |
| 6591 ins_pipe(ialu_reg_fat); // XXX | |
| 6592 %} | |
| 6593 | |
| 6594 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr) | |
| 6595 %{ | |
| 6596 match(Set dst src); | |
| 6597 effect(KILL cr); | |
| 6598 | |
| 6599 ins_cost(50); | |
| 6600 format %{ "xorl $dst, $dst\t# int" %} | |
| 6601 opcode(0x33); /* + rd */ | |
| 6602 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst)); | |
| 6603 ins_pipe(ialu_reg); | |
| 6604 %} | |
| 6605 | |
| 6606 instruct loadConL(rRegL dst, immL src) | |
| 6607 %{ | |
| 6608 match(Set dst src); | |
| 6609 | |
| 6610 ins_cost(150); | |
| 6611 format %{ "movq $dst, $src\t# long" %} | |
| 6612 ins_encode(load_immL(dst, src)); | |
| 6613 ins_pipe(ialu_reg); | |
| 6614 %} | |
| 6615 | |
| 6616 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr) | |
| 6617 %{ | |
| 6618 match(Set dst src); | |
| 6619 effect(KILL cr); | |
| 6620 | |
| 6621 ins_cost(50); | |
| 6622 format %{ "xorl $dst, $dst\t# long" %} | |
| 6623 opcode(0x33); /* + rd */ | |
| 6624 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst)); | |
| 6625 ins_pipe(ialu_reg); // XXX | |
| 6626 %} | |
| 6627 | |
| 6628 instruct loadConUL32(rRegL dst, immUL32 src) | |
| 6629 %{ | |
| 6630 match(Set dst src); | |
| 6631 | |
| 6632 ins_cost(60); | |
| 6633 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %} | |
| 6634 ins_encode(load_immUL32(dst, src)); | |
| 6635 ins_pipe(ialu_reg); | |
| 6636 %} | |
| 6637 | |
| 6638 instruct loadConL32(rRegL dst, immL32 src) | |
| 6639 %{ | |
| 6640 match(Set dst src); | |
| 6641 | |
| 6642 ins_cost(70); | |
| 6643 format %{ "movq $dst, $src\t# long (32-bit)" %} | |
| 6644 ins_encode(load_immL32(dst, src)); | |
| 6645 ins_pipe(ialu_reg); | |
| 6646 %} | |
| 6647 | |
| 6648 instruct loadConP(rRegP dst, immP src) | |
| 6649 %{ | |
| 6650 match(Set dst src); | |
| 6651 | |
| 6652 format %{ "movq $dst, $src\t# ptr" %} | |
| 6653 ins_encode(load_immP(dst, src)); | |
| 6654 ins_pipe(ialu_reg_fat); // XXX | |
| 6655 %} | |
| 6656 | |
| 6657 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr) | |
| 6658 %{ | |
| 6659 match(Set dst src); | |
| 6660 effect(KILL cr); | |
| 6661 | |
| 6662 ins_cost(50); | |
| 6663 format %{ "xorl $dst, $dst\t# ptr" %} | |
| 6664 opcode(0x33); /* + rd */ | |
| 6665 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst)); | |
| 6666 ins_pipe(ialu_reg); | |
| 6667 %} | |
| 6668 | |
| 6669 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr) | |
| 6670 %{ | |
| 6671 match(Set dst src); | |
| 6672 effect(KILL cr); | |
| 6673 | |
| 6674 ins_cost(60); | |
| 6675 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %} | |
| 6676 ins_encode(load_immP31(dst, src)); | |
| 6677 ins_pipe(ialu_reg); | |
| 6678 %} | |
| 6679 | |
| 6680 instruct loadConF(regF dst, immF src) | |
| 6681 %{ | |
| 6682 match(Set dst src); | |
| 6683 ins_cost(125); | |
| 6684 | |
| 6685 format %{ "movss $dst, [$src]" %} | |
| 6686 ins_encode(load_conF(dst, src)); | |
| 6687 ins_pipe(pipe_slow); | |
| 6688 %} | |
| 6689 | |
|
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6690 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{ |
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6691 match(Set dst src); |
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6692 effect(KILL cr); |
|
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6693 format %{ "xorq $dst, $src\t# compressed NULL ptr" %} |
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6694 ins_encode %{ |
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6695 __ xorq($dst$$Register, $dst$$Register); |
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6696 %} |
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6697 ins_pipe(ialu_reg); |
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6698 %} |
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6699 |
|
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6700 instruct loadConN(rRegN dst, immN src) %{ |
|
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6701 match(Set dst src); |
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6702 |
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6703 ins_cost(125); |
|
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6704 format %{ "movl $dst, $src\t# compressed ptr" %} |
|
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6705 ins_encode %{ |
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6706 address con = (address)$src$$constant; |
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6707 if (con == NULL) { |
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6708 ShouldNotReachHere(); |
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6709 } else { |
|
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6710 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant); |
|
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6711 } |
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6712 %} |
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6713 ins_pipe(ialu_reg_fat); // XXX |
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6714 %} |
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6715 |
| 0 | 6716 instruct loadConF0(regF dst, immF0 src) |
| 6717 %{ | |
| 6718 match(Set dst src); | |
| 6719 ins_cost(100); | |
| 6720 | |
| 6721 format %{ "xorps $dst, $dst\t# float 0.0" %} | |
| 6722 opcode(0x0F, 0x57); | |
| 6723 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 6724 ins_pipe(pipe_slow); | |
| 6725 %} | |
| 6726 | |
| 6727 // Use the same format since predicate() can not be used here. | |
| 6728 instruct loadConD(regD dst, immD src) | |
| 6729 %{ | |
| 6730 match(Set dst src); | |
| 6731 ins_cost(125); | |
| 6732 | |
| 6733 format %{ "movsd $dst, [$src]" %} | |
| 6734 ins_encode(load_conD(dst, src)); | |
| 6735 ins_pipe(pipe_slow); | |
| 6736 %} | |
| 6737 | |
| 6738 instruct loadConD0(regD dst, immD0 src) | |
| 6739 %{ | |
| 6740 match(Set dst src); | |
| 6741 ins_cost(100); | |
| 6742 | |
| 6743 format %{ "xorpd $dst, $dst\t# double 0.0" %} | |
| 6744 opcode(0x66, 0x0F, 0x57); | |
| 6745 ins_encode(OpcP, REX_reg_reg(dst, dst), OpcS, OpcT, reg_reg(dst, dst)); | |
| 6746 ins_pipe(pipe_slow); | |
| 6747 %} | |
| 6748 | |
| 6749 instruct loadSSI(rRegI dst, stackSlotI src) | |
| 6750 %{ | |
| 6751 match(Set dst src); | |
| 6752 | |
| 6753 ins_cost(125); | |
| 6754 format %{ "movl $dst, $src\t# int stk" %} | |
| 6755 opcode(0x8B); | |
| 6756 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 6757 ins_pipe(ialu_reg_mem); | |
| 6758 %} | |
| 6759 | |
| 6760 instruct loadSSL(rRegL dst, stackSlotL src) | |
| 6761 %{ | |
| 6762 match(Set dst src); | |
| 6763 | |
| 6764 ins_cost(125); | |
| 6765 format %{ "movq $dst, $src\t# long stk" %} | |
| 6766 opcode(0x8B); | |
| 6767 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 6768 ins_pipe(ialu_reg_mem); | |
| 6769 %} | |
| 6770 | |
| 6771 instruct loadSSP(rRegP dst, stackSlotP src) | |
| 6772 %{ | |
| 6773 match(Set dst src); | |
| 6774 | |
| 6775 ins_cost(125); | |
| 6776 format %{ "movq $dst, $src\t# ptr stk" %} | |
| 6777 opcode(0x8B); | |
| 6778 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 6779 ins_pipe(ialu_reg_mem); | |
| 6780 %} | |
| 6781 | |
| 6782 instruct loadSSF(regF dst, stackSlotF src) | |
| 6783 %{ | |
| 6784 match(Set dst src); | |
| 6785 | |
| 6786 ins_cost(125); | |
| 6787 format %{ "movss $dst, $src\t# float stk" %} | |
| 6788 opcode(0xF3, 0x0F, 0x10); | |
| 6789 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 6790 ins_pipe(pipe_slow); // XXX | |
| 6791 %} | |
| 6792 | |
| 6793 // Use the same format since predicate() can not be used here. | |
| 6794 instruct loadSSD(regD dst, stackSlotD src) | |
| 6795 %{ | |
| 6796 match(Set dst src); | |
| 6797 | |
| 6798 ins_cost(125); | |
| 6799 format %{ "movsd $dst, $src\t# double stk" %} | |
| 6800 ins_encode %{ | |
| 6801 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 6802 %} | |
| 6803 ins_pipe(pipe_slow); // XXX | |
| 6804 %} | |
| 6805 | |
| 6806 // Prefetch instructions. | |
| 6807 // Must be safe to execute with invalid address (cannot fault). | |
| 6808 | |
| 6809 instruct prefetchr( memory mem ) %{ | |
| 6810 predicate(ReadPrefetchInstr==3); | |
| 6811 match(PrefetchRead mem); | |
| 6812 ins_cost(125); | |
| 6813 | |
| 6814 format %{ "PREFETCHR $mem\t# Prefetch into level 1 cache" %} | |
| 6815 opcode(0x0F, 0x0D); /* Opcode 0F 0D /0 */ | |
| 6816 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x00, mem)); | |
| 6817 ins_pipe(ialu_mem); | |
| 6818 %} | |
| 6819 | |
| 6820 instruct prefetchrNTA( memory mem ) %{ | |
| 6821 predicate(ReadPrefetchInstr==0); | |
| 6822 match(PrefetchRead mem); | |
| 6823 ins_cost(125); | |
| 6824 | |
| 6825 format %{ "PREFETCHNTA $mem\t# Prefetch into non-temporal cache for read" %} | |
| 6826 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */ | |
| 6827 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x00, mem)); | |
| 6828 ins_pipe(ialu_mem); | |
| 6829 %} | |
| 6830 | |
| 6831 instruct prefetchrT0( memory mem ) %{ | |
| 6832 predicate(ReadPrefetchInstr==1); | |
| 6833 match(PrefetchRead mem); | |
| 6834 ins_cost(125); | |
| 6835 | |
| 6836 format %{ "PREFETCHT0 $mem\t# prefetch into L1 and L2 caches for read" %} | |
| 6837 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */ | |
| 6838 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x01, mem)); | |
| 6839 ins_pipe(ialu_mem); | |
| 6840 %} | |
| 6841 | |
| 6842 instruct prefetchrT2( memory mem ) %{ | |
| 6843 predicate(ReadPrefetchInstr==2); | |
| 6844 match(PrefetchRead mem); | |
| 6845 ins_cost(125); | |
| 6846 | |
| 6847 format %{ "PREFETCHT2 $mem\t# prefetch into L2 caches for read" %} | |
| 6848 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */ | |
| 6849 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x03, mem)); | |
| 6850 ins_pipe(ialu_mem); | |
| 6851 %} | |
| 6852 | |
| 6853 instruct prefetchw( memory mem ) %{ | |
| 6854 predicate(AllocatePrefetchInstr==3); | |
| 6855 match(PrefetchWrite mem); | |
| 6856 ins_cost(125); | |
| 6857 | |
| 6858 format %{ "PREFETCHW $mem\t# Prefetch into level 1 cache and mark modified" %} | |
| 6859 opcode(0x0F, 0x0D); /* Opcode 0F 0D /1 */ | |
| 6860 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x01, mem)); | |
| 6861 ins_pipe(ialu_mem); | |
| 6862 %} | |
| 6863 | |
| 6864 instruct prefetchwNTA( memory mem ) %{ | |
| 6865 predicate(AllocatePrefetchInstr==0); | |
| 6866 match(PrefetchWrite mem); | |
| 6867 ins_cost(125); | |
| 6868 | |
| 6869 format %{ "PREFETCHNTA $mem\t# Prefetch to non-temporal cache for write" %} | |
| 6870 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */ | |
| 6871 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x00, mem)); | |
| 6872 ins_pipe(ialu_mem); | |
| 6873 %} | |
| 6874 | |
| 6875 instruct prefetchwT0( memory mem ) %{ | |
| 6876 predicate(AllocatePrefetchInstr==1); | |
| 6877 match(PrefetchWrite mem); | |
| 6878 ins_cost(125); | |
| 6879 | |
| 6880 format %{ "PREFETCHT0 $mem\t# Prefetch to level 1 and 2 caches for write" %} | |
| 6881 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */ | |
| 6882 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x01, mem)); | |
| 6883 ins_pipe(ialu_mem); | |
| 6884 %} | |
| 6885 | |
| 6886 instruct prefetchwT2( memory mem ) %{ | |
| 6887 predicate(AllocatePrefetchInstr==2); | |
| 6888 match(PrefetchWrite mem); | |
| 6889 ins_cost(125); | |
| 6890 | |
| 6891 format %{ "PREFETCHT2 $mem\t# Prefetch to level 2 cache for write" %} | |
| 6892 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */ | |
| 6893 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x03, mem)); | |
| 6894 ins_pipe(ialu_mem); | |
| 6895 %} | |
| 6896 | |
| 6897 //----------Store Instructions------------------------------------------------- | |
| 6898 | |
| 6899 // Store Byte | |
| 6900 instruct storeB(memory mem, rRegI src) | |
| 6901 %{ | |
| 6902 match(Set mem (StoreB mem src)); | |
| 6903 | |
| 6904 ins_cost(125); // XXX | |
| 6905 format %{ "movb $mem, $src\t# byte" %} | |
| 6906 opcode(0x88); | |
| 6907 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
| 6908 ins_pipe(ialu_mem_reg); | |
| 6909 %} | |
| 6910 | |
| 6911 // Store Char/Short | |
| 6912 instruct storeC(memory mem, rRegI src) | |
| 6913 %{ | |
| 6914 match(Set mem (StoreC mem src)); | |
| 6915 | |
| 6916 ins_cost(125); // XXX | |
| 6917 format %{ "movw $mem, $src\t# char/short" %} | |
| 6918 opcode(0x89); | |
| 6919 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
| 6920 ins_pipe(ialu_mem_reg); | |
| 6921 %} | |
| 6922 | |
| 6923 // Store Integer | |
| 6924 instruct storeI(memory mem, rRegI src) | |
| 6925 %{ | |
| 6926 match(Set mem (StoreI mem src)); | |
| 6927 | |
| 6928 ins_cost(125); // XXX | |
| 6929 format %{ "movl $mem, $src\t# int" %} | |
| 6930 opcode(0x89); | |
| 6931 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
| 6932 ins_pipe(ialu_mem_reg); | |
| 6933 %} | |
| 6934 | |
| 6935 // Store Long | |
| 6936 instruct storeL(memory mem, rRegL src) | |
| 6937 %{ | |
| 6938 match(Set mem (StoreL mem src)); | |
| 6939 | |
| 6940 ins_cost(125); // XXX | |
| 6941 format %{ "movq $mem, $src\t# long" %} | |
| 6942 opcode(0x89); | |
| 6943 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem)); | |
| 6944 ins_pipe(ialu_mem_reg); // XXX | |
| 6945 %} | |
| 6946 | |
| 6947 // Store Pointer | |
| 6948 instruct storeP(memory mem, any_RegP src) | |
| 6949 %{ | |
| 6950 match(Set mem (StoreP mem src)); | |
| 6951 | |
| 6952 ins_cost(125); // XXX | |
| 6953 format %{ "movq $mem, $src\t# ptr" %} | |
| 6954 opcode(0x89); | |
| 6955 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem)); | |
| 6956 ins_pipe(ialu_mem_reg); | |
| 6957 %} | |
| 6958 | |
|
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6959 instruct storeImmP0(memory mem, immP0 zero) |
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6960 %{ |
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6961 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
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6962 match(Set mem (StoreP mem zero)); |
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6963 |
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6964 ins_cost(125); // XXX |
|
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6965 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %} |
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6966 ins_encode %{ |
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6967 __ movq($mem$$Address, r12); |
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6968 %} |
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6969 ins_pipe(ialu_mem_reg); |
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6970 %} |
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6971 |
| 0 | 6972 // Store NULL Pointer, mark word, or other simple pointer constant. |
| 6973 instruct storeImmP(memory mem, immP31 src) | |
| 6974 %{ | |
| 6975 match(Set mem (StoreP mem src)); | |
| 6976 | |
|
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6977 ins_cost(150); // XXX |
| 0 | 6978 format %{ "movq $mem, $src\t# ptr" %} |
| 6979 opcode(0xC7); /* C7 /0 */ | |
| 6980 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); | |
| 6981 ins_pipe(ialu_mem_imm); | |
| 6982 %} | |
| 6983 | |
|
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6984 // Store Compressed Pointer |
| 163 | 6985 instruct storeN(memory mem, rRegN src) |
|
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6986 %{ |
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|
6987 match(Set mem (StoreN mem src)); |
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6988 |
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6989 ins_cost(125); // XXX |
|
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6990 format %{ "movl $mem, $src\t# compressed ptr" %} |
|
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6991 ins_encode %{ |
|
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6992 __ movl($mem$$Address, $src$$Register); |
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6993 %} |
|
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6994 ins_pipe(ialu_mem_reg); |
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parents:
624
diff
changeset
|
6995 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6996 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6997 instruct storeImmN0(memory mem, immN0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6998 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6999 predicate(Universe::narrow_oop_base() == NULL); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7000 match(Set mem (StoreN mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7001 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7002 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7003 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7004 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7005 __ movl($mem$$Address, r12); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
7006 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
7007 ins_pipe(ialu_mem_reg); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
7008 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
7009 |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7010 instruct storeImmN(memory mem, immN src) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7011 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7012 match(Set mem (StoreN mem src)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7013 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7014 ins_cost(150); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7015 format %{ "movl $mem, $src\t# compressed ptr" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7016 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7017 address con = (address)$src$$constant; |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7018 if (con == NULL) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7019 __ movl($mem$$Address, (int32_t)0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7020 } else { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7021 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7022 } |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7023 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7024 ins_pipe(ialu_mem_imm); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7025 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7026 |
| 0 | 7027 // Store Integer Immediate |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7028 instruct storeImmI0(memory mem, immI0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7029 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7030 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7031 match(Set mem (StoreI mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7032 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7033 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7034 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7035 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7036 __ movl($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7037 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7038 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7039 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7040 |
| 0 | 7041 instruct storeImmI(memory mem, immI src) |
| 7042 %{ | |
| 7043 match(Set mem (StoreI mem src)); | |
| 7044 | |
| 7045 ins_cost(150); | |
| 7046 format %{ "movl $mem, $src\t# int" %} | |
| 7047 opcode(0xC7); /* C7 /0 */ | |
| 7048 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); | |
| 7049 ins_pipe(ialu_mem_imm); | |
| 7050 %} | |
| 7051 | |
| 7052 // Store Long Immediate | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7053 instruct storeImmL0(memory mem, immL0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7054 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7055 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7056 match(Set mem (StoreL mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7057 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7058 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7059 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7060 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7061 __ movq($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7062 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7063 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7064 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7065 |
| 0 | 7066 instruct storeImmL(memory mem, immL32 src) |
| 7067 %{ | |
| 7068 match(Set mem (StoreL mem src)); | |
| 7069 | |
| 7070 ins_cost(150); | |
| 7071 format %{ "movq $mem, $src\t# long" %} | |
| 7072 opcode(0xC7); /* C7 /0 */ | |
| 7073 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); | |
| 7074 ins_pipe(ialu_mem_imm); | |
| 7075 %} | |
| 7076 | |
| 7077 // Store Short/Char Immediate | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7078 instruct storeImmC0(memory mem, immI0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7079 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7080 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7081 match(Set mem (StoreC mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7082 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7083 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7084 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7085 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7086 __ movw($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7087 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7088 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7089 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7090 |
| 0 | 7091 instruct storeImmI16(memory mem, immI16 src) |
| 7092 %{ | |
| 7093 predicate(UseStoreImmI16); | |
| 7094 match(Set mem (StoreC mem src)); | |
| 7095 | |
| 7096 ins_cost(150); | |
| 7097 format %{ "movw $mem, $src\t# short/char" %} | |
| 7098 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */ | |
| 7099 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src)); | |
| 7100 ins_pipe(ialu_mem_imm); | |
| 7101 %} | |
| 7102 | |
| 7103 // Store Byte Immediate | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7104 instruct storeImmB0(memory mem, immI0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7105 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7106 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7107 match(Set mem (StoreB mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7108 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7109 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7110 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7111 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7112 __ movb($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7113 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7114 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7115 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7116 |
| 0 | 7117 instruct storeImmB(memory mem, immI8 src) |
| 7118 %{ | |
| 7119 match(Set mem (StoreB mem src)); | |
| 7120 | |
| 7121 ins_cost(150); // XXX | |
| 7122 format %{ "movb $mem, $src\t# byte" %} | |
| 7123 opcode(0xC6); /* C6 /0 */ | |
| 7124 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src)); | |
| 7125 ins_pipe(ialu_mem_imm); | |
| 7126 %} | |
| 7127 | |
| 7128 // Store Aligned Packed Byte XMM register to memory | |
| 7129 instruct storeA8B(memory mem, regD src) %{ | |
| 7130 match(Set mem (Store8B mem src)); | |
| 7131 ins_cost(145); | |
| 7132 format %{ "MOVQ $mem,$src\t! packed8B" %} | |
| 7133 ins_encode( movq_st(mem, src)); | |
| 7134 ins_pipe( pipe_slow ); | |
| 7135 %} | |
| 7136 | |
| 7137 // Store Aligned Packed Char/Short XMM register to memory | |
| 7138 instruct storeA4C(memory mem, regD src) %{ | |
| 7139 match(Set mem (Store4C mem src)); | |
| 7140 ins_cost(145); | |
| 7141 format %{ "MOVQ $mem,$src\t! packed4C" %} | |
| 7142 ins_encode( movq_st(mem, src)); | |
| 7143 ins_pipe( pipe_slow ); | |
| 7144 %} | |
| 7145 | |
| 7146 // Store Aligned Packed Integer XMM register to memory | |
| 7147 instruct storeA2I(memory mem, regD src) %{ | |
| 7148 match(Set mem (Store2I mem src)); | |
| 7149 ins_cost(145); | |
| 7150 format %{ "MOVQ $mem,$src\t! packed2I" %} | |
| 7151 ins_encode( movq_st(mem, src)); | |
| 7152 ins_pipe( pipe_slow ); | |
| 7153 %} | |
| 7154 | |
| 7155 // Store CMS card-mark Immediate | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7156 instruct storeImmCM0_reg(memory mem, immI0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7157 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7158 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7159 match(Set mem (StoreCM mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7160 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7161 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7162 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7163 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7164 __ movb($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7165 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7166 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7167 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7168 |
| 0 | 7169 instruct storeImmCM0(memory mem, immI0 src) |
| 7170 %{ | |
| 7171 match(Set mem (StoreCM mem src)); | |
| 7172 | |
| 7173 ins_cost(150); // XXX | |
| 7174 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %} | |
| 7175 opcode(0xC6); /* C6 /0 */ | |
| 7176 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src)); | |
| 7177 ins_pipe(ialu_mem_imm); | |
| 7178 %} | |
| 7179 | |
| 7180 // Store Aligned Packed Single Float XMM register to memory | |
| 7181 instruct storeA2F(memory mem, regD src) %{ | |
| 7182 match(Set mem (Store2F mem src)); | |
| 7183 ins_cost(145); | |
| 7184 format %{ "MOVQ $mem,$src\t! packed2F" %} | |
| 7185 ins_encode( movq_st(mem, src)); | |
| 7186 ins_pipe( pipe_slow ); | |
| 7187 %} | |
| 7188 | |
| 7189 // Store Float | |
| 7190 instruct storeF(memory mem, regF src) | |
| 7191 %{ | |
| 7192 match(Set mem (StoreF mem src)); | |
| 7193 | |
| 7194 ins_cost(95); // XXX | |
| 7195 format %{ "movss $mem, $src\t# float" %} | |
| 7196 opcode(0xF3, 0x0F, 0x11); | |
| 7197 ins_encode(OpcP, REX_reg_mem(src, mem), OpcS, OpcT, reg_mem(src, mem)); | |
| 7198 ins_pipe(pipe_slow); // XXX | |
| 7199 %} | |
| 7200 | |
| 7201 // Store immediate Float value (it is faster than store from XMM register) | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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|
7202 instruct storeF0(memory mem, immF0 zero) |
|
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|
7203 %{ |
|
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|
7204 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
|
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|
7205 match(Set mem (StoreF mem zero)); |
|
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|
7206 |
|
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|
7207 ins_cost(25); // XXX |
|
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|
7208 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %} |
|
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|
7209 ins_encode %{ |
|
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|
7210 __ movl($mem$$Address, r12); |
|
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|
7211 %} |
|
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|
7212 ins_pipe(ialu_mem_reg); |
|
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|
7213 %} |
|
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|
7214 |
| 0 | 7215 instruct storeF_imm(memory mem, immF src) |
| 7216 %{ | |
| 7217 match(Set mem (StoreF mem src)); | |
| 7218 | |
| 7219 ins_cost(50); | |
| 7220 format %{ "movl $mem, $src\t# float" %} | |
| 7221 opcode(0xC7); /* C7 /0 */ | |
| 7222 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src)); | |
| 7223 ins_pipe(ialu_mem_imm); | |
| 7224 %} | |
| 7225 | |
| 7226 // Store Double | |
| 7227 instruct storeD(memory mem, regD src) | |
| 7228 %{ | |
| 7229 match(Set mem (StoreD mem src)); | |
| 7230 | |
| 7231 ins_cost(95); // XXX | |
| 7232 format %{ "movsd $mem, $src\t# double" %} | |
| 7233 opcode(0xF2, 0x0F, 0x11); | |
| 7234 ins_encode(OpcP, REX_reg_mem(src, mem), OpcS, OpcT, reg_mem(src, mem)); | |
| 7235 ins_pipe(pipe_slow); // XXX | |
| 7236 %} | |
| 7237 | |
| 7238 // Store immediate double 0.0 (it is faster than store from XMM register) | |
| 7239 instruct storeD0_imm(memory mem, immD0 src) | |
| 7240 %{ | |
|
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|
7241 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL)); |
| 0 | 7242 match(Set mem (StoreD mem src)); |
| 7243 | |
| 7244 ins_cost(50); | |
| 7245 format %{ "movq $mem, $src\t# double 0." %} | |
| 7246 opcode(0xC7); /* C7 /0 */ | |
| 7247 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src)); | |
| 7248 ins_pipe(ialu_mem_imm); | |
| 7249 %} | |
| 7250 | |
|
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|
7251 instruct storeD0(memory mem, immD0 zero) |
|
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|
7252 %{ |
|
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|
7253 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
|
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|
7254 match(Set mem (StoreD mem zero)); |
|
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|
7255 |
|
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|
7256 ins_cost(25); // XXX |
|
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|
7257 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %} |
|
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|
7258 ins_encode %{ |
|
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|
7259 __ movq($mem$$Address, r12); |
|
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|
7260 %} |
|
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|
7261 ins_pipe(ialu_mem_reg); |
|
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|
7262 %} |
|
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|
7263 |
| 0 | 7264 instruct storeSSI(stackSlotI dst, rRegI src) |
| 7265 %{ | |
| 7266 match(Set dst src); | |
| 7267 | |
| 7268 ins_cost(100); | |
| 7269 format %{ "movl $dst, $src\t# int stk" %} | |
| 7270 opcode(0x89); | |
| 7271 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 7272 ins_pipe( ialu_mem_reg ); | |
| 7273 %} | |
| 7274 | |
| 7275 instruct storeSSL(stackSlotL dst, rRegL src) | |
| 7276 %{ | |
| 7277 match(Set dst src); | |
| 7278 | |
| 7279 ins_cost(100); | |
| 7280 format %{ "movq $dst, $src\t# long stk" %} | |
| 7281 opcode(0x89); | |
| 7282 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 7283 ins_pipe(ialu_mem_reg); | |
| 7284 %} | |
| 7285 | |
| 7286 instruct storeSSP(stackSlotP dst, rRegP src) | |
| 7287 %{ | |
| 7288 match(Set dst src); | |
| 7289 | |
| 7290 ins_cost(100); | |
| 7291 format %{ "movq $dst, $src\t# ptr stk" %} | |
| 7292 opcode(0x89); | |
| 7293 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 7294 ins_pipe(ialu_mem_reg); | |
| 7295 %} | |
| 7296 | |
| 7297 instruct storeSSF(stackSlotF dst, regF src) | |
| 7298 %{ | |
| 7299 match(Set dst src); | |
| 7300 | |
| 7301 ins_cost(95); // XXX | |
| 7302 format %{ "movss $dst, $src\t# float stk" %} | |
| 7303 opcode(0xF3, 0x0F, 0x11); | |
| 7304 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst)); | |
| 7305 ins_pipe(pipe_slow); // XXX | |
| 7306 %} | |
| 7307 | |
| 7308 instruct storeSSD(stackSlotD dst, regD src) | |
| 7309 %{ | |
| 7310 match(Set dst src); | |
| 7311 | |
| 7312 ins_cost(95); // XXX | |
| 7313 format %{ "movsd $dst, $src\t# double stk" %} | |
| 7314 opcode(0xF2, 0x0F, 0x11); | |
| 7315 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst)); | |
| 7316 ins_pipe(pipe_slow); // XXX | |
| 7317 %} | |
| 7318 | |
| 7319 //----------BSWAP Instructions------------------------------------------------- | |
| 7320 instruct bytes_reverse_int(rRegI dst) %{ | |
| 7321 match(Set dst (ReverseBytesI dst)); | |
| 7322 | |
| 7323 format %{ "bswapl $dst" %} | |
| 7324 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */ | |
| 7325 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) ); | |
| 7326 ins_pipe( ialu_reg ); | |
| 7327 %} | |
| 7328 | |
| 7329 instruct bytes_reverse_long(rRegL dst) %{ | |
| 7330 match(Set dst (ReverseBytesL dst)); | |
| 7331 | |
| 7332 format %{ "bswapq $dst" %} | |
| 7333 | |
| 7334 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */ | |
| 7335 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) ); | |
| 7336 ins_pipe( ialu_reg); | |
| 7337 %} | |
| 7338 | |
| 7339 instruct loadI_reversed(rRegI dst, memory src) %{ | |
| 7340 match(Set dst (ReverseBytesI (LoadI src))); | |
| 7341 | |
| 7342 format %{ "bswap_movl $dst, $src" %} | |
| 7343 opcode(0x8B, 0x0F, 0xC8); /* Opcode 8B 0F C8 */ | |
| 7344 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src), REX_reg(dst), OpcS, opc3_reg(dst)); | |
| 7345 ins_pipe( ialu_reg_mem ); | |
| 7346 %} | |
| 7347 | |
| 7348 instruct loadL_reversed(rRegL dst, memory src) %{ | |
| 7349 match(Set dst (ReverseBytesL (LoadL src))); | |
| 7350 | |
| 7351 format %{ "bswap_movq $dst, $src" %} | |
| 7352 opcode(0x8B, 0x0F, 0xC8); /* Opcode 8B 0F C8 */ | |
| 7353 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src), REX_reg_wide(dst), OpcS, opc3_reg(dst)); | |
| 7354 ins_pipe( ialu_reg_mem ); | |
| 7355 %} | |
| 7356 | |
| 7357 instruct storeI_reversed(memory dst, rRegI src) %{ | |
| 7358 match(Set dst (StoreI dst (ReverseBytesI src))); | |
| 7359 | |
| 7360 format %{ "movl_bswap $dst, $src" %} | |
| 7361 opcode(0x0F, 0xC8, 0x89); /* Opcode 0F C8 89 */ | |
| 7362 ins_encode( REX_reg(src), OpcP, opc2_reg(src), REX_reg_mem(src, dst), OpcT, reg_mem(src, dst) ); | |
| 7363 ins_pipe( ialu_mem_reg ); | |
| 7364 %} | |
| 7365 | |
| 7366 instruct storeL_reversed(memory dst, rRegL src) %{ | |
| 7367 match(Set dst (StoreL dst (ReverseBytesL src))); | |
| 7368 | |
| 7369 format %{ "movq_bswap $dst, $src" %} | |
| 7370 opcode(0x0F, 0xC8, 0x89); /* Opcode 0F C8 89 */ | |
| 7371 ins_encode( REX_reg_wide(src), OpcP, opc2_reg(src), REX_reg_mem_wide(src, dst), OpcT, reg_mem(src, dst) ); | |
| 7372 ins_pipe( ialu_mem_reg ); | |
| 7373 %} | |
| 7374 | |
|
643
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|
7375 |
|
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|
7376 //---------- Population Count Instructions ------------------------------------- |
|
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|
7377 |
|
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|
7378 instruct popCountI(rRegI dst, rRegI src) %{ |
|
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|
7379 predicate(UsePopCountInstruction); |
|
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|
7380 match(Set dst (PopCountI src)); |
|
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|
7381 |
|
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|
7382 format %{ "popcnt $dst, $src" %} |
|
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|
7383 ins_encode %{ |
|
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|
7384 __ popcntl($dst$$Register, $src$$Register); |
|
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|
7385 %} |
|
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|
7386 ins_pipe(ialu_reg); |
|
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diff
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|
7387 %} |
|
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|
7388 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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diff
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|
7389 instruct popCountI_mem(rRegI dst, memory mem) %{ |
|
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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|
7390 predicate(UsePopCountInstruction); |
|
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|
7391 match(Set dst (PopCountI (LoadI mem))); |
|
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|
7392 |
|
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diff
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|
7393 format %{ "popcnt $dst, $mem" %} |
|
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|
7394 ins_encode %{ |
|
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|
7395 __ popcntl($dst$$Register, $mem$$Address); |
|
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|
7396 %} |
|
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|
7397 ins_pipe(ialu_reg); |
|
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|
7398 %} |
|
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|
7399 |
|
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|
7400 // Note: Long.bitCount(long) returns an int. |
|
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|
7401 instruct popCountL(rRegI dst, rRegL src) %{ |
|
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|
7402 predicate(UsePopCountInstruction); |
|
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|
7403 match(Set dst (PopCountL src)); |
|
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|
7404 |
|
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|
7405 format %{ "popcnt $dst, $src" %} |
|
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|
7406 ins_encode %{ |
|
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|
7407 __ popcntq($dst$$Register, $src$$Register); |
|
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|
7408 %} |
|
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|
7409 ins_pipe(ialu_reg); |
|
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|
7410 %} |
|
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|
7411 |
|
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|
7412 // Note: Long.bitCount(long) returns an int. |
|
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|
7413 instruct popCountL_mem(rRegI dst, memory mem) %{ |
|
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|
7414 predicate(UsePopCountInstruction); |
|
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|
7415 match(Set dst (PopCountL (LoadL mem))); |
|
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|
7416 |
|
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|
7417 format %{ "popcnt $dst, $mem" %} |
|
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|
7418 ins_encode %{ |
|
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|
7419 __ popcntq($dst$$Register, $mem$$Address); |
|
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|
7420 %} |
|
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|
7421 ins_pipe(ialu_reg); |
|
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|
7422 %} |
|
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|
7423 |
|
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|
7424 |
| 0 | 7425 //----------MemBar Instructions----------------------------------------------- |
| 7426 // Memory barrier flavors | |
| 7427 | |
| 7428 instruct membar_acquire() | |
| 7429 %{ | |
| 7430 match(MemBarAcquire); | |
| 7431 ins_cost(0); | |
| 7432 | |
| 7433 size(0); | |
|
671
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|
7434 format %{ "MEMBAR-acquire ! (empty encoding)" %} |
| 0 | 7435 ins_encode(); |
| 7436 ins_pipe(empty); | |
| 7437 %} | |
| 7438 | |
| 7439 instruct membar_acquire_lock() | |
| 7440 %{ | |
| 7441 match(MemBarAcquire); | |
| 7442 predicate(Matcher::prior_fast_lock(n)); | |
| 7443 ins_cost(0); | |
| 7444 | |
| 7445 size(0); | |
| 7446 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %} | |
| 7447 ins_encode(); | |
| 7448 ins_pipe(empty); | |
| 7449 %} | |
| 7450 | |
| 7451 instruct membar_release() | |
| 7452 %{ | |
| 7453 match(MemBarRelease); | |
| 7454 ins_cost(0); | |
| 7455 | |
| 7456 size(0); | |
|
671
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6822204: volatile fences should prefer lock:addl to actual mfence instructions
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647
diff
changeset
|
7457 format %{ "MEMBAR-release ! (empty encoding)" %} |
| 0 | 7458 ins_encode(); |
| 7459 ins_pipe(empty); | |
| 7460 %} | |
| 7461 | |
| 7462 instruct membar_release_lock() | |
| 7463 %{ | |
| 7464 match(MemBarRelease); | |
| 7465 predicate(Matcher::post_fast_unlock(n)); | |
| 7466 ins_cost(0); | |
| 7467 | |
| 7468 size(0); | |
| 7469 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %} | |
| 7470 ins_encode(); | |
| 7471 ins_pipe(empty); | |
| 7472 %} | |
| 7473 | |
|
671
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6822204: volatile fences should prefer lock:addl to actual mfence instructions
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647
diff
changeset
|
7474 instruct membar_volatile(rFlagsReg cr) %{ |
| 0 | 7475 match(MemBarVolatile); |
|
671
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6822204: volatile fences should prefer lock:addl to actual mfence instructions
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parents:
647
diff
changeset
|
7476 effect(KILL cr); |
| 0 | 7477 ins_cost(400); |
| 7478 | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
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parents:
647
diff
changeset
|
7479 format %{ |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7480 $$template |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7481 if (os::is_MP()) { |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
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parents:
647
diff
changeset
|
7482 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile" |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7483 } else { |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7484 $$emit$$"MEMBAR-volatile ! (empty encoding)" |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7485 } |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7486 %} |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7487 ins_encode %{ |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7488 __ membar(Assembler::StoreLoad); |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
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parents:
647
diff
changeset
|
7489 %} |
| 0 | 7490 ins_pipe(pipe_slow); |
| 7491 %} | |
| 7492 | |
| 7493 instruct unnecessary_membar_volatile() | |
| 7494 %{ | |
| 7495 match(MemBarVolatile); | |
| 7496 predicate(Matcher::post_store_load_barrier(n)); | |
| 7497 ins_cost(0); | |
| 7498 | |
| 7499 size(0); | |
| 7500 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %} | |
| 7501 ins_encode(); | |
| 7502 ins_pipe(empty); | |
| 7503 %} | |
| 7504 | |
| 7505 //----------Move Instructions-------------------------------------------------- | |
| 7506 | |
| 7507 instruct castX2P(rRegP dst, rRegL src) | |
| 7508 %{ | |
| 7509 match(Set dst (CastX2P src)); | |
| 7510 | |
| 7511 format %{ "movq $dst, $src\t# long->ptr" %} | |
| 7512 ins_encode(enc_copy_wide(dst, src)); | |
| 7513 ins_pipe(ialu_reg_reg); // XXX | |
| 7514 %} | |
| 7515 | |
| 7516 instruct castP2X(rRegL dst, rRegP src) | |
| 7517 %{ | |
| 7518 match(Set dst (CastP2X src)); | |
| 7519 | |
| 7520 format %{ "movq $dst, $src\t# ptr -> long" %} | |
| 7521 ins_encode(enc_copy_wide(dst, src)); | |
| 7522 ins_pipe(ialu_reg_reg); // XXX | |
| 7523 %} | |
| 7524 | |
|
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|
7525 |
|
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changeset
|
7526 // Convert oop pointer into compressed form |
|
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diff
changeset
|
7527 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{ |
|
221
1e026f8da827
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changeset
|
7528 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); |
|
113
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|
7529 match(Set dst (EncodeP src)); |
|
ba764ed4b6f2
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71
diff
changeset
|
7530 effect(KILL cr); |
|
ba764ed4b6f2
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diff
changeset
|
7531 format %{ "encode_heap_oop $dst,$src" %} |
|
ba764ed4b6f2
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changeset
|
7532 ins_encode %{ |
|
ba764ed4b6f2
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diff
changeset
|
7533 Register s = $src$$Register; |
|
ba764ed4b6f2
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diff
changeset
|
7534 Register d = $dst$$Register; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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71
diff
changeset
|
7535 if (s != d) { |
|
ba764ed4b6f2
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71
diff
changeset
|
7536 __ movq(d, s); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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diff
changeset
|
7537 } |
|
ba764ed4b6f2
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diff
changeset
|
7538 __ encode_heap_oop(d); |
|
ba764ed4b6f2
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changeset
|
7539 %} |
|
ba764ed4b6f2
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coleenp
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71
diff
changeset
|
7540 ins_pipe(ialu_reg_long); |
|
ba764ed4b6f2
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71
diff
changeset
|
7541 %} |
|
ba764ed4b6f2
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71
diff
changeset
|
7542 |
|
124
b130b98db9cf
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kvn
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113
diff
changeset
|
7543 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{ |
|
221
1e026f8da827
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changeset
|
7544 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); |
|
124
b130b98db9cf
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kvn
parents:
113
diff
changeset
|
7545 match(Set dst (EncodeP src)); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
7546 effect(KILL cr); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
7547 format %{ "encode_heap_oop_not_null $dst,$src" %} |
|
b130b98db9cf
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kvn
parents:
113
diff
changeset
|
7548 ins_encode %{ |
|
642
660978a2a31a
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diff
changeset
|
7549 __ encode_heap_oop_not_null($dst$$Register, $src$$Register); |
|
124
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diff
changeset
|
7550 %} |
|
b130b98db9cf
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kvn
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113
diff
changeset
|
7551 ins_pipe(ialu_reg_long); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
7552 %} |
|
b130b98db9cf
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kvn
parents:
113
diff
changeset
|
7553 |
|
113
ba764ed4b6f2
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coleenp
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diff
changeset
|
7554 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{ |
|
182
44abbb0d4c18
6709093: Compressed Oops: reduce size of compiled methods
kvn
parents:
169
diff
changeset
|
7555 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && |
|
44abbb0d4c18
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kvn
parents:
169
diff
changeset
|
7556 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant); |
|
113
ba764ed4b6f2
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71
diff
changeset
|
7557 match(Set dst (DecodeN src)); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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71
diff
changeset
|
7558 effect(KILL cr); |
|
ba764ed4b6f2
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coleenp
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71
diff
changeset
|
7559 format %{ "decode_heap_oop $dst,$src" %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
7560 ins_encode %{ |
|
ba764ed4b6f2
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coleenp
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71
diff
changeset
|
7561 Register s = $src$$Register; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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71
diff
changeset
|
7562 Register d = $dst$$Register; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
7563 if (s != d) { |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
7564 __ movq(d, s); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
7565 } |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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71
diff
changeset
|
7566 __ decode_heap_oop(d); |
|
ba764ed4b6f2
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71
diff
changeset
|
7567 %} |
|
ba764ed4b6f2
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coleenp
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71
diff
changeset
|
7568 ins_pipe(ialu_reg_long); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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71
diff
changeset
|
7569 %} |
|
ba764ed4b6f2
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coleenp
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71
diff
changeset
|
7570 |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
7571 instruct decodeHeapOop_not_null(rRegP dst, rRegN src) %{ |
|
182
44abbb0d4c18
6709093: Compressed Oops: reduce size of compiled methods
kvn
parents:
169
diff
changeset
|
7572 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || |
|
44abbb0d4c18
6709093: Compressed Oops: reduce size of compiled methods
kvn
parents:
169
diff
changeset
|
7573 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant); |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
7574 match(Set dst (DecodeN src)); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
7575 format %{ "decode_heap_oop_not_null $dst,$src" %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
7576 ins_encode %{ |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
7577 Register s = $src$$Register; |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
7578 Register d = $dst$$Register; |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7579 if (s != d) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7580 __ decode_heap_oop_not_null(d, s); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7581 } else { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7582 __ decode_heap_oop_not_null(d); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7583 } |
|
124
b130b98db9cf
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kvn
parents:
113
diff
changeset
|
7584 %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
7585 ins_pipe(ialu_reg_long); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
7586 %} |
|
b130b98db9cf
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kvn
parents:
113
diff
changeset
|
7587 |
|
113
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coleenp
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71
diff
changeset
|
7588 |
| 0 | 7589 //----------Conditional Move--------------------------------------------------- |
| 7590 // Jump | |
| 7591 // dummy instruction for generating temp registers | |
| 7592 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{ | |
| 7593 match(Jump (LShiftL switch_val shift)); | |
| 7594 ins_cost(350); | |
| 7595 predicate(false); | |
| 7596 effect(TEMP dest); | |
| 7597 | |
| 7598 format %{ "leaq $dest, table_base\n\t" | |
| 7599 "jmp [$dest + $switch_val << $shift]\n\t" %} | |
| 7600 ins_encode(jump_enc_offset(switch_val, shift, dest)); | |
| 7601 ins_pipe(pipe_jmp); | |
| 7602 ins_pc_relative(1); | |
| 7603 %} | |
| 7604 | |
| 7605 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{ | |
| 7606 match(Jump (AddL (LShiftL switch_val shift) offset)); | |
| 7607 ins_cost(350); | |
| 7608 effect(TEMP dest); | |
| 7609 | |
| 7610 format %{ "leaq $dest, table_base\n\t" | |
| 7611 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %} | |
| 7612 ins_encode(jump_enc_addr(switch_val, shift, offset, dest)); | |
| 7613 ins_pipe(pipe_jmp); | |
| 7614 ins_pc_relative(1); | |
| 7615 %} | |
| 7616 | |
| 7617 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{ | |
| 7618 match(Jump switch_val); | |
| 7619 ins_cost(350); | |
| 7620 effect(TEMP dest); | |
| 7621 | |
| 7622 format %{ "leaq $dest, table_base\n\t" | |
| 7623 "jmp [$dest + $switch_val]\n\t" %} | |
| 7624 ins_encode(jump_enc(switch_val, dest)); | |
| 7625 ins_pipe(pipe_jmp); | |
| 7626 ins_pc_relative(1); | |
| 7627 %} | |
| 7628 | |
| 7629 // Conditional move | |
| 7630 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop) | |
| 7631 %{ | |
| 7632 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 7633 | |
| 7634 ins_cost(200); // XXX | |
| 7635 format %{ "cmovl$cop $dst, $src\t# signed, int" %} | |
| 7636 opcode(0x0F, 0x40); | |
| 7637 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 7638 ins_pipe(pipe_cmov_reg); | |
| 7639 %} | |
| 7640 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7641 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{ |
| 0 | 7642 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); |
| 7643 | |
| 7644 ins_cost(200); // XXX | |
| 7645 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %} | |
| 7646 opcode(0x0F, 0x40); | |
| 7647 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 7648 ins_pipe(pipe_cmov_reg); | |
| 7649 %} | |
| 7650 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7651 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7652 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7653 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7654 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7655 cmovI_regU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7656 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7657 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7658 |
| 0 | 7659 // Conditional move |
|
415
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6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7660 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{ |
| 0 | 7661 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); |
| 7662 | |
| 7663 ins_cost(250); // XXX | |
| 7664 format %{ "cmovl$cop $dst, $src\t# signed, int" %} | |
| 7665 opcode(0x0F, 0x40); | |
| 7666 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
| 7667 ins_pipe(pipe_cmov_mem); | |
| 7668 %} | |
| 7669 | |
| 7670 // Conditional move | |
| 7671 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src) | |
| 7672 %{ | |
| 7673 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); | |
| 7674 | |
| 7675 ins_cost(250); // XXX | |
| 7676 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %} | |
| 7677 opcode(0x0F, 0x40); | |
| 7678 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
| 7679 ins_pipe(pipe_cmov_mem); | |
| 7680 %} | |
| 7681 | |
|
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|
7682 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{ |
|
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|
7683 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); |
|
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diff
changeset
|
7684 ins_cost(250); |
|
4d9884b01ba6
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never
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403
diff
changeset
|
7685 expand %{ |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7686 cmovI_memU(cop, cr, dst, src); |
|
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403
diff
changeset
|
7687 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7688 %} |
|
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6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
7689 |
| 0 | 7690 // Conditional move |
|
164
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|
7691 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop) |
|
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changeset
|
7692 %{ |
|
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|
7693 match(Set dst (CMoveN (Binary cop cr) (Binary dst src))); |
|
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changeset
|
7694 |
|
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changeset
|
7695 ins_cost(200); // XXX |
|
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|
7696 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %} |
|
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changeset
|
7697 opcode(0x0F, 0x40); |
|
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changeset
|
7698 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); |
|
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changeset
|
7699 ins_pipe(pipe_cmov_reg); |
|
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changeset
|
7700 %} |
|
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changeset
|
7701 |
|
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changeset
|
7702 // Conditional move |
|
415
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|
7703 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src) |
|
164
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changeset
|
7704 %{ |
|
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changeset
|
7705 match(Set dst (CMoveN (Binary cop cr) (Binary dst src))); |
|
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changeset
|
7706 |
|
c436414a719e
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kvn
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diff
changeset
|
7707 ins_cost(200); // XXX |
|
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changeset
|
7708 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %} |
|
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changeset
|
7709 opcode(0x0F, 0x40); |
|
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kvn
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changeset
|
7710 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); |
|
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changeset
|
7711 ins_pipe(pipe_cmov_reg); |
|
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changeset
|
7712 %} |
|
c436414a719e
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163
diff
changeset
|
7713 |
|
415
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parents:
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diff
changeset
|
7714 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{ |
|
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diff
changeset
|
7715 match(Set dst (CMoveN (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7716 ins_cost(200); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7717 expand %{ |
|
4d9884b01ba6
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403
diff
changeset
|
7718 cmovN_regU(cop, cr, dst, src); |
|
4d9884b01ba6
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diff
changeset
|
7719 %} |
|
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never
parents:
403
diff
changeset
|
7720 %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7721 |
|
164
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|
7722 // Conditional move |
| 0 | 7723 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop) |
| 7724 %{ | |
| 7725 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 7726 | |
| 7727 ins_cost(200); // XXX | |
| 7728 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %} | |
| 7729 opcode(0x0F, 0x40); | |
| 7730 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 7731 ins_pipe(pipe_cmov_reg); // XXX | |
| 7732 %} | |
| 7733 | |
| 7734 // Conditional move | |
|
415
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changeset
|
7735 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src) |
| 0 | 7736 %{ |
| 7737 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 7738 | |
| 7739 ins_cost(200); // XXX | |
| 7740 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %} | |
| 7741 opcode(0x0F, 0x40); | |
| 7742 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 7743 ins_pipe(pipe_cmov_reg); // XXX | |
| 7744 %} | |
| 7745 | |
|
415
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changeset
|
7746 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{ |
|
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403
diff
changeset
|
7747 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7748 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7749 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7750 cmovP_regU(cop, cr, dst, src); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7751 %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7752 %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7753 |
| 0 | 7754 // DISABLED: Requires the ADLC to emit a bottom_type call that |
| 7755 // correctly meets the two pointer arguments; one is an incoming | |
| 7756 // register but the other is a memory operand. ALSO appears to | |
| 7757 // be buggy with implicit null checks. | |
| 7758 // | |
| 7759 //// Conditional move | |
| 7760 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src) | |
| 7761 //%{ | |
| 7762 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 7763 // ins_cost(250); | |
| 7764 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 7765 // opcode(0x0F,0x40); | |
| 7766 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) ); | |
| 7767 // ins_pipe( pipe_cmov_mem ); | |
| 7768 //%} | |
| 7769 // | |
| 7770 //// Conditional move | |
| 7771 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src) | |
| 7772 //%{ | |
| 7773 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 7774 // ins_cost(250); | |
| 7775 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 7776 // opcode(0x0F,0x40); | |
| 7777 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) ); | |
| 7778 // ins_pipe( pipe_cmov_mem ); | |
| 7779 //%} | |
| 7780 | |
| 7781 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src) | |
| 7782 %{ | |
| 7783 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 7784 | |
| 7785 ins_cost(200); // XXX | |
| 7786 format %{ "cmovq$cop $dst, $src\t# signed, long" %} | |
| 7787 opcode(0x0F, 0x40); | |
| 7788 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 7789 ins_pipe(pipe_cmov_reg); // XXX | |
| 7790 %} | |
| 7791 | |
| 7792 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src) | |
| 7793 %{ | |
| 7794 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src)))); | |
| 7795 | |
| 7796 ins_cost(200); // XXX | |
| 7797 format %{ "cmovq$cop $dst, $src\t# signed, long" %} | |
| 7798 opcode(0x0F, 0x40); | |
| 7799 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
| 7800 ins_pipe(pipe_cmov_mem); // XXX | |
| 7801 %} | |
| 7802 | |
| 7803 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src) | |
| 7804 %{ | |
| 7805 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 7806 | |
| 7807 ins_cost(200); // XXX | |
| 7808 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %} | |
| 7809 opcode(0x0F, 0x40); | |
| 7810 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 7811 ins_pipe(pipe_cmov_reg); // XXX | |
| 7812 %} | |
| 7813 | |
|
415
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diff
changeset
|
7814 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{ |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
7815 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7816 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7817 expand %{ |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
7818 cmovL_regU(cop, cr, dst, src); |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
7819 %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7820 %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7821 |
| 0 | 7822 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src) |
| 7823 %{ | |
| 7824 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src)))); | |
| 7825 | |
| 7826 ins_cost(200); // XXX | |
| 7827 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %} | |
| 7828 opcode(0x0F, 0x40); | |
| 7829 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
| 7830 ins_pipe(pipe_cmov_mem); // XXX | |
| 7831 %} | |
| 7832 | |
|
415
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diff
changeset
|
7833 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{ |
|
4d9884b01ba6
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diff
changeset
|
7834 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src)))); |
|
4d9884b01ba6
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diff
changeset
|
7835 ins_cost(200); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7836 expand %{ |
|
4d9884b01ba6
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diff
changeset
|
7837 cmovL_memU(cop, cr, dst, src); |
|
4d9884b01ba6
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403
diff
changeset
|
7838 %} |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
7839 %} |
|
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parents:
403
diff
changeset
|
7840 |
| 0 | 7841 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src) |
| 7842 %{ | |
| 7843 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 7844 | |
| 7845 ins_cost(200); // XXX | |
| 7846 format %{ "jn$cop skip\t# signed cmove float\n\t" | |
| 7847 "movss $dst, $src\n" | |
| 7848 "skip:" %} | |
| 7849 ins_encode(enc_cmovf_branch(cop, dst, src)); | |
| 7850 ins_pipe(pipe_slow); | |
| 7851 %} | |
| 7852 | |
| 7853 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src) | |
| 7854 // %{ | |
| 7855 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src)))); | |
| 7856 | |
| 7857 // ins_cost(200); // XXX | |
| 7858 // format %{ "jn$cop skip\t# signed cmove float\n\t" | |
| 7859 // "movss $dst, $src\n" | |
| 7860 // "skip:" %} | |
| 7861 // ins_encode(enc_cmovf_mem_branch(cop, dst, src)); | |
| 7862 // ins_pipe(pipe_slow); | |
| 7863 // %} | |
| 7864 | |
| 7865 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src) | |
| 7866 %{ | |
| 7867 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 7868 | |
| 7869 ins_cost(200); // XXX | |
| 7870 format %{ "jn$cop skip\t# unsigned cmove float\n\t" | |
| 7871 "movss $dst, $src\n" | |
| 7872 "skip:" %} | |
| 7873 ins_encode(enc_cmovf_branch(cop, dst, src)); | |
| 7874 ins_pipe(pipe_slow); | |
| 7875 %} | |
| 7876 | |
|
415
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diff
changeset
|
7877 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{ |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
7878 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7879 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7880 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7881 cmovF_regU(cop, cr, dst, src); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7882 %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7883 %} |
|
4d9884b01ba6
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diff
changeset
|
7884 |
| 0 | 7885 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src) |
| 7886 %{ | |
| 7887 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 7888 | |
| 7889 ins_cost(200); // XXX | |
| 7890 format %{ "jn$cop skip\t# signed cmove double\n\t" | |
| 7891 "movsd $dst, $src\n" | |
| 7892 "skip:" %} | |
| 7893 ins_encode(enc_cmovd_branch(cop, dst, src)); | |
| 7894 ins_pipe(pipe_slow); | |
| 7895 %} | |
| 7896 | |
| 7897 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src) | |
| 7898 %{ | |
| 7899 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 7900 | |
| 7901 ins_cost(200); // XXX | |
| 7902 format %{ "jn$cop skip\t# unsigned cmove double\n\t" | |
| 7903 "movsd $dst, $src\n" | |
| 7904 "skip:" %} | |
| 7905 ins_encode(enc_cmovd_branch(cop, dst, src)); | |
| 7906 ins_pipe(pipe_slow); | |
| 7907 %} | |
| 7908 | |
|
415
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|
7909 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{ |
|
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|
7910 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); |
|
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|
7911 ins_cost(200); |
|
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diff
changeset
|
7912 expand %{ |
|
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diff
changeset
|
7913 cmovD_regU(cop, cr, dst, src); |
|
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diff
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|
7914 %} |
|
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|
7915 %} |
|
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|
7916 |
| 0 | 7917 //----------Arithmetic Instructions-------------------------------------------- |
| 7918 //----------Addition Instructions---------------------------------------------- | |
| 7919 | |
| 7920 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 7921 %{ | |
| 7922 match(Set dst (AddI dst src)); | |
| 7923 effect(KILL cr); | |
| 7924 | |
| 7925 format %{ "addl $dst, $src\t# int" %} | |
| 7926 opcode(0x03); | |
| 7927 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 7928 ins_pipe(ialu_reg_reg); | |
| 7929 %} | |
| 7930 | |
| 7931 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 7932 %{ | |
| 7933 match(Set dst (AddI dst src)); | |
| 7934 effect(KILL cr); | |
| 7935 | |
| 7936 format %{ "addl $dst, $src\t# int" %} | |
| 7937 opcode(0x81, 0x00); /* /0 id */ | |
| 7938 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 7939 ins_pipe( ialu_reg ); | |
| 7940 %} | |
| 7941 | |
| 7942 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 7943 %{ | |
| 7944 match(Set dst (AddI dst (LoadI src))); | |
| 7945 effect(KILL cr); | |
| 7946 | |
| 7947 ins_cost(125); // XXX | |
| 7948 format %{ "addl $dst, $src\t# int" %} | |
| 7949 opcode(0x03); | |
| 7950 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 7951 ins_pipe(ialu_reg_mem); | |
| 7952 %} | |
| 7953 | |
| 7954 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 7955 %{ | |
| 7956 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7957 effect(KILL cr); | |
| 7958 | |
| 7959 ins_cost(150); // XXX | |
| 7960 format %{ "addl $dst, $src\t# int" %} | |
| 7961 opcode(0x01); /* Opcode 01 /r */ | |
| 7962 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 7963 ins_pipe(ialu_mem_reg); | |
| 7964 %} | |
| 7965 | |
| 7966 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 7967 %{ | |
| 7968 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7969 effect(KILL cr); | |
| 7970 | |
| 7971 ins_cost(125); // XXX | |
| 7972 format %{ "addl $dst, $src\t# int" %} | |
| 7973 opcode(0x81); /* Opcode 81 /0 id */ | |
| 7974 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src)); | |
| 7975 ins_pipe(ialu_mem_imm); | |
| 7976 %} | |
| 7977 | |
| 7978 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr) | |
| 7979 %{ | |
| 7980 predicate(UseIncDec); | |
| 7981 match(Set dst (AddI dst src)); | |
| 7982 effect(KILL cr); | |
| 7983 | |
| 7984 format %{ "incl $dst\t# int" %} | |
| 7985 opcode(0xFF, 0x00); // FF /0 | |
| 7986 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 7987 ins_pipe(ialu_reg); | |
| 7988 %} | |
| 7989 | |
| 7990 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr) | |
| 7991 %{ | |
| 7992 predicate(UseIncDec); | |
| 7993 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7994 effect(KILL cr); | |
| 7995 | |
| 7996 ins_cost(125); // XXX | |
| 7997 format %{ "incl $dst\t# int" %} | |
| 7998 opcode(0xFF); /* Opcode FF /0 */ | |
| 7999 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst)); | |
| 8000 ins_pipe(ialu_mem_imm); | |
| 8001 %} | |
| 8002 | |
| 8003 // XXX why does that use AddI | |
| 8004 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr) | |
| 8005 %{ | |
| 8006 predicate(UseIncDec); | |
| 8007 match(Set dst (AddI dst src)); | |
| 8008 effect(KILL cr); | |
| 8009 | |
| 8010 format %{ "decl $dst\t# int" %} | |
| 8011 opcode(0xFF, 0x01); // FF /1 | |
| 8012 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8013 ins_pipe(ialu_reg); | |
| 8014 %} | |
| 8015 | |
| 8016 // XXX why does that use AddI | |
| 8017 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr) | |
| 8018 %{ | |
| 8019 predicate(UseIncDec); | |
| 8020 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 8021 effect(KILL cr); | |
| 8022 | |
| 8023 ins_cost(125); // XXX | |
| 8024 format %{ "decl $dst\t# int" %} | |
| 8025 opcode(0xFF); /* Opcode FF /1 */ | |
| 8026 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst)); | |
| 8027 ins_pipe(ialu_mem_imm); | |
| 8028 %} | |
| 8029 | |
| 8030 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1) | |
| 8031 %{ | |
| 8032 match(Set dst (AddI src0 src1)); | |
| 8033 | |
| 8034 ins_cost(110); | |
| 8035 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %} | |
| 8036 opcode(0x8D); /* 0x8D /r */ | |
| 8037 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX | |
| 8038 ins_pipe(ialu_reg_reg); | |
| 8039 %} | |
| 8040 | |
| 8041 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 8042 %{ | |
| 8043 match(Set dst (AddL dst src)); | |
| 8044 effect(KILL cr); | |
| 8045 | |
| 8046 format %{ "addq $dst, $src\t# long" %} | |
| 8047 opcode(0x03); | |
| 8048 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 8049 ins_pipe(ialu_reg_reg); | |
| 8050 %} | |
| 8051 | |
| 8052 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
| 8053 %{ | |
| 8054 match(Set dst (AddL dst src)); | |
| 8055 effect(KILL cr); | |
| 8056 | |
| 8057 format %{ "addq $dst, $src\t# long" %} | |
| 8058 opcode(0x81, 0x00); /* /0 id */ | |
| 8059 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 8060 ins_pipe( ialu_reg ); | |
| 8061 %} | |
| 8062 | |
| 8063 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 8064 %{ | |
| 8065 match(Set dst (AddL dst (LoadL src))); | |
| 8066 effect(KILL cr); | |
| 8067 | |
| 8068 ins_cost(125); // XXX | |
| 8069 format %{ "addq $dst, $src\t# long" %} | |
| 8070 opcode(0x03); | |
| 8071 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 8072 ins_pipe(ialu_reg_mem); | |
| 8073 %} | |
| 8074 | |
| 8075 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 8076 %{ | |
| 8077 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
| 8078 effect(KILL cr); | |
| 8079 | |
| 8080 ins_cost(150); // XXX | |
| 8081 format %{ "addq $dst, $src\t# long" %} | |
| 8082 opcode(0x01); /* Opcode 01 /r */ | |
| 8083 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 8084 ins_pipe(ialu_mem_reg); | |
| 8085 %} | |
| 8086 | |
| 8087 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 8088 %{ | |
| 8089 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
| 8090 effect(KILL cr); | |
| 8091 | |
| 8092 ins_cost(125); // XXX | |
| 8093 format %{ "addq $dst, $src\t# long" %} | |
| 8094 opcode(0x81); /* Opcode 81 /0 id */ | |
| 8095 ins_encode(REX_mem_wide(dst), | |
| 8096 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src)); | |
| 8097 ins_pipe(ialu_mem_imm); | |
| 8098 %} | |
| 8099 | |
| 8100 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr) | |
| 8101 %{ | |
| 8102 predicate(UseIncDec); | |
| 8103 match(Set dst (AddL dst src)); | |
| 8104 effect(KILL cr); | |
| 8105 | |
| 8106 format %{ "incq $dst\t# long" %} | |
| 8107 opcode(0xFF, 0x00); // FF /0 | |
| 8108 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8109 ins_pipe(ialu_reg); | |
| 8110 %} | |
| 8111 | |
| 8112 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr) | |
| 8113 %{ | |
| 8114 predicate(UseIncDec); | |
| 8115 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
| 8116 effect(KILL cr); | |
| 8117 | |
| 8118 ins_cost(125); // XXX | |
| 8119 format %{ "incq $dst\t# long" %} | |
| 8120 opcode(0xFF); /* Opcode FF /0 */ | |
| 8121 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst)); | |
| 8122 ins_pipe(ialu_mem_imm); | |
| 8123 %} | |
| 8124 | |
| 8125 // XXX why does that use AddL | |
| 8126 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr) | |
| 8127 %{ | |
| 8128 predicate(UseIncDec); | |
| 8129 match(Set dst (AddL dst src)); | |
| 8130 effect(KILL cr); | |
| 8131 | |
| 8132 format %{ "decq $dst\t# long" %} | |
| 8133 opcode(0xFF, 0x01); // FF /1 | |
| 8134 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8135 ins_pipe(ialu_reg); | |
| 8136 %} | |
| 8137 | |
| 8138 // XXX why does that use AddL | |
| 8139 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr) | |
| 8140 %{ | |
| 8141 predicate(UseIncDec); | |
| 8142 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
| 8143 effect(KILL cr); | |
| 8144 | |
| 8145 ins_cost(125); // XXX | |
| 8146 format %{ "decq $dst\t# long" %} | |
| 8147 opcode(0xFF); /* Opcode FF /1 */ | |
| 8148 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst)); | |
| 8149 ins_pipe(ialu_mem_imm); | |
| 8150 %} | |
| 8151 | |
| 8152 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1) | |
| 8153 %{ | |
| 8154 match(Set dst (AddL src0 src1)); | |
| 8155 | |
| 8156 ins_cost(110); | |
| 8157 format %{ "leaq $dst, [$src0 + $src1]\t# long" %} | |
| 8158 opcode(0x8D); /* 0x8D /r */ | |
| 8159 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX | |
| 8160 ins_pipe(ialu_reg_reg); | |
| 8161 %} | |
| 8162 | |
| 8163 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr) | |
| 8164 %{ | |
| 8165 match(Set dst (AddP dst src)); | |
| 8166 effect(KILL cr); | |
| 8167 | |
| 8168 format %{ "addq $dst, $src\t# ptr" %} | |
| 8169 opcode(0x03); | |
| 8170 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 8171 ins_pipe(ialu_reg_reg); | |
| 8172 %} | |
| 8173 | |
| 8174 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr) | |
| 8175 %{ | |
| 8176 match(Set dst (AddP dst src)); | |
| 8177 effect(KILL cr); | |
| 8178 | |
| 8179 format %{ "addq $dst, $src\t# ptr" %} | |
| 8180 opcode(0x81, 0x00); /* /0 id */ | |
| 8181 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 8182 ins_pipe( ialu_reg ); | |
| 8183 %} | |
| 8184 | |
| 8185 // XXX addP mem ops ???? | |
| 8186 | |
| 8187 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1) | |
| 8188 %{ | |
| 8189 match(Set dst (AddP src0 src1)); | |
| 8190 | |
| 8191 ins_cost(110); | |
| 8192 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %} | |
| 8193 opcode(0x8D); /* 0x8D /r */ | |
| 8194 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX | |
| 8195 ins_pipe(ialu_reg_reg); | |
| 8196 %} | |
| 8197 | |
| 8198 instruct checkCastPP(rRegP dst) | |
| 8199 %{ | |
| 8200 match(Set dst (CheckCastPP dst)); | |
| 8201 | |
| 8202 size(0); | |
| 8203 format %{ "# checkcastPP of $dst" %} | |
| 8204 ins_encode(/* empty encoding */); | |
| 8205 ins_pipe(empty); | |
| 8206 %} | |
| 8207 | |
| 8208 instruct castPP(rRegP dst) | |
| 8209 %{ | |
| 8210 match(Set dst (CastPP dst)); | |
| 8211 | |
| 8212 size(0); | |
| 8213 format %{ "# castPP of $dst" %} | |
| 8214 ins_encode(/* empty encoding */); | |
| 8215 ins_pipe(empty); | |
| 8216 %} | |
| 8217 | |
| 8218 instruct castII(rRegI dst) | |
| 8219 %{ | |
| 8220 match(Set dst (CastII dst)); | |
| 8221 | |
| 8222 size(0); | |
| 8223 format %{ "# castII of $dst" %} | |
| 8224 ins_encode(/* empty encoding */); | |
| 8225 ins_cost(0); | |
| 8226 ins_pipe(empty); | |
| 8227 %} | |
| 8228 | |
| 8229 // LoadP-locked same as a regular LoadP when used with compare-swap | |
| 8230 instruct loadPLocked(rRegP dst, memory mem) | |
| 8231 %{ | |
| 8232 match(Set dst (LoadPLocked mem)); | |
| 8233 | |
| 8234 ins_cost(125); // XXX | |
| 8235 format %{ "movq $dst, $mem\t# ptr locked" %} | |
| 8236 opcode(0x8B); | |
| 8237 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 8238 ins_pipe(ialu_reg_mem); // XXX | |
| 8239 %} | |
| 8240 | |
| 8241 // LoadL-locked - same as a regular LoadL when used with compare-swap | |
| 8242 instruct loadLLocked(rRegL dst, memory mem) | |
| 8243 %{ | |
| 8244 match(Set dst (LoadLLocked mem)); | |
| 8245 | |
| 8246 ins_cost(125); // XXX | |
| 8247 format %{ "movq $dst, $mem\t# long locked" %} | |
| 8248 opcode(0x8B); | |
| 8249 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 8250 ins_pipe(ialu_reg_mem); // XXX | |
| 8251 %} | |
| 8252 | |
| 8253 // Conditional-store of the updated heap-top. | |
| 8254 // Used during allocation of the shared heap. | |
| 8255 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel. | |
| 8256 | |
| 8257 instruct storePConditional(memory heap_top_ptr, | |
| 8258 rax_RegP oldval, rRegP newval, | |
| 8259 rFlagsReg cr) | |
| 8260 %{ | |
| 8261 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval))); | |
|
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8262 |
| 0 | 8263 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) " |
| 8264 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %} | |
| 8265 opcode(0x0F, 0xB1); | |
| 8266 ins_encode(lock_prefix, | |
| 8267 REX_reg_mem_wide(newval, heap_top_ptr), | |
| 8268 OpcP, OpcS, | |
| 8269 reg_mem(newval, heap_top_ptr)); | |
| 8270 ins_pipe(pipe_cmpxchg); | |
| 8271 %} | |
| 8272 | |
|
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8273 // Conditional-store of an int value. |
|
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8274 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG. |
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8275 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr) |
|
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8276 %{ |
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8277 match(Set cr (StoreIConditional mem (Binary oldval newval))); |
|
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8278 effect(KILL oldval); |
|
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8279 |
|
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8280 format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %} |
| 0 | 8281 opcode(0x0F, 0xB1); |
| 8282 ins_encode(lock_prefix, | |
|
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8283 REX_reg_mem(newval, mem), |
| 0 | 8284 OpcP, OpcS, |
|
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8285 reg_mem(newval, mem)); |
| 0 | 8286 ins_pipe(pipe_cmpxchg); |
| 8287 %} | |
| 8288 | |
|
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8289 // Conditional-store of a long value. |
|
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8290 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG. |
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8291 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr) |
|
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8292 %{ |
|
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8293 match(Set cr (StoreLConditional mem (Binary oldval newval))); |
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8294 effect(KILL oldval); |
|
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8295 |
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8296 format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %} |
| 0 | 8297 opcode(0x0F, 0xB1); |
| 8298 ins_encode(lock_prefix, | |
|
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8299 REX_reg_mem_wide(newval, mem), |
| 0 | 8300 OpcP, OpcS, |
|
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8301 reg_mem(newval, mem)); |
| 0 | 8302 ins_pipe(pipe_cmpxchg); |
| 8303 %} | |
| 8304 | |
|
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|
8305 |
|
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8306 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them |
| 0 | 8307 instruct compareAndSwapP(rRegI res, |
| 8308 memory mem_ptr, | |
| 8309 rax_RegP oldval, rRegP newval, | |
| 8310 rFlagsReg cr) | |
| 8311 %{ | |
| 8312 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); | |
| 8313 effect(KILL cr, KILL oldval); | |
| 8314 | |
| 8315 format %{ "cmpxchgq $mem_ptr,$newval\t# " | |
| 8316 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" | |
| 8317 "sete $res\n\t" | |
| 8318 "movzbl $res, $res" %} | |
| 8319 opcode(0x0F, 0xB1); | |
| 8320 ins_encode(lock_prefix, | |
| 8321 REX_reg_mem_wide(newval, mem_ptr), | |
| 8322 OpcP, OpcS, | |
| 8323 reg_mem(newval, mem_ptr), | |
| 8324 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete | |
| 8325 REX_reg_breg(res, res), // movzbl | |
| 8326 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); | |
| 8327 ins_pipe( pipe_cmpxchg ); | |
| 8328 %} | |
| 8329 | |
| 8330 instruct compareAndSwapL(rRegI res, | |
| 8331 memory mem_ptr, | |
| 8332 rax_RegL oldval, rRegL newval, | |
| 8333 rFlagsReg cr) | |
| 8334 %{ | |
| 8335 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); | |
| 8336 effect(KILL cr, KILL oldval); | |
| 8337 | |
| 8338 format %{ "cmpxchgq $mem_ptr,$newval\t# " | |
| 8339 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" | |
| 8340 "sete $res\n\t" | |
| 8341 "movzbl $res, $res" %} | |
| 8342 opcode(0x0F, 0xB1); | |
| 8343 ins_encode(lock_prefix, | |
| 8344 REX_reg_mem_wide(newval, mem_ptr), | |
| 8345 OpcP, OpcS, | |
| 8346 reg_mem(newval, mem_ptr), | |
| 8347 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete | |
| 8348 REX_reg_breg(res, res), // movzbl | |
| 8349 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); | |
| 8350 ins_pipe( pipe_cmpxchg ); | |
| 8351 %} | |
| 8352 | |
| 8353 instruct compareAndSwapI(rRegI res, | |
| 8354 memory mem_ptr, | |
| 8355 rax_RegI oldval, rRegI newval, | |
| 8356 rFlagsReg cr) | |
| 8357 %{ | |
| 8358 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); | |
| 8359 effect(KILL cr, KILL oldval); | |
| 8360 | |
| 8361 format %{ "cmpxchgl $mem_ptr,$newval\t# " | |
| 8362 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" | |
| 8363 "sete $res\n\t" | |
| 8364 "movzbl $res, $res" %} | |
| 8365 opcode(0x0F, 0xB1); | |
| 8366 ins_encode(lock_prefix, | |
| 8367 REX_reg_mem(newval, mem_ptr), | |
| 8368 OpcP, OpcS, | |
| 8369 reg_mem(newval, mem_ptr), | |
| 8370 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete | |
| 8371 REX_reg_breg(res, res), // movzbl | |
| 8372 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); | |
| 8373 ins_pipe( pipe_cmpxchg ); | |
| 8374 %} | |
| 8375 | |
| 8376 | |
|
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8377 instruct compareAndSwapN(rRegI res, |
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8378 memory mem_ptr, |
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8379 rax_RegN oldval, rRegN newval, |
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8380 rFlagsReg cr) %{ |
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8381 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); |
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8382 effect(KILL cr, KILL oldval); |
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8383 |
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8384 format %{ "cmpxchgl $mem_ptr,$newval\t# " |
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8385 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" |
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8386 "sete $res\n\t" |
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8387 "movzbl $res, $res" %} |
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8388 opcode(0x0F, 0xB1); |
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8389 ins_encode(lock_prefix, |
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8390 REX_reg_mem(newval, mem_ptr), |
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8391 OpcP, OpcS, |
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8392 reg_mem(newval, mem_ptr), |
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8393 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete |
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8394 REX_reg_breg(res, res), // movzbl |
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8395 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); |
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8396 ins_pipe( pipe_cmpxchg ); |
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8397 %} |
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8398 |
| 0 | 8399 //----------Subtraction Instructions------------------------------------------- |
| 8400 | |
| 8401 // Integer Subtraction Instructions | |
| 8402 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 8403 %{ | |
| 8404 match(Set dst (SubI dst src)); | |
| 8405 effect(KILL cr); | |
| 8406 | |
| 8407 format %{ "subl $dst, $src\t# int" %} | |
| 8408 opcode(0x2B); | |
| 8409 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 8410 ins_pipe(ialu_reg_reg); | |
| 8411 %} | |
| 8412 | |
| 8413 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 8414 %{ | |
| 8415 match(Set dst (SubI dst src)); | |
| 8416 effect(KILL cr); | |
| 8417 | |
| 8418 format %{ "subl $dst, $src\t# int" %} | |
| 8419 opcode(0x81, 0x05); /* Opcode 81 /5 */ | |
| 8420 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 8421 ins_pipe(ialu_reg); | |
| 8422 %} | |
| 8423 | |
| 8424 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 8425 %{ | |
| 8426 match(Set dst (SubI dst (LoadI src))); | |
| 8427 effect(KILL cr); | |
| 8428 | |
| 8429 ins_cost(125); | |
| 8430 format %{ "subl $dst, $src\t# int" %} | |
| 8431 opcode(0x2B); | |
| 8432 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 8433 ins_pipe(ialu_reg_mem); | |
| 8434 %} | |
| 8435 | |
| 8436 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 8437 %{ | |
| 8438 match(Set dst (StoreI dst (SubI (LoadI dst) src))); | |
| 8439 effect(KILL cr); | |
| 8440 | |
| 8441 ins_cost(150); | |
| 8442 format %{ "subl $dst, $src\t# int" %} | |
| 8443 opcode(0x29); /* Opcode 29 /r */ | |
| 8444 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 8445 ins_pipe(ialu_mem_reg); | |
| 8446 %} | |
| 8447 | |
| 8448 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 8449 %{ | |
| 8450 match(Set dst (StoreI dst (SubI (LoadI dst) src))); | |
| 8451 effect(KILL cr); | |
| 8452 | |
| 8453 ins_cost(125); // XXX | |
| 8454 format %{ "subl $dst, $src\t# int" %} | |
| 8455 opcode(0x81); /* Opcode 81 /5 id */ | |
| 8456 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src)); | |
| 8457 ins_pipe(ialu_mem_imm); | |
| 8458 %} | |
| 8459 | |
| 8460 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 8461 %{ | |
| 8462 match(Set dst (SubL dst src)); | |
| 8463 effect(KILL cr); | |
| 8464 | |
| 8465 format %{ "subq $dst, $src\t# long" %} | |
| 8466 opcode(0x2B); | |
| 8467 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 8468 ins_pipe(ialu_reg_reg); | |
| 8469 %} | |
| 8470 | |
| 8471 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr) | |
| 8472 %{ | |
| 8473 match(Set dst (SubL dst src)); | |
| 8474 effect(KILL cr); | |
| 8475 | |
| 8476 format %{ "subq $dst, $src\t# long" %} | |
| 8477 opcode(0x81, 0x05); /* Opcode 81 /5 */ | |
| 8478 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 8479 ins_pipe(ialu_reg); | |
| 8480 %} | |
| 8481 | |
| 8482 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 8483 %{ | |
| 8484 match(Set dst (SubL dst (LoadL src))); | |
| 8485 effect(KILL cr); | |
| 8486 | |
| 8487 ins_cost(125); | |
| 8488 format %{ "subq $dst, $src\t# long" %} | |
| 8489 opcode(0x2B); | |
| 8490 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 8491 ins_pipe(ialu_reg_mem); | |
| 8492 %} | |
| 8493 | |
| 8494 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 8495 %{ | |
| 8496 match(Set dst (StoreL dst (SubL (LoadL dst) src))); | |
| 8497 effect(KILL cr); | |
| 8498 | |
| 8499 ins_cost(150); | |
| 8500 format %{ "subq $dst, $src\t# long" %} | |
| 8501 opcode(0x29); /* Opcode 29 /r */ | |
| 8502 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 8503 ins_pipe(ialu_mem_reg); | |
| 8504 %} | |
| 8505 | |
| 8506 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 8507 %{ | |
| 8508 match(Set dst (StoreL dst (SubL (LoadL dst) src))); | |
| 8509 effect(KILL cr); | |
| 8510 | |
| 8511 ins_cost(125); // XXX | |
| 8512 format %{ "subq $dst, $src\t# long" %} | |
| 8513 opcode(0x81); /* Opcode 81 /5 id */ | |
| 8514 ins_encode(REX_mem_wide(dst), | |
| 8515 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src)); | |
| 8516 ins_pipe(ialu_mem_imm); | |
| 8517 %} | |
| 8518 | |
| 8519 // Subtract from a pointer | |
| 8520 // XXX hmpf??? | |
| 8521 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr) | |
| 8522 %{ | |
| 8523 match(Set dst (AddP dst (SubI zero src))); | |
| 8524 effect(KILL cr); | |
| 8525 | |
| 8526 format %{ "subq $dst, $src\t# ptr - int" %} | |
| 8527 opcode(0x2B); | |
| 8528 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 8529 ins_pipe(ialu_reg_reg); | |
| 8530 %} | |
| 8531 | |
| 8532 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr) | |
| 8533 %{ | |
| 8534 match(Set dst (SubI zero dst)); | |
| 8535 effect(KILL cr); | |
| 8536 | |
| 8537 format %{ "negl $dst\t# int" %} | |
| 8538 opcode(0xF7, 0x03); // Opcode F7 /3 | |
| 8539 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8540 ins_pipe(ialu_reg); | |
| 8541 %} | |
| 8542 | |
| 8543 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr) | |
| 8544 %{ | |
| 8545 match(Set dst (StoreI dst (SubI zero (LoadI dst)))); | |
| 8546 effect(KILL cr); | |
| 8547 | |
| 8548 format %{ "negl $dst\t# int" %} | |
| 8549 opcode(0xF7, 0x03); // Opcode F7 /3 | |
| 8550 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8551 ins_pipe(ialu_reg); | |
| 8552 %} | |
| 8553 | |
| 8554 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr) | |
| 8555 %{ | |
| 8556 match(Set dst (SubL zero dst)); | |
| 8557 effect(KILL cr); | |
| 8558 | |
| 8559 format %{ "negq $dst\t# long" %} | |
| 8560 opcode(0xF7, 0x03); // Opcode F7 /3 | |
| 8561 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8562 ins_pipe(ialu_reg); | |
| 8563 %} | |
| 8564 | |
| 8565 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr) | |
| 8566 %{ | |
| 8567 match(Set dst (StoreL dst (SubL zero (LoadL dst)))); | |
| 8568 effect(KILL cr); | |
| 8569 | |
| 8570 format %{ "negq $dst\t# long" %} | |
| 8571 opcode(0xF7, 0x03); // Opcode F7 /3 | |
| 8572 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8573 ins_pipe(ialu_reg); | |
| 8574 %} | |
| 8575 | |
| 8576 | |
| 8577 //----------Multiplication/Division Instructions------------------------------- | |
| 8578 // Integer Multiplication Instructions | |
| 8579 // Multiply Register | |
| 8580 | |
| 8581 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 8582 %{ | |
| 8583 match(Set dst (MulI dst src)); | |
| 8584 effect(KILL cr); | |
| 8585 | |
| 8586 ins_cost(300); | |
| 8587 format %{ "imull $dst, $src\t# int" %} | |
| 8588 opcode(0x0F, 0xAF); | |
| 8589 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 8590 ins_pipe(ialu_reg_reg_alu0); | |
| 8591 %} | |
| 8592 | |
| 8593 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr) | |
| 8594 %{ | |
| 8595 match(Set dst (MulI src imm)); | |
| 8596 effect(KILL cr); | |
| 8597 | |
| 8598 ins_cost(300); | |
| 8599 format %{ "imull $dst, $src, $imm\t# int" %} | |
| 8600 opcode(0x69); /* 69 /r id */ | |
| 8601 ins_encode(REX_reg_reg(dst, src), | |
| 8602 OpcSE(imm), reg_reg(dst, src), Con8or32(imm)); | |
| 8603 ins_pipe(ialu_reg_reg_alu0); | |
| 8604 %} | |
| 8605 | |
| 8606 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 8607 %{ | |
| 8608 match(Set dst (MulI dst (LoadI src))); | |
| 8609 effect(KILL cr); | |
| 8610 | |
| 8611 ins_cost(350); | |
| 8612 format %{ "imull $dst, $src\t# int" %} | |
| 8613 opcode(0x0F, 0xAF); | |
| 8614 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src)); | |
| 8615 ins_pipe(ialu_reg_mem_alu0); | |
| 8616 %} | |
| 8617 | |
| 8618 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr) | |
| 8619 %{ | |
| 8620 match(Set dst (MulI (LoadI src) imm)); | |
| 8621 effect(KILL cr); | |
| 8622 | |
| 8623 ins_cost(300); | |
| 8624 format %{ "imull $dst, $src, $imm\t# int" %} | |
| 8625 opcode(0x69); /* 69 /r id */ | |
| 8626 ins_encode(REX_reg_mem(dst, src), | |
| 8627 OpcSE(imm), reg_mem(dst, src), Con8or32(imm)); | |
| 8628 ins_pipe(ialu_reg_mem_alu0); | |
| 8629 %} | |
| 8630 | |
| 8631 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 8632 %{ | |
| 8633 match(Set dst (MulL dst src)); | |
| 8634 effect(KILL cr); | |
| 8635 | |
| 8636 ins_cost(300); | |
| 8637 format %{ "imulq $dst, $src\t# long" %} | |
| 8638 opcode(0x0F, 0xAF); | |
| 8639 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 8640 ins_pipe(ialu_reg_reg_alu0); | |
| 8641 %} | |
| 8642 | |
| 8643 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr) | |
| 8644 %{ | |
| 8645 match(Set dst (MulL src imm)); | |
| 8646 effect(KILL cr); | |
| 8647 | |
| 8648 ins_cost(300); | |
| 8649 format %{ "imulq $dst, $src, $imm\t# long" %} | |
| 8650 opcode(0x69); /* 69 /r id */ | |
| 8651 ins_encode(REX_reg_reg_wide(dst, src), | |
| 8652 OpcSE(imm), reg_reg(dst, src), Con8or32(imm)); | |
| 8653 ins_pipe(ialu_reg_reg_alu0); | |
| 8654 %} | |
| 8655 | |
| 8656 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 8657 %{ | |
| 8658 match(Set dst (MulL dst (LoadL src))); | |
| 8659 effect(KILL cr); | |
| 8660 | |
| 8661 ins_cost(350); | |
| 8662 format %{ "imulq $dst, $src\t# long" %} | |
| 8663 opcode(0x0F, 0xAF); | |
| 8664 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src)); | |
| 8665 ins_pipe(ialu_reg_mem_alu0); | |
| 8666 %} | |
| 8667 | |
| 8668 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr) | |
| 8669 %{ | |
| 8670 match(Set dst (MulL (LoadL src) imm)); | |
| 8671 effect(KILL cr); | |
| 8672 | |
| 8673 ins_cost(300); | |
| 8674 format %{ "imulq $dst, $src, $imm\t# long" %} | |
| 8675 opcode(0x69); /* 69 /r id */ | |
| 8676 ins_encode(REX_reg_mem_wide(dst, src), | |
| 8677 OpcSE(imm), reg_mem(dst, src), Con8or32(imm)); | |
| 8678 ins_pipe(ialu_reg_mem_alu0); | |
| 8679 %} | |
| 8680 | |
| 145 | 8681 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr) |
| 8682 %{ | |
| 8683 match(Set dst (MulHiL src rax)); | |
| 8684 effect(USE_KILL rax, KILL cr); | |
| 8685 | |
| 8686 ins_cost(300); | |
| 8687 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %} | |
| 8688 opcode(0xF7, 0x5); /* Opcode F7 /5 */ | |
| 8689 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src)); | |
| 8690 ins_pipe(ialu_reg_reg_alu0); | |
| 8691 %} | |
| 8692 | |
| 0 | 8693 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div, |
| 8694 rFlagsReg cr) | |
| 8695 %{ | |
| 8696 match(Set rax (DivI rax div)); | |
| 8697 effect(KILL rdx, KILL cr); | |
| 8698 | |
| 8699 ins_cost(30*100+10*100); // XXX | |
| 8700 format %{ "cmpl rax, 0x80000000\t# idiv\n\t" | |
| 8701 "jne,s normal\n\t" | |
| 8702 "xorl rdx, rdx\n\t" | |
| 8703 "cmpl $div, -1\n\t" | |
| 8704 "je,s done\n" | |
| 8705 "normal: cdql\n\t" | |
| 8706 "idivl $div\n" | |
| 8707 "done:" %} | |
| 8708 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8709 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div)); | |
| 8710 ins_pipe(ialu_reg_reg_alu0); | |
| 8711 %} | |
| 8712 | |
| 8713 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div, | |
| 8714 rFlagsReg cr) | |
| 8715 %{ | |
| 8716 match(Set rax (DivL rax div)); | |
| 8717 effect(KILL rdx, KILL cr); | |
| 8718 | |
| 8719 ins_cost(30*100+10*100); // XXX | |
| 8720 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t" | |
| 8721 "cmpq rax, rdx\n\t" | |
| 8722 "jne,s normal\n\t" | |
| 8723 "xorl rdx, rdx\n\t" | |
| 8724 "cmpq $div, -1\n\t" | |
| 8725 "je,s done\n" | |
| 8726 "normal: cdqq\n\t" | |
| 8727 "idivq $div\n" | |
| 8728 "done:" %} | |
| 8729 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8730 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div)); | |
| 8731 ins_pipe(ialu_reg_reg_alu0); | |
| 8732 %} | |
| 8733 | |
| 8734 // Integer DIVMOD with Register, both quotient and mod results | |
| 8735 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div, | |
| 8736 rFlagsReg cr) | |
| 8737 %{ | |
| 8738 match(DivModI rax div); | |
| 8739 effect(KILL cr); | |
| 8740 | |
| 8741 ins_cost(30*100+10*100); // XXX | |
| 8742 format %{ "cmpl rax, 0x80000000\t# idiv\n\t" | |
| 8743 "jne,s normal\n\t" | |
| 8744 "xorl rdx, rdx\n\t" | |
| 8745 "cmpl $div, -1\n\t" | |
| 8746 "je,s done\n" | |
| 8747 "normal: cdql\n\t" | |
| 8748 "idivl $div\n" | |
| 8749 "done:" %} | |
| 8750 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8751 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div)); | |
| 8752 ins_pipe(pipe_slow); | |
| 8753 %} | |
| 8754 | |
| 8755 // Long DIVMOD with Register, both quotient and mod results | |
| 8756 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div, | |
| 8757 rFlagsReg cr) | |
| 8758 %{ | |
| 8759 match(DivModL rax div); | |
| 8760 effect(KILL cr); | |
| 8761 | |
| 8762 ins_cost(30*100+10*100); // XXX | |
| 8763 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t" | |
| 8764 "cmpq rax, rdx\n\t" | |
| 8765 "jne,s normal\n\t" | |
| 8766 "xorl rdx, rdx\n\t" | |
| 8767 "cmpq $div, -1\n\t" | |
| 8768 "je,s done\n" | |
| 8769 "normal: cdqq\n\t" | |
| 8770 "idivq $div\n" | |
| 8771 "done:" %} | |
| 8772 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8773 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div)); | |
| 8774 ins_pipe(pipe_slow); | |
| 8775 %} | |
| 8776 | |
| 8777 //----------- DivL-By-Constant-Expansions-------------------------------------- | |
| 8778 // DivI cases are handled by the compiler | |
| 8779 | |
| 605 | 8780 // Magic constant, reciprocal of 10 |
| 0 | 8781 instruct loadConL_0x6666666666666667(rRegL dst) |
| 8782 %{ | |
| 8783 effect(DEF dst); | |
| 8784 | |
| 8785 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %} | |
| 8786 ins_encode(load_immL(dst, 0x6666666666666667)); | |
| 8787 ins_pipe(ialu_reg); | |
| 8788 %} | |
| 8789 | |
| 8790 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr) | |
| 8791 %{ | |
| 8792 effect(DEF dst, USE src, USE_KILL rax, KILL cr); | |
| 8793 | |
| 8794 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %} | |
| 8795 opcode(0xF7, 0x5); /* Opcode F7 /5 */ | |
| 8796 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src)); | |
| 8797 ins_pipe(ialu_reg_reg_alu0); | |
| 8798 %} | |
| 8799 | |
| 8800 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr) | |
| 8801 %{ | |
| 8802 effect(USE_DEF dst, KILL cr); | |
| 8803 | |
| 8804 format %{ "sarq $dst, #63\t# Used in div-by-10" %} | |
| 8805 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8806 ins_encode(reg_opc_imm_wide(dst, 0x3F)); | |
| 8807 ins_pipe(ialu_reg); | |
| 8808 %} | |
| 8809 | |
| 8810 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr) | |
| 8811 %{ | |
| 8812 effect(USE_DEF dst, KILL cr); | |
| 8813 | |
| 8814 format %{ "sarq $dst, #2\t# Used in div-by-10" %} | |
| 8815 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8816 ins_encode(reg_opc_imm_wide(dst, 0x2)); | |
| 8817 ins_pipe(ialu_reg); | |
| 8818 %} | |
| 8819 | |
| 8820 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div) | |
| 8821 %{ | |
| 8822 match(Set dst (DivL src div)); | |
| 8823 | |
| 8824 ins_cost((5+8)*100); | |
| 8825 expand %{ | |
| 8826 rax_RegL rax; // Killed temp | |
| 8827 rFlagsReg cr; // Killed | |
| 8828 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667 | |
| 8829 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src | |
| 8830 sarL_rReg_63(src, cr); // sarq src, 63 | |
| 8831 sarL_rReg_2(dst, cr); // sarq rdx, 2 | |
| 8832 subL_rReg(dst, src, cr); // subl rdx, src | |
| 8833 %} | |
| 8834 %} | |
| 8835 | |
| 8836 //----------------------------------------------------------------------------- | |
| 8837 | |
| 8838 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div, | |
| 8839 rFlagsReg cr) | |
| 8840 %{ | |
| 8841 match(Set rdx (ModI rax div)); | |
| 8842 effect(KILL rax, KILL cr); | |
| 8843 | |
| 8844 ins_cost(300); // XXX | |
| 8845 format %{ "cmpl rax, 0x80000000\t# irem\n\t" | |
| 8846 "jne,s normal\n\t" | |
| 8847 "xorl rdx, rdx\n\t" | |
| 8848 "cmpl $div, -1\n\t" | |
| 8849 "je,s done\n" | |
| 8850 "normal: cdql\n\t" | |
| 8851 "idivl $div\n" | |
| 8852 "done:" %} | |
| 8853 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8854 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div)); | |
| 8855 ins_pipe(ialu_reg_reg_alu0); | |
| 8856 %} | |
| 8857 | |
| 8858 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div, | |
| 8859 rFlagsReg cr) | |
| 8860 %{ | |
| 8861 match(Set rdx (ModL rax div)); | |
| 8862 effect(KILL rax, KILL cr); | |
| 8863 | |
| 8864 ins_cost(300); // XXX | |
| 8865 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t" | |
| 8866 "cmpq rax, rdx\n\t" | |
| 8867 "jne,s normal\n\t" | |
| 8868 "xorl rdx, rdx\n\t" | |
| 8869 "cmpq $div, -1\n\t" | |
| 8870 "je,s done\n" | |
| 8871 "normal: cdqq\n\t" | |
| 8872 "idivq $div\n" | |
| 8873 "done:" %} | |
| 8874 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8875 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div)); | |
| 8876 ins_pipe(ialu_reg_reg_alu0); | |
| 8877 %} | |
| 8878 | |
| 8879 // Integer Shift Instructions | |
| 8880 // Shift Left by one | |
| 8881 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr) | |
| 8882 %{ | |
| 8883 match(Set dst (LShiftI dst shift)); | |
| 8884 effect(KILL cr); | |
| 8885 | |
| 8886 format %{ "sall $dst, $shift" %} | |
| 8887 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 8888 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8889 ins_pipe(ialu_reg); | |
| 8890 %} | |
| 8891 | |
| 8892 // Shift Left by one | |
| 8893 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 8894 %{ | |
| 8895 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift))); | |
| 8896 effect(KILL cr); | |
| 8897 | |
| 8898 format %{ "sall $dst, $shift\t" %} | |
| 8899 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 8900 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8901 ins_pipe(ialu_mem_imm); | |
| 8902 %} | |
| 8903 | |
| 8904 // Shift Left by 8-bit immediate | |
| 8905 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) | |
| 8906 %{ | |
| 8907 match(Set dst (LShiftI dst shift)); | |
| 8908 effect(KILL cr); | |
| 8909 | |
| 8910 format %{ "sall $dst, $shift" %} | |
| 8911 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 8912 ins_encode(reg_opc_imm(dst, shift)); | |
| 8913 ins_pipe(ialu_reg); | |
| 8914 %} | |
| 8915 | |
| 8916 // Shift Left by 8-bit immediate | |
| 8917 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 8918 %{ | |
| 8919 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift))); | |
| 8920 effect(KILL cr); | |
| 8921 | |
| 8922 format %{ "sall $dst, $shift" %} | |
| 8923 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 8924 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 8925 ins_pipe(ialu_mem_imm); | |
| 8926 %} | |
| 8927 | |
| 8928 // Shift Left by variable | |
| 8929 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 8930 %{ | |
| 8931 match(Set dst (LShiftI dst shift)); | |
| 8932 effect(KILL cr); | |
| 8933 | |
| 8934 format %{ "sall $dst, $shift" %} | |
| 8935 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 8936 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8937 ins_pipe(ialu_reg_reg); | |
| 8938 %} | |
| 8939 | |
| 8940 // Shift Left by variable | |
| 8941 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 8942 %{ | |
| 8943 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift))); | |
| 8944 effect(KILL cr); | |
| 8945 | |
| 8946 format %{ "sall $dst, $shift" %} | |
| 8947 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 8948 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8949 ins_pipe(ialu_mem_reg); | |
| 8950 %} | |
| 8951 | |
| 8952 // Arithmetic shift right by one | |
| 8953 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr) | |
| 8954 %{ | |
| 8955 match(Set dst (RShiftI dst shift)); | |
| 8956 effect(KILL cr); | |
| 8957 | |
| 8958 format %{ "sarl $dst, $shift" %} | |
| 8959 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 8960 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8961 ins_pipe(ialu_reg); | |
| 8962 %} | |
| 8963 | |
| 8964 // Arithmetic shift right by one | |
| 8965 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 8966 %{ | |
| 8967 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 8968 effect(KILL cr); | |
| 8969 | |
| 8970 format %{ "sarl $dst, $shift" %} | |
| 8971 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 8972 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8973 ins_pipe(ialu_mem_imm); | |
| 8974 %} | |
| 8975 | |
| 8976 // Arithmetic Shift Right by 8-bit immediate | |
| 8977 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) | |
| 8978 %{ | |
| 8979 match(Set dst (RShiftI dst shift)); | |
| 8980 effect(KILL cr); | |
| 8981 | |
| 8982 format %{ "sarl $dst, $shift" %} | |
| 8983 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8984 ins_encode(reg_opc_imm(dst, shift)); | |
| 8985 ins_pipe(ialu_mem_imm); | |
| 8986 %} | |
| 8987 | |
| 8988 // Arithmetic Shift Right by 8-bit immediate | |
| 8989 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 8990 %{ | |
| 8991 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 8992 effect(KILL cr); | |
| 8993 | |
| 8994 format %{ "sarl $dst, $shift" %} | |
| 8995 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8996 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 8997 ins_pipe(ialu_mem_imm); | |
| 8998 %} | |
| 8999 | |
| 9000 // Arithmetic Shift Right by variable | |
| 9001 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 9002 %{ | |
| 9003 match(Set dst (RShiftI dst shift)); | |
| 9004 effect(KILL cr); | |
| 9005 | |
| 9006 format %{ "sarl $dst, $shift" %} | |
| 9007 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 9008 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 9009 ins_pipe(ialu_reg_reg); | |
| 9010 %} | |
| 9011 | |
| 9012 // Arithmetic Shift Right by variable | |
| 9013 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 9014 %{ | |
| 9015 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 9016 effect(KILL cr); | |
| 9017 | |
| 9018 format %{ "sarl $dst, $shift" %} | |
| 9019 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 9020 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 9021 ins_pipe(ialu_mem_reg); | |
| 9022 %} | |
| 9023 | |
| 9024 // Logical shift right by one | |
| 9025 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr) | |
| 9026 %{ | |
| 9027 match(Set dst (URShiftI dst shift)); | |
| 9028 effect(KILL cr); | |
| 9029 | |
| 9030 format %{ "shrl $dst, $shift" %} | |
| 9031 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 9032 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 9033 ins_pipe(ialu_reg); | |
| 9034 %} | |
| 9035 | |
| 9036 // Logical shift right by one | |
| 9037 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 9038 %{ | |
| 9039 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift))); | |
| 9040 effect(KILL cr); | |
| 9041 | |
| 9042 format %{ "shrl $dst, $shift" %} | |
| 9043 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 9044 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 9045 ins_pipe(ialu_mem_imm); | |
| 9046 %} | |
| 9047 | |
| 9048 // Logical Shift Right by 8-bit immediate | |
| 9049 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) | |
| 9050 %{ | |
| 9051 match(Set dst (URShiftI dst shift)); | |
| 9052 effect(KILL cr); | |
| 9053 | |
| 9054 format %{ "shrl $dst, $shift" %} | |
| 9055 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 9056 ins_encode(reg_opc_imm(dst, shift)); | |
| 9057 ins_pipe(ialu_reg); | |
| 9058 %} | |
| 9059 | |
| 9060 // Logical Shift Right by 8-bit immediate | |
| 9061 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 9062 %{ | |
| 9063 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift))); | |
| 9064 effect(KILL cr); | |
| 9065 | |
| 9066 format %{ "shrl $dst, $shift" %} | |
| 9067 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 9068 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 9069 ins_pipe(ialu_mem_imm); | |
| 9070 %} | |
| 9071 | |
| 9072 // Logical Shift Right by variable | |
| 9073 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 9074 %{ | |
| 9075 match(Set dst (URShiftI dst shift)); | |
| 9076 effect(KILL cr); | |
| 9077 | |
| 9078 format %{ "shrl $dst, $shift" %} | |
| 9079 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 9080 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 9081 ins_pipe(ialu_reg_reg); | |
| 9082 %} | |
| 9083 | |
| 9084 // Logical Shift Right by variable | |
| 9085 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 9086 %{ | |
| 9087 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift))); | |
| 9088 effect(KILL cr); | |
| 9089 | |
| 9090 format %{ "shrl $dst, $shift" %} | |
| 9091 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 9092 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 9093 ins_pipe(ialu_mem_reg); | |
| 9094 %} | |
| 9095 | |
| 9096 // Long Shift Instructions | |
| 9097 // Shift Left by one | |
| 9098 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr) | |
| 9099 %{ | |
| 9100 match(Set dst (LShiftL dst shift)); | |
| 9101 effect(KILL cr); | |
| 9102 | |
| 9103 format %{ "salq $dst, $shift" %} | |
| 9104 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 9105 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 9106 ins_pipe(ialu_reg); | |
| 9107 %} | |
| 9108 | |
| 9109 // Shift Left by one | |
| 9110 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 9111 %{ | |
| 9112 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift))); | |
| 9113 effect(KILL cr); | |
| 9114 | |
| 9115 format %{ "salq $dst, $shift" %} | |
| 9116 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 9117 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 9118 ins_pipe(ialu_mem_imm); | |
| 9119 %} | |
| 9120 | |
| 9121 // Shift Left by 8-bit immediate | |
| 9122 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr) | |
| 9123 %{ | |
| 9124 match(Set dst (LShiftL dst shift)); | |
| 9125 effect(KILL cr); | |
| 9126 | |
| 9127 format %{ "salq $dst, $shift" %} | |
| 9128 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 9129 ins_encode(reg_opc_imm_wide(dst, shift)); | |
| 9130 ins_pipe(ialu_reg); | |
| 9131 %} | |
| 9132 | |
| 9133 // Shift Left by 8-bit immediate | |
| 9134 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 9135 %{ | |
| 9136 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift))); | |
| 9137 effect(KILL cr); | |
| 9138 | |
| 9139 format %{ "salq $dst, $shift" %} | |
| 9140 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 9141 ins_encode(REX_mem_wide(dst), OpcP, | |
| 9142 RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 9143 ins_pipe(ialu_mem_imm); | |
| 9144 %} | |
| 9145 | |
| 9146 // Shift Left by variable | |
| 9147 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 9148 %{ | |
| 9149 match(Set dst (LShiftL dst shift)); | |
| 9150 effect(KILL cr); | |
| 9151 | |
| 9152 format %{ "salq $dst, $shift" %} | |
| 9153 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 9154 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 9155 ins_pipe(ialu_reg_reg); | |
| 9156 %} | |
| 9157 | |
| 9158 // Shift Left by variable | |
| 9159 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 9160 %{ | |
| 9161 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift))); | |
| 9162 effect(KILL cr); | |
| 9163 | |
| 9164 format %{ "salq $dst, $shift" %} | |
| 9165 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 9166 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 9167 ins_pipe(ialu_mem_reg); | |
| 9168 %} | |
| 9169 | |
| 9170 // Arithmetic shift right by one | |
| 9171 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr) | |
| 9172 %{ | |
| 9173 match(Set dst (RShiftL dst shift)); | |
| 9174 effect(KILL cr); | |
| 9175 | |
| 9176 format %{ "sarq $dst, $shift" %} | |
| 9177 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 9178 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 9179 ins_pipe(ialu_reg); | |
| 9180 %} | |
| 9181 | |
| 9182 // Arithmetic shift right by one | |
| 9183 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 9184 %{ | |
| 9185 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift))); | |
| 9186 effect(KILL cr); | |
| 9187 | |
| 9188 format %{ "sarq $dst, $shift" %} | |
| 9189 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 9190 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 9191 ins_pipe(ialu_mem_imm); | |
| 9192 %} | |
| 9193 | |
| 9194 // Arithmetic Shift Right by 8-bit immediate | |
| 9195 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr) | |
| 9196 %{ | |
| 9197 match(Set dst (RShiftL dst shift)); | |
| 9198 effect(KILL cr); | |
| 9199 | |
| 9200 format %{ "sarq $dst, $shift" %} | |
| 9201 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 9202 ins_encode(reg_opc_imm_wide(dst, shift)); | |
| 9203 ins_pipe(ialu_mem_imm); | |
| 9204 %} | |
| 9205 | |
| 9206 // Arithmetic Shift Right by 8-bit immediate | |
| 9207 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 9208 %{ | |
| 9209 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift))); | |
| 9210 effect(KILL cr); | |
| 9211 | |
| 9212 format %{ "sarq $dst, $shift" %} | |
| 9213 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 9214 ins_encode(REX_mem_wide(dst), OpcP, | |
| 9215 RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 9216 ins_pipe(ialu_mem_imm); | |
| 9217 %} | |
| 9218 | |
| 9219 // Arithmetic Shift Right by variable | |
| 9220 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 9221 %{ | |
| 9222 match(Set dst (RShiftL dst shift)); | |
| 9223 effect(KILL cr); | |
| 9224 | |
| 9225 format %{ "sarq $dst, $shift" %} | |
| 9226 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 9227 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 9228 ins_pipe(ialu_reg_reg); | |
| 9229 %} | |
| 9230 | |
| 9231 // Arithmetic Shift Right by variable | |
| 9232 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 9233 %{ | |
| 9234 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift))); | |
| 9235 effect(KILL cr); | |
| 9236 | |
| 9237 format %{ "sarq $dst, $shift" %} | |
| 9238 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 9239 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 9240 ins_pipe(ialu_mem_reg); | |
| 9241 %} | |
| 9242 | |
| 9243 // Logical shift right by one | |
| 9244 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr) | |
| 9245 %{ | |
| 9246 match(Set dst (URShiftL dst shift)); | |
| 9247 effect(KILL cr); | |
| 9248 | |
| 9249 format %{ "shrq $dst, $shift" %} | |
| 9250 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 9251 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst )); | |
| 9252 ins_pipe(ialu_reg); | |
| 9253 %} | |
| 9254 | |
| 9255 // Logical shift right by one | |
| 9256 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 9257 %{ | |
| 9258 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift))); | |
| 9259 effect(KILL cr); | |
| 9260 | |
| 9261 format %{ "shrq $dst, $shift" %} | |
| 9262 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 9263 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 9264 ins_pipe(ialu_mem_imm); | |
| 9265 %} | |
| 9266 | |
| 9267 // Logical Shift Right by 8-bit immediate | |
| 9268 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr) | |
| 9269 %{ | |
| 9270 match(Set dst (URShiftL dst shift)); | |
| 9271 effect(KILL cr); | |
| 9272 | |
| 9273 format %{ "shrq $dst, $shift" %} | |
| 9274 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 9275 ins_encode(reg_opc_imm_wide(dst, shift)); | |
| 9276 ins_pipe(ialu_reg); | |
| 9277 %} | |
| 9278 | |
|
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|
9279 |
| 0 | 9280 // Logical Shift Right by 8-bit immediate |
| 9281 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 9282 %{ | |
| 9283 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift))); | |
| 9284 effect(KILL cr); | |
| 9285 | |
| 9286 format %{ "shrq $dst, $shift" %} | |
| 9287 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 9288 ins_encode(REX_mem_wide(dst), OpcP, | |
| 9289 RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 9290 ins_pipe(ialu_mem_imm); | |
| 9291 %} | |
| 9292 | |
| 9293 // Logical Shift Right by variable | |
| 9294 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 9295 %{ | |
| 9296 match(Set dst (URShiftL dst shift)); | |
| 9297 effect(KILL cr); | |
| 9298 | |
| 9299 format %{ "shrq $dst, $shift" %} | |
| 9300 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 9301 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 9302 ins_pipe(ialu_reg_reg); | |
| 9303 %} | |
| 9304 | |
| 9305 // Logical Shift Right by variable | |
| 9306 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 9307 %{ | |
| 9308 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift))); | |
| 9309 effect(KILL cr); | |
| 9310 | |
| 9311 format %{ "shrq $dst, $shift" %} | |
| 9312 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 9313 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 9314 ins_pipe(ialu_mem_reg); | |
| 9315 %} | |
| 9316 | |
| 9317 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24. | |
| 9318 // This idiom is used by the compiler for the i2b bytecode. | |
| 9319 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour) | |
| 9320 %{ | |
| 9321 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour)); | |
| 9322 | |
| 9323 format %{ "movsbl $dst, $src\t# i2b" %} | |
| 9324 opcode(0x0F, 0xBE); | |
| 9325 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 9326 ins_pipe(ialu_reg_reg); | |
| 9327 %} | |
| 9328 | |
| 9329 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16. | |
| 9330 // This idiom is used by the compiler the i2s bytecode. | |
| 9331 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen) | |
| 9332 %{ | |
| 9333 match(Set dst (RShiftI (LShiftI src sixteen) sixteen)); | |
| 9334 | |
| 9335 format %{ "movswl $dst, $src\t# i2s" %} | |
| 9336 opcode(0x0F, 0xBF); | |
| 9337 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 9338 ins_pipe(ialu_reg_reg); | |
| 9339 %} | |
| 9340 | |
| 9341 // ROL/ROR instructions | |
| 9342 | |
| 9343 // ROL expand | |
| 9344 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{ | |
| 9345 effect(KILL cr, USE_DEF dst); | |
| 9346 | |
| 9347 format %{ "roll $dst" %} | |
| 9348 opcode(0xD1, 0x0); /* Opcode D1 /0 */ | |
| 9349 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 9350 ins_pipe(ialu_reg); | |
| 9351 %} | |
| 9352 | |
| 9353 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{ | |
| 9354 effect(USE_DEF dst, USE shift, KILL cr); | |
| 9355 | |
| 9356 format %{ "roll $dst, $shift" %} | |
| 9357 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */ | |
| 9358 ins_encode( reg_opc_imm(dst, shift) ); | |
| 9359 ins_pipe(ialu_reg); | |
| 9360 %} | |
| 9361 | |
| 9362 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 9363 %{ | |
| 9364 effect(USE_DEF dst, USE shift, KILL cr); | |
| 9365 | |
| 9366 format %{ "roll $dst, $shift" %} | |
| 9367 opcode(0xD3, 0x0); /* Opcode D3 /0 */ | |
| 9368 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 9369 ins_pipe(ialu_reg_reg); | |
| 9370 %} | |
| 9371 // end of ROL expand | |
| 9372 | |
| 9373 // Rotate Left by one | |
| 9374 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr) | |
| 9375 %{ | |
| 9376 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift))); | |
| 9377 | |
| 9378 expand %{ | |
| 9379 rolI_rReg_imm1(dst, cr); | |
| 9380 %} | |
| 9381 %} | |
| 9382 | |
| 9383 // Rotate Left by 8-bit immediate | |
| 9384 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr) | |
| 9385 %{ | |
| 9386 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); | |
| 9387 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift))); | |
| 9388 | |
| 9389 expand %{ | |
| 9390 rolI_rReg_imm8(dst, lshift, cr); | |
| 9391 %} | |
| 9392 %} | |
| 9393 | |
| 9394 // Rotate Left by variable | |
| 9395 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
| 9396 %{ | |
| 9397 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift)))); | |
| 9398 | |
| 9399 expand %{ | |
| 9400 rolI_rReg_CL(dst, shift, cr); | |
| 9401 %} | |
| 9402 %} | |
| 9403 | |
| 9404 // Rotate Left by variable | |
| 9405 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr) | |
| 9406 %{ | |
| 9407 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift)))); | |
| 9408 | |
| 9409 expand %{ | |
| 9410 rolI_rReg_CL(dst, shift, cr); | |
| 9411 %} | |
| 9412 %} | |
| 9413 | |
| 9414 // ROR expand | |
| 9415 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr) | |
| 9416 %{ | |
| 9417 effect(USE_DEF dst, KILL cr); | |
| 9418 | |
| 9419 format %{ "rorl $dst" %} | |
| 9420 opcode(0xD1, 0x1); /* D1 /1 */ | |
| 9421 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 9422 ins_pipe(ialu_reg); | |
| 9423 %} | |
| 9424 | |
| 9425 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) | |
| 9426 %{ | |
| 9427 effect(USE_DEF dst, USE shift, KILL cr); | |
| 9428 | |
| 9429 format %{ "rorl $dst, $shift" %} | |
| 9430 opcode(0xC1, 0x1); /* C1 /1 ib */ | |
| 9431 ins_encode(reg_opc_imm(dst, shift)); | |
| 9432 ins_pipe(ialu_reg); | |
| 9433 %} | |
| 9434 | |
| 9435 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 9436 %{ | |
| 9437 effect(USE_DEF dst, USE shift, KILL cr); | |
| 9438 | |
| 9439 format %{ "rorl $dst, $shift" %} | |
| 9440 opcode(0xD3, 0x1); /* D3 /1 */ | |
| 9441 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 9442 ins_pipe(ialu_reg_reg); | |
| 9443 %} | |
| 9444 // end of ROR expand | |
| 9445 | |
| 9446 // Rotate Right by one | |
| 9447 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr) | |
| 9448 %{ | |
| 9449 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift))); | |
| 9450 | |
| 9451 expand %{ | |
| 9452 rorI_rReg_imm1(dst, cr); | |
| 9453 %} | |
| 9454 %} | |
| 9455 | |
| 9456 // Rotate Right by 8-bit immediate | |
| 9457 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr) | |
| 9458 %{ | |
| 9459 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); | |
| 9460 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift))); | |
| 9461 | |
| 9462 expand %{ | |
| 9463 rorI_rReg_imm8(dst, rshift, cr); | |
| 9464 %} | |
| 9465 %} | |
| 9466 | |
| 9467 // Rotate Right by variable | |
| 9468 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
| 9469 %{ | |
| 9470 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift)))); | |
| 9471 | |
| 9472 expand %{ | |
| 9473 rorI_rReg_CL(dst, shift, cr); | |
| 9474 %} | |
| 9475 %} | |
| 9476 | |
| 9477 // Rotate Right by variable | |
| 9478 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr) | |
| 9479 %{ | |
| 9480 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift)))); | |
| 9481 | |
| 9482 expand %{ | |
| 9483 rorI_rReg_CL(dst, shift, cr); | |
| 9484 %} | |
| 9485 %} | |
| 9486 | |
| 9487 // for long rotate | |
| 9488 // ROL expand | |
| 9489 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{ | |
| 9490 effect(USE_DEF dst, KILL cr); | |
| 9491 | |
| 9492 format %{ "rolq $dst" %} | |
| 9493 opcode(0xD1, 0x0); /* Opcode D1 /0 */ | |
| 9494 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 9495 ins_pipe(ialu_reg); | |
| 9496 %} | |
| 9497 | |
| 9498 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{ | |
| 9499 effect(USE_DEF dst, USE shift, KILL cr); | |
| 9500 | |
| 9501 format %{ "rolq $dst, $shift" %} | |
| 9502 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */ | |
| 9503 ins_encode( reg_opc_imm_wide(dst, shift) ); | |
| 9504 ins_pipe(ialu_reg); | |
| 9505 %} | |
| 9506 | |
| 9507 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 9508 %{ | |
| 9509 effect(USE_DEF dst, USE shift, KILL cr); | |
| 9510 | |
| 9511 format %{ "rolq $dst, $shift" %} | |
| 9512 opcode(0xD3, 0x0); /* Opcode D3 /0 */ | |
| 9513 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 9514 ins_pipe(ialu_reg_reg); | |
| 9515 %} | |
| 9516 // end of ROL expand | |
| 9517 | |
| 9518 // Rotate Left by one | |
| 9519 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr) | |
| 9520 %{ | |
| 9521 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift))); | |
| 9522 | |
| 9523 expand %{ | |
| 9524 rolL_rReg_imm1(dst, cr); | |
| 9525 %} | |
| 9526 %} | |
| 9527 | |
| 9528 // Rotate Left by 8-bit immediate | |
| 9529 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr) | |
| 9530 %{ | |
| 9531 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f)); | |
| 9532 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift))); | |
| 9533 | |
| 9534 expand %{ | |
| 9535 rolL_rReg_imm8(dst, lshift, cr); | |
| 9536 %} | |
| 9537 %} | |
| 9538 | |
| 9539 // Rotate Left by variable | |
| 9540 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
| 9541 %{ | |
| 9542 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift)))); | |
| 9543 | |
| 9544 expand %{ | |
| 9545 rolL_rReg_CL(dst, shift, cr); | |
| 9546 %} | |
| 9547 %} | |
| 9548 | |
| 9549 // Rotate Left by variable | |
| 9550 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr) | |
| 9551 %{ | |
| 9552 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift)))); | |
| 9553 | |
| 9554 expand %{ | |
| 9555 rolL_rReg_CL(dst, shift, cr); | |
| 9556 %} | |
| 9557 %} | |
| 9558 | |
| 9559 // ROR expand | |
| 9560 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr) | |
| 9561 %{ | |
| 9562 effect(USE_DEF dst, KILL cr); | |
| 9563 | |
| 9564 format %{ "rorq $dst" %} | |
| 9565 opcode(0xD1, 0x1); /* D1 /1 */ | |
| 9566 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 9567 ins_pipe(ialu_reg); | |
| 9568 %} | |
| 9569 | |
| 9570 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) | |
| 9571 %{ | |
| 9572 effect(USE_DEF dst, USE shift, KILL cr); | |
| 9573 | |
| 9574 format %{ "rorq $dst, $shift" %} | |
| 9575 opcode(0xC1, 0x1); /* C1 /1 ib */ | |
| 9576 ins_encode(reg_opc_imm_wide(dst, shift)); | |
| 9577 ins_pipe(ialu_reg); | |
| 9578 %} | |
| 9579 | |
| 9580 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 9581 %{ | |
| 9582 effect(USE_DEF dst, USE shift, KILL cr); | |
| 9583 | |
| 9584 format %{ "rorq $dst, $shift" %} | |
| 9585 opcode(0xD3, 0x1); /* D3 /1 */ | |
| 9586 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 9587 ins_pipe(ialu_reg_reg); | |
| 9588 %} | |
| 9589 // end of ROR expand | |
| 9590 | |
| 9591 // Rotate Right by one | |
| 9592 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr) | |
| 9593 %{ | |
| 9594 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift))); | |
| 9595 | |
| 9596 expand %{ | |
| 9597 rorL_rReg_imm1(dst, cr); | |
| 9598 %} | |
| 9599 %} | |
| 9600 | |
| 9601 // Rotate Right by 8-bit immediate | |
| 9602 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr) | |
| 9603 %{ | |
| 9604 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f)); | |
| 9605 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift))); | |
| 9606 | |
| 9607 expand %{ | |
| 9608 rorL_rReg_imm8(dst, rshift, cr); | |
| 9609 %} | |
| 9610 %} | |
| 9611 | |
| 9612 // Rotate Right by variable | |
| 9613 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
| 9614 %{ | |
| 9615 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift)))); | |
| 9616 | |
| 9617 expand %{ | |
| 9618 rorL_rReg_CL(dst, shift, cr); | |
| 9619 %} | |
| 9620 %} | |
| 9621 | |
| 9622 // Rotate Right by variable | |
| 9623 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr) | |
| 9624 %{ | |
| 9625 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift)))); | |
| 9626 | |
| 9627 expand %{ | |
| 9628 rorL_rReg_CL(dst, shift, cr); | |
| 9629 %} | |
| 9630 %} | |
| 9631 | |
| 9632 // Logical Instructions | |
| 9633 | |
| 9634 // Integer Logical Instructions | |
| 9635 | |
| 9636 // And Instructions | |
| 9637 // And Register with Register | |
| 9638 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 9639 %{ | |
| 9640 match(Set dst (AndI dst src)); | |
| 9641 effect(KILL cr); | |
| 9642 | |
| 9643 format %{ "andl $dst, $src\t# int" %} | |
| 9644 opcode(0x23); | |
| 9645 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 9646 ins_pipe(ialu_reg_reg); | |
| 9647 %} | |
| 9648 | |
| 9649 // And Register with Immediate 255 | |
| 9650 instruct andI_rReg_imm255(rRegI dst, immI_255 src) | |
| 9651 %{ | |
| 9652 match(Set dst (AndI dst src)); | |
| 9653 | |
| 9654 format %{ "movzbl $dst, $dst\t# int & 0xFF" %} | |
| 9655 opcode(0x0F, 0xB6); | |
| 9656 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 9657 ins_pipe(ialu_reg); | |
| 9658 %} | |
| 9659 | |
| 9660 // And Register with Immediate 255 and promote to long | |
| 9661 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask) | |
| 9662 %{ | |
| 9663 match(Set dst (ConvI2L (AndI src mask))); | |
| 9664 | |
| 9665 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %} | |
| 9666 opcode(0x0F, 0xB6); | |
| 9667 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 9668 ins_pipe(ialu_reg); | |
| 9669 %} | |
| 9670 | |
| 9671 // And Register with Immediate 65535 | |
| 9672 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src) | |
| 9673 %{ | |
| 9674 match(Set dst (AndI dst src)); | |
| 9675 | |
| 9676 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %} | |
| 9677 opcode(0x0F, 0xB7); | |
| 9678 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 9679 ins_pipe(ialu_reg); | |
| 9680 %} | |
| 9681 | |
| 9682 // And Register with Immediate 65535 and promote to long | |
| 9683 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask) | |
| 9684 %{ | |
| 9685 match(Set dst (ConvI2L (AndI src mask))); | |
| 9686 | |
| 9687 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %} | |
| 9688 opcode(0x0F, 0xB7); | |
| 9689 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 9690 ins_pipe(ialu_reg); | |
| 9691 %} | |
| 9692 | |
| 9693 // And Register with Immediate | |
| 9694 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 9695 %{ | |
| 9696 match(Set dst (AndI dst src)); | |
| 9697 effect(KILL cr); | |
| 9698 | |
| 9699 format %{ "andl $dst, $src\t# int" %} | |
| 9700 opcode(0x81, 0x04); /* Opcode 81 /4 */ | |
| 9701 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 9702 ins_pipe(ialu_reg); | |
| 9703 %} | |
| 9704 | |
| 9705 // And Register with Memory | |
| 9706 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 9707 %{ | |
| 9708 match(Set dst (AndI dst (LoadI src))); | |
| 9709 effect(KILL cr); | |
| 9710 | |
| 9711 ins_cost(125); | |
| 9712 format %{ "andl $dst, $src\t# int" %} | |
| 9713 opcode(0x23); | |
| 9714 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 9715 ins_pipe(ialu_reg_mem); | |
| 9716 %} | |
| 9717 | |
| 9718 // And Memory with Register | |
| 9719 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 9720 %{ | |
| 9721 match(Set dst (StoreI dst (AndI (LoadI dst) src))); | |
| 9722 effect(KILL cr); | |
| 9723 | |
| 9724 ins_cost(150); | |
| 9725 format %{ "andl $dst, $src\t# int" %} | |
| 9726 opcode(0x21); /* Opcode 21 /r */ | |
| 9727 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 9728 ins_pipe(ialu_mem_reg); | |
| 9729 %} | |
| 9730 | |
| 9731 // And Memory with Immediate | |
| 9732 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 9733 %{ | |
| 9734 match(Set dst (StoreI dst (AndI (LoadI dst) src))); | |
| 9735 effect(KILL cr); | |
| 9736 | |
| 9737 ins_cost(125); | |
| 9738 format %{ "andl $dst, $src\t# int" %} | |
| 9739 opcode(0x81, 0x4); /* Opcode 81 /4 id */ | |
| 9740 ins_encode(REX_mem(dst), OpcSE(src), | |
| 9741 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 9742 ins_pipe(ialu_mem_imm); | |
| 9743 %} | |
| 9744 | |
| 9745 // Or Instructions | |
| 9746 // Or Register with Register | |
| 9747 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 9748 %{ | |
| 9749 match(Set dst (OrI dst src)); | |
| 9750 effect(KILL cr); | |
| 9751 | |
| 9752 format %{ "orl $dst, $src\t# int" %} | |
| 9753 opcode(0x0B); | |
| 9754 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 9755 ins_pipe(ialu_reg_reg); | |
| 9756 %} | |
| 9757 | |
| 9758 // Or Register with Immediate | |
| 9759 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 9760 %{ | |
| 9761 match(Set dst (OrI dst src)); | |
| 9762 effect(KILL cr); | |
| 9763 | |
| 9764 format %{ "orl $dst, $src\t# int" %} | |
| 9765 opcode(0x81, 0x01); /* Opcode 81 /1 id */ | |
| 9766 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 9767 ins_pipe(ialu_reg); | |
| 9768 %} | |
| 9769 | |
| 9770 // Or Register with Memory | |
| 9771 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 9772 %{ | |
| 9773 match(Set dst (OrI dst (LoadI src))); | |
| 9774 effect(KILL cr); | |
| 9775 | |
| 9776 ins_cost(125); | |
| 9777 format %{ "orl $dst, $src\t# int" %} | |
| 9778 opcode(0x0B); | |
| 9779 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 9780 ins_pipe(ialu_reg_mem); | |
| 9781 %} | |
| 9782 | |
| 9783 // Or Memory with Register | |
| 9784 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 9785 %{ | |
| 9786 match(Set dst (StoreI dst (OrI (LoadI dst) src))); | |
| 9787 effect(KILL cr); | |
| 9788 | |
| 9789 ins_cost(150); | |
| 9790 format %{ "orl $dst, $src\t# int" %} | |
| 9791 opcode(0x09); /* Opcode 09 /r */ | |
| 9792 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 9793 ins_pipe(ialu_mem_reg); | |
| 9794 %} | |
| 9795 | |
| 9796 // Or Memory with Immediate | |
| 9797 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 9798 %{ | |
| 9799 match(Set dst (StoreI dst (OrI (LoadI dst) src))); | |
| 9800 effect(KILL cr); | |
| 9801 | |
| 9802 ins_cost(125); | |
| 9803 format %{ "orl $dst, $src\t# int" %} | |
| 9804 opcode(0x81, 0x1); /* Opcode 81 /1 id */ | |
| 9805 ins_encode(REX_mem(dst), OpcSE(src), | |
| 9806 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 9807 ins_pipe(ialu_mem_imm); | |
| 9808 %} | |
| 9809 | |
| 9810 // Xor Instructions | |
| 9811 // Xor Register with Register | |
| 9812 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 9813 %{ | |
| 9814 match(Set dst (XorI dst src)); | |
| 9815 effect(KILL cr); | |
| 9816 | |
| 9817 format %{ "xorl $dst, $src\t# int" %} | |
| 9818 opcode(0x33); | |
| 9819 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 9820 ins_pipe(ialu_reg_reg); | |
| 9821 %} | |
| 9822 | |
| 403 | 9823 // Xor Register with Immediate -1 |
| 9824 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{ | |
| 9825 match(Set dst (XorI dst imm)); | |
| 9826 | |
| 9827 format %{ "not $dst" %} | |
| 9828 ins_encode %{ | |
| 9829 __ notl($dst$$Register); | |
| 9830 %} | |
| 9831 ins_pipe(ialu_reg); | |
| 9832 %} | |
| 9833 | |
| 0 | 9834 // Xor Register with Immediate |
| 9835 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 9836 %{ | |
| 9837 match(Set dst (XorI dst src)); | |
| 9838 effect(KILL cr); | |
| 9839 | |
| 9840 format %{ "xorl $dst, $src\t# int" %} | |
| 9841 opcode(0x81, 0x06); /* Opcode 81 /6 id */ | |
| 9842 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 9843 ins_pipe(ialu_reg); | |
| 9844 %} | |
| 9845 | |
| 9846 // Xor Register with Memory | |
| 9847 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 9848 %{ | |
| 9849 match(Set dst (XorI dst (LoadI src))); | |
| 9850 effect(KILL cr); | |
| 9851 | |
| 9852 ins_cost(125); | |
| 9853 format %{ "xorl $dst, $src\t# int" %} | |
| 9854 opcode(0x33); | |
| 9855 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 9856 ins_pipe(ialu_reg_mem); | |
| 9857 %} | |
| 9858 | |
| 9859 // Xor Memory with Register | |
| 9860 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 9861 %{ | |
| 9862 match(Set dst (StoreI dst (XorI (LoadI dst) src))); | |
| 9863 effect(KILL cr); | |
| 9864 | |
| 9865 ins_cost(150); | |
| 9866 format %{ "xorl $dst, $src\t# int" %} | |
| 9867 opcode(0x31); /* Opcode 31 /r */ | |
| 9868 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 9869 ins_pipe(ialu_mem_reg); | |
| 9870 %} | |
| 9871 | |
| 9872 // Xor Memory with Immediate | |
| 9873 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 9874 %{ | |
| 9875 match(Set dst (StoreI dst (XorI (LoadI dst) src))); | |
| 9876 effect(KILL cr); | |
| 9877 | |
| 9878 ins_cost(125); | |
| 9879 format %{ "xorl $dst, $src\t# int" %} | |
| 9880 opcode(0x81, 0x6); /* Opcode 81 /6 id */ | |
| 9881 ins_encode(REX_mem(dst), OpcSE(src), | |
| 9882 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 9883 ins_pipe(ialu_mem_imm); | |
| 9884 %} | |
| 9885 | |
| 9886 | |
| 9887 // Long Logical Instructions | |
| 9888 | |
| 9889 // And Instructions | |
| 9890 // And Register with Register | |
| 9891 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 9892 %{ | |
| 9893 match(Set dst (AndL dst src)); | |
| 9894 effect(KILL cr); | |
| 9895 | |
| 9896 format %{ "andq $dst, $src\t# long" %} | |
| 9897 opcode(0x23); | |
| 9898 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 9899 ins_pipe(ialu_reg_reg); | |
| 9900 %} | |
| 9901 | |
| 9902 // And Register with Immediate 255 | |
| 9903 instruct andL_rReg_imm255(rRegL dst, immL_255 src) | |
| 9904 %{ | |
| 9905 match(Set dst (AndL dst src)); | |
| 9906 | |
|
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9907 format %{ "movzbq $dst, $dst\t# long & 0xFF" %} |
| 0 | 9908 opcode(0x0F, 0xB6); |
| 9909 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 9910 ins_pipe(ialu_reg); | |
| 9911 %} | |
| 9912 | |
| 9913 // And Register with Immediate 65535 | |
|
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9914 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src) |
| 0 | 9915 %{ |
| 9916 match(Set dst (AndL dst src)); | |
| 9917 | |
| 9918 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %} | |
| 9919 opcode(0x0F, 0xB7); | |
| 9920 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 9921 ins_pipe(ialu_reg); | |
| 9922 %} | |
| 9923 | |
| 9924 // And Register with Immediate | |
| 9925 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
| 9926 %{ | |
| 9927 match(Set dst (AndL dst src)); | |
| 9928 effect(KILL cr); | |
| 9929 | |
| 9930 format %{ "andq $dst, $src\t# long" %} | |
| 9931 opcode(0x81, 0x04); /* Opcode 81 /4 */ | |
| 9932 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 9933 ins_pipe(ialu_reg); | |
| 9934 %} | |
| 9935 | |
| 9936 // And Register with Memory | |
| 9937 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 9938 %{ | |
| 9939 match(Set dst (AndL dst (LoadL src))); | |
| 9940 effect(KILL cr); | |
| 9941 | |
| 9942 ins_cost(125); | |
| 9943 format %{ "andq $dst, $src\t# long" %} | |
| 9944 opcode(0x23); | |
| 9945 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 9946 ins_pipe(ialu_reg_mem); | |
| 9947 %} | |
| 9948 | |
| 9949 // And Memory with Register | |
| 9950 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 9951 %{ | |
| 9952 match(Set dst (StoreL dst (AndL (LoadL dst) src))); | |
| 9953 effect(KILL cr); | |
| 9954 | |
| 9955 ins_cost(150); | |
| 9956 format %{ "andq $dst, $src\t# long" %} | |
| 9957 opcode(0x21); /* Opcode 21 /r */ | |
| 9958 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 9959 ins_pipe(ialu_mem_reg); | |
| 9960 %} | |
| 9961 | |
| 9962 // And Memory with Immediate | |
| 9963 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 9964 %{ | |
| 9965 match(Set dst (StoreL dst (AndL (LoadL dst) src))); | |
| 9966 effect(KILL cr); | |
| 9967 | |
| 9968 ins_cost(125); | |
| 9969 format %{ "andq $dst, $src\t# long" %} | |
| 9970 opcode(0x81, 0x4); /* Opcode 81 /4 id */ | |
| 9971 ins_encode(REX_mem_wide(dst), OpcSE(src), | |
| 9972 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 9973 ins_pipe(ialu_mem_imm); | |
| 9974 %} | |
| 9975 | |
| 9976 // Or Instructions | |
| 9977 // Or Register with Register | |
| 9978 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 9979 %{ | |
| 9980 match(Set dst (OrL dst src)); | |
| 9981 effect(KILL cr); | |
| 9982 | |
| 9983 format %{ "orq $dst, $src\t# long" %} | |
| 9984 opcode(0x0B); | |
| 9985 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 9986 ins_pipe(ialu_reg_reg); | |
| 9987 %} | |
| 9988 | |
|
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9989 // Use any_RegP to match R15 (TLS register) without spilling. |
|
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9990 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{ |
|
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9991 match(Set dst (OrL dst (CastP2X src))); |
|
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9992 effect(KILL cr); |
|
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9993 |
|
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9994 format %{ "orq $dst, $src\t# long" %} |
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9995 opcode(0x0B); |
|
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9996 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); |
|
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9997 ins_pipe(ialu_reg_reg); |
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9998 %} |
|
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9999 |
|
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10000 |
| 0 | 10001 // Or Register with Immediate |
| 10002 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
| 10003 %{ | |
| 10004 match(Set dst (OrL dst src)); | |
| 10005 effect(KILL cr); | |
| 10006 | |
| 10007 format %{ "orq $dst, $src\t# long" %} | |
| 10008 opcode(0x81, 0x01); /* Opcode 81 /1 id */ | |
| 10009 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 10010 ins_pipe(ialu_reg); | |
| 10011 %} | |
| 10012 | |
| 10013 // Or Register with Memory | |
| 10014 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 10015 %{ | |
| 10016 match(Set dst (OrL dst (LoadL src))); | |
| 10017 effect(KILL cr); | |
| 10018 | |
| 10019 ins_cost(125); | |
| 10020 format %{ "orq $dst, $src\t# long" %} | |
| 10021 opcode(0x0B); | |
| 10022 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 10023 ins_pipe(ialu_reg_mem); | |
| 10024 %} | |
| 10025 | |
| 10026 // Or Memory with Register | |
| 10027 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 10028 %{ | |
| 10029 match(Set dst (StoreL dst (OrL (LoadL dst) src))); | |
| 10030 effect(KILL cr); | |
| 10031 | |
| 10032 ins_cost(150); | |
| 10033 format %{ "orq $dst, $src\t# long" %} | |
| 10034 opcode(0x09); /* Opcode 09 /r */ | |
| 10035 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 10036 ins_pipe(ialu_mem_reg); | |
| 10037 %} | |
| 10038 | |
| 10039 // Or Memory with Immediate | |
| 10040 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 10041 %{ | |
| 10042 match(Set dst (StoreL dst (OrL (LoadL dst) src))); | |
| 10043 effect(KILL cr); | |
| 10044 | |
| 10045 ins_cost(125); | |
| 10046 format %{ "orq $dst, $src\t# long" %} | |
| 10047 opcode(0x81, 0x1); /* Opcode 81 /1 id */ | |
| 10048 ins_encode(REX_mem_wide(dst), OpcSE(src), | |
| 10049 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 10050 ins_pipe(ialu_mem_imm); | |
| 10051 %} | |
| 10052 | |
| 10053 // Xor Instructions | |
| 10054 // Xor Register with Register | |
| 10055 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 10056 %{ | |
| 10057 match(Set dst (XorL dst src)); | |
| 10058 effect(KILL cr); | |
| 10059 | |
| 10060 format %{ "xorq $dst, $src\t# long" %} | |
| 10061 opcode(0x33); | |
| 10062 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 10063 ins_pipe(ialu_reg_reg); | |
| 10064 %} | |
| 10065 | |
| 403 | 10066 // Xor Register with Immediate -1 |
| 10067 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{ | |
| 10068 match(Set dst (XorL dst imm)); | |
| 10069 | |
| 10070 format %{ "notq $dst" %} | |
| 10071 ins_encode %{ | |
| 10072 __ notq($dst$$Register); | |
| 10073 %} | |
| 10074 ins_pipe(ialu_reg); | |
| 10075 %} | |
| 10076 | |
| 0 | 10077 // Xor Register with Immediate |
| 10078 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
| 10079 %{ | |
| 10080 match(Set dst (XorL dst src)); | |
| 10081 effect(KILL cr); | |
| 10082 | |
| 10083 format %{ "xorq $dst, $src\t# long" %} | |
| 10084 opcode(0x81, 0x06); /* Opcode 81 /6 id */ | |
| 10085 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 10086 ins_pipe(ialu_reg); | |
| 10087 %} | |
| 10088 | |
| 10089 // Xor Register with Memory | |
| 10090 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 10091 %{ | |
| 10092 match(Set dst (XorL dst (LoadL src))); | |
| 10093 effect(KILL cr); | |
| 10094 | |
| 10095 ins_cost(125); | |
| 10096 format %{ "xorq $dst, $src\t# long" %} | |
| 10097 opcode(0x33); | |
| 10098 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 10099 ins_pipe(ialu_reg_mem); | |
| 10100 %} | |
| 10101 | |
| 10102 // Xor Memory with Register | |
| 10103 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 10104 %{ | |
| 10105 match(Set dst (StoreL dst (XorL (LoadL dst) src))); | |
| 10106 effect(KILL cr); | |
| 10107 | |
| 10108 ins_cost(150); | |
| 10109 format %{ "xorq $dst, $src\t# long" %} | |
| 10110 opcode(0x31); /* Opcode 31 /r */ | |
| 10111 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 10112 ins_pipe(ialu_mem_reg); | |
| 10113 %} | |
| 10114 | |
| 10115 // Xor Memory with Immediate | |
| 10116 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 10117 %{ | |
| 10118 match(Set dst (StoreL dst (XorL (LoadL dst) src))); | |
| 10119 effect(KILL cr); | |
| 10120 | |
| 10121 ins_cost(125); | |
| 10122 format %{ "xorq $dst, $src\t# long" %} | |
| 10123 opcode(0x81, 0x6); /* Opcode 81 /6 id */ | |
| 10124 ins_encode(REX_mem_wide(dst), OpcSE(src), | |
| 10125 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 10126 ins_pipe(ialu_mem_imm); | |
| 10127 %} | |
| 10128 | |
| 10129 // Convert Int to Boolean | |
| 10130 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr) | |
| 10131 %{ | |
| 10132 match(Set dst (Conv2B src)); | |
| 10133 effect(KILL cr); | |
| 10134 | |
| 10135 format %{ "testl $src, $src\t# ci2b\n\t" | |
| 10136 "setnz $dst\n\t" | |
| 10137 "movzbl $dst, $dst" %} | |
| 10138 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl | |
| 10139 setNZ_reg(dst), | |
| 10140 REX_reg_breg(dst, dst), // movzbl | |
| 10141 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst)); | |
| 10142 ins_pipe(pipe_slow); // XXX | |
| 10143 %} | |
| 10144 | |
| 10145 // Convert Pointer to Boolean | |
| 10146 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr) | |
| 10147 %{ | |
| 10148 match(Set dst (Conv2B src)); | |
| 10149 effect(KILL cr); | |
| 10150 | |
| 10151 format %{ "testq $src, $src\t# cp2b\n\t" | |
| 10152 "setnz $dst\n\t" | |
| 10153 "movzbl $dst, $dst" %} | |
| 10154 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq | |
| 10155 setNZ_reg(dst), | |
| 10156 REX_reg_breg(dst, dst), // movzbl | |
| 10157 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst)); | |
| 10158 ins_pipe(pipe_slow); // XXX | |
| 10159 %} | |
| 10160 | |
| 10161 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr) | |
| 10162 %{ | |
| 10163 match(Set dst (CmpLTMask p q)); | |
| 10164 effect(KILL cr); | |
| 10165 | |
| 10166 ins_cost(400); // XXX | |
| 10167 format %{ "cmpl $p, $q\t# cmpLTMask\n\t" | |
| 10168 "setlt $dst\n\t" | |
| 10169 "movzbl $dst, $dst\n\t" | |
| 10170 "negl $dst" %} | |
| 10171 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl | |
| 10172 setLT_reg(dst), | |
| 10173 REX_reg_breg(dst, dst), // movzbl | |
| 10174 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst), | |
| 10175 neg_reg(dst)); | |
| 10176 ins_pipe(pipe_slow); | |
| 10177 %} | |
| 10178 | |
| 10179 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr) | |
| 10180 %{ | |
| 10181 match(Set dst (CmpLTMask dst zero)); | |
| 10182 effect(KILL cr); | |
| 10183 | |
| 10184 ins_cost(100); // XXX | |
| 10185 format %{ "sarl $dst, #31\t# cmpLTMask0" %} | |
| 10186 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 10187 ins_encode(reg_opc_imm(dst, 0x1F)); | |
| 10188 ins_pipe(ialu_reg); | |
| 10189 %} | |
| 10190 | |
| 10191 | |
| 10192 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, | |
| 10193 rRegI tmp, | |
| 10194 rFlagsReg cr) | |
| 10195 %{ | |
| 10196 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); | |
| 10197 effect(TEMP tmp, KILL cr); | |
| 10198 | |
| 10199 ins_cost(400); // XXX | |
| 10200 format %{ "subl $p, $q\t# cadd_cmpLTMask1\n\t" | |
| 10201 "sbbl $tmp, $tmp\n\t" | |
| 10202 "andl $tmp, $y\n\t" | |
| 10203 "addl $p, $tmp" %} | |
| 10204 ins_encode(enc_cmpLTP(p, q, y, tmp)); | |
| 10205 ins_pipe(pipe_cmplt); | |
| 10206 %} | |
| 10207 | |
| 10208 /* If I enable this, I encourage spilling in the inner loop of compress. | |
| 10209 instruct cadd_cmpLTMask_mem( rRegI p, rRegI q, memory y, rRegI tmp, rFlagsReg cr ) | |
| 10210 %{ | |
| 10211 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q))); | |
| 10212 effect( TEMP tmp, KILL cr ); | |
| 10213 ins_cost(400); | |
| 10214 | |
| 10215 format %{ "SUB $p,$q\n\t" | |
| 10216 "SBB RCX,RCX\n\t" | |
| 10217 "AND RCX,$y\n\t" | |
| 10218 "ADD $p,RCX" %} | |
| 10219 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) ); | |
| 10220 %} | |
| 10221 */ | |
| 10222 | |
| 10223 //---------- FP Instructions------------------------------------------------ | |
| 10224 | |
| 10225 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2) | |
| 10226 %{ | |
| 10227 match(Set cr (CmpF src1 src2)); | |
| 10228 | |
| 10229 ins_cost(145); | |
| 10230 format %{ "ucomiss $src1, $src2\n\t" | |
| 10231 "jnp,s exit\n\t" | |
| 10232 "pushfq\t# saw NaN, set CF\n\t" | |
| 10233 "andq [rsp], #0xffffff2b\n\t" | |
| 10234 "popfq\n" | |
| 10235 "exit: nop\t# avoid branch to branch" %} | |
| 10236 opcode(0x0F, 0x2E); | |
| 10237 ins_encode(REX_reg_reg(src1, src2), OpcP, OpcS, reg_reg(src1, src2), | |
| 10238 cmpfp_fixup); | |
| 10239 ins_pipe(pipe_slow); | |
| 10240 %} | |
| 10241 | |
|
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10242 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{ |
|
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|
10243 match(Set cr (CmpF src1 src2)); |
|
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|
10244 |
|
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|
10245 ins_cost(145); |
|
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|
10246 format %{ "ucomiss $src1, $src2" %} |
|
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|
10247 ins_encode %{ |
|
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|
10248 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); |
|
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|
10249 %} |
|
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diff
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|
10250 ins_pipe(pipe_slow); |
|
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|
10251 %} |
|
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|
10252 |
| 0 | 10253 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2) |
| 10254 %{ | |
| 10255 match(Set cr (CmpF src1 (LoadF src2))); | |
| 10256 | |
| 10257 ins_cost(145); | |
| 10258 format %{ "ucomiss $src1, $src2\n\t" | |
| 10259 "jnp,s exit\n\t" | |
| 10260 "pushfq\t# saw NaN, set CF\n\t" | |
| 10261 "andq [rsp], #0xffffff2b\n\t" | |
| 10262 "popfq\n" | |
| 10263 "exit: nop\t# avoid branch to branch" %} | |
| 10264 opcode(0x0F, 0x2E); | |
| 10265 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, reg_mem(src1, src2), | |
| 10266 cmpfp_fixup); | |
| 10267 ins_pipe(pipe_slow); | |
| 10268 %} | |
| 10269 | |
|
415
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|
10270 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{ |
|
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|
10271 match(Set cr (CmpF src1 (LoadF src2))); |
|
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|
10272 |
|
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|
10273 ins_cost(100); |
|
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|
10274 format %{ "ucomiss $src1, $src2" %} |
|
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|
10275 opcode(0x0F, 0x2E); |
|
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|
10276 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, reg_mem(src1, src2)); |
|
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|
10277 ins_pipe(pipe_slow); |
|
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|
10278 %} |
|
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|
10279 |
| 0 | 10280 instruct cmpF_cc_imm(rFlagsRegU cr, regF src1, immF src2) |
| 10281 %{ | |
| 10282 match(Set cr (CmpF src1 src2)); | |
| 10283 | |
| 10284 ins_cost(145); | |
| 10285 format %{ "ucomiss $src1, $src2\n\t" | |
| 10286 "jnp,s exit\n\t" | |
| 10287 "pushfq\t# saw NaN, set CF\n\t" | |
| 10288 "andq [rsp], #0xffffff2b\n\t" | |
| 10289 "popfq\n" | |
| 10290 "exit: nop\t# avoid branch to branch" %} | |
| 10291 opcode(0x0F, 0x2E); | |
| 10292 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, load_immF(src1, src2), | |
| 10293 cmpfp_fixup); | |
| 10294 ins_pipe(pipe_slow); | |
| 10295 %} | |
| 10296 | |
|
415
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|
10297 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src1, immF src2) %{ |
|
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|
10298 match(Set cr (CmpF src1 src2)); |
|
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|
10299 |
|
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|
10300 ins_cost(100); |
|
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|
10301 format %{ "ucomiss $src1, $src2" %} |
|
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|
10302 opcode(0x0F, 0x2E); |
|
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|
10303 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, load_immF(src1, src2)); |
|
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|
10304 ins_pipe(pipe_slow); |
|
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|
10305 %} |
|
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|
10306 |
| 0 | 10307 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2) |
| 10308 %{ | |
| 10309 match(Set cr (CmpD src1 src2)); | |
| 10310 | |
| 10311 ins_cost(145); | |
| 10312 format %{ "ucomisd $src1, $src2\n\t" | |
| 10313 "jnp,s exit\n\t" | |
| 10314 "pushfq\t# saw NaN, set CF\n\t" | |
| 10315 "andq [rsp], #0xffffff2b\n\t" | |
| 10316 "popfq\n" | |
| 10317 "exit: nop\t# avoid branch to branch" %} | |
| 10318 opcode(0x66, 0x0F, 0x2E); | |
| 10319 ins_encode(OpcP, REX_reg_reg(src1, src2), OpcS, OpcT, reg_reg(src1, src2), | |
| 10320 cmpfp_fixup); | |
| 10321 ins_pipe(pipe_slow); | |
| 10322 %} | |
| 10323 | |
|
415
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|
10324 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{ |
|
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|
10325 match(Set cr (CmpD src1 src2)); |
|
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|
10326 |
|
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changeset
|
10327 ins_cost(100); |
|
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diff
changeset
|
10328 format %{ "ucomisd $src1, $src2 test" %} |
|
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|
10329 ins_encode %{ |
|
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|
10330 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); |
|
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|
10331 %} |
|
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|
10332 ins_pipe(pipe_slow); |
|
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|
10333 %} |
|
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|
10334 |
| 0 | 10335 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2) |
| 10336 %{ | |
| 10337 match(Set cr (CmpD src1 (LoadD src2))); | |
| 10338 | |
| 10339 ins_cost(145); | |
| 10340 format %{ "ucomisd $src1, $src2\n\t" | |
| 10341 "jnp,s exit\n\t" | |
| 10342 "pushfq\t# saw NaN, set CF\n\t" | |
| 10343 "andq [rsp], #0xffffff2b\n\t" | |
| 10344 "popfq\n" | |
| 10345 "exit: nop\t# avoid branch to branch" %} | |
| 10346 opcode(0x66, 0x0F, 0x2E); | |
| 10347 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, reg_mem(src1, src2), | |
| 10348 cmpfp_fixup); | |
| 10349 ins_pipe(pipe_slow); | |
| 10350 %} | |
| 10351 | |
|
415
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|
10352 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{ |
|
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|
10353 match(Set cr (CmpD src1 (LoadD src2))); |
|
4d9884b01ba6
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|
10354 |
|
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|
10355 ins_cost(100); |
|
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|
10356 format %{ "ucomisd $src1, $src2" %} |
|
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|
10357 opcode(0x66, 0x0F, 0x2E); |
|
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|
10358 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, reg_mem(src1, src2)); |
|
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|
10359 ins_pipe(pipe_slow); |
|
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|
10360 %} |
|
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|
10361 |
| 0 | 10362 instruct cmpD_cc_imm(rFlagsRegU cr, regD src1, immD src2) |
| 10363 %{ | |
| 10364 match(Set cr (CmpD src1 src2)); | |
| 10365 | |
| 10366 ins_cost(145); | |
| 10367 format %{ "ucomisd $src1, [$src2]\n\t" | |
| 10368 "jnp,s exit\n\t" | |
| 10369 "pushfq\t# saw NaN, set CF\n\t" | |
| 10370 "andq [rsp], #0xffffff2b\n\t" | |
| 10371 "popfq\n" | |
| 10372 "exit: nop\t# avoid branch to branch" %} | |
| 10373 opcode(0x66, 0x0F, 0x2E); | |
| 10374 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, load_immD(src1, src2), | |
| 10375 cmpfp_fixup); | |
| 10376 ins_pipe(pipe_slow); | |
| 10377 %} | |
| 10378 | |
|
415
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|
10379 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src1, immD src2) %{ |
|
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changeset
|
10380 match(Set cr (CmpD src1 src2)); |
|
4d9884b01ba6
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diff
changeset
|
10381 |
|
4d9884b01ba6
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diff
changeset
|
10382 ins_cost(100); |
|
4d9884b01ba6
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diff
changeset
|
10383 format %{ "ucomisd $src1, [$src2]" %} |
|
4d9884b01ba6
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parents:
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diff
changeset
|
10384 opcode(0x66, 0x0F, 0x2E); |
|
4d9884b01ba6
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changeset
|
10385 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, load_immD(src1, src2)); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10386 ins_pipe(pipe_slow); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10387 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10388 |
| 0 | 10389 // Compare into -1,0,1 |
| 10390 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr) | |
| 10391 %{ | |
| 10392 match(Set dst (CmpF3 src1 src2)); | |
| 10393 effect(KILL cr); | |
| 10394 | |
| 10395 ins_cost(275); | |
| 10396 format %{ "ucomiss $src1, $src2\n\t" | |
| 10397 "movl $dst, #-1\n\t" | |
| 10398 "jp,s done\n\t" | |
| 10399 "jb,s done\n\t" | |
| 10400 "setne $dst\n\t" | |
| 10401 "movzbl $dst, $dst\n" | |
| 10402 "done:" %} | |
| 10403 | |
| 10404 opcode(0x0F, 0x2E); | |
| 10405 ins_encode(REX_reg_reg(src1, src2), OpcP, OpcS, reg_reg(src1, src2), | |
| 10406 cmpfp3(dst)); | |
| 10407 ins_pipe(pipe_slow); | |
| 10408 %} | |
| 10409 | |
| 10410 // Compare into -1,0,1 | |
| 10411 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr) | |
| 10412 %{ | |
| 10413 match(Set dst (CmpF3 src1 (LoadF src2))); | |
| 10414 effect(KILL cr); | |
| 10415 | |
| 10416 ins_cost(275); | |
| 10417 format %{ "ucomiss $src1, $src2\n\t" | |
| 10418 "movl $dst, #-1\n\t" | |
| 10419 "jp,s done\n\t" | |
| 10420 "jb,s done\n\t" | |
| 10421 "setne $dst\n\t" | |
| 10422 "movzbl $dst, $dst\n" | |
| 10423 "done:" %} | |
| 10424 | |
| 10425 opcode(0x0F, 0x2E); | |
| 10426 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, reg_mem(src1, src2), | |
| 10427 cmpfp3(dst)); | |
| 10428 ins_pipe(pipe_slow); | |
| 10429 %} | |
| 10430 | |
| 10431 // Compare into -1,0,1 | |
| 10432 instruct cmpF_imm(rRegI dst, regF src1, immF src2, rFlagsReg cr) | |
| 10433 %{ | |
| 10434 match(Set dst (CmpF3 src1 src2)); | |
| 10435 effect(KILL cr); | |
| 10436 | |
| 10437 ins_cost(275); | |
| 10438 format %{ "ucomiss $src1, [$src2]\n\t" | |
| 10439 "movl $dst, #-1\n\t" | |
| 10440 "jp,s done\n\t" | |
| 10441 "jb,s done\n\t" | |
| 10442 "setne $dst\n\t" | |
| 10443 "movzbl $dst, $dst\n" | |
| 10444 "done:" %} | |
| 10445 | |
| 10446 opcode(0x0F, 0x2E); | |
| 10447 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, load_immF(src1, src2), | |
| 10448 cmpfp3(dst)); | |
| 10449 ins_pipe(pipe_slow); | |
| 10450 %} | |
| 10451 | |
| 10452 // Compare into -1,0,1 | |
| 10453 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr) | |
| 10454 %{ | |
| 10455 match(Set dst (CmpD3 src1 src2)); | |
| 10456 effect(KILL cr); | |
| 10457 | |
| 10458 ins_cost(275); | |
| 10459 format %{ "ucomisd $src1, $src2\n\t" | |
| 10460 "movl $dst, #-1\n\t" | |
| 10461 "jp,s done\n\t" | |
| 10462 "jb,s done\n\t" | |
| 10463 "setne $dst\n\t" | |
| 10464 "movzbl $dst, $dst\n" | |
| 10465 "done:" %} | |
| 10466 | |
| 10467 opcode(0x66, 0x0F, 0x2E); | |
| 10468 ins_encode(OpcP, REX_reg_reg(src1, src2), OpcS, OpcT, reg_reg(src1, src2), | |
| 10469 cmpfp3(dst)); | |
| 10470 ins_pipe(pipe_slow); | |
| 10471 %} | |
| 10472 | |
| 10473 // Compare into -1,0,1 | |
| 10474 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr) | |
| 10475 %{ | |
| 10476 match(Set dst (CmpD3 src1 (LoadD src2))); | |
| 10477 effect(KILL cr); | |
| 10478 | |
| 10479 ins_cost(275); | |
| 10480 format %{ "ucomisd $src1, $src2\n\t" | |
| 10481 "movl $dst, #-1\n\t" | |
| 10482 "jp,s done\n\t" | |
| 10483 "jb,s done\n\t" | |
| 10484 "setne $dst\n\t" | |
| 10485 "movzbl $dst, $dst\n" | |
| 10486 "done:" %} | |
| 10487 | |
| 10488 opcode(0x66, 0x0F, 0x2E); | |
| 10489 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, reg_mem(src1, src2), | |
| 10490 cmpfp3(dst)); | |
| 10491 ins_pipe(pipe_slow); | |
| 10492 %} | |
| 10493 | |
| 10494 // Compare into -1,0,1 | |
| 10495 instruct cmpD_imm(rRegI dst, regD src1, immD src2, rFlagsReg cr) | |
| 10496 %{ | |
| 10497 match(Set dst (CmpD3 src1 src2)); | |
| 10498 effect(KILL cr); | |
| 10499 | |
| 10500 ins_cost(275); | |
| 10501 format %{ "ucomisd $src1, [$src2]\n\t" | |
| 10502 "movl $dst, #-1\n\t" | |
| 10503 "jp,s done\n\t" | |
| 10504 "jb,s done\n\t" | |
| 10505 "setne $dst\n\t" | |
| 10506 "movzbl $dst, $dst\n" | |
| 10507 "done:" %} | |
| 10508 | |
| 10509 opcode(0x66, 0x0F, 0x2E); | |
| 10510 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, load_immD(src1, src2), | |
| 10511 cmpfp3(dst)); | |
| 10512 ins_pipe(pipe_slow); | |
| 10513 %} | |
| 10514 | |
| 10515 instruct addF_reg(regF dst, regF src) | |
| 10516 %{ | |
| 10517 match(Set dst (AddF dst src)); | |
| 10518 | |
| 10519 format %{ "addss $dst, $src" %} | |
| 10520 ins_cost(150); // XXX | |
| 10521 opcode(0xF3, 0x0F, 0x58); | |
| 10522 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10523 ins_pipe(pipe_slow); | |
| 10524 %} | |
| 10525 | |
| 10526 instruct addF_mem(regF dst, memory src) | |
| 10527 %{ | |
| 10528 match(Set dst (AddF dst (LoadF src))); | |
| 10529 | |
| 10530 format %{ "addss $dst, $src" %} | |
| 10531 ins_cost(150); // XXX | |
| 10532 opcode(0xF3, 0x0F, 0x58); | |
| 10533 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10534 ins_pipe(pipe_slow); | |
| 10535 %} | |
| 10536 | |
| 10537 instruct addF_imm(regF dst, immF src) | |
| 10538 %{ | |
| 10539 match(Set dst (AddF dst src)); | |
| 10540 | |
| 10541 format %{ "addss $dst, [$src]" %} | |
| 10542 ins_cost(150); // XXX | |
| 10543 opcode(0xF3, 0x0F, 0x58); | |
| 10544 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immF(dst, src)); | |
| 10545 ins_pipe(pipe_slow); | |
| 10546 %} | |
| 10547 | |
| 10548 instruct addD_reg(regD dst, regD src) | |
| 10549 %{ | |
| 10550 match(Set dst (AddD dst src)); | |
| 10551 | |
| 10552 format %{ "addsd $dst, $src" %} | |
| 10553 ins_cost(150); // XXX | |
| 10554 opcode(0xF2, 0x0F, 0x58); | |
| 10555 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10556 ins_pipe(pipe_slow); | |
| 10557 %} | |
| 10558 | |
| 10559 instruct addD_mem(regD dst, memory src) | |
| 10560 %{ | |
| 10561 match(Set dst (AddD dst (LoadD src))); | |
| 10562 | |
| 10563 format %{ "addsd $dst, $src" %} | |
| 10564 ins_cost(150); // XXX | |
| 10565 opcode(0xF2, 0x0F, 0x58); | |
| 10566 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10567 ins_pipe(pipe_slow); | |
| 10568 %} | |
| 10569 | |
| 10570 instruct addD_imm(regD dst, immD src) | |
| 10571 %{ | |
| 10572 match(Set dst (AddD dst src)); | |
| 10573 | |
| 10574 format %{ "addsd $dst, [$src]" %} | |
| 10575 ins_cost(150); // XXX | |
| 10576 opcode(0xF2, 0x0F, 0x58); | |
| 10577 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immD(dst, src)); | |
| 10578 ins_pipe(pipe_slow); | |
| 10579 %} | |
| 10580 | |
| 10581 instruct subF_reg(regF dst, regF src) | |
| 10582 %{ | |
| 10583 match(Set dst (SubF dst src)); | |
| 10584 | |
| 10585 format %{ "subss $dst, $src" %} | |
| 10586 ins_cost(150); // XXX | |
| 10587 opcode(0xF3, 0x0F, 0x5C); | |
| 10588 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10589 ins_pipe(pipe_slow); | |
| 10590 %} | |
| 10591 | |
| 10592 instruct subF_mem(regF dst, memory src) | |
| 10593 %{ | |
| 10594 match(Set dst (SubF dst (LoadF src))); | |
| 10595 | |
| 10596 format %{ "subss $dst, $src" %} | |
| 10597 ins_cost(150); // XXX | |
| 10598 opcode(0xF3, 0x0F, 0x5C); | |
| 10599 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10600 ins_pipe(pipe_slow); | |
| 10601 %} | |
| 10602 | |
| 10603 instruct subF_imm(regF dst, immF src) | |
| 10604 %{ | |
| 10605 match(Set dst (SubF dst src)); | |
| 10606 | |
| 10607 format %{ "subss $dst, [$src]" %} | |
| 10608 ins_cost(150); // XXX | |
| 10609 opcode(0xF3, 0x0F, 0x5C); | |
| 10610 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immF(dst, src)); | |
| 10611 ins_pipe(pipe_slow); | |
| 10612 %} | |
| 10613 | |
| 10614 instruct subD_reg(regD dst, regD src) | |
| 10615 %{ | |
| 10616 match(Set dst (SubD dst src)); | |
| 10617 | |
| 10618 format %{ "subsd $dst, $src" %} | |
| 10619 ins_cost(150); // XXX | |
| 10620 opcode(0xF2, 0x0F, 0x5C); | |
| 10621 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10622 ins_pipe(pipe_slow); | |
| 10623 %} | |
| 10624 | |
| 10625 instruct subD_mem(regD dst, memory src) | |
| 10626 %{ | |
| 10627 match(Set dst (SubD dst (LoadD src))); | |
| 10628 | |
| 10629 format %{ "subsd $dst, $src" %} | |
| 10630 ins_cost(150); // XXX | |
| 10631 opcode(0xF2, 0x0F, 0x5C); | |
| 10632 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10633 ins_pipe(pipe_slow); | |
| 10634 %} | |
| 10635 | |
| 10636 instruct subD_imm(regD dst, immD src) | |
| 10637 %{ | |
| 10638 match(Set dst (SubD dst src)); | |
| 10639 | |
| 10640 format %{ "subsd $dst, [$src]" %} | |
| 10641 ins_cost(150); // XXX | |
| 10642 opcode(0xF2, 0x0F, 0x5C); | |
| 10643 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immD(dst, src)); | |
| 10644 ins_pipe(pipe_slow); | |
| 10645 %} | |
| 10646 | |
| 10647 instruct mulF_reg(regF dst, regF src) | |
| 10648 %{ | |
| 10649 match(Set dst (MulF dst src)); | |
| 10650 | |
| 10651 format %{ "mulss $dst, $src" %} | |
| 10652 ins_cost(150); // XXX | |
| 10653 opcode(0xF3, 0x0F, 0x59); | |
| 10654 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10655 ins_pipe(pipe_slow); | |
| 10656 %} | |
| 10657 | |
| 10658 instruct mulF_mem(regF dst, memory src) | |
| 10659 %{ | |
| 10660 match(Set dst (MulF dst (LoadF src))); | |
| 10661 | |
| 10662 format %{ "mulss $dst, $src" %} | |
| 10663 ins_cost(150); // XXX | |
| 10664 opcode(0xF3, 0x0F, 0x59); | |
| 10665 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10666 ins_pipe(pipe_slow); | |
| 10667 %} | |
| 10668 | |
| 10669 instruct mulF_imm(regF dst, immF src) | |
| 10670 %{ | |
| 10671 match(Set dst (MulF dst src)); | |
| 10672 | |
| 10673 format %{ "mulss $dst, [$src]" %} | |
| 10674 ins_cost(150); // XXX | |
| 10675 opcode(0xF3, 0x0F, 0x59); | |
| 10676 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immF(dst, src)); | |
| 10677 ins_pipe(pipe_slow); | |
| 10678 %} | |
| 10679 | |
| 10680 instruct mulD_reg(regD dst, regD src) | |
| 10681 %{ | |
| 10682 match(Set dst (MulD dst src)); | |
| 10683 | |
| 10684 format %{ "mulsd $dst, $src" %} | |
| 10685 ins_cost(150); // XXX | |
| 10686 opcode(0xF2, 0x0F, 0x59); | |
| 10687 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10688 ins_pipe(pipe_slow); | |
| 10689 %} | |
| 10690 | |
| 10691 instruct mulD_mem(regD dst, memory src) | |
| 10692 %{ | |
| 10693 match(Set dst (MulD dst (LoadD src))); | |
| 10694 | |
| 10695 format %{ "mulsd $dst, $src" %} | |
| 10696 ins_cost(150); // XXX | |
| 10697 opcode(0xF2, 0x0F, 0x59); | |
| 10698 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10699 ins_pipe(pipe_slow); | |
| 10700 %} | |
| 10701 | |
| 10702 instruct mulD_imm(regD dst, immD src) | |
| 10703 %{ | |
| 10704 match(Set dst (MulD dst src)); | |
| 10705 | |
| 10706 format %{ "mulsd $dst, [$src]" %} | |
| 10707 ins_cost(150); // XXX | |
| 10708 opcode(0xF2, 0x0F, 0x59); | |
| 10709 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immD(dst, src)); | |
| 10710 ins_pipe(pipe_slow); | |
| 10711 %} | |
| 10712 | |
| 10713 instruct divF_reg(regF dst, regF src) | |
| 10714 %{ | |
| 10715 match(Set dst (DivF dst src)); | |
| 10716 | |
| 10717 format %{ "divss $dst, $src" %} | |
| 10718 ins_cost(150); // XXX | |
| 10719 opcode(0xF3, 0x0F, 0x5E); | |
| 10720 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10721 ins_pipe(pipe_slow); | |
| 10722 %} | |
| 10723 | |
| 10724 instruct divF_mem(regF dst, memory src) | |
| 10725 %{ | |
| 10726 match(Set dst (DivF dst (LoadF src))); | |
| 10727 | |
| 10728 format %{ "divss $dst, $src" %} | |
| 10729 ins_cost(150); // XXX | |
| 10730 opcode(0xF3, 0x0F, 0x5E); | |
| 10731 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10732 ins_pipe(pipe_slow); | |
| 10733 %} | |
| 10734 | |
| 10735 instruct divF_imm(regF dst, immF src) | |
| 10736 %{ | |
| 10737 match(Set dst (DivF dst src)); | |
| 10738 | |
| 10739 format %{ "divss $dst, [$src]" %} | |
| 10740 ins_cost(150); // XXX | |
| 10741 opcode(0xF3, 0x0F, 0x5E); | |
| 10742 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immF(dst, src)); | |
| 10743 ins_pipe(pipe_slow); | |
| 10744 %} | |
| 10745 | |
| 10746 instruct divD_reg(regD dst, regD src) | |
| 10747 %{ | |
| 10748 match(Set dst (DivD dst src)); | |
| 10749 | |
| 10750 format %{ "divsd $dst, $src" %} | |
| 10751 ins_cost(150); // XXX | |
| 10752 opcode(0xF2, 0x0F, 0x5E); | |
| 10753 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10754 ins_pipe(pipe_slow); | |
| 10755 %} | |
| 10756 | |
| 10757 instruct divD_mem(regD dst, memory src) | |
| 10758 %{ | |
| 10759 match(Set dst (DivD dst (LoadD src))); | |
| 10760 | |
| 10761 format %{ "divsd $dst, $src" %} | |
| 10762 ins_cost(150); // XXX | |
| 10763 opcode(0xF2, 0x0F, 0x5E); | |
| 10764 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10765 ins_pipe(pipe_slow); | |
| 10766 %} | |
| 10767 | |
| 10768 instruct divD_imm(regD dst, immD src) | |
| 10769 %{ | |
| 10770 match(Set dst (DivD dst src)); | |
| 10771 | |
| 10772 format %{ "divsd $dst, [$src]" %} | |
| 10773 ins_cost(150); // XXX | |
| 10774 opcode(0xF2, 0x0F, 0x5E); | |
| 10775 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immD(dst, src)); | |
| 10776 ins_pipe(pipe_slow); | |
| 10777 %} | |
| 10778 | |
| 10779 instruct sqrtF_reg(regF dst, regF src) | |
| 10780 %{ | |
| 10781 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); | |
| 10782 | |
| 10783 format %{ "sqrtss $dst, $src" %} | |
| 10784 ins_cost(150); // XXX | |
| 10785 opcode(0xF3, 0x0F, 0x51); | |
| 10786 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10787 ins_pipe(pipe_slow); | |
| 10788 %} | |
| 10789 | |
| 10790 instruct sqrtF_mem(regF dst, memory src) | |
| 10791 %{ | |
| 10792 match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF src))))); | |
| 10793 | |
| 10794 format %{ "sqrtss $dst, $src" %} | |
| 10795 ins_cost(150); // XXX | |
| 10796 opcode(0xF3, 0x0F, 0x51); | |
| 10797 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10798 ins_pipe(pipe_slow); | |
| 10799 %} | |
| 10800 | |
| 10801 instruct sqrtF_imm(regF dst, immF src) | |
| 10802 %{ | |
| 10803 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); | |
| 10804 | |
| 10805 format %{ "sqrtss $dst, [$src]" %} | |
| 10806 ins_cost(150); // XXX | |
| 10807 opcode(0xF3, 0x0F, 0x51); | |
| 10808 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immF(dst, src)); | |
| 10809 ins_pipe(pipe_slow); | |
| 10810 %} | |
| 10811 | |
| 10812 instruct sqrtD_reg(regD dst, regD src) | |
| 10813 %{ | |
| 10814 match(Set dst (SqrtD src)); | |
| 10815 | |
| 10816 format %{ "sqrtsd $dst, $src" %} | |
| 10817 ins_cost(150); // XXX | |
| 10818 opcode(0xF2, 0x0F, 0x51); | |
| 10819 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10820 ins_pipe(pipe_slow); | |
| 10821 %} | |
| 10822 | |
| 10823 instruct sqrtD_mem(regD dst, memory src) | |
| 10824 %{ | |
| 10825 match(Set dst (SqrtD (LoadD src))); | |
| 10826 | |
| 10827 format %{ "sqrtsd $dst, $src" %} | |
| 10828 ins_cost(150); // XXX | |
| 10829 opcode(0xF2, 0x0F, 0x51); | |
| 10830 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10831 ins_pipe(pipe_slow); | |
| 10832 %} | |
| 10833 | |
| 10834 instruct sqrtD_imm(regD dst, immD src) | |
| 10835 %{ | |
| 10836 match(Set dst (SqrtD src)); | |
| 10837 | |
| 10838 format %{ "sqrtsd $dst, [$src]" %} | |
| 10839 ins_cost(150); // XXX | |
| 10840 opcode(0xF2, 0x0F, 0x51); | |
| 10841 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immD(dst, src)); | |
| 10842 ins_pipe(pipe_slow); | |
| 10843 %} | |
| 10844 | |
| 10845 instruct absF_reg(regF dst) | |
| 10846 %{ | |
| 10847 match(Set dst (AbsF dst)); | |
| 10848 | |
| 10849 format %{ "andps $dst, [0x7fffffff]\t# abs float by sign masking" %} | |
| 10850 ins_encode(absF_encoding(dst)); | |
| 10851 ins_pipe(pipe_slow); | |
| 10852 %} | |
| 10853 | |
| 10854 instruct absD_reg(regD dst) | |
| 10855 %{ | |
| 10856 match(Set dst (AbsD dst)); | |
| 10857 | |
| 10858 format %{ "andpd $dst, [0x7fffffffffffffff]\t" | |
| 10859 "# abs double by sign masking" %} | |
| 10860 ins_encode(absD_encoding(dst)); | |
| 10861 ins_pipe(pipe_slow); | |
| 10862 %} | |
| 10863 | |
| 10864 instruct negF_reg(regF dst) | |
| 10865 %{ | |
| 10866 match(Set dst (NegF dst)); | |
| 10867 | |
| 10868 format %{ "xorps $dst, [0x80000000]\t# neg float by sign flipping" %} | |
| 10869 ins_encode(negF_encoding(dst)); | |
| 10870 ins_pipe(pipe_slow); | |
| 10871 %} | |
| 10872 | |
| 10873 instruct negD_reg(regD dst) | |
| 10874 %{ | |
| 10875 match(Set dst (NegD dst)); | |
| 10876 | |
| 10877 format %{ "xorpd $dst, [0x8000000000000000]\t" | |
| 10878 "# neg double by sign flipping" %} | |
| 10879 ins_encode(negD_encoding(dst)); | |
| 10880 ins_pipe(pipe_slow); | |
| 10881 %} | |
| 10882 | |
| 10883 // -----------Trig and Trancendental Instructions------------------------------ | |
| 10884 instruct cosD_reg(regD dst) %{ | |
| 10885 match(Set dst (CosD dst)); | |
| 10886 | |
| 10887 format %{ "dcos $dst\n\t" %} | |
| 10888 opcode(0xD9, 0xFF); | |
| 10889 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) ); | |
| 10890 ins_pipe( pipe_slow ); | |
| 10891 %} | |
| 10892 | |
| 10893 instruct sinD_reg(regD dst) %{ | |
| 10894 match(Set dst (SinD dst)); | |
| 10895 | |
| 10896 format %{ "dsin $dst\n\t" %} | |
| 10897 opcode(0xD9, 0xFE); | |
| 10898 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) ); | |
| 10899 ins_pipe( pipe_slow ); | |
| 10900 %} | |
| 10901 | |
| 10902 instruct tanD_reg(regD dst) %{ | |
| 10903 match(Set dst (TanD dst)); | |
| 10904 | |
| 10905 format %{ "dtan $dst\n\t" %} | |
| 10906 ins_encode( Push_SrcXD(dst), | |
| 10907 Opcode(0xD9), Opcode(0xF2), //fptan | |
| 10908 Opcode(0xDD), Opcode(0xD8), //fstp st | |
| 10909 Push_ResultXD(dst) ); | |
| 10910 ins_pipe( pipe_slow ); | |
| 10911 %} | |
| 10912 | |
| 10913 instruct log10D_reg(regD dst) %{ | |
| 10914 // The source and result Double operands in XMM registers | |
| 10915 match(Set dst (Log10D dst)); | |
| 10916 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number | |
| 10917 // fyl2x ; compute log_10(2) * log_2(x) | |
| 10918 format %{ "fldlg2\t\t\t#Log10\n\t" | |
| 10919 "fyl2x\t\t\t# Q=Log10*Log_2(x)\n\t" | |
| 10920 %} | |
| 10921 ins_encode(Opcode(0xD9), Opcode(0xEC), // fldlg2 | |
| 10922 Push_SrcXD(dst), | |
| 10923 Opcode(0xD9), Opcode(0xF1), // fyl2x | |
| 10924 Push_ResultXD(dst)); | |
| 10925 | |
| 10926 ins_pipe( pipe_slow ); | |
| 10927 %} | |
| 10928 | |
| 10929 instruct logD_reg(regD dst) %{ | |
| 10930 // The source and result Double operands in XMM registers | |
| 10931 match(Set dst (LogD dst)); | |
| 10932 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number | |
| 10933 // fyl2x ; compute log_e(2) * log_2(x) | |
| 10934 format %{ "fldln2\t\t\t#Log_e\n\t" | |
| 10935 "fyl2x\t\t\t# Q=Log_e*Log_2(x)\n\t" | |
| 10936 %} | |
| 10937 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 | |
| 10938 Push_SrcXD(dst), | |
| 10939 Opcode(0xD9), Opcode(0xF1), // fyl2x | |
| 10940 Push_ResultXD(dst)); | |
| 10941 ins_pipe( pipe_slow ); | |
| 10942 %} | |
| 10943 | |
| 10944 | |
| 10945 | |
| 10946 //----------Arithmetic Conversion Instructions--------------------------------- | |
| 10947 | |
| 10948 instruct roundFloat_nop(regF dst) | |
| 10949 %{ | |
| 10950 match(Set dst (RoundFloat dst)); | |
| 10951 | |
| 10952 ins_cost(0); | |
| 10953 ins_encode(); | |
| 10954 ins_pipe(empty); | |
| 10955 %} | |
| 10956 | |
| 10957 instruct roundDouble_nop(regD dst) | |
| 10958 %{ | |
| 10959 match(Set dst (RoundDouble dst)); | |
| 10960 | |
| 10961 ins_cost(0); | |
| 10962 ins_encode(); | |
| 10963 ins_pipe(empty); | |
| 10964 %} | |
| 10965 | |
| 10966 instruct convF2D_reg_reg(regD dst, regF src) | |
| 10967 %{ | |
| 10968 match(Set dst (ConvF2D src)); | |
| 10969 | |
| 10970 format %{ "cvtss2sd $dst, $src" %} | |
| 10971 opcode(0xF3, 0x0F, 0x5A); | |
| 10972 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10973 ins_pipe(pipe_slow); // XXX | |
| 10974 %} | |
| 10975 | |
| 10976 instruct convF2D_reg_mem(regD dst, memory src) | |
| 10977 %{ | |
| 10978 match(Set dst (ConvF2D (LoadF src))); | |
| 10979 | |
| 10980 format %{ "cvtss2sd $dst, $src" %} | |
| 10981 opcode(0xF3, 0x0F, 0x5A); | |
| 10982 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10983 ins_pipe(pipe_slow); // XXX | |
| 10984 %} | |
| 10985 | |
| 10986 instruct convD2F_reg_reg(regF dst, regD src) | |
| 10987 %{ | |
| 10988 match(Set dst (ConvD2F src)); | |
| 10989 | |
| 10990 format %{ "cvtsd2ss $dst, $src" %} | |
| 10991 opcode(0xF2, 0x0F, 0x5A); | |
| 10992 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10993 ins_pipe(pipe_slow); // XXX | |
| 10994 %} | |
| 10995 | |
| 10996 instruct convD2F_reg_mem(regF dst, memory src) | |
| 10997 %{ | |
| 10998 match(Set dst (ConvD2F (LoadD src))); | |
| 10999 | |
| 11000 format %{ "cvtsd2ss $dst, $src" %} | |
| 11001 opcode(0xF2, 0x0F, 0x5A); | |
| 11002 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 11003 ins_pipe(pipe_slow); // XXX | |
| 11004 %} | |
| 11005 | |
| 11006 // XXX do mem variants | |
| 11007 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr) | |
| 11008 %{ | |
| 11009 match(Set dst (ConvF2I src)); | |
| 11010 effect(KILL cr); | |
| 11011 | |
| 11012 format %{ "cvttss2sil $dst, $src\t# f2i\n\t" | |
| 11013 "cmpl $dst, #0x80000000\n\t" | |
| 11014 "jne,s done\n\t" | |
| 11015 "subq rsp, #8\n\t" | |
| 11016 "movss [rsp], $src\n\t" | |
| 11017 "call f2i_fixup\n\t" | |
| 11018 "popq $dst\n" | |
| 11019 "done: "%} | |
| 11020 opcode(0xF3, 0x0F, 0x2C); | |
| 11021 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src), | |
| 11022 f2i_fixup(dst, src)); | |
| 11023 ins_pipe(pipe_slow); | |
| 11024 %} | |
| 11025 | |
| 11026 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr) | |
| 11027 %{ | |
| 11028 match(Set dst (ConvF2L src)); | |
| 11029 effect(KILL cr); | |
| 11030 | |
| 11031 format %{ "cvttss2siq $dst, $src\t# f2l\n\t" | |
| 11032 "cmpq $dst, [0x8000000000000000]\n\t" | |
| 11033 "jne,s done\n\t" | |
| 11034 "subq rsp, #8\n\t" | |
| 11035 "movss [rsp], $src\n\t" | |
| 11036 "call f2l_fixup\n\t" | |
| 11037 "popq $dst\n" | |
| 11038 "done: "%} | |
| 11039 opcode(0xF3, 0x0F, 0x2C); | |
| 11040 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src), | |
| 11041 f2l_fixup(dst, src)); | |
| 11042 ins_pipe(pipe_slow); | |
| 11043 %} | |
| 11044 | |
| 11045 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr) | |
| 11046 %{ | |
| 11047 match(Set dst (ConvD2I src)); | |
| 11048 effect(KILL cr); | |
| 11049 | |
| 11050 format %{ "cvttsd2sil $dst, $src\t# d2i\n\t" | |
| 11051 "cmpl $dst, #0x80000000\n\t" | |
| 11052 "jne,s done\n\t" | |
| 11053 "subq rsp, #8\n\t" | |
| 11054 "movsd [rsp], $src\n\t" | |
| 11055 "call d2i_fixup\n\t" | |
| 11056 "popq $dst\n" | |
| 11057 "done: "%} | |
| 11058 opcode(0xF2, 0x0F, 0x2C); | |
| 11059 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src), | |
| 11060 d2i_fixup(dst, src)); | |
| 11061 ins_pipe(pipe_slow); | |
| 11062 %} | |
| 11063 | |
| 11064 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr) | |
| 11065 %{ | |
| 11066 match(Set dst (ConvD2L src)); | |
| 11067 effect(KILL cr); | |
| 11068 | |
| 11069 format %{ "cvttsd2siq $dst, $src\t# d2l\n\t" | |
| 11070 "cmpq $dst, [0x8000000000000000]\n\t" | |
| 11071 "jne,s done\n\t" | |
| 11072 "subq rsp, #8\n\t" | |
| 11073 "movsd [rsp], $src\n\t" | |
| 11074 "call d2l_fixup\n\t" | |
| 11075 "popq $dst\n" | |
| 11076 "done: "%} | |
| 11077 opcode(0xF2, 0x0F, 0x2C); | |
| 11078 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src), | |
| 11079 d2l_fixup(dst, src)); | |
| 11080 ins_pipe(pipe_slow); | |
| 11081 %} | |
| 11082 | |
| 11083 instruct convI2F_reg_reg(regF dst, rRegI src) | |
| 11084 %{ | |
| 71 | 11085 predicate(!UseXmmI2F); |
| 0 | 11086 match(Set dst (ConvI2F src)); |
| 11087 | |
| 11088 format %{ "cvtsi2ssl $dst, $src\t# i2f" %} | |
| 11089 opcode(0xF3, 0x0F, 0x2A); | |
| 11090 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 11091 ins_pipe(pipe_slow); // XXX | |
| 11092 %} | |
| 11093 | |
| 11094 instruct convI2F_reg_mem(regF dst, memory src) | |
| 11095 %{ | |
| 11096 match(Set dst (ConvI2F (LoadI src))); | |
| 11097 | |
| 11098 format %{ "cvtsi2ssl $dst, $src\t# i2f" %} | |
| 11099 opcode(0xF3, 0x0F, 0x2A); | |
| 11100 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 11101 ins_pipe(pipe_slow); // XXX | |
| 11102 %} | |
| 11103 | |
| 11104 instruct convI2D_reg_reg(regD dst, rRegI src) | |
| 11105 %{ | |
| 71 | 11106 predicate(!UseXmmI2D); |
| 0 | 11107 match(Set dst (ConvI2D src)); |
| 11108 | |
| 11109 format %{ "cvtsi2sdl $dst, $src\t# i2d" %} | |
| 11110 opcode(0xF2, 0x0F, 0x2A); | |
| 11111 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 11112 ins_pipe(pipe_slow); // XXX | |
| 11113 %} | |
| 11114 | |
| 11115 instruct convI2D_reg_mem(regD dst, memory src) | |
| 11116 %{ | |
| 11117 match(Set dst (ConvI2D (LoadI src))); | |
| 11118 | |
| 11119 format %{ "cvtsi2sdl $dst, $src\t# i2d" %} | |
| 11120 opcode(0xF2, 0x0F, 0x2A); | |
| 11121 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 11122 ins_pipe(pipe_slow); // XXX | |
| 11123 %} | |
| 11124 | |
| 71 | 11125 instruct convXI2F_reg(regF dst, rRegI src) |
| 11126 %{ | |
| 11127 predicate(UseXmmI2F); | |
| 11128 match(Set dst (ConvI2F src)); | |
| 11129 | |
| 11130 format %{ "movdl $dst, $src\n\t" | |
| 11131 "cvtdq2psl $dst, $dst\t# i2f" %} | |
| 11132 ins_encode %{ | |
| 11133 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 11134 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister); | |
| 11135 %} | |
| 11136 ins_pipe(pipe_slow); // XXX | |
| 11137 %} | |
| 11138 | |
| 11139 instruct convXI2D_reg(regD dst, rRegI src) | |
| 11140 %{ | |
| 11141 predicate(UseXmmI2D); | |
| 11142 match(Set dst (ConvI2D src)); | |
| 11143 | |
| 11144 format %{ "movdl $dst, $src\n\t" | |
| 11145 "cvtdq2pdl $dst, $dst\t# i2d" %} | |
| 11146 ins_encode %{ | |
| 11147 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 11148 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister); | |
| 11149 %} | |
| 11150 ins_pipe(pipe_slow); // XXX | |
| 11151 %} | |
| 11152 | |
| 0 | 11153 instruct convL2F_reg_reg(regF dst, rRegL src) |
| 11154 %{ | |
| 11155 match(Set dst (ConvL2F src)); | |
| 11156 | |
| 11157 format %{ "cvtsi2ssq $dst, $src\t# l2f" %} | |
| 11158 opcode(0xF3, 0x0F, 0x2A); | |
| 11159 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 11160 ins_pipe(pipe_slow); // XXX | |
| 11161 %} | |
| 11162 | |
| 11163 instruct convL2F_reg_mem(regF dst, memory src) | |
| 11164 %{ | |
| 11165 match(Set dst (ConvL2F (LoadL src))); | |
| 11166 | |
| 11167 format %{ "cvtsi2ssq $dst, $src\t# l2f" %} | |
| 11168 opcode(0xF3, 0x0F, 0x2A); | |
| 11169 ins_encode(OpcP, REX_reg_mem_wide(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 11170 ins_pipe(pipe_slow); // XXX | |
| 11171 %} | |
| 11172 | |
| 11173 instruct convL2D_reg_reg(regD dst, rRegL src) | |
| 11174 %{ | |
| 11175 match(Set dst (ConvL2D src)); | |
| 11176 | |
| 11177 format %{ "cvtsi2sdq $dst, $src\t# l2d" %} | |
| 11178 opcode(0xF2, 0x0F, 0x2A); | |
| 11179 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 11180 ins_pipe(pipe_slow); // XXX | |
| 11181 %} | |
| 11182 | |
| 11183 instruct convL2D_reg_mem(regD dst, memory src) | |
| 11184 %{ | |
| 11185 match(Set dst (ConvL2D (LoadL src))); | |
| 11186 | |
| 11187 format %{ "cvtsi2sdq $dst, $src\t# l2d" %} | |
| 11188 opcode(0xF2, 0x0F, 0x2A); | |
| 11189 ins_encode(OpcP, REX_reg_mem_wide(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 11190 ins_pipe(pipe_slow); // XXX | |
| 11191 %} | |
| 11192 | |
| 11193 instruct convI2L_reg_reg(rRegL dst, rRegI src) | |
| 11194 %{ | |
| 11195 match(Set dst (ConvI2L src)); | |
| 11196 | |
| 11197 ins_cost(125); | |
| 11198 format %{ "movslq $dst, $src\t# i2l" %} | |
| 11199 opcode(0x63); // needs REX.W | |
| 11200 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src)); | |
| 11201 ins_pipe(ialu_reg_reg); | |
| 11202 %} | |
| 11203 | |
| 11204 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src) | |
| 11205 // %{ | |
| 11206 // match(Set dst (ConvI2L src)); | |
| 11207 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 && | |
| 11208 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0); | |
| 11209 // predicate(((const TypeNode*) n)->type()->is_long()->_hi == | |
| 11210 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi && | |
| 11211 // ((const TypeNode*) n)->type()->is_long()->_lo == | |
| 11212 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo); | |
| 11213 | |
| 11214 // format %{ "movl $dst, $src\t# unsigned i2l" %} | |
| 11215 // ins_encode(enc_copy(dst, src)); | |
| 11216 // // opcode(0x63); // needs REX.W | |
| 11217 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src)); | |
| 11218 // ins_pipe(ialu_reg_reg); | |
| 11219 // %} | |
| 11220 | |
| 11221 // Zero-extend convert int to long | |
| 11222 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask) | |
| 11223 %{ | |
| 11224 match(Set dst (AndL (ConvI2L src) mask)); | |
| 11225 | |
| 11226 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %} | |
| 11227 ins_encode(enc_copy(dst, src)); | |
| 11228 ins_pipe(ialu_reg_reg); | |
| 11229 %} | |
| 11230 | |
| 11231 // Zero-extend convert int to long | |
| 11232 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask) | |
| 11233 %{ | |
| 11234 match(Set dst (AndL (ConvI2L (LoadI src)) mask)); | |
| 11235 | |
| 11236 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %} | |
| 11237 opcode(0x8B); | |
| 11238 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 11239 ins_pipe(ialu_reg_mem); | |
| 11240 %} | |
| 11241 | |
| 11242 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask) | |
| 11243 %{ | |
| 11244 match(Set dst (AndL src mask)); | |
| 11245 | |
| 11246 format %{ "movl $dst, $src\t# zero-extend long" %} | |
| 11247 ins_encode(enc_copy_always(dst, src)); | |
| 11248 ins_pipe(ialu_reg_reg); | |
| 11249 %} | |
| 11250 | |
| 11251 instruct convL2I_reg_reg(rRegI dst, rRegL src) | |
| 11252 %{ | |
| 11253 match(Set dst (ConvL2I src)); | |
| 11254 | |
| 11255 format %{ "movl $dst, $src\t# l2i" %} | |
| 11256 ins_encode(enc_copy_always(dst, src)); | |
| 11257 ins_pipe(ialu_reg_reg); | |
| 11258 %} | |
| 11259 | |
| 11260 | |
| 11261 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{ | |
| 11262 match(Set dst (MoveF2I src)); | |
| 11263 effect(DEF dst, USE src); | |
| 11264 | |
| 11265 ins_cost(125); | |
| 11266 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %} | |
| 11267 opcode(0x8B); | |
| 11268 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 11269 ins_pipe(ialu_reg_mem); | |
| 11270 %} | |
| 11271 | |
| 11272 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ | |
| 11273 match(Set dst (MoveI2F src)); | |
| 11274 effect(DEF dst, USE src); | |
| 11275 | |
| 11276 ins_cost(125); | |
| 11277 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %} | |
| 11278 opcode(0xF3, 0x0F, 0x10); | |
| 11279 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 11280 ins_pipe(pipe_slow); | |
| 11281 %} | |
| 11282 | |
| 11283 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{ | |
| 11284 match(Set dst (MoveD2L src)); | |
| 11285 effect(DEF dst, USE src); | |
| 11286 | |
| 11287 ins_cost(125); | |
| 11288 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %} | |
| 11289 opcode(0x8B); | |
| 11290 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 11291 ins_pipe(ialu_reg_mem); | |
| 11292 %} | |
| 11293 | |
| 11294 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{ | |
| 11295 predicate(!UseXmmLoadAndClearUpper); | |
| 11296 match(Set dst (MoveL2D src)); | |
| 11297 effect(DEF dst, USE src); | |
| 11298 | |
| 11299 ins_cost(125); | |
| 11300 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %} | |
| 11301 opcode(0x66, 0x0F, 0x12); | |
| 11302 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 11303 ins_pipe(pipe_slow); | |
| 11304 %} | |
| 11305 | |
| 11306 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ | |
| 11307 predicate(UseXmmLoadAndClearUpper); | |
| 11308 match(Set dst (MoveL2D src)); | |
| 11309 effect(DEF dst, USE src); | |
| 11310 | |
| 11311 ins_cost(125); | |
| 11312 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %} | |
| 11313 opcode(0xF2, 0x0F, 0x10); | |
| 11314 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 11315 ins_pipe(pipe_slow); | |
| 11316 %} | |
| 11317 | |
| 11318 | |
| 11319 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ | |
| 11320 match(Set dst (MoveF2I src)); | |
| 11321 effect(DEF dst, USE src); | |
| 11322 | |
| 11323 ins_cost(95); // XXX | |
| 11324 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %} | |
| 11325 opcode(0xF3, 0x0F, 0x11); | |
| 11326 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst)); | |
| 11327 ins_pipe(pipe_slow); | |
| 11328 %} | |
| 11329 | |
| 11330 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{ | |
| 11331 match(Set dst (MoveI2F src)); | |
| 11332 effect(DEF dst, USE src); | |
| 11333 | |
| 11334 ins_cost(100); | |
| 11335 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %} | |
| 11336 opcode(0x89); | |
| 11337 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 11338 ins_pipe( ialu_mem_reg ); | |
| 11339 %} | |
| 11340 | |
| 11341 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ | |
| 11342 match(Set dst (MoveD2L src)); | |
| 11343 effect(DEF dst, USE src); | |
| 11344 | |
| 11345 ins_cost(95); // XXX | |
| 11346 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %} | |
| 11347 opcode(0xF2, 0x0F, 0x11); | |
| 11348 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst)); | |
| 11349 ins_pipe(pipe_slow); | |
| 11350 %} | |
| 11351 | |
| 11352 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{ | |
| 11353 match(Set dst (MoveL2D src)); | |
| 11354 effect(DEF dst, USE src); | |
| 11355 | |
| 11356 ins_cost(100); | |
| 11357 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %} | |
| 11358 opcode(0x89); | |
| 11359 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 11360 ins_pipe(ialu_mem_reg); | |
| 11361 %} | |
| 11362 | |
| 11363 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{ | |
| 11364 match(Set dst (MoveF2I src)); | |
| 11365 effect(DEF dst, USE src); | |
| 11366 ins_cost(85); | |
| 11367 format %{ "movd $dst,$src\t# MoveF2I" %} | |
| 11368 ins_encode %{ __ movdl($dst$$Register, $src$$XMMRegister); %} | |
| 11369 ins_pipe( pipe_slow ); | |
| 11370 %} | |
| 11371 | |
| 11372 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{ | |
| 11373 match(Set dst (MoveD2L src)); | |
| 11374 effect(DEF dst, USE src); | |
| 11375 ins_cost(85); | |
| 11376 format %{ "movd $dst,$src\t# MoveD2L" %} | |
| 11377 ins_encode %{ __ movdq($dst$$Register, $src$$XMMRegister); %} | |
| 11378 ins_pipe( pipe_slow ); | |
| 11379 %} | |
| 11380 | |
| 11381 // The next instructions have long latency and use Int unit. Set high cost. | |
| 11382 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{ | |
| 11383 match(Set dst (MoveI2F src)); | |
| 11384 effect(DEF dst, USE src); | |
| 11385 ins_cost(300); | |
| 11386 format %{ "movd $dst,$src\t# MoveI2F" %} | |
| 11387 ins_encode %{ __ movdl($dst$$XMMRegister, $src$$Register); %} | |
| 11388 ins_pipe( pipe_slow ); | |
| 11389 %} | |
| 11390 | |
| 11391 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{ | |
| 11392 match(Set dst (MoveL2D src)); | |
| 11393 effect(DEF dst, USE src); | |
| 11394 ins_cost(300); | |
| 11395 format %{ "movd $dst,$src\t# MoveL2D" %} | |
| 11396 ins_encode %{ __ movdq($dst$$XMMRegister, $src$$Register); %} | |
| 11397 ins_pipe( pipe_slow ); | |
| 11398 %} | |
| 11399 | |
| 11400 // Replicate scalar to packed byte (1 byte) values in xmm | |
| 11401 instruct Repl8B_reg(regD dst, regD src) %{ | |
| 11402 match(Set dst (Replicate8B src)); | |
| 11403 format %{ "MOVDQA $dst,$src\n\t" | |
| 11404 "PUNPCKLBW $dst,$dst\n\t" | |
| 11405 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %} | |
| 11406 ins_encode( pshufd_8x8(dst, src)); | |
| 11407 ins_pipe( pipe_slow ); | |
| 11408 %} | |
| 11409 | |
| 11410 // Replicate scalar to packed byte (1 byte) values in xmm | |
| 11411 instruct Repl8B_rRegI(regD dst, rRegI src) %{ | |
| 11412 match(Set dst (Replicate8B src)); | |
| 11413 format %{ "MOVD $dst,$src\n\t" | |
| 11414 "PUNPCKLBW $dst,$dst\n\t" | |
| 11415 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %} | |
| 11416 ins_encode( mov_i2x(dst, src), pshufd_8x8(dst, dst)); | |
| 11417 ins_pipe( pipe_slow ); | |
| 11418 %} | |
| 11419 | |
| 11420 // Replicate scalar zero to packed byte (1 byte) values in xmm | |
| 11421 instruct Repl8B_immI0(regD dst, immI0 zero) %{ | |
| 11422 match(Set dst (Replicate8B zero)); | |
| 11423 format %{ "PXOR $dst,$dst\t! replicate8B" %} | |
| 11424 ins_encode( pxor(dst, dst)); | |
| 11425 ins_pipe( fpu_reg_reg ); | |
| 11426 %} | |
| 11427 | |
| 11428 // Replicate scalar to packed shore (2 byte) values in xmm | |
| 11429 instruct Repl4S_reg(regD dst, regD src) %{ | |
| 11430 match(Set dst (Replicate4S src)); | |
| 11431 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %} | |
| 11432 ins_encode( pshufd_4x16(dst, src)); | |
| 11433 ins_pipe( fpu_reg_reg ); | |
| 11434 %} | |
| 11435 | |
| 11436 // Replicate scalar to packed shore (2 byte) values in xmm | |
| 11437 instruct Repl4S_rRegI(regD dst, rRegI src) %{ | |
| 11438 match(Set dst (Replicate4S src)); | |
| 11439 format %{ "MOVD $dst,$src\n\t" | |
| 11440 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %} | |
| 11441 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst)); | |
| 11442 ins_pipe( fpu_reg_reg ); | |
| 11443 %} | |
| 11444 | |
| 11445 // Replicate scalar zero to packed short (2 byte) values in xmm | |
| 11446 instruct Repl4S_immI0(regD dst, immI0 zero) %{ | |
| 11447 match(Set dst (Replicate4S zero)); | |
| 11448 format %{ "PXOR $dst,$dst\t! replicate4S" %} | |
| 11449 ins_encode( pxor(dst, dst)); | |
| 11450 ins_pipe( fpu_reg_reg ); | |
| 11451 %} | |
| 11452 | |
| 11453 // Replicate scalar to packed char (2 byte) values in xmm | |
| 11454 instruct Repl4C_reg(regD dst, regD src) %{ | |
| 11455 match(Set dst (Replicate4C src)); | |
| 11456 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %} | |
| 11457 ins_encode( pshufd_4x16(dst, src)); | |
| 11458 ins_pipe( fpu_reg_reg ); | |
| 11459 %} | |
| 11460 | |
| 11461 // Replicate scalar to packed char (2 byte) values in xmm | |
| 11462 instruct Repl4C_rRegI(regD dst, rRegI src) %{ | |
| 11463 match(Set dst (Replicate4C src)); | |
| 11464 format %{ "MOVD $dst,$src\n\t" | |
| 11465 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %} | |
| 11466 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst)); | |
| 11467 ins_pipe( fpu_reg_reg ); | |
| 11468 %} | |
| 11469 | |
| 11470 // Replicate scalar zero to packed char (2 byte) values in xmm | |
| 11471 instruct Repl4C_immI0(regD dst, immI0 zero) %{ | |
| 11472 match(Set dst (Replicate4C zero)); | |
| 11473 format %{ "PXOR $dst,$dst\t! replicate4C" %} | |
| 11474 ins_encode( pxor(dst, dst)); | |
| 11475 ins_pipe( fpu_reg_reg ); | |
| 11476 %} | |
| 11477 | |
| 11478 // Replicate scalar to packed integer (4 byte) values in xmm | |
| 11479 instruct Repl2I_reg(regD dst, regD src) %{ | |
| 11480 match(Set dst (Replicate2I src)); | |
| 11481 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %} | |
| 11482 ins_encode( pshufd(dst, src, 0x00)); | |
| 11483 ins_pipe( fpu_reg_reg ); | |
| 11484 %} | |
| 11485 | |
| 11486 // Replicate scalar to packed integer (4 byte) values in xmm | |
| 11487 instruct Repl2I_rRegI(regD dst, rRegI src) %{ | |
| 11488 match(Set dst (Replicate2I src)); | |
| 11489 format %{ "MOVD $dst,$src\n\t" | |
| 11490 "PSHUFD $dst,$dst,0x00\t! replicate2I" %} | |
| 11491 ins_encode( mov_i2x(dst, src), pshufd(dst, dst, 0x00)); | |
| 11492 ins_pipe( fpu_reg_reg ); | |
| 11493 %} | |
| 11494 | |
| 11495 // Replicate scalar zero to packed integer (2 byte) values in xmm | |
| 11496 instruct Repl2I_immI0(regD dst, immI0 zero) %{ | |
| 11497 match(Set dst (Replicate2I zero)); | |
| 11498 format %{ "PXOR $dst,$dst\t! replicate2I" %} | |
| 11499 ins_encode( pxor(dst, dst)); | |
| 11500 ins_pipe( fpu_reg_reg ); | |
| 11501 %} | |
| 11502 | |
| 11503 // Replicate scalar to packed single precision floating point values in xmm | |
| 11504 instruct Repl2F_reg(regD dst, regD src) %{ | |
| 11505 match(Set dst (Replicate2F src)); | |
| 11506 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %} | |
| 11507 ins_encode( pshufd(dst, src, 0xe0)); | |
| 11508 ins_pipe( fpu_reg_reg ); | |
| 11509 %} | |
| 11510 | |
| 11511 // Replicate scalar to packed single precision floating point values in xmm | |
| 11512 instruct Repl2F_regF(regD dst, regF src) %{ | |
| 11513 match(Set dst (Replicate2F src)); | |
| 11514 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %} | |
| 11515 ins_encode( pshufd(dst, src, 0xe0)); | |
| 11516 ins_pipe( fpu_reg_reg ); | |
| 11517 %} | |
| 11518 | |
| 11519 // Replicate scalar to packed single precision floating point values in xmm | |
| 11520 instruct Repl2F_immF0(regD dst, immF0 zero) %{ | |
| 11521 match(Set dst (Replicate2F zero)); | |
| 11522 format %{ "PXOR $dst,$dst\t! replicate2F" %} | |
| 11523 ins_encode( pxor(dst, dst)); | |
| 11524 ins_pipe( fpu_reg_reg ); | |
| 11525 %} | |
| 11526 | |
| 11527 | |
| 11528 // ======================================================================= | |
| 11529 // fast clearing of an array | |
| 11530 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy, | |
| 11531 rFlagsReg cr) | |
| 11532 %{ | |
| 11533 match(Set dummy (ClearArray cnt base)); | |
| 11534 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr); | |
| 11535 | |
| 11536 format %{ "xorl rax, rax\t# ClearArray:\n\t" | |
| 11537 "rep stosq\t# Store rax to *rdi++ while rcx--" %} | |
| 11538 ins_encode(opc_reg_reg(0x33, RAX, RAX), // xorl %eax, %eax | |
| 11539 Opcode(0xF3), Opcode(0x48), Opcode(0xAB)); // rep REX_W stos | |
| 11540 ins_pipe(pipe_slow); | |
| 11541 %} | |
| 11542 | |
| 11543 instruct string_compare(rdi_RegP str1, rsi_RegP str2, rax_RegI tmp1, | |
| 11544 rbx_RegI tmp2, rcx_RegI result, rFlagsReg cr) | |
| 11545 %{ | |
| 11546 match(Set result (StrComp str1 str2)); | |
| 11547 effect(USE_KILL str1, USE_KILL str2, KILL tmp1, KILL tmp2, KILL cr); | |
| 11548 //ins_cost(300); | |
| 11549 | |
| 11550 format %{ "String Compare $str1, $str2 -> $result // XXX KILL RAX, RBX" %} | |
| 11551 ins_encode( enc_String_Compare() ); | |
| 11552 ins_pipe( pipe_slow ); | |
| 11553 %} | |
| 11554 | |
|
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11555 // fast array equals |
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11556 instruct array_equals(rdi_RegP ary1, rsi_RegP ary2, rax_RegI tmp1, |
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11557 rbx_RegI tmp2, rcx_RegI result, rFlagsReg cr) %{ |
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11558 match(Set result (AryEq ary1 ary2)); |
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11559 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL cr); |
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11560 //ins_cost(300); |
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11561 |
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11562 format %{ "Array Equals $ary1,$ary2 -> $result // KILL RAX, RBX" %} |
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11563 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, tmp2, result) ); |
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11564 ins_pipe( pipe_slow ); |
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11565 %} |
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11566 |
| 0 | 11567 //----------Control Flow Instructions------------------------------------------ |
| 11568 // Signed compare Instructions | |
| 11569 | |
| 11570 // XXX more variants!! | |
| 11571 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2) | |
| 11572 %{ | |
| 11573 match(Set cr (CmpI op1 op2)); | |
| 11574 effect(DEF cr, USE op1, USE op2); | |
| 11575 | |
| 11576 format %{ "cmpl $op1, $op2" %} | |
| 11577 opcode(0x3B); /* Opcode 3B /r */ | |
| 11578 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2)); | |
| 11579 ins_pipe(ialu_cr_reg_reg); | |
| 11580 %} | |
| 11581 | |
| 11582 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2) | |
| 11583 %{ | |
| 11584 match(Set cr (CmpI op1 op2)); | |
| 11585 | |
| 11586 format %{ "cmpl $op1, $op2" %} | |
| 11587 opcode(0x81, 0x07); /* Opcode 81 /7 */ | |
| 11588 ins_encode(OpcSErm(op1, op2), Con8or32(op2)); | |
| 11589 ins_pipe(ialu_cr_reg_imm); | |
| 11590 %} | |
| 11591 | |
| 11592 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2) | |
| 11593 %{ | |
| 11594 match(Set cr (CmpI op1 (LoadI op2))); | |
| 11595 | |
| 11596 ins_cost(500); // XXX | |
| 11597 format %{ "cmpl $op1, $op2" %} | |
| 11598 opcode(0x3B); /* Opcode 3B /r */ | |
| 11599 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 11600 ins_pipe(ialu_cr_reg_mem); | |
| 11601 %} | |
| 11602 | |
| 11603 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero) | |
| 11604 %{ | |
| 11605 match(Set cr (CmpI src zero)); | |
| 11606 | |
| 11607 format %{ "testl $src, $src" %} | |
| 11608 opcode(0x85); | |
| 11609 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src)); | |
| 11610 ins_pipe(ialu_cr_reg_imm); | |
| 11611 %} | |
| 11612 | |
| 11613 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero) | |
| 11614 %{ | |
| 11615 match(Set cr (CmpI (AndI src con) zero)); | |
| 11616 | |
| 11617 format %{ "testl $src, $con" %} | |
| 11618 opcode(0xF7, 0x00); | |
| 11619 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con)); | |
| 11620 ins_pipe(ialu_cr_reg_imm); | |
| 11621 %} | |
| 11622 | |
| 11623 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero) | |
| 11624 %{ | |
| 11625 match(Set cr (CmpI (AndI src (LoadI mem)) zero)); | |
| 11626 | |
| 11627 format %{ "testl $src, $mem" %} | |
| 11628 opcode(0x85); | |
| 11629 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
| 11630 ins_pipe(ialu_cr_reg_mem); | |
| 11631 %} | |
| 11632 | |
| 11633 // Unsigned compare Instructions; really, same as signed except they | |
| 11634 // produce an rFlagsRegU instead of rFlagsReg. | |
| 11635 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2) | |
| 11636 %{ | |
| 11637 match(Set cr (CmpU op1 op2)); | |
| 11638 | |
| 11639 format %{ "cmpl $op1, $op2\t# unsigned" %} | |
| 11640 opcode(0x3B); /* Opcode 3B /r */ | |
| 11641 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2)); | |
| 11642 ins_pipe(ialu_cr_reg_reg); | |
| 11643 %} | |
| 11644 | |
| 11645 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2) | |
| 11646 %{ | |
| 11647 match(Set cr (CmpU op1 op2)); | |
| 11648 | |
| 11649 format %{ "cmpl $op1, $op2\t# unsigned" %} | |
| 11650 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 11651 ins_encode(OpcSErm(op1, op2), Con8or32(op2)); | |
| 11652 ins_pipe(ialu_cr_reg_imm); | |
| 11653 %} | |
| 11654 | |
| 11655 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2) | |
| 11656 %{ | |
| 11657 match(Set cr (CmpU op1 (LoadI op2))); | |
| 11658 | |
| 11659 ins_cost(500); // XXX | |
| 11660 format %{ "cmpl $op1, $op2\t# unsigned" %} | |
| 11661 opcode(0x3B); /* Opcode 3B /r */ | |
| 11662 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 11663 ins_pipe(ialu_cr_reg_mem); | |
| 11664 %} | |
| 11665 | |
| 11666 // // // Cisc-spilled version of cmpU_rReg | |
| 11667 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2) | |
| 11668 // //%{ | |
| 11669 // // match(Set cr (CmpU (LoadI op1) op2)); | |
| 11670 // // | |
| 11671 // // format %{ "CMPu $op1,$op2" %} | |
| 11672 // // ins_cost(500); | |
| 11673 // // opcode(0x39); /* Opcode 39 /r */ | |
| 11674 // // ins_encode( OpcP, reg_mem( op1, op2) ); | |
| 11675 // //%} | |
| 11676 | |
| 11677 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero) | |
| 11678 %{ | |
| 11679 match(Set cr (CmpU src zero)); | |
| 11680 | |
| 11681 format %{ "testl $src, $src\t# unsigned" %} | |
| 11682 opcode(0x85); | |
| 11683 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src)); | |
| 11684 ins_pipe(ialu_cr_reg_imm); | |
| 11685 %} | |
| 11686 | |
| 11687 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2) | |
| 11688 %{ | |
| 11689 match(Set cr (CmpP op1 op2)); | |
| 11690 | |
| 11691 format %{ "cmpq $op1, $op2\t# ptr" %} | |
| 11692 opcode(0x3B); /* Opcode 3B /r */ | |
| 11693 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2)); | |
| 11694 ins_pipe(ialu_cr_reg_reg); | |
| 11695 %} | |
| 11696 | |
| 11697 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2) | |
| 11698 %{ | |
| 11699 match(Set cr (CmpP op1 (LoadP op2))); | |
| 11700 | |
| 11701 ins_cost(500); // XXX | |
| 11702 format %{ "cmpq $op1, $op2\t# ptr" %} | |
| 11703 opcode(0x3B); /* Opcode 3B /r */ | |
| 11704 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 11705 ins_pipe(ialu_cr_reg_mem); | |
| 11706 %} | |
| 11707 | |
| 11708 // // // Cisc-spilled version of cmpP_rReg | |
| 11709 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2) | |
| 11710 // //%{ | |
| 11711 // // match(Set cr (CmpP (LoadP op1) op2)); | |
| 11712 // // | |
| 11713 // // format %{ "CMPu $op1,$op2" %} | |
| 11714 // // ins_cost(500); | |
| 11715 // // opcode(0x39); /* Opcode 39 /r */ | |
| 11716 // // ins_encode( OpcP, reg_mem( op1, op2) ); | |
| 11717 // //%} | |
| 11718 | |
| 11719 // XXX this is generalized by compP_rReg_mem??? | |
| 11720 // Compare raw pointer (used in out-of-heap check). | |
| 11721 // Only works because non-oop pointers must be raw pointers | |
| 11722 // and raw pointers have no anti-dependencies. | |
| 11723 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2) | |
| 11724 %{ | |
| 11725 predicate(!n->in(2)->in(2)->bottom_type()->isa_oop_ptr()); | |
| 11726 match(Set cr (CmpP op1 (LoadP op2))); | |
| 11727 | |
| 11728 format %{ "cmpq $op1, $op2\t# raw ptr" %} | |
| 11729 opcode(0x3B); /* Opcode 3B /r */ | |
| 11730 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 11731 ins_pipe(ialu_cr_reg_mem); | |
| 11732 %} | |
| 11733 | |
| 11734 // This will generate a signed flags result. This should be OK since | |
| 11735 // any compare to a zero should be eq/neq. | |
| 11736 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero) | |
| 11737 %{ | |
| 11738 match(Set cr (CmpP src zero)); | |
| 11739 | |
| 11740 format %{ "testq $src, $src\t# ptr" %} | |
| 11741 opcode(0x85); | |
| 11742 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src)); | |
| 11743 ins_pipe(ialu_cr_reg_imm); | |
| 11744 %} | |
| 11745 | |
| 11746 // This will generate a signed flags result. This should be OK since | |
| 11747 // any compare to a zero should be eq/neq. | |
|
642
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|
11748 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero) |
|
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|
11749 %{ |
|
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|
11750 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL)); |
| 0 | 11751 match(Set cr (CmpP (LoadP op) zero)); |
| 11752 | |
| 11753 ins_cost(500); // XXX | |
| 11754 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %} | |
| 11755 opcode(0xF7); /* Opcode F7 /0 */ | |
| 11756 ins_encode(REX_mem_wide(op), | |
| 11757 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF)); | |
| 11758 ins_pipe(ialu_cr_reg_imm); | |
| 11759 %} | |
| 11760 | |
|
642
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|
11761 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero) |
|
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|
11762 %{ |
|
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|
11763 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
|
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|
11764 match(Set cr (CmpP (LoadP mem) zero)); |
|
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|
11765 |
|
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|
11766 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %} |
|
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|
11767 ins_encode %{ |
|
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|
11768 __ cmpq(r12, $mem$$Address); |
|
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|
11769 %} |
|
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|
11770 ins_pipe(ialu_cr_reg_mem); |
|
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|
11771 %} |
|
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|
11772 |
|
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11773 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2) |
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11774 %{ |
|
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11775 match(Set cr (CmpN op1 op2)); |
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|
11776 |
|
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|
11777 format %{ "cmpl $op1, $op2\t# compressed ptr" %} |
|
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11778 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %} |
|
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11779 ins_pipe(ialu_cr_reg_reg); |
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11780 %} |
|
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|
11781 |
|
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|
11782 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem) |
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11783 %{ |
|
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11784 match(Set cr (CmpN src (LoadN mem))); |
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|
11785 |
|
642
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|
11786 format %{ "cmpl $src, $mem\t# compressed ptr" %} |
|
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|
11787 ins_encode %{ |
|
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|
11788 __ cmpl($src$$Register, $mem$$Address); |
|
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|
11789 %} |
|
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|
11790 ins_pipe(ialu_cr_reg_mem); |
|
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|
11791 %} |
|
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|
11792 |
|
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|
11793 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{ |
|
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|
11794 match(Set cr (CmpN op1 op2)); |
|
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|
11795 |
|
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|
11796 format %{ "cmpl $op1, $op2\t# compressed ptr" %} |
|
164
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|
11797 ins_encode %{ |
|
642
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|
11798 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant); |
|
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|
11799 %} |
|
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|
11800 ins_pipe(ialu_cr_reg_imm); |
|
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|
11801 %} |
|
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|
11802 |
|
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|
11803 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src) |
|
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|
11804 %{ |
|
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|
11805 match(Set cr (CmpN src (LoadN mem))); |
|
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|
11806 |
|
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|
11807 format %{ "cmpl $mem, $src\t# compressed ptr" %} |
|
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|
11808 ins_encode %{ |
|
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|
11809 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant); |
|
164
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|
11810 %} |
|
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|
11811 ins_pipe(ialu_cr_reg_mem); |
|
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|
11812 %} |
|
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|
11813 |
|
113
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|
11814 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{ |
|
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|
11815 match(Set cr (CmpN src zero)); |
|
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|
11816 |
|
164
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|
11817 format %{ "testl $src, $src\t# compressed ptr" %} |
|
113
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|
11818 ins_encode %{ __ testl($src$$Register, $src$$Register); %} |
|
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|
11819 ins_pipe(ialu_cr_reg_imm); |
|
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|
11820 %} |
|
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|
11821 |
|
642
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|
11822 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero) |
|
660978a2a31a
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|
11823 %{ |
|
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|
11824 predicate(Universe::narrow_oop_base() != NULL); |
|
164
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|
11825 match(Set cr (CmpN (LoadN mem) zero)); |
|
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|
11826 |
|
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|
11827 ins_cost(500); // XXX |
|
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|
11828 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %} |
|
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|
11829 ins_encode %{ |
|
642
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|
11830 __ cmpl($mem$$Address, (int)0xFFFFFFFF); |
|
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|
11831 %} |
|
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|
11832 ins_pipe(ialu_cr_reg_mem); |
|
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|
11833 %} |
|
660978a2a31a
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|
11834 |
|
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|
11835 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero) |
|
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|
11836 %{ |
|
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|
11837 predicate(Universe::narrow_oop_base() == NULL); |
|
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|
11838 match(Set cr (CmpN (LoadN mem) zero)); |
|
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|
11839 |
|
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|
11840 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %} |
|
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|
11841 ins_encode %{ |
|
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|
11842 __ cmpl(r12, $mem$$Address); |
|
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11843 %} |
|
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|
11844 ins_pipe(ialu_cr_reg_mem); |
|
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|
11845 %} |
|
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11846 |
| 0 | 11847 // Yanked all unsigned pointer compare operations. |
| 11848 // Pointer compares are done with CmpP which is already unsigned. | |
| 11849 | |
| 11850 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2) | |
| 11851 %{ | |
| 11852 match(Set cr (CmpL op1 op2)); | |
| 11853 | |
| 11854 format %{ "cmpq $op1, $op2" %} | |
| 11855 opcode(0x3B); /* Opcode 3B /r */ | |
| 11856 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2)); | |
| 11857 ins_pipe(ialu_cr_reg_reg); | |
| 11858 %} | |
| 11859 | |
| 11860 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2) | |
| 11861 %{ | |
| 11862 match(Set cr (CmpL op1 op2)); | |
| 11863 | |
| 11864 format %{ "cmpq $op1, $op2" %} | |
| 11865 opcode(0x81, 0x07); /* Opcode 81 /7 */ | |
| 11866 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2)); | |
| 11867 ins_pipe(ialu_cr_reg_imm); | |
| 11868 %} | |
| 11869 | |
| 11870 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2) | |
| 11871 %{ | |
| 11872 match(Set cr (CmpL op1 (LoadL op2))); | |
| 11873 | |
| 11874 format %{ "cmpq $op1, $op2" %} | |
| 11875 opcode(0x3B); /* Opcode 3B /r */ | |
| 11876 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 11877 ins_pipe(ialu_cr_reg_mem); | |
| 11878 %} | |
| 11879 | |
| 11880 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero) | |
| 11881 %{ | |
| 11882 match(Set cr (CmpL src zero)); | |
| 11883 | |
| 11884 format %{ "testq $src, $src" %} | |
| 11885 opcode(0x85); | |
| 11886 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src)); | |
| 11887 ins_pipe(ialu_cr_reg_imm); | |
| 11888 %} | |
| 11889 | |
| 11890 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero) | |
| 11891 %{ | |
| 11892 match(Set cr (CmpL (AndL src con) zero)); | |
| 11893 | |
| 11894 format %{ "testq $src, $con\t# long" %} | |
| 11895 opcode(0xF7, 0x00); | |
| 11896 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con)); | |
| 11897 ins_pipe(ialu_cr_reg_imm); | |
| 11898 %} | |
| 11899 | |
| 11900 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero) | |
| 11901 %{ | |
| 11902 match(Set cr (CmpL (AndL src (LoadL mem)) zero)); | |
| 11903 | |
| 11904 format %{ "testq $src, $mem" %} | |
| 11905 opcode(0x85); | |
| 11906 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem)); | |
| 11907 ins_pipe(ialu_cr_reg_mem); | |
| 11908 %} | |
| 11909 | |
| 11910 // Manifest a CmpL result in an integer register. Very painful. | |
| 11911 // This is the test to avoid. | |
| 11912 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags) | |
| 11913 %{ | |
| 11914 match(Set dst (CmpL3 src1 src2)); | |
| 11915 effect(KILL flags); | |
| 11916 | |
| 11917 ins_cost(275); // XXX | |
| 11918 format %{ "cmpq $src1, $src2\t# CmpL3\n\t" | |
| 11919 "movl $dst, -1\n\t" | |
| 11920 "jl,s done\n\t" | |
| 11921 "setne $dst\n\t" | |
| 11922 "movzbl $dst, $dst\n\t" | |
| 11923 "done:" %} | |
| 11924 ins_encode(cmpl3_flag(src1, src2, dst)); | |
| 11925 ins_pipe(pipe_slow); | |
| 11926 %} | |
| 11927 | |
| 11928 //----------Max and Min-------------------------------------------------------- | |
| 11929 // Min Instructions | |
| 11930 | |
| 11931 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr) | |
| 11932 %{ | |
| 11933 effect(USE_DEF dst, USE src, USE cr); | |
| 11934 | |
| 11935 format %{ "cmovlgt $dst, $src\t# min" %} | |
| 11936 opcode(0x0F, 0x4F); | |
| 11937 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 11938 ins_pipe(pipe_cmov_reg); | |
| 11939 %} | |
| 11940 | |
| 11941 | |
| 11942 instruct minI_rReg(rRegI dst, rRegI src) | |
| 11943 %{ | |
| 11944 match(Set dst (MinI dst src)); | |
| 11945 | |
| 11946 ins_cost(200); | |
| 11947 expand %{ | |
| 11948 rFlagsReg cr; | |
| 11949 compI_rReg(cr, dst, src); | |
| 11950 cmovI_reg_g(dst, src, cr); | |
| 11951 %} | |
| 11952 %} | |
| 11953 | |
| 11954 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr) | |
| 11955 %{ | |
| 11956 effect(USE_DEF dst, USE src, USE cr); | |
| 11957 | |
| 11958 format %{ "cmovllt $dst, $src\t# max" %} | |
| 11959 opcode(0x0F, 0x4C); | |
| 11960 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 11961 ins_pipe(pipe_cmov_reg); | |
| 11962 %} | |
| 11963 | |
| 11964 | |
| 11965 instruct maxI_rReg(rRegI dst, rRegI src) | |
| 11966 %{ | |
| 11967 match(Set dst (MaxI dst src)); | |
| 11968 | |
| 11969 ins_cost(200); | |
| 11970 expand %{ | |
| 11971 rFlagsReg cr; | |
| 11972 compI_rReg(cr, dst, src); | |
| 11973 cmovI_reg_l(dst, src, cr); | |
| 11974 %} | |
| 11975 %} | |
| 11976 | |
| 11977 // ============================================================================ | |
| 11978 // Branch Instructions | |
| 11979 | |
| 11980 // Jump Direct - Label defines a relative address from JMP+1 | |
| 11981 instruct jmpDir(label labl) | |
| 11982 %{ | |
| 11983 match(Goto); | |
| 11984 effect(USE labl); | |
| 11985 | |
| 11986 ins_cost(300); | |
| 11987 format %{ "jmp $labl" %} | |
| 11988 size(5); | |
| 11989 opcode(0xE9); | |
| 11990 ins_encode(OpcP, Lbl(labl)); | |
| 11991 ins_pipe(pipe_jmp); | |
| 11992 ins_pc_relative(1); | |
| 11993 %} | |
| 11994 | |
| 11995 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 11996 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl) | |
| 11997 %{ | |
| 11998 match(If cop cr); | |
| 11999 effect(USE labl); | |
| 12000 | |
| 12001 ins_cost(300); | |
| 12002 format %{ "j$cop $labl" %} | |
| 12003 size(6); | |
| 12004 opcode(0x0F, 0x80); | |
| 12005 ins_encode(Jcc(cop, labl)); | |
| 12006 ins_pipe(pipe_jcc); | |
| 12007 ins_pc_relative(1); | |
| 12008 %} | |
| 12009 | |
| 12010 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12011 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl) | |
| 12012 %{ | |
| 12013 match(CountedLoopEnd cop cr); | |
| 12014 effect(USE labl); | |
| 12015 | |
| 12016 ins_cost(300); | |
| 12017 format %{ "j$cop $labl\t# loop end" %} | |
| 12018 size(6); | |
| 12019 opcode(0x0F, 0x80); | |
| 12020 ins_encode(Jcc(cop, labl)); | |
| 12021 ins_pipe(pipe_jcc); | |
| 12022 ins_pc_relative(1); | |
| 12023 %} | |
| 12024 | |
| 12025 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
|
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12026 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
| 0 | 12027 match(CountedLoopEnd cop cmp); |
| 12028 effect(USE labl); | |
| 12029 | |
| 12030 ins_cost(300); | |
| 12031 format %{ "j$cop,u $labl\t# loop end" %} | |
| 12032 size(6); | |
| 12033 opcode(0x0F, 0x80); | |
| 12034 ins_encode(Jcc(cop, labl)); | |
| 12035 ins_pipe(pipe_jcc); | |
| 12036 ins_pc_relative(1); | |
| 12037 %} | |
| 12038 | |
|
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12039 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
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12040 match(CountedLoopEnd cop cmp); |
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12041 effect(USE labl); |
|
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12042 |
|
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12043 ins_cost(200); |
|
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12044 format %{ "j$cop,u $labl\t# loop end" %} |
|
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12045 size(6); |
|
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|
12046 opcode(0x0F, 0x80); |
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12047 ins_encode(Jcc(cop, labl)); |
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12048 ins_pipe(pipe_jcc); |
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12049 ins_pc_relative(1); |
|
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|
12050 %} |
|
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|
12051 |
| 0 | 12052 // Jump Direct Conditional - using unsigned comparison |
|
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12053 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
| 0 | 12054 match(If cop cmp); |
| 12055 effect(USE labl); | |
| 12056 | |
| 12057 ins_cost(300); | |
|
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12058 format %{ "j$cop,u $labl" %} |
|
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|
12059 size(6); |
|
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|
12060 opcode(0x0F, 0x80); |
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12061 ins_encode(Jcc(cop, labl)); |
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12062 ins_pipe(pipe_jcc); |
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12063 ins_pc_relative(1); |
|
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12064 %} |
|
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|
12065 |
|
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12066 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
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12067 match(If cop cmp); |
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12068 effect(USE labl); |
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12069 |
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12070 ins_cost(200); |
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12071 format %{ "j$cop,u $labl" %} |
| 0 | 12072 size(6); |
| 12073 opcode(0x0F, 0x80); | |
| 12074 ins_encode(Jcc(cop, labl)); | |
| 12075 ins_pipe(pipe_jcc); | |
| 12076 ins_pc_relative(1); | |
| 12077 %} | |
| 12078 | |
|
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12079 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{ |
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12080 match(If cop cmp); |
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12081 effect(USE labl); |
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12082 |
|
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12083 ins_cost(200); |
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|
12084 format %{ $$template |
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12085 if ($cop$$cmpcode == Assembler::notEqual) { |
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12086 $$emit$$"jp,u $labl\n\t" |
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12087 $$emit$$"j$cop,u $labl" |
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12088 } else { |
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12089 $$emit$$"jp,u done\n\t" |
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12090 $$emit$$"j$cop,u $labl\n\t" |
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12091 $$emit$$"done:" |
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12092 } |
|
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|
12093 %} |
|
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|
12094 size(12); |
|
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|
12095 opcode(0x0F, 0x80); |
|
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|
12096 ins_encode %{ |
|
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12097 Label* l = $labl$$label; |
|
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12098 $$$emit8$primary; |
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12099 emit_cc(cbuf, $secondary, Assembler::parity); |
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12100 int parity_disp = -1; |
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12101 if ($cop$$cmpcode == Assembler::notEqual) { |
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12102 // the two jumps 6 bytes apart so the jump distances are too |
|
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12103 parity_disp = l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0; |
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12104 } else if ($cop$$cmpcode == Assembler::equal) { |
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12105 parity_disp = 6; |
|
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|
12106 } else { |
|
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|
12107 ShouldNotReachHere(); |
|
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|
12108 } |
|
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|
12109 emit_d32(cbuf, parity_disp); |
|
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12110 $$$emit8$primary; |
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12111 emit_cc(cbuf, $secondary, $cop$$cmpcode); |
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12112 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0; |
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12113 emit_d32(cbuf, disp); |
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|
12114 %} |
|
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|
12115 ins_pipe(pipe_jcc); |
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|
12116 ins_pc_relative(1); |
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|
12117 %} |
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|
12118 |
| 0 | 12119 // ============================================================================ |
| 12120 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary | |
| 12121 // superklass array for an instance of the superklass. Set a hidden | |
| 12122 // internal cache on a hit (cache is checked with exposed code in | |
| 12123 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The | |
| 12124 // encoding ALSO sets flags. | |
| 12125 | |
| 12126 instruct partialSubtypeCheck(rdi_RegP result, | |
| 12127 rsi_RegP sub, rax_RegP super, rcx_RegI rcx, | |
| 12128 rFlagsReg cr) | |
| 12129 %{ | |
| 12130 match(Set result (PartialSubtypeCheck sub super)); | |
| 12131 effect(KILL rcx, KILL cr); | |
| 12132 | |
| 12133 ins_cost(1100); // slightly larger than the next version | |
|
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|
12134 format %{ "movq rdi, [$sub + (sizeof(oopDesc) + Klass::secondary_supers_offset_in_bytes())]\n\t" |
| 0 | 12135 "movl rcx, [rdi + arrayOopDesc::length_offset_in_bytes()]\t# length to scan\n\t" |
| 12136 "addq rdi, arrayOopDex::base_offset_in_bytes(T_OBJECT)\t# Skip to start of data; set NZ in case count is zero\n\t" | |
| 12137 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t" | |
| 12138 "jne,s miss\t\t# Missed: rdi not-zero\n\t" | |
| 12139 "movq [$sub + (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes())], $super\t# Hit: update cache\n\t" | |
| 12140 "xorq $result, $result\t\t Hit: rdi zero\n\t" | |
| 12141 "miss:\t" %} | |
| 12142 | |
| 12143 opcode(0x1); // Force a XOR of RDI | |
| 12144 ins_encode(enc_PartialSubtypeCheck()); | |
| 12145 ins_pipe(pipe_slow); | |
| 12146 %} | |
| 12147 | |
| 12148 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr, | |
| 12149 rsi_RegP sub, rax_RegP super, rcx_RegI rcx, | |
| 12150 immP0 zero, | |
| 12151 rdi_RegP result) | |
| 12152 %{ | |
| 12153 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero)); | |
| 12154 effect(KILL rcx, KILL result); | |
| 12155 | |
| 12156 ins_cost(1000); | |
|
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|
12157 format %{ "movq rdi, [$sub + (sizeof(oopDesc) + Klass::secondary_supers_offset_in_bytes())]\n\t" |
| 0 | 12158 "movl rcx, [rdi + arrayOopDesc::length_offset_in_bytes()]\t# length to scan\n\t" |
| 12159 "addq rdi, arrayOopDex::base_offset_in_bytes(T_OBJECT)\t# Skip to start of data; set NZ in case count is zero\n\t" | |
| 12160 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t" | |
| 12161 "jne,s miss\t\t# Missed: flags nz\n\t" | |
| 12162 "movq [$sub + (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes())], $super\t# Hit: update cache\n\t" | |
| 12163 "miss:\t" %} | |
| 12164 | |
| 12165 opcode(0x0); // No need to XOR RDI | |
| 12166 ins_encode(enc_PartialSubtypeCheck()); | |
| 12167 ins_pipe(pipe_slow); | |
| 12168 %} | |
| 12169 | |
| 12170 // ============================================================================ | |
| 12171 // Branch Instructions -- short offset versions | |
| 12172 // | |
| 12173 // These instructions are used to replace jumps of a long offset (the default | |
| 12174 // match) with jumps of a shorter offset. These instructions are all tagged | |
| 12175 // with the ins_short_branch attribute, which causes the ADLC to suppress the | |
| 12176 // match rules in general matching. Instead, the ADLC generates a conversion | |
| 12177 // method in the MachNode which can be used to do in-place replacement of the | |
| 12178 // long variant with the shorter variant. The compiler will determine if a | |
| 12179 // branch can be taken by the is_short_branch_offset() predicate in the machine | |
| 12180 // specific code section of the file. | |
| 12181 | |
| 12182 // Jump Direct - Label defines a relative address from JMP+1 | |
|
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|
12183 instruct jmpDir_short(label labl) %{ |
| 0 | 12184 match(Goto); |
| 12185 effect(USE labl); | |
| 12186 | |
| 12187 ins_cost(300); | |
| 12188 format %{ "jmp,s $labl" %} | |
| 12189 size(2); | |
| 12190 opcode(0xEB); | |
| 12191 ins_encode(OpcP, LblShort(labl)); | |
| 12192 ins_pipe(pipe_jmp); | |
| 12193 ins_pc_relative(1); | |
| 12194 ins_short_branch(1); | |
| 12195 %} | |
| 12196 | |
| 12197 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
|
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|
12198 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{ |
| 0 | 12199 match(If cop cr); |
| 12200 effect(USE labl); | |
| 12201 | |
| 12202 ins_cost(300); | |
| 12203 format %{ "j$cop,s $labl" %} | |
| 12204 size(2); | |
| 12205 opcode(0x70); | |
| 12206 ins_encode(JccShort(cop, labl)); | |
| 12207 ins_pipe(pipe_jcc); | |
| 12208 ins_pc_relative(1); | |
| 12209 ins_short_branch(1); | |
| 12210 %} | |
| 12211 | |
| 12212 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
|
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|
12213 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{ |
| 0 | 12214 match(CountedLoopEnd cop cr); |
| 12215 effect(USE labl); | |
| 12216 | |
| 12217 ins_cost(300); | |
|
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|
12218 format %{ "j$cop,s $labl\t# loop end" %} |
| 0 | 12219 size(2); |
| 12220 opcode(0x70); | |
| 12221 ins_encode(JccShort(cop, labl)); | |
| 12222 ins_pipe(pipe_jcc); | |
| 12223 ins_pc_relative(1); | |
| 12224 ins_short_branch(1); | |
| 12225 %} | |
| 12226 | |
| 12227 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
|
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12228 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
|
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|
12229 match(CountedLoopEnd cop cmp); |
|
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|
12230 effect(USE labl); |
|
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|
12231 |
|
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|
12232 ins_cost(300); |
|
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|
12233 format %{ "j$cop,us $labl\t# loop end" %} |
|
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|
12234 size(2); |
|
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|
12235 opcode(0x70); |
|
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|
12236 ins_encode(JccShort(cop, labl)); |
|
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|
12237 ins_pipe(pipe_jcc); |
|
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|
12238 ins_pc_relative(1); |
|
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|
12239 ins_short_branch(1); |
|
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|
12240 %} |
|
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|
12241 |
|
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|
12242 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
| 0 | 12243 match(CountedLoopEnd cop cmp); |
| 12244 effect(USE labl); | |
| 12245 | |
| 12246 ins_cost(300); | |
|
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12247 format %{ "j$cop,us $labl\t# loop end" %} |
|
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|
12248 size(2); |
|
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|
12249 opcode(0x70); |
|
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|
12250 ins_encode(JccShort(cop, labl)); |
|
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|
12251 ins_pipe(pipe_jcc); |
|
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|
12252 ins_pc_relative(1); |
|
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|
12253 ins_short_branch(1); |
|
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|
12254 %} |
|
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|
12255 |
|
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|
12256 // Jump Direct Conditional - using unsigned comparison |
|
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12257 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
|
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12258 match(If cop cmp); |
|
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|
12259 effect(USE labl); |
|
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|
12260 |
|
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|
12261 ins_cost(300); |
| 0 | 12262 format %{ "j$cop,us $labl" %} |
| 12263 size(2); | |
| 12264 opcode(0x70); | |
| 12265 ins_encode(JccShort(cop, labl)); | |
| 12266 ins_pipe(pipe_jcc); | |
| 12267 ins_pc_relative(1); | |
| 12268 ins_short_branch(1); | |
| 12269 %} | |
| 12270 | |
|
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12271 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
| 0 | 12272 match(If cop cmp); |
| 12273 effect(USE labl); | |
| 12274 | |
| 12275 ins_cost(300); | |
| 12276 format %{ "j$cop,us $labl" %} | |
| 12277 size(2); | |
| 12278 opcode(0x70); | |
| 12279 ins_encode(JccShort(cop, labl)); | |
| 12280 ins_pipe(pipe_jcc); | |
| 12281 ins_pc_relative(1); | |
| 12282 ins_short_branch(1); | |
| 12283 %} | |
| 12284 | |
|
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12285 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{ |
|
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|
12286 match(If cop cmp); |
|
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|
12287 effect(USE labl); |
|
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|
12288 |
|
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|
12289 ins_cost(300); |
|
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|
12290 format %{ $$template |
|
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|
12291 if ($cop$$cmpcode == Assembler::notEqual) { |
|
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|
12292 $$emit$$"jp,u,s $labl\n\t" |
|
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|
12293 $$emit$$"j$cop,u,s $labl" |
|
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|
12294 } else { |
|
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|
12295 $$emit$$"jp,u,s done\n\t" |
|
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|
12296 $$emit$$"j$cop,u,s $labl\n\t" |
|
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|
12297 $$emit$$"done:" |
|
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|
12298 } |
|
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|
12299 %} |
|
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changeset
|
12300 size(4); |
|
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changeset
|
12301 opcode(0x70); |
|
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|
12302 ins_encode %{ |
|
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|
12303 Label* l = $labl$$label; |
|
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|
12304 emit_cc(cbuf, $primary, Assembler::parity); |
|
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|
12305 int parity_disp = -1; |
|
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|
12306 if ($cop$$cmpcode == Assembler::notEqual) { |
|
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|
12307 parity_disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0; |
|
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|
12308 } else if ($cop$$cmpcode == Assembler::equal) { |
|
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|
12309 parity_disp = 2; |
|
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|
12310 } else { |
|
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changeset
|
12311 ShouldNotReachHere(); |
|
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|
12312 } |
|
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|
12313 emit_d8(cbuf, parity_disp); |
|
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|
12314 emit_cc(cbuf, $primary, $cop$$cmpcode); |
|
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|
12315 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0; |
|
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|
12316 emit_d8(cbuf, disp); |
|
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|
12317 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp"); |
|
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|
12318 assert(-128 <= parity_disp && parity_disp <= 127, "Displacement too large for short jmp"); |
|
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|
12319 %} |
|
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|
12320 ins_pipe(pipe_jcc); |
|
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|
12321 ins_pc_relative(1); |
|
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|
12322 ins_short_branch(1); |
|
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|
12323 %} |
|
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|
12324 |
| 0 | 12325 // ============================================================================ |
| 12326 // inlined locking and unlocking | |
| 12327 | |
| 12328 instruct cmpFastLock(rFlagsReg cr, | |
| 12329 rRegP object, rRegP box, rax_RegI tmp, rRegP scr) | |
| 12330 %{ | |
| 12331 match(Set cr (FastLock object box)); | |
| 12332 effect(TEMP tmp, TEMP scr); | |
| 12333 | |
| 12334 ins_cost(300); | |
| 12335 format %{ "fastlock $object,$box,$tmp,$scr" %} | |
| 12336 ins_encode(Fast_Lock(object, box, tmp, scr)); | |
| 12337 ins_pipe(pipe_slow); | |
| 12338 ins_pc_relative(1); | |
| 12339 %} | |
| 12340 | |
| 12341 instruct cmpFastUnlock(rFlagsReg cr, | |
| 12342 rRegP object, rax_RegP box, rRegP tmp) | |
| 12343 %{ | |
| 12344 match(Set cr (FastUnlock object box)); | |
| 12345 effect(TEMP tmp); | |
| 12346 | |
| 12347 ins_cost(300); | |
| 12348 format %{ "fastunlock $object, $box, $tmp" %} | |
| 12349 ins_encode(Fast_Unlock(object, box, tmp)); | |
| 12350 ins_pipe(pipe_slow); | |
| 12351 ins_pc_relative(1); | |
| 12352 %} | |
| 12353 | |
| 12354 | |
| 12355 // ============================================================================ | |
| 12356 // Safepoint Instructions | |
| 12357 instruct safePoint_poll(rFlagsReg cr) | |
| 12358 %{ | |
| 12359 match(SafePoint); | |
| 12360 effect(KILL cr); | |
| 12361 | |
| 12362 format %{ "testl rax, [rip + #offset_to_poll_page]\t" | |
| 12363 "# Safepoint: poll for GC" %} | |
| 12364 size(6); // Opcode + ModRM + Disp32 == 6 bytes | |
| 12365 ins_cost(125); | |
| 12366 ins_encode(enc_safepoint_poll); | |
| 12367 ins_pipe(ialu_reg_mem); | |
| 12368 %} | |
| 12369 | |
| 12370 // ============================================================================ | |
| 12371 // Procedure Call/Return Instructions | |
| 12372 // Call Java Static Instruction | |
| 12373 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 12374 // compute_padding() functions will have to be adjusted. | |
| 12375 instruct CallStaticJavaDirect(method meth) | |
| 12376 %{ | |
| 12377 match(CallStaticJava); | |
| 12378 effect(USE meth); | |
| 12379 | |
| 12380 ins_cost(300); | |
| 12381 format %{ "call,static " %} | |
| 12382 opcode(0xE8); /* E8 cd */ | |
| 12383 ins_encode(Java_Static_Call(meth), call_epilog); | |
| 12384 ins_pipe(pipe_slow); | |
| 12385 ins_pc_relative(1); | |
| 12386 ins_alignment(4); | |
| 12387 %} | |
| 12388 | |
| 12389 // Call Java Dynamic Instruction | |
| 12390 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 12391 // compute_padding() functions will have to be adjusted. | |
| 12392 instruct CallDynamicJavaDirect(method meth) | |
| 12393 %{ | |
| 12394 match(CallDynamicJava); | |
| 12395 effect(USE meth); | |
| 12396 | |
| 12397 ins_cost(300); | |
| 12398 format %{ "movq rax, #Universe::non_oop_word()\n\t" | |
| 12399 "call,dynamic " %} | |
| 12400 opcode(0xE8); /* E8 cd */ | |
| 12401 ins_encode(Java_Dynamic_Call(meth), call_epilog); | |
| 12402 ins_pipe(pipe_slow); | |
| 12403 ins_pc_relative(1); | |
| 12404 ins_alignment(4); | |
| 12405 %} | |
| 12406 | |
| 12407 // Call Runtime Instruction | |
| 12408 instruct CallRuntimeDirect(method meth) | |
| 12409 %{ | |
| 12410 match(CallRuntime); | |
| 12411 effect(USE meth); | |
| 12412 | |
| 12413 ins_cost(300); | |
| 12414 format %{ "call,runtime " %} | |
| 12415 opcode(0xE8); /* E8 cd */ | |
| 12416 ins_encode(Java_To_Runtime(meth)); | |
| 12417 ins_pipe(pipe_slow); | |
| 12418 ins_pc_relative(1); | |
| 12419 %} | |
| 12420 | |
| 12421 // Call runtime without safepoint | |
| 12422 instruct CallLeafDirect(method meth) | |
| 12423 %{ | |
| 12424 match(CallLeaf); | |
| 12425 effect(USE meth); | |
| 12426 | |
| 12427 ins_cost(300); | |
| 12428 format %{ "call_leaf,runtime " %} | |
| 12429 opcode(0xE8); /* E8 cd */ | |
| 12430 ins_encode(Java_To_Runtime(meth)); | |
| 12431 ins_pipe(pipe_slow); | |
| 12432 ins_pc_relative(1); | |
| 12433 %} | |
| 12434 | |
| 12435 // Call runtime without safepoint | |
| 12436 instruct CallLeafNoFPDirect(method meth) | |
| 12437 %{ | |
| 12438 match(CallLeafNoFP); | |
| 12439 effect(USE meth); | |
| 12440 | |
| 12441 ins_cost(300); | |
| 12442 format %{ "call_leaf_nofp,runtime " %} | |
| 12443 opcode(0xE8); /* E8 cd */ | |
| 12444 ins_encode(Java_To_Runtime(meth)); | |
| 12445 ins_pipe(pipe_slow); | |
| 12446 ins_pc_relative(1); | |
| 12447 %} | |
| 12448 | |
| 12449 // Return Instruction | |
| 12450 // Remove the return address & jump to it. | |
| 12451 // Notice: We always emit a nop after a ret to make sure there is room | |
| 12452 // for safepoint patching | |
| 12453 instruct Ret() | |
| 12454 %{ | |
| 12455 match(Return); | |
| 12456 | |
| 12457 format %{ "ret" %} | |
| 12458 opcode(0xC3); | |
| 12459 ins_encode(OpcP); | |
| 12460 ins_pipe(pipe_jmp); | |
| 12461 %} | |
| 12462 | |
| 12463 // Tail Call; Jump from runtime stub to Java code. | |
| 12464 // Also known as an 'interprocedural jump'. | |
| 12465 // Target of jump will eventually return to caller. | |
| 12466 // TailJump below removes the return address. | |
| 12467 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop) | |
| 12468 %{ | |
| 12469 match(TailCall jump_target method_oop); | |
| 12470 | |
| 12471 ins_cost(300); | |
| 12472 format %{ "jmp $jump_target\t# rbx holds method oop" %} | |
| 12473 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 12474 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target)); | |
| 12475 ins_pipe(pipe_jmp); | |
| 12476 %} | |
| 12477 | |
| 12478 // Tail Jump; remove the return address; jump to target. | |
| 12479 // TailCall above leaves the return address around. | |
| 12480 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop) | |
| 12481 %{ | |
| 12482 match(TailJump jump_target ex_oop); | |
| 12483 | |
| 12484 ins_cost(300); | |
| 12485 format %{ "popq rdx\t# pop return address\n\t" | |
| 12486 "jmp $jump_target" %} | |
| 12487 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 12488 ins_encode(Opcode(0x5a), // popq rdx | |
| 12489 REX_reg(jump_target), OpcP, reg_opc(jump_target)); | |
| 12490 ins_pipe(pipe_jmp); | |
| 12491 %} | |
| 12492 | |
| 12493 // Create exception oop: created by stack-crawling runtime code. | |
| 12494 // Created exception is now available to this handler, and is setup | |
| 12495 // just prior to jumping to this handler. No code emitted. | |
| 12496 instruct CreateException(rax_RegP ex_oop) | |
| 12497 %{ | |
| 12498 match(Set ex_oop (CreateEx)); | |
| 12499 | |
| 12500 size(0); | |
| 12501 // use the following format syntax | |
| 12502 format %{ "# exception oop is in rax; no code emitted" %} | |
| 12503 ins_encode(); | |
| 12504 ins_pipe(empty); | |
| 12505 %} | |
| 12506 | |
| 12507 // Rethrow exception: | |
| 12508 // The exception oop will come in the first argument position. | |
| 12509 // Then JUMP (not call) to the rethrow stub code. | |
| 12510 instruct RethrowException() | |
| 12511 %{ | |
| 12512 match(Rethrow); | |
| 12513 | |
| 12514 // use the following format syntax | |
| 12515 format %{ "jmp rethrow_stub" %} | |
| 12516 ins_encode(enc_rethrow); | |
| 12517 ins_pipe(pipe_jmp); | |
| 12518 %} | |
| 12519 | |
| 12520 | |
| 12521 //----------PEEPHOLE RULES----------------------------------------------------- | |
| 12522 // These must follow all instruction definitions as they use the names | |
| 12523 // defined in the instructions definitions. | |
| 12524 // | |
| 605 | 12525 // peepmatch ( root_instr_name [preceding_instruction]* ); |
| 0 | 12526 // |
| 12527 // peepconstraint %{ | |
| 12528 // (instruction_number.operand_name relational_op instruction_number.operand_name | |
| 12529 // [, ...] ); | |
| 12530 // // instruction numbers are zero-based using left to right order in peepmatch | |
| 12531 // | |
| 12532 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); | |
| 12533 // // provide an instruction_number.operand_name for each operand that appears | |
| 12534 // // in the replacement instruction's match rule | |
| 12535 // | |
| 12536 // ---------VM FLAGS--------------------------------------------------------- | |
| 12537 // | |
| 12538 // All peephole optimizations can be turned off using -XX:-OptoPeephole | |
| 12539 // | |
| 12540 // Each peephole rule is given an identifying number starting with zero and | |
| 12541 // increasing by one in the order seen by the parser. An individual peephole | |
| 12542 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# | |
| 12543 // on the command-line. | |
| 12544 // | |
| 12545 // ---------CURRENT LIMITATIONS---------------------------------------------- | |
| 12546 // | |
| 12547 // Only match adjacent instructions in same basic block | |
| 12548 // Only equality constraints | |
| 12549 // Only constraints between operands, not (0.dest_reg == RAX_enc) | |
| 12550 // Only one replacement instruction | |
| 12551 // | |
| 12552 // ---------EXAMPLE---------------------------------------------------------- | |
| 12553 // | |
| 12554 // // pertinent parts of existing instructions in architecture description | |
| 12555 // instruct movI(rRegI dst, rRegI src) | |
| 12556 // %{ | |
| 12557 // match(Set dst (CopyI src)); | |
| 12558 // %} | |
| 12559 // | |
| 12560 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr) | |
| 12561 // %{ | |
| 12562 // match(Set dst (AddI dst src)); | |
| 12563 // effect(KILL cr); | |
| 12564 // %} | |
| 12565 // | |
| 12566 // // Change (inc mov) to lea | |
| 12567 // peephole %{ | |
| 12568 // // increment preceeded by register-register move | |
| 12569 // peepmatch ( incI_rReg movI ); | |
| 12570 // // require that the destination register of the increment | |
| 12571 // // match the destination register of the move | |
| 12572 // peepconstraint ( 0.dst == 1.dst ); | |
| 12573 // // construct a replacement instruction that sets | |
| 12574 // // the destination to ( move's source register + one ) | |
| 12575 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) ); | |
| 12576 // %} | |
| 12577 // | |
| 12578 | |
| 12579 // Implementation no longer uses movX instructions since | |
| 12580 // machine-independent system no longer uses CopyX nodes. | |
| 12581 // | |
| 12582 // peephole | |
| 12583 // %{ | |
| 12584 // peepmatch (incI_rReg movI); | |
| 12585 // peepconstraint (0.dst == 1.dst); | |
| 12586 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src)); | |
| 12587 // %} | |
| 12588 | |
| 12589 // peephole | |
| 12590 // %{ | |
| 12591 // peepmatch (decI_rReg movI); | |
| 12592 // peepconstraint (0.dst == 1.dst); | |
| 12593 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src)); | |
| 12594 // %} | |
| 12595 | |
| 12596 // peephole | |
| 12597 // %{ | |
| 12598 // peepmatch (addI_rReg_imm movI); | |
| 12599 // peepconstraint (0.dst == 1.dst); | |
| 12600 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src)); | |
| 12601 // %} | |
| 12602 | |
| 12603 // peephole | |
| 12604 // %{ | |
| 12605 // peepmatch (incL_rReg movL); | |
| 12606 // peepconstraint (0.dst == 1.dst); | |
| 12607 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src)); | |
| 12608 // %} | |
| 12609 | |
| 12610 // peephole | |
| 12611 // %{ | |
| 12612 // peepmatch (decL_rReg movL); | |
| 12613 // peepconstraint (0.dst == 1.dst); | |
| 12614 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src)); | |
| 12615 // %} | |
| 12616 | |
| 12617 // peephole | |
| 12618 // %{ | |
| 12619 // peepmatch (addL_rReg_imm movL); | |
| 12620 // peepconstraint (0.dst == 1.dst); | |
| 12621 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src)); | |
| 12622 // %} | |
| 12623 | |
| 12624 // peephole | |
| 12625 // %{ | |
| 12626 // peepmatch (addP_rReg_imm movP); | |
| 12627 // peepconstraint (0.dst == 1.dst); | |
| 12628 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src)); | |
| 12629 // %} | |
| 12630 | |
| 12631 // // Change load of spilled value to only a spill | |
| 12632 // instruct storeI(memory mem, rRegI src) | |
| 12633 // %{ | |
| 12634 // match(Set mem (StoreI mem src)); | |
| 12635 // %} | |
| 12636 // | |
| 12637 // instruct loadI(rRegI dst, memory mem) | |
| 12638 // %{ | |
| 12639 // match(Set dst (LoadI mem)); | |
| 12640 // %} | |
| 12641 // | |
| 12642 | |
| 12643 peephole | |
| 12644 %{ | |
| 12645 peepmatch (loadI storeI); | |
| 12646 peepconstraint (1.src == 0.dst, 1.mem == 0.mem); | |
| 12647 peepreplace (storeI(1.mem 1.mem 1.src)); | |
| 12648 %} | |
| 12649 | |
| 12650 peephole | |
| 12651 %{ | |
| 12652 peepmatch (loadL storeL); | |
| 12653 peepconstraint (1.src == 0.dst, 1.mem == 0.mem); | |
| 12654 peepreplace (storeL(1.mem 1.mem 1.src)); | |
| 12655 %} | |
| 12656 | |
| 12657 //----------SMARTSPILL RULES--------------------------------------------------- | |
| 12658 // These must follow all instruction definitions as they use the names | |
| 12659 // defined in the instructions definitions. |