Mercurial > hg > truffle
annotate src/cpu/x86/vm/x86_64.ad @ 5984:fd09f2d8283e
7157141: crash in 64 bit with corrupted oops
Reviewed-by: kvn, iveresov
| author | never |
|---|---|
| date | Mon, 02 Apr 2012 16:05:56 -0700 |
| parents | 61b82be3b1ff |
| children | 6759698e3140 |
| rev | line source |
|---|---|
| 0 | 1 // |
| 4950 | 2 // Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 // | |
| 5 // This code is free software; you can redistribute it and/or modify it | |
| 6 // under the terms of the GNU General Public License version 2 only, as | |
| 7 // published by the Free Software Foundation. | |
| 8 // | |
| 9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 // version 2 for more details (a copy is included in the LICENSE file that | |
| 13 // accompanied this code). | |
| 14 // | |
| 15 // You should have received a copy of the GNU General Public License version | |
| 16 // 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 // | |
|
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19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
|
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20 // or visit www.oracle.com if you need additional information or have any |
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21 // questions. |
| 0 | 22 // |
| 23 // | |
| 24 | |
| 25 // AMD64 Architecture Description File | |
| 26 | |
| 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ | |
| 28 // This information is used by the matcher and the register allocator to | |
| 29 // describe individual registers and classes of registers within the target | |
| 30 // archtecture. | |
| 31 | |
| 32 register %{ | |
| 33 //----------Architecture Description Register Definitions---------------------- | |
| 34 // General Registers | |
| 35 // "reg_def" name ( register save type, C convention save type, | |
| 36 // ideal register type, encoding ); | |
| 37 // Register Save Types: | |
| 38 // | |
| 39 // NS = No-Save: The register allocator assumes that these registers | |
| 40 // can be used without saving upon entry to the method, & | |
| 41 // that they do not need to be saved at call sites. | |
| 42 // | |
| 43 // SOC = Save-On-Call: The register allocator assumes that these registers | |
| 44 // can be used without saving upon entry to the method, | |
| 45 // but that they must be saved at call sites. | |
| 46 // | |
| 47 // SOE = Save-On-Entry: The register allocator assumes that these registers | |
| 48 // must be saved before using them upon entry to the | |
| 49 // method, but they do not need to be saved at call | |
| 50 // sites. | |
| 51 // | |
| 52 // AS = Always-Save: The register allocator assumes that these registers | |
| 53 // must be saved before using them upon entry to the | |
| 54 // method, & that they must be saved at call sites. | |
| 55 // | |
| 56 // Ideal Register Type is used to determine how to save & restore a | |
| 57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get | |
| 58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. | |
| 59 // | |
| 60 // The encoding number is the actual bit-pattern placed into the opcodes. | |
| 61 | |
| 62 // General Registers | |
| 63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when | |
| 64 // used as byte registers) | |
| 65 | |
| 66 // Previously set RBX, RSI, and RDI as save-on-entry for java code | |
| 67 // Turn off SOE in java-code due to frequent use of uncommon-traps. | |
| 68 // Now that allocator is better, turn on RSI and RDI as SOE registers. | |
| 69 | |
| 70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg()); | |
| 71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next()); | |
| 72 | |
| 73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg()); | |
| 74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next()); | |
| 75 | |
| 76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg()); | |
| 77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next()); | |
| 78 | |
| 79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg()); | |
| 80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next()); | |
| 81 | |
| 82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg()); | |
| 83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next()); | |
| 84 | |
| 85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code | |
| 86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg()); | |
| 87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next()); | |
| 88 | |
| 89 #ifdef _WIN64 | |
| 90 | |
| 91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg()); | |
| 92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next()); | |
| 93 | |
| 94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg()); | |
| 95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next()); | |
| 96 | |
| 97 #else | |
| 98 | |
| 99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg()); | |
| 100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next()); | |
| 101 | |
| 102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg()); | |
| 103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next()); | |
| 104 | |
| 105 #endif | |
| 106 | |
| 107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg()); | |
| 108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next()); | |
| 109 | |
| 110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg()); | |
| 111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next()); | |
| 112 | |
| 113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg()); | |
| 114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next()); | |
| 115 | |
| 116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg()); | |
| 117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next()); | |
| 118 | |
| 119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg()); | |
| 120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next()); | |
| 121 | |
| 122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg()); | |
| 123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next()); | |
| 124 | |
| 125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg()); | |
| 126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next()); | |
| 127 | |
| 128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg()); | |
| 129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next()); | |
| 130 | |
| 131 | |
| 132 // Floating Point Registers | |
| 133 | |
| 134 // XMM registers. 128-bit registers or 4 words each, labeled (a)-d. | |
| 135 // Word a in each register holds a Float, words ab hold a Double. We | |
| 136 // currently do not use the SIMD capabilities, so registers cd are | |
| 137 // unused at the moment. | |
| 138 // XMM8-XMM15 must be encoded with REX. | |
| 139 // Linux ABI: No register preserved across function calls | |
| 140 // XMM0-XMM7 might hold parameters | |
| 141 // Windows ABI: XMM6-XMM15 preserved across function calls | |
| 142 // XMM0-XMM3 might hold parameters | |
| 143 | |
| 144 reg_def XMM0 (SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()); | |
| 145 reg_def XMM0_H (SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next()); | |
| 146 | |
| 147 reg_def XMM1 (SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()); | |
| 148 reg_def XMM1_H (SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next()); | |
| 149 | |
| 150 reg_def XMM2 (SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()); | |
| 151 reg_def XMM2_H (SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next()); | |
| 152 | |
| 153 reg_def XMM3 (SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()); | |
| 154 reg_def XMM3_H (SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next()); | |
| 155 | |
| 156 reg_def XMM4 (SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()); | |
| 157 reg_def XMM4_H (SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next()); | |
| 158 | |
| 159 reg_def XMM5 (SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()); | |
| 160 reg_def XMM5_H (SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next()); | |
| 161 | |
| 162 #ifdef _WIN64 | |
| 163 | |
| 164 reg_def XMM6 (SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()); | |
| 165 reg_def XMM6_H (SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next()); | |
| 166 | |
| 167 reg_def XMM7 (SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()); | |
| 168 reg_def XMM7_H (SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next()); | |
| 169 | |
| 170 reg_def XMM8 (SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()); | |
| 171 reg_def XMM8_H (SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next()); | |
| 172 | |
| 173 reg_def XMM9 (SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()); | |
| 174 reg_def XMM9_H (SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next()); | |
| 175 | |
| 176 reg_def XMM10 (SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()); | |
| 177 reg_def XMM10_H(SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next()); | |
| 178 | |
| 179 reg_def XMM11 (SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()); | |
| 180 reg_def XMM11_H(SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next()); | |
| 181 | |
| 182 reg_def XMM12 (SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()); | |
| 183 reg_def XMM12_H(SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next()); | |
| 184 | |
| 185 reg_def XMM13 (SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()); | |
| 186 reg_def XMM13_H(SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next()); | |
| 187 | |
| 188 reg_def XMM14 (SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()); | |
| 189 reg_def XMM14_H(SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next()); | |
| 190 | |
| 191 reg_def XMM15 (SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()); | |
| 192 reg_def XMM15_H(SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next()); | |
| 193 | |
| 194 #else | |
| 195 | |
| 196 reg_def XMM6 (SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()); | |
| 197 reg_def XMM6_H (SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next()); | |
| 198 | |
| 199 reg_def XMM7 (SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()); | |
| 200 reg_def XMM7_H (SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next()); | |
| 201 | |
| 202 reg_def XMM8 (SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()); | |
| 203 reg_def XMM8_H (SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next()); | |
| 204 | |
| 205 reg_def XMM9 (SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()); | |
| 206 reg_def XMM9_H (SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next()); | |
| 207 | |
| 208 reg_def XMM10 (SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()); | |
| 209 reg_def XMM10_H(SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next()); | |
| 210 | |
| 211 reg_def XMM11 (SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()); | |
| 212 reg_def XMM11_H(SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next()); | |
| 213 | |
| 214 reg_def XMM12 (SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()); | |
| 215 reg_def XMM12_H(SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next()); | |
| 216 | |
| 217 reg_def XMM13 (SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()); | |
| 218 reg_def XMM13_H(SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next()); | |
| 219 | |
| 220 reg_def XMM14 (SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()); | |
| 221 reg_def XMM14_H(SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next()); | |
| 222 | |
| 223 reg_def XMM15 (SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()); | |
| 224 reg_def XMM15_H(SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next()); | |
| 225 | |
| 226 #endif // _WIN64 | |
| 227 | |
| 228 reg_def RFLAGS(SOC, SOC, 0, 16, VMRegImpl::Bad()); | |
| 229 | |
| 230 // Specify priority of register selection within phases of register | |
| 231 // allocation. Highest priority is first. A useful heuristic is to | |
| 232 // give registers a low priority when they are required by machine | |
| 233 // instructions, like EAX and EDX on I486, and choose no-save registers | |
| 234 // before save-on-call, & save-on-call before save-on-entry. Registers | |
| 235 // which participate in fixed calling sequences should come last. | |
| 236 // Registers which are used as pairs must fall on an even boundary. | |
| 237 | |
| 238 alloc_class chunk0(R10, R10_H, | |
| 239 R11, R11_H, | |
| 240 R8, R8_H, | |
| 241 R9, R9_H, | |
| 242 R12, R12_H, | |
| 243 RCX, RCX_H, | |
| 244 RBX, RBX_H, | |
| 245 RDI, RDI_H, | |
| 246 RDX, RDX_H, | |
| 247 RSI, RSI_H, | |
| 248 RAX, RAX_H, | |
| 249 RBP, RBP_H, | |
| 250 R13, R13_H, | |
| 251 R14, R14_H, | |
| 252 R15, R15_H, | |
| 253 RSP, RSP_H); | |
| 254 | |
| 255 // XXX probably use 8-15 first on Linux | |
| 256 alloc_class chunk1(XMM0, XMM0_H, | |
| 257 XMM1, XMM1_H, | |
| 258 XMM2, XMM2_H, | |
| 259 XMM3, XMM3_H, | |
| 260 XMM4, XMM4_H, | |
| 261 XMM5, XMM5_H, | |
| 262 XMM6, XMM6_H, | |
| 263 XMM7, XMM7_H, | |
| 264 XMM8, XMM8_H, | |
| 265 XMM9, XMM9_H, | |
| 266 XMM10, XMM10_H, | |
| 267 XMM11, XMM11_H, | |
| 268 XMM12, XMM12_H, | |
| 269 XMM13, XMM13_H, | |
| 270 XMM14, XMM14_H, | |
| 271 XMM15, XMM15_H); | |
| 272 | |
| 273 alloc_class chunk2(RFLAGS); | |
| 274 | |
| 275 | |
| 276 //----------Architecture Description Register Classes-------------------------- | |
| 277 // Several register classes are automatically defined based upon information in | |
| 278 // this architecture description. | |
| 279 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ ) | |
| 280 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ ) | |
| 281 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ ) | |
| 282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) | |
| 283 // | |
| 284 | |
| 285 // Class for all pointer registers (including RSP) | |
| 286 reg_class any_reg(RAX, RAX_H, | |
| 287 RDX, RDX_H, | |
| 288 RBP, RBP_H, | |
| 289 RDI, RDI_H, | |
| 290 RSI, RSI_H, | |
| 291 RCX, RCX_H, | |
| 292 RBX, RBX_H, | |
| 293 RSP, RSP_H, | |
| 294 R8, R8_H, | |
| 295 R9, R9_H, | |
| 296 R10, R10_H, | |
| 297 R11, R11_H, | |
| 298 R12, R12_H, | |
| 299 R13, R13_H, | |
| 300 R14, R14_H, | |
| 301 R15, R15_H); | |
| 302 | |
| 303 // Class for all pointer registers except RSP | |
| 304 reg_class ptr_reg(RAX, RAX_H, | |
| 305 RDX, RDX_H, | |
| 306 RBP, RBP_H, | |
| 307 RDI, RDI_H, | |
| 308 RSI, RSI_H, | |
| 309 RCX, RCX_H, | |
| 310 RBX, RBX_H, | |
| 311 R8, R8_H, | |
| 312 R9, R9_H, | |
| 313 R10, R10_H, | |
| 314 R11, R11_H, | |
| 315 R13, R13_H, | |
| 316 R14, R14_H); | |
| 317 | |
| 318 // Class for all pointer registers except RAX and RSP | |
| 319 reg_class ptr_no_rax_reg(RDX, RDX_H, | |
| 320 RBP, RBP_H, | |
| 321 RDI, RDI_H, | |
| 322 RSI, RSI_H, | |
| 323 RCX, RCX_H, | |
| 324 RBX, RBX_H, | |
| 325 R8, R8_H, | |
| 326 R9, R9_H, | |
| 327 R10, R10_H, | |
| 328 R11, R11_H, | |
| 329 R13, R13_H, | |
| 330 R14, R14_H); | |
| 331 | |
| 332 reg_class ptr_no_rbp_reg(RDX, RDX_H, | |
| 333 RAX, RAX_H, | |
| 334 RDI, RDI_H, | |
| 335 RSI, RSI_H, | |
| 336 RCX, RCX_H, | |
| 337 RBX, RBX_H, | |
| 338 R8, R8_H, | |
| 339 R9, R9_H, | |
| 340 R10, R10_H, | |
| 341 R11, R11_H, | |
| 342 R13, R13_H, | |
| 343 R14, R14_H); | |
| 344 | |
| 345 // Class for all pointer registers except RAX, RBX and RSP | |
| 346 reg_class ptr_no_rax_rbx_reg(RDX, RDX_H, | |
| 347 RBP, RBP_H, | |
| 348 RDI, RDI_H, | |
| 349 RSI, RSI_H, | |
| 350 RCX, RCX_H, | |
| 351 R8, R8_H, | |
| 352 R9, R9_H, | |
| 353 R10, R10_H, | |
| 354 R11, R11_H, | |
| 355 R13, R13_H, | |
| 356 R14, R14_H); | |
| 357 | |
| 358 // Singleton class for RAX pointer register | |
| 359 reg_class ptr_rax_reg(RAX, RAX_H); | |
| 360 | |
| 361 // Singleton class for RBX pointer register | |
| 362 reg_class ptr_rbx_reg(RBX, RBX_H); | |
| 363 | |
| 364 // Singleton class for RSI pointer register | |
| 365 reg_class ptr_rsi_reg(RSI, RSI_H); | |
| 366 | |
| 367 // Singleton class for RDI pointer register | |
| 368 reg_class ptr_rdi_reg(RDI, RDI_H); | |
| 369 | |
| 370 // Singleton class for RBP pointer register | |
| 371 reg_class ptr_rbp_reg(RBP, RBP_H); | |
| 372 | |
| 373 // Singleton class for stack pointer | |
| 374 reg_class ptr_rsp_reg(RSP, RSP_H); | |
| 375 | |
| 376 // Singleton class for TLS pointer | |
| 377 reg_class ptr_r15_reg(R15, R15_H); | |
| 378 | |
| 379 // Class for all long registers (except RSP) | |
| 380 reg_class long_reg(RAX, RAX_H, | |
| 381 RDX, RDX_H, | |
| 382 RBP, RBP_H, | |
| 383 RDI, RDI_H, | |
| 384 RSI, RSI_H, | |
| 385 RCX, RCX_H, | |
| 386 RBX, RBX_H, | |
| 387 R8, R8_H, | |
| 388 R9, R9_H, | |
| 389 R10, R10_H, | |
| 390 R11, R11_H, | |
| 391 R13, R13_H, | |
| 392 R14, R14_H); | |
| 393 | |
| 394 // Class for all long registers except RAX, RDX (and RSP) | |
| 395 reg_class long_no_rax_rdx_reg(RBP, RBP_H, | |
| 396 RDI, RDI_H, | |
| 397 RSI, RSI_H, | |
| 398 RCX, RCX_H, | |
| 399 RBX, RBX_H, | |
| 400 R8, R8_H, | |
| 401 R9, R9_H, | |
| 402 R10, R10_H, | |
| 403 R11, R11_H, | |
| 404 R13, R13_H, | |
| 405 R14, R14_H); | |
| 406 | |
| 407 // Class for all long registers except RCX (and RSP) | |
| 408 reg_class long_no_rcx_reg(RBP, RBP_H, | |
| 409 RDI, RDI_H, | |
| 410 RSI, RSI_H, | |
| 411 RAX, RAX_H, | |
| 412 RDX, RDX_H, | |
| 413 RBX, RBX_H, | |
| 414 R8, R8_H, | |
| 415 R9, R9_H, | |
| 416 R10, R10_H, | |
| 417 R11, R11_H, | |
| 418 R13, R13_H, | |
| 419 R14, R14_H); | |
| 420 | |
| 421 // Class for all long registers except RAX (and RSP) | |
| 422 reg_class long_no_rax_reg(RBP, RBP_H, | |
| 423 RDX, RDX_H, | |
| 424 RDI, RDI_H, | |
| 425 RSI, RSI_H, | |
| 426 RCX, RCX_H, | |
| 427 RBX, RBX_H, | |
| 428 R8, R8_H, | |
| 429 R9, R9_H, | |
| 430 R10, R10_H, | |
| 431 R11, R11_H, | |
| 432 R13, R13_H, | |
| 433 R14, R14_H); | |
| 434 | |
| 435 // Singleton class for RAX long register | |
| 436 reg_class long_rax_reg(RAX, RAX_H); | |
| 437 | |
| 438 // Singleton class for RCX long register | |
| 439 reg_class long_rcx_reg(RCX, RCX_H); | |
| 440 | |
| 441 // Singleton class for RDX long register | |
| 442 reg_class long_rdx_reg(RDX, RDX_H); | |
| 443 | |
| 444 // Class for all int registers (except RSP) | |
| 445 reg_class int_reg(RAX, | |
| 446 RDX, | |
| 447 RBP, | |
| 448 RDI, | |
| 449 RSI, | |
| 450 RCX, | |
| 451 RBX, | |
| 452 R8, | |
| 453 R9, | |
| 454 R10, | |
| 455 R11, | |
| 456 R13, | |
| 457 R14); | |
| 458 | |
| 459 // Class for all int registers except RCX (and RSP) | |
| 460 reg_class int_no_rcx_reg(RAX, | |
| 461 RDX, | |
| 462 RBP, | |
| 463 RDI, | |
| 464 RSI, | |
| 465 RBX, | |
| 466 R8, | |
| 467 R9, | |
| 468 R10, | |
| 469 R11, | |
| 470 R13, | |
| 471 R14); | |
| 472 | |
| 473 // Class for all int registers except RAX, RDX (and RSP) | |
| 474 reg_class int_no_rax_rdx_reg(RBP, | |
| 304 | 475 RDI, |
| 0 | 476 RSI, |
| 477 RCX, | |
| 478 RBX, | |
| 479 R8, | |
| 480 R9, | |
| 481 R10, | |
| 482 R11, | |
| 483 R13, | |
| 484 R14); | |
| 485 | |
| 486 // Singleton class for RAX int register | |
| 487 reg_class int_rax_reg(RAX); | |
| 488 | |
| 489 // Singleton class for RBX int register | |
| 490 reg_class int_rbx_reg(RBX); | |
| 491 | |
| 492 // Singleton class for RCX int register | |
| 493 reg_class int_rcx_reg(RCX); | |
| 494 | |
| 495 // Singleton class for RCX int register | |
| 496 reg_class int_rdx_reg(RDX); | |
| 497 | |
| 498 // Singleton class for RCX int register | |
| 499 reg_class int_rdi_reg(RDI); | |
| 500 | |
| 501 // Singleton class for instruction pointer | |
| 502 // reg_class ip_reg(RIP); | |
| 503 | |
| 504 // Singleton class for condition codes | |
| 505 reg_class int_flags(RFLAGS); | |
| 506 | |
| 507 // Class for all float registers | |
| 508 reg_class float_reg(XMM0, | |
| 509 XMM1, | |
| 510 XMM2, | |
| 511 XMM3, | |
| 512 XMM4, | |
| 513 XMM5, | |
| 514 XMM6, | |
| 515 XMM7, | |
| 516 XMM8, | |
| 517 XMM9, | |
| 518 XMM10, | |
| 519 XMM11, | |
| 520 XMM12, | |
| 521 XMM13, | |
| 522 XMM14, | |
| 523 XMM15); | |
| 524 | |
| 525 // Class for all double registers | |
| 526 reg_class double_reg(XMM0, XMM0_H, | |
| 527 XMM1, XMM1_H, | |
| 528 XMM2, XMM2_H, | |
| 529 XMM3, XMM3_H, | |
| 530 XMM4, XMM4_H, | |
| 531 XMM5, XMM5_H, | |
| 532 XMM6, XMM6_H, | |
| 533 XMM7, XMM7_H, | |
| 534 XMM8, XMM8_H, | |
| 535 XMM9, XMM9_H, | |
| 536 XMM10, XMM10_H, | |
| 537 XMM11, XMM11_H, | |
| 538 XMM12, XMM12_H, | |
| 539 XMM13, XMM13_H, | |
| 540 XMM14, XMM14_H, | |
| 541 XMM15, XMM15_H); | |
| 542 %} | |
| 543 | |
| 544 | |
| 545 //----------SOURCE BLOCK------------------------------------------------------- | |
| 546 // This is a block of C++ code which provides values, functions, and | |
| 547 // definitions necessary in the rest of the architecture description | |
| 548 source %{ | |
| 304 | 549 #define RELOC_IMM64 Assembler::imm_operand |
| 0 | 550 #define RELOC_DISP32 Assembler::disp32_operand |
| 551 | |
| 552 #define __ _masm. | |
| 553 | |
|
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554 static int preserve_SP_size() { |
| 4759 | 555 return 3; // rex.w, op, rm(reg/reg) |
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556 } |
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557 |
| 0 | 558 // !!!!! Special hack to get all types of calls to specify the byte offset |
| 559 // from the start of the call to the point where the return address | |
| 560 // will point. | |
| 561 int MachCallStaticJavaNode::ret_addr_offset() | |
| 562 { | |
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563 int offset = 5; // 5 bytes from start of call to where return address points |
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564 if (_method_handle_invoke) |
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565 offset += preserve_SP_size(); |
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566 return offset; |
| 0 | 567 } |
| 568 | |
| 569 int MachCallDynamicJavaNode::ret_addr_offset() | |
| 570 { | |
| 571 return 15; // 15 bytes from start of call to where return address points | |
| 572 } | |
| 573 | |
| 574 // In os_cpu .ad file | |
| 575 // int MachCallRuntimeNode::ret_addr_offset() | |
| 576 | |
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577 // Indicate if the safepoint node needs the polling page as an input, |
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578 // it does if the polling page is more than disp32 away. |
| 0 | 579 bool SafePointNode::needs_polling_address_input() |
| 580 { | |
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581 return Assembler::is_polling_page_far(); |
| 0 | 582 } |
| 583 | |
| 584 // | |
| 585 // Compute padding required for nodes which need alignment | |
| 586 // | |
| 587 | |
| 588 // The address of the call instruction needs to be 4-byte aligned to | |
| 589 // ensure that it does not span a cache line so that it can be patched. | |
| 590 int CallStaticJavaDirectNode::compute_padding(int current_offset) const | |
| 591 { | |
| 592 current_offset += 1; // skip call opcode byte | |
| 593 return round_to(current_offset, alignment_required()) - current_offset; | |
| 594 } | |
| 595 | |
| 596 // The address of the call instruction needs to be 4-byte aligned to | |
| 597 // ensure that it does not span a cache line so that it can be patched. | |
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598 int CallStaticJavaHandleNode::compute_padding(int current_offset) const |
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599 { |
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600 current_offset += preserve_SP_size(); // skip mov rbp, rsp |
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601 current_offset += 1; // skip call opcode byte |
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602 return round_to(current_offset, alignment_required()) - current_offset; |
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603 } |
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604 |
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605 // The address of the call instruction needs to be 4-byte aligned to |
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606 // ensure that it does not span a cache line so that it can be patched. |
| 0 | 607 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const |
| 608 { | |
| 609 current_offset += 11; // skip movq instruction + call opcode byte | |
| 610 return round_to(current_offset, alignment_required()) - current_offset; | |
| 611 } | |
| 612 | |
| 613 // EMIT_RM() | |
| 1748 | 614 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) { |
| 0 | 615 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3); |
| 1748 | 616 cbuf.insts()->emit_int8(c); |
| 0 | 617 } |
| 618 | |
| 619 // EMIT_CC() | |
| 1748 | 620 void emit_cc(CodeBuffer &cbuf, int f1, int f2) { |
| 0 | 621 unsigned char c = (unsigned char) (f1 | f2); |
| 1748 | 622 cbuf.insts()->emit_int8(c); |
| 0 | 623 } |
| 624 | |
| 625 // EMIT_OPCODE() | |
| 1748 | 626 void emit_opcode(CodeBuffer &cbuf, int code) { |
| 627 cbuf.insts()->emit_int8((unsigned char) code); | |
| 0 | 628 } |
| 629 | |
| 630 // EMIT_OPCODE() w/ relocation information | |
| 631 void emit_opcode(CodeBuffer &cbuf, | |
| 632 int code, relocInfo::relocType reloc, int offset, int format) | |
| 633 { | |
| 1748 | 634 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format); |
| 0 | 635 emit_opcode(cbuf, code); |
| 636 } | |
| 637 | |
| 638 // EMIT_D8() | |
| 1748 | 639 void emit_d8(CodeBuffer &cbuf, int d8) { |
| 640 cbuf.insts()->emit_int8((unsigned char) d8); | |
| 0 | 641 } |
| 642 | |
| 643 // EMIT_D16() | |
| 1748 | 644 void emit_d16(CodeBuffer &cbuf, int d16) { |
| 645 cbuf.insts()->emit_int16(d16); | |
| 0 | 646 } |
| 647 | |
| 648 // EMIT_D32() | |
| 1748 | 649 void emit_d32(CodeBuffer &cbuf, int d32) { |
| 650 cbuf.insts()->emit_int32(d32); | |
| 0 | 651 } |
| 652 | |
| 653 // EMIT_D64() | |
| 1748 | 654 void emit_d64(CodeBuffer &cbuf, int64_t d64) { |
| 655 cbuf.insts()->emit_int64(d64); | |
| 0 | 656 } |
| 657 | |
| 658 // emit 32 bit value and construct relocation entry from relocInfo::relocType | |
| 659 void emit_d32_reloc(CodeBuffer& cbuf, | |
| 660 int d32, | |
| 661 relocInfo::relocType reloc, | |
| 662 int format) | |
| 663 { | |
| 664 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc"); | |
| 1748 | 665 cbuf.relocate(cbuf.insts_mark(), reloc, format); |
| 666 cbuf.insts()->emit_int32(d32); | |
| 0 | 667 } |
| 668 | |
| 669 // emit 32 bit value and construct relocation entry from RelocationHolder | |
| 1748 | 670 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) { |
| 0 | 671 #ifdef ASSERT |
| 672 if (rspec.reloc()->type() == relocInfo::oop_type && | |
| 673 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) { | |
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674 assert(oop((intptr_t)d32)->is_oop() && (ScavengeRootsInCode || !oop((intptr_t)d32)->is_scavengable()), "cannot embed scavengable oops in code"); |
| 0 | 675 } |
| 676 #endif | |
| 1748 | 677 cbuf.relocate(cbuf.insts_mark(), rspec, format); |
| 678 cbuf.insts()->emit_int32(d32); | |
| 0 | 679 } |
| 680 | |
| 681 void emit_d32_reloc(CodeBuffer& cbuf, address addr) { | |
| 1748 | 682 address next_ip = cbuf.insts_end() + 4; |
| 0 | 683 emit_d32_reloc(cbuf, (int) (addr - next_ip), |
| 684 external_word_Relocation::spec(addr), | |
| 685 RELOC_DISP32); | |
| 686 } | |
| 687 | |
| 688 | |
| 689 // emit 64 bit value and construct relocation entry from relocInfo::relocType | |
| 1748 | 690 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) { |
| 691 cbuf.relocate(cbuf.insts_mark(), reloc, format); | |
| 692 cbuf.insts()->emit_int64(d64); | |
| 0 | 693 } |
| 694 | |
| 695 // emit 64 bit value and construct relocation entry from RelocationHolder | |
| 1748 | 696 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) { |
| 0 | 697 #ifdef ASSERT |
| 698 if (rspec.reloc()->type() == relocInfo::oop_type && | |
| 699 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) { | |
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700 assert(oop(d64)->is_oop() && (ScavengeRootsInCode || !oop(d64)->is_scavengable()), |
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701 "cannot embed scavengable oops in code"); |
| 0 | 702 } |
| 703 #endif | |
| 1748 | 704 cbuf.relocate(cbuf.insts_mark(), rspec, format); |
| 705 cbuf.insts()->emit_int64(d64); | |
| 0 | 706 } |
| 707 | |
| 708 // Access stack slot for load or store | |
| 709 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) | |
| 710 { | |
| 711 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src]) | |
| 712 if (-0x80 <= disp && disp < 0x80) { | |
| 713 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte | |
| 714 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte | |
| 715 emit_d8(cbuf, disp); // Displacement // R/M byte | |
| 716 } else { | |
| 717 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte | |
| 718 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte | |
| 719 emit_d32(cbuf, disp); // Displacement // R/M byte | |
| 720 } | |
| 721 } | |
| 722 | |
| 723 // rRegI ereg, memory mem) %{ // emit_reg_mem | |
| 724 void encode_RegMem(CodeBuffer &cbuf, | |
| 725 int reg, | |
| 726 int base, int index, int scale, int disp, bool disp_is_oop) | |
| 727 { | |
| 728 assert(!disp_is_oop, "cannot have disp"); | |
| 729 int regenc = reg & 7; | |
| 730 int baseenc = base & 7; | |
| 731 int indexenc = index & 7; | |
| 732 | |
| 733 // There is no index & no scale, use form without SIB byte | |
| 734 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) { | |
| 735 // If no displacement, mode is 0x0; unless base is [RBP] or [R13] | |
| 736 if (disp == 0 && base != RBP_enc && base != R13_enc) { | |
| 737 emit_rm(cbuf, 0x0, regenc, baseenc); // * | |
| 738 } else if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) { | |
| 739 // If 8-bit displacement, mode 0x1 | |
| 740 emit_rm(cbuf, 0x1, regenc, baseenc); // * | |
| 741 emit_d8(cbuf, disp); | |
| 742 } else { | |
| 743 // If 32-bit displacement | |
| 744 if (base == -1) { // Special flag for absolute address | |
| 745 emit_rm(cbuf, 0x0, regenc, 0x5); // * | |
| 746 if (disp_is_oop) { | |
| 747 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32); | |
| 748 } else { | |
| 749 emit_d32(cbuf, disp); | |
| 750 } | |
| 751 } else { | |
| 752 // Normal base + offset | |
| 753 emit_rm(cbuf, 0x2, regenc, baseenc); // * | |
| 754 if (disp_is_oop) { | |
| 755 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32); | |
| 756 } else { | |
| 757 emit_d32(cbuf, disp); | |
| 758 } | |
| 759 } | |
| 760 } | |
| 761 } else { | |
| 762 // Else, encode with the SIB byte | |
| 763 // If no displacement, mode is 0x0; unless base is [RBP] or [R13] | |
| 764 if (disp == 0 && base != RBP_enc && base != R13_enc) { | |
| 765 // If no displacement | |
| 766 emit_rm(cbuf, 0x0, regenc, 0x4); // * | |
| 767 emit_rm(cbuf, scale, indexenc, baseenc); | |
| 768 } else { | |
| 769 if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) { | |
| 770 // If 8-bit displacement, mode 0x1 | |
| 771 emit_rm(cbuf, 0x1, regenc, 0x4); // * | |
| 772 emit_rm(cbuf, scale, indexenc, baseenc); | |
| 773 emit_d8(cbuf, disp); | |
| 774 } else { | |
| 775 // If 32-bit displacement | |
| 776 if (base == 0x04 ) { | |
| 777 emit_rm(cbuf, 0x2, regenc, 0x4); | |
| 778 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid??? | |
| 779 } else { | |
| 780 emit_rm(cbuf, 0x2, regenc, 0x4); | |
| 781 emit_rm(cbuf, scale, indexenc, baseenc); // * | |
| 782 } | |
| 783 if (disp_is_oop) { | |
| 784 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32); | |
| 785 } else { | |
| 786 emit_d32(cbuf, disp); | |
| 787 } | |
| 788 } | |
| 789 } | |
| 790 } | |
| 791 } | |
| 792 | |
| 3783 | 793 // This could be in MacroAssembler but it's fairly C2 specific |
| 794 void emit_cmpfp_fixup(MacroAssembler& _masm) { | |
| 795 Label exit; | |
| 796 __ jccb(Assembler::noParity, exit); | |
| 797 __ pushf(); | |
| 4759 | 798 // |
| 799 // comiss/ucomiss instructions set ZF,PF,CF flags and | |
| 800 // zero OF,AF,SF for NaN values. | |
| 801 // Fixup flags by zeroing ZF,PF so that compare of NaN | |
| 802 // values returns 'less than' result (CF is set). | |
| 803 // Leave the rest of flags unchanged. | |
| 804 // | |
| 805 // 7 6 5 4 3 2 1 0 | |
| 806 // |S|Z|r|A|r|P|r|C| (r - reserved bit) | |
| 807 // 0 0 1 0 1 0 1 1 (0x2B) | |
| 808 // | |
| 3783 | 809 __ andq(Address(rsp, 0), 0xffffff2b); |
| 810 __ popf(); | |
| 811 __ bind(exit); | |
| 4759 | 812 } |
| 813 | |
| 814 void emit_cmpfp3(MacroAssembler& _masm, Register dst) { | |
| 815 Label done; | |
| 816 __ movl(dst, -1); | |
| 817 __ jcc(Assembler::parity, done); | |
| 818 __ jcc(Assembler::below, done); | |
| 819 __ setb(Assembler::notEqual, dst); | |
| 820 __ movzbl(dst, dst); | |
| 821 __ bind(done); | |
| 3783 | 822 } |
| 823 | |
| 0 | 824 |
| 825 //============================================================================= | |
| 2008 | 826 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty; |
| 827 | |
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828 int Compile::ConstantTable::calculate_table_base_offset() const { |
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829 return 0; // absolute addressing, no offset |
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830 } |
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831 |
| 2008 | 832 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { |
| 833 // Empty encoding | |
| 834 } | |
| 835 | |
| 836 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const { | |
| 837 return 0; | |
| 838 } | |
| 839 | |
| 840 #ifndef PRODUCT | |
| 841 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { | |
| 842 st->print("# MachConstantBaseNode (empty encoding)"); | |
| 843 } | |
| 844 #endif | |
| 845 | |
| 846 | |
| 847 //============================================================================= | |
| 0 | 848 #ifndef PRODUCT |
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849 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const { |
| 0 | 850 Compile* C = ra_->C; |
| 851 | |
| 852 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 853 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
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854 // Remove wordSize for return addr which is already pushed. |
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855 framesize -= wordSize; |
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856 |
| 0 | 857 if (C->need_stack_bang(framesize)) { |
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858 framesize -= wordSize; |
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859 st->print("# stack bang"); |
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860 st->print("\n\t"); |
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861 st->print("pushq rbp\t# Save rbp"); |
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862 if (framesize) { |
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863 st->print("\n\t"); |
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864 st->print("subq rsp, #%d\t# Create frame",framesize); |
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865 } |
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866 } else { |
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867 st->print("subq rsp, #%d\t# Create frame",framesize); |
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868 st->print("\n\t"); |
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869 framesize -= wordSize; |
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870 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize); |
| 0 | 871 } |
| 872 | |
| 873 if (VerifyStackAtCalls) { | |
|
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874 st->print("\n\t"); |
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875 framesize -= wordSize; |
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876 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize); |
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877 #ifdef ASSERT |
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878 st->print("\n\t"); |
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879 st->print("# stack alignment check"); |
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880 #endif |
| 0 | 881 } |
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882 st->cr(); |
| 0 | 883 } |
| 884 #endif | |
| 885 | |
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886 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { |
| 0 | 887 Compile* C = ra_->C; |
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888 MacroAssembler _masm(&cbuf); |
| 0 | 889 |
| 890 int framesize = C->frame_slots() << LogBytesPerInt; | |
|
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891 |
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892 __ verified_entry(framesize, C->need_stack_bang(framesize), false); |
| 0 | 893 |
| 1748 | 894 C->set_frame_complete(cbuf.insts_size()); |
| 0 | 895 |
|
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896 if (C->has_mach_constant_base_node()) { |
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897 // NOTE: We set the table base offset here because users might be |
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898 // emitted before MachConstantBaseNode. |
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899 Compile::ConstantTable& constant_table = C->constant_table(); |
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900 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset()); |
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901 } |
| 0 | 902 } |
| 903 | |
| 904 uint MachPrologNode::size(PhaseRegAlloc* ra_) const | |
| 905 { | |
| 906 return MachNode::size(ra_); // too many variables; just compute it | |
| 907 // the hard way | |
| 908 } | |
| 909 | |
| 910 int MachPrologNode::reloc() const | |
| 911 { | |
| 912 return 0; // a large enough number | |
| 913 } | |
| 914 | |
| 915 //============================================================================= | |
| 916 #ifndef PRODUCT | |
| 917 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const | |
| 918 { | |
| 919 Compile* C = ra_->C; | |
| 920 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 921 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 922 // Remove word for return adr already pushed | |
| 923 // and RBP | |
| 924 framesize -= 2*wordSize; | |
| 925 | |
| 926 if (framesize) { | |
|
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927 st->print_cr("addq rsp, %d\t# Destroy frame", framesize); |
| 0 | 928 st->print("\t"); |
| 929 } | |
| 930 | |
|
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931 st->print_cr("popq rbp"); |
| 0 | 932 if (do_polling() && C->is_method_compilation()) { |
| 933 st->print("\t"); | |
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934 if (Assembler::is_polling_page_far()) { |
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935 st->print_cr("movq rscratch1, #polling_page_address\n\t" |
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936 "testl rax, [rscratch1]\t" |
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937 "# Safepoint: poll for GC"); |
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938 } else { |
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939 st->print_cr("testl rax, [rip + #offset_to_poll_page]\t" |
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940 "# Safepoint: poll for GC"); |
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941 } |
| 0 | 942 } |
| 943 } | |
| 944 #endif | |
| 945 | |
| 946 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const | |
| 947 { | |
| 948 Compile* C = ra_->C; | |
| 949 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 950 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 951 // Remove word for return adr already pushed | |
| 952 // and RBP | |
| 953 framesize -= 2*wordSize; | |
| 954 | |
| 955 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here | |
| 956 | |
| 957 if (framesize) { | |
| 958 emit_opcode(cbuf, Assembler::REX_W); | |
| 959 if (framesize < 0x80) { | |
| 960 emit_opcode(cbuf, 0x83); // addq rsp, #framesize | |
| 961 emit_rm(cbuf, 0x3, 0x00, RSP_enc); | |
| 962 emit_d8(cbuf, framesize); | |
| 963 } else { | |
| 964 emit_opcode(cbuf, 0x81); // addq rsp, #framesize | |
| 965 emit_rm(cbuf, 0x3, 0x00, RSP_enc); | |
| 966 emit_d32(cbuf, framesize); | |
| 967 } | |
| 968 } | |
| 969 | |
| 970 // popq rbp | |
| 971 emit_opcode(cbuf, 0x58 | RBP_enc); | |
| 972 | |
| 973 if (do_polling() && C->is_method_compilation()) { | |
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974 MacroAssembler _masm(&cbuf); |
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975 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type); |
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976 if (Assembler::is_polling_page_far()) { |
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977 __ lea(rscratch1, polling_page); |
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978 __ relocate(relocInfo::poll_return_type); |
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979 __ testl(rax, Address(rscratch1, 0)); |
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980 } else { |
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981 __ testl(rax, polling_page); |
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982 } |
| 0 | 983 } |
| 984 } | |
| 985 | |
| 986 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const | |
| 987 { | |
|
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988 return MachNode::size(ra_); // too many variables; just compute it |
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989 // the hard way |
| 0 | 990 } |
| 991 | |
| 992 int MachEpilogNode::reloc() const | |
| 993 { | |
| 994 return 2; // a large enough number | |
| 995 } | |
| 996 | |
| 997 const Pipeline* MachEpilogNode::pipeline() const | |
| 998 { | |
| 999 return MachNode::pipeline_class(); | |
| 1000 } | |
| 1001 | |
| 1002 int MachEpilogNode::safepoint_offset() const | |
| 1003 { | |
| 1004 return 0; | |
| 1005 } | |
| 1006 | |
| 1007 //============================================================================= | |
| 1008 | |
| 1009 enum RC { | |
| 1010 rc_bad, | |
| 1011 rc_int, | |
| 1012 rc_float, | |
| 1013 rc_stack | |
| 1014 }; | |
| 1015 | |
| 1016 static enum RC rc_class(OptoReg::Name reg) | |
| 1017 { | |
| 1018 if( !OptoReg::is_valid(reg) ) return rc_bad; | |
| 1019 | |
| 1020 if (OptoReg::is_stack(reg)) return rc_stack; | |
| 1021 | |
| 1022 VMReg r = OptoReg::as_VMReg(reg); | |
| 1023 | |
| 1024 if (r->is_Register()) return rc_int; | |
| 1025 | |
| 1026 assert(r->is_XMMRegister(), "must be"); | |
| 1027 return rc_float; | |
| 1028 } | |
| 1029 | |
| 1030 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf, | |
| 1031 PhaseRegAlloc* ra_, | |
| 1032 bool do_size, | |
| 1033 outputStream* st) const | |
| 1034 { | |
| 1035 | |
| 1036 // Get registers to move | |
| 1037 OptoReg::Name src_second = ra_->get_reg_second(in(1)); | |
| 1038 OptoReg::Name src_first = ra_->get_reg_first(in(1)); | |
| 1039 OptoReg::Name dst_second = ra_->get_reg_second(this); | |
| 1040 OptoReg::Name dst_first = ra_->get_reg_first(this); | |
| 1041 | |
| 1042 enum RC src_second_rc = rc_class(src_second); | |
| 1043 enum RC src_first_rc = rc_class(src_first); | |
| 1044 enum RC dst_second_rc = rc_class(dst_second); | |
| 1045 enum RC dst_first_rc = rc_class(dst_first); | |
| 1046 | |
| 1047 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), | |
| 1048 "must move at least 1 register" ); | |
| 1049 | |
| 1050 if (src_first == dst_first && src_second == dst_second) { | |
| 1051 // Self copy, no move | |
| 1052 return 0; | |
| 1053 } else if (src_first_rc == rc_stack) { | |
| 1054 // mem -> | |
| 1055 if (dst_first_rc == rc_stack) { | |
| 1056 // mem -> mem | |
| 1057 assert(src_second != dst_first, "overlap"); | |
| 1058 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1059 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1060 // 64-bit | |
| 1061 int src_offset = ra_->reg2offset(src_first); | |
| 1062 int dst_offset = ra_->reg2offset(dst_first); | |
| 1063 if (cbuf) { | |
| 1064 emit_opcode(*cbuf, 0xFF); | |
| 1065 encode_RegMem(*cbuf, RSI_enc, RSP_enc, 0x4, 0, src_offset, false); | |
| 1066 | |
| 1067 emit_opcode(*cbuf, 0x8F); | |
| 1068 encode_RegMem(*cbuf, RAX_enc, RSP_enc, 0x4, 0, dst_offset, false); | |
| 1069 | |
| 1070 #ifndef PRODUCT | |
| 1071 } else if (!do_size) { | |
| 1072 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t" | |
| 1073 "popq [rsp + #%d]", | |
| 1074 src_offset, | |
| 1075 dst_offset); | |
| 1076 #endif | |
| 1077 } | |
| 1078 return | |
| 1079 3 + ((src_offset == 0) ? 0 : (src_offset < 0x80 ? 1 : 4)) + | |
| 1080 3 + ((dst_offset == 0) ? 0 : (dst_offset < 0x80 ? 1 : 4)); | |
| 1081 } else { | |
| 1082 // 32-bit | |
| 1083 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1084 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1085 // No pushl/popl, so: | |
| 1086 int src_offset = ra_->reg2offset(src_first); | |
| 1087 int dst_offset = ra_->reg2offset(dst_first); | |
| 1088 if (cbuf) { | |
| 1089 emit_opcode(*cbuf, Assembler::REX_W); | |
| 1090 emit_opcode(*cbuf, 0x89); | |
| 1091 emit_opcode(*cbuf, 0x44); | |
| 1092 emit_opcode(*cbuf, 0x24); | |
| 1093 emit_opcode(*cbuf, 0xF8); | |
| 1094 | |
| 1095 emit_opcode(*cbuf, 0x8B); | |
| 1096 encode_RegMem(*cbuf, | |
| 1097 RAX_enc, | |
| 1098 RSP_enc, 0x4, 0, src_offset, | |
| 1099 false); | |
| 1100 | |
| 1101 emit_opcode(*cbuf, 0x89); | |
| 1102 encode_RegMem(*cbuf, | |
| 1103 RAX_enc, | |
| 1104 RSP_enc, 0x4, 0, dst_offset, | |
| 1105 false); | |
| 1106 | |
| 1107 emit_opcode(*cbuf, Assembler::REX_W); | |
| 1108 emit_opcode(*cbuf, 0x8B); | |
| 1109 emit_opcode(*cbuf, 0x44); | |
| 1110 emit_opcode(*cbuf, 0x24); | |
| 1111 emit_opcode(*cbuf, 0xF8); | |
| 1112 | |
| 1113 #ifndef PRODUCT | |
| 1114 } else if (!do_size) { | |
| 1115 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t" | |
| 1116 "movl rax, [rsp + #%d]\n\t" | |
| 1117 "movl [rsp + #%d], rax\n\t" | |
| 1118 "movq rax, [rsp - #8]", | |
| 1119 src_offset, | |
| 1120 dst_offset); | |
| 1121 #endif | |
| 1122 } | |
| 1123 return | |
| 1124 5 + // movq | |
| 1125 3 + ((src_offset == 0) ? 0 : (src_offset < 0x80 ? 1 : 4)) + // movl | |
| 1126 3 + ((dst_offset == 0) ? 0 : (dst_offset < 0x80 ? 1 : 4)) + // movl | |
| 1127 5; // movq | |
| 1128 } | |
| 1129 } else if (dst_first_rc == rc_int) { | |
| 1130 // mem -> gpr | |
| 1131 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1132 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1133 // 64-bit | |
| 1134 int offset = ra_->reg2offset(src_first); | |
| 1135 if (cbuf) { | |
| 1136 if (Matcher::_regEncode[dst_first] < 8) { | |
| 1137 emit_opcode(*cbuf, Assembler::REX_W); | |
| 1138 } else { | |
| 1139 emit_opcode(*cbuf, Assembler::REX_WR); | |
| 1140 } | |
| 1141 emit_opcode(*cbuf, 0x8B); | |
| 1142 encode_RegMem(*cbuf, | |
| 1143 Matcher::_regEncode[dst_first], | |
| 1144 RSP_enc, 0x4, 0, offset, | |
| 1145 false); | |
| 1146 #ifndef PRODUCT | |
| 1147 } else if (!do_size) { | |
| 1148 st->print("movq %s, [rsp + #%d]\t# spill", | |
| 1149 Matcher::regName[dst_first], | |
| 1150 offset); | |
| 1151 #endif | |
| 1152 } | |
| 1153 return | |
| 1154 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + 4; // REX | |
| 1155 } else { | |
| 1156 // 32-bit | |
| 1157 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1158 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1159 int offset = ra_->reg2offset(src_first); | |
| 1160 if (cbuf) { | |
| 1161 if (Matcher::_regEncode[dst_first] >= 8) { | |
| 1162 emit_opcode(*cbuf, Assembler::REX_R); | |
| 1163 } | |
| 1164 emit_opcode(*cbuf, 0x8B); | |
| 1165 encode_RegMem(*cbuf, | |
| 1166 Matcher::_regEncode[dst_first], | |
| 1167 RSP_enc, 0x4, 0, offset, | |
| 1168 false); | |
| 1169 #ifndef PRODUCT | |
| 1170 } else if (!do_size) { | |
| 1171 st->print("movl %s, [rsp + #%d]\t# spill", | |
| 1172 Matcher::regName[dst_first], | |
| 1173 offset); | |
| 1174 #endif | |
| 1175 } | |
| 1176 return | |
| 1177 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + | |
| 1178 ((Matcher::_regEncode[dst_first] < 8) | |
| 1179 ? 3 | |
| 1180 : 4); // REX | |
| 1181 } | |
| 1182 } else if (dst_first_rc == rc_float) { | |
| 1183 // mem-> xmm | |
| 1184 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1185 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1186 // 64-bit | |
| 1187 int offset = ra_->reg2offset(src_first); | |
| 1188 if (cbuf) { | |
| 4759 | 1189 MacroAssembler _masm(cbuf); |
| 1190 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset)); | |
| 0 | 1191 #ifndef PRODUCT |
| 1192 } else if (!do_size) { | |
| 1193 st->print("%s %s, [rsp + #%d]\t# spill", | |
| 1194 UseXmmLoadAndClearUpper ? "movsd " : "movlpd", | |
| 1195 Matcher::regName[dst_first], | |
| 1196 offset); | |
| 1197 #endif | |
| 1198 } | |
| 1199 return | |
| 1200 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + | |
| 4759 | 1201 ((Matcher::_regEncode[dst_first] >= 8) |
| 1202 ? 6 | |
| 1203 : (5 + ((UseAVX>0)?1:0))); // REX | |
| 0 | 1204 } else { |
| 1205 // 32-bit | |
| 1206 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1207 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1208 int offset = ra_->reg2offset(src_first); | |
| 1209 if (cbuf) { | |
| 4759 | 1210 MacroAssembler _masm(cbuf); |
| 1211 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset)); | |
| 0 | 1212 #ifndef PRODUCT |
| 1213 } else if (!do_size) { | |
| 1214 st->print("movss %s, [rsp + #%d]\t# spill", | |
| 1215 Matcher::regName[dst_first], | |
| 1216 offset); | |
| 1217 #endif | |
| 1218 } | |
| 1219 return | |
| 1220 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + | |
| 4759 | 1221 ((Matcher::_regEncode[dst_first] >= 8) |
| 1222 ? 6 | |
| 1223 : (5 + ((UseAVX>0)?1:0))); // REX | |
| 0 | 1224 } |
| 1225 } | |
| 1226 } else if (src_first_rc == rc_int) { | |
| 1227 // gpr -> | |
| 1228 if (dst_first_rc == rc_stack) { | |
| 1229 // gpr -> mem | |
| 1230 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1231 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1232 // 64-bit | |
| 1233 int offset = ra_->reg2offset(dst_first); | |
| 1234 if (cbuf) { | |
| 1235 if (Matcher::_regEncode[src_first] < 8) { | |
| 1236 emit_opcode(*cbuf, Assembler::REX_W); | |
| 1237 } else { | |
| 1238 emit_opcode(*cbuf, Assembler::REX_WR); | |
| 1239 } | |
| 1240 emit_opcode(*cbuf, 0x89); | |
| 1241 encode_RegMem(*cbuf, | |
| 1242 Matcher::_regEncode[src_first], | |
| 1243 RSP_enc, 0x4, 0, offset, | |
| 1244 false); | |
| 1245 #ifndef PRODUCT | |
| 1246 } else if (!do_size) { | |
| 1247 st->print("movq [rsp + #%d], %s\t# spill", | |
| 1248 offset, | |
| 1249 Matcher::regName[src_first]); | |
| 1250 #endif | |
| 1251 } | |
| 1252 return ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + 4; // REX | |
| 1253 } else { | |
| 1254 // 32-bit | |
| 1255 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1256 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1257 int offset = ra_->reg2offset(dst_first); | |
| 1258 if (cbuf) { | |
| 1259 if (Matcher::_regEncode[src_first] >= 8) { | |
| 1260 emit_opcode(*cbuf, Assembler::REX_R); | |
| 1261 } | |
| 1262 emit_opcode(*cbuf, 0x89); | |
| 1263 encode_RegMem(*cbuf, | |
| 1264 Matcher::_regEncode[src_first], | |
| 1265 RSP_enc, 0x4, 0, offset, | |
| 1266 false); | |
| 1267 #ifndef PRODUCT | |
| 1268 } else if (!do_size) { | |
| 1269 st->print("movl [rsp + #%d], %s\t# spill", | |
| 1270 offset, | |
| 1271 Matcher::regName[src_first]); | |
| 1272 #endif | |
| 1273 } | |
| 1274 return | |
| 1275 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + | |
| 1276 ((Matcher::_regEncode[src_first] < 8) | |
| 1277 ? 3 | |
| 1278 : 4); // REX | |
| 1279 } | |
| 1280 } else if (dst_first_rc == rc_int) { | |
| 1281 // gpr -> gpr | |
| 1282 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1283 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1284 // 64-bit | |
| 1285 if (cbuf) { | |
| 1286 if (Matcher::_regEncode[dst_first] < 8) { | |
| 1287 if (Matcher::_regEncode[src_first] < 8) { | |
| 1288 emit_opcode(*cbuf, Assembler::REX_W); | |
| 1289 } else { | |
| 1290 emit_opcode(*cbuf, Assembler::REX_WB); | |
| 1291 } | |
| 1292 } else { | |
| 1293 if (Matcher::_regEncode[src_first] < 8) { | |
| 1294 emit_opcode(*cbuf, Assembler::REX_WR); | |
| 1295 } else { | |
| 1296 emit_opcode(*cbuf, Assembler::REX_WRB); | |
| 1297 } | |
| 1298 } | |
| 1299 emit_opcode(*cbuf, 0x8B); | |
| 1300 emit_rm(*cbuf, 0x3, | |
| 1301 Matcher::_regEncode[dst_first] & 7, | |
| 1302 Matcher::_regEncode[src_first] & 7); | |
| 1303 #ifndef PRODUCT | |
| 1304 } else if (!do_size) { | |
| 1305 st->print("movq %s, %s\t# spill", | |
| 1306 Matcher::regName[dst_first], | |
| 1307 Matcher::regName[src_first]); | |
| 1308 #endif | |
| 1309 } | |
| 1310 return 3; // REX | |
| 1311 } else { | |
| 1312 // 32-bit | |
| 1313 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1314 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1315 if (cbuf) { | |
| 1316 if (Matcher::_regEncode[dst_first] < 8) { | |
| 1317 if (Matcher::_regEncode[src_first] >= 8) { | |
| 1318 emit_opcode(*cbuf, Assembler::REX_B); | |
| 1319 } | |
| 1320 } else { | |
| 1321 if (Matcher::_regEncode[src_first] < 8) { | |
| 1322 emit_opcode(*cbuf, Assembler::REX_R); | |
| 1323 } else { | |
| 1324 emit_opcode(*cbuf, Assembler::REX_RB); | |
| 1325 } | |
| 1326 } | |
| 1327 emit_opcode(*cbuf, 0x8B); | |
| 1328 emit_rm(*cbuf, 0x3, | |
| 1329 Matcher::_regEncode[dst_first] & 7, | |
| 1330 Matcher::_regEncode[src_first] & 7); | |
| 1331 #ifndef PRODUCT | |
| 1332 } else if (!do_size) { | |
| 1333 st->print("movl %s, %s\t# spill", | |
| 1334 Matcher::regName[dst_first], | |
| 1335 Matcher::regName[src_first]); | |
| 1336 #endif | |
| 1337 } | |
| 1338 return | |
| 1339 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8) | |
| 1340 ? 2 | |
| 1341 : 3; // REX | |
| 1342 } | |
| 1343 } else if (dst_first_rc == rc_float) { | |
| 1344 // gpr -> xmm | |
| 1345 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1346 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1347 // 64-bit | |
| 1348 if (cbuf) { | |
| 4759 | 1349 MacroAssembler _masm(cbuf); |
| 1350 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first])); | |
| 0 | 1351 #ifndef PRODUCT |
| 1352 } else if (!do_size) { | |
| 1353 st->print("movdq %s, %s\t# spill", | |
| 1354 Matcher::regName[dst_first], | |
| 1355 Matcher::regName[src_first]); | |
| 1356 #endif | |
| 1357 } | |
| 1358 return 5; // REX | |
| 1359 } else { | |
| 1360 // 32-bit | |
| 1361 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1362 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1363 if (cbuf) { | |
| 4759 | 1364 MacroAssembler _masm(cbuf); |
| 1365 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first])); | |
| 0 | 1366 #ifndef PRODUCT |
| 1367 } else if (!do_size) { | |
| 1368 st->print("movdl %s, %s\t# spill", | |
| 1369 Matcher::regName[dst_first], | |
| 1370 Matcher::regName[src_first]); | |
| 1371 #endif | |
| 1372 } | |
| 1373 return | |
| 4759 | 1374 (Matcher::_regEncode[src_first] >= 8 || Matcher::_regEncode[dst_first] >= 8) |
| 1375 ? 5 | |
| 1376 : (4 + ((UseAVX>0)?1:0)); // REX | |
| 0 | 1377 } |
| 1378 } | |
| 1379 } else if (src_first_rc == rc_float) { | |
| 1380 // xmm -> | |
| 1381 if (dst_first_rc == rc_stack) { | |
| 1382 // xmm -> mem | |
| 1383 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1384 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1385 // 64-bit | |
| 1386 int offset = ra_->reg2offset(dst_first); | |
| 1387 if (cbuf) { | |
| 4759 | 1388 MacroAssembler _masm(cbuf); |
| 1389 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first])); | |
| 0 | 1390 #ifndef PRODUCT |
| 1391 } else if (!do_size) { | |
| 1392 st->print("movsd [rsp + #%d], %s\t# spill", | |
| 1393 offset, | |
| 1394 Matcher::regName[src_first]); | |
| 1395 #endif | |
| 1396 } | |
| 1397 return | |
| 1398 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + | |
| 4759 | 1399 ((Matcher::_regEncode[src_first] >= 8) |
| 1400 ? 6 | |
| 1401 : (5 + ((UseAVX>0)?1:0))); // REX | |
| 0 | 1402 } else { |
| 1403 // 32-bit | |
| 1404 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1405 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1406 int offset = ra_->reg2offset(dst_first); | |
| 1407 if (cbuf) { | |
| 4759 | 1408 MacroAssembler _masm(cbuf); |
| 1409 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first])); | |
| 0 | 1410 #ifndef PRODUCT |
| 1411 } else if (!do_size) { | |
| 1412 st->print("movss [rsp + #%d], %s\t# spill", | |
| 1413 offset, | |
| 1414 Matcher::regName[src_first]); | |
| 1415 #endif | |
| 1416 } | |
| 1417 return | |
| 1418 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + | |
| 4759 | 1419 ((Matcher::_regEncode[src_first] >=8) |
| 1420 ? 6 | |
| 1421 : (5 + ((UseAVX>0)?1:0))); // REX | |
| 0 | 1422 } |
| 1423 } else if (dst_first_rc == rc_int) { | |
| 1424 // xmm -> gpr | |
| 1425 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1426 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1427 // 64-bit | |
| 1428 if (cbuf) { | |
| 4759 | 1429 MacroAssembler _masm(cbuf); |
| 1430 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first])); | |
| 0 | 1431 #ifndef PRODUCT |
| 1432 } else if (!do_size) { | |
| 1433 st->print("movdq %s, %s\t# spill", | |
| 1434 Matcher::regName[dst_first], | |
| 1435 Matcher::regName[src_first]); | |
| 1436 #endif | |
| 1437 } | |
| 1438 return 5; // REX | |
| 1439 } else { | |
| 1440 // 32-bit | |
| 1441 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1442 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1443 if (cbuf) { | |
| 4759 | 1444 MacroAssembler _masm(cbuf); |
| 1445 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first])); | |
| 0 | 1446 #ifndef PRODUCT |
| 1447 } else if (!do_size) { | |
| 1448 st->print("movdl %s, %s\t# spill", | |
| 1449 Matcher::regName[dst_first], | |
| 1450 Matcher::regName[src_first]); | |
| 1451 #endif | |
| 1452 } | |
| 1453 return | |
| 4759 | 1454 (Matcher::_regEncode[src_first] >= 8 || Matcher::_regEncode[dst_first] >= 8) |
| 1455 ? 5 | |
| 1456 : (4 + ((UseAVX>0)?1:0)); // REX | |
| 0 | 1457 } |
| 1458 } else if (dst_first_rc == rc_float) { | |
| 1459 // xmm -> xmm | |
| 1460 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1461 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1462 // 64-bit | |
| 1463 if (cbuf) { | |
| 4759 | 1464 MacroAssembler _masm(cbuf); |
| 1465 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first])); | |
| 0 | 1466 #ifndef PRODUCT |
| 1467 } else if (!do_size) { | |
| 1468 st->print("%s %s, %s\t# spill", | |
| 1469 UseXmmRegToRegMoveAll ? "movapd" : "movsd ", | |
| 1470 Matcher::regName[dst_first], | |
| 1471 Matcher::regName[src_first]); | |
| 1472 #endif | |
| 1473 } | |
| 1474 return | |
| 4759 | 1475 (Matcher::_regEncode[src_first] >= 8 || Matcher::_regEncode[dst_first] >= 8) |
| 1476 ? 5 | |
| 1477 : (4 + ((UseAVX>0)?1:0)); // REX | |
| 0 | 1478 } else { |
| 1479 // 32-bit | |
| 1480 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1481 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1482 if (cbuf) { | |
| 4759 | 1483 MacroAssembler _masm(cbuf); |
| 1484 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first])); | |
| 0 | 1485 #ifndef PRODUCT |
| 1486 } else if (!do_size) { | |
| 1487 st->print("%s %s, %s\t# spill", | |
| 1488 UseXmmRegToRegMoveAll ? "movaps" : "movss ", | |
| 1489 Matcher::regName[dst_first], | |
| 1490 Matcher::regName[src_first]); | |
| 1491 #endif | |
| 1492 } | |
| 4759 | 1493 return ((UseAVX>0) ? 5: |
| 1494 ((Matcher::_regEncode[src_first] >= 8 || Matcher::_regEncode[dst_first] >= 8) | |
| 1495 ? (UseXmmRegToRegMoveAll ? 4 : 5) | |
| 1496 : (UseXmmRegToRegMoveAll ? 3 : 4))); // REX | |
| 0 | 1497 } |
| 1498 } | |
| 1499 } | |
| 1500 | |
| 1501 assert(0," foo "); | |
| 1502 Unimplemented(); | |
| 1503 | |
| 1504 return 0; | |
| 1505 } | |
| 1506 | |
| 1507 #ifndef PRODUCT | |
| 1508 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const | |
| 1509 { | |
| 1510 implementation(NULL, ra_, false, st); | |
| 1511 } | |
| 1512 #endif | |
| 1513 | |
| 1514 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const | |
| 1515 { | |
| 1516 implementation(&cbuf, ra_, false, NULL); | |
| 1517 } | |
| 1518 | |
| 1519 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const | |
| 1520 { | |
| 1521 return implementation(NULL, ra_, true, NULL); | |
| 1522 } | |
| 1523 | |
| 1524 //============================================================================= | |
| 1525 #ifndef PRODUCT | |
| 1526 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const | |
| 1527 { | |
| 1528 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1529 int reg = ra_->get_reg_first(this); | |
| 1530 st->print("leaq %s, [rsp + #%d]\t# box lock", | |
| 1531 Matcher::regName[reg], offset); | |
| 1532 } | |
| 1533 #endif | |
| 1534 | |
| 1535 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const | |
| 1536 { | |
| 1537 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1538 int reg = ra_->get_encode(this); | |
| 1539 if (offset >= 0x80) { | |
| 1540 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR); | |
| 1541 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1542 emit_rm(cbuf, 0x2, reg & 7, 0x04); | |
| 1543 emit_rm(cbuf, 0x0, 0x04, RSP_enc); | |
| 1544 emit_d32(cbuf, offset); | |
| 1545 } else { | |
| 1546 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR); | |
| 1547 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1548 emit_rm(cbuf, 0x1, reg & 7, 0x04); | |
| 1549 emit_rm(cbuf, 0x0, 0x04, RSP_enc); | |
| 1550 emit_d8(cbuf, offset); | |
| 1551 } | |
| 1552 } | |
| 1553 | |
| 1554 uint BoxLockNode::size(PhaseRegAlloc *ra_) const | |
| 1555 { | |
| 1556 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1557 return (offset < 0x80) ? 5 : 8; // REX | |
| 1558 } | |
| 1559 | |
| 1560 //============================================================================= | |
| 1561 | |
| 1562 // emit call stub, compiled java to interpreter | |
| 1563 void emit_java_to_interp(CodeBuffer& cbuf) | |
| 1564 { | |
| 1565 // Stub is fixed up when the corresponding call is converted from | |
| 1566 // calling compiled code to calling interpreted code. | |
| 1567 // movq rbx, 0 | |
| 1568 // jmp -5 # to self | |
| 1569 | |
| 1748 | 1570 address mark = cbuf.insts_mark(); // get mark within main instrs section |
| 1571 | |
| 1572 // Note that the code buffer's insts_mark is always relative to insts. | |
| 0 | 1573 // That's why we must use the macroassembler to generate a stub. |
| 1574 MacroAssembler _masm(&cbuf); | |
| 1575 | |
| 1576 address base = | |
| 1577 __ start_a_stub(Compile::MAX_stubs_size); | |
| 1578 if (base == NULL) return; // CodeBuffer::expand failed | |
| 1579 // static stub relocation stores the instruction address of the call | |
| 1580 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM64); | |
| 1581 // static stub relocation also tags the methodOop in the code-stream. | |
| 1582 __ movoop(rbx, (jobject) NULL); // method is zapped till fixup time | |
| 304 | 1583 // This is recognized as unresolved by relocs/nativeinst/ic code |
| 0 | 1584 __ jump(RuntimeAddress(__ pc())); |
| 1585 | |
| 1748 | 1586 // Update current stubs pointer and restore insts_end. |
| 0 | 1587 __ end_a_stub(); |
| 1588 } | |
| 1589 | |
| 1590 // size of call stub, compiled java to interpretor | |
| 1591 uint size_java_to_interp() | |
| 1592 { | |
| 1593 return 15; // movq (1+1+8); jmp (1+4) | |
| 1594 } | |
| 1595 | |
| 1596 // relocation entries for call stub, compiled java to interpretor | |
| 1597 uint reloc_java_to_interp() | |
| 1598 { | |
| 1599 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call | |
| 1600 } | |
| 1601 | |
| 1602 //============================================================================= | |
| 1603 #ifndef PRODUCT | |
| 1604 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const | |
| 1605 { | |
|
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1606 if (UseCompressedOops) { |
|
1571
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1607 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass"); |
|
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1608 if (Universe::narrow_oop_shift() != 0) { |
|
1571
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1609 st->print_cr("\tdecode_heap_oop_not_null rscratch1, rscratch1"); |
|
2d127394260e
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1610 } |
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2d127394260e
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1611 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check"); |
|
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1612 } else { |
|
1571
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1613 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t" |
|
2d127394260e
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1614 "# Inline cache check"); |
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1615 } |
| 0 | 1616 st->print_cr("\tjne SharedRuntime::_ic_miss_stub"); |
|
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1617 st->print_cr("\tnop\t# nops to align entry point"); |
| 0 | 1618 } |
| 1619 #endif | |
| 1620 | |
| 1621 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const | |
| 1622 { | |
| 1623 MacroAssembler masm(&cbuf); | |
| 1748 | 1624 uint insts_size = cbuf.insts_size(); |
|
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1625 if (UseCompressedOops) { |
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1626 masm.load_klass(rscratch1, j_rarg0); |
| 304 | 1627 masm.cmpptr(rax, rscratch1); |
|
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1628 } else { |
| 304 | 1629 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes())); |
|
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1630 } |
| 0 | 1631 |
| 1632 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub())); | |
| 1633 | |
| 1634 /* WARNING these NOPs are critical so that verified entry point is properly | |
|
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|
1635 4 bytes aligned for patching by NativeJump::patch_verified_entry() */ |
| 1748 | 1636 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3); |
|
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|
1637 if (OptoBreakpoint) { |
| 0 | 1638 // Leave space for int3 |
|
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|
1639 nops_cnt -= 1; |
| 0 | 1640 } |
|
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1641 nops_cnt &= 0x3; // Do not add nops if code is aligned. |
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1642 if (nops_cnt > 0) |
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|
1643 masm.nop(nops_cnt); |
| 0 | 1644 } |
| 1645 | |
| 1646 uint MachUEPNode::size(PhaseRegAlloc* ra_) const | |
| 1647 { | |
|
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1648 return MachNode::size(ra_); // too many variables; just compute it |
|
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|
1649 // the hard way |
| 0 | 1650 } |
| 1651 | |
| 1652 | |
| 1653 //============================================================================= | |
| 1654 uint size_exception_handler() | |
| 1655 { | |
| 1656 // NativeCall instruction size is the same as NativeJump. | |
| 1657 // Note that this value is also credited (in output.cpp) to | |
| 1658 // the size of the code section. | |
| 1659 return NativeJump::instruction_size; | |
| 1660 } | |
| 1661 | |
| 1662 // Emit exception handler code. | |
| 1663 int emit_exception_handler(CodeBuffer& cbuf) | |
| 1664 { | |
| 1665 | |
| 1748 | 1666 // Note that the code buffer's insts_mark is always relative to insts. |
| 0 | 1667 // That's why we must use the macroassembler to generate a handler. |
| 1668 MacroAssembler _masm(&cbuf); | |
| 1669 address base = | |
| 1670 __ start_a_stub(size_exception_handler()); | |
| 1671 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1672 int offset = __ offset(); | |
| 1748 | 1673 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point())); |
| 0 | 1674 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); |
| 1675 __ end_a_stub(); | |
| 1676 return offset; | |
| 1677 } | |
| 1678 | |
| 1679 uint size_deopt_handler() | |
| 1680 { | |
| 1681 // three 5 byte instructions | |
| 1682 return 15; | |
| 1683 } | |
| 1684 | |
| 1685 // Emit deopt handler code. | |
| 1686 int emit_deopt_handler(CodeBuffer& cbuf) | |
| 1687 { | |
| 1688 | |
| 1748 | 1689 // Note that the code buffer's insts_mark is always relative to insts. |
| 0 | 1690 // That's why we must use the macroassembler to generate a handler. |
| 1691 MacroAssembler _masm(&cbuf); | |
| 1692 address base = | |
| 1693 __ start_a_stub(size_deopt_handler()); | |
| 1694 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1695 int offset = __ offset(); | |
| 1696 address the_pc = (address) __ pc(); | |
| 1697 Label next; | |
| 1698 // push a "the_pc" on the stack without destroying any registers | |
| 1699 // as they all may be live. | |
| 1700 | |
| 1701 // push address of "next" | |
| 1702 __ call(next, relocInfo::none); // reloc none is fine since it is a disp32 | |
| 1703 __ bind(next); | |
| 1704 // adjust it so it matches "the_pc" | |
| 304 | 1705 __ subptr(Address(rsp, 0), __ offset() - offset); |
| 0 | 1706 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); |
| 1707 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); | |
| 1708 __ end_a_stub(); | |
| 1709 return offset; | |
| 1710 } | |
| 1711 | |
| 1712 | |
|
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|
1713 const bool Matcher::match_rule_supported(int opcode) { |
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1714 if (!has_match_rule(opcode)) |
|
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1715 return false; |
|
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1716 |
|
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1717 switch (opcode) { |
|
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|
1718 case Op_PopCountI: |
|
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|
1719 case Op_PopCountL: |
|
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1720 if (!UsePopCountInstruction) |
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1721 return false; |
|
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|
1722 break; |
|
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|
1723 } |
|
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1724 |
|
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1725 return true; // Per default match rules are supported. |
|
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1726 } |
|
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1727 |
| 0 | 1728 int Matcher::regnum_to_fpu_offset(int regnum) |
| 1729 { | |
| 1730 return regnum - 32; // The FP registers are in the second chunk | |
| 1731 } | |
| 1732 | |
| 1733 // This is UltraSparc specific, true just means we have fast l2f conversion | |
| 1734 const bool Matcher::convL2FSupported(void) { | |
| 1735 return true; | |
| 1736 } | |
| 1737 | |
| 1738 // Vector width in bytes | |
| 1739 const uint Matcher::vector_width_in_bytes(void) { | |
| 1740 return 8; | |
| 1741 } | |
| 1742 | |
| 1743 // Vector ideal reg | |
| 1744 const uint Matcher::vector_ideal_reg(void) { | |
| 1745 return Op_RegD; | |
| 1746 } | |
| 1747 | |
| 1748 // Is this branch offset short enough that a short branch can be used? | |
| 1749 // | |
| 1750 // NOTE: If the platform does not provide any short branch variants, then | |
| 1751 // this method should return false for offset 0. | |
| 3851 | 1752 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { |
| 1753 // The passed offset is relative to address of the branch. | |
| 1754 // On 86 a branch displacement is calculated relative to address | |
| 1755 // of a next instruction. | |
| 1756 offset -= br_size; | |
| 1757 | |
|
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1758 // the short version of jmpConUCF2 contains multiple branches, |
|
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1759 // making the reach slightly less |
|
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1760 if (rule == jmpConUCF2_rule) |
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1761 return (-126 <= offset && offset <= 125); |
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1762 return (-128 <= offset && offset <= 127); |
| 0 | 1763 } |
| 1764 | |
| 1765 const bool Matcher::isSimpleConstant64(jlong value) { | |
| 1766 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. | |
| 1767 //return value == (int) value; // Cf. storeImmL and immL32. | |
| 1768 | |
| 1769 // Probably always true, even if a temp register is required. | |
| 1770 return true; | |
| 1771 } | |
| 1772 | |
| 1773 // The ecx parameter to rep stosq for the ClearArray node is in words. | |
| 1774 const bool Matcher::init_array_count_is_in_bytes = false; | |
| 1775 | |
| 1776 // Threshold size for cleararray. | |
| 1777 const int Matcher::init_array_short_size = 8 * BytesPerLong; | |
| 1778 | |
| 4047 | 1779 // No additional cost for CMOVL. |
| 1780 const int Matcher::long_cmove_cost() { return 0; } | |
| 1781 | |
| 1782 // No CMOVF/CMOVD with SSE2 | |
| 1783 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; } | |
| 1784 | |
| 0 | 1785 // Should the Matcher clone shifts on addressing modes, expecting them |
| 1786 // to be subsumed into complex addressing expressions or compute them | |
| 1787 // into registers? True for Intel but false for most RISCs | |
| 1788 const bool Matcher::clone_shift_expressions = true; | |
| 1789 | |
|
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1790 // Do we need to mask the count passed to shift instructions or does |
|
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1791 // the cpu only look at the lower 5/6 bits anyway? |
|
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|
1792 const bool Matcher::need_masked_shift_count = false; |
|
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1793 |
|
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1794 bool Matcher::narrow_oop_use_complex_address() { |
|
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1795 assert(UseCompressedOops, "only for compressed oops code"); |
|
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1796 return (LogMinObjAlignmentInBytes <= 3); |
|
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|
1797 } |
|
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|
1798 |
| 0 | 1799 // Is it better to copy float constants, or load them directly from |
| 1800 // memory? Intel can load a float constant from a direct address, | |
| 1801 // requiring no extra registers. Most RISCs will have to materialize | |
| 1802 // an address into a register first, so they would do better to copy | |
| 1803 // the constant from stack. | |
| 1804 const bool Matcher::rematerialize_float_constants = true; // XXX | |
| 1805 | |
| 1806 // If CPU can load and store mis-aligned doubles directly then no | |
| 1807 // fixup is needed. Else we split the double into 2 integer pieces | |
| 1808 // and move it piece-by-piece. Only happens when passing doubles into | |
| 1809 // C code as the Java calling convention forces doubles to be aligned. | |
| 1810 const bool Matcher::misaligned_doubles_ok = true; | |
| 1811 | |
| 1812 // No-op on amd64 | |
| 1813 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {} | |
| 1814 | |
| 1815 // Advertise here if the CPU requires explicit rounding operations to | |
| 1816 // implement the UseStrictFP mode. | |
| 1817 const bool Matcher::strict_fp_requires_explicit_rounding = true; | |
| 1818 | |
|
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|
1819 // Are floats conerted to double when stored to stack during deoptimization? |
|
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|
1820 // On x64 it is stored without convertion so we can use normal access. |
|
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|
1821 bool Matcher::float_in_double() { return false; } |
|
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|
1822 |
| 0 | 1823 // Do ints take an entire long register or just half? |
| 1824 const bool Matcher::int_in_long = true; | |
| 1825 | |
| 1826 // Return whether or not this register is ever used as an argument. | |
| 1827 // This function is used on startup to build the trampoline stubs in | |
| 1828 // generateOptoStub. Registers not mentioned will be killed by the VM | |
| 1829 // call in the trampoline, and arguments in those registers not be | |
| 1830 // available to the callee. | |
| 1831 bool Matcher::can_be_java_arg(int reg) | |
| 1832 { | |
| 1833 return | |
| 1834 reg == RDI_num || reg == RDI_H_num || | |
| 1835 reg == RSI_num || reg == RSI_H_num || | |
| 1836 reg == RDX_num || reg == RDX_H_num || | |
| 1837 reg == RCX_num || reg == RCX_H_num || | |
| 1838 reg == R8_num || reg == R8_H_num || | |
| 1839 reg == R9_num || reg == R9_H_num || | |
|
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1840 reg == R12_num || reg == R12_H_num || |
| 0 | 1841 reg == XMM0_num || reg == XMM0_H_num || |
| 1842 reg == XMM1_num || reg == XMM1_H_num || | |
| 1843 reg == XMM2_num || reg == XMM2_H_num || | |
| 1844 reg == XMM3_num || reg == XMM3_H_num || | |
| 1845 reg == XMM4_num || reg == XMM4_H_num || | |
| 1846 reg == XMM5_num || reg == XMM5_H_num || | |
| 1847 reg == XMM6_num || reg == XMM6_H_num || | |
| 1848 reg == XMM7_num || reg == XMM7_H_num; | |
| 1849 } | |
| 1850 | |
| 1851 bool Matcher::is_spillable_arg(int reg) | |
| 1852 { | |
| 1853 return can_be_java_arg(reg); | |
| 1854 } | |
| 1855 | |
|
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|
1856 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) { |
|
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|
1857 // In 64 bit mode a code which use multiply when |
|
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1858 // devisor is constant is faster than hardware |
|
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|
1859 // DIV instruction (it uses MulHiL). |
|
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|
1860 return false; |
|
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|
1861 } |
|
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|
1862 |
| 0 | 1863 // Register for DIVI projection of divmodI |
| 1864 RegMask Matcher::divI_proj_mask() { | |
|
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1865 return INT_RAX_REG_mask(); |
| 0 | 1866 } |
| 1867 | |
| 1868 // Register for MODI projection of divmodI | |
| 1869 RegMask Matcher::modI_proj_mask() { | |
|
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1870 return INT_RDX_REG_mask(); |
| 0 | 1871 } |
| 1872 | |
| 1873 // Register for DIVL projection of divmodL | |
| 1874 RegMask Matcher::divL_proj_mask() { | |
|
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|
1875 return LONG_RAX_REG_mask(); |
| 0 | 1876 } |
| 1877 | |
| 1878 // Register for MODL projection of divmodL | |
| 1879 RegMask Matcher::modL_proj_mask() { | |
|
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|
1880 return LONG_RDX_REG_mask(); |
| 0 | 1881 } |
| 1882 | |
|
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|
1883 const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
|
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|
1884 return PTR_RBP_REG_mask(); |
|
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|
1885 } |
|
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|
1886 |
|
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1887 static Address build_address(int b, int i, int s, int d) { |
|
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1888 Register index = as_Register(i); |
|
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|
1889 Address::ScaleFactor scale = (Address::ScaleFactor)s; |
|
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1890 if (index == rsp) { |
|
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|
1891 index = noreg; |
|
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1892 scale = Address::no_scale; |
|
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|
1893 } |
|
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|
1894 Address addr(as_Register(b), index, scale, d); |
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1895 return addr; |
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1896 } |
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1897 |
| 0 | 1898 %} |
| 1899 | |
| 1900 //----------ENCODING BLOCK----------------------------------------------------- | |
| 1901 // This block specifies the encoding classes used by the compiler to | |
| 1902 // output byte streams. Encoding classes are parameterized macros | |
| 1903 // used by Machine Instruction Nodes in order to generate the bit | |
| 1904 // encoding of the instruction. Operands specify their base encoding | |
| 1905 // interface with the interface keyword. There are currently | |
| 1906 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, & | |
| 1907 // COND_INTER. REG_INTER causes an operand to generate a function | |
| 1908 // which returns its register number when queried. CONST_INTER causes | |
| 1909 // an operand to generate a function which returns the value of the | |
| 1910 // constant when queried. MEMORY_INTER causes an operand to generate | |
| 1911 // four functions which return the Base Register, the Index Register, | |
| 1912 // the Scale Value, and the Offset Value of the operand when queried. | |
| 1913 // COND_INTER causes an operand to generate six functions which return | |
| 1914 // the encoding code (ie - encoding bits for the instruction) | |
| 1915 // associated with each basic boolean condition for a conditional | |
| 1916 // instruction. | |
| 1917 // | |
| 1918 // Instructions specify two basic values for encoding. Again, a | |
| 1919 // function is available to check if the constant displacement is an | |
| 1920 // oop. They use the ins_encode keyword to specify their encoding | |
| 1921 // classes (which must be a sequence of enc_class names, and their | |
| 1922 // parameters, specified in the encoding block), and they use the | |
| 1923 // opcode keyword to specify, in order, their primary, secondary, and | |
| 1924 // tertiary opcode. Only the opcode sections which a particular | |
| 1925 // instruction needs for encoding need to be specified. | |
| 1926 encode %{ | |
| 1927 // Build emit functions for each basic byte or larger field in the | |
| 1928 // intel encoding scheme (opcode, rm, sib, immediate), and call them | |
| 1929 // from C++ code in the enc_class source block. Emit functions will | |
| 1930 // live in the main source block for now. In future, we can | |
| 1931 // generalize this by adding a syntax that specifies the sizes of | |
| 1932 // fields in an order, so that the adlc can build the emit functions | |
| 1933 // automagically | |
| 1934 | |
| 1935 // Emit primary opcode | |
| 1936 enc_class OpcP | |
| 1937 %{ | |
| 1938 emit_opcode(cbuf, $primary); | |
| 1939 %} | |
| 1940 | |
| 1941 // Emit secondary opcode | |
| 1942 enc_class OpcS | |
| 1943 %{ | |
| 1944 emit_opcode(cbuf, $secondary); | |
| 1945 %} | |
| 1946 | |
| 1947 // Emit tertiary opcode | |
| 1948 enc_class OpcT | |
| 1949 %{ | |
| 1950 emit_opcode(cbuf, $tertiary); | |
| 1951 %} | |
| 1952 | |
| 1953 // Emit opcode directly | |
| 1954 enc_class Opcode(immI d8) | |
| 1955 %{ | |
| 1956 emit_opcode(cbuf, $d8$$constant); | |
| 1957 %} | |
| 1958 | |
| 1959 // Emit size prefix | |
| 1960 enc_class SizePrefix | |
| 1961 %{ | |
| 1962 emit_opcode(cbuf, 0x66); | |
| 1963 %} | |
| 1964 | |
| 1965 enc_class reg(rRegI reg) | |
| 1966 %{ | |
| 1967 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7); | |
| 1968 %} | |
| 1969 | |
| 1970 enc_class reg_reg(rRegI dst, rRegI src) | |
| 1971 %{ | |
| 1972 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7); | |
| 1973 %} | |
| 1974 | |
| 1975 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src) | |
| 1976 %{ | |
| 1977 emit_opcode(cbuf, $opcode$$constant); | |
| 1978 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7); | |
| 1979 %} | |
| 1980 | |
| 1981 enc_class cdql_enc(no_rax_rdx_RegI div) | |
| 1982 %{ | |
| 1983 // Full implementation of Java idiv and irem; checks for | |
| 1984 // special case as described in JVM spec., p.243 & p.271. | |
| 1985 // | |
| 1986 // normal case special case | |
| 1987 // | |
| 1988 // input : rax: dividend min_int | |
| 1989 // reg: divisor -1 | |
| 1990 // | |
| 1991 // output: rax: quotient (= rax idiv reg) min_int | |
| 1992 // rdx: remainder (= rax irem reg) 0 | |
| 1993 // | |
| 1994 // Code sequnce: | |
| 1995 // | |
| 1996 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax | |
| 1997 // 5: 75 07/08 jne e <normal> | |
| 1998 // 7: 33 d2 xor %edx,%edx | |
| 1999 // [div >= 8 -> offset + 1] | |
| 2000 // [REX_B] | |
| 2001 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div | |
| 2002 // c: 74 03/04 je 11 <done> | |
| 2003 // 000000000000000e <normal>: | |
| 2004 // e: 99 cltd | |
| 2005 // [div >= 8 -> offset + 1] | |
| 2006 // [REX_B] | |
| 2007 // f: f7 f9 idiv $div | |
| 2008 // 0000000000000011 <done>: | |
| 2009 | |
| 2010 // cmp $0x80000000,%eax | |
| 2011 emit_opcode(cbuf, 0x3d); | |
| 2012 emit_d8(cbuf, 0x00); | |
| 2013 emit_d8(cbuf, 0x00); | |
| 2014 emit_d8(cbuf, 0x00); | |
| 2015 emit_d8(cbuf, 0x80); | |
| 2016 | |
| 2017 // jne e <normal> | |
| 2018 emit_opcode(cbuf, 0x75); | |
| 2019 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08); | |
| 2020 | |
| 2021 // xor %edx,%edx | |
| 2022 emit_opcode(cbuf, 0x33); | |
| 2023 emit_d8(cbuf, 0xD2); | |
| 2024 | |
| 2025 // cmp $0xffffffffffffffff,%ecx | |
| 2026 if ($div$$reg >= 8) { | |
| 2027 emit_opcode(cbuf, Assembler::REX_B); | |
| 2028 } | |
| 2029 emit_opcode(cbuf, 0x83); | |
| 2030 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7); | |
| 2031 emit_d8(cbuf, 0xFF); | |
| 2032 | |
| 2033 // je 11 <done> | |
| 2034 emit_opcode(cbuf, 0x74); | |
| 2035 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04); | |
| 2036 | |
| 2037 // <normal> | |
| 2038 // cltd | |
| 2039 emit_opcode(cbuf, 0x99); | |
| 2040 | |
| 2041 // idivl (note: must be emitted by the user of this rule) | |
| 2042 // <done> | |
| 2043 %} | |
| 2044 | |
| 2045 enc_class cdqq_enc(no_rax_rdx_RegL div) | |
| 2046 %{ | |
| 2047 // Full implementation of Java ldiv and lrem; checks for | |
| 2048 // special case as described in JVM spec., p.243 & p.271. | |
| 2049 // | |
| 2050 // normal case special case | |
| 2051 // | |
| 2052 // input : rax: dividend min_long | |
| 2053 // reg: divisor -1 | |
| 2054 // | |
| 2055 // output: rax: quotient (= rax idiv reg) min_long | |
| 2056 // rdx: remainder (= rax irem reg) 0 | |
| 2057 // | |
| 2058 // Code sequnce: | |
| 2059 // | |
| 2060 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx | |
| 2061 // 7: 00 00 80 | |
| 2062 // a: 48 39 d0 cmp %rdx,%rax | |
| 2063 // d: 75 08 jne 17 <normal> | |
| 2064 // f: 33 d2 xor %edx,%edx | |
| 2065 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div | |
| 2066 // 15: 74 05 je 1c <done> | |
| 2067 // 0000000000000017 <normal>: | |
| 2068 // 17: 48 99 cqto | |
| 2069 // 19: 48 f7 f9 idiv $div | |
| 2070 // 000000000000001c <done>: | |
| 2071 | |
| 2072 // mov $0x8000000000000000,%rdx | |
| 2073 emit_opcode(cbuf, Assembler::REX_W); | |
| 2074 emit_opcode(cbuf, 0xBA); | |
| 2075 emit_d8(cbuf, 0x00); | |
| 2076 emit_d8(cbuf, 0x00); | |
| 2077 emit_d8(cbuf, 0x00); | |
| 2078 emit_d8(cbuf, 0x00); | |
| 2079 emit_d8(cbuf, 0x00); | |
| 2080 emit_d8(cbuf, 0x00); | |
| 2081 emit_d8(cbuf, 0x00); | |
| 2082 emit_d8(cbuf, 0x80); | |
| 2083 | |
| 2084 // cmp %rdx,%rax | |
| 2085 emit_opcode(cbuf, Assembler::REX_W); | |
| 2086 emit_opcode(cbuf, 0x39); | |
| 2087 emit_d8(cbuf, 0xD0); | |
| 2088 | |
| 2089 // jne 17 <normal> | |
| 2090 emit_opcode(cbuf, 0x75); | |
| 2091 emit_d8(cbuf, 0x08); | |
| 2092 | |
| 2093 // xor %edx,%edx | |
| 2094 emit_opcode(cbuf, 0x33); | |
| 2095 emit_d8(cbuf, 0xD2); | |
| 2096 | |
| 2097 // cmp $0xffffffffffffffff,$div | |
| 2098 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB); | |
| 2099 emit_opcode(cbuf, 0x83); | |
| 2100 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7); | |
| 2101 emit_d8(cbuf, 0xFF); | |
| 2102 | |
| 2103 // je 1e <done> | |
| 2104 emit_opcode(cbuf, 0x74); | |
| 2105 emit_d8(cbuf, 0x05); | |
| 2106 | |
| 2107 // <normal> | |
| 2108 // cqto | |
| 2109 emit_opcode(cbuf, Assembler::REX_W); | |
| 2110 emit_opcode(cbuf, 0x99); | |
| 2111 | |
| 2112 // idivq (note: must be emitted by the user of this rule) | |
| 2113 // <done> | |
| 2114 %} | |
| 2115 | |
| 2116 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension | |
| 2117 enc_class OpcSE(immI imm) | |
| 2118 %{ | |
| 2119 // Emit primary opcode and set sign-extend bit | |
| 2120 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 2121 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
| 2122 emit_opcode(cbuf, $primary | 0x02); | |
| 2123 } else { | |
| 2124 // 32-bit immediate | |
| 2125 emit_opcode(cbuf, $primary); | |
| 2126 } | |
| 2127 %} | |
| 2128 | |
| 2129 enc_class OpcSErm(rRegI dst, immI imm) | |
| 2130 %{ | |
| 2131 // OpcSEr/m | |
| 2132 int dstenc = $dst$$reg; | |
| 2133 if (dstenc >= 8) { | |
| 2134 emit_opcode(cbuf, Assembler::REX_B); | |
| 2135 dstenc -= 8; | |
| 2136 } | |
| 2137 // Emit primary opcode and set sign-extend bit | |
| 2138 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 2139 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
| 2140 emit_opcode(cbuf, $primary | 0x02); | |
| 2141 } else { | |
| 2142 // 32-bit immediate | |
| 2143 emit_opcode(cbuf, $primary); | |
| 2144 } | |
| 2145 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 2146 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
| 2147 %} | |
| 2148 | |
| 2149 enc_class OpcSErm_wide(rRegL dst, immI imm) | |
| 2150 %{ | |
| 2151 // OpcSEr/m | |
| 2152 int dstenc = $dst$$reg; | |
| 2153 if (dstenc < 8) { | |
| 2154 emit_opcode(cbuf, Assembler::REX_W); | |
| 2155 } else { | |
| 2156 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2157 dstenc -= 8; | |
| 2158 } | |
| 2159 // Emit primary opcode and set sign-extend bit | |
| 2160 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 2161 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
| 2162 emit_opcode(cbuf, $primary | 0x02); | |
| 2163 } else { | |
| 2164 // 32-bit immediate | |
| 2165 emit_opcode(cbuf, $primary); | |
| 2166 } | |
| 2167 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 2168 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
| 2169 %} | |
| 2170 | |
| 2171 enc_class Con8or32(immI imm) | |
| 2172 %{ | |
| 2173 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 2174 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
| 2175 $$$emit8$imm$$constant; | |
| 2176 } else { | |
| 2177 // 32-bit immediate | |
| 2178 $$$emit32$imm$$constant; | |
| 2179 } | |
| 2180 %} | |
| 2181 | |
| 2182 enc_class opc2_reg(rRegI dst) | |
| 2183 %{ | |
| 2184 // BSWAP | |
| 2185 emit_cc(cbuf, $secondary, $dst$$reg); | |
| 2186 %} | |
| 2187 | |
| 2188 enc_class opc3_reg(rRegI dst) | |
| 2189 %{ | |
| 2190 // BSWAP | |
| 2191 emit_cc(cbuf, $tertiary, $dst$$reg); | |
| 2192 %} | |
| 2193 | |
| 2194 enc_class reg_opc(rRegI div) | |
| 2195 %{ | |
| 2196 // INC, DEC, IDIV, IMOD, JMP indirect, ... | |
| 2197 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7); | |
| 2198 %} | |
| 2199 | |
| 2200 enc_class enc_cmov(cmpOp cop) | |
| 2201 %{ | |
| 2202 // CMOV | |
| 2203 $$$emit8$primary; | |
| 2204 emit_cc(cbuf, $secondary, $cop$$cmpcode); | |
| 2205 %} | |
| 2206 | |
| 2207 enc_class enc_PartialSubtypeCheck() | |
| 2208 %{ | |
| 2209 Register Rrdi = as_Register(RDI_enc); // result register | |
| 2210 Register Rrax = as_Register(RAX_enc); // super class | |
| 2211 Register Rrcx = as_Register(RCX_enc); // killed | |
| 2212 Register Rrsi = as_Register(RSI_enc); // sub class | |
|
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2213 Label miss; |
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2214 const bool set_cond_codes = true; |
| 0 | 2215 |
| 2216 MacroAssembler _masm(&cbuf); | |
|
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2217 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi, |
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2218 NULL, &miss, |
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2219 /*set_cond_codes:*/ true); |
| 0 | 2220 if ($primary) { |
| 304 | 2221 __ xorptr(Rrdi, Rrdi); |
| 0 | 2222 } |
| 2223 __ bind(miss); | |
| 2224 %} | |
| 2225 | |
| 2226 enc_class Java_To_Interpreter(method meth) | |
| 2227 %{ | |
| 2228 // CALL Java_To_Interpreter | |
| 2229 // This is the instruction starting address for relocation info. | |
| 1748 | 2230 cbuf.set_insts_mark(); |
| 0 | 2231 $$$emit8$primary; |
| 2232 // CALL directly to the runtime | |
| 2233 emit_d32_reloc(cbuf, | |
| 1748 | 2234 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4), |
| 0 | 2235 runtime_call_Relocation::spec(), |
| 2236 RELOC_DISP32); | |
| 2237 %} | |
| 2238 | |
| 2239 enc_class Java_Static_Call(method meth) | |
| 2240 %{ | |
| 2241 // JAVA STATIC CALL | |
| 2242 // CALL to fixup routine. Fixup routine uses ScopeDesc info to | |
| 2243 // determine who we intended to call. | |
| 1748 | 2244 cbuf.set_insts_mark(); |
| 0 | 2245 $$$emit8$primary; |
| 2246 | |
| 2247 if (!_method) { | |
| 2248 emit_d32_reloc(cbuf, | |
| 1748 | 2249 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4), |
| 0 | 2250 runtime_call_Relocation::spec(), |
| 2251 RELOC_DISP32); | |
| 2252 } else if (_optimized_virtual) { | |
| 2253 emit_d32_reloc(cbuf, | |
| 1748 | 2254 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4), |
| 0 | 2255 opt_virtual_call_Relocation::spec(), |
| 2256 RELOC_DISP32); | |
| 2257 } else { | |
| 2258 emit_d32_reloc(cbuf, | |
| 1748 | 2259 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4), |
| 0 | 2260 static_call_Relocation::spec(), |
| 2261 RELOC_DISP32); | |
| 2262 } | |
| 2263 if (_method) { | |
| 2264 // Emit stub for static call | |
| 2265 emit_java_to_interp(cbuf); | |
| 2266 } | |
| 2267 %} | |
| 2268 | |
| 2269 enc_class Java_Dynamic_Call(method meth) | |
| 2270 %{ | |
| 2271 // JAVA DYNAMIC CALL | |
| 2272 // !!!!! | |
| 2273 // Generate "movq rax, -1", placeholder instruction to load oop-info | |
| 2274 // emit_call_dynamic_prologue( cbuf ); | |
| 1748 | 2275 cbuf.set_insts_mark(); |
| 0 | 2276 |
| 2277 // movq rax, -1 | |
| 2278 emit_opcode(cbuf, Assembler::REX_W); | |
| 2279 emit_opcode(cbuf, 0xB8 | RAX_enc); | |
| 2280 emit_d64_reloc(cbuf, | |
| 2281 (int64_t) Universe::non_oop_word(), | |
| 2282 oop_Relocation::spec_for_immediate(), RELOC_IMM64); | |
| 1748 | 2283 address virtual_call_oop_addr = cbuf.insts_mark(); |
| 0 | 2284 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine |
| 2285 // who we intended to call. | |
| 1748 | 2286 cbuf.set_insts_mark(); |
| 0 | 2287 $$$emit8$primary; |
| 2288 emit_d32_reloc(cbuf, | |
| 1748 | 2289 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4), |
| 0 | 2290 virtual_call_Relocation::spec(virtual_call_oop_addr), |
| 2291 RELOC_DISP32); | |
| 2292 %} | |
| 2293 | |
| 2294 enc_class Java_Compiled_Call(method meth) | |
| 2295 %{ | |
| 2296 // JAVA COMPILED CALL | |
| 2297 int disp = in_bytes(methodOopDesc:: from_compiled_offset()); | |
| 2298 | |
| 2299 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!! | |
| 2300 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small"); | |
| 2301 | |
| 2302 // callq *disp(%rax) | |
| 1748 | 2303 cbuf.set_insts_mark(); |
| 0 | 2304 $$$emit8$primary; |
| 2305 if (disp < 0x80) { | |
| 2306 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte | |
| 2307 emit_d8(cbuf, disp); // Displacement | |
| 2308 } else { | |
| 2309 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte | |
| 2310 emit_d32(cbuf, disp); // Displacement | |
| 2311 } | |
| 2312 %} | |
| 2313 | |
| 2314 enc_class reg_opc_imm(rRegI dst, immI8 shift) | |
| 2315 %{ | |
| 2316 // SAL, SAR, SHR | |
| 2317 int dstenc = $dst$$reg; | |
| 2318 if (dstenc >= 8) { | |
| 2319 emit_opcode(cbuf, Assembler::REX_B); | |
| 2320 dstenc -= 8; | |
| 2321 } | |
| 2322 $$$emit8$primary; | |
| 2323 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
| 2324 $$$emit8$shift$$constant; | |
| 2325 %} | |
| 2326 | |
| 2327 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift) | |
| 2328 %{ | |
| 2329 // SAL, SAR, SHR | |
| 2330 int dstenc = $dst$$reg; | |
| 2331 if (dstenc < 8) { | |
| 2332 emit_opcode(cbuf, Assembler::REX_W); | |
| 2333 } else { | |
| 2334 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2335 dstenc -= 8; | |
| 2336 } | |
| 2337 $$$emit8$primary; | |
| 2338 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
| 2339 $$$emit8$shift$$constant; | |
| 2340 %} | |
| 2341 | |
| 2342 enc_class load_immI(rRegI dst, immI src) | |
| 2343 %{ | |
| 2344 int dstenc = $dst$$reg; | |
| 2345 if (dstenc >= 8) { | |
| 2346 emit_opcode(cbuf, Assembler::REX_B); | |
| 2347 dstenc -= 8; | |
| 2348 } | |
| 2349 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2350 $$$emit32$src$$constant; | |
| 2351 %} | |
| 2352 | |
| 2353 enc_class load_immL(rRegL dst, immL src) | |
| 2354 %{ | |
| 2355 int dstenc = $dst$$reg; | |
| 2356 if (dstenc < 8) { | |
| 2357 emit_opcode(cbuf, Assembler::REX_W); | |
| 2358 } else { | |
| 2359 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2360 dstenc -= 8; | |
| 2361 } | |
| 2362 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2363 emit_d64(cbuf, $src$$constant); | |
| 2364 %} | |
| 2365 | |
| 2366 enc_class load_immUL32(rRegL dst, immUL32 src) | |
| 2367 %{ | |
| 2368 // same as load_immI, but this time we care about zeroes in the high word | |
| 2369 int dstenc = $dst$$reg; | |
| 2370 if (dstenc >= 8) { | |
| 2371 emit_opcode(cbuf, Assembler::REX_B); | |
| 2372 dstenc -= 8; | |
| 2373 } | |
| 2374 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2375 $$$emit32$src$$constant; | |
| 2376 %} | |
| 2377 | |
| 2378 enc_class load_immL32(rRegL dst, immL32 src) | |
| 2379 %{ | |
| 2380 int dstenc = $dst$$reg; | |
| 2381 if (dstenc < 8) { | |
| 2382 emit_opcode(cbuf, Assembler::REX_W); | |
| 2383 } else { | |
| 2384 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2385 dstenc -= 8; | |
| 2386 } | |
| 2387 emit_opcode(cbuf, 0xC7); | |
| 2388 emit_rm(cbuf, 0x03, 0x00, dstenc); | |
| 2389 $$$emit32$src$$constant; | |
| 2390 %} | |
| 2391 | |
| 2392 enc_class load_immP31(rRegP dst, immP32 src) | |
| 2393 %{ | |
| 2394 // same as load_immI, but this time we care about zeroes in the high word | |
| 2395 int dstenc = $dst$$reg; | |
| 2396 if (dstenc >= 8) { | |
| 2397 emit_opcode(cbuf, Assembler::REX_B); | |
| 2398 dstenc -= 8; | |
| 2399 } | |
| 2400 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2401 $$$emit32$src$$constant; | |
| 2402 %} | |
| 2403 | |
| 2404 enc_class load_immP(rRegP dst, immP src) | |
| 2405 %{ | |
| 2406 int dstenc = $dst$$reg; | |
| 2407 if (dstenc < 8) { | |
| 2408 emit_opcode(cbuf, Assembler::REX_W); | |
| 2409 } else { | |
| 2410 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2411 dstenc -= 8; | |
| 2412 } | |
| 2413 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2414 // This next line should be generated from ADLC | |
| 2415 if ($src->constant_is_oop()) { | |
| 2416 emit_d64_reloc(cbuf, $src$$constant, relocInfo::oop_type, RELOC_IMM64); | |
| 2417 } else { | |
| 2418 emit_d64(cbuf, $src$$constant); | |
| 2419 } | |
| 2420 %} | |
| 2421 | |
| 2422 enc_class Con32(immI src) | |
| 2423 %{ | |
| 2424 // Output immediate | |
| 2425 $$$emit32$src$$constant; | |
| 2426 %} | |
| 2427 | |
| 2428 enc_class Con64(immL src) | |
| 2429 %{ | |
| 2430 // Output immediate | |
| 2431 emit_d64($src$$constant); | |
| 2432 %} | |
| 2433 | |
| 2434 enc_class Con32F_as_bits(immF src) | |
| 2435 %{ | |
| 2436 // Output Float immediate bits | |
| 2437 jfloat jf = $src$$constant; | |
| 2438 jint jf_as_bits = jint_cast(jf); | |
| 2439 emit_d32(cbuf, jf_as_bits); | |
| 2440 %} | |
| 2441 | |
| 2442 enc_class Con16(immI src) | |
| 2443 %{ | |
| 2444 // Output immediate | |
| 2445 $$$emit16$src$$constant; | |
| 2446 %} | |
| 2447 | |
| 2448 // How is this different from Con32??? XXX | |
| 2449 enc_class Con_d32(immI src) | |
| 2450 %{ | |
| 2451 emit_d32(cbuf,$src$$constant); | |
| 2452 %} | |
| 2453 | |
| 2454 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI) | |
| 2455 // Output immediate memory reference | |
| 2456 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 ); | |
| 2457 emit_d32(cbuf, 0x00); | |
| 2458 %} | |
| 2459 | |
| 2460 enc_class lock_prefix() | |
| 2461 %{ | |
| 2462 if (os::is_MP()) { | |
| 2463 emit_opcode(cbuf, 0xF0); // lock | |
| 2464 } | |
| 2465 %} | |
| 2466 | |
| 2467 enc_class REX_mem(memory mem) | |
| 2468 %{ | |
| 2469 if ($mem$$base >= 8) { | |
| 2470 if ($mem$$index < 8) { | |
| 2471 emit_opcode(cbuf, Assembler::REX_B); | |
| 2472 } else { | |
| 2473 emit_opcode(cbuf, Assembler::REX_XB); | |
| 2474 } | |
| 2475 } else { | |
| 2476 if ($mem$$index >= 8) { | |
| 2477 emit_opcode(cbuf, Assembler::REX_X); | |
| 2478 } | |
| 2479 } | |
| 2480 %} | |
| 2481 | |
| 2482 enc_class REX_mem_wide(memory mem) | |
| 2483 %{ | |
| 2484 if ($mem$$base >= 8) { | |
| 2485 if ($mem$$index < 8) { | |
| 2486 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2487 } else { | |
| 2488 emit_opcode(cbuf, Assembler::REX_WXB); | |
| 2489 } | |
| 2490 } else { | |
| 2491 if ($mem$$index < 8) { | |
| 2492 emit_opcode(cbuf, Assembler::REX_W); | |
| 2493 } else { | |
| 2494 emit_opcode(cbuf, Assembler::REX_WX); | |
| 2495 } | |
| 2496 } | |
| 2497 %} | |
| 2498 | |
| 2499 // for byte regs | |
| 2500 enc_class REX_breg(rRegI reg) | |
| 2501 %{ | |
| 2502 if ($reg$$reg >= 4) { | |
| 2503 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B); | |
| 2504 } | |
| 2505 %} | |
| 2506 | |
| 2507 // for byte regs | |
| 2508 enc_class REX_reg_breg(rRegI dst, rRegI src) | |
| 2509 %{ | |
| 2510 if ($dst$$reg < 8) { | |
| 2511 if ($src$$reg >= 4) { | |
| 2512 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B); | |
| 2513 } | |
| 2514 } else { | |
| 2515 if ($src$$reg < 8) { | |
| 2516 emit_opcode(cbuf, Assembler::REX_R); | |
| 2517 } else { | |
| 2518 emit_opcode(cbuf, Assembler::REX_RB); | |
| 2519 } | |
| 2520 } | |
| 2521 %} | |
| 2522 | |
| 2523 // for byte regs | |
| 2524 enc_class REX_breg_mem(rRegI reg, memory mem) | |
| 2525 %{ | |
| 2526 if ($reg$$reg < 8) { | |
| 2527 if ($mem$$base < 8) { | |
| 2528 if ($mem$$index >= 8) { | |
| 2529 emit_opcode(cbuf, Assembler::REX_X); | |
| 2530 } else if ($reg$$reg >= 4) { | |
| 2531 emit_opcode(cbuf, Assembler::REX); | |
| 2532 } | |
| 2533 } else { | |
| 2534 if ($mem$$index < 8) { | |
| 2535 emit_opcode(cbuf, Assembler::REX_B); | |
| 2536 } else { | |
| 2537 emit_opcode(cbuf, Assembler::REX_XB); | |
| 2538 } | |
| 2539 } | |
| 2540 } else { | |
| 2541 if ($mem$$base < 8) { | |
| 2542 if ($mem$$index < 8) { | |
| 2543 emit_opcode(cbuf, Assembler::REX_R); | |
| 2544 } else { | |
| 2545 emit_opcode(cbuf, Assembler::REX_RX); | |
| 2546 } | |
| 2547 } else { | |
| 2548 if ($mem$$index < 8) { | |
| 2549 emit_opcode(cbuf, Assembler::REX_RB); | |
| 2550 } else { | |
| 2551 emit_opcode(cbuf, Assembler::REX_RXB); | |
| 2552 } | |
| 2553 } | |
| 2554 } | |
| 2555 %} | |
| 2556 | |
| 2557 enc_class REX_reg(rRegI reg) | |
| 2558 %{ | |
| 2559 if ($reg$$reg >= 8) { | |
| 2560 emit_opcode(cbuf, Assembler::REX_B); | |
| 2561 } | |
| 2562 %} | |
| 2563 | |
| 2564 enc_class REX_reg_wide(rRegI reg) | |
| 2565 %{ | |
| 2566 if ($reg$$reg < 8) { | |
| 2567 emit_opcode(cbuf, Assembler::REX_W); | |
| 2568 } else { | |
| 2569 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2570 } | |
| 2571 %} | |
| 2572 | |
| 2573 enc_class REX_reg_reg(rRegI dst, rRegI src) | |
| 2574 %{ | |
| 2575 if ($dst$$reg < 8) { | |
| 2576 if ($src$$reg >= 8) { | |
| 2577 emit_opcode(cbuf, Assembler::REX_B); | |
| 2578 } | |
| 2579 } else { | |
| 2580 if ($src$$reg < 8) { | |
| 2581 emit_opcode(cbuf, Assembler::REX_R); | |
| 2582 } else { | |
| 2583 emit_opcode(cbuf, Assembler::REX_RB); | |
| 2584 } | |
| 2585 } | |
| 2586 %} | |
| 2587 | |
| 2588 enc_class REX_reg_reg_wide(rRegI dst, rRegI src) | |
| 2589 %{ | |
| 2590 if ($dst$$reg < 8) { | |
| 2591 if ($src$$reg < 8) { | |
| 2592 emit_opcode(cbuf, Assembler::REX_W); | |
| 2593 } else { | |
| 2594 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2595 } | |
| 2596 } else { | |
| 2597 if ($src$$reg < 8) { | |
| 2598 emit_opcode(cbuf, Assembler::REX_WR); | |
| 2599 } else { | |
| 2600 emit_opcode(cbuf, Assembler::REX_WRB); | |
| 2601 } | |
| 2602 } | |
| 2603 %} | |
| 2604 | |
| 2605 enc_class REX_reg_mem(rRegI reg, memory mem) | |
| 2606 %{ | |
| 2607 if ($reg$$reg < 8) { | |
| 2608 if ($mem$$base < 8) { | |
| 2609 if ($mem$$index >= 8) { | |
| 2610 emit_opcode(cbuf, Assembler::REX_X); | |
| 2611 } | |
| 2612 } else { | |
| 2613 if ($mem$$index < 8) { | |
| 2614 emit_opcode(cbuf, Assembler::REX_B); | |
| 2615 } else { | |
| 2616 emit_opcode(cbuf, Assembler::REX_XB); | |
| 2617 } | |
| 2618 } | |
| 2619 } else { | |
| 2620 if ($mem$$base < 8) { | |
| 2621 if ($mem$$index < 8) { | |
| 2622 emit_opcode(cbuf, Assembler::REX_R); | |
| 2623 } else { | |
| 2624 emit_opcode(cbuf, Assembler::REX_RX); | |
| 2625 } | |
| 2626 } else { | |
| 2627 if ($mem$$index < 8) { | |
| 2628 emit_opcode(cbuf, Assembler::REX_RB); | |
| 2629 } else { | |
| 2630 emit_opcode(cbuf, Assembler::REX_RXB); | |
| 2631 } | |
| 2632 } | |
| 2633 } | |
| 2634 %} | |
| 2635 | |
| 2636 enc_class REX_reg_mem_wide(rRegL reg, memory mem) | |
| 2637 %{ | |
| 2638 if ($reg$$reg < 8) { | |
| 2639 if ($mem$$base < 8) { | |
| 2640 if ($mem$$index < 8) { | |
| 2641 emit_opcode(cbuf, Assembler::REX_W); | |
| 2642 } else { | |
| 2643 emit_opcode(cbuf, Assembler::REX_WX); | |
| 2644 } | |
| 2645 } else { | |
| 2646 if ($mem$$index < 8) { | |
| 2647 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2648 } else { | |
| 2649 emit_opcode(cbuf, Assembler::REX_WXB); | |
| 2650 } | |
| 2651 } | |
| 2652 } else { | |
| 2653 if ($mem$$base < 8) { | |
| 2654 if ($mem$$index < 8) { | |
| 2655 emit_opcode(cbuf, Assembler::REX_WR); | |
| 2656 } else { | |
| 2657 emit_opcode(cbuf, Assembler::REX_WRX); | |
| 2658 } | |
| 2659 } else { | |
| 2660 if ($mem$$index < 8) { | |
| 2661 emit_opcode(cbuf, Assembler::REX_WRB); | |
| 2662 } else { | |
| 2663 emit_opcode(cbuf, Assembler::REX_WRXB); | |
| 2664 } | |
| 2665 } | |
| 2666 } | |
| 2667 %} | |
| 2668 | |
| 2669 enc_class reg_mem(rRegI ereg, memory mem) | |
| 2670 %{ | |
| 2671 // High registers handle in encode_RegMem | |
| 2672 int reg = $ereg$$reg; | |
| 2673 int base = $mem$$base; | |
| 2674 int index = $mem$$index; | |
| 2675 int scale = $mem$$scale; | |
| 2676 int disp = $mem$$disp; | |
| 2677 bool disp_is_oop = $mem->disp_is_oop(); | |
| 2678 | |
| 2679 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_is_oop); | |
| 2680 %} | |
| 2681 | |
| 2682 enc_class RM_opc_mem(immI rm_opcode, memory mem) | |
| 2683 %{ | |
| 2684 int rm_byte_opcode = $rm_opcode$$constant; | |
| 2685 | |
| 2686 // High registers handle in encode_RegMem | |
| 2687 int base = $mem$$base; | |
| 2688 int index = $mem$$index; | |
| 2689 int scale = $mem$$scale; | |
| 2690 int displace = $mem$$disp; | |
| 2691 | |
| 2692 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when | |
| 2693 // working with static | |
| 2694 // globals | |
| 2695 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, | |
| 2696 disp_is_oop); | |
| 2697 %} | |
| 2698 | |
| 2699 enc_class reg_lea(rRegI dst, rRegI src0, immI src1) | |
| 2700 %{ | |
| 2701 int reg_encoding = $dst$$reg; | |
| 2702 int base = $src0$$reg; // 0xFFFFFFFF indicates no base | |
| 2703 int index = 0x04; // 0x04 indicates no index | |
| 2704 int scale = 0x00; // 0x00 indicates no scale | |
| 2705 int displace = $src1$$constant; // 0x00 indicates no displacement | |
| 2706 bool disp_is_oop = false; | |
| 2707 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, | |
| 2708 disp_is_oop); | |
| 2709 %} | |
| 2710 | |
| 2711 enc_class neg_reg(rRegI dst) | |
| 2712 %{ | |
| 2713 int dstenc = $dst$$reg; | |
| 2714 if (dstenc >= 8) { | |
| 2715 emit_opcode(cbuf, Assembler::REX_B); | |
| 2716 dstenc -= 8; | |
| 2717 } | |
| 2718 // NEG $dst | |
| 2719 emit_opcode(cbuf, 0xF7); | |
| 2720 emit_rm(cbuf, 0x3, 0x03, dstenc); | |
| 2721 %} | |
| 2722 | |
| 2723 enc_class neg_reg_wide(rRegI dst) | |
| 2724 %{ | |
| 2725 int dstenc = $dst$$reg; | |
| 2726 if (dstenc < 8) { | |
| 2727 emit_opcode(cbuf, Assembler::REX_W); | |
| 2728 } else { | |
| 2729 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2730 dstenc -= 8; | |
| 2731 } | |
| 2732 // NEG $dst | |
| 2733 emit_opcode(cbuf, 0xF7); | |
| 2734 emit_rm(cbuf, 0x3, 0x03, dstenc); | |
| 2735 %} | |
| 2736 | |
| 2737 enc_class setLT_reg(rRegI dst) | |
| 2738 %{ | |
| 2739 int dstenc = $dst$$reg; | |
| 2740 if (dstenc >= 8) { | |
| 2741 emit_opcode(cbuf, Assembler::REX_B); | |
| 2742 dstenc -= 8; | |
| 2743 } else if (dstenc >= 4) { | |
| 2744 emit_opcode(cbuf, Assembler::REX); | |
| 2745 } | |
| 2746 // SETLT $dst | |
| 2747 emit_opcode(cbuf, 0x0F); | |
| 2748 emit_opcode(cbuf, 0x9C); | |
| 2749 emit_rm(cbuf, 0x3, 0x0, dstenc); | |
| 2750 %} | |
| 2751 | |
| 2752 enc_class setNZ_reg(rRegI dst) | |
| 2753 %{ | |
| 2754 int dstenc = $dst$$reg; | |
| 2755 if (dstenc >= 8) { | |
| 2756 emit_opcode(cbuf, Assembler::REX_B); | |
| 2757 dstenc -= 8; | |
| 2758 } else if (dstenc >= 4) { | |
| 2759 emit_opcode(cbuf, Assembler::REX); | |
| 2760 } | |
| 2761 // SETNZ $dst | |
| 2762 emit_opcode(cbuf, 0x0F); | |
| 2763 emit_opcode(cbuf, 0x95); | |
| 2764 emit_rm(cbuf, 0x3, 0x0, dstenc); | |
| 2765 %} | |
| 2766 | |
| 2767 | |
| 2768 // Compare the lonogs and set -1, 0, or 1 into dst | |
| 2769 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst) | |
| 2770 %{ | |
| 2771 int src1enc = $src1$$reg; | |
| 2772 int src2enc = $src2$$reg; | |
| 2773 int dstenc = $dst$$reg; | |
| 2774 | |
| 2775 // cmpq $src1, $src2 | |
| 2776 if (src1enc < 8) { | |
| 2777 if (src2enc < 8) { | |
| 2778 emit_opcode(cbuf, Assembler::REX_W); | |
| 2779 } else { | |
| 2780 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2781 } | |
| 2782 } else { | |
| 2783 if (src2enc < 8) { | |
| 2784 emit_opcode(cbuf, Assembler::REX_WR); | |
| 2785 } else { | |
| 2786 emit_opcode(cbuf, Assembler::REX_WRB); | |
| 2787 } | |
| 2788 } | |
| 2789 emit_opcode(cbuf, 0x3B); | |
| 2790 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7); | |
| 2791 | |
| 2792 // movl $dst, -1 | |
| 2793 if (dstenc >= 8) { | |
| 2794 emit_opcode(cbuf, Assembler::REX_B); | |
| 2795 } | |
| 2796 emit_opcode(cbuf, 0xB8 | (dstenc & 7)); | |
| 2797 emit_d32(cbuf, -1); | |
| 2798 | |
| 2799 // jl,s done | |
| 2800 emit_opcode(cbuf, 0x7C); | |
| 2801 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08); | |
| 2802 | |
| 2803 // setne $dst | |
| 2804 if (dstenc >= 4) { | |
| 2805 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B); | |
| 2806 } | |
| 2807 emit_opcode(cbuf, 0x0F); | |
| 2808 emit_opcode(cbuf, 0x95); | |
| 2809 emit_opcode(cbuf, 0xC0 | (dstenc & 7)); | |
| 2810 | |
| 2811 // movzbl $dst, $dst | |
| 2812 if (dstenc >= 4) { | |
| 2813 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB); | |
| 2814 } | |
| 2815 emit_opcode(cbuf, 0x0F); | |
| 2816 emit_opcode(cbuf, 0xB6); | |
| 2817 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7); | |
| 2818 %} | |
| 2819 | |
| 2820 enc_class Push_ResultXD(regD dst) %{ | |
| 4759 | 2821 MacroAssembler _masm(&cbuf); |
| 2822 __ fstp_d(Address(rsp, 0)); | |
| 2823 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); | |
| 2824 __ addptr(rsp, 8); | |
| 0 | 2825 %} |
| 2826 | |
| 2827 enc_class Push_SrcXD(regD src) %{ | |
| 2828 MacroAssembler _masm(&cbuf); | |
| 4759 | 2829 __ subptr(rsp, 8); |
| 2830 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 2831 __ fld_d(Address(rsp, 0)); | |
| 2832 %} | |
| 2833 | |
| 0 | 2834 |
| 2835 // obj: object to lock | |
| 2836 // box: box address (header location) -- killed | |
| 2837 // tmp: rax -- killed | |
| 2838 // scr: rbx -- killed | |
| 2839 // | |
| 2840 // What follows is a direct transliteration of fast_lock() and fast_unlock() | |
| 2841 // from i486.ad. See that file for comments. | |
| 2842 // TODO: where possible switch from movq (r, 0) to movl(r,0) and | |
| 2843 // use the shorter encoding. (Movl clears the high-order 32-bits). | |
| 2844 | |
| 2845 | |
| 2846 enc_class Fast_Lock(rRegP obj, rRegP box, rax_RegI tmp, rRegP scr) | |
| 2847 %{ | |
| 2848 Register objReg = as_Register((int)$obj$$reg); | |
| 2849 Register boxReg = as_Register((int)$box$$reg); | |
| 2850 Register tmpReg = as_Register($tmp$$reg); | |
| 2851 Register scrReg = as_Register($scr$$reg); | |
| 2852 MacroAssembler masm(&cbuf); | |
| 2853 | |
| 2854 // Verify uniqueness of register assignments -- necessary but not sufficient | |
| 2855 assert (objReg != boxReg && objReg != tmpReg && | |
| 2856 objReg != scrReg && tmpReg != scrReg, "invariant") ; | |
| 2857 | |
| 2858 if (_counters != NULL) { | |
| 2859 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr())); | |
| 2860 } | |
| 2861 if (EmitSync & 1) { | |
| 304 | 2862 // Without cast to int32_t a movptr will destroy r10 which is typically obj |
|
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2863 masm.movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ; |
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2864 masm.cmpptr(rsp, (int32_t)NULL_WORD) ; |
| 0 | 2865 } else |
| 2866 if (EmitSync & 2) { | |
| 2867 Label DONE_LABEL; | |
| 2868 if (UseBiasedLocking) { | |
| 2869 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument. | |
| 2870 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters); | |
| 2871 } | |
| 304 | 2872 // QQQ was movl... |
| 2873 masm.movptr(tmpReg, 0x1); | |
| 2874 masm.orptr(tmpReg, Address(objReg, 0)); | |
| 2875 masm.movptr(Address(boxReg, 0), tmpReg); | |
| 0 | 2876 if (os::is_MP()) { |
| 2877 masm.lock(); | |
| 2878 } | |
| 304 | 2879 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg |
| 0 | 2880 masm.jcc(Assembler::equal, DONE_LABEL); |
| 2881 | |
| 2882 // Recursive locking | |
| 304 | 2883 masm.subptr(tmpReg, rsp); |
| 2884 masm.andptr(tmpReg, 7 - os::vm_page_size()); | |
| 2885 masm.movptr(Address(boxReg, 0), tmpReg); | |
| 0 | 2886 |
| 2887 masm.bind(DONE_LABEL); | |
| 2888 masm.nop(); // avoid branch to branch | |
| 2889 } else { | |
| 2890 Label DONE_LABEL, IsInflated, Egress; | |
| 2891 | |
|
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2892 masm.movptr(tmpReg, Address(objReg, 0)) ; |
| 304 | 2893 masm.testl (tmpReg, 0x02) ; // inflated vs stack-locked|neutral|biased |
|
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2894 masm.jcc (Assembler::notZero, IsInflated) ; |
|
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2895 |
| 0 | 2896 // it's stack-locked, biased or neutral |
| 2897 // TODO: optimize markword triage order to reduce the number of | |
| 2898 // conditional branches in the most common cases. | |
| 2899 // Beware -- there's a subtle invariant that fetch of the markword | |
| 2900 // at [FETCH], below, will never observe a biased encoding (*101b). | |
| 2901 // If this invariant is not held we'll suffer exclusion (safety) failure. | |
| 2902 | |
|
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2903 if (UseBiasedLocking && !UseOptoBiasInlining) { |
| 0 | 2904 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, true, DONE_LABEL, NULL, _counters); |
| 304 | 2905 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH] |
| 0 | 2906 } |
| 2907 | |
| 304 | 2908 // was q will it destroy high? |
|
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2909 masm.orl (tmpReg, 1) ; |
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2910 masm.movptr(Address(boxReg, 0), tmpReg) ; |
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2911 if (os::is_MP()) { masm.lock(); } |
| 304 | 2912 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg |
| 0 | 2913 if (_counters != NULL) { |
| 2914 masm.cond_inc32(Assembler::equal, | |
| 2915 ExternalAddress((address) _counters->fast_path_entry_count_addr())); | |
| 2916 } | |
| 2917 masm.jcc (Assembler::equal, DONE_LABEL); | |
| 2918 | |
| 2919 // Recursive locking | |
| 304 | 2920 masm.subptr(tmpReg, rsp); |
| 2921 masm.andptr(tmpReg, 7 - os::vm_page_size()); | |
| 2922 masm.movptr(Address(boxReg, 0), tmpReg); | |
| 0 | 2923 if (_counters != NULL) { |
| 2924 masm.cond_inc32(Assembler::equal, | |
| 2925 ExternalAddress((address) _counters->fast_path_entry_count_addr())); | |
| 2926 } | |
| 2927 masm.jmp (DONE_LABEL) ; | |
| 2928 | |
| 2929 masm.bind (IsInflated) ; | |
| 2930 // It's inflated | |
| 2931 | |
| 2932 // TODO: someday avoid the ST-before-CAS penalty by | |
| 2933 // relocating (deferring) the following ST. | |
| 2934 // We should also think about trying a CAS without having | |
| 2935 // fetched _owner. If the CAS is successful we may | |
| 2936 // avoid an RTO->RTS upgrade on the $line. | |
| 304 | 2937 // Without cast to int32_t a movptr will destroy r10 which is typically obj |
|
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2938 masm.movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ; |
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2939 |
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2940 masm.mov (boxReg, tmpReg) ; |
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2941 masm.movptr (tmpReg, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
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2942 masm.testptr(tmpReg, tmpReg) ; |
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2943 masm.jcc (Assembler::notZero, DONE_LABEL) ; |
| 0 | 2944 |
| 2945 // It's inflated and appears unlocked | |
|
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2946 if (os::is_MP()) { masm.lock(); } |
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2947 masm.cmpxchgptr(r15_thread, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
| 0 | 2948 // Intentional fall-through into DONE_LABEL ... |
| 2949 | |
| 2950 masm.bind (DONE_LABEL) ; | |
| 2951 masm.nop () ; // avoid jmp to jmp | |
| 2952 } | |
| 2953 %} | |
| 2954 | |
| 2955 // obj: object to unlock | |
| 2956 // box: box address (displaced header location), killed | |
| 2957 // RBX: killed tmp; cannot be obj nor box | |
| 2958 enc_class Fast_Unlock(rRegP obj, rax_RegP box, rRegP tmp) | |
| 2959 %{ | |
| 2960 | |
| 2961 Register objReg = as_Register($obj$$reg); | |
| 2962 Register boxReg = as_Register($box$$reg); | |
| 2963 Register tmpReg = as_Register($tmp$$reg); | |
| 2964 MacroAssembler masm(&cbuf); | |
| 2965 | |
|
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2966 if (EmitSync & 4) { |
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2967 masm.cmpptr(rsp, 0) ; |
| 0 | 2968 } else |
| 2969 if (EmitSync & 8) { | |
| 2970 Label DONE_LABEL; | |
| 2971 if (UseBiasedLocking) { | |
| 2972 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); | |
| 2973 } | |
| 2974 | |
| 2975 // Check whether the displaced header is 0 | |
| 2976 //(=> recursive unlock) | |
| 304 | 2977 masm.movptr(tmpReg, Address(boxReg, 0)); |
| 2978 masm.testptr(tmpReg, tmpReg); | |
| 0 | 2979 masm.jcc(Assembler::zero, DONE_LABEL); |
| 2980 | |
| 2981 // If not recursive lock, reset the header to displaced header | |
| 2982 if (os::is_MP()) { | |
| 2983 masm.lock(); | |
| 2984 } | |
| 304 | 2985 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box |
| 0 | 2986 masm.bind(DONE_LABEL); |
| 2987 masm.nop(); // avoid branch to branch | |
| 2988 } else { | |
| 2989 Label DONE_LABEL, Stacked, CheckSucc ; | |
| 2990 | |
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2991 if (UseBiasedLocking && !UseOptoBiasInlining) { |
| 0 | 2992 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); |
| 2993 } | |
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2994 |
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2995 masm.movptr(tmpReg, Address(objReg, 0)) ; |
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2996 masm.cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD) ; |
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2997 masm.jcc (Assembler::zero, DONE_LABEL) ; |
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2998 masm.testl (tmpReg, 0x02) ; |
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2999 masm.jcc (Assembler::zero, Stacked) ; |
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3000 |
| 0 | 3001 // It's inflated |
|
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3002 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
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3003 masm.xorptr(boxReg, r15_thread) ; |
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3004 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ; |
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3005 masm.jcc (Assembler::notZero, DONE_LABEL) ; |
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3006 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ; |
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3007 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ; |
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3008 masm.jcc (Assembler::notZero, CheckSucc) ; |
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3009 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ; |
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3010 masm.jmp (DONE_LABEL) ; |
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3011 |
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|
3012 if ((EmitSync & 65536) == 0) { |
| 0 | 3013 Label LSuccess, LGoSlowPath ; |
| 3014 masm.bind (CheckSucc) ; | |
| 304 | 3015 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ; |
| 0 | 3016 masm.jcc (Assembler::zero, LGoSlowPath) ; |
| 3017 | |
| 3018 // I'd much rather use lock:andl m->_owner, 0 as it's faster than the | |
| 3019 // the explicit ST;MEMBAR combination, but masm doesn't currently support | |
| 3020 // "ANDQ M,IMM". Don't use MFENCE here. lock:add to TOS, xchg, etc | |
| 3021 // are all faster when the write buffer is populated. | |
| 304 | 3022 masm.movptr (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ; |
| 0 | 3023 if (os::is_MP()) { |
| 304 | 3024 masm.lock () ; masm.addl (Address(rsp, 0), 0) ; |
| 0 | 3025 } |
| 304 | 3026 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ; |
| 0 | 3027 masm.jcc (Assembler::notZero, LSuccess) ; |
| 3028 | |
| 304 | 3029 masm.movptr (boxReg, (int32_t)NULL_WORD) ; // box is really EAX |
| 0 | 3030 if (os::is_MP()) { masm.lock(); } |
| 304 | 3031 masm.cmpxchgptr(r15_thread, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)); |
| 0 | 3032 masm.jcc (Assembler::notEqual, LSuccess) ; |
| 3033 // Intentional fall-through into slow-path | |
| 3034 | |
| 3035 masm.bind (LGoSlowPath) ; | |
| 3036 masm.orl (boxReg, 1) ; // set ICC.ZF=0 to indicate failure | |
| 3037 masm.jmp (DONE_LABEL) ; | |
| 3038 | |
| 3039 masm.bind (LSuccess) ; | |
| 3040 masm.testl (boxReg, 0) ; // set ICC.ZF=1 to indicate success | |
| 3041 masm.jmp (DONE_LABEL) ; | |
| 3042 } | |
| 3043 | |
|
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3044 masm.bind (Stacked) ; |
| 304 | 3045 masm.movptr(tmpReg, Address (boxReg, 0)) ; // re-fetch |
|
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3046 if (os::is_MP()) { masm.lock(); } |
| 304 | 3047 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box |
| 0 | 3048 |
| 3049 if (EmitSync & 65536) { | |
| 3050 masm.bind (CheckSucc) ; | |
| 3051 } | |
| 3052 masm.bind(DONE_LABEL); | |
| 3053 if (EmitSync & 32768) { | |
| 3054 masm.nop(); // avoid branch to branch | |
| 3055 } | |
| 3056 } | |
| 3057 %} | |
| 3058 | |
|
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3059 |
| 0 | 3060 enc_class enc_rethrow() |
| 3061 %{ | |
| 1748 | 3062 cbuf.set_insts_mark(); |
| 0 | 3063 emit_opcode(cbuf, 0xE9); // jmp entry |
| 3064 emit_d32_reloc(cbuf, | |
| 1748 | 3065 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4), |
| 0 | 3066 runtime_call_Relocation::spec(), |
| 3067 RELOC_DISP32); | |
| 3068 %} | |
| 3069 | |
| 3070 %} | |
| 3071 | |
| 3072 | |
|
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3073 |
| 0 | 3074 //----------FRAME-------------------------------------------------------------- |
| 3075 // Definition of frame structure and management information. | |
| 3076 // | |
| 3077 // S T A C K L A Y O U T Allocators stack-slot number | |
| 3078 // | (to get allocators register number | |
| 3079 // G Owned by | | v add OptoReg::stack0()) | |
| 3080 // r CALLER | | | |
| 3081 // o | +--------+ pad to even-align allocators stack-slot | |
| 3082 // w V | pad0 | numbers; owned by CALLER | |
| 3083 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned | |
| 3084 // h ^ | in | 5 | |
| 3085 // | | args | 4 Holes in incoming args owned by SELF | |
| 3086 // | | | | 3 | |
| 3087 // | | +--------+ | |
| 3088 // V | | old out| Empty on Intel, window on Sparc | |
| 3089 // | old |preserve| Must be even aligned. | |
| 3090 // | SP-+--------+----> Matcher::_old_SP, even aligned | |
| 3091 // | | in | 3 area for Intel ret address | |
| 3092 // Owned by |preserve| Empty on Sparc. | |
| 3093 // SELF +--------+ | |
| 3094 // | | pad2 | 2 pad to align old SP | |
| 3095 // | +--------+ 1 | |
| 3096 // | | locks | 0 | |
| 3097 // | +--------+----> OptoReg::stack0(), even aligned | |
| 3098 // | | pad1 | 11 pad to align new SP | |
| 3099 // | +--------+ | |
| 3100 // | | | 10 | |
| 3101 // | | spills | 9 spills | |
| 3102 // V | | 8 (pad0 slot for callee) | |
| 3103 // -----------+--------+----> Matcher::_out_arg_limit, unaligned | |
| 3104 // ^ | out | 7 | |
| 3105 // | | args | 6 Holes in outgoing args owned by CALLEE | |
| 3106 // Owned by +--------+ | |
| 3107 // CALLEE | new out| 6 Empty on Intel, window on Sparc | |
| 3108 // | new |preserve| Must be even-aligned. | |
| 3109 // | SP-+--------+----> Matcher::_new_SP, even aligned | |
| 3110 // | | | | |
| 3111 // | |
| 3112 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is | |
| 3113 // known from SELF's arguments and the Java calling convention. | |
| 3114 // Region 6-7 is determined per call site. | |
| 3115 // Note 2: If the calling convention leaves holes in the incoming argument | |
| 3116 // area, those holes are owned by SELF. Holes in the outgoing area | |
| 3117 // are owned by the CALLEE. Holes should not be nessecary in the | |
| 3118 // incoming area, as the Java calling convention is completely under | |
| 3119 // the control of the AD file. Doubles can be sorted and packed to | |
| 3120 // avoid holes. Holes in the outgoing arguments may be nessecary for | |
| 3121 // varargs C calling conventions. | |
| 3122 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is | |
| 3123 // even aligned with pad0 as needed. | |
| 3124 // Region 6 is even aligned. Region 6-7 is NOT even aligned; | |
| 3125 // region 6-11 is even aligned; it may be padded out more so that | |
| 3126 // the region from SP to FP meets the minimum stack alignment. | |
| 3127 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack | |
| 3128 // alignment. Region 11, pad1, may be dynamically extended so that | |
| 3129 // SP meets the minimum alignment. | |
| 3130 | |
| 3131 frame | |
| 3132 %{ | |
| 3133 // What direction does stack grow in (assumed to be same for C & Java) | |
| 3134 stack_direction(TOWARDS_LOW); | |
| 3135 | |
| 3136 // These three registers define part of the calling convention | |
| 3137 // between compiled code and the interpreter. | |
| 3138 inline_cache_reg(RAX); // Inline Cache Register | |
| 3139 interpreter_method_oop_reg(RBX); // Method Oop Register when | |
| 3140 // calling interpreter | |
| 3141 | |
| 3142 // Optional: name the operand used by cisc-spilling to access | |
| 3143 // [stack_pointer + offset] | |
| 3144 cisc_spilling_operand_name(indOffset32); | |
| 3145 | |
| 3146 // Number of stack slots consumed by locking an object | |
| 3147 sync_stack_slots(2); | |
| 3148 | |
| 3149 // Compiled code's Frame Pointer | |
| 3150 frame_pointer(RSP); | |
| 3151 | |
| 3152 // Interpreter stores its frame pointer in a register which is | |
| 3153 // stored to the stack by I2CAdaptors. | |
| 3154 // I2CAdaptors convert from interpreted java to compiled java. | |
| 3155 interpreter_frame_pointer(RBP); | |
| 3156 | |
| 3157 // Stack alignment requirement | |
| 3158 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes) | |
| 3159 | |
| 3160 // Number of stack slots between incoming argument block and the start of | |
| 3161 // a new frame. The PROLOG must add this many slots to the stack. The | |
| 3162 // EPILOG must remove this many slots. amd64 needs two slots for | |
| 3163 // return address. | |
| 3164 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls); | |
| 3165 | |
| 3166 // Number of outgoing stack slots killed above the out_preserve_stack_slots | |
| 3167 // for calls to C. Supports the var-args backing area for register parms. | |
| 3168 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt); | |
| 3169 | |
| 3170 // The after-PROLOG location of the return address. Location of | |
| 3171 // return address specifies a type (REG or STACK) and a number | |
| 3172 // representing the register number (i.e. - use a register name) or | |
| 3173 // stack slot. | |
| 3174 // Ret Addr is on stack in slot 0 if no locks or verification or alignment. | |
| 3175 // Otherwise, it is above the locks and verification slot and alignment word | |
| 3176 return_addr(STACK - 2 + | |
| 4950 | 3177 round_to((Compile::current()->in_preserve_stack_slots() + |
| 3178 Compile::current()->fixed_slots()), | |
| 3179 stack_alignment_in_slots())); | |
| 0 | 3180 |
| 3181 // Body of function which returns an integer array locating | |
| 3182 // arguments either in registers or in stack slots. Passed an array | |
| 3183 // of ideal registers called "sig" and a "length" count. Stack-slot | |
| 3184 // offsets are based on outgoing arguments, i.e. a CALLER setting up | |
| 3185 // arguments for a CALLEE. Incoming stack arguments are | |
| 3186 // automatically biased by the preserve_stack_slots field above. | |
| 3187 | |
| 3188 calling_convention | |
| 3189 %{ | |
| 3190 // No difference between ingoing/outgoing just pass false | |
| 3191 SharedRuntime::java_calling_convention(sig_bt, regs, length, false); | |
| 3192 %} | |
| 3193 | |
| 3194 c_calling_convention | |
| 3195 %{ | |
| 3196 // This is obviously always outgoing | |
| 3197 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); | |
| 3198 %} | |
| 3199 | |
| 3200 // Location of compiled Java return values. Same as C for now. | |
| 3201 return_value | |
| 3202 %{ | |
| 3203 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, | |
| 3204 "only return normal values"); | |
| 3205 | |
| 3206 static const int lo[Op_RegL + 1] = { | |
| 3207 0, | |
| 3208 0, | |
|
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3209 RAX_num, // Op_RegN |
| 0 | 3210 RAX_num, // Op_RegI |
| 3211 RAX_num, // Op_RegP | |
| 3212 XMM0_num, // Op_RegF | |
| 3213 XMM0_num, // Op_RegD | |
| 3214 RAX_num // Op_RegL | |
| 3215 }; | |
| 3216 static const int hi[Op_RegL + 1] = { | |
| 3217 0, | |
| 3218 0, | |
|
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3219 OptoReg::Bad, // Op_RegN |
| 0 | 3220 OptoReg::Bad, // Op_RegI |
| 3221 RAX_H_num, // Op_RegP | |
| 3222 OptoReg::Bad, // Op_RegF | |
| 3223 XMM0_H_num, // Op_RegD | |
| 3224 RAX_H_num // Op_RegL | |
| 3225 }; | |
|
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3226 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 1, "missing type"); |
| 0 | 3227 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]); |
| 3228 %} | |
| 3229 %} | |
| 3230 | |
| 3231 //----------ATTRIBUTES--------------------------------------------------------- | |
| 3232 //----------Operand Attributes------------------------------------------------- | |
| 3233 op_attrib op_cost(0); // Required cost attribute | |
| 3234 | |
| 3235 //----------Instruction Attributes--------------------------------------------- | |
| 3236 ins_attrib ins_cost(100); // Required cost attribute | |
| 3237 ins_attrib ins_size(8); // Required size attribute (in bits) | |
| 3238 ins_attrib ins_short_branch(0); // Required flag: is this instruction | |
| 3239 // a non-matching short branch variant | |
| 3240 // of some long branch? | |
| 3241 ins_attrib ins_alignment(1); // Required alignment attribute (must | |
| 3242 // be a power of 2) specifies the | |
| 3243 // alignment that some part of the | |
| 3244 // instruction (not necessarily the | |
| 3245 // start) requires. If > 1, a | |
| 3246 // compute_padding() function must be | |
| 3247 // provided for the instruction | |
| 3248 | |
| 3249 //----------OPERANDS----------------------------------------------------------- | |
| 3250 // Operand definitions must precede instruction definitions for correct parsing | |
| 3251 // in the ADLC because operands constitute user defined types which are used in | |
| 3252 // instruction definitions. | |
| 3253 | |
| 3254 //----------Simple Operands---------------------------------------------------- | |
| 3255 // Immediate Operands | |
| 3256 // Integer Immediate | |
| 3257 operand immI() | |
| 3258 %{ | |
| 3259 match(ConI); | |
| 3260 | |
| 3261 op_cost(10); | |
| 3262 format %{ %} | |
| 3263 interface(CONST_INTER); | |
| 3264 %} | |
| 3265 | |
| 3266 // Constant for test vs zero | |
| 3267 operand immI0() | |
| 3268 %{ | |
| 3269 predicate(n->get_int() == 0); | |
| 3270 match(ConI); | |
| 3271 | |
| 3272 op_cost(0); | |
| 3273 format %{ %} | |
| 3274 interface(CONST_INTER); | |
| 3275 %} | |
| 3276 | |
| 3277 // Constant for increment | |
| 3278 operand immI1() | |
| 3279 %{ | |
| 3280 predicate(n->get_int() == 1); | |
| 3281 match(ConI); | |
| 3282 | |
| 3283 op_cost(0); | |
| 3284 format %{ %} | |
| 3285 interface(CONST_INTER); | |
| 3286 %} | |
| 3287 | |
| 3288 // Constant for decrement | |
| 3289 operand immI_M1() | |
| 3290 %{ | |
| 3291 predicate(n->get_int() == -1); | |
| 3292 match(ConI); | |
| 3293 | |
| 3294 op_cost(0); | |
| 3295 format %{ %} | |
| 3296 interface(CONST_INTER); | |
| 3297 %} | |
| 3298 | |
| 3299 // Valid scale values for addressing modes | |
| 3300 operand immI2() | |
| 3301 %{ | |
| 3302 predicate(0 <= n->get_int() && (n->get_int() <= 3)); | |
| 3303 match(ConI); | |
| 3304 | |
| 3305 format %{ %} | |
| 3306 interface(CONST_INTER); | |
| 3307 %} | |
| 3308 | |
| 3309 operand immI8() | |
| 3310 %{ | |
| 3311 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80)); | |
| 3312 match(ConI); | |
| 3313 | |
| 3314 op_cost(5); | |
| 3315 format %{ %} | |
| 3316 interface(CONST_INTER); | |
| 3317 %} | |
| 3318 | |
| 3319 operand immI16() | |
| 3320 %{ | |
| 3321 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767)); | |
| 3322 match(ConI); | |
| 3323 | |
| 3324 op_cost(10); | |
| 3325 format %{ %} | |
| 3326 interface(CONST_INTER); | |
| 3327 %} | |
| 3328 | |
| 3329 // Constant for long shifts | |
| 3330 operand immI_32() | |
| 3331 %{ | |
| 3332 predicate( n->get_int() == 32 ); | |
| 3333 match(ConI); | |
| 3334 | |
| 3335 op_cost(0); | |
| 3336 format %{ %} | |
| 3337 interface(CONST_INTER); | |
| 3338 %} | |
| 3339 | |
| 3340 // Constant for long shifts | |
| 3341 operand immI_64() | |
| 3342 %{ | |
| 3343 predicate( n->get_int() == 64 ); | |
| 3344 match(ConI); | |
| 3345 | |
| 3346 op_cost(0); | |
| 3347 format %{ %} | |
| 3348 interface(CONST_INTER); | |
| 3349 %} | |
| 3350 | |
| 3351 // Pointer Immediate | |
| 3352 operand immP() | |
| 3353 %{ | |
| 3354 match(ConP); | |
| 3355 | |
| 3356 op_cost(10); | |
| 3357 format %{ %} | |
| 3358 interface(CONST_INTER); | |
| 3359 %} | |
| 3360 | |
| 3361 // NULL Pointer Immediate | |
| 3362 operand immP0() | |
| 3363 %{ | |
| 3364 predicate(n->get_ptr() == 0); | |
| 3365 match(ConP); | |
| 3366 | |
| 3367 op_cost(5); | |
| 3368 format %{ %} | |
| 3369 interface(CONST_INTER); | |
| 3370 %} | |
| 3371 | |
|
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3372 // Pointer Immediate |
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3373 operand immN() %{ |
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3374 match(ConN); |
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3375 |
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3376 op_cost(10); |
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3377 format %{ %} |
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3378 interface(CONST_INTER); |
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3379 %} |
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3380 |
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3381 // NULL Pointer Immediate |
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3382 operand immN0() %{ |
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3383 predicate(n->get_narrowcon() == 0); |
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3384 match(ConN); |
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3385 |
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3386 op_cost(5); |
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3387 format %{ %} |
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3388 interface(CONST_INTER); |
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3389 %} |
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3390 |
| 0 | 3391 operand immP31() |
| 3392 %{ | |
| 3393 predicate(!n->as_Type()->type()->isa_oopptr() | |
| 3394 && (n->get_ptr() >> 31) == 0); | |
| 3395 match(ConP); | |
| 3396 | |
| 3397 op_cost(5); | |
| 3398 format %{ %} | |
| 3399 interface(CONST_INTER); | |
| 3400 %} | |
| 3401 | |
|
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3402 |
| 0 | 3403 // Long Immediate |
| 3404 operand immL() | |
| 3405 %{ | |
| 3406 match(ConL); | |
| 3407 | |
| 3408 op_cost(20); | |
| 3409 format %{ %} | |
| 3410 interface(CONST_INTER); | |
| 3411 %} | |
| 3412 | |
| 3413 // Long Immediate 8-bit | |
| 3414 operand immL8() | |
| 3415 %{ | |
| 3416 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L); | |
| 3417 match(ConL); | |
| 3418 | |
| 3419 op_cost(5); | |
| 3420 format %{ %} | |
| 3421 interface(CONST_INTER); | |
| 3422 %} | |
| 3423 | |
| 3424 // Long Immediate 32-bit unsigned | |
| 3425 operand immUL32() | |
| 3426 %{ | |
| 3427 predicate(n->get_long() == (unsigned int) (n->get_long())); | |
| 3428 match(ConL); | |
| 3429 | |
| 3430 op_cost(10); | |
| 3431 format %{ %} | |
| 3432 interface(CONST_INTER); | |
| 3433 %} | |
| 3434 | |
| 3435 // Long Immediate 32-bit signed | |
| 3436 operand immL32() | |
| 3437 %{ | |
| 3438 predicate(n->get_long() == (int) (n->get_long())); | |
| 3439 match(ConL); | |
| 3440 | |
| 3441 op_cost(15); | |
| 3442 format %{ %} | |
| 3443 interface(CONST_INTER); | |
| 3444 %} | |
| 3445 | |
| 3446 // Long Immediate zero | |
| 3447 operand immL0() | |
| 3448 %{ | |
| 3449 predicate(n->get_long() == 0L); | |
| 3450 match(ConL); | |
| 3451 | |
| 3452 op_cost(10); | |
| 3453 format %{ %} | |
| 3454 interface(CONST_INTER); | |
| 3455 %} | |
| 3456 | |
| 3457 // Constant for increment | |
| 3458 operand immL1() | |
| 3459 %{ | |
| 3460 predicate(n->get_long() == 1); | |
| 3461 match(ConL); | |
| 3462 | |
| 3463 format %{ %} | |
| 3464 interface(CONST_INTER); | |
| 3465 %} | |
| 3466 | |
| 3467 // Constant for decrement | |
| 3468 operand immL_M1() | |
| 3469 %{ | |
| 3470 predicate(n->get_long() == -1); | |
| 3471 match(ConL); | |
| 3472 | |
| 3473 format %{ %} | |
| 3474 interface(CONST_INTER); | |
| 3475 %} | |
| 3476 | |
| 3477 // Long Immediate: the value 10 | |
| 3478 operand immL10() | |
| 3479 %{ | |
| 3480 predicate(n->get_long() == 10); | |
| 3481 match(ConL); | |
| 3482 | |
| 3483 format %{ %} | |
| 3484 interface(CONST_INTER); | |
| 3485 %} | |
| 3486 | |
| 3487 // Long immediate from 0 to 127. | |
| 3488 // Used for a shorter form of long mul by 10. | |
| 3489 operand immL_127() | |
| 3490 %{ | |
| 3491 predicate(0 <= n->get_long() && n->get_long() < 0x80); | |
| 3492 match(ConL); | |
| 3493 | |
| 3494 op_cost(10); | |
| 3495 format %{ %} | |
| 3496 interface(CONST_INTER); | |
| 3497 %} | |
| 3498 | |
| 3499 // Long Immediate: low 32-bit mask | |
| 3500 operand immL_32bits() | |
| 3501 %{ | |
| 3502 predicate(n->get_long() == 0xFFFFFFFFL); | |
| 3503 match(ConL); | |
| 3504 op_cost(20); | |
| 3505 | |
| 3506 format %{ %} | |
| 3507 interface(CONST_INTER); | |
| 3508 %} | |
| 3509 | |
| 3510 // Float Immediate zero | |
| 3511 operand immF0() | |
| 3512 %{ | |
| 3513 predicate(jint_cast(n->getf()) == 0); | |
| 3514 match(ConF); | |
| 3515 | |
| 3516 op_cost(5); | |
| 3517 format %{ %} | |
| 3518 interface(CONST_INTER); | |
| 3519 %} | |
| 3520 | |
| 3521 // Float Immediate | |
| 3522 operand immF() | |
| 3523 %{ | |
| 3524 match(ConF); | |
| 3525 | |
| 3526 op_cost(15); | |
| 3527 format %{ %} | |
| 3528 interface(CONST_INTER); | |
| 3529 %} | |
| 3530 | |
| 3531 // Double Immediate zero | |
| 3532 operand immD0() | |
| 3533 %{ | |
| 3534 predicate(jlong_cast(n->getd()) == 0); | |
| 3535 match(ConD); | |
| 3536 | |
| 3537 op_cost(5); | |
| 3538 format %{ %} | |
| 3539 interface(CONST_INTER); | |
| 3540 %} | |
| 3541 | |
| 3542 // Double Immediate | |
| 3543 operand immD() | |
| 3544 %{ | |
| 3545 match(ConD); | |
| 3546 | |
| 3547 op_cost(15); | |
| 3548 format %{ %} | |
| 3549 interface(CONST_INTER); | |
| 3550 %} | |
| 3551 | |
| 3552 // Immediates for special shifts (sign extend) | |
| 3553 | |
| 3554 // Constants for increment | |
| 3555 operand immI_16() | |
| 3556 %{ | |
| 3557 predicate(n->get_int() == 16); | |
| 3558 match(ConI); | |
| 3559 | |
| 3560 format %{ %} | |
| 3561 interface(CONST_INTER); | |
| 3562 %} | |
| 3563 | |
| 3564 operand immI_24() | |
| 3565 %{ | |
| 3566 predicate(n->get_int() == 24); | |
| 3567 match(ConI); | |
| 3568 | |
| 3569 format %{ %} | |
| 3570 interface(CONST_INTER); | |
| 3571 %} | |
| 3572 | |
| 3573 // Constant for byte-wide masking | |
| 3574 operand immI_255() | |
| 3575 %{ | |
| 3576 predicate(n->get_int() == 255); | |
| 3577 match(ConI); | |
| 3578 | |
| 3579 format %{ %} | |
| 3580 interface(CONST_INTER); | |
| 3581 %} | |
| 3582 | |
| 3583 // Constant for short-wide masking | |
| 3584 operand immI_65535() | |
| 3585 %{ | |
| 3586 predicate(n->get_int() == 65535); | |
| 3587 match(ConI); | |
| 3588 | |
| 3589 format %{ %} | |
| 3590 interface(CONST_INTER); | |
| 3591 %} | |
| 3592 | |
| 3593 // Constant for byte-wide masking | |
| 3594 operand immL_255() | |
| 3595 %{ | |
| 3596 predicate(n->get_long() == 255); | |
| 3597 match(ConL); | |
| 3598 | |
| 3599 format %{ %} | |
| 3600 interface(CONST_INTER); | |
| 3601 %} | |
| 3602 | |
| 3603 // Constant for short-wide masking | |
| 3604 operand immL_65535() | |
| 3605 %{ | |
| 3606 predicate(n->get_long() == 65535); | |
| 3607 match(ConL); | |
| 3608 | |
| 3609 format %{ %} | |
| 3610 interface(CONST_INTER); | |
| 3611 %} | |
| 3612 | |
| 3613 // Register Operands | |
| 3614 // Integer Register | |
| 3615 operand rRegI() | |
| 3616 %{ | |
| 3617 constraint(ALLOC_IN_RC(int_reg)); | |
| 3618 match(RegI); | |
| 3619 | |
| 3620 match(rax_RegI); | |
| 3621 match(rbx_RegI); | |
| 3622 match(rcx_RegI); | |
| 3623 match(rdx_RegI); | |
| 3624 match(rdi_RegI); | |
| 3625 | |
| 3626 format %{ %} | |
| 3627 interface(REG_INTER); | |
| 3628 %} | |
| 3629 | |
| 3630 // Special Registers | |
| 3631 operand rax_RegI() | |
| 3632 %{ | |
| 3633 constraint(ALLOC_IN_RC(int_rax_reg)); | |
| 3634 match(RegI); | |
| 3635 match(rRegI); | |
| 3636 | |
| 3637 format %{ "RAX" %} | |
| 3638 interface(REG_INTER); | |
| 3639 %} | |
| 3640 | |
| 3641 // Special Registers | |
| 3642 operand rbx_RegI() | |
| 3643 %{ | |
| 3644 constraint(ALLOC_IN_RC(int_rbx_reg)); | |
| 3645 match(RegI); | |
| 3646 match(rRegI); | |
| 3647 | |
| 3648 format %{ "RBX" %} | |
| 3649 interface(REG_INTER); | |
| 3650 %} | |
| 3651 | |
| 3652 operand rcx_RegI() | |
| 3653 %{ | |
| 3654 constraint(ALLOC_IN_RC(int_rcx_reg)); | |
| 3655 match(RegI); | |
| 3656 match(rRegI); | |
| 3657 | |
| 3658 format %{ "RCX" %} | |
| 3659 interface(REG_INTER); | |
| 3660 %} | |
| 3661 | |
| 3662 operand rdx_RegI() | |
| 3663 %{ | |
| 3664 constraint(ALLOC_IN_RC(int_rdx_reg)); | |
| 3665 match(RegI); | |
| 3666 match(rRegI); | |
| 3667 | |
| 3668 format %{ "RDX" %} | |
| 3669 interface(REG_INTER); | |
| 3670 %} | |
| 3671 | |
| 3672 operand rdi_RegI() | |
| 3673 %{ | |
| 3674 constraint(ALLOC_IN_RC(int_rdi_reg)); | |
| 3675 match(RegI); | |
| 3676 match(rRegI); | |
| 3677 | |
| 3678 format %{ "RDI" %} | |
| 3679 interface(REG_INTER); | |
| 3680 %} | |
| 3681 | |
| 3682 operand no_rcx_RegI() | |
| 3683 %{ | |
| 3684 constraint(ALLOC_IN_RC(int_no_rcx_reg)); | |
| 3685 match(RegI); | |
| 3686 match(rax_RegI); | |
| 3687 match(rbx_RegI); | |
| 3688 match(rdx_RegI); | |
| 3689 match(rdi_RegI); | |
| 3690 | |
| 3691 format %{ %} | |
| 3692 interface(REG_INTER); | |
| 3693 %} | |
| 3694 | |
| 3695 operand no_rax_rdx_RegI() | |
| 3696 %{ | |
| 3697 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg)); | |
| 3698 match(RegI); | |
| 3699 match(rbx_RegI); | |
| 3700 match(rcx_RegI); | |
| 3701 match(rdi_RegI); | |
| 3702 | |
| 3703 format %{ %} | |
| 3704 interface(REG_INTER); | |
| 3705 %} | |
| 3706 | |
| 3707 // Pointer Register | |
| 3708 operand any_RegP() | |
| 3709 %{ | |
| 3710 constraint(ALLOC_IN_RC(any_reg)); | |
| 3711 match(RegP); | |
| 3712 match(rax_RegP); | |
| 3713 match(rbx_RegP); | |
| 3714 match(rdi_RegP); | |
| 3715 match(rsi_RegP); | |
| 3716 match(rbp_RegP); | |
| 3717 match(r15_RegP); | |
| 3718 match(rRegP); | |
| 3719 | |
| 3720 format %{ %} | |
| 3721 interface(REG_INTER); | |
| 3722 %} | |
| 3723 | |
| 3724 operand rRegP() | |
| 3725 %{ | |
| 3726 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3727 match(RegP); | |
| 3728 match(rax_RegP); | |
| 3729 match(rbx_RegP); | |
| 3730 match(rdi_RegP); | |
| 3731 match(rsi_RegP); | |
| 3732 match(rbp_RegP); | |
| 3733 match(r15_RegP); // See Q&A below about r15_RegP. | |
| 3734 | |
| 3735 format %{ %} | |
| 3736 interface(REG_INTER); | |
| 3737 %} | |
| 3738 | |
|
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3739 operand rRegN() %{ |
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3740 constraint(ALLOC_IN_RC(int_reg)); |
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3741 match(RegN); |
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3742 |
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3743 format %{ %} |
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3744 interface(REG_INTER); |
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3745 %} |
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3746 |
| 0 | 3747 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP? |
| 3748 // Answer: Operand match rules govern the DFA as it processes instruction inputs. | |
| 3749 // It's fine for an instruction input which expects rRegP to match a r15_RegP. | |
| 3750 // The output of an instruction is controlled by the allocator, which respects | |
| 3751 // register class masks, not match rules. Unless an instruction mentions | |
| 3752 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered | |
| 3753 // by the allocator as an input. | |
| 3754 | |
| 3755 operand no_rax_RegP() | |
| 3756 %{ | |
| 3757 constraint(ALLOC_IN_RC(ptr_no_rax_reg)); | |
| 3758 match(RegP); | |
| 3759 match(rbx_RegP); | |
| 3760 match(rsi_RegP); | |
| 3761 match(rdi_RegP); | |
| 3762 | |
| 3763 format %{ %} | |
| 3764 interface(REG_INTER); | |
| 3765 %} | |
| 3766 | |
| 3767 operand no_rbp_RegP() | |
| 3768 %{ | |
| 3769 constraint(ALLOC_IN_RC(ptr_no_rbp_reg)); | |
| 3770 match(RegP); | |
| 3771 match(rbx_RegP); | |
| 3772 match(rsi_RegP); | |
| 3773 match(rdi_RegP); | |
| 3774 | |
| 3775 format %{ %} | |
| 3776 interface(REG_INTER); | |
| 3777 %} | |
| 3778 | |
| 3779 operand no_rax_rbx_RegP() | |
| 3780 %{ | |
| 3781 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg)); | |
| 3782 match(RegP); | |
| 3783 match(rsi_RegP); | |
| 3784 match(rdi_RegP); | |
| 3785 | |
| 3786 format %{ %} | |
| 3787 interface(REG_INTER); | |
| 3788 %} | |
| 3789 | |
| 3790 // Special Registers | |
| 3791 // Return a pointer value | |
| 3792 operand rax_RegP() | |
| 3793 %{ | |
| 3794 constraint(ALLOC_IN_RC(ptr_rax_reg)); | |
| 3795 match(RegP); | |
| 3796 match(rRegP); | |
| 3797 | |
| 3798 format %{ %} | |
| 3799 interface(REG_INTER); | |
| 3800 %} | |
| 3801 | |
|
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3802 // Special Registers |
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3803 // Return a compressed pointer value |
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3804 operand rax_RegN() |
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3805 %{ |
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3806 constraint(ALLOC_IN_RC(int_rax_reg)); |
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3807 match(RegN); |
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3808 match(rRegN); |
|
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|
3809 |
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3810 format %{ %} |
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3811 interface(REG_INTER); |
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3812 %} |
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3813 |
| 0 | 3814 // Used in AtomicAdd |
| 3815 operand rbx_RegP() | |
| 3816 %{ | |
| 3817 constraint(ALLOC_IN_RC(ptr_rbx_reg)); | |
| 3818 match(RegP); | |
| 3819 match(rRegP); | |
| 3820 | |
| 3821 format %{ %} | |
| 3822 interface(REG_INTER); | |
| 3823 %} | |
| 3824 | |
| 3825 operand rsi_RegP() | |
| 3826 %{ | |
| 3827 constraint(ALLOC_IN_RC(ptr_rsi_reg)); | |
| 3828 match(RegP); | |
| 3829 match(rRegP); | |
| 3830 | |
| 3831 format %{ %} | |
| 3832 interface(REG_INTER); | |
| 3833 %} | |
| 3834 | |
| 3835 // Used in rep stosq | |
| 3836 operand rdi_RegP() | |
| 3837 %{ | |
| 3838 constraint(ALLOC_IN_RC(ptr_rdi_reg)); | |
| 3839 match(RegP); | |
| 3840 match(rRegP); | |
| 3841 | |
| 3842 format %{ %} | |
| 3843 interface(REG_INTER); | |
| 3844 %} | |
| 3845 | |
| 3846 operand rbp_RegP() | |
| 3847 %{ | |
| 3848 constraint(ALLOC_IN_RC(ptr_rbp_reg)); | |
| 3849 match(RegP); | |
| 3850 match(rRegP); | |
| 3851 | |
| 3852 format %{ %} | |
| 3853 interface(REG_INTER); | |
| 3854 %} | |
| 3855 | |
| 3856 operand r15_RegP() | |
| 3857 %{ | |
| 3858 constraint(ALLOC_IN_RC(ptr_r15_reg)); | |
| 3859 match(RegP); | |
| 3860 match(rRegP); | |
| 3861 | |
| 3862 format %{ %} | |
| 3863 interface(REG_INTER); | |
| 3864 %} | |
| 3865 | |
| 3866 operand rRegL() | |
| 3867 %{ | |
| 3868 constraint(ALLOC_IN_RC(long_reg)); | |
| 3869 match(RegL); | |
| 3870 match(rax_RegL); | |
| 3871 match(rdx_RegL); | |
| 3872 | |
| 3873 format %{ %} | |
| 3874 interface(REG_INTER); | |
| 3875 %} | |
| 3876 | |
| 3877 // Special Registers | |
| 3878 operand no_rax_rdx_RegL() | |
| 3879 %{ | |
| 3880 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg)); | |
| 3881 match(RegL); | |
| 3882 match(rRegL); | |
| 3883 | |
| 3884 format %{ %} | |
| 3885 interface(REG_INTER); | |
| 3886 %} | |
| 3887 | |
| 3888 operand no_rax_RegL() | |
| 3889 %{ | |
| 3890 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg)); | |
| 3891 match(RegL); | |
| 3892 match(rRegL); | |
| 3893 match(rdx_RegL); | |
| 3894 | |
| 3895 format %{ %} | |
| 3896 interface(REG_INTER); | |
| 3897 %} | |
| 3898 | |
| 3899 operand no_rcx_RegL() | |
| 3900 %{ | |
| 3901 constraint(ALLOC_IN_RC(long_no_rcx_reg)); | |
| 3902 match(RegL); | |
| 3903 match(rRegL); | |
| 3904 | |
| 3905 format %{ %} | |
| 3906 interface(REG_INTER); | |
| 3907 %} | |
| 3908 | |
| 3909 operand rax_RegL() | |
| 3910 %{ | |
| 3911 constraint(ALLOC_IN_RC(long_rax_reg)); | |
| 3912 match(RegL); | |
| 3913 match(rRegL); | |
| 3914 | |
| 3915 format %{ "RAX" %} | |
| 3916 interface(REG_INTER); | |
| 3917 %} | |
| 3918 | |
| 3919 operand rcx_RegL() | |
| 3920 %{ | |
| 3921 constraint(ALLOC_IN_RC(long_rcx_reg)); | |
| 3922 match(RegL); | |
| 3923 match(rRegL); | |
| 3924 | |
| 3925 format %{ %} | |
| 3926 interface(REG_INTER); | |
| 3927 %} | |
| 3928 | |
| 3929 operand rdx_RegL() | |
| 3930 %{ | |
| 3931 constraint(ALLOC_IN_RC(long_rdx_reg)); | |
| 3932 match(RegL); | |
| 3933 match(rRegL); | |
| 3934 | |
| 3935 format %{ %} | |
| 3936 interface(REG_INTER); | |
| 3937 %} | |
| 3938 | |
| 3939 // Flags register, used as output of compare instructions | |
| 3940 operand rFlagsReg() | |
| 3941 %{ | |
| 3942 constraint(ALLOC_IN_RC(int_flags)); | |
| 3943 match(RegFlags); | |
| 3944 | |
| 3945 format %{ "RFLAGS" %} | |
| 3946 interface(REG_INTER); | |
| 3947 %} | |
| 3948 | |
| 3949 // Flags register, used as output of FLOATING POINT compare instructions | |
| 3950 operand rFlagsRegU() | |
| 3951 %{ | |
| 3952 constraint(ALLOC_IN_RC(int_flags)); | |
| 3953 match(RegFlags); | |
| 3954 | |
| 3955 format %{ "RFLAGS_U" %} | |
| 3956 interface(REG_INTER); | |
| 3957 %} | |
| 3958 | |
|
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3959 operand rFlagsRegUCF() %{ |
|
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|
3960 constraint(ALLOC_IN_RC(int_flags)); |
|
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|
3961 match(RegFlags); |
|
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|
3962 predicate(false); |
|
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|
3963 |
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|
3964 format %{ "RFLAGS_U_CF" %} |
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3965 interface(REG_INTER); |
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|
3966 %} |
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|
3967 |
| 0 | 3968 // Float register operands |
| 3969 operand regF() | |
| 3970 %{ | |
| 3971 constraint(ALLOC_IN_RC(float_reg)); | |
| 3972 match(RegF); | |
| 3973 | |
| 3974 format %{ %} | |
| 3975 interface(REG_INTER); | |
| 3976 %} | |
| 3977 | |
| 3978 // Double register operands | |
|
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3979 operand regD() |
| 0 | 3980 %{ |
| 3981 constraint(ALLOC_IN_RC(double_reg)); | |
| 3982 match(RegD); | |
| 3983 | |
| 3984 format %{ %} | |
| 3985 interface(REG_INTER); | |
| 3986 %} | |
| 3987 | |
| 3988 | |
| 3989 //----------Memory Operands---------------------------------------------------- | |
| 3990 // Direct Memory Operand | |
| 3991 // operand direct(immP addr) | |
| 3992 // %{ | |
| 3993 // match(addr); | |
| 3994 | |
| 3995 // format %{ "[$addr]" %} | |
| 3996 // interface(MEMORY_INTER) %{ | |
| 3997 // base(0xFFFFFFFF); | |
| 3998 // index(0x4); | |
| 3999 // scale(0x0); | |
| 4000 // disp($addr); | |
| 4001 // %} | |
| 4002 // %} | |
| 4003 | |
| 4004 // Indirect Memory Operand | |
| 4005 operand indirect(any_RegP reg) | |
| 4006 %{ | |
| 4007 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 4008 match(reg); | |
| 4009 | |
| 4010 format %{ "[$reg]" %} | |
| 4011 interface(MEMORY_INTER) %{ | |
| 4012 base($reg); | |
| 4013 index(0x4); | |
| 4014 scale(0x0); | |
| 4015 disp(0x0); | |
| 4016 %} | |
| 4017 %} | |
| 4018 | |
| 4019 // Indirect Memory Plus Short Offset Operand | |
| 4020 operand indOffset8(any_RegP reg, immL8 off) | |
| 4021 %{ | |
| 4022 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 4023 match(AddP reg off); | |
| 4024 | |
| 4025 format %{ "[$reg + $off (8-bit)]" %} | |
| 4026 interface(MEMORY_INTER) %{ | |
| 4027 base($reg); | |
| 4028 index(0x4); | |
| 4029 scale(0x0); | |
| 4030 disp($off); | |
| 4031 %} | |
| 4032 %} | |
| 4033 | |
| 4034 // Indirect Memory Plus Long Offset Operand | |
| 4035 operand indOffset32(any_RegP reg, immL32 off) | |
| 4036 %{ | |
| 4037 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 4038 match(AddP reg off); | |
| 4039 | |
| 4040 format %{ "[$reg + $off (32-bit)]" %} | |
| 4041 interface(MEMORY_INTER) %{ | |
| 4042 base($reg); | |
| 4043 index(0x4); | |
| 4044 scale(0x0); | |
| 4045 disp($off); | |
| 4046 %} | |
| 4047 %} | |
| 4048 | |
| 4049 // Indirect Memory Plus Index Register Plus Offset Operand | |
| 4050 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off) | |
| 4051 %{ | |
| 4052 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 4053 match(AddP (AddP reg lreg) off); | |
| 4054 | |
| 4055 op_cost(10); | |
| 4056 format %{"[$reg + $off + $lreg]" %} | |
| 4057 interface(MEMORY_INTER) %{ | |
| 4058 base($reg); | |
| 4059 index($lreg); | |
| 4060 scale(0x0); | |
| 4061 disp($off); | |
| 4062 %} | |
| 4063 %} | |
| 4064 | |
| 4065 // Indirect Memory Plus Index Register Plus Offset Operand | |
| 4066 operand indIndex(any_RegP reg, rRegL lreg) | |
| 4067 %{ | |
| 4068 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 4069 match(AddP reg lreg); | |
| 4070 | |
| 4071 op_cost(10); | |
| 4072 format %{"[$reg + $lreg]" %} | |
| 4073 interface(MEMORY_INTER) %{ | |
| 4074 base($reg); | |
| 4075 index($lreg); | |
| 4076 scale(0x0); | |
| 4077 disp(0x0); | |
| 4078 %} | |
| 4079 %} | |
| 4080 | |
| 4081 // Indirect Memory Times Scale Plus Index Register | |
| 4082 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale) | |
| 4083 %{ | |
| 4084 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 4085 match(AddP reg (LShiftL lreg scale)); | |
| 4086 | |
| 4087 op_cost(10); | |
| 4088 format %{"[$reg + $lreg << $scale]" %} | |
| 4089 interface(MEMORY_INTER) %{ | |
| 4090 base($reg); | |
| 4091 index($lreg); | |
| 4092 scale($scale); | |
| 4093 disp(0x0); | |
| 4094 %} | |
| 4095 %} | |
| 4096 | |
| 4097 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand | |
| 4098 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale) | |
| 4099 %{ | |
| 4100 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 4101 match(AddP (AddP reg (LShiftL lreg scale)) off); | |
| 4102 | |
| 4103 op_cost(10); | |
| 4104 format %{"[$reg + $off + $lreg << $scale]" %} | |
| 4105 interface(MEMORY_INTER) %{ | |
| 4106 base($reg); | |
| 4107 index($lreg); | |
| 4108 scale($scale); | |
| 4109 disp($off); | |
| 4110 %} | |
| 4111 %} | |
| 4112 | |
| 4113 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand | |
| 4114 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale) | |
| 4115 %{ | |
| 4116 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 4117 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0); | |
| 4118 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off); | |
| 4119 | |
| 4120 op_cost(10); | |
| 4121 format %{"[$reg + $off + $idx << $scale]" %} | |
| 4122 interface(MEMORY_INTER) %{ | |
| 4123 base($reg); | |
| 4124 index($idx); | |
| 4125 scale($scale); | |
| 4126 disp($off); | |
| 4127 %} | |
| 4128 %} | |
| 4129 | |
|
642
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4130 // Indirect Narrow Oop Plus Offset Operand |
|
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4131 // Note: x86 architecture doesn't support "scale * index + offset" without a base |
|
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4132 // we can't free r12 even with Universe::narrow_oop_base() == NULL. |
|
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4133 operand indCompressedOopOffset(rRegN reg, immL32 off) %{ |
|
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4134 predicate(UseCompressedOops && (Universe::narrow_oop_shift() == Address::times_8)); |
|
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4135 constraint(ALLOC_IN_RC(ptr_reg)); |
|
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4136 match(AddP (DecodeN reg) off); |
|
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4137 |
|
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|
4138 op_cost(10); |
|
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|
4139 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %} |
|
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4140 interface(MEMORY_INTER) %{ |
|
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4141 base(0xc); // R12 |
|
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4142 index($reg); |
|
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4143 scale(0x3); |
|
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4144 disp($off); |
|
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4145 %} |
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4146 %} |
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|
4147 |
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4148 // Indirect Memory Operand |
|
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4149 operand indirectNarrow(rRegN reg) |
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4150 %{ |
|
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4151 predicate(Universe::narrow_oop_shift() == 0); |
|
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4152 constraint(ALLOC_IN_RC(ptr_reg)); |
|
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4153 match(DecodeN reg); |
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|
4154 |
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4155 format %{ "[$reg]" %} |
|
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4156 interface(MEMORY_INTER) %{ |
|
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4157 base($reg); |
|
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4158 index(0x4); |
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4159 scale(0x0); |
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|
4160 disp(0x0); |
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|
4161 %} |
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|
4162 %} |
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4163 |
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4164 // Indirect Memory Plus Short Offset Operand |
|
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4165 operand indOffset8Narrow(rRegN reg, immL8 off) |
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4166 %{ |
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4167 predicate(Universe::narrow_oop_shift() == 0); |
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4168 constraint(ALLOC_IN_RC(ptr_reg)); |
|
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4169 match(AddP (DecodeN reg) off); |
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diff
changeset
|
4170 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4171 format %{ "[$reg + $off (8-bit)]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4172 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4173 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4174 index(0x4); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4175 scale(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4176 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4177 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4178 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4179 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4180 // Indirect Memory Plus Long Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4181 operand indOffset32Narrow(rRegN reg, immL32 off) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4182 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4183 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4184 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4185 match(AddP (DecodeN reg) off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4186 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4187 format %{ "[$reg + $off (32-bit)]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4188 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4189 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4190 index(0x4); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4191 scale(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4192 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4193 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4194 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4195 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4196 // Indirect Memory Plus Index Register Plus Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4197 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4198 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4199 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4200 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4201 match(AddP (AddP (DecodeN reg) lreg) off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4202 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4203 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4204 format %{"[$reg + $off + $lreg]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4205 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4206 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4207 index($lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4208 scale(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4209 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4210 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4211 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4212 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4213 // Indirect Memory Plus Index Register Plus Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4214 operand indIndexNarrow(rRegN reg, rRegL lreg) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4215 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4216 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4217 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4218 match(AddP (DecodeN reg) lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4219 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4220 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4221 format %{"[$reg + $lreg]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4222 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4223 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4224 index($lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4225 scale(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4226 disp(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4227 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4228 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4229 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4230 // Indirect Memory Times Scale Plus Index Register |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4231 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4232 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4233 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4234 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4235 match(AddP (DecodeN reg) (LShiftL lreg scale)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4236 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4237 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4238 format %{"[$reg + $lreg << $scale]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4239 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4240 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4241 index($lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4242 scale($scale); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4243 disp(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4244 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4245 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4246 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4247 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4248 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4249 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4250 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4251 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4252 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4253 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4254 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4255 format %{"[$reg + $off + $lreg << $scale]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4256 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4257 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4258 index($lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4259 scale($scale); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4260 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4261 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4262 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4263 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4264 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4265 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4266 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4267 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4268 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4269 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4270 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4271 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4272 format %{"[$reg + $off + $idx << $scale]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4273 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4274 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4275 index($idx); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4276 scale($scale); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4277 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4278 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4279 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4280 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4281 |
| 0 | 4282 //----------Special Memory Operands-------------------------------------------- |
| 4283 // Stack Slot Operand - This operand is used for loading and storing temporary | |
| 4284 // values on the stack where a match requires a value to | |
| 4285 // flow through memory. | |
| 4286 operand stackSlotP(sRegP reg) | |
| 4287 %{ | |
| 4288 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4289 // No match rule because this operand is only generated in matching | |
| 4290 | |
| 4291 format %{ "[$reg]" %} | |
| 4292 interface(MEMORY_INTER) %{ | |
| 4293 base(0x4); // RSP | |
| 4294 index(0x4); // No Index | |
| 4295 scale(0x0); // No Scale | |
| 4296 disp($reg); // Stack Offset | |
| 4297 %} | |
| 4298 %} | |
| 4299 | |
| 4300 operand stackSlotI(sRegI reg) | |
| 4301 %{ | |
| 4302 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4303 // No match rule because this operand is only generated in matching | |
| 4304 | |
| 4305 format %{ "[$reg]" %} | |
| 4306 interface(MEMORY_INTER) %{ | |
| 4307 base(0x4); // RSP | |
| 4308 index(0x4); // No Index | |
| 4309 scale(0x0); // No Scale | |
| 4310 disp($reg); // Stack Offset | |
| 4311 %} | |
| 4312 %} | |
| 4313 | |
| 4314 operand stackSlotF(sRegF reg) | |
| 4315 %{ | |
| 4316 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4317 // No match rule because this operand is only generated in matching | |
| 4318 | |
| 4319 format %{ "[$reg]" %} | |
| 4320 interface(MEMORY_INTER) %{ | |
| 4321 base(0x4); // RSP | |
| 4322 index(0x4); // No Index | |
| 4323 scale(0x0); // No Scale | |
| 4324 disp($reg); // Stack Offset | |
| 4325 %} | |
| 4326 %} | |
| 4327 | |
| 4328 operand stackSlotD(sRegD reg) | |
| 4329 %{ | |
| 4330 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4331 // No match rule because this operand is only generated in matching | |
| 4332 | |
| 4333 format %{ "[$reg]" %} | |
| 4334 interface(MEMORY_INTER) %{ | |
| 4335 base(0x4); // RSP | |
| 4336 index(0x4); // No Index | |
| 4337 scale(0x0); // No Scale | |
| 4338 disp($reg); // Stack Offset | |
| 4339 %} | |
| 4340 %} | |
| 4341 operand stackSlotL(sRegL reg) | |
| 4342 %{ | |
| 4343 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4344 // No match rule because this operand is only generated in matching | |
| 4345 | |
| 4346 format %{ "[$reg]" %} | |
| 4347 interface(MEMORY_INTER) %{ | |
| 4348 base(0x4); // RSP | |
| 4349 index(0x4); // No Index | |
| 4350 scale(0x0); // No Scale | |
| 4351 disp($reg); // Stack Offset | |
| 4352 %} | |
| 4353 %} | |
| 4354 | |
| 4355 //----------Conditional Branch Operands---------------------------------------- | |
| 4356 // Comparison Op - This is the operation of the comparison, and is limited to | |
| 4357 // the following set of codes: | |
| 4358 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) | |
| 4359 // | |
| 4360 // Other attributes of the comparison, such as unsignedness, are specified | |
| 4361 // by the comparison instruction that sets a condition code flags register. | |
| 4362 // That result is represented by a flags operand whose subtype is appropriate | |
| 4363 // to the unsignedness (etc.) of the comparison. | |
| 4364 // | |
| 4365 // Later, the instruction which matches both the Comparison Op (a Bool) and | |
| 4366 // the flags (produced by the Cmp) specifies the coding of the comparison op | |
| 4367 // by matching a specific subtype of Bool operand below, such as cmpOpU. | |
| 4368 | |
| 4369 // Comparision Code | |
| 4370 operand cmpOp() | |
| 4371 %{ | |
| 4372 match(Bool); | |
| 4373 | |
| 4374 format %{ "" %} | |
| 4375 interface(COND_INTER) %{ | |
|
415
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|
4376 equal(0x4, "e"); |
|
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|
4377 not_equal(0x5, "ne"); |
|
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|
4378 less(0xC, "l"); |
|
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|
4379 greater_equal(0xD, "ge"); |
|
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|
4380 less_equal(0xE, "le"); |
|
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|
4381 greater(0xF, "g"); |
| 0 | 4382 %} |
| 4383 %} | |
| 4384 | |
| 4385 // Comparison Code, unsigned compare. Used by FP also, with | |
| 4386 // C2 (unordered) turned into GT or LT already. The other bits | |
| 4387 // C0 and C3 are turned into Carry & Zero flags. | |
| 4388 operand cmpOpU() | |
| 4389 %{ | |
| 4390 match(Bool); | |
| 4391 | |
| 4392 format %{ "" %} | |
| 4393 interface(COND_INTER) %{ | |
|
415
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|
4394 equal(0x4, "e"); |
|
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|
4395 not_equal(0x5, "ne"); |
|
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|
4396 less(0x2, "b"); |
|
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|
4397 greater_equal(0x3, "nb"); |
|
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|
4398 less_equal(0x6, "be"); |
|
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|
4399 greater(0x7, "nbe"); |
|
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|
4400 %} |
|
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|
4401 %} |
|
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|
4402 |
|
4d9884b01ba6
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changeset
|
4403 |
|
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|
4404 // Floating comparisons that don't require any fixup for the unordered case |
|
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|
4405 operand cmpOpUCF() %{ |
|
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|
4406 match(Bool); |
|
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|
4407 predicate(n->as_Bool()->_test._test == BoolTest::lt || |
|
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|
4408 n->as_Bool()->_test._test == BoolTest::ge || |
|
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|
4409 n->as_Bool()->_test._test == BoolTest::le || |
|
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|
4410 n->as_Bool()->_test._test == BoolTest::gt); |
|
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|
4411 format %{ "" %} |
|
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|
4412 interface(COND_INTER) %{ |
|
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|
4413 equal(0x4, "e"); |
|
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diff
changeset
|
4414 not_equal(0x5, "ne"); |
|
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changeset
|
4415 less(0x2, "b"); |
|
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changeset
|
4416 greater_equal(0x3, "nb"); |
|
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|
4417 less_equal(0x6, "be"); |
|
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|
4418 greater(0x7, "nbe"); |
|
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|
4419 %} |
|
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|
4420 %} |
|
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|
4421 |
|
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|
4422 |
|
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|
4423 // Floating comparisons that can be fixed up with extra conditional jumps |
|
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|
4424 operand cmpOpUCF2() %{ |
|
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|
4425 match(Bool); |
|
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|
4426 predicate(n->as_Bool()->_test._test == BoolTest::ne || |
|
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|
4427 n->as_Bool()->_test._test == BoolTest::eq); |
|
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|
4428 format %{ "" %} |
|
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|
4429 interface(COND_INTER) %{ |
|
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|
4430 equal(0x4, "e"); |
|
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changeset
|
4431 not_equal(0x5, "ne"); |
|
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|
4432 less(0x2, "b"); |
|
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|
4433 greater_equal(0x3, "nb"); |
|
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|
4434 less_equal(0x6, "be"); |
|
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|
4435 greater(0x7, "nbe"); |
| 0 | 4436 %} |
| 4437 %} | |
| 4438 | |
| 4439 | |
| 4440 //----------OPERAND CLASSES---------------------------------------------------- | |
| 4441 // Operand Classes are groups of operands that are used as to simplify | |
| 605 | 4442 // instruction definitions by not requiring the AD writer to specify separate |
| 0 | 4443 // instructions for every form of operand when the instruction accepts |
| 4444 // multiple operand types with the same basic encoding and format. The classic | |
| 4445 // case of this is memory operands. | |
| 4446 | |
| 4447 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex, | |
|
113
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|
4448 indIndexScale, indIndexScaleOffset, indPosIndexScaleOffset, |
|
642
660978a2a31a
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|
4449 indCompressedOopOffset, |
|
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|
4450 indirectNarrow, indOffset8Narrow, indOffset32Narrow, |
|
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|
4451 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow, |
|
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|
4452 indIndexScaleOffsetNarrow, indPosIndexScaleOffsetNarrow); |
| 0 | 4453 |
| 4454 //----------PIPELINE----------------------------------------------------------- | |
| 4455 // Rules which define the behavior of the target architectures pipeline. | |
| 4456 pipeline %{ | |
| 4457 | |
| 4458 //----------ATTRIBUTES--------------------------------------------------------- | |
| 4459 attributes %{ | |
| 4460 variable_size_instructions; // Fixed size instructions | |
| 4461 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle | |
| 4462 instruction_unit_size = 1; // An instruction is 1 bytes long | |
| 4463 instruction_fetch_unit_size = 16; // The processor fetches one line | |
| 4464 instruction_fetch_units = 1; // of 16 bytes | |
| 4465 | |
| 4466 // List of nop instructions | |
| 4467 nops( MachNop ); | |
| 4468 %} | |
| 4469 | |
| 4470 //----------RESOURCES---------------------------------------------------------- | |
| 4471 // Resources are the functional units available to the machine | |
| 4472 | |
| 4473 // Generic P2/P3 pipeline | |
| 4474 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of | |
| 4475 // 3 instructions decoded per cycle. | |
| 4476 // 2 load/store ops per cycle, 1 branch, 1 FPU, | |
| 4477 // 3 ALU op, only ALU0 handles mul instructions. | |
| 4478 resources( D0, D1, D2, DECODE = D0 | D1 | D2, | |
| 4479 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2, | |
| 4480 BR, FPU, | |
| 4481 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2); | |
| 4482 | |
| 4483 //----------PIPELINE DESCRIPTION----------------------------------------------- | |
| 4484 // Pipeline Description specifies the stages in the machine's pipeline | |
| 4485 | |
| 4486 // Generic P2/P3 pipeline | |
| 4487 pipe_desc(S0, S1, S2, S3, S4, S5); | |
| 4488 | |
| 4489 //----------PIPELINE CLASSES--------------------------------------------------- | |
| 4490 // Pipeline Classes describe the stages in which input and output are | |
| 4491 // referenced by the hardware pipeline. | |
| 4492 | |
| 4493 // Naming convention: ialu or fpu | |
| 4494 // Then: _reg | |
| 4495 // Then: _reg if there is a 2nd register | |
| 4496 // Then: _long if it's a pair of instructions implementing a long | |
| 4497 // Then: _fat if it requires the big decoder | |
| 4498 // Or: _mem if it requires the big decoder and a memory unit. | |
| 4499 | |
| 4500 // Integer ALU reg operation | |
| 4501 pipe_class ialu_reg(rRegI dst) | |
| 4502 %{ | |
| 4503 single_instruction; | |
| 4504 dst : S4(write); | |
| 4505 dst : S3(read); | |
| 4506 DECODE : S0; // any decoder | |
| 4507 ALU : S3; // any alu | |
| 4508 %} | |
| 4509 | |
| 4510 // Long ALU reg operation | |
| 4511 pipe_class ialu_reg_long(rRegL dst) | |
| 4512 %{ | |
| 4513 instruction_count(2); | |
| 4514 dst : S4(write); | |
| 4515 dst : S3(read); | |
| 4516 DECODE : S0(2); // any 2 decoders | |
| 4517 ALU : S3(2); // both alus | |
| 4518 %} | |
| 4519 | |
| 4520 // Integer ALU reg operation using big decoder | |
| 4521 pipe_class ialu_reg_fat(rRegI dst) | |
| 4522 %{ | |
| 4523 single_instruction; | |
| 4524 dst : S4(write); | |
| 4525 dst : S3(read); | |
| 4526 D0 : S0; // big decoder only | |
| 4527 ALU : S3; // any alu | |
| 4528 %} | |
| 4529 | |
| 4530 // Long ALU reg operation using big decoder | |
| 4531 pipe_class ialu_reg_long_fat(rRegL dst) | |
| 4532 %{ | |
| 4533 instruction_count(2); | |
| 4534 dst : S4(write); | |
| 4535 dst : S3(read); | |
| 4536 D0 : S0(2); // big decoder only; twice | |
| 4537 ALU : S3(2); // any 2 alus | |
| 4538 %} | |
| 4539 | |
| 4540 // Integer ALU reg-reg operation | |
| 4541 pipe_class ialu_reg_reg(rRegI dst, rRegI src) | |
| 4542 %{ | |
| 4543 single_instruction; | |
| 4544 dst : S4(write); | |
| 4545 src : S3(read); | |
| 4546 DECODE : S0; // any decoder | |
| 4547 ALU : S3; // any alu | |
| 4548 %} | |
| 4549 | |
| 4550 // Long ALU reg-reg operation | |
| 4551 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src) | |
| 4552 %{ | |
| 4553 instruction_count(2); | |
| 4554 dst : S4(write); | |
| 4555 src : S3(read); | |
| 4556 DECODE : S0(2); // any 2 decoders | |
| 4557 ALU : S3(2); // both alus | |
| 4558 %} | |
| 4559 | |
| 4560 // Integer ALU reg-reg operation | |
| 4561 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) | |
| 4562 %{ | |
| 4563 single_instruction; | |
| 4564 dst : S4(write); | |
| 4565 src : S3(read); | |
| 4566 D0 : S0; // big decoder only | |
| 4567 ALU : S3; // any alu | |
| 4568 %} | |
| 4569 | |
| 4570 // Long ALU reg-reg operation | |
| 4571 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src) | |
| 4572 %{ | |
| 4573 instruction_count(2); | |
| 4574 dst : S4(write); | |
| 4575 src : S3(read); | |
| 4576 D0 : S0(2); // big decoder only; twice | |
| 4577 ALU : S3(2); // both alus | |
| 4578 %} | |
| 4579 | |
| 4580 // Integer ALU reg-mem operation | |
| 4581 pipe_class ialu_reg_mem(rRegI dst, memory mem) | |
| 4582 %{ | |
| 4583 single_instruction; | |
| 4584 dst : S5(write); | |
| 4585 mem : S3(read); | |
| 4586 D0 : S0; // big decoder only | |
| 4587 ALU : S4; // any alu | |
| 4588 MEM : S3; // any mem | |
| 4589 %} | |
| 4590 | |
| 4591 // Integer mem operation (prefetch) | |
| 4592 pipe_class ialu_mem(memory mem) | |
| 4593 %{ | |
| 4594 single_instruction; | |
| 4595 mem : S3(read); | |
| 4596 D0 : S0; // big decoder only | |
| 4597 MEM : S3; // any mem | |
| 4598 %} | |
| 4599 | |
| 4600 // Integer Store to Memory | |
| 4601 pipe_class ialu_mem_reg(memory mem, rRegI src) | |
| 4602 %{ | |
| 4603 single_instruction; | |
| 4604 mem : S3(read); | |
| 4605 src : S5(read); | |
| 4606 D0 : S0; // big decoder only | |
| 4607 ALU : S4; // any alu | |
| 4608 MEM : S3; | |
| 4609 %} | |
| 4610 | |
| 4611 // // Long Store to Memory | |
| 4612 // pipe_class ialu_mem_long_reg(memory mem, rRegL src) | |
| 4613 // %{ | |
| 4614 // instruction_count(2); | |
| 4615 // mem : S3(read); | |
| 4616 // src : S5(read); | |
| 4617 // D0 : S0(2); // big decoder only; twice | |
| 4618 // ALU : S4(2); // any 2 alus | |
| 4619 // MEM : S3(2); // Both mems | |
| 4620 // %} | |
| 4621 | |
| 4622 // Integer Store to Memory | |
| 4623 pipe_class ialu_mem_imm(memory mem) | |
| 4624 %{ | |
| 4625 single_instruction; | |
| 4626 mem : S3(read); | |
| 4627 D0 : S0; // big decoder only | |
| 4628 ALU : S4; // any alu | |
| 4629 MEM : S3; | |
| 4630 %} | |
| 4631 | |
| 4632 // Integer ALU0 reg-reg operation | |
| 4633 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) | |
| 4634 %{ | |
| 4635 single_instruction; | |
| 4636 dst : S4(write); | |
| 4637 src : S3(read); | |
| 4638 D0 : S0; // Big decoder only | |
| 4639 ALU0 : S3; // only alu0 | |
| 4640 %} | |
| 4641 | |
| 4642 // Integer ALU0 reg-mem operation | |
| 4643 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) | |
| 4644 %{ | |
| 4645 single_instruction; | |
| 4646 dst : S5(write); | |
| 4647 mem : S3(read); | |
| 4648 D0 : S0; // big decoder only | |
| 4649 ALU0 : S4; // ALU0 only | |
| 4650 MEM : S3; // any mem | |
| 4651 %} | |
| 4652 | |
| 4653 // Integer ALU reg-reg operation | |
| 4654 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2) | |
| 4655 %{ | |
| 4656 single_instruction; | |
| 4657 cr : S4(write); | |
| 4658 src1 : S3(read); | |
| 4659 src2 : S3(read); | |
| 4660 DECODE : S0; // any decoder | |
| 4661 ALU : S3; // any alu | |
| 4662 %} | |
| 4663 | |
| 4664 // Integer ALU reg-imm operation | |
| 4665 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1) | |
| 4666 %{ | |
| 4667 single_instruction; | |
| 4668 cr : S4(write); | |
| 4669 src1 : S3(read); | |
| 4670 DECODE : S0; // any decoder | |
| 4671 ALU : S3; // any alu | |
| 4672 %} | |
| 4673 | |
| 4674 // Integer ALU reg-mem operation | |
| 4675 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2) | |
| 4676 %{ | |
| 4677 single_instruction; | |
| 4678 cr : S4(write); | |
| 4679 src1 : S3(read); | |
| 4680 src2 : S3(read); | |
| 4681 D0 : S0; // big decoder only | |
| 4682 ALU : S4; // any alu | |
| 4683 MEM : S3; | |
| 4684 %} | |
| 4685 | |
| 4686 // Conditional move reg-reg | |
| 4687 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y) | |
| 4688 %{ | |
| 4689 instruction_count(4); | |
| 4690 y : S4(read); | |
| 4691 q : S3(read); | |
| 4692 p : S3(read); | |
| 4693 DECODE : S0(4); // any decoder | |
| 4694 %} | |
| 4695 | |
| 4696 // Conditional move reg-reg | |
| 4697 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr) | |
| 4698 %{ | |
| 4699 single_instruction; | |
| 4700 dst : S4(write); | |
| 4701 src : S3(read); | |
| 4702 cr : S3(read); | |
| 4703 DECODE : S0; // any decoder | |
| 4704 %} | |
| 4705 | |
| 4706 // Conditional move reg-mem | |
| 4707 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src) | |
| 4708 %{ | |
| 4709 single_instruction; | |
| 4710 dst : S4(write); | |
| 4711 src : S3(read); | |
| 4712 cr : S3(read); | |
| 4713 DECODE : S0; // any decoder | |
| 4714 MEM : S3; | |
| 4715 %} | |
| 4716 | |
| 4717 // Conditional move reg-reg long | |
| 4718 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src) | |
| 4719 %{ | |
| 4720 single_instruction; | |
| 4721 dst : S4(write); | |
| 4722 src : S3(read); | |
| 4723 cr : S3(read); | |
| 4724 DECODE : S0(2); // any 2 decoders | |
| 4725 %} | |
| 4726 | |
| 4727 // XXX | |
| 4728 // // Conditional move double reg-reg | |
| 4729 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src) | |
| 4730 // %{ | |
| 4731 // single_instruction; | |
| 4732 // dst : S4(write); | |
| 4733 // src : S3(read); | |
| 4734 // cr : S3(read); | |
| 4735 // DECODE : S0; // any decoder | |
| 4736 // %} | |
| 4737 | |
| 4738 // Float reg-reg operation | |
| 4739 pipe_class fpu_reg(regD dst) | |
| 4740 %{ | |
| 4741 instruction_count(2); | |
| 4742 dst : S3(read); | |
| 4743 DECODE : S0(2); // any 2 decoders | |
| 4744 FPU : S3; | |
| 4745 %} | |
| 4746 | |
| 4747 // Float reg-reg operation | |
| 4748 pipe_class fpu_reg_reg(regD dst, regD src) | |
| 4749 %{ | |
| 4750 instruction_count(2); | |
| 4751 dst : S4(write); | |
| 4752 src : S3(read); | |
| 4753 DECODE : S0(2); // any 2 decoders | |
| 4754 FPU : S3; | |
| 4755 %} | |
| 4756 | |
| 4757 // Float reg-reg operation | |
| 4758 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2) | |
| 4759 %{ | |
| 4760 instruction_count(3); | |
| 4761 dst : S4(write); | |
| 4762 src1 : S3(read); | |
| 4763 src2 : S3(read); | |
| 4764 DECODE : S0(3); // any 3 decoders | |
| 4765 FPU : S3(2); | |
| 4766 %} | |
| 4767 | |
| 4768 // Float reg-reg operation | |
| 4769 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3) | |
| 4770 %{ | |
| 4771 instruction_count(4); | |
| 4772 dst : S4(write); | |
| 4773 src1 : S3(read); | |
| 4774 src2 : S3(read); | |
| 4775 src3 : S3(read); | |
| 4776 DECODE : S0(4); // any 3 decoders | |
| 4777 FPU : S3(2); | |
| 4778 %} | |
| 4779 | |
| 4780 // Float reg-reg operation | |
| 4781 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3) | |
| 4782 %{ | |
| 4783 instruction_count(4); | |
| 4784 dst : S4(write); | |
| 4785 src1 : S3(read); | |
| 4786 src2 : S3(read); | |
| 4787 src3 : S3(read); | |
| 4788 DECODE : S1(3); // any 3 decoders | |
| 4789 D0 : S0; // Big decoder only | |
| 4790 FPU : S3(2); | |
| 4791 MEM : S3; | |
| 4792 %} | |
| 4793 | |
| 4794 // Float reg-mem operation | |
| 4795 pipe_class fpu_reg_mem(regD dst, memory mem) | |
| 4796 %{ | |
| 4797 instruction_count(2); | |
| 4798 dst : S5(write); | |
| 4799 mem : S3(read); | |
| 4800 D0 : S0; // big decoder only | |
| 4801 DECODE : S1; // any decoder for FPU POP | |
| 4802 FPU : S4; | |
| 4803 MEM : S3; // any mem | |
| 4804 %} | |
| 4805 | |
| 4806 // Float reg-mem operation | |
| 4807 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem) | |
| 4808 %{ | |
| 4809 instruction_count(3); | |
| 4810 dst : S5(write); | |
| 4811 src1 : S3(read); | |
| 4812 mem : S3(read); | |
| 4813 D0 : S0; // big decoder only | |
| 4814 DECODE : S1(2); // any decoder for FPU POP | |
| 4815 FPU : S4; | |
| 4816 MEM : S3; // any mem | |
| 4817 %} | |
| 4818 | |
| 4819 // Float mem-reg operation | |
| 4820 pipe_class fpu_mem_reg(memory mem, regD src) | |
| 4821 %{ | |
| 4822 instruction_count(2); | |
| 4823 src : S5(read); | |
| 4824 mem : S3(read); | |
| 4825 DECODE : S0; // any decoder for FPU PUSH | |
| 4826 D0 : S1; // big decoder only | |
| 4827 FPU : S4; | |
| 4828 MEM : S3; // any mem | |
| 4829 %} | |
| 4830 | |
| 4831 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2) | |
| 4832 %{ | |
| 4833 instruction_count(3); | |
| 4834 src1 : S3(read); | |
| 4835 src2 : S3(read); | |
| 4836 mem : S3(read); | |
| 4837 DECODE : S0(2); // any decoder for FPU PUSH | |
| 4838 D0 : S1; // big decoder only | |
| 4839 FPU : S4; | |
| 4840 MEM : S3; // any mem | |
| 4841 %} | |
| 4842 | |
| 4843 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2) | |
| 4844 %{ | |
| 4845 instruction_count(3); | |
| 4846 src1 : S3(read); | |
| 4847 src2 : S3(read); | |
| 4848 mem : S4(read); | |
| 4849 DECODE : S0; // any decoder for FPU PUSH | |
| 4850 D0 : S0(2); // big decoder only | |
| 4851 FPU : S4; | |
| 4852 MEM : S3(2); // any mem | |
| 4853 %} | |
| 4854 | |
| 4855 pipe_class fpu_mem_mem(memory dst, memory src1) | |
| 4856 %{ | |
| 4857 instruction_count(2); | |
| 4858 src1 : S3(read); | |
| 4859 dst : S4(read); | |
| 4860 D0 : S0(2); // big decoder only | |
| 4861 MEM : S3(2); // any mem | |
| 4862 %} | |
| 4863 | |
| 4864 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) | |
| 4865 %{ | |
| 4866 instruction_count(3); | |
| 4867 src1 : S3(read); | |
| 4868 src2 : S3(read); | |
| 4869 dst : S4(read); | |
| 4870 D0 : S0(3); // big decoder only | |
| 4871 FPU : S4; | |
| 4872 MEM : S3(3); // any mem | |
| 4873 %} | |
| 4874 | |
| 4875 pipe_class fpu_mem_reg_con(memory mem, regD src1) | |
| 4876 %{ | |
| 4877 instruction_count(3); | |
| 4878 src1 : S4(read); | |
| 4879 mem : S4(read); | |
| 4880 DECODE : S0; // any decoder for FPU PUSH | |
| 4881 D0 : S0(2); // big decoder only | |
| 4882 FPU : S4; | |
| 4883 MEM : S3(2); // any mem | |
| 4884 %} | |
| 4885 | |
| 4886 // Float load constant | |
| 4887 pipe_class fpu_reg_con(regD dst) | |
| 4888 %{ | |
| 4889 instruction_count(2); | |
| 4890 dst : S5(write); | |
| 4891 D0 : S0; // big decoder only for the load | |
| 4892 DECODE : S1; // any decoder for FPU POP | |
| 4893 FPU : S4; | |
| 4894 MEM : S3; // any mem | |
| 4895 %} | |
| 4896 | |
| 4897 // Float load constant | |
| 4898 pipe_class fpu_reg_reg_con(regD dst, regD src) | |
| 4899 %{ | |
| 4900 instruction_count(3); | |
| 4901 dst : S5(write); | |
| 4902 src : S3(read); | |
| 4903 D0 : S0; // big decoder only for the load | |
| 4904 DECODE : S1(2); // any decoder for FPU POP | |
| 4905 FPU : S4; | |
| 4906 MEM : S3; // any mem | |
| 4907 %} | |
| 4908 | |
| 4909 // UnConditional branch | |
| 4910 pipe_class pipe_jmp(label labl) | |
| 4911 %{ | |
| 4912 single_instruction; | |
| 4913 BR : S3; | |
| 4914 %} | |
| 4915 | |
| 4916 // Conditional branch | |
| 4917 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl) | |
| 4918 %{ | |
| 4919 single_instruction; | |
| 4920 cr : S1(read); | |
| 4921 BR : S3; | |
| 4922 %} | |
| 4923 | |
| 4924 // Allocation idiom | |
| 4925 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr) | |
| 4926 %{ | |
| 4927 instruction_count(1); force_serialization; | |
| 4928 fixed_latency(6); | |
| 4929 heap_ptr : S3(read); | |
| 4930 DECODE : S0(3); | |
| 4931 D0 : S2; | |
| 4932 MEM : S3; | |
| 4933 ALU : S3(2); | |
| 4934 dst : S5(write); | |
| 4935 BR : S5; | |
| 4936 %} | |
| 4937 | |
| 4938 // Generic big/slow expanded idiom | |
| 4939 pipe_class pipe_slow() | |
| 4940 %{ | |
| 4941 instruction_count(10); multiple_bundles; force_serialization; | |
| 4942 fixed_latency(100); | |
| 4943 D0 : S0(2); | |
| 4944 MEM : S3(2); | |
| 4945 %} | |
| 4946 | |
| 4947 // The real do-nothing guy | |
| 4948 pipe_class empty() | |
| 4949 %{ | |
| 4950 instruction_count(0); | |
| 4951 %} | |
| 4952 | |
| 4953 // Define the class for the Nop node | |
| 4954 define | |
| 4955 %{ | |
| 4956 MachNop = empty; | |
| 4957 %} | |
| 4958 | |
| 4959 %} | |
| 4960 | |
| 4961 //----------INSTRUCTIONS------------------------------------------------------- | |
| 4962 // | |
| 4963 // match -- States which machine-independent subtree may be replaced | |
| 4964 // by this instruction. | |
| 4965 // ins_cost -- The estimated cost of this instruction is used by instruction | |
| 4966 // selection to identify a minimum cost tree of machine | |
| 4967 // instructions that matches a tree of machine-independent | |
| 4968 // instructions. | |
| 4969 // format -- A string providing the disassembly for this instruction. | |
| 4970 // The value of an instruction's operand may be inserted | |
| 4971 // by referring to it with a '$' prefix. | |
| 4972 // opcode -- Three instruction opcodes may be provided. These are referred | |
| 4973 // to within an encode class as $primary, $secondary, and $tertiary | |
| 4974 // rrspectively. The primary opcode is commonly used to | |
| 4975 // indicate the type of machine instruction, while secondary | |
| 4976 // and tertiary are often used for prefix options or addressing | |
| 4977 // modes. | |
| 4978 // ins_encode -- A list of encode classes with parameters. The encode class | |
| 4979 // name must have been defined in an 'enc_class' specification | |
| 4980 // in the encode section of the architecture description. | |
| 4981 | |
| 4982 | |
| 4983 //----------Load/Store/Move Instructions--------------------------------------- | |
| 4984 //----------Load Instructions-------------------------------------------------- | |
| 4985 | |
| 4986 // Load Byte (8 bit signed) | |
| 4987 instruct loadB(rRegI dst, memory mem) | |
| 4988 %{ | |
| 4989 match(Set dst (LoadB mem)); | |
| 4990 | |
| 4991 ins_cost(125); | |
| 4992 format %{ "movsbl $dst, $mem\t# byte" %} | |
| 624 | 4993 |
| 4994 ins_encode %{ | |
| 4995 __ movsbl($dst$$Register, $mem$$Address); | |
| 4996 %} | |
| 4997 | |
| 0 | 4998 ins_pipe(ialu_reg_mem); |
| 4999 %} | |
| 5000 | |
| 624 | 5001 // Load Byte (8 bit signed) into Long Register |
| 5002 instruct loadB2L(rRegL dst, memory mem) | |
| 5003 %{ | |
| 5004 match(Set dst (ConvI2L (LoadB mem))); | |
| 5005 | |
| 5006 ins_cost(125); | |
| 5007 format %{ "movsbq $dst, $mem\t# byte -> long" %} | |
| 5008 | |
| 5009 ins_encode %{ | |
| 5010 __ movsbq($dst$$Register, $mem$$Address); | |
| 5011 %} | |
| 5012 | |
| 5013 ins_pipe(ialu_reg_mem); | |
| 5014 %} | |
| 5015 | |
| 5016 // Load Unsigned Byte (8 bit UNsigned) | |
| 5017 instruct loadUB(rRegI dst, memory mem) | |
| 5018 %{ | |
| 5019 match(Set dst (LoadUB mem)); | |
| 0 | 5020 |
| 5021 ins_cost(125); | |
| 5022 format %{ "movzbl $dst, $mem\t# ubyte" %} | |
| 624 | 5023 |
| 5024 ins_encode %{ | |
| 5025 __ movzbl($dst$$Register, $mem$$Address); | |
| 5026 %} | |
| 5027 | |
| 0 | 5028 ins_pipe(ialu_reg_mem); |
| 5029 %} | |
| 5030 | |
| 624 | 5031 // Load Unsigned Byte (8 bit UNsigned) into Long Register |
| 5032 instruct loadUB2L(rRegL dst, memory mem) | |
| 5033 %{ | |
| 5034 match(Set dst (ConvI2L (LoadUB mem))); | |
| 5035 | |
| 5036 ins_cost(125); | |
| 5037 format %{ "movzbq $dst, $mem\t# ubyte -> long" %} | |
| 5038 | |
| 5039 ins_encode %{ | |
| 5040 __ movzbq($dst$$Register, $mem$$Address); | |
| 5041 %} | |
| 5042 | |
| 5043 ins_pipe(ialu_reg_mem); | |
| 5044 %} | |
| 0 | 5045 |
| 824 | 5046 // Load Unsigned Byte (8 bit UNsigned) with a 8-bit mask into Long Register |
| 5047 instruct loadUB2L_immI8(rRegL dst, memory mem, immI8 mask, rFlagsReg cr) %{ | |
| 5048 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); | |
| 5049 effect(KILL cr); | |
| 5050 | |
| 5051 format %{ "movzbq $dst, $mem\t# ubyte & 8-bit mask -> long\n\t" | |
| 5052 "andl $dst, $mask" %} | |
| 5053 ins_encode %{ | |
| 5054 Register Rdst = $dst$$Register; | |
| 5055 __ movzbq(Rdst, $mem$$Address); | |
| 5056 __ andl(Rdst, $mask$$constant); | |
| 5057 %} | |
| 5058 ins_pipe(ialu_reg_mem); | |
| 5059 %} | |
| 5060 | |
| 0 | 5061 // Load Short (16 bit signed) |
| 5062 instruct loadS(rRegI dst, memory mem) | |
| 5063 %{ | |
| 5064 match(Set dst (LoadS mem)); | |
| 5065 | |
| 624 | 5066 ins_cost(125); |
| 0 | 5067 format %{ "movswl $dst, $mem\t# short" %} |
| 624 | 5068 |
| 5069 ins_encode %{ | |
| 5070 __ movswl($dst$$Register, $mem$$Address); | |
| 5071 %} | |
| 5072 | |
| 0 | 5073 ins_pipe(ialu_reg_mem); |
| 5074 %} | |
| 5075 | |
| 785 | 5076 // Load Short (16 bit signed) to Byte (8 bit signed) |
| 5077 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{ | |
| 5078 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); | |
| 5079 | |
| 5080 ins_cost(125); | |
| 5081 format %{ "movsbl $dst, $mem\t# short -> byte" %} | |
| 5082 ins_encode %{ | |
| 5083 __ movsbl($dst$$Register, $mem$$Address); | |
| 5084 %} | |
| 5085 ins_pipe(ialu_reg_mem); | |
| 5086 %} | |
| 5087 | |
| 624 | 5088 // Load Short (16 bit signed) into Long Register |
| 5089 instruct loadS2L(rRegL dst, memory mem) | |
| 5090 %{ | |
| 5091 match(Set dst (ConvI2L (LoadS mem))); | |
| 5092 | |
| 5093 ins_cost(125); | |
| 5094 format %{ "movswq $dst, $mem\t# short -> long" %} | |
| 5095 | |
| 5096 ins_encode %{ | |
| 5097 __ movswq($dst$$Register, $mem$$Address); | |
| 5098 %} | |
| 5099 | |
| 5100 ins_pipe(ialu_reg_mem); | |
| 5101 %} | |
| 0 | 5102 |
|
558
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|
5103 // Load Unsigned Short/Char (16 bit UNsigned) |
|
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|
5104 instruct loadUS(rRegI dst, memory mem) |
|
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
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parents:
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diff
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|
5105 %{ |
|
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
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diff
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|
5106 match(Set dst (LoadUS mem)); |
| 0 | 5107 |
| 5108 ins_cost(125); | |
|
558
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|
5109 format %{ "movzwl $dst, $mem\t# ushort/char" %} |
| 624 | 5110 |
| 5111 ins_encode %{ | |
| 5112 __ movzwl($dst$$Register, $mem$$Address); | |
| 5113 %} | |
| 5114 | |
| 0 | 5115 ins_pipe(ialu_reg_mem); |
| 5116 %} | |
| 5117 | |
| 785 | 5118 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) |
| 5119 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{ | |
| 5120 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); | |
| 5121 | |
| 5122 ins_cost(125); | |
| 5123 format %{ "movsbl $dst, $mem\t# ushort -> byte" %} | |
| 5124 ins_encode %{ | |
| 5125 __ movsbl($dst$$Register, $mem$$Address); | |
| 5126 %} | |
| 5127 ins_pipe(ialu_reg_mem); | |
| 5128 %} | |
| 5129 | |
| 624 | 5130 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register |
| 5131 instruct loadUS2L(rRegL dst, memory mem) | |
| 5132 %{ | |
| 5133 match(Set dst (ConvI2L (LoadUS mem))); | |
| 5134 | |
| 5135 ins_cost(125); | |
| 5136 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %} | |
| 5137 | |
| 5138 ins_encode %{ | |
| 5139 __ movzwq($dst$$Register, $mem$$Address); | |
| 5140 %} | |
| 5141 | |
| 5142 ins_pipe(ialu_reg_mem); | |
| 5143 %} | |
| 0 | 5144 |
| 824 | 5145 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register |
| 5146 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{ | |
| 5147 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5148 | |
| 5149 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %} | |
| 5150 ins_encode %{ | |
| 5151 __ movzbq($dst$$Register, $mem$$Address); | |
| 5152 %} | |
| 5153 ins_pipe(ialu_reg_mem); | |
| 5154 %} | |
| 5155 | |
| 5156 // Load Unsigned Short/Char (16 bit UNsigned) with mask into Long Register | |
| 5157 instruct loadUS2L_immI16(rRegL dst, memory mem, immI16 mask, rFlagsReg cr) %{ | |
| 5158 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5159 effect(KILL cr); | |
| 5160 | |
| 5161 format %{ "movzwq $dst, $mem\t# ushort/char & 16-bit mask -> long\n\t" | |
| 5162 "andl $dst, $mask" %} | |
| 5163 ins_encode %{ | |
| 5164 Register Rdst = $dst$$Register; | |
| 5165 __ movzwq(Rdst, $mem$$Address); | |
| 5166 __ andl(Rdst, $mask$$constant); | |
| 5167 %} | |
| 5168 ins_pipe(ialu_reg_mem); | |
| 5169 %} | |
| 5170 | |
| 0 | 5171 // Load Integer |
| 5172 instruct loadI(rRegI dst, memory mem) | |
| 5173 %{ | |
| 5174 match(Set dst (LoadI mem)); | |
| 5175 | |
| 624 | 5176 ins_cost(125); |
| 0 | 5177 format %{ "movl $dst, $mem\t# int" %} |
| 624 | 5178 |
| 5179 ins_encode %{ | |
| 5180 __ movl($dst$$Register, $mem$$Address); | |
| 5181 %} | |
| 5182 | |
| 5183 ins_pipe(ialu_reg_mem); | |
| 5184 %} | |
| 5185 | |
| 785 | 5186 // Load Integer (32 bit signed) to Byte (8 bit signed) |
| 5187 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{ | |
| 5188 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); | |
| 5189 | |
| 5190 ins_cost(125); | |
| 5191 format %{ "movsbl $dst, $mem\t# int -> byte" %} | |
| 5192 ins_encode %{ | |
| 5193 __ movsbl($dst$$Register, $mem$$Address); | |
| 5194 %} | |
| 5195 ins_pipe(ialu_reg_mem); | |
| 5196 %} | |
| 5197 | |
| 5198 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned) | |
| 5199 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{ | |
| 5200 match(Set dst (AndI (LoadI mem) mask)); | |
| 5201 | |
| 5202 ins_cost(125); | |
| 5203 format %{ "movzbl $dst, $mem\t# int -> ubyte" %} | |
| 5204 ins_encode %{ | |
| 5205 __ movzbl($dst$$Register, $mem$$Address); | |
| 5206 %} | |
| 5207 ins_pipe(ialu_reg_mem); | |
| 5208 %} | |
| 5209 | |
| 5210 // Load Integer (32 bit signed) to Short (16 bit signed) | |
| 5211 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{ | |
| 5212 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); | |
| 5213 | |
| 5214 ins_cost(125); | |
| 5215 format %{ "movswl $dst, $mem\t# int -> short" %} | |
| 5216 ins_encode %{ | |
| 5217 __ movswl($dst$$Register, $mem$$Address); | |
| 5218 %} | |
| 5219 ins_pipe(ialu_reg_mem); | |
| 5220 %} | |
| 5221 | |
| 5222 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned) | |
| 5223 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{ | |
| 5224 match(Set dst (AndI (LoadI mem) mask)); | |
| 5225 | |
| 5226 ins_cost(125); | |
| 5227 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %} | |
| 5228 ins_encode %{ | |
| 5229 __ movzwl($dst$$Register, $mem$$Address); | |
| 5230 %} | |
| 5231 ins_pipe(ialu_reg_mem); | |
| 5232 %} | |
| 5233 | |
| 624 | 5234 // Load Integer into Long Register |
| 5235 instruct loadI2L(rRegL dst, memory mem) | |
| 5236 %{ | |
| 5237 match(Set dst (ConvI2L (LoadI mem))); | |
| 5238 | |
| 5239 ins_cost(125); | |
| 5240 format %{ "movslq $dst, $mem\t# int -> long" %} | |
| 5241 | |
| 5242 ins_encode %{ | |
| 5243 __ movslq($dst$$Register, $mem$$Address); | |
| 5244 %} | |
| 5245 | |
| 5246 ins_pipe(ialu_reg_mem); | |
| 5247 %} | |
| 5248 | |
| 824 | 5249 // Load Integer with mask 0xFF into Long Register |
| 5250 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{ | |
| 5251 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5252 | |
| 5253 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %} | |
| 5254 ins_encode %{ | |
| 5255 __ movzbq($dst$$Register, $mem$$Address); | |
| 5256 %} | |
| 5257 ins_pipe(ialu_reg_mem); | |
| 5258 %} | |
| 5259 | |
| 5260 // Load Integer with mask 0xFFFF into Long Register | |
| 5261 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{ | |
| 5262 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5263 | |
| 5264 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %} | |
| 5265 ins_encode %{ | |
| 5266 __ movzwq($dst$$Register, $mem$$Address); | |
| 5267 %} | |
| 5268 ins_pipe(ialu_reg_mem); | |
| 5269 %} | |
| 5270 | |
| 5271 // Load Integer with a 32-bit mask into Long Register | |
| 5272 instruct loadI2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{ | |
| 5273 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5274 effect(KILL cr); | |
| 5275 | |
| 5276 format %{ "movl $dst, $mem\t# int & 32-bit mask -> long\n\t" | |
| 5277 "andl $dst, $mask" %} | |
| 5278 ins_encode %{ | |
| 5279 Register Rdst = $dst$$Register; | |
| 5280 __ movl(Rdst, $mem$$Address); | |
| 5281 __ andl(Rdst, $mask$$constant); | |
| 5282 %} | |
| 5283 ins_pipe(ialu_reg_mem); | |
| 5284 %} | |
| 5285 | |
| 624 | 5286 // Load Unsigned Integer into Long Register |
| 5287 instruct loadUI2L(rRegL dst, memory mem) | |
| 5288 %{ | |
| 5289 match(Set dst (LoadUI2L mem)); | |
| 5290 | |
| 5291 ins_cost(125); | |
| 5292 format %{ "movl $dst, $mem\t# uint -> long" %} | |
| 5293 | |
| 5294 ins_encode %{ | |
| 5295 __ movl($dst$$Register, $mem$$Address); | |
| 5296 %} | |
| 5297 | |
| 0 | 5298 ins_pipe(ialu_reg_mem); |
| 5299 %} | |
| 5300 | |
| 5301 // Load Long | |
| 5302 instruct loadL(rRegL dst, memory mem) | |
| 5303 %{ | |
| 5304 match(Set dst (LoadL mem)); | |
| 5305 | |
| 624 | 5306 ins_cost(125); |
| 0 | 5307 format %{ "movq $dst, $mem\t# long" %} |
| 624 | 5308 |
| 5309 ins_encode %{ | |
| 5310 __ movq($dst$$Register, $mem$$Address); | |
| 5311 %} | |
| 5312 | |
| 0 | 5313 ins_pipe(ialu_reg_mem); // XXX |
| 5314 %} | |
| 5315 | |
| 5316 // Load Range | |
| 5317 instruct loadRange(rRegI dst, memory mem) | |
| 5318 %{ | |
| 5319 match(Set dst (LoadRange mem)); | |
| 5320 | |
| 5321 ins_cost(125); // XXX | |
| 5322 format %{ "movl $dst, $mem\t# range" %} | |
| 5323 opcode(0x8B); | |
| 5324 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5325 ins_pipe(ialu_reg_mem); | |
| 5326 %} | |
| 5327 | |
| 5328 // Load Pointer | |
| 5329 instruct loadP(rRegP dst, memory mem) | |
| 5330 %{ | |
| 5331 match(Set dst (LoadP mem)); | |
| 5332 | |
| 5333 ins_cost(125); // XXX | |
| 5334 format %{ "movq $dst, $mem\t# ptr" %} | |
| 5335 opcode(0x8B); | |
| 5336 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5337 ins_pipe(ialu_reg_mem); // XXX | |
| 5338 %} | |
| 5339 | |
|
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5340 // Load Compressed Pointer |
| 163 | 5341 instruct loadN(rRegN dst, memory mem) |
|
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5342 %{ |
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5343 match(Set dst (LoadN mem)); |
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5344 |
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5345 ins_cost(125); // XXX |
|
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5346 format %{ "movl $dst, $mem\t# compressed ptr" %} |
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5347 ins_encode %{ |
|
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5348 __ movl($dst$$Register, $mem$$Address); |
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5349 %} |
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5350 ins_pipe(ialu_reg_mem); // XXX |
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5351 %} |
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5352 |
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5353 |
| 0 | 5354 // Load Klass Pointer |
| 5355 instruct loadKlass(rRegP dst, memory mem) | |
| 5356 %{ | |
| 5357 match(Set dst (LoadKlass mem)); | |
| 5358 | |
| 5359 ins_cost(125); // XXX | |
| 5360 format %{ "movq $dst, $mem\t# class" %} | |
| 5361 opcode(0x8B); | |
| 5362 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5363 ins_pipe(ialu_reg_mem); // XXX | |
| 5364 %} | |
| 5365 | |
|
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5366 // Load narrow Klass Pointer |
|
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5367 instruct loadNKlass(rRegN dst, memory mem) |
|
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5368 %{ |
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5369 match(Set dst (LoadNKlass mem)); |
|
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5370 |
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5371 ins_cost(125); // XXX |
|
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5372 format %{ "movl $dst, $mem\t# compressed klass ptr" %} |
|
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5373 ins_encode %{ |
|
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5374 __ movl($dst$$Register, $mem$$Address); |
|
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5375 %} |
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5376 ins_pipe(ialu_reg_mem); // XXX |
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5377 %} |
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5378 |
| 0 | 5379 // Load Float |
| 5380 instruct loadF(regF dst, memory mem) | |
| 5381 %{ | |
| 5382 match(Set dst (LoadF mem)); | |
| 5383 | |
| 5384 ins_cost(145); // XXX | |
| 5385 format %{ "movss $dst, $mem\t# float" %} | |
| 4759 | 5386 ins_encode %{ |
| 5387 __ movflt($dst$$XMMRegister, $mem$$Address); | |
| 5388 %} | |
| 0 | 5389 ins_pipe(pipe_slow); // XXX |
| 5390 %} | |
| 5391 | |
| 5392 // Load Double | |
| 5393 instruct loadD_partial(regD dst, memory mem) | |
| 5394 %{ | |
| 5395 predicate(!UseXmmLoadAndClearUpper); | |
| 5396 match(Set dst (LoadD mem)); | |
| 5397 | |
| 5398 ins_cost(145); // XXX | |
| 5399 format %{ "movlpd $dst, $mem\t# double" %} | |
| 4759 | 5400 ins_encode %{ |
| 5401 __ movdbl($dst$$XMMRegister, $mem$$Address); | |
| 5402 %} | |
| 0 | 5403 ins_pipe(pipe_slow); // XXX |
| 5404 %} | |
| 5405 | |
| 5406 instruct loadD(regD dst, memory mem) | |
| 5407 %{ | |
| 5408 predicate(UseXmmLoadAndClearUpper); | |
| 5409 match(Set dst (LoadD mem)); | |
| 5410 | |
| 5411 ins_cost(145); // XXX | |
| 5412 format %{ "movsd $dst, $mem\t# double" %} | |
| 4759 | 5413 ins_encode %{ |
| 5414 __ movdbl($dst$$XMMRegister, $mem$$Address); | |
| 5415 %} | |
| 0 | 5416 ins_pipe(pipe_slow); // XXX |
| 5417 %} | |
| 5418 | |
| 5419 // Load Aligned Packed Byte to XMM register | |
| 5420 instruct loadA8B(regD dst, memory mem) %{ | |
| 5421 match(Set dst (Load8B mem)); | |
| 5422 ins_cost(125); | |
| 5423 format %{ "MOVQ $dst,$mem\t! packed8B" %} | |
| 4759 | 5424 ins_encode %{ |
| 5425 __ movq($dst$$XMMRegister, $mem$$Address); | |
| 5426 %} | |
| 0 | 5427 ins_pipe( pipe_slow ); |
| 5428 %} | |
| 5429 | |
| 5430 // Load Aligned Packed Short to XMM register | |
| 5431 instruct loadA4S(regD dst, memory mem) %{ | |
| 5432 match(Set dst (Load4S mem)); | |
| 5433 ins_cost(125); | |
| 5434 format %{ "MOVQ $dst,$mem\t! packed4S" %} | |
| 4759 | 5435 ins_encode %{ |
| 5436 __ movq($dst$$XMMRegister, $mem$$Address); | |
| 5437 %} | |
| 0 | 5438 ins_pipe( pipe_slow ); |
| 5439 %} | |
| 5440 | |
| 5441 // Load Aligned Packed Char to XMM register | |
| 5442 instruct loadA4C(regD dst, memory mem) %{ | |
| 5443 match(Set dst (Load4C mem)); | |
| 5444 ins_cost(125); | |
| 5445 format %{ "MOVQ $dst,$mem\t! packed4C" %} | |
| 4759 | 5446 ins_encode %{ |
| 5447 __ movq($dst$$XMMRegister, $mem$$Address); | |
| 5448 %} | |
| 0 | 5449 ins_pipe( pipe_slow ); |
| 5450 %} | |
| 5451 | |
| 5452 // Load Aligned Packed Integer to XMM register | |
| 5453 instruct load2IU(regD dst, memory mem) %{ | |
| 5454 match(Set dst (Load2I mem)); | |
| 5455 ins_cost(125); | |
| 5456 format %{ "MOVQ $dst,$mem\t! packed2I" %} | |
| 4759 | 5457 ins_encode %{ |
| 5458 __ movq($dst$$XMMRegister, $mem$$Address); | |
| 5459 %} | |
| 0 | 5460 ins_pipe( pipe_slow ); |
| 5461 %} | |
| 5462 | |
| 5463 // Load Aligned Packed Single to XMM | |
| 5464 instruct loadA2F(regD dst, memory mem) %{ | |
| 5465 match(Set dst (Load2F mem)); | |
| 4759 | 5466 ins_cost(125); |
| 0 | 5467 format %{ "MOVQ $dst,$mem\t! packed2F" %} |
| 4759 | 5468 ins_encode %{ |
| 5469 __ movq($dst$$XMMRegister, $mem$$Address); | |
| 5470 %} | |
| 0 | 5471 ins_pipe( pipe_slow ); |
| 5472 %} | |
| 5473 | |
| 5474 // Load Effective Address | |
| 5475 instruct leaP8(rRegP dst, indOffset8 mem) | |
| 5476 %{ | |
| 5477 match(Set dst mem); | |
| 5478 | |
| 5479 ins_cost(110); // XXX | |
| 5480 format %{ "leaq $dst, $mem\t# ptr 8" %} | |
| 5481 opcode(0x8D); | |
| 5482 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5483 ins_pipe(ialu_reg_reg_fat); | |
| 5484 %} | |
| 5485 | |
| 5486 instruct leaP32(rRegP dst, indOffset32 mem) | |
| 5487 %{ | |
| 5488 match(Set dst mem); | |
| 5489 | |
| 5490 ins_cost(110); | |
| 5491 format %{ "leaq $dst, $mem\t# ptr 32" %} | |
| 5492 opcode(0x8D); | |
| 5493 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5494 ins_pipe(ialu_reg_reg_fat); | |
| 5495 %} | |
| 5496 | |
| 5497 // instruct leaPIdx(rRegP dst, indIndex mem) | |
| 5498 // %{ | |
| 5499 // match(Set dst mem); | |
| 5500 | |
| 5501 // ins_cost(110); | |
| 5502 // format %{ "leaq $dst, $mem\t# ptr idx" %} | |
| 5503 // opcode(0x8D); | |
| 5504 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5505 // ins_pipe(ialu_reg_reg_fat); | |
| 5506 // %} | |
| 5507 | |
| 5508 instruct leaPIdxOff(rRegP dst, indIndexOffset mem) | |
| 5509 %{ | |
| 5510 match(Set dst mem); | |
| 5511 | |
| 5512 ins_cost(110); | |
| 5513 format %{ "leaq $dst, $mem\t# ptr idxoff" %} | |
| 5514 opcode(0x8D); | |
| 5515 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5516 ins_pipe(ialu_reg_reg_fat); | |
| 5517 %} | |
| 5518 | |
| 5519 instruct leaPIdxScale(rRegP dst, indIndexScale mem) | |
| 5520 %{ | |
| 5521 match(Set dst mem); | |
| 5522 | |
| 5523 ins_cost(110); | |
| 5524 format %{ "leaq $dst, $mem\t# ptr idxscale" %} | |
| 5525 opcode(0x8D); | |
| 5526 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5527 ins_pipe(ialu_reg_reg_fat); | |
| 5528 %} | |
| 5529 | |
| 5530 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem) | |
| 5531 %{ | |
| 5532 match(Set dst mem); | |
| 5533 | |
| 5534 ins_cost(110); | |
| 5535 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %} | |
| 5536 opcode(0x8D); | |
| 5537 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5538 ins_pipe(ialu_reg_reg_fat); | |
| 5539 %} | |
| 5540 | |
|
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5541 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem) |
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5542 %{ |
|
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5543 match(Set dst mem); |
|
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|
5544 |
|
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5545 ins_cost(110); |
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|
5546 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %} |
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5547 opcode(0x8D); |
|
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5548 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
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5549 ins_pipe(ialu_reg_reg_fat); |
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5550 %} |
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5551 |
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5552 // Load Effective Address which uses Narrow (32-bits) oop |
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5553 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem) |
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5554 %{ |
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5555 predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0)); |
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5556 match(Set dst mem); |
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5557 |
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5558 ins_cost(110); |
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5559 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %} |
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5560 opcode(0x8D); |
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5561 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
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5562 ins_pipe(ialu_reg_reg_fat); |
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5563 %} |
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5564 |
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5565 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem) |
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5566 %{ |
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5567 predicate(Universe::narrow_oop_shift() == 0); |
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5568 match(Set dst mem); |
|
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5569 |
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5570 ins_cost(110); // XXX |
|
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5571 format %{ "leaq $dst, $mem\t# ptr off8narrow" %} |
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5572 opcode(0x8D); |
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5573 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
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5574 ins_pipe(ialu_reg_reg_fat); |
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5575 %} |
|
660978a2a31a
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kvn
parents:
624
diff
changeset
|
5576 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5577 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5578 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5579 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5580 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5581 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5582 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5583 format %{ "leaq $dst, $mem\t# ptr off32narrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5584 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5585 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5586 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5587 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5588 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5589 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5590 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5591 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5592 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5593 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5594 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5595 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5596 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5597 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5598 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5599 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5600 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5601 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5602 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5603 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5604 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5605 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5606 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5607 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5608 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5609 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
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kvn
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624
diff
changeset
|
5610 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5611 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5612 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5613 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5614 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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624
diff
changeset
|
5615 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5616 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5617 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5618 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5619 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5620 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5621 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
5622 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5623 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5624 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5625 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5626 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5627 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5628 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5629 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5630 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5631 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5632 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5633 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5634 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5635 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
5636 |
| 0 | 5637 instruct loadConI(rRegI dst, immI src) |
| 5638 %{ | |
| 5639 match(Set dst src); | |
| 5640 | |
| 5641 format %{ "movl $dst, $src\t# int" %} | |
| 5642 ins_encode(load_immI(dst, src)); | |
| 5643 ins_pipe(ialu_reg_fat); // XXX | |
| 5644 %} | |
| 5645 | |
| 5646 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr) | |
| 5647 %{ | |
| 5648 match(Set dst src); | |
| 5649 effect(KILL cr); | |
| 5650 | |
| 5651 ins_cost(50); | |
| 5652 format %{ "xorl $dst, $dst\t# int" %} | |
| 5653 opcode(0x33); /* + rd */ | |
| 5654 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst)); | |
| 5655 ins_pipe(ialu_reg); | |
| 5656 %} | |
| 5657 | |
| 5658 instruct loadConL(rRegL dst, immL src) | |
| 5659 %{ | |
| 5660 match(Set dst src); | |
| 5661 | |
| 5662 ins_cost(150); | |
| 5663 format %{ "movq $dst, $src\t# long" %} | |
| 5664 ins_encode(load_immL(dst, src)); | |
| 5665 ins_pipe(ialu_reg); | |
| 5666 %} | |
| 5667 | |
| 5668 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr) | |
| 5669 %{ | |
| 5670 match(Set dst src); | |
| 5671 effect(KILL cr); | |
| 5672 | |
| 5673 ins_cost(50); | |
| 5674 format %{ "xorl $dst, $dst\t# long" %} | |
| 5675 opcode(0x33); /* + rd */ | |
| 5676 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst)); | |
| 5677 ins_pipe(ialu_reg); // XXX | |
| 5678 %} | |
| 5679 | |
| 5680 instruct loadConUL32(rRegL dst, immUL32 src) | |
| 5681 %{ | |
| 5682 match(Set dst src); | |
| 5683 | |
| 5684 ins_cost(60); | |
| 5685 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %} | |
| 5686 ins_encode(load_immUL32(dst, src)); | |
| 5687 ins_pipe(ialu_reg); | |
| 5688 %} | |
| 5689 | |
| 5690 instruct loadConL32(rRegL dst, immL32 src) | |
| 5691 %{ | |
| 5692 match(Set dst src); | |
| 5693 | |
| 5694 ins_cost(70); | |
| 5695 format %{ "movq $dst, $src\t# long (32-bit)" %} | |
| 5696 ins_encode(load_immL32(dst, src)); | |
| 5697 ins_pipe(ialu_reg); | |
| 5698 %} | |
| 5699 | |
| 2008 | 5700 instruct loadConP(rRegP dst, immP con) %{ |
| 5701 match(Set dst con); | |
| 5702 | |
| 5703 format %{ "movq $dst, $con\t# ptr" %} | |
| 5704 ins_encode(load_immP(dst, con)); | |
| 0 | 5705 ins_pipe(ialu_reg_fat); // XXX |
| 5706 %} | |
| 5707 | |
| 5708 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr) | |
| 5709 %{ | |
| 5710 match(Set dst src); | |
| 5711 effect(KILL cr); | |
| 5712 | |
| 5713 ins_cost(50); | |
| 5714 format %{ "xorl $dst, $dst\t# ptr" %} | |
| 5715 opcode(0x33); /* + rd */ | |
| 5716 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst)); | |
| 5717 ins_pipe(ialu_reg); | |
| 5718 %} | |
| 5719 | |
| 5720 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr) | |
| 5721 %{ | |
| 5722 match(Set dst src); | |
| 5723 effect(KILL cr); | |
| 5724 | |
| 5725 ins_cost(60); | |
| 5726 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %} | |
| 5727 ins_encode(load_immP31(dst, src)); | |
| 5728 ins_pipe(ialu_reg); | |
| 5729 %} | |
| 5730 | |
| 2008 | 5731 instruct loadConF(regF dst, immF con) %{ |
| 5732 match(Set dst con); | |
| 0 | 5733 ins_cost(125); |
| 2008 | 5734 format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %} |
| 5735 ins_encode %{ | |
| 5736 __ movflt($dst$$XMMRegister, $constantaddress($con)); | |
| 5737 %} | |
| 0 | 5738 ins_pipe(pipe_slow); |
| 5739 %} | |
| 5740 | |
|
113
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6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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71
diff
changeset
|
5741 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{ |
|
ba764ed4b6f2
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diff
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|
5742 match(Set dst src); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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71
diff
changeset
|
5743 effect(KILL cr); |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
5744 format %{ "xorq $dst, $src\t# compressed NULL ptr" %} |
|
113
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diff
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|
5745 ins_encode %{ |
|
642
660978a2a31a
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624
diff
changeset
|
5746 __ xorq($dst$$Register, $dst$$Register); |
|
113
ba764ed4b6f2
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|
5747 %} |
|
ba764ed4b6f2
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diff
changeset
|
5748 ins_pipe(ialu_reg); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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71
diff
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|
5749 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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71
diff
changeset
|
5750 |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
5751 instruct loadConN(rRegN dst, immN src) %{ |
|
113
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|
5752 match(Set dst src); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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71
diff
changeset
|
5753 |
|
ba764ed4b6f2
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coleenp
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71
diff
changeset
|
5754 ins_cost(125); |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
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parents:
163
diff
changeset
|
5755 format %{ "movl $dst, $src\t# compressed ptr" %} |
|
113
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|
5756 ins_encode %{ |
|
ba764ed4b6f2
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71
diff
changeset
|
5757 address con = (address)$src$$constant; |
|
ba764ed4b6f2
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71
diff
changeset
|
5758 if (con == NULL) { |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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71
diff
changeset
|
5759 ShouldNotReachHere(); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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71
diff
changeset
|
5760 } else { |
|
642
660978a2a31a
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parents:
624
diff
changeset
|
5761 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant); |
|
113
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|
5762 } |
|
ba764ed4b6f2
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71
diff
changeset
|
5763 %} |
|
ba764ed4b6f2
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diff
changeset
|
5764 ins_pipe(ialu_reg_fat); // XXX |
|
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|
5765 %} |
|
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|
5766 |
| 0 | 5767 instruct loadConF0(regF dst, immF0 src) |
| 5768 %{ | |
| 5769 match(Set dst src); | |
| 5770 ins_cost(100); | |
| 5771 | |
| 5772 format %{ "xorps $dst, $dst\t# float 0.0" %} | |
| 4759 | 5773 ins_encode %{ |
| 5774 __ xorps($dst$$XMMRegister, $dst$$XMMRegister); | |
| 5775 %} | |
| 0 | 5776 ins_pipe(pipe_slow); |
| 5777 %} | |
| 5778 | |
| 5779 // Use the same format since predicate() can not be used here. | |
| 2008 | 5780 instruct loadConD(regD dst, immD con) %{ |
| 5781 match(Set dst con); | |
| 0 | 5782 ins_cost(125); |
| 2008 | 5783 format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %} |
| 5784 ins_encode %{ | |
| 5785 __ movdbl($dst$$XMMRegister, $constantaddress($con)); | |
| 5786 %} | |
| 0 | 5787 ins_pipe(pipe_slow); |
| 5788 %} | |
| 5789 | |
| 5790 instruct loadConD0(regD dst, immD0 src) | |
| 5791 %{ | |
| 5792 match(Set dst src); | |
| 5793 ins_cost(100); | |
| 5794 | |
| 5795 format %{ "xorpd $dst, $dst\t# double 0.0" %} | |
| 4759 | 5796 ins_encode %{ |
| 5797 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister); | |
| 5798 %} | |
| 0 | 5799 ins_pipe(pipe_slow); |
| 5800 %} | |
| 5801 | |
| 5802 instruct loadSSI(rRegI dst, stackSlotI src) | |
| 5803 %{ | |
| 5804 match(Set dst src); | |
| 5805 | |
| 5806 ins_cost(125); | |
| 5807 format %{ "movl $dst, $src\t# int stk" %} | |
| 5808 opcode(0x8B); | |
| 5809 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 5810 ins_pipe(ialu_reg_mem); | |
| 5811 %} | |
| 5812 | |
| 5813 instruct loadSSL(rRegL dst, stackSlotL src) | |
| 5814 %{ | |
| 5815 match(Set dst src); | |
| 5816 | |
| 5817 ins_cost(125); | |
| 5818 format %{ "movq $dst, $src\t# long stk" %} | |
| 5819 opcode(0x8B); | |
| 5820 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 5821 ins_pipe(ialu_reg_mem); | |
| 5822 %} | |
| 5823 | |
| 5824 instruct loadSSP(rRegP dst, stackSlotP src) | |
| 5825 %{ | |
| 5826 match(Set dst src); | |
| 5827 | |
| 5828 ins_cost(125); | |
| 5829 format %{ "movq $dst, $src\t# ptr stk" %} | |
| 5830 opcode(0x8B); | |
| 5831 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 5832 ins_pipe(ialu_reg_mem); | |
| 5833 %} | |
| 5834 | |
| 5835 instruct loadSSF(regF dst, stackSlotF src) | |
| 5836 %{ | |
| 5837 match(Set dst src); | |
| 5838 | |
| 5839 ins_cost(125); | |
| 5840 format %{ "movss $dst, $src\t# float stk" %} | |
| 4759 | 5841 ins_encode %{ |
| 5842 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 5843 %} | |
| 0 | 5844 ins_pipe(pipe_slow); // XXX |
| 5845 %} | |
| 5846 | |
| 5847 // Use the same format since predicate() can not be used here. | |
| 5848 instruct loadSSD(regD dst, stackSlotD src) | |
| 5849 %{ | |
| 5850 match(Set dst src); | |
| 5851 | |
| 5852 ins_cost(125); | |
| 5853 format %{ "movsd $dst, $src\t# double stk" %} | |
| 5854 ins_encode %{ | |
| 5855 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 5856 %} | |
| 5857 ins_pipe(pipe_slow); // XXX | |
| 5858 %} | |
| 5859 | |
| 5860 // Prefetch instructions. | |
| 5861 // Must be safe to execute with invalid address (cannot fault). | |
| 5862 | |
| 5863 instruct prefetchr( memory mem ) %{ | |
| 5864 predicate(ReadPrefetchInstr==3); | |
| 5865 match(PrefetchRead mem); | |
| 5866 ins_cost(125); | |
| 5867 | |
| 5868 format %{ "PREFETCHR $mem\t# Prefetch into level 1 cache" %} | |
| 3854 | 5869 ins_encode %{ |
| 5870 __ prefetchr($mem$$Address); | |
| 5871 %} | |
| 0 | 5872 ins_pipe(ialu_mem); |
| 5873 %} | |
| 5874 | |
| 5875 instruct prefetchrNTA( memory mem ) %{ | |
| 5876 predicate(ReadPrefetchInstr==0); | |
| 5877 match(PrefetchRead mem); | |
| 5878 ins_cost(125); | |
| 5879 | |
| 5880 format %{ "PREFETCHNTA $mem\t# Prefetch into non-temporal cache for read" %} | |
| 3854 | 5881 ins_encode %{ |
| 5882 __ prefetchnta($mem$$Address); | |
| 5883 %} | |
| 0 | 5884 ins_pipe(ialu_mem); |
| 5885 %} | |
| 5886 | |
| 5887 instruct prefetchrT0( memory mem ) %{ | |
| 5888 predicate(ReadPrefetchInstr==1); | |
| 5889 match(PrefetchRead mem); | |
| 5890 ins_cost(125); | |
| 5891 | |
| 5892 format %{ "PREFETCHT0 $mem\t# prefetch into L1 and L2 caches for read" %} | |
| 3854 | 5893 ins_encode %{ |
| 5894 __ prefetcht0($mem$$Address); | |
| 5895 %} | |
| 0 | 5896 ins_pipe(ialu_mem); |
| 5897 %} | |
| 5898 | |
| 5899 instruct prefetchrT2( memory mem ) %{ | |
| 5900 predicate(ReadPrefetchInstr==2); | |
| 5901 match(PrefetchRead mem); | |
| 5902 ins_cost(125); | |
| 5903 | |
| 5904 format %{ "PREFETCHT2 $mem\t# prefetch into L2 caches for read" %} | |
| 3854 | 5905 ins_encode %{ |
| 5906 __ prefetcht2($mem$$Address); | |
| 5907 %} | |
| 0 | 5908 ins_pipe(ialu_mem); |
| 5909 %} | |
| 5910 | |
| 5911 instruct prefetchwNTA( memory mem ) %{ | |
| 5912 match(PrefetchWrite mem); | |
| 5913 ins_cost(125); | |
| 5914 | |
| 5915 format %{ "PREFETCHNTA $mem\t# Prefetch to non-temporal cache for write" %} | |
| 3854 | 5916 ins_encode %{ |
| 5917 __ prefetchnta($mem$$Address); | |
| 5918 %} | |
| 0 | 5919 ins_pipe(ialu_mem); |
| 5920 %} | |
| 5921 | |
| 3854 | 5922 // Prefetch instructions for allocation. |
| 5923 | |
| 5924 instruct prefetchAlloc( memory mem ) %{ | |
| 5925 predicate(AllocatePrefetchInstr==3); | |
| 5926 match(PrefetchAllocation mem); | |
| 5927 ins_cost(125); | |
| 5928 | |
| 5929 format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %} | |
| 5930 ins_encode %{ | |
| 5931 __ prefetchw($mem$$Address); | |
| 5932 %} | |
| 5933 ins_pipe(ialu_mem); | |
| 5934 %} | |
| 5935 | |
| 5936 instruct prefetchAllocNTA( memory mem ) %{ | |
| 5937 predicate(AllocatePrefetchInstr==0); | |
| 5938 match(PrefetchAllocation mem); | |
| 0 | 5939 ins_cost(125); |
| 5940 | |
| 3854 | 5941 format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %} |
| 5942 ins_encode %{ | |
| 5943 __ prefetchnta($mem$$Address); | |
| 5944 %} | |
| 0 | 5945 ins_pipe(ialu_mem); |
| 5946 %} | |
| 5947 | |
| 3854 | 5948 instruct prefetchAllocT0( memory mem ) %{ |
| 5949 predicate(AllocatePrefetchInstr==1); | |
| 5950 match(PrefetchAllocation mem); | |
| 0 | 5951 ins_cost(125); |
| 5952 | |
| 3854 | 5953 format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %} |
| 5954 ins_encode %{ | |
| 5955 __ prefetcht0($mem$$Address); | |
| 5956 %} | |
| 5957 ins_pipe(ialu_mem); | |
| 5958 %} | |
| 5959 | |
| 5960 instruct prefetchAllocT2( memory mem ) %{ | |
| 5961 predicate(AllocatePrefetchInstr==2); | |
| 5962 match(PrefetchAllocation mem); | |
| 5963 ins_cost(125); | |
| 5964 | |
| 5965 format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %} | |
| 5966 ins_encode %{ | |
| 5967 __ prefetcht2($mem$$Address); | |
| 5968 %} | |
| 0 | 5969 ins_pipe(ialu_mem); |
| 5970 %} | |
| 5971 | |
| 5972 //----------Store Instructions------------------------------------------------- | |
| 5973 | |
| 5974 // Store Byte | |
| 5975 instruct storeB(memory mem, rRegI src) | |
| 5976 %{ | |
| 5977 match(Set mem (StoreB mem src)); | |
| 5978 | |
| 5979 ins_cost(125); // XXX | |
| 5980 format %{ "movb $mem, $src\t# byte" %} | |
| 5981 opcode(0x88); | |
| 5982 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
| 5983 ins_pipe(ialu_mem_reg); | |
| 5984 %} | |
| 5985 | |
| 5986 // Store Char/Short | |
| 5987 instruct storeC(memory mem, rRegI src) | |
| 5988 %{ | |
| 5989 match(Set mem (StoreC mem src)); | |
| 5990 | |
| 5991 ins_cost(125); // XXX | |
| 5992 format %{ "movw $mem, $src\t# char/short" %} | |
| 5993 opcode(0x89); | |
| 5994 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
| 5995 ins_pipe(ialu_mem_reg); | |
| 5996 %} | |
| 5997 | |
| 5998 // Store Integer | |
| 5999 instruct storeI(memory mem, rRegI src) | |
| 6000 %{ | |
| 6001 match(Set mem (StoreI mem src)); | |
| 6002 | |
| 6003 ins_cost(125); // XXX | |
| 6004 format %{ "movl $mem, $src\t# int" %} | |
| 6005 opcode(0x89); | |
| 6006 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
| 6007 ins_pipe(ialu_mem_reg); | |
| 6008 %} | |
| 6009 | |
| 6010 // Store Long | |
| 6011 instruct storeL(memory mem, rRegL src) | |
| 6012 %{ | |
| 6013 match(Set mem (StoreL mem src)); | |
| 6014 | |
| 6015 ins_cost(125); // XXX | |
| 6016 format %{ "movq $mem, $src\t# long" %} | |
| 6017 opcode(0x89); | |
| 6018 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem)); | |
| 6019 ins_pipe(ialu_mem_reg); // XXX | |
| 6020 %} | |
| 6021 | |
| 6022 // Store Pointer | |
| 6023 instruct storeP(memory mem, any_RegP src) | |
| 6024 %{ | |
| 6025 match(Set mem (StoreP mem src)); | |
| 6026 | |
| 6027 ins_cost(125); // XXX | |
| 6028 format %{ "movq $mem, $src\t# ptr" %} | |
| 6029 opcode(0x89); | |
| 6030 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem)); | |
| 6031 ins_pipe(ialu_mem_reg); | |
| 6032 %} | |
| 6033 | |
|
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|
6034 instruct storeImmP0(memory mem, immP0 zero) |
|
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6035 %{ |
|
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|
6036 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
|
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6037 match(Set mem (StoreP mem zero)); |
|
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|
6038 |
|
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|
6039 ins_cost(125); // XXX |
|
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|
6040 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %} |
|
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6041 ins_encode %{ |
|
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|
6042 __ movq($mem$$Address, r12); |
|
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|
6043 %} |
|
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|
6044 ins_pipe(ialu_mem_reg); |
|
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|
6045 %} |
|
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|
6046 |
| 0 | 6047 // Store NULL Pointer, mark word, or other simple pointer constant. |
| 6048 instruct storeImmP(memory mem, immP31 src) | |
| 6049 %{ | |
| 6050 match(Set mem (StoreP mem src)); | |
| 6051 | |
|
642
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|
6052 ins_cost(150); // XXX |
| 0 | 6053 format %{ "movq $mem, $src\t# ptr" %} |
| 6054 opcode(0xC7); /* C7 /0 */ | |
| 6055 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); | |
| 6056 ins_pipe(ialu_mem_imm); | |
| 6057 %} | |
| 6058 | |
|
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|
6059 // Store Compressed Pointer |
| 163 | 6060 instruct storeN(memory mem, rRegN src) |
|
113
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6061 %{ |
|
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|
6062 match(Set mem (StoreN mem src)); |
|
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|
6063 |
|
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|
6064 ins_cost(125); // XXX |
|
164
c436414a719e
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|
6065 format %{ "movl $mem, $src\t# compressed ptr" %} |
|
113
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6066 ins_encode %{ |
|
642
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|
6067 __ movl($mem$$Address, $src$$Register); |
|
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|
6068 %} |
|
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|
6069 ins_pipe(ialu_mem_reg); |
|
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|
6070 %} |
|
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|
6071 |
|
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|
6072 instruct storeImmN0(memory mem, immN0 zero) |
|
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|
6073 %{ |
|
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|
6074 predicate(Universe::narrow_oop_base() == NULL); |
|
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|
6075 match(Set mem (StoreN mem zero)); |
|
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|
6076 |
|
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|
6077 ins_cost(125); // XXX |
|
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|
6078 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %} |
|
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|
6079 ins_encode %{ |
|
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|
6080 __ movl($mem$$Address, r12); |
|
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|
6081 %} |
|
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|
6082 ins_pipe(ialu_mem_reg); |
|
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|
6083 %} |
|
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|
6084 |
|
642
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|
6085 instruct storeImmN(memory mem, immN src) |
|
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|
6086 %{ |
|
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|
6087 match(Set mem (StoreN mem src)); |
|
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|
6088 |
|
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|
6089 ins_cost(150); // XXX |
|
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|
6090 format %{ "movl $mem, $src\t# compressed ptr" %} |
|
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|
6091 ins_encode %{ |
|
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|
6092 address con = (address)$src$$constant; |
|
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|
6093 if (con == NULL) { |
|
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|
6094 __ movl($mem$$Address, (int32_t)0); |
|
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|
6095 } else { |
|
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|
6096 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant); |
|
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6097 } |
|
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|
6098 %} |
|
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|
6099 ins_pipe(ialu_mem_imm); |
|
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|
6100 %} |
|
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6101 |
| 0 | 6102 // Store Integer Immediate |
|
642
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|
6103 instruct storeImmI0(memory mem, immI0 zero) |
|
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6104 %{ |
|
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|
6105 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
|
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|
6106 match(Set mem (StoreI mem zero)); |
|
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|
6107 |
|
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|
6108 ins_cost(125); // XXX |
|
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|
6109 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %} |
|
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|
6110 ins_encode %{ |
|
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|
6111 __ movl($mem$$Address, r12); |
|
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|
6112 %} |
|
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|
6113 ins_pipe(ialu_mem_reg); |
|
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|
6114 %} |
|
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6115 |
| 0 | 6116 instruct storeImmI(memory mem, immI src) |
| 6117 %{ | |
| 6118 match(Set mem (StoreI mem src)); | |
| 6119 | |
| 6120 ins_cost(150); | |
| 6121 format %{ "movl $mem, $src\t# int" %} | |
| 6122 opcode(0xC7); /* C7 /0 */ | |
| 6123 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); | |
| 6124 ins_pipe(ialu_mem_imm); | |
| 6125 %} | |
| 6126 | |
| 6127 // Store Long Immediate | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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624
diff
changeset
|
6128 instruct storeImmL0(memory mem, immL0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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624
diff
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|
6129 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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624
diff
changeset
|
6130 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
6131 match(Set mem (StoreL mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
6132 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
6133 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6134 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
6135 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6136 __ movq($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
6137 %} |
|
660978a2a31a
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kvn
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624
diff
changeset
|
6138 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
6139 %} |
|
660978a2a31a
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diff
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|
6140 |
| 0 | 6141 instruct storeImmL(memory mem, immL32 src) |
| 6142 %{ | |
| 6143 match(Set mem (StoreL mem src)); | |
| 6144 | |
| 6145 ins_cost(150); | |
| 6146 format %{ "movq $mem, $src\t# long" %} | |
| 6147 opcode(0xC7); /* C7 /0 */ | |
| 6148 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); | |
| 6149 ins_pipe(ialu_mem_imm); | |
| 6150 %} | |
| 6151 | |
| 6152 // Store Short/Char Immediate | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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624
diff
changeset
|
6153 instruct storeImmC0(memory mem, immI0 zero) |
|
660978a2a31a
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624
diff
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|
6154 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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624
diff
changeset
|
6155 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6156 match(Set mem (StoreC mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
6157 |
|
660978a2a31a
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kvn
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624
diff
changeset
|
6158 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
6159 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
6160 ins_encode %{ |
|
660978a2a31a
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kvn
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624
diff
changeset
|
6161 __ movw($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
6162 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6163 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6164 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
6165 |
| 0 | 6166 instruct storeImmI16(memory mem, immI16 src) |
| 6167 %{ | |
| 6168 predicate(UseStoreImmI16); | |
| 6169 match(Set mem (StoreC mem src)); | |
| 6170 | |
| 6171 ins_cost(150); | |
| 6172 format %{ "movw $mem, $src\t# short/char" %} | |
| 6173 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */ | |
| 6174 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src)); | |
| 6175 ins_pipe(ialu_mem_imm); | |
| 6176 %} | |
| 6177 | |
| 6178 // Store Byte Immediate | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6179 instruct storeImmB0(memory mem, immI0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
6180 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
6181 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
6182 match(Set mem (StoreB mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
6183 |
|
660978a2a31a
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kvn
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624
diff
changeset
|
6184 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
6185 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %} |
|
660978a2a31a
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kvn
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diff
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|
6186 ins_encode %{ |
|
660978a2a31a
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kvn
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624
diff
changeset
|
6187 __ movb($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
6188 %} |
|
660978a2a31a
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kvn
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624
diff
changeset
|
6189 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
6190 %} |
|
660978a2a31a
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kvn
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624
diff
changeset
|
6191 |
| 0 | 6192 instruct storeImmB(memory mem, immI8 src) |
| 6193 %{ | |
| 6194 match(Set mem (StoreB mem src)); | |
| 6195 | |
| 6196 ins_cost(150); // XXX | |
| 6197 format %{ "movb $mem, $src\t# byte" %} | |
| 6198 opcode(0xC6); /* C6 /0 */ | |
| 6199 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src)); | |
| 6200 ins_pipe(ialu_mem_imm); | |
| 6201 %} | |
| 6202 | |
| 6203 // Store Aligned Packed Byte XMM register to memory | |
| 6204 instruct storeA8B(memory mem, regD src) %{ | |
| 6205 match(Set mem (Store8B mem src)); | |
| 6206 ins_cost(145); | |
| 6207 format %{ "MOVQ $mem,$src\t! packed8B" %} | |
| 4759 | 6208 ins_encode %{ |
| 6209 __ movq($mem$$Address, $src$$XMMRegister); | |
| 6210 %} | |
| 0 | 6211 ins_pipe( pipe_slow ); |
| 6212 %} | |
| 6213 | |
| 6214 // Store Aligned Packed Char/Short XMM register to memory | |
| 6215 instruct storeA4C(memory mem, regD src) %{ | |
| 6216 match(Set mem (Store4C mem src)); | |
| 6217 ins_cost(145); | |
| 6218 format %{ "MOVQ $mem,$src\t! packed4C" %} | |
| 4759 | 6219 ins_encode %{ |
| 6220 __ movq($mem$$Address, $src$$XMMRegister); | |
| 6221 %} | |
| 0 | 6222 ins_pipe( pipe_slow ); |
| 6223 %} | |
| 6224 | |
| 6225 // Store Aligned Packed Integer XMM register to memory | |
| 6226 instruct storeA2I(memory mem, regD src) %{ | |
| 6227 match(Set mem (Store2I mem src)); | |
| 6228 ins_cost(145); | |
| 6229 format %{ "MOVQ $mem,$src\t! packed2I" %} | |
| 4759 | 6230 ins_encode %{ |
| 6231 __ movq($mem$$Address, $src$$XMMRegister); | |
| 6232 %} | |
| 0 | 6233 ins_pipe( pipe_slow ); |
| 6234 %} | |
| 6235 | |
| 6236 // Store CMS card-mark Immediate | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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624
diff
changeset
|
6237 instruct storeImmCM0_reg(memory mem, immI0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
6238 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
6239 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
6240 match(Set mem (StoreCM mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
6241 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
6242 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6243 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
6244 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6245 __ movb($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
6246 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
6247 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6248 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
6249 |
| 0 | 6250 instruct storeImmCM0(memory mem, immI0 src) |
| 6251 %{ | |
| 6252 match(Set mem (StoreCM mem src)); | |
| 6253 | |
| 6254 ins_cost(150); // XXX | |
| 6255 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %} | |
| 6256 opcode(0xC6); /* C6 /0 */ | |
| 6257 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src)); | |
| 6258 ins_pipe(ialu_mem_imm); | |
| 6259 %} | |
| 6260 | |
| 6261 // Store Aligned Packed Single Float XMM register to memory | |
| 6262 instruct storeA2F(memory mem, regD src) %{ | |
| 6263 match(Set mem (Store2F mem src)); | |
| 6264 ins_cost(145); | |
| 6265 format %{ "MOVQ $mem,$src\t! packed2F" %} | |
| 4759 | 6266 ins_encode %{ |
| 6267 __ movq($mem$$Address, $src$$XMMRegister); | |
| 6268 %} | |
| 0 | 6269 ins_pipe( pipe_slow ); |
| 6270 %} | |
| 6271 | |
| 6272 // Store Float | |
| 6273 instruct storeF(memory mem, regF src) | |
| 6274 %{ | |
| 6275 match(Set mem (StoreF mem src)); | |
| 6276 | |
| 6277 ins_cost(95); // XXX | |
| 6278 format %{ "movss $mem, $src\t# float" %} | |
| 4759 | 6279 ins_encode %{ |
| 6280 __ movflt($mem$$Address, $src$$XMMRegister); | |
| 6281 %} | |
| 0 | 6282 ins_pipe(pipe_slow); // XXX |
| 6283 %} | |
| 6284 | |
| 6285 // Store immediate Float value (it is faster than store from XMM register) | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6286 instruct storeF0(memory mem, immF0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
6287 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
6288 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6289 match(Set mem (StoreF mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6290 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6291 ins_cost(25); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6292 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6293 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
6294 __ movl($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6295 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
6296 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6297 %} |
|
660978a2a31a
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changeset
|
6298 |
| 0 | 6299 instruct storeF_imm(memory mem, immF src) |
| 6300 %{ | |
| 6301 match(Set mem (StoreF mem src)); | |
| 6302 | |
| 6303 ins_cost(50); | |
| 6304 format %{ "movl $mem, $src\t# float" %} | |
| 6305 opcode(0xC7); /* C7 /0 */ | |
| 6306 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src)); | |
| 6307 ins_pipe(ialu_mem_imm); | |
| 6308 %} | |
| 6309 | |
| 6310 // Store Double | |
| 6311 instruct storeD(memory mem, regD src) | |
| 6312 %{ | |
| 6313 match(Set mem (StoreD mem src)); | |
| 6314 | |
| 6315 ins_cost(95); // XXX | |
| 6316 format %{ "movsd $mem, $src\t# double" %} | |
| 4759 | 6317 ins_encode %{ |
| 6318 __ movdbl($mem$$Address, $src$$XMMRegister); | |
| 6319 %} | |
| 0 | 6320 ins_pipe(pipe_slow); // XXX |
| 6321 %} | |
| 6322 | |
| 6323 // Store immediate double 0.0 (it is faster than store from XMM register) | |
| 6324 instruct storeD0_imm(memory mem, immD0 src) | |
| 6325 %{ | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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624
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changeset
|
6326 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL)); |
| 0 | 6327 match(Set mem (StoreD mem src)); |
| 6328 | |
| 6329 ins_cost(50); | |
| 6330 format %{ "movq $mem, $src\t# double 0." %} | |
| 6331 opcode(0xC7); /* C7 /0 */ | |
| 6332 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src)); | |
| 6333 ins_pipe(ialu_mem_imm); | |
| 6334 %} | |
| 6335 | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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624
diff
changeset
|
6336 instruct storeD0(memory mem, immD0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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624
diff
changeset
|
6337 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
6338 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
|
660978a2a31a
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kvn
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624
diff
changeset
|
6339 match(Set mem (StoreD mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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diff
changeset
|
6340 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6341 ins_cost(25); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6342 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6343 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6344 __ movq($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6345 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
6346 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6347 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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changeset
|
6348 |
| 0 | 6349 instruct storeSSI(stackSlotI dst, rRegI src) |
| 6350 %{ | |
| 6351 match(Set dst src); | |
| 6352 | |
| 6353 ins_cost(100); | |
| 6354 format %{ "movl $dst, $src\t# int stk" %} | |
| 6355 opcode(0x89); | |
| 6356 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 6357 ins_pipe( ialu_mem_reg ); | |
| 6358 %} | |
| 6359 | |
| 6360 instruct storeSSL(stackSlotL dst, rRegL src) | |
| 6361 %{ | |
| 6362 match(Set dst src); | |
| 6363 | |
| 6364 ins_cost(100); | |
| 6365 format %{ "movq $dst, $src\t# long stk" %} | |
| 6366 opcode(0x89); | |
| 6367 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 6368 ins_pipe(ialu_mem_reg); | |
| 6369 %} | |
| 6370 | |
| 6371 instruct storeSSP(stackSlotP dst, rRegP src) | |
| 6372 %{ | |
| 6373 match(Set dst src); | |
| 6374 | |
| 6375 ins_cost(100); | |
| 6376 format %{ "movq $dst, $src\t# ptr stk" %} | |
| 6377 opcode(0x89); | |
| 6378 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 6379 ins_pipe(ialu_mem_reg); | |
| 6380 %} | |
| 6381 | |
| 6382 instruct storeSSF(stackSlotF dst, regF src) | |
| 6383 %{ | |
| 6384 match(Set dst src); | |
| 6385 | |
| 6386 ins_cost(95); // XXX | |
| 6387 format %{ "movss $dst, $src\t# float stk" %} | |
| 4759 | 6388 ins_encode %{ |
| 6389 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister); | |
| 6390 %} | |
| 0 | 6391 ins_pipe(pipe_slow); // XXX |
| 6392 %} | |
| 6393 | |
| 6394 instruct storeSSD(stackSlotD dst, regD src) | |
| 6395 %{ | |
| 6396 match(Set dst src); | |
| 6397 | |
| 6398 ins_cost(95); // XXX | |
| 6399 format %{ "movsd $dst, $src\t# double stk" %} | |
| 4759 | 6400 ins_encode %{ |
| 6401 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister); | |
| 6402 %} | |
| 0 | 6403 ins_pipe(pipe_slow); // XXX |
| 6404 %} | |
| 6405 | |
| 6406 //----------BSWAP Instructions------------------------------------------------- | |
| 6407 instruct bytes_reverse_int(rRegI dst) %{ | |
| 6408 match(Set dst (ReverseBytesI dst)); | |
| 6409 | |
| 6410 format %{ "bswapl $dst" %} | |
| 6411 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */ | |
| 6412 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) ); | |
| 6413 ins_pipe( ialu_reg ); | |
| 6414 %} | |
| 6415 | |
| 6416 instruct bytes_reverse_long(rRegL dst) %{ | |
| 6417 match(Set dst (ReverseBytesL dst)); | |
| 6418 | |
| 6419 format %{ "bswapq $dst" %} | |
| 6420 | |
| 6421 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */ | |
| 6422 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) ); | |
| 6423 ins_pipe( ialu_reg); | |
| 6424 %} | |
| 6425 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6426 instruct bytes_reverse_unsigned_short(rRegI dst) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6427 match(Set dst (ReverseBytesUS dst)); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6428 |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
6429 format %{ "bswapl $dst\n\t" |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6430 "shrl $dst,16\n\t" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6431 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6432 __ bswapl($dst$$Register); |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
6433 __ shrl($dst$$Register, 16); |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6434 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6435 ins_pipe( ialu_reg ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6436 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6437 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6438 instruct bytes_reverse_short(rRegI dst) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6439 match(Set dst (ReverseBytesS dst)); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6440 |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
6441 format %{ "bswapl $dst\n\t" |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6442 "sar $dst,16\n\t" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6443 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6444 __ bswapl($dst$$Register); |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
6445 __ sarl($dst$$Register, 16); |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6446 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6447 ins_pipe( ialu_reg ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6448 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6449 |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6450 //---------- Zeros Count Instructions ------------------------------------------ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6451 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6452 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6453 predicate(UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6454 match(Set dst (CountLeadingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6455 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6456 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6457 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6458 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6459 __ lzcntl($dst$$Register, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6460 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6461 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6462 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6463 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6464 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6465 predicate(!UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6466 match(Set dst (CountLeadingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6467 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6468 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6469 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6470 "jnz skip\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6471 "movl $dst, -1\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6472 "skip:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6473 "negl $dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6474 "addl $dst, 31" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6475 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6476 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6477 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6478 Label skip; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6479 __ bsrl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6480 __ jccb(Assembler::notZero, skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6481 __ movl(Rdst, -1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6482 __ bind(skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6483 __ negl(Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6484 __ addl(Rdst, BitsPerInt - 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6485 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6486 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6487 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6488 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6489 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6490 predicate(UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6491 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6492 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6493 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6494 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6495 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6496 __ lzcntq($dst$$Register, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6497 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6498 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6499 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6500 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6501 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6502 predicate(!UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6503 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6504 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6505 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6506 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6507 "jnz skip\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6508 "movl $dst, -1\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6509 "skip:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6510 "negl $dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6511 "addl $dst, 63" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6512 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6513 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6514 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6515 Label skip; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6516 __ bsrq(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6517 __ jccb(Assembler::notZero, skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6518 __ movl(Rdst, -1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6519 __ bind(skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6520 __ negl(Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6521 __ addl(Rdst, BitsPerLong - 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6522 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6523 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6524 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6525 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6526 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6527 match(Set dst (CountTrailingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6528 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6529 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6530 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6531 "jnz done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6532 "movl $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6533 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6534 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6535 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6536 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6537 __ bsfl(Rdst, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6538 __ jccb(Assembler::notZero, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6539 __ movl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6540 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6541 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6542 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6543 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6544 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6545 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6546 match(Set dst (CountTrailingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6547 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6548 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6549 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6550 "jnz done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6551 "movl $dst, 64\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6552 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6553 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6554 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6555 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6556 __ bsfq(Rdst, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6557 __ jccb(Assembler::notZero, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6558 __ movl(Rdst, BitsPerLong); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6559 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6560 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6561 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6562 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6563 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6564 |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6565 //---------- Population Count Instructions ------------------------------------- |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6566 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6567 instruct popCountI(rRegI dst, rRegI src) %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6568 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6569 match(Set dst (PopCountI src)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6570 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6571 format %{ "popcnt $dst, $src" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6572 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6573 __ popcntl($dst$$Register, $src$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6574 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6575 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6576 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6577 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6578 instruct popCountI_mem(rRegI dst, memory mem) %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6579 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6580 match(Set dst (PopCountI (LoadI mem))); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6581 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6582 format %{ "popcnt $dst, $mem" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6583 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6584 __ popcntl($dst$$Register, $mem$$Address); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6585 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6586 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6587 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6588 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6589 // Note: Long.bitCount(long) returns an int. |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6590 instruct popCountL(rRegI dst, rRegL src) %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6591 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6592 match(Set dst (PopCountL src)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6593 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6594 format %{ "popcnt $dst, $src" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6595 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6596 __ popcntq($dst$$Register, $src$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6597 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6598 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6599 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6600 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6601 // Note: Long.bitCount(long) returns an int. |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6602 instruct popCountL_mem(rRegI dst, memory mem) %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6603 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6604 match(Set dst (PopCountL (LoadL mem))); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6605 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6606 format %{ "popcnt $dst, $mem" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6607 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6608 __ popcntq($dst$$Register, $mem$$Address); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6609 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6610 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6611 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6612 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6613 |
| 0 | 6614 //----------MemBar Instructions----------------------------------------------- |
| 6615 // Memory barrier flavors | |
| 6616 | |
| 6617 instruct membar_acquire() | |
| 6618 %{ | |
| 6619 match(MemBarAcquire); | |
| 6620 ins_cost(0); | |
| 6621 | |
| 6622 size(0); | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6623 format %{ "MEMBAR-acquire ! (empty encoding)" %} |
| 0 | 6624 ins_encode(); |
| 6625 ins_pipe(empty); | |
| 6626 %} | |
| 6627 | |
| 6628 instruct membar_acquire_lock() | |
| 6629 %{ | |
|
3849
f1c12354c3f7
7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents:
3842
diff
changeset
|
6630 match(MemBarAcquireLock); |
| 0 | 6631 ins_cost(0); |
| 6632 | |
| 6633 size(0); | |
| 6634 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %} | |
| 6635 ins_encode(); | |
| 6636 ins_pipe(empty); | |
| 6637 %} | |
| 6638 | |
| 6639 instruct membar_release() | |
| 6640 %{ | |
| 6641 match(MemBarRelease); | |
| 6642 ins_cost(0); | |
| 6643 | |
| 6644 size(0); | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6645 format %{ "MEMBAR-release ! (empty encoding)" %} |
| 0 | 6646 ins_encode(); |
| 6647 ins_pipe(empty); | |
| 6648 %} | |
| 6649 | |
| 6650 instruct membar_release_lock() | |
| 6651 %{ | |
|
3849
f1c12354c3f7
7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents:
3842
diff
changeset
|
6652 match(MemBarReleaseLock); |
| 0 | 6653 ins_cost(0); |
| 6654 | |
| 6655 size(0); | |
| 6656 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %} | |
| 6657 ins_encode(); | |
| 6658 ins_pipe(empty); | |
| 6659 %} | |
| 6660 | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6661 instruct membar_volatile(rFlagsReg cr) %{ |
| 0 | 6662 match(MemBarVolatile); |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6663 effect(KILL cr); |
| 0 | 6664 ins_cost(400); |
| 6665 | |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
6666 format %{ |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6667 $$template |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6668 if (os::is_MP()) { |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6669 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile" |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6670 } else { |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6671 $$emit$$"MEMBAR-volatile ! (empty encoding)" |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6672 } |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6673 %} |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6674 ins_encode %{ |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6675 __ membar(Assembler::StoreLoad); |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6676 %} |
| 0 | 6677 ins_pipe(pipe_slow); |
| 6678 %} | |
| 6679 | |
| 6680 instruct unnecessary_membar_volatile() | |
| 6681 %{ | |
| 6682 match(MemBarVolatile); | |
| 6683 predicate(Matcher::post_store_load_barrier(n)); | |
| 6684 ins_cost(0); | |
| 6685 | |
| 6686 size(0); | |
| 6687 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %} | |
| 6688 ins_encode(); | |
| 6689 ins_pipe(empty); | |
| 6690 %} | |
| 6691 | |
|
4763
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
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diff
changeset
|
6692 instruct membar_storestore() %{ |
|
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diff
changeset
|
6693 match(MemBarStoreStore); |
|
1dc233a8c7fe
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4762
diff
changeset
|
6694 ins_cost(0); |
|
1dc233a8c7fe
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4762
diff
changeset
|
6695 |
|
1dc233a8c7fe
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4762
diff
changeset
|
6696 size(0); |
|
1dc233a8c7fe
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parents:
4762
diff
changeset
|
6697 format %{ "MEMBAR-storestore (empty encoding)" %} |
|
1dc233a8c7fe
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roland
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4762
diff
changeset
|
6698 ins_encode( ); |
|
1dc233a8c7fe
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parents:
4762
diff
changeset
|
6699 ins_pipe(empty); |
|
1dc233a8c7fe
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4762
diff
changeset
|
6700 %} |
|
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diff
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|
6701 |
| 0 | 6702 //----------Move Instructions-------------------------------------------------- |
| 6703 | |
| 6704 instruct castX2P(rRegP dst, rRegL src) | |
| 6705 %{ | |
| 6706 match(Set dst (CastX2P src)); | |
| 6707 | |
| 6708 format %{ "movq $dst, $src\t# long->ptr" %} | |
| 4759 | 6709 ins_encode %{ |
| 6710 if ($dst$$reg != $src$$reg) { | |
| 6711 __ movptr($dst$$Register, $src$$Register); | |
| 6712 } | |
| 6713 %} | |
| 0 | 6714 ins_pipe(ialu_reg_reg); // XXX |
| 6715 %} | |
| 6716 | |
| 6717 instruct castP2X(rRegL dst, rRegP src) | |
| 6718 %{ | |
| 6719 match(Set dst (CastP2X src)); | |
| 6720 | |
| 6721 format %{ "movq $dst, $src\t# ptr -> long" %} | |
| 4759 | 6722 ins_encode %{ |
| 6723 if ($dst$$reg != $src$$reg) { | |
| 6724 __ movptr($dst$$Register, $src$$Register); | |
| 6725 } | |
| 6726 %} | |
| 0 | 6727 ins_pipe(ialu_reg_reg); // XXX |
| 6728 %} | |
| 6729 | |
|
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|
6730 |
|
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changeset
|
6731 // Convert oop pointer into compressed form |
|
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|
6732 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{ |
|
221
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|
6733 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); |
|
113
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|
6734 match(Set dst (EncodeP src)); |
|
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|
6735 effect(KILL cr); |
|
ba764ed4b6f2
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|
6736 format %{ "encode_heap_oop $dst,$src" %} |
|
ba764ed4b6f2
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|
6737 ins_encode %{ |
|
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changeset
|
6738 Register s = $src$$Register; |
|
ba764ed4b6f2
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diff
changeset
|
6739 Register d = $dst$$Register; |
|
ba764ed4b6f2
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71
diff
changeset
|
6740 if (s != d) { |
|
ba764ed4b6f2
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changeset
|
6741 __ movq(d, s); |
|
ba764ed4b6f2
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|
6742 } |
|
ba764ed4b6f2
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changeset
|
6743 __ encode_heap_oop(d); |
|
ba764ed4b6f2
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|
6744 %} |
|
ba764ed4b6f2
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diff
changeset
|
6745 ins_pipe(ialu_reg_long); |
|
ba764ed4b6f2
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|
6746 %} |
|
ba764ed4b6f2
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changeset
|
6747 |
|
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|
6748 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{ |
|
221
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|
6749 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); |
|
124
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|
6750 match(Set dst (EncodeP src)); |
|
b130b98db9cf
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kvn
parents:
113
diff
changeset
|
6751 effect(KILL cr); |
|
b130b98db9cf
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parents:
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diff
changeset
|
6752 format %{ "encode_heap_oop_not_null $dst,$src" %} |
|
b130b98db9cf
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diff
changeset
|
6753 ins_encode %{ |
|
642
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changeset
|
6754 __ encode_heap_oop_not_null($dst$$Register, $src$$Register); |
|
124
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|
6755 %} |
|
b130b98db9cf
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113
diff
changeset
|
6756 ins_pipe(ialu_reg_long); |
|
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kvn
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diff
changeset
|
6757 %} |
|
b130b98db9cf
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113
diff
changeset
|
6758 |
|
113
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diff
changeset
|
6759 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{ |
|
182
44abbb0d4c18
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|
6760 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && |
|
44abbb0d4c18
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diff
changeset
|
6761 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant); |
|
113
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changeset
|
6762 match(Set dst (DecodeN src)); |
|
ba764ed4b6f2
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71
diff
changeset
|
6763 effect(KILL cr); |
|
ba764ed4b6f2
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71
diff
changeset
|
6764 format %{ "decode_heap_oop $dst,$src" %} |
|
ba764ed4b6f2
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changeset
|
6765 ins_encode %{ |
|
ba764ed4b6f2
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diff
changeset
|
6766 Register s = $src$$Register; |
|
ba764ed4b6f2
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71
diff
changeset
|
6767 Register d = $dst$$Register; |
|
ba764ed4b6f2
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71
diff
changeset
|
6768 if (s != d) { |
|
ba764ed4b6f2
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71
diff
changeset
|
6769 __ movq(d, s); |
|
ba764ed4b6f2
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71
diff
changeset
|
6770 } |
|
ba764ed4b6f2
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71
diff
changeset
|
6771 __ decode_heap_oop(d); |
|
ba764ed4b6f2
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71
diff
changeset
|
6772 %} |
|
ba764ed4b6f2
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71
diff
changeset
|
6773 ins_pipe(ialu_reg_long); |
|
ba764ed4b6f2
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71
diff
changeset
|
6774 %} |
|
ba764ed4b6f2
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71
diff
changeset
|
6775 |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1567
diff
changeset
|
6776 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{ |
|
182
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169
diff
changeset
|
6777 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || |
|
44abbb0d4c18
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kvn
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169
diff
changeset
|
6778 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant); |
|
124
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kvn
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113
diff
changeset
|
6779 match(Set dst (DecodeN src)); |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1567
diff
changeset
|
6780 effect(KILL cr); |
|
124
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diff
changeset
|
6781 format %{ "decode_heap_oop_not_null $dst,$src" %} |
|
b130b98db9cf
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113
diff
changeset
|
6782 ins_encode %{ |
|
b130b98db9cf
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113
diff
changeset
|
6783 Register s = $src$$Register; |
|
b130b98db9cf
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113
diff
changeset
|
6784 Register d = $dst$$Register; |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6785 if (s != d) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6786 __ decode_heap_oop_not_null(d, s); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
6787 } else { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6788 __ decode_heap_oop_not_null(d); |
|
660978a2a31a
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624
diff
changeset
|
6789 } |
|
124
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113
diff
changeset
|
6790 %} |
|
b130b98db9cf
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113
diff
changeset
|
6791 ins_pipe(ialu_reg_long); |
|
b130b98db9cf
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kvn
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113
diff
changeset
|
6792 %} |
|
b130b98db9cf
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113
diff
changeset
|
6793 |
|
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|
6794 |
| 0 | 6795 //----------Conditional Move--------------------------------------------------- |
| 6796 // Jump | |
| 6797 // dummy instruction for generating temp registers | |
| 6798 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{ | |
| 6799 match(Jump (LShiftL switch_val shift)); | |
| 6800 ins_cost(350); | |
| 6801 predicate(false); | |
| 6802 effect(TEMP dest); | |
| 6803 | |
| 2008 | 6804 format %{ "leaq $dest, [$constantaddress]\n\t" |
| 0 | 6805 "jmp [$dest + $switch_val << $shift]\n\t" %} |
| 2008 | 6806 ins_encode %{ |
| 6807 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10 | |
| 6808 // to do that and the compiler is using that register as one it can allocate. | |
| 6809 // So we build it all by hand. | |
| 6810 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant); | |
| 6811 // ArrayAddress dispatch(table, index); | |
| 6812 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant); | |
| 6813 __ lea($dest$$Register, $constantaddress); | |
| 6814 __ jmp(dispatch); | |
| 6815 %} | |
| 0 | 6816 ins_pipe(pipe_jmp); |
| 6817 %} | |
| 6818 | |
| 6819 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{ | |
| 6820 match(Jump (AddL (LShiftL switch_val shift) offset)); | |
| 6821 ins_cost(350); | |
| 6822 effect(TEMP dest); | |
| 6823 | |
| 2008 | 6824 format %{ "leaq $dest, [$constantaddress]\n\t" |
| 0 | 6825 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %} |
| 2008 | 6826 ins_encode %{ |
| 6827 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10 | |
| 6828 // to do that and the compiler is using that register as one it can allocate. | |
| 6829 // So we build it all by hand. | |
| 6830 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant); | |
| 6831 // ArrayAddress dispatch(table, index); | |
| 6832 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant); | |
| 6833 __ lea($dest$$Register, $constantaddress); | |
| 6834 __ jmp(dispatch); | |
| 6835 %} | |
| 0 | 6836 ins_pipe(pipe_jmp); |
| 6837 %} | |
| 6838 | |
| 6839 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{ | |
| 6840 match(Jump switch_val); | |
| 6841 ins_cost(350); | |
| 6842 effect(TEMP dest); | |
| 6843 | |
| 2008 | 6844 format %{ "leaq $dest, [$constantaddress]\n\t" |
| 0 | 6845 "jmp [$dest + $switch_val]\n\t" %} |
| 2008 | 6846 ins_encode %{ |
| 6847 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10 | |
| 6848 // to do that and the compiler is using that register as one it can allocate. | |
| 6849 // So we build it all by hand. | |
| 6850 // Address index(noreg, switch_reg, Address::times_1); | |
| 6851 // ArrayAddress dispatch(table, index); | |
| 6852 Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1); | |
| 6853 __ lea($dest$$Register, $constantaddress); | |
| 6854 __ jmp(dispatch); | |
| 6855 %} | |
| 0 | 6856 ins_pipe(pipe_jmp); |
| 6857 %} | |
| 6858 | |
| 6859 // Conditional move | |
| 6860 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop) | |
| 6861 %{ | |
| 6862 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 6863 | |
| 6864 ins_cost(200); // XXX | |
| 6865 format %{ "cmovl$cop $dst, $src\t# signed, int" %} | |
| 6866 opcode(0x0F, 0x40); | |
| 6867 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 6868 ins_pipe(pipe_cmov_reg); | |
| 6869 %} | |
| 6870 | |
|
415
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403
diff
changeset
|
6871 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{ |
| 0 | 6872 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); |
| 6873 | |
| 6874 ins_cost(200); // XXX | |
| 6875 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %} | |
| 6876 opcode(0x0F, 0x40); | |
| 6877 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 6878 ins_pipe(pipe_cmov_reg); | |
| 6879 %} | |
| 6880 | |
|
415
4d9884b01ba6
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never
parents:
403
diff
changeset
|
6881 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6882 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6883 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6884 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6885 cmovI_regU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6886 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6887 %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
6888 |
| 0 | 6889 // Conditional move |
|
415
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6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6890 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{ |
| 0 | 6891 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); |
| 6892 | |
| 6893 ins_cost(250); // XXX | |
| 6894 format %{ "cmovl$cop $dst, $src\t# signed, int" %} | |
| 6895 opcode(0x0F, 0x40); | |
| 6896 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
| 6897 ins_pipe(pipe_cmov_mem); | |
| 6898 %} | |
| 6899 | |
| 6900 // Conditional move | |
| 6901 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src) | |
| 6902 %{ | |
| 6903 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); | |
| 6904 | |
| 6905 ins_cost(250); // XXX | |
| 6906 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %} | |
| 6907 opcode(0x0F, 0x40); | |
| 6908 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
| 6909 ins_pipe(pipe_cmov_mem); | |
| 6910 %} | |
| 6911 | |
|
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|
6912 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{ |
|
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|
6913 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); |
|
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diff
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|
6914 ins_cost(250); |
|
4d9884b01ba6
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diff
changeset
|
6915 expand %{ |
|
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diff
changeset
|
6916 cmovI_memU(cop, cr, dst, src); |
|
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diff
changeset
|
6917 %} |
|
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never
parents:
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diff
changeset
|
6918 %} |
|
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diff
changeset
|
6919 |
| 0 | 6920 // Conditional move |
|
164
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|
6921 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop) |
|
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|
6922 %{ |
|
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|
6923 match(Set dst (CMoveN (Binary cop cr) (Binary dst src))); |
|
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|
6924 |
|
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|
6925 ins_cost(200); // XXX |
|
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|
6926 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %} |
|
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|
6927 opcode(0x0F, 0x40); |
|
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|
6928 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); |
|
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changeset
|
6929 ins_pipe(pipe_cmov_reg); |
|
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changeset
|
6930 %} |
|
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changeset
|
6931 |
|
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changeset
|
6932 // Conditional move |
|
415
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|
6933 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src) |
|
164
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changeset
|
6934 %{ |
|
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|
6935 match(Set dst (CMoveN (Binary cop cr) (Binary dst src))); |
|
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|
6936 |
|
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changeset
|
6937 ins_cost(200); // XXX |
|
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|
6938 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %} |
|
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|
6939 opcode(0x0F, 0x40); |
|
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kvn
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changeset
|
6940 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); |
|
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changeset
|
6941 ins_pipe(pipe_cmov_reg); |
|
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changeset
|
6942 %} |
|
c436414a719e
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163
diff
changeset
|
6943 |
|
415
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never
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changeset
|
6944 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{ |
|
4d9884b01ba6
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diff
changeset
|
6945 match(Set dst (CMoveN (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
6946 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6947 expand %{ |
|
4d9884b01ba6
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403
diff
changeset
|
6948 cmovN_regU(cop, cr, dst, src); |
|
4d9884b01ba6
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never
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403
diff
changeset
|
6949 %} |
|
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never
parents:
403
diff
changeset
|
6950 %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
6951 |
|
164
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|
6952 // Conditional move |
| 0 | 6953 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop) |
| 6954 %{ | |
| 6955 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 6956 | |
| 6957 ins_cost(200); // XXX | |
| 6958 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %} | |
| 6959 opcode(0x0F, 0x40); | |
| 6960 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 6961 ins_pipe(pipe_cmov_reg); // XXX | |
| 6962 %} | |
| 6963 | |
| 6964 // Conditional move | |
|
415
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diff
changeset
|
6965 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src) |
| 0 | 6966 %{ |
| 6967 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 6968 | |
| 6969 ins_cost(200); // XXX | |
| 6970 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %} | |
| 6971 opcode(0x0F, 0x40); | |
| 6972 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 6973 ins_pipe(pipe_cmov_reg); // XXX | |
| 6974 %} | |
| 6975 | |
|
415
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never
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diff
changeset
|
6976 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{ |
|
4d9884b01ba6
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diff
changeset
|
6977 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6978 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6979 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
6980 cmovP_regU(cop, cr, dst, src); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
6981 %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
6982 %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
6983 |
| 0 | 6984 // DISABLED: Requires the ADLC to emit a bottom_type call that |
| 6985 // correctly meets the two pointer arguments; one is an incoming | |
| 6986 // register but the other is a memory operand. ALSO appears to | |
| 6987 // be buggy with implicit null checks. | |
| 6988 // | |
| 6989 //// Conditional move | |
| 6990 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src) | |
| 6991 //%{ | |
| 6992 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 6993 // ins_cost(250); | |
| 6994 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 6995 // opcode(0x0F,0x40); | |
| 6996 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) ); | |
| 6997 // ins_pipe( pipe_cmov_mem ); | |
| 6998 //%} | |
| 6999 // | |
| 7000 //// Conditional move | |
| 7001 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src) | |
| 7002 //%{ | |
| 7003 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 7004 // ins_cost(250); | |
| 7005 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 7006 // opcode(0x0F,0x40); | |
| 7007 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) ); | |
| 7008 // ins_pipe( pipe_cmov_mem ); | |
| 7009 //%} | |
| 7010 | |
| 7011 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src) | |
| 7012 %{ | |
| 7013 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 7014 | |
| 7015 ins_cost(200); // XXX | |
| 7016 format %{ "cmovq$cop $dst, $src\t# signed, long" %} | |
| 7017 opcode(0x0F, 0x40); | |
| 7018 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 7019 ins_pipe(pipe_cmov_reg); // XXX | |
| 7020 %} | |
| 7021 | |
| 7022 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src) | |
| 7023 %{ | |
| 7024 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src)))); | |
| 7025 | |
| 7026 ins_cost(200); // XXX | |
| 7027 format %{ "cmovq$cop $dst, $src\t# signed, long" %} | |
| 7028 opcode(0x0F, 0x40); | |
| 7029 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
| 7030 ins_pipe(pipe_cmov_mem); // XXX | |
| 7031 %} | |
| 7032 | |
| 7033 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src) | |
| 7034 %{ | |
| 7035 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 7036 | |
| 7037 ins_cost(200); // XXX | |
| 7038 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %} | |
| 7039 opcode(0x0F, 0x40); | |
| 7040 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 7041 ins_pipe(pipe_cmov_reg); // XXX | |
| 7042 %} | |
| 7043 | |
|
415
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changeset
|
7044 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{ |
|
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403
diff
changeset
|
7045 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7046 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7047 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7048 cmovL_regU(cop, cr, dst, src); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7049 %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7050 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7051 |
| 0 | 7052 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src) |
| 7053 %{ | |
| 7054 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src)))); | |
| 7055 | |
| 7056 ins_cost(200); // XXX | |
| 7057 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %} | |
| 7058 opcode(0x0F, 0x40); | |
| 7059 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
| 7060 ins_pipe(pipe_cmov_mem); // XXX | |
| 7061 %} | |
| 7062 | |
|
415
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changeset
|
7063 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{ |
|
4d9884b01ba6
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diff
changeset
|
7064 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src)))); |
|
4d9884b01ba6
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diff
changeset
|
7065 ins_cost(200); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7066 expand %{ |
|
4d9884b01ba6
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403
diff
changeset
|
7067 cmovL_memU(cop, cr, dst, src); |
|
4d9884b01ba6
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403
diff
changeset
|
7068 %} |
|
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parents:
403
diff
changeset
|
7069 %} |
|
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parents:
403
diff
changeset
|
7070 |
| 0 | 7071 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src) |
| 7072 %{ | |
| 7073 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 7074 | |
| 7075 ins_cost(200); // XXX | |
| 7076 format %{ "jn$cop skip\t# signed cmove float\n\t" | |
| 7077 "movss $dst, $src\n" | |
| 7078 "skip:" %} | |
| 4759 | 7079 ins_encode %{ |
| 7080 Label Lskip; | |
| 7081 // Invert sense of branch from sense of CMOV | |
| 7082 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
| 7083 __ movflt($dst$$XMMRegister, $src$$XMMRegister); | |
| 7084 __ bind(Lskip); | |
| 7085 %} | |
| 0 | 7086 ins_pipe(pipe_slow); |
| 7087 %} | |
| 7088 | |
| 7089 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src) | |
| 7090 // %{ | |
| 7091 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src)))); | |
| 7092 | |
| 7093 // ins_cost(200); // XXX | |
| 7094 // format %{ "jn$cop skip\t# signed cmove float\n\t" | |
| 7095 // "movss $dst, $src\n" | |
| 7096 // "skip:" %} | |
| 7097 // ins_encode(enc_cmovf_mem_branch(cop, dst, src)); | |
| 7098 // ins_pipe(pipe_slow); | |
| 7099 // %} | |
| 7100 | |
| 7101 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src) | |
| 7102 %{ | |
| 7103 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 7104 | |
| 7105 ins_cost(200); // XXX | |
| 7106 format %{ "jn$cop skip\t# unsigned cmove float\n\t" | |
| 7107 "movss $dst, $src\n" | |
| 7108 "skip:" %} | |
| 4759 | 7109 ins_encode %{ |
| 7110 Label Lskip; | |
| 7111 // Invert sense of branch from sense of CMOV | |
| 7112 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
| 7113 __ movflt($dst$$XMMRegister, $src$$XMMRegister); | |
| 7114 __ bind(Lskip); | |
| 7115 %} | |
| 0 | 7116 ins_pipe(pipe_slow); |
| 7117 %} | |
| 7118 | |
|
415
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diff
changeset
|
7119 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{ |
|
4d9884b01ba6
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diff
changeset
|
7120 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
7121 ins_cost(200); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7122 expand %{ |
|
4d9884b01ba6
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diff
changeset
|
7123 cmovF_regU(cop, cr, dst, src); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7124 %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7125 %} |
|
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never
parents:
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diff
changeset
|
7126 |
| 0 | 7127 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src) |
| 7128 %{ | |
| 7129 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 7130 | |
| 7131 ins_cost(200); // XXX | |
| 7132 format %{ "jn$cop skip\t# signed cmove double\n\t" | |
| 7133 "movsd $dst, $src\n" | |
| 7134 "skip:" %} | |
| 4759 | 7135 ins_encode %{ |
| 7136 Label Lskip; | |
| 7137 // Invert sense of branch from sense of CMOV | |
| 7138 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
| 7139 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); | |
| 7140 __ bind(Lskip); | |
| 7141 %} | |
| 0 | 7142 ins_pipe(pipe_slow); |
| 7143 %} | |
| 7144 | |
| 7145 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src) | |
| 7146 %{ | |
| 7147 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 7148 | |
| 7149 ins_cost(200); // XXX | |
| 7150 format %{ "jn$cop skip\t# unsigned cmove double\n\t" | |
| 7151 "movsd $dst, $src\n" | |
| 7152 "skip:" %} | |
| 4759 | 7153 ins_encode %{ |
| 7154 Label Lskip; | |
| 7155 // Invert sense of branch from sense of CMOV | |
| 7156 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
| 7157 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); | |
| 7158 __ bind(Lskip); | |
| 7159 %} | |
| 0 | 7160 ins_pipe(pipe_slow); |
| 7161 %} | |
| 7162 | |
|
415
4d9884b01ba6
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diff
changeset
|
7163 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{ |
|
4d9884b01ba6
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diff
changeset
|
7164 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
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parents:
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diff
changeset
|
7165 ins_cost(200); |
|
4d9884b01ba6
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diff
changeset
|
7166 expand %{ |
|
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diff
changeset
|
7167 cmovD_regU(cop, cr, dst, src); |
|
4d9884b01ba6
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parents:
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diff
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|
7168 %} |
|
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diff
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|
7169 %} |
|
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|
7170 |
| 0 | 7171 //----------Arithmetic Instructions-------------------------------------------- |
| 7172 //----------Addition Instructions---------------------------------------------- | |
| 7173 | |
| 7174 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 7175 %{ | |
| 7176 match(Set dst (AddI dst src)); | |
| 7177 effect(KILL cr); | |
| 7178 | |
| 7179 format %{ "addl $dst, $src\t# int" %} | |
| 7180 opcode(0x03); | |
| 7181 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 7182 ins_pipe(ialu_reg_reg); | |
| 7183 %} | |
| 7184 | |
| 7185 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 7186 %{ | |
| 7187 match(Set dst (AddI dst src)); | |
| 7188 effect(KILL cr); | |
| 7189 | |
| 7190 format %{ "addl $dst, $src\t# int" %} | |
| 7191 opcode(0x81, 0x00); /* /0 id */ | |
| 7192 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 7193 ins_pipe( ialu_reg ); | |
| 7194 %} | |
| 7195 | |
| 7196 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 7197 %{ | |
| 7198 match(Set dst (AddI dst (LoadI src))); | |
| 7199 effect(KILL cr); | |
| 7200 | |
| 7201 ins_cost(125); // XXX | |
| 7202 format %{ "addl $dst, $src\t# int" %} | |
| 7203 opcode(0x03); | |
| 7204 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 7205 ins_pipe(ialu_reg_mem); | |
| 7206 %} | |
| 7207 | |
| 7208 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 7209 %{ | |
| 7210 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7211 effect(KILL cr); | |
| 7212 | |
| 7213 ins_cost(150); // XXX | |
| 7214 format %{ "addl $dst, $src\t# int" %} | |
| 7215 opcode(0x01); /* Opcode 01 /r */ | |
| 7216 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 7217 ins_pipe(ialu_mem_reg); | |
| 7218 %} | |
| 7219 | |
| 7220 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 7221 %{ | |
| 7222 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7223 effect(KILL cr); | |
| 7224 | |
| 7225 ins_cost(125); // XXX | |
| 7226 format %{ "addl $dst, $src\t# int" %} | |
| 7227 opcode(0x81); /* Opcode 81 /0 id */ | |
| 7228 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src)); | |
| 7229 ins_pipe(ialu_mem_imm); | |
| 7230 %} | |
| 7231 | |
| 7232 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr) | |
| 7233 %{ | |
| 7234 predicate(UseIncDec); | |
| 7235 match(Set dst (AddI dst src)); | |
| 7236 effect(KILL cr); | |
| 7237 | |
| 7238 format %{ "incl $dst\t# int" %} | |
| 7239 opcode(0xFF, 0x00); // FF /0 | |
| 7240 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 7241 ins_pipe(ialu_reg); | |
| 7242 %} | |
| 7243 | |
| 7244 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr) | |
| 7245 %{ | |
| 7246 predicate(UseIncDec); | |
| 7247 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7248 effect(KILL cr); | |
| 7249 | |
| 7250 ins_cost(125); // XXX | |
| 7251 format %{ "incl $dst\t# int" %} | |
| 7252 opcode(0xFF); /* Opcode FF /0 */ | |
| 7253 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst)); | |
| 7254 ins_pipe(ialu_mem_imm); | |
| 7255 %} | |
| 7256 | |
| 7257 // XXX why does that use AddI | |
| 7258 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr) | |
| 7259 %{ | |
| 7260 predicate(UseIncDec); | |
| 7261 match(Set dst (AddI dst src)); | |
| 7262 effect(KILL cr); | |
| 7263 | |
| 7264 format %{ "decl $dst\t# int" %} | |
| 7265 opcode(0xFF, 0x01); // FF /1 | |
| 7266 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 7267 ins_pipe(ialu_reg); | |
| 7268 %} | |
| 7269 | |
| 7270 // XXX why does that use AddI | |
| 7271 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr) | |
| 7272 %{ | |
| 7273 predicate(UseIncDec); | |
| 7274 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7275 effect(KILL cr); | |
| 7276 | |
| 7277 ins_cost(125); // XXX | |
| 7278 format %{ "decl $dst\t# int" %} | |
| 7279 opcode(0xFF); /* Opcode FF /1 */ | |
| 7280 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst)); | |
| 7281 ins_pipe(ialu_mem_imm); | |
| 7282 %} | |
| 7283 | |
| 7284 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1) | |
| 7285 %{ | |
| 7286 match(Set dst (AddI src0 src1)); | |
| 7287 | |
| 7288 ins_cost(110); | |
| 7289 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %} | |
| 7290 opcode(0x8D); /* 0x8D /r */ | |
| 7291 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX | |
| 7292 ins_pipe(ialu_reg_reg); | |
| 7293 %} | |
| 7294 | |
| 7295 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 7296 %{ | |
| 7297 match(Set dst (AddL dst src)); | |
| 7298 effect(KILL cr); | |
| 7299 | |
| 7300 format %{ "addq $dst, $src\t# long" %} | |
| 7301 opcode(0x03); | |
| 7302 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 7303 ins_pipe(ialu_reg_reg); | |
| 7304 %} | |
| 7305 | |
| 7306 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
| 7307 %{ | |
| 7308 match(Set dst (AddL dst src)); | |
| 7309 effect(KILL cr); | |
| 7310 | |
| 7311 format %{ "addq $dst, $src\t# long" %} | |
| 7312 opcode(0x81, 0x00); /* /0 id */ | |
| 7313 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 7314 ins_pipe( ialu_reg ); | |
| 7315 %} | |
| 7316 | |
| 7317 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 7318 %{ | |
| 7319 match(Set dst (AddL dst (LoadL src))); | |
| 7320 effect(KILL cr); | |
| 7321 | |
| 7322 ins_cost(125); // XXX | |
| 7323 format %{ "addq $dst, $src\t# long" %} | |
| 7324 opcode(0x03); | |
| 7325 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 7326 ins_pipe(ialu_reg_mem); | |
| 7327 %} | |
| 7328 | |
| 7329 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 7330 %{ | |
| 7331 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
| 7332 effect(KILL cr); | |
| 7333 | |
| 7334 ins_cost(150); // XXX | |
| 7335 format %{ "addq $dst, $src\t# long" %} | |
| 7336 opcode(0x01); /* Opcode 01 /r */ | |
| 7337 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 7338 ins_pipe(ialu_mem_reg); | |
| 7339 %} | |
| 7340 | |
| 7341 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 7342 %{ | |
| 7343 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
| 7344 effect(KILL cr); | |
| 7345 | |
| 7346 ins_cost(125); // XXX | |
| 7347 format %{ "addq $dst, $src\t# long" %} | |
| 7348 opcode(0x81); /* Opcode 81 /0 id */ | |
| 7349 ins_encode(REX_mem_wide(dst), | |
| 7350 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src)); | |
| 7351 ins_pipe(ialu_mem_imm); | |
| 7352 %} | |
| 7353 | |
| 7354 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr) | |
| 7355 %{ | |
| 7356 predicate(UseIncDec); | |
| 7357 match(Set dst (AddL dst src)); | |
| 7358 effect(KILL cr); | |
| 7359 | |
| 7360 format %{ "incq $dst\t# long" %} | |
| 7361 opcode(0xFF, 0x00); // FF /0 | |
| 7362 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 7363 ins_pipe(ialu_reg); | |
| 7364 %} | |
| 7365 | |
| 7366 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr) | |
| 7367 %{ | |
| 7368 predicate(UseIncDec); | |
| 7369 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
| 7370 effect(KILL cr); | |
| 7371 | |
| 7372 ins_cost(125); // XXX | |
| 7373 format %{ "incq $dst\t# long" %} | |
| 7374 opcode(0xFF); /* Opcode FF /0 */ | |
| 7375 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst)); | |
| 7376 ins_pipe(ialu_mem_imm); | |
| 7377 %} | |
| 7378 | |
| 7379 // XXX why does that use AddL | |
| 7380 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr) | |
| 7381 %{ | |
| 7382 predicate(UseIncDec); | |
| 7383 match(Set dst (AddL dst src)); | |
| 7384 effect(KILL cr); | |
| 7385 | |
| 7386 format %{ "decq $dst\t# long" %} | |
| 7387 opcode(0xFF, 0x01); // FF /1 | |
| 7388 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 7389 ins_pipe(ialu_reg); | |
| 7390 %} | |
| 7391 | |
| 7392 // XXX why does that use AddL | |
| 7393 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr) | |
| 7394 %{ | |
| 7395 predicate(UseIncDec); | |
| 7396 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
| 7397 effect(KILL cr); | |
| 7398 | |
| 7399 ins_cost(125); // XXX | |
| 7400 format %{ "decq $dst\t# long" %} | |
| 7401 opcode(0xFF); /* Opcode FF /1 */ | |
| 7402 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst)); | |
| 7403 ins_pipe(ialu_mem_imm); | |
| 7404 %} | |
| 7405 | |
| 7406 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1) | |
| 7407 %{ | |
| 7408 match(Set dst (AddL src0 src1)); | |
| 7409 | |
| 7410 ins_cost(110); | |
| 7411 format %{ "leaq $dst, [$src0 + $src1]\t# long" %} | |
| 7412 opcode(0x8D); /* 0x8D /r */ | |
| 7413 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX | |
| 7414 ins_pipe(ialu_reg_reg); | |
| 7415 %} | |
| 7416 | |
| 7417 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr) | |
| 7418 %{ | |
| 7419 match(Set dst (AddP dst src)); | |
| 7420 effect(KILL cr); | |
| 7421 | |
| 7422 format %{ "addq $dst, $src\t# ptr" %} | |
| 7423 opcode(0x03); | |
| 7424 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 7425 ins_pipe(ialu_reg_reg); | |
| 7426 %} | |
| 7427 | |
| 7428 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr) | |
| 7429 %{ | |
| 7430 match(Set dst (AddP dst src)); | |
| 7431 effect(KILL cr); | |
| 7432 | |
| 7433 format %{ "addq $dst, $src\t# ptr" %} | |
| 7434 opcode(0x81, 0x00); /* /0 id */ | |
| 7435 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 7436 ins_pipe( ialu_reg ); | |
| 7437 %} | |
| 7438 | |
| 7439 // XXX addP mem ops ???? | |
| 7440 | |
| 7441 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1) | |
| 7442 %{ | |
| 7443 match(Set dst (AddP src0 src1)); | |
| 7444 | |
| 7445 ins_cost(110); | |
| 7446 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %} | |
| 7447 opcode(0x8D); /* 0x8D /r */ | |
| 7448 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX | |
| 7449 ins_pipe(ialu_reg_reg); | |
| 7450 %} | |
| 7451 | |
| 7452 instruct checkCastPP(rRegP dst) | |
| 7453 %{ | |
| 7454 match(Set dst (CheckCastPP dst)); | |
| 7455 | |
| 7456 size(0); | |
| 7457 format %{ "# checkcastPP of $dst" %} | |
| 7458 ins_encode(/* empty encoding */); | |
| 7459 ins_pipe(empty); | |
| 7460 %} | |
| 7461 | |
| 7462 instruct castPP(rRegP dst) | |
| 7463 %{ | |
| 7464 match(Set dst (CastPP dst)); | |
| 7465 | |
| 7466 size(0); | |
| 7467 format %{ "# castPP of $dst" %} | |
| 7468 ins_encode(/* empty encoding */); | |
| 7469 ins_pipe(empty); | |
| 7470 %} | |
| 7471 | |
| 7472 instruct castII(rRegI dst) | |
| 7473 %{ | |
| 7474 match(Set dst (CastII dst)); | |
| 7475 | |
| 7476 size(0); | |
| 7477 format %{ "# castII of $dst" %} | |
| 7478 ins_encode(/* empty encoding */); | |
| 7479 ins_cost(0); | |
| 7480 ins_pipe(empty); | |
| 7481 %} | |
| 7482 | |
| 7483 // LoadP-locked same as a regular LoadP when used with compare-swap | |
| 7484 instruct loadPLocked(rRegP dst, memory mem) | |
| 7485 %{ | |
| 7486 match(Set dst (LoadPLocked mem)); | |
| 7487 | |
| 7488 ins_cost(125); // XXX | |
| 7489 format %{ "movq $dst, $mem\t# ptr locked" %} | |
| 7490 opcode(0x8B); | |
| 7491 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 7492 ins_pipe(ialu_reg_mem); // XXX | |
| 7493 %} | |
| 7494 | |
| 7495 // LoadL-locked - same as a regular LoadL when used with compare-swap | |
| 7496 instruct loadLLocked(rRegL dst, memory mem) | |
| 7497 %{ | |
| 7498 match(Set dst (LoadLLocked mem)); | |
| 7499 | |
| 7500 ins_cost(125); // XXX | |
| 7501 format %{ "movq $dst, $mem\t# long locked" %} | |
| 7502 opcode(0x8B); | |
| 7503 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 7504 ins_pipe(ialu_reg_mem); // XXX | |
| 7505 %} | |
| 7506 | |
| 7507 // Conditional-store of the updated heap-top. | |
| 7508 // Used during allocation of the shared heap. | |
| 7509 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel. | |
| 7510 | |
| 7511 instruct storePConditional(memory heap_top_ptr, | |
| 7512 rax_RegP oldval, rRegP newval, | |
| 7513 rFlagsReg cr) | |
| 7514 %{ | |
| 7515 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval))); | |
|
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7516 |
| 0 | 7517 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) " |
| 7518 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %} | |
| 7519 opcode(0x0F, 0xB1); | |
| 7520 ins_encode(lock_prefix, | |
| 7521 REX_reg_mem_wide(newval, heap_top_ptr), | |
| 7522 OpcP, OpcS, | |
| 7523 reg_mem(newval, heap_top_ptr)); | |
| 7524 ins_pipe(pipe_cmpxchg); | |
| 7525 %} | |
| 7526 | |
|
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7527 // Conditional-store of an int value. |
|
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7528 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG. |
|
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7529 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr) |
|
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7530 %{ |
|
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7531 match(Set cr (StoreIConditional mem (Binary oldval newval))); |
|
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6462850: generate biased locking code in C2 ideal graph
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7532 effect(KILL oldval); |
|
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|
7533 |
|
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|
7534 format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %} |
| 0 | 7535 opcode(0x0F, 0xB1); |
| 7536 ins_encode(lock_prefix, | |
|
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7537 REX_reg_mem(newval, mem), |
| 0 | 7538 OpcP, OpcS, |
|
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7539 reg_mem(newval, mem)); |
| 0 | 7540 ins_pipe(pipe_cmpxchg); |
| 7541 %} | |
| 7542 | |
|
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7543 // Conditional-store of a long value. |
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7544 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG. |
|
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7545 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr) |
|
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7546 %{ |
|
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7547 match(Set cr (StoreLConditional mem (Binary oldval newval))); |
|
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7548 effect(KILL oldval); |
|
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7549 |
|
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7550 format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %} |
| 0 | 7551 opcode(0x0F, 0xB1); |
| 7552 ins_encode(lock_prefix, | |
|
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|
7553 REX_reg_mem_wide(newval, mem), |
| 0 | 7554 OpcP, OpcS, |
|
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|
7555 reg_mem(newval, mem)); |
| 0 | 7556 ins_pipe(pipe_cmpxchg); |
| 7557 %} | |
| 7558 | |
|
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7559 |
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7560 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them |
| 0 | 7561 instruct compareAndSwapP(rRegI res, |
| 7562 memory mem_ptr, | |
| 7563 rax_RegP oldval, rRegP newval, | |
| 7564 rFlagsReg cr) | |
| 7565 %{ | |
| 7566 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); | |
| 7567 effect(KILL cr, KILL oldval); | |
| 7568 | |
| 7569 format %{ "cmpxchgq $mem_ptr,$newval\t# " | |
| 7570 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" | |
| 7571 "sete $res\n\t" | |
| 7572 "movzbl $res, $res" %} | |
| 7573 opcode(0x0F, 0xB1); | |
| 7574 ins_encode(lock_prefix, | |
| 7575 REX_reg_mem_wide(newval, mem_ptr), | |
| 7576 OpcP, OpcS, | |
| 7577 reg_mem(newval, mem_ptr), | |
| 7578 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete | |
| 7579 REX_reg_breg(res, res), // movzbl | |
| 7580 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); | |
| 7581 ins_pipe( pipe_cmpxchg ); | |
| 7582 %} | |
| 7583 | |
| 7584 instruct compareAndSwapL(rRegI res, | |
| 7585 memory mem_ptr, | |
| 7586 rax_RegL oldval, rRegL newval, | |
| 7587 rFlagsReg cr) | |
| 7588 %{ | |
| 7589 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); | |
| 7590 effect(KILL cr, KILL oldval); | |
| 7591 | |
| 7592 format %{ "cmpxchgq $mem_ptr,$newval\t# " | |
| 7593 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" | |
| 7594 "sete $res\n\t" | |
| 7595 "movzbl $res, $res" %} | |
| 7596 opcode(0x0F, 0xB1); | |
| 7597 ins_encode(lock_prefix, | |
| 7598 REX_reg_mem_wide(newval, mem_ptr), | |
| 7599 OpcP, OpcS, | |
| 7600 reg_mem(newval, mem_ptr), | |
| 7601 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete | |
| 7602 REX_reg_breg(res, res), // movzbl | |
| 7603 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); | |
| 7604 ins_pipe( pipe_cmpxchg ); | |
| 7605 %} | |
| 7606 | |
| 7607 instruct compareAndSwapI(rRegI res, | |
| 7608 memory mem_ptr, | |
| 7609 rax_RegI oldval, rRegI newval, | |
| 7610 rFlagsReg cr) | |
| 7611 %{ | |
| 7612 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); | |
| 7613 effect(KILL cr, KILL oldval); | |
| 7614 | |
| 7615 format %{ "cmpxchgl $mem_ptr,$newval\t# " | |
| 7616 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" | |
| 7617 "sete $res\n\t" | |
| 7618 "movzbl $res, $res" %} | |
| 7619 opcode(0x0F, 0xB1); | |
| 7620 ins_encode(lock_prefix, | |
| 7621 REX_reg_mem(newval, mem_ptr), | |
| 7622 OpcP, OpcS, | |
| 7623 reg_mem(newval, mem_ptr), | |
| 7624 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete | |
| 7625 REX_reg_breg(res, res), // movzbl | |
| 7626 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); | |
| 7627 ins_pipe( pipe_cmpxchg ); | |
| 7628 %} | |
| 7629 | |
| 7630 | |
|
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7631 instruct compareAndSwapN(rRegI res, |
|
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7632 memory mem_ptr, |
|
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7633 rax_RegN oldval, rRegN newval, |
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7634 rFlagsReg cr) %{ |
|
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7635 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); |
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7636 effect(KILL cr, KILL oldval); |
|
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7637 |
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7638 format %{ "cmpxchgl $mem_ptr,$newval\t# " |
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7639 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" |
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7640 "sete $res\n\t" |
|
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7641 "movzbl $res, $res" %} |
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7642 opcode(0x0F, 0xB1); |
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7643 ins_encode(lock_prefix, |
|
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|
7644 REX_reg_mem(newval, mem_ptr), |
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7645 OpcP, OpcS, |
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|
7646 reg_mem(newval, mem_ptr), |
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|
7647 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete |
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7648 REX_reg_breg(res, res), // movzbl |
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7649 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); |
|
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|
7650 ins_pipe( pipe_cmpxchg ); |
|
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|
7651 %} |
|
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|
7652 |
| 0 | 7653 //----------Subtraction Instructions------------------------------------------- |
| 7654 | |
| 7655 // Integer Subtraction Instructions | |
| 7656 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 7657 %{ | |
| 7658 match(Set dst (SubI dst src)); | |
| 7659 effect(KILL cr); | |
| 7660 | |
| 7661 format %{ "subl $dst, $src\t# int" %} | |
| 7662 opcode(0x2B); | |
| 7663 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 7664 ins_pipe(ialu_reg_reg); | |
| 7665 %} | |
| 7666 | |
| 7667 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 7668 %{ | |
| 7669 match(Set dst (SubI dst src)); | |
| 7670 effect(KILL cr); | |
| 7671 | |
| 7672 format %{ "subl $dst, $src\t# int" %} | |
| 7673 opcode(0x81, 0x05); /* Opcode 81 /5 */ | |
| 7674 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 7675 ins_pipe(ialu_reg); | |
| 7676 %} | |
| 7677 | |
| 7678 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 7679 %{ | |
| 7680 match(Set dst (SubI dst (LoadI src))); | |
| 7681 effect(KILL cr); | |
| 7682 | |
| 7683 ins_cost(125); | |
| 7684 format %{ "subl $dst, $src\t# int" %} | |
| 7685 opcode(0x2B); | |
| 7686 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 7687 ins_pipe(ialu_reg_mem); | |
| 7688 %} | |
| 7689 | |
| 7690 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 7691 %{ | |
| 7692 match(Set dst (StoreI dst (SubI (LoadI dst) src))); | |
| 7693 effect(KILL cr); | |
| 7694 | |
| 7695 ins_cost(150); | |
| 7696 format %{ "subl $dst, $src\t# int" %} | |
| 7697 opcode(0x29); /* Opcode 29 /r */ | |
| 7698 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 7699 ins_pipe(ialu_mem_reg); | |
| 7700 %} | |
| 7701 | |
| 7702 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 7703 %{ | |
| 7704 match(Set dst (StoreI dst (SubI (LoadI dst) src))); | |
| 7705 effect(KILL cr); | |
| 7706 | |
| 7707 ins_cost(125); // XXX | |
| 7708 format %{ "subl $dst, $src\t# int" %} | |
| 7709 opcode(0x81); /* Opcode 81 /5 id */ | |
| 7710 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src)); | |
| 7711 ins_pipe(ialu_mem_imm); | |
| 7712 %} | |
| 7713 | |
| 7714 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 7715 %{ | |
| 7716 match(Set dst (SubL dst src)); | |
| 7717 effect(KILL cr); | |
| 7718 | |
| 7719 format %{ "subq $dst, $src\t# long" %} | |
| 7720 opcode(0x2B); | |
| 7721 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 7722 ins_pipe(ialu_reg_reg); | |
| 7723 %} | |
| 7724 | |
| 7725 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr) | |
| 7726 %{ | |
| 7727 match(Set dst (SubL dst src)); | |
| 7728 effect(KILL cr); | |
| 7729 | |
| 7730 format %{ "subq $dst, $src\t# long" %} | |
| 7731 opcode(0x81, 0x05); /* Opcode 81 /5 */ | |
| 7732 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 7733 ins_pipe(ialu_reg); | |
| 7734 %} | |
| 7735 | |
| 7736 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 7737 %{ | |
| 7738 match(Set dst (SubL dst (LoadL src))); | |
| 7739 effect(KILL cr); | |
| 7740 | |
| 7741 ins_cost(125); | |
| 7742 format %{ "subq $dst, $src\t# long" %} | |
| 7743 opcode(0x2B); | |
| 7744 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 7745 ins_pipe(ialu_reg_mem); | |
| 7746 %} | |
| 7747 | |
| 7748 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 7749 %{ | |
| 7750 match(Set dst (StoreL dst (SubL (LoadL dst) src))); | |
| 7751 effect(KILL cr); | |
| 7752 | |
| 7753 ins_cost(150); | |
| 7754 format %{ "subq $dst, $src\t# long" %} | |
| 7755 opcode(0x29); /* Opcode 29 /r */ | |
| 7756 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 7757 ins_pipe(ialu_mem_reg); | |
| 7758 %} | |
| 7759 | |
| 7760 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 7761 %{ | |
| 7762 match(Set dst (StoreL dst (SubL (LoadL dst) src))); | |
| 7763 effect(KILL cr); | |
| 7764 | |
| 7765 ins_cost(125); // XXX | |
| 7766 format %{ "subq $dst, $src\t# long" %} | |
| 7767 opcode(0x81); /* Opcode 81 /5 id */ | |
| 7768 ins_encode(REX_mem_wide(dst), | |
| 7769 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src)); | |
| 7770 ins_pipe(ialu_mem_imm); | |
| 7771 %} | |
| 7772 | |
| 7773 // Subtract from a pointer | |
| 7774 // XXX hmpf??? | |
| 7775 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr) | |
| 7776 %{ | |
| 7777 match(Set dst (AddP dst (SubI zero src))); | |
| 7778 effect(KILL cr); | |
| 7779 | |
| 7780 format %{ "subq $dst, $src\t# ptr - int" %} | |
| 7781 opcode(0x2B); | |
| 7782 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 7783 ins_pipe(ialu_reg_reg); | |
| 7784 %} | |
| 7785 | |
| 7786 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr) | |
| 7787 %{ | |
| 7788 match(Set dst (SubI zero dst)); | |
| 7789 effect(KILL cr); | |
| 7790 | |
| 7791 format %{ "negl $dst\t# int" %} | |
| 7792 opcode(0xF7, 0x03); // Opcode F7 /3 | |
| 7793 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 7794 ins_pipe(ialu_reg); | |
| 7795 %} | |
| 7796 | |
| 7797 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr) | |
| 7798 %{ | |
| 7799 match(Set dst (StoreI dst (SubI zero (LoadI dst)))); | |
| 7800 effect(KILL cr); | |
| 7801 | |
| 7802 format %{ "negl $dst\t# int" %} | |
| 7803 opcode(0xF7, 0x03); // Opcode F7 /3 | |
| 7804 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 7805 ins_pipe(ialu_reg); | |
| 7806 %} | |
| 7807 | |
| 7808 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr) | |
| 7809 %{ | |
| 7810 match(Set dst (SubL zero dst)); | |
| 7811 effect(KILL cr); | |
| 7812 | |
| 7813 format %{ "negq $dst\t# long" %} | |
| 7814 opcode(0xF7, 0x03); // Opcode F7 /3 | |
| 7815 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 7816 ins_pipe(ialu_reg); | |
| 7817 %} | |
| 7818 | |
| 7819 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr) | |
| 7820 %{ | |
| 7821 match(Set dst (StoreL dst (SubL zero (LoadL dst)))); | |
| 7822 effect(KILL cr); | |
| 7823 | |
| 7824 format %{ "negq $dst\t# long" %} | |
| 7825 opcode(0xF7, 0x03); // Opcode F7 /3 | |
| 7826 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 7827 ins_pipe(ialu_reg); | |
| 7828 %} | |
| 7829 | |
| 7830 | |
| 7831 //----------Multiplication/Division Instructions------------------------------- | |
| 7832 // Integer Multiplication Instructions | |
| 7833 // Multiply Register | |
| 7834 | |
| 7835 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 7836 %{ | |
| 7837 match(Set dst (MulI dst src)); | |
| 7838 effect(KILL cr); | |
| 7839 | |
| 7840 ins_cost(300); | |
| 7841 format %{ "imull $dst, $src\t# int" %} | |
| 7842 opcode(0x0F, 0xAF); | |
| 7843 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 7844 ins_pipe(ialu_reg_reg_alu0); | |
| 7845 %} | |
| 7846 | |
| 7847 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr) | |
| 7848 %{ | |
| 7849 match(Set dst (MulI src imm)); | |
| 7850 effect(KILL cr); | |
| 7851 | |
| 7852 ins_cost(300); | |
| 7853 format %{ "imull $dst, $src, $imm\t# int" %} | |
| 7854 opcode(0x69); /* 69 /r id */ | |
| 7855 ins_encode(REX_reg_reg(dst, src), | |
| 7856 OpcSE(imm), reg_reg(dst, src), Con8or32(imm)); | |
| 7857 ins_pipe(ialu_reg_reg_alu0); | |
| 7858 %} | |
| 7859 | |
| 7860 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 7861 %{ | |
| 7862 match(Set dst (MulI dst (LoadI src))); | |
| 7863 effect(KILL cr); | |
| 7864 | |
| 7865 ins_cost(350); | |
| 7866 format %{ "imull $dst, $src\t# int" %} | |
| 7867 opcode(0x0F, 0xAF); | |
| 7868 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src)); | |
| 7869 ins_pipe(ialu_reg_mem_alu0); | |
| 7870 %} | |
| 7871 | |
| 7872 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr) | |
| 7873 %{ | |
| 7874 match(Set dst (MulI (LoadI src) imm)); | |
| 7875 effect(KILL cr); | |
| 7876 | |
| 7877 ins_cost(300); | |
| 7878 format %{ "imull $dst, $src, $imm\t# int" %} | |
| 7879 opcode(0x69); /* 69 /r id */ | |
| 7880 ins_encode(REX_reg_mem(dst, src), | |
| 7881 OpcSE(imm), reg_mem(dst, src), Con8or32(imm)); | |
| 7882 ins_pipe(ialu_reg_mem_alu0); | |
| 7883 %} | |
| 7884 | |
| 7885 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 7886 %{ | |
| 7887 match(Set dst (MulL dst src)); | |
| 7888 effect(KILL cr); | |
| 7889 | |
| 7890 ins_cost(300); | |
| 7891 format %{ "imulq $dst, $src\t# long" %} | |
| 7892 opcode(0x0F, 0xAF); | |
| 7893 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 7894 ins_pipe(ialu_reg_reg_alu0); | |
| 7895 %} | |
| 7896 | |
| 7897 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr) | |
| 7898 %{ | |
| 7899 match(Set dst (MulL src imm)); | |
| 7900 effect(KILL cr); | |
| 7901 | |
| 7902 ins_cost(300); | |
| 7903 format %{ "imulq $dst, $src, $imm\t# long" %} | |
| 7904 opcode(0x69); /* 69 /r id */ | |
| 7905 ins_encode(REX_reg_reg_wide(dst, src), | |
| 7906 OpcSE(imm), reg_reg(dst, src), Con8or32(imm)); | |
| 7907 ins_pipe(ialu_reg_reg_alu0); | |
| 7908 %} | |
| 7909 | |
| 7910 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 7911 %{ | |
| 7912 match(Set dst (MulL dst (LoadL src))); | |
| 7913 effect(KILL cr); | |
| 7914 | |
| 7915 ins_cost(350); | |
| 7916 format %{ "imulq $dst, $src\t# long" %} | |
| 7917 opcode(0x0F, 0xAF); | |
| 7918 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src)); | |
| 7919 ins_pipe(ialu_reg_mem_alu0); | |
| 7920 %} | |
| 7921 | |
| 7922 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr) | |
| 7923 %{ | |
| 7924 match(Set dst (MulL (LoadL src) imm)); | |
| 7925 effect(KILL cr); | |
| 7926 | |
| 7927 ins_cost(300); | |
| 7928 format %{ "imulq $dst, $src, $imm\t# long" %} | |
| 7929 opcode(0x69); /* 69 /r id */ | |
| 7930 ins_encode(REX_reg_mem_wide(dst, src), | |
| 7931 OpcSE(imm), reg_mem(dst, src), Con8or32(imm)); | |
| 7932 ins_pipe(ialu_reg_mem_alu0); | |
| 7933 %} | |
| 7934 | |
| 145 | 7935 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr) |
| 7936 %{ | |
| 7937 match(Set dst (MulHiL src rax)); | |
| 7938 effect(USE_KILL rax, KILL cr); | |
| 7939 | |
| 7940 ins_cost(300); | |
| 7941 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %} | |
| 7942 opcode(0xF7, 0x5); /* Opcode F7 /5 */ | |
| 7943 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src)); | |
| 7944 ins_pipe(ialu_reg_reg_alu0); | |
| 7945 %} | |
| 7946 | |
| 0 | 7947 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div, |
| 7948 rFlagsReg cr) | |
| 7949 %{ | |
| 7950 match(Set rax (DivI rax div)); | |
| 7951 effect(KILL rdx, KILL cr); | |
| 7952 | |
| 7953 ins_cost(30*100+10*100); // XXX | |
| 7954 format %{ "cmpl rax, 0x80000000\t# idiv\n\t" | |
| 7955 "jne,s normal\n\t" | |
| 7956 "xorl rdx, rdx\n\t" | |
| 7957 "cmpl $div, -1\n\t" | |
| 7958 "je,s done\n" | |
| 7959 "normal: cdql\n\t" | |
| 7960 "idivl $div\n" | |
| 7961 "done:" %} | |
| 7962 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 7963 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div)); | |
| 7964 ins_pipe(ialu_reg_reg_alu0); | |
| 7965 %} | |
| 7966 | |
| 7967 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div, | |
| 7968 rFlagsReg cr) | |
| 7969 %{ | |
| 7970 match(Set rax (DivL rax div)); | |
| 7971 effect(KILL rdx, KILL cr); | |
| 7972 | |
| 7973 ins_cost(30*100+10*100); // XXX | |
| 7974 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t" | |
| 7975 "cmpq rax, rdx\n\t" | |
| 7976 "jne,s normal\n\t" | |
| 7977 "xorl rdx, rdx\n\t" | |
| 7978 "cmpq $div, -1\n\t" | |
| 7979 "je,s done\n" | |
| 7980 "normal: cdqq\n\t" | |
| 7981 "idivq $div\n" | |
| 7982 "done:" %} | |
| 7983 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 7984 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div)); | |
| 7985 ins_pipe(ialu_reg_reg_alu0); | |
| 7986 %} | |
| 7987 | |
| 7988 // Integer DIVMOD with Register, both quotient and mod results | |
| 7989 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div, | |
| 7990 rFlagsReg cr) | |
| 7991 %{ | |
| 7992 match(DivModI rax div); | |
| 7993 effect(KILL cr); | |
| 7994 | |
| 7995 ins_cost(30*100+10*100); // XXX | |
| 7996 format %{ "cmpl rax, 0x80000000\t# idiv\n\t" | |
| 7997 "jne,s normal\n\t" | |
| 7998 "xorl rdx, rdx\n\t" | |
| 7999 "cmpl $div, -1\n\t" | |
| 8000 "je,s done\n" | |
| 8001 "normal: cdql\n\t" | |
| 8002 "idivl $div\n" | |
| 8003 "done:" %} | |
| 8004 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8005 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div)); | |
| 8006 ins_pipe(pipe_slow); | |
| 8007 %} | |
| 8008 | |
| 8009 // Long DIVMOD with Register, both quotient and mod results | |
| 8010 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div, | |
| 8011 rFlagsReg cr) | |
| 8012 %{ | |
| 8013 match(DivModL rax div); | |
| 8014 effect(KILL cr); | |
| 8015 | |
| 8016 ins_cost(30*100+10*100); // XXX | |
| 8017 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t" | |
| 8018 "cmpq rax, rdx\n\t" | |
| 8019 "jne,s normal\n\t" | |
| 8020 "xorl rdx, rdx\n\t" | |
| 8021 "cmpq $div, -1\n\t" | |
| 8022 "je,s done\n" | |
| 8023 "normal: cdqq\n\t" | |
| 8024 "idivq $div\n" | |
| 8025 "done:" %} | |
| 8026 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8027 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div)); | |
| 8028 ins_pipe(pipe_slow); | |
| 8029 %} | |
| 8030 | |
| 8031 //----------- DivL-By-Constant-Expansions-------------------------------------- | |
| 8032 // DivI cases are handled by the compiler | |
| 8033 | |
| 605 | 8034 // Magic constant, reciprocal of 10 |
| 0 | 8035 instruct loadConL_0x6666666666666667(rRegL dst) |
| 8036 %{ | |
| 8037 effect(DEF dst); | |
| 8038 | |
| 8039 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %} | |
| 8040 ins_encode(load_immL(dst, 0x6666666666666667)); | |
| 8041 ins_pipe(ialu_reg); | |
| 8042 %} | |
| 8043 | |
| 8044 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr) | |
| 8045 %{ | |
| 8046 effect(DEF dst, USE src, USE_KILL rax, KILL cr); | |
| 8047 | |
| 8048 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %} | |
| 8049 opcode(0xF7, 0x5); /* Opcode F7 /5 */ | |
| 8050 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src)); | |
| 8051 ins_pipe(ialu_reg_reg_alu0); | |
| 8052 %} | |
| 8053 | |
| 8054 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr) | |
| 8055 %{ | |
| 8056 effect(USE_DEF dst, KILL cr); | |
| 8057 | |
| 8058 format %{ "sarq $dst, #63\t# Used in div-by-10" %} | |
| 8059 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8060 ins_encode(reg_opc_imm_wide(dst, 0x3F)); | |
| 8061 ins_pipe(ialu_reg); | |
| 8062 %} | |
| 8063 | |
| 8064 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr) | |
| 8065 %{ | |
| 8066 effect(USE_DEF dst, KILL cr); | |
| 8067 | |
| 8068 format %{ "sarq $dst, #2\t# Used in div-by-10" %} | |
| 8069 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8070 ins_encode(reg_opc_imm_wide(dst, 0x2)); | |
| 8071 ins_pipe(ialu_reg); | |
| 8072 %} | |
| 8073 | |
| 8074 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div) | |
| 8075 %{ | |
| 8076 match(Set dst (DivL src div)); | |
| 8077 | |
| 8078 ins_cost((5+8)*100); | |
| 8079 expand %{ | |
| 8080 rax_RegL rax; // Killed temp | |
| 8081 rFlagsReg cr; // Killed | |
| 8082 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667 | |
| 8083 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src | |
| 8084 sarL_rReg_63(src, cr); // sarq src, 63 | |
| 8085 sarL_rReg_2(dst, cr); // sarq rdx, 2 | |
| 8086 subL_rReg(dst, src, cr); // subl rdx, src | |
| 8087 %} | |
| 8088 %} | |
| 8089 | |
| 8090 //----------------------------------------------------------------------------- | |
| 8091 | |
| 8092 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div, | |
| 8093 rFlagsReg cr) | |
| 8094 %{ | |
| 8095 match(Set rdx (ModI rax div)); | |
| 8096 effect(KILL rax, KILL cr); | |
| 8097 | |
| 8098 ins_cost(300); // XXX | |
| 8099 format %{ "cmpl rax, 0x80000000\t# irem\n\t" | |
| 8100 "jne,s normal\n\t" | |
| 8101 "xorl rdx, rdx\n\t" | |
| 8102 "cmpl $div, -1\n\t" | |
| 8103 "je,s done\n" | |
| 8104 "normal: cdql\n\t" | |
| 8105 "idivl $div\n" | |
| 8106 "done:" %} | |
| 8107 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8108 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div)); | |
| 8109 ins_pipe(ialu_reg_reg_alu0); | |
| 8110 %} | |
| 8111 | |
| 8112 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div, | |
| 8113 rFlagsReg cr) | |
| 8114 %{ | |
| 8115 match(Set rdx (ModL rax div)); | |
| 8116 effect(KILL rax, KILL cr); | |
| 8117 | |
| 8118 ins_cost(300); // XXX | |
| 8119 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t" | |
| 8120 "cmpq rax, rdx\n\t" | |
| 8121 "jne,s normal\n\t" | |
| 8122 "xorl rdx, rdx\n\t" | |
| 8123 "cmpq $div, -1\n\t" | |
| 8124 "je,s done\n" | |
| 8125 "normal: cdqq\n\t" | |
| 8126 "idivq $div\n" | |
| 8127 "done:" %} | |
| 8128 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8129 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div)); | |
| 8130 ins_pipe(ialu_reg_reg_alu0); | |
| 8131 %} | |
| 8132 | |
| 8133 // Integer Shift Instructions | |
| 8134 // Shift Left by one | |
| 8135 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr) | |
| 8136 %{ | |
| 8137 match(Set dst (LShiftI dst shift)); | |
| 8138 effect(KILL cr); | |
| 8139 | |
| 8140 format %{ "sall $dst, $shift" %} | |
| 8141 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 8142 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8143 ins_pipe(ialu_reg); | |
| 8144 %} | |
| 8145 | |
| 8146 // Shift Left by one | |
| 8147 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 8148 %{ | |
| 8149 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift))); | |
| 8150 effect(KILL cr); | |
| 8151 | |
| 8152 format %{ "sall $dst, $shift\t" %} | |
| 8153 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 8154 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8155 ins_pipe(ialu_mem_imm); | |
| 8156 %} | |
| 8157 | |
| 8158 // Shift Left by 8-bit immediate | |
| 8159 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) | |
| 8160 %{ | |
| 8161 match(Set dst (LShiftI dst shift)); | |
| 8162 effect(KILL cr); | |
| 8163 | |
| 8164 format %{ "sall $dst, $shift" %} | |
| 8165 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 8166 ins_encode(reg_opc_imm(dst, shift)); | |
| 8167 ins_pipe(ialu_reg); | |
| 8168 %} | |
| 8169 | |
| 8170 // Shift Left by 8-bit immediate | |
| 8171 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 8172 %{ | |
| 8173 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift))); | |
| 8174 effect(KILL cr); | |
| 8175 | |
| 8176 format %{ "sall $dst, $shift" %} | |
| 8177 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 8178 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 8179 ins_pipe(ialu_mem_imm); | |
| 8180 %} | |
| 8181 | |
| 8182 // Shift Left by variable | |
| 8183 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 8184 %{ | |
| 8185 match(Set dst (LShiftI dst shift)); | |
| 8186 effect(KILL cr); | |
| 8187 | |
| 8188 format %{ "sall $dst, $shift" %} | |
| 8189 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 8190 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8191 ins_pipe(ialu_reg_reg); | |
| 8192 %} | |
| 8193 | |
| 8194 // Shift Left by variable | |
| 8195 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 8196 %{ | |
| 8197 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift))); | |
| 8198 effect(KILL cr); | |
| 8199 | |
| 8200 format %{ "sall $dst, $shift" %} | |
| 8201 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 8202 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8203 ins_pipe(ialu_mem_reg); | |
| 8204 %} | |
| 8205 | |
| 8206 // Arithmetic shift right by one | |
| 8207 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr) | |
| 8208 %{ | |
| 8209 match(Set dst (RShiftI dst shift)); | |
| 8210 effect(KILL cr); | |
| 8211 | |
| 8212 format %{ "sarl $dst, $shift" %} | |
| 8213 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 8214 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8215 ins_pipe(ialu_reg); | |
| 8216 %} | |
| 8217 | |
| 8218 // Arithmetic shift right by one | |
| 8219 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 8220 %{ | |
| 8221 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 8222 effect(KILL cr); | |
| 8223 | |
| 8224 format %{ "sarl $dst, $shift" %} | |
| 8225 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 8226 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8227 ins_pipe(ialu_mem_imm); | |
| 8228 %} | |
| 8229 | |
| 8230 // Arithmetic Shift Right by 8-bit immediate | |
| 8231 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) | |
| 8232 %{ | |
| 8233 match(Set dst (RShiftI dst shift)); | |
| 8234 effect(KILL cr); | |
| 8235 | |
| 8236 format %{ "sarl $dst, $shift" %} | |
| 8237 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8238 ins_encode(reg_opc_imm(dst, shift)); | |
| 8239 ins_pipe(ialu_mem_imm); | |
| 8240 %} | |
| 8241 | |
| 8242 // Arithmetic Shift Right by 8-bit immediate | |
| 8243 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 8244 %{ | |
| 8245 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 8246 effect(KILL cr); | |
| 8247 | |
| 8248 format %{ "sarl $dst, $shift" %} | |
| 8249 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8250 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 8251 ins_pipe(ialu_mem_imm); | |
| 8252 %} | |
| 8253 | |
| 8254 // Arithmetic Shift Right by variable | |
| 8255 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 8256 %{ | |
| 8257 match(Set dst (RShiftI dst shift)); | |
| 8258 effect(KILL cr); | |
| 8259 | |
| 8260 format %{ "sarl $dst, $shift" %} | |
| 8261 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 8262 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8263 ins_pipe(ialu_reg_reg); | |
| 8264 %} | |
| 8265 | |
| 8266 // Arithmetic Shift Right by variable | |
| 8267 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 8268 %{ | |
| 8269 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 8270 effect(KILL cr); | |
| 8271 | |
| 8272 format %{ "sarl $dst, $shift" %} | |
| 8273 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 8274 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8275 ins_pipe(ialu_mem_reg); | |
| 8276 %} | |
| 8277 | |
| 8278 // Logical shift right by one | |
| 8279 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr) | |
| 8280 %{ | |
| 8281 match(Set dst (URShiftI dst shift)); | |
| 8282 effect(KILL cr); | |
| 8283 | |
| 8284 format %{ "shrl $dst, $shift" %} | |
| 8285 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 8286 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8287 ins_pipe(ialu_reg); | |
| 8288 %} | |
| 8289 | |
| 8290 // Logical shift right by one | |
| 8291 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 8292 %{ | |
| 8293 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift))); | |
| 8294 effect(KILL cr); | |
| 8295 | |
| 8296 format %{ "shrl $dst, $shift" %} | |
| 8297 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 8298 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8299 ins_pipe(ialu_mem_imm); | |
| 8300 %} | |
| 8301 | |
| 8302 // Logical Shift Right by 8-bit immediate | |
| 8303 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) | |
| 8304 %{ | |
| 8305 match(Set dst (URShiftI dst shift)); | |
| 8306 effect(KILL cr); | |
| 8307 | |
| 8308 format %{ "shrl $dst, $shift" %} | |
| 8309 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 8310 ins_encode(reg_opc_imm(dst, shift)); | |
| 8311 ins_pipe(ialu_reg); | |
| 8312 %} | |
| 8313 | |
| 8314 // Logical Shift Right by 8-bit immediate | |
| 8315 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 8316 %{ | |
| 8317 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift))); | |
| 8318 effect(KILL cr); | |
| 8319 | |
| 8320 format %{ "shrl $dst, $shift" %} | |
| 8321 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 8322 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 8323 ins_pipe(ialu_mem_imm); | |
| 8324 %} | |
| 8325 | |
| 8326 // Logical Shift Right by variable | |
| 8327 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 8328 %{ | |
| 8329 match(Set dst (URShiftI dst shift)); | |
| 8330 effect(KILL cr); | |
| 8331 | |
| 8332 format %{ "shrl $dst, $shift" %} | |
| 8333 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 8334 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8335 ins_pipe(ialu_reg_reg); | |
| 8336 %} | |
| 8337 | |
| 8338 // Logical Shift Right by variable | |
| 8339 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 8340 %{ | |
| 8341 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift))); | |
| 8342 effect(KILL cr); | |
| 8343 | |
| 8344 format %{ "shrl $dst, $shift" %} | |
| 8345 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 8346 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8347 ins_pipe(ialu_mem_reg); | |
| 8348 %} | |
| 8349 | |
| 8350 // Long Shift Instructions | |
| 8351 // Shift Left by one | |
| 8352 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr) | |
| 8353 %{ | |
| 8354 match(Set dst (LShiftL dst shift)); | |
| 8355 effect(KILL cr); | |
| 8356 | |
| 8357 format %{ "salq $dst, $shift" %} | |
| 8358 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 8359 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8360 ins_pipe(ialu_reg); | |
| 8361 %} | |
| 8362 | |
| 8363 // Shift Left by one | |
| 8364 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 8365 %{ | |
| 8366 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift))); | |
| 8367 effect(KILL cr); | |
| 8368 | |
| 8369 format %{ "salq $dst, $shift" %} | |
| 8370 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 8371 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8372 ins_pipe(ialu_mem_imm); | |
| 8373 %} | |
| 8374 | |
| 8375 // Shift Left by 8-bit immediate | |
| 8376 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr) | |
| 8377 %{ | |
| 8378 match(Set dst (LShiftL dst shift)); | |
| 8379 effect(KILL cr); | |
| 8380 | |
| 8381 format %{ "salq $dst, $shift" %} | |
| 8382 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 8383 ins_encode(reg_opc_imm_wide(dst, shift)); | |
| 8384 ins_pipe(ialu_reg); | |
| 8385 %} | |
| 8386 | |
| 8387 // Shift Left by 8-bit immediate | |
| 8388 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 8389 %{ | |
| 8390 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift))); | |
| 8391 effect(KILL cr); | |
| 8392 | |
| 8393 format %{ "salq $dst, $shift" %} | |
| 8394 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 8395 ins_encode(REX_mem_wide(dst), OpcP, | |
| 8396 RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 8397 ins_pipe(ialu_mem_imm); | |
| 8398 %} | |
| 8399 | |
| 8400 // Shift Left by variable | |
| 8401 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 8402 %{ | |
| 8403 match(Set dst (LShiftL dst shift)); | |
| 8404 effect(KILL cr); | |
| 8405 | |
| 8406 format %{ "salq $dst, $shift" %} | |
| 8407 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 8408 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8409 ins_pipe(ialu_reg_reg); | |
| 8410 %} | |
| 8411 | |
| 8412 // Shift Left by variable | |
| 8413 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 8414 %{ | |
| 8415 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift))); | |
| 8416 effect(KILL cr); | |
| 8417 | |
| 8418 format %{ "salq $dst, $shift" %} | |
| 8419 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 8420 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8421 ins_pipe(ialu_mem_reg); | |
| 8422 %} | |
| 8423 | |
| 8424 // Arithmetic shift right by one | |
| 8425 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr) | |
| 8426 %{ | |
| 8427 match(Set dst (RShiftL dst shift)); | |
| 8428 effect(KILL cr); | |
| 8429 | |
| 8430 format %{ "sarq $dst, $shift" %} | |
| 8431 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 8432 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8433 ins_pipe(ialu_reg); | |
| 8434 %} | |
| 8435 | |
| 8436 // Arithmetic shift right by one | |
| 8437 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 8438 %{ | |
| 8439 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift))); | |
| 8440 effect(KILL cr); | |
| 8441 | |
| 8442 format %{ "sarq $dst, $shift" %} | |
| 8443 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 8444 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8445 ins_pipe(ialu_mem_imm); | |
| 8446 %} | |
| 8447 | |
| 8448 // Arithmetic Shift Right by 8-bit immediate | |
| 8449 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr) | |
| 8450 %{ | |
| 8451 match(Set dst (RShiftL dst shift)); | |
| 8452 effect(KILL cr); | |
| 8453 | |
| 8454 format %{ "sarq $dst, $shift" %} | |
| 8455 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8456 ins_encode(reg_opc_imm_wide(dst, shift)); | |
| 8457 ins_pipe(ialu_mem_imm); | |
| 8458 %} | |
| 8459 | |
| 8460 // Arithmetic Shift Right by 8-bit immediate | |
| 8461 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 8462 %{ | |
| 8463 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift))); | |
| 8464 effect(KILL cr); | |
| 8465 | |
| 8466 format %{ "sarq $dst, $shift" %} | |
| 8467 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8468 ins_encode(REX_mem_wide(dst), OpcP, | |
| 8469 RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 8470 ins_pipe(ialu_mem_imm); | |
| 8471 %} | |
| 8472 | |
| 8473 // Arithmetic Shift Right by variable | |
| 8474 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 8475 %{ | |
| 8476 match(Set dst (RShiftL dst shift)); | |
| 8477 effect(KILL cr); | |
| 8478 | |
| 8479 format %{ "sarq $dst, $shift" %} | |
| 8480 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 8481 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8482 ins_pipe(ialu_reg_reg); | |
| 8483 %} | |
| 8484 | |
| 8485 // Arithmetic Shift Right by variable | |
| 8486 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 8487 %{ | |
| 8488 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift))); | |
| 8489 effect(KILL cr); | |
| 8490 | |
| 8491 format %{ "sarq $dst, $shift" %} | |
| 8492 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 8493 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8494 ins_pipe(ialu_mem_reg); | |
| 8495 %} | |
| 8496 | |
| 8497 // Logical shift right by one | |
| 8498 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr) | |
| 8499 %{ | |
| 8500 match(Set dst (URShiftL dst shift)); | |
| 8501 effect(KILL cr); | |
| 8502 | |
| 8503 format %{ "shrq $dst, $shift" %} | |
| 8504 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 8505 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst )); | |
| 8506 ins_pipe(ialu_reg); | |
| 8507 %} | |
| 8508 | |
| 8509 // Logical shift right by one | |
| 8510 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 8511 %{ | |
| 8512 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift))); | |
| 8513 effect(KILL cr); | |
| 8514 | |
| 8515 format %{ "shrq $dst, $shift" %} | |
| 8516 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 8517 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8518 ins_pipe(ialu_mem_imm); | |
| 8519 %} | |
| 8520 | |
| 8521 // Logical Shift Right by 8-bit immediate | |
| 8522 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr) | |
| 8523 %{ | |
| 8524 match(Set dst (URShiftL dst shift)); | |
| 8525 effect(KILL cr); | |
| 8526 | |
| 8527 format %{ "shrq $dst, $shift" %} | |
| 8528 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 8529 ins_encode(reg_opc_imm_wide(dst, shift)); | |
| 8530 ins_pipe(ialu_reg); | |
| 8531 %} | |
| 8532 | |
|
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|
8533 |
| 0 | 8534 // Logical Shift Right by 8-bit immediate |
| 8535 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 8536 %{ | |
| 8537 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift))); | |
| 8538 effect(KILL cr); | |
| 8539 | |
| 8540 format %{ "shrq $dst, $shift" %} | |
| 8541 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 8542 ins_encode(REX_mem_wide(dst), OpcP, | |
| 8543 RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 8544 ins_pipe(ialu_mem_imm); | |
| 8545 %} | |
| 8546 | |
| 8547 // Logical Shift Right by variable | |
| 8548 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 8549 %{ | |
| 8550 match(Set dst (URShiftL dst shift)); | |
| 8551 effect(KILL cr); | |
| 8552 | |
| 8553 format %{ "shrq $dst, $shift" %} | |
| 8554 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 8555 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8556 ins_pipe(ialu_reg_reg); | |
| 8557 %} | |
| 8558 | |
| 8559 // Logical Shift Right by variable | |
| 8560 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 8561 %{ | |
| 8562 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift))); | |
| 8563 effect(KILL cr); | |
| 8564 | |
| 8565 format %{ "shrq $dst, $shift" %} | |
| 8566 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 8567 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8568 ins_pipe(ialu_mem_reg); | |
| 8569 %} | |
| 8570 | |
| 8571 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24. | |
| 8572 // This idiom is used by the compiler for the i2b bytecode. | |
| 8573 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour) | |
| 8574 %{ | |
| 8575 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour)); | |
| 8576 | |
| 8577 format %{ "movsbl $dst, $src\t# i2b" %} | |
| 8578 opcode(0x0F, 0xBE); | |
| 8579 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 8580 ins_pipe(ialu_reg_reg); | |
| 8581 %} | |
| 8582 | |
| 8583 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16. | |
| 8584 // This idiom is used by the compiler the i2s bytecode. | |
| 8585 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen) | |
| 8586 %{ | |
| 8587 match(Set dst (RShiftI (LShiftI src sixteen) sixteen)); | |
| 8588 | |
| 8589 format %{ "movswl $dst, $src\t# i2s" %} | |
| 8590 opcode(0x0F, 0xBF); | |
| 8591 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 8592 ins_pipe(ialu_reg_reg); | |
| 8593 %} | |
| 8594 | |
| 8595 // ROL/ROR instructions | |
| 8596 | |
| 8597 // ROL expand | |
| 8598 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{ | |
| 8599 effect(KILL cr, USE_DEF dst); | |
| 8600 | |
| 8601 format %{ "roll $dst" %} | |
| 8602 opcode(0xD1, 0x0); /* Opcode D1 /0 */ | |
| 8603 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8604 ins_pipe(ialu_reg); | |
| 8605 %} | |
| 8606 | |
| 8607 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{ | |
| 8608 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8609 | |
| 8610 format %{ "roll $dst, $shift" %} | |
| 8611 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */ | |
| 8612 ins_encode( reg_opc_imm(dst, shift) ); | |
| 8613 ins_pipe(ialu_reg); | |
| 8614 %} | |
| 8615 | |
| 8616 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 8617 %{ | |
| 8618 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8619 | |
| 8620 format %{ "roll $dst, $shift" %} | |
| 8621 opcode(0xD3, 0x0); /* Opcode D3 /0 */ | |
| 8622 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8623 ins_pipe(ialu_reg_reg); | |
| 8624 %} | |
| 8625 // end of ROL expand | |
| 8626 | |
| 8627 // Rotate Left by one | |
| 8628 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr) | |
| 8629 %{ | |
| 8630 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift))); | |
| 8631 | |
| 8632 expand %{ | |
| 8633 rolI_rReg_imm1(dst, cr); | |
| 8634 %} | |
| 8635 %} | |
| 8636 | |
| 8637 // Rotate Left by 8-bit immediate | |
| 8638 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr) | |
| 8639 %{ | |
| 8640 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); | |
| 8641 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift))); | |
| 8642 | |
| 8643 expand %{ | |
| 8644 rolI_rReg_imm8(dst, lshift, cr); | |
| 8645 %} | |
| 8646 %} | |
| 8647 | |
| 8648 // Rotate Left by variable | |
| 8649 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
| 8650 %{ | |
| 8651 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift)))); | |
| 8652 | |
| 8653 expand %{ | |
| 8654 rolI_rReg_CL(dst, shift, cr); | |
| 8655 %} | |
| 8656 %} | |
| 8657 | |
| 8658 // Rotate Left by variable | |
| 8659 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr) | |
| 8660 %{ | |
| 8661 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift)))); | |
| 8662 | |
| 8663 expand %{ | |
| 8664 rolI_rReg_CL(dst, shift, cr); | |
| 8665 %} | |
| 8666 %} | |
| 8667 | |
| 8668 // ROR expand | |
| 8669 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr) | |
| 8670 %{ | |
| 8671 effect(USE_DEF dst, KILL cr); | |
| 8672 | |
| 8673 format %{ "rorl $dst" %} | |
| 8674 opcode(0xD1, 0x1); /* D1 /1 */ | |
| 8675 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8676 ins_pipe(ialu_reg); | |
| 8677 %} | |
| 8678 | |
| 8679 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) | |
| 8680 %{ | |
| 8681 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8682 | |
| 8683 format %{ "rorl $dst, $shift" %} | |
| 8684 opcode(0xC1, 0x1); /* C1 /1 ib */ | |
| 8685 ins_encode(reg_opc_imm(dst, shift)); | |
| 8686 ins_pipe(ialu_reg); | |
| 8687 %} | |
| 8688 | |
| 8689 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 8690 %{ | |
| 8691 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8692 | |
| 8693 format %{ "rorl $dst, $shift" %} | |
| 8694 opcode(0xD3, 0x1); /* D3 /1 */ | |
| 8695 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8696 ins_pipe(ialu_reg_reg); | |
| 8697 %} | |
| 8698 // end of ROR expand | |
| 8699 | |
| 8700 // Rotate Right by one | |
| 8701 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr) | |
| 8702 %{ | |
| 8703 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift))); | |
| 8704 | |
| 8705 expand %{ | |
| 8706 rorI_rReg_imm1(dst, cr); | |
| 8707 %} | |
| 8708 %} | |
| 8709 | |
| 8710 // Rotate Right by 8-bit immediate | |
| 8711 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr) | |
| 8712 %{ | |
| 8713 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); | |
| 8714 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift))); | |
| 8715 | |
| 8716 expand %{ | |
| 8717 rorI_rReg_imm8(dst, rshift, cr); | |
| 8718 %} | |
| 8719 %} | |
| 8720 | |
| 8721 // Rotate Right by variable | |
| 8722 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
| 8723 %{ | |
| 8724 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift)))); | |
| 8725 | |
| 8726 expand %{ | |
| 8727 rorI_rReg_CL(dst, shift, cr); | |
| 8728 %} | |
| 8729 %} | |
| 8730 | |
| 8731 // Rotate Right by variable | |
| 8732 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr) | |
| 8733 %{ | |
| 8734 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift)))); | |
| 8735 | |
| 8736 expand %{ | |
| 8737 rorI_rReg_CL(dst, shift, cr); | |
| 8738 %} | |
| 8739 %} | |
| 8740 | |
| 8741 // for long rotate | |
| 8742 // ROL expand | |
| 8743 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{ | |
| 8744 effect(USE_DEF dst, KILL cr); | |
| 8745 | |
| 8746 format %{ "rolq $dst" %} | |
| 8747 opcode(0xD1, 0x0); /* Opcode D1 /0 */ | |
| 8748 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8749 ins_pipe(ialu_reg); | |
| 8750 %} | |
| 8751 | |
| 8752 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{ | |
| 8753 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8754 | |
| 8755 format %{ "rolq $dst, $shift" %} | |
| 8756 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */ | |
| 8757 ins_encode( reg_opc_imm_wide(dst, shift) ); | |
| 8758 ins_pipe(ialu_reg); | |
| 8759 %} | |
| 8760 | |
| 8761 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 8762 %{ | |
| 8763 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8764 | |
| 8765 format %{ "rolq $dst, $shift" %} | |
| 8766 opcode(0xD3, 0x0); /* Opcode D3 /0 */ | |
| 8767 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8768 ins_pipe(ialu_reg_reg); | |
| 8769 %} | |
| 8770 // end of ROL expand | |
| 8771 | |
| 8772 // Rotate Left by one | |
| 8773 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr) | |
| 8774 %{ | |
| 8775 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift))); | |
| 8776 | |
| 8777 expand %{ | |
| 8778 rolL_rReg_imm1(dst, cr); | |
| 8779 %} | |
| 8780 %} | |
| 8781 | |
| 8782 // Rotate Left by 8-bit immediate | |
| 8783 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr) | |
| 8784 %{ | |
| 8785 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f)); | |
| 8786 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift))); | |
| 8787 | |
| 8788 expand %{ | |
| 8789 rolL_rReg_imm8(dst, lshift, cr); | |
| 8790 %} | |
| 8791 %} | |
| 8792 | |
| 8793 // Rotate Left by variable | |
| 8794 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
| 8795 %{ | |
| 8796 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift)))); | |
| 8797 | |
| 8798 expand %{ | |
| 8799 rolL_rReg_CL(dst, shift, cr); | |
| 8800 %} | |
| 8801 %} | |
| 8802 | |
| 8803 // Rotate Left by variable | |
| 8804 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr) | |
| 8805 %{ | |
| 8806 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift)))); | |
| 8807 | |
| 8808 expand %{ | |
| 8809 rolL_rReg_CL(dst, shift, cr); | |
| 8810 %} | |
| 8811 %} | |
| 8812 | |
| 8813 // ROR expand | |
| 8814 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr) | |
| 8815 %{ | |
| 8816 effect(USE_DEF dst, KILL cr); | |
| 8817 | |
| 8818 format %{ "rorq $dst" %} | |
| 8819 opcode(0xD1, 0x1); /* D1 /1 */ | |
| 8820 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8821 ins_pipe(ialu_reg); | |
| 8822 %} | |
| 8823 | |
| 8824 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) | |
| 8825 %{ | |
| 8826 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8827 | |
| 8828 format %{ "rorq $dst, $shift" %} | |
| 8829 opcode(0xC1, 0x1); /* C1 /1 ib */ | |
| 8830 ins_encode(reg_opc_imm_wide(dst, shift)); | |
| 8831 ins_pipe(ialu_reg); | |
| 8832 %} | |
| 8833 | |
| 8834 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 8835 %{ | |
| 8836 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8837 | |
| 8838 format %{ "rorq $dst, $shift" %} | |
| 8839 opcode(0xD3, 0x1); /* D3 /1 */ | |
| 8840 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8841 ins_pipe(ialu_reg_reg); | |
| 8842 %} | |
| 8843 // end of ROR expand | |
| 8844 | |
| 8845 // Rotate Right by one | |
| 8846 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr) | |
| 8847 %{ | |
| 8848 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift))); | |
| 8849 | |
| 8850 expand %{ | |
| 8851 rorL_rReg_imm1(dst, cr); | |
| 8852 %} | |
| 8853 %} | |
| 8854 | |
| 8855 // Rotate Right by 8-bit immediate | |
| 8856 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr) | |
| 8857 %{ | |
| 8858 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f)); | |
| 8859 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift))); | |
| 8860 | |
| 8861 expand %{ | |
| 8862 rorL_rReg_imm8(dst, rshift, cr); | |
| 8863 %} | |
| 8864 %} | |
| 8865 | |
| 8866 // Rotate Right by variable | |
| 8867 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
| 8868 %{ | |
| 8869 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift)))); | |
| 8870 | |
| 8871 expand %{ | |
| 8872 rorL_rReg_CL(dst, shift, cr); | |
| 8873 %} | |
| 8874 %} | |
| 8875 | |
| 8876 // Rotate Right by variable | |
| 8877 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr) | |
| 8878 %{ | |
| 8879 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift)))); | |
| 8880 | |
| 8881 expand %{ | |
| 8882 rorL_rReg_CL(dst, shift, cr); | |
| 8883 %} | |
| 8884 %} | |
| 8885 | |
| 8886 // Logical Instructions | |
| 8887 | |
| 8888 // Integer Logical Instructions | |
| 8889 | |
| 8890 // And Instructions | |
| 8891 // And Register with Register | |
| 8892 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 8893 %{ | |
| 8894 match(Set dst (AndI dst src)); | |
| 8895 effect(KILL cr); | |
| 8896 | |
| 8897 format %{ "andl $dst, $src\t# int" %} | |
| 8898 opcode(0x23); | |
| 8899 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 8900 ins_pipe(ialu_reg_reg); | |
| 8901 %} | |
| 8902 | |
| 8903 // And Register with Immediate 255 | |
| 8904 instruct andI_rReg_imm255(rRegI dst, immI_255 src) | |
| 8905 %{ | |
| 8906 match(Set dst (AndI dst src)); | |
| 8907 | |
| 8908 format %{ "movzbl $dst, $dst\t# int & 0xFF" %} | |
| 8909 opcode(0x0F, 0xB6); | |
| 8910 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 8911 ins_pipe(ialu_reg); | |
| 8912 %} | |
| 8913 | |
| 8914 // And Register with Immediate 255 and promote to long | |
| 8915 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask) | |
| 8916 %{ | |
| 8917 match(Set dst (ConvI2L (AndI src mask))); | |
| 8918 | |
| 8919 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %} | |
| 8920 opcode(0x0F, 0xB6); | |
| 8921 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 8922 ins_pipe(ialu_reg); | |
| 8923 %} | |
| 8924 | |
| 8925 // And Register with Immediate 65535 | |
| 8926 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src) | |
| 8927 %{ | |
| 8928 match(Set dst (AndI dst src)); | |
| 8929 | |
| 8930 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %} | |
| 8931 opcode(0x0F, 0xB7); | |
| 8932 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 8933 ins_pipe(ialu_reg); | |
| 8934 %} | |
| 8935 | |
| 8936 // And Register with Immediate 65535 and promote to long | |
| 8937 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask) | |
| 8938 %{ | |
| 8939 match(Set dst (ConvI2L (AndI src mask))); | |
| 8940 | |
| 8941 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %} | |
| 8942 opcode(0x0F, 0xB7); | |
| 8943 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 8944 ins_pipe(ialu_reg); | |
| 8945 %} | |
| 8946 | |
| 8947 // And Register with Immediate | |
| 8948 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 8949 %{ | |
| 8950 match(Set dst (AndI dst src)); | |
| 8951 effect(KILL cr); | |
| 8952 | |
| 8953 format %{ "andl $dst, $src\t# int" %} | |
| 8954 opcode(0x81, 0x04); /* Opcode 81 /4 */ | |
| 8955 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 8956 ins_pipe(ialu_reg); | |
| 8957 %} | |
| 8958 | |
| 8959 // And Register with Memory | |
| 8960 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 8961 %{ | |
| 8962 match(Set dst (AndI dst (LoadI src))); | |
| 8963 effect(KILL cr); | |
| 8964 | |
| 8965 ins_cost(125); | |
| 8966 format %{ "andl $dst, $src\t# int" %} | |
| 8967 opcode(0x23); | |
| 8968 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 8969 ins_pipe(ialu_reg_mem); | |
| 8970 %} | |
| 8971 | |
| 8972 // And Memory with Register | |
| 8973 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 8974 %{ | |
| 8975 match(Set dst (StoreI dst (AndI (LoadI dst) src))); | |
| 8976 effect(KILL cr); | |
| 8977 | |
| 8978 ins_cost(150); | |
| 8979 format %{ "andl $dst, $src\t# int" %} | |
| 8980 opcode(0x21); /* Opcode 21 /r */ | |
| 8981 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 8982 ins_pipe(ialu_mem_reg); | |
| 8983 %} | |
| 8984 | |
| 8985 // And Memory with Immediate | |
| 8986 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 8987 %{ | |
| 8988 match(Set dst (StoreI dst (AndI (LoadI dst) src))); | |
| 8989 effect(KILL cr); | |
| 8990 | |
| 8991 ins_cost(125); | |
| 8992 format %{ "andl $dst, $src\t# int" %} | |
| 8993 opcode(0x81, 0x4); /* Opcode 81 /4 id */ | |
| 8994 ins_encode(REX_mem(dst), OpcSE(src), | |
| 8995 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 8996 ins_pipe(ialu_mem_imm); | |
| 8997 %} | |
| 8998 | |
| 8999 // Or Instructions | |
| 9000 // Or Register with Register | |
| 9001 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 9002 %{ | |
| 9003 match(Set dst (OrI dst src)); | |
| 9004 effect(KILL cr); | |
| 9005 | |
| 9006 format %{ "orl $dst, $src\t# int" %} | |
| 9007 opcode(0x0B); | |
| 9008 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 9009 ins_pipe(ialu_reg_reg); | |
| 9010 %} | |
| 9011 | |
| 9012 // Or Register with Immediate | |
| 9013 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 9014 %{ | |
| 9015 match(Set dst (OrI dst src)); | |
| 9016 effect(KILL cr); | |
| 9017 | |
| 9018 format %{ "orl $dst, $src\t# int" %} | |
| 9019 opcode(0x81, 0x01); /* Opcode 81 /1 id */ | |
| 9020 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 9021 ins_pipe(ialu_reg); | |
| 9022 %} | |
| 9023 | |
| 9024 // Or Register with Memory | |
| 9025 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 9026 %{ | |
| 9027 match(Set dst (OrI dst (LoadI src))); | |
| 9028 effect(KILL cr); | |
| 9029 | |
| 9030 ins_cost(125); | |
| 9031 format %{ "orl $dst, $src\t# int" %} | |
| 9032 opcode(0x0B); | |
| 9033 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 9034 ins_pipe(ialu_reg_mem); | |
| 9035 %} | |
| 9036 | |
| 9037 // Or Memory with Register | |
| 9038 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 9039 %{ | |
| 9040 match(Set dst (StoreI dst (OrI (LoadI dst) src))); | |
| 9041 effect(KILL cr); | |
| 9042 | |
| 9043 ins_cost(150); | |
| 9044 format %{ "orl $dst, $src\t# int" %} | |
| 9045 opcode(0x09); /* Opcode 09 /r */ | |
| 9046 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 9047 ins_pipe(ialu_mem_reg); | |
| 9048 %} | |
| 9049 | |
| 9050 // Or Memory with Immediate | |
| 9051 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 9052 %{ | |
| 9053 match(Set dst (StoreI dst (OrI (LoadI dst) src))); | |
| 9054 effect(KILL cr); | |
| 9055 | |
| 9056 ins_cost(125); | |
| 9057 format %{ "orl $dst, $src\t# int" %} | |
| 9058 opcode(0x81, 0x1); /* Opcode 81 /1 id */ | |
| 9059 ins_encode(REX_mem(dst), OpcSE(src), | |
| 9060 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 9061 ins_pipe(ialu_mem_imm); | |
| 9062 %} | |
| 9063 | |
| 9064 // Xor Instructions | |
| 9065 // Xor Register with Register | |
| 9066 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 9067 %{ | |
| 9068 match(Set dst (XorI dst src)); | |
| 9069 effect(KILL cr); | |
| 9070 | |
| 9071 format %{ "xorl $dst, $src\t# int" %} | |
| 9072 opcode(0x33); | |
| 9073 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 9074 ins_pipe(ialu_reg_reg); | |
| 9075 %} | |
| 9076 | |
| 403 | 9077 // Xor Register with Immediate -1 |
| 9078 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{ | |
|
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9079 match(Set dst (XorI dst imm)); |
|
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9080 |
|
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9081 format %{ "not $dst" %} |
| 403 | 9082 ins_encode %{ |
| 9083 __ notl($dst$$Register); | |
| 9084 %} | |
| 9085 ins_pipe(ialu_reg); | |
| 9086 %} | |
| 9087 | |
| 0 | 9088 // Xor Register with Immediate |
| 9089 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 9090 %{ | |
| 9091 match(Set dst (XorI dst src)); | |
| 9092 effect(KILL cr); | |
| 9093 | |
| 9094 format %{ "xorl $dst, $src\t# int" %} | |
| 9095 opcode(0x81, 0x06); /* Opcode 81 /6 id */ | |
| 9096 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 9097 ins_pipe(ialu_reg); | |
| 9098 %} | |
| 9099 | |
| 9100 // Xor Register with Memory | |
| 9101 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 9102 %{ | |
| 9103 match(Set dst (XorI dst (LoadI src))); | |
| 9104 effect(KILL cr); | |
| 9105 | |
| 9106 ins_cost(125); | |
| 9107 format %{ "xorl $dst, $src\t# int" %} | |
| 9108 opcode(0x33); | |
| 9109 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 9110 ins_pipe(ialu_reg_mem); | |
| 9111 %} | |
| 9112 | |
| 9113 // Xor Memory with Register | |
| 9114 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 9115 %{ | |
| 9116 match(Set dst (StoreI dst (XorI (LoadI dst) src))); | |
| 9117 effect(KILL cr); | |
| 9118 | |
| 9119 ins_cost(150); | |
| 9120 format %{ "xorl $dst, $src\t# int" %} | |
| 9121 opcode(0x31); /* Opcode 31 /r */ | |
| 9122 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 9123 ins_pipe(ialu_mem_reg); | |
| 9124 %} | |
| 9125 | |
| 9126 // Xor Memory with Immediate | |
| 9127 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 9128 %{ | |
| 9129 match(Set dst (StoreI dst (XorI (LoadI dst) src))); | |
| 9130 effect(KILL cr); | |
| 9131 | |
| 9132 ins_cost(125); | |
| 9133 format %{ "xorl $dst, $src\t# int" %} | |
| 9134 opcode(0x81, 0x6); /* Opcode 81 /6 id */ | |
| 9135 ins_encode(REX_mem(dst), OpcSE(src), | |
| 9136 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 9137 ins_pipe(ialu_mem_imm); | |
| 9138 %} | |
| 9139 | |
| 9140 | |
| 9141 // Long Logical Instructions | |
| 9142 | |
| 9143 // And Instructions | |
| 9144 // And Register with Register | |
| 9145 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 9146 %{ | |
| 9147 match(Set dst (AndL dst src)); | |
| 9148 effect(KILL cr); | |
| 9149 | |
| 9150 format %{ "andq $dst, $src\t# long" %} | |
| 9151 opcode(0x23); | |
| 9152 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 9153 ins_pipe(ialu_reg_reg); | |
| 9154 %} | |
| 9155 | |
| 9156 // And Register with Immediate 255 | |
| 9157 instruct andL_rReg_imm255(rRegL dst, immL_255 src) | |
| 9158 %{ | |
| 9159 match(Set dst (AndL dst src)); | |
| 9160 | |
|
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9161 format %{ "movzbq $dst, $dst\t# long & 0xFF" %} |
| 0 | 9162 opcode(0x0F, 0xB6); |
| 9163 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 9164 ins_pipe(ialu_reg); | |
| 9165 %} | |
| 9166 | |
| 9167 // And Register with Immediate 65535 | |
|
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9168 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src) |
| 0 | 9169 %{ |
| 9170 match(Set dst (AndL dst src)); | |
| 9171 | |
| 9172 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %} | |
| 9173 opcode(0x0F, 0xB7); | |
| 9174 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 9175 ins_pipe(ialu_reg); | |
| 9176 %} | |
| 9177 | |
| 9178 // And Register with Immediate | |
| 9179 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
| 9180 %{ | |
| 9181 match(Set dst (AndL dst src)); | |
| 9182 effect(KILL cr); | |
| 9183 | |
| 9184 format %{ "andq $dst, $src\t# long" %} | |
| 9185 opcode(0x81, 0x04); /* Opcode 81 /4 */ | |
| 9186 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 9187 ins_pipe(ialu_reg); | |
| 9188 %} | |
| 9189 | |
| 9190 // And Register with Memory | |
| 9191 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 9192 %{ | |
| 9193 match(Set dst (AndL dst (LoadL src))); | |
| 9194 effect(KILL cr); | |
| 9195 | |
| 9196 ins_cost(125); | |
| 9197 format %{ "andq $dst, $src\t# long" %} | |
| 9198 opcode(0x23); | |
| 9199 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 9200 ins_pipe(ialu_reg_mem); | |
| 9201 %} | |
| 9202 | |
| 9203 // And Memory with Register | |
| 9204 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 9205 %{ | |
| 9206 match(Set dst (StoreL dst (AndL (LoadL dst) src))); | |
| 9207 effect(KILL cr); | |
| 9208 | |
| 9209 ins_cost(150); | |
| 9210 format %{ "andq $dst, $src\t# long" %} | |
| 9211 opcode(0x21); /* Opcode 21 /r */ | |
| 9212 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 9213 ins_pipe(ialu_mem_reg); | |
| 9214 %} | |
| 9215 | |
| 9216 // And Memory with Immediate | |
| 9217 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 9218 %{ | |
| 9219 match(Set dst (StoreL dst (AndL (LoadL dst) src))); | |
| 9220 effect(KILL cr); | |
| 9221 | |
| 9222 ins_cost(125); | |
| 9223 format %{ "andq $dst, $src\t# long" %} | |
| 9224 opcode(0x81, 0x4); /* Opcode 81 /4 id */ | |
| 9225 ins_encode(REX_mem_wide(dst), OpcSE(src), | |
| 9226 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 9227 ins_pipe(ialu_mem_imm); | |
| 9228 %} | |
| 9229 | |
| 9230 // Or Instructions | |
| 9231 // Or Register with Register | |
| 9232 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 9233 %{ | |
| 9234 match(Set dst (OrL dst src)); | |
| 9235 effect(KILL cr); | |
| 9236 | |
| 9237 format %{ "orq $dst, $src\t# long" %} | |
| 9238 opcode(0x0B); | |
| 9239 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 9240 ins_pipe(ialu_reg_reg); | |
| 9241 %} | |
| 9242 | |
|
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9243 // Use any_RegP to match R15 (TLS register) without spilling. |
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9244 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{ |
|
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9245 match(Set dst (OrL dst (CastP2X src))); |
|
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9246 effect(KILL cr); |
|
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9247 |
|
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9248 format %{ "orq $dst, $src\t# long" %} |
|
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9249 opcode(0x0B); |
|
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9250 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); |
|
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9251 ins_pipe(ialu_reg_reg); |
|
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9252 %} |
|
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9253 |
|
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9254 |
| 0 | 9255 // Or Register with Immediate |
| 9256 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
| 9257 %{ | |
| 9258 match(Set dst (OrL dst src)); | |
| 9259 effect(KILL cr); | |
| 9260 | |
| 9261 format %{ "orq $dst, $src\t# long" %} | |
| 9262 opcode(0x81, 0x01); /* Opcode 81 /1 id */ | |
| 9263 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 9264 ins_pipe(ialu_reg); | |
| 9265 %} | |
| 9266 | |
| 9267 // Or Register with Memory | |
| 9268 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 9269 %{ | |
| 9270 match(Set dst (OrL dst (LoadL src))); | |
| 9271 effect(KILL cr); | |
| 9272 | |
| 9273 ins_cost(125); | |
| 9274 format %{ "orq $dst, $src\t# long" %} | |
| 9275 opcode(0x0B); | |
| 9276 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 9277 ins_pipe(ialu_reg_mem); | |
| 9278 %} | |
| 9279 | |
| 9280 // Or Memory with Register | |
| 9281 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 9282 %{ | |
| 9283 match(Set dst (StoreL dst (OrL (LoadL dst) src))); | |
| 9284 effect(KILL cr); | |
| 9285 | |
| 9286 ins_cost(150); | |
| 9287 format %{ "orq $dst, $src\t# long" %} | |
| 9288 opcode(0x09); /* Opcode 09 /r */ | |
| 9289 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 9290 ins_pipe(ialu_mem_reg); | |
| 9291 %} | |
| 9292 | |
| 9293 // Or Memory with Immediate | |
| 9294 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 9295 %{ | |
| 9296 match(Set dst (StoreL dst (OrL (LoadL dst) src))); | |
| 9297 effect(KILL cr); | |
| 9298 | |
| 9299 ins_cost(125); | |
| 9300 format %{ "orq $dst, $src\t# long" %} | |
| 9301 opcode(0x81, 0x1); /* Opcode 81 /1 id */ | |
| 9302 ins_encode(REX_mem_wide(dst), OpcSE(src), | |
| 9303 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 9304 ins_pipe(ialu_mem_imm); | |
| 9305 %} | |
| 9306 | |
| 9307 // Xor Instructions | |
| 9308 // Xor Register with Register | |
| 9309 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 9310 %{ | |
| 9311 match(Set dst (XorL dst src)); | |
| 9312 effect(KILL cr); | |
| 9313 | |
| 9314 format %{ "xorq $dst, $src\t# long" %} | |
| 9315 opcode(0x33); | |
| 9316 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 9317 ins_pipe(ialu_reg_reg); | |
| 9318 %} | |
| 9319 | |
| 403 | 9320 // Xor Register with Immediate -1 |
| 9321 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{ | |
|
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9322 match(Set dst (XorL dst imm)); |
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9323 |
|
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|
9324 format %{ "notq $dst" %} |
| 403 | 9325 ins_encode %{ |
| 9326 __ notq($dst$$Register); | |
| 9327 %} | |
| 9328 ins_pipe(ialu_reg); | |
| 9329 %} | |
| 9330 | |
| 0 | 9331 // Xor Register with Immediate |
| 9332 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
| 9333 %{ | |
| 9334 match(Set dst (XorL dst src)); | |
| 9335 effect(KILL cr); | |
| 9336 | |
| 9337 format %{ "xorq $dst, $src\t# long" %} | |
| 9338 opcode(0x81, 0x06); /* Opcode 81 /6 id */ | |
| 9339 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 9340 ins_pipe(ialu_reg); | |
| 9341 %} | |
| 9342 | |
| 9343 // Xor Register with Memory | |
| 9344 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 9345 %{ | |
| 9346 match(Set dst (XorL dst (LoadL src))); | |
| 9347 effect(KILL cr); | |
| 9348 | |
| 9349 ins_cost(125); | |
| 9350 format %{ "xorq $dst, $src\t# long" %} | |
| 9351 opcode(0x33); | |
| 9352 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 9353 ins_pipe(ialu_reg_mem); | |
| 9354 %} | |
| 9355 | |
| 9356 // Xor Memory with Register | |
| 9357 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 9358 %{ | |
| 9359 match(Set dst (StoreL dst (XorL (LoadL dst) src))); | |
| 9360 effect(KILL cr); | |
| 9361 | |
| 9362 ins_cost(150); | |
| 9363 format %{ "xorq $dst, $src\t# long" %} | |
| 9364 opcode(0x31); /* Opcode 31 /r */ | |
| 9365 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 9366 ins_pipe(ialu_mem_reg); | |
| 9367 %} | |
| 9368 | |
| 9369 // Xor Memory with Immediate | |
| 9370 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 9371 %{ | |
| 9372 match(Set dst (StoreL dst (XorL (LoadL dst) src))); | |
| 9373 effect(KILL cr); | |
| 9374 | |
| 9375 ins_cost(125); | |
| 9376 format %{ "xorq $dst, $src\t# long" %} | |
| 9377 opcode(0x81, 0x6); /* Opcode 81 /6 id */ | |
| 9378 ins_encode(REX_mem_wide(dst), OpcSE(src), | |
| 9379 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 9380 ins_pipe(ialu_mem_imm); | |
| 9381 %} | |
| 9382 | |
| 9383 // Convert Int to Boolean | |
| 9384 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr) | |
| 9385 %{ | |
| 9386 match(Set dst (Conv2B src)); | |
| 9387 effect(KILL cr); | |
| 9388 | |
| 9389 format %{ "testl $src, $src\t# ci2b\n\t" | |
| 9390 "setnz $dst\n\t" | |
| 9391 "movzbl $dst, $dst" %} | |
| 9392 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl | |
| 9393 setNZ_reg(dst), | |
| 9394 REX_reg_breg(dst, dst), // movzbl | |
| 9395 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst)); | |
| 9396 ins_pipe(pipe_slow); // XXX | |
| 9397 %} | |
| 9398 | |
| 9399 // Convert Pointer to Boolean | |
| 9400 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr) | |
| 9401 %{ | |
| 9402 match(Set dst (Conv2B src)); | |
| 9403 effect(KILL cr); | |
| 9404 | |
| 9405 format %{ "testq $src, $src\t# cp2b\n\t" | |
| 9406 "setnz $dst\n\t" | |
| 9407 "movzbl $dst, $dst" %} | |
| 9408 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq | |
| 9409 setNZ_reg(dst), | |
| 9410 REX_reg_breg(dst, dst), // movzbl | |
| 9411 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst)); | |
| 9412 ins_pipe(pipe_slow); // XXX | |
| 9413 %} | |
| 9414 | |
| 9415 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr) | |
| 9416 %{ | |
| 9417 match(Set dst (CmpLTMask p q)); | |
| 9418 effect(KILL cr); | |
| 9419 | |
| 9420 ins_cost(400); // XXX | |
| 9421 format %{ "cmpl $p, $q\t# cmpLTMask\n\t" | |
| 9422 "setlt $dst\n\t" | |
| 9423 "movzbl $dst, $dst\n\t" | |
| 9424 "negl $dst" %} | |
| 9425 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl | |
| 9426 setLT_reg(dst), | |
| 9427 REX_reg_breg(dst, dst), // movzbl | |
| 9428 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst), | |
| 9429 neg_reg(dst)); | |
| 9430 ins_pipe(pipe_slow); | |
| 9431 %} | |
| 9432 | |
| 9433 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr) | |
| 9434 %{ | |
| 9435 match(Set dst (CmpLTMask dst zero)); | |
| 9436 effect(KILL cr); | |
| 9437 | |
| 9438 ins_cost(100); // XXX | |
| 9439 format %{ "sarl $dst, #31\t# cmpLTMask0" %} | |
| 9440 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 9441 ins_encode(reg_opc_imm(dst, 0x1F)); | |
| 9442 ins_pipe(ialu_reg); | |
| 9443 %} | |
| 9444 | |
| 9445 | |
|
3738
c7c81f18c834
7048332: Cadd_cmpLTMask doesn't handle 64-bit tmp register properly
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parents:
2404
diff
changeset
|
9446 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rRegI tmp, rFlagsReg cr) |
| 0 | 9447 %{ |
| 9448 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); | |
| 9449 effect(TEMP tmp, KILL cr); | |
| 9450 | |
| 9451 ins_cost(400); // XXX | |
| 9452 format %{ "subl $p, $q\t# cadd_cmpLTMask1\n\t" | |
| 9453 "sbbl $tmp, $tmp\n\t" | |
| 9454 "andl $tmp, $y\n\t" | |
| 9455 "addl $p, $tmp" %} | |
|
3738
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diff
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|
9456 ins_encode %{ |
|
c7c81f18c834
7048332: Cadd_cmpLTMask doesn't handle 64-bit tmp register properly
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diff
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|
9457 Register Rp = $p$$Register; |
|
c7c81f18c834
7048332: Cadd_cmpLTMask doesn't handle 64-bit tmp register properly
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2404
diff
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|
9458 Register Rq = $q$$Register; |
|
c7c81f18c834
7048332: Cadd_cmpLTMask doesn't handle 64-bit tmp register properly
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2404
diff
changeset
|
9459 Register Ry = $y$$Register; |
|
c7c81f18c834
7048332: Cadd_cmpLTMask doesn't handle 64-bit tmp register properly
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2404
diff
changeset
|
9460 Register Rt = $tmp$$Register; |
|
c7c81f18c834
7048332: Cadd_cmpLTMask doesn't handle 64-bit tmp register properly
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parents:
2404
diff
changeset
|
9461 __ subl(Rp, Rq); |
|
c7c81f18c834
7048332: Cadd_cmpLTMask doesn't handle 64-bit tmp register properly
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parents:
2404
diff
changeset
|
9462 __ sbbl(Rt, Rt); |
|
c7c81f18c834
7048332: Cadd_cmpLTMask doesn't handle 64-bit tmp register properly
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parents:
2404
diff
changeset
|
9463 __ andl(Rt, Ry); |
|
c7c81f18c834
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parents:
2404
diff
changeset
|
9464 __ addl(Rp, Rt); |
|
c7c81f18c834
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2404
diff
changeset
|
9465 %} |
| 0 | 9466 ins_pipe(pipe_cmplt); |
| 9467 %} | |
| 9468 | |
| 9469 //---------- FP Instructions------------------------------------------------ | |
| 9470 | |
| 9471 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2) | |
| 9472 %{ | |
| 9473 match(Set cr (CmpF src1 src2)); | |
| 9474 | |
| 9475 ins_cost(145); | |
| 9476 format %{ "ucomiss $src1, $src2\n\t" | |
| 9477 "jnp,s exit\n\t" | |
| 9478 "pushfq\t# saw NaN, set CF\n\t" | |
| 9479 "andq [rsp], #0xffffff2b\n\t" | |
| 9480 "popfq\n" | |
| 4759 | 9481 "exit:" %} |
| 9482 ins_encode %{ | |
| 9483 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9484 emit_cmpfp_fixup(_masm); | |
| 9485 %} | |
| 0 | 9486 ins_pipe(pipe_slow); |
| 9487 %} | |
| 9488 | |
|
415
4d9884b01ba6
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changeset
|
9489 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{ |
|
4d9884b01ba6
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403
diff
changeset
|
9490 match(Set cr (CmpF src1 src2)); |
|
4d9884b01ba6
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403
diff
changeset
|
9491 |
| 4759 | 9492 ins_cost(100); |
|
415
4d9884b01ba6
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never
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403
diff
changeset
|
9493 format %{ "ucomiss $src1, $src2" %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
9494 ins_encode %{ |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
9495 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9496 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9497 ins_pipe(pipe_slow); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9498 %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
9499 |
| 0 | 9500 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2) |
| 9501 %{ | |
| 9502 match(Set cr (CmpF src1 (LoadF src2))); | |
| 9503 | |
| 9504 ins_cost(145); | |
| 9505 format %{ "ucomiss $src1, $src2\n\t" | |
| 9506 "jnp,s exit\n\t" | |
| 9507 "pushfq\t# saw NaN, set CF\n\t" | |
| 9508 "andq [rsp], #0xffffff2b\n\t" | |
| 9509 "popfq\n" | |
| 4759 | 9510 "exit:" %} |
| 9511 ins_encode %{ | |
| 9512 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 9513 emit_cmpfp_fixup(_masm); | |
| 9514 %} | |
| 0 | 9515 ins_pipe(pipe_slow); |
| 9516 %} | |
| 9517 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9518 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9519 match(Set cr (CmpF src1 (LoadF src2))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9520 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9521 ins_cost(100); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9522 format %{ "ucomiss $src1, $src2" %} |
| 4759 | 9523 ins_encode %{ |
| 9524 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 9525 %} | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9526 ins_pipe(pipe_slow); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9527 %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
9528 |
| 2008 | 9529 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{ |
| 9530 match(Set cr (CmpF src con)); | |
| 0 | 9531 |
| 9532 ins_cost(145); | |
| 2008 | 9533 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t" |
| 0 | 9534 "jnp,s exit\n\t" |
| 9535 "pushfq\t# saw NaN, set CF\n\t" | |
| 9536 "andq [rsp], #0xffffff2b\n\t" | |
| 9537 "popfq\n" | |
| 4759 | 9538 "exit:" %} |
| 2008 | 9539 ins_encode %{ |
| 9540 __ ucomiss($src$$XMMRegister, $constantaddress($con)); | |
| 3783 | 9541 emit_cmpfp_fixup(_masm); |
| 2008 | 9542 %} |
| 9543 ins_pipe(pipe_slow); | |
| 9544 %} | |
| 9545 | |
| 9546 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{ | |
| 9547 match(Set cr (CmpF src con)); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9548 ins_cost(100); |
| 2008 | 9549 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %} |
| 9550 ins_encode %{ | |
| 9551 __ ucomiss($src$$XMMRegister, $constantaddress($con)); | |
| 9552 %} | |
|
415
4d9884b01ba6
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never
parents:
403
diff
changeset
|
9553 ins_pipe(pipe_slow); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9554 %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
9555 |
| 0 | 9556 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2) |
| 9557 %{ | |
| 9558 match(Set cr (CmpD src1 src2)); | |
| 9559 | |
| 9560 ins_cost(145); | |
| 9561 format %{ "ucomisd $src1, $src2\n\t" | |
| 9562 "jnp,s exit\n\t" | |
| 9563 "pushfq\t# saw NaN, set CF\n\t" | |
| 9564 "andq [rsp], #0xffffff2b\n\t" | |
| 9565 "popfq\n" | |
| 4759 | 9566 "exit:" %} |
| 9567 ins_encode %{ | |
| 9568 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9569 emit_cmpfp_fixup(_masm); | |
| 9570 %} | |
| 0 | 9571 ins_pipe(pipe_slow); |
| 9572 %} | |
| 9573 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9574 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{ |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
9575 match(Set cr (CmpD src1 src2)); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9576 |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
9577 ins_cost(100); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9578 format %{ "ucomisd $src1, $src2 test" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9579 ins_encode %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9580 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9581 %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
9582 ins_pipe(pipe_slow); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9583 %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
9584 |
| 0 | 9585 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2) |
| 9586 %{ | |
| 9587 match(Set cr (CmpD src1 (LoadD src2))); | |
| 9588 | |
| 9589 ins_cost(145); | |
| 9590 format %{ "ucomisd $src1, $src2\n\t" | |
| 9591 "jnp,s exit\n\t" | |
| 9592 "pushfq\t# saw NaN, set CF\n\t" | |
| 9593 "andq [rsp], #0xffffff2b\n\t" | |
| 9594 "popfq\n" | |
| 4759 | 9595 "exit:" %} |
| 9596 ins_encode %{ | |
| 9597 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9598 emit_cmpfp_fixup(_masm); | |
| 9599 %} | |
| 0 | 9600 ins_pipe(pipe_slow); |
| 9601 %} | |
| 9602 | |
|
415
4d9884b01ba6
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never
parents:
403
diff
changeset
|
9603 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9604 match(Set cr (CmpD src1 (LoadD src2))); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
9605 |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
9606 ins_cost(100); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9607 format %{ "ucomisd $src1, $src2" %} |
| 4759 | 9608 ins_encode %{ |
| 9609 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9610 %} | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
9611 ins_pipe(pipe_slow); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9612 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9613 |
| 2008 | 9614 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{ |
| 9615 match(Set cr (CmpD src con)); | |
| 0 | 9616 |
| 9617 ins_cost(145); | |
| 2008 | 9618 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 9619 "jnp,s exit\n\t" |
| 9620 "pushfq\t# saw NaN, set CF\n\t" | |
| 9621 "andq [rsp], #0xffffff2b\n\t" | |
| 9622 "popfq\n" | |
| 4759 | 9623 "exit:" %} |
| 2008 | 9624 ins_encode %{ |
| 9625 __ ucomisd($src$$XMMRegister, $constantaddress($con)); | |
| 3783 | 9626 emit_cmpfp_fixup(_masm); |
| 2008 | 9627 %} |
| 9628 ins_pipe(pipe_slow); | |
| 9629 %} | |
| 9630 | |
| 9631 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{ | |
| 9632 match(Set cr (CmpD src con)); | |
|
415
4d9884b01ba6
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parents:
403
diff
changeset
|
9633 ins_cost(100); |
| 2008 | 9634 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %} |
| 9635 ins_encode %{ | |
| 9636 __ ucomisd($src$$XMMRegister, $constantaddress($con)); | |
| 9637 %} | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9638 ins_pipe(pipe_slow); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9639 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9640 |
| 0 | 9641 // Compare into -1,0,1 |
| 9642 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr) | |
| 9643 %{ | |
| 9644 match(Set dst (CmpF3 src1 src2)); | |
| 9645 effect(KILL cr); | |
| 9646 | |
| 9647 ins_cost(275); | |
| 9648 format %{ "ucomiss $src1, $src2\n\t" | |
| 9649 "movl $dst, #-1\n\t" | |
| 9650 "jp,s done\n\t" | |
| 9651 "jb,s done\n\t" | |
| 9652 "setne $dst\n\t" | |
| 9653 "movzbl $dst, $dst\n" | |
| 9654 "done:" %} | |
| 4759 | 9655 ins_encode %{ |
| 9656 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9657 emit_cmpfp3(_masm, $dst$$Register); | |
| 9658 %} | |
| 0 | 9659 ins_pipe(pipe_slow); |
| 9660 %} | |
| 9661 | |
| 9662 // Compare into -1,0,1 | |
| 9663 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr) | |
| 9664 %{ | |
| 9665 match(Set dst (CmpF3 src1 (LoadF src2))); | |
| 9666 effect(KILL cr); | |
| 9667 | |
| 9668 ins_cost(275); | |
| 9669 format %{ "ucomiss $src1, $src2\n\t" | |
| 9670 "movl $dst, #-1\n\t" | |
| 9671 "jp,s done\n\t" | |
| 9672 "jb,s done\n\t" | |
| 9673 "setne $dst\n\t" | |
| 9674 "movzbl $dst, $dst\n" | |
| 9675 "done:" %} | |
| 4759 | 9676 ins_encode %{ |
| 9677 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 9678 emit_cmpfp3(_masm, $dst$$Register); | |
| 9679 %} | |
| 0 | 9680 ins_pipe(pipe_slow); |
| 9681 %} | |
| 9682 | |
| 9683 // Compare into -1,0,1 | |
| 2008 | 9684 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{ |
| 9685 match(Set dst (CmpF3 src con)); | |
| 0 | 9686 effect(KILL cr); |
| 9687 | |
| 9688 ins_cost(275); | |
| 2008 | 9689 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t" |
| 0 | 9690 "movl $dst, #-1\n\t" |
| 9691 "jp,s done\n\t" | |
| 9692 "jb,s done\n\t" | |
| 9693 "setne $dst\n\t" | |
| 9694 "movzbl $dst, $dst\n" | |
| 9695 "done:" %} | |
| 2008 | 9696 ins_encode %{ |
| 9697 __ ucomiss($src$$XMMRegister, $constantaddress($con)); | |
| 4759 | 9698 emit_cmpfp3(_masm, $dst$$Register); |
| 2008 | 9699 %} |
| 0 | 9700 ins_pipe(pipe_slow); |
| 9701 %} | |
| 9702 | |
| 9703 // Compare into -1,0,1 | |
| 9704 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr) | |
| 9705 %{ | |
| 9706 match(Set dst (CmpD3 src1 src2)); | |
| 9707 effect(KILL cr); | |
| 9708 | |
| 9709 ins_cost(275); | |
| 9710 format %{ "ucomisd $src1, $src2\n\t" | |
| 9711 "movl $dst, #-1\n\t" | |
| 9712 "jp,s done\n\t" | |
| 9713 "jb,s done\n\t" | |
| 9714 "setne $dst\n\t" | |
| 9715 "movzbl $dst, $dst\n" | |
| 9716 "done:" %} | |
| 4759 | 9717 ins_encode %{ |
| 9718 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9719 emit_cmpfp3(_masm, $dst$$Register); | |
| 9720 %} | |
| 0 | 9721 ins_pipe(pipe_slow); |
| 9722 %} | |
| 9723 | |
| 9724 // Compare into -1,0,1 | |
| 9725 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr) | |
| 9726 %{ | |
| 9727 match(Set dst (CmpD3 src1 (LoadD src2))); | |
| 9728 effect(KILL cr); | |
| 9729 | |
| 9730 ins_cost(275); | |
| 9731 format %{ "ucomisd $src1, $src2\n\t" | |
| 9732 "movl $dst, #-1\n\t" | |
| 9733 "jp,s done\n\t" | |
| 9734 "jb,s done\n\t" | |
| 9735 "setne $dst\n\t" | |
| 9736 "movzbl $dst, $dst\n" | |
| 9737 "done:" %} | |
| 4759 | 9738 ins_encode %{ |
| 9739 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9740 emit_cmpfp3(_masm, $dst$$Register); | |
| 9741 %} | |
| 0 | 9742 ins_pipe(pipe_slow); |
| 9743 %} | |
| 9744 | |
| 9745 // Compare into -1,0,1 | |
| 2008 | 9746 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{ |
| 9747 match(Set dst (CmpD3 src con)); | |
| 0 | 9748 effect(KILL cr); |
| 9749 | |
| 9750 ins_cost(275); | |
| 2008 | 9751 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 9752 "movl $dst, #-1\n\t" |
| 9753 "jp,s done\n\t" | |
| 9754 "jb,s done\n\t" | |
| 9755 "setne $dst\n\t" | |
| 9756 "movzbl $dst, $dst\n" | |
| 9757 "done:" %} | |
| 2008 | 9758 ins_encode %{ |
| 9759 __ ucomisd($src$$XMMRegister, $constantaddress($con)); | |
| 4759 | 9760 emit_cmpfp3(_masm, $dst$$Register); |
| 2008 | 9761 %} |
| 0 | 9762 ins_pipe(pipe_slow); |
| 9763 %} | |
| 9764 | |
| 9765 // -----------Trig and Trancendental Instructions------------------------------ | |
| 9766 instruct cosD_reg(regD dst) %{ | |
| 9767 match(Set dst (CosD dst)); | |
| 9768 | |
| 9769 format %{ "dcos $dst\n\t" %} | |
| 9770 opcode(0xD9, 0xFF); | |
| 9771 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) ); | |
| 9772 ins_pipe( pipe_slow ); | |
| 9773 %} | |
| 9774 | |
| 9775 instruct sinD_reg(regD dst) %{ | |
| 9776 match(Set dst (SinD dst)); | |
| 9777 | |
| 9778 format %{ "dsin $dst\n\t" %} | |
| 9779 opcode(0xD9, 0xFE); | |
| 9780 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) ); | |
| 9781 ins_pipe( pipe_slow ); | |
| 9782 %} | |
| 9783 | |
| 9784 instruct tanD_reg(regD dst) %{ | |
| 9785 match(Set dst (TanD dst)); | |
| 9786 | |
| 9787 format %{ "dtan $dst\n\t" %} | |
| 9788 ins_encode( Push_SrcXD(dst), | |
| 9789 Opcode(0xD9), Opcode(0xF2), //fptan | |
| 9790 Opcode(0xDD), Opcode(0xD8), //fstp st | |
| 9791 Push_ResultXD(dst) ); | |
| 9792 ins_pipe( pipe_slow ); | |
| 9793 %} | |
| 9794 | |
| 9795 instruct log10D_reg(regD dst) %{ | |
| 9796 // The source and result Double operands in XMM registers | |
| 9797 match(Set dst (Log10D dst)); | |
| 9798 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number | |
| 9799 // fyl2x ; compute log_10(2) * log_2(x) | |
| 9800 format %{ "fldlg2\t\t\t#Log10\n\t" | |
| 9801 "fyl2x\t\t\t# Q=Log10*Log_2(x)\n\t" | |
| 9802 %} | |
| 9803 ins_encode(Opcode(0xD9), Opcode(0xEC), // fldlg2 | |
| 9804 Push_SrcXD(dst), | |
| 9805 Opcode(0xD9), Opcode(0xF1), // fyl2x | |
| 9806 Push_ResultXD(dst)); | |
| 9807 | |
| 9808 ins_pipe( pipe_slow ); | |
| 9809 %} | |
| 9810 | |
| 9811 instruct logD_reg(regD dst) %{ | |
| 9812 // The source and result Double operands in XMM registers | |
| 9813 match(Set dst (LogD dst)); | |
| 9814 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number | |
| 9815 // fyl2x ; compute log_e(2) * log_2(x) | |
| 9816 format %{ "fldln2\t\t\t#Log_e\n\t" | |
| 9817 "fyl2x\t\t\t# Q=Log_e*Log_2(x)\n\t" | |
| 9818 %} | |
| 9819 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 | |
| 9820 Push_SrcXD(dst), | |
| 9821 Opcode(0xD9), Opcode(0xF1), // fyl2x | |
| 9822 Push_ResultXD(dst)); | |
| 9823 ins_pipe( pipe_slow ); | |
| 9824 %} | |
| 9825 | |
| 9826 | |
| 9827 | |
| 9828 //----------Arithmetic Conversion Instructions--------------------------------- | |
| 9829 | |
| 9830 instruct roundFloat_nop(regF dst) | |
| 9831 %{ | |
| 9832 match(Set dst (RoundFloat dst)); | |
| 9833 | |
| 9834 ins_cost(0); | |
| 9835 ins_encode(); | |
| 9836 ins_pipe(empty); | |
| 9837 %} | |
| 9838 | |
| 9839 instruct roundDouble_nop(regD dst) | |
| 9840 %{ | |
| 9841 match(Set dst (RoundDouble dst)); | |
| 9842 | |
| 9843 ins_cost(0); | |
| 9844 ins_encode(); | |
| 9845 ins_pipe(empty); | |
| 9846 %} | |
| 9847 | |
| 9848 instruct convF2D_reg_reg(regD dst, regF src) | |
| 9849 %{ | |
| 9850 match(Set dst (ConvF2D src)); | |
| 9851 | |
| 9852 format %{ "cvtss2sd $dst, $src" %} | |
| 4759 | 9853 ins_encode %{ |
| 9854 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister); | |
| 9855 %} | |
| 0 | 9856 ins_pipe(pipe_slow); // XXX |
| 9857 %} | |
| 9858 | |
| 9859 instruct convF2D_reg_mem(regD dst, memory src) | |
| 9860 %{ | |
| 9861 match(Set dst (ConvF2D (LoadF src))); | |
| 9862 | |
| 9863 format %{ "cvtss2sd $dst, $src" %} | |
| 4759 | 9864 ins_encode %{ |
| 9865 __ cvtss2sd ($dst$$XMMRegister, $src$$Address); | |
| 9866 %} | |
| 0 | 9867 ins_pipe(pipe_slow); // XXX |
| 9868 %} | |
| 9869 | |
| 9870 instruct convD2F_reg_reg(regF dst, regD src) | |
| 9871 %{ | |
| 9872 match(Set dst (ConvD2F src)); | |
| 9873 | |
| 9874 format %{ "cvtsd2ss $dst, $src" %} | |
| 4759 | 9875 ins_encode %{ |
| 9876 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister); | |
| 9877 %} | |
| 0 | 9878 ins_pipe(pipe_slow); // XXX |
| 9879 %} | |
| 9880 | |
| 9881 instruct convD2F_reg_mem(regF dst, memory src) | |
| 9882 %{ | |
| 9883 match(Set dst (ConvD2F (LoadD src))); | |
| 9884 | |
| 9885 format %{ "cvtsd2ss $dst, $src" %} | |
| 4759 | 9886 ins_encode %{ |
| 9887 __ cvtsd2ss ($dst$$XMMRegister, $src$$Address); | |
| 9888 %} | |
| 0 | 9889 ins_pipe(pipe_slow); // XXX |
| 9890 %} | |
| 9891 | |
| 9892 // XXX do mem variants | |
| 9893 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr) | |
| 9894 %{ | |
| 9895 match(Set dst (ConvF2I src)); | |
| 9896 effect(KILL cr); | |
| 9897 | |
| 9898 format %{ "cvttss2sil $dst, $src\t# f2i\n\t" | |
| 9899 "cmpl $dst, #0x80000000\n\t" | |
| 9900 "jne,s done\n\t" | |
| 9901 "subq rsp, #8\n\t" | |
| 9902 "movss [rsp], $src\n\t" | |
| 9903 "call f2i_fixup\n\t" | |
| 9904 "popq $dst\n" | |
| 9905 "done: "%} | |
| 4759 | 9906 ins_encode %{ |
| 9907 Label done; | |
| 9908 __ cvttss2sil($dst$$Register, $src$$XMMRegister); | |
| 9909 __ cmpl($dst$$Register, 0x80000000); | |
| 9910 __ jccb(Assembler::notEqual, done); | |
| 9911 __ subptr(rsp, 8); | |
| 9912 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 9913 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup()))); | |
| 9914 __ pop($dst$$Register); | |
| 9915 __ bind(done); | |
| 9916 %} | |
| 0 | 9917 ins_pipe(pipe_slow); |
| 9918 %} | |
| 9919 | |
| 9920 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr) | |
| 9921 %{ | |
| 9922 match(Set dst (ConvF2L src)); | |
| 9923 effect(KILL cr); | |
| 9924 | |
| 9925 format %{ "cvttss2siq $dst, $src\t# f2l\n\t" | |
| 9926 "cmpq $dst, [0x8000000000000000]\n\t" | |
| 9927 "jne,s done\n\t" | |
| 9928 "subq rsp, #8\n\t" | |
| 9929 "movss [rsp], $src\n\t" | |
| 9930 "call f2l_fixup\n\t" | |
| 9931 "popq $dst\n" | |
| 9932 "done: "%} | |
| 4759 | 9933 ins_encode %{ |
| 9934 Label done; | |
| 9935 __ cvttss2siq($dst$$Register, $src$$XMMRegister); | |
| 9936 __ cmp64($dst$$Register, | |
| 9937 ExternalAddress((address) StubRoutines::x86::double_sign_flip())); | |
| 9938 __ jccb(Assembler::notEqual, done); | |
| 9939 __ subptr(rsp, 8); | |
| 9940 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 9941 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup()))); | |
| 9942 __ pop($dst$$Register); | |
| 9943 __ bind(done); | |
| 9944 %} | |
| 0 | 9945 ins_pipe(pipe_slow); |
| 9946 %} | |
| 9947 | |
| 9948 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr) | |
| 9949 %{ | |
| 9950 match(Set dst (ConvD2I src)); | |
| 9951 effect(KILL cr); | |
| 9952 | |
| 9953 format %{ "cvttsd2sil $dst, $src\t# d2i\n\t" | |
| 9954 "cmpl $dst, #0x80000000\n\t" | |
| 9955 "jne,s done\n\t" | |
| 9956 "subq rsp, #8\n\t" | |
| 9957 "movsd [rsp], $src\n\t" | |
| 9958 "call d2i_fixup\n\t" | |
| 9959 "popq $dst\n" | |
| 9960 "done: "%} | |
| 4759 | 9961 ins_encode %{ |
| 9962 Label done; | |
| 9963 __ cvttsd2sil($dst$$Register, $src$$XMMRegister); | |
| 9964 __ cmpl($dst$$Register, 0x80000000); | |
| 9965 __ jccb(Assembler::notEqual, done); | |
| 9966 __ subptr(rsp, 8); | |
| 9967 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 9968 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup()))); | |
| 9969 __ pop($dst$$Register); | |
| 9970 __ bind(done); | |
| 9971 %} | |
| 0 | 9972 ins_pipe(pipe_slow); |
| 9973 %} | |
| 9974 | |
| 9975 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr) | |
| 9976 %{ | |
| 9977 match(Set dst (ConvD2L src)); | |
| 9978 effect(KILL cr); | |
| 9979 | |
| 9980 format %{ "cvttsd2siq $dst, $src\t# d2l\n\t" | |
| 9981 "cmpq $dst, [0x8000000000000000]\n\t" | |
| 9982 "jne,s done\n\t" | |
| 9983 "subq rsp, #8\n\t" | |
| 9984 "movsd [rsp], $src\n\t" | |
| 9985 "call d2l_fixup\n\t" | |
| 9986 "popq $dst\n" | |
| 9987 "done: "%} | |
| 4759 | 9988 ins_encode %{ |
| 9989 Label done; | |
| 9990 __ cvttsd2siq($dst$$Register, $src$$XMMRegister); | |
| 9991 __ cmp64($dst$$Register, | |
| 9992 ExternalAddress((address) StubRoutines::x86::double_sign_flip())); | |
| 9993 __ jccb(Assembler::notEqual, done); | |
| 9994 __ subptr(rsp, 8); | |
| 9995 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 9996 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup()))); | |
| 9997 __ pop($dst$$Register); | |
| 9998 __ bind(done); | |
| 9999 %} | |
| 0 | 10000 ins_pipe(pipe_slow); |
| 10001 %} | |
| 10002 | |
| 10003 instruct convI2F_reg_reg(regF dst, rRegI src) | |
| 10004 %{ | |
| 71 | 10005 predicate(!UseXmmI2F); |
| 0 | 10006 match(Set dst (ConvI2F src)); |
| 10007 | |
| 10008 format %{ "cvtsi2ssl $dst, $src\t# i2f" %} | |
| 4759 | 10009 ins_encode %{ |
| 10010 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register); | |
| 10011 %} | |
| 0 | 10012 ins_pipe(pipe_slow); // XXX |
| 10013 %} | |
| 10014 | |
| 10015 instruct convI2F_reg_mem(regF dst, memory src) | |
| 10016 %{ | |
| 10017 match(Set dst (ConvI2F (LoadI src))); | |
| 10018 | |
| 10019 format %{ "cvtsi2ssl $dst, $src\t# i2f" %} | |
| 4759 | 10020 ins_encode %{ |
| 10021 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address); | |
| 10022 %} | |
| 0 | 10023 ins_pipe(pipe_slow); // XXX |
| 10024 %} | |
| 10025 | |
| 10026 instruct convI2D_reg_reg(regD dst, rRegI src) | |
| 10027 %{ | |
| 71 | 10028 predicate(!UseXmmI2D); |
| 0 | 10029 match(Set dst (ConvI2D src)); |
| 10030 | |
| 10031 format %{ "cvtsi2sdl $dst, $src\t# i2d" %} | |
| 4759 | 10032 ins_encode %{ |
| 10033 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register); | |
| 10034 %} | |
| 0 | 10035 ins_pipe(pipe_slow); // XXX |
| 10036 %} | |
| 10037 | |
| 10038 instruct convI2D_reg_mem(regD dst, memory src) | |
| 10039 %{ | |
| 10040 match(Set dst (ConvI2D (LoadI src))); | |
| 10041 | |
| 10042 format %{ "cvtsi2sdl $dst, $src\t# i2d" %} | |
| 4759 | 10043 ins_encode %{ |
| 10044 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address); | |
| 10045 %} | |
| 0 | 10046 ins_pipe(pipe_slow); // XXX |
| 10047 %} | |
| 10048 | |
| 71 | 10049 instruct convXI2F_reg(regF dst, rRegI src) |
| 10050 %{ | |
| 10051 predicate(UseXmmI2F); | |
| 10052 match(Set dst (ConvI2F src)); | |
| 10053 | |
| 10054 format %{ "movdl $dst, $src\n\t" | |
| 10055 "cvtdq2psl $dst, $dst\t# i2f" %} | |
| 10056 ins_encode %{ | |
| 10057 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 10058 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister); | |
| 10059 %} | |
| 10060 ins_pipe(pipe_slow); // XXX | |
| 10061 %} | |
| 10062 | |
| 10063 instruct convXI2D_reg(regD dst, rRegI src) | |
| 10064 %{ | |
| 10065 predicate(UseXmmI2D); | |
| 10066 match(Set dst (ConvI2D src)); | |
| 10067 | |
| 10068 format %{ "movdl $dst, $src\n\t" | |
| 10069 "cvtdq2pdl $dst, $dst\t# i2d" %} | |
| 10070 ins_encode %{ | |
| 10071 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 10072 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister); | |
| 10073 %} | |
| 10074 ins_pipe(pipe_slow); // XXX | |
| 10075 %} | |
| 10076 | |
| 0 | 10077 instruct convL2F_reg_reg(regF dst, rRegL src) |
| 10078 %{ | |
| 10079 match(Set dst (ConvL2F src)); | |
| 10080 | |
| 10081 format %{ "cvtsi2ssq $dst, $src\t# l2f" %} | |
| 4759 | 10082 ins_encode %{ |
| 10083 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register); | |
| 10084 %} | |
| 0 | 10085 ins_pipe(pipe_slow); // XXX |
| 10086 %} | |
| 10087 | |
| 10088 instruct convL2F_reg_mem(regF dst, memory src) | |
| 10089 %{ | |
| 10090 match(Set dst (ConvL2F (LoadL src))); | |
| 10091 | |
| 10092 format %{ "cvtsi2ssq $dst, $src\t# l2f" %} | |
| 4759 | 10093 ins_encode %{ |
| 10094 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address); | |
| 10095 %} | |
| 0 | 10096 ins_pipe(pipe_slow); // XXX |
| 10097 %} | |
| 10098 | |
| 10099 instruct convL2D_reg_reg(regD dst, rRegL src) | |
| 10100 %{ | |
| 10101 match(Set dst (ConvL2D src)); | |
| 10102 | |
| 10103 format %{ "cvtsi2sdq $dst, $src\t# l2d" %} | |
| 4759 | 10104 ins_encode %{ |
| 10105 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register); | |
| 10106 %} | |
| 0 | 10107 ins_pipe(pipe_slow); // XXX |
| 10108 %} | |
| 10109 | |
| 10110 instruct convL2D_reg_mem(regD dst, memory src) | |
| 10111 %{ | |
| 10112 match(Set dst (ConvL2D (LoadL src))); | |
| 10113 | |
| 10114 format %{ "cvtsi2sdq $dst, $src\t# l2d" %} | |
| 4759 | 10115 ins_encode %{ |
| 10116 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address); | |
| 10117 %} | |
| 0 | 10118 ins_pipe(pipe_slow); // XXX |
| 10119 %} | |
| 10120 | |
| 10121 instruct convI2L_reg_reg(rRegL dst, rRegI src) | |
| 10122 %{ | |
| 10123 match(Set dst (ConvI2L src)); | |
| 10124 | |
| 10125 ins_cost(125); | |
| 10126 format %{ "movslq $dst, $src\t# i2l" %} | |
| 824 | 10127 ins_encode %{ |
| 10128 __ movslq($dst$$Register, $src$$Register); | |
| 10129 %} | |
| 0 | 10130 ins_pipe(ialu_reg_reg); |
| 10131 %} | |
| 10132 | |
| 10133 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src) | |
| 10134 // %{ | |
| 10135 // match(Set dst (ConvI2L src)); | |
| 10136 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 && | |
| 10137 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0); | |
| 10138 // predicate(((const TypeNode*) n)->type()->is_long()->_hi == | |
| 10139 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi && | |
| 10140 // ((const TypeNode*) n)->type()->is_long()->_lo == | |
| 10141 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo); | |
| 10142 | |
| 10143 // format %{ "movl $dst, $src\t# unsigned i2l" %} | |
| 10144 // ins_encode(enc_copy(dst, src)); | |
| 10145 // // opcode(0x63); // needs REX.W | |
| 10146 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src)); | |
| 10147 // ins_pipe(ialu_reg_reg); | |
| 10148 // %} | |
| 10149 | |
| 10150 // Zero-extend convert int to long | |
| 10151 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask) | |
| 10152 %{ | |
| 10153 match(Set dst (AndL (ConvI2L src) mask)); | |
| 10154 | |
| 10155 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %} | |
| 4759 | 10156 ins_encode %{ |
| 10157 if ($dst$$reg != $src$$reg) { | |
| 10158 __ movl($dst$$Register, $src$$Register); | |
| 10159 } | |
| 10160 %} | |
| 0 | 10161 ins_pipe(ialu_reg_reg); |
| 10162 %} | |
| 10163 | |
| 10164 // Zero-extend convert int to long | |
| 10165 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask) | |
| 10166 %{ | |
| 10167 match(Set dst (AndL (ConvI2L (LoadI src)) mask)); | |
| 10168 | |
| 10169 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %} | |
| 4759 | 10170 ins_encode %{ |
| 10171 __ movl($dst$$Register, $src$$Address); | |
| 10172 %} | |
| 0 | 10173 ins_pipe(ialu_reg_mem); |
| 10174 %} | |
| 10175 | |
| 10176 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask) | |
| 10177 %{ | |
| 10178 match(Set dst (AndL src mask)); | |
| 10179 | |
| 10180 format %{ "movl $dst, $src\t# zero-extend long" %} | |
| 4759 | 10181 ins_encode %{ |
| 10182 __ movl($dst$$Register, $src$$Register); | |
| 10183 %} | |
| 0 | 10184 ins_pipe(ialu_reg_reg); |
| 10185 %} | |
| 10186 | |
| 10187 instruct convL2I_reg_reg(rRegI dst, rRegL src) | |
| 10188 %{ | |
| 10189 match(Set dst (ConvL2I src)); | |
| 10190 | |
| 10191 format %{ "movl $dst, $src\t# l2i" %} | |
| 4759 | 10192 ins_encode %{ |
| 10193 __ movl($dst$$Register, $src$$Register); | |
| 10194 %} | |
| 0 | 10195 ins_pipe(ialu_reg_reg); |
| 10196 %} | |
| 10197 | |
| 10198 | |
| 10199 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{ | |
| 10200 match(Set dst (MoveF2I src)); | |
| 10201 effect(DEF dst, USE src); | |
| 10202 | |
| 10203 ins_cost(125); | |
| 10204 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %} | |
| 4759 | 10205 ins_encode %{ |
| 10206 __ movl($dst$$Register, Address(rsp, $src$$disp)); | |
| 10207 %} | |
| 0 | 10208 ins_pipe(ialu_reg_mem); |
| 10209 %} | |
| 10210 | |
| 10211 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ | |
| 10212 match(Set dst (MoveI2F src)); | |
| 10213 effect(DEF dst, USE src); | |
| 10214 | |
| 10215 ins_cost(125); | |
| 10216 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %} | |
| 4759 | 10217 ins_encode %{ |
| 10218 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 10219 %} | |
| 0 | 10220 ins_pipe(pipe_slow); |
| 10221 %} | |
| 10222 | |
| 10223 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{ | |
| 10224 match(Set dst (MoveD2L src)); | |
| 10225 effect(DEF dst, USE src); | |
| 10226 | |
| 10227 ins_cost(125); | |
| 10228 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %} | |
| 4759 | 10229 ins_encode %{ |
| 10230 __ movq($dst$$Register, Address(rsp, $src$$disp)); | |
| 10231 %} | |
| 0 | 10232 ins_pipe(ialu_reg_mem); |
| 10233 %} | |
| 10234 | |
| 10235 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{ | |
| 10236 predicate(!UseXmmLoadAndClearUpper); | |
| 10237 match(Set dst (MoveL2D src)); | |
| 10238 effect(DEF dst, USE src); | |
| 10239 | |
| 10240 ins_cost(125); | |
| 10241 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %} | |
| 4759 | 10242 ins_encode %{ |
| 10243 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 10244 %} | |
| 0 | 10245 ins_pipe(pipe_slow); |
| 10246 %} | |
| 10247 | |
| 10248 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ | |
| 10249 predicate(UseXmmLoadAndClearUpper); | |
| 10250 match(Set dst (MoveL2D src)); | |
| 10251 effect(DEF dst, USE src); | |
| 10252 | |
| 10253 ins_cost(125); | |
| 10254 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %} | |
| 4759 | 10255 ins_encode %{ |
| 10256 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 10257 %} | |
| 0 | 10258 ins_pipe(pipe_slow); |
| 10259 %} | |
| 10260 | |
| 10261 | |
| 10262 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ | |
| 10263 match(Set dst (MoveF2I src)); | |
| 10264 effect(DEF dst, USE src); | |
| 10265 | |
| 10266 ins_cost(95); // XXX | |
| 10267 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %} | |
| 4759 | 10268 ins_encode %{ |
| 10269 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister); | |
| 10270 %} | |
| 0 | 10271 ins_pipe(pipe_slow); |
| 10272 %} | |
| 10273 | |
| 10274 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{ | |
| 10275 match(Set dst (MoveI2F src)); | |
| 10276 effect(DEF dst, USE src); | |
| 10277 | |
| 10278 ins_cost(100); | |
| 10279 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %} | |
| 4759 | 10280 ins_encode %{ |
| 10281 __ movl(Address(rsp, $dst$$disp), $src$$Register); | |
| 10282 %} | |
| 0 | 10283 ins_pipe( ialu_mem_reg ); |
| 10284 %} | |
| 10285 | |
| 10286 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ | |
| 10287 match(Set dst (MoveD2L src)); | |
| 10288 effect(DEF dst, USE src); | |
| 10289 | |
| 10290 ins_cost(95); // XXX | |
| 10291 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %} | |
| 4759 | 10292 ins_encode %{ |
| 10293 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister); | |
| 10294 %} | |
| 0 | 10295 ins_pipe(pipe_slow); |
| 10296 %} | |
| 10297 | |
| 10298 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{ | |
| 10299 match(Set dst (MoveL2D src)); | |
| 10300 effect(DEF dst, USE src); | |
| 10301 | |
| 10302 ins_cost(100); | |
| 10303 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %} | |
| 4759 | 10304 ins_encode %{ |
| 10305 __ movq(Address(rsp, $dst$$disp), $src$$Register); | |
| 10306 %} | |
| 0 | 10307 ins_pipe(ialu_mem_reg); |
| 10308 %} | |
| 10309 | |
| 10310 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{ | |
| 10311 match(Set dst (MoveF2I src)); | |
| 10312 effect(DEF dst, USE src); | |
| 10313 ins_cost(85); | |
| 10314 format %{ "movd $dst,$src\t# MoveF2I" %} | |
| 4759 | 10315 ins_encode %{ |
| 10316 __ movdl($dst$$Register, $src$$XMMRegister); | |
| 10317 %} | |
| 0 | 10318 ins_pipe( pipe_slow ); |
| 10319 %} | |
| 10320 | |
| 10321 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{ | |
| 10322 match(Set dst (MoveD2L src)); | |
| 10323 effect(DEF dst, USE src); | |
| 10324 ins_cost(85); | |
| 10325 format %{ "movd $dst,$src\t# MoveD2L" %} | |
| 4759 | 10326 ins_encode %{ |
| 10327 __ movdq($dst$$Register, $src$$XMMRegister); | |
| 10328 %} | |
| 0 | 10329 ins_pipe( pipe_slow ); |
| 10330 %} | |
| 10331 | |
| 10332 // The next instructions have long latency and use Int unit. Set high cost. | |
| 10333 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{ | |
| 10334 match(Set dst (MoveI2F src)); | |
| 10335 effect(DEF dst, USE src); | |
| 10336 ins_cost(300); | |
| 10337 format %{ "movd $dst,$src\t# MoveI2F" %} | |
| 4759 | 10338 ins_encode %{ |
| 10339 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 10340 %} | |
| 0 | 10341 ins_pipe( pipe_slow ); |
| 10342 %} | |
| 10343 | |
| 10344 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{ | |
| 10345 match(Set dst (MoveL2D src)); | |
| 10346 effect(DEF dst, USE src); | |
| 10347 ins_cost(300); | |
| 10348 format %{ "movd $dst,$src\t# MoveL2D" %} | |
| 4759 | 10349 ins_encode %{ |
| 10350 __ movdq($dst$$XMMRegister, $src$$Register); | |
| 10351 %} | |
| 0 | 10352 ins_pipe( pipe_slow ); |
| 10353 %} | |
| 10354 | |
| 10355 // Replicate scalar to packed byte (1 byte) values in xmm | |
| 10356 instruct Repl8B_reg(regD dst, regD src) %{ | |
| 10357 match(Set dst (Replicate8B src)); | |
| 10358 format %{ "MOVDQA $dst,$src\n\t" | |
| 10359 "PUNPCKLBW $dst,$dst\n\t" | |
| 10360 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %} | |
| 4759 | 10361 ins_encode %{ |
| 10362 if ($dst$$reg != $src$$reg) { | |
| 10363 __ movdqa($dst$$XMMRegister, $src$$XMMRegister); | |
| 10364 } | |
| 10365 __ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister); | |
| 10366 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); | |
| 10367 %} | |
| 0 | 10368 ins_pipe( pipe_slow ); |
| 10369 %} | |
| 10370 | |
| 10371 // Replicate scalar to packed byte (1 byte) values in xmm | |
| 10372 instruct Repl8B_rRegI(regD dst, rRegI src) %{ | |
| 10373 match(Set dst (Replicate8B src)); | |
| 10374 format %{ "MOVD $dst,$src\n\t" | |
| 10375 "PUNPCKLBW $dst,$dst\n\t" | |
| 10376 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %} | |
| 4759 | 10377 ins_encode %{ |
| 10378 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 10379 __ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister); | |
| 10380 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); | |
| 10381 %} | |
| 0 | 10382 ins_pipe( pipe_slow ); |
| 10383 %} | |
| 10384 | |
| 10385 // Replicate scalar zero to packed byte (1 byte) values in xmm | |
| 10386 instruct Repl8B_immI0(regD dst, immI0 zero) %{ | |
| 10387 match(Set dst (Replicate8B zero)); | |
| 10388 format %{ "PXOR $dst,$dst\t! replicate8B" %} | |
| 4759 | 10389 ins_encode %{ |
| 10390 __ pxor($dst$$XMMRegister, $dst$$XMMRegister); | |
| 10391 %} | |
| 0 | 10392 ins_pipe( fpu_reg_reg ); |
| 10393 %} | |
| 10394 | |
| 10395 // Replicate scalar to packed shore (2 byte) values in xmm | |
| 10396 instruct Repl4S_reg(regD dst, regD src) %{ | |
| 10397 match(Set dst (Replicate4S src)); | |
| 10398 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %} | |
| 4759 | 10399 ins_encode %{ |
| 10400 __ pshuflw($dst$$XMMRegister, $src$$XMMRegister, 0x00); | |
| 10401 %} | |
| 0 | 10402 ins_pipe( fpu_reg_reg ); |
| 10403 %} | |
| 10404 | |
| 10405 // Replicate scalar to packed shore (2 byte) values in xmm | |
| 10406 instruct Repl4S_rRegI(regD dst, rRegI src) %{ | |
| 10407 match(Set dst (Replicate4S src)); | |
| 10408 format %{ "MOVD $dst,$src\n\t" | |
| 10409 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %} | |
| 4759 | 10410 ins_encode %{ |
| 10411 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 10412 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); | |
| 10413 %} | |
| 0 | 10414 ins_pipe( fpu_reg_reg ); |
| 10415 %} | |
| 10416 | |
| 10417 // Replicate scalar zero to packed short (2 byte) values in xmm | |
| 10418 instruct Repl4S_immI0(regD dst, immI0 zero) %{ | |
| 10419 match(Set dst (Replicate4S zero)); | |
| 10420 format %{ "PXOR $dst,$dst\t! replicate4S" %} | |
| 4759 | 10421 ins_encode %{ |
| 10422 __ pxor($dst$$XMMRegister, $dst$$XMMRegister); | |
| 10423 %} | |
| 0 | 10424 ins_pipe( fpu_reg_reg ); |
| 10425 %} | |
| 10426 | |
| 10427 // Replicate scalar to packed char (2 byte) values in xmm | |
| 10428 instruct Repl4C_reg(regD dst, regD src) %{ | |
| 10429 match(Set dst (Replicate4C src)); | |
| 10430 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %} | |
| 4759 | 10431 ins_encode %{ |
| 10432 __ pshuflw($dst$$XMMRegister, $src$$XMMRegister, 0x00); | |
| 10433 %} | |
| 0 | 10434 ins_pipe( fpu_reg_reg ); |
| 10435 %} | |
| 10436 | |
| 10437 // Replicate scalar to packed char (2 byte) values in xmm | |
| 10438 instruct Repl4C_rRegI(regD dst, rRegI src) %{ | |
| 10439 match(Set dst (Replicate4C src)); | |
| 10440 format %{ "MOVD $dst,$src\n\t" | |
| 10441 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %} | |
| 4759 | 10442 ins_encode %{ |
| 10443 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 10444 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); | |
| 10445 %} | |
| 0 | 10446 ins_pipe( fpu_reg_reg ); |
| 10447 %} | |
| 10448 | |
| 10449 // Replicate scalar zero to packed char (2 byte) values in xmm | |
| 10450 instruct Repl4C_immI0(regD dst, immI0 zero) %{ | |
| 10451 match(Set dst (Replicate4C zero)); | |
| 10452 format %{ "PXOR $dst,$dst\t! replicate4C" %} | |
| 4759 | 10453 ins_encode %{ |
| 10454 __ pxor($dst$$XMMRegister, $dst$$XMMRegister); | |
| 10455 %} | |
| 0 | 10456 ins_pipe( fpu_reg_reg ); |
| 10457 %} | |
| 10458 | |
| 10459 // Replicate scalar to packed integer (4 byte) values in xmm | |
| 10460 instruct Repl2I_reg(regD dst, regD src) %{ | |
| 10461 match(Set dst (Replicate2I src)); | |
| 10462 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %} | |
| 4759 | 10463 ins_encode %{ |
| 10464 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0x00); | |
| 10465 %} | |
| 0 | 10466 ins_pipe( fpu_reg_reg ); |
| 10467 %} | |
| 10468 | |
| 10469 // Replicate scalar to packed integer (4 byte) values in xmm | |
| 10470 instruct Repl2I_rRegI(regD dst, rRegI src) %{ | |
| 10471 match(Set dst (Replicate2I src)); | |
| 10472 format %{ "MOVD $dst,$src\n\t" | |
| 10473 "PSHUFD $dst,$dst,0x00\t! replicate2I" %} | |
| 4759 | 10474 ins_encode %{ |
| 10475 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 10476 __ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00); | |
| 10477 %} | |
| 0 | 10478 ins_pipe( fpu_reg_reg ); |
| 10479 %} | |
| 10480 | |
| 10481 // Replicate scalar zero to packed integer (2 byte) values in xmm | |
| 10482 instruct Repl2I_immI0(regD dst, immI0 zero) %{ | |
| 10483 match(Set dst (Replicate2I zero)); | |
| 10484 format %{ "PXOR $dst,$dst\t! replicate2I" %} | |
| 4759 | 10485 ins_encode %{ |
| 10486 __ pxor($dst$$XMMRegister, $dst$$XMMRegister); | |
| 10487 %} | |
| 0 | 10488 ins_pipe( fpu_reg_reg ); |
| 10489 %} | |
| 10490 | |
| 10491 // Replicate scalar to packed single precision floating point values in xmm | |
| 10492 instruct Repl2F_reg(regD dst, regD src) %{ | |
| 10493 match(Set dst (Replicate2F src)); | |
| 10494 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %} | |
| 4759 | 10495 ins_encode %{ |
| 10496 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0xe0); | |
| 10497 %} | |
| 0 | 10498 ins_pipe( fpu_reg_reg ); |
| 10499 %} | |
| 10500 | |
| 10501 // Replicate scalar to packed single precision floating point values in xmm | |
| 10502 instruct Repl2F_regF(regD dst, regF src) %{ | |
| 10503 match(Set dst (Replicate2F src)); | |
| 10504 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %} | |
| 4759 | 10505 ins_encode %{ |
| 10506 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0xe0); | |
| 10507 %} | |
| 0 | 10508 ins_pipe( fpu_reg_reg ); |
| 10509 %} | |
| 10510 | |
| 10511 // Replicate scalar to packed single precision floating point values in xmm | |
| 10512 instruct Repl2F_immF0(regD dst, immF0 zero) %{ | |
| 10513 match(Set dst (Replicate2F zero)); | |
| 10514 format %{ "PXOR $dst,$dst\t! replicate2F" %} | |
| 4759 | 10515 ins_encode %{ |
| 10516 __ pxor($dst$$XMMRegister, $dst$$XMMRegister); | |
| 10517 %} | |
| 0 | 10518 ins_pipe( fpu_reg_reg ); |
| 10519 %} | |
| 10520 | |
| 10521 | |
| 10522 // ======================================================================= | |
| 10523 // fast clearing of an array | |
| 10524 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy, | |
| 10525 rFlagsReg cr) | |
| 10526 %{ | |
| 10527 match(Set dummy (ClearArray cnt base)); | |
| 10528 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr); | |
| 10529 | |
| 10530 format %{ "xorl rax, rax\t# ClearArray:\n\t" | |
| 10531 "rep stosq\t# Store rax to *rdi++ while rcx--" %} | |
| 10532 ins_encode(opc_reg_reg(0x33, RAX, RAX), // xorl %eax, %eax | |
| 10533 Opcode(0xF3), Opcode(0x48), Opcode(0xAB)); // rep REX_W stos | |
| 10534 ins_pipe(pipe_slow); | |
| 10535 %} | |
| 10536 | |
| 2262 | 10537 instruct string_compare(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2, |
| 10538 rax_RegI result, regD tmp1, rFlagsReg cr) | |
|
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10539 %{ |
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10540 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); |
| 2262 | 10541 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr); |
| 10542 | |
| 10543 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %} | |
|
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10544 ins_encode %{ |
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10545 __ string_compare($str1$$Register, $str2$$Register, |
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10546 $cnt1$$Register, $cnt2$$Register, $result$$Register, |
| 2262 | 10547 $tmp1$$XMMRegister); |
|
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10548 %} |
| 681 | 10549 ins_pipe( pipe_slow ); |
| 10550 %} | |
| 10551 | |
|
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10552 // fast search of substring with known size. |
|
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10553 instruct string_indexof_con(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2, |
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10554 rbx_RegI result, regD vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr) |
|
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10555 %{ |
|
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10556 predicate(UseSSE42Intrinsics); |
|
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10557 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2))); |
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10558 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr); |
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|
10559 |
|
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10560 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %} |
|
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|
10561 ins_encode %{ |
|
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|
10562 int icnt2 = (int)$int_cnt2$$constant; |
|
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|
10563 if (icnt2 >= 8) { |
|
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|
10564 // IndexOf for constant substrings with size >= 8 elements |
|
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|
10565 // which don't need to be loaded through stack. |
|
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|
10566 __ string_indexofC8($str1$$Register, $str2$$Register, |
|
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|
10567 $cnt1$$Register, $cnt2$$Register, |
|
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|
10568 icnt2, $result$$Register, |
|
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|
10569 $vec$$XMMRegister, $tmp$$Register); |
|
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|
10570 } else { |
|
41d4973cf100
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diff
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|
10571 // Small strings are loaded through stack if they cross page boundary. |
|
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|
10572 __ string_indexof($str1$$Register, $str2$$Register, |
|
41d4973cf100
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|
10573 $cnt1$$Register, $cnt2$$Register, |
|
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|
10574 icnt2, $result$$Register, |
|
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|
10575 $vec$$XMMRegister, $tmp$$Register); |
|
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|
10576 } |
|
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|
10577 %} |
|
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|
10578 ins_pipe( pipe_slow ); |
|
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|
10579 %} |
|
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|
10580 |
|
986
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|
10581 instruct string_indexof(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2, |
|
2320
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|
10582 rbx_RegI result, regD vec, rcx_RegI tmp, rFlagsReg cr) |
| 681 | 10583 %{ |
| 10584 predicate(UseSSE42Intrinsics); | |
|
986
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|
10585 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2))); |
|
2320
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|
10586 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr); |
|
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|
10587 |
|
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|
10588 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %} |
|
986
62001a362ce9
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diff
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|
10589 ins_encode %{ |
|
62001a362ce9
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diff
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|
10590 __ string_indexof($str1$$Register, $str2$$Register, |
|
2320
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|
10591 $cnt1$$Register, $cnt2$$Register, |
|
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|
10592 (-1), $result$$Register, |
|
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|
10593 $vec$$XMMRegister, $tmp$$Register); |
|
986
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|
10594 %} |
| 681 | 10595 ins_pipe( pipe_slow ); |
| 10596 %} | |
| 10597 | |
| 10598 // fast string equals | |
|
986
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|
10599 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result, |
|
62001a362ce9
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|
10600 regD tmp1, regD tmp2, rbx_RegI tmp3, rFlagsReg cr) |
|
62001a362ce9
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|
10601 %{ |
|
62001a362ce9
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diff
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|
10602 match(Set result (StrEquals (Binary str1 str2) cnt)); |
|
62001a362ce9
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|
10603 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr); |
|
62001a362ce9
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changeset
|
10604 |
|
62001a362ce9
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diff
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|
10605 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %} |
|
62001a362ce9
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|
10606 ins_encode %{ |
|
62001a362ce9
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changeset
|
10607 __ char_arrays_equals(false, $str1$$Register, $str2$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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diff
changeset
|
10608 $cnt$$Register, $result$$Register, $tmp3$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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diff
changeset
|
10609 $tmp1$$XMMRegister, $tmp2$$XMMRegister); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
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diff
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|
10610 %} |
| 0 | 10611 ins_pipe( pipe_slow ); |
| 10612 %} | |
| 10613 | |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
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|
10614 // fast array equals |
|
986
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diff
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|
10615 instruct array_equals(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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|
10616 regD tmp1, regD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr) |
| 681 | 10617 %{ |
|
169
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|
10618 match(Set result (AryEq ary1 ary2)); |
| 681 | 10619 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr); |
|
169
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changeset
|
10620 //ins_cost(300); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
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diff
changeset
|
10621 |
|
986
62001a362ce9
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diff
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|
10622 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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824
diff
changeset
|
10623 ins_encode %{ |
|
62001a362ce9
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824
diff
changeset
|
10624 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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diff
changeset
|
10625 $tmp3$$Register, $result$$Register, $tmp4$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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824
diff
changeset
|
10626 $tmp1$$XMMRegister, $tmp2$$XMMRegister); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
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824
diff
changeset
|
10627 %} |
|
169
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6695049: (coll) Create an x86 intrinsic for Arrays.equals
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parents:
168
diff
changeset
|
10628 ins_pipe( pipe_slow ); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
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168
diff
changeset
|
10629 %} |
|
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|
10630 |
| 0 | 10631 //----------Control Flow Instructions------------------------------------------ |
| 10632 // Signed compare Instructions | |
| 10633 | |
| 10634 // XXX more variants!! | |
| 10635 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2) | |
| 10636 %{ | |
| 10637 match(Set cr (CmpI op1 op2)); | |
| 10638 effect(DEF cr, USE op1, USE op2); | |
| 10639 | |
| 10640 format %{ "cmpl $op1, $op2" %} | |
| 10641 opcode(0x3B); /* Opcode 3B /r */ | |
| 10642 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2)); | |
| 10643 ins_pipe(ialu_cr_reg_reg); | |
| 10644 %} | |
| 10645 | |
| 10646 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2) | |
| 10647 %{ | |
| 10648 match(Set cr (CmpI op1 op2)); | |
| 10649 | |
| 10650 format %{ "cmpl $op1, $op2" %} | |
| 10651 opcode(0x81, 0x07); /* Opcode 81 /7 */ | |
| 10652 ins_encode(OpcSErm(op1, op2), Con8or32(op2)); | |
| 10653 ins_pipe(ialu_cr_reg_imm); | |
| 10654 %} | |
| 10655 | |
| 10656 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2) | |
| 10657 %{ | |
| 10658 match(Set cr (CmpI op1 (LoadI op2))); | |
| 10659 | |
| 10660 ins_cost(500); // XXX | |
| 10661 format %{ "cmpl $op1, $op2" %} | |
| 10662 opcode(0x3B); /* Opcode 3B /r */ | |
| 10663 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 10664 ins_pipe(ialu_cr_reg_mem); | |
| 10665 %} | |
| 10666 | |
| 10667 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero) | |
| 10668 %{ | |
| 10669 match(Set cr (CmpI src zero)); | |
| 10670 | |
| 10671 format %{ "testl $src, $src" %} | |
| 10672 opcode(0x85); | |
| 10673 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src)); | |
| 10674 ins_pipe(ialu_cr_reg_imm); | |
| 10675 %} | |
| 10676 | |
| 10677 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero) | |
| 10678 %{ | |
| 10679 match(Set cr (CmpI (AndI src con) zero)); | |
| 10680 | |
| 10681 format %{ "testl $src, $con" %} | |
| 10682 opcode(0xF7, 0x00); | |
| 10683 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con)); | |
| 10684 ins_pipe(ialu_cr_reg_imm); | |
| 10685 %} | |
| 10686 | |
| 10687 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero) | |
| 10688 %{ | |
| 10689 match(Set cr (CmpI (AndI src (LoadI mem)) zero)); | |
| 10690 | |
| 10691 format %{ "testl $src, $mem" %} | |
| 10692 opcode(0x85); | |
| 10693 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
| 10694 ins_pipe(ialu_cr_reg_mem); | |
| 10695 %} | |
| 10696 | |
| 10697 // Unsigned compare Instructions; really, same as signed except they | |
| 10698 // produce an rFlagsRegU instead of rFlagsReg. | |
| 10699 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2) | |
| 10700 %{ | |
| 10701 match(Set cr (CmpU op1 op2)); | |
| 10702 | |
| 10703 format %{ "cmpl $op1, $op2\t# unsigned" %} | |
| 10704 opcode(0x3B); /* Opcode 3B /r */ | |
| 10705 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2)); | |
| 10706 ins_pipe(ialu_cr_reg_reg); | |
| 10707 %} | |
| 10708 | |
| 10709 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2) | |
| 10710 %{ | |
| 10711 match(Set cr (CmpU op1 op2)); | |
| 10712 | |
| 10713 format %{ "cmpl $op1, $op2\t# unsigned" %} | |
| 10714 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 10715 ins_encode(OpcSErm(op1, op2), Con8or32(op2)); | |
| 10716 ins_pipe(ialu_cr_reg_imm); | |
| 10717 %} | |
| 10718 | |
| 10719 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2) | |
| 10720 %{ | |
| 10721 match(Set cr (CmpU op1 (LoadI op2))); | |
| 10722 | |
| 10723 ins_cost(500); // XXX | |
| 10724 format %{ "cmpl $op1, $op2\t# unsigned" %} | |
| 10725 opcode(0x3B); /* Opcode 3B /r */ | |
| 10726 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 10727 ins_pipe(ialu_cr_reg_mem); | |
| 10728 %} | |
| 10729 | |
| 10730 // // // Cisc-spilled version of cmpU_rReg | |
| 10731 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2) | |
| 10732 // //%{ | |
| 10733 // // match(Set cr (CmpU (LoadI op1) op2)); | |
| 10734 // // | |
| 10735 // // format %{ "CMPu $op1,$op2" %} | |
| 10736 // // ins_cost(500); | |
| 10737 // // opcode(0x39); /* Opcode 39 /r */ | |
| 10738 // // ins_encode( OpcP, reg_mem( op1, op2) ); | |
| 10739 // //%} | |
| 10740 | |
| 10741 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero) | |
| 10742 %{ | |
| 10743 match(Set cr (CmpU src zero)); | |
| 10744 | |
| 10745 format %{ "testl $src, $src\t# unsigned" %} | |
| 10746 opcode(0x85); | |
| 10747 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src)); | |
| 10748 ins_pipe(ialu_cr_reg_imm); | |
| 10749 %} | |
| 10750 | |
| 10751 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2) | |
| 10752 %{ | |
| 10753 match(Set cr (CmpP op1 op2)); | |
| 10754 | |
| 10755 format %{ "cmpq $op1, $op2\t# ptr" %} | |
| 10756 opcode(0x3B); /* Opcode 3B /r */ | |
| 10757 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2)); | |
| 10758 ins_pipe(ialu_cr_reg_reg); | |
| 10759 %} | |
| 10760 | |
| 10761 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2) | |
| 10762 %{ | |
| 10763 match(Set cr (CmpP op1 (LoadP op2))); | |
| 10764 | |
| 10765 ins_cost(500); // XXX | |
| 10766 format %{ "cmpq $op1, $op2\t# ptr" %} | |
| 10767 opcode(0x3B); /* Opcode 3B /r */ | |
| 10768 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 10769 ins_pipe(ialu_cr_reg_mem); | |
| 10770 %} | |
| 10771 | |
| 10772 // // // Cisc-spilled version of cmpP_rReg | |
| 10773 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2) | |
| 10774 // //%{ | |
| 10775 // // match(Set cr (CmpP (LoadP op1) op2)); | |
| 10776 // // | |
| 10777 // // format %{ "CMPu $op1,$op2" %} | |
| 10778 // // ins_cost(500); | |
| 10779 // // opcode(0x39); /* Opcode 39 /r */ | |
| 10780 // // ins_encode( OpcP, reg_mem( op1, op2) ); | |
| 10781 // //%} | |
| 10782 | |
| 10783 // XXX this is generalized by compP_rReg_mem??? | |
| 10784 // Compare raw pointer (used in out-of-heap check). | |
| 10785 // Only works because non-oop pointers must be raw pointers | |
| 10786 // and raw pointers have no anti-dependencies. | |
| 10787 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2) | |
| 10788 %{ | |
| 10789 predicate(!n->in(2)->in(2)->bottom_type()->isa_oop_ptr()); | |
| 10790 match(Set cr (CmpP op1 (LoadP op2))); | |
| 10791 | |
| 10792 format %{ "cmpq $op1, $op2\t# raw ptr" %} | |
| 10793 opcode(0x3B); /* Opcode 3B /r */ | |
| 10794 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 10795 ins_pipe(ialu_cr_reg_mem); | |
| 10796 %} | |
| 10797 | |
| 10798 // This will generate a signed flags result. This should be OK since | |
| 10799 // any compare to a zero should be eq/neq. | |
| 10800 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero) | |
| 10801 %{ | |
| 10802 match(Set cr (CmpP src zero)); | |
| 10803 | |
| 10804 format %{ "testq $src, $src\t# ptr" %} | |
| 10805 opcode(0x85); | |
| 10806 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src)); | |
| 10807 ins_pipe(ialu_cr_reg_imm); | |
| 10808 %} | |
| 10809 | |
| 10810 // This will generate a signed flags result. This should be OK since | |
| 10811 // any compare to a zero should be eq/neq. | |
|
642
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|
10812 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero) |
|
660978a2a31a
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|
10813 %{ |
|
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|
10814 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL)); |
| 0 | 10815 match(Set cr (CmpP (LoadP op) zero)); |
| 10816 | |
| 10817 ins_cost(500); // XXX | |
| 10818 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %} | |
| 10819 opcode(0xF7); /* Opcode F7 /0 */ | |
| 10820 ins_encode(REX_mem_wide(op), | |
| 10821 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF)); | |
| 10822 ins_pipe(ialu_cr_reg_imm); | |
| 10823 %} | |
| 10824 | |
|
642
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10825 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero) |
|
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|
10826 %{ |
|
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|
10827 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
|
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|
10828 match(Set cr (CmpP (LoadP mem) zero)); |
|
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|
10829 |
|
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|
10830 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %} |
|
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|
10831 ins_encode %{ |
|
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diff
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|
10832 __ cmpq(r12, $mem$$Address); |
|
660978a2a31a
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|
10833 %} |
|
660978a2a31a
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|
10834 ins_pipe(ialu_cr_reg_mem); |
|
660978a2a31a
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|
10835 %} |
|
164
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|
10836 |
|
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|
10837 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2) |
|
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|
10838 %{ |
|
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|
10839 match(Set cr (CmpN op1 op2)); |
|
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|
10840 |
|
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|
10841 format %{ "cmpl $op1, $op2\t# compressed ptr" %} |
|
642
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|
10842 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %} |
|
164
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|
10843 ins_pipe(ialu_cr_reg_reg); |
|
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|
10844 %} |
|
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|
10845 |
|
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|
10846 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem) |
|
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|
10847 %{ |
|
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|
10848 match(Set cr (CmpN src (LoadN mem))); |
|
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|
10849 |
|
642
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|
10850 format %{ "cmpl $src, $mem\t# compressed ptr" %} |
|
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|
10851 ins_encode %{ |
|
660978a2a31a
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|
10852 __ cmpl($src$$Register, $mem$$Address); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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|
10853 %} |
|
660978a2a31a
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diff
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|
10854 ins_pipe(ialu_cr_reg_mem); |
|
660978a2a31a
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624
diff
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|
10855 %} |
|
660978a2a31a
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kvn
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624
diff
changeset
|
10856 |
|
660978a2a31a
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624
diff
changeset
|
10857 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{ |
|
660978a2a31a
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|
10858 match(Set cr (CmpN op1 op2)); |
|
660978a2a31a
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624
diff
changeset
|
10859 |
|
660978a2a31a
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diff
changeset
|
10860 format %{ "cmpl $op1, $op2\t# compressed ptr" %} |
|
164
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|
10861 ins_encode %{ |
|
642
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|
10862 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant); |
|
660978a2a31a
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|
10863 %} |
|
660978a2a31a
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|
10864 ins_pipe(ialu_cr_reg_imm); |
|
660978a2a31a
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624
diff
changeset
|
10865 %} |
|
660978a2a31a
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kvn
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624
diff
changeset
|
10866 |
|
660978a2a31a
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diff
changeset
|
10867 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src) |
|
660978a2a31a
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kvn
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|
10868 %{ |
|
660978a2a31a
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|
10869 match(Set cr (CmpN src (LoadN mem))); |
|
660978a2a31a
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kvn
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624
diff
changeset
|
10870 |
|
660978a2a31a
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diff
changeset
|
10871 format %{ "cmpl $mem, $src\t# compressed ptr" %} |
|
660978a2a31a
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|
10872 ins_encode %{ |
|
660978a2a31a
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diff
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|
10873 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant); |
|
164
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|
10874 %} |
|
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|
10875 ins_pipe(ialu_cr_reg_mem); |
|
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|
10876 %} |
|
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|
10877 |
|
113
ba764ed4b6f2
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71
diff
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|
10878 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{ |
|
ba764ed4b6f2
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|
10879 match(Set cr (CmpN src zero)); |
|
ba764ed4b6f2
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71
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|
10880 |
|
164
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|
10881 format %{ "testl $src, $src\t# compressed ptr" %} |
|
113
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|
10882 ins_encode %{ __ testl($src$$Register, $src$$Register); %} |
|
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|
10883 ins_pipe(ialu_cr_reg_imm); |
|
ba764ed4b6f2
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71
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|
10884 %} |
|
ba764ed4b6f2
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71
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changeset
|
10885 |
|
642
660978a2a31a
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624
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changeset
|
10886 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero) |
|
660978a2a31a
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|
10887 %{ |
|
660978a2a31a
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|
10888 predicate(Universe::narrow_oop_base() != NULL); |
|
164
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|
10889 match(Set cr (CmpN (LoadN mem) zero)); |
|
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|
10890 |
|
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|
10891 ins_cost(500); // XXX |
|
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|
10892 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %} |
|
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|
10893 ins_encode %{ |
|
642
660978a2a31a
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|
10894 __ cmpl($mem$$Address, (int)0xFFFFFFFF); |
|
660978a2a31a
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624
diff
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|
10895 %} |
|
660978a2a31a
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624
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|
10896 ins_pipe(ialu_cr_reg_mem); |
|
660978a2a31a
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624
diff
changeset
|
10897 %} |
|
660978a2a31a
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624
diff
changeset
|
10898 |
|
660978a2a31a
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kvn
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624
diff
changeset
|
10899 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero) |
|
660978a2a31a
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kvn
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|
10900 %{ |
|
660978a2a31a
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624
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|
10901 predicate(Universe::narrow_oop_base() == NULL); |
|
660978a2a31a
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|
10902 match(Set cr (CmpN (LoadN mem) zero)); |
|
660978a2a31a
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624
diff
changeset
|
10903 |
|
660978a2a31a
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changeset
|
10904 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %} |
|
660978a2a31a
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kvn
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changeset
|
10905 ins_encode %{ |
|
660978a2a31a
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changeset
|
10906 __ cmpl(r12, $mem$$Address); |
|
164
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|
10907 %} |
|
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|
10908 ins_pipe(ialu_cr_reg_mem); |
|
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|
10909 %} |
|
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|
10910 |
| 0 | 10911 // Yanked all unsigned pointer compare operations. |
| 10912 // Pointer compares are done with CmpP which is already unsigned. | |
| 10913 | |
| 10914 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2) | |
| 10915 %{ | |
| 10916 match(Set cr (CmpL op1 op2)); | |
| 10917 | |
| 10918 format %{ "cmpq $op1, $op2" %} | |
| 10919 opcode(0x3B); /* Opcode 3B /r */ | |
| 10920 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2)); | |
| 10921 ins_pipe(ialu_cr_reg_reg); | |
| 10922 %} | |
| 10923 | |
| 10924 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2) | |
| 10925 %{ | |
| 10926 match(Set cr (CmpL op1 op2)); | |
| 10927 | |
| 10928 format %{ "cmpq $op1, $op2" %} | |
| 10929 opcode(0x81, 0x07); /* Opcode 81 /7 */ | |
| 10930 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2)); | |
| 10931 ins_pipe(ialu_cr_reg_imm); | |
| 10932 %} | |
| 10933 | |
| 10934 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2) | |
| 10935 %{ | |
| 10936 match(Set cr (CmpL op1 (LoadL op2))); | |
| 10937 | |
| 10938 format %{ "cmpq $op1, $op2" %} | |
| 10939 opcode(0x3B); /* Opcode 3B /r */ | |
| 10940 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 10941 ins_pipe(ialu_cr_reg_mem); | |
| 10942 %} | |
| 10943 | |
| 10944 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero) | |
| 10945 %{ | |
| 10946 match(Set cr (CmpL src zero)); | |
| 10947 | |
| 10948 format %{ "testq $src, $src" %} | |
| 10949 opcode(0x85); | |
| 10950 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src)); | |
| 10951 ins_pipe(ialu_cr_reg_imm); | |
| 10952 %} | |
| 10953 | |
| 10954 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero) | |
| 10955 %{ | |
| 10956 match(Set cr (CmpL (AndL src con) zero)); | |
| 10957 | |
| 10958 format %{ "testq $src, $con\t# long" %} | |
| 10959 opcode(0xF7, 0x00); | |
| 10960 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con)); | |
| 10961 ins_pipe(ialu_cr_reg_imm); | |
| 10962 %} | |
| 10963 | |
| 10964 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero) | |
| 10965 %{ | |
| 10966 match(Set cr (CmpL (AndL src (LoadL mem)) zero)); | |
| 10967 | |
| 10968 format %{ "testq $src, $mem" %} | |
| 10969 opcode(0x85); | |
| 10970 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem)); | |
| 10971 ins_pipe(ialu_cr_reg_mem); | |
| 10972 %} | |
| 10973 | |
| 10974 // Manifest a CmpL result in an integer register. Very painful. | |
| 10975 // This is the test to avoid. | |
| 10976 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags) | |
| 10977 %{ | |
| 10978 match(Set dst (CmpL3 src1 src2)); | |
| 10979 effect(KILL flags); | |
| 10980 | |
| 10981 ins_cost(275); // XXX | |
| 10982 format %{ "cmpq $src1, $src2\t# CmpL3\n\t" | |
| 10983 "movl $dst, -1\n\t" | |
| 10984 "jl,s done\n\t" | |
| 10985 "setne $dst\n\t" | |
| 10986 "movzbl $dst, $dst\n\t" | |
| 10987 "done:" %} | |
| 10988 ins_encode(cmpl3_flag(src1, src2, dst)); | |
| 10989 ins_pipe(pipe_slow); | |
| 10990 %} | |
| 10991 | |
| 10992 //----------Max and Min-------------------------------------------------------- | |
| 10993 // Min Instructions | |
| 10994 | |
| 10995 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr) | |
| 10996 %{ | |
| 10997 effect(USE_DEF dst, USE src, USE cr); | |
| 10998 | |
| 10999 format %{ "cmovlgt $dst, $src\t# min" %} | |
| 11000 opcode(0x0F, 0x4F); | |
| 11001 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 11002 ins_pipe(pipe_cmov_reg); | |
| 11003 %} | |
| 11004 | |
| 11005 | |
| 11006 instruct minI_rReg(rRegI dst, rRegI src) | |
| 11007 %{ | |
| 11008 match(Set dst (MinI dst src)); | |
| 11009 | |
| 11010 ins_cost(200); | |
| 11011 expand %{ | |
| 11012 rFlagsReg cr; | |
| 11013 compI_rReg(cr, dst, src); | |
| 11014 cmovI_reg_g(dst, src, cr); | |
| 11015 %} | |
| 11016 %} | |
| 11017 | |
| 11018 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr) | |
| 11019 %{ | |
| 11020 effect(USE_DEF dst, USE src, USE cr); | |
| 11021 | |
| 11022 format %{ "cmovllt $dst, $src\t# max" %} | |
| 11023 opcode(0x0F, 0x4C); | |
| 11024 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 11025 ins_pipe(pipe_cmov_reg); | |
| 11026 %} | |
| 11027 | |
| 11028 | |
| 11029 instruct maxI_rReg(rRegI dst, rRegI src) | |
| 11030 %{ | |
| 11031 match(Set dst (MaxI dst src)); | |
| 11032 | |
| 11033 ins_cost(200); | |
| 11034 expand %{ | |
| 11035 rFlagsReg cr; | |
| 11036 compI_rReg(cr, dst, src); | |
| 11037 cmovI_reg_l(dst, src, cr); | |
| 11038 %} | |
| 11039 %} | |
| 11040 | |
| 11041 // ============================================================================ | |
| 11042 // Branch Instructions | |
| 11043 | |
| 11044 // Jump Direct - Label defines a relative address from JMP+1 | |
| 11045 instruct jmpDir(label labl) | |
| 11046 %{ | |
| 11047 match(Goto); | |
| 11048 effect(USE labl); | |
| 11049 | |
| 11050 ins_cost(300); | |
| 11051 format %{ "jmp $labl" %} | |
| 11052 size(5); | |
| 3851 | 11053 ins_encode %{ |
| 11054 Label* L = $labl$$label; | |
| 11055 __ jmp(*L, false); // Always long jump | |
| 11056 %} | |
| 0 | 11057 ins_pipe(pipe_jmp); |
| 11058 %} | |
| 11059 | |
| 11060 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 11061 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl) | |
| 11062 %{ | |
| 11063 match(If cop cr); | |
| 11064 effect(USE labl); | |
| 11065 | |
| 11066 ins_cost(300); | |
| 11067 format %{ "j$cop $labl" %} | |
| 11068 size(6); | |
| 3851 | 11069 ins_encode %{ |
| 11070 Label* L = $labl$$label; | |
| 11071 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 11072 %} | |
| 0 | 11073 ins_pipe(pipe_jcc); |
| 11074 %} | |
| 11075 | |
| 11076 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 11077 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl) | |
| 11078 %{ | |
| 11079 match(CountedLoopEnd cop cr); | |
| 11080 effect(USE labl); | |
| 11081 | |
| 11082 ins_cost(300); | |
| 11083 format %{ "j$cop $labl\t# loop end" %} | |
| 11084 size(6); | |
| 3851 | 11085 ins_encode %{ |
| 11086 Label* L = $labl$$label; | |
| 11087 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 11088 %} | |
| 0 | 11089 ins_pipe(pipe_jcc); |
| 11090 %} | |
| 11091 | |
| 11092 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
|
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11093 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
| 0 | 11094 match(CountedLoopEnd cop cmp); |
| 11095 effect(USE labl); | |
| 11096 | |
| 11097 ins_cost(300); | |
| 11098 format %{ "j$cop,u $labl\t# loop end" %} | |
| 11099 size(6); | |
| 3851 | 11100 ins_encode %{ |
| 11101 Label* L = $labl$$label; | |
| 11102 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 11103 %} | |
| 0 | 11104 ins_pipe(pipe_jcc); |
| 11105 %} | |
| 11106 | |
|
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11107 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
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11108 match(CountedLoopEnd cop cmp); |
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11109 effect(USE labl); |
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11110 |
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11111 ins_cost(200); |
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11112 format %{ "j$cop,u $labl\t# loop end" %} |
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11113 size(6); |
| 3851 | 11114 ins_encode %{ |
| 11115 Label* L = $labl$$label; | |
| 11116 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 11117 %} | |
|
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11118 ins_pipe(pipe_jcc); |
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11119 %} |
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11120 |
| 0 | 11121 // Jump Direct Conditional - using unsigned comparison |
|
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11122 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
| 0 | 11123 match(If cop cmp); |
| 11124 effect(USE labl); | |
| 11125 | |
| 11126 ins_cost(300); | |
|
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11127 format %{ "j$cop,u $labl" %} |
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11128 size(6); |
| 3851 | 11129 ins_encode %{ |
| 11130 Label* L = $labl$$label; | |
| 11131 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 11132 %} | |
|
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11133 ins_pipe(pipe_jcc); |
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11134 %} |
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11135 |
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11136 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
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11137 match(If cop cmp); |
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11138 effect(USE labl); |
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11139 |
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11140 ins_cost(200); |
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11141 format %{ "j$cop,u $labl" %} |
| 0 | 11142 size(6); |
| 3851 | 11143 ins_encode %{ |
| 11144 Label* L = $labl$$label; | |
| 11145 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 11146 %} | |
| 0 | 11147 ins_pipe(pipe_jcc); |
| 11148 %} | |
| 11149 | |
|
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11150 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{ |
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11151 match(If cop cmp); |
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11152 effect(USE labl); |
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11153 |
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11154 ins_cost(200); |
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11155 format %{ $$template |
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11156 if ($cop$$cmpcode == Assembler::notEqual) { |
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11157 $$emit$$"jp,u $labl\n\t" |
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11158 $$emit$$"j$cop,u $labl" |
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11159 } else { |
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11160 $$emit$$"jp,u done\n\t" |
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11161 $$emit$$"j$cop,u $labl\n\t" |
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11162 $$emit$$"done:" |
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11163 } |
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11164 %} |
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11165 ins_encode %{ |
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11166 Label* l = $labl$$label; |
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11167 if ($cop$$cmpcode == Assembler::notEqual) { |
| 3851 | 11168 __ jcc(Assembler::parity, *l, false); |
| 11169 __ jcc(Assembler::notEqual, *l, false); | |
|
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11170 } else if ($cop$$cmpcode == Assembler::equal) { |
| 3851 | 11171 Label done; |
| 11172 __ jccb(Assembler::parity, done); | |
| 11173 __ jcc(Assembler::equal, *l, false); | |
| 11174 __ bind(done); | |
|
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11175 } else { |
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11176 ShouldNotReachHere(); |
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11177 } |
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11178 %} |
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11179 ins_pipe(pipe_jcc); |
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11180 %} |
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11181 |
| 0 | 11182 // ============================================================================ |
| 11183 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary | |
| 11184 // superklass array for an instance of the superklass. Set a hidden | |
| 11185 // internal cache on a hit (cache is checked with exposed code in | |
| 11186 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The | |
| 11187 // encoding ALSO sets flags. | |
| 11188 | |
| 11189 instruct partialSubtypeCheck(rdi_RegP result, | |
| 11190 rsi_RegP sub, rax_RegP super, rcx_RegI rcx, | |
| 11191 rFlagsReg cr) | |
| 11192 %{ | |
| 11193 match(Set result (PartialSubtypeCheck sub super)); | |
| 11194 effect(KILL rcx, KILL cr); | |
| 11195 | |
| 11196 ins_cost(1100); // slightly larger than the next version | |
|
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11197 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t" |
| 0 | 11198 "movl rcx, [rdi + arrayOopDesc::length_offset_in_bytes()]\t# length to scan\n\t" |
| 11199 "addq rdi, arrayOopDex::base_offset_in_bytes(T_OBJECT)\t# Skip to start of data; set NZ in case count is zero\n\t" | |
| 11200 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t" | |
| 11201 "jne,s miss\t\t# Missed: rdi not-zero\n\t" | |
|
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11202 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t" |
| 0 | 11203 "xorq $result, $result\t\t Hit: rdi zero\n\t" |
| 11204 "miss:\t" %} | |
| 11205 | |
| 11206 opcode(0x1); // Force a XOR of RDI | |
| 11207 ins_encode(enc_PartialSubtypeCheck()); | |
| 11208 ins_pipe(pipe_slow); | |
| 11209 %} | |
| 11210 | |
| 11211 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr, | |
| 11212 rsi_RegP sub, rax_RegP super, rcx_RegI rcx, | |
| 11213 immP0 zero, | |
| 11214 rdi_RegP result) | |
| 11215 %{ | |
| 11216 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero)); | |
| 11217 effect(KILL rcx, KILL result); | |
| 11218 | |
| 11219 ins_cost(1000); | |
|
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|
11220 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t" |
| 0 | 11221 "movl rcx, [rdi + arrayOopDesc::length_offset_in_bytes()]\t# length to scan\n\t" |
| 11222 "addq rdi, arrayOopDex::base_offset_in_bytes(T_OBJECT)\t# Skip to start of data; set NZ in case count is zero\n\t" | |
| 11223 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t" | |
| 11224 "jne,s miss\t\t# Missed: flags nz\n\t" | |
|
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11225 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t" |
| 0 | 11226 "miss:\t" %} |
| 11227 | |
| 11228 opcode(0x0); // No need to XOR RDI | |
| 11229 ins_encode(enc_PartialSubtypeCheck()); | |
| 11230 ins_pipe(pipe_slow); | |
| 11231 %} | |
| 11232 | |
| 11233 // ============================================================================ | |
| 11234 // Branch Instructions -- short offset versions | |
| 11235 // | |
| 11236 // These instructions are used to replace jumps of a long offset (the default | |
| 11237 // match) with jumps of a shorter offset. These instructions are all tagged | |
| 11238 // with the ins_short_branch attribute, which causes the ADLC to suppress the | |
| 11239 // match rules in general matching. Instead, the ADLC generates a conversion | |
| 11240 // method in the MachNode which can be used to do in-place replacement of the | |
| 11241 // long variant with the shorter variant. The compiler will determine if a | |
| 11242 // branch can be taken by the is_short_branch_offset() predicate in the machine | |
| 11243 // specific code section of the file. | |
| 11244 | |
| 11245 // Jump Direct - Label defines a relative address from JMP+1 | |
|
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11246 instruct jmpDir_short(label labl) %{ |
| 0 | 11247 match(Goto); |
| 11248 effect(USE labl); | |
| 11249 | |
| 11250 ins_cost(300); | |
| 11251 format %{ "jmp,s $labl" %} | |
| 11252 size(2); | |
| 3851 | 11253 ins_encode %{ |
| 11254 Label* L = $labl$$label; | |
| 11255 __ jmpb(*L); | |
| 11256 %} | |
| 0 | 11257 ins_pipe(pipe_jmp); |
| 11258 ins_short_branch(1); | |
| 11259 %} | |
| 11260 | |
| 11261 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
|
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11262 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{ |
| 0 | 11263 match(If cop cr); |
| 11264 effect(USE labl); | |
| 11265 | |
| 11266 ins_cost(300); | |
| 11267 format %{ "j$cop,s $labl" %} | |
| 11268 size(2); | |
| 3851 | 11269 ins_encode %{ |
| 11270 Label* L = $labl$$label; | |
| 11271 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11272 %} | |
| 0 | 11273 ins_pipe(pipe_jcc); |
| 11274 ins_short_branch(1); | |
| 11275 %} | |
| 11276 | |
| 11277 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
|
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11278 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{ |
| 0 | 11279 match(CountedLoopEnd cop cr); |
| 11280 effect(USE labl); | |
| 11281 | |
| 11282 ins_cost(300); | |
|
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11283 format %{ "j$cop,s $labl\t# loop end" %} |
| 0 | 11284 size(2); |
| 3851 | 11285 ins_encode %{ |
| 11286 Label* L = $labl$$label; | |
| 11287 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11288 %} | |
| 0 | 11289 ins_pipe(pipe_jcc); |
| 11290 ins_short_branch(1); | |
| 11291 %} | |
| 11292 | |
| 11293 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
|
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11294 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
|
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|
11295 match(CountedLoopEnd cop cmp); |
|
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|
11296 effect(USE labl); |
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|
11297 |
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|
11298 ins_cost(300); |
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|
11299 format %{ "j$cop,us $labl\t# loop end" %} |
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|
11300 size(2); |
| 3851 | 11301 ins_encode %{ |
| 11302 Label* L = $labl$$label; | |
| 11303 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11304 %} | |
|
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|
11305 ins_pipe(pipe_jcc); |
|
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|
11306 ins_short_branch(1); |
|
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|
11307 %} |
|
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|
11308 |
|
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|
11309 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
| 0 | 11310 match(CountedLoopEnd cop cmp); |
| 11311 effect(USE labl); | |
| 11312 | |
| 11313 ins_cost(300); | |
|
415
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|
11314 format %{ "j$cop,us $labl\t# loop end" %} |
|
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|
11315 size(2); |
| 3851 | 11316 ins_encode %{ |
| 11317 Label* L = $labl$$label; | |
| 11318 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11319 %} | |
|
415
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|
11320 ins_pipe(pipe_jcc); |
|
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|
11321 ins_short_branch(1); |
|
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diff
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|
11322 %} |
|
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never
parents:
403
diff
changeset
|
11323 |
|
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|
11324 // Jump Direct Conditional - using unsigned comparison |
|
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|
11325 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
|
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|
11326 match(If cop cmp); |
|
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|
11327 effect(USE labl); |
|
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|
11328 |
|
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|
11329 ins_cost(300); |
| 0 | 11330 format %{ "j$cop,us $labl" %} |
| 11331 size(2); | |
| 3851 | 11332 ins_encode %{ |
| 11333 Label* L = $labl$$label; | |
| 11334 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11335 %} | |
| 0 | 11336 ins_pipe(pipe_jcc); |
| 11337 ins_short_branch(1); | |
| 11338 %} | |
| 11339 | |
|
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|
11340 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
| 0 | 11341 match(If cop cmp); |
| 11342 effect(USE labl); | |
| 11343 | |
| 11344 ins_cost(300); | |
| 11345 format %{ "j$cop,us $labl" %} | |
| 11346 size(2); | |
| 3851 | 11347 ins_encode %{ |
| 11348 Label* L = $labl$$label; | |
| 11349 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11350 %} | |
| 0 | 11351 ins_pipe(pipe_jcc); |
| 11352 ins_short_branch(1); | |
| 11353 %} | |
| 11354 | |
|
415
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|
11355 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{ |
|
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|
11356 match(If cop cmp); |
|
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|
11357 effect(USE labl); |
|
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|
11358 |
|
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|
11359 ins_cost(300); |
|
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|
11360 format %{ $$template |
|
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|
11361 if ($cop$$cmpcode == Assembler::notEqual) { |
|
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|
11362 $$emit$$"jp,u,s $labl\n\t" |
|
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|
11363 $$emit$$"j$cop,u,s $labl" |
|
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|
11364 } else { |
|
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|
11365 $$emit$$"jp,u,s done\n\t" |
|
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|
11366 $$emit$$"j$cop,u,s $labl\n\t" |
|
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|
11367 $$emit$$"done:" |
|
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|
11368 } |
|
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|
11369 %} |
|
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|
11370 size(4); |
|
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|
11371 ins_encode %{ |
|
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|
11372 Label* l = $labl$$label; |
|
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|
11373 if ($cop$$cmpcode == Assembler::notEqual) { |
| 3851 | 11374 __ jccb(Assembler::parity, *l); |
| 11375 __ jccb(Assembler::notEqual, *l); | |
|
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|
11376 } else if ($cop$$cmpcode == Assembler::equal) { |
| 3851 | 11377 Label done; |
| 11378 __ jccb(Assembler::parity, done); | |
| 11379 __ jccb(Assembler::equal, *l); | |
| 11380 __ bind(done); | |
|
415
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|
11381 } else { |
| 3851 | 11382 ShouldNotReachHere(); |
| 11383 } | |
|
415
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|
11384 %} |
|
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diff
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|
11385 ins_pipe(pipe_jcc); |
|
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|
11386 ins_short_branch(1); |
|
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diff
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|
11387 %} |
|
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|
11388 |
| 0 | 11389 // ============================================================================ |
| 11390 // inlined locking and unlocking | |
| 11391 | |
| 11392 instruct cmpFastLock(rFlagsReg cr, | |
| 4777 | 11393 rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr) |
| 0 | 11394 %{ |
| 11395 match(Set cr (FastLock object box)); | |
| 4777 | 11396 effect(TEMP tmp, TEMP scr, USE_KILL box); |
| 0 | 11397 |
| 11398 ins_cost(300); | |
| 4777 | 11399 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %} |
| 0 | 11400 ins_encode(Fast_Lock(object, box, tmp, scr)); |
| 11401 ins_pipe(pipe_slow); | |
| 11402 %} | |
| 11403 | |
| 11404 instruct cmpFastUnlock(rFlagsReg cr, | |
| 11405 rRegP object, rax_RegP box, rRegP tmp) | |
| 11406 %{ | |
| 11407 match(Set cr (FastUnlock object box)); | |
| 4777 | 11408 effect(TEMP tmp, USE_KILL box); |
| 0 | 11409 |
| 11410 ins_cost(300); | |
| 4777 | 11411 format %{ "fastunlock $object,$box\t! kills $box,$tmp" %} |
| 0 | 11412 ins_encode(Fast_Unlock(object, box, tmp)); |
| 11413 ins_pipe(pipe_slow); | |
| 11414 %} | |
| 11415 | |
| 11416 | |
| 11417 // ============================================================================ | |
| 11418 // Safepoint Instructions | |
| 11419 instruct safePoint_poll(rFlagsReg cr) | |
| 11420 %{ | |
|
2404
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|
11421 predicate(!Assembler::is_polling_page_far()); |
| 0 | 11422 match(SafePoint); |
| 11423 effect(KILL cr); | |
| 11424 | |
|
2404
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|
11425 format %{ "testl rax, [rip + #offset_to_poll_page]\t" |
| 0 | 11426 "# Safepoint: poll for GC" %} |
| 11427 ins_cost(125); | |
|
2404
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|
11428 ins_encode %{ |
|
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diff
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|
11429 AddressLiteral addr(os::get_polling_page(), relocInfo::poll_type); |
|
b40d4fa697bf
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iveresov
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diff
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|
11430 __ testl(rax, addr); |
|
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diff
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|
11431 %} |
|
b40d4fa697bf
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iveresov
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diff
changeset
|
11432 ins_pipe(ialu_reg_mem); |
|
b40d4fa697bf
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iveresov
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2401
diff
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|
11433 %} |
|
b40d4fa697bf
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iveresov
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diff
changeset
|
11434 |
|
b40d4fa697bf
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iveresov
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diff
changeset
|
11435 instruct safePoint_poll_far(rFlagsReg cr, rRegP poll) |
|
b40d4fa697bf
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iveresov
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2401
diff
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|
11436 %{ |
|
b40d4fa697bf
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2401
diff
changeset
|
11437 predicate(Assembler::is_polling_page_far()); |
|
b40d4fa697bf
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iveresov
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diff
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|
11438 match(SafePoint poll); |
|
b40d4fa697bf
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diff
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|
11439 effect(KILL cr, USE poll); |
|
b40d4fa697bf
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iveresov
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diff
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|
11440 |
|
b40d4fa697bf
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iveresov
parents:
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diff
changeset
|
11441 format %{ "testl rax, [$poll]\t" |
|
b40d4fa697bf
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iveresov
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2401
diff
changeset
|
11442 "# Safepoint: poll for GC" %} |
|
b40d4fa697bf
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diff
changeset
|
11443 ins_cost(125); |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
11444 ins_encode %{ |
|
b40d4fa697bf
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iveresov
parents:
2401
diff
changeset
|
11445 __ relocate(relocInfo::poll_type); |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
11446 __ testl(rax, Address($poll$$Register, 0)); |
|
b40d4fa697bf
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iveresov
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2401
diff
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|
11447 %} |
| 0 | 11448 ins_pipe(ialu_reg_mem); |
| 11449 %} | |
| 11450 | |
| 11451 // ============================================================================ | |
| 11452 // Procedure Call/Return Instructions | |
| 11453 // Call Java Static Instruction | |
| 11454 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 11455 // compute_padding() functions will have to be adjusted. | |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
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diff
changeset
|
11456 instruct CallStaticJavaDirect(method meth) %{ |
| 0 | 11457 match(CallStaticJava); |
|
1137
97125851f396
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diff
changeset
|
11458 predicate(!((CallStaticJavaNode*) n)->is_method_handle_invoke()); |
| 0 | 11459 effect(USE meth); |
| 11460 | |
| 11461 ins_cost(300); | |
| 11462 format %{ "call,static " %} | |
| 11463 opcode(0xE8); /* E8 cd */ | |
| 11464 ins_encode(Java_Static_Call(meth), call_epilog); | |
| 11465 ins_pipe(pipe_slow); | |
| 11466 ins_alignment(4); | |
| 11467 %} | |
| 11468 | |
|
1137
97125851f396
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diff
changeset
|
11469 // Call Java Static Instruction (method handle version) |
|
97125851f396
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diff
changeset
|
11470 // Note: If this code changes, the corresponding ret_addr_offset() and |
|
97125851f396
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diff
changeset
|
11471 // compute_padding() functions will have to be adjusted. |
| 1567 | 11472 instruct CallStaticJavaHandle(method meth, rbp_RegP rbp_mh_SP_save) %{ |
|
1137
97125851f396
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|
11473 match(CallStaticJava); |
|
97125851f396
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diff
changeset
|
11474 predicate(((CallStaticJavaNode*) n)->is_method_handle_invoke()); |
|
97125851f396
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diff
changeset
|
11475 effect(USE meth); |
|
97125851f396
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diff
changeset
|
11476 // RBP is saved by all callees (for interpreter stack correction). |
|
97125851f396
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diff
changeset
|
11477 // We use it here for a similar purpose, in {preserve,restore}_SP. |
|
97125851f396
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diff
changeset
|
11478 |
|
97125851f396
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diff
changeset
|
11479 ins_cost(300); |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
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diff
changeset
|
11480 format %{ "call,static/MethodHandle " %} |
|
97125851f396
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diff
changeset
|
11481 opcode(0xE8); /* E8 cd */ |
|
97125851f396
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twisti
parents:
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diff
changeset
|
11482 ins_encode(preserve_SP, |
|
97125851f396
6829187: compiler optimizations required for JSR 292
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diff
changeset
|
11483 Java_Static_Call(meth), |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
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diff
changeset
|
11484 restore_SP, |
|
97125851f396
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diff
changeset
|
11485 call_epilog); |
|
97125851f396
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diff
changeset
|
11486 ins_pipe(pipe_slow); |
|
97125851f396
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diff
changeset
|
11487 ins_alignment(4); |
|
97125851f396
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diff
changeset
|
11488 %} |
|
97125851f396
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|
11489 |
| 0 | 11490 // Call Java Dynamic Instruction |
| 11491 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 11492 // compute_padding() functions will have to be adjusted. | |
| 11493 instruct CallDynamicJavaDirect(method meth) | |
| 11494 %{ | |
| 11495 match(CallDynamicJava); | |
| 11496 effect(USE meth); | |
| 11497 | |
| 11498 ins_cost(300); | |
| 11499 format %{ "movq rax, #Universe::non_oop_word()\n\t" | |
| 11500 "call,dynamic " %} | |
| 11501 opcode(0xE8); /* E8 cd */ | |
| 11502 ins_encode(Java_Dynamic_Call(meth), call_epilog); | |
| 11503 ins_pipe(pipe_slow); | |
| 11504 ins_alignment(4); | |
| 11505 %} | |
| 11506 | |
| 11507 // Call Runtime Instruction | |
| 11508 instruct CallRuntimeDirect(method meth) | |
| 11509 %{ | |
| 11510 match(CallRuntime); | |
| 11511 effect(USE meth); | |
| 11512 | |
| 11513 ins_cost(300); | |
| 11514 format %{ "call,runtime " %} | |
| 11515 opcode(0xE8); /* E8 cd */ | |
| 11516 ins_encode(Java_To_Runtime(meth)); | |
| 11517 ins_pipe(pipe_slow); | |
| 11518 %} | |
| 11519 | |
| 11520 // Call runtime without safepoint | |
| 11521 instruct CallLeafDirect(method meth) | |
| 11522 %{ | |
| 11523 match(CallLeaf); | |
| 11524 effect(USE meth); | |
| 11525 | |
| 11526 ins_cost(300); | |
| 11527 format %{ "call_leaf,runtime " %} | |
| 11528 opcode(0xE8); /* E8 cd */ | |
| 11529 ins_encode(Java_To_Runtime(meth)); | |
| 11530 ins_pipe(pipe_slow); | |
| 11531 %} | |
| 11532 | |
| 11533 // Call runtime without safepoint | |
| 11534 instruct CallLeafNoFPDirect(method meth) | |
| 11535 %{ | |
| 11536 match(CallLeafNoFP); | |
| 11537 effect(USE meth); | |
| 11538 | |
| 11539 ins_cost(300); | |
| 11540 format %{ "call_leaf_nofp,runtime " %} | |
| 11541 opcode(0xE8); /* E8 cd */ | |
| 11542 ins_encode(Java_To_Runtime(meth)); | |
| 11543 ins_pipe(pipe_slow); | |
| 11544 %} | |
| 11545 | |
| 11546 // Return Instruction | |
| 11547 // Remove the return address & jump to it. | |
| 11548 // Notice: We always emit a nop after a ret to make sure there is room | |
| 11549 // for safepoint patching | |
| 11550 instruct Ret() | |
| 11551 %{ | |
| 11552 match(Return); | |
| 11553 | |
| 11554 format %{ "ret" %} | |
| 11555 opcode(0xC3); | |
| 11556 ins_encode(OpcP); | |
| 11557 ins_pipe(pipe_jmp); | |
| 11558 %} | |
| 11559 | |
| 11560 // Tail Call; Jump from runtime stub to Java code. | |
| 11561 // Also known as an 'interprocedural jump'. | |
| 11562 // Target of jump will eventually return to caller. | |
| 11563 // TailJump below removes the return address. | |
| 11564 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop) | |
| 11565 %{ | |
| 11566 match(TailCall jump_target method_oop); | |
| 11567 | |
| 11568 ins_cost(300); | |
| 11569 format %{ "jmp $jump_target\t# rbx holds method oop" %} | |
| 11570 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 11571 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target)); | |
| 11572 ins_pipe(pipe_jmp); | |
| 11573 %} | |
| 11574 | |
| 11575 // Tail Jump; remove the return address; jump to target. | |
| 11576 // TailCall above leaves the return address around. | |
| 11577 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop) | |
| 11578 %{ | |
| 11579 match(TailJump jump_target ex_oop); | |
| 11580 | |
| 11581 ins_cost(300); | |
| 11582 format %{ "popq rdx\t# pop return address\n\t" | |
| 11583 "jmp $jump_target" %} | |
| 11584 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 11585 ins_encode(Opcode(0x5a), // popq rdx | |
| 11586 REX_reg(jump_target), OpcP, reg_opc(jump_target)); | |
| 11587 ins_pipe(pipe_jmp); | |
| 11588 %} | |
| 11589 | |
| 11590 // Create exception oop: created by stack-crawling runtime code. | |
| 11591 // Created exception is now available to this handler, and is setup | |
| 11592 // just prior to jumping to this handler. No code emitted. | |
| 11593 instruct CreateException(rax_RegP ex_oop) | |
| 11594 %{ | |
| 11595 match(Set ex_oop (CreateEx)); | |
| 11596 | |
| 11597 size(0); | |
| 11598 // use the following format syntax | |
| 11599 format %{ "# exception oop is in rax; no code emitted" %} | |
| 11600 ins_encode(); | |
| 11601 ins_pipe(empty); | |
| 11602 %} | |
| 11603 | |
| 11604 // Rethrow exception: | |
| 11605 // The exception oop will come in the first argument position. | |
| 11606 // Then JUMP (not call) to the rethrow stub code. | |
| 11607 instruct RethrowException() | |
| 11608 %{ | |
| 11609 match(Rethrow); | |
| 11610 | |
| 11611 // use the following format syntax | |
| 11612 format %{ "jmp rethrow_stub" %} | |
| 11613 ins_encode(enc_rethrow); | |
| 11614 ins_pipe(pipe_jmp); | |
| 11615 %} | |
| 11616 | |
| 11617 | |
| 4950 | 11618 // ============================================================================ |
| 11619 // This name is KNOWN by the ADLC and cannot be changed. | |
| 11620 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type | |
| 11621 // for this guy. | |
| 11622 instruct tlsLoadP(r15_RegP dst) %{ | |
| 11623 match(Set dst (ThreadLocal)); | |
| 11624 effect(DEF dst); | |
| 11625 | |
| 11626 size(0); | |
| 11627 format %{ "# TLS is in R15" %} | |
| 11628 ins_encode( /*empty encoding*/ ); | |
| 11629 ins_pipe(ialu_reg_reg); | |
| 11630 %} | |
| 11631 | |
| 11632 | |
| 0 | 11633 //----------PEEPHOLE RULES----------------------------------------------------- |
| 11634 // These must follow all instruction definitions as they use the names | |
| 11635 // defined in the instructions definitions. | |
| 11636 // | |
| 605 | 11637 // peepmatch ( root_instr_name [preceding_instruction]* ); |
| 0 | 11638 // |
| 11639 // peepconstraint %{ | |
| 11640 // (instruction_number.operand_name relational_op instruction_number.operand_name | |
| 11641 // [, ...] ); | |
| 11642 // // instruction numbers are zero-based using left to right order in peepmatch | |
| 11643 // | |
| 11644 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); | |
| 11645 // // provide an instruction_number.operand_name for each operand that appears | |
| 11646 // // in the replacement instruction's match rule | |
| 11647 // | |
| 11648 // ---------VM FLAGS--------------------------------------------------------- | |
| 11649 // | |
| 11650 // All peephole optimizations can be turned off using -XX:-OptoPeephole | |
| 11651 // | |
| 11652 // Each peephole rule is given an identifying number starting with zero and | |
| 11653 // increasing by one in the order seen by the parser. An individual peephole | |
| 11654 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# | |
| 11655 // on the command-line. | |
| 11656 // | |
| 11657 // ---------CURRENT LIMITATIONS---------------------------------------------- | |
| 11658 // | |
| 11659 // Only match adjacent instructions in same basic block | |
| 11660 // Only equality constraints | |
| 11661 // Only constraints between operands, not (0.dest_reg == RAX_enc) | |
| 11662 // Only one replacement instruction | |
| 11663 // | |
| 11664 // ---------EXAMPLE---------------------------------------------------------- | |
| 11665 // | |
| 11666 // // pertinent parts of existing instructions in architecture description | |
| 11667 // instruct movI(rRegI dst, rRegI src) | |
| 11668 // %{ | |
| 11669 // match(Set dst (CopyI src)); | |
| 11670 // %} | |
| 11671 // | |
| 11672 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr) | |
| 11673 // %{ | |
| 11674 // match(Set dst (AddI dst src)); | |
| 11675 // effect(KILL cr); | |
| 11676 // %} | |
| 11677 // | |
| 11678 // // Change (inc mov) to lea | |
| 11679 // peephole %{ | |
| 11680 // // increment preceeded by register-register move | |
| 11681 // peepmatch ( incI_rReg movI ); | |
| 11682 // // require that the destination register of the increment | |
| 11683 // // match the destination register of the move | |
| 11684 // peepconstraint ( 0.dst == 1.dst ); | |
| 11685 // // construct a replacement instruction that sets | |
| 11686 // // the destination to ( move's source register + one ) | |
| 11687 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) ); | |
| 11688 // %} | |
| 11689 // | |
| 11690 | |
| 11691 // Implementation no longer uses movX instructions since | |
| 11692 // machine-independent system no longer uses CopyX nodes. | |
| 11693 // | |
| 11694 // peephole | |
| 11695 // %{ | |
| 11696 // peepmatch (incI_rReg movI); | |
| 11697 // peepconstraint (0.dst == 1.dst); | |
| 11698 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src)); | |
| 11699 // %} | |
| 11700 | |
| 11701 // peephole | |
| 11702 // %{ | |
| 11703 // peepmatch (decI_rReg movI); | |
| 11704 // peepconstraint (0.dst == 1.dst); | |
| 11705 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src)); | |
| 11706 // %} | |
| 11707 | |
| 11708 // peephole | |
| 11709 // %{ | |
| 11710 // peepmatch (addI_rReg_imm movI); | |
| 11711 // peepconstraint (0.dst == 1.dst); | |
| 11712 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src)); | |
| 11713 // %} | |
| 11714 | |
| 11715 // peephole | |
| 11716 // %{ | |
| 11717 // peepmatch (incL_rReg movL); | |
| 11718 // peepconstraint (0.dst == 1.dst); | |
| 11719 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src)); | |
| 11720 // %} | |
| 11721 | |
| 11722 // peephole | |
| 11723 // %{ | |
| 11724 // peepmatch (decL_rReg movL); | |
| 11725 // peepconstraint (0.dst == 1.dst); | |
| 11726 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src)); | |
| 11727 // %} | |
| 11728 | |
| 11729 // peephole | |
| 11730 // %{ | |
| 11731 // peepmatch (addL_rReg_imm movL); | |
| 11732 // peepconstraint (0.dst == 1.dst); | |
| 11733 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src)); | |
| 11734 // %} | |
| 11735 | |
| 11736 // peephole | |
| 11737 // %{ | |
| 11738 // peepmatch (addP_rReg_imm movP); | |
| 11739 // peepconstraint (0.dst == 1.dst); | |
| 11740 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src)); | |
| 11741 // %} | |
| 11742 | |
| 11743 // // Change load of spilled value to only a spill | |
| 11744 // instruct storeI(memory mem, rRegI src) | |
| 11745 // %{ | |
| 11746 // match(Set mem (StoreI mem src)); | |
| 11747 // %} | |
| 11748 // | |
| 11749 // instruct loadI(rRegI dst, memory mem) | |
| 11750 // %{ | |
| 11751 // match(Set dst (LoadI mem)); | |
| 11752 // %} | |
| 11753 // | |
| 11754 | |
| 11755 peephole | |
| 11756 %{ | |
| 11757 peepmatch (loadI storeI); | |
| 11758 peepconstraint (1.src == 0.dst, 1.mem == 0.mem); | |
| 11759 peepreplace (storeI(1.mem 1.mem 1.src)); | |
| 11760 %} | |
| 11761 | |
| 11762 peephole | |
| 11763 %{ | |
| 11764 peepmatch (loadL storeL); | |
| 11765 peepconstraint (1.src == 0.dst, 1.mem == 0.mem); | |
| 11766 peepreplace (storeL(1.mem 1.mem 1.src)); | |
| 11767 %} | |
| 11768 | |
| 11769 //----------SMARTSPILL RULES--------------------------------------------------- | |
| 11770 // These must follow all instruction definitions as they use the names | |
| 11771 // defined in the instructions definitions. |