Mercurial > hg > truffle
annotate src/cpu/x86/vm/x86_64.ad @ 4761:65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
Summary: Use 3-operands SIMD instructions in C2 generated code for machines with AVX.
Reviewed-by: never
| author | kvn |
|---|---|
| date | Tue, 20 Dec 2011 00:55:02 -0800 |
| parents | 127b3692c168 |
| children | 069ab3f976d3 |
| rev | line source |
|---|---|
| 0 | 1 // |
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2 // Copyright (c) 2003, 2011, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 // | |
| 5 // This code is free software; you can redistribute it and/or modify it | |
| 6 // under the terms of the GNU General Public License version 2 only, as | |
| 7 // published by the Free Software Foundation. | |
| 8 // | |
| 9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 // version 2 for more details (a copy is included in the LICENSE file that | |
| 13 // accompanied this code). | |
| 14 // | |
| 15 // You should have received a copy of the GNU General Public License version | |
| 16 // 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 // | |
|
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19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 // or visit www.oracle.com if you need additional information or have any |
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21 // questions. |
| 0 | 22 // |
| 23 // | |
| 24 | |
| 25 // AMD64 Architecture Description File | |
| 26 | |
| 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ | |
| 28 // This information is used by the matcher and the register allocator to | |
| 29 // describe individual registers and classes of registers within the target | |
| 30 // archtecture. | |
| 31 | |
| 32 register %{ | |
| 33 //----------Architecture Description Register Definitions---------------------- | |
| 34 // General Registers | |
| 35 // "reg_def" name ( register save type, C convention save type, | |
| 36 // ideal register type, encoding ); | |
| 37 // Register Save Types: | |
| 38 // | |
| 39 // NS = No-Save: The register allocator assumes that these registers | |
| 40 // can be used without saving upon entry to the method, & | |
| 41 // that they do not need to be saved at call sites. | |
| 42 // | |
| 43 // SOC = Save-On-Call: The register allocator assumes that these registers | |
| 44 // can be used without saving upon entry to the method, | |
| 45 // but that they must be saved at call sites. | |
| 46 // | |
| 47 // SOE = Save-On-Entry: The register allocator assumes that these registers | |
| 48 // must be saved before using them upon entry to the | |
| 49 // method, but they do not need to be saved at call | |
| 50 // sites. | |
| 51 // | |
| 52 // AS = Always-Save: The register allocator assumes that these registers | |
| 53 // must be saved before using them upon entry to the | |
| 54 // method, & that they must be saved at call sites. | |
| 55 // | |
| 56 // Ideal Register Type is used to determine how to save & restore a | |
| 57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get | |
| 58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. | |
| 59 // | |
| 60 // The encoding number is the actual bit-pattern placed into the opcodes. | |
| 61 | |
| 62 // General Registers | |
| 63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when | |
| 64 // used as byte registers) | |
| 65 | |
| 66 // Previously set RBX, RSI, and RDI as save-on-entry for java code | |
| 67 // Turn off SOE in java-code due to frequent use of uncommon-traps. | |
| 68 // Now that allocator is better, turn on RSI and RDI as SOE registers. | |
| 69 | |
| 70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg()); | |
| 71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next()); | |
| 72 | |
| 73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg()); | |
| 74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next()); | |
| 75 | |
| 76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg()); | |
| 77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next()); | |
| 78 | |
| 79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg()); | |
| 80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next()); | |
| 81 | |
| 82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg()); | |
| 83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next()); | |
| 84 | |
| 85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code | |
| 86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg()); | |
| 87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next()); | |
| 88 | |
| 89 #ifdef _WIN64 | |
| 90 | |
| 91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg()); | |
| 92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next()); | |
| 93 | |
| 94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg()); | |
| 95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next()); | |
| 96 | |
| 97 #else | |
| 98 | |
| 99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg()); | |
| 100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next()); | |
| 101 | |
| 102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg()); | |
| 103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next()); | |
| 104 | |
| 105 #endif | |
| 106 | |
| 107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg()); | |
| 108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next()); | |
| 109 | |
| 110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg()); | |
| 111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next()); | |
| 112 | |
| 113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg()); | |
| 114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next()); | |
| 115 | |
| 116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg()); | |
| 117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next()); | |
| 118 | |
| 119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg()); | |
| 120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next()); | |
| 121 | |
| 122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg()); | |
| 123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next()); | |
| 124 | |
| 125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg()); | |
| 126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next()); | |
| 127 | |
| 128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg()); | |
| 129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next()); | |
| 130 | |
| 131 | |
| 132 // Floating Point Registers | |
| 133 | |
| 134 // XMM registers. 128-bit registers or 4 words each, labeled (a)-d. | |
| 135 // Word a in each register holds a Float, words ab hold a Double. We | |
| 136 // currently do not use the SIMD capabilities, so registers cd are | |
| 137 // unused at the moment. | |
| 138 // XMM8-XMM15 must be encoded with REX. | |
| 139 // Linux ABI: No register preserved across function calls | |
| 140 // XMM0-XMM7 might hold parameters | |
| 141 // Windows ABI: XMM6-XMM15 preserved across function calls | |
| 142 // XMM0-XMM3 might hold parameters | |
| 143 | |
| 144 reg_def XMM0 (SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()); | |
| 145 reg_def XMM0_H (SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next()); | |
| 146 | |
| 147 reg_def XMM1 (SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()); | |
| 148 reg_def XMM1_H (SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next()); | |
| 149 | |
| 150 reg_def XMM2 (SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()); | |
| 151 reg_def XMM2_H (SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next()); | |
| 152 | |
| 153 reg_def XMM3 (SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()); | |
| 154 reg_def XMM3_H (SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next()); | |
| 155 | |
| 156 reg_def XMM4 (SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()); | |
| 157 reg_def XMM4_H (SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next()); | |
| 158 | |
| 159 reg_def XMM5 (SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()); | |
| 160 reg_def XMM5_H (SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next()); | |
| 161 | |
| 162 #ifdef _WIN64 | |
| 163 | |
| 164 reg_def XMM6 (SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()); | |
| 165 reg_def XMM6_H (SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next()); | |
| 166 | |
| 167 reg_def XMM7 (SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()); | |
| 168 reg_def XMM7_H (SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next()); | |
| 169 | |
| 170 reg_def XMM8 (SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()); | |
| 171 reg_def XMM8_H (SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next()); | |
| 172 | |
| 173 reg_def XMM9 (SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()); | |
| 174 reg_def XMM9_H (SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next()); | |
| 175 | |
| 176 reg_def XMM10 (SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()); | |
| 177 reg_def XMM10_H(SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next()); | |
| 178 | |
| 179 reg_def XMM11 (SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()); | |
| 180 reg_def XMM11_H(SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next()); | |
| 181 | |
| 182 reg_def XMM12 (SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()); | |
| 183 reg_def XMM12_H(SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next()); | |
| 184 | |
| 185 reg_def XMM13 (SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()); | |
| 186 reg_def XMM13_H(SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next()); | |
| 187 | |
| 188 reg_def XMM14 (SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()); | |
| 189 reg_def XMM14_H(SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next()); | |
| 190 | |
| 191 reg_def XMM15 (SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()); | |
| 192 reg_def XMM15_H(SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next()); | |
| 193 | |
| 194 #else | |
| 195 | |
| 196 reg_def XMM6 (SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()); | |
| 197 reg_def XMM6_H (SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next()); | |
| 198 | |
| 199 reg_def XMM7 (SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()); | |
| 200 reg_def XMM7_H (SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next()); | |
| 201 | |
| 202 reg_def XMM8 (SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()); | |
| 203 reg_def XMM8_H (SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next()); | |
| 204 | |
| 205 reg_def XMM9 (SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()); | |
| 206 reg_def XMM9_H (SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next()); | |
| 207 | |
| 208 reg_def XMM10 (SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()); | |
| 209 reg_def XMM10_H(SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next()); | |
| 210 | |
| 211 reg_def XMM11 (SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()); | |
| 212 reg_def XMM11_H(SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next()); | |
| 213 | |
| 214 reg_def XMM12 (SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()); | |
| 215 reg_def XMM12_H(SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next()); | |
| 216 | |
| 217 reg_def XMM13 (SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()); | |
| 218 reg_def XMM13_H(SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next()); | |
| 219 | |
| 220 reg_def XMM14 (SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()); | |
| 221 reg_def XMM14_H(SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next()); | |
| 222 | |
| 223 reg_def XMM15 (SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()); | |
| 224 reg_def XMM15_H(SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next()); | |
| 225 | |
| 226 #endif // _WIN64 | |
| 227 | |
| 228 reg_def RFLAGS(SOC, SOC, 0, 16, VMRegImpl::Bad()); | |
| 229 | |
| 230 // Specify priority of register selection within phases of register | |
| 231 // allocation. Highest priority is first. A useful heuristic is to | |
| 232 // give registers a low priority when they are required by machine | |
| 233 // instructions, like EAX and EDX on I486, and choose no-save registers | |
| 234 // before save-on-call, & save-on-call before save-on-entry. Registers | |
| 235 // which participate in fixed calling sequences should come last. | |
| 236 // Registers which are used as pairs must fall on an even boundary. | |
| 237 | |
| 238 alloc_class chunk0(R10, R10_H, | |
| 239 R11, R11_H, | |
| 240 R8, R8_H, | |
| 241 R9, R9_H, | |
| 242 R12, R12_H, | |
| 243 RCX, RCX_H, | |
| 244 RBX, RBX_H, | |
| 245 RDI, RDI_H, | |
| 246 RDX, RDX_H, | |
| 247 RSI, RSI_H, | |
| 248 RAX, RAX_H, | |
| 249 RBP, RBP_H, | |
| 250 R13, R13_H, | |
| 251 R14, R14_H, | |
| 252 R15, R15_H, | |
| 253 RSP, RSP_H); | |
| 254 | |
| 255 // XXX probably use 8-15 first on Linux | |
| 256 alloc_class chunk1(XMM0, XMM0_H, | |
| 257 XMM1, XMM1_H, | |
| 258 XMM2, XMM2_H, | |
| 259 XMM3, XMM3_H, | |
| 260 XMM4, XMM4_H, | |
| 261 XMM5, XMM5_H, | |
| 262 XMM6, XMM6_H, | |
| 263 XMM7, XMM7_H, | |
| 264 XMM8, XMM8_H, | |
| 265 XMM9, XMM9_H, | |
| 266 XMM10, XMM10_H, | |
| 267 XMM11, XMM11_H, | |
| 268 XMM12, XMM12_H, | |
| 269 XMM13, XMM13_H, | |
| 270 XMM14, XMM14_H, | |
| 271 XMM15, XMM15_H); | |
| 272 | |
| 273 alloc_class chunk2(RFLAGS); | |
| 274 | |
| 275 | |
| 276 //----------Architecture Description Register Classes-------------------------- | |
| 277 // Several register classes are automatically defined based upon information in | |
| 278 // this architecture description. | |
| 279 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ ) | |
| 280 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ ) | |
| 281 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ ) | |
| 282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) | |
| 283 // | |
| 284 | |
| 285 // Class for all pointer registers (including RSP) | |
| 286 reg_class any_reg(RAX, RAX_H, | |
| 287 RDX, RDX_H, | |
| 288 RBP, RBP_H, | |
| 289 RDI, RDI_H, | |
| 290 RSI, RSI_H, | |
| 291 RCX, RCX_H, | |
| 292 RBX, RBX_H, | |
| 293 RSP, RSP_H, | |
| 294 R8, R8_H, | |
| 295 R9, R9_H, | |
| 296 R10, R10_H, | |
| 297 R11, R11_H, | |
| 298 R12, R12_H, | |
| 299 R13, R13_H, | |
| 300 R14, R14_H, | |
| 301 R15, R15_H); | |
| 302 | |
| 303 // Class for all pointer registers except RSP | |
| 304 reg_class ptr_reg(RAX, RAX_H, | |
| 305 RDX, RDX_H, | |
| 306 RBP, RBP_H, | |
| 307 RDI, RDI_H, | |
| 308 RSI, RSI_H, | |
| 309 RCX, RCX_H, | |
| 310 RBX, RBX_H, | |
| 311 R8, R8_H, | |
| 312 R9, R9_H, | |
| 313 R10, R10_H, | |
| 314 R11, R11_H, | |
| 315 R13, R13_H, | |
| 316 R14, R14_H); | |
| 317 | |
| 318 // Class for all pointer registers except RAX and RSP | |
| 319 reg_class ptr_no_rax_reg(RDX, RDX_H, | |
| 320 RBP, RBP_H, | |
| 321 RDI, RDI_H, | |
| 322 RSI, RSI_H, | |
| 323 RCX, RCX_H, | |
| 324 RBX, RBX_H, | |
| 325 R8, R8_H, | |
| 326 R9, R9_H, | |
| 327 R10, R10_H, | |
| 328 R11, R11_H, | |
| 329 R13, R13_H, | |
| 330 R14, R14_H); | |
| 331 | |
| 332 reg_class ptr_no_rbp_reg(RDX, RDX_H, | |
| 333 RAX, RAX_H, | |
| 334 RDI, RDI_H, | |
| 335 RSI, RSI_H, | |
| 336 RCX, RCX_H, | |
| 337 RBX, RBX_H, | |
| 338 R8, R8_H, | |
| 339 R9, R9_H, | |
| 340 R10, R10_H, | |
| 341 R11, R11_H, | |
| 342 R13, R13_H, | |
| 343 R14, R14_H); | |
| 344 | |
| 345 // Class for all pointer registers except RAX, RBX and RSP | |
| 346 reg_class ptr_no_rax_rbx_reg(RDX, RDX_H, | |
| 347 RBP, RBP_H, | |
| 348 RDI, RDI_H, | |
| 349 RSI, RSI_H, | |
| 350 RCX, RCX_H, | |
| 351 R8, R8_H, | |
| 352 R9, R9_H, | |
| 353 R10, R10_H, | |
| 354 R11, R11_H, | |
| 355 R13, R13_H, | |
| 356 R14, R14_H); | |
| 357 | |
| 358 // Singleton class for RAX pointer register | |
| 359 reg_class ptr_rax_reg(RAX, RAX_H); | |
| 360 | |
| 361 // Singleton class for RBX pointer register | |
| 362 reg_class ptr_rbx_reg(RBX, RBX_H); | |
| 363 | |
| 364 // Singleton class for RSI pointer register | |
| 365 reg_class ptr_rsi_reg(RSI, RSI_H); | |
| 366 | |
| 367 // Singleton class for RDI pointer register | |
| 368 reg_class ptr_rdi_reg(RDI, RDI_H); | |
| 369 | |
| 370 // Singleton class for RBP pointer register | |
| 371 reg_class ptr_rbp_reg(RBP, RBP_H); | |
| 372 | |
| 373 // Singleton class for stack pointer | |
| 374 reg_class ptr_rsp_reg(RSP, RSP_H); | |
| 375 | |
| 376 // Singleton class for TLS pointer | |
| 377 reg_class ptr_r15_reg(R15, R15_H); | |
| 378 | |
| 379 // Class for all long registers (except RSP) | |
| 380 reg_class long_reg(RAX, RAX_H, | |
| 381 RDX, RDX_H, | |
| 382 RBP, RBP_H, | |
| 383 RDI, RDI_H, | |
| 384 RSI, RSI_H, | |
| 385 RCX, RCX_H, | |
| 386 RBX, RBX_H, | |
| 387 R8, R8_H, | |
| 388 R9, R9_H, | |
| 389 R10, R10_H, | |
| 390 R11, R11_H, | |
| 391 R13, R13_H, | |
| 392 R14, R14_H); | |
| 393 | |
| 394 // Class for all long registers except RAX, RDX (and RSP) | |
| 395 reg_class long_no_rax_rdx_reg(RBP, RBP_H, | |
| 396 RDI, RDI_H, | |
| 397 RSI, RSI_H, | |
| 398 RCX, RCX_H, | |
| 399 RBX, RBX_H, | |
| 400 R8, R8_H, | |
| 401 R9, R9_H, | |
| 402 R10, R10_H, | |
| 403 R11, R11_H, | |
| 404 R13, R13_H, | |
| 405 R14, R14_H); | |
| 406 | |
| 407 // Class for all long registers except RCX (and RSP) | |
| 408 reg_class long_no_rcx_reg(RBP, RBP_H, | |
| 409 RDI, RDI_H, | |
| 410 RSI, RSI_H, | |
| 411 RAX, RAX_H, | |
| 412 RDX, RDX_H, | |
| 413 RBX, RBX_H, | |
| 414 R8, R8_H, | |
| 415 R9, R9_H, | |
| 416 R10, R10_H, | |
| 417 R11, R11_H, | |
| 418 R13, R13_H, | |
| 419 R14, R14_H); | |
| 420 | |
| 421 // Class for all long registers except RAX (and RSP) | |
| 422 reg_class long_no_rax_reg(RBP, RBP_H, | |
| 423 RDX, RDX_H, | |
| 424 RDI, RDI_H, | |
| 425 RSI, RSI_H, | |
| 426 RCX, RCX_H, | |
| 427 RBX, RBX_H, | |
| 428 R8, R8_H, | |
| 429 R9, R9_H, | |
| 430 R10, R10_H, | |
| 431 R11, R11_H, | |
| 432 R13, R13_H, | |
| 433 R14, R14_H); | |
| 434 | |
| 435 // Singleton class for RAX long register | |
| 436 reg_class long_rax_reg(RAX, RAX_H); | |
| 437 | |
| 438 // Singleton class for RCX long register | |
| 439 reg_class long_rcx_reg(RCX, RCX_H); | |
| 440 | |
| 441 // Singleton class for RDX long register | |
| 442 reg_class long_rdx_reg(RDX, RDX_H); | |
| 443 | |
| 444 // Class for all int registers (except RSP) | |
| 445 reg_class int_reg(RAX, | |
| 446 RDX, | |
| 447 RBP, | |
| 448 RDI, | |
| 449 RSI, | |
| 450 RCX, | |
| 451 RBX, | |
| 452 R8, | |
| 453 R9, | |
| 454 R10, | |
| 455 R11, | |
| 456 R13, | |
| 457 R14); | |
| 458 | |
| 459 // Class for all int registers except RCX (and RSP) | |
| 460 reg_class int_no_rcx_reg(RAX, | |
| 461 RDX, | |
| 462 RBP, | |
| 463 RDI, | |
| 464 RSI, | |
| 465 RBX, | |
| 466 R8, | |
| 467 R9, | |
| 468 R10, | |
| 469 R11, | |
| 470 R13, | |
| 471 R14); | |
| 472 | |
| 473 // Class for all int registers except RAX, RDX (and RSP) | |
| 474 reg_class int_no_rax_rdx_reg(RBP, | |
| 304 | 475 RDI, |
| 0 | 476 RSI, |
| 477 RCX, | |
| 478 RBX, | |
| 479 R8, | |
| 480 R9, | |
| 481 R10, | |
| 482 R11, | |
| 483 R13, | |
| 484 R14); | |
| 485 | |
| 486 // Singleton class for RAX int register | |
| 487 reg_class int_rax_reg(RAX); | |
| 488 | |
| 489 // Singleton class for RBX int register | |
| 490 reg_class int_rbx_reg(RBX); | |
| 491 | |
| 492 // Singleton class for RCX int register | |
| 493 reg_class int_rcx_reg(RCX); | |
| 494 | |
| 495 // Singleton class for RCX int register | |
| 496 reg_class int_rdx_reg(RDX); | |
| 497 | |
| 498 // Singleton class for RCX int register | |
| 499 reg_class int_rdi_reg(RDI); | |
| 500 | |
| 501 // Singleton class for instruction pointer | |
| 502 // reg_class ip_reg(RIP); | |
| 503 | |
| 504 // Singleton class for condition codes | |
| 505 reg_class int_flags(RFLAGS); | |
| 506 | |
| 507 // Class for all float registers | |
| 508 reg_class float_reg(XMM0, | |
| 509 XMM1, | |
| 510 XMM2, | |
| 511 XMM3, | |
| 512 XMM4, | |
| 513 XMM5, | |
| 514 XMM6, | |
| 515 XMM7, | |
| 516 XMM8, | |
| 517 XMM9, | |
| 518 XMM10, | |
| 519 XMM11, | |
| 520 XMM12, | |
| 521 XMM13, | |
| 522 XMM14, | |
| 523 XMM15); | |
| 524 | |
| 525 // Class for all double registers | |
| 526 reg_class double_reg(XMM0, XMM0_H, | |
| 527 XMM1, XMM1_H, | |
| 528 XMM2, XMM2_H, | |
| 529 XMM3, XMM3_H, | |
| 530 XMM4, XMM4_H, | |
| 531 XMM5, XMM5_H, | |
| 532 XMM6, XMM6_H, | |
| 533 XMM7, XMM7_H, | |
| 534 XMM8, XMM8_H, | |
| 535 XMM9, XMM9_H, | |
| 536 XMM10, XMM10_H, | |
| 537 XMM11, XMM11_H, | |
| 538 XMM12, XMM12_H, | |
| 539 XMM13, XMM13_H, | |
| 540 XMM14, XMM14_H, | |
| 541 XMM15, XMM15_H); | |
| 542 %} | |
| 543 | |
| 544 | |
| 545 //----------SOURCE BLOCK------------------------------------------------------- | |
| 546 // This is a block of C++ code which provides values, functions, and | |
| 547 // definitions necessary in the rest of the architecture description | |
| 548 source %{ | |
| 304 | 549 #define RELOC_IMM64 Assembler::imm_operand |
| 0 | 550 #define RELOC_DISP32 Assembler::disp32_operand |
| 551 | |
| 552 #define __ _masm. | |
| 553 | |
|
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554 static int preserve_SP_size() { |
| 4759 | 555 return 3; // rex.w, op, rm(reg/reg) |
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556 } |
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557 |
| 0 | 558 // !!!!! Special hack to get all types of calls to specify the byte offset |
| 559 // from the start of the call to the point where the return address | |
| 560 // will point. | |
| 561 int MachCallStaticJavaNode::ret_addr_offset() | |
| 562 { | |
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563 int offset = 5; // 5 bytes from start of call to where return address points |
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564 if (_method_handle_invoke) |
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565 offset += preserve_SP_size(); |
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566 return offset; |
| 0 | 567 } |
| 568 | |
| 569 int MachCallDynamicJavaNode::ret_addr_offset() | |
| 570 { | |
| 571 return 15; // 15 bytes from start of call to where return address points | |
| 572 } | |
| 573 | |
| 574 // In os_cpu .ad file | |
| 575 // int MachCallRuntimeNode::ret_addr_offset() | |
| 576 | |
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577 // Indicate if the safepoint node needs the polling page as an input, |
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578 // it does if the polling page is more than disp32 away. |
| 0 | 579 bool SafePointNode::needs_polling_address_input() |
| 580 { | |
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581 return Assembler::is_polling_page_far(); |
| 0 | 582 } |
| 583 | |
| 584 // | |
| 585 // Compute padding required for nodes which need alignment | |
| 586 // | |
| 587 | |
| 588 // The address of the call instruction needs to be 4-byte aligned to | |
| 589 // ensure that it does not span a cache line so that it can be patched. | |
| 590 int CallStaticJavaDirectNode::compute_padding(int current_offset) const | |
| 591 { | |
| 592 current_offset += 1; // skip call opcode byte | |
| 593 return round_to(current_offset, alignment_required()) - current_offset; | |
| 594 } | |
| 595 | |
| 596 // The address of the call instruction needs to be 4-byte aligned to | |
| 597 // ensure that it does not span a cache line so that it can be patched. | |
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598 int CallStaticJavaHandleNode::compute_padding(int current_offset) const |
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599 { |
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600 current_offset += preserve_SP_size(); // skip mov rbp, rsp |
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601 current_offset += 1; // skip call opcode byte |
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602 return round_to(current_offset, alignment_required()) - current_offset; |
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603 } |
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604 |
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605 // The address of the call instruction needs to be 4-byte aligned to |
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606 // ensure that it does not span a cache line so that it can be patched. |
| 0 | 607 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const |
| 608 { | |
| 609 current_offset += 11; // skip movq instruction + call opcode byte | |
| 610 return round_to(current_offset, alignment_required()) - current_offset; | |
| 611 } | |
| 612 | |
| 613 #ifndef PRODUCT | |
| 614 void MachBreakpointNode::format(PhaseRegAlloc*, outputStream* st) const | |
| 615 { | |
| 616 st->print("INT3"); | |
| 617 } | |
| 618 #endif | |
| 619 | |
| 620 // EMIT_RM() | |
| 1748 | 621 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) { |
| 0 | 622 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3); |
| 1748 | 623 cbuf.insts()->emit_int8(c); |
| 0 | 624 } |
| 625 | |
| 626 // EMIT_CC() | |
| 1748 | 627 void emit_cc(CodeBuffer &cbuf, int f1, int f2) { |
| 0 | 628 unsigned char c = (unsigned char) (f1 | f2); |
| 1748 | 629 cbuf.insts()->emit_int8(c); |
| 0 | 630 } |
| 631 | |
| 632 // EMIT_OPCODE() | |
| 1748 | 633 void emit_opcode(CodeBuffer &cbuf, int code) { |
| 634 cbuf.insts()->emit_int8((unsigned char) code); | |
| 0 | 635 } |
| 636 | |
| 637 // EMIT_OPCODE() w/ relocation information | |
| 638 void emit_opcode(CodeBuffer &cbuf, | |
| 639 int code, relocInfo::relocType reloc, int offset, int format) | |
| 640 { | |
| 1748 | 641 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format); |
| 0 | 642 emit_opcode(cbuf, code); |
| 643 } | |
| 644 | |
| 645 // EMIT_D8() | |
| 1748 | 646 void emit_d8(CodeBuffer &cbuf, int d8) { |
| 647 cbuf.insts()->emit_int8((unsigned char) d8); | |
| 0 | 648 } |
| 649 | |
| 650 // EMIT_D16() | |
| 1748 | 651 void emit_d16(CodeBuffer &cbuf, int d16) { |
| 652 cbuf.insts()->emit_int16(d16); | |
| 0 | 653 } |
| 654 | |
| 655 // EMIT_D32() | |
| 1748 | 656 void emit_d32(CodeBuffer &cbuf, int d32) { |
| 657 cbuf.insts()->emit_int32(d32); | |
| 0 | 658 } |
| 659 | |
| 660 // EMIT_D64() | |
| 1748 | 661 void emit_d64(CodeBuffer &cbuf, int64_t d64) { |
| 662 cbuf.insts()->emit_int64(d64); | |
| 0 | 663 } |
| 664 | |
| 665 // emit 32 bit value and construct relocation entry from relocInfo::relocType | |
| 666 void emit_d32_reloc(CodeBuffer& cbuf, | |
| 667 int d32, | |
| 668 relocInfo::relocType reloc, | |
| 669 int format) | |
| 670 { | |
| 671 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc"); | |
| 1748 | 672 cbuf.relocate(cbuf.insts_mark(), reloc, format); |
| 673 cbuf.insts()->emit_int32(d32); | |
| 0 | 674 } |
| 675 | |
| 676 // emit 32 bit value and construct relocation entry from RelocationHolder | |
| 1748 | 677 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) { |
| 0 | 678 #ifdef ASSERT |
| 679 if (rspec.reloc()->type() == relocInfo::oop_type && | |
| 680 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) { | |
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681 assert(oop((intptr_t)d32)->is_oop() && (ScavengeRootsInCode || !oop((intptr_t)d32)->is_scavengable()), "cannot embed scavengable oops in code"); |
| 0 | 682 } |
| 683 #endif | |
| 1748 | 684 cbuf.relocate(cbuf.insts_mark(), rspec, format); |
| 685 cbuf.insts()->emit_int32(d32); | |
| 0 | 686 } |
| 687 | |
| 688 void emit_d32_reloc(CodeBuffer& cbuf, address addr) { | |
| 1748 | 689 address next_ip = cbuf.insts_end() + 4; |
| 0 | 690 emit_d32_reloc(cbuf, (int) (addr - next_ip), |
| 691 external_word_Relocation::spec(addr), | |
| 692 RELOC_DISP32); | |
| 693 } | |
| 694 | |
| 695 | |
| 696 // emit 64 bit value and construct relocation entry from relocInfo::relocType | |
| 1748 | 697 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) { |
| 698 cbuf.relocate(cbuf.insts_mark(), reloc, format); | |
| 699 cbuf.insts()->emit_int64(d64); | |
| 0 | 700 } |
| 701 | |
| 702 // emit 64 bit value and construct relocation entry from RelocationHolder | |
| 1748 | 703 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) { |
| 0 | 704 #ifdef ASSERT |
| 705 if (rspec.reloc()->type() == relocInfo::oop_type && | |
| 706 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) { | |
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707 assert(oop(d64)->is_oop() && (ScavengeRootsInCode || !oop(d64)->is_scavengable()), |
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708 "cannot embed scavengable oops in code"); |
| 0 | 709 } |
| 710 #endif | |
| 1748 | 711 cbuf.relocate(cbuf.insts_mark(), rspec, format); |
| 712 cbuf.insts()->emit_int64(d64); | |
| 0 | 713 } |
| 714 | |
| 715 // Access stack slot for load or store | |
| 716 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) | |
| 717 { | |
| 718 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src]) | |
| 719 if (-0x80 <= disp && disp < 0x80) { | |
| 720 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte | |
| 721 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte | |
| 722 emit_d8(cbuf, disp); // Displacement // R/M byte | |
| 723 } else { | |
| 724 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte | |
| 725 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte | |
| 726 emit_d32(cbuf, disp); // Displacement // R/M byte | |
| 727 } | |
| 728 } | |
| 729 | |
| 730 // rRegI ereg, memory mem) %{ // emit_reg_mem | |
| 731 void encode_RegMem(CodeBuffer &cbuf, | |
| 732 int reg, | |
| 733 int base, int index, int scale, int disp, bool disp_is_oop) | |
| 734 { | |
| 735 assert(!disp_is_oop, "cannot have disp"); | |
| 736 int regenc = reg & 7; | |
| 737 int baseenc = base & 7; | |
| 738 int indexenc = index & 7; | |
| 739 | |
| 740 // There is no index & no scale, use form without SIB byte | |
| 741 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) { | |
| 742 // If no displacement, mode is 0x0; unless base is [RBP] or [R13] | |
| 743 if (disp == 0 && base != RBP_enc && base != R13_enc) { | |
| 744 emit_rm(cbuf, 0x0, regenc, baseenc); // * | |
| 745 } else if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) { | |
| 746 // If 8-bit displacement, mode 0x1 | |
| 747 emit_rm(cbuf, 0x1, regenc, baseenc); // * | |
| 748 emit_d8(cbuf, disp); | |
| 749 } else { | |
| 750 // If 32-bit displacement | |
| 751 if (base == -1) { // Special flag for absolute address | |
| 752 emit_rm(cbuf, 0x0, regenc, 0x5); // * | |
| 753 if (disp_is_oop) { | |
| 754 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32); | |
| 755 } else { | |
| 756 emit_d32(cbuf, disp); | |
| 757 } | |
| 758 } else { | |
| 759 // Normal base + offset | |
| 760 emit_rm(cbuf, 0x2, regenc, baseenc); // * | |
| 761 if (disp_is_oop) { | |
| 762 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32); | |
| 763 } else { | |
| 764 emit_d32(cbuf, disp); | |
| 765 } | |
| 766 } | |
| 767 } | |
| 768 } else { | |
| 769 // Else, encode with the SIB byte | |
| 770 // If no displacement, mode is 0x0; unless base is [RBP] or [R13] | |
| 771 if (disp == 0 && base != RBP_enc && base != R13_enc) { | |
| 772 // If no displacement | |
| 773 emit_rm(cbuf, 0x0, regenc, 0x4); // * | |
| 774 emit_rm(cbuf, scale, indexenc, baseenc); | |
| 775 } else { | |
| 776 if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) { | |
| 777 // If 8-bit displacement, mode 0x1 | |
| 778 emit_rm(cbuf, 0x1, regenc, 0x4); // * | |
| 779 emit_rm(cbuf, scale, indexenc, baseenc); | |
| 780 emit_d8(cbuf, disp); | |
| 781 } else { | |
| 782 // If 32-bit displacement | |
| 783 if (base == 0x04 ) { | |
| 784 emit_rm(cbuf, 0x2, regenc, 0x4); | |
| 785 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid??? | |
| 786 } else { | |
| 787 emit_rm(cbuf, 0x2, regenc, 0x4); | |
| 788 emit_rm(cbuf, scale, indexenc, baseenc); // * | |
| 789 } | |
| 790 if (disp_is_oop) { | |
| 791 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32); | |
| 792 } else { | |
| 793 emit_d32(cbuf, disp); | |
| 794 } | |
| 795 } | |
| 796 } | |
| 797 } | |
| 798 } | |
| 799 | |
| 3783 | 800 // This could be in MacroAssembler but it's fairly C2 specific |
| 801 void emit_cmpfp_fixup(MacroAssembler& _masm) { | |
| 802 Label exit; | |
| 803 __ jccb(Assembler::noParity, exit); | |
| 804 __ pushf(); | |
| 4759 | 805 // |
| 806 // comiss/ucomiss instructions set ZF,PF,CF flags and | |
| 807 // zero OF,AF,SF for NaN values. | |
| 808 // Fixup flags by zeroing ZF,PF so that compare of NaN | |
| 809 // values returns 'less than' result (CF is set). | |
| 810 // Leave the rest of flags unchanged. | |
| 811 // | |
| 812 // 7 6 5 4 3 2 1 0 | |
| 813 // |S|Z|r|A|r|P|r|C| (r - reserved bit) | |
| 814 // 0 0 1 0 1 0 1 1 (0x2B) | |
| 815 // | |
| 3783 | 816 __ andq(Address(rsp, 0), 0xffffff2b); |
| 817 __ popf(); | |
| 818 __ bind(exit); | |
| 4759 | 819 } |
| 820 | |
| 821 void emit_cmpfp3(MacroAssembler& _masm, Register dst) { | |
| 822 Label done; | |
| 823 __ movl(dst, -1); | |
| 824 __ jcc(Assembler::parity, done); | |
| 825 __ jcc(Assembler::below, done); | |
| 826 __ setb(Assembler::notEqual, dst); | |
| 827 __ movzbl(dst, dst); | |
| 828 __ bind(done); | |
| 3783 | 829 } |
| 830 | |
| 0 | 831 |
| 832 //============================================================================= | |
| 2008 | 833 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty; |
| 834 | |
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835 int Compile::ConstantTable::calculate_table_base_offset() const { |
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836 return 0; // absolute addressing, no offset |
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837 } |
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838 |
| 2008 | 839 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { |
| 840 // Empty encoding | |
| 841 } | |
| 842 | |
| 843 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const { | |
| 844 return 0; | |
| 845 } | |
| 846 | |
| 847 #ifndef PRODUCT | |
| 848 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { | |
| 849 st->print("# MachConstantBaseNode (empty encoding)"); | |
| 850 } | |
| 851 #endif | |
| 852 | |
| 853 | |
| 854 //============================================================================= | |
| 0 | 855 #ifndef PRODUCT |
| 856 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const | |
| 857 { | |
| 858 Compile* C = ra_->C; | |
| 859 | |
| 860 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 861 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 862 // Remove wordSize for return adr already pushed | |
| 863 // and another for the RBP we are going to save | |
| 864 framesize -= 2*wordSize; | |
| 865 bool need_nop = true; | |
| 866 | |
| 867 // Calls to C2R adapters often do not accept exceptional returns. | |
| 868 // We require that their callers must bang for them. But be | |
| 869 // careful, because some VM calls (such as call site linkage) can | |
| 870 // use several kilobytes of stack. But the stack safety zone should | |
| 871 // account for that. See bugs 4446381, 4468289, 4497237. | |
| 872 if (C->need_stack_bang(framesize)) { | |
| 873 st->print_cr("# stack bang"); st->print("\t"); | |
| 874 need_nop = false; | |
| 875 } | |
| 876 st->print_cr("pushq rbp"); st->print("\t"); | |
| 877 | |
| 878 if (VerifyStackAtCalls) { | |
| 879 // Majik cookie to verify stack depth | |
| 880 st->print_cr("pushq 0xffffffffbadb100d" | |
| 881 "\t# Majik cookie for stack depth check"); | |
| 882 st->print("\t"); | |
| 883 framesize -= wordSize; // Remove 2 for cookie | |
| 884 need_nop = false; | |
| 885 } | |
| 886 | |
| 887 if (framesize) { | |
| 888 st->print("subq rsp, #%d\t# Create frame", framesize); | |
| 889 if (framesize < 0x80 && need_nop) { | |
| 890 st->print("\n\tnop\t# nop for patch_verified_entry"); | |
| 891 } | |
| 892 } | |
| 893 } | |
| 894 #endif | |
| 895 | |
| 896 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const | |
| 897 { | |
| 898 Compile* C = ra_->C; | |
| 899 | |
| 900 // WARNING: Initial instruction MUST be 5 bytes or longer so that | |
| 901 // NativeJump::patch_verified_entry will be able to patch out the entry | |
| 902 // code safely. The fldcw is ok at 6 bytes, the push to verify stack | |
| 903 // depth is ok at 5 bytes, the frame allocation can be either 3 or | |
| 904 // 6 bytes. So if we don't do the fldcw or the push then we must | |
| 905 // use the 6 byte frame allocation even if we have no frame. :-( | |
| 906 // If method sets FPU control word do it now | |
| 907 | |
| 908 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 909 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 910 // Remove wordSize for return adr already pushed | |
| 911 // and another for the RBP we are going to save | |
| 912 framesize -= 2*wordSize; | |
| 913 bool need_nop = true; | |
| 914 | |
| 915 // Calls to C2R adapters often do not accept exceptional returns. | |
| 916 // We require that their callers must bang for them. But be | |
| 917 // careful, because some VM calls (such as call site linkage) can | |
| 918 // use several kilobytes of stack. But the stack safety zone should | |
| 919 // account for that. See bugs 4446381, 4468289, 4497237. | |
| 920 if (C->need_stack_bang(framesize)) { | |
| 921 MacroAssembler masm(&cbuf); | |
| 922 masm.generate_stack_overflow_check(framesize); | |
| 923 need_nop = false; | |
| 924 } | |
| 925 | |
| 926 // We always push rbp so that on return to interpreter rbp will be | |
| 927 // restored correctly and we can correct the stack. | |
| 928 emit_opcode(cbuf, 0x50 | RBP_enc); | |
| 929 | |
| 930 if (VerifyStackAtCalls) { | |
| 931 // Majik cookie to verify stack depth | |
| 932 emit_opcode(cbuf, 0x68); // pushq (sign-extended) 0xbadb100d | |
| 933 emit_d32(cbuf, 0xbadb100d); | |
| 934 framesize -= wordSize; // Remove 2 for cookie | |
| 935 need_nop = false; | |
| 936 } | |
| 937 | |
| 938 if (framesize) { | |
| 939 emit_opcode(cbuf, Assembler::REX_W); | |
| 940 if (framesize < 0x80) { | |
| 941 emit_opcode(cbuf, 0x83); // sub SP,#framesize | |
| 942 emit_rm(cbuf, 0x3, 0x05, RSP_enc); | |
| 943 emit_d8(cbuf, framesize); | |
| 944 if (need_nop) { | |
| 945 emit_opcode(cbuf, 0x90); // nop | |
| 946 } | |
| 947 } else { | |
| 948 emit_opcode(cbuf, 0x81); // sub SP,#framesize | |
| 949 emit_rm(cbuf, 0x3, 0x05, RSP_enc); | |
| 950 emit_d32(cbuf, framesize); | |
| 951 } | |
| 952 } | |
| 953 | |
| 1748 | 954 C->set_frame_complete(cbuf.insts_size()); |
| 0 | 955 |
| 956 #ifdef ASSERT | |
| 957 if (VerifyStackAtCalls) { | |
| 958 Label L; | |
| 959 MacroAssembler masm(&cbuf); | |
| 304 | 960 masm.push(rax); |
| 961 masm.mov(rax, rsp); | |
| 962 masm.andptr(rax, StackAlignmentInBytes-1); | |
| 963 masm.cmpptr(rax, StackAlignmentInBytes-wordSize); | |
| 964 masm.pop(rax); | |
| 0 | 965 masm.jcc(Assembler::equal, L); |
| 966 masm.stop("Stack is not properly aligned!"); | |
| 967 masm.bind(L); | |
| 968 } | |
| 969 #endif | |
|
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970 |
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971 if (C->has_mach_constant_base_node()) { |
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972 // NOTE: We set the table base offset here because users might be |
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973 // emitted before MachConstantBaseNode. |
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974 Compile::ConstantTable& constant_table = C->constant_table(); |
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975 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset()); |
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976 } |
| 0 | 977 } |
| 978 | |
| 979 uint MachPrologNode::size(PhaseRegAlloc* ra_) const | |
| 980 { | |
| 981 return MachNode::size(ra_); // too many variables; just compute it | |
| 982 // the hard way | |
| 983 } | |
| 984 | |
| 985 int MachPrologNode::reloc() const | |
| 986 { | |
| 987 return 0; // a large enough number | |
| 988 } | |
| 989 | |
| 990 //============================================================================= | |
| 991 #ifndef PRODUCT | |
| 992 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const | |
| 993 { | |
| 994 Compile* C = ra_->C; | |
| 995 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 996 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 997 // Remove word for return adr already pushed | |
| 998 // and RBP | |
| 999 framesize -= 2*wordSize; | |
| 1000 | |
| 1001 if (framesize) { | |
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1002 st->print_cr("addq rsp, %d\t# Destroy frame", framesize); |
| 0 | 1003 st->print("\t"); |
| 1004 } | |
| 1005 | |
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1006 st->print_cr("popq rbp"); |
| 0 | 1007 if (do_polling() && C->is_method_compilation()) { |
| 1008 st->print("\t"); | |
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1009 if (Assembler::is_polling_page_far()) { |
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1010 st->print_cr("movq rscratch1, #polling_page_address\n\t" |
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1011 "testl rax, [rscratch1]\t" |
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1012 "# Safepoint: poll for GC"); |
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1013 } else { |
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1014 st->print_cr("testl rax, [rip + #offset_to_poll_page]\t" |
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1015 "# Safepoint: poll for GC"); |
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1016 } |
| 0 | 1017 } |
| 1018 } | |
| 1019 #endif | |
| 1020 | |
| 1021 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const | |
| 1022 { | |
| 1023 Compile* C = ra_->C; | |
| 1024 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 1025 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 1026 // Remove word for return adr already pushed | |
| 1027 // and RBP | |
| 1028 framesize -= 2*wordSize; | |
| 1029 | |
| 1030 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here | |
| 1031 | |
| 1032 if (framesize) { | |
| 1033 emit_opcode(cbuf, Assembler::REX_W); | |
| 1034 if (framesize < 0x80) { | |
| 1035 emit_opcode(cbuf, 0x83); // addq rsp, #framesize | |
| 1036 emit_rm(cbuf, 0x3, 0x00, RSP_enc); | |
| 1037 emit_d8(cbuf, framesize); | |
| 1038 } else { | |
| 1039 emit_opcode(cbuf, 0x81); // addq rsp, #framesize | |
| 1040 emit_rm(cbuf, 0x3, 0x00, RSP_enc); | |
| 1041 emit_d32(cbuf, framesize); | |
| 1042 } | |
| 1043 } | |
| 1044 | |
| 1045 // popq rbp | |
| 1046 emit_opcode(cbuf, 0x58 | RBP_enc); | |
| 1047 | |
| 1048 if (do_polling() && C->is_method_compilation()) { | |
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1049 MacroAssembler _masm(&cbuf); |
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1050 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type); |
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1051 if (Assembler::is_polling_page_far()) { |
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1052 __ lea(rscratch1, polling_page); |
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1053 __ relocate(relocInfo::poll_return_type); |
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1054 __ testl(rax, Address(rscratch1, 0)); |
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1055 } else { |
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1056 __ testl(rax, polling_page); |
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1057 } |
| 0 | 1058 } |
| 1059 } | |
| 1060 | |
| 1061 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const | |
| 1062 { | |
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1063 return MachNode::size(ra_); // too many variables; just compute it |
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1064 // the hard way |
| 0 | 1065 } |
| 1066 | |
| 1067 int MachEpilogNode::reloc() const | |
| 1068 { | |
| 1069 return 2; // a large enough number | |
| 1070 } | |
| 1071 | |
| 1072 const Pipeline* MachEpilogNode::pipeline() const | |
| 1073 { | |
| 1074 return MachNode::pipeline_class(); | |
| 1075 } | |
| 1076 | |
| 1077 int MachEpilogNode::safepoint_offset() const | |
| 1078 { | |
| 1079 return 0; | |
| 1080 } | |
| 1081 | |
| 1082 //============================================================================= | |
| 1083 | |
| 1084 enum RC { | |
| 1085 rc_bad, | |
| 1086 rc_int, | |
| 1087 rc_float, | |
| 1088 rc_stack | |
| 1089 }; | |
| 1090 | |
| 1091 static enum RC rc_class(OptoReg::Name reg) | |
| 1092 { | |
| 1093 if( !OptoReg::is_valid(reg) ) return rc_bad; | |
| 1094 | |
| 1095 if (OptoReg::is_stack(reg)) return rc_stack; | |
| 1096 | |
| 1097 VMReg r = OptoReg::as_VMReg(reg); | |
| 1098 | |
| 1099 if (r->is_Register()) return rc_int; | |
| 1100 | |
| 1101 assert(r->is_XMMRegister(), "must be"); | |
| 1102 return rc_float; | |
| 1103 } | |
| 1104 | |
| 1105 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf, | |
| 1106 PhaseRegAlloc* ra_, | |
| 1107 bool do_size, | |
| 1108 outputStream* st) const | |
| 1109 { | |
| 1110 | |
| 1111 // Get registers to move | |
| 1112 OptoReg::Name src_second = ra_->get_reg_second(in(1)); | |
| 1113 OptoReg::Name src_first = ra_->get_reg_first(in(1)); | |
| 1114 OptoReg::Name dst_second = ra_->get_reg_second(this); | |
| 1115 OptoReg::Name dst_first = ra_->get_reg_first(this); | |
| 1116 | |
| 1117 enum RC src_second_rc = rc_class(src_second); | |
| 1118 enum RC src_first_rc = rc_class(src_first); | |
| 1119 enum RC dst_second_rc = rc_class(dst_second); | |
| 1120 enum RC dst_first_rc = rc_class(dst_first); | |
| 1121 | |
| 1122 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), | |
| 1123 "must move at least 1 register" ); | |
| 1124 | |
| 1125 if (src_first == dst_first && src_second == dst_second) { | |
| 1126 // Self copy, no move | |
| 1127 return 0; | |
| 1128 } else if (src_first_rc == rc_stack) { | |
| 1129 // mem -> | |
| 1130 if (dst_first_rc == rc_stack) { | |
| 1131 // mem -> mem | |
| 1132 assert(src_second != dst_first, "overlap"); | |
| 1133 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1134 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1135 // 64-bit | |
| 1136 int src_offset = ra_->reg2offset(src_first); | |
| 1137 int dst_offset = ra_->reg2offset(dst_first); | |
| 1138 if (cbuf) { | |
| 1139 emit_opcode(*cbuf, 0xFF); | |
| 1140 encode_RegMem(*cbuf, RSI_enc, RSP_enc, 0x4, 0, src_offset, false); | |
| 1141 | |
| 1142 emit_opcode(*cbuf, 0x8F); | |
| 1143 encode_RegMem(*cbuf, RAX_enc, RSP_enc, 0x4, 0, dst_offset, false); | |
| 1144 | |
| 1145 #ifndef PRODUCT | |
| 1146 } else if (!do_size) { | |
| 1147 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t" | |
| 1148 "popq [rsp + #%d]", | |
| 1149 src_offset, | |
| 1150 dst_offset); | |
| 1151 #endif | |
| 1152 } | |
| 1153 return | |
| 1154 3 + ((src_offset == 0) ? 0 : (src_offset < 0x80 ? 1 : 4)) + | |
| 1155 3 + ((dst_offset == 0) ? 0 : (dst_offset < 0x80 ? 1 : 4)); | |
| 1156 } else { | |
| 1157 // 32-bit | |
| 1158 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1159 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1160 // No pushl/popl, so: | |
| 1161 int src_offset = ra_->reg2offset(src_first); | |
| 1162 int dst_offset = ra_->reg2offset(dst_first); | |
| 1163 if (cbuf) { | |
| 1164 emit_opcode(*cbuf, Assembler::REX_W); | |
| 1165 emit_opcode(*cbuf, 0x89); | |
| 1166 emit_opcode(*cbuf, 0x44); | |
| 1167 emit_opcode(*cbuf, 0x24); | |
| 1168 emit_opcode(*cbuf, 0xF8); | |
| 1169 | |
| 1170 emit_opcode(*cbuf, 0x8B); | |
| 1171 encode_RegMem(*cbuf, | |
| 1172 RAX_enc, | |
| 1173 RSP_enc, 0x4, 0, src_offset, | |
| 1174 false); | |
| 1175 | |
| 1176 emit_opcode(*cbuf, 0x89); | |
| 1177 encode_RegMem(*cbuf, | |
| 1178 RAX_enc, | |
| 1179 RSP_enc, 0x4, 0, dst_offset, | |
| 1180 false); | |
| 1181 | |
| 1182 emit_opcode(*cbuf, Assembler::REX_W); | |
| 1183 emit_opcode(*cbuf, 0x8B); | |
| 1184 emit_opcode(*cbuf, 0x44); | |
| 1185 emit_opcode(*cbuf, 0x24); | |
| 1186 emit_opcode(*cbuf, 0xF8); | |
| 1187 | |
| 1188 #ifndef PRODUCT | |
| 1189 } else if (!do_size) { | |
| 1190 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t" | |
| 1191 "movl rax, [rsp + #%d]\n\t" | |
| 1192 "movl [rsp + #%d], rax\n\t" | |
| 1193 "movq rax, [rsp - #8]", | |
| 1194 src_offset, | |
| 1195 dst_offset); | |
| 1196 #endif | |
| 1197 } | |
| 1198 return | |
| 1199 5 + // movq | |
| 1200 3 + ((src_offset == 0) ? 0 : (src_offset < 0x80 ? 1 : 4)) + // movl | |
| 1201 3 + ((dst_offset == 0) ? 0 : (dst_offset < 0x80 ? 1 : 4)) + // movl | |
| 1202 5; // movq | |
| 1203 } | |
| 1204 } else if (dst_first_rc == rc_int) { | |
| 1205 // mem -> gpr | |
| 1206 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1207 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1208 // 64-bit | |
| 1209 int offset = ra_->reg2offset(src_first); | |
| 1210 if (cbuf) { | |
| 1211 if (Matcher::_regEncode[dst_first] < 8) { | |
| 1212 emit_opcode(*cbuf, Assembler::REX_W); | |
| 1213 } else { | |
| 1214 emit_opcode(*cbuf, Assembler::REX_WR); | |
| 1215 } | |
| 1216 emit_opcode(*cbuf, 0x8B); | |
| 1217 encode_RegMem(*cbuf, | |
| 1218 Matcher::_regEncode[dst_first], | |
| 1219 RSP_enc, 0x4, 0, offset, | |
| 1220 false); | |
| 1221 #ifndef PRODUCT | |
| 1222 } else if (!do_size) { | |
| 1223 st->print("movq %s, [rsp + #%d]\t# spill", | |
| 1224 Matcher::regName[dst_first], | |
| 1225 offset); | |
| 1226 #endif | |
| 1227 } | |
| 1228 return | |
| 1229 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + 4; // REX | |
| 1230 } else { | |
| 1231 // 32-bit | |
| 1232 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1233 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1234 int offset = ra_->reg2offset(src_first); | |
| 1235 if (cbuf) { | |
| 1236 if (Matcher::_regEncode[dst_first] >= 8) { | |
| 1237 emit_opcode(*cbuf, Assembler::REX_R); | |
| 1238 } | |
| 1239 emit_opcode(*cbuf, 0x8B); | |
| 1240 encode_RegMem(*cbuf, | |
| 1241 Matcher::_regEncode[dst_first], | |
| 1242 RSP_enc, 0x4, 0, offset, | |
| 1243 false); | |
| 1244 #ifndef PRODUCT | |
| 1245 } else if (!do_size) { | |
| 1246 st->print("movl %s, [rsp + #%d]\t# spill", | |
| 1247 Matcher::regName[dst_first], | |
| 1248 offset); | |
| 1249 #endif | |
| 1250 } | |
| 1251 return | |
| 1252 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + | |
| 1253 ((Matcher::_regEncode[dst_first] < 8) | |
| 1254 ? 3 | |
| 1255 : 4); // REX | |
| 1256 } | |
| 1257 } else if (dst_first_rc == rc_float) { | |
| 1258 // mem-> xmm | |
| 1259 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1260 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1261 // 64-bit | |
| 1262 int offset = ra_->reg2offset(src_first); | |
| 1263 if (cbuf) { | |
| 4759 | 1264 MacroAssembler _masm(cbuf); |
| 1265 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset)); | |
| 0 | 1266 #ifndef PRODUCT |
| 1267 } else if (!do_size) { | |
| 1268 st->print("%s %s, [rsp + #%d]\t# spill", | |
| 1269 UseXmmLoadAndClearUpper ? "movsd " : "movlpd", | |
| 1270 Matcher::regName[dst_first], | |
| 1271 offset); | |
| 1272 #endif | |
| 1273 } | |
| 1274 return | |
| 1275 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + | |
| 4759 | 1276 ((Matcher::_regEncode[dst_first] >= 8) |
| 1277 ? 6 | |
| 1278 : (5 + ((UseAVX>0)?1:0))); // REX | |
| 0 | 1279 } else { |
| 1280 // 32-bit | |
| 1281 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1282 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1283 int offset = ra_->reg2offset(src_first); | |
| 1284 if (cbuf) { | |
| 4759 | 1285 MacroAssembler _masm(cbuf); |
| 1286 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset)); | |
| 0 | 1287 #ifndef PRODUCT |
| 1288 } else if (!do_size) { | |
| 1289 st->print("movss %s, [rsp + #%d]\t# spill", | |
| 1290 Matcher::regName[dst_first], | |
| 1291 offset); | |
| 1292 #endif | |
| 1293 } | |
| 1294 return | |
| 1295 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + | |
| 4759 | 1296 ((Matcher::_regEncode[dst_first] >= 8) |
| 1297 ? 6 | |
| 1298 : (5 + ((UseAVX>0)?1:0))); // REX | |
| 0 | 1299 } |
| 1300 } | |
| 1301 } else if (src_first_rc == rc_int) { | |
| 1302 // gpr -> | |
| 1303 if (dst_first_rc == rc_stack) { | |
| 1304 // gpr -> mem | |
| 1305 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1306 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1307 // 64-bit | |
| 1308 int offset = ra_->reg2offset(dst_first); | |
| 1309 if (cbuf) { | |
| 1310 if (Matcher::_regEncode[src_first] < 8) { | |
| 1311 emit_opcode(*cbuf, Assembler::REX_W); | |
| 1312 } else { | |
| 1313 emit_opcode(*cbuf, Assembler::REX_WR); | |
| 1314 } | |
| 1315 emit_opcode(*cbuf, 0x89); | |
| 1316 encode_RegMem(*cbuf, | |
| 1317 Matcher::_regEncode[src_first], | |
| 1318 RSP_enc, 0x4, 0, offset, | |
| 1319 false); | |
| 1320 #ifndef PRODUCT | |
| 1321 } else if (!do_size) { | |
| 1322 st->print("movq [rsp + #%d], %s\t# spill", | |
| 1323 offset, | |
| 1324 Matcher::regName[src_first]); | |
| 1325 #endif | |
| 1326 } | |
| 1327 return ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + 4; // REX | |
| 1328 } else { | |
| 1329 // 32-bit | |
| 1330 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1331 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1332 int offset = ra_->reg2offset(dst_first); | |
| 1333 if (cbuf) { | |
| 1334 if (Matcher::_regEncode[src_first] >= 8) { | |
| 1335 emit_opcode(*cbuf, Assembler::REX_R); | |
| 1336 } | |
| 1337 emit_opcode(*cbuf, 0x89); | |
| 1338 encode_RegMem(*cbuf, | |
| 1339 Matcher::_regEncode[src_first], | |
| 1340 RSP_enc, 0x4, 0, offset, | |
| 1341 false); | |
| 1342 #ifndef PRODUCT | |
| 1343 } else if (!do_size) { | |
| 1344 st->print("movl [rsp + #%d], %s\t# spill", | |
| 1345 offset, | |
| 1346 Matcher::regName[src_first]); | |
| 1347 #endif | |
| 1348 } | |
| 1349 return | |
| 1350 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + | |
| 1351 ((Matcher::_regEncode[src_first] < 8) | |
| 1352 ? 3 | |
| 1353 : 4); // REX | |
| 1354 } | |
| 1355 } else if (dst_first_rc == rc_int) { | |
| 1356 // gpr -> gpr | |
| 1357 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1358 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1359 // 64-bit | |
| 1360 if (cbuf) { | |
| 1361 if (Matcher::_regEncode[dst_first] < 8) { | |
| 1362 if (Matcher::_regEncode[src_first] < 8) { | |
| 1363 emit_opcode(*cbuf, Assembler::REX_W); | |
| 1364 } else { | |
| 1365 emit_opcode(*cbuf, Assembler::REX_WB); | |
| 1366 } | |
| 1367 } else { | |
| 1368 if (Matcher::_regEncode[src_first] < 8) { | |
| 1369 emit_opcode(*cbuf, Assembler::REX_WR); | |
| 1370 } else { | |
| 1371 emit_opcode(*cbuf, Assembler::REX_WRB); | |
| 1372 } | |
| 1373 } | |
| 1374 emit_opcode(*cbuf, 0x8B); | |
| 1375 emit_rm(*cbuf, 0x3, | |
| 1376 Matcher::_regEncode[dst_first] & 7, | |
| 1377 Matcher::_regEncode[src_first] & 7); | |
| 1378 #ifndef PRODUCT | |
| 1379 } else if (!do_size) { | |
| 1380 st->print("movq %s, %s\t# spill", | |
| 1381 Matcher::regName[dst_first], | |
| 1382 Matcher::regName[src_first]); | |
| 1383 #endif | |
| 1384 } | |
| 1385 return 3; // REX | |
| 1386 } else { | |
| 1387 // 32-bit | |
| 1388 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1389 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1390 if (cbuf) { | |
| 1391 if (Matcher::_regEncode[dst_first] < 8) { | |
| 1392 if (Matcher::_regEncode[src_first] >= 8) { | |
| 1393 emit_opcode(*cbuf, Assembler::REX_B); | |
| 1394 } | |
| 1395 } else { | |
| 1396 if (Matcher::_regEncode[src_first] < 8) { | |
| 1397 emit_opcode(*cbuf, Assembler::REX_R); | |
| 1398 } else { | |
| 1399 emit_opcode(*cbuf, Assembler::REX_RB); | |
| 1400 } | |
| 1401 } | |
| 1402 emit_opcode(*cbuf, 0x8B); | |
| 1403 emit_rm(*cbuf, 0x3, | |
| 1404 Matcher::_regEncode[dst_first] & 7, | |
| 1405 Matcher::_regEncode[src_first] & 7); | |
| 1406 #ifndef PRODUCT | |
| 1407 } else if (!do_size) { | |
| 1408 st->print("movl %s, %s\t# spill", | |
| 1409 Matcher::regName[dst_first], | |
| 1410 Matcher::regName[src_first]); | |
| 1411 #endif | |
| 1412 } | |
| 1413 return | |
| 1414 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8) | |
| 1415 ? 2 | |
| 1416 : 3; // REX | |
| 1417 } | |
| 1418 } else if (dst_first_rc == rc_float) { | |
| 1419 // gpr -> xmm | |
| 1420 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1421 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1422 // 64-bit | |
| 1423 if (cbuf) { | |
| 4759 | 1424 MacroAssembler _masm(cbuf); |
| 1425 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first])); | |
| 0 | 1426 #ifndef PRODUCT |
| 1427 } else if (!do_size) { | |
| 1428 st->print("movdq %s, %s\t# spill", | |
| 1429 Matcher::regName[dst_first], | |
| 1430 Matcher::regName[src_first]); | |
| 1431 #endif | |
| 1432 } | |
| 1433 return 5; // REX | |
| 1434 } else { | |
| 1435 // 32-bit | |
| 1436 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1437 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1438 if (cbuf) { | |
| 4759 | 1439 MacroAssembler _masm(cbuf); |
| 1440 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first])); | |
| 0 | 1441 #ifndef PRODUCT |
| 1442 } else if (!do_size) { | |
| 1443 st->print("movdl %s, %s\t# spill", | |
| 1444 Matcher::regName[dst_first], | |
| 1445 Matcher::regName[src_first]); | |
| 1446 #endif | |
| 1447 } | |
| 1448 return | |
| 4759 | 1449 (Matcher::_regEncode[src_first] >= 8 || Matcher::_regEncode[dst_first] >= 8) |
| 1450 ? 5 | |
| 1451 : (4 + ((UseAVX>0)?1:0)); // REX | |
| 0 | 1452 } |
| 1453 } | |
| 1454 } else if (src_first_rc == rc_float) { | |
| 1455 // xmm -> | |
| 1456 if (dst_first_rc == rc_stack) { | |
| 1457 // xmm -> mem | |
| 1458 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1459 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1460 // 64-bit | |
| 1461 int offset = ra_->reg2offset(dst_first); | |
| 1462 if (cbuf) { | |
| 4759 | 1463 MacroAssembler _masm(cbuf); |
| 1464 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first])); | |
| 0 | 1465 #ifndef PRODUCT |
| 1466 } else if (!do_size) { | |
| 1467 st->print("movsd [rsp + #%d], %s\t# spill", | |
| 1468 offset, | |
| 1469 Matcher::regName[src_first]); | |
| 1470 #endif | |
| 1471 } | |
| 1472 return | |
| 1473 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + | |
| 4759 | 1474 ((Matcher::_regEncode[src_first] >= 8) |
| 1475 ? 6 | |
| 1476 : (5 + ((UseAVX>0)?1:0))); // REX | |
| 0 | 1477 } else { |
| 1478 // 32-bit | |
| 1479 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1480 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1481 int offset = ra_->reg2offset(dst_first); | |
| 1482 if (cbuf) { | |
| 4759 | 1483 MacroAssembler _masm(cbuf); |
| 1484 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first])); | |
| 0 | 1485 #ifndef PRODUCT |
| 1486 } else if (!do_size) { | |
| 1487 st->print("movss [rsp + #%d], %s\t# spill", | |
| 1488 offset, | |
| 1489 Matcher::regName[src_first]); | |
| 1490 #endif | |
| 1491 } | |
| 1492 return | |
| 1493 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + | |
| 4759 | 1494 ((Matcher::_regEncode[src_first] >=8) |
| 1495 ? 6 | |
| 1496 : (5 + ((UseAVX>0)?1:0))); // REX | |
| 0 | 1497 } |
| 1498 } else if (dst_first_rc == rc_int) { | |
| 1499 // xmm -> gpr | |
| 1500 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1501 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1502 // 64-bit | |
| 1503 if (cbuf) { | |
| 4759 | 1504 MacroAssembler _masm(cbuf); |
| 1505 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first])); | |
| 0 | 1506 #ifndef PRODUCT |
| 1507 } else if (!do_size) { | |
| 1508 st->print("movdq %s, %s\t# spill", | |
| 1509 Matcher::regName[dst_first], | |
| 1510 Matcher::regName[src_first]); | |
| 1511 #endif | |
| 1512 } | |
| 1513 return 5; // REX | |
| 1514 } else { | |
| 1515 // 32-bit | |
| 1516 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1517 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1518 if (cbuf) { | |
| 4759 | 1519 MacroAssembler _masm(cbuf); |
| 1520 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first])); | |
| 0 | 1521 #ifndef PRODUCT |
| 1522 } else if (!do_size) { | |
| 1523 st->print("movdl %s, %s\t# spill", | |
| 1524 Matcher::regName[dst_first], | |
| 1525 Matcher::regName[src_first]); | |
| 1526 #endif | |
| 1527 } | |
| 1528 return | |
| 4759 | 1529 (Matcher::_regEncode[src_first] >= 8 || Matcher::_regEncode[dst_first] >= 8) |
| 1530 ? 5 | |
| 1531 : (4 + ((UseAVX>0)?1:0)); // REX | |
| 0 | 1532 } |
| 1533 } else if (dst_first_rc == rc_float) { | |
| 1534 // xmm -> xmm | |
| 1535 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1536 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1537 // 64-bit | |
| 1538 if (cbuf) { | |
| 4759 | 1539 MacroAssembler _masm(cbuf); |
| 1540 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first])); | |
| 0 | 1541 #ifndef PRODUCT |
| 1542 } else if (!do_size) { | |
| 1543 st->print("%s %s, %s\t# spill", | |
| 1544 UseXmmRegToRegMoveAll ? "movapd" : "movsd ", | |
| 1545 Matcher::regName[dst_first], | |
| 1546 Matcher::regName[src_first]); | |
| 1547 #endif | |
| 1548 } | |
| 1549 return | |
| 4759 | 1550 (Matcher::_regEncode[src_first] >= 8 || Matcher::_regEncode[dst_first] >= 8) |
| 1551 ? 5 | |
| 1552 : (4 + ((UseAVX>0)?1:0)); // REX | |
| 0 | 1553 } else { |
| 1554 // 32-bit | |
| 1555 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1556 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1557 if (cbuf) { | |
| 4759 | 1558 MacroAssembler _masm(cbuf); |
| 1559 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first])); | |
| 0 | 1560 #ifndef PRODUCT |
| 1561 } else if (!do_size) { | |
| 1562 st->print("%s %s, %s\t# spill", | |
| 1563 UseXmmRegToRegMoveAll ? "movaps" : "movss ", | |
| 1564 Matcher::regName[dst_first], | |
| 1565 Matcher::regName[src_first]); | |
| 1566 #endif | |
| 1567 } | |
| 4759 | 1568 return ((UseAVX>0) ? 5: |
| 1569 ((Matcher::_regEncode[src_first] >= 8 || Matcher::_regEncode[dst_first] >= 8) | |
| 1570 ? (UseXmmRegToRegMoveAll ? 4 : 5) | |
| 1571 : (UseXmmRegToRegMoveAll ? 3 : 4))); // REX | |
| 0 | 1572 } |
| 1573 } | |
| 1574 } | |
| 1575 | |
| 1576 assert(0," foo "); | |
| 1577 Unimplemented(); | |
| 1578 | |
| 1579 return 0; | |
| 1580 } | |
| 1581 | |
| 1582 #ifndef PRODUCT | |
| 1583 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const | |
| 1584 { | |
| 1585 implementation(NULL, ra_, false, st); | |
| 1586 } | |
| 1587 #endif | |
| 1588 | |
| 1589 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const | |
| 1590 { | |
| 1591 implementation(&cbuf, ra_, false, NULL); | |
| 1592 } | |
| 1593 | |
| 1594 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const | |
| 1595 { | |
| 1596 return implementation(NULL, ra_, true, NULL); | |
| 1597 } | |
| 1598 | |
| 1599 //============================================================================= | |
| 1600 #ifndef PRODUCT | |
| 1601 void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const | |
| 1602 { | |
| 1603 st->print("nop \t# %d bytes pad for loops and calls", _count); | |
| 1604 } | |
| 1605 #endif | |
| 1606 | |
| 1607 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const | |
| 1608 { | |
| 1609 MacroAssembler _masm(&cbuf); | |
| 1610 __ nop(_count); | |
| 1611 } | |
| 1612 | |
| 1613 uint MachNopNode::size(PhaseRegAlloc*) const | |
| 1614 { | |
| 1615 return _count; | |
| 1616 } | |
| 1617 | |
| 1618 | |
| 1619 //============================================================================= | |
| 1620 #ifndef PRODUCT | |
| 1621 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const | |
| 1622 { | |
| 1623 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1624 int reg = ra_->get_reg_first(this); | |
| 1625 st->print("leaq %s, [rsp + #%d]\t# box lock", | |
| 1626 Matcher::regName[reg], offset); | |
| 1627 } | |
| 1628 #endif | |
| 1629 | |
| 1630 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const | |
| 1631 { | |
| 1632 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1633 int reg = ra_->get_encode(this); | |
| 1634 if (offset >= 0x80) { | |
| 1635 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR); | |
| 1636 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1637 emit_rm(cbuf, 0x2, reg & 7, 0x04); | |
| 1638 emit_rm(cbuf, 0x0, 0x04, RSP_enc); | |
| 1639 emit_d32(cbuf, offset); | |
| 1640 } else { | |
| 1641 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR); | |
| 1642 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1643 emit_rm(cbuf, 0x1, reg & 7, 0x04); | |
| 1644 emit_rm(cbuf, 0x0, 0x04, RSP_enc); | |
| 1645 emit_d8(cbuf, offset); | |
| 1646 } | |
| 1647 } | |
| 1648 | |
| 1649 uint BoxLockNode::size(PhaseRegAlloc *ra_) const | |
| 1650 { | |
| 1651 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1652 return (offset < 0x80) ? 5 : 8; // REX | |
| 1653 } | |
| 1654 | |
| 1655 //============================================================================= | |
| 1656 | |
| 1657 // emit call stub, compiled java to interpreter | |
| 1658 void emit_java_to_interp(CodeBuffer& cbuf) | |
| 1659 { | |
| 1660 // Stub is fixed up when the corresponding call is converted from | |
| 1661 // calling compiled code to calling interpreted code. | |
| 1662 // movq rbx, 0 | |
| 1663 // jmp -5 # to self | |
| 1664 | |
| 1748 | 1665 address mark = cbuf.insts_mark(); // get mark within main instrs section |
| 1666 | |
| 1667 // Note that the code buffer's insts_mark is always relative to insts. | |
| 0 | 1668 // That's why we must use the macroassembler to generate a stub. |
| 1669 MacroAssembler _masm(&cbuf); | |
| 1670 | |
| 1671 address base = | |
| 1672 __ start_a_stub(Compile::MAX_stubs_size); | |
| 1673 if (base == NULL) return; // CodeBuffer::expand failed | |
| 1674 // static stub relocation stores the instruction address of the call | |
| 1675 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM64); | |
| 1676 // static stub relocation also tags the methodOop in the code-stream. | |
| 1677 __ movoop(rbx, (jobject) NULL); // method is zapped till fixup time | |
| 304 | 1678 // This is recognized as unresolved by relocs/nativeinst/ic code |
| 0 | 1679 __ jump(RuntimeAddress(__ pc())); |
| 1680 | |
| 1748 | 1681 // Update current stubs pointer and restore insts_end. |
| 0 | 1682 __ end_a_stub(); |
| 1683 } | |
| 1684 | |
| 1685 // size of call stub, compiled java to interpretor | |
| 1686 uint size_java_to_interp() | |
| 1687 { | |
| 1688 return 15; // movq (1+1+8); jmp (1+4) | |
| 1689 } | |
| 1690 | |
| 1691 // relocation entries for call stub, compiled java to interpretor | |
| 1692 uint reloc_java_to_interp() | |
| 1693 { | |
| 1694 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call | |
| 1695 } | |
| 1696 | |
| 1697 //============================================================================= | |
| 1698 #ifndef PRODUCT | |
| 1699 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const | |
| 1700 { | |
|
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1701 if (UseCompressedOops) { |
|
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1702 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass"); |
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1703 if (Universe::narrow_oop_shift() != 0) { |
|
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1704 st->print_cr("\tdecode_heap_oop_not_null rscratch1, rscratch1"); |
|
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1705 } |
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1706 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check"); |
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1707 } else { |
|
1571
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1708 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t" |
|
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1709 "# Inline cache check"); |
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1710 } |
| 0 | 1711 st->print_cr("\tjne SharedRuntime::_ic_miss_stub"); |
|
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1712 st->print_cr("\tnop\t# nops to align entry point"); |
| 0 | 1713 } |
| 1714 #endif | |
| 1715 | |
| 1716 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const | |
| 1717 { | |
| 1718 MacroAssembler masm(&cbuf); | |
| 1748 | 1719 uint insts_size = cbuf.insts_size(); |
|
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|
1720 if (UseCompressedOops) { |
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1721 masm.load_klass(rscratch1, j_rarg0); |
| 304 | 1722 masm.cmpptr(rax, rscratch1); |
|
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1723 } else { |
| 304 | 1724 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes())); |
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1725 } |
| 0 | 1726 |
| 1727 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub())); | |
| 1728 | |
| 1729 /* WARNING these NOPs are critical so that verified entry point is properly | |
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1730 4 bytes aligned for patching by NativeJump::patch_verified_entry() */ |
| 1748 | 1731 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3); |
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1732 if (OptoBreakpoint) { |
| 0 | 1733 // Leave space for int3 |
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1734 nops_cnt -= 1; |
| 0 | 1735 } |
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1736 nops_cnt &= 0x3; // Do not add nops if code is aligned. |
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1737 if (nops_cnt > 0) |
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1738 masm.nop(nops_cnt); |
| 0 | 1739 } |
| 1740 | |
| 1741 uint MachUEPNode::size(PhaseRegAlloc* ra_) const | |
| 1742 { | |
|
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1743 return MachNode::size(ra_); // too many variables; just compute it |
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1744 // the hard way |
| 0 | 1745 } |
| 1746 | |
| 1747 | |
| 1748 //============================================================================= | |
| 1749 uint size_exception_handler() | |
| 1750 { | |
| 1751 // NativeCall instruction size is the same as NativeJump. | |
| 1752 // Note that this value is also credited (in output.cpp) to | |
| 1753 // the size of the code section. | |
| 1754 return NativeJump::instruction_size; | |
| 1755 } | |
| 1756 | |
| 1757 // Emit exception handler code. | |
| 1758 int emit_exception_handler(CodeBuffer& cbuf) | |
| 1759 { | |
| 1760 | |
| 1748 | 1761 // Note that the code buffer's insts_mark is always relative to insts. |
| 0 | 1762 // That's why we must use the macroassembler to generate a handler. |
| 1763 MacroAssembler _masm(&cbuf); | |
| 1764 address base = | |
| 1765 __ start_a_stub(size_exception_handler()); | |
| 1766 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1767 int offset = __ offset(); | |
| 1748 | 1768 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point())); |
| 0 | 1769 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); |
| 1770 __ end_a_stub(); | |
| 1771 return offset; | |
| 1772 } | |
| 1773 | |
| 1774 uint size_deopt_handler() | |
| 1775 { | |
| 1776 // three 5 byte instructions | |
| 1777 return 15; | |
| 1778 } | |
| 1779 | |
| 1780 // Emit deopt handler code. | |
| 1781 int emit_deopt_handler(CodeBuffer& cbuf) | |
| 1782 { | |
| 1783 | |
| 1748 | 1784 // Note that the code buffer's insts_mark is always relative to insts. |
| 0 | 1785 // That's why we must use the macroassembler to generate a handler. |
| 1786 MacroAssembler _masm(&cbuf); | |
| 1787 address base = | |
| 1788 __ start_a_stub(size_deopt_handler()); | |
| 1789 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1790 int offset = __ offset(); | |
| 1791 address the_pc = (address) __ pc(); | |
| 1792 Label next; | |
| 1793 // push a "the_pc" on the stack without destroying any registers | |
| 1794 // as they all may be live. | |
| 1795 | |
| 1796 // push address of "next" | |
| 1797 __ call(next, relocInfo::none); // reloc none is fine since it is a disp32 | |
| 1798 __ bind(next); | |
| 1799 // adjust it so it matches "the_pc" | |
| 304 | 1800 __ subptr(Address(rsp, 0), __ offset() - offset); |
| 0 | 1801 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); |
| 1802 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); | |
| 1803 __ end_a_stub(); | |
| 1804 return offset; | |
| 1805 } | |
| 1806 | |
| 1807 | |
|
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1808 const bool Matcher::match_rule_supported(int opcode) { |
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1809 if (!has_match_rule(opcode)) |
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1810 return false; |
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1811 |
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1812 return true; // Per default match rules are supported. |
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1813 } |
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1814 |
| 0 | 1815 int Matcher::regnum_to_fpu_offset(int regnum) |
| 1816 { | |
| 1817 return regnum - 32; // The FP registers are in the second chunk | |
| 1818 } | |
| 1819 | |
| 1820 // This is UltraSparc specific, true just means we have fast l2f conversion | |
| 1821 const bool Matcher::convL2FSupported(void) { | |
| 1822 return true; | |
| 1823 } | |
| 1824 | |
| 1825 // Vector width in bytes | |
| 1826 const uint Matcher::vector_width_in_bytes(void) { | |
| 1827 return 8; | |
| 1828 } | |
| 1829 | |
| 1830 // Vector ideal reg | |
| 1831 const uint Matcher::vector_ideal_reg(void) { | |
| 1832 return Op_RegD; | |
| 1833 } | |
| 1834 | |
| 1835 // Is this branch offset short enough that a short branch can be used? | |
| 1836 // | |
| 1837 // NOTE: If the platform does not provide any short branch variants, then | |
| 1838 // this method should return false for offset 0. | |
| 3851 | 1839 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { |
| 1840 // The passed offset is relative to address of the branch. | |
| 1841 // On 86 a branch displacement is calculated relative to address | |
| 1842 // of a next instruction. | |
| 1843 offset -= br_size; | |
| 1844 | |
|
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1845 // the short version of jmpConUCF2 contains multiple branches, |
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1846 // making the reach slightly less |
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1847 if (rule == jmpConUCF2_rule) |
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1848 return (-126 <= offset && offset <= 125); |
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1849 return (-128 <= offset && offset <= 127); |
| 0 | 1850 } |
| 1851 | |
| 1852 const bool Matcher::isSimpleConstant64(jlong value) { | |
| 1853 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. | |
| 1854 //return value == (int) value; // Cf. storeImmL and immL32. | |
| 1855 | |
| 1856 // Probably always true, even if a temp register is required. | |
| 1857 return true; | |
| 1858 } | |
| 1859 | |
| 1860 // The ecx parameter to rep stosq for the ClearArray node is in words. | |
| 1861 const bool Matcher::init_array_count_is_in_bytes = false; | |
| 1862 | |
| 1863 // Threshold size for cleararray. | |
| 1864 const int Matcher::init_array_short_size = 8 * BytesPerLong; | |
| 1865 | |
| 4047 | 1866 // No additional cost for CMOVL. |
| 1867 const int Matcher::long_cmove_cost() { return 0; } | |
| 1868 | |
| 1869 // No CMOVF/CMOVD with SSE2 | |
| 1870 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; } | |
| 1871 | |
| 0 | 1872 // Should the Matcher clone shifts on addressing modes, expecting them |
| 1873 // to be subsumed into complex addressing expressions or compute them | |
| 1874 // into registers? True for Intel but false for most RISCs | |
| 1875 const bool Matcher::clone_shift_expressions = true; | |
| 1876 | |
|
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1877 // Do we need to mask the count passed to shift instructions or does |
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1878 // the cpu only look at the lower 5/6 bits anyway? |
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1879 const bool Matcher::need_masked_shift_count = false; |
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1880 |
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1881 bool Matcher::narrow_oop_use_complex_address() { |
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1882 assert(UseCompressedOops, "only for compressed oops code"); |
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1883 return (LogMinObjAlignmentInBytes <= 3); |
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1884 } |
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1885 |
| 0 | 1886 // Is it better to copy float constants, or load them directly from |
| 1887 // memory? Intel can load a float constant from a direct address, | |
| 1888 // requiring no extra registers. Most RISCs will have to materialize | |
| 1889 // an address into a register first, so they would do better to copy | |
| 1890 // the constant from stack. | |
| 1891 const bool Matcher::rematerialize_float_constants = true; // XXX | |
| 1892 | |
| 1893 // If CPU can load and store mis-aligned doubles directly then no | |
| 1894 // fixup is needed. Else we split the double into 2 integer pieces | |
| 1895 // and move it piece-by-piece. Only happens when passing doubles into | |
| 1896 // C code as the Java calling convention forces doubles to be aligned. | |
| 1897 const bool Matcher::misaligned_doubles_ok = true; | |
| 1898 | |
| 1899 // No-op on amd64 | |
| 1900 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {} | |
| 1901 | |
| 1902 // Advertise here if the CPU requires explicit rounding operations to | |
| 1903 // implement the UseStrictFP mode. | |
| 1904 const bool Matcher::strict_fp_requires_explicit_rounding = true; | |
| 1905 | |
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1906 // Are floats conerted to double when stored to stack during deoptimization? |
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1907 // On x64 it is stored without convertion so we can use normal access. |
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1908 bool Matcher::float_in_double() { return false; } |
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1909 |
| 0 | 1910 // Do ints take an entire long register or just half? |
| 1911 const bool Matcher::int_in_long = true; | |
| 1912 | |
| 1913 // Return whether or not this register is ever used as an argument. | |
| 1914 // This function is used on startup to build the trampoline stubs in | |
| 1915 // generateOptoStub. Registers not mentioned will be killed by the VM | |
| 1916 // call in the trampoline, and arguments in those registers not be | |
| 1917 // available to the callee. | |
| 1918 bool Matcher::can_be_java_arg(int reg) | |
| 1919 { | |
| 1920 return | |
| 1921 reg == RDI_num || reg == RDI_H_num || | |
| 1922 reg == RSI_num || reg == RSI_H_num || | |
| 1923 reg == RDX_num || reg == RDX_H_num || | |
| 1924 reg == RCX_num || reg == RCX_H_num || | |
| 1925 reg == R8_num || reg == R8_H_num || | |
| 1926 reg == R9_num || reg == R9_H_num || | |
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1927 reg == R12_num || reg == R12_H_num || |
| 0 | 1928 reg == XMM0_num || reg == XMM0_H_num || |
| 1929 reg == XMM1_num || reg == XMM1_H_num || | |
| 1930 reg == XMM2_num || reg == XMM2_H_num || | |
| 1931 reg == XMM3_num || reg == XMM3_H_num || | |
| 1932 reg == XMM4_num || reg == XMM4_H_num || | |
| 1933 reg == XMM5_num || reg == XMM5_H_num || | |
| 1934 reg == XMM6_num || reg == XMM6_H_num || | |
| 1935 reg == XMM7_num || reg == XMM7_H_num; | |
| 1936 } | |
| 1937 | |
| 1938 bool Matcher::is_spillable_arg(int reg) | |
| 1939 { | |
| 1940 return can_be_java_arg(reg); | |
| 1941 } | |
| 1942 | |
|
1914
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1943 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) { |
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1944 // In 64 bit mode a code which use multiply when |
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1945 // devisor is constant is faster than hardware |
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1946 // DIV instruction (it uses MulHiL). |
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1947 return false; |
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1948 } |
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1949 |
| 0 | 1950 // Register for DIVI projection of divmodI |
| 1951 RegMask Matcher::divI_proj_mask() { | |
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1952 return INT_RAX_REG_mask(); |
| 0 | 1953 } |
| 1954 | |
| 1955 // Register for MODI projection of divmodI | |
| 1956 RegMask Matcher::modI_proj_mask() { | |
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1957 return INT_RDX_REG_mask(); |
| 0 | 1958 } |
| 1959 | |
| 1960 // Register for DIVL projection of divmodL | |
| 1961 RegMask Matcher::divL_proj_mask() { | |
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1962 return LONG_RAX_REG_mask(); |
| 0 | 1963 } |
| 1964 | |
| 1965 // Register for MODL projection of divmodL | |
| 1966 RegMask Matcher::modL_proj_mask() { | |
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1967 return LONG_RDX_REG_mask(); |
| 0 | 1968 } |
| 1969 | |
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1970 const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
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1971 return PTR_RBP_REG_mask(); |
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1972 } |
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1973 |
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1974 static Address build_address(int b, int i, int s, int d) { |
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1975 Register index = as_Register(i); |
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1976 Address::ScaleFactor scale = (Address::ScaleFactor)s; |
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1977 if (index == rsp) { |
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1978 index = noreg; |
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1979 scale = Address::no_scale; |
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1980 } |
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1981 Address addr(as_Register(b), index, scale, d); |
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1982 return addr; |
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1983 } |
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1984 |
| 0 | 1985 %} |
| 1986 | |
| 1987 //----------ENCODING BLOCK----------------------------------------------------- | |
| 1988 // This block specifies the encoding classes used by the compiler to | |
| 1989 // output byte streams. Encoding classes are parameterized macros | |
| 1990 // used by Machine Instruction Nodes in order to generate the bit | |
| 1991 // encoding of the instruction. Operands specify their base encoding | |
| 1992 // interface with the interface keyword. There are currently | |
| 1993 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, & | |
| 1994 // COND_INTER. REG_INTER causes an operand to generate a function | |
| 1995 // which returns its register number when queried. CONST_INTER causes | |
| 1996 // an operand to generate a function which returns the value of the | |
| 1997 // constant when queried. MEMORY_INTER causes an operand to generate | |
| 1998 // four functions which return the Base Register, the Index Register, | |
| 1999 // the Scale Value, and the Offset Value of the operand when queried. | |
| 2000 // COND_INTER causes an operand to generate six functions which return | |
| 2001 // the encoding code (ie - encoding bits for the instruction) | |
| 2002 // associated with each basic boolean condition for a conditional | |
| 2003 // instruction. | |
| 2004 // | |
| 2005 // Instructions specify two basic values for encoding. Again, a | |
| 2006 // function is available to check if the constant displacement is an | |
| 2007 // oop. They use the ins_encode keyword to specify their encoding | |
| 2008 // classes (which must be a sequence of enc_class names, and their | |
| 2009 // parameters, specified in the encoding block), and they use the | |
| 2010 // opcode keyword to specify, in order, their primary, secondary, and | |
| 2011 // tertiary opcode. Only the opcode sections which a particular | |
| 2012 // instruction needs for encoding need to be specified. | |
| 2013 encode %{ | |
| 2014 // Build emit functions for each basic byte or larger field in the | |
| 2015 // intel encoding scheme (opcode, rm, sib, immediate), and call them | |
| 2016 // from C++ code in the enc_class source block. Emit functions will | |
| 2017 // live in the main source block for now. In future, we can | |
| 2018 // generalize this by adding a syntax that specifies the sizes of | |
| 2019 // fields in an order, so that the adlc can build the emit functions | |
| 2020 // automagically | |
| 2021 | |
| 2022 // Emit primary opcode | |
| 2023 enc_class OpcP | |
| 2024 %{ | |
| 2025 emit_opcode(cbuf, $primary); | |
| 2026 %} | |
| 2027 | |
| 2028 // Emit secondary opcode | |
| 2029 enc_class OpcS | |
| 2030 %{ | |
| 2031 emit_opcode(cbuf, $secondary); | |
| 2032 %} | |
| 2033 | |
| 2034 // Emit tertiary opcode | |
| 2035 enc_class OpcT | |
| 2036 %{ | |
| 2037 emit_opcode(cbuf, $tertiary); | |
| 2038 %} | |
| 2039 | |
| 2040 // Emit opcode directly | |
| 2041 enc_class Opcode(immI d8) | |
| 2042 %{ | |
| 2043 emit_opcode(cbuf, $d8$$constant); | |
| 2044 %} | |
| 2045 | |
| 2046 // Emit size prefix | |
| 2047 enc_class SizePrefix | |
| 2048 %{ | |
| 2049 emit_opcode(cbuf, 0x66); | |
| 2050 %} | |
| 2051 | |
| 2052 enc_class reg(rRegI reg) | |
| 2053 %{ | |
| 2054 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7); | |
| 2055 %} | |
| 2056 | |
| 2057 enc_class reg_reg(rRegI dst, rRegI src) | |
| 2058 %{ | |
| 2059 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7); | |
| 2060 %} | |
| 2061 | |
| 2062 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src) | |
| 2063 %{ | |
| 2064 emit_opcode(cbuf, $opcode$$constant); | |
| 2065 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7); | |
| 2066 %} | |
| 2067 | |
| 2068 enc_class cdql_enc(no_rax_rdx_RegI div) | |
| 2069 %{ | |
| 2070 // Full implementation of Java idiv and irem; checks for | |
| 2071 // special case as described in JVM spec., p.243 & p.271. | |
| 2072 // | |
| 2073 // normal case special case | |
| 2074 // | |
| 2075 // input : rax: dividend min_int | |
| 2076 // reg: divisor -1 | |
| 2077 // | |
| 2078 // output: rax: quotient (= rax idiv reg) min_int | |
| 2079 // rdx: remainder (= rax irem reg) 0 | |
| 2080 // | |
| 2081 // Code sequnce: | |
| 2082 // | |
| 2083 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax | |
| 2084 // 5: 75 07/08 jne e <normal> | |
| 2085 // 7: 33 d2 xor %edx,%edx | |
| 2086 // [div >= 8 -> offset + 1] | |
| 2087 // [REX_B] | |
| 2088 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div | |
| 2089 // c: 74 03/04 je 11 <done> | |
| 2090 // 000000000000000e <normal>: | |
| 2091 // e: 99 cltd | |
| 2092 // [div >= 8 -> offset + 1] | |
| 2093 // [REX_B] | |
| 2094 // f: f7 f9 idiv $div | |
| 2095 // 0000000000000011 <done>: | |
| 2096 | |
| 2097 // cmp $0x80000000,%eax | |
| 2098 emit_opcode(cbuf, 0x3d); | |
| 2099 emit_d8(cbuf, 0x00); | |
| 2100 emit_d8(cbuf, 0x00); | |
| 2101 emit_d8(cbuf, 0x00); | |
| 2102 emit_d8(cbuf, 0x80); | |
| 2103 | |
| 2104 // jne e <normal> | |
| 2105 emit_opcode(cbuf, 0x75); | |
| 2106 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08); | |
| 2107 | |
| 2108 // xor %edx,%edx | |
| 2109 emit_opcode(cbuf, 0x33); | |
| 2110 emit_d8(cbuf, 0xD2); | |
| 2111 | |
| 2112 // cmp $0xffffffffffffffff,%ecx | |
| 2113 if ($div$$reg >= 8) { | |
| 2114 emit_opcode(cbuf, Assembler::REX_B); | |
| 2115 } | |
| 2116 emit_opcode(cbuf, 0x83); | |
| 2117 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7); | |
| 2118 emit_d8(cbuf, 0xFF); | |
| 2119 | |
| 2120 // je 11 <done> | |
| 2121 emit_opcode(cbuf, 0x74); | |
| 2122 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04); | |
| 2123 | |
| 2124 // <normal> | |
| 2125 // cltd | |
| 2126 emit_opcode(cbuf, 0x99); | |
| 2127 | |
| 2128 // idivl (note: must be emitted by the user of this rule) | |
| 2129 // <done> | |
| 2130 %} | |
| 2131 | |
| 2132 enc_class cdqq_enc(no_rax_rdx_RegL div) | |
| 2133 %{ | |
| 2134 // Full implementation of Java ldiv and lrem; checks for | |
| 2135 // special case as described in JVM spec., p.243 & p.271. | |
| 2136 // | |
| 2137 // normal case special case | |
| 2138 // | |
| 2139 // input : rax: dividend min_long | |
| 2140 // reg: divisor -1 | |
| 2141 // | |
| 2142 // output: rax: quotient (= rax idiv reg) min_long | |
| 2143 // rdx: remainder (= rax irem reg) 0 | |
| 2144 // | |
| 2145 // Code sequnce: | |
| 2146 // | |
| 2147 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx | |
| 2148 // 7: 00 00 80 | |
| 2149 // a: 48 39 d0 cmp %rdx,%rax | |
| 2150 // d: 75 08 jne 17 <normal> | |
| 2151 // f: 33 d2 xor %edx,%edx | |
| 2152 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div | |
| 2153 // 15: 74 05 je 1c <done> | |
| 2154 // 0000000000000017 <normal>: | |
| 2155 // 17: 48 99 cqto | |
| 2156 // 19: 48 f7 f9 idiv $div | |
| 2157 // 000000000000001c <done>: | |
| 2158 | |
| 2159 // mov $0x8000000000000000,%rdx | |
| 2160 emit_opcode(cbuf, Assembler::REX_W); | |
| 2161 emit_opcode(cbuf, 0xBA); | |
| 2162 emit_d8(cbuf, 0x00); | |
| 2163 emit_d8(cbuf, 0x00); | |
| 2164 emit_d8(cbuf, 0x00); | |
| 2165 emit_d8(cbuf, 0x00); | |
| 2166 emit_d8(cbuf, 0x00); | |
| 2167 emit_d8(cbuf, 0x00); | |
| 2168 emit_d8(cbuf, 0x00); | |
| 2169 emit_d8(cbuf, 0x80); | |
| 2170 | |
| 2171 // cmp %rdx,%rax | |
| 2172 emit_opcode(cbuf, Assembler::REX_W); | |
| 2173 emit_opcode(cbuf, 0x39); | |
| 2174 emit_d8(cbuf, 0xD0); | |
| 2175 | |
| 2176 // jne 17 <normal> | |
| 2177 emit_opcode(cbuf, 0x75); | |
| 2178 emit_d8(cbuf, 0x08); | |
| 2179 | |
| 2180 // xor %edx,%edx | |
| 2181 emit_opcode(cbuf, 0x33); | |
| 2182 emit_d8(cbuf, 0xD2); | |
| 2183 | |
| 2184 // cmp $0xffffffffffffffff,$div | |
| 2185 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB); | |
| 2186 emit_opcode(cbuf, 0x83); | |
| 2187 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7); | |
| 2188 emit_d8(cbuf, 0xFF); | |
| 2189 | |
| 2190 // je 1e <done> | |
| 2191 emit_opcode(cbuf, 0x74); | |
| 2192 emit_d8(cbuf, 0x05); | |
| 2193 | |
| 2194 // <normal> | |
| 2195 // cqto | |
| 2196 emit_opcode(cbuf, Assembler::REX_W); | |
| 2197 emit_opcode(cbuf, 0x99); | |
| 2198 | |
| 2199 // idivq (note: must be emitted by the user of this rule) | |
| 2200 // <done> | |
| 2201 %} | |
| 2202 | |
| 2203 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension | |
| 2204 enc_class OpcSE(immI imm) | |
| 2205 %{ | |
| 2206 // Emit primary opcode and set sign-extend bit | |
| 2207 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 2208 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
| 2209 emit_opcode(cbuf, $primary | 0x02); | |
| 2210 } else { | |
| 2211 // 32-bit immediate | |
| 2212 emit_opcode(cbuf, $primary); | |
| 2213 } | |
| 2214 %} | |
| 2215 | |
| 2216 enc_class OpcSErm(rRegI dst, immI imm) | |
| 2217 %{ | |
| 2218 // OpcSEr/m | |
| 2219 int dstenc = $dst$$reg; | |
| 2220 if (dstenc >= 8) { | |
| 2221 emit_opcode(cbuf, Assembler::REX_B); | |
| 2222 dstenc -= 8; | |
| 2223 } | |
| 2224 // Emit primary opcode and set sign-extend bit | |
| 2225 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 2226 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
| 2227 emit_opcode(cbuf, $primary | 0x02); | |
| 2228 } else { | |
| 2229 // 32-bit immediate | |
| 2230 emit_opcode(cbuf, $primary); | |
| 2231 } | |
| 2232 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 2233 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
| 2234 %} | |
| 2235 | |
| 2236 enc_class OpcSErm_wide(rRegL dst, immI imm) | |
| 2237 %{ | |
| 2238 // OpcSEr/m | |
| 2239 int dstenc = $dst$$reg; | |
| 2240 if (dstenc < 8) { | |
| 2241 emit_opcode(cbuf, Assembler::REX_W); | |
| 2242 } else { | |
| 2243 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2244 dstenc -= 8; | |
| 2245 } | |
| 2246 // Emit primary opcode and set sign-extend bit | |
| 2247 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 2248 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
| 2249 emit_opcode(cbuf, $primary | 0x02); | |
| 2250 } else { | |
| 2251 // 32-bit immediate | |
| 2252 emit_opcode(cbuf, $primary); | |
| 2253 } | |
| 2254 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 2255 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
| 2256 %} | |
| 2257 | |
| 2258 enc_class Con8or32(immI imm) | |
| 2259 %{ | |
| 2260 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 2261 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
| 2262 $$$emit8$imm$$constant; | |
| 2263 } else { | |
| 2264 // 32-bit immediate | |
| 2265 $$$emit32$imm$$constant; | |
| 2266 } | |
| 2267 %} | |
| 2268 | |
| 2269 enc_class opc2_reg(rRegI dst) | |
| 2270 %{ | |
| 2271 // BSWAP | |
| 2272 emit_cc(cbuf, $secondary, $dst$$reg); | |
| 2273 %} | |
| 2274 | |
| 2275 enc_class opc3_reg(rRegI dst) | |
| 2276 %{ | |
| 2277 // BSWAP | |
| 2278 emit_cc(cbuf, $tertiary, $dst$$reg); | |
| 2279 %} | |
| 2280 | |
| 2281 enc_class reg_opc(rRegI div) | |
| 2282 %{ | |
| 2283 // INC, DEC, IDIV, IMOD, JMP indirect, ... | |
| 2284 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7); | |
| 2285 %} | |
| 2286 | |
| 2287 enc_class enc_cmov(cmpOp cop) | |
| 2288 %{ | |
| 2289 // CMOV | |
| 2290 $$$emit8$primary; | |
| 2291 emit_cc(cbuf, $secondary, $cop$$cmpcode); | |
| 2292 %} | |
| 2293 | |
| 2294 enc_class enc_PartialSubtypeCheck() | |
| 2295 %{ | |
| 2296 Register Rrdi = as_Register(RDI_enc); // result register | |
| 2297 Register Rrax = as_Register(RAX_enc); // super class | |
| 2298 Register Rrcx = as_Register(RCX_enc); // killed | |
| 2299 Register Rrsi = as_Register(RSI_enc); // sub class | |
|
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2300 Label miss; |
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2301 const bool set_cond_codes = true; |
| 0 | 2302 |
| 2303 MacroAssembler _masm(&cbuf); | |
|
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2304 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi, |
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2305 NULL, &miss, |
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2306 /*set_cond_codes:*/ true); |
| 0 | 2307 if ($primary) { |
| 304 | 2308 __ xorptr(Rrdi, Rrdi); |
| 0 | 2309 } |
| 2310 __ bind(miss); | |
| 2311 %} | |
| 2312 | |
| 2313 enc_class Java_To_Interpreter(method meth) | |
| 2314 %{ | |
| 2315 // CALL Java_To_Interpreter | |
| 2316 // This is the instruction starting address for relocation info. | |
| 1748 | 2317 cbuf.set_insts_mark(); |
| 0 | 2318 $$$emit8$primary; |
| 2319 // CALL directly to the runtime | |
| 2320 emit_d32_reloc(cbuf, | |
| 1748 | 2321 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4), |
| 0 | 2322 runtime_call_Relocation::spec(), |
| 2323 RELOC_DISP32); | |
| 2324 %} | |
| 2325 | |
|
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2326 enc_class preserve_SP %{ |
| 1748 | 2327 debug_only(int off0 = cbuf.insts_size()); |
|
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2328 MacroAssembler _masm(&cbuf); |
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2329 // RBP is preserved across all calls, even compiled calls. |
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2330 // Use it to preserve RSP in places where the callee might change the SP. |
| 1567 | 2331 __ movptr(rbp_mh_SP_save, rsp); |
| 1748 | 2332 debug_only(int off1 = cbuf.insts_size()); |
|
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2333 assert(off1 - off0 == preserve_SP_size(), "correct size prediction"); |
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2334 %} |
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2335 |
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2336 enc_class restore_SP %{ |
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2337 MacroAssembler _masm(&cbuf); |
| 1567 | 2338 __ movptr(rsp, rbp_mh_SP_save); |
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2339 %} |
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2340 |
| 0 | 2341 enc_class Java_Static_Call(method meth) |
| 2342 %{ | |
| 2343 // JAVA STATIC CALL | |
| 2344 // CALL to fixup routine. Fixup routine uses ScopeDesc info to | |
| 2345 // determine who we intended to call. | |
| 1748 | 2346 cbuf.set_insts_mark(); |
| 0 | 2347 $$$emit8$primary; |
| 2348 | |
| 2349 if (!_method) { | |
| 2350 emit_d32_reloc(cbuf, | |
| 1748 | 2351 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4), |
| 0 | 2352 runtime_call_Relocation::spec(), |
| 2353 RELOC_DISP32); | |
| 2354 } else if (_optimized_virtual) { | |
| 2355 emit_d32_reloc(cbuf, | |
| 1748 | 2356 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4), |
| 0 | 2357 opt_virtual_call_Relocation::spec(), |
| 2358 RELOC_DISP32); | |
| 2359 } else { | |
| 2360 emit_d32_reloc(cbuf, | |
| 1748 | 2361 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4), |
| 0 | 2362 static_call_Relocation::spec(), |
| 2363 RELOC_DISP32); | |
| 2364 } | |
| 2365 if (_method) { | |
| 2366 // Emit stub for static call | |
| 2367 emit_java_to_interp(cbuf); | |
| 2368 } | |
| 2369 %} | |
| 2370 | |
| 2371 enc_class Java_Dynamic_Call(method meth) | |
| 2372 %{ | |
| 2373 // JAVA DYNAMIC CALL | |
| 2374 // !!!!! | |
| 2375 // Generate "movq rax, -1", placeholder instruction to load oop-info | |
| 2376 // emit_call_dynamic_prologue( cbuf ); | |
| 1748 | 2377 cbuf.set_insts_mark(); |
| 0 | 2378 |
| 2379 // movq rax, -1 | |
| 2380 emit_opcode(cbuf, Assembler::REX_W); | |
| 2381 emit_opcode(cbuf, 0xB8 | RAX_enc); | |
| 2382 emit_d64_reloc(cbuf, | |
| 2383 (int64_t) Universe::non_oop_word(), | |
| 2384 oop_Relocation::spec_for_immediate(), RELOC_IMM64); | |
| 1748 | 2385 address virtual_call_oop_addr = cbuf.insts_mark(); |
| 0 | 2386 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine |
| 2387 // who we intended to call. | |
| 1748 | 2388 cbuf.set_insts_mark(); |
| 0 | 2389 $$$emit8$primary; |
| 2390 emit_d32_reloc(cbuf, | |
| 1748 | 2391 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4), |
| 0 | 2392 virtual_call_Relocation::spec(virtual_call_oop_addr), |
| 2393 RELOC_DISP32); | |
| 2394 %} | |
| 2395 | |
| 2396 enc_class Java_Compiled_Call(method meth) | |
| 2397 %{ | |
| 2398 // JAVA COMPILED CALL | |
| 2399 int disp = in_bytes(methodOopDesc:: from_compiled_offset()); | |
| 2400 | |
| 2401 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!! | |
| 2402 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small"); | |
| 2403 | |
| 2404 // callq *disp(%rax) | |
| 1748 | 2405 cbuf.set_insts_mark(); |
| 0 | 2406 $$$emit8$primary; |
| 2407 if (disp < 0x80) { | |
| 2408 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte | |
| 2409 emit_d8(cbuf, disp); // Displacement | |
| 2410 } else { | |
| 2411 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte | |
| 2412 emit_d32(cbuf, disp); // Displacement | |
| 2413 } | |
| 2414 %} | |
| 2415 | |
| 2416 enc_class reg_opc_imm(rRegI dst, immI8 shift) | |
| 2417 %{ | |
| 2418 // SAL, SAR, SHR | |
| 2419 int dstenc = $dst$$reg; | |
| 2420 if (dstenc >= 8) { | |
| 2421 emit_opcode(cbuf, Assembler::REX_B); | |
| 2422 dstenc -= 8; | |
| 2423 } | |
| 2424 $$$emit8$primary; | |
| 2425 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
| 2426 $$$emit8$shift$$constant; | |
| 2427 %} | |
| 2428 | |
| 2429 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift) | |
| 2430 %{ | |
| 2431 // SAL, SAR, SHR | |
| 2432 int dstenc = $dst$$reg; | |
| 2433 if (dstenc < 8) { | |
| 2434 emit_opcode(cbuf, Assembler::REX_W); | |
| 2435 } else { | |
| 2436 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2437 dstenc -= 8; | |
| 2438 } | |
| 2439 $$$emit8$primary; | |
| 2440 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
| 2441 $$$emit8$shift$$constant; | |
| 2442 %} | |
| 2443 | |
| 2444 enc_class load_immI(rRegI dst, immI src) | |
| 2445 %{ | |
| 2446 int dstenc = $dst$$reg; | |
| 2447 if (dstenc >= 8) { | |
| 2448 emit_opcode(cbuf, Assembler::REX_B); | |
| 2449 dstenc -= 8; | |
| 2450 } | |
| 2451 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2452 $$$emit32$src$$constant; | |
| 2453 %} | |
| 2454 | |
| 2455 enc_class load_immL(rRegL dst, immL src) | |
| 2456 %{ | |
| 2457 int dstenc = $dst$$reg; | |
| 2458 if (dstenc < 8) { | |
| 2459 emit_opcode(cbuf, Assembler::REX_W); | |
| 2460 } else { | |
| 2461 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2462 dstenc -= 8; | |
| 2463 } | |
| 2464 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2465 emit_d64(cbuf, $src$$constant); | |
| 2466 %} | |
| 2467 | |
| 2468 enc_class load_immUL32(rRegL dst, immUL32 src) | |
| 2469 %{ | |
| 2470 // same as load_immI, but this time we care about zeroes in the high word | |
| 2471 int dstenc = $dst$$reg; | |
| 2472 if (dstenc >= 8) { | |
| 2473 emit_opcode(cbuf, Assembler::REX_B); | |
| 2474 dstenc -= 8; | |
| 2475 } | |
| 2476 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2477 $$$emit32$src$$constant; | |
| 2478 %} | |
| 2479 | |
| 2480 enc_class load_immL32(rRegL dst, immL32 src) | |
| 2481 %{ | |
| 2482 int dstenc = $dst$$reg; | |
| 2483 if (dstenc < 8) { | |
| 2484 emit_opcode(cbuf, Assembler::REX_W); | |
| 2485 } else { | |
| 2486 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2487 dstenc -= 8; | |
| 2488 } | |
| 2489 emit_opcode(cbuf, 0xC7); | |
| 2490 emit_rm(cbuf, 0x03, 0x00, dstenc); | |
| 2491 $$$emit32$src$$constant; | |
| 2492 %} | |
| 2493 | |
| 2494 enc_class load_immP31(rRegP dst, immP32 src) | |
| 2495 %{ | |
| 2496 // same as load_immI, but this time we care about zeroes in the high word | |
| 2497 int dstenc = $dst$$reg; | |
| 2498 if (dstenc >= 8) { | |
| 2499 emit_opcode(cbuf, Assembler::REX_B); | |
| 2500 dstenc -= 8; | |
| 2501 } | |
| 2502 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2503 $$$emit32$src$$constant; | |
| 2504 %} | |
| 2505 | |
| 2506 enc_class load_immP(rRegP dst, immP src) | |
| 2507 %{ | |
| 2508 int dstenc = $dst$$reg; | |
| 2509 if (dstenc < 8) { | |
| 2510 emit_opcode(cbuf, Assembler::REX_W); | |
| 2511 } else { | |
| 2512 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2513 dstenc -= 8; | |
| 2514 } | |
| 2515 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2516 // This next line should be generated from ADLC | |
| 2517 if ($src->constant_is_oop()) { | |
| 2518 emit_d64_reloc(cbuf, $src$$constant, relocInfo::oop_type, RELOC_IMM64); | |
| 2519 } else { | |
| 2520 emit_d64(cbuf, $src$$constant); | |
| 2521 } | |
| 2522 %} | |
| 2523 | |
| 2524 enc_class Con32(immI src) | |
| 2525 %{ | |
| 2526 // Output immediate | |
| 2527 $$$emit32$src$$constant; | |
| 2528 %} | |
| 2529 | |
| 2530 enc_class Con64(immL src) | |
| 2531 %{ | |
| 2532 // Output immediate | |
| 2533 emit_d64($src$$constant); | |
| 2534 %} | |
| 2535 | |
| 2536 enc_class Con32F_as_bits(immF src) | |
| 2537 %{ | |
| 2538 // Output Float immediate bits | |
| 2539 jfloat jf = $src$$constant; | |
| 2540 jint jf_as_bits = jint_cast(jf); | |
| 2541 emit_d32(cbuf, jf_as_bits); | |
| 2542 %} | |
| 2543 | |
| 2544 enc_class Con16(immI src) | |
| 2545 %{ | |
| 2546 // Output immediate | |
| 2547 $$$emit16$src$$constant; | |
| 2548 %} | |
| 2549 | |
| 2550 // How is this different from Con32??? XXX | |
| 2551 enc_class Con_d32(immI src) | |
| 2552 %{ | |
| 2553 emit_d32(cbuf,$src$$constant); | |
| 2554 %} | |
| 2555 | |
| 2556 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI) | |
| 2557 // Output immediate memory reference | |
| 2558 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 ); | |
| 2559 emit_d32(cbuf, 0x00); | |
| 2560 %} | |
| 2561 | |
| 2562 enc_class lock_prefix() | |
| 2563 %{ | |
| 2564 if (os::is_MP()) { | |
| 2565 emit_opcode(cbuf, 0xF0); // lock | |
| 2566 } | |
| 2567 %} | |
| 2568 | |
| 2569 enc_class REX_mem(memory mem) | |
| 2570 %{ | |
| 2571 if ($mem$$base >= 8) { | |
| 2572 if ($mem$$index < 8) { | |
| 2573 emit_opcode(cbuf, Assembler::REX_B); | |
| 2574 } else { | |
| 2575 emit_opcode(cbuf, Assembler::REX_XB); | |
| 2576 } | |
| 2577 } else { | |
| 2578 if ($mem$$index >= 8) { | |
| 2579 emit_opcode(cbuf, Assembler::REX_X); | |
| 2580 } | |
| 2581 } | |
| 2582 %} | |
| 2583 | |
| 2584 enc_class REX_mem_wide(memory mem) | |
| 2585 %{ | |
| 2586 if ($mem$$base >= 8) { | |
| 2587 if ($mem$$index < 8) { | |
| 2588 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2589 } else { | |
| 2590 emit_opcode(cbuf, Assembler::REX_WXB); | |
| 2591 } | |
| 2592 } else { | |
| 2593 if ($mem$$index < 8) { | |
| 2594 emit_opcode(cbuf, Assembler::REX_W); | |
| 2595 } else { | |
| 2596 emit_opcode(cbuf, Assembler::REX_WX); | |
| 2597 } | |
| 2598 } | |
| 2599 %} | |
| 2600 | |
| 2601 // for byte regs | |
| 2602 enc_class REX_breg(rRegI reg) | |
| 2603 %{ | |
| 2604 if ($reg$$reg >= 4) { | |
| 2605 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B); | |
| 2606 } | |
| 2607 %} | |
| 2608 | |
| 2609 // for byte regs | |
| 2610 enc_class REX_reg_breg(rRegI dst, rRegI src) | |
| 2611 %{ | |
| 2612 if ($dst$$reg < 8) { | |
| 2613 if ($src$$reg >= 4) { | |
| 2614 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B); | |
| 2615 } | |
| 2616 } else { | |
| 2617 if ($src$$reg < 8) { | |
| 2618 emit_opcode(cbuf, Assembler::REX_R); | |
| 2619 } else { | |
| 2620 emit_opcode(cbuf, Assembler::REX_RB); | |
| 2621 } | |
| 2622 } | |
| 2623 %} | |
| 2624 | |
| 2625 // for byte regs | |
| 2626 enc_class REX_breg_mem(rRegI reg, memory mem) | |
| 2627 %{ | |
| 2628 if ($reg$$reg < 8) { | |
| 2629 if ($mem$$base < 8) { | |
| 2630 if ($mem$$index >= 8) { | |
| 2631 emit_opcode(cbuf, Assembler::REX_X); | |
| 2632 } else if ($reg$$reg >= 4) { | |
| 2633 emit_opcode(cbuf, Assembler::REX); | |
| 2634 } | |
| 2635 } else { | |
| 2636 if ($mem$$index < 8) { | |
| 2637 emit_opcode(cbuf, Assembler::REX_B); | |
| 2638 } else { | |
| 2639 emit_opcode(cbuf, Assembler::REX_XB); | |
| 2640 } | |
| 2641 } | |
| 2642 } else { | |
| 2643 if ($mem$$base < 8) { | |
| 2644 if ($mem$$index < 8) { | |
| 2645 emit_opcode(cbuf, Assembler::REX_R); | |
| 2646 } else { | |
| 2647 emit_opcode(cbuf, Assembler::REX_RX); | |
| 2648 } | |
| 2649 } else { | |
| 2650 if ($mem$$index < 8) { | |
| 2651 emit_opcode(cbuf, Assembler::REX_RB); | |
| 2652 } else { | |
| 2653 emit_opcode(cbuf, Assembler::REX_RXB); | |
| 2654 } | |
| 2655 } | |
| 2656 } | |
| 2657 %} | |
| 2658 | |
| 2659 enc_class REX_reg(rRegI reg) | |
| 2660 %{ | |
| 2661 if ($reg$$reg >= 8) { | |
| 2662 emit_opcode(cbuf, Assembler::REX_B); | |
| 2663 } | |
| 2664 %} | |
| 2665 | |
| 2666 enc_class REX_reg_wide(rRegI reg) | |
| 2667 %{ | |
| 2668 if ($reg$$reg < 8) { | |
| 2669 emit_opcode(cbuf, Assembler::REX_W); | |
| 2670 } else { | |
| 2671 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2672 } | |
| 2673 %} | |
| 2674 | |
| 2675 enc_class REX_reg_reg(rRegI dst, rRegI src) | |
| 2676 %{ | |
| 2677 if ($dst$$reg < 8) { | |
| 2678 if ($src$$reg >= 8) { | |
| 2679 emit_opcode(cbuf, Assembler::REX_B); | |
| 2680 } | |
| 2681 } else { | |
| 2682 if ($src$$reg < 8) { | |
| 2683 emit_opcode(cbuf, Assembler::REX_R); | |
| 2684 } else { | |
| 2685 emit_opcode(cbuf, Assembler::REX_RB); | |
| 2686 } | |
| 2687 } | |
| 2688 %} | |
| 2689 | |
| 2690 enc_class REX_reg_reg_wide(rRegI dst, rRegI src) | |
| 2691 %{ | |
| 2692 if ($dst$$reg < 8) { | |
| 2693 if ($src$$reg < 8) { | |
| 2694 emit_opcode(cbuf, Assembler::REX_W); | |
| 2695 } else { | |
| 2696 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2697 } | |
| 2698 } else { | |
| 2699 if ($src$$reg < 8) { | |
| 2700 emit_opcode(cbuf, Assembler::REX_WR); | |
| 2701 } else { | |
| 2702 emit_opcode(cbuf, Assembler::REX_WRB); | |
| 2703 } | |
| 2704 } | |
| 2705 %} | |
| 2706 | |
| 2707 enc_class REX_reg_mem(rRegI reg, memory mem) | |
| 2708 %{ | |
| 2709 if ($reg$$reg < 8) { | |
| 2710 if ($mem$$base < 8) { | |
| 2711 if ($mem$$index >= 8) { | |
| 2712 emit_opcode(cbuf, Assembler::REX_X); | |
| 2713 } | |
| 2714 } else { | |
| 2715 if ($mem$$index < 8) { | |
| 2716 emit_opcode(cbuf, Assembler::REX_B); | |
| 2717 } else { | |
| 2718 emit_opcode(cbuf, Assembler::REX_XB); | |
| 2719 } | |
| 2720 } | |
| 2721 } else { | |
| 2722 if ($mem$$base < 8) { | |
| 2723 if ($mem$$index < 8) { | |
| 2724 emit_opcode(cbuf, Assembler::REX_R); | |
| 2725 } else { | |
| 2726 emit_opcode(cbuf, Assembler::REX_RX); | |
| 2727 } | |
| 2728 } else { | |
| 2729 if ($mem$$index < 8) { | |
| 2730 emit_opcode(cbuf, Assembler::REX_RB); | |
| 2731 } else { | |
| 2732 emit_opcode(cbuf, Assembler::REX_RXB); | |
| 2733 } | |
| 2734 } | |
| 2735 } | |
| 2736 %} | |
| 2737 | |
| 2738 enc_class REX_reg_mem_wide(rRegL reg, memory mem) | |
| 2739 %{ | |
| 2740 if ($reg$$reg < 8) { | |
| 2741 if ($mem$$base < 8) { | |
| 2742 if ($mem$$index < 8) { | |
| 2743 emit_opcode(cbuf, Assembler::REX_W); | |
| 2744 } else { | |
| 2745 emit_opcode(cbuf, Assembler::REX_WX); | |
| 2746 } | |
| 2747 } else { | |
| 2748 if ($mem$$index < 8) { | |
| 2749 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2750 } else { | |
| 2751 emit_opcode(cbuf, Assembler::REX_WXB); | |
| 2752 } | |
| 2753 } | |
| 2754 } else { | |
| 2755 if ($mem$$base < 8) { | |
| 2756 if ($mem$$index < 8) { | |
| 2757 emit_opcode(cbuf, Assembler::REX_WR); | |
| 2758 } else { | |
| 2759 emit_opcode(cbuf, Assembler::REX_WRX); | |
| 2760 } | |
| 2761 } else { | |
| 2762 if ($mem$$index < 8) { | |
| 2763 emit_opcode(cbuf, Assembler::REX_WRB); | |
| 2764 } else { | |
| 2765 emit_opcode(cbuf, Assembler::REX_WRXB); | |
| 2766 } | |
| 2767 } | |
| 2768 } | |
| 2769 %} | |
| 2770 | |
| 2771 enc_class reg_mem(rRegI ereg, memory mem) | |
| 2772 %{ | |
| 2773 // High registers handle in encode_RegMem | |
| 2774 int reg = $ereg$$reg; | |
| 2775 int base = $mem$$base; | |
| 2776 int index = $mem$$index; | |
| 2777 int scale = $mem$$scale; | |
| 2778 int disp = $mem$$disp; | |
| 2779 bool disp_is_oop = $mem->disp_is_oop(); | |
| 2780 | |
| 2781 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_is_oop); | |
| 2782 %} | |
| 2783 | |
| 2784 enc_class RM_opc_mem(immI rm_opcode, memory mem) | |
| 2785 %{ | |
| 2786 int rm_byte_opcode = $rm_opcode$$constant; | |
| 2787 | |
| 2788 // High registers handle in encode_RegMem | |
| 2789 int base = $mem$$base; | |
| 2790 int index = $mem$$index; | |
| 2791 int scale = $mem$$scale; | |
| 2792 int displace = $mem$$disp; | |
| 2793 | |
| 2794 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when | |
| 2795 // working with static | |
| 2796 // globals | |
| 2797 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, | |
| 2798 disp_is_oop); | |
| 2799 %} | |
| 2800 | |
| 2801 enc_class reg_lea(rRegI dst, rRegI src0, immI src1) | |
| 2802 %{ | |
| 2803 int reg_encoding = $dst$$reg; | |
| 2804 int base = $src0$$reg; // 0xFFFFFFFF indicates no base | |
| 2805 int index = 0x04; // 0x04 indicates no index | |
| 2806 int scale = 0x00; // 0x00 indicates no scale | |
| 2807 int displace = $src1$$constant; // 0x00 indicates no displacement | |
| 2808 bool disp_is_oop = false; | |
| 2809 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, | |
| 2810 disp_is_oop); | |
| 2811 %} | |
| 2812 | |
| 2813 enc_class neg_reg(rRegI dst) | |
| 2814 %{ | |
| 2815 int dstenc = $dst$$reg; | |
| 2816 if (dstenc >= 8) { | |
| 2817 emit_opcode(cbuf, Assembler::REX_B); | |
| 2818 dstenc -= 8; | |
| 2819 } | |
| 2820 // NEG $dst | |
| 2821 emit_opcode(cbuf, 0xF7); | |
| 2822 emit_rm(cbuf, 0x3, 0x03, dstenc); | |
| 2823 %} | |
| 2824 | |
| 2825 enc_class neg_reg_wide(rRegI dst) | |
| 2826 %{ | |
| 2827 int dstenc = $dst$$reg; | |
| 2828 if (dstenc < 8) { | |
| 2829 emit_opcode(cbuf, Assembler::REX_W); | |
| 2830 } else { | |
| 2831 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2832 dstenc -= 8; | |
| 2833 } | |
| 2834 // NEG $dst | |
| 2835 emit_opcode(cbuf, 0xF7); | |
| 2836 emit_rm(cbuf, 0x3, 0x03, dstenc); | |
| 2837 %} | |
| 2838 | |
| 2839 enc_class setLT_reg(rRegI dst) | |
| 2840 %{ | |
| 2841 int dstenc = $dst$$reg; | |
| 2842 if (dstenc >= 8) { | |
| 2843 emit_opcode(cbuf, Assembler::REX_B); | |
| 2844 dstenc -= 8; | |
| 2845 } else if (dstenc >= 4) { | |
| 2846 emit_opcode(cbuf, Assembler::REX); | |
| 2847 } | |
| 2848 // SETLT $dst | |
| 2849 emit_opcode(cbuf, 0x0F); | |
| 2850 emit_opcode(cbuf, 0x9C); | |
| 2851 emit_rm(cbuf, 0x3, 0x0, dstenc); | |
| 2852 %} | |
| 2853 | |
| 2854 enc_class setNZ_reg(rRegI dst) | |
| 2855 %{ | |
| 2856 int dstenc = $dst$$reg; | |
| 2857 if (dstenc >= 8) { | |
| 2858 emit_opcode(cbuf, Assembler::REX_B); | |
| 2859 dstenc -= 8; | |
| 2860 } else if (dstenc >= 4) { | |
| 2861 emit_opcode(cbuf, Assembler::REX); | |
| 2862 } | |
| 2863 // SETNZ $dst | |
| 2864 emit_opcode(cbuf, 0x0F); | |
| 2865 emit_opcode(cbuf, 0x95); | |
| 2866 emit_rm(cbuf, 0x3, 0x0, dstenc); | |
| 2867 %} | |
| 2868 | |
| 2869 | |
| 2870 // Compare the lonogs and set -1, 0, or 1 into dst | |
| 2871 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst) | |
| 2872 %{ | |
| 2873 int src1enc = $src1$$reg; | |
| 2874 int src2enc = $src2$$reg; | |
| 2875 int dstenc = $dst$$reg; | |
| 2876 | |
| 2877 // cmpq $src1, $src2 | |
| 2878 if (src1enc < 8) { | |
| 2879 if (src2enc < 8) { | |
| 2880 emit_opcode(cbuf, Assembler::REX_W); | |
| 2881 } else { | |
| 2882 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2883 } | |
| 2884 } else { | |
| 2885 if (src2enc < 8) { | |
| 2886 emit_opcode(cbuf, Assembler::REX_WR); | |
| 2887 } else { | |
| 2888 emit_opcode(cbuf, Assembler::REX_WRB); | |
| 2889 } | |
| 2890 } | |
| 2891 emit_opcode(cbuf, 0x3B); | |
| 2892 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7); | |
| 2893 | |
| 2894 // movl $dst, -1 | |
| 2895 if (dstenc >= 8) { | |
| 2896 emit_opcode(cbuf, Assembler::REX_B); | |
| 2897 } | |
| 2898 emit_opcode(cbuf, 0xB8 | (dstenc & 7)); | |
| 2899 emit_d32(cbuf, -1); | |
| 2900 | |
| 2901 // jl,s done | |
| 2902 emit_opcode(cbuf, 0x7C); | |
| 2903 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08); | |
| 2904 | |
| 2905 // setne $dst | |
| 2906 if (dstenc >= 4) { | |
| 2907 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B); | |
| 2908 } | |
| 2909 emit_opcode(cbuf, 0x0F); | |
| 2910 emit_opcode(cbuf, 0x95); | |
| 2911 emit_opcode(cbuf, 0xC0 | (dstenc & 7)); | |
| 2912 | |
| 2913 // movzbl $dst, $dst | |
| 2914 if (dstenc >= 4) { | |
| 2915 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB); | |
| 2916 } | |
| 2917 emit_opcode(cbuf, 0x0F); | |
| 2918 emit_opcode(cbuf, 0xB6); | |
| 2919 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7); | |
| 2920 %} | |
| 2921 | |
| 2922 enc_class Push_ResultXD(regD dst) %{ | |
| 4759 | 2923 MacroAssembler _masm(&cbuf); |
| 2924 __ fstp_d(Address(rsp, 0)); | |
| 2925 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); | |
| 2926 __ addptr(rsp, 8); | |
| 0 | 2927 %} |
| 2928 | |
| 2929 enc_class Push_SrcXD(regD src) %{ | |
| 2930 MacroAssembler _masm(&cbuf); | |
| 4759 | 2931 __ subptr(rsp, 8); |
| 2932 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 2933 __ fld_d(Address(rsp, 0)); | |
| 2934 %} | |
| 2935 | |
| 0 | 2936 |
| 2937 // obj: object to lock | |
| 2938 // box: box address (header location) -- killed | |
| 2939 // tmp: rax -- killed | |
| 2940 // scr: rbx -- killed | |
| 2941 // | |
| 2942 // What follows is a direct transliteration of fast_lock() and fast_unlock() | |
| 2943 // from i486.ad. See that file for comments. | |
| 2944 // TODO: where possible switch from movq (r, 0) to movl(r,0) and | |
| 2945 // use the shorter encoding. (Movl clears the high-order 32-bits). | |
| 2946 | |
| 2947 | |
| 2948 enc_class Fast_Lock(rRegP obj, rRegP box, rax_RegI tmp, rRegP scr) | |
| 2949 %{ | |
| 2950 Register objReg = as_Register((int)$obj$$reg); | |
| 2951 Register boxReg = as_Register((int)$box$$reg); | |
| 2952 Register tmpReg = as_Register($tmp$$reg); | |
| 2953 Register scrReg = as_Register($scr$$reg); | |
| 2954 MacroAssembler masm(&cbuf); | |
| 2955 | |
| 2956 // Verify uniqueness of register assignments -- necessary but not sufficient | |
| 2957 assert (objReg != boxReg && objReg != tmpReg && | |
| 2958 objReg != scrReg && tmpReg != scrReg, "invariant") ; | |
| 2959 | |
| 2960 if (_counters != NULL) { | |
| 2961 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr())); | |
| 2962 } | |
| 2963 if (EmitSync & 1) { | |
| 304 | 2964 // Without cast to int32_t a movptr will destroy r10 which is typically obj |
|
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2965 masm.movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ; |
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2966 masm.cmpptr(rsp, (int32_t)NULL_WORD) ; |
| 0 | 2967 } else |
| 2968 if (EmitSync & 2) { | |
| 2969 Label DONE_LABEL; | |
| 2970 if (UseBiasedLocking) { | |
| 2971 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument. | |
| 2972 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters); | |
| 2973 } | |
| 304 | 2974 // QQQ was movl... |
| 2975 masm.movptr(tmpReg, 0x1); | |
| 2976 masm.orptr(tmpReg, Address(objReg, 0)); | |
| 2977 masm.movptr(Address(boxReg, 0), tmpReg); | |
| 0 | 2978 if (os::is_MP()) { |
| 2979 masm.lock(); | |
| 2980 } | |
| 304 | 2981 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg |
| 0 | 2982 masm.jcc(Assembler::equal, DONE_LABEL); |
| 2983 | |
| 2984 // Recursive locking | |
| 304 | 2985 masm.subptr(tmpReg, rsp); |
| 2986 masm.andptr(tmpReg, 7 - os::vm_page_size()); | |
| 2987 masm.movptr(Address(boxReg, 0), tmpReg); | |
| 0 | 2988 |
| 2989 masm.bind(DONE_LABEL); | |
| 2990 masm.nop(); // avoid branch to branch | |
| 2991 } else { | |
| 2992 Label DONE_LABEL, IsInflated, Egress; | |
| 2993 | |
|
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2994 masm.movptr(tmpReg, Address(objReg, 0)) ; |
| 304 | 2995 masm.testl (tmpReg, 0x02) ; // inflated vs stack-locked|neutral|biased |
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2996 masm.jcc (Assembler::notZero, IsInflated) ; |
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2997 |
| 0 | 2998 // it's stack-locked, biased or neutral |
| 2999 // TODO: optimize markword triage order to reduce the number of | |
| 3000 // conditional branches in the most common cases. | |
| 3001 // Beware -- there's a subtle invariant that fetch of the markword | |
| 3002 // at [FETCH], below, will never observe a biased encoding (*101b). | |
| 3003 // If this invariant is not held we'll suffer exclusion (safety) failure. | |
| 3004 | |
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3005 if (UseBiasedLocking && !UseOptoBiasInlining) { |
| 0 | 3006 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, true, DONE_LABEL, NULL, _counters); |
| 304 | 3007 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH] |
| 0 | 3008 } |
| 3009 | |
| 304 | 3010 // was q will it destroy high? |
|
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3011 masm.orl (tmpReg, 1) ; |
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3012 masm.movptr(Address(boxReg, 0), tmpReg) ; |
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3013 if (os::is_MP()) { masm.lock(); } |
| 304 | 3014 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg |
| 0 | 3015 if (_counters != NULL) { |
| 3016 masm.cond_inc32(Assembler::equal, | |
| 3017 ExternalAddress((address) _counters->fast_path_entry_count_addr())); | |
| 3018 } | |
| 3019 masm.jcc (Assembler::equal, DONE_LABEL); | |
| 3020 | |
| 3021 // Recursive locking | |
| 304 | 3022 masm.subptr(tmpReg, rsp); |
| 3023 masm.andptr(tmpReg, 7 - os::vm_page_size()); | |
| 3024 masm.movptr(Address(boxReg, 0), tmpReg); | |
| 0 | 3025 if (_counters != NULL) { |
| 3026 masm.cond_inc32(Assembler::equal, | |
| 3027 ExternalAddress((address) _counters->fast_path_entry_count_addr())); | |
| 3028 } | |
| 3029 masm.jmp (DONE_LABEL) ; | |
| 3030 | |
| 3031 masm.bind (IsInflated) ; | |
| 3032 // It's inflated | |
| 3033 | |
| 3034 // TODO: someday avoid the ST-before-CAS penalty by | |
| 3035 // relocating (deferring) the following ST. | |
| 3036 // We should also think about trying a CAS without having | |
| 3037 // fetched _owner. If the CAS is successful we may | |
| 3038 // avoid an RTO->RTS upgrade on the $line. | |
| 304 | 3039 // Without cast to int32_t a movptr will destroy r10 which is typically obj |
|
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3040 masm.movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ; |
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3041 |
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3042 masm.mov (boxReg, tmpReg) ; |
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3043 masm.movptr (tmpReg, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
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3044 masm.testptr(tmpReg, tmpReg) ; |
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3045 masm.jcc (Assembler::notZero, DONE_LABEL) ; |
| 0 | 3046 |
| 3047 // It's inflated and appears unlocked | |
|
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3048 if (os::is_MP()) { masm.lock(); } |
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3049 masm.cmpxchgptr(r15_thread, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
| 0 | 3050 // Intentional fall-through into DONE_LABEL ... |
| 3051 | |
| 3052 masm.bind (DONE_LABEL) ; | |
| 3053 masm.nop () ; // avoid jmp to jmp | |
| 3054 } | |
| 3055 %} | |
| 3056 | |
| 3057 // obj: object to unlock | |
| 3058 // box: box address (displaced header location), killed | |
| 3059 // RBX: killed tmp; cannot be obj nor box | |
| 3060 enc_class Fast_Unlock(rRegP obj, rax_RegP box, rRegP tmp) | |
| 3061 %{ | |
| 3062 | |
| 3063 Register objReg = as_Register($obj$$reg); | |
| 3064 Register boxReg = as_Register($box$$reg); | |
| 3065 Register tmpReg = as_Register($tmp$$reg); | |
| 3066 MacroAssembler masm(&cbuf); | |
| 3067 | |
|
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3068 if (EmitSync & 4) { |
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3069 masm.cmpptr(rsp, 0) ; |
| 0 | 3070 } else |
| 3071 if (EmitSync & 8) { | |
| 3072 Label DONE_LABEL; | |
| 3073 if (UseBiasedLocking) { | |
| 3074 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); | |
| 3075 } | |
| 3076 | |
| 3077 // Check whether the displaced header is 0 | |
| 3078 //(=> recursive unlock) | |
| 304 | 3079 masm.movptr(tmpReg, Address(boxReg, 0)); |
| 3080 masm.testptr(tmpReg, tmpReg); | |
| 0 | 3081 masm.jcc(Assembler::zero, DONE_LABEL); |
| 3082 | |
| 3083 // If not recursive lock, reset the header to displaced header | |
| 3084 if (os::is_MP()) { | |
| 3085 masm.lock(); | |
| 3086 } | |
| 304 | 3087 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box |
| 0 | 3088 masm.bind(DONE_LABEL); |
| 3089 masm.nop(); // avoid branch to branch | |
| 3090 } else { | |
| 3091 Label DONE_LABEL, Stacked, CheckSucc ; | |
| 3092 | |
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3093 if (UseBiasedLocking && !UseOptoBiasInlining) { |
| 0 | 3094 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); |
| 3095 } | |
|
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3096 |
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3097 masm.movptr(tmpReg, Address(objReg, 0)) ; |
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3098 masm.cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD) ; |
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3099 masm.jcc (Assembler::zero, DONE_LABEL) ; |
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3100 masm.testl (tmpReg, 0x02) ; |
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3101 masm.jcc (Assembler::zero, Stacked) ; |
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3102 |
| 0 | 3103 // It's inflated |
|
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3104 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
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3105 masm.xorptr(boxReg, r15_thread) ; |
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3106 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ; |
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3107 masm.jcc (Assembler::notZero, DONE_LABEL) ; |
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3108 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ; |
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3109 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ; |
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3110 masm.jcc (Assembler::notZero, CheckSucc) ; |
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3111 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ; |
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3112 masm.jmp (DONE_LABEL) ; |
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3113 |
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|
3114 if ((EmitSync & 65536) == 0) { |
| 0 | 3115 Label LSuccess, LGoSlowPath ; |
| 3116 masm.bind (CheckSucc) ; | |
| 304 | 3117 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ; |
| 0 | 3118 masm.jcc (Assembler::zero, LGoSlowPath) ; |
| 3119 | |
| 3120 // I'd much rather use lock:andl m->_owner, 0 as it's faster than the | |
| 3121 // the explicit ST;MEMBAR combination, but masm doesn't currently support | |
| 3122 // "ANDQ M,IMM". Don't use MFENCE here. lock:add to TOS, xchg, etc | |
| 3123 // are all faster when the write buffer is populated. | |
| 304 | 3124 masm.movptr (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ; |
| 0 | 3125 if (os::is_MP()) { |
| 304 | 3126 masm.lock () ; masm.addl (Address(rsp, 0), 0) ; |
| 0 | 3127 } |
| 304 | 3128 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ; |
| 0 | 3129 masm.jcc (Assembler::notZero, LSuccess) ; |
| 3130 | |
| 304 | 3131 masm.movptr (boxReg, (int32_t)NULL_WORD) ; // box is really EAX |
| 0 | 3132 if (os::is_MP()) { masm.lock(); } |
| 304 | 3133 masm.cmpxchgptr(r15_thread, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)); |
| 0 | 3134 masm.jcc (Assembler::notEqual, LSuccess) ; |
| 3135 // Intentional fall-through into slow-path | |
| 3136 | |
| 3137 masm.bind (LGoSlowPath) ; | |
| 3138 masm.orl (boxReg, 1) ; // set ICC.ZF=0 to indicate failure | |
| 3139 masm.jmp (DONE_LABEL) ; | |
| 3140 | |
| 3141 masm.bind (LSuccess) ; | |
| 3142 masm.testl (boxReg, 0) ; // set ICC.ZF=1 to indicate success | |
| 3143 masm.jmp (DONE_LABEL) ; | |
| 3144 } | |
| 3145 | |
|
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3146 masm.bind (Stacked) ; |
| 304 | 3147 masm.movptr(tmpReg, Address (boxReg, 0)) ; // re-fetch |
|
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3148 if (os::is_MP()) { masm.lock(); } |
| 304 | 3149 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box |
| 0 | 3150 |
| 3151 if (EmitSync & 65536) { | |
| 3152 masm.bind (CheckSucc) ; | |
| 3153 } | |
| 3154 masm.bind(DONE_LABEL); | |
| 3155 if (EmitSync & 32768) { | |
| 3156 masm.nop(); // avoid branch to branch | |
| 3157 } | |
| 3158 } | |
| 3159 %} | |
| 3160 | |
|
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3161 |
| 0 | 3162 enc_class enc_rethrow() |
| 3163 %{ | |
| 1748 | 3164 cbuf.set_insts_mark(); |
| 0 | 3165 emit_opcode(cbuf, 0xE9); // jmp entry |
| 3166 emit_d32_reloc(cbuf, | |
| 1748 | 3167 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4), |
| 0 | 3168 runtime_call_Relocation::spec(), |
| 3169 RELOC_DISP32); | |
| 3170 %} | |
| 3171 | |
| 3172 %} | |
| 3173 | |
| 3174 | |
|
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3175 |
| 0 | 3176 //----------FRAME-------------------------------------------------------------- |
| 3177 // Definition of frame structure and management information. | |
| 3178 // | |
| 3179 // S T A C K L A Y O U T Allocators stack-slot number | |
| 3180 // | (to get allocators register number | |
| 3181 // G Owned by | | v add OptoReg::stack0()) | |
| 3182 // r CALLER | | | |
| 3183 // o | +--------+ pad to even-align allocators stack-slot | |
| 3184 // w V | pad0 | numbers; owned by CALLER | |
| 3185 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned | |
| 3186 // h ^ | in | 5 | |
| 3187 // | | args | 4 Holes in incoming args owned by SELF | |
| 3188 // | | | | 3 | |
| 3189 // | | +--------+ | |
| 3190 // V | | old out| Empty on Intel, window on Sparc | |
| 3191 // | old |preserve| Must be even aligned. | |
| 3192 // | SP-+--------+----> Matcher::_old_SP, even aligned | |
| 3193 // | | in | 3 area for Intel ret address | |
| 3194 // Owned by |preserve| Empty on Sparc. | |
| 3195 // SELF +--------+ | |
| 3196 // | | pad2 | 2 pad to align old SP | |
| 3197 // | +--------+ 1 | |
| 3198 // | | locks | 0 | |
| 3199 // | +--------+----> OptoReg::stack0(), even aligned | |
| 3200 // | | pad1 | 11 pad to align new SP | |
| 3201 // | +--------+ | |
| 3202 // | | | 10 | |
| 3203 // | | spills | 9 spills | |
| 3204 // V | | 8 (pad0 slot for callee) | |
| 3205 // -----------+--------+----> Matcher::_out_arg_limit, unaligned | |
| 3206 // ^ | out | 7 | |
| 3207 // | | args | 6 Holes in outgoing args owned by CALLEE | |
| 3208 // Owned by +--------+ | |
| 3209 // CALLEE | new out| 6 Empty on Intel, window on Sparc | |
| 3210 // | new |preserve| Must be even-aligned. | |
| 3211 // | SP-+--------+----> Matcher::_new_SP, even aligned | |
| 3212 // | | | | |
| 3213 // | |
| 3214 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is | |
| 3215 // known from SELF's arguments and the Java calling convention. | |
| 3216 // Region 6-7 is determined per call site. | |
| 3217 // Note 2: If the calling convention leaves holes in the incoming argument | |
| 3218 // area, those holes are owned by SELF. Holes in the outgoing area | |
| 3219 // are owned by the CALLEE. Holes should not be nessecary in the | |
| 3220 // incoming area, as the Java calling convention is completely under | |
| 3221 // the control of the AD file. Doubles can be sorted and packed to | |
| 3222 // avoid holes. Holes in the outgoing arguments may be nessecary for | |
| 3223 // varargs C calling conventions. | |
| 3224 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is | |
| 3225 // even aligned with pad0 as needed. | |
| 3226 // Region 6 is even aligned. Region 6-7 is NOT even aligned; | |
| 3227 // region 6-11 is even aligned; it may be padded out more so that | |
| 3228 // the region from SP to FP meets the minimum stack alignment. | |
| 3229 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack | |
| 3230 // alignment. Region 11, pad1, may be dynamically extended so that | |
| 3231 // SP meets the minimum alignment. | |
| 3232 | |
| 3233 frame | |
| 3234 %{ | |
| 3235 // What direction does stack grow in (assumed to be same for C & Java) | |
| 3236 stack_direction(TOWARDS_LOW); | |
| 3237 | |
| 3238 // These three registers define part of the calling convention | |
| 3239 // between compiled code and the interpreter. | |
| 3240 inline_cache_reg(RAX); // Inline Cache Register | |
| 3241 interpreter_method_oop_reg(RBX); // Method Oop Register when | |
| 3242 // calling interpreter | |
| 3243 | |
| 3244 // Optional: name the operand used by cisc-spilling to access | |
| 3245 // [stack_pointer + offset] | |
| 3246 cisc_spilling_operand_name(indOffset32); | |
| 3247 | |
| 3248 // Number of stack slots consumed by locking an object | |
| 3249 sync_stack_slots(2); | |
| 3250 | |
| 3251 // Compiled code's Frame Pointer | |
| 3252 frame_pointer(RSP); | |
| 3253 | |
| 3254 // Interpreter stores its frame pointer in a register which is | |
| 3255 // stored to the stack by I2CAdaptors. | |
| 3256 // I2CAdaptors convert from interpreted java to compiled java. | |
| 3257 interpreter_frame_pointer(RBP); | |
| 3258 | |
| 3259 // Stack alignment requirement | |
| 3260 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes) | |
| 3261 | |
| 3262 // Number of stack slots between incoming argument block and the start of | |
| 3263 // a new frame. The PROLOG must add this many slots to the stack. The | |
| 3264 // EPILOG must remove this many slots. amd64 needs two slots for | |
| 3265 // return address. | |
| 3266 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls); | |
| 3267 | |
| 3268 // Number of outgoing stack slots killed above the out_preserve_stack_slots | |
| 3269 // for calls to C. Supports the var-args backing area for register parms. | |
| 3270 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt); | |
| 3271 | |
| 3272 // The after-PROLOG location of the return address. Location of | |
| 3273 // return address specifies a type (REG or STACK) and a number | |
| 3274 // representing the register number (i.e. - use a register name) or | |
| 3275 // stack slot. | |
| 3276 // Ret Addr is on stack in slot 0 if no locks or verification or alignment. | |
| 3277 // Otherwise, it is above the locks and verification slot and alignment word | |
| 3278 return_addr(STACK - 2 + | |
| 3279 round_to(2 + 2 * VerifyStackAtCalls + | |
| 3280 Compile::current()->fixed_slots(), | |
| 3281 WordsPerLong * 2)); | |
| 3282 | |
| 3283 // Body of function which returns an integer array locating | |
| 3284 // arguments either in registers or in stack slots. Passed an array | |
| 3285 // of ideal registers called "sig" and a "length" count. Stack-slot | |
| 3286 // offsets are based on outgoing arguments, i.e. a CALLER setting up | |
| 3287 // arguments for a CALLEE. Incoming stack arguments are | |
| 3288 // automatically biased by the preserve_stack_slots field above. | |
| 3289 | |
| 3290 calling_convention | |
| 3291 %{ | |
| 3292 // No difference between ingoing/outgoing just pass false | |
| 3293 SharedRuntime::java_calling_convention(sig_bt, regs, length, false); | |
| 3294 %} | |
| 3295 | |
| 3296 c_calling_convention | |
| 3297 %{ | |
| 3298 // This is obviously always outgoing | |
| 3299 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); | |
| 3300 %} | |
| 3301 | |
| 3302 // Location of compiled Java return values. Same as C for now. | |
| 3303 return_value | |
| 3304 %{ | |
| 3305 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, | |
| 3306 "only return normal values"); | |
| 3307 | |
| 3308 static const int lo[Op_RegL + 1] = { | |
| 3309 0, | |
| 3310 0, | |
|
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3311 RAX_num, // Op_RegN |
| 0 | 3312 RAX_num, // Op_RegI |
| 3313 RAX_num, // Op_RegP | |
| 3314 XMM0_num, // Op_RegF | |
| 3315 XMM0_num, // Op_RegD | |
| 3316 RAX_num // Op_RegL | |
| 3317 }; | |
| 3318 static const int hi[Op_RegL + 1] = { | |
| 3319 0, | |
| 3320 0, | |
|
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3321 OptoReg::Bad, // Op_RegN |
| 0 | 3322 OptoReg::Bad, // Op_RegI |
| 3323 RAX_H_num, // Op_RegP | |
| 3324 OptoReg::Bad, // Op_RegF | |
| 3325 XMM0_H_num, // Op_RegD | |
| 3326 RAX_H_num // Op_RegL | |
| 3327 }; | |
|
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3328 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 1, "missing type"); |
| 0 | 3329 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]); |
| 3330 %} | |
| 3331 %} | |
| 3332 | |
| 3333 //----------ATTRIBUTES--------------------------------------------------------- | |
| 3334 //----------Operand Attributes------------------------------------------------- | |
| 3335 op_attrib op_cost(0); // Required cost attribute | |
| 3336 | |
| 3337 //----------Instruction Attributes--------------------------------------------- | |
| 3338 ins_attrib ins_cost(100); // Required cost attribute | |
| 3339 ins_attrib ins_size(8); // Required size attribute (in bits) | |
| 3340 ins_attrib ins_short_branch(0); // Required flag: is this instruction | |
| 3341 // a non-matching short branch variant | |
| 3342 // of some long branch? | |
| 3343 ins_attrib ins_alignment(1); // Required alignment attribute (must | |
| 3344 // be a power of 2) specifies the | |
| 3345 // alignment that some part of the | |
| 3346 // instruction (not necessarily the | |
| 3347 // start) requires. If > 1, a | |
| 3348 // compute_padding() function must be | |
| 3349 // provided for the instruction | |
| 3350 | |
| 3351 //----------OPERANDS----------------------------------------------------------- | |
| 3352 // Operand definitions must precede instruction definitions for correct parsing | |
| 3353 // in the ADLC because operands constitute user defined types which are used in | |
| 3354 // instruction definitions. | |
| 3355 | |
| 3356 //----------Simple Operands---------------------------------------------------- | |
| 3357 // Immediate Operands | |
| 3358 // Integer Immediate | |
| 3359 operand immI() | |
| 3360 %{ | |
| 3361 match(ConI); | |
| 3362 | |
| 3363 op_cost(10); | |
| 3364 format %{ %} | |
| 3365 interface(CONST_INTER); | |
| 3366 %} | |
| 3367 | |
| 3368 // Constant for test vs zero | |
| 3369 operand immI0() | |
| 3370 %{ | |
| 3371 predicate(n->get_int() == 0); | |
| 3372 match(ConI); | |
| 3373 | |
| 3374 op_cost(0); | |
| 3375 format %{ %} | |
| 3376 interface(CONST_INTER); | |
| 3377 %} | |
| 3378 | |
| 3379 // Constant for increment | |
| 3380 operand immI1() | |
| 3381 %{ | |
| 3382 predicate(n->get_int() == 1); | |
| 3383 match(ConI); | |
| 3384 | |
| 3385 op_cost(0); | |
| 3386 format %{ %} | |
| 3387 interface(CONST_INTER); | |
| 3388 %} | |
| 3389 | |
| 3390 // Constant for decrement | |
| 3391 operand immI_M1() | |
| 3392 %{ | |
| 3393 predicate(n->get_int() == -1); | |
| 3394 match(ConI); | |
| 3395 | |
| 3396 op_cost(0); | |
| 3397 format %{ %} | |
| 3398 interface(CONST_INTER); | |
| 3399 %} | |
| 3400 | |
| 3401 // Valid scale values for addressing modes | |
| 3402 operand immI2() | |
| 3403 %{ | |
| 3404 predicate(0 <= n->get_int() && (n->get_int() <= 3)); | |
| 3405 match(ConI); | |
| 3406 | |
| 3407 format %{ %} | |
| 3408 interface(CONST_INTER); | |
| 3409 %} | |
| 3410 | |
| 3411 operand immI8() | |
| 3412 %{ | |
| 3413 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80)); | |
| 3414 match(ConI); | |
| 3415 | |
| 3416 op_cost(5); | |
| 3417 format %{ %} | |
| 3418 interface(CONST_INTER); | |
| 3419 %} | |
| 3420 | |
| 3421 operand immI16() | |
| 3422 %{ | |
| 3423 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767)); | |
| 3424 match(ConI); | |
| 3425 | |
| 3426 op_cost(10); | |
| 3427 format %{ %} | |
| 3428 interface(CONST_INTER); | |
| 3429 %} | |
| 3430 | |
| 3431 // Constant for long shifts | |
| 3432 operand immI_32() | |
| 3433 %{ | |
| 3434 predicate( n->get_int() == 32 ); | |
| 3435 match(ConI); | |
| 3436 | |
| 3437 op_cost(0); | |
| 3438 format %{ %} | |
| 3439 interface(CONST_INTER); | |
| 3440 %} | |
| 3441 | |
| 3442 // Constant for long shifts | |
| 3443 operand immI_64() | |
| 3444 %{ | |
| 3445 predicate( n->get_int() == 64 ); | |
| 3446 match(ConI); | |
| 3447 | |
| 3448 op_cost(0); | |
| 3449 format %{ %} | |
| 3450 interface(CONST_INTER); | |
| 3451 %} | |
| 3452 | |
| 3453 // Pointer Immediate | |
| 3454 operand immP() | |
| 3455 %{ | |
| 3456 match(ConP); | |
| 3457 | |
| 3458 op_cost(10); | |
| 3459 format %{ %} | |
| 3460 interface(CONST_INTER); | |
| 3461 %} | |
| 3462 | |
| 3463 // NULL Pointer Immediate | |
| 3464 operand immP0() | |
| 3465 %{ | |
| 3466 predicate(n->get_ptr() == 0); | |
| 3467 match(ConP); | |
| 3468 | |
| 3469 op_cost(5); | |
| 3470 format %{ %} | |
| 3471 interface(CONST_INTER); | |
| 3472 %} | |
| 3473 | |
|
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3474 operand immP_poll() %{ |
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3475 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page()); |
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3476 match(ConP); |
|
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3477 |
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3478 // formats are generated automatically for constants and base registers |
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3479 format %{ %} |
|
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3480 interface(CONST_INTER); |
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3481 %} |
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3482 |
|
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3483 // Pointer Immediate |
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3484 operand immN() %{ |
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3485 match(ConN); |
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3486 |
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3487 op_cost(10); |
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3488 format %{ %} |
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3489 interface(CONST_INTER); |
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3490 %} |
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3491 |
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3492 // NULL Pointer Immediate |
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3493 operand immN0() %{ |
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3494 predicate(n->get_narrowcon() == 0); |
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3495 match(ConN); |
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3496 |
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3497 op_cost(5); |
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3498 format %{ %} |
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3499 interface(CONST_INTER); |
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3500 %} |
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3501 |
| 0 | 3502 operand immP31() |
| 3503 %{ | |
| 3504 predicate(!n->as_Type()->type()->isa_oopptr() | |
| 3505 && (n->get_ptr() >> 31) == 0); | |
| 3506 match(ConP); | |
| 3507 | |
| 3508 op_cost(5); | |
| 3509 format %{ %} | |
| 3510 interface(CONST_INTER); | |
| 3511 %} | |
| 3512 | |
|
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3513 |
| 0 | 3514 // Long Immediate |
| 3515 operand immL() | |
| 3516 %{ | |
| 3517 match(ConL); | |
| 3518 | |
| 3519 op_cost(20); | |
| 3520 format %{ %} | |
| 3521 interface(CONST_INTER); | |
| 3522 %} | |
| 3523 | |
| 3524 // Long Immediate 8-bit | |
| 3525 operand immL8() | |
| 3526 %{ | |
| 3527 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L); | |
| 3528 match(ConL); | |
| 3529 | |
| 3530 op_cost(5); | |
| 3531 format %{ %} | |
| 3532 interface(CONST_INTER); | |
| 3533 %} | |
| 3534 | |
| 3535 // Long Immediate 32-bit unsigned | |
| 3536 operand immUL32() | |
| 3537 %{ | |
| 3538 predicate(n->get_long() == (unsigned int) (n->get_long())); | |
| 3539 match(ConL); | |
| 3540 | |
| 3541 op_cost(10); | |
| 3542 format %{ %} | |
| 3543 interface(CONST_INTER); | |
| 3544 %} | |
| 3545 | |
| 3546 // Long Immediate 32-bit signed | |
| 3547 operand immL32() | |
| 3548 %{ | |
| 3549 predicate(n->get_long() == (int) (n->get_long())); | |
| 3550 match(ConL); | |
| 3551 | |
| 3552 op_cost(15); | |
| 3553 format %{ %} | |
| 3554 interface(CONST_INTER); | |
| 3555 %} | |
| 3556 | |
| 3557 // Long Immediate zero | |
| 3558 operand immL0() | |
| 3559 %{ | |
| 3560 predicate(n->get_long() == 0L); | |
| 3561 match(ConL); | |
| 3562 | |
| 3563 op_cost(10); | |
| 3564 format %{ %} | |
| 3565 interface(CONST_INTER); | |
| 3566 %} | |
| 3567 | |
| 3568 // Constant for increment | |
| 3569 operand immL1() | |
| 3570 %{ | |
| 3571 predicate(n->get_long() == 1); | |
| 3572 match(ConL); | |
| 3573 | |
| 3574 format %{ %} | |
| 3575 interface(CONST_INTER); | |
| 3576 %} | |
| 3577 | |
| 3578 // Constant for decrement | |
| 3579 operand immL_M1() | |
| 3580 %{ | |
| 3581 predicate(n->get_long() == -1); | |
| 3582 match(ConL); | |
| 3583 | |
| 3584 format %{ %} | |
| 3585 interface(CONST_INTER); | |
| 3586 %} | |
| 3587 | |
| 3588 // Long Immediate: the value 10 | |
| 3589 operand immL10() | |
| 3590 %{ | |
| 3591 predicate(n->get_long() == 10); | |
| 3592 match(ConL); | |
| 3593 | |
| 3594 format %{ %} | |
| 3595 interface(CONST_INTER); | |
| 3596 %} | |
| 3597 | |
| 3598 // Long immediate from 0 to 127. | |
| 3599 // Used for a shorter form of long mul by 10. | |
| 3600 operand immL_127() | |
| 3601 %{ | |
| 3602 predicate(0 <= n->get_long() && n->get_long() < 0x80); | |
| 3603 match(ConL); | |
| 3604 | |
| 3605 op_cost(10); | |
| 3606 format %{ %} | |
| 3607 interface(CONST_INTER); | |
| 3608 %} | |
| 3609 | |
| 3610 // Long Immediate: low 32-bit mask | |
| 3611 operand immL_32bits() | |
| 3612 %{ | |
| 3613 predicate(n->get_long() == 0xFFFFFFFFL); | |
| 3614 match(ConL); | |
| 3615 op_cost(20); | |
| 3616 | |
| 3617 format %{ %} | |
| 3618 interface(CONST_INTER); | |
| 3619 %} | |
| 3620 | |
| 3621 // Float Immediate zero | |
| 3622 operand immF0() | |
| 3623 %{ | |
| 3624 predicate(jint_cast(n->getf()) == 0); | |
| 3625 match(ConF); | |
| 3626 | |
| 3627 op_cost(5); | |
| 3628 format %{ %} | |
| 3629 interface(CONST_INTER); | |
| 3630 %} | |
| 3631 | |
| 3632 // Float Immediate | |
| 3633 operand immF() | |
| 3634 %{ | |
| 3635 match(ConF); | |
| 3636 | |
| 3637 op_cost(15); | |
| 3638 format %{ %} | |
| 3639 interface(CONST_INTER); | |
| 3640 %} | |
| 3641 | |
| 3642 // Double Immediate zero | |
| 3643 operand immD0() | |
| 3644 %{ | |
| 3645 predicate(jlong_cast(n->getd()) == 0); | |
| 3646 match(ConD); | |
| 3647 | |
| 3648 op_cost(5); | |
| 3649 format %{ %} | |
| 3650 interface(CONST_INTER); | |
| 3651 %} | |
| 3652 | |
| 3653 // Double Immediate | |
| 3654 operand immD() | |
| 3655 %{ | |
| 3656 match(ConD); | |
| 3657 | |
| 3658 op_cost(15); | |
| 3659 format %{ %} | |
| 3660 interface(CONST_INTER); | |
| 3661 %} | |
| 3662 | |
| 3663 // Immediates for special shifts (sign extend) | |
| 3664 | |
| 3665 // Constants for increment | |
| 3666 operand immI_16() | |
| 3667 %{ | |
| 3668 predicate(n->get_int() == 16); | |
| 3669 match(ConI); | |
| 3670 | |
| 3671 format %{ %} | |
| 3672 interface(CONST_INTER); | |
| 3673 %} | |
| 3674 | |
| 3675 operand immI_24() | |
| 3676 %{ | |
| 3677 predicate(n->get_int() == 24); | |
| 3678 match(ConI); | |
| 3679 | |
| 3680 format %{ %} | |
| 3681 interface(CONST_INTER); | |
| 3682 %} | |
| 3683 | |
| 3684 // Constant for byte-wide masking | |
| 3685 operand immI_255() | |
| 3686 %{ | |
| 3687 predicate(n->get_int() == 255); | |
| 3688 match(ConI); | |
| 3689 | |
| 3690 format %{ %} | |
| 3691 interface(CONST_INTER); | |
| 3692 %} | |
| 3693 | |
| 3694 // Constant for short-wide masking | |
| 3695 operand immI_65535() | |
| 3696 %{ | |
| 3697 predicate(n->get_int() == 65535); | |
| 3698 match(ConI); | |
| 3699 | |
| 3700 format %{ %} | |
| 3701 interface(CONST_INTER); | |
| 3702 %} | |
| 3703 | |
| 3704 // Constant for byte-wide masking | |
| 3705 operand immL_255() | |
| 3706 %{ | |
| 3707 predicate(n->get_long() == 255); | |
| 3708 match(ConL); | |
| 3709 | |
| 3710 format %{ %} | |
| 3711 interface(CONST_INTER); | |
| 3712 %} | |
| 3713 | |
| 3714 // Constant for short-wide masking | |
| 3715 operand immL_65535() | |
| 3716 %{ | |
| 3717 predicate(n->get_long() == 65535); | |
| 3718 match(ConL); | |
| 3719 | |
| 3720 format %{ %} | |
| 3721 interface(CONST_INTER); | |
| 3722 %} | |
| 3723 | |
| 3724 // Register Operands | |
| 3725 // Integer Register | |
| 3726 operand rRegI() | |
| 3727 %{ | |
| 3728 constraint(ALLOC_IN_RC(int_reg)); | |
| 3729 match(RegI); | |
| 3730 | |
| 3731 match(rax_RegI); | |
| 3732 match(rbx_RegI); | |
| 3733 match(rcx_RegI); | |
| 3734 match(rdx_RegI); | |
| 3735 match(rdi_RegI); | |
| 3736 | |
| 3737 format %{ %} | |
| 3738 interface(REG_INTER); | |
| 3739 %} | |
| 3740 | |
| 3741 // Special Registers | |
| 3742 operand rax_RegI() | |
| 3743 %{ | |
| 3744 constraint(ALLOC_IN_RC(int_rax_reg)); | |
| 3745 match(RegI); | |
| 3746 match(rRegI); | |
| 3747 | |
| 3748 format %{ "RAX" %} | |
| 3749 interface(REG_INTER); | |
| 3750 %} | |
| 3751 | |
| 3752 // Special Registers | |
| 3753 operand rbx_RegI() | |
| 3754 %{ | |
| 3755 constraint(ALLOC_IN_RC(int_rbx_reg)); | |
| 3756 match(RegI); | |
| 3757 match(rRegI); | |
| 3758 | |
| 3759 format %{ "RBX" %} | |
| 3760 interface(REG_INTER); | |
| 3761 %} | |
| 3762 | |
| 3763 operand rcx_RegI() | |
| 3764 %{ | |
| 3765 constraint(ALLOC_IN_RC(int_rcx_reg)); | |
| 3766 match(RegI); | |
| 3767 match(rRegI); | |
| 3768 | |
| 3769 format %{ "RCX" %} | |
| 3770 interface(REG_INTER); | |
| 3771 %} | |
| 3772 | |
| 3773 operand rdx_RegI() | |
| 3774 %{ | |
| 3775 constraint(ALLOC_IN_RC(int_rdx_reg)); | |
| 3776 match(RegI); | |
| 3777 match(rRegI); | |
| 3778 | |
| 3779 format %{ "RDX" %} | |
| 3780 interface(REG_INTER); | |
| 3781 %} | |
| 3782 | |
| 3783 operand rdi_RegI() | |
| 3784 %{ | |
| 3785 constraint(ALLOC_IN_RC(int_rdi_reg)); | |
| 3786 match(RegI); | |
| 3787 match(rRegI); | |
| 3788 | |
| 3789 format %{ "RDI" %} | |
| 3790 interface(REG_INTER); | |
| 3791 %} | |
| 3792 | |
| 3793 operand no_rcx_RegI() | |
| 3794 %{ | |
| 3795 constraint(ALLOC_IN_RC(int_no_rcx_reg)); | |
| 3796 match(RegI); | |
| 3797 match(rax_RegI); | |
| 3798 match(rbx_RegI); | |
| 3799 match(rdx_RegI); | |
| 3800 match(rdi_RegI); | |
| 3801 | |
| 3802 format %{ %} | |
| 3803 interface(REG_INTER); | |
| 3804 %} | |
| 3805 | |
| 3806 operand no_rax_rdx_RegI() | |
| 3807 %{ | |
| 3808 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg)); | |
| 3809 match(RegI); | |
| 3810 match(rbx_RegI); | |
| 3811 match(rcx_RegI); | |
| 3812 match(rdi_RegI); | |
| 3813 | |
| 3814 format %{ %} | |
| 3815 interface(REG_INTER); | |
| 3816 %} | |
| 3817 | |
| 3818 // Pointer Register | |
| 3819 operand any_RegP() | |
| 3820 %{ | |
| 3821 constraint(ALLOC_IN_RC(any_reg)); | |
| 3822 match(RegP); | |
| 3823 match(rax_RegP); | |
| 3824 match(rbx_RegP); | |
| 3825 match(rdi_RegP); | |
| 3826 match(rsi_RegP); | |
| 3827 match(rbp_RegP); | |
| 3828 match(r15_RegP); | |
| 3829 match(rRegP); | |
| 3830 | |
| 3831 format %{ %} | |
| 3832 interface(REG_INTER); | |
| 3833 %} | |
| 3834 | |
| 3835 operand rRegP() | |
| 3836 %{ | |
| 3837 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3838 match(RegP); | |
| 3839 match(rax_RegP); | |
| 3840 match(rbx_RegP); | |
| 3841 match(rdi_RegP); | |
| 3842 match(rsi_RegP); | |
| 3843 match(rbp_RegP); | |
| 3844 match(r15_RegP); // See Q&A below about r15_RegP. | |
| 3845 | |
| 3846 format %{ %} | |
| 3847 interface(REG_INTER); | |
| 3848 %} | |
| 3849 | |
|
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3850 operand rRegN() %{ |
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3851 constraint(ALLOC_IN_RC(int_reg)); |
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3852 match(RegN); |
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3853 |
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3854 format %{ %} |
|
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3855 interface(REG_INTER); |
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3856 %} |
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3857 |
| 0 | 3858 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP? |
| 3859 // Answer: Operand match rules govern the DFA as it processes instruction inputs. | |
| 3860 // It's fine for an instruction input which expects rRegP to match a r15_RegP. | |
| 3861 // The output of an instruction is controlled by the allocator, which respects | |
| 3862 // register class masks, not match rules. Unless an instruction mentions | |
| 3863 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered | |
| 3864 // by the allocator as an input. | |
| 3865 | |
| 3866 operand no_rax_RegP() | |
| 3867 %{ | |
| 3868 constraint(ALLOC_IN_RC(ptr_no_rax_reg)); | |
| 3869 match(RegP); | |
| 3870 match(rbx_RegP); | |
| 3871 match(rsi_RegP); | |
| 3872 match(rdi_RegP); | |
| 3873 | |
| 3874 format %{ %} | |
| 3875 interface(REG_INTER); | |
| 3876 %} | |
| 3877 | |
| 3878 operand no_rbp_RegP() | |
| 3879 %{ | |
| 3880 constraint(ALLOC_IN_RC(ptr_no_rbp_reg)); | |
| 3881 match(RegP); | |
| 3882 match(rbx_RegP); | |
| 3883 match(rsi_RegP); | |
| 3884 match(rdi_RegP); | |
| 3885 | |
| 3886 format %{ %} | |
| 3887 interface(REG_INTER); | |
| 3888 %} | |
| 3889 | |
| 3890 operand no_rax_rbx_RegP() | |
| 3891 %{ | |
| 3892 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg)); | |
| 3893 match(RegP); | |
| 3894 match(rsi_RegP); | |
| 3895 match(rdi_RegP); | |
| 3896 | |
| 3897 format %{ %} | |
| 3898 interface(REG_INTER); | |
| 3899 %} | |
| 3900 | |
| 3901 // Special Registers | |
| 3902 // Return a pointer value | |
| 3903 operand rax_RegP() | |
| 3904 %{ | |
| 3905 constraint(ALLOC_IN_RC(ptr_rax_reg)); | |
| 3906 match(RegP); | |
| 3907 match(rRegP); | |
| 3908 | |
| 3909 format %{ %} | |
| 3910 interface(REG_INTER); | |
| 3911 %} | |
| 3912 | |
|
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3913 // Special Registers |
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3914 // Return a compressed pointer value |
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3915 operand rax_RegN() |
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3916 %{ |
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3917 constraint(ALLOC_IN_RC(int_rax_reg)); |
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3918 match(RegN); |
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3919 match(rRegN); |
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3920 |
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3921 format %{ %} |
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3922 interface(REG_INTER); |
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3923 %} |
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3924 |
| 0 | 3925 // Used in AtomicAdd |
| 3926 operand rbx_RegP() | |
| 3927 %{ | |
| 3928 constraint(ALLOC_IN_RC(ptr_rbx_reg)); | |
| 3929 match(RegP); | |
| 3930 match(rRegP); | |
| 3931 | |
| 3932 format %{ %} | |
| 3933 interface(REG_INTER); | |
| 3934 %} | |
| 3935 | |
| 3936 operand rsi_RegP() | |
| 3937 %{ | |
| 3938 constraint(ALLOC_IN_RC(ptr_rsi_reg)); | |
| 3939 match(RegP); | |
| 3940 match(rRegP); | |
| 3941 | |
| 3942 format %{ %} | |
| 3943 interface(REG_INTER); | |
| 3944 %} | |
| 3945 | |
| 3946 // Used in rep stosq | |
| 3947 operand rdi_RegP() | |
| 3948 %{ | |
| 3949 constraint(ALLOC_IN_RC(ptr_rdi_reg)); | |
| 3950 match(RegP); | |
| 3951 match(rRegP); | |
| 3952 | |
| 3953 format %{ %} | |
| 3954 interface(REG_INTER); | |
| 3955 %} | |
| 3956 | |
| 3957 operand rbp_RegP() | |
| 3958 %{ | |
| 3959 constraint(ALLOC_IN_RC(ptr_rbp_reg)); | |
| 3960 match(RegP); | |
| 3961 match(rRegP); | |
| 3962 | |
| 3963 format %{ %} | |
| 3964 interface(REG_INTER); | |
| 3965 %} | |
| 3966 | |
| 3967 operand r15_RegP() | |
| 3968 %{ | |
| 3969 constraint(ALLOC_IN_RC(ptr_r15_reg)); | |
| 3970 match(RegP); | |
| 3971 match(rRegP); | |
| 3972 | |
| 3973 format %{ %} | |
| 3974 interface(REG_INTER); | |
| 3975 %} | |
| 3976 | |
| 3977 operand rRegL() | |
| 3978 %{ | |
| 3979 constraint(ALLOC_IN_RC(long_reg)); | |
| 3980 match(RegL); | |
| 3981 match(rax_RegL); | |
| 3982 match(rdx_RegL); | |
| 3983 | |
| 3984 format %{ %} | |
| 3985 interface(REG_INTER); | |
| 3986 %} | |
| 3987 | |
| 3988 // Special Registers | |
| 3989 operand no_rax_rdx_RegL() | |
| 3990 %{ | |
| 3991 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg)); | |
| 3992 match(RegL); | |
| 3993 match(rRegL); | |
| 3994 | |
| 3995 format %{ %} | |
| 3996 interface(REG_INTER); | |
| 3997 %} | |
| 3998 | |
| 3999 operand no_rax_RegL() | |
| 4000 %{ | |
| 4001 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg)); | |
| 4002 match(RegL); | |
| 4003 match(rRegL); | |
| 4004 match(rdx_RegL); | |
| 4005 | |
| 4006 format %{ %} | |
| 4007 interface(REG_INTER); | |
| 4008 %} | |
| 4009 | |
| 4010 operand no_rcx_RegL() | |
| 4011 %{ | |
| 4012 constraint(ALLOC_IN_RC(long_no_rcx_reg)); | |
| 4013 match(RegL); | |
| 4014 match(rRegL); | |
| 4015 | |
| 4016 format %{ %} | |
| 4017 interface(REG_INTER); | |
| 4018 %} | |
| 4019 | |
| 4020 operand rax_RegL() | |
| 4021 %{ | |
| 4022 constraint(ALLOC_IN_RC(long_rax_reg)); | |
| 4023 match(RegL); | |
| 4024 match(rRegL); | |
| 4025 | |
| 4026 format %{ "RAX" %} | |
| 4027 interface(REG_INTER); | |
| 4028 %} | |
| 4029 | |
| 4030 operand rcx_RegL() | |
| 4031 %{ | |
| 4032 constraint(ALLOC_IN_RC(long_rcx_reg)); | |
| 4033 match(RegL); | |
| 4034 match(rRegL); | |
| 4035 | |
| 4036 format %{ %} | |
| 4037 interface(REG_INTER); | |
| 4038 %} | |
| 4039 | |
| 4040 operand rdx_RegL() | |
| 4041 %{ | |
| 4042 constraint(ALLOC_IN_RC(long_rdx_reg)); | |
| 4043 match(RegL); | |
| 4044 match(rRegL); | |
| 4045 | |
| 4046 format %{ %} | |
| 4047 interface(REG_INTER); | |
| 4048 %} | |
| 4049 | |
| 4050 // Flags register, used as output of compare instructions | |
| 4051 operand rFlagsReg() | |
| 4052 %{ | |
| 4053 constraint(ALLOC_IN_RC(int_flags)); | |
| 4054 match(RegFlags); | |
| 4055 | |
| 4056 format %{ "RFLAGS" %} | |
| 4057 interface(REG_INTER); | |
| 4058 %} | |
| 4059 | |
| 4060 // Flags register, used as output of FLOATING POINT compare instructions | |
| 4061 operand rFlagsRegU() | |
| 4062 %{ | |
| 4063 constraint(ALLOC_IN_RC(int_flags)); | |
| 4064 match(RegFlags); | |
| 4065 | |
| 4066 format %{ "RFLAGS_U" %} | |
| 4067 interface(REG_INTER); | |
| 4068 %} | |
| 4069 | |
|
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4070 operand rFlagsRegUCF() %{ |
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4071 constraint(ALLOC_IN_RC(int_flags)); |
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4072 match(RegFlags); |
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|
4073 predicate(false); |
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|
4074 |
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4075 format %{ "RFLAGS_U_CF" %} |
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4076 interface(REG_INTER); |
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4077 %} |
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|
4078 |
| 0 | 4079 // Float register operands |
| 4080 operand regF() | |
| 4081 %{ | |
| 4082 constraint(ALLOC_IN_RC(float_reg)); | |
| 4083 match(RegF); | |
| 4084 | |
| 4085 format %{ %} | |
| 4086 interface(REG_INTER); | |
| 4087 %} | |
| 4088 | |
| 4089 // Double register operands | |
|
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4090 operand regD() |
| 0 | 4091 %{ |
| 4092 constraint(ALLOC_IN_RC(double_reg)); | |
| 4093 match(RegD); | |
| 4094 | |
| 4095 format %{ %} | |
| 4096 interface(REG_INTER); | |
| 4097 %} | |
| 4098 | |
| 4099 | |
| 4100 //----------Memory Operands---------------------------------------------------- | |
| 4101 // Direct Memory Operand | |
| 4102 // operand direct(immP addr) | |
| 4103 // %{ | |
| 4104 // match(addr); | |
| 4105 | |
| 4106 // format %{ "[$addr]" %} | |
| 4107 // interface(MEMORY_INTER) %{ | |
| 4108 // base(0xFFFFFFFF); | |
| 4109 // index(0x4); | |
| 4110 // scale(0x0); | |
| 4111 // disp($addr); | |
| 4112 // %} | |
| 4113 // %} | |
| 4114 | |
| 4115 // Indirect Memory Operand | |
| 4116 operand indirect(any_RegP reg) | |
| 4117 %{ | |
| 4118 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 4119 match(reg); | |
| 4120 | |
| 4121 format %{ "[$reg]" %} | |
| 4122 interface(MEMORY_INTER) %{ | |
| 4123 base($reg); | |
| 4124 index(0x4); | |
| 4125 scale(0x0); | |
| 4126 disp(0x0); | |
| 4127 %} | |
| 4128 %} | |
| 4129 | |
| 4130 // Indirect Memory Plus Short Offset Operand | |
| 4131 operand indOffset8(any_RegP reg, immL8 off) | |
| 4132 %{ | |
| 4133 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 4134 match(AddP reg off); | |
| 4135 | |
| 4136 format %{ "[$reg + $off (8-bit)]" %} | |
| 4137 interface(MEMORY_INTER) %{ | |
| 4138 base($reg); | |
| 4139 index(0x4); | |
| 4140 scale(0x0); | |
| 4141 disp($off); | |
| 4142 %} | |
| 4143 %} | |
| 4144 | |
| 4145 // Indirect Memory Plus Long Offset Operand | |
| 4146 operand indOffset32(any_RegP reg, immL32 off) | |
| 4147 %{ | |
| 4148 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 4149 match(AddP reg off); | |
| 4150 | |
| 4151 format %{ "[$reg + $off (32-bit)]" %} | |
| 4152 interface(MEMORY_INTER) %{ | |
| 4153 base($reg); | |
| 4154 index(0x4); | |
| 4155 scale(0x0); | |
| 4156 disp($off); | |
| 4157 %} | |
| 4158 %} | |
| 4159 | |
| 4160 // Indirect Memory Plus Index Register Plus Offset Operand | |
| 4161 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off) | |
| 4162 %{ | |
| 4163 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 4164 match(AddP (AddP reg lreg) off); | |
| 4165 | |
| 4166 op_cost(10); | |
| 4167 format %{"[$reg + $off + $lreg]" %} | |
| 4168 interface(MEMORY_INTER) %{ | |
| 4169 base($reg); | |
| 4170 index($lreg); | |
| 4171 scale(0x0); | |
| 4172 disp($off); | |
| 4173 %} | |
| 4174 %} | |
| 4175 | |
| 4176 // Indirect Memory Plus Index Register Plus Offset Operand | |
| 4177 operand indIndex(any_RegP reg, rRegL lreg) | |
| 4178 %{ | |
| 4179 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 4180 match(AddP reg lreg); | |
| 4181 | |
| 4182 op_cost(10); | |
| 4183 format %{"[$reg + $lreg]" %} | |
| 4184 interface(MEMORY_INTER) %{ | |
| 4185 base($reg); | |
| 4186 index($lreg); | |
| 4187 scale(0x0); | |
| 4188 disp(0x0); | |
| 4189 %} | |
| 4190 %} | |
| 4191 | |
| 4192 // Indirect Memory Times Scale Plus Index Register | |
| 4193 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale) | |
| 4194 %{ | |
| 4195 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 4196 match(AddP reg (LShiftL lreg scale)); | |
| 4197 | |
| 4198 op_cost(10); | |
| 4199 format %{"[$reg + $lreg << $scale]" %} | |
| 4200 interface(MEMORY_INTER) %{ | |
| 4201 base($reg); | |
| 4202 index($lreg); | |
| 4203 scale($scale); | |
| 4204 disp(0x0); | |
| 4205 %} | |
| 4206 %} | |
| 4207 | |
| 4208 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand | |
| 4209 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale) | |
| 4210 %{ | |
| 4211 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 4212 match(AddP (AddP reg (LShiftL lreg scale)) off); | |
| 4213 | |
| 4214 op_cost(10); | |
| 4215 format %{"[$reg + $off + $lreg << $scale]" %} | |
| 4216 interface(MEMORY_INTER) %{ | |
| 4217 base($reg); | |
| 4218 index($lreg); | |
| 4219 scale($scale); | |
| 4220 disp($off); | |
| 4221 %} | |
| 4222 %} | |
| 4223 | |
| 4224 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand | |
| 4225 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale) | |
| 4226 %{ | |
| 4227 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 4228 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0); | |
| 4229 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off); | |
| 4230 | |
| 4231 op_cost(10); | |
| 4232 format %{"[$reg + $off + $idx << $scale]" %} | |
| 4233 interface(MEMORY_INTER) %{ | |
| 4234 base($reg); | |
| 4235 index($idx); | |
| 4236 scale($scale); | |
| 4237 disp($off); | |
| 4238 %} | |
| 4239 %} | |
| 4240 | |
|
642
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4241 // Indirect Narrow Oop Plus Offset Operand |
|
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4242 // Note: x86 architecture doesn't support "scale * index + offset" without a base |
|
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4243 // we can't free r12 even with Universe::narrow_oop_base() == NULL. |
|
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4244 operand indCompressedOopOffset(rRegN reg, immL32 off) %{ |
|
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4245 predicate(UseCompressedOops && (Universe::narrow_oop_shift() == Address::times_8)); |
|
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4246 constraint(ALLOC_IN_RC(ptr_reg)); |
|
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4247 match(AddP (DecodeN reg) off); |
|
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4248 |
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|
4249 op_cost(10); |
|
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|
4250 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %} |
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4251 interface(MEMORY_INTER) %{ |
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4252 base(0xc); // R12 |
|
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4253 index($reg); |
|
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4254 scale(0x3); |
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|
4255 disp($off); |
|
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|
4256 %} |
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4257 %} |
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|
4258 |
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4259 // Indirect Memory Operand |
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4260 operand indirectNarrow(rRegN reg) |
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4261 %{ |
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4262 predicate(Universe::narrow_oop_shift() == 0); |
|
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4263 constraint(ALLOC_IN_RC(ptr_reg)); |
|
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|
4264 match(DecodeN reg); |
|
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|
4265 |
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|
4266 format %{ "[$reg]" %} |
|
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4267 interface(MEMORY_INTER) %{ |
|
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4268 base($reg); |
|
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624
diff
changeset
|
4269 index(0x4); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4270 scale(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4271 disp(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4272 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4273 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4274 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4275 // Indirect Memory Plus Short Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4276 operand indOffset8Narrow(rRegN reg, immL8 off) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4277 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4278 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4279 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4280 match(AddP (DecodeN reg) off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4281 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4282 format %{ "[$reg + $off (8-bit)]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4283 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4284 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4285 index(0x4); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4286 scale(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4287 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4288 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4289 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4290 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4291 // Indirect Memory Plus Long Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4292 operand indOffset32Narrow(rRegN reg, immL32 off) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4293 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4294 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4295 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4296 match(AddP (DecodeN reg) off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4297 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4298 format %{ "[$reg + $off (32-bit)]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4299 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4300 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4301 index(0x4); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4302 scale(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4303 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4304 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4305 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4306 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4307 // Indirect Memory Plus Index Register Plus Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4308 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4309 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4310 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4311 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4312 match(AddP (AddP (DecodeN reg) lreg) off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4313 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4314 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4315 format %{"[$reg + $off + $lreg]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4316 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4317 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4318 index($lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4319 scale(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4320 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4321 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4322 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4323 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4324 // Indirect Memory Plus Index Register Plus Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4325 operand indIndexNarrow(rRegN reg, rRegL lreg) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4326 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4327 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4328 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4329 match(AddP (DecodeN reg) lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4330 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4331 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4332 format %{"[$reg + $lreg]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4333 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4334 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4335 index($lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4336 scale(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4337 disp(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4338 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4339 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4340 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4341 // Indirect Memory Times Scale Plus Index Register |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4342 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4343 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4344 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4345 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4346 match(AddP (DecodeN reg) (LShiftL lreg scale)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4347 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4348 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4349 format %{"[$reg + $lreg << $scale]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4350 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4351 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4352 index($lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4353 scale($scale); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4354 disp(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4355 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4356 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4357 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4358 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4359 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4360 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4361 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4362 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4363 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4364 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4365 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4366 format %{"[$reg + $off + $lreg << $scale]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4367 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4368 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4369 index($lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4370 scale($scale); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4371 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4372 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4373 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4374 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4375 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4376 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4377 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4378 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4379 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4380 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4381 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4382 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4383 format %{"[$reg + $off + $idx << $scale]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4384 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4385 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4386 index($idx); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4387 scale($scale); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4388 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4389 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4390 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4391 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4392 |
| 0 | 4393 //----------Special Memory Operands-------------------------------------------- |
| 4394 // Stack Slot Operand - This operand is used for loading and storing temporary | |
| 4395 // values on the stack where a match requires a value to | |
| 4396 // flow through memory. | |
| 4397 operand stackSlotP(sRegP reg) | |
| 4398 %{ | |
| 4399 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4400 // No match rule because this operand is only generated in matching | |
| 4401 | |
| 4402 format %{ "[$reg]" %} | |
| 4403 interface(MEMORY_INTER) %{ | |
| 4404 base(0x4); // RSP | |
| 4405 index(0x4); // No Index | |
| 4406 scale(0x0); // No Scale | |
| 4407 disp($reg); // Stack Offset | |
| 4408 %} | |
| 4409 %} | |
| 4410 | |
| 4411 operand stackSlotI(sRegI reg) | |
| 4412 %{ | |
| 4413 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4414 // No match rule because this operand is only generated in matching | |
| 4415 | |
| 4416 format %{ "[$reg]" %} | |
| 4417 interface(MEMORY_INTER) %{ | |
| 4418 base(0x4); // RSP | |
| 4419 index(0x4); // No Index | |
| 4420 scale(0x0); // No Scale | |
| 4421 disp($reg); // Stack Offset | |
| 4422 %} | |
| 4423 %} | |
| 4424 | |
| 4425 operand stackSlotF(sRegF reg) | |
| 4426 %{ | |
| 4427 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4428 // No match rule because this operand is only generated in matching | |
| 4429 | |
| 4430 format %{ "[$reg]" %} | |
| 4431 interface(MEMORY_INTER) %{ | |
| 4432 base(0x4); // RSP | |
| 4433 index(0x4); // No Index | |
| 4434 scale(0x0); // No Scale | |
| 4435 disp($reg); // Stack Offset | |
| 4436 %} | |
| 4437 %} | |
| 4438 | |
| 4439 operand stackSlotD(sRegD reg) | |
| 4440 %{ | |
| 4441 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4442 // No match rule because this operand is only generated in matching | |
| 4443 | |
| 4444 format %{ "[$reg]" %} | |
| 4445 interface(MEMORY_INTER) %{ | |
| 4446 base(0x4); // RSP | |
| 4447 index(0x4); // No Index | |
| 4448 scale(0x0); // No Scale | |
| 4449 disp($reg); // Stack Offset | |
| 4450 %} | |
| 4451 %} | |
| 4452 operand stackSlotL(sRegL reg) | |
| 4453 %{ | |
| 4454 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4455 // No match rule because this operand is only generated in matching | |
| 4456 | |
| 4457 format %{ "[$reg]" %} | |
| 4458 interface(MEMORY_INTER) %{ | |
| 4459 base(0x4); // RSP | |
| 4460 index(0x4); // No Index | |
| 4461 scale(0x0); // No Scale | |
| 4462 disp($reg); // Stack Offset | |
| 4463 %} | |
| 4464 %} | |
| 4465 | |
| 4466 //----------Conditional Branch Operands---------------------------------------- | |
| 4467 // Comparison Op - This is the operation of the comparison, and is limited to | |
| 4468 // the following set of codes: | |
| 4469 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) | |
| 4470 // | |
| 4471 // Other attributes of the comparison, such as unsignedness, are specified | |
| 4472 // by the comparison instruction that sets a condition code flags register. | |
| 4473 // That result is represented by a flags operand whose subtype is appropriate | |
| 4474 // to the unsignedness (etc.) of the comparison. | |
| 4475 // | |
| 4476 // Later, the instruction which matches both the Comparison Op (a Bool) and | |
| 4477 // the flags (produced by the Cmp) specifies the coding of the comparison op | |
| 4478 // by matching a specific subtype of Bool operand below, such as cmpOpU. | |
| 4479 | |
| 4480 // Comparision Code | |
| 4481 operand cmpOp() | |
| 4482 %{ | |
| 4483 match(Bool); | |
| 4484 | |
| 4485 format %{ "" %} | |
| 4486 interface(COND_INTER) %{ | |
|
415
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|
4487 equal(0x4, "e"); |
|
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|
4488 not_equal(0x5, "ne"); |
|
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|
4489 less(0xC, "l"); |
|
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|
4490 greater_equal(0xD, "ge"); |
|
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|
4491 less_equal(0xE, "le"); |
|
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|
4492 greater(0xF, "g"); |
| 0 | 4493 %} |
| 4494 %} | |
| 4495 | |
| 4496 // Comparison Code, unsigned compare. Used by FP also, with | |
| 4497 // C2 (unordered) turned into GT or LT already. The other bits | |
| 4498 // C0 and C3 are turned into Carry & Zero flags. | |
| 4499 operand cmpOpU() | |
| 4500 %{ | |
| 4501 match(Bool); | |
| 4502 | |
| 4503 format %{ "" %} | |
| 4504 interface(COND_INTER) %{ | |
|
415
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|
4505 equal(0x4, "e"); |
|
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|
4506 not_equal(0x5, "ne"); |
|
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|
4507 less(0x2, "b"); |
|
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|
4508 greater_equal(0x3, "nb"); |
|
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|
4509 less_equal(0x6, "be"); |
|
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changeset
|
4510 greater(0x7, "nbe"); |
|
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|
4511 %} |
|
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|
4512 %} |
|
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|
4513 |
|
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changeset
|
4514 |
|
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|
4515 // Floating comparisons that don't require any fixup for the unordered case |
|
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|
4516 operand cmpOpUCF() %{ |
|
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|
4517 match(Bool); |
|
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|
4518 predicate(n->as_Bool()->_test._test == BoolTest::lt || |
|
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|
4519 n->as_Bool()->_test._test == BoolTest::ge || |
|
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|
4520 n->as_Bool()->_test._test == BoolTest::le || |
|
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|
4521 n->as_Bool()->_test._test == BoolTest::gt); |
|
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diff
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|
4522 format %{ "" %} |
|
4d9884b01ba6
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diff
changeset
|
4523 interface(COND_INTER) %{ |
|
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diff
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|
4524 equal(0x4, "e"); |
|
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diff
changeset
|
4525 not_equal(0x5, "ne"); |
|
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diff
changeset
|
4526 less(0x2, "b"); |
|
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diff
changeset
|
4527 greater_equal(0x3, "nb"); |
|
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diff
changeset
|
4528 less_equal(0x6, "be"); |
|
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diff
changeset
|
4529 greater(0x7, "nbe"); |
|
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|
4530 %} |
|
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|
4531 %} |
|
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|
4532 |
|
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|
4533 |
|
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|
4534 // Floating comparisons that can be fixed up with extra conditional jumps |
|
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|
4535 operand cmpOpUCF2() %{ |
|
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|
4536 match(Bool); |
|
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changeset
|
4537 predicate(n->as_Bool()->_test._test == BoolTest::ne || |
|
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|
4538 n->as_Bool()->_test._test == BoolTest::eq); |
|
4d9884b01ba6
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changeset
|
4539 format %{ "" %} |
|
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changeset
|
4540 interface(COND_INTER) %{ |
|
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|
4541 equal(0x4, "e"); |
|
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|
4542 not_equal(0x5, "ne"); |
|
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|
4543 less(0x2, "b"); |
|
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|
4544 greater_equal(0x3, "nb"); |
|
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|
4545 less_equal(0x6, "be"); |
|
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|
4546 greater(0x7, "nbe"); |
| 0 | 4547 %} |
| 4548 %} | |
| 4549 | |
| 4550 | |
| 4551 //----------OPERAND CLASSES---------------------------------------------------- | |
| 4552 // Operand Classes are groups of operands that are used as to simplify | |
| 605 | 4553 // instruction definitions by not requiring the AD writer to specify separate |
| 0 | 4554 // instructions for every form of operand when the instruction accepts |
| 4555 // multiple operand types with the same basic encoding and format. The classic | |
| 4556 // case of this is memory operands. | |
| 4557 | |
| 4558 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex, | |
|
113
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|
4559 indIndexScale, indIndexScaleOffset, indPosIndexScaleOffset, |
|
642
660978a2a31a
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kvn
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624
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|
4560 indCompressedOopOffset, |
|
660978a2a31a
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|
4561 indirectNarrow, indOffset8Narrow, indOffset32Narrow, |
|
660978a2a31a
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|
4562 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow, |
|
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|
4563 indIndexScaleOffsetNarrow, indPosIndexScaleOffsetNarrow); |
| 0 | 4564 |
| 4565 //----------PIPELINE----------------------------------------------------------- | |
| 4566 // Rules which define the behavior of the target architectures pipeline. | |
| 4567 pipeline %{ | |
| 4568 | |
| 4569 //----------ATTRIBUTES--------------------------------------------------------- | |
| 4570 attributes %{ | |
| 4571 variable_size_instructions; // Fixed size instructions | |
| 4572 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle | |
| 4573 instruction_unit_size = 1; // An instruction is 1 bytes long | |
| 4574 instruction_fetch_unit_size = 16; // The processor fetches one line | |
| 4575 instruction_fetch_units = 1; // of 16 bytes | |
| 4576 | |
| 4577 // List of nop instructions | |
| 4578 nops( MachNop ); | |
| 4579 %} | |
| 4580 | |
| 4581 //----------RESOURCES---------------------------------------------------------- | |
| 4582 // Resources are the functional units available to the machine | |
| 4583 | |
| 4584 // Generic P2/P3 pipeline | |
| 4585 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of | |
| 4586 // 3 instructions decoded per cycle. | |
| 4587 // 2 load/store ops per cycle, 1 branch, 1 FPU, | |
| 4588 // 3 ALU op, only ALU0 handles mul instructions. | |
| 4589 resources( D0, D1, D2, DECODE = D0 | D1 | D2, | |
| 4590 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2, | |
| 4591 BR, FPU, | |
| 4592 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2); | |
| 4593 | |
| 4594 //----------PIPELINE DESCRIPTION----------------------------------------------- | |
| 4595 // Pipeline Description specifies the stages in the machine's pipeline | |
| 4596 | |
| 4597 // Generic P2/P3 pipeline | |
| 4598 pipe_desc(S0, S1, S2, S3, S4, S5); | |
| 4599 | |
| 4600 //----------PIPELINE CLASSES--------------------------------------------------- | |
| 4601 // Pipeline Classes describe the stages in which input and output are | |
| 4602 // referenced by the hardware pipeline. | |
| 4603 | |
| 4604 // Naming convention: ialu or fpu | |
| 4605 // Then: _reg | |
| 4606 // Then: _reg if there is a 2nd register | |
| 4607 // Then: _long if it's a pair of instructions implementing a long | |
| 4608 // Then: _fat if it requires the big decoder | |
| 4609 // Or: _mem if it requires the big decoder and a memory unit. | |
| 4610 | |
| 4611 // Integer ALU reg operation | |
| 4612 pipe_class ialu_reg(rRegI dst) | |
| 4613 %{ | |
| 4614 single_instruction; | |
| 4615 dst : S4(write); | |
| 4616 dst : S3(read); | |
| 4617 DECODE : S0; // any decoder | |
| 4618 ALU : S3; // any alu | |
| 4619 %} | |
| 4620 | |
| 4621 // Long ALU reg operation | |
| 4622 pipe_class ialu_reg_long(rRegL dst) | |
| 4623 %{ | |
| 4624 instruction_count(2); | |
| 4625 dst : S4(write); | |
| 4626 dst : S3(read); | |
| 4627 DECODE : S0(2); // any 2 decoders | |
| 4628 ALU : S3(2); // both alus | |
| 4629 %} | |
| 4630 | |
| 4631 // Integer ALU reg operation using big decoder | |
| 4632 pipe_class ialu_reg_fat(rRegI dst) | |
| 4633 %{ | |
| 4634 single_instruction; | |
| 4635 dst : S4(write); | |
| 4636 dst : S3(read); | |
| 4637 D0 : S0; // big decoder only | |
| 4638 ALU : S3; // any alu | |
| 4639 %} | |
| 4640 | |
| 4641 // Long ALU reg operation using big decoder | |
| 4642 pipe_class ialu_reg_long_fat(rRegL dst) | |
| 4643 %{ | |
| 4644 instruction_count(2); | |
| 4645 dst : S4(write); | |
| 4646 dst : S3(read); | |
| 4647 D0 : S0(2); // big decoder only; twice | |
| 4648 ALU : S3(2); // any 2 alus | |
| 4649 %} | |
| 4650 | |
| 4651 // Integer ALU reg-reg operation | |
| 4652 pipe_class ialu_reg_reg(rRegI dst, rRegI src) | |
| 4653 %{ | |
| 4654 single_instruction; | |
| 4655 dst : S4(write); | |
| 4656 src : S3(read); | |
| 4657 DECODE : S0; // any decoder | |
| 4658 ALU : S3; // any alu | |
| 4659 %} | |
| 4660 | |
| 4661 // Long ALU reg-reg operation | |
| 4662 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src) | |
| 4663 %{ | |
| 4664 instruction_count(2); | |
| 4665 dst : S4(write); | |
| 4666 src : S3(read); | |
| 4667 DECODE : S0(2); // any 2 decoders | |
| 4668 ALU : S3(2); // both alus | |
| 4669 %} | |
| 4670 | |
| 4671 // Integer ALU reg-reg operation | |
| 4672 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) | |
| 4673 %{ | |
| 4674 single_instruction; | |
| 4675 dst : S4(write); | |
| 4676 src : S3(read); | |
| 4677 D0 : S0; // big decoder only | |
| 4678 ALU : S3; // any alu | |
| 4679 %} | |
| 4680 | |
| 4681 // Long ALU reg-reg operation | |
| 4682 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src) | |
| 4683 %{ | |
| 4684 instruction_count(2); | |
| 4685 dst : S4(write); | |
| 4686 src : S3(read); | |
| 4687 D0 : S0(2); // big decoder only; twice | |
| 4688 ALU : S3(2); // both alus | |
| 4689 %} | |
| 4690 | |
| 4691 // Integer ALU reg-mem operation | |
| 4692 pipe_class ialu_reg_mem(rRegI dst, memory mem) | |
| 4693 %{ | |
| 4694 single_instruction; | |
| 4695 dst : S5(write); | |
| 4696 mem : S3(read); | |
| 4697 D0 : S0; // big decoder only | |
| 4698 ALU : S4; // any alu | |
| 4699 MEM : S3; // any mem | |
| 4700 %} | |
| 4701 | |
| 4702 // Integer mem operation (prefetch) | |
| 4703 pipe_class ialu_mem(memory mem) | |
| 4704 %{ | |
| 4705 single_instruction; | |
| 4706 mem : S3(read); | |
| 4707 D0 : S0; // big decoder only | |
| 4708 MEM : S3; // any mem | |
| 4709 %} | |
| 4710 | |
| 4711 // Integer Store to Memory | |
| 4712 pipe_class ialu_mem_reg(memory mem, rRegI src) | |
| 4713 %{ | |
| 4714 single_instruction; | |
| 4715 mem : S3(read); | |
| 4716 src : S5(read); | |
| 4717 D0 : S0; // big decoder only | |
| 4718 ALU : S4; // any alu | |
| 4719 MEM : S3; | |
| 4720 %} | |
| 4721 | |
| 4722 // // Long Store to Memory | |
| 4723 // pipe_class ialu_mem_long_reg(memory mem, rRegL src) | |
| 4724 // %{ | |
| 4725 // instruction_count(2); | |
| 4726 // mem : S3(read); | |
| 4727 // src : S5(read); | |
| 4728 // D0 : S0(2); // big decoder only; twice | |
| 4729 // ALU : S4(2); // any 2 alus | |
| 4730 // MEM : S3(2); // Both mems | |
| 4731 // %} | |
| 4732 | |
| 4733 // Integer Store to Memory | |
| 4734 pipe_class ialu_mem_imm(memory mem) | |
| 4735 %{ | |
| 4736 single_instruction; | |
| 4737 mem : S3(read); | |
| 4738 D0 : S0; // big decoder only | |
| 4739 ALU : S4; // any alu | |
| 4740 MEM : S3; | |
| 4741 %} | |
| 4742 | |
| 4743 // Integer ALU0 reg-reg operation | |
| 4744 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) | |
| 4745 %{ | |
| 4746 single_instruction; | |
| 4747 dst : S4(write); | |
| 4748 src : S3(read); | |
| 4749 D0 : S0; // Big decoder only | |
| 4750 ALU0 : S3; // only alu0 | |
| 4751 %} | |
| 4752 | |
| 4753 // Integer ALU0 reg-mem operation | |
| 4754 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) | |
| 4755 %{ | |
| 4756 single_instruction; | |
| 4757 dst : S5(write); | |
| 4758 mem : S3(read); | |
| 4759 D0 : S0; // big decoder only | |
| 4760 ALU0 : S4; // ALU0 only | |
| 4761 MEM : S3; // any mem | |
| 4762 %} | |
| 4763 | |
| 4764 // Integer ALU reg-reg operation | |
| 4765 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2) | |
| 4766 %{ | |
| 4767 single_instruction; | |
| 4768 cr : S4(write); | |
| 4769 src1 : S3(read); | |
| 4770 src2 : S3(read); | |
| 4771 DECODE : S0; // any decoder | |
| 4772 ALU : S3; // any alu | |
| 4773 %} | |
| 4774 | |
| 4775 // Integer ALU reg-imm operation | |
| 4776 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1) | |
| 4777 %{ | |
| 4778 single_instruction; | |
| 4779 cr : S4(write); | |
| 4780 src1 : S3(read); | |
| 4781 DECODE : S0; // any decoder | |
| 4782 ALU : S3; // any alu | |
| 4783 %} | |
| 4784 | |
| 4785 // Integer ALU reg-mem operation | |
| 4786 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2) | |
| 4787 %{ | |
| 4788 single_instruction; | |
| 4789 cr : S4(write); | |
| 4790 src1 : S3(read); | |
| 4791 src2 : S3(read); | |
| 4792 D0 : S0; // big decoder only | |
| 4793 ALU : S4; // any alu | |
| 4794 MEM : S3; | |
| 4795 %} | |
| 4796 | |
| 4797 // Conditional move reg-reg | |
| 4798 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y) | |
| 4799 %{ | |
| 4800 instruction_count(4); | |
| 4801 y : S4(read); | |
| 4802 q : S3(read); | |
| 4803 p : S3(read); | |
| 4804 DECODE : S0(4); // any decoder | |
| 4805 %} | |
| 4806 | |
| 4807 // Conditional move reg-reg | |
| 4808 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr) | |
| 4809 %{ | |
| 4810 single_instruction; | |
| 4811 dst : S4(write); | |
| 4812 src : S3(read); | |
| 4813 cr : S3(read); | |
| 4814 DECODE : S0; // any decoder | |
| 4815 %} | |
| 4816 | |
| 4817 // Conditional move reg-mem | |
| 4818 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src) | |
| 4819 %{ | |
| 4820 single_instruction; | |
| 4821 dst : S4(write); | |
| 4822 src : S3(read); | |
| 4823 cr : S3(read); | |
| 4824 DECODE : S0; // any decoder | |
| 4825 MEM : S3; | |
| 4826 %} | |
| 4827 | |
| 4828 // Conditional move reg-reg long | |
| 4829 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src) | |
| 4830 %{ | |
| 4831 single_instruction; | |
| 4832 dst : S4(write); | |
| 4833 src : S3(read); | |
| 4834 cr : S3(read); | |
| 4835 DECODE : S0(2); // any 2 decoders | |
| 4836 %} | |
| 4837 | |
| 4838 // XXX | |
| 4839 // // Conditional move double reg-reg | |
| 4840 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src) | |
| 4841 // %{ | |
| 4842 // single_instruction; | |
| 4843 // dst : S4(write); | |
| 4844 // src : S3(read); | |
| 4845 // cr : S3(read); | |
| 4846 // DECODE : S0; // any decoder | |
| 4847 // %} | |
| 4848 | |
| 4849 // Float reg-reg operation | |
| 4850 pipe_class fpu_reg(regD dst) | |
| 4851 %{ | |
| 4852 instruction_count(2); | |
| 4853 dst : S3(read); | |
| 4854 DECODE : S0(2); // any 2 decoders | |
| 4855 FPU : S3; | |
| 4856 %} | |
| 4857 | |
| 4858 // Float reg-reg operation | |
| 4859 pipe_class fpu_reg_reg(regD dst, regD src) | |
| 4860 %{ | |
| 4861 instruction_count(2); | |
| 4862 dst : S4(write); | |
| 4863 src : S3(read); | |
| 4864 DECODE : S0(2); // any 2 decoders | |
| 4865 FPU : S3; | |
| 4866 %} | |
| 4867 | |
| 4868 // Float reg-reg operation | |
| 4869 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2) | |
| 4870 %{ | |
| 4871 instruction_count(3); | |
| 4872 dst : S4(write); | |
| 4873 src1 : S3(read); | |
| 4874 src2 : S3(read); | |
| 4875 DECODE : S0(3); // any 3 decoders | |
| 4876 FPU : S3(2); | |
| 4877 %} | |
| 4878 | |
| 4879 // Float reg-reg operation | |
| 4880 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3) | |
| 4881 %{ | |
| 4882 instruction_count(4); | |
| 4883 dst : S4(write); | |
| 4884 src1 : S3(read); | |
| 4885 src2 : S3(read); | |
| 4886 src3 : S3(read); | |
| 4887 DECODE : S0(4); // any 3 decoders | |
| 4888 FPU : S3(2); | |
| 4889 %} | |
| 4890 | |
| 4891 // Float reg-reg operation | |
| 4892 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3) | |
| 4893 %{ | |
| 4894 instruction_count(4); | |
| 4895 dst : S4(write); | |
| 4896 src1 : S3(read); | |
| 4897 src2 : S3(read); | |
| 4898 src3 : S3(read); | |
| 4899 DECODE : S1(3); // any 3 decoders | |
| 4900 D0 : S0; // Big decoder only | |
| 4901 FPU : S3(2); | |
| 4902 MEM : S3; | |
| 4903 %} | |
| 4904 | |
| 4905 // Float reg-mem operation | |
| 4906 pipe_class fpu_reg_mem(regD dst, memory mem) | |
| 4907 %{ | |
| 4908 instruction_count(2); | |
| 4909 dst : S5(write); | |
| 4910 mem : S3(read); | |
| 4911 D0 : S0; // big decoder only | |
| 4912 DECODE : S1; // any decoder for FPU POP | |
| 4913 FPU : S4; | |
| 4914 MEM : S3; // any mem | |
| 4915 %} | |
| 4916 | |
| 4917 // Float reg-mem operation | |
| 4918 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem) | |
| 4919 %{ | |
| 4920 instruction_count(3); | |
| 4921 dst : S5(write); | |
| 4922 src1 : S3(read); | |
| 4923 mem : S3(read); | |
| 4924 D0 : S0; // big decoder only | |
| 4925 DECODE : S1(2); // any decoder for FPU POP | |
| 4926 FPU : S4; | |
| 4927 MEM : S3; // any mem | |
| 4928 %} | |
| 4929 | |
| 4930 // Float mem-reg operation | |
| 4931 pipe_class fpu_mem_reg(memory mem, regD src) | |
| 4932 %{ | |
| 4933 instruction_count(2); | |
| 4934 src : S5(read); | |
| 4935 mem : S3(read); | |
| 4936 DECODE : S0; // any decoder for FPU PUSH | |
| 4937 D0 : S1; // big decoder only | |
| 4938 FPU : S4; | |
| 4939 MEM : S3; // any mem | |
| 4940 %} | |
| 4941 | |
| 4942 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2) | |
| 4943 %{ | |
| 4944 instruction_count(3); | |
| 4945 src1 : S3(read); | |
| 4946 src2 : S3(read); | |
| 4947 mem : S3(read); | |
| 4948 DECODE : S0(2); // any decoder for FPU PUSH | |
| 4949 D0 : S1; // big decoder only | |
| 4950 FPU : S4; | |
| 4951 MEM : S3; // any mem | |
| 4952 %} | |
| 4953 | |
| 4954 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2) | |
| 4955 %{ | |
| 4956 instruction_count(3); | |
| 4957 src1 : S3(read); | |
| 4958 src2 : S3(read); | |
| 4959 mem : S4(read); | |
| 4960 DECODE : S0; // any decoder for FPU PUSH | |
| 4961 D0 : S0(2); // big decoder only | |
| 4962 FPU : S4; | |
| 4963 MEM : S3(2); // any mem | |
| 4964 %} | |
| 4965 | |
| 4966 pipe_class fpu_mem_mem(memory dst, memory src1) | |
| 4967 %{ | |
| 4968 instruction_count(2); | |
| 4969 src1 : S3(read); | |
| 4970 dst : S4(read); | |
| 4971 D0 : S0(2); // big decoder only | |
| 4972 MEM : S3(2); // any mem | |
| 4973 %} | |
| 4974 | |
| 4975 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) | |
| 4976 %{ | |
| 4977 instruction_count(3); | |
| 4978 src1 : S3(read); | |
| 4979 src2 : S3(read); | |
| 4980 dst : S4(read); | |
| 4981 D0 : S0(3); // big decoder only | |
| 4982 FPU : S4; | |
| 4983 MEM : S3(3); // any mem | |
| 4984 %} | |
| 4985 | |
| 4986 pipe_class fpu_mem_reg_con(memory mem, regD src1) | |
| 4987 %{ | |
| 4988 instruction_count(3); | |
| 4989 src1 : S4(read); | |
| 4990 mem : S4(read); | |
| 4991 DECODE : S0; // any decoder for FPU PUSH | |
| 4992 D0 : S0(2); // big decoder only | |
| 4993 FPU : S4; | |
| 4994 MEM : S3(2); // any mem | |
| 4995 %} | |
| 4996 | |
| 4997 // Float load constant | |
| 4998 pipe_class fpu_reg_con(regD dst) | |
| 4999 %{ | |
| 5000 instruction_count(2); | |
| 5001 dst : S5(write); | |
| 5002 D0 : S0; // big decoder only for the load | |
| 5003 DECODE : S1; // any decoder for FPU POP | |
| 5004 FPU : S4; | |
| 5005 MEM : S3; // any mem | |
| 5006 %} | |
| 5007 | |
| 5008 // Float load constant | |
| 5009 pipe_class fpu_reg_reg_con(regD dst, regD src) | |
| 5010 %{ | |
| 5011 instruction_count(3); | |
| 5012 dst : S5(write); | |
| 5013 src : S3(read); | |
| 5014 D0 : S0; // big decoder only for the load | |
| 5015 DECODE : S1(2); // any decoder for FPU POP | |
| 5016 FPU : S4; | |
| 5017 MEM : S3; // any mem | |
| 5018 %} | |
| 5019 | |
| 5020 // UnConditional branch | |
| 5021 pipe_class pipe_jmp(label labl) | |
| 5022 %{ | |
| 5023 single_instruction; | |
| 5024 BR : S3; | |
| 5025 %} | |
| 5026 | |
| 5027 // Conditional branch | |
| 5028 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl) | |
| 5029 %{ | |
| 5030 single_instruction; | |
| 5031 cr : S1(read); | |
| 5032 BR : S3; | |
| 5033 %} | |
| 5034 | |
| 5035 // Allocation idiom | |
| 5036 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr) | |
| 5037 %{ | |
| 5038 instruction_count(1); force_serialization; | |
| 5039 fixed_latency(6); | |
| 5040 heap_ptr : S3(read); | |
| 5041 DECODE : S0(3); | |
| 5042 D0 : S2; | |
| 5043 MEM : S3; | |
| 5044 ALU : S3(2); | |
| 5045 dst : S5(write); | |
| 5046 BR : S5; | |
| 5047 %} | |
| 5048 | |
| 5049 // Generic big/slow expanded idiom | |
| 5050 pipe_class pipe_slow() | |
| 5051 %{ | |
| 5052 instruction_count(10); multiple_bundles; force_serialization; | |
| 5053 fixed_latency(100); | |
| 5054 D0 : S0(2); | |
| 5055 MEM : S3(2); | |
| 5056 %} | |
| 5057 | |
| 5058 // The real do-nothing guy | |
| 5059 pipe_class empty() | |
| 5060 %{ | |
| 5061 instruction_count(0); | |
| 5062 %} | |
| 5063 | |
| 5064 // Define the class for the Nop node | |
| 5065 define | |
| 5066 %{ | |
| 5067 MachNop = empty; | |
| 5068 %} | |
| 5069 | |
| 5070 %} | |
| 5071 | |
| 5072 //----------INSTRUCTIONS------------------------------------------------------- | |
| 5073 // | |
| 5074 // match -- States which machine-independent subtree may be replaced | |
| 5075 // by this instruction. | |
| 5076 // ins_cost -- The estimated cost of this instruction is used by instruction | |
| 5077 // selection to identify a minimum cost tree of machine | |
| 5078 // instructions that matches a tree of machine-independent | |
| 5079 // instructions. | |
| 5080 // format -- A string providing the disassembly for this instruction. | |
| 5081 // The value of an instruction's operand may be inserted | |
| 5082 // by referring to it with a '$' prefix. | |
| 5083 // opcode -- Three instruction opcodes may be provided. These are referred | |
| 5084 // to within an encode class as $primary, $secondary, and $tertiary | |
| 5085 // rrspectively. The primary opcode is commonly used to | |
| 5086 // indicate the type of machine instruction, while secondary | |
| 5087 // and tertiary are often used for prefix options or addressing | |
| 5088 // modes. | |
| 5089 // ins_encode -- A list of encode classes with parameters. The encode class | |
| 5090 // name must have been defined in an 'enc_class' specification | |
| 5091 // in the encode section of the architecture description. | |
| 5092 | |
| 5093 | |
| 5094 //----------Load/Store/Move Instructions--------------------------------------- | |
| 5095 //----------Load Instructions-------------------------------------------------- | |
| 5096 | |
| 5097 // Load Byte (8 bit signed) | |
| 5098 instruct loadB(rRegI dst, memory mem) | |
| 5099 %{ | |
| 5100 match(Set dst (LoadB mem)); | |
| 5101 | |
| 5102 ins_cost(125); | |
| 5103 format %{ "movsbl $dst, $mem\t# byte" %} | |
| 624 | 5104 |
| 5105 ins_encode %{ | |
| 5106 __ movsbl($dst$$Register, $mem$$Address); | |
| 5107 %} | |
| 5108 | |
| 0 | 5109 ins_pipe(ialu_reg_mem); |
| 5110 %} | |
| 5111 | |
| 624 | 5112 // Load Byte (8 bit signed) into Long Register |
| 5113 instruct loadB2L(rRegL dst, memory mem) | |
| 5114 %{ | |
| 5115 match(Set dst (ConvI2L (LoadB mem))); | |
| 5116 | |
| 5117 ins_cost(125); | |
| 5118 format %{ "movsbq $dst, $mem\t# byte -> long" %} | |
| 5119 | |
| 5120 ins_encode %{ | |
| 5121 __ movsbq($dst$$Register, $mem$$Address); | |
| 5122 %} | |
| 5123 | |
| 5124 ins_pipe(ialu_reg_mem); | |
| 5125 %} | |
| 5126 | |
| 5127 // Load Unsigned Byte (8 bit UNsigned) | |
| 5128 instruct loadUB(rRegI dst, memory mem) | |
| 5129 %{ | |
| 5130 match(Set dst (LoadUB mem)); | |
| 0 | 5131 |
| 5132 ins_cost(125); | |
| 5133 format %{ "movzbl $dst, $mem\t# ubyte" %} | |
| 624 | 5134 |
| 5135 ins_encode %{ | |
| 5136 __ movzbl($dst$$Register, $mem$$Address); | |
| 5137 %} | |
| 5138 | |
| 0 | 5139 ins_pipe(ialu_reg_mem); |
| 5140 %} | |
| 5141 | |
| 624 | 5142 // Load Unsigned Byte (8 bit UNsigned) into Long Register |
| 5143 instruct loadUB2L(rRegL dst, memory mem) | |
| 5144 %{ | |
| 5145 match(Set dst (ConvI2L (LoadUB mem))); | |
| 5146 | |
| 5147 ins_cost(125); | |
| 5148 format %{ "movzbq $dst, $mem\t# ubyte -> long" %} | |
| 5149 | |
| 5150 ins_encode %{ | |
| 5151 __ movzbq($dst$$Register, $mem$$Address); | |
| 5152 %} | |
| 5153 | |
| 5154 ins_pipe(ialu_reg_mem); | |
| 5155 %} | |
| 0 | 5156 |
| 824 | 5157 // Load Unsigned Byte (8 bit UNsigned) with a 8-bit mask into Long Register |
| 5158 instruct loadUB2L_immI8(rRegL dst, memory mem, immI8 mask, rFlagsReg cr) %{ | |
| 5159 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); | |
| 5160 effect(KILL cr); | |
| 5161 | |
| 5162 format %{ "movzbq $dst, $mem\t# ubyte & 8-bit mask -> long\n\t" | |
| 5163 "andl $dst, $mask" %} | |
| 5164 ins_encode %{ | |
| 5165 Register Rdst = $dst$$Register; | |
| 5166 __ movzbq(Rdst, $mem$$Address); | |
| 5167 __ andl(Rdst, $mask$$constant); | |
| 5168 %} | |
| 5169 ins_pipe(ialu_reg_mem); | |
| 5170 %} | |
| 5171 | |
| 0 | 5172 // Load Short (16 bit signed) |
| 5173 instruct loadS(rRegI dst, memory mem) | |
| 5174 %{ | |
| 5175 match(Set dst (LoadS mem)); | |
| 5176 | |
| 624 | 5177 ins_cost(125); |
| 0 | 5178 format %{ "movswl $dst, $mem\t# short" %} |
| 624 | 5179 |
| 5180 ins_encode %{ | |
| 5181 __ movswl($dst$$Register, $mem$$Address); | |
| 5182 %} | |
| 5183 | |
| 0 | 5184 ins_pipe(ialu_reg_mem); |
| 5185 %} | |
| 5186 | |
| 785 | 5187 // Load Short (16 bit signed) to Byte (8 bit signed) |
| 5188 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{ | |
| 5189 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); | |
| 5190 | |
| 5191 ins_cost(125); | |
| 5192 format %{ "movsbl $dst, $mem\t# short -> byte" %} | |
| 5193 ins_encode %{ | |
| 5194 __ movsbl($dst$$Register, $mem$$Address); | |
| 5195 %} | |
| 5196 ins_pipe(ialu_reg_mem); | |
| 5197 %} | |
| 5198 | |
| 624 | 5199 // Load Short (16 bit signed) into Long Register |
| 5200 instruct loadS2L(rRegL dst, memory mem) | |
| 5201 %{ | |
| 5202 match(Set dst (ConvI2L (LoadS mem))); | |
| 5203 | |
| 5204 ins_cost(125); | |
| 5205 format %{ "movswq $dst, $mem\t# short -> long" %} | |
| 5206 | |
| 5207 ins_encode %{ | |
| 5208 __ movswq($dst$$Register, $mem$$Address); | |
| 5209 %} | |
| 5210 | |
| 5211 ins_pipe(ialu_reg_mem); | |
| 5212 %} | |
| 0 | 5213 |
|
558
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|
5214 // Load Unsigned Short/Char (16 bit UNsigned) |
|
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
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diff
changeset
|
5215 instruct loadUS(rRegI dst, memory mem) |
|
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents:
420
diff
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|
5216 %{ |
|
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
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parents:
420
diff
changeset
|
5217 match(Set dst (LoadUS mem)); |
| 0 | 5218 |
| 5219 ins_cost(125); | |
|
558
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6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
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parents:
420
diff
changeset
|
5220 format %{ "movzwl $dst, $mem\t# ushort/char" %} |
| 624 | 5221 |
| 5222 ins_encode %{ | |
| 5223 __ movzwl($dst$$Register, $mem$$Address); | |
| 5224 %} | |
| 5225 | |
| 0 | 5226 ins_pipe(ialu_reg_mem); |
| 5227 %} | |
| 5228 | |
| 785 | 5229 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) |
| 5230 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{ | |
| 5231 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); | |
| 5232 | |
| 5233 ins_cost(125); | |
| 5234 format %{ "movsbl $dst, $mem\t# ushort -> byte" %} | |
| 5235 ins_encode %{ | |
| 5236 __ movsbl($dst$$Register, $mem$$Address); | |
| 5237 %} | |
| 5238 ins_pipe(ialu_reg_mem); | |
| 5239 %} | |
| 5240 | |
| 624 | 5241 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register |
| 5242 instruct loadUS2L(rRegL dst, memory mem) | |
| 5243 %{ | |
| 5244 match(Set dst (ConvI2L (LoadUS mem))); | |
| 5245 | |
| 5246 ins_cost(125); | |
| 5247 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %} | |
| 5248 | |
| 5249 ins_encode %{ | |
| 5250 __ movzwq($dst$$Register, $mem$$Address); | |
| 5251 %} | |
| 5252 | |
| 5253 ins_pipe(ialu_reg_mem); | |
| 5254 %} | |
| 0 | 5255 |
| 824 | 5256 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register |
| 5257 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{ | |
| 5258 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5259 | |
| 5260 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %} | |
| 5261 ins_encode %{ | |
| 5262 __ movzbq($dst$$Register, $mem$$Address); | |
| 5263 %} | |
| 5264 ins_pipe(ialu_reg_mem); | |
| 5265 %} | |
| 5266 | |
| 5267 // Load Unsigned Short/Char (16 bit UNsigned) with mask into Long Register | |
| 5268 instruct loadUS2L_immI16(rRegL dst, memory mem, immI16 mask, rFlagsReg cr) %{ | |
| 5269 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5270 effect(KILL cr); | |
| 5271 | |
| 5272 format %{ "movzwq $dst, $mem\t# ushort/char & 16-bit mask -> long\n\t" | |
| 5273 "andl $dst, $mask" %} | |
| 5274 ins_encode %{ | |
| 5275 Register Rdst = $dst$$Register; | |
| 5276 __ movzwq(Rdst, $mem$$Address); | |
| 5277 __ andl(Rdst, $mask$$constant); | |
| 5278 %} | |
| 5279 ins_pipe(ialu_reg_mem); | |
| 5280 %} | |
| 5281 | |
| 0 | 5282 // Load Integer |
| 5283 instruct loadI(rRegI dst, memory mem) | |
| 5284 %{ | |
| 5285 match(Set dst (LoadI mem)); | |
| 5286 | |
| 624 | 5287 ins_cost(125); |
| 0 | 5288 format %{ "movl $dst, $mem\t# int" %} |
| 624 | 5289 |
| 5290 ins_encode %{ | |
| 5291 __ movl($dst$$Register, $mem$$Address); | |
| 5292 %} | |
| 5293 | |
| 5294 ins_pipe(ialu_reg_mem); | |
| 5295 %} | |
| 5296 | |
| 785 | 5297 // Load Integer (32 bit signed) to Byte (8 bit signed) |
| 5298 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{ | |
| 5299 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); | |
| 5300 | |
| 5301 ins_cost(125); | |
| 5302 format %{ "movsbl $dst, $mem\t# int -> byte" %} | |
| 5303 ins_encode %{ | |
| 5304 __ movsbl($dst$$Register, $mem$$Address); | |
| 5305 %} | |
| 5306 ins_pipe(ialu_reg_mem); | |
| 5307 %} | |
| 5308 | |
| 5309 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned) | |
| 5310 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{ | |
| 5311 match(Set dst (AndI (LoadI mem) mask)); | |
| 5312 | |
| 5313 ins_cost(125); | |
| 5314 format %{ "movzbl $dst, $mem\t# int -> ubyte" %} | |
| 5315 ins_encode %{ | |
| 5316 __ movzbl($dst$$Register, $mem$$Address); | |
| 5317 %} | |
| 5318 ins_pipe(ialu_reg_mem); | |
| 5319 %} | |
| 5320 | |
| 5321 // Load Integer (32 bit signed) to Short (16 bit signed) | |
| 5322 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{ | |
| 5323 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); | |
| 5324 | |
| 5325 ins_cost(125); | |
| 5326 format %{ "movswl $dst, $mem\t# int -> short" %} | |
| 5327 ins_encode %{ | |
| 5328 __ movswl($dst$$Register, $mem$$Address); | |
| 5329 %} | |
| 5330 ins_pipe(ialu_reg_mem); | |
| 5331 %} | |
| 5332 | |
| 5333 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned) | |
| 5334 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{ | |
| 5335 match(Set dst (AndI (LoadI mem) mask)); | |
| 5336 | |
| 5337 ins_cost(125); | |
| 5338 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %} | |
| 5339 ins_encode %{ | |
| 5340 __ movzwl($dst$$Register, $mem$$Address); | |
| 5341 %} | |
| 5342 ins_pipe(ialu_reg_mem); | |
| 5343 %} | |
| 5344 | |
| 624 | 5345 // Load Integer into Long Register |
| 5346 instruct loadI2L(rRegL dst, memory mem) | |
| 5347 %{ | |
| 5348 match(Set dst (ConvI2L (LoadI mem))); | |
| 5349 | |
| 5350 ins_cost(125); | |
| 5351 format %{ "movslq $dst, $mem\t# int -> long" %} | |
| 5352 | |
| 5353 ins_encode %{ | |
| 5354 __ movslq($dst$$Register, $mem$$Address); | |
| 5355 %} | |
| 5356 | |
| 5357 ins_pipe(ialu_reg_mem); | |
| 5358 %} | |
| 5359 | |
| 824 | 5360 // Load Integer with mask 0xFF into Long Register |
| 5361 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{ | |
| 5362 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5363 | |
| 5364 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %} | |
| 5365 ins_encode %{ | |
| 5366 __ movzbq($dst$$Register, $mem$$Address); | |
| 5367 %} | |
| 5368 ins_pipe(ialu_reg_mem); | |
| 5369 %} | |
| 5370 | |
| 5371 // Load Integer with mask 0xFFFF into Long Register | |
| 5372 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{ | |
| 5373 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5374 | |
| 5375 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %} | |
| 5376 ins_encode %{ | |
| 5377 __ movzwq($dst$$Register, $mem$$Address); | |
| 5378 %} | |
| 5379 ins_pipe(ialu_reg_mem); | |
| 5380 %} | |
| 5381 | |
| 5382 // Load Integer with a 32-bit mask into Long Register | |
| 5383 instruct loadI2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{ | |
| 5384 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5385 effect(KILL cr); | |
| 5386 | |
| 5387 format %{ "movl $dst, $mem\t# int & 32-bit mask -> long\n\t" | |
| 5388 "andl $dst, $mask" %} | |
| 5389 ins_encode %{ | |
| 5390 Register Rdst = $dst$$Register; | |
| 5391 __ movl(Rdst, $mem$$Address); | |
| 5392 __ andl(Rdst, $mask$$constant); | |
| 5393 %} | |
| 5394 ins_pipe(ialu_reg_mem); | |
| 5395 %} | |
| 5396 | |
| 624 | 5397 // Load Unsigned Integer into Long Register |
| 5398 instruct loadUI2L(rRegL dst, memory mem) | |
| 5399 %{ | |
| 5400 match(Set dst (LoadUI2L mem)); | |
| 5401 | |
| 5402 ins_cost(125); | |
| 5403 format %{ "movl $dst, $mem\t# uint -> long" %} | |
| 5404 | |
| 5405 ins_encode %{ | |
| 5406 __ movl($dst$$Register, $mem$$Address); | |
| 5407 %} | |
| 5408 | |
| 0 | 5409 ins_pipe(ialu_reg_mem); |
| 5410 %} | |
| 5411 | |
| 5412 // Load Long | |
| 5413 instruct loadL(rRegL dst, memory mem) | |
| 5414 %{ | |
| 5415 match(Set dst (LoadL mem)); | |
| 5416 | |
| 624 | 5417 ins_cost(125); |
| 0 | 5418 format %{ "movq $dst, $mem\t# long" %} |
| 624 | 5419 |
| 5420 ins_encode %{ | |
| 5421 __ movq($dst$$Register, $mem$$Address); | |
| 5422 %} | |
| 5423 | |
| 0 | 5424 ins_pipe(ialu_reg_mem); // XXX |
| 5425 %} | |
| 5426 | |
| 5427 // Load Range | |
| 5428 instruct loadRange(rRegI dst, memory mem) | |
| 5429 %{ | |
| 5430 match(Set dst (LoadRange mem)); | |
| 5431 | |
| 5432 ins_cost(125); // XXX | |
| 5433 format %{ "movl $dst, $mem\t# range" %} | |
| 5434 opcode(0x8B); | |
| 5435 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5436 ins_pipe(ialu_reg_mem); | |
| 5437 %} | |
| 5438 | |
| 5439 // Load Pointer | |
| 5440 instruct loadP(rRegP dst, memory mem) | |
| 5441 %{ | |
| 5442 match(Set dst (LoadP mem)); | |
| 5443 | |
| 5444 ins_cost(125); // XXX | |
| 5445 format %{ "movq $dst, $mem\t# ptr" %} | |
| 5446 opcode(0x8B); | |
| 5447 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5448 ins_pipe(ialu_reg_mem); // XXX | |
| 5449 %} | |
| 5450 | |
|
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5451 // Load Compressed Pointer |
| 163 | 5452 instruct loadN(rRegN dst, memory mem) |
|
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5453 %{ |
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5454 match(Set dst (LoadN mem)); |
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5455 |
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5456 ins_cost(125); // XXX |
|
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5457 format %{ "movl $dst, $mem\t# compressed ptr" %} |
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5458 ins_encode %{ |
|
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5459 __ movl($dst$$Register, $mem$$Address); |
|
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5460 %} |
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5461 ins_pipe(ialu_reg_mem); // XXX |
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5462 %} |
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5463 |
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5464 |
| 0 | 5465 // Load Klass Pointer |
| 5466 instruct loadKlass(rRegP dst, memory mem) | |
| 5467 %{ | |
| 5468 match(Set dst (LoadKlass mem)); | |
| 5469 | |
| 5470 ins_cost(125); // XXX | |
| 5471 format %{ "movq $dst, $mem\t# class" %} | |
| 5472 opcode(0x8B); | |
| 5473 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5474 ins_pipe(ialu_reg_mem); // XXX | |
| 5475 %} | |
| 5476 | |
|
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5477 // Load narrow Klass Pointer |
|
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5478 instruct loadNKlass(rRegN dst, memory mem) |
|
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5479 %{ |
|
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5480 match(Set dst (LoadNKlass mem)); |
|
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5481 |
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5482 ins_cost(125); // XXX |
|
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5483 format %{ "movl $dst, $mem\t# compressed klass ptr" %} |
|
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5484 ins_encode %{ |
|
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5485 __ movl($dst$$Register, $mem$$Address); |
|
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5486 %} |
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5487 ins_pipe(ialu_reg_mem); // XXX |
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5488 %} |
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5489 |
| 0 | 5490 // Load Float |
| 5491 instruct loadF(regF dst, memory mem) | |
| 5492 %{ | |
| 5493 match(Set dst (LoadF mem)); | |
| 5494 | |
| 5495 ins_cost(145); // XXX | |
| 5496 format %{ "movss $dst, $mem\t# float" %} | |
| 4759 | 5497 ins_encode %{ |
| 5498 __ movflt($dst$$XMMRegister, $mem$$Address); | |
| 5499 %} | |
| 0 | 5500 ins_pipe(pipe_slow); // XXX |
| 5501 %} | |
| 5502 | |
| 5503 // Load Double | |
| 5504 instruct loadD_partial(regD dst, memory mem) | |
| 5505 %{ | |
| 5506 predicate(!UseXmmLoadAndClearUpper); | |
| 5507 match(Set dst (LoadD mem)); | |
| 5508 | |
| 5509 ins_cost(145); // XXX | |
| 5510 format %{ "movlpd $dst, $mem\t# double" %} | |
| 4759 | 5511 ins_encode %{ |
| 5512 __ movdbl($dst$$XMMRegister, $mem$$Address); | |
| 5513 %} | |
| 0 | 5514 ins_pipe(pipe_slow); // XXX |
| 5515 %} | |
| 5516 | |
| 5517 instruct loadD(regD dst, memory mem) | |
| 5518 %{ | |
| 5519 predicate(UseXmmLoadAndClearUpper); | |
| 5520 match(Set dst (LoadD mem)); | |
| 5521 | |
| 5522 ins_cost(145); // XXX | |
| 5523 format %{ "movsd $dst, $mem\t# double" %} | |
| 4759 | 5524 ins_encode %{ |
| 5525 __ movdbl($dst$$XMMRegister, $mem$$Address); | |
| 5526 %} | |
| 0 | 5527 ins_pipe(pipe_slow); // XXX |
| 5528 %} | |
| 5529 | |
| 5530 // Load Aligned Packed Byte to XMM register | |
| 5531 instruct loadA8B(regD dst, memory mem) %{ | |
| 5532 match(Set dst (Load8B mem)); | |
| 5533 ins_cost(125); | |
| 5534 format %{ "MOVQ $dst,$mem\t! packed8B" %} | |
| 4759 | 5535 ins_encode %{ |
| 5536 __ movq($dst$$XMMRegister, $mem$$Address); | |
| 5537 %} | |
| 0 | 5538 ins_pipe( pipe_slow ); |
| 5539 %} | |
| 5540 | |
| 5541 // Load Aligned Packed Short to XMM register | |
| 5542 instruct loadA4S(regD dst, memory mem) %{ | |
| 5543 match(Set dst (Load4S mem)); | |
| 5544 ins_cost(125); | |
| 5545 format %{ "MOVQ $dst,$mem\t! packed4S" %} | |
| 4759 | 5546 ins_encode %{ |
| 5547 __ movq($dst$$XMMRegister, $mem$$Address); | |
| 5548 %} | |
| 0 | 5549 ins_pipe( pipe_slow ); |
| 5550 %} | |
| 5551 | |
| 5552 // Load Aligned Packed Char to XMM register | |
| 5553 instruct loadA4C(regD dst, memory mem) %{ | |
| 5554 match(Set dst (Load4C mem)); | |
| 5555 ins_cost(125); | |
| 5556 format %{ "MOVQ $dst,$mem\t! packed4C" %} | |
| 4759 | 5557 ins_encode %{ |
| 5558 __ movq($dst$$XMMRegister, $mem$$Address); | |
| 5559 %} | |
| 0 | 5560 ins_pipe( pipe_slow ); |
| 5561 %} | |
| 5562 | |
| 5563 // Load Aligned Packed Integer to XMM register | |
| 5564 instruct load2IU(regD dst, memory mem) %{ | |
| 5565 match(Set dst (Load2I mem)); | |
| 5566 ins_cost(125); | |
| 5567 format %{ "MOVQ $dst,$mem\t! packed2I" %} | |
| 4759 | 5568 ins_encode %{ |
| 5569 __ movq($dst$$XMMRegister, $mem$$Address); | |
| 5570 %} | |
| 0 | 5571 ins_pipe( pipe_slow ); |
| 5572 %} | |
| 5573 | |
| 5574 // Load Aligned Packed Single to XMM | |
| 5575 instruct loadA2F(regD dst, memory mem) %{ | |
| 5576 match(Set dst (Load2F mem)); | |
| 4759 | 5577 ins_cost(125); |
| 0 | 5578 format %{ "MOVQ $dst,$mem\t! packed2F" %} |
| 4759 | 5579 ins_encode %{ |
| 5580 __ movq($dst$$XMMRegister, $mem$$Address); | |
| 5581 %} | |
| 0 | 5582 ins_pipe( pipe_slow ); |
| 5583 %} | |
| 5584 | |
| 5585 // Load Effective Address | |
| 5586 instruct leaP8(rRegP dst, indOffset8 mem) | |
| 5587 %{ | |
| 5588 match(Set dst mem); | |
| 5589 | |
| 5590 ins_cost(110); // XXX | |
| 5591 format %{ "leaq $dst, $mem\t# ptr 8" %} | |
| 5592 opcode(0x8D); | |
| 5593 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5594 ins_pipe(ialu_reg_reg_fat); | |
| 5595 %} | |
| 5596 | |
| 5597 instruct leaP32(rRegP dst, indOffset32 mem) | |
| 5598 %{ | |
| 5599 match(Set dst mem); | |
| 5600 | |
| 5601 ins_cost(110); | |
| 5602 format %{ "leaq $dst, $mem\t# ptr 32" %} | |
| 5603 opcode(0x8D); | |
| 5604 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5605 ins_pipe(ialu_reg_reg_fat); | |
| 5606 %} | |
| 5607 | |
| 5608 // instruct leaPIdx(rRegP dst, indIndex mem) | |
| 5609 // %{ | |
| 5610 // match(Set dst mem); | |
| 5611 | |
| 5612 // ins_cost(110); | |
| 5613 // format %{ "leaq $dst, $mem\t# ptr idx" %} | |
| 5614 // opcode(0x8D); | |
| 5615 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5616 // ins_pipe(ialu_reg_reg_fat); | |
| 5617 // %} | |
| 5618 | |
| 5619 instruct leaPIdxOff(rRegP dst, indIndexOffset mem) | |
| 5620 %{ | |
| 5621 match(Set dst mem); | |
| 5622 | |
| 5623 ins_cost(110); | |
| 5624 format %{ "leaq $dst, $mem\t# ptr idxoff" %} | |
| 5625 opcode(0x8D); | |
| 5626 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5627 ins_pipe(ialu_reg_reg_fat); | |
| 5628 %} | |
| 5629 | |
| 5630 instruct leaPIdxScale(rRegP dst, indIndexScale mem) | |
| 5631 %{ | |
| 5632 match(Set dst mem); | |
| 5633 | |
| 5634 ins_cost(110); | |
| 5635 format %{ "leaq $dst, $mem\t# ptr idxscale" %} | |
| 5636 opcode(0x8D); | |
| 5637 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5638 ins_pipe(ialu_reg_reg_fat); | |
| 5639 %} | |
| 5640 | |
| 5641 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem) | |
| 5642 %{ | |
| 5643 match(Set dst mem); | |
| 5644 | |
| 5645 ins_cost(110); | |
| 5646 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %} | |
| 5647 opcode(0x8D); | |
| 5648 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5649 ins_pipe(ialu_reg_reg_fat); | |
| 5650 %} | |
| 5651 | |
|
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5652 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem) |
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5653 %{ |
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5654 match(Set dst mem); |
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5655 |
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5656 ins_cost(110); |
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5657 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %} |
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5658 opcode(0x8D); |
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5659 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
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5660 ins_pipe(ialu_reg_reg_fat); |
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5661 %} |
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5662 |
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5663 // Load Effective Address which uses Narrow (32-bits) oop |
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5664 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem) |
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5665 %{ |
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5666 predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0)); |
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5667 match(Set dst mem); |
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5668 |
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5669 ins_cost(110); |
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5670 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %} |
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5671 opcode(0x8D); |
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5672 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
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5673 ins_pipe(ialu_reg_reg_fat); |
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5674 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5675 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5676 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5677 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5678 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5679 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5680 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5681 ins_cost(110); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5682 format %{ "leaq $dst, $mem\t# ptr off8narrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5683 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5684 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5685 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5686 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5687 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5688 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5689 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5690 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5691 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5692 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5693 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5694 format %{ "leaq $dst, $mem\t# ptr off32narrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5695 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5696 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5697 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5698 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5699 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5700 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5701 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5702 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5703 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5704 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5705 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5706 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5707 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5708 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5709 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5710 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5711 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5712 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5713 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5714 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5715 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5716 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5717 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5718 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5719 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5720 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5721 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5722 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5723 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5724 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5725 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5726 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5727 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5728 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5729 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5730 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5731 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5732 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5733 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5734 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5735 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5736 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5737 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5738 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5739 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5740 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5741 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5742 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5743 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5744 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5745 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5746 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5747 |
| 0 | 5748 instruct loadConI(rRegI dst, immI src) |
| 5749 %{ | |
| 5750 match(Set dst src); | |
| 5751 | |
| 5752 format %{ "movl $dst, $src\t# int" %} | |
| 5753 ins_encode(load_immI(dst, src)); | |
| 5754 ins_pipe(ialu_reg_fat); // XXX | |
| 5755 %} | |
| 5756 | |
| 5757 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr) | |
| 5758 %{ | |
| 5759 match(Set dst src); | |
| 5760 effect(KILL cr); | |
| 5761 | |
| 5762 ins_cost(50); | |
| 5763 format %{ "xorl $dst, $dst\t# int" %} | |
| 5764 opcode(0x33); /* + rd */ | |
| 5765 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst)); | |
| 5766 ins_pipe(ialu_reg); | |
| 5767 %} | |
| 5768 | |
| 5769 instruct loadConL(rRegL dst, immL src) | |
| 5770 %{ | |
| 5771 match(Set dst src); | |
| 5772 | |
| 5773 ins_cost(150); | |
| 5774 format %{ "movq $dst, $src\t# long" %} | |
| 5775 ins_encode(load_immL(dst, src)); | |
| 5776 ins_pipe(ialu_reg); | |
| 5777 %} | |
| 5778 | |
| 5779 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr) | |
| 5780 %{ | |
| 5781 match(Set dst src); | |
| 5782 effect(KILL cr); | |
| 5783 | |
| 5784 ins_cost(50); | |
| 5785 format %{ "xorl $dst, $dst\t# long" %} | |
| 5786 opcode(0x33); /* + rd */ | |
| 5787 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst)); | |
| 5788 ins_pipe(ialu_reg); // XXX | |
| 5789 %} | |
| 5790 | |
| 5791 instruct loadConUL32(rRegL dst, immUL32 src) | |
| 5792 %{ | |
| 5793 match(Set dst src); | |
| 5794 | |
| 5795 ins_cost(60); | |
| 5796 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %} | |
| 5797 ins_encode(load_immUL32(dst, src)); | |
| 5798 ins_pipe(ialu_reg); | |
| 5799 %} | |
| 5800 | |
| 5801 instruct loadConL32(rRegL dst, immL32 src) | |
| 5802 %{ | |
| 5803 match(Set dst src); | |
| 5804 | |
| 5805 ins_cost(70); | |
| 5806 format %{ "movq $dst, $src\t# long (32-bit)" %} | |
| 5807 ins_encode(load_immL32(dst, src)); | |
| 5808 ins_pipe(ialu_reg); | |
| 5809 %} | |
| 5810 | |
| 2008 | 5811 instruct loadConP(rRegP dst, immP con) %{ |
| 5812 match(Set dst con); | |
| 5813 | |
| 5814 format %{ "movq $dst, $con\t# ptr" %} | |
| 5815 ins_encode(load_immP(dst, con)); | |
| 0 | 5816 ins_pipe(ialu_reg_fat); // XXX |
| 5817 %} | |
| 5818 | |
| 5819 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr) | |
| 5820 %{ | |
| 5821 match(Set dst src); | |
| 5822 effect(KILL cr); | |
| 5823 | |
| 5824 ins_cost(50); | |
| 5825 format %{ "xorl $dst, $dst\t# ptr" %} | |
| 5826 opcode(0x33); /* + rd */ | |
| 5827 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst)); | |
| 5828 ins_pipe(ialu_reg); | |
| 5829 %} | |
| 5830 | |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
5831 instruct loadConP_poll(rRegP dst, immP_poll src) %{ |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
5832 match(Set dst src); |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
5833 format %{ "movq $dst, $src\t!ptr" %} |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
5834 ins_encode %{ |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
5835 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_type); |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
5836 __ lea($dst$$Register, polling_page); |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
5837 %} |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
5838 ins_pipe(ialu_reg_fat); |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
5839 %} |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
5840 |
| 0 | 5841 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr) |
| 5842 %{ | |
| 5843 match(Set dst src); | |
| 5844 effect(KILL cr); | |
| 5845 | |
| 5846 ins_cost(60); | |
| 5847 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %} | |
| 5848 ins_encode(load_immP31(dst, src)); | |
| 5849 ins_pipe(ialu_reg); | |
| 5850 %} | |
| 5851 | |
| 2008 | 5852 instruct loadConF(regF dst, immF con) %{ |
| 5853 match(Set dst con); | |
| 0 | 5854 ins_cost(125); |
| 2008 | 5855 format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %} |
| 5856 ins_encode %{ | |
| 5857 __ movflt($dst$$XMMRegister, $constantaddress($con)); | |
| 5858 %} | |
| 0 | 5859 ins_pipe(pipe_slow); |
| 5860 %} | |
| 5861 | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5862 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5863 match(Set dst src); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5864 effect(KILL cr); |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
5865 format %{ "xorq $dst, $src\t# compressed NULL ptr" %} |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5866 ins_encode %{ |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5867 __ xorq($dst$$Register, $dst$$Register); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5868 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5869 ins_pipe(ialu_reg); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5870 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5871 |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
5872 instruct loadConN(rRegN dst, immN src) %{ |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5873 match(Set dst src); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5874 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5875 ins_cost(125); |
|
164
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5876 format %{ "movl $dst, $src\t# compressed ptr" %} |
|
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5877 ins_encode %{ |
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5878 address con = (address)$src$$constant; |
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5879 if (con == NULL) { |
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5880 ShouldNotReachHere(); |
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5881 } else { |
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5882 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant); |
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5883 } |
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5884 %} |
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5885 ins_pipe(ialu_reg_fat); // XXX |
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5886 %} |
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5887 |
| 0 | 5888 instruct loadConF0(regF dst, immF0 src) |
| 5889 %{ | |
| 5890 match(Set dst src); | |
| 5891 ins_cost(100); | |
| 5892 | |
| 5893 format %{ "xorps $dst, $dst\t# float 0.0" %} | |
| 4759 | 5894 ins_encode %{ |
| 5895 __ xorps($dst$$XMMRegister, $dst$$XMMRegister); | |
| 5896 %} | |
| 0 | 5897 ins_pipe(pipe_slow); |
| 5898 %} | |
| 5899 | |
| 5900 // Use the same format since predicate() can not be used here. | |
| 2008 | 5901 instruct loadConD(regD dst, immD con) %{ |
| 5902 match(Set dst con); | |
| 0 | 5903 ins_cost(125); |
| 2008 | 5904 format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %} |
| 5905 ins_encode %{ | |
| 5906 __ movdbl($dst$$XMMRegister, $constantaddress($con)); | |
| 5907 %} | |
| 0 | 5908 ins_pipe(pipe_slow); |
| 5909 %} | |
| 5910 | |
| 5911 instruct loadConD0(regD dst, immD0 src) | |
| 5912 %{ | |
| 5913 match(Set dst src); | |
| 5914 ins_cost(100); | |
| 5915 | |
| 5916 format %{ "xorpd $dst, $dst\t# double 0.0" %} | |
| 4759 | 5917 ins_encode %{ |
| 5918 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister); | |
| 5919 %} | |
| 0 | 5920 ins_pipe(pipe_slow); |
| 5921 %} | |
| 5922 | |
| 5923 instruct loadSSI(rRegI dst, stackSlotI src) | |
| 5924 %{ | |
| 5925 match(Set dst src); | |
| 5926 | |
| 5927 ins_cost(125); | |
| 5928 format %{ "movl $dst, $src\t# int stk" %} | |
| 5929 opcode(0x8B); | |
| 5930 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 5931 ins_pipe(ialu_reg_mem); | |
| 5932 %} | |
| 5933 | |
| 5934 instruct loadSSL(rRegL dst, stackSlotL src) | |
| 5935 %{ | |
| 5936 match(Set dst src); | |
| 5937 | |
| 5938 ins_cost(125); | |
| 5939 format %{ "movq $dst, $src\t# long stk" %} | |
| 5940 opcode(0x8B); | |
| 5941 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 5942 ins_pipe(ialu_reg_mem); | |
| 5943 %} | |
| 5944 | |
| 5945 instruct loadSSP(rRegP dst, stackSlotP src) | |
| 5946 %{ | |
| 5947 match(Set dst src); | |
| 5948 | |
| 5949 ins_cost(125); | |
| 5950 format %{ "movq $dst, $src\t# ptr stk" %} | |
| 5951 opcode(0x8B); | |
| 5952 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 5953 ins_pipe(ialu_reg_mem); | |
| 5954 %} | |
| 5955 | |
| 5956 instruct loadSSF(regF dst, stackSlotF src) | |
| 5957 %{ | |
| 5958 match(Set dst src); | |
| 5959 | |
| 5960 ins_cost(125); | |
| 5961 format %{ "movss $dst, $src\t# float stk" %} | |
| 4759 | 5962 ins_encode %{ |
| 5963 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 5964 %} | |
| 0 | 5965 ins_pipe(pipe_slow); // XXX |
| 5966 %} | |
| 5967 | |
| 5968 // Use the same format since predicate() can not be used here. | |
| 5969 instruct loadSSD(regD dst, stackSlotD src) | |
| 5970 %{ | |
| 5971 match(Set dst src); | |
| 5972 | |
| 5973 ins_cost(125); | |
| 5974 format %{ "movsd $dst, $src\t# double stk" %} | |
| 5975 ins_encode %{ | |
| 5976 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 5977 %} | |
| 5978 ins_pipe(pipe_slow); // XXX | |
| 5979 %} | |
| 5980 | |
| 5981 // Prefetch instructions. | |
| 5982 // Must be safe to execute with invalid address (cannot fault). | |
| 5983 | |
| 5984 instruct prefetchr( memory mem ) %{ | |
| 5985 predicate(ReadPrefetchInstr==3); | |
| 5986 match(PrefetchRead mem); | |
| 5987 ins_cost(125); | |
| 5988 | |
| 5989 format %{ "PREFETCHR $mem\t# Prefetch into level 1 cache" %} | |
| 3854 | 5990 ins_encode %{ |
| 5991 __ prefetchr($mem$$Address); | |
| 5992 %} | |
| 0 | 5993 ins_pipe(ialu_mem); |
| 5994 %} | |
| 5995 | |
| 5996 instruct prefetchrNTA( memory mem ) %{ | |
| 5997 predicate(ReadPrefetchInstr==0); | |
| 5998 match(PrefetchRead mem); | |
| 5999 ins_cost(125); | |
| 6000 | |
| 6001 format %{ "PREFETCHNTA $mem\t# Prefetch into non-temporal cache for read" %} | |
| 3854 | 6002 ins_encode %{ |
| 6003 __ prefetchnta($mem$$Address); | |
| 6004 %} | |
| 0 | 6005 ins_pipe(ialu_mem); |
| 6006 %} | |
| 6007 | |
| 6008 instruct prefetchrT0( memory mem ) %{ | |
| 6009 predicate(ReadPrefetchInstr==1); | |
| 6010 match(PrefetchRead mem); | |
| 6011 ins_cost(125); | |
| 6012 | |
| 6013 format %{ "PREFETCHT0 $mem\t# prefetch into L1 and L2 caches for read" %} | |
| 3854 | 6014 ins_encode %{ |
| 6015 __ prefetcht0($mem$$Address); | |
| 6016 %} | |
| 0 | 6017 ins_pipe(ialu_mem); |
| 6018 %} | |
| 6019 | |
| 6020 instruct prefetchrT2( memory mem ) %{ | |
| 6021 predicate(ReadPrefetchInstr==2); | |
| 6022 match(PrefetchRead mem); | |
| 6023 ins_cost(125); | |
| 6024 | |
| 6025 format %{ "PREFETCHT2 $mem\t# prefetch into L2 caches for read" %} | |
| 3854 | 6026 ins_encode %{ |
| 6027 __ prefetcht2($mem$$Address); | |
| 6028 %} | |
| 0 | 6029 ins_pipe(ialu_mem); |
| 6030 %} | |
| 6031 | |
| 6032 instruct prefetchwNTA( memory mem ) %{ | |
| 6033 match(PrefetchWrite mem); | |
| 6034 ins_cost(125); | |
| 6035 | |
| 6036 format %{ "PREFETCHNTA $mem\t# Prefetch to non-temporal cache for write" %} | |
| 3854 | 6037 ins_encode %{ |
| 6038 __ prefetchnta($mem$$Address); | |
| 6039 %} | |
| 0 | 6040 ins_pipe(ialu_mem); |
| 6041 %} | |
| 6042 | |
| 3854 | 6043 // Prefetch instructions for allocation. |
| 6044 | |
| 6045 instruct prefetchAlloc( memory mem ) %{ | |
| 6046 predicate(AllocatePrefetchInstr==3); | |
| 6047 match(PrefetchAllocation mem); | |
| 6048 ins_cost(125); | |
| 6049 | |
| 6050 format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %} | |
| 6051 ins_encode %{ | |
| 6052 __ prefetchw($mem$$Address); | |
| 6053 %} | |
| 6054 ins_pipe(ialu_mem); | |
| 6055 %} | |
| 6056 | |
| 6057 instruct prefetchAllocNTA( memory mem ) %{ | |
| 6058 predicate(AllocatePrefetchInstr==0); | |
| 6059 match(PrefetchAllocation mem); | |
| 0 | 6060 ins_cost(125); |
| 6061 | |
| 3854 | 6062 format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %} |
| 6063 ins_encode %{ | |
| 6064 __ prefetchnta($mem$$Address); | |
| 6065 %} | |
| 0 | 6066 ins_pipe(ialu_mem); |
| 6067 %} | |
| 6068 | |
| 3854 | 6069 instruct prefetchAllocT0( memory mem ) %{ |
| 6070 predicate(AllocatePrefetchInstr==1); | |
| 6071 match(PrefetchAllocation mem); | |
| 0 | 6072 ins_cost(125); |
| 6073 | |
| 3854 | 6074 format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %} |
| 6075 ins_encode %{ | |
| 6076 __ prefetcht0($mem$$Address); | |
| 6077 %} | |
| 6078 ins_pipe(ialu_mem); | |
| 6079 %} | |
| 6080 | |
| 6081 instruct prefetchAllocT2( memory mem ) %{ | |
| 6082 predicate(AllocatePrefetchInstr==2); | |
| 6083 match(PrefetchAllocation mem); | |
| 6084 ins_cost(125); | |
| 6085 | |
| 6086 format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %} | |
| 6087 ins_encode %{ | |
| 6088 __ prefetcht2($mem$$Address); | |
| 6089 %} | |
| 0 | 6090 ins_pipe(ialu_mem); |
| 6091 %} | |
| 6092 | |
| 6093 //----------Store Instructions------------------------------------------------- | |
| 6094 | |
| 6095 // Store Byte | |
| 6096 instruct storeB(memory mem, rRegI src) | |
| 6097 %{ | |
| 6098 match(Set mem (StoreB mem src)); | |
| 6099 | |
| 6100 ins_cost(125); // XXX | |
| 6101 format %{ "movb $mem, $src\t# byte" %} | |
| 6102 opcode(0x88); | |
| 6103 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
| 6104 ins_pipe(ialu_mem_reg); | |
| 6105 %} | |
| 6106 | |
| 6107 // Store Char/Short | |
| 6108 instruct storeC(memory mem, rRegI src) | |
| 6109 %{ | |
| 6110 match(Set mem (StoreC mem src)); | |
| 6111 | |
| 6112 ins_cost(125); // XXX | |
| 6113 format %{ "movw $mem, $src\t# char/short" %} | |
| 6114 opcode(0x89); | |
| 6115 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
| 6116 ins_pipe(ialu_mem_reg); | |
| 6117 %} | |
| 6118 | |
| 6119 // Store Integer | |
| 6120 instruct storeI(memory mem, rRegI src) | |
| 6121 %{ | |
| 6122 match(Set mem (StoreI mem src)); | |
| 6123 | |
| 6124 ins_cost(125); // XXX | |
| 6125 format %{ "movl $mem, $src\t# int" %} | |
| 6126 opcode(0x89); | |
| 6127 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
| 6128 ins_pipe(ialu_mem_reg); | |
| 6129 %} | |
| 6130 | |
| 6131 // Store Long | |
| 6132 instruct storeL(memory mem, rRegL src) | |
| 6133 %{ | |
| 6134 match(Set mem (StoreL mem src)); | |
| 6135 | |
| 6136 ins_cost(125); // XXX | |
| 6137 format %{ "movq $mem, $src\t# long" %} | |
| 6138 opcode(0x89); | |
| 6139 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem)); | |
| 6140 ins_pipe(ialu_mem_reg); // XXX | |
| 6141 %} | |
| 6142 | |
| 6143 // Store Pointer | |
| 6144 instruct storeP(memory mem, any_RegP src) | |
| 6145 %{ | |
| 6146 match(Set mem (StoreP mem src)); | |
| 6147 | |
| 6148 ins_cost(125); // XXX | |
| 6149 format %{ "movq $mem, $src\t# ptr" %} | |
| 6150 opcode(0x89); | |
| 6151 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem)); | |
| 6152 ins_pipe(ialu_mem_reg); | |
| 6153 %} | |
| 6154 | |
|
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6155 instruct storeImmP0(memory mem, immP0 zero) |
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6156 %{ |
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6157 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
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6158 match(Set mem (StoreP mem zero)); |
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6159 |
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6160 ins_cost(125); // XXX |
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6161 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %} |
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6162 ins_encode %{ |
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6163 __ movq($mem$$Address, r12); |
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6164 %} |
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6165 ins_pipe(ialu_mem_reg); |
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6166 %} |
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6167 |
| 0 | 6168 // Store NULL Pointer, mark word, or other simple pointer constant. |
| 6169 instruct storeImmP(memory mem, immP31 src) | |
| 6170 %{ | |
| 6171 match(Set mem (StoreP mem src)); | |
| 6172 | |
|
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6173 ins_cost(150); // XXX |
| 0 | 6174 format %{ "movq $mem, $src\t# ptr" %} |
| 6175 opcode(0xC7); /* C7 /0 */ | |
| 6176 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); | |
| 6177 ins_pipe(ialu_mem_imm); | |
| 6178 %} | |
| 6179 | |
|
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6180 // Store Compressed Pointer |
| 163 | 6181 instruct storeN(memory mem, rRegN src) |
|
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6182 %{ |
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6183 match(Set mem (StoreN mem src)); |
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6184 |
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6185 ins_cost(125); // XXX |
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6186 format %{ "movl $mem, $src\t# compressed ptr" %} |
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6187 ins_encode %{ |
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6188 __ movl($mem$$Address, $src$$Register); |
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6189 %} |
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6190 ins_pipe(ialu_mem_reg); |
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6191 %} |
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6192 |
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6193 instruct storeImmN0(memory mem, immN0 zero) |
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6194 %{ |
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6195 predicate(Universe::narrow_oop_base() == NULL); |
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6196 match(Set mem (StoreN mem zero)); |
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6197 |
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6198 ins_cost(125); // XXX |
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6199 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %} |
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6200 ins_encode %{ |
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6201 __ movl($mem$$Address, r12); |
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6202 %} |
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6203 ins_pipe(ialu_mem_reg); |
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6204 %} |
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6205 |
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6206 instruct storeImmN(memory mem, immN src) |
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6207 %{ |
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6208 match(Set mem (StoreN mem src)); |
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6209 |
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6210 ins_cost(150); // XXX |
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6211 format %{ "movl $mem, $src\t# compressed ptr" %} |
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6212 ins_encode %{ |
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6213 address con = (address)$src$$constant; |
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6214 if (con == NULL) { |
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diff
changeset
|
6215 __ movl($mem$$Address, (int32_t)0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
6216 } else { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6217 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6218 } |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6219 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6220 ins_pipe(ialu_mem_imm); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6221 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6222 |
| 0 | 6223 // Store Integer Immediate |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6224 instruct storeImmI0(memory mem, immI0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6225 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6226 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6227 match(Set mem (StoreI mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6228 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6229 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6230 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6231 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6232 __ movl($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6233 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6234 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6235 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
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|
6236 |
| 0 | 6237 instruct storeImmI(memory mem, immI src) |
| 6238 %{ | |
| 6239 match(Set mem (StoreI mem src)); | |
| 6240 | |
| 6241 ins_cost(150); | |
| 6242 format %{ "movl $mem, $src\t# int" %} | |
| 6243 opcode(0xC7); /* C7 /0 */ | |
| 6244 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); | |
| 6245 ins_pipe(ialu_mem_imm); | |
| 6246 %} | |
| 6247 | |
| 6248 // Store Long Immediate | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6249 instruct storeImmL0(memory mem, immL0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6250 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6251 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6252 match(Set mem (StoreL mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6253 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6254 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6255 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6256 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6257 __ movq($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6258 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6259 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6260 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
6261 |
| 0 | 6262 instruct storeImmL(memory mem, immL32 src) |
| 6263 %{ | |
| 6264 match(Set mem (StoreL mem src)); | |
| 6265 | |
| 6266 ins_cost(150); | |
| 6267 format %{ "movq $mem, $src\t# long" %} | |
| 6268 opcode(0xC7); /* C7 /0 */ | |
| 6269 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); | |
| 6270 ins_pipe(ialu_mem_imm); | |
| 6271 %} | |
| 6272 | |
| 6273 // Store Short/Char Immediate | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6274 instruct storeImmC0(memory mem, immI0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6275 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6276 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6277 match(Set mem (StoreC mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6278 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6279 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6280 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6281 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6282 __ movw($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6283 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6284 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6285 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6286 |
| 0 | 6287 instruct storeImmI16(memory mem, immI16 src) |
| 6288 %{ | |
| 6289 predicate(UseStoreImmI16); | |
| 6290 match(Set mem (StoreC mem src)); | |
| 6291 | |
| 6292 ins_cost(150); | |
| 6293 format %{ "movw $mem, $src\t# short/char" %} | |
| 6294 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */ | |
| 6295 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src)); | |
| 6296 ins_pipe(ialu_mem_imm); | |
| 6297 %} | |
| 6298 | |
| 6299 // Store Byte Immediate | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6300 instruct storeImmB0(memory mem, immI0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6301 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6302 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6303 match(Set mem (StoreB mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6304 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6305 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6306 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6307 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6308 __ movb($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6309 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6310 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6311 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6312 |
| 0 | 6313 instruct storeImmB(memory mem, immI8 src) |
| 6314 %{ | |
| 6315 match(Set mem (StoreB mem src)); | |
| 6316 | |
| 6317 ins_cost(150); // XXX | |
| 6318 format %{ "movb $mem, $src\t# byte" %} | |
| 6319 opcode(0xC6); /* C6 /0 */ | |
| 6320 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src)); | |
| 6321 ins_pipe(ialu_mem_imm); | |
| 6322 %} | |
| 6323 | |
| 6324 // Store Aligned Packed Byte XMM register to memory | |
| 6325 instruct storeA8B(memory mem, regD src) %{ | |
| 6326 match(Set mem (Store8B mem src)); | |
| 6327 ins_cost(145); | |
| 6328 format %{ "MOVQ $mem,$src\t! packed8B" %} | |
| 4759 | 6329 ins_encode %{ |
| 6330 __ movq($mem$$Address, $src$$XMMRegister); | |
| 6331 %} | |
| 0 | 6332 ins_pipe( pipe_slow ); |
| 6333 %} | |
| 6334 | |
| 6335 // Store Aligned Packed Char/Short XMM register to memory | |
| 6336 instruct storeA4C(memory mem, regD src) %{ | |
| 6337 match(Set mem (Store4C mem src)); | |
| 6338 ins_cost(145); | |
| 6339 format %{ "MOVQ $mem,$src\t! packed4C" %} | |
| 4759 | 6340 ins_encode %{ |
| 6341 __ movq($mem$$Address, $src$$XMMRegister); | |
| 6342 %} | |
| 0 | 6343 ins_pipe( pipe_slow ); |
| 6344 %} | |
| 6345 | |
| 6346 // Store Aligned Packed Integer XMM register to memory | |
| 6347 instruct storeA2I(memory mem, regD src) %{ | |
| 6348 match(Set mem (Store2I mem src)); | |
| 6349 ins_cost(145); | |
| 6350 format %{ "MOVQ $mem,$src\t! packed2I" %} | |
| 4759 | 6351 ins_encode %{ |
| 6352 __ movq($mem$$Address, $src$$XMMRegister); | |
| 6353 %} | |
| 0 | 6354 ins_pipe( pipe_slow ); |
| 6355 %} | |
| 6356 | |
| 6357 // Store CMS card-mark Immediate | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6358 instruct storeImmCM0_reg(memory mem, immI0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
6359 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6360 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6361 match(Set mem (StoreCM mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6362 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6363 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6364 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6365 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6366 __ movb($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6367 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6368 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6369 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6370 |
| 0 | 6371 instruct storeImmCM0(memory mem, immI0 src) |
| 6372 %{ | |
| 6373 match(Set mem (StoreCM mem src)); | |
| 6374 | |
| 6375 ins_cost(150); // XXX | |
| 6376 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %} | |
| 6377 opcode(0xC6); /* C6 /0 */ | |
| 6378 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src)); | |
| 6379 ins_pipe(ialu_mem_imm); | |
| 6380 %} | |
| 6381 | |
| 6382 // Store Aligned Packed Single Float XMM register to memory | |
| 6383 instruct storeA2F(memory mem, regD src) %{ | |
| 6384 match(Set mem (Store2F mem src)); | |
| 6385 ins_cost(145); | |
| 6386 format %{ "MOVQ $mem,$src\t! packed2F" %} | |
| 4759 | 6387 ins_encode %{ |
| 6388 __ movq($mem$$Address, $src$$XMMRegister); | |
| 6389 %} | |
| 0 | 6390 ins_pipe( pipe_slow ); |
| 6391 %} | |
| 6392 | |
| 6393 // Store Float | |
| 6394 instruct storeF(memory mem, regF src) | |
| 6395 %{ | |
| 6396 match(Set mem (StoreF mem src)); | |
| 6397 | |
| 6398 ins_cost(95); // XXX | |
| 6399 format %{ "movss $mem, $src\t# float" %} | |
| 4759 | 6400 ins_encode %{ |
| 6401 __ movflt($mem$$Address, $src$$XMMRegister); | |
| 6402 %} | |
| 0 | 6403 ins_pipe(pipe_slow); // XXX |
| 6404 %} | |
| 6405 | |
| 6406 // Store immediate Float value (it is faster than store from XMM register) | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6407 instruct storeF0(memory mem, immF0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6408 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6409 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6410 match(Set mem (StoreF mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6411 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6412 ins_cost(25); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6413 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6414 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6415 __ movl($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6416 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6417 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6418 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6419 |
| 0 | 6420 instruct storeF_imm(memory mem, immF src) |
| 6421 %{ | |
| 6422 match(Set mem (StoreF mem src)); | |
| 6423 | |
| 6424 ins_cost(50); | |
| 6425 format %{ "movl $mem, $src\t# float" %} | |
| 6426 opcode(0xC7); /* C7 /0 */ | |
| 6427 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src)); | |
| 6428 ins_pipe(ialu_mem_imm); | |
| 6429 %} | |
| 6430 | |
| 6431 // Store Double | |
| 6432 instruct storeD(memory mem, regD src) | |
| 6433 %{ | |
| 6434 match(Set mem (StoreD mem src)); | |
| 6435 | |
| 6436 ins_cost(95); // XXX | |
| 6437 format %{ "movsd $mem, $src\t# double" %} | |
| 4759 | 6438 ins_encode %{ |
| 6439 __ movdbl($mem$$Address, $src$$XMMRegister); | |
| 6440 %} | |
| 0 | 6441 ins_pipe(pipe_slow); // XXX |
| 6442 %} | |
| 6443 | |
| 6444 // Store immediate double 0.0 (it is faster than store from XMM register) | |
| 6445 instruct storeD0_imm(memory mem, immD0 src) | |
| 6446 %{ | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6447 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL)); |
| 0 | 6448 match(Set mem (StoreD mem src)); |
| 6449 | |
| 6450 ins_cost(50); | |
| 6451 format %{ "movq $mem, $src\t# double 0." %} | |
| 6452 opcode(0xC7); /* C7 /0 */ | |
| 6453 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src)); | |
| 6454 ins_pipe(ialu_mem_imm); | |
| 6455 %} | |
| 6456 | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6457 instruct storeD0(memory mem, immD0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6458 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6459 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6460 match(Set mem (StoreD mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6461 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6462 ins_cost(25); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6463 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6464 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6465 __ movq($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6466 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6467 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6468 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6469 |
| 0 | 6470 instruct storeSSI(stackSlotI dst, rRegI src) |
| 6471 %{ | |
| 6472 match(Set dst src); | |
| 6473 | |
| 6474 ins_cost(100); | |
| 6475 format %{ "movl $dst, $src\t# int stk" %} | |
| 6476 opcode(0x89); | |
| 6477 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 6478 ins_pipe( ialu_mem_reg ); | |
| 6479 %} | |
| 6480 | |
| 6481 instruct storeSSL(stackSlotL dst, rRegL src) | |
| 6482 %{ | |
| 6483 match(Set dst src); | |
| 6484 | |
| 6485 ins_cost(100); | |
| 6486 format %{ "movq $dst, $src\t# long stk" %} | |
| 6487 opcode(0x89); | |
| 6488 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 6489 ins_pipe(ialu_mem_reg); | |
| 6490 %} | |
| 6491 | |
| 6492 instruct storeSSP(stackSlotP dst, rRegP src) | |
| 6493 %{ | |
| 6494 match(Set dst src); | |
| 6495 | |
| 6496 ins_cost(100); | |
| 6497 format %{ "movq $dst, $src\t# ptr stk" %} | |
| 6498 opcode(0x89); | |
| 6499 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 6500 ins_pipe(ialu_mem_reg); | |
| 6501 %} | |
| 6502 | |
| 6503 instruct storeSSF(stackSlotF dst, regF src) | |
| 6504 %{ | |
| 6505 match(Set dst src); | |
| 6506 | |
| 6507 ins_cost(95); // XXX | |
| 6508 format %{ "movss $dst, $src\t# float stk" %} | |
| 4759 | 6509 ins_encode %{ |
| 6510 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister); | |
| 6511 %} | |
| 0 | 6512 ins_pipe(pipe_slow); // XXX |
| 6513 %} | |
| 6514 | |
| 6515 instruct storeSSD(stackSlotD dst, regD src) | |
| 6516 %{ | |
| 6517 match(Set dst src); | |
| 6518 | |
| 6519 ins_cost(95); // XXX | |
| 6520 format %{ "movsd $dst, $src\t# double stk" %} | |
| 4759 | 6521 ins_encode %{ |
| 6522 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister); | |
| 6523 %} | |
| 0 | 6524 ins_pipe(pipe_slow); // XXX |
| 6525 %} | |
| 6526 | |
| 6527 //----------BSWAP Instructions------------------------------------------------- | |
| 6528 instruct bytes_reverse_int(rRegI dst) %{ | |
| 6529 match(Set dst (ReverseBytesI dst)); | |
| 6530 | |
| 6531 format %{ "bswapl $dst" %} | |
| 6532 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */ | |
| 6533 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) ); | |
| 6534 ins_pipe( ialu_reg ); | |
| 6535 %} | |
| 6536 | |
| 6537 instruct bytes_reverse_long(rRegL dst) %{ | |
| 6538 match(Set dst (ReverseBytesL dst)); | |
| 6539 | |
| 6540 format %{ "bswapq $dst" %} | |
| 6541 | |
| 6542 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */ | |
| 6543 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) ); | |
| 6544 ins_pipe( ialu_reg); | |
| 6545 %} | |
| 6546 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6547 instruct bytes_reverse_unsigned_short(rRegI dst) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6548 match(Set dst (ReverseBytesUS dst)); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6549 |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
6550 format %{ "bswapl $dst\n\t" |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6551 "shrl $dst,16\n\t" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6552 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6553 __ bswapl($dst$$Register); |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
6554 __ shrl($dst$$Register, 16); |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6555 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6556 ins_pipe( ialu_reg ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6557 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6558 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6559 instruct bytes_reverse_short(rRegI dst) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6560 match(Set dst (ReverseBytesS dst)); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6561 |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
6562 format %{ "bswapl $dst\n\t" |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6563 "sar $dst,16\n\t" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6564 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6565 __ bswapl($dst$$Register); |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
6566 __ sarl($dst$$Register, 16); |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6567 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6568 ins_pipe( ialu_reg ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6569 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6570 |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6571 //---------- Zeros Count Instructions ------------------------------------------ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6572 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6573 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6574 predicate(UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6575 match(Set dst (CountLeadingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6576 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6577 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6578 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6579 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6580 __ lzcntl($dst$$Register, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6581 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6582 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6583 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6584 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6585 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6586 predicate(!UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6587 match(Set dst (CountLeadingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6588 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6589 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6590 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6591 "jnz skip\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6592 "movl $dst, -1\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6593 "skip:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6594 "negl $dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6595 "addl $dst, 31" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6596 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6597 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6598 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6599 Label skip; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6600 __ bsrl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6601 __ jccb(Assembler::notZero, skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6602 __ movl(Rdst, -1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6603 __ bind(skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6604 __ negl(Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6605 __ addl(Rdst, BitsPerInt - 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6606 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6607 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6608 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6609 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6610 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6611 predicate(UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6612 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6613 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6614 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6615 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6616 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6617 __ lzcntq($dst$$Register, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6618 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6619 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6620 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6621 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6622 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6623 predicate(!UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6624 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6625 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6626 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6627 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6628 "jnz skip\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6629 "movl $dst, -1\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6630 "skip:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6631 "negl $dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6632 "addl $dst, 63" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6633 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6634 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6635 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6636 Label skip; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6637 __ bsrq(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6638 __ jccb(Assembler::notZero, skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6639 __ movl(Rdst, -1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6640 __ bind(skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6641 __ negl(Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6642 __ addl(Rdst, BitsPerLong - 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6643 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6644 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6645 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6646 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6647 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6648 match(Set dst (CountTrailingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6649 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6650 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6651 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6652 "jnz done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6653 "movl $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6654 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6655 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6656 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6657 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6658 __ bsfl(Rdst, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6659 __ jccb(Assembler::notZero, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6660 __ movl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6661 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6662 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6663 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6664 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6665 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6666 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6667 match(Set dst (CountTrailingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6668 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6669 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6670 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6671 "jnz done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6672 "movl $dst, 64\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6673 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6674 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6675 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6676 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6677 __ bsfq(Rdst, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6678 __ jccb(Assembler::notZero, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6679 __ movl(Rdst, BitsPerLong); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6680 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6681 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6682 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6683 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6684 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6685 |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6686 //---------- Population Count Instructions ------------------------------------- |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6687 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6688 instruct popCountI(rRegI dst, rRegI src) %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6689 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6690 match(Set dst (PopCountI src)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6691 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6692 format %{ "popcnt $dst, $src" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6693 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6694 __ popcntl($dst$$Register, $src$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6695 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6696 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6697 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6698 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6699 instruct popCountI_mem(rRegI dst, memory mem) %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6700 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6701 match(Set dst (PopCountI (LoadI mem))); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6702 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6703 format %{ "popcnt $dst, $mem" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6704 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6705 __ popcntl($dst$$Register, $mem$$Address); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6706 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6707 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6708 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6709 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6710 // Note: Long.bitCount(long) returns an int. |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6711 instruct popCountL(rRegI dst, rRegL src) %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6712 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6713 match(Set dst (PopCountL src)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6714 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6715 format %{ "popcnt $dst, $src" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6716 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6717 __ popcntq($dst$$Register, $src$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6718 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6719 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6720 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6721 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6722 // Note: Long.bitCount(long) returns an int. |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6723 instruct popCountL_mem(rRegI dst, memory mem) %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6724 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6725 match(Set dst (PopCountL (LoadL mem))); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6726 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6727 format %{ "popcnt $dst, $mem" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6728 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6729 __ popcntq($dst$$Register, $mem$$Address); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6730 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6731 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6732 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6733 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6734 |
| 0 | 6735 //----------MemBar Instructions----------------------------------------------- |
| 6736 // Memory barrier flavors | |
| 6737 | |
| 6738 instruct membar_acquire() | |
| 6739 %{ | |
| 6740 match(MemBarAcquire); | |
| 6741 ins_cost(0); | |
| 6742 | |
| 6743 size(0); | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6744 format %{ "MEMBAR-acquire ! (empty encoding)" %} |
| 0 | 6745 ins_encode(); |
| 6746 ins_pipe(empty); | |
| 6747 %} | |
| 6748 | |
| 6749 instruct membar_acquire_lock() | |
| 6750 %{ | |
|
3849
f1c12354c3f7
7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents:
3842
diff
changeset
|
6751 match(MemBarAcquireLock); |
| 0 | 6752 ins_cost(0); |
| 6753 | |
| 6754 size(0); | |
| 6755 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %} | |
| 6756 ins_encode(); | |
| 6757 ins_pipe(empty); | |
| 6758 %} | |
| 6759 | |
| 6760 instruct membar_release() | |
| 6761 %{ | |
| 6762 match(MemBarRelease); | |
| 6763 ins_cost(0); | |
| 6764 | |
| 6765 size(0); | |
|
671
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6822204: volatile fences should prefer lock:addl to actual mfence instructions
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647
diff
changeset
|
6766 format %{ "MEMBAR-release ! (empty encoding)" %} |
| 0 | 6767 ins_encode(); |
| 6768 ins_pipe(empty); | |
| 6769 %} | |
| 6770 | |
| 6771 instruct membar_release_lock() | |
| 6772 %{ | |
|
3849
f1c12354c3f7
7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents:
3842
diff
changeset
|
6773 match(MemBarReleaseLock); |
| 0 | 6774 ins_cost(0); |
| 6775 | |
| 6776 size(0); | |
| 6777 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %} | |
| 6778 ins_encode(); | |
| 6779 ins_pipe(empty); | |
| 6780 %} | |
| 6781 | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6782 instruct membar_volatile(rFlagsReg cr) %{ |
| 0 | 6783 match(MemBarVolatile); |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
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parents:
647
diff
changeset
|
6784 effect(KILL cr); |
| 0 | 6785 ins_cost(400); |
| 6786 | |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
6787 format %{ |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6788 $$template |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
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parents:
647
diff
changeset
|
6789 if (os::is_MP()) { |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
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parents:
647
diff
changeset
|
6790 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile" |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6791 } else { |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6792 $$emit$$"MEMBAR-volatile ! (empty encoding)" |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6793 } |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6794 %} |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6795 ins_encode %{ |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6796 __ membar(Assembler::StoreLoad); |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
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parents:
647
diff
changeset
|
6797 %} |
| 0 | 6798 ins_pipe(pipe_slow); |
| 6799 %} | |
| 6800 | |
| 6801 instruct unnecessary_membar_volatile() | |
| 6802 %{ | |
| 6803 match(MemBarVolatile); | |
| 6804 predicate(Matcher::post_store_load_barrier(n)); | |
| 6805 ins_cost(0); | |
| 6806 | |
| 6807 size(0); | |
| 6808 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %} | |
| 6809 ins_encode(); | |
| 6810 ins_pipe(empty); | |
| 6811 %} | |
| 6812 | |
| 6813 //----------Move Instructions-------------------------------------------------- | |
| 6814 | |
| 6815 instruct castX2P(rRegP dst, rRegL src) | |
| 6816 %{ | |
| 6817 match(Set dst (CastX2P src)); | |
| 6818 | |
| 6819 format %{ "movq $dst, $src\t# long->ptr" %} | |
| 4759 | 6820 ins_encode %{ |
| 6821 if ($dst$$reg != $src$$reg) { | |
| 6822 __ movptr($dst$$Register, $src$$Register); | |
| 6823 } | |
| 6824 %} | |
| 0 | 6825 ins_pipe(ialu_reg_reg); // XXX |
| 6826 %} | |
| 6827 | |
| 6828 instruct castP2X(rRegL dst, rRegP src) | |
| 6829 %{ | |
| 6830 match(Set dst (CastP2X src)); | |
| 6831 | |
| 6832 format %{ "movq $dst, $src\t# ptr -> long" %} | |
| 4759 | 6833 ins_encode %{ |
| 6834 if ($dst$$reg != $src$$reg) { | |
| 6835 __ movptr($dst$$Register, $src$$Register); | |
| 6836 } | |
| 6837 %} | |
| 0 | 6838 ins_pipe(ialu_reg_reg); // XXX |
| 6839 %} | |
| 6840 | |
|
113
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6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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71
diff
changeset
|
6841 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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71
diff
changeset
|
6842 // Convert oop pointer into compressed form |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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71
diff
changeset
|
6843 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{ |
|
221
1e026f8da827
6710487: More than half of JDI Regression tests hang with COOPs in -Xcomp mode
kvn
parents:
182
diff
changeset
|
6844 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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71
diff
changeset
|
6845 match(Set dst (EncodeP src)); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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71
diff
changeset
|
6846 effect(KILL cr); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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71
diff
changeset
|
6847 format %{ "encode_heap_oop $dst,$src" %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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71
diff
changeset
|
6848 ins_encode %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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71
diff
changeset
|
6849 Register s = $src$$Register; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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71
diff
changeset
|
6850 Register d = $dst$$Register; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6851 if (s != d) { |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6852 __ movq(d, s); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6853 } |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6854 __ encode_heap_oop(d); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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71
diff
changeset
|
6855 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6856 ins_pipe(ialu_reg_long); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6857 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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71
diff
changeset
|
6858 |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6859 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{ |
|
221
1e026f8da827
6710487: More than half of JDI Regression tests hang with COOPs in -Xcomp mode
kvn
parents:
182
diff
changeset
|
6860 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6861 match(Set dst (EncodeP src)); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6862 effect(KILL cr); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6863 format %{ "encode_heap_oop_not_null $dst,$src" %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6864 ins_encode %{ |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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624
diff
changeset
|
6865 __ encode_heap_oop_not_null($dst$$Register, $src$$Register); |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6866 %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6867 ins_pipe(ialu_reg_long); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6868 %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6869 |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6870 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{ |
|
182
44abbb0d4c18
6709093: Compressed Oops: reduce size of compiled methods
kvn
parents:
169
diff
changeset
|
6871 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && |
|
44abbb0d4c18
6709093: Compressed Oops: reduce size of compiled methods
kvn
parents:
169
diff
changeset
|
6872 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6873 match(Set dst (DecodeN src)); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6874 effect(KILL cr); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6875 format %{ "decode_heap_oop $dst,$src" %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6876 ins_encode %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6877 Register s = $src$$Register; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6878 Register d = $dst$$Register; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6879 if (s != d) { |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6880 __ movq(d, s); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6881 } |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6882 __ decode_heap_oop(d); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6883 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6884 ins_pipe(ialu_reg_long); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6885 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6886 |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1567
diff
changeset
|
6887 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{ |
|
182
44abbb0d4c18
6709093: Compressed Oops: reduce size of compiled methods
kvn
parents:
169
diff
changeset
|
6888 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || |
|
44abbb0d4c18
6709093: Compressed Oops: reduce size of compiled methods
kvn
parents:
169
diff
changeset
|
6889 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant); |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6890 match(Set dst (DecodeN src)); |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1567
diff
changeset
|
6891 effect(KILL cr); |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6892 format %{ "decode_heap_oop_not_null $dst,$src" %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6893 ins_encode %{ |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6894 Register s = $src$$Register; |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6895 Register d = $dst$$Register; |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6896 if (s != d) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6897 __ decode_heap_oop_not_null(d, s); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6898 } else { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6899 __ decode_heap_oop_not_null(d); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6900 } |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6901 %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6902 ins_pipe(ialu_reg_long); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6903 %} |
|
b130b98db9cf
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kvn
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113
diff
changeset
|
6904 |
|
113
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coleenp
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71
diff
changeset
|
6905 |
| 0 | 6906 //----------Conditional Move--------------------------------------------------- |
| 6907 // Jump | |
| 6908 // dummy instruction for generating temp registers | |
| 6909 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{ | |
| 6910 match(Jump (LShiftL switch_val shift)); | |
| 6911 ins_cost(350); | |
| 6912 predicate(false); | |
| 6913 effect(TEMP dest); | |
| 6914 | |
| 2008 | 6915 format %{ "leaq $dest, [$constantaddress]\n\t" |
| 0 | 6916 "jmp [$dest + $switch_val << $shift]\n\t" %} |
| 2008 | 6917 ins_encode %{ |
| 6918 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10 | |
| 6919 // to do that and the compiler is using that register as one it can allocate. | |
| 6920 // So we build it all by hand. | |
| 6921 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant); | |
| 6922 // ArrayAddress dispatch(table, index); | |
| 6923 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant); | |
| 6924 __ lea($dest$$Register, $constantaddress); | |
| 6925 __ jmp(dispatch); | |
| 6926 %} | |
| 0 | 6927 ins_pipe(pipe_jmp); |
| 6928 %} | |
| 6929 | |
| 6930 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{ | |
| 6931 match(Jump (AddL (LShiftL switch_val shift) offset)); | |
| 6932 ins_cost(350); | |
| 6933 effect(TEMP dest); | |
| 6934 | |
| 2008 | 6935 format %{ "leaq $dest, [$constantaddress]\n\t" |
| 0 | 6936 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %} |
| 2008 | 6937 ins_encode %{ |
| 6938 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10 | |
| 6939 // to do that and the compiler is using that register as one it can allocate. | |
| 6940 // So we build it all by hand. | |
| 6941 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant); | |
| 6942 // ArrayAddress dispatch(table, index); | |
| 6943 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant); | |
| 6944 __ lea($dest$$Register, $constantaddress); | |
| 6945 __ jmp(dispatch); | |
| 6946 %} | |
| 0 | 6947 ins_pipe(pipe_jmp); |
| 6948 %} | |
| 6949 | |
| 6950 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{ | |
| 6951 match(Jump switch_val); | |
| 6952 ins_cost(350); | |
| 6953 effect(TEMP dest); | |
| 6954 | |
| 2008 | 6955 format %{ "leaq $dest, [$constantaddress]\n\t" |
| 0 | 6956 "jmp [$dest + $switch_val]\n\t" %} |
| 2008 | 6957 ins_encode %{ |
| 6958 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10 | |
| 6959 // to do that and the compiler is using that register as one it can allocate. | |
| 6960 // So we build it all by hand. | |
| 6961 // Address index(noreg, switch_reg, Address::times_1); | |
| 6962 // ArrayAddress dispatch(table, index); | |
| 6963 Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1); | |
| 6964 __ lea($dest$$Register, $constantaddress); | |
| 6965 __ jmp(dispatch); | |
| 6966 %} | |
| 0 | 6967 ins_pipe(pipe_jmp); |
| 6968 %} | |
| 6969 | |
| 6970 // Conditional move | |
| 6971 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop) | |
| 6972 %{ | |
| 6973 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 6974 | |
| 6975 ins_cost(200); // XXX | |
| 6976 format %{ "cmovl$cop $dst, $src\t# signed, int" %} | |
| 6977 opcode(0x0F, 0x40); | |
| 6978 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 6979 ins_pipe(pipe_cmov_reg); | |
| 6980 %} | |
| 6981 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6982 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{ |
| 0 | 6983 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); |
| 6984 | |
| 6985 ins_cost(200); // XXX | |
| 6986 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %} | |
| 6987 opcode(0x0F, 0x40); | |
| 6988 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 6989 ins_pipe(pipe_cmov_reg); | |
| 6990 %} | |
| 6991 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6992 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6993 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); |
|
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|
6994 ins_cost(200); |
|
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never
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diff
changeset
|
6995 expand %{ |
|
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never
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403
diff
changeset
|
6996 cmovI_regU(cop, cr, dst, src); |
|
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403
diff
changeset
|
6997 %} |
|
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never
parents:
403
diff
changeset
|
6998 %} |
|
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never
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403
diff
changeset
|
6999 |
| 0 | 7000 // Conditional move |
|
415
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|
7001 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{ |
| 0 | 7002 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); |
| 7003 | |
| 7004 ins_cost(250); // XXX | |
| 7005 format %{ "cmovl$cop $dst, $src\t# signed, int" %} | |
| 7006 opcode(0x0F, 0x40); | |
| 7007 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
| 7008 ins_pipe(pipe_cmov_mem); | |
| 7009 %} | |
| 7010 | |
| 7011 // Conditional move | |
| 7012 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src) | |
| 7013 %{ | |
| 7014 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); | |
| 7015 | |
| 7016 ins_cost(250); // XXX | |
| 7017 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %} | |
| 7018 opcode(0x0F, 0x40); | |
| 7019 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
| 7020 ins_pipe(pipe_cmov_mem); | |
| 7021 %} | |
| 7022 | |
|
415
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|
7023 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{ |
|
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|
7024 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); |
|
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|
7025 ins_cost(250); |
|
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diff
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|
7026 expand %{ |
|
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diff
changeset
|
7027 cmovI_memU(cop, cr, dst, src); |
|
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diff
changeset
|
7028 %} |
|
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never
parents:
403
diff
changeset
|
7029 %} |
|
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diff
changeset
|
7030 |
| 0 | 7031 // Conditional move |
|
164
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|
7032 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop) |
|
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|
7033 %{ |
|
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|
7034 match(Set dst (CMoveN (Binary cop cr) (Binary dst src))); |
|
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|
7035 |
|
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changeset
|
7036 ins_cost(200); // XXX |
|
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|
7037 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %} |
|
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|
7038 opcode(0x0F, 0x40); |
|
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|
7039 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); |
|
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|
7040 ins_pipe(pipe_cmov_reg); |
|
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kvn
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|
7041 %} |
|
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kvn
parents:
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|
7042 |
|
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|
7043 // Conditional move |
|
415
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|
7044 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src) |
|
164
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|
7045 %{ |
|
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|
7046 match(Set dst (CMoveN (Binary cop cr) (Binary dst src))); |
|
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|
7047 |
|
c436414a719e
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changeset
|
7048 ins_cost(200); // XXX |
|
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|
7049 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %} |
|
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|
7050 opcode(0x0F, 0x40); |
|
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kvn
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changeset
|
7051 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); |
|
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|
7052 ins_pipe(pipe_cmov_reg); |
|
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|
7053 %} |
|
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|
7054 |
|
415
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changeset
|
7055 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{ |
|
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changeset
|
7056 match(Set dst (CMoveN (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
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never
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changeset
|
7057 ins_cost(200); |
|
4d9884b01ba6
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never
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diff
changeset
|
7058 expand %{ |
|
4d9884b01ba6
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diff
changeset
|
7059 cmovN_regU(cop, cr, dst, src); |
|
4d9884b01ba6
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diff
changeset
|
7060 %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7061 %} |
|
4d9884b01ba6
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never
parents:
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diff
changeset
|
7062 |
|
164
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|
7063 // Conditional move |
| 0 | 7064 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop) |
| 7065 %{ | |
| 7066 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 7067 | |
| 7068 ins_cost(200); // XXX | |
| 7069 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %} | |
| 7070 opcode(0x0F, 0x40); | |
| 7071 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 7072 ins_pipe(pipe_cmov_reg); // XXX | |
| 7073 %} | |
| 7074 | |
| 7075 // Conditional move | |
|
415
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changeset
|
7076 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src) |
| 0 | 7077 %{ |
| 7078 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 7079 | |
| 7080 ins_cost(200); // XXX | |
| 7081 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %} | |
| 7082 opcode(0x0F, 0x40); | |
| 7083 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 7084 ins_pipe(pipe_cmov_reg); // XXX | |
| 7085 %} | |
| 7086 | |
|
415
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parents:
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changeset
|
7087 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{ |
|
4d9884b01ba6
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changeset
|
7088 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
7089 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7090 expand %{ |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7091 cmovP_regU(cop, cr, dst, src); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7092 %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7093 %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7094 |
| 0 | 7095 // DISABLED: Requires the ADLC to emit a bottom_type call that |
| 7096 // correctly meets the two pointer arguments; one is an incoming | |
| 7097 // register but the other is a memory operand. ALSO appears to | |
| 7098 // be buggy with implicit null checks. | |
| 7099 // | |
| 7100 //// Conditional move | |
| 7101 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src) | |
| 7102 //%{ | |
| 7103 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 7104 // ins_cost(250); | |
| 7105 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 7106 // opcode(0x0F,0x40); | |
| 7107 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) ); | |
| 7108 // ins_pipe( pipe_cmov_mem ); | |
| 7109 //%} | |
| 7110 // | |
| 7111 //// Conditional move | |
| 7112 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src) | |
| 7113 //%{ | |
| 7114 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 7115 // ins_cost(250); | |
| 7116 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 7117 // opcode(0x0F,0x40); | |
| 7118 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) ); | |
| 7119 // ins_pipe( pipe_cmov_mem ); | |
| 7120 //%} | |
| 7121 | |
| 7122 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src) | |
| 7123 %{ | |
| 7124 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 7125 | |
| 7126 ins_cost(200); // XXX | |
| 7127 format %{ "cmovq$cop $dst, $src\t# signed, long" %} | |
| 7128 opcode(0x0F, 0x40); | |
| 7129 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 7130 ins_pipe(pipe_cmov_reg); // XXX | |
| 7131 %} | |
| 7132 | |
| 7133 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src) | |
| 7134 %{ | |
| 7135 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src)))); | |
| 7136 | |
| 7137 ins_cost(200); // XXX | |
| 7138 format %{ "cmovq$cop $dst, $src\t# signed, long" %} | |
| 7139 opcode(0x0F, 0x40); | |
| 7140 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
| 7141 ins_pipe(pipe_cmov_mem); // XXX | |
| 7142 %} | |
| 7143 | |
| 7144 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src) | |
| 7145 %{ | |
| 7146 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 7147 | |
| 7148 ins_cost(200); // XXX | |
| 7149 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %} | |
| 7150 opcode(0x0F, 0x40); | |
| 7151 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 7152 ins_pipe(pipe_cmov_reg); // XXX | |
| 7153 %} | |
| 7154 | |
|
415
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changeset
|
7155 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{ |
|
4d9884b01ba6
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diff
changeset
|
7156 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
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403
diff
changeset
|
7157 ins_cost(200); |
|
4d9884b01ba6
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never
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403
diff
changeset
|
7158 expand %{ |
|
4d9884b01ba6
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diff
changeset
|
7159 cmovL_regU(cop, cr, dst, src); |
|
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diff
changeset
|
7160 %} |
|
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parents:
403
diff
changeset
|
7161 %} |
|
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changeset
|
7162 |
| 0 | 7163 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src) |
| 7164 %{ | |
| 7165 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src)))); | |
| 7166 | |
| 7167 ins_cost(200); // XXX | |
| 7168 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %} | |
| 7169 opcode(0x0F, 0x40); | |
| 7170 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
| 7171 ins_pipe(pipe_cmov_mem); // XXX | |
| 7172 %} | |
| 7173 | |
|
415
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changeset
|
7174 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{ |
|
4d9884b01ba6
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|
7175 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src)))); |
|
4d9884b01ba6
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diff
changeset
|
7176 ins_cost(200); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7177 expand %{ |
|
4d9884b01ba6
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403
diff
changeset
|
7178 cmovL_memU(cop, cr, dst, src); |
|
4d9884b01ba6
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diff
changeset
|
7179 %} |
|
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diff
changeset
|
7180 %} |
|
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diff
changeset
|
7181 |
| 0 | 7182 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src) |
| 7183 %{ | |
| 7184 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 7185 | |
| 7186 ins_cost(200); // XXX | |
| 7187 format %{ "jn$cop skip\t# signed cmove float\n\t" | |
| 7188 "movss $dst, $src\n" | |
| 7189 "skip:" %} | |
| 4759 | 7190 ins_encode %{ |
| 7191 Label Lskip; | |
| 7192 // Invert sense of branch from sense of CMOV | |
| 7193 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
| 7194 __ movflt($dst$$XMMRegister, $src$$XMMRegister); | |
| 7195 __ bind(Lskip); | |
| 7196 %} | |
| 0 | 7197 ins_pipe(pipe_slow); |
| 7198 %} | |
| 7199 | |
| 7200 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src) | |
| 7201 // %{ | |
| 7202 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src)))); | |
| 7203 | |
| 7204 // ins_cost(200); // XXX | |
| 7205 // format %{ "jn$cop skip\t# signed cmove float\n\t" | |
| 7206 // "movss $dst, $src\n" | |
| 7207 // "skip:" %} | |
| 7208 // ins_encode(enc_cmovf_mem_branch(cop, dst, src)); | |
| 7209 // ins_pipe(pipe_slow); | |
| 7210 // %} | |
| 7211 | |
| 7212 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src) | |
| 7213 %{ | |
| 7214 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 7215 | |
| 7216 ins_cost(200); // XXX | |
| 7217 format %{ "jn$cop skip\t# unsigned cmove float\n\t" | |
| 7218 "movss $dst, $src\n" | |
| 7219 "skip:" %} | |
| 4759 | 7220 ins_encode %{ |
| 7221 Label Lskip; | |
| 7222 // Invert sense of branch from sense of CMOV | |
| 7223 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
| 7224 __ movflt($dst$$XMMRegister, $src$$XMMRegister); | |
| 7225 __ bind(Lskip); | |
| 7226 %} | |
| 0 | 7227 ins_pipe(pipe_slow); |
| 7228 %} | |
| 7229 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7230 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7231 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7232 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7233 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7234 cmovF_regU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7235 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7236 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7237 |
| 0 | 7238 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src) |
| 7239 %{ | |
| 7240 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 7241 | |
| 7242 ins_cost(200); // XXX | |
| 7243 format %{ "jn$cop skip\t# signed cmove double\n\t" | |
| 7244 "movsd $dst, $src\n" | |
| 7245 "skip:" %} | |
| 4759 | 7246 ins_encode %{ |
| 7247 Label Lskip; | |
| 7248 // Invert sense of branch from sense of CMOV | |
| 7249 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
| 7250 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); | |
| 7251 __ bind(Lskip); | |
| 7252 %} | |
| 0 | 7253 ins_pipe(pipe_slow); |
| 7254 %} | |
| 7255 | |
| 7256 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src) | |
| 7257 %{ | |
| 7258 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 7259 | |
| 7260 ins_cost(200); // XXX | |
| 7261 format %{ "jn$cop skip\t# unsigned cmove double\n\t" | |
| 7262 "movsd $dst, $src\n" | |
| 7263 "skip:" %} | |
| 4759 | 7264 ins_encode %{ |
| 7265 Label Lskip; | |
| 7266 // Invert sense of branch from sense of CMOV | |
| 7267 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
| 7268 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); | |
| 7269 __ bind(Lskip); | |
| 7270 %} | |
| 0 | 7271 ins_pipe(pipe_slow); |
| 7272 %} | |
| 7273 | |
|
415
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7274 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7275 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7276 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7277 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7278 cmovD_regU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7279 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7280 %} |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
7281 |
| 0 | 7282 //----------Arithmetic Instructions-------------------------------------------- |
| 7283 //----------Addition Instructions---------------------------------------------- | |
| 7284 | |
| 7285 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 7286 %{ | |
| 7287 match(Set dst (AddI dst src)); | |
| 7288 effect(KILL cr); | |
| 7289 | |
| 7290 format %{ "addl $dst, $src\t# int" %} | |
| 7291 opcode(0x03); | |
| 7292 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 7293 ins_pipe(ialu_reg_reg); | |
| 7294 %} | |
| 7295 | |
| 7296 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 7297 %{ | |
| 7298 match(Set dst (AddI dst src)); | |
| 7299 effect(KILL cr); | |
| 7300 | |
| 7301 format %{ "addl $dst, $src\t# int" %} | |
| 7302 opcode(0x81, 0x00); /* /0 id */ | |
| 7303 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 7304 ins_pipe( ialu_reg ); | |
| 7305 %} | |
| 7306 | |
| 7307 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 7308 %{ | |
| 7309 match(Set dst (AddI dst (LoadI src))); | |
| 7310 effect(KILL cr); | |
| 7311 | |
| 7312 ins_cost(125); // XXX | |
| 7313 format %{ "addl $dst, $src\t# int" %} | |
| 7314 opcode(0x03); | |
| 7315 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 7316 ins_pipe(ialu_reg_mem); | |
| 7317 %} | |
| 7318 | |
| 7319 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 7320 %{ | |
| 7321 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7322 effect(KILL cr); | |
| 7323 | |
| 7324 ins_cost(150); // XXX | |
| 7325 format %{ "addl $dst, $src\t# int" %} | |
| 7326 opcode(0x01); /* Opcode 01 /r */ | |
| 7327 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 7328 ins_pipe(ialu_mem_reg); | |
| 7329 %} | |
| 7330 | |
| 7331 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 7332 %{ | |
| 7333 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7334 effect(KILL cr); | |
| 7335 | |
| 7336 ins_cost(125); // XXX | |
| 7337 format %{ "addl $dst, $src\t# int" %} | |
| 7338 opcode(0x81); /* Opcode 81 /0 id */ | |
| 7339 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src)); | |
| 7340 ins_pipe(ialu_mem_imm); | |
| 7341 %} | |
| 7342 | |
| 7343 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr) | |
| 7344 %{ | |
| 7345 predicate(UseIncDec); | |
| 7346 match(Set dst (AddI dst src)); | |
| 7347 effect(KILL cr); | |
| 7348 | |
| 7349 format %{ "incl $dst\t# int" %} | |
| 7350 opcode(0xFF, 0x00); // FF /0 | |
| 7351 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 7352 ins_pipe(ialu_reg); | |
| 7353 %} | |
| 7354 | |
| 7355 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr) | |
| 7356 %{ | |
| 7357 predicate(UseIncDec); | |
| 7358 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7359 effect(KILL cr); | |
| 7360 | |
| 7361 ins_cost(125); // XXX | |
| 7362 format %{ "incl $dst\t# int" %} | |
| 7363 opcode(0xFF); /* Opcode FF /0 */ | |
| 7364 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst)); | |
| 7365 ins_pipe(ialu_mem_imm); | |
| 7366 %} | |
| 7367 | |
| 7368 // XXX why does that use AddI | |
| 7369 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr) | |
| 7370 %{ | |
| 7371 predicate(UseIncDec); | |
| 7372 match(Set dst (AddI dst src)); | |
| 7373 effect(KILL cr); | |
| 7374 | |
| 7375 format %{ "decl $dst\t# int" %} | |
| 7376 opcode(0xFF, 0x01); // FF /1 | |
| 7377 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 7378 ins_pipe(ialu_reg); | |
| 7379 %} | |
| 7380 | |
| 7381 // XXX why does that use AddI | |
| 7382 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr) | |
| 7383 %{ | |
| 7384 predicate(UseIncDec); | |
| 7385 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7386 effect(KILL cr); | |
| 7387 | |
| 7388 ins_cost(125); // XXX | |
| 7389 format %{ "decl $dst\t# int" %} | |
| 7390 opcode(0xFF); /* Opcode FF /1 */ | |
| 7391 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst)); | |
| 7392 ins_pipe(ialu_mem_imm); | |
| 7393 %} | |
| 7394 | |
| 7395 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1) | |
| 7396 %{ | |
| 7397 match(Set dst (AddI src0 src1)); | |
| 7398 | |
| 7399 ins_cost(110); | |
| 7400 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %} | |
| 7401 opcode(0x8D); /* 0x8D /r */ | |
| 7402 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX | |
| 7403 ins_pipe(ialu_reg_reg); | |
| 7404 %} | |
| 7405 | |
| 7406 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 7407 %{ | |
| 7408 match(Set dst (AddL dst src)); | |
| 7409 effect(KILL cr); | |
| 7410 | |
| 7411 format %{ "addq $dst, $src\t# long" %} | |
| 7412 opcode(0x03); | |
| 7413 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 7414 ins_pipe(ialu_reg_reg); | |
| 7415 %} | |
| 7416 | |
| 7417 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
| 7418 %{ | |
| 7419 match(Set dst (AddL dst src)); | |
| 7420 effect(KILL cr); | |
| 7421 | |
| 7422 format %{ "addq $dst, $src\t# long" %} | |
| 7423 opcode(0x81, 0x00); /* /0 id */ | |
| 7424 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 7425 ins_pipe( ialu_reg ); | |
| 7426 %} | |
| 7427 | |
| 7428 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 7429 %{ | |
| 7430 match(Set dst (AddL dst (LoadL src))); | |
| 7431 effect(KILL cr); | |
| 7432 | |
| 7433 ins_cost(125); // XXX | |
| 7434 format %{ "addq $dst, $src\t# long" %} | |
| 7435 opcode(0x03); | |
| 7436 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 7437 ins_pipe(ialu_reg_mem); | |
| 7438 %} | |
| 7439 | |
| 7440 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 7441 %{ | |
| 7442 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
| 7443 effect(KILL cr); | |
| 7444 | |
| 7445 ins_cost(150); // XXX | |
| 7446 format %{ "addq $dst, $src\t# long" %} | |
| 7447 opcode(0x01); /* Opcode 01 /r */ | |
| 7448 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 7449 ins_pipe(ialu_mem_reg); | |
| 7450 %} | |
| 7451 | |
| 7452 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 7453 %{ | |
| 7454 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
| 7455 effect(KILL cr); | |
| 7456 | |
| 7457 ins_cost(125); // XXX | |
| 7458 format %{ "addq $dst, $src\t# long" %} | |
| 7459 opcode(0x81); /* Opcode 81 /0 id */ | |
| 7460 ins_encode(REX_mem_wide(dst), | |
| 7461 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src)); | |
| 7462 ins_pipe(ialu_mem_imm); | |
| 7463 %} | |
| 7464 | |
| 7465 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr) | |
| 7466 %{ | |
| 7467 predicate(UseIncDec); | |
| 7468 match(Set dst (AddL dst src)); | |
| 7469 effect(KILL cr); | |
| 7470 | |
| 7471 format %{ "incq $dst\t# long" %} | |
| 7472 opcode(0xFF, 0x00); // FF /0 | |
| 7473 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 7474 ins_pipe(ialu_reg); | |
| 7475 %} | |
| 7476 | |
| 7477 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr) | |
| 7478 %{ | |
| 7479 predicate(UseIncDec); | |
| 7480 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
| 7481 effect(KILL cr); | |
| 7482 | |
| 7483 ins_cost(125); // XXX | |
| 7484 format %{ "incq $dst\t# long" %} | |
| 7485 opcode(0xFF); /* Opcode FF /0 */ | |
| 7486 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst)); | |
| 7487 ins_pipe(ialu_mem_imm); | |
| 7488 %} | |
| 7489 | |
| 7490 // XXX why does that use AddL | |
| 7491 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr) | |
| 7492 %{ | |
| 7493 predicate(UseIncDec); | |
| 7494 match(Set dst (AddL dst src)); | |
| 7495 effect(KILL cr); | |
| 7496 | |
| 7497 format %{ "decq $dst\t# long" %} | |
| 7498 opcode(0xFF, 0x01); // FF /1 | |
| 7499 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 7500 ins_pipe(ialu_reg); | |
| 7501 %} | |
| 7502 | |
| 7503 // XXX why does that use AddL | |
| 7504 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr) | |
| 7505 %{ | |
| 7506 predicate(UseIncDec); | |
| 7507 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
| 7508 effect(KILL cr); | |
| 7509 | |
| 7510 ins_cost(125); // XXX | |
| 7511 format %{ "decq $dst\t# long" %} | |
| 7512 opcode(0xFF); /* Opcode FF /1 */ | |
| 7513 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst)); | |
| 7514 ins_pipe(ialu_mem_imm); | |
| 7515 %} | |
| 7516 | |
| 7517 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1) | |
| 7518 %{ | |
| 7519 match(Set dst (AddL src0 src1)); | |
| 7520 | |
| 7521 ins_cost(110); | |
| 7522 format %{ "leaq $dst, [$src0 + $src1]\t# long" %} | |
| 7523 opcode(0x8D); /* 0x8D /r */ | |
| 7524 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX | |
| 7525 ins_pipe(ialu_reg_reg); | |
| 7526 %} | |
| 7527 | |
| 7528 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr) | |
| 7529 %{ | |
| 7530 match(Set dst (AddP dst src)); | |
| 7531 effect(KILL cr); | |
| 7532 | |
| 7533 format %{ "addq $dst, $src\t# ptr" %} | |
| 7534 opcode(0x03); | |
| 7535 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 7536 ins_pipe(ialu_reg_reg); | |
| 7537 %} | |
| 7538 | |
| 7539 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr) | |
| 7540 %{ | |
| 7541 match(Set dst (AddP dst src)); | |
| 7542 effect(KILL cr); | |
| 7543 | |
| 7544 format %{ "addq $dst, $src\t# ptr" %} | |
| 7545 opcode(0x81, 0x00); /* /0 id */ | |
| 7546 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 7547 ins_pipe( ialu_reg ); | |
| 7548 %} | |
| 7549 | |
| 7550 // XXX addP mem ops ???? | |
| 7551 | |
| 7552 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1) | |
| 7553 %{ | |
| 7554 match(Set dst (AddP src0 src1)); | |
| 7555 | |
| 7556 ins_cost(110); | |
| 7557 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %} | |
| 7558 opcode(0x8D); /* 0x8D /r */ | |
| 7559 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX | |
| 7560 ins_pipe(ialu_reg_reg); | |
| 7561 %} | |
| 7562 | |
| 7563 instruct checkCastPP(rRegP dst) | |
| 7564 %{ | |
| 7565 match(Set dst (CheckCastPP dst)); | |
| 7566 | |
| 7567 size(0); | |
| 7568 format %{ "# checkcastPP of $dst" %} | |
| 7569 ins_encode(/* empty encoding */); | |
| 7570 ins_pipe(empty); | |
| 7571 %} | |
| 7572 | |
| 7573 instruct castPP(rRegP dst) | |
| 7574 %{ | |
| 7575 match(Set dst (CastPP dst)); | |
| 7576 | |
| 7577 size(0); | |
| 7578 format %{ "# castPP of $dst" %} | |
| 7579 ins_encode(/* empty encoding */); | |
| 7580 ins_pipe(empty); | |
| 7581 %} | |
| 7582 | |
| 7583 instruct castII(rRegI dst) | |
| 7584 %{ | |
| 7585 match(Set dst (CastII dst)); | |
| 7586 | |
| 7587 size(0); | |
| 7588 format %{ "# castII of $dst" %} | |
| 7589 ins_encode(/* empty encoding */); | |
| 7590 ins_cost(0); | |
| 7591 ins_pipe(empty); | |
| 7592 %} | |
| 7593 | |
| 7594 // LoadP-locked same as a regular LoadP when used with compare-swap | |
| 7595 instruct loadPLocked(rRegP dst, memory mem) | |
| 7596 %{ | |
| 7597 match(Set dst (LoadPLocked mem)); | |
| 7598 | |
| 7599 ins_cost(125); // XXX | |
| 7600 format %{ "movq $dst, $mem\t# ptr locked" %} | |
| 7601 opcode(0x8B); | |
| 7602 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 7603 ins_pipe(ialu_reg_mem); // XXX | |
| 7604 %} | |
| 7605 | |
| 7606 // LoadL-locked - same as a regular LoadL when used with compare-swap | |
| 7607 instruct loadLLocked(rRegL dst, memory mem) | |
| 7608 %{ | |
| 7609 match(Set dst (LoadLLocked mem)); | |
| 7610 | |
| 7611 ins_cost(125); // XXX | |
| 7612 format %{ "movq $dst, $mem\t# long locked" %} | |
| 7613 opcode(0x8B); | |
| 7614 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 7615 ins_pipe(ialu_reg_mem); // XXX | |
| 7616 %} | |
| 7617 | |
| 7618 // Conditional-store of the updated heap-top. | |
| 7619 // Used during allocation of the shared heap. | |
| 7620 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel. | |
| 7621 | |
| 7622 instruct storePConditional(memory heap_top_ptr, | |
| 7623 rax_RegP oldval, rRegP newval, | |
| 7624 rFlagsReg cr) | |
| 7625 %{ | |
| 7626 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval))); | |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
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2401
diff
changeset
|
7627 |
| 0 | 7628 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) " |
| 7629 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %} | |
| 7630 opcode(0x0F, 0xB1); | |
| 7631 ins_encode(lock_prefix, | |
| 7632 REX_reg_mem_wide(newval, heap_top_ptr), | |
| 7633 OpcP, OpcS, | |
| 7634 reg_mem(newval, heap_top_ptr)); | |
| 7635 ins_pipe(pipe_cmpxchg); | |
| 7636 %} | |
| 7637 | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
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diff
changeset
|
7638 // Conditional-store of an int value. |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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parents:
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diff
changeset
|
7639 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG. |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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parents:
415
diff
changeset
|
7640 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr) |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7641 %{ |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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415
diff
changeset
|
7642 match(Set cr (StoreIConditional mem (Binary oldval newval))); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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parents:
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diff
changeset
|
7643 effect(KILL oldval); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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diff
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|
7644 |
|
a1980da045cc
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7645 format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %} |
| 0 | 7646 opcode(0x0F, 0xB1); |
| 7647 ins_encode(lock_prefix, | |
|
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7648 REX_reg_mem(newval, mem), |
| 0 | 7649 OpcP, OpcS, |
|
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7650 reg_mem(newval, mem)); |
| 0 | 7651 ins_pipe(pipe_cmpxchg); |
| 7652 %} | |
| 7653 | |
|
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7654 // Conditional-store of a long value. |
|
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7655 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG. |
|
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|
7656 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr) |
|
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7657 %{ |
|
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7658 match(Set cr (StoreLConditional mem (Binary oldval newval))); |
|
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|
7659 effect(KILL oldval); |
|
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|
7660 |
|
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|
7661 format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %} |
| 0 | 7662 opcode(0x0F, 0xB1); |
| 7663 ins_encode(lock_prefix, | |
|
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7664 REX_reg_mem_wide(newval, mem), |
| 0 | 7665 OpcP, OpcS, |
|
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|
7666 reg_mem(newval, mem)); |
| 0 | 7667 ins_pipe(pipe_cmpxchg); |
| 7668 %} | |
| 7669 | |
|
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7670 |
|
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7671 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them |
| 0 | 7672 instruct compareAndSwapP(rRegI res, |
| 7673 memory mem_ptr, | |
| 7674 rax_RegP oldval, rRegP newval, | |
| 7675 rFlagsReg cr) | |
| 7676 %{ | |
| 7677 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); | |
| 7678 effect(KILL cr, KILL oldval); | |
| 7679 | |
| 7680 format %{ "cmpxchgq $mem_ptr,$newval\t# " | |
| 7681 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" | |
| 7682 "sete $res\n\t" | |
| 7683 "movzbl $res, $res" %} | |
| 7684 opcode(0x0F, 0xB1); | |
| 7685 ins_encode(lock_prefix, | |
| 7686 REX_reg_mem_wide(newval, mem_ptr), | |
| 7687 OpcP, OpcS, | |
| 7688 reg_mem(newval, mem_ptr), | |
| 7689 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete | |
| 7690 REX_reg_breg(res, res), // movzbl | |
| 7691 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); | |
| 7692 ins_pipe( pipe_cmpxchg ); | |
| 7693 %} | |
| 7694 | |
| 7695 instruct compareAndSwapL(rRegI res, | |
| 7696 memory mem_ptr, | |
| 7697 rax_RegL oldval, rRegL newval, | |
| 7698 rFlagsReg cr) | |
| 7699 %{ | |
| 7700 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); | |
| 7701 effect(KILL cr, KILL oldval); | |
| 7702 | |
| 7703 format %{ "cmpxchgq $mem_ptr,$newval\t# " | |
| 7704 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" | |
| 7705 "sete $res\n\t" | |
| 7706 "movzbl $res, $res" %} | |
| 7707 opcode(0x0F, 0xB1); | |
| 7708 ins_encode(lock_prefix, | |
| 7709 REX_reg_mem_wide(newval, mem_ptr), | |
| 7710 OpcP, OpcS, | |
| 7711 reg_mem(newval, mem_ptr), | |
| 7712 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete | |
| 7713 REX_reg_breg(res, res), // movzbl | |
| 7714 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); | |
| 7715 ins_pipe( pipe_cmpxchg ); | |
| 7716 %} | |
| 7717 | |
| 7718 instruct compareAndSwapI(rRegI res, | |
| 7719 memory mem_ptr, | |
| 7720 rax_RegI oldval, rRegI newval, | |
| 7721 rFlagsReg cr) | |
| 7722 %{ | |
| 7723 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); | |
| 7724 effect(KILL cr, KILL oldval); | |
| 7725 | |
| 7726 format %{ "cmpxchgl $mem_ptr,$newval\t# " | |
| 7727 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" | |
| 7728 "sete $res\n\t" | |
| 7729 "movzbl $res, $res" %} | |
| 7730 opcode(0x0F, 0xB1); | |
| 7731 ins_encode(lock_prefix, | |
| 7732 REX_reg_mem(newval, mem_ptr), | |
| 7733 OpcP, OpcS, | |
| 7734 reg_mem(newval, mem_ptr), | |
| 7735 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete | |
| 7736 REX_reg_breg(res, res), // movzbl | |
| 7737 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); | |
| 7738 ins_pipe( pipe_cmpxchg ); | |
| 7739 %} | |
| 7740 | |
| 7741 | |
|
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7742 instruct compareAndSwapN(rRegI res, |
|
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7743 memory mem_ptr, |
|
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7744 rax_RegN oldval, rRegN newval, |
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7745 rFlagsReg cr) %{ |
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7746 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); |
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7747 effect(KILL cr, KILL oldval); |
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7748 |
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7749 format %{ "cmpxchgl $mem_ptr,$newval\t# " |
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7750 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" |
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|
7751 "sete $res\n\t" |
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7752 "movzbl $res, $res" %} |
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7753 opcode(0x0F, 0xB1); |
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7754 ins_encode(lock_prefix, |
|
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7755 REX_reg_mem(newval, mem_ptr), |
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7756 OpcP, OpcS, |
|
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7757 reg_mem(newval, mem_ptr), |
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7758 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete |
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7759 REX_reg_breg(res, res), // movzbl |
|
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7760 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); |
|
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7761 ins_pipe( pipe_cmpxchg ); |
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7762 %} |
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7763 |
| 0 | 7764 //----------Subtraction Instructions------------------------------------------- |
| 7765 | |
| 7766 // Integer Subtraction Instructions | |
| 7767 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 7768 %{ | |
| 7769 match(Set dst (SubI dst src)); | |
| 7770 effect(KILL cr); | |
| 7771 | |
| 7772 format %{ "subl $dst, $src\t# int" %} | |
| 7773 opcode(0x2B); | |
| 7774 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 7775 ins_pipe(ialu_reg_reg); | |
| 7776 %} | |
| 7777 | |
| 7778 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 7779 %{ | |
| 7780 match(Set dst (SubI dst src)); | |
| 7781 effect(KILL cr); | |
| 7782 | |
| 7783 format %{ "subl $dst, $src\t# int" %} | |
| 7784 opcode(0x81, 0x05); /* Opcode 81 /5 */ | |
| 7785 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 7786 ins_pipe(ialu_reg); | |
| 7787 %} | |
| 7788 | |
| 7789 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 7790 %{ | |
| 7791 match(Set dst (SubI dst (LoadI src))); | |
| 7792 effect(KILL cr); | |
| 7793 | |
| 7794 ins_cost(125); | |
| 7795 format %{ "subl $dst, $src\t# int" %} | |
| 7796 opcode(0x2B); | |
| 7797 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 7798 ins_pipe(ialu_reg_mem); | |
| 7799 %} | |
| 7800 | |
| 7801 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 7802 %{ | |
| 7803 match(Set dst (StoreI dst (SubI (LoadI dst) src))); | |
| 7804 effect(KILL cr); | |
| 7805 | |
| 7806 ins_cost(150); | |
| 7807 format %{ "subl $dst, $src\t# int" %} | |
| 7808 opcode(0x29); /* Opcode 29 /r */ | |
| 7809 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 7810 ins_pipe(ialu_mem_reg); | |
| 7811 %} | |
| 7812 | |
| 7813 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 7814 %{ | |
| 7815 match(Set dst (StoreI dst (SubI (LoadI dst) src))); | |
| 7816 effect(KILL cr); | |
| 7817 | |
| 7818 ins_cost(125); // XXX | |
| 7819 format %{ "subl $dst, $src\t# int" %} | |
| 7820 opcode(0x81); /* Opcode 81 /5 id */ | |
| 7821 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src)); | |
| 7822 ins_pipe(ialu_mem_imm); | |
| 7823 %} | |
| 7824 | |
| 7825 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 7826 %{ | |
| 7827 match(Set dst (SubL dst src)); | |
| 7828 effect(KILL cr); | |
| 7829 | |
| 7830 format %{ "subq $dst, $src\t# long" %} | |
| 7831 opcode(0x2B); | |
| 7832 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 7833 ins_pipe(ialu_reg_reg); | |
| 7834 %} | |
| 7835 | |
| 7836 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr) | |
| 7837 %{ | |
| 7838 match(Set dst (SubL dst src)); | |
| 7839 effect(KILL cr); | |
| 7840 | |
| 7841 format %{ "subq $dst, $src\t# long" %} | |
| 7842 opcode(0x81, 0x05); /* Opcode 81 /5 */ | |
| 7843 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 7844 ins_pipe(ialu_reg); | |
| 7845 %} | |
| 7846 | |
| 7847 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 7848 %{ | |
| 7849 match(Set dst (SubL dst (LoadL src))); | |
| 7850 effect(KILL cr); | |
| 7851 | |
| 7852 ins_cost(125); | |
| 7853 format %{ "subq $dst, $src\t# long" %} | |
| 7854 opcode(0x2B); | |
| 7855 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 7856 ins_pipe(ialu_reg_mem); | |
| 7857 %} | |
| 7858 | |
| 7859 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 7860 %{ | |
| 7861 match(Set dst (StoreL dst (SubL (LoadL dst) src))); | |
| 7862 effect(KILL cr); | |
| 7863 | |
| 7864 ins_cost(150); | |
| 7865 format %{ "subq $dst, $src\t# long" %} | |
| 7866 opcode(0x29); /* Opcode 29 /r */ | |
| 7867 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 7868 ins_pipe(ialu_mem_reg); | |
| 7869 %} | |
| 7870 | |
| 7871 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 7872 %{ | |
| 7873 match(Set dst (StoreL dst (SubL (LoadL dst) src))); | |
| 7874 effect(KILL cr); | |
| 7875 | |
| 7876 ins_cost(125); // XXX | |
| 7877 format %{ "subq $dst, $src\t# long" %} | |
| 7878 opcode(0x81); /* Opcode 81 /5 id */ | |
| 7879 ins_encode(REX_mem_wide(dst), | |
| 7880 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src)); | |
| 7881 ins_pipe(ialu_mem_imm); | |
| 7882 %} | |
| 7883 | |
| 7884 // Subtract from a pointer | |
| 7885 // XXX hmpf??? | |
| 7886 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr) | |
| 7887 %{ | |
| 7888 match(Set dst (AddP dst (SubI zero src))); | |
| 7889 effect(KILL cr); | |
| 7890 | |
| 7891 format %{ "subq $dst, $src\t# ptr - int" %} | |
| 7892 opcode(0x2B); | |
| 7893 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 7894 ins_pipe(ialu_reg_reg); | |
| 7895 %} | |
| 7896 | |
| 7897 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr) | |
| 7898 %{ | |
| 7899 match(Set dst (SubI zero dst)); | |
| 7900 effect(KILL cr); | |
| 7901 | |
| 7902 format %{ "negl $dst\t# int" %} | |
| 7903 opcode(0xF7, 0x03); // Opcode F7 /3 | |
| 7904 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 7905 ins_pipe(ialu_reg); | |
| 7906 %} | |
| 7907 | |
| 7908 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr) | |
| 7909 %{ | |
| 7910 match(Set dst (StoreI dst (SubI zero (LoadI dst)))); | |
| 7911 effect(KILL cr); | |
| 7912 | |
| 7913 format %{ "negl $dst\t# int" %} | |
| 7914 opcode(0xF7, 0x03); // Opcode F7 /3 | |
| 7915 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 7916 ins_pipe(ialu_reg); | |
| 7917 %} | |
| 7918 | |
| 7919 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr) | |
| 7920 %{ | |
| 7921 match(Set dst (SubL zero dst)); | |
| 7922 effect(KILL cr); | |
| 7923 | |
| 7924 format %{ "negq $dst\t# long" %} | |
| 7925 opcode(0xF7, 0x03); // Opcode F7 /3 | |
| 7926 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 7927 ins_pipe(ialu_reg); | |
| 7928 %} | |
| 7929 | |
| 7930 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr) | |
| 7931 %{ | |
| 7932 match(Set dst (StoreL dst (SubL zero (LoadL dst)))); | |
| 7933 effect(KILL cr); | |
| 7934 | |
| 7935 format %{ "negq $dst\t# long" %} | |
| 7936 opcode(0xF7, 0x03); // Opcode F7 /3 | |
| 7937 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 7938 ins_pipe(ialu_reg); | |
| 7939 %} | |
| 7940 | |
| 7941 | |
| 7942 //----------Multiplication/Division Instructions------------------------------- | |
| 7943 // Integer Multiplication Instructions | |
| 7944 // Multiply Register | |
| 7945 | |
| 7946 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 7947 %{ | |
| 7948 match(Set dst (MulI dst src)); | |
| 7949 effect(KILL cr); | |
| 7950 | |
| 7951 ins_cost(300); | |
| 7952 format %{ "imull $dst, $src\t# int" %} | |
| 7953 opcode(0x0F, 0xAF); | |
| 7954 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 7955 ins_pipe(ialu_reg_reg_alu0); | |
| 7956 %} | |
| 7957 | |
| 7958 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr) | |
| 7959 %{ | |
| 7960 match(Set dst (MulI src imm)); | |
| 7961 effect(KILL cr); | |
| 7962 | |
| 7963 ins_cost(300); | |
| 7964 format %{ "imull $dst, $src, $imm\t# int" %} | |
| 7965 opcode(0x69); /* 69 /r id */ | |
| 7966 ins_encode(REX_reg_reg(dst, src), | |
| 7967 OpcSE(imm), reg_reg(dst, src), Con8or32(imm)); | |
| 7968 ins_pipe(ialu_reg_reg_alu0); | |
| 7969 %} | |
| 7970 | |
| 7971 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 7972 %{ | |
| 7973 match(Set dst (MulI dst (LoadI src))); | |
| 7974 effect(KILL cr); | |
| 7975 | |
| 7976 ins_cost(350); | |
| 7977 format %{ "imull $dst, $src\t# int" %} | |
| 7978 opcode(0x0F, 0xAF); | |
| 7979 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src)); | |
| 7980 ins_pipe(ialu_reg_mem_alu0); | |
| 7981 %} | |
| 7982 | |
| 7983 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr) | |
| 7984 %{ | |
| 7985 match(Set dst (MulI (LoadI src) imm)); | |
| 7986 effect(KILL cr); | |
| 7987 | |
| 7988 ins_cost(300); | |
| 7989 format %{ "imull $dst, $src, $imm\t# int" %} | |
| 7990 opcode(0x69); /* 69 /r id */ | |
| 7991 ins_encode(REX_reg_mem(dst, src), | |
| 7992 OpcSE(imm), reg_mem(dst, src), Con8or32(imm)); | |
| 7993 ins_pipe(ialu_reg_mem_alu0); | |
| 7994 %} | |
| 7995 | |
| 7996 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 7997 %{ | |
| 7998 match(Set dst (MulL dst src)); | |
| 7999 effect(KILL cr); | |
| 8000 | |
| 8001 ins_cost(300); | |
| 8002 format %{ "imulq $dst, $src\t# long" %} | |
| 8003 opcode(0x0F, 0xAF); | |
| 8004 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 8005 ins_pipe(ialu_reg_reg_alu0); | |
| 8006 %} | |
| 8007 | |
| 8008 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr) | |
| 8009 %{ | |
| 8010 match(Set dst (MulL src imm)); | |
| 8011 effect(KILL cr); | |
| 8012 | |
| 8013 ins_cost(300); | |
| 8014 format %{ "imulq $dst, $src, $imm\t# long" %} | |
| 8015 opcode(0x69); /* 69 /r id */ | |
| 8016 ins_encode(REX_reg_reg_wide(dst, src), | |
| 8017 OpcSE(imm), reg_reg(dst, src), Con8or32(imm)); | |
| 8018 ins_pipe(ialu_reg_reg_alu0); | |
| 8019 %} | |
| 8020 | |
| 8021 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 8022 %{ | |
| 8023 match(Set dst (MulL dst (LoadL src))); | |
| 8024 effect(KILL cr); | |
| 8025 | |
| 8026 ins_cost(350); | |
| 8027 format %{ "imulq $dst, $src\t# long" %} | |
| 8028 opcode(0x0F, 0xAF); | |
| 8029 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src)); | |
| 8030 ins_pipe(ialu_reg_mem_alu0); | |
| 8031 %} | |
| 8032 | |
| 8033 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr) | |
| 8034 %{ | |
| 8035 match(Set dst (MulL (LoadL src) imm)); | |
| 8036 effect(KILL cr); | |
| 8037 | |
| 8038 ins_cost(300); | |
| 8039 format %{ "imulq $dst, $src, $imm\t# long" %} | |
| 8040 opcode(0x69); /* 69 /r id */ | |
| 8041 ins_encode(REX_reg_mem_wide(dst, src), | |
| 8042 OpcSE(imm), reg_mem(dst, src), Con8or32(imm)); | |
| 8043 ins_pipe(ialu_reg_mem_alu0); | |
| 8044 %} | |
| 8045 | |
| 145 | 8046 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr) |
| 8047 %{ | |
| 8048 match(Set dst (MulHiL src rax)); | |
| 8049 effect(USE_KILL rax, KILL cr); | |
| 8050 | |
| 8051 ins_cost(300); | |
| 8052 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %} | |
| 8053 opcode(0xF7, 0x5); /* Opcode F7 /5 */ | |
| 8054 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src)); | |
| 8055 ins_pipe(ialu_reg_reg_alu0); | |
| 8056 %} | |
| 8057 | |
| 0 | 8058 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div, |
| 8059 rFlagsReg cr) | |
| 8060 %{ | |
| 8061 match(Set rax (DivI rax div)); | |
| 8062 effect(KILL rdx, KILL cr); | |
| 8063 | |
| 8064 ins_cost(30*100+10*100); // XXX | |
| 8065 format %{ "cmpl rax, 0x80000000\t# idiv\n\t" | |
| 8066 "jne,s normal\n\t" | |
| 8067 "xorl rdx, rdx\n\t" | |
| 8068 "cmpl $div, -1\n\t" | |
| 8069 "je,s done\n" | |
| 8070 "normal: cdql\n\t" | |
| 8071 "idivl $div\n" | |
| 8072 "done:" %} | |
| 8073 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8074 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div)); | |
| 8075 ins_pipe(ialu_reg_reg_alu0); | |
| 8076 %} | |
| 8077 | |
| 8078 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div, | |
| 8079 rFlagsReg cr) | |
| 8080 %{ | |
| 8081 match(Set rax (DivL rax div)); | |
| 8082 effect(KILL rdx, KILL cr); | |
| 8083 | |
| 8084 ins_cost(30*100+10*100); // XXX | |
| 8085 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t" | |
| 8086 "cmpq rax, rdx\n\t" | |
| 8087 "jne,s normal\n\t" | |
| 8088 "xorl rdx, rdx\n\t" | |
| 8089 "cmpq $div, -1\n\t" | |
| 8090 "je,s done\n" | |
| 8091 "normal: cdqq\n\t" | |
| 8092 "idivq $div\n" | |
| 8093 "done:" %} | |
| 8094 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8095 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div)); | |
| 8096 ins_pipe(ialu_reg_reg_alu0); | |
| 8097 %} | |
| 8098 | |
| 8099 // Integer DIVMOD with Register, both quotient and mod results | |
| 8100 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div, | |
| 8101 rFlagsReg cr) | |
| 8102 %{ | |
| 8103 match(DivModI rax div); | |
| 8104 effect(KILL cr); | |
| 8105 | |
| 8106 ins_cost(30*100+10*100); // XXX | |
| 8107 format %{ "cmpl rax, 0x80000000\t# idiv\n\t" | |
| 8108 "jne,s normal\n\t" | |
| 8109 "xorl rdx, rdx\n\t" | |
| 8110 "cmpl $div, -1\n\t" | |
| 8111 "je,s done\n" | |
| 8112 "normal: cdql\n\t" | |
| 8113 "idivl $div\n" | |
| 8114 "done:" %} | |
| 8115 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8116 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div)); | |
| 8117 ins_pipe(pipe_slow); | |
| 8118 %} | |
| 8119 | |
| 8120 // Long DIVMOD with Register, both quotient and mod results | |
| 8121 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div, | |
| 8122 rFlagsReg cr) | |
| 8123 %{ | |
| 8124 match(DivModL rax div); | |
| 8125 effect(KILL cr); | |
| 8126 | |
| 8127 ins_cost(30*100+10*100); // XXX | |
| 8128 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t" | |
| 8129 "cmpq rax, rdx\n\t" | |
| 8130 "jne,s normal\n\t" | |
| 8131 "xorl rdx, rdx\n\t" | |
| 8132 "cmpq $div, -1\n\t" | |
| 8133 "je,s done\n" | |
| 8134 "normal: cdqq\n\t" | |
| 8135 "idivq $div\n" | |
| 8136 "done:" %} | |
| 8137 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8138 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div)); | |
| 8139 ins_pipe(pipe_slow); | |
| 8140 %} | |
| 8141 | |
| 8142 //----------- DivL-By-Constant-Expansions-------------------------------------- | |
| 8143 // DivI cases are handled by the compiler | |
| 8144 | |
| 605 | 8145 // Magic constant, reciprocal of 10 |
| 0 | 8146 instruct loadConL_0x6666666666666667(rRegL dst) |
| 8147 %{ | |
| 8148 effect(DEF dst); | |
| 8149 | |
| 8150 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %} | |
| 8151 ins_encode(load_immL(dst, 0x6666666666666667)); | |
| 8152 ins_pipe(ialu_reg); | |
| 8153 %} | |
| 8154 | |
| 8155 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr) | |
| 8156 %{ | |
| 8157 effect(DEF dst, USE src, USE_KILL rax, KILL cr); | |
| 8158 | |
| 8159 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %} | |
| 8160 opcode(0xF7, 0x5); /* Opcode F7 /5 */ | |
| 8161 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src)); | |
| 8162 ins_pipe(ialu_reg_reg_alu0); | |
| 8163 %} | |
| 8164 | |
| 8165 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr) | |
| 8166 %{ | |
| 8167 effect(USE_DEF dst, KILL cr); | |
| 8168 | |
| 8169 format %{ "sarq $dst, #63\t# Used in div-by-10" %} | |
| 8170 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8171 ins_encode(reg_opc_imm_wide(dst, 0x3F)); | |
| 8172 ins_pipe(ialu_reg); | |
| 8173 %} | |
| 8174 | |
| 8175 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr) | |
| 8176 %{ | |
| 8177 effect(USE_DEF dst, KILL cr); | |
| 8178 | |
| 8179 format %{ "sarq $dst, #2\t# Used in div-by-10" %} | |
| 8180 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8181 ins_encode(reg_opc_imm_wide(dst, 0x2)); | |
| 8182 ins_pipe(ialu_reg); | |
| 8183 %} | |
| 8184 | |
| 8185 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div) | |
| 8186 %{ | |
| 8187 match(Set dst (DivL src div)); | |
| 8188 | |
| 8189 ins_cost((5+8)*100); | |
| 8190 expand %{ | |
| 8191 rax_RegL rax; // Killed temp | |
| 8192 rFlagsReg cr; // Killed | |
| 8193 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667 | |
| 8194 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src | |
| 8195 sarL_rReg_63(src, cr); // sarq src, 63 | |
| 8196 sarL_rReg_2(dst, cr); // sarq rdx, 2 | |
| 8197 subL_rReg(dst, src, cr); // subl rdx, src | |
| 8198 %} | |
| 8199 %} | |
| 8200 | |
| 8201 //----------------------------------------------------------------------------- | |
| 8202 | |
| 8203 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div, | |
| 8204 rFlagsReg cr) | |
| 8205 %{ | |
| 8206 match(Set rdx (ModI rax div)); | |
| 8207 effect(KILL rax, KILL cr); | |
| 8208 | |
| 8209 ins_cost(300); // XXX | |
| 8210 format %{ "cmpl rax, 0x80000000\t# irem\n\t" | |
| 8211 "jne,s normal\n\t" | |
| 8212 "xorl rdx, rdx\n\t" | |
| 8213 "cmpl $div, -1\n\t" | |
| 8214 "je,s done\n" | |
| 8215 "normal: cdql\n\t" | |
| 8216 "idivl $div\n" | |
| 8217 "done:" %} | |
| 8218 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8219 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div)); | |
| 8220 ins_pipe(ialu_reg_reg_alu0); | |
| 8221 %} | |
| 8222 | |
| 8223 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div, | |
| 8224 rFlagsReg cr) | |
| 8225 %{ | |
| 8226 match(Set rdx (ModL rax div)); | |
| 8227 effect(KILL rax, KILL cr); | |
| 8228 | |
| 8229 ins_cost(300); // XXX | |
| 8230 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t" | |
| 8231 "cmpq rax, rdx\n\t" | |
| 8232 "jne,s normal\n\t" | |
| 8233 "xorl rdx, rdx\n\t" | |
| 8234 "cmpq $div, -1\n\t" | |
| 8235 "je,s done\n" | |
| 8236 "normal: cdqq\n\t" | |
| 8237 "idivq $div\n" | |
| 8238 "done:" %} | |
| 8239 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8240 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div)); | |
| 8241 ins_pipe(ialu_reg_reg_alu0); | |
| 8242 %} | |
| 8243 | |
| 8244 // Integer Shift Instructions | |
| 8245 // Shift Left by one | |
| 8246 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr) | |
| 8247 %{ | |
| 8248 match(Set dst (LShiftI dst shift)); | |
| 8249 effect(KILL cr); | |
| 8250 | |
| 8251 format %{ "sall $dst, $shift" %} | |
| 8252 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 8253 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8254 ins_pipe(ialu_reg); | |
| 8255 %} | |
| 8256 | |
| 8257 // Shift Left by one | |
| 8258 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 8259 %{ | |
| 8260 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift))); | |
| 8261 effect(KILL cr); | |
| 8262 | |
| 8263 format %{ "sall $dst, $shift\t" %} | |
| 8264 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 8265 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8266 ins_pipe(ialu_mem_imm); | |
| 8267 %} | |
| 8268 | |
| 8269 // Shift Left by 8-bit immediate | |
| 8270 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) | |
| 8271 %{ | |
| 8272 match(Set dst (LShiftI dst shift)); | |
| 8273 effect(KILL cr); | |
| 8274 | |
| 8275 format %{ "sall $dst, $shift" %} | |
| 8276 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 8277 ins_encode(reg_opc_imm(dst, shift)); | |
| 8278 ins_pipe(ialu_reg); | |
| 8279 %} | |
| 8280 | |
| 8281 // Shift Left by 8-bit immediate | |
| 8282 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 8283 %{ | |
| 8284 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift))); | |
| 8285 effect(KILL cr); | |
| 8286 | |
| 8287 format %{ "sall $dst, $shift" %} | |
| 8288 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 8289 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 8290 ins_pipe(ialu_mem_imm); | |
| 8291 %} | |
| 8292 | |
| 8293 // Shift Left by variable | |
| 8294 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 8295 %{ | |
| 8296 match(Set dst (LShiftI dst shift)); | |
| 8297 effect(KILL cr); | |
| 8298 | |
| 8299 format %{ "sall $dst, $shift" %} | |
| 8300 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 8301 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8302 ins_pipe(ialu_reg_reg); | |
| 8303 %} | |
| 8304 | |
| 8305 // Shift Left by variable | |
| 8306 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 8307 %{ | |
| 8308 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift))); | |
| 8309 effect(KILL cr); | |
| 8310 | |
| 8311 format %{ "sall $dst, $shift" %} | |
| 8312 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 8313 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8314 ins_pipe(ialu_mem_reg); | |
| 8315 %} | |
| 8316 | |
| 8317 // Arithmetic shift right by one | |
| 8318 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr) | |
| 8319 %{ | |
| 8320 match(Set dst (RShiftI dst shift)); | |
| 8321 effect(KILL cr); | |
| 8322 | |
| 8323 format %{ "sarl $dst, $shift" %} | |
| 8324 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 8325 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8326 ins_pipe(ialu_reg); | |
| 8327 %} | |
| 8328 | |
| 8329 // Arithmetic shift right by one | |
| 8330 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 8331 %{ | |
| 8332 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 8333 effect(KILL cr); | |
| 8334 | |
| 8335 format %{ "sarl $dst, $shift" %} | |
| 8336 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 8337 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8338 ins_pipe(ialu_mem_imm); | |
| 8339 %} | |
| 8340 | |
| 8341 // Arithmetic Shift Right by 8-bit immediate | |
| 8342 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) | |
| 8343 %{ | |
| 8344 match(Set dst (RShiftI dst shift)); | |
| 8345 effect(KILL cr); | |
| 8346 | |
| 8347 format %{ "sarl $dst, $shift" %} | |
| 8348 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8349 ins_encode(reg_opc_imm(dst, shift)); | |
| 8350 ins_pipe(ialu_mem_imm); | |
| 8351 %} | |
| 8352 | |
| 8353 // Arithmetic Shift Right by 8-bit immediate | |
| 8354 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 8355 %{ | |
| 8356 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 8357 effect(KILL cr); | |
| 8358 | |
| 8359 format %{ "sarl $dst, $shift" %} | |
| 8360 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8361 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 8362 ins_pipe(ialu_mem_imm); | |
| 8363 %} | |
| 8364 | |
| 8365 // Arithmetic Shift Right by variable | |
| 8366 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 8367 %{ | |
| 8368 match(Set dst (RShiftI dst shift)); | |
| 8369 effect(KILL cr); | |
| 8370 | |
| 8371 format %{ "sarl $dst, $shift" %} | |
| 8372 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 8373 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8374 ins_pipe(ialu_reg_reg); | |
| 8375 %} | |
| 8376 | |
| 8377 // Arithmetic Shift Right by variable | |
| 8378 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 8379 %{ | |
| 8380 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 8381 effect(KILL cr); | |
| 8382 | |
| 8383 format %{ "sarl $dst, $shift" %} | |
| 8384 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 8385 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8386 ins_pipe(ialu_mem_reg); | |
| 8387 %} | |
| 8388 | |
| 8389 // Logical shift right by one | |
| 8390 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr) | |
| 8391 %{ | |
| 8392 match(Set dst (URShiftI dst shift)); | |
| 8393 effect(KILL cr); | |
| 8394 | |
| 8395 format %{ "shrl $dst, $shift" %} | |
| 8396 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 8397 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8398 ins_pipe(ialu_reg); | |
| 8399 %} | |
| 8400 | |
| 8401 // Logical shift right by one | |
| 8402 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 8403 %{ | |
| 8404 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift))); | |
| 8405 effect(KILL cr); | |
| 8406 | |
| 8407 format %{ "shrl $dst, $shift" %} | |
| 8408 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 8409 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8410 ins_pipe(ialu_mem_imm); | |
| 8411 %} | |
| 8412 | |
| 8413 // Logical Shift Right by 8-bit immediate | |
| 8414 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) | |
| 8415 %{ | |
| 8416 match(Set dst (URShiftI dst shift)); | |
| 8417 effect(KILL cr); | |
| 8418 | |
| 8419 format %{ "shrl $dst, $shift" %} | |
| 8420 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 8421 ins_encode(reg_opc_imm(dst, shift)); | |
| 8422 ins_pipe(ialu_reg); | |
| 8423 %} | |
| 8424 | |
| 8425 // Logical Shift Right by 8-bit immediate | |
| 8426 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 8427 %{ | |
| 8428 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift))); | |
| 8429 effect(KILL cr); | |
| 8430 | |
| 8431 format %{ "shrl $dst, $shift" %} | |
| 8432 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 8433 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 8434 ins_pipe(ialu_mem_imm); | |
| 8435 %} | |
| 8436 | |
| 8437 // Logical Shift Right by variable | |
| 8438 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 8439 %{ | |
| 8440 match(Set dst (URShiftI dst shift)); | |
| 8441 effect(KILL cr); | |
| 8442 | |
| 8443 format %{ "shrl $dst, $shift" %} | |
| 8444 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 8445 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8446 ins_pipe(ialu_reg_reg); | |
| 8447 %} | |
| 8448 | |
| 8449 // Logical Shift Right by variable | |
| 8450 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 8451 %{ | |
| 8452 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift))); | |
| 8453 effect(KILL cr); | |
| 8454 | |
| 8455 format %{ "shrl $dst, $shift" %} | |
| 8456 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 8457 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8458 ins_pipe(ialu_mem_reg); | |
| 8459 %} | |
| 8460 | |
| 8461 // Long Shift Instructions | |
| 8462 // Shift Left by one | |
| 8463 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr) | |
| 8464 %{ | |
| 8465 match(Set dst (LShiftL dst shift)); | |
| 8466 effect(KILL cr); | |
| 8467 | |
| 8468 format %{ "salq $dst, $shift" %} | |
| 8469 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 8470 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8471 ins_pipe(ialu_reg); | |
| 8472 %} | |
| 8473 | |
| 8474 // Shift Left by one | |
| 8475 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 8476 %{ | |
| 8477 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift))); | |
| 8478 effect(KILL cr); | |
| 8479 | |
| 8480 format %{ "salq $dst, $shift" %} | |
| 8481 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 8482 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8483 ins_pipe(ialu_mem_imm); | |
| 8484 %} | |
| 8485 | |
| 8486 // Shift Left by 8-bit immediate | |
| 8487 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr) | |
| 8488 %{ | |
| 8489 match(Set dst (LShiftL dst shift)); | |
| 8490 effect(KILL cr); | |
| 8491 | |
| 8492 format %{ "salq $dst, $shift" %} | |
| 8493 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 8494 ins_encode(reg_opc_imm_wide(dst, shift)); | |
| 8495 ins_pipe(ialu_reg); | |
| 8496 %} | |
| 8497 | |
| 8498 // Shift Left by 8-bit immediate | |
| 8499 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 8500 %{ | |
| 8501 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift))); | |
| 8502 effect(KILL cr); | |
| 8503 | |
| 8504 format %{ "salq $dst, $shift" %} | |
| 8505 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 8506 ins_encode(REX_mem_wide(dst), OpcP, | |
| 8507 RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 8508 ins_pipe(ialu_mem_imm); | |
| 8509 %} | |
| 8510 | |
| 8511 // Shift Left by variable | |
| 8512 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 8513 %{ | |
| 8514 match(Set dst (LShiftL dst shift)); | |
| 8515 effect(KILL cr); | |
| 8516 | |
| 8517 format %{ "salq $dst, $shift" %} | |
| 8518 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 8519 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8520 ins_pipe(ialu_reg_reg); | |
| 8521 %} | |
| 8522 | |
| 8523 // Shift Left by variable | |
| 8524 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 8525 %{ | |
| 8526 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift))); | |
| 8527 effect(KILL cr); | |
| 8528 | |
| 8529 format %{ "salq $dst, $shift" %} | |
| 8530 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 8531 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8532 ins_pipe(ialu_mem_reg); | |
| 8533 %} | |
| 8534 | |
| 8535 // Arithmetic shift right by one | |
| 8536 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr) | |
| 8537 %{ | |
| 8538 match(Set dst (RShiftL dst shift)); | |
| 8539 effect(KILL cr); | |
| 8540 | |
| 8541 format %{ "sarq $dst, $shift" %} | |
| 8542 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 8543 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8544 ins_pipe(ialu_reg); | |
| 8545 %} | |
| 8546 | |
| 8547 // Arithmetic shift right by one | |
| 8548 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 8549 %{ | |
| 8550 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift))); | |
| 8551 effect(KILL cr); | |
| 8552 | |
| 8553 format %{ "sarq $dst, $shift" %} | |
| 8554 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 8555 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8556 ins_pipe(ialu_mem_imm); | |
| 8557 %} | |
| 8558 | |
| 8559 // Arithmetic Shift Right by 8-bit immediate | |
| 8560 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr) | |
| 8561 %{ | |
| 8562 match(Set dst (RShiftL dst shift)); | |
| 8563 effect(KILL cr); | |
| 8564 | |
| 8565 format %{ "sarq $dst, $shift" %} | |
| 8566 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8567 ins_encode(reg_opc_imm_wide(dst, shift)); | |
| 8568 ins_pipe(ialu_mem_imm); | |
| 8569 %} | |
| 8570 | |
| 8571 // Arithmetic Shift Right by 8-bit immediate | |
| 8572 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 8573 %{ | |
| 8574 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift))); | |
| 8575 effect(KILL cr); | |
| 8576 | |
| 8577 format %{ "sarq $dst, $shift" %} | |
| 8578 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8579 ins_encode(REX_mem_wide(dst), OpcP, | |
| 8580 RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 8581 ins_pipe(ialu_mem_imm); | |
| 8582 %} | |
| 8583 | |
| 8584 // Arithmetic Shift Right by variable | |
| 8585 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 8586 %{ | |
| 8587 match(Set dst (RShiftL dst shift)); | |
| 8588 effect(KILL cr); | |
| 8589 | |
| 8590 format %{ "sarq $dst, $shift" %} | |
| 8591 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 8592 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8593 ins_pipe(ialu_reg_reg); | |
| 8594 %} | |
| 8595 | |
| 8596 // Arithmetic Shift Right by variable | |
| 8597 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 8598 %{ | |
| 8599 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift))); | |
| 8600 effect(KILL cr); | |
| 8601 | |
| 8602 format %{ "sarq $dst, $shift" %} | |
| 8603 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 8604 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8605 ins_pipe(ialu_mem_reg); | |
| 8606 %} | |
| 8607 | |
| 8608 // Logical shift right by one | |
| 8609 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr) | |
| 8610 %{ | |
| 8611 match(Set dst (URShiftL dst shift)); | |
| 8612 effect(KILL cr); | |
| 8613 | |
| 8614 format %{ "shrq $dst, $shift" %} | |
| 8615 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 8616 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst )); | |
| 8617 ins_pipe(ialu_reg); | |
| 8618 %} | |
| 8619 | |
| 8620 // Logical shift right by one | |
| 8621 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 8622 %{ | |
| 8623 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift))); | |
| 8624 effect(KILL cr); | |
| 8625 | |
| 8626 format %{ "shrq $dst, $shift" %} | |
| 8627 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 8628 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8629 ins_pipe(ialu_mem_imm); | |
| 8630 %} | |
| 8631 | |
| 8632 // Logical Shift Right by 8-bit immediate | |
| 8633 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr) | |
| 8634 %{ | |
| 8635 match(Set dst (URShiftL dst shift)); | |
| 8636 effect(KILL cr); | |
| 8637 | |
| 8638 format %{ "shrq $dst, $shift" %} | |
| 8639 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 8640 ins_encode(reg_opc_imm_wide(dst, shift)); | |
| 8641 ins_pipe(ialu_reg); | |
| 8642 %} | |
| 8643 | |
|
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|
8644 |
| 0 | 8645 // Logical Shift Right by 8-bit immediate |
| 8646 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 8647 %{ | |
| 8648 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift))); | |
| 8649 effect(KILL cr); | |
| 8650 | |
| 8651 format %{ "shrq $dst, $shift" %} | |
| 8652 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 8653 ins_encode(REX_mem_wide(dst), OpcP, | |
| 8654 RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 8655 ins_pipe(ialu_mem_imm); | |
| 8656 %} | |
| 8657 | |
| 8658 // Logical Shift Right by variable | |
| 8659 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 8660 %{ | |
| 8661 match(Set dst (URShiftL dst shift)); | |
| 8662 effect(KILL cr); | |
| 8663 | |
| 8664 format %{ "shrq $dst, $shift" %} | |
| 8665 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 8666 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8667 ins_pipe(ialu_reg_reg); | |
| 8668 %} | |
| 8669 | |
| 8670 // Logical Shift Right by variable | |
| 8671 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 8672 %{ | |
| 8673 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift))); | |
| 8674 effect(KILL cr); | |
| 8675 | |
| 8676 format %{ "shrq $dst, $shift" %} | |
| 8677 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 8678 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8679 ins_pipe(ialu_mem_reg); | |
| 8680 %} | |
| 8681 | |
| 8682 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24. | |
| 8683 // This idiom is used by the compiler for the i2b bytecode. | |
| 8684 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour) | |
| 8685 %{ | |
| 8686 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour)); | |
| 8687 | |
| 8688 format %{ "movsbl $dst, $src\t# i2b" %} | |
| 8689 opcode(0x0F, 0xBE); | |
| 8690 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 8691 ins_pipe(ialu_reg_reg); | |
| 8692 %} | |
| 8693 | |
| 8694 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16. | |
| 8695 // This idiom is used by the compiler the i2s bytecode. | |
| 8696 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen) | |
| 8697 %{ | |
| 8698 match(Set dst (RShiftI (LShiftI src sixteen) sixteen)); | |
| 8699 | |
| 8700 format %{ "movswl $dst, $src\t# i2s" %} | |
| 8701 opcode(0x0F, 0xBF); | |
| 8702 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 8703 ins_pipe(ialu_reg_reg); | |
| 8704 %} | |
| 8705 | |
| 8706 // ROL/ROR instructions | |
| 8707 | |
| 8708 // ROL expand | |
| 8709 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{ | |
| 8710 effect(KILL cr, USE_DEF dst); | |
| 8711 | |
| 8712 format %{ "roll $dst" %} | |
| 8713 opcode(0xD1, 0x0); /* Opcode D1 /0 */ | |
| 8714 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8715 ins_pipe(ialu_reg); | |
| 8716 %} | |
| 8717 | |
| 8718 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{ | |
| 8719 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8720 | |
| 8721 format %{ "roll $dst, $shift" %} | |
| 8722 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */ | |
| 8723 ins_encode( reg_opc_imm(dst, shift) ); | |
| 8724 ins_pipe(ialu_reg); | |
| 8725 %} | |
| 8726 | |
| 8727 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 8728 %{ | |
| 8729 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8730 | |
| 8731 format %{ "roll $dst, $shift" %} | |
| 8732 opcode(0xD3, 0x0); /* Opcode D3 /0 */ | |
| 8733 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8734 ins_pipe(ialu_reg_reg); | |
| 8735 %} | |
| 8736 // end of ROL expand | |
| 8737 | |
| 8738 // Rotate Left by one | |
| 8739 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr) | |
| 8740 %{ | |
| 8741 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift))); | |
| 8742 | |
| 8743 expand %{ | |
| 8744 rolI_rReg_imm1(dst, cr); | |
| 8745 %} | |
| 8746 %} | |
| 8747 | |
| 8748 // Rotate Left by 8-bit immediate | |
| 8749 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr) | |
| 8750 %{ | |
| 8751 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); | |
| 8752 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift))); | |
| 8753 | |
| 8754 expand %{ | |
| 8755 rolI_rReg_imm8(dst, lshift, cr); | |
| 8756 %} | |
| 8757 %} | |
| 8758 | |
| 8759 // Rotate Left by variable | |
| 8760 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
| 8761 %{ | |
| 8762 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift)))); | |
| 8763 | |
| 8764 expand %{ | |
| 8765 rolI_rReg_CL(dst, shift, cr); | |
| 8766 %} | |
| 8767 %} | |
| 8768 | |
| 8769 // Rotate Left by variable | |
| 8770 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr) | |
| 8771 %{ | |
| 8772 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift)))); | |
| 8773 | |
| 8774 expand %{ | |
| 8775 rolI_rReg_CL(dst, shift, cr); | |
| 8776 %} | |
| 8777 %} | |
| 8778 | |
| 8779 // ROR expand | |
| 8780 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr) | |
| 8781 %{ | |
| 8782 effect(USE_DEF dst, KILL cr); | |
| 8783 | |
| 8784 format %{ "rorl $dst" %} | |
| 8785 opcode(0xD1, 0x1); /* D1 /1 */ | |
| 8786 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8787 ins_pipe(ialu_reg); | |
| 8788 %} | |
| 8789 | |
| 8790 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) | |
| 8791 %{ | |
| 8792 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8793 | |
| 8794 format %{ "rorl $dst, $shift" %} | |
| 8795 opcode(0xC1, 0x1); /* C1 /1 ib */ | |
| 8796 ins_encode(reg_opc_imm(dst, shift)); | |
| 8797 ins_pipe(ialu_reg); | |
| 8798 %} | |
| 8799 | |
| 8800 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 8801 %{ | |
| 8802 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8803 | |
| 8804 format %{ "rorl $dst, $shift" %} | |
| 8805 opcode(0xD3, 0x1); /* D3 /1 */ | |
| 8806 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8807 ins_pipe(ialu_reg_reg); | |
| 8808 %} | |
| 8809 // end of ROR expand | |
| 8810 | |
| 8811 // Rotate Right by one | |
| 8812 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr) | |
| 8813 %{ | |
| 8814 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift))); | |
| 8815 | |
| 8816 expand %{ | |
| 8817 rorI_rReg_imm1(dst, cr); | |
| 8818 %} | |
| 8819 %} | |
| 8820 | |
| 8821 // Rotate Right by 8-bit immediate | |
| 8822 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr) | |
| 8823 %{ | |
| 8824 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); | |
| 8825 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift))); | |
| 8826 | |
| 8827 expand %{ | |
| 8828 rorI_rReg_imm8(dst, rshift, cr); | |
| 8829 %} | |
| 8830 %} | |
| 8831 | |
| 8832 // Rotate Right by variable | |
| 8833 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
| 8834 %{ | |
| 8835 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift)))); | |
| 8836 | |
| 8837 expand %{ | |
| 8838 rorI_rReg_CL(dst, shift, cr); | |
| 8839 %} | |
| 8840 %} | |
| 8841 | |
| 8842 // Rotate Right by variable | |
| 8843 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr) | |
| 8844 %{ | |
| 8845 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift)))); | |
| 8846 | |
| 8847 expand %{ | |
| 8848 rorI_rReg_CL(dst, shift, cr); | |
| 8849 %} | |
| 8850 %} | |
| 8851 | |
| 8852 // for long rotate | |
| 8853 // ROL expand | |
| 8854 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{ | |
| 8855 effect(USE_DEF dst, KILL cr); | |
| 8856 | |
| 8857 format %{ "rolq $dst" %} | |
| 8858 opcode(0xD1, 0x0); /* Opcode D1 /0 */ | |
| 8859 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8860 ins_pipe(ialu_reg); | |
| 8861 %} | |
| 8862 | |
| 8863 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{ | |
| 8864 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8865 | |
| 8866 format %{ "rolq $dst, $shift" %} | |
| 8867 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */ | |
| 8868 ins_encode( reg_opc_imm_wide(dst, shift) ); | |
| 8869 ins_pipe(ialu_reg); | |
| 8870 %} | |
| 8871 | |
| 8872 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 8873 %{ | |
| 8874 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8875 | |
| 8876 format %{ "rolq $dst, $shift" %} | |
| 8877 opcode(0xD3, 0x0); /* Opcode D3 /0 */ | |
| 8878 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8879 ins_pipe(ialu_reg_reg); | |
| 8880 %} | |
| 8881 // end of ROL expand | |
| 8882 | |
| 8883 // Rotate Left by one | |
| 8884 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr) | |
| 8885 %{ | |
| 8886 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift))); | |
| 8887 | |
| 8888 expand %{ | |
| 8889 rolL_rReg_imm1(dst, cr); | |
| 8890 %} | |
| 8891 %} | |
| 8892 | |
| 8893 // Rotate Left by 8-bit immediate | |
| 8894 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr) | |
| 8895 %{ | |
| 8896 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f)); | |
| 8897 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift))); | |
| 8898 | |
| 8899 expand %{ | |
| 8900 rolL_rReg_imm8(dst, lshift, cr); | |
| 8901 %} | |
| 8902 %} | |
| 8903 | |
| 8904 // Rotate Left by variable | |
| 8905 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
| 8906 %{ | |
| 8907 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift)))); | |
| 8908 | |
| 8909 expand %{ | |
| 8910 rolL_rReg_CL(dst, shift, cr); | |
| 8911 %} | |
| 8912 %} | |
| 8913 | |
| 8914 // Rotate Left by variable | |
| 8915 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr) | |
| 8916 %{ | |
| 8917 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift)))); | |
| 8918 | |
| 8919 expand %{ | |
| 8920 rolL_rReg_CL(dst, shift, cr); | |
| 8921 %} | |
| 8922 %} | |
| 8923 | |
| 8924 // ROR expand | |
| 8925 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr) | |
| 8926 %{ | |
| 8927 effect(USE_DEF dst, KILL cr); | |
| 8928 | |
| 8929 format %{ "rorq $dst" %} | |
| 8930 opcode(0xD1, 0x1); /* D1 /1 */ | |
| 8931 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8932 ins_pipe(ialu_reg); | |
| 8933 %} | |
| 8934 | |
| 8935 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) | |
| 8936 %{ | |
| 8937 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8938 | |
| 8939 format %{ "rorq $dst, $shift" %} | |
| 8940 opcode(0xC1, 0x1); /* C1 /1 ib */ | |
| 8941 ins_encode(reg_opc_imm_wide(dst, shift)); | |
| 8942 ins_pipe(ialu_reg); | |
| 8943 %} | |
| 8944 | |
| 8945 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 8946 %{ | |
| 8947 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8948 | |
| 8949 format %{ "rorq $dst, $shift" %} | |
| 8950 opcode(0xD3, 0x1); /* D3 /1 */ | |
| 8951 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8952 ins_pipe(ialu_reg_reg); | |
| 8953 %} | |
| 8954 // end of ROR expand | |
| 8955 | |
| 8956 // Rotate Right by one | |
| 8957 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr) | |
| 8958 %{ | |
| 8959 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift))); | |
| 8960 | |
| 8961 expand %{ | |
| 8962 rorL_rReg_imm1(dst, cr); | |
| 8963 %} | |
| 8964 %} | |
| 8965 | |
| 8966 // Rotate Right by 8-bit immediate | |
| 8967 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr) | |
| 8968 %{ | |
| 8969 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f)); | |
| 8970 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift))); | |
| 8971 | |
| 8972 expand %{ | |
| 8973 rorL_rReg_imm8(dst, rshift, cr); | |
| 8974 %} | |
| 8975 %} | |
| 8976 | |
| 8977 // Rotate Right by variable | |
| 8978 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
| 8979 %{ | |
| 8980 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift)))); | |
| 8981 | |
| 8982 expand %{ | |
| 8983 rorL_rReg_CL(dst, shift, cr); | |
| 8984 %} | |
| 8985 %} | |
| 8986 | |
| 8987 // Rotate Right by variable | |
| 8988 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr) | |
| 8989 %{ | |
| 8990 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift)))); | |
| 8991 | |
| 8992 expand %{ | |
| 8993 rorL_rReg_CL(dst, shift, cr); | |
| 8994 %} | |
| 8995 %} | |
| 8996 | |
| 8997 // Logical Instructions | |
| 8998 | |
| 8999 // Integer Logical Instructions | |
| 9000 | |
| 9001 // And Instructions | |
| 9002 // And Register with Register | |
| 9003 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 9004 %{ | |
| 9005 match(Set dst (AndI dst src)); | |
| 9006 effect(KILL cr); | |
| 9007 | |
| 9008 format %{ "andl $dst, $src\t# int" %} | |
| 9009 opcode(0x23); | |
| 9010 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 9011 ins_pipe(ialu_reg_reg); | |
| 9012 %} | |
| 9013 | |
| 9014 // And Register with Immediate 255 | |
| 9015 instruct andI_rReg_imm255(rRegI dst, immI_255 src) | |
| 9016 %{ | |
| 9017 match(Set dst (AndI dst src)); | |
| 9018 | |
| 9019 format %{ "movzbl $dst, $dst\t# int & 0xFF" %} | |
| 9020 opcode(0x0F, 0xB6); | |
| 9021 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 9022 ins_pipe(ialu_reg); | |
| 9023 %} | |
| 9024 | |
| 9025 // And Register with Immediate 255 and promote to long | |
| 9026 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask) | |
| 9027 %{ | |
| 9028 match(Set dst (ConvI2L (AndI src mask))); | |
| 9029 | |
| 9030 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %} | |
| 9031 opcode(0x0F, 0xB6); | |
| 9032 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 9033 ins_pipe(ialu_reg); | |
| 9034 %} | |
| 9035 | |
| 9036 // And Register with Immediate 65535 | |
| 9037 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src) | |
| 9038 %{ | |
| 9039 match(Set dst (AndI dst src)); | |
| 9040 | |
| 9041 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %} | |
| 9042 opcode(0x0F, 0xB7); | |
| 9043 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 9044 ins_pipe(ialu_reg); | |
| 9045 %} | |
| 9046 | |
| 9047 // And Register with Immediate 65535 and promote to long | |
| 9048 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask) | |
| 9049 %{ | |
| 9050 match(Set dst (ConvI2L (AndI src mask))); | |
| 9051 | |
| 9052 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %} | |
| 9053 opcode(0x0F, 0xB7); | |
| 9054 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 9055 ins_pipe(ialu_reg); | |
| 9056 %} | |
| 9057 | |
| 9058 // And Register with Immediate | |
| 9059 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 9060 %{ | |
| 9061 match(Set dst (AndI dst src)); | |
| 9062 effect(KILL cr); | |
| 9063 | |
| 9064 format %{ "andl $dst, $src\t# int" %} | |
| 9065 opcode(0x81, 0x04); /* Opcode 81 /4 */ | |
| 9066 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 9067 ins_pipe(ialu_reg); | |
| 9068 %} | |
| 9069 | |
| 9070 // And Register with Memory | |
| 9071 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 9072 %{ | |
| 9073 match(Set dst (AndI dst (LoadI src))); | |
| 9074 effect(KILL cr); | |
| 9075 | |
| 9076 ins_cost(125); | |
| 9077 format %{ "andl $dst, $src\t# int" %} | |
| 9078 opcode(0x23); | |
| 9079 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 9080 ins_pipe(ialu_reg_mem); | |
| 9081 %} | |
| 9082 | |
| 9083 // And Memory with Register | |
| 9084 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 9085 %{ | |
| 9086 match(Set dst (StoreI dst (AndI (LoadI dst) src))); | |
| 9087 effect(KILL cr); | |
| 9088 | |
| 9089 ins_cost(150); | |
| 9090 format %{ "andl $dst, $src\t# int" %} | |
| 9091 opcode(0x21); /* Opcode 21 /r */ | |
| 9092 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 9093 ins_pipe(ialu_mem_reg); | |
| 9094 %} | |
| 9095 | |
| 9096 // And Memory with Immediate | |
| 9097 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 9098 %{ | |
| 9099 match(Set dst (StoreI dst (AndI (LoadI dst) src))); | |
| 9100 effect(KILL cr); | |
| 9101 | |
| 9102 ins_cost(125); | |
| 9103 format %{ "andl $dst, $src\t# int" %} | |
| 9104 opcode(0x81, 0x4); /* Opcode 81 /4 id */ | |
| 9105 ins_encode(REX_mem(dst), OpcSE(src), | |
| 9106 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 9107 ins_pipe(ialu_mem_imm); | |
| 9108 %} | |
| 9109 | |
| 9110 // Or Instructions | |
| 9111 // Or Register with Register | |
| 9112 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 9113 %{ | |
| 9114 match(Set dst (OrI dst src)); | |
| 9115 effect(KILL cr); | |
| 9116 | |
| 9117 format %{ "orl $dst, $src\t# int" %} | |
| 9118 opcode(0x0B); | |
| 9119 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 9120 ins_pipe(ialu_reg_reg); | |
| 9121 %} | |
| 9122 | |
| 9123 // Or Register with Immediate | |
| 9124 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 9125 %{ | |
| 9126 match(Set dst (OrI dst src)); | |
| 9127 effect(KILL cr); | |
| 9128 | |
| 9129 format %{ "orl $dst, $src\t# int" %} | |
| 9130 opcode(0x81, 0x01); /* Opcode 81 /1 id */ | |
| 9131 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 9132 ins_pipe(ialu_reg); | |
| 9133 %} | |
| 9134 | |
| 9135 // Or Register with Memory | |
| 9136 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 9137 %{ | |
| 9138 match(Set dst (OrI dst (LoadI src))); | |
| 9139 effect(KILL cr); | |
| 9140 | |
| 9141 ins_cost(125); | |
| 9142 format %{ "orl $dst, $src\t# int" %} | |
| 9143 opcode(0x0B); | |
| 9144 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 9145 ins_pipe(ialu_reg_mem); | |
| 9146 %} | |
| 9147 | |
| 9148 // Or Memory with Register | |
| 9149 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 9150 %{ | |
| 9151 match(Set dst (StoreI dst (OrI (LoadI dst) src))); | |
| 9152 effect(KILL cr); | |
| 9153 | |
| 9154 ins_cost(150); | |
| 9155 format %{ "orl $dst, $src\t# int" %} | |
| 9156 opcode(0x09); /* Opcode 09 /r */ | |
| 9157 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 9158 ins_pipe(ialu_mem_reg); | |
| 9159 %} | |
| 9160 | |
| 9161 // Or Memory with Immediate | |
| 9162 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 9163 %{ | |
| 9164 match(Set dst (StoreI dst (OrI (LoadI dst) src))); | |
| 9165 effect(KILL cr); | |
| 9166 | |
| 9167 ins_cost(125); | |
| 9168 format %{ "orl $dst, $src\t# int" %} | |
| 9169 opcode(0x81, 0x1); /* Opcode 81 /1 id */ | |
| 9170 ins_encode(REX_mem(dst), OpcSE(src), | |
| 9171 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 9172 ins_pipe(ialu_mem_imm); | |
| 9173 %} | |
| 9174 | |
| 9175 // Xor Instructions | |
| 9176 // Xor Register with Register | |
| 9177 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 9178 %{ | |
| 9179 match(Set dst (XorI dst src)); | |
| 9180 effect(KILL cr); | |
| 9181 | |
| 9182 format %{ "xorl $dst, $src\t# int" %} | |
| 9183 opcode(0x33); | |
| 9184 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 9185 ins_pipe(ialu_reg_reg); | |
| 9186 %} | |
| 9187 | |
| 403 | 9188 // Xor Register with Immediate -1 |
| 9189 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{ | |
|
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9190 match(Set dst (XorI dst imm)); |
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9191 |
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9192 format %{ "not $dst" %} |
| 403 | 9193 ins_encode %{ |
| 9194 __ notl($dst$$Register); | |
| 9195 %} | |
| 9196 ins_pipe(ialu_reg); | |
| 9197 %} | |
| 9198 | |
| 0 | 9199 // Xor Register with Immediate |
| 9200 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 9201 %{ | |
| 9202 match(Set dst (XorI dst src)); | |
| 9203 effect(KILL cr); | |
| 9204 | |
| 9205 format %{ "xorl $dst, $src\t# int" %} | |
| 9206 opcode(0x81, 0x06); /* Opcode 81 /6 id */ | |
| 9207 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 9208 ins_pipe(ialu_reg); | |
| 9209 %} | |
| 9210 | |
| 9211 // Xor Register with Memory | |
| 9212 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 9213 %{ | |
| 9214 match(Set dst (XorI dst (LoadI src))); | |
| 9215 effect(KILL cr); | |
| 9216 | |
| 9217 ins_cost(125); | |
| 9218 format %{ "xorl $dst, $src\t# int" %} | |
| 9219 opcode(0x33); | |
| 9220 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 9221 ins_pipe(ialu_reg_mem); | |
| 9222 %} | |
| 9223 | |
| 9224 // Xor Memory with Register | |
| 9225 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 9226 %{ | |
| 9227 match(Set dst (StoreI dst (XorI (LoadI dst) src))); | |
| 9228 effect(KILL cr); | |
| 9229 | |
| 9230 ins_cost(150); | |
| 9231 format %{ "xorl $dst, $src\t# int" %} | |
| 9232 opcode(0x31); /* Opcode 31 /r */ | |
| 9233 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 9234 ins_pipe(ialu_mem_reg); | |
| 9235 %} | |
| 9236 | |
| 9237 // Xor Memory with Immediate | |
| 9238 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 9239 %{ | |
| 9240 match(Set dst (StoreI dst (XorI (LoadI dst) src))); | |
| 9241 effect(KILL cr); | |
| 9242 | |
| 9243 ins_cost(125); | |
| 9244 format %{ "xorl $dst, $src\t# int" %} | |
| 9245 opcode(0x81, 0x6); /* Opcode 81 /6 id */ | |
| 9246 ins_encode(REX_mem(dst), OpcSE(src), | |
| 9247 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 9248 ins_pipe(ialu_mem_imm); | |
| 9249 %} | |
| 9250 | |
| 9251 | |
| 9252 // Long Logical Instructions | |
| 9253 | |
| 9254 // And Instructions | |
| 9255 // And Register with Register | |
| 9256 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 9257 %{ | |
| 9258 match(Set dst (AndL dst src)); | |
| 9259 effect(KILL cr); | |
| 9260 | |
| 9261 format %{ "andq $dst, $src\t# long" %} | |
| 9262 opcode(0x23); | |
| 9263 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 9264 ins_pipe(ialu_reg_reg); | |
| 9265 %} | |
| 9266 | |
| 9267 // And Register with Immediate 255 | |
| 9268 instruct andL_rReg_imm255(rRegL dst, immL_255 src) | |
| 9269 %{ | |
| 9270 match(Set dst (AndL dst src)); | |
| 9271 | |
|
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9272 format %{ "movzbq $dst, $dst\t# long & 0xFF" %} |
| 0 | 9273 opcode(0x0F, 0xB6); |
| 9274 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 9275 ins_pipe(ialu_reg); | |
| 9276 %} | |
| 9277 | |
| 9278 // And Register with Immediate 65535 | |
|
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9279 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src) |
| 0 | 9280 %{ |
| 9281 match(Set dst (AndL dst src)); | |
| 9282 | |
| 9283 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %} | |
| 9284 opcode(0x0F, 0xB7); | |
| 9285 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 9286 ins_pipe(ialu_reg); | |
| 9287 %} | |
| 9288 | |
| 9289 // And Register with Immediate | |
| 9290 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
| 9291 %{ | |
| 9292 match(Set dst (AndL dst src)); | |
| 9293 effect(KILL cr); | |
| 9294 | |
| 9295 format %{ "andq $dst, $src\t# long" %} | |
| 9296 opcode(0x81, 0x04); /* Opcode 81 /4 */ | |
| 9297 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 9298 ins_pipe(ialu_reg); | |
| 9299 %} | |
| 9300 | |
| 9301 // And Register with Memory | |
| 9302 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 9303 %{ | |
| 9304 match(Set dst (AndL dst (LoadL src))); | |
| 9305 effect(KILL cr); | |
| 9306 | |
| 9307 ins_cost(125); | |
| 9308 format %{ "andq $dst, $src\t# long" %} | |
| 9309 opcode(0x23); | |
| 9310 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 9311 ins_pipe(ialu_reg_mem); | |
| 9312 %} | |
| 9313 | |
| 9314 // And Memory with Register | |
| 9315 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 9316 %{ | |
| 9317 match(Set dst (StoreL dst (AndL (LoadL dst) src))); | |
| 9318 effect(KILL cr); | |
| 9319 | |
| 9320 ins_cost(150); | |
| 9321 format %{ "andq $dst, $src\t# long" %} | |
| 9322 opcode(0x21); /* Opcode 21 /r */ | |
| 9323 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 9324 ins_pipe(ialu_mem_reg); | |
| 9325 %} | |
| 9326 | |
| 9327 // And Memory with Immediate | |
| 9328 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 9329 %{ | |
| 9330 match(Set dst (StoreL dst (AndL (LoadL dst) src))); | |
| 9331 effect(KILL cr); | |
| 9332 | |
| 9333 ins_cost(125); | |
| 9334 format %{ "andq $dst, $src\t# long" %} | |
| 9335 opcode(0x81, 0x4); /* Opcode 81 /4 id */ | |
| 9336 ins_encode(REX_mem_wide(dst), OpcSE(src), | |
| 9337 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 9338 ins_pipe(ialu_mem_imm); | |
| 9339 %} | |
| 9340 | |
| 9341 // Or Instructions | |
| 9342 // Or Register with Register | |
| 9343 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 9344 %{ | |
| 9345 match(Set dst (OrL dst src)); | |
| 9346 effect(KILL cr); | |
| 9347 | |
| 9348 format %{ "orq $dst, $src\t# long" %} | |
| 9349 opcode(0x0B); | |
| 9350 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 9351 ins_pipe(ialu_reg_reg); | |
| 9352 %} | |
| 9353 | |
|
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9354 // Use any_RegP to match R15 (TLS register) without spilling. |
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9355 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{ |
|
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9356 match(Set dst (OrL dst (CastP2X src))); |
|
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9357 effect(KILL cr); |
|
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|
9358 |
|
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9359 format %{ "orq $dst, $src\t# long" %} |
|
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9360 opcode(0x0B); |
|
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9361 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); |
|
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9362 ins_pipe(ialu_reg_reg); |
|
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9363 %} |
|
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9364 |
|
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9365 |
| 0 | 9366 // Or Register with Immediate |
| 9367 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
| 9368 %{ | |
| 9369 match(Set dst (OrL dst src)); | |
| 9370 effect(KILL cr); | |
| 9371 | |
| 9372 format %{ "orq $dst, $src\t# long" %} | |
| 9373 opcode(0x81, 0x01); /* Opcode 81 /1 id */ | |
| 9374 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 9375 ins_pipe(ialu_reg); | |
| 9376 %} | |
| 9377 | |
| 9378 // Or Register with Memory | |
| 9379 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 9380 %{ | |
| 9381 match(Set dst (OrL dst (LoadL src))); | |
| 9382 effect(KILL cr); | |
| 9383 | |
| 9384 ins_cost(125); | |
| 9385 format %{ "orq $dst, $src\t# long" %} | |
| 9386 opcode(0x0B); | |
| 9387 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 9388 ins_pipe(ialu_reg_mem); | |
| 9389 %} | |
| 9390 | |
| 9391 // Or Memory with Register | |
| 9392 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 9393 %{ | |
| 9394 match(Set dst (StoreL dst (OrL (LoadL dst) src))); | |
| 9395 effect(KILL cr); | |
| 9396 | |
| 9397 ins_cost(150); | |
| 9398 format %{ "orq $dst, $src\t# long" %} | |
| 9399 opcode(0x09); /* Opcode 09 /r */ | |
| 9400 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 9401 ins_pipe(ialu_mem_reg); | |
| 9402 %} | |
| 9403 | |
| 9404 // Or Memory with Immediate | |
| 9405 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 9406 %{ | |
| 9407 match(Set dst (StoreL dst (OrL (LoadL dst) src))); | |
| 9408 effect(KILL cr); | |
| 9409 | |
| 9410 ins_cost(125); | |
| 9411 format %{ "orq $dst, $src\t# long" %} | |
| 9412 opcode(0x81, 0x1); /* Opcode 81 /1 id */ | |
| 9413 ins_encode(REX_mem_wide(dst), OpcSE(src), | |
| 9414 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 9415 ins_pipe(ialu_mem_imm); | |
| 9416 %} | |
| 9417 | |
| 9418 // Xor Instructions | |
| 9419 // Xor Register with Register | |
| 9420 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 9421 %{ | |
| 9422 match(Set dst (XorL dst src)); | |
| 9423 effect(KILL cr); | |
| 9424 | |
| 9425 format %{ "xorq $dst, $src\t# long" %} | |
| 9426 opcode(0x33); | |
| 9427 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 9428 ins_pipe(ialu_reg_reg); | |
| 9429 %} | |
| 9430 | |
| 403 | 9431 // Xor Register with Immediate -1 |
| 9432 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{ | |
|
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|
9433 match(Set dst (XorL dst imm)); |
|
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|
9434 |
|
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|
9435 format %{ "notq $dst" %} |
| 403 | 9436 ins_encode %{ |
| 9437 __ notq($dst$$Register); | |
| 9438 %} | |
| 9439 ins_pipe(ialu_reg); | |
| 9440 %} | |
| 9441 | |
| 0 | 9442 // Xor Register with Immediate |
| 9443 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
| 9444 %{ | |
| 9445 match(Set dst (XorL dst src)); | |
| 9446 effect(KILL cr); | |
| 9447 | |
| 9448 format %{ "xorq $dst, $src\t# long" %} | |
| 9449 opcode(0x81, 0x06); /* Opcode 81 /6 id */ | |
| 9450 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 9451 ins_pipe(ialu_reg); | |
| 9452 %} | |
| 9453 | |
| 9454 // Xor Register with Memory | |
| 9455 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 9456 %{ | |
| 9457 match(Set dst (XorL dst (LoadL src))); | |
| 9458 effect(KILL cr); | |
| 9459 | |
| 9460 ins_cost(125); | |
| 9461 format %{ "xorq $dst, $src\t# long" %} | |
| 9462 opcode(0x33); | |
| 9463 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 9464 ins_pipe(ialu_reg_mem); | |
| 9465 %} | |
| 9466 | |
| 9467 // Xor Memory with Register | |
| 9468 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 9469 %{ | |
| 9470 match(Set dst (StoreL dst (XorL (LoadL dst) src))); | |
| 9471 effect(KILL cr); | |
| 9472 | |
| 9473 ins_cost(150); | |
| 9474 format %{ "xorq $dst, $src\t# long" %} | |
| 9475 opcode(0x31); /* Opcode 31 /r */ | |
| 9476 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 9477 ins_pipe(ialu_mem_reg); | |
| 9478 %} | |
| 9479 | |
| 9480 // Xor Memory with Immediate | |
| 9481 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 9482 %{ | |
| 9483 match(Set dst (StoreL dst (XorL (LoadL dst) src))); | |
| 9484 effect(KILL cr); | |
| 9485 | |
| 9486 ins_cost(125); | |
| 9487 format %{ "xorq $dst, $src\t# long" %} | |
| 9488 opcode(0x81, 0x6); /* Opcode 81 /6 id */ | |
| 9489 ins_encode(REX_mem_wide(dst), OpcSE(src), | |
| 9490 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 9491 ins_pipe(ialu_mem_imm); | |
| 9492 %} | |
| 9493 | |
| 9494 // Convert Int to Boolean | |
| 9495 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr) | |
| 9496 %{ | |
| 9497 match(Set dst (Conv2B src)); | |
| 9498 effect(KILL cr); | |
| 9499 | |
| 9500 format %{ "testl $src, $src\t# ci2b\n\t" | |
| 9501 "setnz $dst\n\t" | |
| 9502 "movzbl $dst, $dst" %} | |
| 9503 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl | |
| 9504 setNZ_reg(dst), | |
| 9505 REX_reg_breg(dst, dst), // movzbl | |
| 9506 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst)); | |
| 9507 ins_pipe(pipe_slow); // XXX | |
| 9508 %} | |
| 9509 | |
| 9510 // Convert Pointer to Boolean | |
| 9511 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr) | |
| 9512 %{ | |
| 9513 match(Set dst (Conv2B src)); | |
| 9514 effect(KILL cr); | |
| 9515 | |
| 9516 format %{ "testq $src, $src\t# cp2b\n\t" | |
| 9517 "setnz $dst\n\t" | |
| 9518 "movzbl $dst, $dst" %} | |
| 9519 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq | |
| 9520 setNZ_reg(dst), | |
| 9521 REX_reg_breg(dst, dst), // movzbl | |
| 9522 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst)); | |
| 9523 ins_pipe(pipe_slow); // XXX | |
| 9524 %} | |
| 9525 | |
| 9526 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr) | |
| 9527 %{ | |
| 9528 match(Set dst (CmpLTMask p q)); | |
| 9529 effect(KILL cr); | |
| 9530 | |
| 9531 ins_cost(400); // XXX | |
| 9532 format %{ "cmpl $p, $q\t# cmpLTMask\n\t" | |
| 9533 "setlt $dst\n\t" | |
| 9534 "movzbl $dst, $dst\n\t" | |
| 9535 "negl $dst" %} | |
| 9536 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl | |
| 9537 setLT_reg(dst), | |
| 9538 REX_reg_breg(dst, dst), // movzbl | |
| 9539 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst), | |
| 9540 neg_reg(dst)); | |
| 9541 ins_pipe(pipe_slow); | |
| 9542 %} | |
| 9543 | |
| 9544 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr) | |
| 9545 %{ | |
| 9546 match(Set dst (CmpLTMask dst zero)); | |
| 9547 effect(KILL cr); | |
| 9548 | |
| 9549 ins_cost(100); // XXX | |
| 9550 format %{ "sarl $dst, #31\t# cmpLTMask0" %} | |
| 9551 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 9552 ins_encode(reg_opc_imm(dst, 0x1F)); | |
| 9553 ins_pipe(ialu_reg); | |
| 9554 %} | |
| 9555 | |
| 9556 | |
|
3738
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parents:
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diff
changeset
|
9557 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rRegI tmp, rFlagsReg cr) |
| 0 | 9558 %{ |
| 9559 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); | |
| 9560 effect(TEMP tmp, KILL cr); | |
| 9561 | |
| 9562 ins_cost(400); // XXX | |
| 9563 format %{ "subl $p, $q\t# cadd_cmpLTMask1\n\t" | |
| 9564 "sbbl $tmp, $tmp\n\t" | |
| 9565 "andl $tmp, $y\n\t" | |
| 9566 "addl $p, $tmp" %} | |
|
3738
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diff
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|
9567 ins_encode %{ |
|
c7c81f18c834
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diff
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|
9568 Register Rp = $p$$Register; |
|
c7c81f18c834
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parents:
2404
diff
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|
9569 Register Rq = $q$$Register; |
|
c7c81f18c834
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parents:
2404
diff
changeset
|
9570 Register Ry = $y$$Register; |
|
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2404
diff
changeset
|
9571 Register Rt = $tmp$$Register; |
|
c7c81f18c834
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parents:
2404
diff
changeset
|
9572 __ subl(Rp, Rq); |
|
c7c81f18c834
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parents:
2404
diff
changeset
|
9573 __ sbbl(Rt, Rt); |
|
c7c81f18c834
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parents:
2404
diff
changeset
|
9574 __ andl(Rt, Ry); |
|
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parents:
2404
diff
changeset
|
9575 __ addl(Rp, Rt); |
|
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2404
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changeset
|
9576 %} |
| 0 | 9577 ins_pipe(pipe_cmplt); |
| 9578 %} | |
| 9579 | |
| 9580 //---------- FP Instructions------------------------------------------------ | |
| 9581 | |
| 9582 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2) | |
| 9583 %{ | |
| 9584 match(Set cr (CmpF src1 src2)); | |
| 9585 | |
| 9586 ins_cost(145); | |
| 9587 format %{ "ucomiss $src1, $src2\n\t" | |
| 9588 "jnp,s exit\n\t" | |
| 9589 "pushfq\t# saw NaN, set CF\n\t" | |
| 9590 "andq [rsp], #0xffffff2b\n\t" | |
| 9591 "popfq\n" | |
| 4759 | 9592 "exit:" %} |
| 9593 ins_encode %{ | |
| 9594 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9595 emit_cmpfp_fixup(_masm); | |
| 9596 %} | |
| 0 | 9597 ins_pipe(pipe_slow); |
| 9598 %} | |
| 9599 | |
|
415
4d9884b01ba6
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diff
changeset
|
9600 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{ |
|
4d9884b01ba6
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403
diff
changeset
|
9601 match(Set cr (CmpF src1 src2)); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
9602 |
| 4759 | 9603 ins_cost(100); |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9604 format %{ "ucomiss $src1, $src2" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9605 ins_encode %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9606 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9607 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9608 ins_pipe(pipe_slow); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9609 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9610 |
| 0 | 9611 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2) |
| 9612 %{ | |
| 9613 match(Set cr (CmpF src1 (LoadF src2))); | |
| 9614 | |
| 9615 ins_cost(145); | |
| 9616 format %{ "ucomiss $src1, $src2\n\t" | |
| 9617 "jnp,s exit\n\t" | |
| 9618 "pushfq\t# saw NaN, set CF\n\t" | |
| 9619 "andq [rsp], #0xffffff2b\n\t" | |
| 9620 "popfq\n" | |
| 4759 | 9621 "exit:" %} |
| 9622 ins_encode %{ | |
| 9623 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 9624 emit_cmpfp_fixup(_masm); | |
| 9625 %} | |
| 0 | 9626 ins_pipe(pipe_slow); |
| 9627 %} | |
| 9628 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9629 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9630 match(Set cr (CmpF src1 (LoadF src2))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9631 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9632 ins_cost(100); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9633 format %{ "ucomiss $src1, $src2" %} |
| 4759 | 9634 ins_encode %{ |
| 9635 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 9636 %} | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9637 ins_pipe(pipe_slow); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9638 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9639 |
| 2008 | 9640 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{ |
| 9641 match(Set cr (CmpF src con)); | |
| 0 | 9642 |
| 9643 ins_cost(145); | |
| 2008 | 9644 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t" |
| 0 | 9645 "jnp,s exit\n\t" |
| 9646 "pushfq\t# saw NaN, set CF\n\t" | |
| 9647 "andq [rsp], #0xffffff2b\n\t" | |
| 9648 "popfq\n" | |
| 4759 | 9649 "exit:" %} |
| 2008 | 9650 ins_encode %{ |
| 9651 __ ucomiss($src$$XMMRegister, $constantaddress($con)); | |
| 3783 | 9652 emit_cmpfp_fixup(_masm); |
| 2008 | 9653 %} |
| 9654 ins_pipe(pipe_slow); | |
| 9655 %} | |
| 9656 | |
| 9657 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{ | |
| 9658 match(Set cr (CmpF src con)); | |
|
415
4d9884b01ba6
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parents:
403
diff
changeset
|
9659 ins_cost(100); |
| 2008 | 9660 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %} |
| 9661 ins_encode %{ | |
| 9662 __ ucomiss($src$$XMMRegister, $constantaddress($con)); | |
| 9663 %} | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9664 ins_pipe(pipe_slow); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9665 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9666 |
| 0 | 9667 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2) |
| 9668 %{ | |
| 9669 match(Set cr (CmpD src1 src2)); | |
| 9670 | |
| 9671 ins_cost(145); | |
| 9672 format %{ "ucomisd $src1, $src2\n\t" | |
| 9673 "jnp,s exit\n\t" | |
| 9674 "pushfq\t# saw NaN, set CF\n\t" | |
| 9675 "andq [rsp], #0xffffff2b\n\t" | |
| 9676 "popfq\n" | |
| 4759 | 9677 "exit:" %} |
| 9678 ins_encode %{ | |
| 9679 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9680 emit_cmpfp_fixup(_masm); | |
| 9681 %} | |
| 0 | 9682 ins_pipe(pipe_slow); |
| 9683 %} | |
| 9684 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
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403
diff
changeset
|
9685 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{ |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
9686 match(Set cr (CmpD src1 src2)); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
9687 |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
9688 ins_cost(100); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9689 format %{ "ucomisd $src1, $src2 test" %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
9690 ins_encode %{ |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
9691 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9692 %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
9693 ins_pipe(pipe_slow); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9694 %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
9695 |
| 0 | 9696 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2) |
| 9697 %{ | |
| 9698 match(Set cr (CmpD src1 (LoadD src2))); | |
| 9699 | |
| 9700 ins_cost(145); | |
| 9701 format %{ "ucomisd $src1, $src2\n\t" | |
| 9702 "jnp,s exit\n\t" | |
| 9703 "pushfq\t# saw NaN, set CF\n\t" | |
| 9704 "andq [rsp], #0xffffff2b\n\t" | |
| 9705 "popfq\n" | |
| 4759 | 9706 "exit:" %} |
| 9707 ins_encode %{ | |
| 9708 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9709 emit_cmpfp_fixup(_masm); | |
| 9710 %} | |
| 0 | 9711 ins_pipe(pipe_slow); |
| 9712 %} | |
| 9713 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9714 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9715 match(Set cr (CmpD src1 (LoadD src2))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9716 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
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diff
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|
9717 ins_cost(100); |
|
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|
9718 format %{ "ucomisd $src1, $src2" %} |
| 4759 | 9719 ins_encode %{ |
| 9720 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9721 %} | |
|
415
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|
9722 ins_pipe(pipe_slow); |
|
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|
9723 %} |
|
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|
9724 |
| 2008 | 9725 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{ |
| 9726 match(Set cr (CmpD src con)); | |
| 0 | 9727 |
| 9728 ins_cost(145); | |
| 2008 | 9729 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 9730 "jnp,s exit\n\t" |
| 9731 "pushfq\t# saw NaN, set CF\n\t" | |
| 9732 "andq [rsp], #0xffffff2b\n\t" | |
| 9733 "popfq\n" | |
| 4759 | 9734 "exit:" %} |
| 2008 | 9735 ins_encode %{ |
| 9736 __ ucomisd($src$$XMMRegister, $constantaddress($con)); | |
| 3783 | 9737 emit_cmpfp_fixup(_masm); |
| 2008 | 9738 %} |
| 9739 ins_pipe(pipe_slow); | |
| 9740 %} | |
| 9741 | |
| 9742 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{ | |
| 9743 match(Set cr (CmpD src con)); | |
|
415
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|
9744 ins_cost(100); |
| 2008 | 9745 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %} |
| 9746 ins_encode %{ | |
| 9747 __ ucomisd($src$$XMMRegister, $constantaddress($con)); | |
| 9748 %} | |
|
415
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|
9749 ins_pipe(pipe_slow); |
|
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|
9750 %} |
|
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|
9751 |
| 0 | 9752 // Compare into -1,0,1 |
| 9753 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr) | |
| 9754 %{ | |
| 9755 match(Set dst (CmpF3 src1 src2)); | |
| 9756 effect(KILL cr); | |
| 9757 | |
| 9758 ins_cost(275); | |
| 9759 format %{ "ucomiss $src1, $src2\n\t" | |
| 9760 "movl $dst, #-1\n\t" | |
| 9761 "jp,s done\n\t" | |
| 9762 "jb,s done\n\t" | |
| 9763 "setne $dst\n\t" | |
| 9764 "movzbl $dst, $dst\n" | |
| 9765 "done:" %} | |
| 4759 | 9766 ins_encode %{ |
| 9767 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9768 emit_cmpfp3(_masm, $dst$$Register); | |
| 9769 %} | |
| 0 | 9770 ins_pipe(pipe_slow); |
| 9771 %} | |
| 9772 | |
| 9773 // Compare into -1,0,1 | |
| 9774 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr) | |
| 9775 %{ | |
| 9776 match(Set dst (CmpF3 src1 (LoadF src2))); | |
| 9777 effect(KILL cr); | |
| 9778 | |
| 9779 ins_cost(275); | |
| 9780 format %{ "ucomiss $src1, $src2\n\t" | |
| 9781 "movl $dst, #-1\n\t" | |
| 9782 "jp,s done\n\t" | |
| 9783 "jb,s done\n\t" | |
| 9784 "setne $dst\n\t" | |
| 9785 "movzbl $dst, $dst\n" | |
| 9786 "done:" %} | |
| 4759 | 9787 ins_encode %{ |
| 9788 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 9789 emit_cmpfp3(_masm, $dst$$Register); | |
| 9790 %} | |
| 0 | 9791 ins_pipe(pipe_slow); |
| 9792 %} | |
| 9793 | |
| 9794 // Compare into -1,0,1 | |
| 2008 | 9795 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{ |
| 9796 match(Set dst (CmpF3 src con)); | |
| 0 | 9797 effect(KILL cr); |
| 9798 | |
| 9799 ins_cost(275); | |
| 2008 | 9800 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t" |
| 0 | 9801 "movl $dst, #-1\n\t" |
| 9802 "jp,s done\n\t" | |
| 9803 "jb,s done\n\t" | |
| 9804 "setne $dst\n\t" | |
| 9805 "movzbl $dst, $dst\n" | |
| 9806 "done:" %} | |
| 2008 | 9807 ins_encode %{ |
| 9808 __ ucomiss($src$$XMMRegister, $constantaddress($con)); | |
| 4759 | 9809 emit_cmpfp3(_masm, $dst$$Register); |
| 2008 | 9810 %} |
| 0 | 9811 ins_pipe(pipe_slow); |
| 9812 %} | |
| 9813 | |
| 9814 // Compare into -1,0,1 | |
| 9815 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr) | |
| 9816 %{ | |
| 9817 match(Set dst (CmpD3 src1 src2)); | |
| 9818 effect(KILL cr); | |
| 9819 | |
| 9820 ins_cost(275); | |
| 9821 format %{ "ucomisd $src1, $src2\n\t" | |
| 9822 "movl $dst, #-1\n\t" | |
| 9823 "jp,s done\n\t" | |
| 9824 "jb,s done\n\t" | |
| 9825 "setne $dst\n\t" | |
| 9826 "movzbl $dst, $dst\n" | |
| 9827 "done:" %} | |
| 4759 | 9828 ins_encode %{ |
| 9829 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9830 emit_cmpfp3(_masm, $dst$$Register); | |
| 9831 %} | |
| 0 | 9832 ins_pipe(pipe_slow); |
| 9833 %} | |
| 9834 | |
| 9835 // Compare into -1,0,1 | |
| 9836 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr) | |
| 9837 %{ | |
| 9838 match(Set dst (CmpD3 src1 (LoadD src2))); | |
| 9839 effect(KILL cr); | |
| 9840 | |
| 9841 ins_cost(275); | |
| 9842 format %{ "ucomisd $src1, $src2\n\t" | |
| 9843 "movl $dst, #-1\n\t" | |
| 9844 "jp,s done\n\t" | |
| 9845 "jb,s done\n\t" | |
| 9846 "setne $dst\n\t" | |
| 9847 "movzbl $dst, $dst\n" | |
| 9848 "done:" %} | |
| 4759 | 9849 ins_encode %{ |
| 9850 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9851 emit_cmpfp3(_masm, $dst$$Register); | |
| 9852 %} | |
| 0 | 9853 ins_pipe(pipe_slow); |
| 9854 %} | |
| 9855 | |
| 9856 // Compare into -1,0,1 | |
| 2008 | 9857 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{ |
| 9858 match(Set dst (CmpD3 src con)); | |
| 0 | 9859 effect(KILL cr); |
| 9860 | |
| 9861 ins_cost(275); | |
| 2008 | 9862 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 9863 "movl $dst, #-1\n\t" |
| 9864 "jp,s done\n\t" | |
| 9865 "jb,s done\n\t" | |
| 9866 "setne $dst\n\t" | |
| 9867 "movzbl $dst, $dst\n" | |
| 9868 "done:" %} | |
| 2008 | 9869 ins_encode %{ |
| 9870 __ ucomisd($src$$XMMRegister, $constantaddress($con)); | |
| 4759 | 9871 emit_cmpfp3(_masm, $dst$$Register); |
| 2008 | 9872 %} |
| 0 | 9873 ins_pipe(pipe_slow); |
| 9874 %} | |
| 9875 | |
| 9876 // -----------Trig and Trancendental Instructions------------------------------ | |
| 9877 instruct cosD_reg(regD dst) %{ | |
| 9878 match(Set dst (CosD dst)); | |
| 9879 | |
| 9880 format %{ "dcos $dst\n\t" %} | |
| 9881 opcode(0xD9, 0xFF); | |
| 9882 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) ); | |
| 9883 ins_pipe( pipe_slow ); | |
| 9884 %} | |
| 9885 | |
| 9886 instruct sinD_reg(regD dst) %{ | |
| 9887 match(Set dst (SinD dst)); | |
| 9888 | |
| 9889 format %{ "dsin $dst\n\t" %} | |
| 9890 opcode(0xD9, 0xFE); | |
| 9891 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) ); | |
| 9892 ins_pipe( pipe_slow ); | |
| 9893 %} | |
| 9894 | |
| 9895 instruct tanD_reg(regD dst) %{ | |
| 9896 match(Set dst (TanD dst)); | |
| 9897 | |
| 9898 format %{ "dtan $dst\n\t" %} | |
| 9899 ins_encode( Push_SrcXD(dst), | |
| 9900 Opcode(0xD9), Opcode(0xF2), //fptan | |
| 9901 Opcode(0xDD), Opcode(0xD8), //fstp st | |
| 9902 Push_ResultXD(dst) ); | |
| 9903 ins_pipe( pipe_slow ); | |
| 9904 %} | |
| 9905 | |
| 9906 instruct log10D_reg(regD dst) %{ | |
| 9907 // The source and result Double operands in XMM registers | |
| 9908 match(Set dst (Log10D dst)); | |
| 9909 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number | |
| 9910 // fyl2x ; compute log_10(2) * log_2(x) | |
| 9911 format %{ "fldlg2\t\t\t#Log10\n\t" | |
| 9912 "fyl2x\t\t\t# Q=Log10*Log_2(x)\n\t" | |
| 9913 %} | |
| 9914 ins_encode(Opcode(0xD9), Opcode(0xEC), // fldlg2 | |
| 9915 Push_SrcXD(dst), | |
| 9916 Opcode(0xD9), Opcode(0xF1), // fyl2x | |
| 9917 Push_ResultXD(dst)); | |
| 9918 | |
| 9919 ins_pipe( pipe_slow ); | |
| 9920 %} | |
| 9921 | |
| 9922 instruct logD_reg(regD dst) %{ | |
| 9923 // The source and result Double operands in XMM registers | |
| 9924 match(Set dst (LogD dst)); | |
| 9925 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number | |
| 9926 // fyl2x ; compute log_e(2) * log_2(x) | |
| 9927 format %{ "fldln2\t\t\t#Log_e\n\t" | |
| 9928 "fyl2x\t\t\t# Q=Log_e*Log_2(x)\n\t" | |
| 9929 %} | |
| 9930 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 | |
| 9931 Push_SrcXD(dst), | |
| 9932 Opcode(0xD9), Opcode(0xF1), // fyl2x | |
| 9933 Push_ResultXD(dst)); | |
| 9934 ins_pipe( pipe_slow ); | |
| 9935 %} | |
| 9936 | |
| 9937 | |
| 9938 | |
| 9939 //----------Arithmetic Conversion Instructions--------------------------------- | |
| 9940 | |
| 9941 instruct roundFloat_nop(regF dst) | |
| 9942 %{ | |
| 9943 match(Set dst (RoundFloat dst)); | |
| 9944 | |
| 9945 ins_cost(0); | |
| 9946 ins_encode(); | |
| 9947 ins_pipe(empty); | |
| 9948 %} | |
| 9949 | |
| 9950 instruct roundDouble_nop(regD dst) | |
| 9951 %{ | |
| 9952 match(Set dst (RoundDouble dst)); | |
| 9953 | |
| 9954 ins_cost(0); | |
| 9955 ins_encode(); | |
| 9956 ins_pipe(empty); | |
| 9957 %} | |
| 9958 | |
| 9959 instruct convF2D_reg_reg(regD dst, regF src) | |
| 9960 %{ | |
| 9961 match(Set dst (ConvF2D src)); | |
| 9962 | |
| 9963 format %{ "cvtss2sd $dst, $src" %} | |
| 4759 | 9964 ins_encode %{ |
| 9965 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister); | |
| 9966 %} | |
| 0 | 9967 ins_pipe(pipe_slow); // XXX |
| 9968 %} | |
| 9969 | |
| 9970 instruct convF2D_reg_mem(regD dst, memory src) | |
| 9971 %{ | |
| 9972 match(Set dst (ConvF2D (LoadF src))); | |
| 9973 | |
| 9974 format %{ "cvtss2sd $dst, $src" %} | |
| 4759 | 9975 ins_encode %{ |
| 9976 __ cvtss2sd ($dst$$XMMRegister, $src$$Address); | |
| 9977 %} | |
| 0 | 9978 ins_pipe(pipe_slow); // XXX |
| 9979 %} | |
| 9980 | |
| 9981 instruct convD2F_reg_reg(regF dst, regD src) | |
| 9982 %{ | |
| 9983 match(Set dst (ConvD2F src)); | |
| 9984 | |
| 9985 format %{ "cvtsd2ss $dst, $src" %} | |
| 4759 | 9986 ins_encode %{ |
| 9987 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister); | |
| 9988 %} | |
| 0 | 9989 ins_pipe(pipe_slow); // XXX |
| 9990 %} | |
| 9991 | |
| 9992 instruct convD2F_reg_mem(regF dst, memory src) | |
| 9993 %{ | |
| 9994 match(Set dst (ConvD2F (LoadD src))); | |
| 9995 | |
| 9996 format %{ "cvtsd2ss $dst, $src" %} | |
| 4759 | 9997 ins_encode %{ |
| 9998 __ cvtsd2ss ($dst$$XMMRegister, $src$$Address); | |
| 9999 %} | |
| 0 | 10000 ins_pipe(pipe_slow); // XXX |
| 10001 %} | |
| 10002 | |
| 10003 // XXX do mem variants | |
| 10004 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr) | |
| 10005 %{ | |
| 10006 match(Set dst (ConvF2I src)); | |
| 10007 effect(KILL cr); | |
| 10008 | |
| 10009 format %{ "cvttss2sil $dst, $src\t# f2i\n\t" | |
| 10010 "cmpl $dst, #0x80000000\n\t" | |
| 10011 "jne,s done\n\t" | |
| 10012 "subq rsp, #8\n\t" | |
| 10013 "movss [rsp], $src\n\t" | |
| 10014 "call f2i_fixup\n\t" | |
| 10015 "popq $dst\n" | |
| 10016 "done: "%} | |
| 4759 | 10017 ins_encode %{ |
| 10018 Label done; | |
| 10019 __ cvttss2sil($dst$$Register, $src$$XMMRegister); | |
| 10020 __ cmpl($dst$$Register, 0x80000000); | |
| 10021 __ jccb(Assembler::notEqual, done); | |
| 10022 __ subptr(rsp, 8); | |
| 10023 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 10024 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup()))); | |
| 10025 __ pop($dst$$Register); | |
| 10026 __ bind(done); | |
| 10027 %} | |
| 0 | 10028 ins_pipe(pipe_slow); |
| 10029 %} | |
| 10030 | |
| 10031 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr) | |
| 10032 %{ | |
| 10033 match(Set dst (ConvF2L src)); | |
| 10034 effect(KILL cr); | |
| 10035 | |
| 10036 format %{ "cvttss2siq $dst, $src\t# f2l\n\t" | |
| 10037 "cmpq $dst, [0x8000000000000000]\n\t" | |
| 10038 "jne,s done\n\t" | |
| 10039 "subq rsp, #8\n\t" | |
| 10040 "movss [rsp], $src\n\t" | |
| 10041 "call f2l_fixup\n\t" | |
| 10042 "popq $dst\n" | |
| 10043 "done: "%} | |
| 4759 | 10044 ins_encode %{ |
| 10045 Label done; | |
| 10046 __ cvttss2siq($dst$$Register, $src$$XMMRegister); | |
| 10047 __ cmp64($dst$$Register, | |
| 10048 ExternalAddress((address) StubRoutines::x86::double_sign_flip())); | |
| 10049 __ jccb(Assembler::notEqual, done); | |
| 10050 __ subptr(rsp, 8); | |
| 10051 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 10052 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup()))); | |
| 10053 __ pop($dst$$Register); | |
| 10054 __ bind(done); | |
| 10055 %} | |
| 0 | 10056 ins_pipe(pipe_slow); |
| 10057 %} | |
| 10058 | |
| 10059 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr) | |
| 10060 %{ | |
| 10061 match(Set dst (ConvD2I src)); | |
| 10062 effect(KILL cr); | |
| 10063 | |
| 10064 format %{ "cvttsd2sil $dst, $src\t# d2i\n\t" | |
| 10065 "cmpl $dst, #0x80000000\n\t" | |
| 10066 "jne,s done\n\t" | |
| 10067 "subq rsp, #8\n\t" | |
| 10068 "movsd [rsp], $src\n\t" | |
| 10069 "call d2i_fixup\n\t" | |
| 10070 "popq $dst\n" | |
| 10071 "done: "%} | |
| 4759 | 10072 ins_encode %{ |
| 10073 Label done; | |
| 10074 __ cvttsd2sil($dst$$Register, $src$$XMMRegister); | |
| 10075 __ cmpl($dst$$Register, 0x80000000); | |
| 10076 __ jccb(Assembler::notEqual, done); | |
| 10077 __ subptr(rsp, 8); | |
| 10078 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 10079 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup()))); | |
| 10080 __ pop($dst$$Register); | |
| 10081 __ bind(done); | |
| 10082 %} | |
| 0 | 10083 ins_pipe(pipe_slow); |
| 10084 %} | |
| 10085 | |
| 10086 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr) | |
| 10087 %{ | |
| 10088 match(Set dst (ConvD2L src)); | |
| 10089 effect(KILL cr); | |
| 10090 | |
| 10091 format %{ "cvttsd2siq $dst, $src\t# d2l\n\t" | |
| 10092 "cmpq $dst, [0x8000000000000000]\n\t" | |
| 10093 "jne,s done\n\t" | |
| 10094 "subq rsp, #8\n\t" | |
| 10095 "movsd [rsp], $src\n\t" | |
| 10096 "call d2l_fixup\n\t" | |
| 10097 "popq $dst\n" | |
| 10098 "done: "%} | |
| 4759 | 10099 ins_encode %{ |
| 10100 Label done; | |
| 10101 __ cvttsd2siq($dst$$Register, $src$$XMMRegister); | |
| 10102 __ cmp64($dst$$Register, | |
| 10103 ExternalAddress((address) StubRoutines::x86::double_sign_flip())); | |
| 10104 __ jccb(Assembler::notEqual, done); | |
| 10105 __ subptr(rsp, 8); | |
| 10106 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 10107 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup()))); | |
| 10108 __ pop($dst$$Register); | |
| 10109 __ bind(done); | |
| 10110 %} | |
| 0 | 10111 ins_pipe(pipe_slow); |
| 10112 %} | |
| 10113 | |
| 10114 instruct convI2F_reg_reg(regF dst, rRegI src) | |
| 10115 %{ | |
| 71 | 10116 predicate(!UseXmmI2F); |
| 0 | 10117 match(Set dst (ConvI2F src)); |
| 10118 | |
| 10119 format %{ "cvtsi2ssl $dst, $src\t# i2f" %} | |
| 4759 | 10120 ins_encode %{ |
| 10121 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register); | |
| 10122 %} | |
| 0 | 10123 ins_pipe(pipe_slow); // XXX |
| 10124 %} | |
| 10125 | |
| 10126 instruct convI2F_reg_mem(regF dst, memory src) | |
| 10127 %{ | |
| 10128 match(Set dst (ConvI2F (LoadI src))); | |
| 10129 | |
| 10130 format %{ "cvtsi2ssl $dst, $src\t# i2f" %} | |
| 4759 | 10131 ins_encode %{ |
| 10132 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address); | |
| 10133 %} | |
| 0 | 10134 ins_pipe(pipe_slow); // XXX |
| 10135 %} | |
| 10136 | |
| 10137 instruct convI2D_reg_reg(regD dst, rRegI src) | |
| 10138 %{ | |
| 71 | 10139 predicate(!UseXmmI2D); |
| 0 | 10140 match(Set dst (ConvI2D src)); |
| 10141 | |
| 10142 format %{ "cvtsi2sdl $dst, $src\t# i2d" %} | |
| 4759 | 10143 ins_encode %{ |
| 10144 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register); | |
| 10145 %} | |
| 0 | 10146 ins_pipe(pipe_slow); // XXX |
| 10147 %} | |
| 10148 | |
| 10149 instruct convI2D_reg_mem(regD dst, memory src) | |
| 10150 %{ | |
| 10151 match(Set dst (ConvI2D (LoadI src))); | |
| 10152 | |
| 10153 format %{ "cvtsi2sdl $dst, $src\t# i2d" %} | |
| 4759 | 10154 ins_encode %{ |
| 10155 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address); | |
| 10156 %} | |
| 0 | 10157 ins_pipe(pipe_slow); // XXX |
| 10158 %} | |
| 10159 | |
| 71 | 10160 instruct convXI2F_reg(regF dst, rRegI src) |
| 10161 %{ | |
| 10162 predicate(UseXmmI2F); | |
| 10163 match(Set dst (ConvI2F src)); | |
| 10164 | |
| 10165 format %{ "movdl $dst, $src\n\t" | |
| 10166 "cvtdq2psl $dst, $dst\t# i2f" %} | |
| 10167 ins_encode %{ | |
| 10168 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 10169 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister); | |
| 10170 %} | |
| 10171 ins_pipe(pipe_slow); // XXX | |
| 10172 %} | |
| 10173 | |
| 10174 instruct convXI2D_reg(regD dst, rRegI src) | |
| 10175 %{ | |
| 10176 predicate(UseXmmI2D); | |
| 10177 match(Set dst (ConvI2D src)); | |
| 10178 | |
| 10179 format %{ "movdl $dst, $src\n\t" | |
| 10180 "cvtdq2pdl $dst, $dst\t# i2d" %} | |
| 10181 ins_encode %{ | |
| 10182 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 10183 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister); | |
| 10184 %} | |
| 10185 ins_pipe(pipe_slow); // XXX | |
| 10186 %} | |
| 10187 | |
| 0 | 10188 instruct convL2F_reg_reg(regF dst, rRegL src) |
| 10189 %{ | |
| 10190 match(Set dst (ConvL2F src)); | |
| 10191 | |
| 10192 format %{ "cvtsi2ssq $dst, $src\t# l2f" %} | |
| 4759 | 10193 ins_encode %{ |
| 10194 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register); | |
| 10195 %} | |
| 0 | 10196 ins_pipe(pipe_slow); // XXX |
| 10197 %} | |
| 10198 | |
| 10199 instruct convL2F_reg_mem(regF dst, memory src) | |
| 10200 %{ | |
| 10201 match(Set dst (ConvL2F (LoadL src))); | |
| 10202 | |
| 10203 format %{ "cvtsi2ssq $dst, $src\t# l2f" %} | |
| 4759 | 10204 ins_encode %{ |
| 10205 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address); | |
| 10206 %} | |
| 0 | 10207 ins_pipe(pipe_slow); // XXX |
| 10208 %} | |
| 10209 | |
| 10210 instruct convL2D_reg_reg(regD dst, rRegL src) | |
| 10211 %{ | |
| 10212 match(Set dst (ConvL2D src)); | |
| 10213 | |
| 10214 format %{ "cvtsi2sdq $dst, $src\t# l2d" %} | |
| 4759 | 10215 ins_encode %{ |
| 10216 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register); | |
| 10217 %} | |
| 0 | 10218 ins_pipe(pipe_slow); // XXX |
| 10219 %} | |
| 10220 | |
| 10221 instruct convL2D_reg_mem(regD dst, memory src) | |
| 10222 %{ | |
| 10223 match(Set dst (ConvL2D (LoadL src))); | |
| 10224 | |
| 10225 format %{ "cvtsi2sdq $dst, $src\t# l2d" %} | |
| 4759 | 10226 ins_encode %{ |
| 10227 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address); | |
| 10228 %} | |
| 0 | 10229 ins_pipe(pipe_slow); // XXX |
| 10230 %} | |
| 10231 | |
| 10232 instruct convI2L_reg_reg(rRegL dst, rRegI src) | |
| 10233 %{ | |
| 10234 match(Set dst (ConvI2L src)); | |
| 10235 | |
| 10236 ins_cost(125); | |
| 10237 format %{ "movslq $dst, $src\t# i2l" %} | |
| 824 | 10238 ins_encode %{ |
| 10239 __ movslq($dst$$Register, $src$$Register); | |
| 10240 %} | |
| 0 | 10241 ins_pipe(ialu_reg_reg); |
| 10242 %} | |
| 10243 | |
| 10244 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src) | |
| 10245 // %{ | |
| 10246 // match(Set dst (ConvI2L src)); | |
| 10247 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 && | |
| 10248 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0); | |
| 10249 // predicate(((const TypeNode*) n)->type()->is_long()->_hi == | |
| 10250 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi && | |
| 10251 // ((const TypeNode*) n)->type()->is_long()->_lo == | |
| 10252 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo); | |
| 10253 | |
| 10254 // format %{ "movl $dst, $src\t# unsigned i2l" %} | |
| 10255 // ins_encode(enc_copy(dst, src)); | |
| 10256 // // opcode(0x63); // needs REX.W | |
| 10257 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src)); | |
| 10258 // ins_pipe(ialu_reg_reg); | |
| 10259 // %} | |
| 10260 | |
| 10261 // Zero-extend convert int to long | |
| 10262 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask) | |
| 10263 %{ | |
| 10264 match(Set dst (AndL (ConvI2L src) mask)); | |
| 10265 | |
| 10266 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %} | |
| 4759 | 10267 ins_encode %{ |
| 10268 if ($dst$$reg != $src$$reg) { | |
| 10269 __ movl($dst$$Register, $src$$Register); | |
| 10270 } | |
| 10271 %} | |
| 0 | 10272 ins_pipe(ialu_reg_reg); |
| 10273 %} | |
| 10274 | |
| 10275 // Zero-extend convert int to long | |
| 10276 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask) | |
| 10277 %{ | |
| 10278 match(Set dst (AndL (ConvI2L (LoadI src)) mask)); | |
| 10279 | |
| 10280 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %} | |
| 4759 | 10281 ins_encode %{ |
| 10282 __ movl($dst$$Register, $src$$Address); | |
| 10283 %} | |
| 0 | 10284 ins_pipe(ialu_reg_mem); |
| 10285 %} | |
| 10286 | |
| 10287 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask) | |
| 10288 %{ | |
| 10289 match(Set dst (AndL src mask)); | |
| 10290 | |
| 10291 format %{ "movl $dst, $src\t# zero-extend long" %} | |
| 4759 | 10292 ins_encode %{ |
| 10293 __ movl($dst$$Register, $src$$Register); | |
| 10294 %} | |
| 0 | 10295 ins_pipe(ialu_reg_reg); |
| 10296 %} | |
| 10297 | |
| 10298 instruct convL2I_reg_reg(rRegI dst, rRegL src) | |
| 10299 %{ | |
| 10300 match(Set dst (ConvL2I src)); | |
| 10301 | |
| 10302 format %{ "movl $dst, $src\t# l2i" %} | |
| 4759 | 10303 ins_encode %{ |
| 10304 __ movl($dst$$Register, $src$$Register); | |
| 10305 %} | |
| 0 | 10306 ins_pipe(ialu_reg_reg); |
| 10307 %} | |
| 10308 | |
| 10309 | |
| 10310 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{ | |
| 10311 match(Set dst (MoveF2I src)); | |
| 10312 effect(DEF dst, USE src); | |
| 10313 | |
| 10314 ins_cost(125); | |
| 10315 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %} | |
| 4759 | 10316 ins_encode %{ |
| 10317 __ movl($dst$$Register, Address(rsp, $src$$disp)); | |
| 10318 %} | |
| 0 | 10319 ins_pipe(ialu_reg_mem); |
| 10320 %} | |
| 10321 | |
| 10322 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ | |
| 10323 match(Set dst (MoveI2F src)); | |
| 10324 effect(DEF dst, USE src); | |
| 10325 | |
| 10326 ins_cost(125); | |
| 10327 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %} | |
| 4759 | 10328 ins_encode %{ |
| 10329 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 10330 %} | |
| 0 | 10331 ins_pipe(pipe_slow); |
| 10332 %} | |
| 10333 | |
| 10334 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{ | |
| 10335 match(Set dst (MoveD2L src)); | |
| 10336 effect(DEF dst, USE src); | |
| 10337 | |
| 10338 ins_cost(125); | |
| 10339 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %} | |
| 4759 | 10340 ins_encode %{ |
| 10341 __ movq($dst$$Register, Address(rsp, $src$$disp)); | |
| 10342 %} | |
| 0 | 10343 ins_pipe(ialu_reg_mem); |
| 10344 %} | |
| 10345 | |
| 10346 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{ | |
| 10347 predicate(!UseXmmLoadAndClearUpper); | |
| 10348 match(Set dst (MoveL2D src)); | |
| 10349 effect(DEF dst, USE src); | |
| 10350 | |
| 10351 ins_cost(125); | |
| 10352 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %} | |
| 4759 | 10353 ins_encode %{ |
| 10354 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 10355 %} | |
| 0 | 10356 ins_pipe(pipe_slow); |
| 10357 %} | |
| 10358 | |
| 10359 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ | |
| 10360 predicate(UseXmmLoadAndClearUpper); | |
| 10361 match(Set dst (MoveL2D src)); | |
| 10362 effect(DEF dst, USE src); | |
| 10363 | |
| 10364 ins_cost(125); | |
| 10365 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %} | |
| 4759 | 10366 ins_encode %{ |
| 10367 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 10368 %} | |
| 0 | 10369 ins_pipe(pipe_slow); |
| 10370 %} | |
| 10371 | |
| 10372 | |
| 10373 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ | |
| 10374 match(Set dst (MoveF2I src)); | |
| 10375 effect(DEF dst, USE src); | |
| 10376 | |
| 10377 ins_cost(95); // XXX | |
| 10378 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %} | |
| 4759 | 10379 ins_encode %{ |
| 10380 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister); | |
| 10381 %} | |
| 0 | 10382 ins_pipe(pipe_slow); |
| 10383 %} | |
| 10384 | |
| 10385 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{ | |
| 10386 match(Set dst (MoveI2F src)); | |
| 10387 effect(DEF dst, USE src); | |
| 10388 | |
| 10389 ins_cost(100); | |
| 10390 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %} | |
| 4759 | 10391 ins_encode %{ |
| 10392 __ movl(Address(rsp, $dst$$disp), $src$$Register); | |
| 10393 %} | |
| 0 | 10394 ins_pipe( ialu_mem_reg ); |
| 10395 %} | |
| 10396 | |
| 10397 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ | |
| 10398 match(Set dst (MoveD2L src)); | |
| 10399 effect(DEF dst, USE src); | |
| 10400 | |
| 10401 ins_cost(95); // XXX | |
| 10402 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %} | |
| 4759 | 10403 ins_encode %{ |
| 10404 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister); | |
| 10405 %} | |
| 0 | 10406 ins_pipe(pipe_slow); |
| 10407 %} | |
| 10408 | |
| 10409 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{ | |
| 10410 match(Set dst (MoveL2D src)); | |
| 10411 effect(DEF dst, USE src); | |
| 10412 | |
| 10413 ins_cost(100); | |
| 10414 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %} | |
| 4759 | 10415 ins_encode %{ |
| 10416 __ movq(Address(rsp, $dst$$disp), $src$$Register); | |
| 10417 %} | |
| 0 | 10418 ins_pipe(ialu_mem_reg); |
| 10419 %} | |
| 10420 | |
| 10421 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{ | |
| 10422 match(Set dst (MoveF2I src)); | |
| 10423 effect(DEF dst, USE src); | |
| 10424 ins_cost(85); | |
| 10425 format %{ "movd $dst,$src\t# MoveF2I" %} | |
| 4759 | 10426 ins_encode %{ |
| 10427 __ movdl($dst$$Register, $src$$XMMRegister); | |
| 10428 %} | |
| 0 | 10429 ins_pipe( pipe_slow ); |
| 10430 %} | |
| 10431 | |
| 10432 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{ | |
| 10433 match(Set dst (MoveD2L src)); | |
| 10434 effect(DEF dst, USE src); | |
| 10435 ins_cost(85); | |
| 10436 format %{ "movd $dst,$src\t# MoveD2L" %} | |
| 4759 | 10437 ins_encode %{ |
| 10438 __ movdq($dst$$Register, $src$$XMMRegister); | |
| 10439 %} | |
| 0 | 10440 ins_pipe( pipe_slow ); |
| 10441 %} | |
| 10442 | |
| 10443 // The next instructions have long latency and use Int unit. Set high cost. | |
| 10444 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{ | |
| 10445 match(Set dst (MoveI2F src)); | |
| 10446 effect(DEF dst, USE src); | |
| 10447 ins_cost(300); | |
| 10448 format %{ "movd $dst,$src\t# MoveI2F" %} | |
| 4759 | 10449 ins_encode %{ |
| 10450 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 10451 %} | |
| 0 | 10452 ins_pipe( pipe_slow ); |
| 10453 %} | |
| 10454 | |
| 10455 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{ | |
| 10456 match(Set dst (MoveL2D src)); | |
| 10457 effect(DEF dst, USE src); | |
| 10458 ins_cost(300); | |
| 10459 format %{ "movd $dst,$src\t# MoveL2D" %} | |
| 4759 | 10460 ins_encode %{ |
| 10461 __ movdq($dst$$XMMRegister, $src$$Register); | |
| 10462 %} | |
| 0 | 10463 ins_pipe( pipe_slow ); |
| 10464 %} | |
| 10465 | |
| 10466 // Replicate scalar to packed byte (1 byte) values in xmm | |
| 10467 instruct Repl8B_reg(regD dst, regD src) %{ | |
| 10468 match(Set dst (Replicate8B src)); | |
| 10469 format %{ "MOVDQA $dst,$src\n\t" | |
| 10470 "PUNPCKLBW $dst,$dst\n\t" | |
| 10471 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %} | |
| 4759 | 10472 ins_encode %{ |
| 10473 if ($dst$$reg != $src$$reg) { | |
| 10474 __ movdqa($dst$$XMMRegister, $src$$XMMRegister); | |
| 10475 } | |
| 10476 __ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister); | |
| 10477 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); | |
| 10478 %} | |
| 0 | 10479 ins_pipe( pipe_slow ); |
| 10480 %} | |
| 10481 | |
| 10482 // Replicate scalar to packed byte (1 byte) values in xmm | |
| 10483 instruct Repl8B_rRegI(regD dst, rRegI src) %{ | |
| 10484 match(Set dst (Replicate8B src)); | |
| 10485 format %{ "MOVD $dst,$src\n\t" | |
| 10486 "PUNPCKLBW $dst,$dst\n\t" | |
| 10487 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %} | |
| 4759 | 10488 ins_encode %{ |
| 10489 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 10490 __ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister); | |
| 10491 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); | |
| 10492 %} | |
| 0 | 10493 ins_pipe( pipe_slow ); |
| 10494 %} | |
| 10495 | |
| 10496 // Replicate scalar zero to packed byte (1 byte) values in xmm | |
| 10497 instruct Repl8B_immI0(regD dst, immI0 zero) %{ | |
| 10498 match(Set dst (Replicate8B zero)); | |
| 10499 format %{ "PXOR $dst,$dst\t! replicate8B" %} | |
| 4759 | 10500 ins_encode %{ |
| 10501 __ pxor($dst$$XMMRegister, $dst$$XMMRegister); | |
| 10502 %} | |
| 0 | 10503 ins_pipe( fpu_reg_reg ); |
| 10504 %} | |
| 10505 | |
| 10506 // Replicate scalar to packed shore (2 byte) values in xmm | |
| 10507 instruct Repl4S_reg(regD dst, regD src) %{ | |
| 10508 match(Set dst (Replicate4S src)); | |
| 10509 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %} | |
| 4759 | 10510 ins_encode %{ |
| 10511 __ pshuflw($dst$$XMMRegister, $src$$XMMRegister, 0x00); | |
| 10512 %} | |
| 0 | 10513 ins_pipe( fpu_reg_reg ); |
| 10514 %} | |
| 10515 | |
| 10516 // Replicate scalar to packed shore (2 byte) values in xmm | |
| 10517 instruct Repl4S_rRegI(regD dst, rRegI src) %{ | |
| 10518 match(Set dst (Replicate4S src)); | |
| 10519 format %{ "MOVD $dst,$src\n\t" | |
| 10520 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %} | |
| 4759 | 10521 ins_encode %{ |
| 10522 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 10523 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); | |
| 10524 %} | |
| 0 | 10525 ins_pipe( fpu_reg_reg ); |
| 10526 %} | |
| 10527 | |
| 10528 // Replicate scalar zero to packed short (2 byte) values in xmm | |
| 10529 instruct Repl4S_immI0(regD dst, immI0 zero) %{ | |
| 10530 match(Set dst (Replicate4S zero)); | |
| 10531 format %{ "PXOR $dst,$dst\t! replicate4S" %} | |
| 4759 | 10532 ins_encode %{ |
| 10533 __ pxor($dst$$XMMRegister, $dst$$XMMRegister); | |
| 10534 %} | |
| 0 | 10535 ins_pipe( fpu_reg_reg ); |
| 10536 %} | |
| 10537 | |
| 10538 // Replicate scalar to packed char (2 byte) values in xmm | |
| 10539 instruct Repl4C_reg(regD dst, regD src) %{ | |
| 10540 match(Set dst (Replicate4C src)); | |
| 10541 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %} | |
| 4759 | 10542 ins_encode %{ |
| 10543 __ pshuflw($dst$$XMMRegister, $src$$XMMRegister, 0x00); | |
| 10544 %} | |
| 0 | 10545 ins_pipe( fpu_reg_reg ); |
| 10546 %} | |
| 10547 | |
| 10548 // Replicate scalar to packed char (2 byte) values in xmm | |
| 10549 instruct Repl4C_rRegI(regD dst, rRegI src) %{ | |
| 10550 match(Set dst (Replicate4C src)); | |
| 10551 format %{ "MOVD $dst,$src\n\t" | |
| 10552 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %} | |
| 4759 | 10553 ins_encode %{ |
| 10554 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 10555 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); | |
| 10556 %} | |
| 0 | 10557 ins_pipe( fpu_reg_reg ); |
| 10558 %} | |
| 10559 | |
| 10560 // Replicate scalar zero to packed char (2 byte) values in xmm | |
| 10561 instruct Repl4C_immI0(regD dst, immI0 zero) %{ | |
| 10562 match(Set dst (Replicate4C zero)); | |
| 10563 format %{ "PXOR $dst,$dst\t! replicate4C" %} | |
| 4759 | 10564 ins_encode %{ |
| 10565 __ pxor($dst$$XMMRegister, $dst$$XMMRegister); | |
| 10566 %} | |
| 0 | 10567 ins_pipe( fpu_reg_reg ); |
| 10568 %} | |
| 10569 | |
| 10570 // Replicate scalar to packed integer (4 byte) values in xmm | |
| 10571 instruct Repl2I_reg(regD dst, regD src) %{ | |
| 10572 match(Set dst (Replicate2I src)); | |
| 10573 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %} | |
| 4759 | 10574 ins_encode %{ |
| 10575 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0x00); | |
| 10576 %} | |
| 0 | 10577 ins_pipe( fpu_reg_reg ); |
| 10578 %} | |
| 10579 | |
| 10580 // Replicate scalar to packed integer (4 byte) values in xmm | |
| 10581 instruct Repl2I_rRegI(regD dst, rRegI src) %{ | |
| 10582 match(Set dst (Replicate2I src)); | |
| 10583 format %{ "MOVD $dst,$src\n\t" | |
| 10584 "PSHUFD $dst,$dst,0x00\t! replicate2I" %} | |
| 4759 | 10585 ins_encode %{ |
| 10586 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 10587 __ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00); | |
| 10588 %} | |
| 0 | 10589 ins_pipe( fpu_reg_reg ); |
| 10590 %} | |
| 10591 | |
| 10592 // Replicate scalar zero to packed integer (2 byte) values in xmm | |
| 10593 instruct Repl2I_immI0(regD dst, immI0 zero) %{ | |
| 10594 match(Set dst (Replicate2I zero)); | |
| 10595 format %{ "PXOR $dst,$dst\t! replicate2I" %} | |
| 4759 | 10596 ins_encode %{ |
| 10597 __ pxor($dst$$XMMRegister, $dst$$XMMRegister); | |
| 10598 %} | |
| 0 | 10599 ins_pipe( fpu_reg_reg ); |
| 10600 %} | |
| 10601 | |
| 10602 // Replicate scalar to packed single precision floating point values in xmm | |
| 10603 instruct Repl2F_reg(regD dst, regD src) %{ | |
| 10604 match(Set dst (Replicate2F src)); | |
| 10605 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %} | |
| 4759 | 10606 ins_encode %{ |
| 10607 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0xe0); | |
| 10608 %} | |
| 0 | 10609 ins_pipe( fpu_reg_reg ); |
| 10610 %} | |
| 10611 | |
| 10612 // Replicate scalar to packed single precision floating point values in xmm | |
| 10613 instruct Repl2F_regF(regD dst, regF src) %{ | |
| 10614 match(Set dst (Replicate2F src)); | |
| 10615 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %} | |
| 4759 | 10616 ins_encode %{ |
| 10617 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0xe0); | |
| 10618 %} | |
| 0 | 10619 ins_pipe( fpu_reg_reg ); |
| 10620 %} | |
| 10621 | |
| 10622 // Replicate scalar to packed single precision floating point values in xmm | |
| 10623 instruct Repl2F_immF0(regD dst, immF0 zero) %{ | |
| 10624 match(Set dst (Replicate2F zero)); | |
| 10625 format %{ "PXOR $dst,$dst\t! replicate2F" %} | |
| 4759 | 10626 ins_encode %{ |
| 10627 __ pxor($dst$$XMMRegister, $dst$$XMMRegister); | |
| 10628 %} | |
| 0 | 10629 ins_pipe( fpu_reg_reg ); |
| 10630 %} | |
| 10631 | |
| 10632 | |
| 10633 // ======================================================================= | |
| 10634 // fast clearing of an array | |
| 10635 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy, | |
| 10636 rFlagsReg cr) | |
| 10637 %{ | |
| 10638 match(Set dummy (ClearArray cnt base)); | |
| 10639 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr); | |
| 10640 | |
| 10641 format %{ "xorl rax, rax\t# ClearArray:\n\t" | |
| 10642 "rep stosq\t# Store rax to *rdi++ while rcx--" %} | |
| 10643 ins_encode(opc_reg_reg(0x33, RAX, RAX), // xorl %eax, %eax | |
| 10644 Opcode(0xF3), Opcode(0x48), Opcode(0xAB)); // rep REX_W stos | |
| 10645 ins_pipe(pipe_slow); | |
| 10646 %} | |
| 10647 | |
| 2262 | 10648 instruct string_compare(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2, |
| 10649 rax_RegI result, regD tmp1, rFlagsReg cr) | |
|
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10650 %{ |
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10651 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); |
| 2262 | 10652 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr); |
| 10653 | |
| 10654 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %} | |
|
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10655 ins_encode %{ |
|
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10656 __ string_compare($str1$$Register, $str2$$Register, |
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diff
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|
10657 $cnt1$$Register, $cnt2$$Register, $result$$Register, |
| 2262 | 10658 $tmp1$$XMMRegister); |
|
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|
10659 %} |
| 681 | 10660 ins_pipe( pipe_slow ); |
| 10661 %} | |
| 10662 | |
|
2320
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|
10663 // fast search of substring with known size. |
|
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|
10664 instruct string_indexof_con(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2, |
|
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|
10665 rbx_RegI result, regD vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr) |
|
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|
10666 %{ |
|
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|
10667 predicate(UseSSE42Intrinsics); |
|
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|
10668 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2))); |
|
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|
10669 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr); |
|
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|
10670 |
|
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|
10671 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %} |
|
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|
10672 ins_encode %{ |
|
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|
10673 int icnt2 = (int)$int_cnt2$$constant; |
|
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|
10674 if (icnt2 >= 8) { |
|
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|
10675 // IndexOf for constant substrings with size >= 8 elements |
|
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|
10676 // which don't need to be loaded through stack. |
|
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|
10677 __ string_indexofC8($str1$$Register, $str2$$Register, |
|
41d4973cf100
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|
10678 $cnt1$$Register, $cnt2$$Register, |
|
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|
10679 icnt2, $result$$Register, |
|
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|
10680 $vec$$XMMRegister, $tmp$$Register); |
|
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|
10681 } else { |
|
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|
10682 // Small strings are loaded through stack if they cross page boundary. |
|
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|
10683 __ string_indexof($str1$$Register, $str2$$Register, |
|
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|
10684 $cnt1$$Register, $cnt2$$Register, |
|
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|
10685 icnt2, $result$$Register, |
|
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|
10686 $vec$$XMMRegister, $tmp$$Register); |
|
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|
10687 } |
|
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|
10688 %} |
|
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|
10689 ins_pipe( pipe_slow ); |
|
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|
10690 %} |
|
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|
10691 |
|
986
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|
10692 instruct string_indexof(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2, |
|
2320
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|
10693 rbx_RegI result, regD vec, rcx_RegI tmp, rFlagsReg cr) |
| 681 | 10694 %{ |
| 10695 predicate(UseSSE42Intrinsics); | |
|
986
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|
10696 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2))); |
|
2320
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|
10697 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr); |
|
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|
10698 |
|
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|
10699 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %} |
|
986
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|
10700 ins_encode %{ |
|
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|
10701 __ string_indexof($str1$$Register, $str2$$Register, |
|
2320
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|
10702 $cnt1$$Register, $cnt2$$Register, |
|
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|
10703 (-1), $result$$Register, |
|
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|
10704 $vec$$XMMRegister, $tmp$$Register); |
|
986
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|
10705 %} |
| 681 | 10706 ins_pipe( pipe_slow ); |
| 10707 %} | |
| 10708 | |
| 10709 // fast string equals | |
|
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|
10710 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result, |
|
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|
10711 regD tmp1, regD tmp2, rbx_RegI tmp3, rFlagsReg cr) |
|
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|
10712 %{ |
|
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|
10713 match(Set result (StrEquals (Binary str1 str2) cnt)); |
|
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|
10714 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr); |
|
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|
10715 |
|
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|
10716 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %} |
|
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|
10717 ins_encode %{ |
|
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|
10718 __ char_arrays_equals(false, $str1$$Register, $str2$$Register, |
|
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changeset
|
10719 $cnt$$Register, $result$$Register, $tmp3$$Register, |
|
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|
10720 $tmp1$$XMMRegister, $tmp2$$XMMRegister); |
|
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|
10721 %} |
| 0 | 10722 ins_pipe( pipe_slow ); |
| 10723 %} | |
| 10724 | |
|
169
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changeset
|
10725 // fast array equals |
|
986
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|
10726 instruct array_equals(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result, |
|
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|
10727 regD tmp1, regD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr) |
| 681 | 10728 %{ |
|
169
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diff
changeset
|
10729 match(Set result (AryEq ary1 ary2)); |
| 681 | 10730 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr); |
|
169
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diff
changeset
|
10731 //ins_cost(300); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
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168
diff
changeset
|
10732 |
|
986
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changeset
|
10733 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %} |
|
62001a362ce9
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diff
changeset
|
10734 ins_encode %{ |
|
62001a362ce9
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changeset
|
10735 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register, |
|
62001a362ce9
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changeset
|
10736 $tmp3$$Register, $result$$Register, $tmp4$$Register, |
|
62001a362ce9
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changeset
|
10737 $tmp1$$XMMRegister, $tmp2$$XMMRegister); |
|
62001a362ce9
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824
diff
changeset
|
10738 %} |
|
169
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parents:
168
diff
changeset
|
10739 ins_pipe( pipe_slow ); |
|
9148c65abefc
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168
diff
changeset
|
10740 %} |
|
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|
10741 |
| 0 | 10742 //----------Control Flow Instructions------------------------------------------ |
| 10743 // Signed compare Instructions | |
| 10744 | |
| 10745 // XXX more variants!! | |
| 10746 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2) | |
| 10747 %{ | |
| 10748 match(Set cr (CmpI op1 op2)); | |
| 10749 effect(DEF cr, USE op1, USE op2); | |
| 10750 | |
| 10751 format %{ "cmpl $op1, $op2" %} | |
| 10752 opcode(0x3B); /* Opcode 3B /r */ | |
| 10753 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2)); | |
| 10754 ins_pipe(ialu_cr_reg_reg); | |
| 10755 %} | |
| 10756 | |
| 10757 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2) | |
| 10758 %{ | |
| 10759 match(Set cr (CmpI op1 op2)); | |
| 10760 | |
| 10761 format %{ "cmpl $op1, $op2" %} | |
| 10762 opcode(0x81, 0x07); /* Opcode 81 /7 */ | |
| 10763 ins_encode(OpcSErm(op1, op2), Con8or32(op2)); | |
| 10764 ins_pipe(ialu_cr_reg_imm); | |
| 10765 %} | |
| 10766 | |
| 10767 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2) | |
| 10768 %{ | |
| 10769 match(Set cr (CmpI op1 (LoadI op2))); | |
| 10770 | |
| 10771 ins_cost(500); // XXX | |
| 10772 format %{ "cmpl $op1, $op2" %} | |
| 10773 opcode(0x3B); /* Opcode 3B /r */ | |
| 10774 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 10775 ins_pipe(ialu_cr_reg_mem); | |
| 10776 %} | |
| 10777 | |
| 10778 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero) | |
| 10779 %{ | |
| 10780 match(Set cr (CmpI src zero)); | |
| 10781 | |
| 10782 format %{ "testl $src, $src" %} | |
| 10783 opcode(0x85); | |
| 10784 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src)); | |
| 10785 ins_pipe(ialu_cr_reg_imm); | |
| 10786 %} | |
| 10787 | |
| 10788 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero) | |
| 10789 %{ | |
| 10790 match(Set cr (CmpI (AndI src con) zero)); | |
| 10791 | |
| 10792 format %{ "testl $src, $con" %} | |
| 10793 opcode(0xF7, 0x00); | |
| 10794 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con)); | |
| 10795 ins_pipe(ialu_cr_reg_imm); | |
| 10796 %} | |
| 10797 | |
| 10798 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero) | |
| 10799 %{ | |
| 10800 match(Set cr (CmpI (AndI src (LoadI mem)) zero)); | |
| 10801 | |
| 10802 format %{ "testl $src, $mem" %} | |
| 10803 opcode(0x85); | |
| 10804 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
| 10805 ins_pipe(ialu_cr_reg_mem); | |
| 10806 %} | |
| 10807 | |
| 10808 // Unsigned compare Instructions; really, same as signed except they | |
| 10809 // produce an rFlagsRegU instead of rFlagsReg. | |
| 10810 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2) | |
| 10811 %{ | |
| 10812 match(Set cr (CmpU op1 op2)); | |
| 10813 | |
| 10814 format %{ "cmpl $op1, $op2\t# unsigned" %} | |
| 10815 opcode(0x3B); /* Opcode 3B /r */ | |
| 10816 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2)); | |
| 10817 ins_pipe(ialu_cr_reg_reg); | |
| 10818 %} | |
| 10819 | |
| 10820 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2) | |
| 10821 %{ | |
| 10822 match(Set cr (CmpU op1 op2)); | |
| 10823 | |
| 10824 format %{ "cmpl $op1, $op2\t# unsigned" %} | |
| 10825 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 10826 ins_encode(OpcSErm(op1, op2), Con8or32(op2)); | |
| 10827 ins_pipe(ialu_cr_reg_imm); | |
| 10828 %} | |
| 10829 | |
| 10830 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2) | |
| 10831 %{ | |
| 10832 match(Set cr (CmpU op1 (LoadI op2))); | |
| 10833 | |
| 10834 ins_cost(500); // XXX | |
| 10835 format %{ "cmpl $op1, $op2\t# unsigned" %} | |
| 10836 opcode(0x3B); /* Opcode 3B /r */ | |
| 10837 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 10838 ins_pipe(ialu_cr_reg_mem); | |
| 10839 %} | |
| 10840 | |
| 10841 // // // Cisc-spilled version of cmpU_rReg | |
| 10842 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2) | |
| 10843 // //%{ | |
| 10844 // // match(Set cr (CmpU (LoadI op1) op2)); | |
| 10845 // // | |
| 10846 // // format %{ "CMPu $op1,$op2" %} | |
| 10847 // // ins_cost(500); | |
| 10848 // // opcode(0x39); /* Opcode 39 /r */ | |
| 10849 // // ins_encode( OpcP, reg_mem( op1, op2) ); | |
| 10850 // //%} | |
| 10851 | |
| 10852 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero) | |
| 10853 %{ | |
| 10854 match(Set cr (CmpU src zero)); | |
| 10855 | |
| 10856 format %{ "testl $src, $src\t# unsigned" %} | |
| 10857 opcode(0x85); | |
| 10858 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src)); | |
| 10859 ins_pipe(ialu_cr_reg_imm); | |
| 10860 %} | |
| 10861 | |
| 10862 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2) | |
| 10863 %{ | |
| 10864 match(Set cr (CmpP op1 op2)); | |
| 10865 | |
| 10866 format %{ "cmpq $op1, $op2\t# ptr" %} | |
| 10867 opcode(0x3B); /* Opcode 3B /r */ | |
| 10868 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2)); | |
| 10869 ins_pipe(ialu_cr_reg_reg); | |
| 10870 %} | |
| 10871 | |
| 10872 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2) | |
| 10873 %{ | |
| 10874 match(Set cr (CmpP op1 (LoadP op2))); | |
| 10875 | |
| 10876 ins_cost(500); // XXX | |
| 10877 format %{ "cmpq $op1, $op2\t# ptr" %} | |
| 10878 opcode(0x3B); /* Opcode 3B /r */ | |
| 10879 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 10880 ins_pipe(ialu_cr_reg_mem); | |
| 10881 %} | |
| 10882 | |
| 10883 // // // Cisc-spilled version of cmpP_rReg | |
| 10884 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2) | |
| 10885 // //%{ | |
| 10886 // // match(Set cr (CmpP (LoadP op1) op2)); | |
| 10887 // // | |
| 10888 // // format %{ "CMPu $op1,$op2" %} | |
| 10889 // // ins_cost(500); | |
| 10890 // // opcode(0x39); /* Opcode 39 /r */ | |
| 10891 // // ins_encode( OpcP, reg_mem( op1, op2) ); | |
| 10892 // //%} | |
| 10893 | |
| 10894 // XXX this is generalized by compP_rReg_mem??? | |
| 10895 // Compare raw pointer (used in out-of-heap check). | |
| 10896 // Only works because non-oop pointers must be raw pointers | |
| 10897 // and raw pointers have no anti-dependencies. | |
| 10898 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2) | |
| 10899 %{ | |
| 10900 predicate(!n->in(2)->in(2)->bottom_type()->isa_oop_ptr()); | |
| 10901 match(Set cr (CmpP op1 (LoadP op2))); | |
| 10902 | |
| 10903 format %{ "cmpq $op1, $op2\t# raw ptr" %} | |
| 10904 opcode(0x3B); /* Opcode 3B /r */ | |
| 10905 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 10906 ins_pipe(ialu_cr_reg_mem); | |
| 10907 %} | |
| 10908 | |
| 10909 // This will generate a signed flags result. This should be OK since | |
| 10910 // any compare to a zero should be eq/neq. | |
| 10911 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero) | |
| 10912 %{ | |
| 10913 match(Set cr (CmpP src zero)); | |
| 10914 | |
| 10915 format %{ "testq $src, $src\t# ptr" %} | |
| 10916 opcode(0x85); | |
| 10917 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src)); | |
| 10918 ins_pipe(ialu_cr_reg_imm); | |
| 10919 %} | |
| 10920 | |
| 10921 // This will generate a signed flags result. This should be OK since | |
| 10922 // any compare to a zero should be eq/neq. | |
|
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10923 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero) |
|
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|
10924 %{ |
|
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|
10925 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL)); |
| 0 | 10926 match(Set cr (CmpP (LoadP op) zero)); |
| 10927 | |
| 10928 ins_cost(500); // XXX | |
| 10929 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %} | |
| 10930 opcode(0xF7); /* Opcode F7 /0 */ | |
| 10931 ins_encode(REX_mem_wide(op), | |
| 10932 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF)); | |
| 10933 ins_pipe(ialu_cr_reg_imm); | |
| 10934 %} | |
| 10935 | |
|
642
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10936 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero) |
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10937 %{ |
|
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|
10938 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
|
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10939 match(Set cr (CmpP (LoadP mem) zero)); |
|
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|
10940 |
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10941 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %} |
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10942 ins_encode %{ |
|
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|
10943 __ cmpq(r12, $mem$$Address); |
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|
10944 %} |
|
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|
10945 ins_pipe(ialu_cr_reg_mem); |
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10946 %} |
|
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10947 |
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10948 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2) |
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10949 %{ |
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10950 match(Set cr (CmpN op1 op2)); |
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10951 |
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10952 format %{ "cmpl $op1, $op2\t# compressed ptr" %} |
|
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10953 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %} |
|
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10954 ins_pipe(ialu_cr_reg_reg); |
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10955 %} |
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|
10956 |
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10957 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem) |
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10958 %{ |
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10959 match(Set cr (CmpN src (LoadN mem))); |
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10960 |
|
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10961 format %{ "cmpl $src, $mem\t# compressed ptr" %} |
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10962 ins_encode %{ |
|
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|
10963 __ cmpl($src$$Register, $mem$$Address); |
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|
10964 %} |
|
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|
10965 ins_pipe(ialu_cr_reg_mem); |
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|
10966 %} |
|
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|
10967 |
|
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|
10968 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{ |
|
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10969 match(Set cr (CmpN op1 op2)); |
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|
10970 |
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|
10971 format %{ "cmpl $op1, $op2\t# compressed ptr" %} |
|
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10972 ins_encode %{ |
|
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10973 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant); |
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10974 %} |
|
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|
10975 ins_pipe(ialu_cr_reg_imm); |
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|
10976 %} |
|
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|
10977 |
|
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|
10978 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src) |
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|
10979 %{ |
|
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|
10980 match(Set cr (CmpN src (LoadN mem))); |
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|
10981 |
|
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|
10982 format %{ "cmpl $mem, $src\t# compressed ptr" %} |
|
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10983 ins_encode %{ |
|
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|
10984 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant); |
|
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10985 %} |
|
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10986 ins_pipe(ialu_cr_reg_mem); |
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10987 %} |
|
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|
10988 |
|
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|
10989 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{ |
|
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10990 match(Set cr (CmpN src zero)); |
|
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|
10991 |
|
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10992 format %{ "testl $src, $src\t# compressed ptr" %} |
|
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10993 ins_encode %{ __ testl($src$$Register, $src$$Register); %} |
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10994 ins_pipe(ialu_cr_reg_imm); |
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10995 %} |
|
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|
10996 |
|
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10997 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero) |
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10998 %{ |
|
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10999 predicate(Universe::narrow_oop_base() != NULL); |
|
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11000 match(Set cr (CmpN (LoadN mem) zero)); |
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11001 |
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11002 ins_cost(500); // XXX |
|
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11003 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %} |
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11004 ins_encode %{ |
|
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11005 __ cmpl($mem$$Address, (int)0xFFFFFFFF); |
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11006 %} |
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11007 ins_pipe(ialu_cr_reg_mem); |
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11008 %} |
|
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11009 |
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11010 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero) |
|
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11011 %{ |
|
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11012 predicate(Universe::narrow_oop_base() == NULL); |
|
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11013 match(Set cr (CmpN (LoadN mem) zero)); |
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11014 |
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11015 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %} |
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11016 ins_encode %{ |
|
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11017 __ cmpl(r12, $mem$$Address); |
|
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11018 %} |
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11019 ins_pipe(ialu_cr_reg_mem); |
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11020 %} |
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11021 |
| 0 | 11022 // Yanked all unsigned pointer compare operations. |
| 11023 // Pointer compares are done with CmpP which is already unsigned. | |
| 11024 | |
| 11025 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2) | |
| 11026 %{ | |
| 11027 match(Set cr (CmpL op1 op2)); | |
| 11028 | |
| 11029 format %{ "cmpq $op1, $op2" %} | |
| 11030 opcode(0x3B); /* Opcode 3B /r */ | |
| 11031 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2)); | |
| 11032 ins_pipe(ialu_cr_reg_reg); | |
| 11033 %} | |
| 11034 | |
| 11035 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2) | |
| 11036 %{ | |
| 11037 match(Set cr (CmpL op1 op2)); | |
| 11038 | |
| 11039 format %{ "cmpq $op1, $op2" %} | |
| 11040 opcode(0x81, 0x07); /* Opcode 81 /7 */ | |
| 11041 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2)); | |
| 11042 ins_pipe(ialu_cr_reg_imm); | |
| 11043 %} | |
| 11044 | |
| 11045 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2) | |
| 11046 %{ | |
| 11047 match(Set cr (CmpL op1 (LoadL op2))); | |
| 11048 | |
| 11049 format %{ "cmpq $op1, $op2" %} | |
| 11050 opcode(0x3B); /* Opcode 3B /r */ | |
| 11051 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 11052 ins_pipe(ialu_cr_reg_mem); | |
| 11053 %} | |
| 11054 | |
| 11055 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero) | |
| 11056 %{ | |
| 11057 match(Set cr (CmpL src zero)); | |
| 11058 | |
| 11059 format %{ "testq $src, $src" %} | |
| 11060 opcode(0x85); | |
| 11061 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src)); | |
| 11062 ins_pipe(ialu_cr_reg_imm); | |
| 11063 %} | |
| 11064 | |
| 11065 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero) | |
| 11066 %{ | |
| 11067 match(Set cr (CmpL (AndL src con) zero)); | |
| 11068 | |
| 11069 format %{ "testq $src, $con\t# long" %} | |
| 11070 opcode(0xF7, 0x00); | |
| 11071 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con)); | |
| 11072 ins_pipe(ialu_cr_reg_imm); | |
| 11073 %} | |
| 11074 | |
| 11075 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero) | |
| 11076 %{ | |
| 11077 match(Set cr (CmpL (AndL src (LoadL mem)) zero)); | |
| 11078 | |
| 11079 format %{ "testq $src, $mem" %} | |
| 11080 opcode(0x85); | |
| 11081 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem)); | |
| 11082 ins_pipe(ialu_cr_reg_mem); | |
| 11083 %} | |
| 11084 | |
| 11085 // Manifest a CmpL result in an integer register. Very painful. | |
| 11086 // This is the test to avoid. | |
| 11087 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags) | |
| 11088 %{ | |
| 11089 match(Set dst (CmpL3 src1 src2)); | |
| 11090 effect(KILL flags); | |
| 11091 | |
| 11092 ins_cost(275); // XXX | |
| 11093 format %{ "cmpq $src1, $src2\t# CmpL3\n\t" | |
| 11094 "movl $dst, -1\n\t" | |
| 11095 "jl,s done\n\t" | |
| 11096 "setne $dst\n\t" | |
| 11097 "movzbl $dst, $dst\n\t" | |
| 11098 "done:" %} | |
| 11099 ins_encode(cmpl3_flag(src1, src2, dst)); | |
| 11100 ins_pipe(pipe_slow); | |
| 11101 %} | |
| 11102 | |
| 11103 //----------Max and Min-------------------------------------------------------- | |
| 11104 // Min Instructions | |
| 11105 | |
| 11106 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr) | |
| 11107 %{ | |
| 11108 effect(USE_DEF dst, USE src, USE cr); | |
| 11109 | |
| 11110 format %{ "cmovlgt $dst, $src\t# min" %} | |
| 11111 opcode(0x0F, 0x4F); | |
| 11112 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 11113 ins_pipe(pipe_cmov_reg); | |
| 11114 %} | |
| 11115 | |
| 11116 | |
| 11117 instruct minI_rReg(rRegI dst, rRegI src) | |
| 11118 %{ | |
| 11119 match(Set dst (MinI dst src)); | |
| 11120 | |
| 11121 ins_cost(200); | |
| 11122 expand %{ | |
| 11123 rFlagsReg cr; | |
| 11124 compI_rReg(cr, dst, src); | |
| 11125 cmovI_reg_g(dst, src, cr); | |
| 11126 %} | |
| 11127 %} | |
| 11128 | |
| 11129 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr) | |
| 11130 %{ | |
| 11131 effect(USE_DEF dst, USE src, USE cr); | |
| 11132 | |
| 11133 format %{ "cmovllt $dst, $src\t# max" %} | |
| 11134 opcode(0x0F, 0x4C); | |
| 11135 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 11136 ins_pipe(pipe_cmov_reg); | |
| 11137 %} | |
| 11138 | |
| 11139 | |
| 11140 instruct maxI_rReg(rRegI dst, rRegI src) | |
| 11141 %{ | |
| 11142 match(Set dst (MaxI dst src)); | |
| 11143 | |
| 11144 ins_cost(200); | |
| 11145 expand %{ | |
| 11146 rFlagsReg cr; | |
| 11147 compI_rReg(cr, dst, src); | |
| 11148 cmovI_reg_l(dst, src, cr); | |
| 11149 %} | |
| 11150 %} | |
| 11151 | |
| 11152 // ============================================================================ | |
| 11153 // Branch Instructions | |
| 11154 | |
| 11155 // Jump Direct - Label defines a relative address from JMP+1 | |
| 11156 instruct jmpDir(label labl) | |
| 11157 %{ | |
| 11158 match(Goto); | |
| 11159 effect(USE labl); | |
| 11160 | |
| 11161 ins_cost(300); | |
| 11162 format %{ "jmp $labl" %} | |
| 11163 size(5); | |
| 3851 | 11164 ins_encode %{ |
| 11165 Label* L = $labl$$label; | |
| 11166 __ jmp(*L, false); // Always long jump | |
| 11167 %} | |
| 0 | 11168 ins_pipe(pipe_jmp); |
| 11169 %} | |
| 11170 | |
| 11171 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 11172 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl) | |
| 11173 %{ | |
| 11174 match(If cop cr); | |
| 11175 effect(USE labl); | |
| 11176 | |
| 11177 ins_cost(300); | |
| 11178 format %{ "j$cop $labl" %} | |
| 11179 size(6); | |
| 3851 | 11180 ins_encode %{ |
| 11181 Label* L = $labl$$label; | |
| 11182 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 11183 %} | |
| 0 | 11184 ins_pipe(pipe_jcc); |
| 11185 %} | |
| 11186 | |
| 11187 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 11188 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl) | |
| 11189 %{ | |
| 11190 match(CountedLoopEnd cop cr); | |
| 11191 effect(USE labl); | |
| 11192 | |
| 11193 ins_cost(300); | |
| 11194 format %{ "j$cop $labl\t# loop end" %} | |
| 11195 size(6); | |
| 3851 | 11196 ins_encode %{ |
| 11197 Label* L = $labl$$label; | |
| 11198 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 11199 %} | |
| 0 | 11200 ins_pipe(pipe_jcc); |
| 11201 %} | |
| 11202 | |
| 11203 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
|
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11204 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
| 0 | 11205 match(CountedLoopEnd cop cmp); |
| 11206 effect(USE labl); | |
| 11207 | |
| 11208 ins_cost(300); | |
| 11209 format %{ "j$cop,u $labl\t# loop end" %} | |
| 11210 size(6); | |
| 3851 | 11211 ins_encode %{ |
| 11212 Label* L = $labl$$label; | |
| 11213 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 11214 %} | |
| 0 | 11215 ins_pipe(pipe_jcc); |
| 11216 %} | |
| 11217 | |
|
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11218 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
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11219 match(CountedLoopEnd cop cmp); |
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11220 effect(USE labl); |
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11221 |
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11222 ins_cost(200); |
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11223 format %{ "j$cop,u $labl\t# loop end" %} |
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11224 size(6); |
| 3851 | 11225 ins_encode %{ |
| 11226 Label* L = $labl$$label; | |
| 11227 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 11228 %} | |
|
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11229 ins_pipe(pipe_jcc); |
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11230 %} |
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11231 |
| 0 | 11232 // Jump Direct Conditional - using unsigned comparison |
|
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11233 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
| 0 | 11234 match(If cop cmp); |
| 11235 effect(USE labl); | |
| 11236 | |
| 11237 ins_cost(300); | |
|
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11238 format %{ "j$cop,u $labl" %} |
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11239 size(6); |
| 3851 | 11240 ins_encode %{ |
| 11241 Label* L = $labl$$label; | |
| 11242 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 11243 %} | |
|
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11244 ins_pipe(pipe_jcc); |
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11245 %} |
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11246 |
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11247 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
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11248 match(If cop cmp); |
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11249 effect(USE labl); |
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11250 |
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11251 ins_cost(200); |
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11252 format %{ "j$cop,u $labl" %} |
| 0 | 11253 size(6); |
| 3851 | 11254 ins_encode %{ |
| 11255 Label* L = $labl$$label; | |
| 11256 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 11257 %} | |
| 0 | 11258 ins_pipe(pipe_jcc); |
| 11259 %} | |
| 11260 | |
|
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11261 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{ |
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11262 match(If cop cmp); |
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11263 effect(USE labl); |
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11264 |
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11265 ins_cost(200); |
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|
11266 format %{ $$template |
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11267 if ($cop$$cmpcode == Assembler::notEqual) { |
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11268 $$emit$$"jp,u $labl\n\t" |
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11269 $$emit$$"j$cop,u $labl" |
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11270 } else { |
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11271 $$emit$$"jp,u done\n\t" |
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11272 $$emit$$"j$cop,u $labl\n\t" |
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11273 $$emit$$"done:" |
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11274 } |
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11275 %} |
|
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11276 ins_encode %{ |
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11277 Label* l = $labl$$label; |
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11278 if ($cop$$cmpcode == Assembler::notEqual) { |
| 3851 | 11279 __ jcc(Assembler::parity, *l, false); |
| 11280 __ jcc(Assembler::notEqual, *l, false); | |
|
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11281 } else if ($cop$$cmpcode == Assembler::equal) { |
| 3851 | 11282 Label done; |
| 11283 __ jccb(Assembler::parity, done); | |
| 11284 __ jcc(Assembler::equal, *l, false); | |
| 11285 __ bind(done); | |
|
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11286 } else { |
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|
11287 ShouldNotReachHere(); |
|
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11288 } |
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|
11289 %} |
|
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|
11290 ins_pipe(pipe_jcc); |
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11291 %} |
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11292 |
| 0 | 11293 // ============================================================================ |
| 11294 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary | |
| 11295 // superklass array for an instance of the superklass. Set a hidden | |
| 11296 // internal cache on a hit (cache is checked with exposed code in | |
| 11297 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The | |
| 11298 // encoding ALSO sets flags. | |
| 11299 | |
| 11300 instruct partialSubtypeCheck(rdi_RegP result, | |
| 11301 rsi_RegP sub, rax_RegP super, rcx_RegI rcx, | |
| 11302 rFlagsReg cr) | |
| 11303 %{ | |
| 11304 match(Set result (PartialSubtypeCheck sub super)); | |
| 11305 effect(KILL rcx, KILL cr); | |
| 11306 | |
| 11307 ins_cost(1100); // slightly larger than the next version | |
|
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11308 format %{ "movq rdi, [$sub + (sizeof(oopDesc) + Klass::secondary_supers_offset_in_bytes())]\n\t" |
| 0 | 11309 "movl rcx, [rdi + arrayOopDesc::length_offset_in_bytes()]\t# length to scan\n\t" |
| 11310 "addq rdi, arrayOopDex::base_offset_in_bytes(T_OBJECT)\t# Skip to start of data; set NZ in case count is zero\n\t" | |
| 11311 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t" | |
| 11312 "jne,s miss\t\t# Missed: rdi not-zero\n\t" | |
| 11313 "movq [$sub + (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes())], $super\t# Hit: update cache\n\t" | |
| 11314 "xorq $result, $result\t\t Hit: rdi zero\n\t" | |
| 11315 "miss:\t" %} | |
| 11316 | |
| 11317 opcode(0x1); // Force a XOR of RDI | |
| 11318 ins_encode(enc_PartialSubtypeCheck()); | |
| 11319 ins_pipe(pipe_slow); | |
| 11320 %} | |
| 11321 | |
| 11322 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr, | |
| 11323 rsi_RegP sub, rax_RegP super, rcx_RegI rcx, | |
| 11324 immP0 zero, | |
| 11325 rdi_RegP result) | |
| 11326 %{ | |
| 11327 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero)); | |
| 11328 effect(KILL rcx, KILL result); | |
| 11329 | |
| 11330 ins_cost(1000); | |
|
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11331 format %{ "movq rdi, [$sub + (sizeof(oopDesc) + Klass::secondary_supers_offset_in_bytes())]\n\t" |
| 0 | 11332 "movl rcx, [rdi + arrayOopDesc::length_offset_in_bytes()]\t# length to scan\n\t" |
| 11333 "addq rdi, arrayOopDex::base_offset_in_bytes(T_OBJECT)\t# Skip to start of data; set NZ in case count is zero\n\t" | |
| 11334 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t" | |
| 11335 "jne,s miss\t\t# Missed: flags nz\n\t" | |
| 11336 "movq [$sub + (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes())], $super\t# Hit: update cache\n\t" | |
| 11337 "miss:\t" %} | |
| 11338 | |
| 11339 opcode(0x0); // No need to XOR RDI | |
| 11340 ins_encode(enc_PartialSubtypeCheck()); | |
| 11341 ins_pipe(pipe_slow); | |
| 11342 %} | |
| 11343 | |
| 11344 // ============================================================================ | |
| 11345 // Branch Instructions -- short offset versions | |
| 11346 // | |
| 11347 // These instructions are used to replace jumps of a long offset (the default | |
| 11348 // match) with jumps of a shorter offset. These instructions are all tagged | |
| 11349 // with the ins_short_branch attribute, which causes the ADLC to suppress the | |
| 11350 // match rules in general matching. Instead, the ADLC generates a conversion | |
| 11351 // method in the MachNode which can be used to do in-place replacement of the | |
| 11352 // long variant with the shorter variant. The compiler will determine if a | |
| 11353 // branch can be taken by the is_short_branch_offset() predicate in the machine | |
| 11354 // specific code section of the file. | |
| 11355 | |
| 11356 // Jump Direct - Label defines a relative address from JMP+1 | |
|
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11357 instruct jmpDir_short(label labl) %{ |
| 0 | 11358 match(Goto); |
| 11359 effect(USE labl); | |
| 11360 | |
| 11361 ins_cost(300); | |
| 11362 format %{ "jmp,s $labl" %} | |
| 11363 size(2); | |
| 3851 | 11364 ins_encode %{ |
| 11365 Label* L = $labl$$label; | |
| 11366 __ jmpb(*L); | |
| 11367 %} | |
| 0 | 11368 ins_pipe(pipe_jmp); |
| 11369 ins_short_branch(1); | |
| 11370 %} | |
| 11371 | |
| 11372 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
|
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11373 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{ |
| 0 | 11374 match(If cop cr); |
| 11375 effect(USE labl); | |
| 11376 | |
| 11377 ins_cost(300); | |
| 11378 format %{ "j$cop,s $labl" %} | |
| 11379 size(2); | |
| 3851 | 11380 ins_encode %{ |
| 11381 Label* L = $labl$$label; | |
| 11382 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11383 %} | |
| 0 | 11384 ins_pipe(pipe_jcc); |
| 11385 ins_short_branch(1); | |
| 11386 %} | |
| 11387 | |
| 11388 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
|
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11389 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{ |
| 0 | 11390 match(CountedLoopEnd cop cr); |
| 11391 effect(USE labl); | |
| 11392 | |
| 11393 ins_cost(300); | |
|
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|
11394 format %{ "j$cop,s $labl\t# loop end" %} |
| 0 | 11395 size(2); |
| 3851 | 11396 ins_encode %{ |
| 11397 Label* L = $labl$$label; | |
| 11398 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11399 %} | |
| 0 | 11400 ins_pipe(pipe_jcc); |
| 11401 ins_short_branch(1); | |
| 11402 %} | |
| 11403 | |
| 11404 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
|
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11405 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
|
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|
11406 match(CountedLoopEnd cop cmp); |
|
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changeset
|
11407 effect(USE labl); |
|
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diff
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|
11408 |
|
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diff
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|
11409 ins_cost(300); |
|
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diff
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|
11410 format %{ "j$cop,us $labl\t# loop end" %} |
|
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|
11411 size(2); |
| 3851 | 11412 ins_encode %{ |
| 11413 Label* L = $labl$$label; | |
| 11414 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11415 %} | |
|
415
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|
11416 ins_pipe(pipe_jcc); |
|
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diff
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|
11417 ins_short_branch(1); |
|
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diff
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|
11418 %} |
|
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never
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403
diff
changeset
|
11419 |
|
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never
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diff
changeset
|
11420 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
| 0 | 11421 match(CountedLoopEnd cop cmp); |
| 11422 effect(USE labl); | |
| 11423 | |
| 11424 ins_cost(300); | |
|
415
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|
11425 format %{ "j$cop,us $labl\t# loop end" %} |
|
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|
11426 size(2); |
| 3851 | 11427 ins_encode %{ |
| 11428 Label* L = $labl$$label; | |
| 11429 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11430 %} | |
|
415
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diff
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|
11431 ins_pipe(pipe_jcc); |
|
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diff
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|
11432 ins_short_branch(1); |
|
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403
diff
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|
11433 %} |
|
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diff
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|
11434 |
|
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never
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403
diff
changeset
|
11435 // Jump Direct Conditional - using unsigned comparison |
|
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|
11436 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
|
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|
11437 match(If cop cmp); |
|
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diff
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|
11438 effect(USE labl); |
|
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diff
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|
11439 |
|
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|
11440 ins_cost(300); |
| 0 | 11441 format %{ "j$cop,us $labl" %} |
| 11442 size(2); | |
| 3851 | 11443 ins_encode %{ |
| 11444 Label* L = $labl$$label; | |
| 11445 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11446 %} | |
| 0 | 11447 ins_pipe(pipe_jcc); |
| 11448 ins_short_branch(1); | |
| 11449 %} | |
| 11450 | |
|
415
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|
11451 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
| 0 | 11452 match(If cop cmp); |
| 11453 effect(USE labl); | |
| 11454 | |
| 11455 ins_cost(300); | |
| 11456 format %{ "j$cop,us $labl" %} | |
| 11457 size(2); | |
| 3851 | 11458 ins_encode %{ |
| 11459 Label* L = $labl$$label; | |
| 11460 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11461 %} | |
| 0 | 11462 ins_pipe(pipe_jcc); |
| 11463 ins_short_branch(1); | |
| 11464 %} | |
| 11465 | |
|
415
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|
11466 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{ |
|
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|
11467 match(If cop cmp); |
|
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diff
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|
11468 effect(USE labl); |
|
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diff
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|
11469 |
|
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diff
changeset
|
11470 ins_cost(300); |
|
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diff
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|
11471 format %{ $$template |
|
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diff
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|
11472 if ($cop$$cmpcode == Assembler::notEqual) { |
|
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|
11473 $$emit$$"jp,u,s $labl\n\t" |
|
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|
11474 $$emit$$"j$cop,u,s $labl" |
|
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diff
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|
11475 } else { |
|
4d9884b01ba6
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diff
changeset
|
11476 $$emit$$"jp,u,s done\n\t" |
|
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diff
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|
11477 $$emit$$"j$cop,u,s $labl\n\t" |
|
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diff
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|
11478 $$emit$$"done:" |
|
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diff
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|
11479 } |
|
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403
diff
changeset
|
11480 %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
11481 size(4); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
11482 ins_encode %{ |
|
4d9884b01ba6
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parents:
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diff
changeset
|
11483 Label* l = $labl$$label; |
|
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|
11484 if ($cop$$cmpcode == Assembler::notEqual) { |
| 3851 | 11485 __ jccb(Assembler::parity, *l); |
| 11486 __ jccb(Assembler::notEqual, *l); | |
|
415
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|
11487 } else if ($cop$$cmpcode == Assembler::equal) { |
| 3851 | 11488 Label done; |
| 11489 __ jccb(Assembler::parity, done); | |
| 11490 __ jccb(Assembler::equal, *l); | |
| 11491 __ bind(done); | |
|
415
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diff
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|
11492 } else { |
| 3851 | 11493 ShouldNotReachHere(); |
| 11494 } | |
|
415
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parents:
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diff
changeset
|
11495 %} |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
11496 ins_pipe(pipe_jcc); |
|
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diff
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|
11497 ins_short_branch(1); |
|
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diff
changeset
|
11498 %} |
|
4d9884b01ba6
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never
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diff
changeset
|
11499 |
| 0 | 11500 // ============================================================================ |
| 11501 // inlined locking and unlocking | |
| 11502 | |
| 11503 instruct cmpFastLock(rFlagsReg cr, | |
| 11504 rRegP object, rRegP box, rax_RegI tmp, rRegP scr) | |
| 11505 %{ | |
| 11506 match(Set cr (FastLock object box)); | |
| 11507 effect(TEMP tmp, TEMP scr); | |
| 11508 | |
| 11509 ins_cost(300); | |
| 11510 format %{ "fastlock $object,$box,$tmp,$scr" %} | |
| 11511 ins_encode(Fast_Lock(object, box, tmp, scr)); | |
| 11512 ins_pipe(pipe_slow); | |
| 11513 %} | |
| 11514 | |
| 11515 instruct cmpFastUnlock(rFlagsReg cr, | |
| 11516 rRegP object, rax_RegP box, rRegP tmp) | |
| 11517 %{ | |
| 11518 match(Set cr (FastUnlock object box)); | |
| 11519 effect(TEMP tmp); | |
| 11520 | |
| 11521 ins_cost(300); | |
| 11522 format %{ "fastunlock $object, $box, $tmp" %} | |
| 11523 ins_encode(Fast_Unlock(object, box, tmp)); | |
| 11524 ins_pipe(pipe_slow); | |
| 11525 %} | |
| 11526 | |
| 11527 | |
| 11528 // ============================================================================ | |
| 11529 // Safepoint Instructions | |
| 11530 instruct safePoint_poll(rFlagsReg cr) | |
| 11531 %{ | |
|
2404
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iveresov
parents:
2401
diff
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|
11532 predicate(!Assembler::is_polling_page_far()); |
| 0 | 11533 match(SafePoint); |
| 11534 effect(KILL cr); | |
| 11535 | |
|
2404
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iveresov
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2401
diff
changeset
|
11536 format %{ "testl rax, [rip + #offset_to_poll_page]\t" |
| 0 | 11537 "# Safepoint: poll for GC" %} |
| 11538 ins_cost(125); | |
|
2404
b40d4fa697bf
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iveresov
parents:
2401
diff
changeset
|
11539 ins_encode %{ |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
11540 AddressLiteral addr(os::get_polling_page(), relocInfo::poll_type); |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
11541 __ testl(rax, addr); |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
11542 %} |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
11543 ins_pipe(ialu_reg_mem); |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
11544 %} |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
11545 |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
11546 instruct safePoint_poll_far(rFlagsReg cr, rRegP poll) |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
11547 %{ |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
11548 predicate(Assembler::is_polling_page_far()); |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
11549 match(SafePoint poll); |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
11550 effect(KILL cr, USE poll); |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
11551 |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
11552 format %{ "testl rax, [$poll]\t" |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
11553 "# Safepoint: poll for GC" %} |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
11554 ins_cost(125); |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
11555 ins_encode %{ |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
11556 __ relocate(relocInfo::poll_type); |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
11557 __ testl(rax, Address($poll$$Register, 0)); |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
11558 %} |
| 0 | 11559 ins_pipe(ialu_reg_mem); |
| 11560 %} | |
| 11561 | |
| 11562 // ============================================================================ | |
| 11563 // Procedure Call/Return Instructions | |
| 11564 // Call Java Static Instruction | |
| 11565 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 11566 // compute_padding() functions will have to be adjusted. | |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
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989
diff
changeset
|
11567 instruct CallStaticJavaDirect(method meth) %{ |
| 0 | 11568 match(CallStaticJava); |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
11569 predicate(!((CallStaticJavaNode*) n)->is_method_handle_invoke()); |
| 0 | 11570 effect(USE meth); |
| 11571 | |
| 11572 ins_cost(300); | |
| 11573 format %{ "call,static " %} | |
| 11574 opcode(0xE8); /* E8 cd */ | |
| 11575 ins_encode(Java_Static_Call(meth), call_epilog); | |
| 11576 ins_pipe(pipe_slow); | |
| 11577 ins_alignment(4); | |
| 11578 %} | |
| 11579 | |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
11580 // Call Java Static Instruction (method handle version) |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
11581 // Note: If this code changes, the corresponding ret_addr_offset() and |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
11582 // compute_padding() functions will have to be adjusted. |
| 1567 | 11583 instruct CallStaticJavaHandle(method meth, rbp_RegP rbp_mh_SP_save) %{ |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
11584 match(CallStaticJava); |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
11585 predicate(((CallStaticJavaNode*) n)->is_method_handle_invoke()); |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
11586 effect(USE meth); |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
11587 // RBP is saved by all callees (for interpreter stack correction). |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
11588 // We use it here for a similar purpose, in {preserve,restore}_SP. |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
11589 |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
11590 ins_cost(300); |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
11591 format %{ "call,static/MethodHandle " %} |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
11592 opcode(0xE8); /* E8 cd */ |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
11593 ins_encode(preserve_SP, |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
11594 Java_Static_Call(meth), |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
11595 restore_SP, |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
11596 call_epilog); |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
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diff
changeset
|
11597 ins_pipe(pipe_slow); |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
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diff
changeset
|
11598 ins_alignment(4); |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
11599 %} |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
11600 |
| 0 | 11601 // Call Java Dynamic Instruction |
| 11602 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 11603 // compute_padding() functions will have to be adjusted. | |
| 11604 instruct CallDynamicJavaDirect(method meth) | |
| 11605 %{ | |
| 11606 match(CallDynamicJava); | |
| 11607 effect(USE meth); | |
| 11608 | |
| 11609 ins_cost(300); | |
| 11610 format %{ "movq rax, #Universe::non_oop_word()\n\t" | |
| 11611 "call,dynamic " %} | |
| 11612 opcode(0xE8); /* E8 cd */ | |
| 11613 ins_encode(Java_Dynamic_Call(meth), call_epilog); | |
| 11614 ins_pipe(pipe_slow); | |
| 11615 ins_alignment(4); | |
| 11616 %} | |
| 11617 | |
| 11618 // Call Runtime Instruction | |
| 11619 instruct CallRuntimeDirect(method meth) | |
| 11620 %{ | |
| 11621 match(CallRuntime); | |
| 11622 effect(USE meth); | |
| 11623 | |
| 11624 ins_cost(300); | |
| 11625 format %{ "call,runtime " %} | |
| 11626 opcode(0xE8); /* E8 cd */ | |
| 11627 ins_encode(Java_To_Runtime(meth)); | |
| 11628 ins_pipe(pipe_slow); | |
| 11629 %} | |
| 11630 | |
| 11631 // Call runtime without safepoint | |
| 11632 instruct CallLeafDirect(method meth) | |
| 11633 %{ | |
| 11634 match(CallLeaf); | |
| 11635 effect(USE meth); | |
| 11636 | |
| 11637 ins_cost(300); | |
| 11638 format %{ "call_leaf,runtime " %} | |
| 11639 opcode(0xE8); /* E8 cd */ | |
| 11640 ins_encode(Java_To_Runtime(meth)); | |
| 11641 ins_pipe(pipe_slow); | |
| 11642 %} | |
| 11643 | |
| 11644 // Call runtime without safepoint | |
| 11645 instruct CallLeafNoFPDirect(method meth) | |
| 11646 %{ | |
| 11647 match(CallLeafNoFP); | |
| 11648 effect(USE meth); | |
| 11649 | |
| 11650 ins_cost(300); | |
| 11651 format %{ "call_leaf_nofp,runtime " %} | |
| 11652 opcode(0xE8); /* E8 cd */ | |
| 11653 ins_encode(Java_To_Runtime(meth)); | |
| 11654 ins_pipe(pipe_slow); | |
| 11655 %} | |
| 11656 | |
| 11657 // Return Instruction | |
| 11658 // Remove the return address & jump to it. | |
| 11659 // Notice: We always emit a nop after a ret to make sure there is room | |
| 11660 // for safepoint patching | |
| 11661 instruct Ret() | |
| 11662 %{ | |
| 11663 match(Return); | |
| 11664 | |
| 11665 format %{ "ret" %} | |
| 11666 opcode(0xC3); | |
| 11667 ins_encode(OpcP); | |
| 11668 ins_pipe(pipe_jmp); | |
| 11669 %} | |
| 11670 | |
| 11671 // Tail Call; Jump from runtime stub to Java code. | |
| 11672 // Also known as an 'interprocedural jump'. | |
| 11673 // Target of jump will eventually return to caller. | |
| 11674 // TailJump below removes the return address. | |
| 11675 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop) | |
| 11676 %{ | |
| 11677 match(TailCall jump_target method_oop); | |
| 11678 | |
| 11679 ins_cost(300); | |
| 11680 format %{ "jmp $jump_target\t# rbx holds method oop" %} | |
| 11681 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 11682 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target)); | |
| 11683 ins_pipe(pipe_jmp); | |
| 11684 %} | |
| 11685 | |
| 11686 // Tail Jump; remove the return address; jump to target. | |
| 11687 // TailCall above leaves the return address around. | |
| 11688 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop) | |
| 11689 %{ | |
| 11690 match(TailJump jump_target ex_oop); | |
| 11691 | |
| 11692 ins_cost(300); | |
| 11693 format %{ "popq rdx\t# pop return address\n\t" | |
| 11694 "jmp $jump_target" %} | |
| 11695 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 11696 ins_encode(Opcode(0x5a), // popq rdx | |
| 11697 REX_reg(jump_target), OpcP, reg_opc(jump_target)); | |
| 11698 ins_pipe(pipe_jmp); | |
| 11699 %} | |
| 11700 | |
| 11701 // Create exception oop: created by stack-crawling runtime code. | |
| 11702 // Created exception is now available to this handler, and is setup | |
| 11703 // just prior to jumping to this handler. No code emitted. | |
| 11704 instruct CreateException(rax_RegP ex_oop) | |
| 11705 %{ | |
| 11706 match(Set ex_oop (CreateEx)); | |
| 11707 | |
| 11708 size(0); | |
| 11709 // use the following format syntax | |
| 11710 format %{ "# exception oop is in rax; no code emitted" %} | |
| 11711 ins_encode(); | |
| 11712 ins_pipe(empty); | |
| 11713 %} | |
| 11714 | |
| 11715 // Rethrow exception: | |
| 11716 // The exception oop will come in the first argument position. | |
| 11717 // Then JUMP (not call) to the rethrow stub code. | |
| 11718 instruct RethrowException() | |
| 11719 %{ | |
| 11720 match(Rethrow); | |
| 11721 | |
| 11722 // use the following format syntax | |
| 11723 format %{ "jmp rethrow_stub" %} | |
| 11724 ins_encode(enc_rethrow); | |
| 11725 ins_pipe(pipe_jmp); | |
| 11726 %} | |
| 11727 | |
| 11728 | |
| 11729 //----------PEEPHOLE RULES----------------------------------------------------- | |
| 11730 // These must follow all instruction definitions as they use the names | |
| 11731 // defined in the instructions definitions. | |
| 11732 // | |
| 605 | 11733 // peepmatch ( root_instr_name [preceding_instruction]* ); |
| 0 | 11734 // |
| 11735 // peepconstraint %{ | |
| 11736 // (instruction_number.operand_name relational_op instruction_number.operand_name | |
| 11737 // [, ...] ); | |
| 11738 // // instruction numbers are zero-based using left to right order in peepmatch | |
| 11739 // | |
| 11740 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); | |
| 11741 // // provide an instruction_number.operand_name for each operand that appears | |
| 11742 // // in the replacement instruction's match rule | |
| 11743 // | |
| 11744 // ---------VM FLAGS--------------------------------------------------------- | |
| 11745 // | |
| 11746 // All peephole optimizations can be turned off using -XX:-OptoPeephole | |
| 11747 // | |
| 11748 // Each peephole rule is given an identifying number starting with zero and | |
| 11749 // increasing by one in the order seen by the parser. An individual peephole | |
| 11750 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# | |
| 11751 // on the command-line. | |
| 11752 // | |
| 11753 // ---------CURRENT LIMITATIONS---------------------------------------------- | |
| 11754 // | |
| 11755 // Only match adjacent instructions in same basic block | |
| 11756 // Only equality constraints | |
| 11757 // Only constraints between operands, not (0.dest_reg == RAX_enc) | |
| 11758 // Only one replacement instruction | |
| 11759 // | |
| 11760 // ---------EXAMPLE---------------------------------------------------------- | |
| 11761 // | |
| 11762 // // pertinent parts of existing instructions in architecture description | |
| 11763 // instruct movI(rRegI dst, rRegI src) | |
| 11764 // %{ | |
| 11765 // match(Set dst (CopyI src)); | |
| 11766 // %} | |
| 11767 // | |
| 11768 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr) | |
| 11769 // %{ | |
| 11770 // match(Set dst (AddI dst src)); | |
| 11771 // effect(KILL cr); | |
| 11772 // %} | |
| 11773 // | |
| 11774 // // Change (inc mov) to lea | |
| 11775 // peephole %{ | |
| 11776 // // increment preceeded by register-register move | |
| 11777 // peepmatch ( incI_rReg movI ); | |
| 11778 // // require that the destination register of the increment | |
| 11779 // // match the destination register of the move | |
| 11780 // peepconstraint ( 0.dst == 1.dst ); | |
| 11781 // // construct a replacement instruction that sets | |
| 11782 // // the destination to ( move's source register + one ) | |
| 11783 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) ); | |
| 11784 // %} | |
| 11785 // | |
| 11786 | |
| 11787 // Implementation no longer uses movX instructions since | |
| 11788 // machine-independent system no longer uses CopyX nodes. | |
| 11789 // | |
| 11790 // peephole | |
| 11791 // %{ | |
| 11792 // peepmatch (incI_rReg movI); | |
| 11793 // peepconstraint (0.dst == 1.dst); | |
| 11794 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src)); | |
| 11795 // %} | |
| 11796 | |
| 11797 // peephole | |
| 11798 // %{ | |
| 11799 // peepmatch (decI_rReg movI); | |
| 11800 // peepconstraint (0.dst == 1.dst); | |
| 11801 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src)); | |
| 11802 // %} | |
| 11803 | |
| 11804 // peephole | |
| 11805 // %{ | |
| 11806 // peepmatch (addI_rReg_imm movI); | |
| 11807 // peepconstraint (0.dst == 1.dst); | |
| 11808 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src)); | |
| 11809 // %} | |
| 11810 | |
| 11811 // peephole | |
| 11812 // %{ | |
| 11813 // peepmatch (incL_rReg movL); | |
| 11814 // peepconstraint (0.dst == 1.dst); | |
| 11815 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src)); | |
| 11816 // %} | |
| 11817 | |
| 11818 // peephole | |
| 11819 // %{ | |
| 11820 // peepmatch (decL_rReg movL); | |
| 11821 // peepconstraint (0.dst == 1.dst); | |
| 11822 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src)); | |
| 11823 // %} | |
| 11824 | |
| 11825 // peephole | |
| 11826 // %{ | |
| 11827 // peepmatch (addL_rReg_imm movL); | |
| 11828 // peepconstraint (0.dst == 1.dst); | |
| 11829 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src)); | |
| 11830 // %} | |
| 11831 | |
| 11832 // peephole | |
| 11833 // %{ | |
| 11834 // peepmatch (addP_rReg_imm movP); | |
| 11835 // peepconstraint (0.dst == 1.dst); | |
| 11836 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src)); | |
| 11837 // %} | |
| 11838 | |
| 11839 // // Change load of spilled value to only a spill | |
| 11840 // instruct storeI(memory mem, rRegI src) | |
| 11841 // %{ | |
| 11842 // match(Set mem (StoreI mem src)); | |
| 11843 // %} | |
| 11844 // | |
| 11845 // instruct loadI(rRegI dst, memory mem) | |
| 11846 // %{ | |
| 11847 // match(Set dst (LoadI mem)); | |
| 11848 // %} | |
| 11849 // | |
| 11850 | |
| 11851 peephole | |
| 11852 %{ | |
| 11853 peepmatch (loadI storeI); | |
| 11854 peepconstraint (1.src == 0.dst, 1.mem == 0.mem); | |
| 11855 peepreplace (storeI(1.mem 1.mem 1.src)); | |
| 11856 %} | |
| 11857 | |
| 11858 peephole | |
| 11859 %{ | |
| 11860 peepmatch (loadL storeL); | |
| 11861 peepconstraint (1.src == 0.dst, 1.mem == 0.mem); | |
| 11862 peepreplace (storeL(1.mem 1.mem 1.src)); | |
| 11863 %} | |
| 11864 | |
| 11865 //----------SMARTSPILL RULES--------------------------------------------------- | |
| 11866 // These must follow all instruction definitions as they use the names | |
| 11867 // defined in the instructions definitions. |