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8027754: Enable loop optimizations for loops with MathExact inside Reviewed-by: kvn, iveresov
author rbackman
date Thu, 23 Jan 2014 12:08:28 +0100
parents 4d4ea046d32a
children 8a8ff6b577ed
comparison
equal deleted inserted replaced
17725:b4ce4e9eb97d 17726:085b304a1cc5
1647 1647
1648 const RegMask Matcher::method_handle_invoke_SP_save_mask() { 1648 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1649 return PTR_RBP_REG_mask(); 1649 return PTR_RBP_REG_mask();
1650 } 1650 }
1651 1651
1652 const RegMask Matcher::mathExactI_result_proj_mask() {
1653 return INT_RAX_REG_mask();
1654 }
1655
1656 const RegMask Matcher::mathExactL_result_proj_mask() {
1657 return LONG_RAX_REG_mask();
1658 }
1659
1660 const RegMask Matcher::mathExactI_flags_proj_mask() {
1661 return INT_FLAGS_mask();
1662 }
1663
1664 %} 1652 %}
1665 1653
1666 //----------ENCODING BLOCK----------------------------------------------------- 1654 //----------ENCODING BLOCK-----------------------------------------------------
1667 // This block specifies the encoding classes used by the compiler to 1655 // This block specifies the encoding classes used by the compiler to
1668 // output byte streams. Encoding classes are parameterized macros 1656 // output byte streams. Encoding classes are parameterized macros
6726 %} 6714 %}
6727 6715
6728 //----------Arithmetic Instructions-------------------------------------------- 6716 //----------Arithmetic Instructions--------------------------------------------
6729 //----------Addition Instructions---------------------------------------------- 6717 //----------Addition Instructions----------------------------------------------
6730 6718
6731 instruct addExactI_rReg(rax_RegI dst, rRegI src, rFlagsReg cr)
6732 %{
6733 match(AddExactI dst src);
6734 effect(DEF cr);
6735
6736 format %{ "addl $dst, $src\t# addExact int" %}
6737 ins_encode %{
6738 __ addl($dst$$Register, $src$$Register);
6739 %}
6740 ins_pipe(ialu_reg_reg);
6741 %}
6742
6743 instruct addExactI_rReg_imm(rax_RegI dst, immI src, rFlagsReg cr)
6744 %{
6745 match(AddExactI dst src);
6746 effect(DEF cr);
6747
6748 format %{ "addl $dst, $src\t# addExact int" %}
6749 ins_encode %{
6750 __ addl($dst$$Register, $src$$constant);
6751 %}
6752 ins_pipe(ialu_reg_reg);
6753 %}
6754
6755 instruct addExactI_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr)
6756 %{
6757 match(AddExactI dst (LoadI src));
6758 effect(DEF cr);
6759
6760 ins_cost(125); // XXX
6761 format %{ "addl $dst, $src\t# addExact int" %}
6762 ins_encode %{
6763 __ addl($dst$$Register, $src$$Address);
6764 %}
6765
6766 ins_pipe(ialu_reg_mem);
6767 %}
6768
6769 instruct addExactL_rReg(rax_RegL dst, rRegL src, rFlagsReg cr)
6770 %{
6771 match(AddExactL dst src);
6772 effect(DEF cr);
6773
6774 format %{ "addq $dst, $src\t# addExact long" %}
6775 ins_encode %{
6776 __ addq($dst$$Register, $src$$Register);
6777 %}
6778 ins_pipe(ialu_reg_reg);
6779 %}
6780
6781 instruct addExactL_rReg_imm(rax_RegL dst, immL32 src, rFlagsReg cr)
6782 %{
6783 match(AddExactL dst src);
6784 effect(DEF cr);
6785
6786 format %{ "addq $dst, $src\t# addExact long" %}
6787 ins_encode %{
6788 __ addq($dst$$Register, $src$$constant);
6789 %}
6790 ins_pipe(ialu_reg_reg);
6791 %}
6792
6793 instruct addExactL_rReg_mem(rax_RegL dst, memory src, rFlagsReg cr)
6794 %{
6795 match(AddExactL dst (LoadL src));
6796 effect(DEF cr);
6797
6798 ins_cost(125); // XXX
6799 format %{ "addq $dst, $src\t# addExact long" %}
6800 ins_encode %{
6801 __ addq($dst$$Register, $src$$Address);
6802 %}
6803
6804 ins_pipe(ialu_reg_mem);
6805 %}
6806
6807 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr) 6719 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
6808 %{ 6720 %{
6809 match(Set dst (AddI dst src)); 6721 match(Set dst (AddI dst src));
6810 effect(KILL cr); 6722 effect(KILL cr);
6811 6723
7414 opcode(0x81); /* Opcode 81 /5 id */ 7326 opcode(0x81); /* Opcode 81 /5 id */
7415 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src)); 7327 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
7416 ins_pipe(ialu_mem_imm); 7328 ins_pipe(ialu_mem_imm);
7417 %} 7329 %}
7418 7330
7419 instruct subExactI_rReg(rax_RegI dst, rRegI src, rFlagsReg cr)
7420 %{
7421 match(SubExactI dst src);
7422 effect(DEF cr);
7423
7424 format %{ "subl $dst, $src\t# subExact int" %}
7425 ins_encode %{
7426 __ subl($dst$$Register, $src$$Register);
7427 %}
7428 ins_pipe(ialu_reg_reg);
7429 %}
7430
7431 instruct subExactI_rReg_imm(rax_RegI dst, immI src, rFlagsReg cr)
7432 %{
7433 match(SubExactI dst src);
7434 effect(DEF cr);
7435
7436 format %{ "subl $dst, $src\t# subExact int" %}
7437 ins_encode %{
7438 __ subl($dst$$Register, $src$$constant);
7439 %}
7440 ins_pipe(ialu_reg_reg);
7441 %}
7442
7443 instruct subExactI_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr)
7444 %{
7445 match(SubExactI dst (LoadI src));
7446 effect(DEF cr);
7447
7448 ins_cost(125);
7449 format %{ "subl $dst, $src\t# subExact int" %}
7450 ins_encode %{
7451 __ subl($dst$$Register, $src$$Address);
7452 %}
7453 ins_pipe(ialu_reg_mem);
7454 %}
7455
7456 instruct subExactL_rReg(rax_RegL dst, rRegL src, rFlagsReg cr)
7457 %{
7458 match(SubExactL dst src);
7459 effect(DEF cr);
7460
7461 format %{ "subq $dst, $src\t# subExact long" %}
7462 ins_encode %{
7463 __ subq($dst$$Register, $src$$Register);
7464 %}
7465 ins_pipe(ialu_reg_reg);
7466 %}
7467
7468 instruct subExactL_rReg_imm(rax_RegL dst, immL32 src, rFlagsReg cr)
7469 %{
7470 match(SubExactL dst (LoadL src));
7471 effect(DEF cr);
7472
7473 format %{ "subq $dst, $src\t# subExact long" %}
7474 ins_encode %{
7475 __ subq($dst$$Register, $src$$constant);
7476 %}
7477 ins_pipe(ialu_reg_reg);
7478 %}
7479
7480 instruct subExactL_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr)
7481 %{
7482 match(SubExactI dst src);
7483 effect(DEF cr);
7484
7485 ins_cost(125);
7486 format %{ "subq $dst, $src\t# subExact long" %}
7487 ins_encode %{
7488 __ subq($dst$$Register, $src$$Address);
7489 %}
7490 ins_pipe(ialu_reg_mem);
7491 %}
7492
7493 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr) 7331 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7494 %{ 7332 %{
7495 match(Set dst (SubL dst src)); 7333 match(Set dst (SubL dst src));
7496 effect(KILL cr); 7334 effect(KILL cr);
7497 7335
7604 opcode(0xF7, 0x03); // Opcode F7 /3 7442 opcode(0xF7, 0x03); // Opcode F7 /3
7605 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); 7443 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
7606 ins_pipe(ialu_reg); 7444 ins_pipe(ialu_reg);
7607 %} 7445 %}
7608 7446
7609 instruct negExactI_rReg(rax_RegI dst, rFlagsReg cr)
7610 %{
7611 match(NegExactI dst);
7612 effect(KILL cr);
7613
7614 format %{ "negl $dst\t# negExact int" %}
7615 ins_encode %{
7616 __ negl($dst$$Register);
7617 %}
7618 ins_pipe(ialu_reg);
7619 %}
7620
7621 instruct negExactL_rReg(rax_RegL dst, rFlagsReg cr)
7622 %{
7623 match(NegExactL dst);
7624 effect(KILL cr);
7625
7626 format %{ "negq $dst\t# negExact long" %}
7627 ins_encode %{
7628 __ negq($dst$$Register);
7629 %}
7630 ins_pipe(ialu_reg);
7631 %}
7632
7633
7634 //----------Multiplication/Division Instructions------------------------------- 7447 //----------Multiplication/Division Instructions-------------------------------
7635 // Integer Multiplication Instructions 7448 // Integer Multiplication Instructions
7636 // Multiply Register 7449 // Multiply Register
7637 7450
7638 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr) 7451 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7743 ins_cost(300); 7556 ins_cost(300);
7744 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %} 7557 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
7745 opcode(0xF7, 0x5); /* Opcode F7 /5 */ 7558 opcode(0xF7, 0x5); /* Opcode F7 /5 */
7746 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src)); 7559 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
7747 ins_pipe(ialu_reg_reg_alu0); 7560 ins_pipe(ialu_reg_reg_alu0);
7748 %}
7749
7750
7751 instruct mulExactI_rReg(rax_RegI dst, rRegI src, rFlagsReg cr)
7752 %{
7753 match(MulExactI dst src);
7754 effect(DEF cr);
7755
7756 ins_cost(300);
7757 format %{ "imull $dst, $src\t# mulExact int" %}
7758 ins_encode %{
7759 __ imull($dst$$Register, $src$$Register);
7760 %}
7761 ins_pipe(ialu_reg_reg_alu0);
7762 %}
7763
7764
7765 instruct mulExactI_rReg_imm(rax_RegI dst, rRegI src, immI imm, rFlagsReg cr)
7766 %{
7767 match(MulExactI src imm);
7768 effect(DEF cr);
7769
7770 ins_cost(300);
7771 format %{ "imull $dst, $src, $imm\t# mulExact int" %}
7772 ins_encode %{
7773 __ imull($dst$$Register, $src$$Register, $imm$$constant);
7774 %}
7775 ins_pipe(ialu_reg_reg_alu0);
7776 %}
7777
7778 instruct mulExactI_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr)
7779 %{
7780 match(MulExactI dst (LoadI src));
7781 effect(DEF cr);
7782
7783 ins_cost(350);
7784 format %{ "imull $dst, $src\t# mulExact int" %}
7785 ins_encode %{
7786 __ imull($dst$$Register, $src$$Address);
7787 %}
7788 ins_pipe(ialu_reg_mem_alu0);
7789 %}
7790
7791 instruct mulExactL_rReg(rax_RegL dst, rRegL src, rFlagsReg cr)
7792 %{
7793 match(MulExactL dst src);
7794 effect(DEF cr);
7795
7796 ins_cost(300);
7797 format %{ "imulq $dst, $src\t# mulExact long" %}
7798 ins_encode %{
7799 __ imulq($dst$$Register, $src$$Register);
7800 %}
7801 ins_pipe(ialu_reg_reg_alu0);
7802 %}
7803
7804 instruct mulExactL_rReg_imm(rax_RegL dst, rRegL src, immL32 imm, rFlagsReg cr)
7805 %{
7806 match(MulExactL src imm);
7807 effect(DEF cr);
7808
7809 ins_cost(300);
7810 format %{ "imulq $dst, $src, $imm\t# mulExact long" %}
7811 ins_encode %{
7812 __ imulq($dst$$Register, $src$$Register, $imm$$constant);
7813 %}
7814 ins_pipe(ialu_reg_reg_alu0);
7815 %}
7816
7817 instruct mulExactL_rReg_mem(rax_RegL dst, memory src, rFlagsReg cr)
7818 %{
7819 match(MulExactL dst (LoadL src));
7820 effect(DEF cr);
7821
7822 ins_cost(350);
7823 format %{ "imulq $dst, $src\t# mulExact long" %}
7824 ins_encode %{
7825 __ imulq($dst$$Register, $src$$Address);
7826 %}
7827 ins_pipe(ialu_reg_mem_alu0);
7828 %} 7561 %}
7829 7562
7830 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div, 7563 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
7831 rFlagsReg cr) 7564 rFlagsReg cr)
7832 %{ 7565 %{
10431 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register, 10164 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
10432 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister, 10165 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
10433 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register); 10166 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
10434 %} 10167 %}
10435 ins_pipe( pipe_slow ); 10168 ins_pipe( pipe_slow );
10169 %}
10170
10171 //----------Overflow Math Instructions-----------------------------------------
10172
10173 instruct overflowAddI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
10174 %{
10175 match(Set cr (OverflowAddI op1 op2));
10176 effect(DEF cr, USE_KILL op1, USE op2);
10177
10178 format %{ "addl $op1, $op2\t# overflow check int" %}
10179
10180 ins_encode %{
10181 __ addl($op1$$Register, $op2$$Register);
10182 %}
10183 ins_pipe(ialu_reg_reg);
10184 %}
10185
10186 instruct overflowAddI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2)
10187 %{
10188 match(Set cr (OverflowAddI op1 op2));
10189 effect(DEF cr, USE_KILL op1, USE op2);
10190
10191 format %{ "addl $op1, $op2\t# overflow check int" %}
10192
10193 ins_encode %{
10194 __ addl($op1$$Register, $op2$$constant);
10195 %}
10196 ins_pipe(ialu_reg_reg);
10197 %}
10198
10199 instruct overflowAddL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
10200 %{
10201 match(Set cr (OverflowAddL op1 op2));
10202 effect(DEF cr, USE_KILL op1, USE op2);
10203
10204 format %{ "addq $op1, $op2\t# overflow check long" %}
10205 ins_encode %{
10206 __ addq($op1$$Register, $op2$$Register);
10207 %}
10208 ins_pipe(ialu_reg_reg);
10209 %}
10210
10211 instruct overflowAddL_rReg_imm(rFlagsReg cr, rax_RegL op1, immL32 op2)
10212 %{
10213 match(Set cr (OverflowAddL op1 op2));
10214 effect(DEF cr, USE_KILL op1, USE op2);
10215
10216 format %{ "addq $op1, $op2\t# overflow check long" %}
10217 ins_encode %{
10218 __ addq($op1$$Register, $op2$$constant);
10219 %}
10220 ins_pipe(ialu_reg_reg);
10221 %}
10222
10223 instruct overflowSubI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
10224 %{
10225 match(Set cr (OverflowSubI op1 op2));
10226
10227 format %{ "cmpl $op1, $op2\t# overflow check int" %}
10228 ins_encode %{
10229 __ cmpl($op1$$Register, $op2$$Register);
10230 %}
10231 ins_pipe(ialu_reg_reg);
10232 %}
10233
10234 instruct overflowSubI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
10235 %{
10236 match(Set cr (OverflowSubI op1 op2));
10237
10238 format %{ "cmpl $op1, $op2\t# overflow check int" %}
10239 ins_encode %{
10240 __ cmpl($op1$$Register, $op2$$constant);
10241 %}
10242 ins_pipe(ialu_reg_reg);
10243 %}
10244
10245 instruct overflowSubL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
10246 %{
10247 match(Set cr (OverflowSubL op1 op2));
10248
10249 format %{ "cmpq $op1, $op2\t# overflow check long" %}
10250 ins_encode %{
10251 __ cmpq($op1$$Register, $op2$$Register);
10252 %}
10253 ins_pipe(ialu_reg_reg);
10254 %}
10255
10256 instruct overflowSubL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
10257 %{
10258 match(Set cr (OverflowSubL op1 op2));
10259
10260 format %{ "cmpq $op1, $op2\t# overflow check long" %}
10261 ins_encode %{
10262 __ cmpq($op1$$Register, $op2$$constant);
10263 %}
10264 ins_pipe(ialu_reg_reg);
10265 %}
10266
10267 instruct overflowNegI_rReg(rFlagsReg cr, immI0 zero, rax_RegI op2)
10268 %{
10269 match(Set cr (OverflowSubI zero op2));
10270 effect(DEF cr, USE_KILL op2);
10271
10272 format %{ "negl $op2\t# overflow check int" %}
10273 ins_encode %{
10274 __ negl($op2$$Register);
10275 %}
10276 ins_pipe(ialu_reg_reg);
10277 %}
10278
10279 instruct overflowNegL_rReg(rFlagsReg cr, immL0 zero, rax_RegL op2)
10280 %{
10281 match(Set cr (OverflowSubL zero op2));
10282 effect(DEF cr, USE_KILL op2);
10283
10284 format %{ "negq $op2\t# overflow check long" %}
10285 ins_encode %{
10286 __ negq($op2$$Register);
10287 %}
10288 ins_pipe(ialu_reg_reg);
10289 %}
10290
10291 instruct overflowMulI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
10292 %{
10293 match(Set cr (OverflowMulI op1 op2));
10294 effect(DEF cr, USE_KILL op1, USE op2);
10295
10296 format %{ "imull $op1, $op2\t# overflow check int" %}
10297 ins_encode %{
10298 __ imull($op1$$Register, $op2$$Register);
10299 %}
10300 ins_pipe(ialu_reg_reg_alu0);
10301 %}
10302
10303 instruct overflowMulI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2, rRegI tmp)
10304 %{
10305 match(Set cr (OverflowMulI op1 op2));
10306 effect(DEF cr, TEMP tmp, USE op1, USE op2);
10307
10308 format %{ "imull $tmp, $op1, $op2\t# overflow check int" %}
10309 ins_encode %{
10310 __ imull($tmp$$Register, $op1$$Register, $op2$$constant);
10311 %}
10312 ins_pipe(ialu_reg_reg_alu0);
10313 %}
10314
10315 instruct overflowMulL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
10316 %{
10317 match(Set cr (OverflowMulL op1 op2));
10318 effect(DEF cr, USE_KILL op1, USE op2);
10319
10320 format %{ "imulq $op1, $op2\t# overflow check long" %}
10321 ins_encode %{
10322 __ imulq($op1$$Register, $op2$$Register);
10323 %}
10324 ins_pipe(ialu_reg_reg_alu0);
10325 %}
10326
10327 instruct overflowMulL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2, rRegL tmp)
10328 %{
10329 match(Set cr (OverflowMulL op1 op2));
10330 effect(DEF cr, TEMP tmp, USE op1, USE op2);
10331
10332 format %{ "imulq $tmp, $op1, $op2\t# overflow check long" %}
10333 ins_encode %{
10334 __ imulq($tmp$$Register, $op1$$Register, $op2$$constant);
10335 %}
10336 ins_pipe(ialu_reg_reg_alu0);
10436 %} 10337 %}
10437 10338
10438 10339
10439 //----------Control Flow Instructions------------------------------------------ 10340 //----------Control Flow Instructions------------------------------------------
10440 // Signed compare Instructions 10341 // Signed compare Instructions