Mercurial > hg > truffle
annotate src/cpu/x86/vm/x86_64.ad @ 17726:085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
Reviewed-by: kvn, iveresov
| author | rbackman |
|---|---|
| date | Thu, 23 Jan 2014 12:08:28 +0100 |
| parents | 4d4ea046d32a |
| children | 8a8ff6b577ed |
| rev | line source |
|---|---|
| 0 | 1 // |
| 9154 | 2 // Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 // | |
| 5 // This code is free software; you can redistribute it and/or modify it | |
| 6 // under the terms of the GNU General Public License version 2 only, as | |
| 7 // published by the Free Software Foundation. | |
| 8 // | |
| 9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 // version 2 for more details (a copy is included in the LICENSE file that | |
| 13 // accompanied this code). | |
| 14 // | |
| 15 // You should have received a copy of the GNU General Public License version | |
| 16 // 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 // | |
|
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19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 // or visit www.oracle.com if you need additional information or have any |
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21 // questions. |
| 0 | 22 // |
| 23 // | |
| 24 | |
| 25 // AMD64 Architecture Description File | |
| 26 | |
| 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ | |
| 28 // This information is used by the matcher and the register allocator to | |
| 29 // describe individual registers and classes of registers within the target | |
| 30 // archtecture. | |
| 31 | |
| 32 register %{ | |
| 33 //----------Architecture Description Register Definitions---------------------- | |
| 34 // General Registers | |
| 35 // "reg_def" name ( register save type, C convention save type, | |
| 36 // ideal register type, encoding ); | |
| 37 // Register Save Types: | |
| 38 // | |
| 39 // NS = No-Save: The register allocator assumes that these registers | |
| 40 // can be used without saving upon entry to the method, & | |
| 41 // that they do not need to be saved at call sites. | |
| 42 // | |
| 43 // SOC = Save-On-Call: The register allocator assumes that these registers | |
| 44 // can be used without saving upon entry to the method, | |
| 45 // but that they must be saved at call sites. | |
| 46 // | |
| 47 // SOE = Save-On-Entry: The register allocator assumes that these registers | |
| 48 // must be saved before using them upon entry to the | |
| 49 // method, but they do not need to be saved at call | |
| 50 // sites. | |
| 51 // | |
| 52 // AS = Always-Save: The register allocator assumes that these registers | |
| 53 // must be saved before using them upon entry to the | |
| 54 // method, & that they must be saved at call sites. | |
| 55 // | |
| 56 // Ideal Register Type is used to determine how to save & restore a | |
| 57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get | |
| 58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. | |
| 59 // | |
| 60 // The encoding number is the actual bit-pattern placed into the opcodes. | |
| 61 | |
| 62 // General Registers | |
| 63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when | |
| 64 // used as byte registers) | |
| 65 | |
| 66 // Previously set RBX, RSI, and RDI as save-on-entry for java code | |
| 67 // Turn off SOE in java-code due to frequent use of uncommon-traps. | |
| 68 // Now that allocator is better, turn on RSI and RDI as SOE registers. | |
| 69 | |
| 70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg()); | |
| 71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next()); | |
| 72 | |
| 73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg()); | |
| 74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next()); | |
| 75 | |
| 76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg()); | |
| 77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next()); | |
| 78 | |
| 79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg()); | |
| 80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next()); | |
| 81 | |
| 82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg()); | |
| 83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next()); | |
| 84 | |
| 85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code | |
| 86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg()); | |
| 87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next()); | |
| 88 | |
| 89 #ifdef _WIN64 | |
| 90 | |
| 91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg()); | |
| 92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next()); | |
| 93 | |
| 94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg()); | |
| 95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next()); | |
| 96 | |
| 97 #else | |
| 98 | |
| 99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg()); | |
| 100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next()); | |
| 101 | |
| 102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg()); | |
| 103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next()); | |
| 104 | |
| 105 #endif | |
| 106 | |
| 107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg()); | |
| 108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next()); | |
| 109 | |
| 110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg()); | |
| 111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next()); | |
| 112 | |
| 113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg()); | |
| 114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next()); | |
| 115 | |
| 116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg()); | |
| 117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next()); | |
| 118 | |
| 119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg()); | |
| 120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next()); | |
| 121 | |
| 122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg()); | |
| 123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next()); | |
| 124 | |
| 125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg()); | |
| 126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next()); | |
| 127 | |
| 128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg()); | |
| 129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next()); | |
| 130 | |
| 131 | |
| 132 // Floating Point Registers | |
| 133 | |
| 134 // Specify priority of register selection within phases of register | |
| 135 // allocation. Highest priority is first. A useful heuristic is to | |
| 136 // give registers a low priority when they are required by machine | |
| 137 // instructions, like EAX and EDX on I486, and choose no-save registers | |
| 138 // before save-on-call, & save-on-call before save-on-entry. Registers | |
| 139 // which participate in fixed calling sequences should come last. | |
| 140 // Registers which are used as pairs must fall on an even boundary. | |
| 141 | |
| 142 alloc_class chunk0(R10, R10_H, | |
| 143 R11, R11_H, | |
| 144 R8, R8_H, | |
| 145 R9, R9_H, | |
| 146 R12, R12_H, | |
| 147 RCX, RCX_H, | |
| 148 RBX, RBX_H, | |
| 149 RDI, RDI_H, | |
| 150 RDX, RDX_H, | |
| 151 RSI, RSI_H, | |
| 152 RAX, RAX_H, | |
| 153 RBP, RBP_H, | |
| 154 R13, R13_H, | |
| 155 R14, R14_H, | |
| 156 R15, R15_H, | |
| 157 RSP, RSP_H); | |
| 158 | |
| 159 | |
| 160 //----------Architecture Description Register Classes-------------------------- | |
| 161 // Several register classes are automatically defined based upon information in | |
| 162 // this architecture description. | |
| 163 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ ) | |
| 164 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ ) | |
| 165 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ ) | |
| 166 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) | |
| 167 // | |
| 168 | |
| 169 // Class for all pointer registers (including RSP) | |
| 170 reg_class any_reg(RAX, RAX_H, | |
| 171 RDX, RDX_H, | |
| 172 RBP, RBP_H, | |
| 173 RDI, RDI_H, | |
| 174 RSI, RSI_H, | |
| 175 RCX, RCX_H, | |
| 176 RBX, RBX_H, | |
| 177 RSP, RSP_H, | |
| 178 R8, R8_H, | |
| 179 R9, R9_H, | |
| 180 R10, R10_H, | |
| 181 R11, R11_H, | |
| 182 R12, R12_H, | |
| 183 R13, R13_H, | |
| 184 R14, R14_H, | |
| 185 R15, R15_H); | |
| 186 | |
| 187 // Class for all pointer registers except RSP | |
| 188 reg_class ptr_reg(RAX, RAX_H, | |
| 189 RDX, RDX_H, | |
| 190 RBP, RBP_H, | |
| 191 RDI, RDI_H, | |
| 192 RSI, RSI_H, | |
| 193 RCX, RCX_H, | |
| 194 RBX, RBX_H, | |
| 195 R8, R8_H, | |
| 196 R9, R9_H, | |
| 197 R10, R10_H, | |
| 198 R11, R11_H, | |
| 199 R13, R13_H, | |
| 200 R14, R14_H); | |
| 201 | |
| 202 // Class for all pointer registers except RAX and RSP | |
| 203 reg_class ptr_no_rax_reg(RDX, RDX_H, | |
| 204 RBP, RBP_H, | |
| 205 RDI, RDI_H, | |
| 206 RSI, RSI_H, | |
| 207 RCX, RCX_H, | |
| 208 RBX, RBX_H, | |
| 209 R8, R8_H, | |
| 210 R9, R9_H, | |
| 211 R10, R10_H, | |
| 212 R11, R11_H, | |
| 213 R13, R13_H, | |
| 214 R14, R14_H); | |
| 215 | |
| 216 reg_class ptr_no_rbp_reg(RDX, RDX_H, | |
| 217 RAX, RAX_H, | |
| 218 RDI, RDI_H, | |
| 219 RSI, RSI_H, | |
| 220 RCX, RCX_H, | |
| 221 RBX, RBX_H, | |
| 222 R8, R8_H, | |
| 223 R9, R9_H, | |
| 224 R10, R10_H, | |
| 225 R11, R11_H, | |
| 226 R13, R13_H, | |
| 227 R14, R14_H); | |
| 228 | |
| 229 // Class for all pointer registers except RAX, RBX and RSP | |
| 230 reg_class ptr_no_rax_rbx_reg(RDX, RDX_H, | |
| 231 RBP, RBP_H, | |
| 232 RDI, RDI_H, | |
| 233 RSI, RSI_H, | |
| 234 RCX, RCX_H, | |
| 235 R8, R8_H, | |
| 236 R9, R9_H, | |
| 237 R10, R10_H, | |
| 238 R11, R11_H, | |
| 239 R13, R13_H, | |
| 240 R14, R14_H); | |
| 241 | |
| 242 // Singleton class for RAX pointer register | |
| 243 reg_class ptr_rax_reg(RAX, RAX_H); | |
| 244 | |
| 245 // Singleton class for RBX pointer register | |
| 246 reg_class ptr_rbx_reg(RBX, RBX_H); | |
| 247 | |
| 248 // Singleton class for RSI pointer register | |
| 249 reg_class ptr_rsi_reg(RSI, RSI_H); | |
| 250 | |
| 251 // Singleton class for RDI pointer register | |
| 252 reg_class ptr_rdi_reg(RDI, RDI_H); | |
| 253 | |
| 254 // Singleton class for RBP pointer register | |
| 255 reg_class ptr_rbp_reg(RBP, RBP_H); | |
| 256 | |
| 257 // Singleton class for stack pointer | |
| 258 reg_class ptr_rsp_reg(RSP, RSP_H); | |
| 259 | |
| 260 // Singleton class for TLS pointer | |
| 261 reg_class ptr_r15_reg(R15, R15_H); | |
| 262 | |
| 263 // Class for all long registers (except RSP) | |
| 264 reg_class long_reg(RAX, RAX_H, | |
| 265 RDX, RDX_H, | |
| 266 RBP, RBP_H, | |
| 267 RDI, RDI_H, | |
| 268 RSI, RSI_H, | |
| 269 RCX, RCX_H, | |
| 270 RBX, RBX_H, | |
| 271 R8, R8_H, | |
| 272 R9, R9_H, | |
| 273 R10, R10_H, | |
| 274 R11, R11_H, | |
| 275 R13, R13_H, | |
| 276 R14, R14_H); | |
| 277 | |
| 278 // Class for all long registers except RAX, RDX (and RSP) | |
| 279 reg_class long_no_rax_rdx_reg(RBP, RBP_H, | |
| 280 RDI, RDI_H, | |
| 281 RSI, RSI_H, | |
| 282 RCX, RCX_H, | |
| 283 RBX, RBX_H, | |
| 284 R8, R8_H, | |
| 285 R9, R9_H, | |
| 286 R10, R10_H, | |
| 287 R11, R11_H, | |
| 288 R13, R13_H, | |
| 289 R14, R14_H); | |
| 290 | |
| 291 // Class for all long registers except RCX (and RSP) | |
| 292 reg_class long_no_rcx_reg(RBP, RBP_H, | |
| 293 RDI, RDI_H, | |
| 294 RSI, RSI_H, | |
| 295 RAX, RAX_H, | |
| 296 RDX, RDX_H, | |
| 297 RBX, RBX_H, | |
| 298 R8, R8_H, | |
| 299 R9, R9_H, | |
| 300 R10, R10_H, | |
| 301 R11, R11_H, | |
| 302 R13, R13_H, | |
| 303 R14, R14_H); | |
| 304 | |
| 305 // Class for all long registers except RAX (and RSP) | |
| 306 reg_class long_no_rax_reg(RBP, RBP_H, | |
| 307 RDX, RDX_H, | |
| 308 RDI, RDI_H, | |
| 309 RSI, RSI_H, | |
| 310 RCX, RCX_H, | |
| 311 RBX, RBX_H, | |
| 312 R8, R8_H, | |
| 313 R9, R9_H, | |
| 314 R10, R10_H, | |
| 315 R11, R11_H, | |
| 316 R13, R13_H, | |
| 317 R14, R14_H); | |
| 318 | |
| 319 // Singleton class for RAX long register | |
| 320 reg_class long_rax_reg(RAX, RAX_H); | |
| 321 | |
| 322 // Singleton class for RCX long register | |
| 323 reg_class long_rcx_reg(RCX, RCX_H); | |
| 324 | |
| 325 // Singleton class for RDX long register | |
| 326 reg_class long_rdx_reg(RDX, RDX_H); | |
| 327 | |
| 328 // Class for all int registers (except RSP) | |
| 329 reg_class int_reg(RAX, | |
| 330 RDX, | |
| 331 RBP, | |
| 332 RDI, | |
| 333 RSI, | |
| 334 RCX, | |
| 335 RBX, | |
| 336 R8, | |
| 337 R9, | |
| 338 R10, | |
| 339 R11, | |
| 340 R13, | |
| 341 R14); | |
| 342 | |
| 343 // Class for all int registers except RCX (and RSP) | |
| 344 reg_class int_no_rcx_reg(RAX, | |
| 345 RDX, | |
| 346 RBP, | |
| 347 RDI, | |
| 348 RSI, | |
| 349 RBX, | |
| 350 R8, | |
| 351 R9, | |
| 352 R10, | |
| 353 R11, | |
| 354 R13, | |
| 355 R14); | |
| 356 | |
| 357 // Class for all int registers except RAX, RDX (and RSP) | |
| 358 reg_class int_no_rax_rdx_reg(RBP, | |
| 304 | 359 RDI, |
| 0 | 360 RSI, |
| 361 RCX, | |
| 362 RBX, | |
| 363 R8, | |
| 364 R9, | |
| 365 R10, | |
| 366 R11, | |
| 367 R13, | |
| 368 R14); | |
| 369 | |
| 370 // Singleton class for RAX int register | |
| 371 reg_class int_rax_reg(RAX); | |
| 372 | |
| 373 // Singleton class for RBX int register | |
| 374 reg_class int_rbx_reg(RBX); | |
| 375 | |
| 376 // Singleton class for RCX int register | |
| 377 reg_class int_rcx_reg(RCX); | |
| 378 | |
| 379 // Singleton class for RCX int register | |
| 380 reg_class int_rdx_reg(RDX); | |
| 381 | |
| 382 // Singleton class for RCX int register | |
| 383 reg_class int_rdi_reg(RDI); | |
| 384 | |
| 385 // Singleton class for instruction pointer | |
| 386 // reg_class ip_reg(RIP); | |
| 387 | |
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388 %} |
| 0 | 389 |
| 390 //----------SOURCE BLOCK------------------------------------------------------- | |
| 391 // This is a block of C++ code which provides values, functions, and | |
| 392 // definitions necessary in the rest of the architecture description | |
| 393 source %{ | |
| 304 | 394 #define RELOC_IMM64 Assembler::imm_operand |
| 0 | 395 #define RELOC_DISP32 Assembler::disp32_operand |
| 396 | |
| 397 #define __ _masm. | |
| 398 | |
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399 static int preserve_SP_size() { |
| 4759 | 400 return 3; // rex.w, op, rm(reg/reg) |
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401 } |
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402 static int clear_avx_size() { |
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403 return (Compile::current()->max_vector_size() > 16) ? 3 : 0; // vzeroupper |
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404 } |
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405 |
| 0 | 406 // !!!!! Special hack to get all types of calls to specify the byte offset |
| 407 // from the start of the call to the point where the return address | |
| 408 // will point. | |
| 409 int MachCallStaticJavaNode::ret_addr_offset() | |
| 410 { | |
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411 int offset = 5; // 5 bytes from start of call to where return address points |
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412 offset += clear_avx_size(); |
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413 if (_method_handle_invoke) |
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414 offset += preserve_SP_size(); |
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415 return offset; |
| 0 | 416 } |
| 417 | |
| 418 int MachCallDynamicJavaNode::ret_addr_offset() | |
| 419 { | |
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420 int offset = 15; // 15 bytes from start of call to where return address points |
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421 offset += clear_avx_size(); |
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422 return offset; |
| 0 | 423 } |
| 424 | |
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425 int MachCallRuntimeNode::ret_addr_offset() { |
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426 int offset = 13; // movq r10,#addr; callq (r10) |
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427 offset += clear_avx_size(); |
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428 return offset; |
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429 } |
| 0 | 430 |
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431 // Indicate if the safepoint node needs the polling page as an input, |
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432 // it does if the polling page is more than disp32 away. |
| 0 | 433 bool SafePointNode::needs_polling_address_input() |
| 434 { | |
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435 return Assembler::is_polling_page_far(); |
| 0 | 436 } |
| 437 | |
| 438 // | |
| 439 // Compute padding required for nodes which need alignment | |
| 440 // | |
| 441 | |
| 442 // The address of the call instruction needs to be 4-byte aligned to | |
| 443 // ensure that it does not span a cache line so that it can be patched. | |
| 444 int CallStaticJavaDirectNode::compute_padding(int current_offset) const | |
| 445 { | |
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446 current_offset += clear_avx_size(); // skip vzeroupper |
| 0 | 447 current_offset += 1; // skip call opcode byte |
| 448 return round_to(current_offset, alignment_required()) - current_offset; | |
| 449 } | |
| 450 | |
| 451 // The address of the call instruction needs to be 4-byte aligned to | |
| 452 // ensure that it does not span a cache line so that it can be patched. | |
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453 int CallStaticJavaHandleNode::compute_padding(int current_offset) const |
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454 { |
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455 current_offset += preserve_SP_size(); // skip mov rbp, rsp |
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456 current_offset += clear_avx_size(); // skip vzeroupper |
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457 current_offset += 1; // skip call opcode byte |
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458 return round_to(current_offset, alignment_required()) - current_offset; |
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459 } |
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460 |
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461 // The address of the call instruction needs to be 4-byte aligned to |
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462 // ensure that it does not span a cache line so that it can be patched. |
| 0 | 463 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const |
| 464 { | |
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465 current_offset += clear_avx_size(); // skip vzeroupper |
| 0 | 466 current_offset += 11; // skip movq instruction + call opcode byte |
| 467 return round_to(current_offset, alignment_required()) - current_offset; | |
| 468 } | |
| 469 | |
| 470 // EMIT_RM() | |
| 1748 | 471 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) { |
| 0 | 472 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3); |
| 1748 | 473 cbuf.insts()->emit_int8(c); |
| 0 | 474 } |
| 475 | |
| 476 // EMIT_CC() | |
| 1748 | 477 void emit_cc(CodeBuffer &cbuf, int f1, int f2) { |
| 0 | 478 unsigned char c = (unsigned char) (f1 | f2); |
| 1748 | 479 cbuf.insts()->emit_int8(c); |
| 0 | 480 } |
| 481 | |
| 482 // EMIT_OPCODE() | |
| 1748 | 483 void emit_opcode(CodeBuffer &cbuf, int code) { |
| 484 cbuf.insts()->emit_int8((unsigned char) code); | |
| 0 | 485 } |
| 486 | |
| 487 // EMIT_OPCODE() w/ relocation information | |
| 488 void emit_opcode(CodeBuffer &cbuf, | |
| 489 int code, relocInfo::relocType reloc, int offset, int format) | |
| 490 { | |
| 1748 | 491 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format); |
| 0 | 492 emit_opcode(cbuf, code); |
| 493 } | |
| 494 | |
| 495 // EMIT_D8() | |
| 1748 | 496 void emit_d8(CodeBuffer &cbuf, int d8) { |
| 497 cbuf.insts()->emit_int8((unsigned char) d8); | |
| 0 | 498 } |
| 499 | |
| 500 // EMIT_D16() | |
| 1748 | 501 void emit_d16(CodeBuffer &cbuf, int d16) { |
| 502 cbuf.insts()->emit_int16(d16); | |
| 0 | 503 } |
| 504 | |
| 505 // EMIT_D32() | |
| 1748 | 506 void emit_d32(CodeBuffer &cbuf, int d32) { |
| 507 cbuf.insts()->emit_int32(d32); | |
| 0 | 508 } |
| 509 | |
| 510 // EMIT_D64() | |
| 1748 | 511 void emit_d64(CodeBuffer &cbuf, int64_t d64) { |
| 512 cbuf.insts()->emit_int64(d64); | |
| 0 | 513 } |
| 514 | |
| 515 // emit 32 bit value and construct relocation entry from relocInfo::relocType | |
| 516 void emit_d32_reloc(CodeBuffer& cbuf, | |
| 517 int d32, | |
| 518 relocInfo::relocType reloc, | |
| 519 int format) | |
| 520 { | |
| 521 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc"); | |
| 1748 | 522 cbuf.relocate(cbuf.insts_mark(), reloc, format); |
| 523 cbuf.insts()->emit_int32(d32); | |
| 0 | 524 } |
| 525 | |
| 526 // emit 32 bit value and construct relocation entry from RelocationHolder | |
| 1748 | 527 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) { |
| 0 | 528 #ifdef ASSERT |
| 529 if (rspec.reloc()->type() == relocInfo::oop_type && | |
| 530 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) { | |
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531 assert(Universe::heap()->is_in_reserved((address)(intptr_t)d32), "should be real oop"); |
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532 assert(cast_to_oop((intptr_t)d32)->is_oop() && (ScavengeRootsInCode || !cast_to_oop((intptr_t)d32)->is_scavengable()), "cannot embed scavengable oops in code"); |
| 0 | 533 } |
| 534 #endif | |
| 1748 | 535 cbuf.relocate(cbuf.insts_mark(), rspec, format); |
| 536 cbuf.insts()->emit_int32(d32); | |
| 0 | 537 } |
| 538 | |
| 539 void emit_d32_reloc(CodeBuffer& cbuf, address addr) { | |
| 1748 | 540 address next_ip = cbuf.insts_end() + 4; |
| 0 | 541 emit_d32_reloc(cbuf, (int) (addr - next_ip), |
| 542 external_word_Relocation::spec(addr), | |
| 543 RELOC_DISP32); | |
| 544 } | |
| 545 | |
| 546 | |
| 547 // emit 64 bit value and construct relocation entry from relocInfo::relocType | |
| 1748 | 548 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) { |
| 549 cbuf.relocate(cbuf.insts_mark(), reloc, format); | |
| 550 cbuf.insts()->emit_int64(d64); | |
| 0 | 551 } |
| 552 | |
| 553 // emit 64 bit value and construct relocation entry from RelocationHolder | |
| 1748 | 554 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) { |
| 0 | 555 #ifdef ASSERT |
| 556 if (rspec.reloc()->type() == relocInfo::oop_type && | |
| 557 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) { | |
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558 assert(Universe::heap()->is_in_reserved((address)d64), "should be real oop"); |
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559 assert(cast_to_oop(d64)->is_oop() && (ScavengeRootsInCode || !cast_to_oop(d64)->is_scavengable()), |
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560 "cannot embed scavengable oops in code"); |
| 0 | 561 } |
| 562 #endif | |
| 1748 | 563 cbuf.relocate(cbuf.insts_mark(), rspec, format); |
| 564 cbuf.insts()->emit_int64(d64); | |
| 0 | 565 } |
| 566 | |
| 567 // Access stack slot for load or store | |
| 568 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) | |
| 569 { | |
| 570 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src]) | |
| 571 if (-0x80 <= disp && disp < 0x80) { | |
| 572 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte | |
| 573 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte | |
| 574 emit_d8(cbuf, disp); // Displacement // R/M byte | |
| 575 } else { | |
| 576 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte | |
| 577 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte | |
| 578 emit_d32(cbuf, disp); // Displacement // R/M byte | |
| 579 } | |
| 580 } | |
| 581 | |
| 582 // rRegI ereg, memory mem) %{ // emit_reg_mem | |
| 583 void encode_RegMem(CodeBuffer &cbuf, | |
| 584 int reg, | |
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585 int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) |
| 0 | 586 { |
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587 assert(disp_reloc == relocInfo::none, "cannot have disp"); |
| 0 | 588 int regenc = reg & 7; |
| 589 int baseenc = base & 7; | |
| 590 int indexenc = index & 7; | |
| 591 | |
| 592 // There is no index & no scale, use form without SIB byte | |
| 593 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) { | |
| 594 // If no displacement, mode is 0x0; unless base is [RBP] or [R13] | |
| 595 if (disp == 0 && base != RBP_enc && base != R13_enc) { | |
| 596 emit_rm(cbuf, 0x0, regenc, baseenc); // * | |
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597 } else if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) { |
| 0 | 598 // If 8-bit displacement, mode 0x1 |
| 599 emit_rm(cbuf, 0x1, regenc, baseenc); // * | |
| 600 emit_d8(cbuf, disp); | |
| 601 } else { | |
| 602 // If 32-bit displacement | |
| 603 if (base == -1) { // Special flag for absolute address | |
| 604 emit_rm(cbuf, 0x0, regenc, 0x5); // * | |
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605 if (disp_reloc != relocInfo::none) { |
| 0 | 606 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32); |
| 607 } else { | |
| 608 emit_d32(cbuf, disp); | |
| 609 } | |
| 610 } else { | |
| 611 // Normal base + offset | |
| 612 emit_rm(cbuf, 0x2, regenc, baseenc); // * | |
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613 if (disp_reloc != relocInfo::none) { |
| 0 | 614 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32); |
| 615 } else { | |
| 616 emit_d32(cbuf, disp); | |
| 617 } | |
| 618 } | |
| 619 } | |
| 620 } else { | |
| 621 // Else, encode with the SIB byte | |
| 622 // If no displacement, mode is 0x0; unless base is [RBP] or [R13] | |
| 623 if (disp == 0 && base != RBP_enc && base != R13_enc) { | |
| 624 // If no displacement | |
| 625 emit_rm(cbuf, 0x0, regenc, 0x4); // * | |
| 626 emit_rm(cbuf, scale, indexenc, baseenc); | |
| 627 } else { | |
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628 if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) { |
| 0 | 629 // If 8-bit displacement, mode 0x1 |
| 630 emit_rm(cbuf, 0x1, regenc, 0x4); // * | |
| 631 emit_rm(cbuf, scale, indexenc, baseenc); | |
| 632 emit_d8(cbuf, disp); | |
| 633 } else { | |
| 634 // If 32-bit displacement | |
| 635 if (base == 0x04 ) { | |
| 636 emit_rm(cbuf, 0x2, regenc, 0x4); | |
| 637 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid??? | |
| 638 } else { | |
| 639 emit_rm(cbuf, 0x2, regenc, 0x4); | |
| 640 emit_rm(cbuf, scale, indexenc, baseenc); // * | |
| 641 } | |
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642 if (disp_reloc != relocInfo::none) { |
| 0 | 643 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32); |
| 644 } else { | |
| 645 emit_d32(cbuf, disp); | |
| 646 } | |
| 647 } | |
| 648 } | |
| 649 } | |
| 650 } | |
| 651 | |
| 3783 | 652 // This could be in MacroAssembler but it's fairly C2 specific |
| 653 void emit_cmpfp_fixup(MacroAssembler& _masm) { | |
| 654 Label exit; | |
| 655 __ jccb(Assembler::noParity, exit); | |
| 656 __ pushf(); | |
| 4759 | 657 // |
| 658 // comiss/ucomiss instructions set ZF,PF,CF flags and | |
| 659 // zero OF,AF,SF for NaN values. | |
| 660 // Fixup flags by zeroing ZF,PF so that compare of NaN | |
| 661 // values returns 'less than' result (CF is set). | |
| 662 // Leave the rest of flags unchanged. | |
| 663 // | |
| 664 // 7 6 5 4 3 2 1 0 | |
| 665 // |S|Z|r|A|r|P|r|C| (r - reserved bit) | |
| 666 // 0 0 1 0 1 0 1 1 (0x2B) | |
| 667 // | |
| 3783 | 668 __ andq(Address(rsp, 0), 0xffffff2b); |
| 669 __ popf(); | |
| 670 __ bind(exit); | |
| 4759 | 671 } |
| 672 | |
| 673 void emit_cmpfp3(MacroAssembler& _masm, Register dst) { | |
| 674 Label done; | |
| 675 __ movl(dst, -1); | |
| 676 __ jcc(Assembler::parity, done); | |
| 677 __ jcc(Assembler::below, done); | |
| 678 __ setb(Assembler::notEqual, dst); | |
| 679 __ movzbl(dst, dst); | |
| 680 __ bind(done); | |
| 3783 | 681 } |
| 682 | |
| 0 | 683 |
| 684 //============================================================================= | |
| 2008 | 685 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty; |
| 686 | |
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687 int Compile::ConstantTable::calculate_table_base_offset() const { |
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688 return 0; // absolute addressing, no offset |
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689 } |
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690 |
| 2008 | 691 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { |
| 692 // Empty encoding | |
| 693 } | |
| 694 | |
| 695 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const { | |
| 696 return 0; | |
| 697 } | |
| 698 | |
| 699 #ifndef PRODUCT | |
| 700 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { | |
| 701 st->print("# MachConstantBaseNode (empty encoding)"); | |
| 702 } | |
| 703 #endif | |
| 704 | |
| 705 | |
| 706 //============================================================================= | |
| 0 | 707 #ifndef PRODUCT |
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708 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const { |
| 0 | 709 Compile* C = ra_->C; |
| 710 | |
| 711 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 712 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
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713 // Remove wordSize for return addr which is already pushed. |
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714 framesize -= wordSize; |
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715 |
| 0 | 716 if (C->need_stack_bang(framesize)) { |
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717 framesize -= wordSize; |
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718 st->print("# stack bang"); |
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719 st->print("\n\t"); |
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720 st->print("pushq rbp\t# Save rbp"); |
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721 if (framesize) { |
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722 st->print("\n\t"); |
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723 st->print("subq rsp, #%d\t# Create frame",framesize); |
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724 } |
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725 } else { |
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726 st->print("subq rsp, #%d\t# Create frame",framesize); |
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727 st->print("\n\t"); |
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728 framesize -= wordSize; |
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729 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize); |
| 0 | 730 } |
| 731 | |
| 732 if (VerifyStackAtCalls) { | |
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733 st->print("\n\t"); |
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734 framesize -= wordSize; |
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735 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize); |
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736 #ifdef ASSERT |
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737 st->print("\n\t"); |
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738 st->print("# stack alignment check"); |
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739 #endif |
| 0 | 740 } |
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741 st->cr(); |
| 0 | 742 } |
| 743 #endif | |
| 744 | |
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745 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { |
| 0 | 746 Compile* C = ra_->C; |
|
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747 MacroAssembler _masm(&cbuf); |
| 0 | 748 |
| 749 int framesize = C->frame_slots() << LogBytesPerInt; | |
|
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750 |
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751 __ verified_entry(framesize, C->need_stack_bang(framesize), false); |
| 0 | 752 |
| 1748 | 753 C->set_frame_complete(cbuf.insts_size()); |
| 0 | 754 |
|
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755 if (C->has_mach_constant_base_node()) { |
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756 // NOTE: We set the table base offset here because users might be |
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757 // emitted before MachConstantBaseNode. |
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758 Compile::ConstantTable& constant_table = C->constant_table(); |
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759 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset()); |
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760 } |
| 0 | 761 } |
| 762 | |
| 763 uint MachPrologNode::size(PhaseRegAlloc* ra_) const | |
| 764 { | |
| 765 return MachNode::size(ra_); // too many variables; just compute it | |
| 766 // the hard way | |
| 767 } | |
| 768 | |
| 769 int MachPrologNode::reloc() const | |
| 770 { | |
| 771 return 0; // a large enough number | |
| 772 } | |
| 773 | |
| 774 //============================================================================= | |
| 775 #ifndef PRODUCT | |
| 776 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const | |
| 777 { | |
| 778 Compile* C = ra_->C; | |
|
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779 if (C->max_vector_size() > 16) { |
|
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780 st->print("vzeroupper"); |
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781 st->cr(); st->print("\t"); |
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782 } |
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783 |
| 0 | 784 int framesize = C->frame_slots() << LogBytesPerInt; |
| 785 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 786 // Remove word for return adr already pushed | |
| 787 // and RBP | |
| 788 framesize -= 2*wordSize; | |
| 789 | |
| 790 if (framesize) { | |
|
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791 st->print_cr("addq rsp, %d\t# Destroy frame", framesize); |
| 0 | 792 st->print("\t"); |
| 793 } | |
| 794 | |
|
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795 st->print_cr("popq rbp"); |
| 0 | 796 if (do_polling() && C->is_method_compilation()) { |
| 797 st->print("\t"); | |
|
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798 if (Assembler::is_polling_page_far()) { |
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799 st->print_cr("movq rscratch1, #polling_page_address\n\t" |
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800 "testl rax, [rscratch1]\t" |
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801 "# Safepoint: poll for GC"); |
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802 } else { |
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803 st->print_cr("testl rax, [rip + #offset_to_poll_page]\t" |
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804 "# Safepoint: poll for GC"); |
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805 } |
| 0 | 806 } |
| 807 } | |
| 808 #endif | |
| 809 | |
| 810 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const | |
| 811 { | |
| 812 Compile* C = ra_->C; | |
|
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813 if (C->max_vector_size() > 16) { |
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814 // Clear upper bits of YMM registers when current compiled code uses |
|
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815 // wide vectors to avoid AVX <-> SSE transition penalty during call. |
|
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816 MacroAssembler _masm(&cbuf); |
|
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|
817 __ vzeroupper(); |
|
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|
818 } |
|
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|
819 |
| 0 | 820 int framesize = C->frame_slots() << LogBytesPerInt; |
| 821 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 822 // Remove word for return adr already pushed | |
| 823 // and RBP | |
| 824 framesize -= 2*wordSize; | |
| 825 | |
| 826 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here | |
| 827 | |
| 828 if (framesize) { | |
| 829 emit_opcode(cbuf, Assembler::REX_W); | |
| 830 if (framesize < 0x80) { | |
| 831 emit_opcode(cbuf, 0x83); // addq rsp, #framesize | |
| 832 emit_rm(cbuf, 0x3, 0x00, RSP_enc); | |
| 833 emit_d8(cbuf, framesize); | |
| 834 } else { | |
| 835 emit_opcode(cbuf, 0x81); // addq rsp, #framesize | |
| 836 emit_rm(cbuf, 0x3, 0x00, RSP_enc); | |
| 837 emit_d32(cbuf, framesize); | |
| 838 } | |
| 839 } | |
| 840 | |
| 841 // popq rbp | |
| 842 emit_opcode(cbuf, 0x58 | RBP_enc); | |
| 843 | |
| 844 if (do_polling() && C->is_method_compilation()) { | |
|
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|
845 MacroAssembler _masm(&cbuf); |
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846 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type); |
|
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847 if (Assembler::is_polling_page_far()) { |
|
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|
848 __ lea(rscratch1, polling_page); |
|
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|
849 __ relocate(relocInfo::poll_return_type); |
|
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850 __ testl(rax, Address(rscratch1, 0)); |
|
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851 } else { |
|
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|
852 __ testl(rax, polling_page); |
|
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|
853 } |
| 0 | 854 } |
| 855 } | |
| 856 | |
| 857 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const | |
| 858 { | |
|
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|
859 return MachNode::size(ra_); // too many variables; just compute it |
|
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|
860 // the hard way |
| 0 | 861 } |
| 862 | |
| 863 int MachEpilogNode::reloc() const | |
| 864 { | |
| 865 return 2; // a large enough number | |
| 866 } | |
| 867 | |
| 868 const Pipeline* MachEpilogNode::pipeline() const | |
| 869 { | |
| 870 return MachNode::pipeline_class(); | |
| 871 } | |
| 872 | |
| 873 int MachEpilogNode::safepoint_offset() const | |
| 874 { | |
| 875 return 0; | |
| 876 } | |
| 877 | |
| 878 //============================================================================= | |
| 879 | |
| 880 enum RC { | |
| 881 rc_bad, | |
| 882 rc_int, | |
| 883 rc_float, | |
| 884 rc_stack | |
| 885 }; | |
| 886 | |
| 887 static enum RC rc_class(OptoReg::Name reg) | |
| 888 { | |
| 889 if( !OptoReg::is_valid(reg) ) return rc_bad; | |
| 890 | |
| 891 if (OptoReg::is_stack(reg)) return rc_stack; | |
| 892 | |
| 893 VMReg r = OptoReg::as_VMReg(reg); | |
| 894 | |
| 895 if (r->is_Register()) return rc_int; | |
| 896 | |
| 897 assert(r->is_XMMRegister(), "must be"); | |
| 898 return rc_float; | |
| 899 } | |
| 900 | |
|
6179
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7119644: Increase superword's vector size up to 256 bits
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|
901 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad. |
|
8c92982cbbc4
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|
902 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, |
|
8c92982cbbc4
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|
903 int src_hi, int dst_hi, uint ireg, outputStream* st); |
|
8c92982cbbc4
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kvn
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|
904 |
|
8c92982cbbc4
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changeset
|
905 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load, |
|
8c92982cbbc4
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|
906 int stack_offset, int reg, uint ireg, outputStream* st); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
907 |
|
8c92982cbbc4
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|
908 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset, |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
909 int dst_offset, uint ireg, outputStream* st) { |
|
8c92982cbbc4
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|
910 if (cbuf) { |
|
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changeset
|
911 MacroAssembler _masm(cbuf); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
912 switch (ireg) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
913 case Op_VecS: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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parents:
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changeset
|
914 __ movq(Address(rsp, -8), rax); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
915 __ movl(rax, Address(rsp, src_offset)); |
|
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changeset
|
916 __ movl(Address(rsp, dst_offset), rax); |
|
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|
917 __ movq(rax, Address(rsp, -8)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
918 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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changeset
|
919 case Op_VecD: |
|
8c92982cbbc4
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changeset
|
920 __ pushq(Address(rsp, src_offset)); |
|
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|
921 __ popq (Address(rsp, dst_offset)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
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changeset
|
922 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
923 case Op_VecX: |
|
8c92982cbbc4
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|
924 __ pushq(Address(rsp, src_offset)); |
|
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|
925 __ popq (Address(rsp, dst_offset)); |
|
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|
926 __ pushq(Address(rsp, src_offset+8)); |
|
8c92982cbbc4
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|
927 __ popq (Address(rsp, dst_offset+8)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
928 break; |
|
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7119644: Increase superword's vector size up to 256 bits
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|
929 case Op_VecY: |
|
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|
930 __ vmovdqu(Address(rsp, -32), xmm0); |
|
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|
931 __ vmovdqu(xmm0, Address(rsp, src_offset)); |
|
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|
932 __ vmovdqu(Address(rsp, dst_offset), xmm0); |
|
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|
933 __ vmovdqu(xmm0, Address(rsp, -32)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
934 break; |
|
8c92982cbbc4
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|
935 default: |
|
8c92982cbbc4
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|
936 ShouldNotReachHere(); |
|
8c92982cbbc4
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|
937 } |
|
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|
938 #ifndef PRODUCT |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
939 } else { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
940 switch (ireg) { |
|
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7119644: Increase superword's vector size up to 256 bits
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|
941 case Op_VecS: |
|
8c92982cbbc4
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|
942 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t" |
|
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|
943 "movl rax, [rsp + #%d]\n\t" |
|
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|
944 "movl [rsp + #%d], rax\n\t" |
|
8c92982cbbc4
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|
945 "movq rax, [rsp - #8]", |
|
8c92982cbbc4
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|
946 src_offset, dst_offset); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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changeset
|
947 break; |
|
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7119644: Increase superword's vector size up to 256 bits
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changeset
|
948 case Op_VecD: |
|
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|
949 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t" |
|
8c92982cbbc4
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|
950 "popq [rsp + #%d]", |
|
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|
951 src_offset, dst_offset); |
|
8c92982cbbc4
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changeset
|
952 break; |
|
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|
953 case Op_VecX: |
|
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|
954 st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t" |
|
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955 "popq [rsp + #%d]\n\t" |
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956 "pushq [rsp + #%d]\n\t" |
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957 "popq [rsp + #%d]", |
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958 src_offset, dst_offset, src_offset+8, dst_offset+8); |
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959 break; |
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960 case Op_VecY: |
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961 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t" |
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962 "vmovdqu xmm0, [rsp + #%d]\n\t" |
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963 "vmovdqu [rsp + #%d], xmm0\n\t" |
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964 "vmovdqu xmm0, [rsp - #32]", |
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965 src_offset, dst_offset); |
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966 break; |
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967 default: |
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968 ShouldNotReachHere(); |
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969 } |
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970 #endif |
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971 } |
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972 } |
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973 |
| 0 | 974 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf, |
| 975 PhaseRegAlloc* ra_, | |
| 976 bool do_size, | |
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977 outputStream* st) const { |
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978 assert(cbuf != NULL || st != NULL, "sanity"); |
| 0 | 979 // Get registers to move |
| 980 OptoReg::Name src_second = ra_->get_reg_second(in(1)); | |
| 981 OptoReg::Name src_first = ra_->get_reg_first(in(1)); | |
| 982 OptoReg::Name dst_second = ra_->get_reg_second(this); | |
| 983 OptoReg::Name dst_first = ra_->get_reg_first(this); | |
| 984 | |
| 985 enum RC src_second_rc = rc_class(src_second); | |
| 986 enum RC src_first_rc = rc_class(src_first); | |
| 987 enum RC dst_second_rc = rc_class(dst_second); | |
| 988 enum RC dst_first_rc = rc_class(dst_first); | |
| 989 | |
| 990 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), | |
| 991 "must move at least 1 register" ); | |
| 992 | |
| 993 if (src_first == dst_first && src_second == dst_second) { | |
| 994 // Self copy, no move | |
| 995 return 0; | |
|
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996 } |
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997 if (bottom_type()->isa_vect() != NULL) { |
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998 uint ireg = ideal_reg(); |
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999 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity"); |
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1000 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity"); |
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1001 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { |
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1002 // mem -> mem |
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1003 int src_offset = ra_->reg2offset(src_first); |
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1004 int dst_offset = ra_->reg2offset(dst_first); |
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1005 vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st); |
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1006 } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) { |
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1007 vec_mov_helper(cbuf, false, src_first, dst_first, src_second, dst_second, ireg, st); |
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1008 } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) { |
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1009 int stack_offset = ra_->reg2offset(dst_first); |
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1010 vec_spill_helper(cbuf, false, false, stack_offset, src_first, ireg, st); |
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1011 } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) { |
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1012 int stack_offset = ra_->reg2offset(src_first); |
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1013 vec_spill_helper(cbuf, false, true, stack_offset, dst_first, ireg, st); |
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1014 } else { |
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1015 ShouldNotReachHere(); |
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1016 } |
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1017 return 0; |
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1018 } |
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1019 if (src_first_rc == rc_stack) { |
| 0 | 1020 // mem -> |
| 1021 if (dst_first_rc == rc_stack) { | |
| 1022 // mem -> mem | |
| 1023 assert(src_second != dst_first, "overlap"); | |
| 1024 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1025 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1026 // 64-bit | |
| 1027 int src_offset = ra_->reg2offset(src_first); | |
| 1028 int dst_offset = ra_->reg2offset(dst_first); | |
| 1029 if (cbuf) { | |
|
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1030 MacroAssembler _masm(cbuf); |
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1031 __ pushq(Address(rsp, src_offset)); |
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1032 __ popq (Address(rsp, dst_offset)); |
| 0 | 1033 #ifndef PRODUCT |
|
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1034 } else { |
| 0 | 1035 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t" |
|
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1036 "popq [rsp + #%d]", |
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1037 src_offset, dst_offset); |
| 0 | 1038 #endif |
| 1039 } | |
| 1040 } else { | |
| 1041 // 32-bit | |
| 1042 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1043 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1044 // No pushl/popl, so: | |
| 1045 int src_offset = ra_->reg2offset(src_first); | |
| 1046 int dst_offset = ra_->reg2offset(dst_first); | |
| 1047 if (cbuf) { | |
|
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1048 MacroAssembler _masm(cbuf); |
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1049 __ movq(Address(rsp, -8), rax); |
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1050 __ movl(rax, Address(rsp, src_offset)); |
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1051 __ movl(Address(rsp, dst_offset), rax); |
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1052 __ movq(rax, Address(rsp, -8)); |
| 0 | 1053 #ifndef PRODUCT |
|
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1054 } else { |
| 0 | 1055 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t" |
|
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1056 "movl rax, [rsp + #%d]\n\t" |
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1057 "movl [rsp + #%d], rax\n\t" |
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1058 "movq rax, [rsp - #8]", |
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1059 src_offset, dst_offset); |
| 0 | 1060 #endif |
| 1061 } | |
| 1062 } | |
|
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1063 return 0; |
| 0 | 1064 } else if (dst_first_rc == rc_int) { |
| 1065 // mem -> gpr | |
| 1066 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1067 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1068 // 64-bit | |
| 1069 int offset = ra_->reg2offset(src_first); | |
| 1070 if (cbuf) { | |
|
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1071 MacroAssembler _masm(cbuf); |
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1072 __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset)); |
| 0 | 1073 #ifndef PRODUCT |
|
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1074 } else { |
| 0 | 1075 st->print("movq %s, [rsp + #%d]\t# spill", |
| 1076 Matcher::regName[dst_first], | |
| 1077 offset); | |
| 1078 #endif | |
| 1079 } | |
| 1080 } else { | |
| 1081 // 32-bit | |
| 1082 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1083 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1084 int offset = ra_->reg2offset(src_first); | |
| 1085 if (cbuf) { | |
|
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1086 MacroAssembler _masm(cbuf); |
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1087 __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset)); |
| 0 | 1088 #ifndef PRODUCT |
|
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1089 } else { |
| 0 | 1090 st->print("movl %s, [rsp + #%d]\t# spill", |
| 1091 Matcher::regName[dst_first], | |
| 1092 offset); | |
| 1093 #endif | |
| 1094 } | |
| 1095 } | |
|
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1096 return 0; |
| 0 | 1097 } else if (dst_first_rc == rc_float) { |
| 1098 // mem-> xmm | |
| 1099 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1100 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1101 // 64-bit | |
| 1102 int offset = ra_->reg2offset(src_first); | |
| 1103 if (cbuf) { | |
| 4759 | 1104 MacroAssembler _masm(cbuf); |
| 1105 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset)); | |
| 0 | 1106 #ifndef PRODUCT |
|
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1107 } else { |
| 0 | 1108 st->print("%s %s, [rsp + #%d]\t# spill", |
| 1109 UseXmmLoadAndClearUpper ? "movsd " : "movlpd", | |
| 1110 Matcher::regName[dst_first], | |
| 1111 offset); | |
| 1112 #endif | |
| 1113 } | |
| 1114 } else { | |
| 1115 // 32-bit | |
| 1116 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1117 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1118 int offset = ra_->reg2offset(src_first); | |
| 1119 if (cbuf) { | |
| 4759 | 1120 MacroAssembler _masm(cbuf); |
| 1121 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset)); | |
| 0 | 1122 #ifndef PRODUCT |
|
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1123 } else { |
| 0 | 1124 st->print("movss %s, [rsp + #%d]\t# spill", |
| 1125 Matcher::regName[dst_first], | |
| 1126 offset); | |
| 1127 #endif | |
| 1128 } | |
| 1129 } | |
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1130 return 0; |
| 0 | 1131 } |
| 1132 } else if (src_first_rc == rc_int) { | |
| 1133 // gpr -> | |
| 1134 if (dst_first_rc == rc_stack) { | |
| 1135 // gpr -> mem | |
| 1136 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1137 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1138 // 64-bit | |
| 1139 int offset = ra_->reg2offset(dst_first); | |
| 1140 if (cbuf) { | |
|
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1141 MacroAssembler _masm(cbuf); |
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1142 __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first])); |
| 0 | 1143 #ifndef PRODUCT |
|
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1144 } else { |
| 0 | 1145 st->print("movq [rsp + #%d], %s\t# spill", |
| 1146 offset, | |
| 1147 Matcher::regName[src_first]); | |
| 1148 #endif | |
| 1149 } | |
| 1150 } else { | |
| 1151 // 32-bit | |
| 1152 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1153 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1154 int offset = ra_->reg2offset(dst_first); | |
| 1155 if (cbuf) { | |
|
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1156 MacroAssembler _masm(cbuf); |
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1157 __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first])); |
| 0 | 1158 #ifndef PRODUCT |
|
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1159 } else { |
| 0 | 1160 st->print("movl [rsp + #%d], %s\t# spill", |
| 1161 offset, | |
| 1162 Matcher::regName[src_first]); | |
| 1163 #endif | |
| 1164 } | |
| 1165 } | |
|
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1166 return 0; |
| 0 | 1167 } else if (dst_first_rc == rc_int) { |
| 1168 // gpr -> gpr | |
| 1169 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1170 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1171 // 64-bit | |
| 1172 if (cbuf) { | |
|
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1173 MacroAssembler _masm(cbuf); |
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1174 __ movq(as_Register(Matcher::_regEncode[dst_first]), |
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1175 as_Register(Matcher::_regEncode[src_first])); |
| 0 | 1176 #ifndef PRODUCT |
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1177 } else { |
| 0 | 1178 st->print("movq %s, %s\t# spill", |
| 1179 Matcher::regName[dst_first], | |
| 1180 Matcher::regName[src_first]); | |
| 1181 #endif | |
| 1182 } | |
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1183 return 0; |
| 0 | 1184 } else { |
| 1185 // 32-bit | |
| 1186 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1187 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1188 if (cbuf) { | |
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1189 MacroAssembler _masm(cbuf); |
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1190 __ movl(as_Register(Matcher::_regEncode[dst_first]), |
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1191 as_Register(Matcher::_regEncode[src_first])); |
| 0 | 1192 #ifndef PRODUCT |
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1193 } else { |
| 0 | 1194 st->print("movl %s, %s\t# spill", |
| 1195 Matcher::regName[dst_first], | |
| 1196 Matcher::regName[src_first]); | |
| 1197 #endif | |
| 1198 } | |
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1199 return 0; |
| 0 | 1200 } |
| 1201 } else if (dst_first_rc == rc_float) { | |
| 1202 // gpr -> xmm | |
| 1203 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1204 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1205 // 64-bit | |
| 1206 if (cbuf) { | |
| 4759 | 1207 MacroAssembler _masm(cbuf); |
| 1208 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first])); | |
| 0 | 1209 #ifndef PRODUCT |
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1210 } else { |
| 0 | 1211 st->print("movdq %s, %s\t# spill", |
| 1212 Matcher::regName[dst_first], | |
| 1213 Matcher::regName[src_first]); | |
| 1214 #endif | |
| 1215 } | |
| 1216 } else { | |
| 1217 // 32-bit | |
| 1218 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1219 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1220 if (cbuf) { | |
| 4759 | 1221 MacroAssembler _masm(cbuf); |
| 1222 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first])); | |
| 0 | 1223 #ifndef PRODUCT |
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1224 } else { |
| 0 | 1225 st->print("movdl %s, %s\t# spill", |
| 1226 Matcher::regName[dst_first], | |
| 1227 Matcher::regName[src_first]); | |
| 1228 #endif | |
| 1229 } | |
| 1230 } | |
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1231 return 0; |
| 0 | 1232 } |
| 1233 } else if (src_first_rc == rc_float) { | |
| 1234 // xmm -> | |
| 1235 if (dst_first_rc == rc_stack) { | |
| 1236 // xmm -> mem | |
| 1237 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1238 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1239 // 64-bit | |
| 1240 int offset = ra_->reg2offset(dst_first); | |
| 1241 if (cbuf) { | |
| 4759 | 1242 MacroAssembler _masm(cbuf); |
| 1243 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first])); | |
| 0 | 1244 #ifndef PRODUCT |
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1245 } else { |
| 0 | 1246 st->print("movsd [rsp + #%d], %s\t# spill", |
| 1247 offset, | |
| 1248 Matcher::regName[src_first]); | |
| 1249 #endif | |
| 1250 } | |
| 1251 } else { | |
| 1252 // 32-bit | |
| 1253 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1254 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1255 int offset = ra_->reg2offset(dst_first); | |
| 1256 if (cbuf) { | |
| 4759 | 1257 MacroAssembler _masm(cbuf); |
| 1258 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first])); | |
| 0 | 1259 #ifndef PRODUCT |
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1260 } else { |
| 0 | 1261 st->print("movss [rsp + #%d], %s\t# spill", |
| 1262 offset, | |
| 1263 Matcher::regName[src_first]); | |
| 1264 #endif | |
| 1265 } | |
| 1266 } | |
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1267 return 0; |
| 0 | 1268 } else if (dst_first_rc == rc_int) { |
| 1269 // xmm -> gpr | |
| 1270 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1271 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1272 // 64-bit | |
| 1273 if (cbuf) { | |
| 4759 | 1274 MacroAssembler _masm(cbuf); |
| 1275 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first])); | |
| 0 | 1276 #ifndef PRODUCT |
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1277 } else { |
| 0 | 1278 st->print("movdq %s, %s\t# spill", |
| 1279 Matcher::regName[dst_first], | |
| 1280 Matcher::regName[src_first]); | |
| 1281 #endif | |
| 1282 } | |
| 1283 } else { | |
| 1284 // 32-bit | |
| 1285 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1286 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1287 if (cbuf) { | |
| 4759 | 1288 MacroAssembler _masm(cbuf); |
| 1289 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first])); | |
| 0 | 1290 #ifndef PRODUCT |
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1291 } else { |
| 0 | 1292 st->print("movdl %s, %s\t# spill", |
| 1293 Matcher::regName[dst_first], | |
| 1294 Matcher::regName[src_first]); | |
| 1295 #endif | |
| 1296 } | |
| 1297 } | |
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1298 return 0; |
| 0 | 1299 } else if (dst_first_rc == rc_float) { |
| 1300 // xmm -> xmm | |
| 1301 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1302 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1303 // 64-bit | |
| 1304 if (cbuf) { | |
| 4759 | 1305 MacroAssembler _masm(cbuf); |
| 1306 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first])); | |
| 0 | 1307 #ifndef PRODUCT |
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1308 } else { |
| 0 | 1309 st->print("%s %s, %s\t# spill", |
| 1310 UseXmmRegToRegMoveAll ? "movapd" : "movsd ", | |
| 1311 Matcher::regName[dst_first], | |
| 1312 Matcher::regName[src_first]); | |
| 1313 #endif | |
| 1314 } | |
| 1315 } else { | |
| 1316 // 32-bit | |
| 1317 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1318 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1319 if (cbuf) { | |
| 4759 | 1320 MacroAssembler _masm(cbuf); |
| 1321 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first])); | |
| 0 | 1322 #ifndef PRODUCT |
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1323 } else { |
| 0 | 1324 st->print("%s %s, %s\t# spill", |
| 1325 UseXmmRegToRegMoveAll ? "movaps" : "movss ", | |
| 1326 Matcher::regName[dst_first], | |
| 1327 Matcher::regName[src_first]); | |
| 1328 #endif | |
| 1329 } | |
| 1330 } | |
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1331 return 0; |
| 0 | 1332 } |
| 1333 } | |
| 1334 | |
| 1335 assert(0," foo "); | |
| 1336 Unimplemented(); | |
| 1337 return 0; | |
| 1338 } | |
| 1339 | |
| 1340 #ifndef PRODUCT | |
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1341 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const { |
| 0 | 1342 implementation(NULL, ra_, false, st); |
| 1343 } | |
| 1344 #endif | |
| 1345 | |
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1346 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { |
| 0 | 1347 implementation(&cbuf, ra_, false, NULL); |
| 1348 } | |
| 1349 | |
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1350 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { |
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1351 return MachNode::size(ra_); |
| 0 | 1352 } |
| 1353 | |
| 1354 //============================================================================= | |
| 1355 #ifndef PRODUCT | |
| 1356 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const | |
| 1357 { | |
| 1358 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1359 int reg = ra_->get_reg_first(this); | |
| 1360 st->print("leaq %s, [rsp + #%d]\t# box lock", | |
| 1361 Matcher::regName[reg], offset); | |
| 1362 } | |
| 1363 #endif | |
| 1364 | |
| 1365 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const | |
| 1366 { | |
| 1367 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1368 int reg = ra_->get_encode(this); | |
| 1369 if (offset >= 0x80) { | |
| 1370 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR); | |
| 1371 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1372 emit_rm(cbuf, 0x2, reg & 7, 0x04); | |
| 1373 emit_rm(cbuf, 0x0, 0x04, RSP_enc); | |
| 1374 emit_d32(cbuf, offset); | |
| 1375 } else { | |
| 1376 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR); | |
| 1377 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1378 emit_rm(cbuf, 0x1, reg & 7, 0x04); | |
| 1379 emit_rm(cbuf, 0x0, 0x04, RSP_enc); | |
| 1380 emit_d8(cbuf, offset); | |
| 1381 } | |
| 1382 } | |
| 1383 | |
| 1384 uint BoxLockNode::size(PhaseRegAlloc *ra_) const | |
| 1385 { | |
| 1386 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1387 return (offset < 0x80) ? 5 : 8; // REX | |
| 1388 } | |
| 1389 | |
| 1390 //============================================================================= | |
| 1391 #ifndef PRODUCT | |
| 1392 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const | |
| 1393 { | |
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1394 if (UseCompressedClassPointers) { |
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1395 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass"); |
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1396 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1"); |
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1397 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check"); |
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1398 } else { |
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1399 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t" |
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1400 "# Inline cache check"); |
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1401 } |
| 0 | 1402 st->print_cr("\tjne SharedRuntime::_ic_miss_stub"); |
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1403 st->print_cr("\tnop\t# nops to align entry point"); |
| 0 | 1404 } |
| 1405 #endif | |
| 1406 | |
| 1407 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const | |
| 1408 { | |
| 1409 MacroAssembler masm(&cbuf); | |
| 1748 | 1410 uint insts_size = cbuf.insts_size(); |
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1411 if (UseCompressedClassPointers) { |
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1412 masm.load_klass(rscratch1, j_rarg0); |
| 304 | 1413 masm.cmpptr(rax, rscratch1); |
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1414 } else { |
| 304 | 1415 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes())); |
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1416 } |
| 0 | 1417 |
| 1418 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub())); | |
| 1419 | |
| 1420 /* WARNING these NOPs are critical so that verified entry point is properly | |
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1421 4 bytes aligned for patching by NativeJump::patch_verified_entry() */ |
| 1748 | 1422 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3); |
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1423 if (OptoBreakpoint) { |
| 0 | 1424 // Leave space for int3 |
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1425 nops_cnt -= 1; |
| 0 | 1426 } |
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1427 nops_cnt &= 0x3; // Do not add nops if code is aligned. |
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1428 if (nops_cnt > 0) |
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1429 masm.nop(nops_cnt); |
| 0 | 1430 } |
| 1431 | |
| 1432 uint MachUEPNode::size(PhaseRegAlloc* ra_) const | |
| 1433 { | |
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1434 return MachNode::size(ra_); // too many variables; just compute it |
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1435 // the hard way |
| 0 | 1436 } |
| 1437 | |
| 1438 | |
| 1439 //============================================================================= | |
| 1440 uint size_exception_handler() | |
| 1441 { | |
| 1442 // NativeCall instruction size is the same as NativeJump. | |
| 1443 // Note that this value is also credited (in output.cpp) to | |
| 1444 // the size of the code section. | |
| 1445 return NativeJump::instruction_size; | |
| 1446 } | |
| 1447 | |
| 1448 // Emit exception handler code. | |
| 1449 int emit_exception_handler(CodeBuffer& cbuf) | |
| 1450 { | |
| 1451 | |
| 1748 | 1452 // Note that the code buffer's insts_mark is always relative to insts. |
| 0 | 1453 // That's why we must use the macroassembler to generate a handler. |
| 1454 MacroAssembler _masm(&cbuf); | |
| 1455 address base = | |
| 1456 __ start_a_stub(size_exception_handler()); | |
| 1457 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1458 int offset = __ offset(); | |
| 1748 | 1459 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point())); |
| 0 | 1460 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); |
| 1461 __ end_a_stub(); | |
| 1462 return offset; | |
| 1463 } | |
| 1464 | |
| 1465 uint size_deopt_handler() | |
| 1466 { | |
| 1467 // three 5 byte instructions | |
| 1468 return 15; | |
| 1469 } | |
| 1470 | |
| 1471 // Emit deopt handler code. | |
| 1472 int emit_deopt_handler(CodeBuffer& cbuf) | |
| 1473 { | |
| 1474 | |
| 1748 | 1475 // Note that the code buffer's insts_mark is always relative to insts. |
| 0 | 1476 // That's why we must use the macroassembler to generate a handler. |
| 1477 MacroAssembler _masm(&cbuf); | |
| 1478 address base = | |
| 1479 __ start_a_stub(size_deopt_handler()); | |
| 1480 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1481 int offset = __ offset(); | |
| 1482 address the_pc = (address) __ pc(); | |
| 1483 Label next; | |
| 1484 // push a "the_pc" on the stack without destroying any registers | |
| 1485 // as they all may be live. | |
| 1486 | |
| 1487 // push address of "next" | |
| 1488 __ call(next, relocInfo::none); // reloc none is fine since it is a disp32 | |
| 1489 __ bind(next); | |
| 1490 // adjust it so it matches "the_pc" | |
| 304 | 1491 __ subptr(Address(rsp, 0), __ offset() - offset); |
| 0 | 1492 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); |
| 1493 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); | |
| 1494 __ end_a_stub(); | |
| 1495 return offset; | |
| 1496 } | |
| 1497 | |
| 1498 int Matcher::regnum_to_fpu_offset(int regnum) | |
| 1499 { | |
| 1500 return regnum - 32; // The FP registers are in the second chunk | |
| 1501 } | |
| 1502 | |
| 1503 // This is UltraSparc specific, true just means we have fast l2f conversion | |
| 1504 const bool Matcher::convL2FSupported(void) { | |
| 1505 return true; | |
| 1506 } | |
| 1507 | |
| 1508 // Is this branch offset short enough that a short branch can be used? | |
| 1509 // | |
| 1510 // NOTE: If the platform does not provide any short branch variants, then | |
| 1511 // this method should return false for offset 0. | |
| 3851 | 1512 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { |
| 1513 // The passed offset is relative to address of the branch. | |
| 1514 // On 86 a branch displacement is calculated relative to address | |
| 1515 // of a next instruction. | |
| 1516 offset -= br_size; | |
| 1517 | |
|
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|
1518 // the short version of jmpConUCF2 contains multiple branches, |
|
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|
1519 // making the reach slightly less |
|
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|
1520 if (rule == jmpConUCF2_rule) |
|
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|
1521 return (-126 <= offset && offset <= 125); |
|
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|
1522 return (-128 <= offset && offset <= 127); |
| 0 | 1523 } |
| 1524 | |
| 1525 const bool Matcher::isSimpleConstant64(jlong value) { | |
| 1526 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. | |
| 1527 //return value == (int) value; // Cf. storeImmL and immL32. | |
| 1528 | |
| 1529 // Probably always true, even if a temp register is required. | |
| 1530 return true; | |
| 1531 } | |
| 1532 | |
| 1533 // The ecx parameter to rep stosq for the ClearArray node is in words. | |
| 1534 const bool Matcher::init_array_count_is_in_bytes = false; | |
| 1535 | |
| 1536 // Threshold size for cleararray. | |
| 1537 const int Matcher::init_array_short_size = 8 * BytesPerLong; | |
| 1538 | |
| 4047 | 1539 // No additional cost for CMOVL. |
| 1540 const int Matcher::long_cmove_cost() { return 0; } | |
| 1541 | |
| 1542 // No CMOVF/CMOVD with SSE2 | |
| 1543 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; } | |
| 1544 | |
| 0 | 1545 // Should the Matcher clone shifts on addressing modes, expecting them |
| 1546 // to be subsumed into complex addressing expressions or compute them | |
| 1547 // into registers? True for Intel but false for most RISCs | |
| 1548 const bool Matcher::clone_shift_expressions = true; | |
| 1549 | |
|
2401
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|
1550 // Do we need to mask the count passed to shift instructions or does |
|
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|
1551 // the cpu only look at the lower 5/6 bits anyway? |
|
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|
1552 const bool Matcher::need_masked_shift_count = false; |
|
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|
1553 |
|
1575
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|
1554 bool Matcher::narrow_oop_use_complex_address() { |
|
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|
1555 assert(UseCompressedOops, "only for compressed oops code"); |
|
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|
1556 return (LogMinObjAlignmentInBytes <= 3); |
|
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|
1557 } |
|
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|
1558 |
|
6848
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|
1559 bool Matcher::narrow_klass_use_complex_address() { |
|
12226
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|
1560 assert(UseCompressedClassPointers, "only for compressed klass code"); |
|
6848
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|
1561 return (LogKlassAlignmentInBytes <= 3); |
|
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|
1562 } |
|
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|
1563 |
| 0 | 1564 // Is it better to copy float constants, or load them directly from |
| 1565 // memory? Intel can load a float constant from a direct address, | |
| 1566 // requiring no extra registers. Most RISCs will have to materialize | |
| 1567 // an address into a register first, so they would do better to copy | |
| 1568 // the constant from stack. | |
| 1569 const bool Matcher::rematerialize_float_constants = true; // XXX | |
| 1570 | |
| 1571 // If CPU can load and store mis-aligned doubles directly then no | |
| 1572 // fixup is needed. Else we split the double into 2 integer pieces | |
| 1573 // and move it piece-by-piece. Only happens when passing doubles into | |
| 1574 // C code as the Java calling convention forces doubles to be aligned. | |
| 1575 const bool Matcher::misaligned_doubles_ok = true; | |
| 1576 | |
| 1577 // No-op on amd64 | |
| 1578 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {} | |
| 1579 | |
| 1580 // Advertise here if the CPU requires explicit rounding operations to | |
| 1581 // implement the UseStrictFP mode. | |
| 1582 const bool Matcher::strict_fp_requires_explicit_rounding = true; | |
| 1583 | |
|
1274
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|
1584 // Are floats conerted to double when stored to stack during deoptimization? |
|
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|
1585 // On x64 it is stored without convertion so we can use normal access. |
|
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|
1586 bool Matcher::float_in_double() { return false; } |
|
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|
1587 |
| 0 | 1588 // Do ints take an entire long register or just half? |
| 1589 const bool Matcher::int_in_long = true; | |
| 1590 | |
| 1591 // Return whether or not this register is ever used as an argument. | |
| 1592 // This function is used on startup to build the trampoline stubs in | |
| 1593 // generateOptoStub. Registers not mentioned will be killed by the VM | |
| 1594 // call in the trampoline, and arguments in those registers not be | |
| 1595 // available to the callee. | |
| 1596 bool Matcher::can_be_java_arg(int reg) | |
| 1597 { | |
| 1598 return | |
|
6179
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|
1599 reg == RDI_num || reg == RDI_H_num || |
|
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|
1600 reg == RSI_num || reg == RSI_H_num || |
|
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|
1601 reg == RDX_num || reg == RDX_H_num || |
|
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|
1602 reg == RCX_num || reg == RCX_H_num || |
|
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|
1603 reg == R8_num || reg == R8_H_num || |
|
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|
1604 reg == R9_num || reg == R9_H_num || |
|
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|
1605 reg == R12_num || reg == R12_H_num || |
|
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|
1606 reg == XMM0_num || reg == XMM0b_num || |
|
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|
1607 reg == XMM1_num || reg == XMM1b_num || |
|
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|
1608 reg == XMM2_num || reg == XMM2b_num || |
|
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|
1609 reg == XMM3_num || reg == XMM3b_num || |
|
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|
1610 reg == XMM4_num || reg == XMM4b_num || |
|
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|
1611 reg == XMM5_num || reg == XMM5b_num || |
|
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|
1612 reg == XMM6_num || reg == XMM6b_num || |
|
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|
1613 reg == XMM7_num || reg == XMM7b_num; |
| 0 | 1614 } |
| 1615 | |
| 1616 bool Matcher::is_spillable_arg(int reg) | |
| 1617 { | |
| 1618 return can_be_java_arg(reg); | |
| 1619 } | |
| 1620 | |
|
1914
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diff
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|
1621 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) { |
|
ae065c367d93
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diff
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|
1622 // In 64 bit mode a code which use multiply when |
|
ae065c367d93
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diff
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|
1623 // devisor is constant is faster than hardware |
|
ae065c367d93
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1827
diff
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|
1624 // DIV instruction (it uses MulHiL). |
|
ae065c367d93
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|
1625 return false; |
|
ae065c367d93
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1827
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|
1626 } |
|
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|
1627 |
| 0 | 1628 // Register for DIVI projection of divmodI |
| 1629 RegMask Matcher::divI_proj_mask() { | |
|
4121
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|
1630 return INT_RAX_REG_mask(); |
| 0 | 1631 } |
| 1632 | |
| 1633 // Register for MODI projection of divmodI | |
| 1634 RegMask Matcher::modI_proj_mask() { | |
|
4121
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|
1635 return INT_RDX_REG_mask(); |
| 0 | 1636 } |
| 1637 | |
| 1638 // Register for DIVL projection of divmodL | |
| 1639 RegMask Matcher::divL_proj_mask() { | |
|
4121
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|
1640 return LONG_RAX_REG_mask(); |
| 0 | 1641 } |
| 1642 | |
| 1643 // Register for MODL projection of divmodL | |
| 1644 RegMask Matcher::modL_proj_mask() { | |
|
4121
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|
1645 return LONG_RDX_REG_mask(); |
| 0 | 1646 } |
| 1647 | |
|
1137
97125851f396
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|
1648 const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
|
4121
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|
1649 return PTR_RBP_REG_mask(); |
|
1137
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|
1650 } |
|
97125851f396
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diff
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|
1651 |
| 0 | 1652 %} |
| 1653 | |
| 1654 //----------ENCODING BLOCK----------------------------------------------------- | |
| 1655 // This block specifies the encoding classes used by the compiler to | |
| 1656 // output byte streams. Encoding classes are parameterized macros | |
| 1657 // used by Machine Instruction Nodes in order to generate the bit | |
| 1658 // encoding of the instruction. Operands specify their base encoding | |
| 1659 // interface with the interface keyword. There are currently | |
| 1660 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, & | |
| 1661 // COND_INTER. REG_INTER causes an operand to generate a function | |
| 1662 // which returns its register number when queried. CONST_INTER causes | |
| 1663 // an operand to generate a function which returns the value of the | |
| 1664 // constant when queried. MEMORY_INTER causes an operand to generate | |
| 1665 // four functions which return the Base Register, the Index Register, | |
| 1666 // the Scale Value, and the Offset Value of the operand when queried. | |
| 1667 // COND_INTER causes an operand to generate six functions which return | |
| 1668 // the encoding code (ie - encoding bits for the instruction) | |
| 1669 // associated with each basic boolean condition for a conditional | |
| 1670 // instruction. | |
| 1671 // | |
| 1672 // Instructions specify two basic values for encoding. Again, a | |
| 1673 // function is available to check if the constant displacement is an | |
| 1674 // oop. They use the ins_encode keyword to specify their encoding | |
| 1675 // classes (which must be a sequence of enc_class names, and their | |
| 1676 // parameters, specified in the encoding block), and they use the | |
| 1677 // opcode keyword to specify, in order, their primary, secondary, and | |
| 1678 // tertiary opcode. Only the opcode sections which a particular | |
| 1679 // instruction needs for encoding need to be specified. | |
| 1680 encode %{ | |
| 1681 // Build emit functions for each basic byte or larger field in the | |
| 1682 // intel encoding scheme (opcode, rm, sib, immediate), and call them | |
| 1683 // from C++ code in the enc_class source block. Emit functions will | |
| 1684 // live in the main source block for now. In future, we can | |
| 1685 // generalize this by adding a syntax that specifies the sizes of | |
| 1686 // fields in an order, so that the adlc can build the emit functions | |
| 1687 // automagically | |
| 1688 | |
| 1689 // Emit primary opcode | |
| 1690 enc_class OpcP | |
| 1691 %{ | |
| 1692 emit_opcode(cbuf, $primary); | |
| 1693 %} | |
| 1694 | |
| 1695 // Emit secondary opcode | |
| 1696 enc_class OpcS | |
| 1697 %{ | |
| 1698 emit_opcode(cbuf, $secondary); | |
| 1699 %} | |
| 1700 | |
| 1701 // Emit tertiary opcode | |
| 1702 enc_class OpcT | |
| 1703 %{ | |
| 1704 emit_opcode(cbuf, $tertiary); | |
| 1705 %} | |
| 1706 | |
| 1707 // Emit opcode directly | |
| 1708 enc_class Opcode(immI d8) | |
| 1709 %{ | |
| 1710 emit_opcode(cbuf, $d8$$constant); | |
| 1711 %} | |
| 1712 | |
| 1713 // Emit size prefix | |
| 1714 enc_class SizePrefix | |
| 1715 %{ | |
| 1716 emit_opcode(cbuf, 0x66); | |
| 1717 %} | |
| 1718 | |
| 1719 enc_class reg(rRegI reg) | |
| 1720 %{ | |
| 1721 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7); | |
| 1722 %} | |
| 1723 | |
| 1724 enc_class reg_reg(rRegI dst, rRegI src) | |
| 1725 %{ | |
| 1726 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7); | |
| 1727 %} | |
| 1728 | |
| 1729 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src) | |
| 1730 %{ | |
| 1731 emit_opcode(cbuf, $opcode$$constant); | |
| 1732 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7); | |
| 1733 %} | |
| 1734 | |
| 1735 enc_class cdql_enc(no_rax_rdx_RegI div) | |
| 1736 %{ | |
| 1737 // Full implementation of Java idiv and irem; checks for | |
| 1738 // special case as described in JVM spec., p.243 & p.271. | |
| 1739 // | |
| 1740 // normal case special case | |
| 1741 // | |
| 1742 // input : rax: dividend min_int | |
| 1743 // reg: divisor -1 | |
| 1744 // | |
| 1745 // output: rax: quotient (= rax idiv reg) min_int | |
| 1746 // rdx: remainder (= rax irem reg) 0 | |
| 1747 // | |
| 1748 // Code sequnce: | |
| 1749 // | |
| 1750 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax | |
| 1751 // 5: 75 07/08 jne e <normal> | |
| 1752 // 7: 33 d2 xor %edx,%edx | |
| 1753 // [div >= 8 -> offset + 1] | |
| 1754 // [REX_B] | |
| 1755 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div | |
| 1756 // c: 74 03/04 je 11 <done> | |
| 1757 // 000000000000000e <normal>: | |
| 1758 // e: 99 cltd | |
| 1759 // [div >= 8 -> offset + 1] | |
| 1760 // [REX_B] | |
| 1761 // f: f7 f9 idiv $div | |
| 1762 // 0000000000000011 <done>: | |
| 1763 | |
| 1764 // cmp $0x80000000,%eax | |
| 1765 emit_opcode(cbuf, 0x3d); | |
| 1766 emit_d8(cbuf, 0x00); | |
| 1767 emit_d8(cbuf, 0x00); | |
| 1768 emit_d8(cbuf, 0x00); | |
| 1769 emit_d8(cbuf, 0x80); | |
| 1770 | |
| 1771 // jne e <normal> | |
| 1772 emit_opcode(cbuf, 0x75); | |
| 1773 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08); | |
| 1774 | |
| 1775 // xor %edx,%edx | |
| 1776 emit_opcode(cbuf, 0x33); | |
| 1777 emit_d8(cbuf, 0xD2); | |
| 1778 | |
| 1779 // cmp $0xffffffffffffffff,%ecx | |
| 1780 if ($div$$reg >= 8) { | |
| 1781 emit_opcode(cbuf, Assembler::REX_B); | |
| 1782 } | |
| 1783 emit_opcode(cbuf, 0x83); | |
| 1784 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7); | |
| 1785 emit_d8(cbuf, 0xFF); | |
| 1786 | |
| 1787 // je 11 <done> | |
| 1788 emit_opcode(cbuf, 0x74); | |
| 1789 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04); | |
| 1790 | |
| 1791 // <normal> | |
| 1792 // cltd | |
| 1793 emit_opcode(cbuf, 0x99); | |
| 1794 | |
| 1795 // idivl (note: must be emitted by the user of this rule) | |
| 1796 // <done> | |
| 1797 %} | |
| 1798 | |
| 1799 enc_class cdqq_enc(no_rax_rdx_RegL div) | |
| 1800 %{ | |
| 1801 // Full implementation of Java ldiv and lrem; checks for | |
| 1802 // special case as described in JVM spec., p.243 & p.271. | |
| 1803 // | |
| 1804 // normal case special case | |
| 1805 // | |
| 1806 // input : rax: dividend min_long | |
| 1807 // reg: divisor -1 | |
| 1808 // | |
| 1809 // output: rax: quotient (= rax idiv reg) min_long | |
| 1810 // rdx: remainder (= rax irem reg) 0 | |
| 1811 // | |
| 1812 // Code sequnce: | |
| 1813 // | |
| 1814 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx | |
| 1815 // 7: 00 00 80 | |
| 1816 // a: 48 39 d0 cmp %rdx,%rax | |
| 1817 // d: 75 08 jne 17 <normal> | |
| 1818 // f: 33 d2 xor %edx,%edx | |
| 1819 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div | |
| 1820 // 15: 74 05 je 1c <done> | |
| 1821 // 0000000000000017 <normal>: | |
| 1822 // 17: 48 99 cqto | |
| 1823 // 19: 48 f7 f9 idiv $div | |
| 1824 // 000000000000001c <done>: | |
| 1825 | |
| 1826 // mov $0x8000000000000000,%rdx | |
| 1827 emit_opcode(cbuf, Assembler::REX_W); | |
| 1828 emit_opcode(cbuf, 0xBA); | |
| 1829 emit_d8(cbuf, 0x00); | |
| 1830 emit_d8(cbuf, 0x00); | |
| 1831 emit_d8(cbuf, 0x00); | |
| 1832 emit_d8(cbuf, 0x00); | |
| 1833 emit_d8(cbuf, 0x00); | |
| 1834 emit_d8(cbuf, 0x00); | |
| 1835 emit_d8(cbuf, 0x00); | |
| 1836 emit_d8(cbuf, 0x80); | |
| 1837 | |
| 1838 // cmp %rdx,%rax | |
| 1839 emit_opcode(cbuf, Assembler::REX_W); | |
| 1840 emit_opcode(cbuf, 0x39); | |
| 1841 emit_d8(cbuf, 0xD0); | |
| 1842 | |
| 1843 // jne 17 <normal> | |
| 1844 emit_opcode(cbuf, 0x75); | |
| 1845 emit_d8(cbuf, 0x08); | |
| 1846 | |
| 1847 // xor %edx,%edx | |
| 1848 emit_opcode(cbuf, 0x33); | |
| 1849 emit_d8(cbuf, 0xD2); | |
| 1850 | |
| 1851 // cmp $0xffffffffffffffff,$div | |
| 1852 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB); | |
| 1853 emit_opcode(cbuf, 0x83); | |
| 1854 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7); | |
| 1855 emit_d8(cbuf, 0xFF); | |
| 1856 | |
| 1857 // je 1e <done> | |
| 1858 emit_opcode(cbuf, 0x74); | |
| 1859 emit_d8(cbuf, 0x05); | |
| 1860 | |
| 1861 // <normal> | |
| 1862 // cqto | |
| 1863 emit_opcode(cbuf, Assembler::REX_W); | |
| 1864 emit_opcode(cbuf, 0x99); | |
| 1865 | |
| 1866 // idivq (note: must be emitted by the user of this rule) | |
| 1867 // <done> | |
| 1868 %} | |
| 1869 | |
| 1870 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension | |
| 1871 enc_class OpcSE(immI imm) | |
| 1872 %{ | |
| 1873 // Emit primary opcode and set sign-extend bit | |
| 1874 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1875 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
| 1876 emit_opcode(cbuf, $primary | 0x02); | |
| 1877 } else { | |
| 1878 // 32-bit immediate | |
| 1879 emit_opcode(cbuf, $primary); | |
| 1880 } | |
| 1881 %} | |
| 1882 | |
| 1883 enc_class OpcSErm(rRegI dst, immI imm) | |
| 1884 %{ | |
| 1885 // OpcSEr/m | |
| 1886 int dstenc = $dst$$reg; | |
| 1887 if (dstenc >= 8) { | |
| 1888 emit_opcode(cbuf, Assembler::REX_B); | |
| 1889 dstenc -= 8; | |
| 1890 } | |
| 1891 // Emit primary opcode and set sign-extend bit | |
| 1892 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1893 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
| 1894 emit_opcode(cbuf, $primary | 0x02); | |
| 1895 } else { | |
| 1896 // 32-bit immediate | |
| 1897 emit_opcode(cbuf, $primary); | |
| 1898 } | |
| 1899 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 1900 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
| 1901 %} | |
| 1902 | |
| 1903 enc_class OpcSErm_wide(rRegL dst, immI imm) | |
| 1904 %{ | |
| 1905 // OpcSEr/m | |
| 1906 int dstenc = $dst$$reg; | |
| 1907 if (dstenc < 8) { | |
| 1908 emit_opcode(cbuf, Assembler::REX_W); | |
| 1909 } else { | |
| 1910 emit_opcode(cbuf, Assembler::REX_WB); | |
| 1911 dstenc -= 8; | |
| 1912 } | |
| 1913 // Emit primary opcode and set sign-extend bit | |
| 1914 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1915 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
| 1916 emit_opcode(cbuf, $primary | 0x02); | |
| 1917 } else { | |
| 1918 // 32-bit immediate | |
| 1919 emit_opcode(cbuf, $primary); | |
| 1920 } | |
| 1921 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 1922 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
| 1923 %} | |
| 1924 | |
| 1925 enc_class Con8or32(immI imm) | |
| 1926 %{ | |
| 1927 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1928 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
| 1929 $$$emit8$imm$$constant; | |
| 1930 } else { | |
| 1931 // 32-bit immediate | |
| 1932 $$$emit32$imm$$constant; | |
| 1933 } | |
| 1934 %} | |
| 1935 | |
| 1936 enc_class opc2_reg(rRegI dst) | |
| 1937 %{ | |
| 1938 // BSWAP | |
| 1939 emit_cc(cbuf, $secondary, $dst$$reg); | |
| 1940 %} | |
| 1941 | |
| 1942 enc_class opc3_reg(rRegI dst) | |
| 1943 %{ | |
| 1944 // BSWAP | |
| 1945 emit_cc(cbuf, $tertiary, $dst$$reg); | |
| 1946 %} | |
| 1947 | |
| 1948 enc_class reg_opc(rRegI div) | |
| 1949 %{ | |
| 1950 // INC, DEC, IDIV, IMOD, JMP indirect, ... | |
| 1951 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7); | |
| 1952 %} | |
| 1953 | |
| 1954 enc_class enc_cmov(cmpOp cop) | |
| 1955 %{ | |
| 1956 // CMOV | |
| 1957 $$$emit8$primary; | |
| 1958 emit_cc(cbuf, $secondary, $cop$$cmpcode); | |
| 1959 %} | |
| 1960 | |
| 1961 enc_class enc_PartialSubtypeCheck() | |
| 1962 %{ | |
| 1963 Register Rrdi = as_Register(RDI_enc); // result register | |
| 1964 Register Rrax = as_Register(RAX_enc); // super class | |
| 1965 Register Rrcx = as_Register(RCX_enc); // killed | |
| 1966 Register Rrsi = as_Register(RSI_enc); // sub class | |
|
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1967 Label miss; |
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1968 const bool set_cond_codes = true; |
| 0 | 1969 |
| 1970 MacroAssembler _masm(&cbuf); | |
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1971 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi, |
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1972 NULL, &miss, |
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1973 /*set_cond_codes:*/ true); |
| 0 | 1974 if ($primary) { |
| 304 | 1975 __ xorptr(Rrdi, Rrdi); |
| 0 | 1976 } |
| 1977 __ bind(miss); | |
| 1978 %} | |
| 1979 | |
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1980 enc_class clear_avx %{ |
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1981 debug_only(int off0 = cbuf.insts_size()); |
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1982 if (ra_->C->max_vector_size() > 16) { |
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1983 // Clear upper bits of YMM registers when current compiled code uses |
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1984 // wide vectors to avoid AVX <-> SSE transition penalty during call. |
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1985 MacroAssembler _masm(&cbuf); |
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1986 __ vzeroupper(); |
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1987 } |
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1988 debug_only(int off1 = cbuf.insts_size()); |
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1989 assert(off1 - off0 == clear_avx_size(), "correct size prediction"); |
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1990 %} |
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1991 |
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1992 enc_class Java_To_Runtime(method meth) %{ |
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1993 // No relocation needed |
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1994 MacroAssembler _masm(&cbuf); |
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1995 __ mov64(r10, (int64_t) $meth$$method); |
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1996 __ call(r10); |
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1997 %} |
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1998 |
| 0 | 1999 enc_class Java_To_Interpreter(method meth) |
| 2000 %{ | |
| 2001 // CALL Java_To_Interpreter | |
| 2002 // This is the instruction starting address for relocation info. | |
| 1748 | 2003 cbuf.set_insts_mark(); |
| 0 | 2004 $$$emit8$primary; |
| 2005 // CALL directly to the runtime | |
| 2006 emit_d32_reloc(cbuf, | |
| 1748 | 2007 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4), |
| 0 | 2008 runtime_call_Relocation::spec(), |
| 2009 RELOC_DISP32); | |
| 2010 %} | |
| 2011 | |
| 2012 enc_class Java_Static_Call(method meth) | |
| 2013 %{ | |
| 2014 // JAVA STATIC CALL | |
| 2015 // CALL to fixup routine. Fixup routine uses ScopeDesc info to | |
| 2016 // determine who we intended to call. | |
| 1748 | 2017 cbuf.set_insts_mark(); |
| 0 | 2018 $$$emit8$primary; |
| 2019 | |
| 2020 if (!_method) { | |
| 2021 emit_d32_reloc(cbuf, | |
| 1748 | 2022 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4), |
| 0 | 2023 runtime_call_Relocation::spec(), |
| 2024 RELOC_DISP32); | |
| 2025 } else if (_optimized_virtual) { | |
| 2026 emit_d32_reloc(cbuf, | |
| 1748 | 2027 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4), |
| 0 | 2028 opt_virtual_call_Relocation::spec(), |
| 2029 RELOC_DISP32); | |
| 2030 } else { | |
| 2031 emit_d32_reloc(cbuf, | |
| 1748 | 2032 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4), |
| 0 | 2033 static_call_Relocation::spec(), |
| 2034 RELOC_DISP32); | |
| 2035 } | |
| 2036 if (_method) { | |
|
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2037 // Emit stub for static call. |
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2038 CompiledStaticCall::emit_to_interp_stub(cbuf); |
| 0 | 2039 } |
| 2040 %} | |
| 2041 | |
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2042 enc_class Java_Dynamic_Call(method meth) %{ |
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2043 MacroAssembler _masm(&cbuf); |
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2044 __ ic_call((address)$meth$$method); |
| 0 | 2045 %} |
| 2046 | |
| 2047 enc_class Java_Compiled_Call(method meth) | |
| 2048 %{ | |
| 2049 // JAVA COMPILED CALL | |
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2050 int disp = in_bytes(Method:: from_compiled_offset()); |
| 0 | 2051 |
| 2052 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!! | |
| 2053 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small"); | |
| 2054 | |
| 2055 // callq *disp(%rax) | |
| 1748 | 2056 cbuf.set_insts_mark(); |
| 0 | 2057 $$$emit8$primary; |
| 2058 if (disp < 0x80) { | |
| 2059 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte | |
| 2060 emit_d8(cbuf, disp); // Displacement | |
| 2061 } else { | |
| 2062 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte | |
| 2063 emit_d32(cbuf, disp); // Displacement | |
| 2064 } | |
| 2065 %} | |
| 2066 | |
| 2067 enc_class reg_opc_imm(rRegI dst, immI8 shift) | |
| 2068 %{ | |
| 2069 // SAL, SAR, SHR | |
| 2070 int dstenc = $dst$$reg; | |
| 2071 if (dstenc >= 8) { | |
| 2072 emit_opcode(cbuf, Assembler::REX_B); | |
| 2073 dstenc -= 8; | |
| 2074 } | |
| 2075 $$$emit8$primary; | |
| 2076 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
| 2077 $$$emit8$shift$$constant; | |
| 2078 %} | |
| 2079 | |
| 2080 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift) | |
| 2081 %{ | |
| 2082 // SAL, SAR, SHR | |
| 2083 int dstenc = $dst$$reg; | |
| 2084 if (dstenc < 8) { | |
| 2085 emit_opcode(cbuf, Assembler::REX_W); | |
| 2086 } else { | |
| 2087 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2088 dstenc -= 8; | |
| 2089 } | |
| 2090 $$$emit8$primary; | |
| 2091 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
| 2092 $$$emit8$shift$$constant; | |
| 2093 %} | |
| 2094 | |
| 2095 enc_class load_immI(rRegI dst, immI src) | |
| 2096 %{ | |
| 2097 int dstenc = $dst$$reg; | |
| 2098 if (dstenc >= 8) { | |
| 2099 emit_opcode(cbuf, Assembler::REX_B); | |
| 2100 dstenc -= 8; | |
| 2101 } | |
| 2102 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2103 $$$emit32$src$$constant; | |
| 2104 %} | |
| 2105 | |
| 2106 enc_class load_immL(rRegL dst, immL src) | |
| 2107 %{ | |
| 2108 int dstenc = $dst$$reg; | |
| 2109 if (dstenc < 8) { | |
| 2110 emit_opcode(cbuf, Assembler::REX_W); | |
| 2111 } else { | |
| 2112 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2113 dstenc -= 8; | |
| 2114 } | |
| 2115 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2116 emit_d64(cbuf, $src$$constant); | |
| 2117 %} | |
| 2118 | |
| 2119 enc_class load_immUL32(rRegL dst, immUL32 src) | |
| 2120 %{ | |
| 2121 // same as load_immI, but this time we care about zeroes in the high word | |
| 2122 int dstenc = $dst$$reg; | |
| 2123 if (dstenc >= 8) { | |
| 2124 emit_opcode(cbuf, Assembler::REX_B); | |
| 2125 dstenc -= 8; | |
| 2126 } | |
| 2127 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2128 $$$emit32$src$$constant; | |
| 2129 %} | |
| 2130 | |
| 2131 enc_class load_immL32(rRegL dst, immL32 src) | |
| 2132 %{ | |
| 2133 int dstenc = $dst$$reg; | |
| 2134 if (dstenc < 8) { | |
| 2135 emit_opcode(cbuf, Assembler::REX_W); | |
| 2136 } else { | |
| 2137 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2138 dstenc -= 8; | |
| 2139 } | |
| 2140 emit_opcode(cbuf, 0xC7); | |
| 2141 emit_rm(cbuf, 0x03, 0x00, dstenc); | |
| 2142 $$$emit32$src$$constant; | |
| 2143 %} | |
| 2144 | |
| 2145 enc_class load_immP31(rRegP dst, immP32 src) | |
| 2146 %{ | |
| 2147 // same as load_immI, but this time we care about zeroes in the high word | |
| 2148 int dstenc = $dst$$reg; | |
| 2149 if (dstenc >= 8) { | |
| 2150 emit_opcode(cbuf, Assembler::REX_B); | |
| 2151 dstenc -= 8; | |
| 2152 } | |
| 2153 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2154 $$$emit32$src$$constant; | |
| 2155 %} | |
| 2156 | |
| 2157 enc_class load_immP(rRegP dst, immP src) | |
| 2158 %{ | |
| 2159 int dstenc = $dst$$reg; | |
| 2160 if (dstenc < 8) { | |
| 2161 emit_opcode(cbuf, Assembler::REX_W); | |
| 2162 } else { | |
| 2163 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2164 dstenc -= 8; | |
| 2165 } | |
| 2166 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2167 // This next line should be generated from ADLC | |
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2168 if ($src->constant_reloc() != relocInfo::none) { |
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2169 emit_d64_reloc(cbuf, $src$$constant, $src->constant_reloc(), RELOC_IMM64); |
| 0 | 2170 } else { |
| 2171 emit_d64(cbuf, $src$$constant); | |
| 2172 } | |
| 2173 %} | |
| 2174 | |
| 2175 enc_class Con32(immI src) | |
| 2176 %{ | |
| 2177 // Output immediate | |
| 2178 $$$emit32$src$$constant; | |
| 2179 %} | |
| 2180 | |
| 2181 enc_class Con32F_as_bits(immF src) | |
| 2182 %{ | |
| 2183 // Output Float immediate bits | |
| 2184 jfloat jf = $src$$constant; | |
| 2185 jint jf_as_bits = jint_cast(jf); | |
| 2186 emit_d32(cbuf, jf_as_bits); | |
| 2187 %} | |
| 2188 | |
| 2189 enc_class Con16(immI src) | |
| 2190 %{ | |
| 2191 // Output immediate | |
| 2192 $$$emit16$src$$constant; | |
| 2193 %} | |
| 2194 | |
| 2195 // How is this different from Con32??? XXX | |
| 2196 enc_class Con_d32(immI src) | |
| 2197 %{ | |
| 2198 emit_d32(cbuf,$src$$constant); | |
| 2199 %} | |
| 2200 | |
| 2201 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI) | |
| 2202 // Output immediate memory reference | |
| 2203 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 ); | |
| 2204 emit_d32(cbuf, 0x00); | |
| 2205 %} | |
| 2206 | |
| 2207 enc_class lock_prefix() | |
| 2208 %{ | |
| 2209 if (os::is_MP()) { | |
| 2210 emit_opcode(cbuf, 0xF0); // lock | |
| 2211 } | |
| 2212 %} | |
| 2213 | |
| 2214 enc_class REX_mem(memory mem) | |
| 2215 %{ | |
| 2216 if ($mem$$base >= 8) { | |
| 2217 if ($mem$$index < 8) { | |
| 2218 emit_opcode(cbuf, Assembler::REX_B); | |
| 2219 } else { | |
| 2220 emit_opcode(cbuf, Assembler::REX_XB); | |
| 2221 } | |
| 2222 } else { | |
| 2223 if ($mem$$index >= 8) { | |
| 2224 emit_opcode(cbuf, Assembler::REX_X); | |
| 2225 } | |
| 2226 } | |
| 2227 %} | |
| 2228 | |
| 2229 enc_class REX_mem_wide(memory mem) | |
| 2230 %{ | |
| 2231 if ($mem$$base >= 8) { | |
| 2232 if ($mem$$index < 8) { | |
| 2233 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2234 } else { | |
| 2235 emit_opcode(cbuf, Assembler::REX_WXB); | |
| 2236 } | |
| 2237 } else { | |
| 2238 if ($mem$$index < 8) { | |
| 2239 emit_opcode(cbuf, Assembler::REX_W); | |
| 2240 } else { | |
| 2241 emit_opcode(cbuf, Assembler::REX_WX); | |
| 2242 } | |
| 2243 } | |
| 2244 %} | |
| 2245 | |
| 2246 // for byte regs | |
| 2247 enc_class REX_breg(rRegI reg) | |
| 2248 %{ | |
| 2249 if ($reg$$reg >= 4) { | |
| 2250 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B); | |
| 2251 } | |
| 2252 %} | |
| 2253 | |
| 2254 // for byte regs | |
| 2255 enc_class REX_reg_breg(rRegI dst, rRegI src) | |
| 2256 %{ | |
| 2257 if ($dst$$reg < 8) { | |
| 2258 if ($src$$reg >= 4) { | |
| 2259 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B); | |
| 2260 } | |
| 2261 } else { | |
| 2262 if ($src$$reg < 8) { | |
| 2263 emit_opcode(cbuf, Assembler::REX_R); | |
| 2264 } else { | |
| 2265 emit_opcode(cbuf, Assembler::REX_RB); | |
| 2266 } | |
| 2267 } | |
| 2268 %} | |
| 2269 | |
| 2270 // for byte regs | |
| 2271 enc_class REX_breg_mem(rRegI reg, memory mem) | |
| 2272 %{ | |
| 2273 if ($reg$$reg < 8) { | |
| 2274 if ($mem$$base < 8) { | |
| 2275 if ($mem$$index >= 8) { | |
| 2276 emit_opcode(cbuf, Assembler::REX_X); | |
| 2277 } else if ($reg$$reg >= 4) { | |
| 2278 emit_opcode(cbuf, Assembler::REX); | |
| 2279 } | |
| 2280 } else { | |
| 2281 if ($mem$$index < 8) { | |
| 2282 emit_opcode(cbuf, Assembler::REX_B); | |
| 2283 } else { | |
| 2284 emit_opcode(cbuf, Assembler::REX_XB); | |
| 2285 } | |
| 2286 } | |
| 2287 } else { | |
| 2288 if ($mem$$base < 8) { | |
| 2289 if ($mem$$index < 8) { | |
| 2290 emit_opcode(cbuf, Assembler::REX_R); | |
| 2291 } else { | |
| 2292 emit_opcode(cbuf, Assembler::REX_RX); | |
| 2293 } | |
| 2294 } else { | |
| 2295 if ($mem$$index < 8) { | |
| 2296 emit_opcode(cbuf, Assembler::REX_RB); | |
| 2297 } else { | |
| 2298 emit_opcode(cbuf, Assembler::REX_RXB); | |
| 2299 } | |
| 2300 } | |
| 2301 } | |
| 2302 %} | |
| 2303 | |
| 2304 enc_class REX_reg(rRegI reg) | |
| 2305 %{ | |
| 2306 if ($reg$$reg >= 8) { | |
| 2307 emit_opcode(cbuf, Assembler::REX_B); | |
| 2308 } | |
| 2309 %} | |
| 2310 | |
| 2311 enc_class REX_reg_wide(rRegI reg) | |
| 2312 %{ | |
| 2313 if ($reg$$reg < 8) { | |
| 2314 emit_opcode(cbuf, Assembler::REX_W); | |
| 2315 } else { | |
| 2316 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2317 } | |
| 2318 %} | |
| 2319 | |
| 2320 enc_class REX_reg_reg(rRegI dst, rRegI src) | |
| 2321 %{ | |
| 2322 if ($dst$$reg < 8) { | |
| 2323 if ($src$$reg >= 8) { | |
| 2324 emit_opcode(cbuf, Assembler::REX_B); | |
| 2325 } | |
| 2326 } else { | |
| 2327 if ($src$$reg < 8) { | |
| 2328 emit_opcode(cbuf, Assembler::REX_R); | |
| 2329 } else { | |
| 2330 emit_opcode(cbuf, Assembler::REX_RB); | |
| 2331 } | |
| 2332 } | |
| 2333 %} | |
| 2334 | |
| 2335 enc_class REX_reg_reg_wide(rRegI dst, rRegI src) | |
| 2336 %{ | |
| 2337 if ($dst$$reg < 8) { | |
| 2338 if ($src$$reg < 8) { | |
| 2339 emit_opcode(cbuf, Assembler::REX_W); | |
| 2340 } else { | |
| 2341 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2342 } | |
| 2343 } else { | |
| 2344 if ($src$$reg < 8) { | |
| 2345 emit_opcode(cbuf, Assembler::REX_WR); | |
| 2346 } else { | |
| 2347 emit_opcode(cbuf, Assembler::REX_WRB); | |
| 2348 } | |
| 2349 } | |
| 2350 %} | |
| 2351 | |
| 2352 enc_class REX_reg_mem(rRegI reg, memory mem) | |
| 2353 %{ | |
| 2354 if ($reg$$reg < 8) { | |
| 2355 if ($mem$$base < 8) { | |
| 2356 if ($mem$$index >= 8) { | |
| 2357 emit_opcode(cbuf, Assembler::REX_X); | |
| 2358 } | |
| 2359 } else { | |
| 2360 if ($mem$$index < 8) { | |
| 2361 emit_opcode(cbuf, Assembler::REX_B); | |
| 2362 } else { | |
| 2363 emit_opcode(cbuf, Assembler::REX_XB); | |
| 2364 } | |
| 2365 } | |
| 2366 } else { | |
| 2367 if ($mem$$base < 8) { | |
| 2368 if ($mem$$index < 8) { | |
| 2369 emit_opcode(cbuf, Assembler::REX_R); | |
| 2370 } else { | |
| 2371 emit_opcode(cbuf, Assembler::REX_RX); | |
| 2372 } | |
| 2373 } else { | |
| 2374 if ($mem$$index < 8) { | |
| 2375 emit_opcode(cbuf, Assembler::REX_RB); | |
| 2376 } else { | |
| 2377 emit_opcode(cbuf, Assembler::REX_RXB); | |
| 2378 } | |
| 2379 } | |
| 2380 } | |
| 2381 %} | |
| 2382 | |
| 2383 enc_class REX_reg_mem_wide(rRegL reg, memory mem) | |
| 2384 %{ | |
| 2385 if ($reg$$reg < 8) { | |
| 2386 if ($mem$$base < 8) { | |
| 2387 if ($mem$$index < 8) { | |
| 2388 emit_opcode(cbuf, Assembler::REX_W); | |
| 2389 } else { | |
| 2390 emit_opcode(cbuf, Assembler::REX_WX); | |
| 2391 } | |
| 2392 } else { | |
| 2393 if ($mem$$index < 8) { | |
| 2394 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2395 } else { | |
| 2396 emit_opcode(cbuf, Assembler::REX_WXB); | |
| 2397 } | |
| 2398 } | |
| 2399 } else { | |
| 2400 if ($mem$$base < 8) { | |
| 2401 if ($mem$$index < 8) { | |
| 2402 emit_opcode(cbuf, Assembler::REX_WR); | |
| 2403 } else { | |
| 2404 emit_opcode(cbuf, Assembler::REX_WRX); | |
| 2405 } | |
| 2406 } else { | |
| 2407 if ($mem$$index < 8) { | |
| 2408 emit_opcode(cbuf, Assembler::REX_WRB); | |
| 2409 } else { | |
| 2410 emit_opcode(cbuf, Assembler::REX_WRXB); | |
| 2411 } | |
| 2412 } | |
| 2413 } | |
| 2414 %} | |
| 2415 | |
| 2416 enc_class reg_mem(rRegI ereg, memory mem) | |
| 2417 %{ | |
| 2418 // High registers handle in encode_RegMem | |
| 2419 int reg = $ereg$$reg; | |
| 2420 int base = $mem$$base; | |
| 2421 int index = $mem$$index; | |
| 2422 int scale = $mem$$scale; | |
| 2423 int disp = $mem$$disp; | |
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2424 relocInfo::relocType disp_reloc = $mem->disp_reloc(); |
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2425 |
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2426 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc); |
| 0 | 2427 %} |
| 2428 | |
| 2429 enc_class RM_opc_mem(immI rm_opcode, memory mem) | |
| 2430 %{ | |
| 2431 int rm_byte_opcode = $rm_opcode$$constant; | |
| 2432 | |
| 2433 // High registers handle in encode_RegMem | |
| 2434 int base = $mem$$base; | |
| 2435 int index = $mem$$index; | |
| 2436 int scale = $mem$$scale; | |
| 2437 int displace = $mem$$disp; | |
| 2438 | |
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2439 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when |
| 0 | 2440 // working with static |
| 2441 // globals | |
| 2442 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, | |
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2443 disp_reloc); |
| 0 | 2444 %} |
| 2445 | |
| 2446 enc_class reg_lea(rRegI dst, rRegI src0, immI src1) | |
| 2447 %{ | |
| 2448 int reg_encoding = $dst$$reg; | |
| 2449 int base = $src0$$reg; // 0xFFFFFFFF indicates no base | |
| 2450 int index = 0x04; // 0x04 indicates no index | |
| 2451 int scale = 0x00; // 0x00 indicates no scale | |
| 2452 int displace = $src1$$constant; // 0x00 indicates no displacement | |
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2453 relocInfo::relocType disp_reloc = relocInfo::none; |
| 0 | 2454 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, |
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2455 disp_reloc); |
| 0 | 2456 %} |
| 2457 | |
| 2458 enc_class neg_reg(rRegI dst) | |
| 2459 %{ | |
| 2460 int dstenc = $dst$$reg; | |
| 2461 if (dstenc >= 8) { | |
| 2462 emit_opcode(cbuf, Assembler::REX_B); | |
| 2463 dstenc -= 8; | |
| 2464 } | |
| 2465 // NEG $dst | |
| 2466 emit_opcode(cbuf, 0xF7); | |
| 2467 emit_rm(cbuf, 0x3, 0x03, dstenc); | |
| 2468 %} | |
| 2469 | |
| 2470 enc_class neg_reg_wide(rRegI dst) | |
| 2471 %{ | |
| 2472 int dstenc = $dst$$reg; | |
| 2473 if (dstenc < 8) { | |
| 2474 emit_opcode(cbuf, Assembler::REX_W); | |
| 2475 } else { | |
| 2476 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2477 dstenc -= 8; | |
| 2478 } | |
| 2479 // NEG $dst | |
| 2480 emit_opcode(cbuf, 0xF7); | |
| 2481 emit_rm(cbuf, 0x3, 0x03, dstenc); | |
| 2482 %} | |
| 2483 | |
| 2484 enc_class setLT_reg(rRegI dst) | |
| 2485 %{ | |
| 2486 int dstenc = $dst$$reg; | |
| 2487 if (dstenc >= 8) { | |
| 2488 emit_opcode(cbuf, Assembler::REX_B); | |
| 2489 dstenc -= 8; | |
| 2490 } else if (dstenc >= 4) { | |
| 2491 emit_opcode(cbuf, Assembler::REX); | |
| 2492 } | |
| 2493 // SETLT $dst | |
| 2494 emit_opcode(cbuf, 0x0F); | |
| 2495 emit_opcode(cbuf, 0x9C); | |
| 2496 emit_rm(cbuf, 0x3, 0x0, dstenc); | |
| 2497 %} | |
| 2498 | |
| 2499 enc_class setNZ_reg(rRegI dst) | |
| 2500 %{ | |
| 2501 int dstenc = $dst$$reg; | |
| 2502 if (dstenc >= 8) { | |
| 2503 emit_opcode(cbuf, Assembler::REX_B); | |
| 2504 dstenc -= 8; | |
| 2505 } else if (dstenc >= 4) { | |
| 2506 emit_opcode(cbuf, Assembler::REX); | |
| 2507 } | |
| 2508 // SETNZ $dst | |
| 2509 emit_opcode(cbuf, 0x0F); | |
| 2510 emit_opcode(cbuf, 0x95); | |
| 2511 emit_rm(cbuf, 0x3, 0x0, dstenc); | |
| 2512 %} | |
| 2513 | |
| 2514 | |
| 2515 // Compare the lonogs and set -1, 0, or 1 into dst | |
| 2516 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst) | |
| 2517 %{ | |
| 2518 int src1enc = $src1$$reg; | |
| 2519 int src2enc = $src2$$reg; | |
| 2520 int dstenc = $dst$$reg; | |
| 2521 | |
| 2522 // cmpq $src1, $src2 | |
| 2523 if (src1enc < 8) { | |
| 2524 if (src2enc < 8) { | |
| 2525 emit_opcode(cbuf, Assembler::REX_W); | |
| 2526 } else { | |
| 2527 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2528 } | |
| 2529 } else { | |
| 2530 if (src2enc < 8) { | |
| 2531 emit_opcode(cbuf, Assembler::REX_WR); | |
| 2532 } else { | |
| 2533 emit_opcode(cbuf, Assembler::REX_WRB); | |
| 2534 } | |
| 2535 } | |
| 2536 emit_opcode(cbuf, 0x3B); | |
| 2537 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7); | |
| 2538 | |
| 2539 // movl $dst, -1 | |
| 2540 if (dstenc >= 8) { | |
| 2541 emit_opcode(cbuf, Assembler::REX_B); | |
| 2542 } | |
| 2543 emit_opcode(cbuf, 0xB8 | (dstenc & 7)); | |
| 2544 emit_d32(cbuf, -1); | |
| 2545 | |
| 2546 // jl,s done | |
| 2547 emit_opcode(cbuf, 0x7C); | |
| 2548 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08); | |
| 2549 | |
| 2550 // setne $dst | |
| 2551 if (dstenc >= 4) { | |
| 2552 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B); | |
| 2553 } | |
| 2554 emit_opcode(cbuf, 0x0F); | |
| 2555 emit_opcode(cbuf, 0x95); | |
| 2556 emit_opcode(cbuf, 0xC0 | (dstenc & 7)); | |
| 2557 | |
| 2558 // movzbl $dst, $dst | |
| 2559 if (dstenc >= 4) { | |
| 2560 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB); | |
| 2561 } | |
| 2562 emit_opcode(cbuf, 0x0F); | |
| 2563 emit_opcode(cbuf, 0xB6); | |
| 2564 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7); | |
| 2565 %} | |
| 2566 | |
| 2567 enc_class Push_ResultXD(regD dst) %{ | |
| 4759 | 2568 MacroAssembler _masm(&cbuf); |
| 2569 __ fstp_d(Address(rsp, 0)); | |
| 2570 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); | |
| 2571 __ addptr(rsp, 8); | |
| 0 | 2572 %} |
| 2573 | |
| 2574 enc_class Push_SrcXD(regD src) %{ | |
| 2575 MacroAssembler _masm(&cbuf); | |
| 4759 | 2576 __ subptr(rsp, 8); |
| 2577 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 2578 __ fld_d(Address(rsp, 0)); | |
| 2579 %} | |
| 2580 | |
| 0 | 2581 |
| 2582 enc_class enc_rethrow() | |
| 2583 %{ | |
| 1748 | 2584 cbuf.set_insts_mark(); |
| 0 | 2585 emit_opcode(cbuf, 0xE9); // jmp entry |
| 2586 emit_d32_reloc(cbuf, | |
| 1748 | 2587 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4), |
| 0 | 2588 runtime_call_Relocation::spec(), |
| 2589 RELOC_DISP32); | |
| 2590 %} | |
| 2591 | |
| 2592 %} | |
| 2593 | |
| 2594 | |
|
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2595 |
| 0 | 2596 //----------FRAME-------------------------------------------------------------- |
| 2597 // Definition of frame structure and management information. | |
| 2598 // | |
| 2599 // S T A C K L A Y O U T Allocators stack-slot number | |
| 2600 // | (to get allocators register number | |
| 2601 // G Owned by | | v add OptoReg::stack0()) | |
| 2602 // r CALLER | | | |
| 2603 // o | +--------+ pad to even-align allocators stack-slot | |
| 2604 // w V | pad0 | numbers; owned by CALLER | |
| 2605 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned | |
| 2606 // h ^ | in | 5 | |
| 2607 // | | args | 4 Holes in incoming args owned by SELF | |
| 2608 // | | | | 3 | |
| 2609 // | | +--------+ | |
| 2610 // V | | old out| Empty on Intel, window on Sparc | |
| 2611 // | old |preserve| Must be even aligned. | |
| 2612 // | SP-+--------+----> Matcher::_old_SP, even aligned | |
| 2613 // | | in | 3 area for Intel ret address | |
| 2614 // Owned by |preserve| Empty on Sparc. | |
| 2615 // SELF +--------+ | |
| 2616 // | | pad2 | 2 pad to align old SP | |
| 2617 // | +--------+ 1 | |
| 2618 // | | locks | 0 | |
| 2619 // | +--------+----> OptoReg::stack0(), even aligned | |
| 2620 // | | pad1 | 11 pad to align new SP | |
| 2621 // | +--------+ | |
| 2622 // | | | 10 | |
| 2623 // | | spills | 9 spills | |
| 2624 // V | | 8 (pad0 slot for callee) | |
| 2625 // -----------+--------+----> Matcher::_out_arg_limit, unaligned | |
| 2626 // ^ | out | 7 | |
| 2627 // | | args | 6 Holes in outgoing args owned by CALLEE | |
| 2628 // Owned by +--------+ | |
| 2629 // CALLEE | new out| 6 Empty on Intel, window on Sparc | |
| 2630 // | new |preserve| Must be even-aligned. | |
| 2631 // | SP-+--------+----> Matcher::_new_SP, even aligned | |
| 2632 // | | | | |
| 2633 // | |
| 2634 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is | |
| 2635 // known from SELF's arguments and the Java calling convention. | |
| 2636 // Region 6-7 is determined per call site. | |
| 2637 // Note 2: If the calling convention leaves holes in the incoming argument | |
| 2638 // area, those holes are owned by SELF. Holes in the outgoing area | |
| 2639 // are owned by the CALLEE. Holes should not be nessecary in the | |
| 2640 // incoming area, as the Java calling convention is completely under | |
| 2641 // the control of the AD file. Doubles can be sorted and packed to | |
| 2642 // avoid holes. Holes in the outgoing arguments may be nessecary for | |
| 2643 // varargs C calling conventions. | |
| 2644 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is | |
| 2645 // even aligned with pad0 as needed. | |
| 2646 // Region 6 is even aligned. Region 6-7 is NOT even aligned; | |
| 2647 // region 6-11 is even aligned; it may be padded out more so that | |
| 2648 // the region from SP to FP meets the minimum stack alignment. | |
| 2649 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack | |
| 2650 // alignment. Region 11, pad1, may be dynamically extended so that | |
| 2651 // SP meets the minimum alignment. | |
| 2652 | |
| 2653 frame | |
| 2654 %{ | |
| 2655 // What direction does stack grow in (assumed to be same for C & Java) | |
| 2656 stack_direction(TOWARDS_LOW); | |
| 2657 | |
| 2658 // These three registers define part of the calling convention | |
| 2659 // between compiled code and the interpreter. | |
| 2660 inline_cache_reg(RAX); // Inline Cache Register | |
| 2661 interpreter_method_oop_reg(RBX); // Method Oop Register when | |
| 2662 // calling interpreter | |
| 2663 | |
| 2664 // Optional: name the operand used by cisc-spilling to access | |
| 2665 // [stack_pointer + offset] | |
| 2666 cisc_spilling_operand_name(indOffset32); | |
| 2667 | |
| 2668 // Number of stack slots consumed by locking an object | |
| 2669 sync_stack_slots(2); | |
| 2670 | |
| 2671 // Compiled code's Frame Pointer | |
| 2672 frame_pointer(RSP); | |
| 2673 | |
| 2674 // Interpreter stores its frame pointer in a register which is | |
| 2675 // stored to the stack by I2CAdaptors. | |
| 2676 // I2CAdaptors convert from interpreted java to compiled java. | |
| 2677 interpreter_frame_pointer(RBP); | |
| 2678 | |
| 2679 // Stack alignment requirement | |
| 2680 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes) | |
| 2681 | |
| 2682 // Number of stack slots between incoming argument block and the start of | |
| 2683 // a new frame. The PROLOG must add this many slots to the stack. The | |
| 2684 // EPILOG must remove this many slots. amd64 needs two slots for | |
| 2685 // return address. | |
| 2686 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls); | |
| 2687 | |
| 2688 // Number of outgoing stack slots killed above the out_preserve_stack_slots | |
| 2689 // for calls to C. Supports the var-args backing area for register parms. | |
| 2690 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt); | |
| 2691 | |
| 2692 // The after-PROLOG location of the return address. Location of | |
| 2693 // return address specifies a type (REG or STACK) and a number | |
| 2694 // representing the register number (i.e. - use a register name) or | |
| 2695 // stack slot. | |
| 2696 // Ret Addr is on stack in slot 0 if no locks or verification or alignment. | |
| 2697 // Otherwise, it is above the locks and verification slot and alignment word | |
| 2698 return_addr(STACK - 2 + | |
| 4950 | 2699 round_to((Compile::current()->in_preserve_stack_slots() + |
| 2700 Compile::current()->fixed_slots()), | |
| 2701 stack_alignment_in_slots())); | |
| 0 | 2702 |
| 2703 // Body of function which returns an integer array locating | |
| 2704 // arguments either in registers or in stack slots. Passed an array | |
| 2705 // of ideal registers called "sig" and a "length" count. Stack-slot | |
| 2706 // offsets are based on outgoing arguments, i.e. a CALLER setting up | |
| 2707 // arguments for a CALLEE. Incoming stack arguments are | |
| 2708 // automatically biased by the preserve_stack_slots field above. | |
| 2709 | |
| 2710 calling_convention | |
| 2711 %{ | |
| 2712 // No difference between ingoing/outgoing just pass false | |
| 2713 SharedRuntime::java_calling_convention(sig_bt, regs, length, false); | |
| 2714 %} | |
| 2715 | |
| 2716 c_calling_convention | |
| 2717 %{ | |
| 2718 // This is obviously always outgoing | |
| 2719 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); | |
| 2720 %} | |
| 2721 | |
| 2722 // Location of compiled Java return values. Same as C for now. | |
| 2723 return_value | |
| 2724 %{ | |
| 2725 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, | |
| 2726 "only return normal values"); | |
| 2727 | |
| 2728 static const int lo[Op_RegL + 1] = { | |
| 2729 0, | |
| 2730 0, | |
|
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2731 RAX_num, // Op_RegN |
| 0 | 2732 RAX_num, // Op_RegI |
| 2733 RAX_num, // Op_RegP | |
| 2734 XMM0_num, // Op_RegF | |
| 2735 XMM0_num, // Op_RegD | |
| 2736 RAX_num // Op_RegL | |
| 2737 }; | |
| 2738 static const int hi[Op_RegL + 1] = { | |
| 2739 0, | |
| 2740 0, | |
|
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2741 OptoReg::Bad, // Op_RegN |
| 0 | 2742 OptoReg::Bad, // Op_RegI |
| 2743 RAX_H_num, // Op_RegP | |
| 2744 OptoReg::Bad, // Op_RegF | |
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2745 XMM0b_num, // Op_RegD |
| 0 | 2746 RAX_H_num // Op_RegL |
| 2747 }; | |
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2748 // Excluded flags and vector registers. |
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2749 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 5, "missing type"); |
| 0 | 2750 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]); |
| 2751 %} | |
| 2752 %} | |
| 2753 | |
| 2754 //----------ATTRIBUTES--------------------------------------------------------- | |
| 2755 //----------Operand Attributes------------------------------------------------- | |
| 2756 op_attrib op_cost(0); // Required cost attribute | |
| 2757 | |
| 2758 //----------Instruction Attributes--------------------------------------------- | |
| 2759 ins_attrib ins_cost(100); // Required cost attribute | |
| 2760 ins_attrib ins_size(8); // Required size attribute (in bits) | |
| 2761 ins_attrib ins_short_branch(0); // Required flag: is this instruction | |
| 2762 // a non-matching short branch variant | |
| 2763 // of some long branch? | |
| 2764 ins_attrib ins_alignment(1); // Required alignment attribute (must | |
| 2765 // be a power of 2) specifies the | |
| 2766 // alignment that some part of the | |
| 2767 // instruction (not necessarily the | |
| 2768 // start) requires. If > 1, a | |
| 2769 // compute_padding() function must be | |
| 2770 // provided for the instruction | |
| 2771 | |
| 2772 //----------OPERANDS----------------------------------------------------------- | |
| 2773 // Operand definitions must precede instruction definitions for correct parsing | |
| 2774 // in the ADLC because operands constitute user defined types which are used in | |
| 2775 // instruction definitions. | |
| 2776 | |
| 2777 //----------Simple Operands---------------------------------------------------- | |
| 2778 // Immediate Operands | |
| 2779 // Integer Immediate | |
| 2780 operand immI() | |
| 2781 %{ | |
| 2782 match(ConI); | |
| 2783 | |
| 2784 op_cost(10); | |
| 2785 format %{ %} | |
| 2786 interface(CONST_INTER); | |
| 2787 %} | |
| 2788 | |
| 2789 // Constant for test vs zero | |
| 2790 operand immI0() | |
| 2791 %{ | |
| 2792 predicate(n->get_int() == 0); | |
| 2793 match(ConI); | |
| 2794 | |
| 2795 op_cost(0); | |
| 2796 format %{ %} | |
| 2797 interface(CONST_INTER); | |
| 2798 %} | |
| 2799 | |
| 2800 // Constant for increment | |
| 2801 operand immI1() | |
| 2802 %{ | |
| 2803 predicate(n->get_int() == 1); | |
| 2804 match(ConI); | |
| 2805 | |
| 2806 op_cost(0); | |
| 2807 format %{ %} | |
| 2808 interface(CONST_INTER); | |
| 2809 %} | |
| 2810 | |
| 2811 // Constant for decrement | |
| 2812 operand immI_M1() | |
| 2813 %{ | |
| 2814 predicate(n->get_int() == -1); | |
| 2815 match(ConI); | |
| 2816 | |
| 2817 op_cost(0); | |
| 2818 format %{ %} | |
| 2819 interface(CONST_INTER); | |
| 2820 %} | |
| 2821 | |
| 2822 // Valid scale values for addressing modes | |
| 2823 operand immI2() | |
| 2824 %{ | |
| 2825 predicate(0 <= n->get_int() && (n->get_int() <= 3)); | |
| 2826 match(ConI); | |
| 2827 | |
| 2828 format %{ %} | |
| 2829 interface(CONST_INTER); | |
| 2830 %} | |
| 2831 | |
| 2832 operand immI8() | |
| 2833 %{ | |
| 2834 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80)); | |
| 2835 match(ConI); | |
| 2836 | |
| 2837 op_cost(5); | |
| 2838 format %{ %} | |
| 2839 interface(CONST_INTER); | |
| 2840 %} | |
| 2841 | |
| 2842 operand immI16() | |
| 2843 %{ | |
| 2844 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767)); | |
| 2845 match(ConI); | |
| 2846 | |
| 2847 op_cost(10); | |
| 2848 format %{ %} | |
| 2849 interface(CONST_INTER); | |
| 2850 %} | |
| 2851 | |
|
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2852 // Int Immediate non-negative |
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2853 operand immU31() |
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2854 %{ |
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2855 predicate(n->get_int() >= 0); |
|
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2856 match(ConI); |
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2857 |
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|
2858 op_cost(0); |
|
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2859 format %{ %} |
|
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2860 interface(CONST_INTER); |
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2861 %} |
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|
2862 |
| 0 | 2863 // Constant for long shifts |
| 2864 operand immI_32() | |
| 2865 %{ | |
| 2866 predicate( n->get_int() == 32 ); | |
| 2867 match(ConI); | |
| 2868 | |
| 2869 op_cost(0); | |
| 2870 format %{ %} | |
| 2871 interface(CONST_INTER); | |
| 2872 %} | |
| 2873 | |
| 2874 // Constant for long shifts | |
| 2875 operand immI_64() | |
| 2876 %{ | |
| 2877 predicate( n->get_int() == 64 ); | |
| 2878 match(ConI); | |
| 2879 | |
| 2880 op_cost(0); | |
| 2881 format %{ %} | |
| 2882 interface(CONST_INTER); | |
| 2883 %} | |
| 2884 | |
| 2885 // Pointer Immediate | |
| 2886 operand immP() | |
| 2887 %{ | |
| 2888 match(ConP); | |
| 2889 | |
| 2890 op_cost(10); | |
| 2891 format %{ %} | |
| 2892 interface(CONST_INTER); | |
| 2893 %} | |
| 2894 | |
| 2895 // NULL Pointer Immediate | |
| 2896 operand immP0() | |
| 2897 %{ | |
| 2898 predicate(n->get_ptr() == 0); | |
| 2899 match(ConP); | |
| 2900 | |
| 2901 op_cost(5); | |
| 2902 format %{ %} | |
| 2903 interface(CONST_INTER); | |
| 2904 %} | |
| 2905 | |
|
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2906 // Pointer Immediate |
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2907 operand immN() %{ |
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2908 match(ConN); |
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2909 |
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2910 op_cost(10); |
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2911 format %{ %} |
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2912 interface(CONST_INTER); |
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2913 %} |
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2914 |
|
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2915 operand immNKlass() %{ |
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|
2916 match(ConNKlass); |
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|
2917 |
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|
2918 op_cost(10); |
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|
2919 format %{ %} |
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|
2920 interface(CONST_INTER); |
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2921 %} |
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2922 |
|
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2923 // NULL Pointer Immediate |
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2924 operand immN0() %{ |
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2925 predicate(n->get_narrowcon() == 0); |
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2926 match(ConN); |
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2927 |
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2928 op_cost(5); |
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2929 format %{ %} |
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2930 interface(CONST_INTER); |
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2931 %} |
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2932 |
| 0 | 2933 operand immP31() |
| 2934 %{ | |
|
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2935 predicate(n->as_Type()->type()->reloc() == relocInfo::none |
| 0 | 2936 && (n->get_ptr() >> 31) == 0); |
| 2937 match(ConP); | |
| 2938 | |
| 2939 op_cost(5); | |
| 2940 format %{ %} | |
| 2941 interface(CONST_INTER); | |
| 2942 %} | |
| 2943 | |
|
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2944 |
| 0 | 2945 // Long Immediate |
| 2946 operand immL() | |
| 2947 %{ | |
| 2948 match(ConL); | |
| 2949 | |
| 2950 op_cost(20); | |
| 2951 format %{ %} | |
| 2952 interface(CONST_INTER); | |
| 2953 %} | |
| 2954 | |
| 2955 // Long Immediate 8-bit | |
| 2956 operand immL8() | |
| 2957 %{ | |
| 2958 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L); | |
| 2959 match(ConL); | |
| 2960 | |
| 2961 op_cost(5); | |
| 2962 format %{ %} | |
| 2963 interface(CONST_INTER); | |
| 2964 %} | |
| 2965 | |
| 2966 // Long Immediate 32-bit unsigned | |
| 2967 operand immUL32() | |
| 2968 %{ | |
| 2969 predicate(n->get_long() == (unsigned int) (n->get_long())); | |
| 2970 match(ConL); | |
| 2971 | |
| 2972 op_cost(10); | |
| 2973 format %{ %} | |
| 2974 interface(CONST_INTER); | |
| 2975 %} | |
| 2976 | |
| 2977 // Long Immediate 32-bit signed | |
| 2978 operand immL32() | |
| 2979 %{ | |
| 2980 predicate(n->get_long() == (int) (n->get_long())); | |
| 2981 match(ConL); | |
| 2982 | |
| 2983 op_cost(15); | |
| 2984 format %{ %} | |
| 2985 interface(CONST_INTER); | |
| 2986 %} | |
| 2987 | |
| 2988 // Long Immediate zero | |
| 2989 operand immL0() | |
| 2990 %{ | |
| 2991 predicate(n->get_long() == 0L); | |
| 2992 match(ConL); | |
| 2993 | |
| 2994 op_cost(10); | |
| 2995 format %{ %} | |
| 2996 interface(CONST_INTER); | |
| 2997 %} | |
| 2998 | |
| 2999 // Constant for increment | |
| 3000 operand immL1() | |
| 3001 %{ | |
| 3002 predicate(n->get_long() == 1); | |
| 3003 match(ConL); | |
| 3004 | |
| 3005 format %{ %} | |
| 3006 interface(CONST_INTER); | |
| 3007 %} | |
| 3008 | |
| 3009 // Constant for decrement | |
| 3010 operand immL_M1() | |
| 3011 %{ | |
| 3012 predicate(n->get_long() == -1); | |
| 3013 match(ConL); | |
| 3014 | |
| 3015 format %{ %} | |
| 3016 interface(CONST_INTER); | |
| 3017 %} | |
| 3018 | |
| 3019 // Long Immediate: the value 10 | |
| 3020 operand immL10() | |
| 3021 %{ | |
| 3022 predicate(n->get_long() == 10); | |
| 3023 match(ConL); | |
| 3024 | |
| 3025 format %{ %} | |
| 3026 interface(CONST_INTER); | |
| 3027 %} | |
| 3028 | |
| 3029 // Long immediate from 0 to 127. | |
| 3030 // Used for a shorter form of long mul by 10. | |
| 3031 operand immL_127() | |
| 3032 %{ | |
| 3033 predicate(0 <= n->get_long() && n->get_long() < 0x80); | |
| 3034 match(ConL); | |
| 3035 | |
| 3036 op_cost(10); | |
| 3037 format %{ %} | |
| 3038 interface(CONST_INTER); | |
| 3039 %} | |
| 3040 | |
| 3041 // Long Immediate: low 32-bit mask | |
| 3042 operand immL_32bits() | |
| 3043 %{ | |
| 3044 predicate(n->get_long() == 0xFFFFFFFFL); | |
| 3045 match(ConL); | |
| 3046 op_cost(20); | |
| 3047 | |
| 3048 format %{ %} | |
| 3049 interface(CONST_INTER); | |
| 3050 %} | |
| 3051 | |
| 3052 // Float Immediate zero | |
| 3053 operand immF0() | |
| 3054 %{ | |
| 3055 predicate(jint_cast(n->getf()) == 0); | |
| 3056 match(ConF); | |
| 3057 | |
| 3058 op_cost(5); | |
| 3059 format %{ %} | |
| 3060 interface(CONST_INTER); | |
| 3061 %} | |
| 3062 | |
| 3063 // Float Immediate | |
| 3064 operand immF() | |
| 3065 %{ | |
| 3066 match(ConF); | |
| 3067 | |
| 3068 op_cost(15); | |
| 3069 format %{ %} | |
| 3070 interface(CONST_INTER); | |
| 3071 %} | |
| 3072 | |
| 3073 // Double Immediate zero | |
| 3074 operand immD0() | |
| 3075 %{ | |
| 3076 predicate(jlong_cast(n->getd()) == 0); | |
| 3077 match(ConD); | |
| 3078 | |
| 3079 op_cost(5); | |
| 3080 format %{ %} | |
| 3081 interface(CONST_INTER); | |
| 3082 %} | |
| 3083 | |
| 3084 // Double Immediate | |
| 3085 operand immD() | |
| 3086 %{ | |
| 3087 match(ConD); | |
| 3088 | |
| 3089 op_cost(15); | |
| 3090 format %{ %} | |
| 3091 interface(CONST_INTER); | |
| 3092 %} | |
| 3093 | |
| 3094 // Immediates for special shifts (sign extend) | |
| 3095 | |
| 3096 // Constants for increment | |
| 3097 operand immI_16() | |
| 3098 %{ | |
| 3099 predicate(n->get_int() == 16); | |
| 3100 match(ConI); | |
| 3101 | |
| 3102 format %{ %} | |
| 3103 interface(CONST_INTER); | |
| 3104 %} | |
| 3105 | |
| 3106 operand immI_24() | |
| 3107 %{ | |
| 3108 predicate(n->get_int() == 24); | |
| 3109 match(ConI); | |
| 3110 | |
| 3111 format %{ %} | |
| 3112 interface(CONST_INTER); | |
| 3113 %} | |
| 3114 | |
| 3115 // Constant for byte-wide masking | |
| 3116 operand immI_255() | |
| 3117 %{ | |
| 3118 predicate(n->get_int() == 255); | |
| 3119 match(ConI); | |
| 3120 | |
| 3121 format %{ %} | |
| 3122 interface(CONST_INTER); | |
| 3123 %} | |
| 3124 | |
| 3125 // Constant for short-wide masking | |
| 3126 operand immI_65535() | |
| 3127 %{ | |
| 3128 predicate(n->get_int() == 65535); | |
| 3129 match(ConI); | |
| 3130 | |
| 3131 format %{ %} | |
| 3132 interface(CONST_INTER); | |
| 3133 %} | |
| 3134 | |
| 3135 // Constant for byte-wide masking | |
| 3136 operand immL_255() | |
| 3137 %{ | |
| 3138 predicate(n->get_long() == 255); | |
| 3139 match(ConL); | |
| 3140 | |
| 3141 format %{ %} | |
| 3142 interface(CONST_INTER); | |
| 3143 %} | |
| 3144 | |
| 3145 // Constant for short-wide masking | |
| 3146 operand immL_65535() | |
| 3147 %{ | |
| 3148 predicate(n->get_long() == 65535); | |
| 3149 match(ConL); | |
| 3150 | |
| 3151 format %{ %} | |
| 3152 interface(CONST_INTER); | |
| 3153 %} | |
| 3154 | |
| 3155 // Register Operands | |
| 3156 // Integer Register | |
| 3157 operand rRegI() | |
| 3158 %{ | |
| 3159 constraint(ALLOC_IN_RC(int_reg)); | |
| 3160 match(RegI); | |
| 3161 | |
| 3162 match(rax_RegI); | |
| 3163 match(rbx_RegI); | |
| 3164 match(rcx_RegI); | |
| 3165 match(rdx_RegI); | |
| 3166 match(rdi_RegI); | |
| 3167 | |
| 3168 format %{ %} | |
| 3169 interface(REG_INTER); | |
| 3170 %} | |
| 3171 | |
| 3172 // Special Registers | |
| 3173 operand rax_RegI() | |
| 3174 %{ | |
| 3175 constraint(ALLOC_IN_RC(int_rax_reg)); | |
| 3176 match(RegI); | |
| 3177 match(rRegI); | |
| 3178 | |
| 3179 format %{ "RAX" %} | |
| 3180 interface(REG_INTER); | |
| 3181 %} | |
| 3182 | |
| 3183 // Special Registers | |
| 3184 operand rbx_RegI() | |
| 3185 %{ | |
| 3186 constraint(ALLOC_IN_RC(int_rbx_reg)); | |
| 3187 match(RegI); | |
| 3188 match(rRegI); | |
| 3189 | |
| 3190 format %{ "RBX" %} | |
| 3191 interface(REG_INTER); | |
| 3192 %} | |
| 3193 | |
| 3194 operand rcx_RegI() | |
| 3195 %{ | |
| 3196 constraint(ALLOC_IN_RC(int_rcx_reg)); | |
| 3197 match(RegI); | |
| 3198 match(rRegI); | |
| 3199 | |
| 3200 format %{ "RCX" %} | |
| 3201 interface(REG_INTER); | |
| 3202 %} | |
| 3203 | |
| 3204 operand rdx_RegI() | |
| 3205 %{ | |
| 3206 constraint(ALLOC_IN_RC(int_rdx_reg)); | |
| 3207 match(RegI); | |
| 3208 match(rRegI); | |
| 3209 | |
| 3210 format %{ "RDX" %} | |
| 3211 interface(REG_INTER); | |
| 3212 %} | |
| 3213 | |
| 3214 operand rdi_RegI() | |
| 3215 %{ | |
| 3216 constraint(ALLOC_IN_RC(int_rdi_reg)); | |
| 3217 match(RegI); | |
| 3218 match(rRegI); | |
| 3219 | |
| 3220 format %{ "RDI" %} | |
| 3221 interface(REG_INTER); | |
| 3222 %} | |
| 3223 | |
| 3224 operand no_rcx_RegI() | |
| 3225 %{ | |
| 3226 constraint(ALLOC_IN_RC(int_no_rcx_reg)); | |
| 3227 match(RegI); | |
| 3228 match(rax_RegI); | |
| 3229 match(rbx_RegI); | |
| 3230 match(rdx_RegI); | |
| 3231 match(rdi_RegI); | |
| 3232 | |
| 3233 format %{ %} | |
| 3234 interface(REG_INTER); | |
| 3235 %} | |
| 3236 | |
| 3237 operand no_rax_rdx_RegI() | |
| 3238 %{ | |
| 3239 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg)); | |
| 3240 match(RegI); | |
| 3241 match(rbx_RegI); | |
| 3242 match(rcx_RegI); | |
| 3243 match(rdi_RegI); | |
| 3244 | |
| 3245 format %{ %} | |
| 3246 interface(REG_INTER); | |
| 3247 %} | |
| 3248 | |
| 3249 // Pointer Register | |
| 3250 operand any_RegP() | |
| 3251 %{ | |
| 3252 constraint(ALLOC_IN_RC(any_reg)); | |
| 3253 match(RegP); | |
| 3254 match(rax_RegP); | |
| 3255 match(rbx_RegP); | |
| 3256 match(rdi_RegP); | |
| 3257 match(rsi_RegP); | |
| 3258 match(rbp_RegP); | |
| 3259 match(r15_RegP); | |
| 3260 match(rRegP); | |
| 3261 | |
| 3262 format %{ %} | |
| 3263 interface(REG_INTER); | |
| 3264 %} | |
| 3265 | |
| 3266 operand rRegP() | |
| 3267 %{ | |
| 3268 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3269 match(RegP); | |
| 3270 match(rax_RegP); | |
| 3271 match(rbx_RegP); | |
| 3272 match(rdi_RegP); | |
| 3273 match(rsi_RegP); | |
| 3274 match(rbp_RegP); | |
| 3275 match(r15_RegP); // See Q&A below about r15_RegP. | |
| 3276 | |
| 3277 format %{ %} | |
| 3278 interface(REG_INTER); | |
| 3279 %} | |
| 3280 | |
|
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3281 operand rRegN() %{ |
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3282 constraint(ALLOC_IN_RC(int_reg)); |
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3283 match(RegN); |
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3284 |
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3285 format %{ %} |
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3286 interface(REG_INTER); |
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3287 %} |
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3288 |
| 0 | 3289 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP? |
| 3290 // Answer: Operand match rules govern the DFA as it processes instruction inputs. | |
| 3291 // It's fine for an instruction input which expects rRegP to match a r15_RegP. | |
| 3292 // The output of an instruction is controlled by the allocator, which respects | |
| 3293 // register class masks, not match rules. Unless an instruction mentions | |
| 3294 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered | |
| 3295 // by the allocator as an input. | |
| 3296 | |
| 3297 operand no_rax_RegP() | |
| 3298 %{ | |
| 3299 constraint(ALLOC_IN_RC(ptr_no_rax_reg)); | |
| 3300 match(RegP); | |
| 3301 match(rbx_RegP); | |
| 3302 match(rsi_RegP); | |
| 3303 match(rdi_RegP); | |
| 3304 | |
| 3305 format %{ %} | |
| 3306 interface(REG_INTER); | |
| 3307 %} | |
| 3308 | |
| 3309 operand no_rbp_RegP() | |
| 3310 %{ | |
| 3311 constraint(ALLOC_IN_RC(ptr_no_rbp_reg)); | |
| 3312 match(RegP); | |
| 3313 match(rbx_RegP); | |
| 3314 match(rsi_RegP); | |
| 3315 match(rdi_RegP); | |
| 3316 | |
| 3317 format %{ %} | |
| 3318 interface(REG_INTER); | |
| 3319 %} | |
| 3320 | |
| 3321 operand no_rax_rbx_RegP() | |
| 3322 %{ | |
| 3323 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg)); | |
| 3324 match(RegP); | |
| 3325 match(rsi_RegP); | |
| 3326 match(rdi_RegP); | |
| 3327 | |
| 3328 format %{ %} | |
| 3329 interface(REG_INTER); | |
| 3330 %} | |
| 3331 | |
| 3332 // Special Registers | |
| 3333 // Return a pointer value | |
| 3334 operand rax_RegP() | |
| 3335 %{ | |
| 3336 constraint(ALLOC_IN_RC(ptr_rax_reg)); | |
| 3337 match(RegP); | |
| 3338 match(rRegP); | |
| 3339 | |
| 3340 format %{ %} | |
| 3341 interface(REG_INTER); | |
| 3342 %} | |
| 3343 | |
|
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3344 // Special Registers |
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3345 // Return a compressed pointer value |
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3346 operand rax_RegN() |
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3347 %{ |
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3348 constraint(ALLOC_IN_RC(int_rax_reg)); |
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3349 match(RegN); |
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3350 match(rRegN); |
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3351 |
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3352 format %{ %} |
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3353 interface(REG_INTER); |
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3354 %} |
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3355 |
| 0 | 3356 // Used in AtomicAdd |
| 3357 operand rbx_RegP() | |
| 3358 %{ | |
| 3359 constraint(ALLOC_IN_RC(ptr_rbx_reg)); | |
| 3360 match(RegP); | |
| 3361 match(rRegP); | |
| 3362 | |
| 3363 format %{ %} | |
| 3364 interface(REG_INTER); | |
| 3365 %} | |
| 3366 | |
| 3367 operand rsi_RegP() | |
| 3368 %{ | |
| 3369 constraint(ALLOC_IN_RC(ptr_rsi_reg)); | |
| 3370 match(RegP); | |
| 3371 match(rRegP); | |
| 3372 | |
| 3373 format %{ %} | |
| 3374 interface(REG_INTER); | |
| 3375 %} | |
| 3376 | |
| 3377 // Used in rep stosq | |
| 3378 operand rdi_RegP() | |
| 3379 %{ | |
| 3380 constraint(ALLOC_IN_RC(ptr_rdi_reg)); | |
| 3381 match(RegP); | |
| 3382 match(rRegP); | |
| 3383 | |
| 3384 format %{ %} | |
| 3385 interface(REG_INTER); | |
| 3386 %} | |
| 3387 | |
| 3388 operand rbp_RegP() | |
| 3389 %{ | |
| 3390 constraint(ALLOC_IN_RC(ptr_rbp_reg)); | |
| 3391 match(RegP); | |
| 3392 match(rRegP); | |
| 3393 | |
| 3394 format %{ %} | |
| 3395 interface(REG_INTER); | |
| 3396 %} | |
| 3397 | |
| 3398 operand r15_RegP() | |
| 3399 %{ | |
| 3400 constraint(ALLOC_IN_RC(ptr_r15_reg)); | |
| 3401 match(RegP); | |
| 3402 match(rRegP); | |
| 3403 | |
| 3404 format %{ %} | |
| 3405 interface(REG_INTER); | |
| 3406 %} | |
| 3407 | |
| 3408 operand rRegL() | |
| 3409 %{ | |
| 3410 constraint(ALLOC_IN_RC(long_reg)); | |
| 3411 match(RegL); | |
| 3412 match(rax_RegL); | |
| 3413 match(rdx_RegL); | |
| 3414 | |
| 3415 format %{ %} | |
| 3416 interface(REG_INTER); | |
| 3417 %} | |
| 3418 | |
| 3419 // Special Registers | |
| 3420 operand no_rax_rdx_RegL() | |
| 3421 %{ | |
| 3422 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg)); | |
| 3423 match(RegL); | |
| 3424 match(rRegL); | |
| 3425 | |
| 3426 format %{ %} | |
| 3427 interface(REG_INTER); | |
| 3428 %} | |
| 3429 | |
| 3430 operand no_rax_RegL() | |
| 3431 %{ | |
| 3432 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg)); | |
| 3433 match(RegL); | |
| 3434 match(rRegL); | |
| 3435 match(rdx_RegL); | |
| 3436 | |
| 3437 format %{ %} | |
| 3438 interface(REG_INTER); | |
| 3439 %} | |
| 3440 | |
| 3441 operand no_rcx_RegL() | |
| 3442 %{ | |
| 3443 constraint(ALLOC_IN_RC(long_no_rcx_reg)); | |
| 3444 match(RegL); | |
| 3445 match(rRegL); | |
| 3446 | |
| 3447 format %{ %} | |
| 3448 interface(REG_INTER); | |
| 3449 %} | |
| 3450 | |
| 3451 operand rax_RegL() | |
| 3452 %{ | |
| 3453 constraint(ALLOC_IN_RC(long_rax_reg)); | |
| 3454 match(RegL); | |
| 3455 match(rRegL); | |
| 3456 | |
| 3457 format %{ "RAX" %} | |
| 3458 interface(REG_INTER); | |
| 3459 %} | |
| 3460 | |
| 3461 operand rcx_RegL() | |
| 3462 %{ | |
| 3463 constraint(ALLOC_IN_RC(long_rcx_reg)); | |
| 3464 match(RegL); | |
| 3465 match(rRegL); | |
| 3466 | |
| 3467 format %{ %} | |
| 3468 interface(REG_INTER); | |
| 3469 %} | |
| 3470 | |
| 3471 operand rdx_RegL() | |
| 3472 %{ | |
| 3473 constraint(ALLOC_IN_RC(long_rdx_reg)); | |
| 3474 match(RegL); | |
| 3475 match(rRegL); | |
| 3476 | |
| 3477 format %{ %} | |
| 3478 interface(REG_INTER); | |
| 3479 %} | |
| 3480 | |
| 3481 // Flags register, used as output of compare instructions | |
| 3482 operand rFlagsReg() | |
| 3483 %{ | |
| 3484 constraint(ALLOC_IN_RC(int_flags)); | |
| 3485 match(RegFlags); | |
| 3486 | |
| 3487 format %{ "RFLAGS" %} | |
| 3488 interface(REG_INTER); | |
| 3489 %} | |
| 3490 | |
| 3491 // Flags register, used as output of FLOATING POINT compare instructions | |
| 3492 operand rFlagsRegU() | |
| 3493 %{ | |
| 3494 constraint(ALLOC_IN_RC(int_flags)); | |
| 3495 match(RegFlags); | |
| 3496 | |
| 3497 format %{ "RFLAGS_U" %} | |
| 3498 interface(REG_INTER); | |
| 3499 %} | |
| 3500 | |
|
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3501 operand rFlagsRegUCF() %{ |
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3502 constraint(ALLOC_IN_RC(int_flags)); |
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3503 match(RegFlags); |
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3504 predicate(false); |
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|
3505 |
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3506 format %{ "RFLAGS_U_CF" %} |
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3507 interface(REG_INTER); |
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3508 %} |
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3509 |
| 0 | 3510 // Float register operands |
| 3511 operand regF() | |
| 3512 %{ | |
| 3513 constraint(ALLOC_IN_RC(float_reg)); | |
| 3514 match(RegF); | |
| 3515 | |
| 3516 format %{ %} | |
| 3517 interface(REG_INTER); | |
| 3518 %} | |
| 3519 | |
| 3520 // Double register operands | |
|
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3521 operand regD() |
| 0 | 3522 %{ |
| 3523 constraint(ALLOC_IN_RC(double_reg)); | |
| 3524 match(RegD); | |
| 3525 | |
| 3526 format %{ %} | |
| 3527 interface(REG_INTER); | |
| 3528 %} | |
| 3529 | |
| 3530 //----------Memory Operands---------------------------------------------------- | |
| 3531 // Direct Memory Operand | |
| 3532 // operand direct(immP addr) | |
| 3533 // %{ | |
| 3534 // match(addr); | |
| 3535 | |
| 3536 // format %{ "[$addr]" %} | |
| 3537 // interface(MEMORY_INTER) %{ | |
| 3538 // base(0xFFFFFFFF); | |
| 3539 // index(0x4); | |
| 3540 // scale(0x0); | |
| 3541 // disp($addr); | |
| 3542 // %} | |
| 3543 // %} | |
| 3544 | |
| 3545 // Indirect Memory Operand | |
| 3546 operand indirect(any_RegP reg) | |
| 3547 %{ | |
| 3548 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3549 match(reg); | |
| 3550 | |
| 3551 format %{ "[$reg]" %} | |
| 3552 interface(MEMORY_INTER) %{ | |
| 3553 base($reg); | |
| 3554 index(0x4); | |
| 3555 scale(0x0); | |
| 3556 disp(0x0); | |
| 3557 %} | |
| 3558 %} | |
| 3559 | |
| 3560 // Indirect Memory Plus Short Offset Operand | |
| 3561 operand indOffset8(any_RegP reg, immL8 off) | |
| 3562 %{ | |
| 3563 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3564 match(AddP reg off); | |
| 3565 | |
| 3566 format %{ "[$reg + $off (8-bit)]" %} | |
| 3567 interface(MEMORY_INTER) %{ | |
| 3568 base($reg); | |
| 3569 index(0x4); | |
| 3570 scale(0x0); | |
| 3571 disp($off); | |
| 3572 %} | |
| 3573 %} | |
| 3574 | |
| 3575 // Indirect Memory Plus Long Offset Operand | |
| 3576 operand indOffset32(any_RegP reg, immL32 off) | |
| 3577 %{ | |
| 3578 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3579 match(AddP reg off); | |
| 3580 | |
| 3581 format %{ "[$reg + $off (32-bit)]" %} | |
| 3582 interface(MEMORY_INTER) %{ | |
| 3583 base($reg); | |
| 3584 index(0x4); | |
| 3585 scale(0x0); | |
| 3586 disp($off); | |
| 3587 %} | |
| 3588 %} | |
| 3589 | |
| 3590 // Indirect Memory Plus Index Register Plus Offset Operand | |
| 3591 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off) | |
| 3592 %{ | |
| 3593 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3594 match(AddP (AddP reg lreg) off); | |
| 3595 | |
| 3596 op_cost(10); | |
| 3597 format %{"[$reg + $off + $lreg]" %} | |
| 3598 interface(MEMORY_INTER) %{ | |
| 3599 base($reg); | |
| 3600 index($lreg); | |
| 3601 scale(0x0); | |
| 3602 disp($off); | |
| 3603 %} | |
| 3604 %} | |
| 3605 | |
| 3606 // Indirect Memory Plus Index Register Plus Offset Operand | |
| 3607 operand indIndex(any_RegP reg, rRegL lreg) | |
| 3608 %{ | |
| 3609 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3610 match(AddP reg lreg); | |
| 3611 | |
| 3612 op_cost(10); | |
| 3613 format %{"[$reg + $lreg]" %} | |
| 3614 interface(MEMORY_INTER) %{ | |
| 3615 base($reg); | |
| 3616 index($lreg); | |
| 3617 scale(0x0); | |
| 3618 disp(0x0); | |
| 3619 %} | |
| 3620 %} | |
| 3621 | |
| 3622 // Indirect Memory Times Scale Plus Index Register | |
| 3623 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale) | |
| 3624 %{ | |
| 3625 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3626 match(AddP reg (LShiftL lreg scale)); | |
| 3627 | |
| 3628 op_cost(10); | |
| 3629 format %{"[$reg + $lreg << $scale]" %} | |
| 3630 interface(MEMORY_INTER) %{ | |
| 3631 base($reg); | |
| 3632 index($lreg); | |
| 3633 scale($scale); | |
| 3634 disp(0x0); | |
| 3635 %} | |
| 3636 %} | |
| 3637 | |
| 3638 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand | |
| 3639 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale) | |
| 3640 %{ | |
| 3641 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3642 match(AddP (AddP reg (LShiftL lreg scale)) off); | |
| 3643 | |
| 3644 op_cost(10); | |
| 3645 format %{"[$reg + $off + $lreg << $scale]" %} | |
| 3646 interface(MEMORY_INTER) %{ | |
| 3647 base($reg); | |
| 3648 index($lreg); | |
| 3649 scale($scale); | |
| 3650 disp($off); | |
| 3651 %} | |
| 3652 %} | |
| 3653 | |
| 3654 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand | |
| 3655 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale) | |
| 3656 %{ | |
| 3657 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3658 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0); | |
| 3659 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off); | |
| 3660 | |
| 3661 op_cost(10); | |
| 3662 format %{"[$reg + $off + $idx << $scale]" %} | |
| 3663 interface(MEMORY_INTER) %{ | |
| 3664 base($reg); | |
| 3665 index($idx); | |
| 3666 scale($scale); | |
| 3667 disp($off); | |
| 3668 %} | |
| 3669 %} | |
| 3670 | |
|
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3671 // Indirect Narrow Oop Plus Offset Operand |
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3672 // Note: x86 architecture doesn't support "scale * index + offset" without a base |
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3673 // we can't free r12 even with Universe::narrow_oop_base() == NULL. |
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3674 operand indCompressedOopOffset(rRegN reg, immL32 off) %{ |
|
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3675 predicate(UseCompressedOops && (Universe::narrow_oop_shift() == Address::times_8)); |
|
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3676 constraint(ALLOC_IN_RC(ptr_reg)); |
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3677 match(AddP (DecodeN reg) off); |
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3678 |
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3679 op_cost(10); |
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3680 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %} |
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3681 interface(MEMORY_INTER) %{ |
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3682 base(0xc); // R12 |
|
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3683 index($reg); |
|
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3684 scale(0x3); |
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3685 disp($off); |
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|
3686 %} |
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3687 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3688 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3689 // Indirect Memory Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3690 operand indirectNarrow(rRegN reg) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3691 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3692 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3693 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3694 match(DecodeN reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3695 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3696 format %{ "[$reg]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3697 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3698 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3699 index(0x4); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3700 scale(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3701 disp(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3702 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3703 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3704 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3705 // Indirect Memory Plus Short Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3706 operand indOffset8Narrow(rRegN reg, immL8 off) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3707 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3708 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3709 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3710 match(AddP (DecodeN reg) off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3711 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3712 format %{ "[$reg + $off (8-bit)]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3713 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3714 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3715 index(0x4); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3716 scale(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3717 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3718 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3719 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3720 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3721 // Indirect Memory Plus Long Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3722 operand indOffset32Narrow(rRegN reg, immL32 off) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3723 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3724 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3725 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3726 match(AddP (DecodeN reg) off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3727 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3728 format %{ "[$reg + $off (32-bit)]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3729 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3730 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3731 index(0x4); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3732 scale(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3733 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3734 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3735 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3736 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3737 // Indirect Memory Plus Index Register Plus Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3738 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3739 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3740 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3741 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3742 match(AddP (AddP (DecodeN reg) lreg) off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3743 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3744 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3745 format %{"[$reg + $off + $lreg]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3746 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3747 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3748 index($lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3749 scale(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3750 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3751 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3752 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3753 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3754 // Indirect Memory Plus Index Register Plus Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3755 operand indIndexNarrow(rRegN reg, rRegL lreg) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3756 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3757 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3758 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3759 match(AddP (DecodeN reg) lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3760 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3761 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3762 format %{"[$reg + $lreg]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3763 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3764 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3765 index($lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3766 scale(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3767 disp(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3768 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3769 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3770 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3771 // Indirect Memory Times Scale Plus Index Register |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3772 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3773 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3774 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3775 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3776 match(AddP (DecodeN reg) (LShiftL lreg scale)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3777 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3778 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3779 format %{"[$reg + $lreg << $scale]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3780 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3781 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3782 index($lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3783 scale($scale); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3784 disp(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3785 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3786 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3787 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3788 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3789 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3790 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3791 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3792 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3793 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3794 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3795 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3796 format %{"[$reg + $off + $lreg << $scale]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3797 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3798 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3799 index($lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3800 scale($scale); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3801 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3802 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3803 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3804 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3805 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3806 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3807 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3808 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3809 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3810 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3811 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3812 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3813 format %{"[$reg + $off + $idx << $scale]" %} |
|
660978a2a31a
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3814 interface(MEMORY_INTER) %{ |
|
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|
3815 base($reg); |
|
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|
3816 index($idx); |
|
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|
3817 scale($scale); |
|
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|
3818 disp($off); |
|
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|
3819 %} |
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|
3820 %} |
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|
3821 |
| 0 | 3822 //----------Special Memory Operands-------------------------------------------- |
| 3823 // Stack Slot Operand - This operand is used for loading and storing temporary | |
| 3824 // values on the stack where a match requires a value to | |
| 3825 // flow through memory. | |
| 3826 operand stackSlotP(sRegP reg) | |
| 3827 %{ | |
| 3828 constraint(ALLOC_IN_RC(stack_slots)); | |
| 3829 // No match rule because this operand is only generated in matching | |
| 3830 | |
| 3831 format %{ "[$reg]" %} | |
| 3832 interface(MEMORY_INTER) %{ | |
| 3833 base(0x4); // RSP | |
| 3834 index(0x4); // No Index | |
| 3835 scale(0x0); // No Scale | |
| 3836 disp($reg); // Stack Offset | |
| 3837 %} | |
| 3838 %} | |
| 3839 | |
| 3840 operand stackSlotI(sRegI reg) | |
| 3841 %{ | |
| 3842 constraint(ALLOC_IN_RC(stack_slots)); | |
| 3843 // No match rule because this operand is only generated in matching | |
| 3844 | |
| 3845 format %{ "[$reg]" %} | |
| 3846 interface(MEMORY_INTER) %{ | |
| 3847 base(0x4); // RSP | |
| 3848 index(0x4); // No Index | |
| 3849 scale(0x0); // No Scale | |
| 3850 disp($reg); // Stack Offset | |
| 3851 %} | |
| 3852 %} | |
| 3853 | |
| 3854 operand stackSlotF(sRegF reg) | |
| 3855 %{ | |
| 3856 constraint(ALLOC_IN_RC(stack_slots)); | |
| 3857 // No match rule because this operand is only generated in matching | |
| 3858 | |
| 3859 format %{ "[$reg]" %} | |
| 3860 interface(MEMORY_INTER) %{ | |
| 3861 base(0x4); // RSP | |
| 3862 index(0x4); // No Index | |
| 3863 scale(0x0); // No Scale | |
| 3864 disp($reg); // Stack Offset | |
| 3865 %} | |
| 3866 %} | |
| 3867 | |
| 3868 operand stackSlotD(sRegD reg) | |
| 3869 %{ | |
| 3870 constraint(ALLOC_IN_RC(stack_slots)); | |
| 3871 // No match rule because this operand is only generated in matching | |
| 3872 | |
| 3873 format %{ "[$reg]" %} | |
| 3874 interface(MEMORY_INTER) %{ | |
| 3875 base(0x4); // RSP | |
| 3876 index(0x4); // No Index | |
| 3877 scale(0x0); // No Scale | |
| 3878 disp($reg); // Stack Offset | |
| 3879 %} | |
| 3880 %} | |
| 3881 operand stackSlotL(sRegL reg) | |
| 3882 %{ | |
| 3883 constraint(ALLOC_IN_RC(stack_slots)); | |
| 3884 // No match rule because this operand is only generated in matching | |
| 3885 | |
| 3886 format %{ "[$reg]" %} | |
| 3887 interface(MEMORY_INTER) %{ | |
| 3888 base(0x4); // RSP | |
| 3889 index(0x4); // No Index | |
| 3890 scale(0x0); // No Scale | |
| 3891 disp($reg); // Stack Offset | |
| 3892 %} | |
| 3893 %} | |
| 3894 | |
| 3895 //----------Conditional Branch Operands---------------------------------------- | |
| 3896 // Comparison Op - This is the operation of the comparison, and is limited to | |
| 3897 // the following set of codes: | |
| 3898 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) | |
| 3899 // | |
| 3900 // Other attributes of the comparison, such as unsignedness, are specified | |
| 3901 // by the comparison instruction that sets a condition code flags register. | |
| 3902 // That result is represented by a flags operand whose subtype is appropriate | |
| 3903 // to the unsignedness (etc.) of the comparison. | |
| 3904 // | |
| 3905 // Later, the instruction which matches both the Comparison Op (a Bool) and | |
| 3906 // the flags (produced by the Cmp) specifies the coding of the comparison op | |
| 3907 // by matching a specific subtype of Bool operand below, such as cmpOpU. | |
| 3908 | |
| 3909 // Comparision Code | |
| 3910 operand cmpOp() | |
| 3911 %{ | |
| 3912 match(Bool); | |
| 3913 | |
| 3914 format %{ "" %} | |
| 3915 interface(COND_INTER) %{ | |
|
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3916 equal(0x4, "e"); |
|
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3917 not_equal(0x5, "ne"); |
|
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3918 less(0xC, "l"); |
|
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|
3919 greater_equal(0xD, "ge"); |
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3920 less_equal(0xE, "le"); |
|
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|
3921 greater(0xF, "g"); |
| 12323 | 3922 overflow(0x0, "o"); |
| 3923 no_overflow(0x1, "no"); | |
| 0 | 3924 %} |
| 3925 %} | |
| 3926 | |
| 3927 // Comparison Code, unsigned compare. Used by FP also, with | |
| 3928 // C2 (unordered) turned into GT or LT already. The other bits | |
| 3929 // C0 and C3 are turned into Carry & Zero flags. | |
| 3930 operand cmpOpU() | |
| 3931 %{ | |
| 3932 match(Bool); | |
| 3933 | |
| 3934 format %{ "" %} | |
| 3935 interface(COND_INTER) %{ | |
|
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|
3936 equal(0x4, "e"); |
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|
3937 not_equal(0x5, "ne"); |
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|
3938 less(0x2, "b"); |
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|
3939 greater_equal(0x3, "nb"); |
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|
3940 less_equal(0x6, "be"); |
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|
3941 greater(0x7, "nbe"); |
| 12323 | 3942 overflow(0x0, "o"); |
| 3943 no_overflow(0x1, "no"); | |
|
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3944 %} |
|
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|
3945 %} |
|
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|
3946 |
|
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|
3947 |
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|
3948 // Floating comparisons that don't require any fixup for the unordered case |
|
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3949 operand cmpOpUCF() %{ |
|
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3950 match(Bool); |
|
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|
3951 predicate(n->as_Bool()->_test._test == BoolTest::lt || |
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|
3952 n->as_Bool()->_test._test == BoolTest::ge || |
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|
3953 n->as_Bool()->_test._test == BoolTest::le || |
|
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|
3954 n->as_Bool()->_test._test == BoolTest::gt); |
|
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|
3955 format %{ "" %} |
|
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|
3956 interface(COND_INTER) %{ |
|
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|
3957 equal(0x4, "e"); |
|
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|
3958 not_equal(0x5, "ne"); |
|
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|
3959 less(0x2, "b"); |
|
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|
3960 greater_equal(0x3, "nb"); |
|
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|
3961 less_equal(0x6, "be"); |
|
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|
3962 greater(0x7, "nbe"); |
| 12323 | 3963 overflow(0x0, "o"); |
| 3964 no_overflow(0x1, "no"); | |
|
415
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|
3965 %} |
|
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|
3966 %} |
|
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|
3967 |
|
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|
3968 |
|
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|
3969 // Floating comparisons that can be fixed up with extra conditional jumps |
|
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|
3970 operand cmpOpUCF2() %{ |
|
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|
3971 match(Bool); |
|
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|
3972 predicate(n->as_Bool()->_test._test == BoolTest::ne || |
|
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|
3973 n->as_Bool()->_test._test == BoolTest::eq); |
|
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|
3974 format %{ "" %} |
|
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|
3975 interface(COND_INTER) %{ |
|
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|
3976 equal(0x4, "e"); |
|
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|
3977 not_equal(0x5, "ne"); |
|
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|
3978 less(0x2, "b"); |
|
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|
3979 greater_equal(0x3, "nb"); |
|
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|
3980 less_equal(0x6, "be"); |
|
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|
3981 greater(0x7, "nbe"); |
| 12323 | 3982 overflow(0x0, "o"); |
| 3983 no_overflow(0x1, "no"); | |
| 0 | 3984 %} |
| 3985 %} | |
| 3986 | |
| 3987 | |
| 3988 //----------OPERAND CLASSES---------------------------------------------------- | |
| 3989 // Operand Classes are groups of operands that are used as to simplify | |
| 605 | 3990 // instruction definitions by not requiring the AD writer to specify separate |
| 0 | 3991 // instructions for every form of operand when the instruction accepts |
| 3992 // multiple operand types with the same basic encoding and format. The classic | |
| 3993 // case of this is memory operands. | |
| 3994 | |
| 3995 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex, | |
|
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3996 indIndexScale, indIndexScaleOffset, indPosIndexScaleOffset, |
|
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3997 indCompressedOopOffset, |
|
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3998 indirectNarrow, indOffset8Narrow, indOffset32Narrow, |
|
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3999 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow, |
|
12056
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4000 indIndexScaleOffsetNarrow, indPosIndexScaleOffsetNarrow); |
| 0 | 4001 |
| 4002 //----------PIPELINE----------------------------------------------------------- | |
| 4003 // Rules which define the behavior of the target architectures pipeline. | |
| 4004 pipeline %{ | |
| 4005 | |
| 4006 //----------ATTRIBUTES--------------------------------------------------------- | |
| 4007 attributes %{ | |
| 4008 variable_size_instructions; // Fixed size instructions | |
| 4009 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle | |
| 4010 instruction_unit_size = 1; // An instruction is 1 bytes long | |
| 4011 instruction_fetch_unit_size = 16; // The processor fetches one line | |
| 4012 instruction_fetch_units = 1; // of 16 bytes | |
| 4013 | |
| 4014 // List of nop instructions | |
| 4015 nops( MachNop ); | |
| 4016 %} | |
| 4017 | |
| 4018 //----------RESOURCES---------------------------------------------------------- | |
| 4019 // Resources are the functional units available to the machine | |
| 4020 | |
| 4021 // Generic P2/P3 pipeline | |
| 4022 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of | |
| 4023 // 3 instructions decoded per cycle. | |
| 4024 // 2 load/store ops per cycle, 1 branch, 1 FPU, | |
| 4025 // 3 ALU op, only ALU0 handles mul instructions. | |
| 4026 resources( D0, D1, D2, DECODE = D0 | D1 | D2, | |
| 4027 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2, | |
| 4028 BR, FPU, | |
| 4029 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2); | |
| 4030 | |
| 4031 //----------PIPELINE DESCRIPTION----------------------------------------------- | |
| 4032 // Pipeline Description specifies the stages in the machine's pipeline | |
| 4033 | |
| 4034 // Generic P2/P3 pipeline | |
| 4035 pipe_desc(S0, S1, S2, S3, S4, S5); | |
| 4036 | |
| 4037 //----------PIPELINE CLASSES--------------------------------------------------- | |
| 4038 // Pipeline Classes describe the stages in which input and output are | |
| 4039 // referenced by the hardware pipeline. | |
| 4040 | |
| 4041 // Naming convention: ialu or fpu | |
| 4042 // Then: _reg | |
| 4043 // Then: _reg if there is a 2nd register | |
| 4044 // Then: _long if it's a pair of instructions implementing a long | |
| 4045 // Then: _fat if it requires the big decoder | |
| 4046 // Or: _mem if it requires the big decoder and a memory unit. | |
| 4047 | |
| 4048 // Integer ALU reg operation | |
| 4049 pipe_class ialu_reg(rRegI dst) | |
| 4050 %{ | |
| 4051 single_instruction; | |
| 4052 dst : S4(write); | |
| 4053 dst : S3(read); | |
| 4054 DECODE : S0; // any decoder | |
| 4055 ALU : S3; // any alu | |
| 4056 %} | |
| 4057 | |
| 4058 // Long ALU reg operation | |
| 4059 pipe_class ialu_reg_long(rRegL dst) | |
| 4060 %{ | |
| 4061 instruction_count(2); | |
| 4062 dst : S4(write); | |
| 4063 dst : S3(read); | |
| 4064 DECODE : S0(2); // any 2 decoders | |
| 4065 ALU : S3(2); // both alus | |
| 4066 %} | |
| 4067 | |
| 4068 // Integer ALU reg operation using big decoder | |
| 4069 pipe_class ialu_reg_fat(rRegI dst) | |
| 4070 %{ | |
| 4071 single_instruction; | |
| 4072 dst : S4(write); | |
| 4073 dst : S3(read); | |
| 4074 D0 : S0; // big decoder only | |
| 4075 ALU : S3; // any alu | |
| 4076 %} | |
| 4077 | |
| 4078 // Long ALU reg operation using big decoder | |
| 4079 pipe_class ialu_reg_long_fat(rRegL dst) | |
| 4080 %{ | |
| 4081 instruction_count(2); | |
| 4082 dst : S4(write); | |
| 4083 dst : S3(read); | |
| 4084 D0 : S0(2); // big decoder only; twice | |
| 4085 ALU : S3(2); // any 2 alus | |
| 4086 %} | |
| 4087 | |
| 4088 // Integer ALU reg-reg operation | |
| 4089 pipe_class ialu_reg_reg(rRegI dst, rRegI src) | |
| 4090 %{ | |
| 4091 single_instruction; | |
| 4092 dst : S4(write); | |
| 4093 src : S3(read); | |
| 4094 DECODE : S0; // any decoder | |
| 4095 ALU : S3; // any alu | |
| 4096 %} | |
| 4097 | |
| 4098 // Long ALU reg-reg operation | |
| 4099 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src) | |
| 4100 %{ | |
| 4101 instruction_count(2); | |
| 4102 dst : S4(write); | |
| 4103 src : S3(read); | |
| 4104 DECODE : S0(2); // any 2 decoders | |
| 4105 ALU : S3(2); // both alus | |
| 4106 %} | |
| 4107 | |
| 4108 // Integer ALU reg-reg operation | |
| 4109 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) | |
| 4110 %{ | |
| 4111 single_instruction; | |
| 4112 dst : S4(write); | |
| 4113 src : S3(read); | |
| 4114 D0 : S0; // big decoder only | |
| 4115 ALU : S3; // any alu | |
| 4116 %} | |
| 4117 | |
| 4118 // Long ALU reg-reg operation | |
| 4119 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src) | |
| 4120 %{ | |
| 4121 instruction_count(2); | |
| 4122 dst : S4(write); | |
| 4123 src : S3(read); | |
| 4124 D0 : S0(2); // big decoder only; twice | |
| 4125 ALU : S3(2); // both alus | |
| 4126 %} | |
| 4127 | |
| 4128 // Integer ALU reg-mem operation | |
| 4129 pipe_class ialu_reg_mem(rRegI dst, memory mem) | |
| 4130 %{ | |
| 4131 single_instruction; | |
| 4132 dst : S5(write); | |
| 4133 mem : S3(read); | |
| 4134 D0 : S0; // big decoder only | |
| 4135 ALU : S4; // any alu | |
| 4136 MEM : S3; // any mem | |
| 4137 %} | |
| 4138 | |
| 4139 // Integer mem operation (prefetch) | |
| 4140 pipe_class ialu_mem(memory mem) | |
| 4141 %{ | |
| 4142 single_instruction; | |
| 4143 mem : S3(read); | |
| 4144 D0 : S0; // big decoder only | |
| 4145 MEM : S3; // any mem | |
| 4146 %} | |
| 4147 | |
| 4148 // Integer Store to Memory | |
| 4149 pipe_class ialu_mem_reg(memory mem, rRegI src) | |
| 4150 %{ | |
| 4151 single_instruction; | |
| 4152 mem : S3(read); | |
| 4153 src : S5(read); | |
| 4154 D0 : S0; // big decoder only | |
| 4155 ALU : S4; // any alu | |
| 4156 MEM : S3; | |
| 4157 %} | |
| 4158 | |
| 4159 // // Long Store to Memory | |
| 4160 // pipe_class ialu_mem_long_reg(memory mem, rRegL src) | |
| 4161 // %{ | |
| 4162 // instruction_count(2); | |
| 4163 // mem : S3(read); | |
| 4164 // src : S5(read); | |
| 4165 // D0 : S0(2); // big decoder only; twice | |
| 4166 // ALU : S4(2); // any 2 alus | |
| 4167 // MEM : S3(2); // Both mems | |
| 4168 // %} | |
| 4169 | |
| 4170 // Integer Store to Memory | |
| 4171 pipe_class ialu_mem_imm(memory mem) | |
| 4172 %{ | |
| 4173 single_instruction; | |
| 4174 mem : S3(read); | |
| 4175 D0 : S0; // big decoder only | |
| 4176 ALU : S4; // any alu | |
| 4177 MEM : S3; | |
| 4178 %} | |
| 4179 | |
| 4180 // Integer ALU0 reg-reg operation | |
| 4181 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) | |
| 4182 %{ | |
| 4183 single_instruction; | |
| 4184 dst : S4(write); | |
| 4185 src : S3(read); | |
| 4186 D0 : S0; // Big decoder only | |
| 4187 ALU0 : S3; // only alu0 | |
| 4188 %} | |
| 4189 | |
| 4190 // Integer ALU0 reg-mem operation | |
| 4191 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) | |
| 4192 %{ | |
| 4193 single_instruction; | |
| 4194 dst : S5(write); | |
| 4195 mem : S3(read); | |
| 4196 D0 : S0; // big decoder only | |
| 4197 ALU0 : S4; // ALU0 only | |
| 4198 MEM : S3; // any mem | |
| 4199 %} | |
| 4200 | |
| 4201 // Integer ALU reg-reg operation | |
| 4202 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2) | |
| 4203 %{ | |
| 4204 single_instruction; | |
| 4205 cr : S4(write); | |
| 4206 src1 : S3(read); | |
| 4207 src2 : S3(read); | |
| 4208 DECODE : S0; // any decoder | |
| 4209 ALU : S3; // any alu | |
| 4210 %} | |
| 4211 | |
| 4212 // Integer ALU reg-imm operation | |
| 4213 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1) | |
| 4214 %{ | |
| 4215 single_instruction; | |
| 4216 cr : S4(write); | |
| 4217 src1 : S3(read); | |
| 4218 DECODE : S0; // any decoder | |
| 4219 ALU : S3; // any alu | |
| 4220 %} | |
| 4221 | |
| 4222 // Integer ALU reg-mem operation | |
| 4223 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2) | |
| 4224 %{ | |
| 4225 single_instruction; | |
| 4226 cr : S4(write); | |
| 4227 src1 : S3(read); | |
| 4228 src2 : S3(read); | |
| 4229 D0 : S0; // big decoder only | |
| 4230 ALU : S4; // any alu | |
| 4231 MEM : S3; | |
| 4232 %} | |
| 4233 | |
| 4234 // Conditional move reg-reg | |
| 4235 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y) | |
| 4236 %{ | |
| 4237 instruction_count(4); | |
| 4238 y : S4(read); | |
| 4239 q : S3(read); | |
| 4240 p : S3(read); | |
| 4241 DECODE : S0(4); // any decoder | |
| 4242 %} | |
| 4243 | |
| 4244 // Conditional move reg-reg | |
| 4245 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr) | |
| 4246 %{ | |
| 4247 single_instruction; | |
| 4248 dst : S4(write); | |
| 4249 src : S3(read); | |
| 4250 cr : S3(read); | |
| 4251 DECODE : S0; // any decoder | |
| 4252 %} | |
| 4253 | |
| 4254 // Conditional move reg-mem | |
| 4255 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src) | |
| 4256 %{ | |
| 4257 single_instruction; | |
| 4258 dst : S4(write); | |
| 4259 src : S3(read); | |
| 4260 cr : S3(read); | |
| 4261 DECODE : S0; // any decoder | |
| 4262 MEM : S3; | |
| 4263 %} | |
| 4264 | |
| 4265 // Conditional move reg-reg long | |
| 4266 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src) | |
| 4267 %{ | |
| 4268 single_instruction; | |
| 4269 dst : S4(write); | |
| 4270 src : S3(read); | |
| 4271 cr : S3(read); | |
| 4272 DECODE : S0(2); // any 2 decoders | |
| 4273 %} | |
| 4274 | |
| 4275 // XXX | |
| 4276 // // Conditional move double reg-reg | |
| 4277 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src) | |
| 4278 // %{ | |
| 4279 // single_instruction; | |
| 4280 // dst : S4(write); | |
| 4281 // src : S3(read); | |
| 4282 // cr : S3(read); | |
| 4283 // DECODE : S0; // any decoder | |
| 4284 // %} | |
| 4285 | |
| 4286 // Float reg-reg operation | |
| 4287 pipe_class fpu_reg(regD dst) | |
| 4288 %{ | |
| 4289 instruction_count(2); | |
| 4290 dst : S3(read); | |
| 4291 DECODE : S0(2); // any 2 decoders | |
| 4292 FPU : S3; | |
| 4293 %} | |
| 4294 | |
| 4295 // Float reg-reg operation | |
| 4296 pipe_class fpu_reg_reg(regD dst, regD src) | |
| 4297 %{ | |
| 4298 instruction_count(2); | |
| 4299 dst : S4(write); | |
| 4300 src : S3(read); | |
| 4301 DECODE : S0(2); // any 2 decoders | |
| 4302 FPU : S3; | |
| 4303 %} | |
| 4304 | |
| 4305 // Float reg-reg operation | |
| 4306 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2) | |
| 4307 %{ | |
| 4308 instruction_count(3); | |
| 4309 dst : S4(write); | |
| 4310 src1 : S3(read); | |
| 4311 src2 : S3(read); | |
| 4312 DECODE : S0(3); // any 3 decoders | |
| 4313 FPU : S3(2); | |
| 4314 %} | |
| 4315 | |
| 4316 // Float reg-reg operation | |
| 4317 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3) | |
| 4318 %{ | |
| 4319 instruction_count(4); | |
| 4320 dst : S4(write); | |
| 4321 src1 : S3(read); | |
| 4322 src2 : S3(read); | |
| 4323 src3 : S3(read); | |
| 4324 DECODE : S0(4); // any 3 decoders | |
| 4325 FPU : S3(2); | |
| 4326 %} | |
| 4327 | |
| 4328 // Float reg-reg operation | |
| 4329 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3) | |
| 4330 %{ | |
| 4331 instruction_count(4); | |
| 4332 dst : S4(write); | |
| 4333 src1 : S3(read); | |
| 4334 src2 : S3(read); | |
| 4335 src3 : S3(read); | |
| 4336 DECODE : S1(3); // any 3 decoders | |
| 4337 D0 : S0; // Big decoder only | |
| 4338 FPU : S3(2); | |
| 4339 MEM : S3; | |
| 4340 %} | |
| 4341 | |
| 4342 // Float reg-mem operation | |
| 4343 pipe_class fpu_reg_mem(regD dst, memory mem) | |
| 4344 %{ | |
| 4345 instruction_count(2); | |
| 4346 dst : S5(write); | |
| 4347 mem : S3(read); | |
| 4348 D0 : S0; // big decoder only | |
| 4349 DECODE : S1; // any decoder for FPU POP | |
| 4350 FPU : S4; | |
| 4351 MEM : S3; // any mem | |
| 4352 %} | |
| 4353 | |
| 4354 // Float reg-mem operation | |
| 4355 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem) | |
| 4356 %{ | |
| 4357 instruction_count(3); | |
| 4358 dst : S5(write); | |
| 4359 src1 : S3(read); | |
| 4360 mem : S3(read); | |
| 4361 D0 : S0; // big decoder only | |
| 4362 DECODE : S1(2); // any decoder for FPU POP | |
| 4363 FPU : S4; | |
| 4364 MEM : S3; // any mem | |
| 4365 %} | |
| 4366 | |
| 4367 // Float mem-reg operation | |
| 4368 pipe_class fpu_mem_reg(memory mem, regD src) | |
| 4369 %{ | |
| 4370 instruction_count(2); | |
| 4371 src : S5(read); | |
| 4372 mem : S3(read); | |
| 4373 DECODE : S0; // any decoder for FPU PUSH | |
| 4374 D0 : S1; // big decoder only | |
| 4375 FPU : S4; | |
| 4376 MEM : S3; // any mem | |
| 4377 %} | |
| 4378 | |
| 4379 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2) | |
| 4380 %{ | |
| 4381 instruction_count(3); | |
| 4382 src1 : S3(read); | |
| 4383 src2 : S3(read); | |
| 4384 mem : S3(read); | |
| 4385 DECODE : S0(2); // any decoder for FPU PUSH | |
| 4386 D0 : S1; // big decoder only | |
| 4387 FPU : S4; | |
| 4388 MEM : S3; // any mem | |
| 4389 %} | |
| 4390 | |
| 4391 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2) | |
| 4392 %{ | |
| 4393 instruction_count(3); | |
| 4394 src1 : S3(read); | |
| 4395 src2 : S3(read); | |
| 4396 mem : S4(read); | |
| 4397 DECODE : S0; // any decoder for FPU PUSH | |
| 4398 D0 : S0(2); // big decoder only | |
| 4399 FPU : S4; | |
| 4400 MEM : S3(2); // any mem | |
| 4401 %} | |
| 4402 | |
| 4403 pipe_class fpu_mem_mem(memory dst, memory src1) | |
| 4404 %{ | |
| 4405 instruction_count(2); | |
| 4406 src1 : S3(read); | |
| 4407 dst : S4(read); | |
| 4408 D0 : S0(2); // big decoder only | |
| 4409 MEM : S3(2); // any mem | |
| 4410 %} | |
| 4411 | |
| 4412 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) | |
| 4413 %{ | |
| 4414 instruction_count(3); | |
| 4415 src1 : S3(read); | |
| 4416 src2 : S3(read); | |
| 4417 dst : S4(read); | |
| 4418 D0 : S0(3); // big decoder only | |
| 4419 FPU : S4; | |
| 4420 MEM : S3(3); // any mem | |
| 4421 %} | |
| 4422 | |
| 4423 pipe_class fpu_mem_reg_con(memory mem, regD src1) | |
| 4424 %{ | |
| 4425 instruction_count(3); | |
| 4426 src1 : S4(read); | |
| 4427 mem : S4(read); | |
| 4428 DECODE : S0; // any decoder for FPU PUSH | |
| 4429 D0 : S0(2); // big decoder only | |
| 4430 FPU : S4; | |
| 4431 MEM : S3(2); // any mem | |
| 4432 %} | |
| 4433 | |
| 4434 // Float load constant | |
| 4435 pipe_class fpu_reg_con(regD dst) | |
| 4436 %{ | |
| 4437 instruction_count(2); | |
| 4438 dst : S5(write); | |
| 4439 D0 : S0; // big decoder only for the load | |
| 4440 DECODE : S1; // any decoder for FPU POP | |
| 4441 FPU : S4; | |
| 4442 MEM : S3; // any mem | |
| 4443 %} | |
| 4444 | |
| 4445 // Float load constant | |
| 4446 pipe_class fpu_reg_reg_con(regD dst, regD src) | |
| 4447 %{ | |
| 4448 instruction_count(3); | |
| 4449 dst : S5(write); | |
| 4450 src : S3(read); | |
| 4451 D0 : S0; // big decoder only for the load | |
| 4452 DECODE : S1(2); // any decoder for FPU POP | |
| 4453 FPU : S4; | |
| 4454 MEM : S3; // any mem | |
| 4455 %} | |
| 4456 | |
| 4457 // UnConditional branch | |
| 4458 pipe_class pipe_jmp(label labl) | |
| 4459 %{ | |
| 4460 single_instruction; | |
| 4461 BR : S3; | |
| 4462 %} | |
| 4463 | |
| 4464 // Conditional branch | |
| 4465 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl) | |
| 4466 %{ | |
| 4467 single_instruction; | |
| 4468 cr : S1(read); | |
| 4469 BR : S3; | |
| 4470 %} | |
| 4471 | |
| 4472 // Allocation idiom | |
| 4473 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr) | |
| 4474 %{ | |
| 4475 instruction_count(1); force_serialization; | |
| 4476 fixed_latency(6); | |
| 4477 heap_ptr : S3(read); | |
| 4478 DECODE : S0(3); | |
| 4479 D0 : S2; | |
| 4480 MEM : S3; | |
| 4481 ALU : S3(2); | |
| 4482 dst : S5(write); | |
| 4483 BR : S5; | |
| 4484 %} | |
| 4485 | |
| 4486 // Generic big/slow expanded idiom | |
| 4487 pipe_class pipe_slow() | |
| 4488 %{ | |
| 4489 instruction_count(10); multiple_bundles; force_serialization; | |
| 4490 fixed_latency(100); | |
| 4491 D0 : S0(2); | |
| 4492 MEM : S3(2); | |
| 4493 %} | |
| 4494 | |
| 4495 // The real do-nothing guy | |
| 4496 pipe_class empty() | |
| 4497 %{ | |
| 4498 instruction_count(0); | |
| 4499 %} | |
| 4500 | |
| 4501 // Define the class for the Nop node | |
| 4502 define | |
| 4503 %{ | |
| 4504 MachNop = empty; | |
| 4505 %} | |
| 4506 | |
| 4507 %} | |
| 4508 | |
| 4509 //----------INSTRUCTIONS------------------------------------------------------- | |
| 4510 // | |
| 4511 // match -- States which machine-independent subtree may be replaced | |
| 4512 // by this instruction. | |
| 4513 // ins_cost -- The estimated cost of this instruction is used by instruction | |
| 4514 // selection to identify a minimum cost tree of machine | |
| 4515 // instructions that matches a tree of machine-independent | |
| 4516 // instructions. | |
| 4517 // format -- A string providing the disassembly for this instruction. | |
| 4518 // The value of an instruction's operand may be inserted | |
| 4519 // by referring to it with a '$' prefix. | |
| 4520 // opcode -- Three instruction opcodes may be provided. These are referred | |
| 4521 // to within an encode class as $primary, $secondary, and $tertiary | |
| 4522 // rrspectively. The primary opcode is commonly used to | |
| 4523 // indicate the type of machine instruction, while secondary | |
| 4524 // and tertiary are often used for prefix options or addressing | |
| 4525 // modes. | |
| 4526 // ins_encode -- A list of encode classes with parameters. The encode class | |
| 4527 // name must have been defined in an 'enc_class' specification | |
| 4528 // in the encode section of the architecture description. | |
| 4529 | |
| 4530 | |
| 4531 //----------Load/Store/Move Instructions--------------------------------------- | |
| 4532 //----------Load Instructions-------------------------------------------------- | |
| 4533 | |
| 4534 // Load Byte (8 bit signed) | |
| 4535 instruct loadB(rRegI dst, memory mem) | |
| 4536 %{ | |
| 4537 match(Set dst (LoadB mem)); | |
| 4538 | |
| 4539 ins_cost(125); | |
| 4540 format %{ "movsbl $dst, $mem\t# byte" %} | |
| 624 | 4541 |
| 4542 ins_encode %{ | |
| 4543 __ movsbl($dst$$Register, $mem$$Address); | |
| 4544 %} | |
| 4545 | |
| 0 | 4546 ins_pipe(ialu_reg_mem); |
| 4547 %} | |
| 4548 | |
| 624 | 4549 // Load Byte (8 bit signed) into Long Register |
| 4550 instruct loadB2L(rRegL dst, memory mem) | |
| 4551 %{ | |
| 4552 match(Set dst (ConvI2L (LoadB mem))); | |
| 4553 | |
| 4554 ins_cost(125); | |
| 4555 format %{ "movsbq $dst, $mem\t# byte -> long" %} | |
| 4556 | |
| 4557 ins_encode %{ | |
| 4558 __ movsbq($dst$$Register, $mem$$Address); | |
| 4559 %} | |
| 4560 | |
| 4561 ins_pipe(ialu_reg_mem); | |
| 4562 %} | |
| 4563 | |
| 4564 // Load Unsigned Byte (8 bit UNsigned) | |
| 4565 instruct loadUB(rRegI dst, memory mem) | |
| 4566 %{ | |
| 4567 match(Set dst (LoadUB mem)); | |
| 0 | 4568 |
| 4569 ins_cost(125); | |
| 4570 format %{ "movzbl $dst, $mem\t# ubyte" %} | |
| 624 | 4571 |
| 4572 ins_encode %{ | |
| 4573 __ movzbl($dst$$Register, $mem$$Address); | |
| 4574 %} | |
| 4575 | |
| 0 | 4576 ins_pipe(ialu_reg_mem); |
| 4577 %} | |
| 4578 | |
| 624 | 4579 // Load Unsigned Byte (8 bit UNsigned) into Long Register |
| 4580 instruct loadUB2L(rRegL dst, memory mem) | |
| 4581 %{ | |
| 4582 match(Set dst (ConvI2L (LoadUB mem))); | |
| 4583 | |
| 4584 ins_cost(125); | |
| 4585 format %{ "movzbq $dst, $mem\t# ubyte -> long" %} | |
| 4586 | |
| 4587 ins_encode %{ | |
| 4588 __ movzbq($dst$$Register, $mem$$Address); | |
| 4589 %} | |
| 4590 | |
| 4591 ins_pipe(ialu_reg_mem); | |
| 4592 %} | |
| 0 | 4593 |
| 824 | 4594 // Load Unsigned Byte (8 bit UNsigned) with a 8-bit mask into Long Register |
| 4595 instruct loadUB2L_immI8(rRegL dst, memory mem, immI8 mask, rFlagsReg cr) %{ | |
| 4596 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); | |
| 4597 effect(KILL cr); | |
| 4598 | |
| 4599 format %{ "movzbq $dst, $mem\t# ubyte & 8-bit mask -> long\n\t" | |
| 4600 "andl $dst, $mask" %} | |
| 4601 ins_encode %{ | |
| 4602 Register Rdst = $dst$$Register; | |
| 4603 __ movzbq(Rdst, $mem$$Address); | |
| 4604 __ andl(Rdst, $mask$$constant); | |
| 4605 %} | |
| 4606 ins_pipe(ialu_reg_mem); | |
| 4607 %} | |
| 4608 | |
| 0 | 4609 // Load Short (16 bit signed) |
| 4610 instruct loadS(rRegI dst, memory mem) | |
| 4611 %{ | |
| 4612 match(Set dst (LoadS mem)); | |
| 4613 | |
| 624 | 4614 ins_cost(125); |
| 0 | 4615 format %{ "movswl $dst, $mem\t# short" %} |
| 624 | 4616 |
| 4617 ins_encode %{ | |
| 4618 __ movswl($dst$$Register, $mem$$Address); | |
| 4619 %} | |
| 4620 | |
| 0 | 4621 ins_pipe(ialu_reg_mem); |
| 4622 %} | |
| 4623 | |
| 785 | 4624 // Load Short (16 bit signed) to Byte (8 bit signed) |
| 4625 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{ | |
| 4626 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); | |
| 4627 | |
| 4628 ins_cost(125); | |
| 4629 format %{ "movsbl $dst, $mem\t# short -> byte" %} | |
| 4630 ins_encode %{ | |
| 4631 __ movsbl($dst$$Register, $mem$$Address); | |
| 4632 %} | |
| 4633 ins_pipe(ialu_reg_mem); | |
| 4634 %} | |
| 4635 | |
| 624 | 4636 // Load Short (16 bit signed) into Long Register |
| 4637 instruct loadS2L(rRegL dst, memory mem) | |
| 4638 %{ | |
| 4639 match(Set dst (ConvI2L (LoadS mem))); | |
| 4640 | |
| 4641 ins_cost(125); | |
| 4642 format %{ "movswq $dst, $mem\t# short -> long" %} | |
| 4643 | |
| 4644 ins_encode %{ | |
| 4645 __ movswq($dst$$Register, $mem$$Address); | |
| 4646 %} | |
| 4647 | |
| 4648 ins_pipe(ialu_reg_mem); | |
| 4649 %} | |
| 0 | 4650 |
|
558
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
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parents:
420
diff
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|
4651 // Load Unsigned Short/Char (16 bit UNsigned) |
|
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
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parents:
420
diff
changeset
|
4652 instruct loadUS(rRegI dst, memory mem) |
|
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents:
420
diff
changeset
|
4653 %{ |
|
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents:
420
diff
changeset
|
4654 match(Set dst (LoadUS mem)); |
| 0 | 4655 |
| 4656 ins_cost(125); | |
|
558
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents:
420
diff
changeset
|
4657 format %{ "movzwl $dst, $mem\t# ushort/char" %} |
| 624 | 4658 |
| 4659 ins_encode %{ | |
| 4660 __ movzwl($dst$$Register, $mem$$Address); | |
| 4661 %} | |
| 4662 | |
| 0 | 4663 ins_pipe(ialu_reg_mem); |
| 4664 %} | |
| 4665 | |
| 785 | 4666 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) |
| 4667 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{ | |
| 4668 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); | |
| 4669 | |
| 4670 ins_cost(125); | |
| 4671 format %{ "movsbl $dst, $mem\t# ushort -> byte" %} | |
| 4672 ins_encode %{ | |
| 4673 __ movsbl($dst$$Register, $mem$$Address); | |
| 4674 %} | |
| 4675 ins_pipe(ialu_reg_mem); | |
| 4676 %} | |
| 4677 | |
| 624 | 4678 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register |
| 4679 instruct loadUS2L(rRegL dst, memory mem) | |
| 4680 %{ | |
| 4681 match(Set dst (ConvI2L (LoadUS mem))); | |
| 4682 | |
| 4683 ins_cost(125); | |
| 4684 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %} | |
| 4685 | |
| 4686 ins_encode %{ | |
| 4687 __ movzwq($dst$$Register, $mem$$Address); | |
| 4688 %} | |
| 4689 | |
| 4690 ins_pipe(ialu_reg_mem); | |
| 4691 %} | |
| 0 | 4692 |
| 824 | 4693 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register |
| 4694 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{ | |
| 4695 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 4696 | |
| 4697 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %} | |
| 4698 ins_encode %{ | |
| 4699 __ movzbq($dst$$Register, $mem$$Address); | |
| 4700 %} | |
| 4701 ins_pipe(ialu_reg_mem); | |
| 4702 %} | |
| 4703 | |
| 4704 // Load Unsigned Short/Char (16 bit UNsigned) with mask into Long Register | |
| 4705 instruct loadUS2L_immI16(rRegL dst, memory mem, immI16 mask, rFlagsReg cr) %{ | |
| 4706 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 4707 effect(KILL cr); | |
| 4708 | |
| 4709 format %{ "movzwq $dst, $mem\t# ushort/char & 16-bit mask -> long\n\t" | |
| 4710 "andl $dst, $mask" %} | |
| 4711 ins_encode %{ | |
| 4712 Register Rdst = $dst$$Register; | |
| 4713 __ movzwq(Rdst, $mem$$Address); | |
| 4714 __ andl(Rdst, $mask$$constant); | |
| 4715 %} | |
| 4716 ins_pipe(ialu_reg_mem); | |
| 4717 %} | |
| 4718 | |
| 0 | 4719 // Load Integer |
| 4720 instruct loadI(rRegI dst, memory mem) | |
| 4721 %{ | |
| 4722 match(Set dst (LoadI mem)); | |
| 4723 | |
| 624 | 4724 ins_cost(125); |
| 0 | 4725 format %{ "movl $dst, $mem\t# int" %} |
| 624 | 4726 |
| 4727 ins_encode %{ | |
| 4728 __ movl($dst$$Register, $mem$$Address); | |
| 4729 %} | |
| 4730 | |
| 4731 ins_pipe(ialu_reg_mem); | |
| 4732 %} | |
| 4733 | |
| 785 | 4734 // Load Integer (32 bit signed) to Byte (8 bit signed) |
| 4735 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{ | |
| 4736 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); | |
| 4737 | |
| 4738 ins_cost(125); | |
| 4739 format %{ "movsbl $dst, $mem\t# int -> byte" %} | |
| 4740 ins_encode %{ | |
| 4741 __ movsbl($dst$$Register, $mem$$Address); | |
| 4742 %} | |
| 4743 ins_pipe(ialu_reg_mem); | |
| 4744 %} | |
| 4745 | |
| 4746 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned) | |
| 4747 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{ | |
| 4748 match(Set dst (AndI (LoadI mem) mask)); | |
| 4749 | |
| 4750 ins_cost(125); | |
| 4751 format %{ "movzbl $dst, $mem\t# int -> ubyte" %} | |
| 4752 ins_encode %{ | |
| 4753 __ movzbl($dst$$Register, $mem$$Address); | |
| 4754 %} | |
| 4755 ins_pipe(ialu_reg_mem); | |
| 4756 %} | |
| 4757 | |
| 4758 // Load Integer (32 bit signed) to Short (16 bit signed) | |
| 4759 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{ | |
| 4760 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); | |
| 4761 | |
| 4762 ins_cost(125); | |
| 4763 format %{ "movswl $dst, $mem\t# int -> short" %} | |
| 4764 ins_encode %{ | |
| 4765 __ movswl($dst$$Register, $mem$$Address); | |
| 4766 %} | |
| 4767 ins_pipe(ialu_reg_mem); | |
| 4768 %} | |
| 4769 | |
| 4770 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned) | |
| 4771 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{ | |
| 4772 match(Set dst (AndI (LoadI mem) mask)); | |
| 4773 | |
| 4774 ins_cost(125); | |
| 4775 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %} | |
| 4776 ins_encode %{ | |
| 4777 __ movzwl($dst$$Register, $mem$$Address); | |
| 4778 %} | |
| 4779 ins_pipe(ialu_reg_mem); | |
| 4780 %} | |
| 4781 | |
| 624 | 4782 // Load Integer into Long Register |
| 4783 instruct loadI2L(rRegL dst, memory mem) | |
| 4784 %{ | |
| 4785 match(Set dst (ConvI2L (LoadI mem))); | |
| 4786 | |
| 4787 ins_cost(125); | |
| 4788 format %{ "movslq $dst, $mem\t# int -> long" %} | |
| 4789 | |
| 4790 ins_encode %{ | |
| 4791 __ movslq($dst$$Register, $mem$$Address); | |
| 4792 %} | |
| 4793 | |
| 4794 ins_pipe(ialu_reg_mem); | |
| 4795 %} | |
| 4796 | |
| 824 | 4797 // Load Integer with mask 0xFF into Long Register |
| 4798 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{ | |
| 4799 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 4800 | |
| 4801 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %} | |
| 4802 ins_encode %{ | |
| 4803 __ movzbq($dst$$Register, $mem$$Address); | |
| 4804 %} | |
| 4805 ins_pipe(ialu_reg_mem); | |
| 4806 %} | |
| 4807 | |
| 4808 // Load Integer with mask 0xFFFF into Long Register | |
| 4809 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{ | |
| 4810 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 4811 | |
| 4812 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %} | |
| 4813 ins_encode %{ | |
| 4814 __ movzwq($dst$$Register, $mem$$Address); | |
| 4815 %} | |
| 4816 ins_pipe(ialu_reg_mem); | |
| 4817 %} | |
| 4818 | |
|
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|
4819 // Load Integer with a 31-bit mask into Long Register |
|
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|
4820 instruct loadI2L_immU31(rRegL dst, memory mem, immU31 mask, rFlagsReg cr) %{ |
| 824 | 4821 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); |
| 4822 effect(KILL cr); | |
| 4823 | |
|
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|
4824 format %{ "movl $dst, $mem\t# int & 31-bit mask -> long\n\t" |
| 824 | 4825 "andl $dst, $mask" %} |
| 4826 ins_encode %{ | |
| 4827 Register Rdst = $dst$$Register; | |
| 4828 __ movl(Rdst, $mem$$Address); | |
| 4829 __ andl(Rdst, $mask$$constant); | |
| 4830 %} | |
| 4831 ins_pipe(ialu_reg_mem); | |
| 4832 %} | |
| 4833 | |
| 624 | 4834 // Load Unsigned Integer into Long Register |
| 6849 | 4835 instruct loadUI2L(rRegL dst, memory mem, immL_32bits mask) |
| 4836 %{ | |
| 4837 match(Set dst (AndL (ConvI2L (LoadI mem)) mask)); | |
| 624 | 4838 |
| 4839 ins_cost(125); | |
| 4840 format %{ "movl $dst, $mem\t# uint -> long" %} | |
| 4841 | |
| 4842 ins_encode %{ | |
| 4843 __ movl($dst$$Register, $mem$$Address); | |
| 4844 %} | |
| 4845 | |
| 0 | 4846 ins_pipe(ialu_reg_mem); |
| 4847 %} | |
| 4848 | |
| 4849 // Load Long | |
| 4850 instruct loadL(rRegL dst, memory mem) | |
| 4851 %{ | |
| 4852 match(Set dst (LoadL mem)); | |
| 4853 | |
| 624 | 4854 ins_cost(125); |
| 0 | 4855 format %{ "movq $dst, $mem\t# long" %} |
| 624 | 4856 |
| 4857 ins_encode %{ | |
| 4858 __ movq($dst$$Register, $mem$$Address); | |
| 4859 %} | |
| 4860 | |
| 0 | 4861 ins_pipe(ialu_reg_mem); // XXX |
| 4862 %} | |
| 4863 | |
| 4864 // Load Range | |
| 4865 instruct loadRange(rRegI dst, memory mem) | |
| 4866 %{ | |
| 4867 match(Set dst (LoadRange mem)); | |
| 4868 | |
| 4869 ins_cost(125); // XXX | |
| 4870 format %{ "movl $dst, $mem\t# range" %} | |
| 4871 opcode(0x8B); | |
| 4872 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 4873 ins_pipe(ialu_reg_mem); | |
| 4874 %} | |
| 4875 | |
| 4876 // Load Pointer | |
| 4877 instruct loadP(rRegP dst, memory mem) | |
| 4878 %{ | |
| 4879 match(Set dst (LoadP mem)); | |
| 4880 | |
| 4881 ins_cost(125); // XXX | |
| 4882 format %{ "movq $dst, $mem\t# ptr" %} | |
| 4883 opcode(0x8B); | |
| 4884 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 4885 ins_pipe(ialu_reg_mem); // XXX | |
| 4886 %} | |
| 4887 | |
|
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4888 // Load Compressed Pointer |
| 163 | 4889 instruct loadN(rRegN dst, memory mem) |
|
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4890 %{ |
|
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|
4891 match(Set dst (LoadN mem)); |
|
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|
4892 |
|
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|
4893 ins_cost(125); // XXX |
|
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4894 format %{ "movl $dst, $mem\t# compressed ptr" %} |
|
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4895 ins_encode %{ |
|
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4896 __ movl($dst$$Register, $mem$$Address); |
|
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4897 %} |
|
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|
4898 ins_pipe(ialu_reg_mem); // XXX |
|
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4899 %} |
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4900 |
|
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4901 |
| 0 | 4902 // Load Klass Pointer |
| 4903 instruct loadKlass(rRegP dst, memory mem) | |
| 4904 %{ | |
| 4905 match(Set dst (LoadKlass mem)); | |
| 4906 | |
| 4907 ins_cost(125); // XXX | |
| 4908 format %{ "movq $dst, $mem\t# class" %} | |
| 4909 opcode(0x8B); | |
| 4910 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 4911 ins_pipe(ialu_reg_mem); // XXX | |
| 4912 %} | |
| 4913 | |
|
164
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|
4914 // Load narrow Klass Pointer |
|
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|
4915 instruct loadNKlass(rRegN dst, memory mem) |
|
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4916 %{ |
|
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4917 match(Set dst (LoadNKlass mem)); |
|
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4918 |
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|
4919 ins_cost(125); // XXX |
|
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4920 format %{ "movl $dst, $mem\t# compressed klass ptr" %} |
|
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4921 ins_encode %{ |
|
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4922 __ movl($dst$$Register, $mem$$Address); |
|
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4923 %} |
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|
4924 ins_pipe(ialu_reg_mem); // XXX |
|
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4925 %} |
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4926 |
| 0 | 4927 // Load Float |
| 4928 instruct loadF(regF dst, memory mem) | |
| 4929 %{ | |
| 4930 match(Set dst (LoadF mem)); | |
| 4931 | |
| 4932 ins_cost(145); // XXX | |
| 4933 format %{ "movss $dst, $mem\t# float" %} | |
| 4759 | 4934 ins_encode %{ |
| 4935 __ movflt($dst$$XMMRegister, $mem$$Address); | |
| 4936 %} | |
| 0 | 4937 ins_pipe(pipe_slow); // XXX |
| 4938 %} | |
| 4939 | |
| 4940 // Load Double | |
| 4941 instruct loadD_partial(regD dst, memory mem) | |
| 4942 %{ | |
| 4943 predicate(!UseXmmLoadAndClearUpper); | |
| 4944 match(Set dst (LoadD mem)); | |
| 4945 | |
| 4946 ins_cost(145); // XXX | |
| 4947 format %{ "movlpd $dst, $mem\t# double" %} | |
| 4759 | 4948 ins_encode %{ |
| 4949 __ movdbl($dst$$XMMRegister, $mem$$Address); | |
| 4950 %} | |
| 0 | 4951 ins_pipe(pipe_slow); // XXX |
| 4952 %} | |
| 4953 | |
| 4954 instruct loadD(regD dst, memory mem) | |
| 4955 %{ | |
| 4956 predicate(UseXmmLoadAndClearUpper); | |
| 4957 match(Set dst (LoadD mem)); | |
| 4958 | |
| 4959 ins_cost(145); // XXX | |
| 4960 format %{ "movsd $dst, $mem\t# double" %} | |
| 4759 | 4961 ins_encode %{ |
| 4962 __ movdbl($dst$$XMMRegister, $mem$$Address); | |
| 4963 %} | |
| 0 | 4964 ins_pipe(pipe_slow); // XXX |
| 4965 %} | |
| 4966 | |
| 4967 // Load Effective Address | |
| 4968 instruct leaP8(rRegP dst, indOffset8 mem) | |
| 4969 %{ | |
| 4970 match(Set dst mem); | |
| 4971 | |
| 4972 ins_cost(110); // XXX | |
| 4973 format %{ "leaq $dst, $mem\t# ptr 8" %} | |
| 4974 opcode(0x8D); | |
| 4975 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 4976 ins_pipe(ialu_reg_reg_fat); | |
| 4977 %} | |
| 4978 | |
| 4979 instruct leaP32(rRegP dst, indOffset32 mem) | |
| 4980 %{ | |
| 4981 match(Set dst mem); | |
| 4982 | |
| 4983 ins_cost(110); | |
| 4984 format %{ "leaq $dst, $mem\t# ptr 32" %} | |
| 4985 opcode(0x8D); | |
| 4986 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 4987 ins_pipe(ialu_reg_reg_fat); | |
| 4988 %} | |
| 4989 | |
| 4990 // instruct leaPIdx(rRegP dst, indIndex mem) | |
| 4991 // %{ | |
| 4992 // match(Set dst mem); | |
| 4993 | |
| 4994 // ins_cost(110); | |
| 4995 // format %{ "leaq $dst, $mem\t# ptr idx" %} | |
| 4996 // opcode(0x8D); | |
| 4997 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 4998 // ins_pipe(ialu_reg_reg_fat); | |
| 4999 // %} | |
| 5000 | |
| 5001 instruct leaPIdxOff(rRegP dst, indIndexOffset mem) | |
| 5002 %{ | |
| 5003 match(Set dst mem); | |
| 5004 | |
| 5005 ins_cost(110); | |
| 5006 format %{ "leaq $dst, $mem\t# ptr idxoff" %} | |
| 5007 opcode(0x8D); | |
| 5008 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5009 ins_pipe(ialu_reg_reg_fat); | |
| 5010 %} | |
| 5011 | |
| 5012 instruct leaPIdxScale(rRegP dst, indIndexScale mem) | |
| 5013 %{ | |
| 5014 match(Set dst mem); | |
| 5015 | |
| 5016 ins_cost(110); | |
| 5017 format %{ "leaq $dst, $mem\t# ptr idxscale" %} | |
| 5018 opcode(0x8D); | |
| 5019 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5020 ins_pipe(ialu_reg_reg_fat); | |
| 5021 %} | |
| 5022 | |
| 5023 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem) | |
| 5024 %{ | |
| 5025 match(Set dst mem); | |
| 5026 | |
| 5027 ins_cost(110); | |
| 5028 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %} | |
| 5029 opcode(0x8D); | |
| 5030 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5031 ins_pipe(ialu_reg_reg_fat); | |
| 5032 %} | |
| 5033 | |
|
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5034 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem) |
|
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5035 %{ |
|
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|
5036 match(Set dst mem); |
|
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|
5037 |
|
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|
5038 ins_cost(110); |
|
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|
5039 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %} |
|
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|
5040 opcode(0x8D); |
|
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5041 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
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5042 ins_pipe(ialu_reg_reg_fat); |
|
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|
5043 %} |
|
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5044 |
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5045 // Load Effective Address which uses Narrow (32-bits) oop |
|
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5046 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem) |
|
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5047 %{ |
|
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5048 predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0)); |
|
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5049 match(Set dst mem); |
|
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|
5050 |
|
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|
5051 ins_cost(110); |
|
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|
5052 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %} |
|
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|
5053 opcode(0x8D); |
|
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624
diff
changeset
|
5054 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5055 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5056 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5057 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5058 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5059 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5060 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5061 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5062 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5063 ins_cost(110); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5064 format %{ "leaq $dst, $mem\t# ptr off8narrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5065 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5066 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5067 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5068 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5069 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5070 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5071 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5072 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5073 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5074 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5075 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5076 format %{ "leaq $dst, $mem\t# ptr off32narrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5077 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5078 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5079 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5080 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5081 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5082 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5083 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5084 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5085 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5086 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5087 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5088 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5089 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5090 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5091 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5092 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5093 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5094 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5095 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5096 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5097 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5098 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5099 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5100 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5101 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5102 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5103 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5104 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5105 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5106 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5107 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5108 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5109 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5110 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5111 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5112 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5113 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5114 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5115 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5116 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5117 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5118 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5119 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5120 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5121 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5122 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5123 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5124 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5125 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5126 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5127 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5128 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5129 |
| 0 | 5130 instruct loadConI(rRegI dst, immI src) |
| 5131 %{ | |
| 5132 match(Set dst src); | |
| 5133 | |
| 5134 format %{ "movl $dst, $src\t# int" %} | |
| 5135 ins_encode(load_immI(dst, src)); | |
| 5136 ins_pipe(ialu_reg_fat); // XXX | |
| 5137 %} | |
| 5138 | |
| 5139 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr) | |
| 5140 %{ | |
| 5141 match(Set dst src); | |
| 5142 effect(KILL cr); | |
| 5143 | |
| 5144 ins_cost(50); | |
| 5145 format %{ "xorl $dst, $dst\t# int" %} | |
| 5146 opcode(0x33); /* + rd */ | |
| 5147 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst)); | |
| 5148 ins_pipe(ialu_reg); | |
| 5149 %} | |
| 5150 | |
| 5151 instruct loadConL(rRegL dst, immL src) | |
| 5152 %{ | |
| 5153 match(Set dst src); | |
| 5154 | |
| 5155 ins_cost(150); | |
| 5156 format %{ "movq $dst, $src\t# long" %} | |
| 5157 ins_encode(load_immL(dst, src)); | |
| 5158 ins_pipe(ialu_reg); | |
| 5159 %} | |
| 5160 | |
| 5161 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr) | |
| 5162 %{ | |
| 5163 match(Set dst src); | |
| 5164 effect(KILL cr); | |
| 5165 | |
| 5166 ins_cost(50); | |
| 5167 format %{ "xorl $dst, $dst\t# long" %} | |
| 5168 opcode(0x33); /* + rd */ | |
| 5169 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst)); | |
| 5170 ins_pipe(ialu_reg); // XXX | |
| 5171 %} | |
| 5172 | |
| 5173 instruct loadConUL32(rRegL dst, immUL32 src) | |
| 5174 %{ | |
| 5175 match(Set dst src); | |
| 5176 | |
| 5177 ins_cost(60); | |
| 5178 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %} | |
| 5179 ins_encode(load_immUL32(dst, src)); | |
| 5180 ins_pipe(ialu_reg); | |
| 5181 %} | |
| 5182 | |
| 5183 instruct loadConL32(rRegL dst, immL32 src) | |
| 5184 %{ | |
| 5185 match(Set dst src); | |
| 5186 | |
| 5187 ins_cost(70); | |
| 5188 format %{ "movq $dst, $src\t# long (32-bit)" %} | |
| 5189 ins_encode(load_immL32(dst, src)); | |
| 5190 ins_pipe(ialu_reg); | |
| 5191 %} | |
| 5192 | |
| 2008 | 5193 instruct loadConP(rRegP dst, immP con) %{ |
| 5194 match(Set dst con); | |
| 5195 | |
| 5196 format %{ "movq $dst, $con\t# ptr" %} | |
| 5197 ins_encode(load_immP(dst, con)); | |
| 0 | 5198 ins_pipe(ialu_reg_fat); // XXX |
| 5199 %} | |
| 5200 | |
| 5201 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr) | |
| 5202 %{ | |
| 5203 match(Set dst src); | |
| 5204 effect(KILL cr); | |
| 5205 | |
| 5206 ins_cost(50); | |
| 5207 format %{ "xorl $dst, $dst\t# ptr" %} | |
| 5208 opcode(0x33); /* + rd */ | |
| 5209 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst)); | |
| 5210 ins_pipe(ialu_reg); | |
| 5211 %} | |
| 5212 | |
| 5213 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr) | |
| 5214 %{ | |
| 5215 match(Set dst src); | |
| 5216 effect(KILL cr); | |
| 5217 | |
| 5218 ins_cost(60); | |
| 5219 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %} | |
| 5220 ins_encode(load_immP31(dst, src)); | |
| 5221 ins_pipe(ialu_reg); | |
| 5222 %} | |
| 5223 | |
| 2008 | 5224 instruct loadConF(regF dst, immF con) %{ |
| 5225 match(Set dst con); | |
| 0 | 5226 ins_cost(125); |
| 2008 | 5227 format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %} |
| 5228 ins_encode %{ | |
| 5229 __ movflt($dst$$XMMRegister, $constantaddress($con)); | |
| 5230 %} | |
| 0 | 5231 ins_pipe(pipe_slow); |
| 5232 %} | |
| 5233 | |
|
113
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6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5234 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
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diff
changeset
|
5235 match(Set dst src); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5236 effect(KILL cr); |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
5237 format %{ "xorq $dst, $src\t# compressed NULL ptr" %} |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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diff
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|
5238 ins_encode %{ |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5239 __ xorq($dst$$Register, $dst$$Register); |
|
113
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6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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|
5240 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5241 ins_pipe(ialu_reg); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
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diff
changeset
|
5242 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5243 |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
5244 instruct loadConN(rRegN dst, immN src) %{ |
|
113
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parents:
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|
5245 match(Set dst src); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5246 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5247 ins_cost(125); |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
5248 format %{ "movl $dst, $src\t# compressed ptr" %} |
|
113
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6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
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diff
changeset
|
5249 ins_encode %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5250 address con = (address)$src$$constant; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5251 if (con == NULL) { |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5252 ShouldNotReachHere(); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5253 } else { |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5254 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant); |
|
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5255 } |
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5256 %} |
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5257 ins_pipe(ialu_reg_fat); // XXX |
|
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5258 %} |
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5259 |
|
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5260 instruct loadConNKlass(rRegN dst, immNKlass src) %{ |
|
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|
5261 match(Set dst src); |
|
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|
5262 |
|
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|
5263 ins_cost(125); |
|
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|
5264 format %{ "movl $dst, $src\t# compressed klass ptr" %} |
|
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|
5265 ins_encode %{ |
|
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|
5266 address con = (address)$src$$constant; |
|
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|
5267 if (con == NULL) { |
|
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|
5268 ShouldNotReachHere(); |
|
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|
5269 } else { |
|
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|
5270 __ set_narrow_klass($dst$$Register, (Klass*)$src$$constant); |
|
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|
5271 } |
|
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|
5272 %} |
|
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|
5273 ins_pipe(ialu_reg_fat); // XXX |
|
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|
5274 %} |
|
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|
5275 |
| 0 | 5276 instruct loadConF0(regF dst, immF0 src) |
| 5277 %{ | |
| 5278 match(Set dst src); | |
| 5279 ins_cost(100); | |
| 5280 | |
| 5281 format %{ "xorps $dst, $dst\t# float 0.0" %} | |
| 4759 | 5282 ins_encode %{ |
| 5283 __ xorps($dst$$XMMRegister, $dst$$XMMRegister); | |
| 5284 %} | |
| 0 | 5285 ins_pipe(pipe_slow); |
| 5286 %} | |
| 5287 | |
| 5288 // Use the same format since predicate() can not be used here. | |
| 2008 | 5289 instruct loadConD(regD dst, immD con) %{ |
| 5290 match(Set dst con); | |
| 0 | 5291 ins_cost(125); |
| 2008 | 5292 format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %} |
| 5293 ins_encode %{ | |
| 5294 __ movdbl($dst$$XMMRegister, $constantaddress($con)); | |
| 5295 %} | |
| 0 | 5296 ins_pipe(pipe_slow); |
| 5297 %} | |
| 5298 | |
| 5299 instruct loadConD0(regD dst, immD0 src) | |
| 5300 %{ | |
| 5301 match(Set dst src); | |
| 5302 ins_cost(100); | |
| 5303 | |
| 5304 format %{ "xorpd $dst, $dst\t# double 0.0" %} | |
| 4759 | 5305 ins_encode %{ |
| 5306 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister); | |
| 5307 %} | |
| 0 | 5308 ins_pipe(pipe_slow); |
| 5309 %} | |
| 5310 | |
| 5311 instruct loadSSI(rRegI dst, stackSlotI src) | |
| 5312 %{ | |
| 5313 match(Set dst src); | |
| 5314 | |
| 5315 ins_cost(125); | |
| 5316 format %{ "movl $dst, $src\t# int stk" %} | |
| 5317 opcode(0x8B); | |
| 5318 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 5319 ins_pipe(ialu_reg_mem); | |
| 5320 %} | |
| 5321 | |
| 5322 instruct loadSSL(rRegL dst, stackSlotL src) | |
| 5323 %{ | |
| 5324 match(Set dst src); | |
| 5325 | |
| 5326 ins_cost(125); | |
| 5327 format %{ "movq $dst, $src\t# long stk" %} | |
| 5328 opcode(0x8B); | |
| 5329 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 5330 ins_pipe(ialu_reg_mem); | |
| 5331 %} | |
| 5332 | |
| 5333 instruct loadSSP(rRegP dst, stackSlotP src) | |
| 5334 %{ | |
| 5335 match(Set dst src); | |
| 5336 | |
| 5337 ins_cost(125); | |
| 5338 format %{ "movq $dst, $src\t# ptr stk" %} | |
| 5339 opcode(0x8B); | |
| 5340 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 5341 ins_pipe(ialu_reg_mem); | |
| 5342 %} | |
| 5343 | |
| 5344 instruct loadSSF(regF dst, stackSlotF src) | |
| 5345 %{ | |
| 5346 match(Set dst src); | |
| 5347 | |
| 5348 ins_cost(125); | |
| 5349 format %{ "movss $dst, $src\t# float stk" %} | |
| 4759 | 5350 ins_encode %{ |
| 5351 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 5352 %} | |
| 0 | 5353 ins_pipe(pipe_slow); // XXX |
| 5354 %} | |
| 5355 | |
| 5356 // Use the same format since predicate() can not be used here. | |
| 5357 instruct loadSSD(regD dst, stackSlotD src) | |
| 5358 %{ | |
| 5359 match(Set dst src); | |
| 5360 | |
| 5361 ins_cost(125); | |
| 5362 format %{ "movsd $dst, $src\t# double stk" %} | |
| 5363 ins_encode %{ | |
| 5364 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 5365 %} | |
| 5366 ins_pipe(pipe_slow); // XXX | |
| 5367 %} | |
| 5368 | |
| 5369 // Prefetch instructions. | |
| 5370 // Must be safe to execute with invalid address (cannot fault). | |
| 5371 | |
| 5372 instruct prefetchr( memory mem ) %{ | |
| 5373 predicate(ReadPrefetchInstr==3); | |
| 5374 match(PrefetchRead mem); | |
| 5375 ins_cost(125); | |
| 5376 | |
| 5377 format %{ "PREFETCHR $mem\t# Prefetch into level 1 cache" %} | |
| 3854 | 5378 ins_encode %{ |
| 5379 __ prefetchr($mem$$Address); | |
| 5380 %} | |
| 0 | 5381 ins_pipe(ialu_mem); |
| 5382 %} | |
| 5383 | |
| 5384 instruct prefetchrNTA( memory mem ) %{ | |
| 5385 predicate(ReadPrefetchInstr==0); | |
| 5386 match(PrefetchRead mem); | |
| 5387 ins_cost(125); | |
| 5388 | |
| 5389 format %{ "PREFETCHNTA $mem\t# Prefetch into non-temporal cache for read" %} | |
| 3854 | 5390 ins_encode %{ |
| 5391 __ prefetchnta($mem$$Address); | |
| 5392 %} | |
| 0 | 5393 ins_pipe(ialu_mem); |
| 5394 %} | |
| 5395 | |
| 5396 instruct prefetchrT0( memory mem ) %{ | |
| 5397 predicate(ReadPrefetchInstr==1); | |
| 5398 match(PrefetchRead mem); | |
| 5399 ins_cost(125); | |
| 5400 | |
| 5401 format %{ "PREFETCHT0 $mem\t# prefetch into L1 and L2 caches for read" %} | |
| 3854 | 5402 ins_encode %{ |
| 5403 __ prefetcht0($mem$$Address); | |
| 5404 %} | |
| 0 | 5405 ins_pipe(ialu_mem); |
| 5406 %} | |
| 5407 | |
| 5408 instruct prefetchrT2( memory mem ) %{ | |
| 5409 predicate(ReadPrefetchInstr==2); | |
| 5410 match(PrefetchRead mem); | |
| 5411 ins_cost(125); | |
| 5412 | |
| 5413 format %{ "PREFETCHT2 $mem\t# prefetch into L2 caches for read" %} | |
| 3854 | 5414 ins_encode %{ |
| 5415 __ prefetcht2($mem$$Address); | |
| 5416 %} | |
| 0 | 5417 ins_pipe(ialu_mem); |
| 5418 %} | |
| 5419 | |
| 5420 instruct prefetchwNTA( memory mem ) %{ | |
| 5421 match(PrefetchWrite mem); | |
| 5422 ins_cost(125); | |
| 5423 | |
| 5424 format %{ "PREFETCHNTA $mem\t# Prefetch to non-temporal cache for write" %} | |
| 3854 | 5425 ins_encode %{ |
| 5426 __ prefetchnta($mem$$Address); | |
| 5427 %} | |
| 0 | 5428 ins_pipe(ialu_mem); |
| 5429 %} | |
| 5430 | |
| 3854 | 5431 // Prefetch instructions for allocation. |
| 5432 | |
| 5433 instruct prefetchAlloc( memory mem ) %{ | |
| 5434 predicate(AllocatePrefetchInstr==3); | |
| 5435 match(PrefetchAllocation mem); | |
| 5436 ins_cost(125); | |
| 5437 | |
| 5438 format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %} | |
| 5439 ins_encode %{ | |
| 5440 __ prefetchw($mem$$Address); | |
| 5441 %} | |
| 5442 ins_pipe(ialu_mem); | |
| 5443 %} | |
| 5444 | |
| 5445 instruct prefetchAllocNTA( memory mem ) %{ | |
| 5446 predicate(AllocatePrefetchInstr==0); | |
| 5447 match(PrefetchAllocation mem); | |
| 0 | 5448 ins_cost(125); |
| 5449 | |
| 3854 | 5450 format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %} |
| 5451 ins_encode %{ | |
| 5452 __ prefetchnta($mem$$Address); | |
| 5453 %} | |
| 0 | 5454 ins_pipe(ialu_mem); |
| 5455 %} | |
| 5456 | |
| 3854 | 5457 instruct prefetchAllocT0( memory mem ) %{ |
| 5458 predicate(AllocatePrefetchInstr==1); | |
| 5459 match(PrefetchAllocation mem); | |
| 0 | 5460 ins_cost(125); |
| 5461 | |
| 3854 | 5462 format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %} |
| 5463 ins_encode %{ | |
| 5464 __ prefetcht0($mem$$Address); | |
| 5465 %} | |
| 5466 ins_pipe(ialu_mem); | |
| 5467 %} | |
| 5468 | |
| 5469 instruct prefetchAllocT2( memory mem ) %{ | |
| 5470 predicate(AllocatePrefetchInstr==2); | |
| 5471 match(PrefetchAllocation mem); | |
| 5472 ins_cost(125); | |
| 5473 | |
| 5474 format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %} | |
| 5475 ins_encode %{ | |
| 5476 __ prefetcht2($mem$$Address); | |
| 5477 %} | |
| 0 | 5478 ins_pipe(ialu_mem); |
| 5479 %} | |
| 5480 | |
| 5481 //----------Store Instructions------------------------------------------------- | |
| 5482 | |
| 5483 // Store Byte | |
| 5484 instruct storeB(memory mem, rRegI src) | |
| 5485 %{ | |
| 5486 match(Set mem (StoreB mem src)); | |
| 5487 | |
| 5488 ins_cost(125); // XXX | |
| 5489 format %{ "movb $mem, $src\t# byte" %} | |
| 5490 opcode(0x88); | |
| 5491 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
| 5492 ins_pipe(ialu_mem_reg); | |
| 5493 %} | |
| 5494 | |
| 5495 // Store Char/Short | |
| 5496 instruct storeC(memory mem, rRegI src) | |
| 5497 %{ | |
| 5498 match(Set mem (StoreC mem src)); | |
| 5499 | |
| 5500 ins_cost(125); // XXX | |
| 5501 format %{ "movw $mem, $src\t# char/short" %} | |
| 5502 opcode(0x89); | |
| 5503 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
| 5504 ins_pipe(ialu_mem_reg); | |
| 5505 %} | |
| 5506 | |
| 5507 // Store Integer | |
| 5508 instruct storeI(memory mem, rRegI src) | |
| 5509 %{ | |
| 5510 match(Set mem (StoreI mem src)); | |
| 5511 | |
| 5512 ins_cost(125); // XXX | |
| 5513 format %{ "movl $mem, $src\t# int" %} | |
| 5514 opcode(0x89); | |
| 5515 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
| 5516 ins_pipe(ialu_mem_reg); | |
| 5517 %} | |
| 5518 | |
| 5519 // Store Long | |
| 5520 instruct storeL(memory mem, rRegL src) | |
| 5521 %{ | |
| 5522 match(Set mem (StoreL mem src)); | |
| 5523 | |
| 5524 ins_cost(125); // XXX | |
| 5525 format %{ "movq $mem, $src\t# long" %} | |
| 5526 opcode(0x89); | |
| 5527 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem)); | |
| 5528 ins_pipe(ialu_mem_reg); // XXX | |
| 5529 %} | |
| 5530 | |
| 5531 // Store Pointer | |
| 5532 instruct storeP(memory mem, any_RegP src) | |
| 5533 %{ | |
| 5534 match(Set mem (StoreP mem src)); | |
| 5535 | |
| 5536 ins_cost(125); // XXX | |
| 5537 format %{ "movq $mem, $src\t# ptr" %} | |
| 5538 opcode(0x89); | |
| 5539 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem)); | |
| 5540 ins_pipe(ialu_mem_reg); | |
| 5541 %} | |
| 5542 | |
|
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|
5543 instruct storeImmP0(memory mem, immP0 zero) |
|
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5544 %{ |
|
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|
5545 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL)); |
|
642
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5546 match(Set mem (StoreP mem zero)); |
|
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|
5547 |
|
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|
5548 ins_cost(125); // XXX |
|
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5549 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %} |
|
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5550 ins_encode %{ |
|
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|
5551 __ movq($mem$$Address, r12); |
|
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|
5552 %} |
|
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|
5553 ins_pipe(ialu_mem_reg); |
|
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|
5554 %} |
|
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|
5555 |
| 0 | 5556 // Store NULL Pointer, mark word, or other simple pointer constant. |
| 5557 instruct storeImmP(memory mem, immP31 src) | |
| 5558 %{ | |
| 5559 match(Set mem (StoreP mem src)); | |
| 5560 | |
|
642
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5561 ins_cost(150); // XXX |
| 0 | 5562 format %{ "movq $mem, $src\t# ptr" %} |
| 5563 opcode(0xC7); /* C7 /0 */ | |
| 5564 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); | |
| 5565 ins_pipe(ialu_mem_imm); | |
| 5566 %} | |
| 5567 | |
|
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5568 // Store Compressed Pointer |
| 163 | 5569 instruct storeN(memory mem, rRegN src) |
|
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5570 %{ |
|
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|
5571 match(Set mem (StoreN mem src)); |
|
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5572 |
|
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|
5573 ins_cost(125); // XXX |
|
164
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5574 format %{ "movl $mem, $src\t# compressed ptr" %} |
|
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5575 ins_encode %{ |
|
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5576 __ movl($mem$$Address, $src$$Register); |
|
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5577 %} |
|
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|
5578 ins_pipe(ialu_mem_reg); |
|
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|
5579 %} |
|
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5580 |
|
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|
5581 instruct storeNKlass(memory mem, rRegN src) |
|
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|
5582 %{ |
|
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|
5583 match(Set mem (StoreNKlass mem src)); |
|
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|
5584 |
|
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|
5585 ins_cost(125); // XXX |
|
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|
5586 format %{ "movl $mem, $src\t# compressed klass ptr" %} |
|
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|
5587 ins_encode %{ |
|
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|
5588 __ movl($mem$$Address, $src$$Register); |
|
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|
5589 %} |
|
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|
5590 ins_pipe(ialu_mem_reg); |
|
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|
5591 %} |
|
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|
5592 |
|
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5593 instruct storeImmN0(memory mem, immN0 zero) |
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5594 %{ |
|
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|
5595 predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_klass_base() == NULL); |
|
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changeset
|
5596 match(Set mem (StoreN mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5597 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5598 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5599 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5600 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5601 __ movl($mem$$Address, r12); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5602 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5603 ins_pipe(ialu_mem_reg); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5604 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5605 |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5606 instruct storeImmN(memory mem, immN src) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5607 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5608 match(Set mem (StoreN mem src)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5609 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5610 ins_cost(150); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5611 format %{ "movl $mem, $src\t# compressed ptr" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5612 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5613 address con = (address)$src$$constant; |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5614 if (con == NULL) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5615 __ movl($mem$$Address, (int32_t)0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5616 } else { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5617 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5618 } |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5619 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5620 ins_pipe(ialu_mem_imm); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5621 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5622 |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5623 instruct storeImmNKlass(memory mem, immNKlass src) |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5624 %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5625 match(Set mem (StoreNKlass mem src)); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5626 |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5627 ins_cost(150); // XXX |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5628 format %{ "movl $mem, $src\t# compressed klass ptr" %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5629 ins_encode %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5630 __ set_narrow_klass($mem$$Address, (Klass*)$src$$constant); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5631 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5632 ins_pipe(ialu_mem_imm); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5633 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5634 |
| 0 | 5635 // Store Integer Immediate |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5636 instruct storeImmI0(memory mem, immI0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5637 %{ |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5638 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL)); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5639 match(Set mem (StoreI mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5640 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5641 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5642 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5643 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5644 __ movl($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5645 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5646 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5647 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5648 |
| 0 | 5649 instruct storeImmI(memory mem, immI src) |
| 5650 %{ | |
| 5651 match(Set mem (StoreI mem src)); | |
| 5652 | |
| 5653 ins_cost(150); | |
| 5654 format %{ "movl $mem, $src\t# int" %} | |
| 5655 opcode(0xC7); /* C7 /0 */ | |
| 5656 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); | |
| 5657 ins_pipe(ialu_mem_imm); | |
| 5658 %} | |
| 5659 | |
| 5660 // Store Long Immediate | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5661 instruct storeImmL0(memory mem, immL0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5662 %{ |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5663 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL)); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5664 match(Set mem (StoreL mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5665 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5666 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5667 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5668 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5669 __ movq($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5670 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5671 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5672 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5673 |
| 0 | 5674 instruct storeImmL(memory mem, immL32 src) |
| 5675 %{ | |
| 5676 match(Set mem (StoreL mem src)); | |
| 5677 | |
| 5678 ins_cost(150); | |
| 5679 format %{ "movq $mem, $src\t# long" %} | |
| 5680 opcode(0xC7); /* C7 /0 */ | |
| 5681 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); | |
| 5682 ins_pipe(ialu_mem_imm); | |
| 5683 %} | |
| 5684 | |
| 5685 // Store Short/Char Immediate | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5686 instruct storeImmC0(memory mem, immI0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5687 %{ |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5688 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL)); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5689 match(Set mem (StoreC mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5690 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5691 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5692 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5693 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5694 __ movw($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5695 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5696 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5697 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5698 |
| 0 | 5699 instruct storeImmI16(memory mem, immI16 src) |
| 5700 %{ | |
| 5701 predicate(UseStoreImmI16); | |
| 5702 match(Set mem (StoreC mem src)); | |
| 5703 | |
| 5704 ins_cost(150); | |
| 5705 format %{ "movw $mem, $src\t# short/char" %} | |
| 5706 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */ | |
| 5707 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src)); | |
| 5708 ins_pipe(ialu_mem_imm); | |
| 5709 %} | |
| 5710 | |
| 5711 // Store Byte Immediate | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5712 instruct storeImmB0(memory mem, immI0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5713 %{ |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5714 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL)); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5715 match(Set mem (StoreB mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5716 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5717 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5718 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5719 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5720 __ movb($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5721 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5722 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5723 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5724 |
| 0 | 5725 instruct storeImmB(memory mem, immI8 src) |
| 5726 %{ | |
| 5727 match(Set mem (StoreB mem src)); | |
| 5728 | |
| 5729 ins_cost(150); // XXX | |
| 5730 format %{ "movb $mem, $src\t# byte" %} | |
| 5731 opcode(0xC6); /* C6 /0 */ | |
| 5732 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src)); | |
| 5733 ins_pipe(ialu_mem_imm); | |
| 5734 %} | |
| 5735 | |
| 5736 // Store CMS card-mark Immediate | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5737 instruct storeImmCM0_reg(memory mem, immI0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5738 %{ |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5739 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL)); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5740 match(Set mem (StoreCM mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5741 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5742 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5743 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5744 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5745 __ movb($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5746 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5747 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5748 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5749 |
| 0 | 5750 instruct storeImmCM0(memory mem, immI0 src) |
| 5751 %{ | |
| 5752 match(Set mem (StoreCM mem src)); | |
| 5753 | |
| 5754 ins_cost(150); // XXX | |
| 5755 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %} | |
| 5756 opcode(0xC6); /* C6 /0 */ | |
| 5757 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src)); | |
| 5758 ins_pipe(ialu_mem_imm); | |
| 5759 %} | |
| 5760 | |
| 5761 // Store Float | |
| 5762 instruct storeF(memory mem, regF src) | |
| 5763 %{ | |
| 5764 match(Set mem (StoreF mem src)); | |
| 5765 | |
| 5766 ins_cost(95); // XXX | |
| 5767 format %{ "movss $mem, $src\t# float" %} | |
| 4759 | 5768 ins_encode %{ |
| 5769 __ movflt($mem$$Address, $src$$XMMRegister); | |
| 5770 %} | |
| 0 | 5771 ins_pipe(pipe_slow); // XXX |
| 5772 %} | |
| 5773 | |
| 5774 // Store immediate Float value (it is faster than store from XMM register) | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5775 instruct storeF0(memory mem, immF0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5776 %{ |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5777 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL)); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5778 match(Set mem (StoreF mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5779 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5780 ins_cost(25); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5781 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5782 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5783 __ movl($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5784 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5785 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5786 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5787 |
| 0 | 5788 instruct storeF_imm(memory mem, immF src) |
| 5789 %{ | |
| 5790 match(Set mem (StoreF mem src)); | |
| 5791 | |
| 5792 ins_cost(50); | |
| 5793 format %{ "movl $mem, $src\t# float" %} | |
| 5794 opcode(0xC7); /* C7 /0 */ | |
| 5795 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src)); | |
| 5796 ins_pipe(ialu_mem_imm); | |
| 5797 %} | |
| 5798 | |
| 5799 // Store Double | |
| 5800 instruct storeD(memory mem, regD src) | |
| 5801 %{ | |
| 5802 match(Set mem (StoreD mem src)); | |
| 5803 | |
| 5804 ins_cost(95); // XXX | |
| 5805 format %{ "movsd $mem, $src\t# double" %} | |
| 4759 | 5806 ins_encode %{ |
| 5807 __ movdbl($mem$$Address, $src$$XMMRegister); | |
| 5808 %} | |
| 0 | 5809 ins_pipe(pipe_slow); // XXX |
| 5810 %} | |
| 5811 | |
| 5812 // Store immediate double 0.0 (it is faster than store from XMM register) | |
| 5813 instruct storeD0_imm(memory mem, immD0 src) | |
| 5814 %{ | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5815 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL)); |
| 0 | 5816 match(Set mem (StoreD mem src)); |
| 5817 | |
| 5818 ins_cost(50); | |
| 5819 format %{ "movq $mem, $src\t# double 0." %} | |
| 5820 opcode(0xC7); /* C7 /0 */ | |
| 5821 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src)); | |
| 5822 ins_pipe(ialu_mem_imm); | |
| 5823 %} | |
| 5824 | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5825 instruct storeD0(memory mem, immD0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5826 %{ |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5827 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL)); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5828 match(Set mem (StoreD mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5829 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5830 ins_cost(25); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5831 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5832 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5833 __ movq($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5834 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5835 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5836 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5837 |
| 0 | 5838 instruct storeSSI(stackSlotI dst, rRegI src) |
| 5839 %{ | |
| 5840 match(Set dst src); | |
| 5841 | |
| 5842 ins_cost(100); | |
| 5843 format %{ "movl $dst, $src\t# int stk" %} | |
| 5844 opcode(0x89); | |
| 5845 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 5846 ins_pipe( ialu_mem_reg ); | |
| 5847 %} | |
| 5848 | |
| 5849 instruct storeSSL(stackSlotL dst, rRegL src) | |
| 5850 %{ | |
| 5851 match(Set dst src); | |
| 5852 | |
| 5853 ins_cost(100); | |
| 5854 format %{ "movq $dst, $src\t# long stk" %} | |
| 5855 opcode(0x89); | |
| 5856 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 5857 ins_pipe(ialu_mem_reg); | |
| 5858 %} | |
| 5859 | |
| 5860 instruct storeSSP(stackSlotP dst, rRegP src) | |
| 5861 %{ | |
| 5862 match(Set dst src); | |
| 5863 | |
| 5864 ins_cost(100); | |
| 5865 format %{ "movq $dst, $src\t# ptr stk" %} | |
| 5866 opcode(0x89); | |
| 5867 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 5868 ins_pipe(ialu_mem_reg); | |
| 5869 %} | |
| 5870 | |
| 5871 instruct storeSSF(stackSlotF dst, regF src) | |
| 5872 %{ | |
| 5873 match(Set dst src); | |
| 5874 | |
| 5875 ins_cost(95); // XXX | |
| 5876 format %{ "movss $dst, $src\t# float stk" %} | |
| 4759 | 5877 ins_encode %{ |
| 5878 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister); | |
| 5879 %} | |
| 0 | 5880 ins_pipe(pipe_slow); // XXX |
| 5881 %} | |
| 5882 | |
| 5883 instruct storeSSD(stackSlotD dst, regD src) | |
| 5884 %{ | |
| 5885 match(Set dst src); | |
| 5886 | |
| 5887 ins_cost(95); // XXX | |
| 5888 format %{ "movsd $dst, $src\t# double stk" %} | |
| 4759 | 5889 ins_encode %{ |
| 5890 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister); | |
| 5891 %} | |
| 0 | 5892 ins_pipe(pipe_slow); // XXX |
| 5893 %} | |
| 5894 | |
| 5895 //----------BSWAP Instructions------------------------------------------------- | |
| 5896 instruct bytes_reverse_int(rRegI dst) %{ | |
| 5897 match(Set dst (ReverseBytesI dst)); | |
| 5898 | |
| 5899 format %{ "bswapl $dst" %} | |
| 5900 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */ | |
| 5901 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) ); | |
| 5902 ins_pipe( ialu_reg ); | |
| 5903 %} | |
| 5904 | |
| 5905 instruct bytes_reverse_long(rRegL dst) %{ | |
| 5906 match(Set dst (ReverseBytesL dst)); | |
| 5907 | |
| 5908 format %{ "bswapq $dst" %} | |
| 5909 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */ | |
| 5910 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) ); | |
| 5911 ins_pipe( ialu_reg); | |
| 5912 %} | |
| 5913 | |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
5914 instruct bytes_reverse_unsigned_short(rRegI dst, rFlagsReg cr) %{ |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5915 match(Set dst (ReverseBytesUS dst)); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
5916 effect(KILL cr); |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5917 |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
5918 format %{ "bswapl $dst\n\t" |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5919 "shrl $dst,16\n\t" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5920 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5921 __ bswapl($dst$$Register); |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
5922 __ shrl($dst$$Register, 16); |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5923 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5924 ins_pipe( ialu_reg ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5925 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5926 |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
5927 instruct bytes_reverse_short(rRegI dst, rFlagsReg cr) %{ |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5928 match(Set dst (ReverseBytesS dst)); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
5929 effect(KILL cr); |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5930 |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
5931 format %{ "bswapl $dst\n\t" |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5932 "sar $dst,16\n\t" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5933 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5934 __ bswapl($dst$$Register); |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
5935 __ sarl($dst$$Register, 16); |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5936 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5937 ins_pipe( ialu_reg ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5938 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5939 |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5940 //---------- Zeros Count Instructions ------------------------------------------ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5941 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5942 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5943 predicate(UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5944 match(Set dst (CountLeadingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5945 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5946 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5947 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5948 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5949 __ lzcntl($dst$$Register, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5950 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5951 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5952 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5953 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5954 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5955 predicate(!UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5956 match(Set dst (CountLeadingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5957 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5958 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5959 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5960 "jnz skip\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5961 "movl $dst, -1\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5962 "skip:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5963 "negl $dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5964 "addl $dst, 31" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5965 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5966 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5967 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5968 Label skip; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5969 __ bsrl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5970 __ jccb(Assembler::notZero, skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5971 __ movl(Rdst, -1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5972 __ bind(skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5973 __ negl(Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5974 __ addl(Rdst, BitsPerInt - 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5975 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5976 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5977 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5978 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5979 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5980 predicate(UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5981 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5982 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5983 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5984 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5985 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5986 __ lzcntq($dst$$Register, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5987 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5988 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5989 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5990 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5991 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5992 predicate(!UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5993 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5994 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5995 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5996 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5997 "jnz skip\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5998 "movl $dst, -1\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5999 "skip:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6000 "negl $dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6001 "addl $dst, 63" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6002 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6003 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6004 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6005 Label skip; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6006 __ bsrq(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6007 __ jccb(Assembler::notZero, skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6008 __ movl(Rdst, -1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6009 __ bind(skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6010 __ negl(Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6011 __ addl(Rdst, BitsPerLong - 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6012 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6013 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6014 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6015 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6016 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6017 match(Set dst (CountTrailingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6018 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6019 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6020 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6021 "jnz done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6022 "movl $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6023 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6024 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6025 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6026 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6027 __ bsfl(Rdst, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6028 __ jccb(Assembler::notZero, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6029 __ movl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6030 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6031 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6032 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6033 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6034 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6035 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6036 match(Set dst (CountTrailingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6037 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6038 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6039 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6040 "jnz done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6041 "movl $dst, 64\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6042 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6043 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6044 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6045 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6046 __ bsfq(Rdst, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6047 __ jccb(Assembler::notZero, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6048 __ movl(Rdst, BitsPerLong); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6049 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6050 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6051 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6052 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6053 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6054 |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6055 //---------- Population Count Instructions ------------------------------------- |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6056 |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6057 instruct popCountI(rRegI dst, rRegI src, rFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6058 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6059 match(Set dst (PopCountI src)); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6060 effect(KILL cr); |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6061 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6062 format %{ "popcnt $dst, $src" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6063 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6064 __ popcntl($dst$$Register, $src$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6065 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6066 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6067 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6068 |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6069 instruct popCountI_mem(rRegI dst, memory mem, rFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6070 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6071 match(Set dst (PopCountI (LoadI mem))); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6072 effect(KILL cr); |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6073 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6074 format %{ "popcnt $dst, $mem" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6075 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6076 __ popcntl($dst$$Register, $mem$$Address); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6077 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6078 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6079 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6080 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6081 // Note: Long.bitCount(long) returns an int. |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6082 instruct popCountL(rRegI dst, rRegL src, rFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6083 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6084 match(Set dst (PopCountL src)); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6085 effect(KILL cr); |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6086 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6087 format %{ "popcnt $dst, $src" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6088 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6089 __ popcntq($dst$$Register, $src$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6090 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6091 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6092 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6093 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6094 // Note: Long.bitCount(long) returns an int. |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6095 instruct popCountL_mem(rRegI dst, memory mem, rFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6096 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6097 match(Set dst (PopCountL (LoadL mem))); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6098 effect(KILL cr); |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6099 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6100 format %{ "popcnt $dst, $mem" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6101 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6102 __ popcntq($dst$$Register, $mem$$Address); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6103 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6104 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6105 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6106 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6107 |
| 0 | 6108 //----------MemBar Instructions----------------------------------------------- |
| 6109 // Memory barrier flavors | |
| 6110 | |
| 6111 instruct membar_acquire() | |
| 6112 %{ | |
| 6113 match(MemBarAcquire); | |
| 6114 ins_cost(0); | |
| 6115 | |
| 6116 size(0); | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6117 format %{ "MEMBAR-acquire ! (empty encoding)" %} |
| 0 | 6118 ins_encode(); |
| 6119 ins_pipe(empty); | |
| 6120 %} | |
| 6121 | |
| 6122 instruct membar_acquire_lock() | |
| 6123 %{ | |
|
3849
f1c12354c3f7
7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents:
3842
diff
changeset
|
6124 match(MemBarAcquireLock); |
| 0 | 6125 ins_cost(0); |
| 6126 | |
| 6127 size(0); | |
| 6128 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %} | |
| 6129 ins_encode(); | |
| 6130 ins_pipe(empty); | |
| 6131 %} | |
| 6132 | |
| 6133 instruct membar_release() | |
| 6134 %{ | |
| 6135 match(MemBarRelease); | |
| 6136 ins_cost(0); | |
| 6137 | |
| 6138 size(0); | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6139 format %{ "MEMBAR-release ! (empty encoding)" %} |
| 0 | 6140 ins_encode(); |
| 6141 ins_pipe(empty); | |
| 6142 %} | |
| 6143 | |
| 6144 instruct membar_release_lock() | |
| 6145 %{ | |
|
3849
f1c12354c3f7
7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents:
3842
diff
changeset
|
6146 match(MemBarReleaseLock); |
| 0 | 6147 ins_cost(0); |
| 6148 | |
| 6149 size(0); | |
| 6150 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %} | |
| 6151 ins_encode(); | |
| 6152 ins_pipe(empty); | |
| 6153 %} | |
| 6154 | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6155 instruct membar_volatile(rFlagsReg cr) %{ |
| 0 | 6156 match(MemBarVolatile); |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6157 effect(KILL cr); |
| 0 | 6158 ins_cost(400); |
| 6159 | |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
6160 format %{ |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6161 $$template |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6162 if (os::is_MP()) { |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6163 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile" |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6164 } else { |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6165 $$emit$$"MEMBAR-volatile ! (empty encoding)" |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6166 } |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6167 %} |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6168 ins_encode %{ |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6169 __ membar(Assembler::StoreLoad); |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6170 %} |
| 0 | 6171 ins_pipe(pipe_slow); |
| 6172 %} | |
| 6173 | |
| 6174 instruct unnecessary_membar_volatile() | |
| 6175 %{ | |
| 6176 match(MemBarVolatile); | |
| 6177 predicate(Matcher::post_store_load_barrier(n)); | |
| 6178 ins_cost(0); | |
| 6179 | |
| 6180 size(0); | |
| 6181 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %} | |
| 6182 ins_encode(); | |
| 6183 ins_pipe(empty); | |
| 6184 %} | |
| 6185 | |
|
4763
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6186 instruct membar_storestore() %{ |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6187 match(MemBarStoreStore); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6188 ins_cost(0); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6189 |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6190 size(0); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6191 format %{ "MEMBAR-storestore (empty encoding)" %} |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6192 ins_encode( ); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6193 ins_pipe(empty); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6194 %} |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6195 |
| 0 | 6196 //----------Move Instructions-------------------------------------------------- |
| 6197 | |
| 6198 instruct castX2P(rRegP dst, rRegL src) | |
| 6199 %{ | |
| 6200 match(Set dst (CastX2P src)); | |
| 6201 | |
| 6202 format %{ "movq $dst, $src\t# long->ptr" %} | |
| 4759 | 6203 ins_encode %{ |
| 6204 if ($dst$$reg != $src$$reg) { | |
| 6205 __ movptr($dst$$Register, $src$$Register); | |
| 6206 } | |
| 6207 %} | |
| 0 | 6208 ins_pipe(ialu_reg_reg); // XXX |
| 6209 %} | |
| 6210 | |
| 6211 instruct castP2X(rRegL dst, rRegP src) | |
| 6212 %{ | |
| 6213 match(Set dst (CastP2X src)); | |
| 6214 | |
| 6215 format %{ "movq $dst, $src\t# ptr -> long" %} | |
| 4759 | 6216 ins_encode %{ |
| 6217 if ($dst$$reg != $src$$reg) { | |
| 6218 __ movptr($dst$$Register, $src$$Register); | |
| 6219 } | |
| 6220 %} | |
| 0 | 6221 ins_pipe(ialu_reg_reg); // XXX |
| 6222 %} | |
| 6223 | |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6224 // Convert oop into int for vectors alignment masking |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6225 instruct convP2I(rRegI dst, rRegP src) |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6226 %{ |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6227 match(Set dst (ConvL2I (CastP2X src))); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6228 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6229 format %{ "movl $dst, $src\t# ptr -> int" %} |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6230 ins_encode %{ |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6231 __ movl($dst$$Register, $src$$Register); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6232 %} |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6233 ins_pipe(ialu_reg_reg); // XXX |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6234 %} |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6235 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6236 // Convert compressed oop into int for vectors alignment masking |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6237 // in case of 32bit oops (heap < 4Gb). |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6238 instruct convN2I(rRegI dst, rRegN src) |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6239 %{ |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6240 predicate(Universe::narrow_oop_shift() == 0); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6241 match(Set dst (ConvL2I (CastP2X (DecodeN src)))); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6242 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6243 format %{ "movl $dst, $src\t# compressed ptr -> int" %} |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6244 ins_encode %{ |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6245 __ movl($dst$$Register, $src$$Register); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6246 %} |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6247 ins_pipe(ialu_reg_reg); // XXX |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6248 %} |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6249 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6250 // Convert oop pointer into compressed form |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6251 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{ |
|
221
1e026f8da827
6710487: More than half of JDI Regression tests hang with COOPs in -Xcomp mode
kvn
parents:
182
diff
changeset
|
6252 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6253 match(Set dst (EncodeP src)); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6254 effect(KILL cr); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6255 format %{ "encode_heap_oop $dst,$src" %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6256 ins_encode %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6257 Register s = $src$$Register; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6258 Register d = $dst$$Register; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6259 if (s != d) { |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6260 __ movq(d, s); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6261 } |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6262 __ encode_heap_oop(d); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6263 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6264 ins_pipe(ialu_reg_long); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6265 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6266 |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6267 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{ |
|
221
1e026f8da827
6710487: More than half of JDI Regression tests hang with COOPs in -Xcomp mode
kvn
parents:
182
diff
changeset
|
6268 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6269 match(Set dst (EncodeP src)); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6270 effect(KILL cr); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6271 format %{ "encode_heap_oop_not_null $dst,$src" %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6272 ins_encode %{ |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6273 __ encode_heap_oop_not_null($dst$$Register, $src$$Register); |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6274 %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6275 ins_pipe(ialu_reg_long); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6276 %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6277 |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6278 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{ |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
6279 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull && |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
6280 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6281 match(Set dst (DecodeN src)); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6282 effect(KILL cr); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6283 format %{ "decode_heap_oop $dst,$src" %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6284 ins_encode %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6285 Register s = $src$$Register; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6286 Register d = $dst$$Register; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6287 if (s != d) { |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6288 __ movq(d, s); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6289 } |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6290 __ decode_heap_oop(d); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6291 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6292 ins_pipe(ialu_reg_long); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6293 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6294 |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1567
diff
changeset
|
6295 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{ |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
6296 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull || |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
6297 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant); |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6298 match(Set dst (DecodeN src)); |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1567
diff
changeset
|
6299 effect(KILL cr); |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6300 format %{ "decode_heap_oop_not_null $dst,$src" %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6301 ins_encode %{ |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6302 Register s = $src$$Register; |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6303 Register d = $dst$$Register; |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6304 if (s != d) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6305 __ decode_heap_oop_not_null(d, s); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6306 } else { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6307 __ decode_heap_oop_not_null(d); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6308 } |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6309 %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6310 ins_pipe(ialu_reg_long); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6311 %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6312 |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6313 instruct encodeKlass_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6314 match(Set dst (EncodePKlass src)); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6315 effect(KILL cr); |
|
12056
740e263c80c6
8003424: Enable Class Data Sharing for CompressedOops
hseigel
parents:
10171
diff
changeset
|
6316 format %{ "encode_klass_not_null $dst,$src" %} |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6317 ins_encode %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6318 __ encode_klass_not_null($dst$$Register, $src$$Register); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6319 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6320 ins_pipe(ialu_reg_long); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6321 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6322 |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6323 instruct decodeKlass_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6324 match(Set dst (DecodeNKlass src)); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6325 effect(KILL cr); |
|
12056
740e263c80c6
8003424: Enable Class Data Sharing for CompressedOops
hseigel
parents:
10171
diff
changeset
|
6326 format %{ "decode_klass_not_null $dst,$src" %} |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6327 ins_encode %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6328 Register s = $src$$Register; |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6329 Register d = $dst$$Register; |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6330 if (s != d) { |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6331 __ decode_klass_not_null(d, s); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6332 } else { |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6333 __ decode_klass_not_null(d); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6334 } |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6335 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6336 ins_pipe(ialu_reg_long); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6337 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6338 |
|
113
ba764ed4b6f2
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coleenp
parents:
71
diff
changeset
|
6339 |
| 0 | 6340 //----------Conditional Move--------------------------------------------------- |
| 6341 // Jump | |
| 6342 // dummy instruction for generating temp registers | |
| 6343 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{ | |
| 6344 match(Jump (LShiftL switch_val shift)); | |
| 6345 ins_cost(350); | |
| 6346 predicate(false); | |
| 6347 effect(TEMP dest); | |
| 6348 | |
| 2008 | 6349 format %{ "leaq $dest, [$constantaddress]\n\t" |
| 0 | 6350 "jmp [$dest + $switch_val << $shift]\n\t" %} |
| 2008 | 6351 ins_encode %{ |
| 6352 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10 | |
| 6353 // to do that and the compiler is using that register as one it can allocate. | |
| 6354 // So we build it all by hand. | |
| 6355 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant); | |
| 6356 // ArrayAddress dispatch(table, index); | |
| 6357 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant); | |
| 6358 __ lea($dest$$Register, $constantaddress); | |
| 6359 __ jmp(dispatch); | |
| 6360 %} | |
| 0 | 6361 ins_pipe(pipe_jmp); |
| 6362 %} | |
| 6363 | |
| 6364 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{ | |
| 6365 match(Jump (AddL (LShiftL switch_val shift) offset)); | |
| 6366 ins_cost(350); | |
| 6367 effect(TEMP dest); | |
| 6368 | |
| 2008 | 6369 format %{ "leaq $dest, [$constantaddress]\n\t" |
| 0 | 6370 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %} |
| 2008 | 6371 ins_encode %{ |
| 6372 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10 | |
| 6373 // to do that and the compiler is using that register as one it can allocate. | |
| 6374 // So we build it all by hand. | |
| 6375 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant); | |
| 6376 // ArrayAddress dispatch(table, index); | |
| 6377 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant); | |
| 6378 __ lea($dest$$Register, $constantaddress); | |
| 6379 __ jmp(dispatch); | |
| 6380 %} | |
| 0 | 6381 ins_pipe(pipe_jmp); |
| 6382 %} | |
| 6383 | |
| 6384 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{ | |
| 6385 match(Jump switch_val); | |
| 6386 ins_cost(350); | |
| 6387 effect(TEMP dest); | |
| 6388 | |
| 2008 | 6389 format %{ "leaq $dest, [$constantaddress]\n\t" |
| 0 | 6390 "jmp [$dest + $switch_val]\n\t" %} |
| 2008 | 6391 ins_encode %{ |
| 6392 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10 | |
| 6393 // to do that and the compiler is using that register as one it can allocate. | |
| 6394 // So we build it all by hand. | |
| 6395 // Address index(noreg, switch_reg, Address::times_1); | |
| 6396 // ArrayAddress dispatch(table, index); | |
| 6397 Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1); | |
| 6398 __ lea($dest$$Register, $constantaddress); | |
| 6399 __ jmp(dispatch); | |
| 6400 %} | |
| 0 | 6401 ins_pipe(pipe_jmp); |
| 6402 %} | |
| 6403 | |
| 6404 // Conditional move | |
| 6405 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop) | |
| 6406 %{ | |
| 6407 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 6408 | |
| 6409 ins_cost(200); // XXX | |
| 6410 format %{ "cmovl$cop $dst, $src\t# signed, int" %} | |
| 6411 opcode(0x0F, 0x40); | |
| 6412 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 6413 ins_pipe(pipe_cmov_reg); | |
| 6414 %} | |
| 6415 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6416 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{ |
| 0 | 6417 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); |
| 6418 | |
| 6419 ins_cost(200); // XXX | |
| 6420 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %} | |
| 6421 opcode(0x0F, 0x40); | |
| 6422 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 6423 ins_pipe(pipe_cmov_reg); | |
| 6424 %} | |
| 6425 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6426 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6427 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6428 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6429 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6430 cmovI_regU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6431 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6432 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6433 |
| 0 | 6434 // Conditional move |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6435 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{ |
| 0 | 6436 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); |
| 6437 | |
| 6438 ins_cost(250); // XXX | |
| 6439 format %{ "cmovl$cop $dst, $src\t# signed, int" %} | |
| 6440 opcode(0x0F, 0x40); | |
| 6441 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
| 6442 ins_pipe(pipe_cmov_mem); | |
| 6443 %} | |
| 6444 | |
| 6445 // Conditional move | |
| 6446 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src) | |
| 6447 %{ | |
| 6448 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); | |
| 6449 | |
| 6450 ins_cost(250); // XXX | |
| 6451 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %} | |
| 6452 opcode(0x0F, 0x40); | |
| 6453 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
| 6454 ins_pipe(pipe_cmov_mem); | |
| 6455 %} | |
| 6456 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6457 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6458 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6459 ins_cost(250); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6460 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6461 cmovI_memU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6462 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6463 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6464 |
| 0 | 6465 // Conditional move |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6466 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop) |
|
c436414a719e
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163
diff
changeset
|
6467 %{ |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6468 match(Set dst (CMoveN (Binary cop cr) (Binary dst src))); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6469 |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6470 ins_cost(200); // XXX |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6471 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6472 opcode(0x0F, 0x40); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6473 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6474 ins_pipe(pipe_cmov_reg); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6475 %} |
|
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6476 |
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6477 // Conditional move |
|
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6478 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src) |
|
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6479 %{ |
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6480 match(Set dst (CMoveN (Binary cop cr) (Binary dst src))); |
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6481 |
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|
6482 ins_cost(200); // XXX |
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6483 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %} |
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6484 opcode(0x0F, 0x40); |
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6485 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); |
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6486 ins_pipe(pipe_cmov_reg); |
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6487 %} |
|
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|
6488 |
|
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6489 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{ |
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6490 match(Set dst (CMoveN (Binary cop cr) (Binary dst src))); |
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|
6491 ins_cost(200); |
|
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|
6492 expand %{ |
|
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|
6493 cmovN_regU(cop, cr, dst, src); |
|
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|
6494 %} |
|
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|
6495 %} |
|
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|
6496 |
|
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|
6497 // Conditional move |
| 0 | 6498 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop) |
| 6499 %{ | |
| 6500 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 6501 | |
| 6502 ins_cost(200); // XXX | |
| 6503 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %} | |
| 6504 opcode(0x0F, 0x40); | |
| 6505 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 6506 ins_pipe(pipe_cmov_reg); // XXX | |
| 6507 %} | |
| 6508 | |
| 6509 // Conditional move | |
|
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|
6510 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src) |
| 0 | 6511 %{ |
| 6512 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 6513 | |
| 6514 ins_cost(200); // XXX | |
| 6515 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %} | |
| 6516 opcode(0x0F, 0x40); | |
| 6517 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 6518 ins_pipe(pipe_cmov_reg); // XXX | |
| 6519 %} | |
| 6520 | |
|
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6521 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{ |
|
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6522 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); |
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|
6523 ins_cost(200); |
|
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|
6524 expand %{ |
|
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|
6525 cmovP_regU(cop, cr, dst, src); |
|
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|
6526 %} |
|
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|
6527 %} |
|
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|
6528 |
| 0 | 6529 // DISABLED: Requires the ADLC to emit a bottom_type call that |
| 6530 // correctly meets the two pointer arguments; one is an incoming | |
| 6531 // register but the other is a memory operand. ALSO appears to | |
| 6532 // be buggy with implicit null checks. | |
| 6533 // | |
| 6534 //// Conditional move | |
| 6535 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src) | |
| 6536 //%{ | |
| 6537 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 6538 // ins_cost(250); | |
| 6539 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 6540 // opcode(0x0F,0x40); | |
| 6541 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) ); | |
| 6542 // ins_pipe( pipe_cmov_mem ); | |
| 6543 //%} | |
| 6544 // | |
| 6545 //// Conditional move | |
| 6546 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src) | |
| 6547 //%{ | |
| 6548 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 6549 // ins_cost(250); | |
| 6550 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 6551 // opcode(0x0F,0x40); | |
| 6552 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) ); | |
| 6553 // ins_pipe( pipe_cmov_mem ); | |
| 6554 //%} | |
| 6555 | |
| 6556 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src) | |
| 6557 %{ | |
| 6558 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 6559 | |
| 6560 ins_cost(200); // XXX | |
| 6561 format %{ "cmovq$cop $dst, $src\t# signed, long" %} | |
| 6562 opcode(0x0F, 0x40); | |
| 6563 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 6564 ins_pipe(pipe_cmov_reg); // XXX | |
| 6565 %} | |
| 6566 | |
| 6567 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src) | |
| 6568 %{ | |
| 6569 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src)))); | |
| 6570 | |
| 6571 ins_cost(200); // XXX | |
| 6572 format %{ "cmovq$cop $dst, $src\t# signed, long" %} | |
| 6573 opcode(0x0F, 0x40); | |
| 6574 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
| 6575 ins_pipe(pipe_cmov_mem); // XXX | |
| 6576 %} | |
| 6577 | |
| 6578 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src) | |
| 6579 %{ | |
| 6580 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 6581 | |
| 6582 ins_cost(200); // XXX | |
| 6583 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %} | |
| 6584 opcode(0x0F, 0x40); | |
| 6585 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 6586 ins_pipe(pipe_cmov_reg); // XXX | |
| 6587 %} | |
| 6588 | |
|
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6589 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{ |
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|
6590 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); |
|
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|
6591 ins_cost(200); |
|
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|
6592 expand %{ |
|
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|
6593 cmovL_regU(cop, cr, dst, src); |
|
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|
6594 %} |
|
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|
6595 %} |
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|
6596 |
| 0 | 6597 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src) |
| 6598 %{ | |
| 6599 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src)))); | |
| 6600 | |
| 6601 ins_cost(200); // XXX | |
| 6602 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %} | |
| 6603 opcode(0x0F, 0x40); | |
| 6604 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
| 6605 ins_pipe(pipe_cmov_mem); // XXX | |
| 6606 %} | |
| 6607 | |
|
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6608 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{ |
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|
6609 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src)))); |
|
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|
6610 ins_cost(200); |
|
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|
6611 expand %{ |
|
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|
6612 cmovL_memU(cop, cr, dst, src); |
|
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|
6613 %} |
|
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|
6614 %} |
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|
6615 |
| 0 | 6616 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src) |
| 6617 %{ | |
| 6618 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 6619 | |
| 6620 ins_cost(200); // XXX | |
| 6621 format %{ "jn$cop skip\t# signed cmove float\n\t" | |
| 6622 "movss $dst, $src\n" | |
| 6623 "skip:" %} | |
| 4759 | 6624 ins_encode %{ |
| 6625 Label Lskip; | |
| 6626 // Invert sense of branch from sense of CMOV | |
| 6627 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
| 6628 __ movflt($dst$$XMMRegister, $src$$XMMRegister); | |
| 6629 __ bind(Lskip); | |
| 6630 %} | |
| 0 | 6631 ins_pipe(pipe_slow); |
| 6632 %} | |
| 6633 | |
| 6634 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src) | |
| 6635 // %{ | |
| 6636 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src)))); | |
| 6637 | |
| 6638 // ins_cost(200); // XXX | |
| 6639 // format %{ "jn$cop skip\t# signed cmove float\n\t" | |
| 6640 // "movss $dst, $src\n" | |
| 6641 // "skip:" %} | |
| 6642 // ins_encode(enc_cmovf_mem_branch(cop, dst, src)); | |
| 6643 // ins_pipe(pipe_slow); | |
| 6644 // %} | |
| 6645 | |
| 6646 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src) | |
| 6647 %{ | |
| 6648 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 6649 | |
| 6650 ins_cost(200); // XXX | |
| 6651 format %{ "jn$cop skip\t# unsigned cmove float\n\t" | |
| 6652 "movss $dst, $src\n" | |
| 6653 "skip:" %} | |
| 4759 | 6654 ins_encode %{ |
| 6655 Label Lskip; | |
| 6656 // Invert sense of branch from sense of CMOV | |
| 6657 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
| 6658 __ movflt($dst$$XMMRegister, $src$$XMMRegister); | |
| 6659 __ bind(Lskip); | |
| 6660 %} | |
| 0 | 6661 ins_pipe(pipe_slow); |
| 6662 %} | |
| 6663 | |
|
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|
6664 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{ |
|
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|
6665 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); |
|
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|
6666 ins_cost(200); |
|
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|
6667 expand %{ |
|
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|
6668 cmovF_regU(cop, cr, dst, src); |
|
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|
6669 %} |
|
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|
6670 %} |
|
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|
6671 |
| 0 | 6672 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src) |
| 6673 %{ | |
| 6674 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 6675 | |
| 6676 ins_cost(200); // XXX | |
| 6677 format %{ "jn$cop skip\t# signed cmove double\n\t" | |
| 6678 "movsd $dst, $src\n" | |
| 6679 "skip:" %} | |
| 4759 | 6680 ins_encode %{ |
| 6681 Label Lskip; | |
| 6682 // Invert sense of branch from sense of CMOV | |
| 6683 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
| 6684 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); | |
| 6685 __ bind(Lskip); | |
| 6686 %} | |
| 0 | 6687 ins_pipe(pipe_slow); |
| 6688 %} | |
| 6689 | |
| 6690 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src) | |
| 6691 %{ | |
| 6692 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 6693 | |
| 6694 ins_cost(200); // XXX | |
| 6695 format %{ "jn$cop skip\t# unsigned cmove double\n\t" | |
| 6696 "movsd $dst, $src\n" | |
| 6697 "skip:" %} | |
| 4759 | 6698 ins_encode %{ |
| 6699 Label Lskip; | |
| 6700 // Invert sense of branch from sense of CMOV | |
| 6701 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
| 6702 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); | |
| 6703 __ bind(Lskip); | |
| 6704 %} | |
| 0 | 6705 ins_pipe(pipe_slow); |
| 6706 %} | |
| 6707 | |
|
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|
6708 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{ |
|
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|
6709 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); |
|
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|
6710 ins_cost(200); |
|
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diff
changeset
|
6711 expand %{ |
|
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|
6712 cmovD_regU(cop, cr, dst, src); |
|
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|
6713 %} |
|
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|
6714 %} |
|
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|
6715 |
| 0 | 6716 //----------Arithmetic Instructions-------------------------------------------- |
| 6717 //----------Addition Instructions---------------------------------------------- | |
| 6718 | |
| 6719 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 6720 %{ | |
| 6721 match(Set dst (AddI dst src)); | |
| 6722 effect(KILL cr); | |
| 6723 | |
| 6724 format %{ "addl $dst, $src\t# int" %} | |
| 6725 opcode(0x03); | |
| 6726 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 6727 ins_pipe(ialu_reg_reg); | |
| 6728 %} | |
| 6729 | |
| 6730 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 6731 %{ | |
| 6732 match(Set dst (AddI dst src)); | |
| 6733 effect(KILL cr); | |
| 6734 | |
| 6735 format %{ "addl $dst, $src\t# int" %} | |
| 6736 opcode(0x81, 0x00); /* /0 id */ | |
| 6737 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 6738 ins_pipe( ialu_reg ); | |
| 6739 %} | |
| 6740 | |
| 6741 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 6742 %{ | |
| 6743 match(Set dst (AddI dst (LoadI src))); | |
| 6744 effect(KILL cr); | |
| 6745 | |
| 6746 ins_cost(125); // XXX | |
| 6747 format %{ "addl $dst, $src\t# int" %} | |
| 6748 opcode(0x03); | |
| 6749 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 6750 ins_pipe(ialu_reg_mem); | |
| 6751 %} | |
| 6752 | |
| 6753 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 6754 %{ | |
| 6755 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 6756 effect(KILL cr); | |
| 6757 | |
| 6758 ins_cost(150); // XXX | |
| 6759 format %{ "addl $dst, $src\t# int" %} | |
| 6760 opcode(0x01); /* Opcode 01 /r */ | |
| 6761 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 6762 ins_pipe(ialu_mem_reg); | |
| 6763 %} | |
| 6764 | |
| 6765 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 6766 %{ | |
| 6767 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 6768 effect(KILL cr); | |
| 6769 | |
| 6770 ins_cost(125); // XXX | |
| 6771 format %{ "addl $dst, $src\t# int" %} | |
| 6772 opcode(0x81); /* Opcode 81 /0 id */ | |
| 6773 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src)); | |
| 6774 ins_pipe(ialu_mem_imm); | |
| 6775 %} | |
| 6776 | |
| 6777 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr) | |
| 6778 %{ | |
| 6779 predicate(UseIncDec); | |
| 6780 match(Set dst (AddI dst src)); | |
| 6781 effect(KILL cr); | |
| 6782 | |
| 6783 format %{ "incl $dst\t# int" %} | |
| 6784 opcode(0xFF, 0x00); // FF /0 | |
| 6785 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 6786 ins_pipe(ialu_reg); | |
| 6787 %} | |
| 6788 | |
| 6789 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr) | |
| 6790 %{ | |
| 6791 predicate(UseIncDec); | |
| 6792 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 6793 effect(KILL cr); | |
| 6794 | |
| 6795 ins_cost(125); // XXX | |
| 6796 format %{ "incl $dst\t# int" %} | |
| 6797 opcode(0xFF); /* Opcode FF /0 */ | |
| 6798 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst)); | |
| 6799 ins_pipe(ialu_mem_imm); | |
| 6800 %} | |
| 6801 | |
| 6802 // XXX why does that use AddI | |
| 6803 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr) | |
| 6804 %{ | |
| 6805 predicate(UseIncDec); | |
| 6806 match(Set dst (AddI dst src)); | |
| 6807 effect(KILL cr); | |
| 6808 | |
| 6809 format %{ "decl $dst\t# int" %} | |
| 6810 opcode(0xFF, 0x01); // FF /1 | |
| 6811 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 6812 ins_pipe(ialu_reg); | |
| 6813 %} | |
| 6814 | |
| 6815 // XXX why does that use AddI | |
| 6816 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr) | |
| 6817 %{ | |
| 6818 predicate(UseIncDec); | |
| 6819 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 6820 effect(KILL cr); | |
| 6821 | |
| 6822 ins_cost(125); // XXX | |
| 6823 format %{ "decl $dst\t# int" %} | |
| 6824 opcode(0xFF); /* Opcode FF /1 */ | |
| 6825 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst)); | |
| 6826 ins_pipe(ialu_mem_imm); | |
| 6827 %} | |
| 6828 | |
| 6829 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1) | |
| 6830 %{ | |
| 6831 match(Set dst (AddI src0 src1)); | |
| 6832 | |
| 6833 ins_cost(110); | |
| 6834 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %} | |
| 6835 opcode(0x8D); /* 0x8D /r */ | |
| 6836 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX | |
| 6837 ins_pipe(ialu_reg_reg); | |
| 6838 %} | |
| 6839 | |
| 6840 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 6841 %{ | |
| 6842 match(Set dst (AddL dst src)); | |
| 6843 effect(KILL cr); | |
| 6844 | |
| 6845 format %{ "addq $dst, $src\t# long" %} | |
| 6846 opcode(0x03); | |
| 6847 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 6848 ins_pipe(ialu_reg_reg); | |
| 6849 %} | |
| 6850 | |
| 6851 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
| 6852 %{ | |
| 6853 match(Set dst (AddL dst src)); | |
| 6854 effect(KILL cr); | |
| 6855 | |
| 6856 format %{ "addq $dst, $src\t# long" %} | |
| 6857 opcode(0x81, 0x00); /* /0 id */ | |
| 6858 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 6859 ins_pipe( ialu_reg ); | |
| 6860 %} | |
| 6861 | |
| 6862 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 6863 %{ | |
| 6864 match(Set dst (AddL dst (LoadL src))); | |
| 6865 effect(KILL cr); | |
| 6866 | |
| 6867 ins_cost(125); // XXX | |
| 6868 format %{ "addq $dst, $src\t# long" %} | |
| 6869 opcode(0x03); | |
| 6870 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 6871 ins_pipe(ialu_reg_mem); | |
| 6872 %} | |
| 6873 | |
| 6874 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 6875 %{ | |
| 6876 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
| 6877 effect(KILL cr); | |
| 6878 | |
| 6879 ins_cost(150); // XXX | |
| 6880 format %{ "addq $dst, $src\t# long" %} | |
| 6881 opcode(0x01); /* Opcode 01 /r */ | |
| 6882 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 6883 ins_pipe(ialu_mem_reg); | |
| 6884 %} | |
| 6885 | |
| 6886 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 6887 %{ | |
| 6888 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
| 6889 effect(KILL cr); | |
| 6890 | |
| 6891 ins_cost(125); // XXX | |
| 6892 format %{ "addq $dst, $src\t# long" %} | |
| 6893 opcode(0x81); /* Opcode 81 /0 id */ | |
| 6894 ins_encode(REX_mem_wide(dst), | |
| 6895 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src)); | |
| 6896 ins_pipe(ialu_mem_imm); | |
| 6897 %} | |
| 6898 | |
| 6899 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr) | |
| 6900 %{ | |
| 6901 predicate(UseIncDec); | |
| 6902 match(Set dst (AddL dst src)); | |
| 6903 effect(KILL cr); | |
| 6904 | |
| 6905 format %{ "incq $dst\t# long" %} | |
| 6906 opcode(0xFF, 0x00); // FF /0 | |
| 6907 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 6908 ins_pipe(ialu_reg); | |
| 6909 %} | |
| 6910 | |
| 6911 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr) | |
| 6912 %{ | |
| 6913 predicate(UseIncDec); | |
| 6914 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
| 6915 effect(KILL cr); | |
| 6916 | |
| 6917 ins_cost(125); // XXX | |
| 6918 format %{ "incq $dst\t# long" %} | |
| 6919 opcode(0xFF); /* Opcode FF /0 */ | |
| 6920 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst)); | |
| 6921 ins_pipe(ialu_mem_imm); | |
| 6922 %} | |
| 6923 | |
| 6924 // XXX why does that use AddL | |
| 6925 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr) | |
| 6926 %{ | |
| 6927 predicate(UseIncDec); | |
| 6928 match(Set dst (AddL dst src)); | |
| 6929 effect(KILL cr); | |
| 6930 | |
| 6931 format %{ "decq $dst\t# long" %} | |
| 6932 opcode(0xFF, 0x01); // FF /1 | |
| 6933 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 6934 ins_pipe(ialu_reg); | |
| 6935 %} | |
| 6936 | |
| 6937 // XXX why does that use AddL | |
| 6938 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr) | |
| 6939 %{ | |
| 6940 predicate(UseIncDec); | |
| 6941 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
| 6942 effect(KILL cr); | |
| 6943 | |
| 6944 ins_cost(125); // XXX | |
| 6945 format %{ "decq $dst\t# long" %} | |
| 6946 opcode(0xFF); /* Opcode FF /1 */ | |
| 6947 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst)); | |
| 6948 ins_pipe(ialu_mem_imm); | |
| 6949 %} | |
| 6950 | |
| 6951 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1) | |
| 6952 %{ | |
| 6953 match(Set dst (AddL src0 src1)); | |
| 6954 | |
| 6955 ins_cost(110); | |
| 6956 format %{ "leaq $dst, [$src0 + $src1]\t# long" %} | |
| 6957 opcode(0x8D); /* 0x8D /r */ | |
| 6958 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX | |
| 6959 ins_pipe(ialu_reg_reg); | |
| 6960 %} | |
| 6961 | |
| 6962 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr) | |
| 6963 %{ | |
| 6964 match(Set dst (AddP dst src)); | |
| 6965 effect(KILL cr); | |
| 6966 | |
| 6967 format %{ "addq $dst, $src\t# ptr" %} | |
| 6968 opcode(0x03); | |
| 6969 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 6970 ins_pipe(ialu_reg_reg); | |
| 6971 %} | |
| 6972 | |
| 6973 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr) | |
| 6974 %{ | |
| 6975 match(Set dst (AddP dst src)); | |
| 6976 effect(KILL cr); | |
| 6977 | |
| 6978 format %{ "addq $dst, $src\t# ptr" %} | |
| 6979 opcode(0x81, 0x00); /* /0 id */ | |
| 6980 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 6981 ins_pipe( ialu_reg ); | |
| 6982 %} | |
| 6983 | |
| 6984 // XXX addP mem ops ???? | |
| 6985 | |
| 6986 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1) | |
| 6987 %{ | |
| 6988 match(Set dst (AddP src0 src1)); | |
| 6989 | |
| 6990 ins_cost(110); | |
| 6991 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %} | |
| 6992 opcode(0x8D); /* 0x8D /r */ | |
| 6993 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX | |
| 6994 ins_pipe(ialu_reg_reg); | |
| 6995 %} | |
| 6996 | |
| 6997 instruct checkCastPP(rRegP dst) | |
| 6998 %{ | |
| 6999 match(Set dst (CheckCastPP dst)); | |
| 7000 | |
| 7001 size(0); | |
| 7002 format %{ "# checkcastPP of $dst" %} | |
| 7003 ins_encode(/* empty encoding */); | |
| 7004 ins_pipe(empty); | |
| 7005 %} | |
| 7006 | |
| 7007 instruct castPP(rRegP dst) | |
| 7008 %{ | |
| 7009 match(Set dst (CastPP dst)); | |
| 7010 | |
| 7011 size(0); | |
| 7012 format %{ "# castPP of $dst" %} | |
| 7013 ins_encode(/* empty encoding */); | |
| 7014 ins_pipe(empty); | |
| 7015 %} | |
| 7016 | |
| 7017 instruct castII(rRegI dst) | |
| 7018 %{ | |
| 7019 match(Set dst (CastII dst)); | |
| 7020 | |
| 7021 size(0); | |
| 7022 format %{ "# castII of $dst" %} | |
| 7023 ins_encode(/* empty encoding */); | |
| 7024 ins_cost(0); | |
| 7025 ins_pipe(empty); | |
| 7026 %} | |
| 7027 | |
| 7028 // LoadP-locked same as a regular LoadP when used with compare-swap | |
| 7029 instruct loadPLocked(rRegP dst, memory mem) | |
| 7030 %{ | |
| 7031 match(Set dst (LoadPLocked mem)); | |
| 7032 | |
| 7033 ins_cost(125); // XXX | |
| 7034 format %{ "movq $dst, $mem\t# ptr locked" %} | |
| 7035 opcode(0x8B); | |
| 7036 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 7037 ins_pipe(ialu_reg_mem); // XXX | |
| 7038 %} | |
| 7039 | |
| 7040 // Conditional-store of the updated heap-top. | |
| 7041 // Used during allocation of the shared heap. | |
| 7042 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel. | |
| 7043 | |
| 7044 instruct storePConditional(memory heap_top_ptr, | |
| 7045 rax_RegP oldval, rRegP newval, | |
| 7046 rFlagsReg cr) | |
| 7047 %{ | |
| 7048 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval))); | |
|
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7049 |
| 0 | 7050 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) " |
| 7051 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %} | |
| 7052 opcode(0x0F, 0xB1); | |
| 7053 ins_encode(lock_prefix, | |
| 7054 REX_reg_mem_wide(newval, heap_top_ptr), | |
| 7055 OpcP, OpcS, | |
| 7056 reg_mem(newval, heap_top_ptr)); | |
| 7057 ins_pipe(pipe_cmpxchg); | |
| 7058 %} | |
| 7059 | |
|
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7060 // Conditional-store of an int value. |
|
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7061 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG. |
|
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7062 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr) |
|
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7063 %{ |
|
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7064 match(Set cr (StoreIConditional mem (Binary oldval newval))); |
|
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7065 effect(KILL oldval); |
|
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7066 |
|
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7067 format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %} |
| 0 | 7068 opcode(0x0F, 0xB1); |
| 7069 ins_encode(lock_prefix, | |
|
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7070 REX_reg_mem(newval, mem), |
| 0 | 7071 OpcP, OpcS, |
|
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7072 reg_mem(newval, mem)); |
| 0 | 7073 ins_pipe(pipe_cmpxchg); |
| 7074 %} | |
| 7075 | |
|
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7076 // Conditional-store of a long value. |
|
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7077 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG. |
|
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7078 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr) |
|
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7079 %{ |
|
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7080 match(Set cr (StoreLConditional mem (Binary oldval newval))); |
|
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7081 effect(KILL oldval); |
|
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|
7082 |
|
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7083 format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %} |
| 0 | 7084 opcode(0x0F, 0xB1); |
| 7085 ins_encode(lock_prefix, | |
|
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7086 REX_reg_mem_wide(newval, mem), |
| 0 | 7087 OpcP, OpcS, |
|
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7088 reg_mem(newval, mem)); |
| 0 | 7089 ins_pipe(pipe_cmpxchg); |
| 7090 %} | |
| 7091 | |
|
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|
7092 |
|
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7093 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them |
| 0 | 7094 instruct compareAndSwapP(rRegI res, |
| 7095 memory mem_ptr, | |
| 7096 rax_RegP oldval, rRegP newval, | |
| 7097 rFlagsReg cr) | |
| 7098 %{ | |
|
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|
7099 predicate(VM_Version::supports_cx8()); |
| 0 | 7100 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); |
| 7101 effect(KILL cr, KILL oldval); | |
| 7102 | |
| 7103 format %{ "cmpxchgq $mem_ptr,$newval\t# " | |
| 7104 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" | |
| 7105 "sete $res\n\t" | |
| 7106 "movzbl $res, $res" %} | |
| 7107 opcode(0x0F, 0xB1); | |
| 7108 ins_encode(lock_prefix, | |
| 7109 REX_reg_mem_wide(newval, mem_ptr), | |
| 7110 OpcP, OpcS, | |
| 7111 reg_mem(newval, mem_ptr), | |
| 7112 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete | |
| 7113 REX_reg_breg(res, res), // movzbl | |
| 7114 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); | |
| 7115 ins_pipe( pipe_cmpxchg ); | |
| 7116 %} | |
| 7117 | |
| 7118 instruct compareAndSwapL(rRegI res, | |
| 7119 memory mem_ptr, | |
| 7120 rax_RegL oldval, rRegL newval, | |
| 7121 rFlagsReg cr) | |
| 7122 %{ | |
|
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7123 predicate(VM_Version::supports_cx8()); |
| 0 | 7124 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); |
| 7125 effect(KILL cr, KILL oldval); | |
| 7126 | |
| 7127 format %{ "cmpxchgq $mem_ptr,$newval\t# " | |
| 7128 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" | |
| 7129 "sete $res\n\t" | |
| 7130 "movzbl $res, $res" %} | |
| 7131 opcode(0x0F, 0xB1); | |
| 7132 ins_encode(lock_prefix, | |
| 7133 REX_reg_mem_wide(newval, mem_ptr), | |
| 7134 OpcP, OpcS, | |
| 7135 reg_mem(newval, mem_ptr), | |
| 7136 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete | |
| 7137 REX_reg_breg(res, res), // movzbl | |
| 7138 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); | |
| 7139 ins_pipe( pipe_cmpxchg ); | |
| 7140 %} | |
| 7141 | |
| 7142 instruct compareAndSwapI(rRegI res, | |
| 7143 memory mem_ptr, | |
| 7144 rax_RegI oldval, rRegI newval, | |
| 7145 rFlagsReg cr) | |
| 7146 %{ | |
| 7147 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); | |
| 7148 effect(KILL cr, KILL oldval); | |
| 7149 | |
| 7150 format %{ "cmpxchgl $mem_ptr,$newval\t# " | |
| 7151 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" | |
| 7152 "sete $res\n\t" | |
| 7153 "movzbl $res, $res" %} | |
| 7154 opcode(0x0F, 0xB1); | |
| 7155 ins_encode(lock_prefix, | |
| 7156 REX_reg_mem(newval, mem_ptr), | |
| 7157 OpcP, OpcS, | |
| 7158 reg_mem(newval, mem_ptr), | |
| 7159 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete | |
| 7160 REX_reg_breg(res, res), // movzbl | |
| 7161 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); | |
| 7162 ins_pipe( pipe_cmpxchg ); | |
| 7163 %} | |
| 7164 | |
| 7165 | |
|
113
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|
7166 instruct compareAndSwapN(rRegI res, |
|
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|
7167 memory mem_ptr, |
|
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|
7168 rax_RegN oldval, rRegN newval, |
|
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|
7169 rFlagsReg cr) %{ |
|
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|
7170 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); |
|
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|
7171 effect(KILL cr, KILL oldval); |
|
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|
7172 |
|
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|
7173 format %{ "cmpxchgl $mem_ptr,$newval\t# " |
|
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|
7174 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" |
|
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|
7175 "sete $res\n\t" |
|
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|
7176 "movzbl $res, $res" %} |
|
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|
7177 opcode(0x0F, 0xB1); |
|
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|
7178 ins_encode(lock_prefix, |
|
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|
7179 REX_reg_mem(newval, mem_ptr), |
|
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|
7180 OpcP, OpcS, |
|
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|
7181 reg_mem(newval, mem_ptr), |
|
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|
7182 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete |
|
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|
7183 REX_reg_breg(res, res), // movzbl |
|
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|
7184 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); |
|
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|
7185 ins_pipe( pipe_cmpxchg ); |
|
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|
7186 %} |
|
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|
7187 |
|
6795
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
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diff
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|
7188 instruct xaddI_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{ |
|
7eca5de9e0b6
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changeset
|
7189 predicate(n->as_LoadStore()->result_not_used()); |
|
7eca5de9e0b6
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diff
changeset
|
7190 match(Set dummy (GetAndAddI mem add)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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diff
changeset
|
7191 effect(KILL cr); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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diff
changeset
|
7192 format %{ "ADDL [$mem],$add" %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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diff
changeset
|
7193 ins_encode %{ |
|
7eca5de9e0b6
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diff
changeset
|
7194 if (os::is_MP()) { __ lock(); } |
|
7eca5de9e0b6
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diff
changeset
|
7195 __ addl($mem$$Address, $add$$constant); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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diff
changeset
|
7196 %} |
|
7eca5de9e0b6
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diff
changeset
|
7197 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
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diff
changeset
|
7198 %} |
|
7eca5de9e0b6
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6725
diff
changeset
|
7199 |
|
7eca5de9e0b6
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roland
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diff
changeset
|
7200 instruct xaddI( memory mem, rRegI newval, rFlagsReg cr) %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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diff
changeset
|
7201 match(Set newval (GetAndAddI mem newval)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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diff
changeset
|
7202 effect(KILL cr); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
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diff
changeset
|
7203 format %{ "XADDL [$mem],$newval" %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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changeset
|
7204 ins_encode %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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diff
changeset
|
7205 if (os::is_MP()) { __ lock(); } |
|
7eca5de9e0b6
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diff
changeset
|
7206 __ xaddl($mem$$Address, $newval$$Register); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
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diff
changeset
|
7207 %} |
|
7eca5de9e0b6
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diff
changeset
|
7208 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
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6725
diff
changeset
|
7209 %} |
|
7eca5de9e0b6
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roland
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diff
changeset
|
7210 |
|
10139
35c15dad89ea
8011901: Unsafe.getAndAddLong(obj, off, delta) does not work properly with long deltas
roland
parents:
9154
diff
changeset
|
7211 instruct xaddL_no_res( memory mem, Universe dummy, immL32 add, rFlagsReg cr) %{ |
|
6795
7eca5de9e0b6
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roland
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diff
changeset
|
7212 predicate(n->as_LoadStore()->result_not_used()); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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diff
changeset
|
7213 match(Set dummy (GetAndAddL mem add)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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diff
changeset
|
7214 effect(KILL cr); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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diff
changeset
|
7215 format %{ "ADDQ [$mem],$add" %} |
|
7eca5de9e0b6
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diff
changeset
|
7216 ins_encode %{ |
|
7eca5de9e0b6
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roland
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diff
changeset
|
7217 if (os::is_MP()) { __ lock(); } |
|
7eca5de9e0b6
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roland
parents:
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diff
changeset
|
7218 __ addq($mem$$Address, $add$$constant); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
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6725
diff
changeset
|
7219 %} |
|
7eca5de9e0b6
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roland
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6725
diff
changeset
|
7220 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
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6725
diff
changeset
|
7221 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
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6725
diff
changeset
|
7222 |
|
7eca5de9e0b6
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roland
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diff
changeset
|
7223 instruct xaddL( memory mem, rRegL newval, rFlagsReg cr) %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7224 match(Set newval (GetAndAddL mem newval)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7225 effect(KILL cr); |
|
7eca5de9e0b6
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roland
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diff
changeset
|
7226 format %{ "XADDQ [$mem],$newval" %} |
|
7eca5de9e0b6
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diff
changeset
|
7227 ins_encode %{ |
|
7eca5de9e0b6
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roland
parents:
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diff
changeset
|
7228 if (os::is_MP()) { __ lock(); } |
|
7eca5de9e0b6
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changeset
|
7229 __ xaddq($mem$$Address, $newval$$Register); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
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6725
diff
changeset
|
7230 %} |
|
7eca5de9e0b6
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roland
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diff
changeset
|
7231 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
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6725
diff
changeset
|
7232 %} |
|
7eca5de9e0b6
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roland
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6725
diff
changeset
|
7233 |
|
7eca5de9e0b6
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roland
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diff
changeset
|
7234 instruct xchgI( memory mem, rRegI newval) %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
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diff
changeset
|
7235 match(Set newval (GetAndSetI mem newval)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
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diff
changeset
|
7236 format %{ "XCHGL $newval,[$mem]" %} |
|
7eca5de9e0b6
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6725
diff
changeset
|
7237 ins_encode %{ |
|
7eca5de9e0b6
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roland
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diff
changeset
|
7238 __ xchgl($newval$$Register, $mem$$Address); |
|
7eca5de9e0b6
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roland
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6725
diff
changeset
|
7239 %} |
|
7eca5de9e0b6
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diff
changeset
|
7240 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
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roland
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6725
diff
changeset
|
7241 %} |
|
7eca5de9e0b6
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roland
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6725
diff
changeset
|
7242 |
|
7eca5de9e0b6
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roland
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6725
diff
changeset
|
7243 instruct xchgL( memory mem, rRegL newval) %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
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6725
diff
changeset
|
7244 match(Set newval (GetAndSetL mem newval)); |
|
7eca5de9e0b6
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roland
parents:
6725
diff
changeset
|
7245 format %{ "XCHGL $newval,[$mem]" %} |
|
7eca5de9e0b6
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roland
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6725
diff
changeset
|
7246 ins_encode %{ |
|
7eca5de9e0b6
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roland
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diff
changeset
|
7247 __ xchgq($newval$$Register, $mem$$Address); |
|
7eca5de9e0b6
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roland
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6725
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changeset
|
7248 %} |
|
7eca5de9e0b6
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diff
changeset
|
7249 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
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6725
diff
changeset
|
7250 %} |
|
7eca5de9e0b6
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roland
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6725
diff
changeset
|
7251 |
|
7eca5de9e0b6
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roland
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6725
diff
changeset
|
7252 instruct xchgP( memory mem, rRegP newval) %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
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6725
diff
changeset
|
7253 match(Set newval (GetAndSetP mem newval)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
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6725
diff
changeset
|
7254 format %{ "XCHGQ $newval,[$mem]" %} |
|
7eca5de9e0b6
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roland
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6725
diff
changeset
|
7255 ins_encode %{ |
|
7eca5de9e0b6
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roland
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diff
changeset
|
7256 __ xchgq($newval$$Register, $mem$$Address); |
|
7eca5de9e0b6
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roland
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6725
diff
changeset
|
7257 %} |
|
7eca5de9e0b6
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roland
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6725
diff
changeset
|
7258 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
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roland
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6725
diff
changeset
|
7259 %} |
|
7eca5de9e0b6
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roland
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6725
diff
changeset
|
7260 |
|
7eca5de9e0b6
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roland
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6725
diff
changeset
|
7261 instruct xchgN( memory mem, rRegN newval) %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
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6725
diff
changeset
|
7262 match(Set newval (GetAndSetN mem newval)); |
|
7eca5de9e0b6
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roland
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6725
diff
changeset
|
7263 format %{ "XCHGL $newval,$mem]" %} |
|
7eca5de9e0b6
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roland
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6725
diff
changeset
|
7264 ins_encode %{ |
|
7eca5de9e0b6
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roland
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6725
diff
changeset
|
7265 __ xchgl($newval$$Register, $mem$$Address); |
|
7eca5de9e0b6
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roland
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6725
diff
changeset
|
7266 %} |
|
7eca5de9e0b6
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roland
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6725
diff
changeset
|
7267 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
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roland
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6725
diff
changeset
|
7268 %} |
|
7eca5de9e0b6
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|
7269 |
| 0 | 7270 //----------Subtraction Instructions------------------------------------------- |
| 7271 | |
| 7272 // Integer Subtraction Instructions | |
| 7273 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 7274 %{ | |
| 7275 match(Set dst (SubI dst src)); | |
| 7276 effect(KILL cr); | |
| 7277 | |
| 7278 format %{ "subl $dst, $src\t# int" %} | |
| 7279 opcode(0x2B); | |
| 7280 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 7281 ins_pipe(ialu_reg_reg); | |
| 7282 %} | |
| 7283 | |
| 7284 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 7285 %{ | |
| 7286 match(Set dst (SubI dst src)); | |
| 7287 effect(KILL cr); | |
| 7288 | |
| 7289 format %{ "subl $dst, $src\t# int" %} | |
| 7290 opcode(0x81, 0x05); /* Opcode 81 /5 */ | |
| 7291 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 7292 ins_pipe(ialu_reg); | |
| 7293 %} | |
| 7294 | |
| 7295 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 7296 %{ | |
| 7297 match(Set dst (SubI dst (LoadI src))); | |
| 7298 effect(KILL cr); | |
| 7299 | |
| 7300 ins_cost(125); | |
| 7301 format %{ "subl $dst, $src\t# int" %} | |
| 7302 opcode(0x2B); | |
| 7303 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 7304 ins_pipe(ialu_reg_mem); | |
| 7305 %} | |
| 7306 | |
| 7307 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 7308 %{ | |
| 7309 match(Set dst (StoreI dst (SubI (LoadI dst) src))); | |
| 7310 effect(KILL cr); | |
| 7311 | |
| 7312 ins_cost(150); | |
| 7313 format %{ "subl $dst, $src\t# int" %} | |
| 7314 opcode(0x29); /* Opcode 29 /r */ | |
| 7315 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 7316 ins_pipe(ialu_mem_reg); | |
| 7317 %} | |
| 7318 | |
| 7319 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 7320 %{ | |
| 7321 match(Set dst (StoreI dst (SubI (LoadI dst) src))); | |
| 7322 effect(KILL cr); | |
| 7323 | |
| 7324 ins_cost(125); // XXX | |
| 7325 format %{ "subl $dst, $src\t# int" %} | |
| 7326 opcode(0x81); /* Opcode 81 /5 id */ | |
| 7327 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src)); | |
| 7328 ins_pipe(ialu_mem_imm); | |
| 7329 %} | |
| 7330 | |
| 7331 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 7332 %{ | |
| 7333 match(Set dst (SubL dst src)); | |
| 7334 effect(KILL cr); | |
| 7335 | |
| 7336 format %{ "subq $dst, $src\t# long" %} | |
| 7337 opcode(0x2B); | |
| 7338 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 7339 ins_pipe(ialu_reg_reg); | |
| 7340 %} | |
| 7341 | |
| 7342 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr) | |
| 7343 %{ | |
| 7344 match(Set dst (SubL dst src)); | |
| 7345 effect(KILL cr); | |
| 7346 | |
| 7347 format %{ "subq $dst, $src\t# long" %} | |
| 7348 opcode(0x81, 0x05); /* Opcode 81 /5 */ | |
| 7349 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 7350 ins_pipe(ialu_reg); | |
| 7351 %} | |
| 7352 | |
| 7353 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 7354 %{ | |
| 7355 match(Set dst (SubL dst (LoadL src))); | |
| 7356 effect(KILL cr); | |
| 7357 | |
| 7358 ins_cost(125); | |
| 7359 format %{ "subq $dst, $src\t# long" %} | |
| 7360 opcode(0x2B); | |
| 7361 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 7362 ins_pipe(ialu_reg_mem); | |
| 7363 %} | |
| 7364 | |
| 7365 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 7366 %{ | |
| 7367 match(Set dst (StoreL dst (SubL (LoadL dst) src))); | |
| 7368 effect(KILL cr); | |
| 7369 | |
| 7370 ins_cost(150); | |
| 7371 format %{ "subq $dst, $src\t# long" %} | |
| 7372 opcode(0x29); /* Opcode 29 /r */ | |
| 7373 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 7374 ins_pipe(ialu_mem_reg); | |
| 7375 %} | |
| 7376 | |
| 7377 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 7378 %{ | |
| 7379 match(Set dst (StoreL dst (SubL (LoadL dst) src))); | |
| 7380 effect(KILL cr); | |
| 7381 | |
| 7382 ins_cost(125); // XXX | |
| 7383 format %{ "subq $dst, $src\t# long" %} | |
| 7384 opcode(0x81); /* Opcode 81 /5 id */ | |
| 7385 ins_encode(REX_mem_wide(dst), | |
| 7386 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src)); | |
| 7387 ins_pipe(ialu_mem_imm); | |
| 7388 %} | |
| 7389 | |
| 7390 // Subtract from a pointer | |
| 7391 // XXX hmpf??? | |
| 7392 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr) | |
| 7393 %{ | |
| 7394 match(Set dst (AddP dst (SubI zero src))); | |
| 7395 effect(KILL cr); | |
| 7396 | |
| 7397 format %{ "subq $dst, $src\t# ptr - int" %} | |
| 7398 opcode(0x2B); | |
| 7399 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 7400 ins_pipe(ialu_reg_reg); | |
| 7401 %} | |
| 7402 | |
| 7403 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr) | |
| 7404 %{ | |
| 7405 match(Set dst (SubI zero dst)); | |
| 7406 effect(KILL cr); | |
| 7407 | |
| 7408 format %{ "negl $dst\t# int" %} | |
| 7409 opcode(0xF7, 0x03); // Opcode F7 /3 | |
| 7410 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 7411 ins_pipe(ialu_reg); | |
| 7412 %} | |
| 7413 | |
| 7414 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr) | |
| 7415 %{ | |
| 7416 match(Set dst (StoreI dst (SubI zero (LoadI dst)))); | |
| 7417 effect(KILL cr); | |
| 7418 | |
| 7419 format %{ "negl $dst\t# int" %} | |
| 7420 opcode(0xF7, 0x03); // Opcode F7 /3 | |
| 7421 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 7422 ins_pipe(ialu_reg); | |
| 7423 %} | |
| 7424 | |
| 7425 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr) | |
| 7426 %{ | |
| 7427 match(Set dst (SubL zero dst)); | |
| 7428 effect(KILL cr); | |
| 7429 | |
| 7430 format %{ "negq $dst\t# long" %} | |
| 7431 opcode(0xF7, 0x03); // Opcode F7 /3 | |
| 7432 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 7433 ins_pipe(ialu_reg); | |
| 7434 %} | |
| 7435 | |
| 7436 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr) | |
| 7437 %{ | |
| 7438 match(Set dst (StoreL dst (SubL zero (LoadL dst)))); | |
| 7439 effect(KILL cr); | |
| 7440 | |
| 7441 format %{ "negq $dst\t# long" %} | |
| 7442 opcode(0xF7, 0x03); // Opcode F7 /3 | |
| 7443 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 7444 ins_pipe(ialu_reg); | |
| 7445 %} | |
| 7446 | |
| 7447 //----------Multiplication/Division Instructions------------------------------- | |
| 7448 // Integer Multiplication Instructions | |
| 7449 // Multiply Register | |
| 7450 | |
| 7451 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 7452 %{ | |
| 7453 match(Set dst (MulI dst src)); | |
| 7454 effect(KILL cr); | |
| 7455 | |
| 7456 ins_cost(300); | |
| 7457 format %{ "imull $dst, $src\t# int" %} | |
| 7458 opcode(0x0F, 0xAF); | |
| 7459 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 7460 ins_pipe(ialu_reg_reg_alu0); | |
| 7461 %} | |
| 7462 | |
| 7463 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr) | |
| 7464 %{ | |
| 7465 match(Set dst (MulI src imm)); | |
| 7466 effect(KILL cr); | |
| 7467 | |
| 7468 ins_cost(300); | |
| 7469 format %{ "imull $dst, $src, $imm\t# int" %} | |
| 7470 opcode(0x69); /* 69 /r id */ | |
| 7471 ins_encode(REX_reg_reg(dst, src), | |
| 7472 OpcSE(imm), reg_reg(dst, src), Con8or32(imm)); | |
| 7473 ins_pipe(ialu_reg_reg_alu0); | |
| 7474 %} | |
| 7475 | |
| 7476 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 7477 %{ | |
| 7478 match(Set dst (MulI dst (LoadI src))); | |
| 7479 effect(KILL cr); | |
| 7480 | |
| 7481 ins_cost(350); | |
| 7482 format %{ "imull $dst, $src\t# int" %} | |
| 7483 opcode(0x0F, 0xAF); | |
| 7484 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src)); | |
| 7485 ins_pipe(ialu_reg_mem_alu0); | |
| 7486 %} | |
| 7487 | |
| 7488 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr) | |
| 7489 %{ | |
| 7490 match(Set dst (MulI (LoadI src) imm)); | |
| 7491 effect(KILL cr); | |
| 7492 | |
| 7493 ins_cost(300); | |
| 7494 format %{ "imull $dst, $src, $imm\t# int" %} | |
| 7495 opcode(0x69); /* 69 /r id */ | |
| 7496 ins_encode(REX_reg_mem(dst, src), | |
| 7497 OpcSE(imm), reg_mem(dst, src), Con8or32(imm)); | |
| 7498 ins_pipe(ialu_reg_mem_alu0); | |
| 7499 %} | |
| 7500 | |
| 7501 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 7502 %{ | |
| 7503 match(Set dst (MulL dst src)); | |
| 7504 effect(KILL cr); | |
| 7505 | |
| 7506 ins_cost(300); | |
| 7507 format %{ "imulq $dst, $src\t# long" %} | |
| 7508 opcode(0x0F, 0xAF); | |
| 7509 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 7510 ins_pipe(ialu_reg_reg_alu0); | |
| 7511 %} | |
| 7512 | |
| 7513 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr) | |
| 7514 %{ | |
| 7515 match(Set dst (MulL src imm)); | |
| 7516 effect(KILL cr); | |
| 7517 | |
| 7518 ins_cost(300); | |
| 7519 format %{ "imulq $dst, $src, $imm\t# long" %} | |
| 7520 opcode(0x69); /* 69 /r id */ | |
| 7521 ins_encode(REX_reg_reg_wide(dst, src), | |
| 7522 OpcSE(imm), reg_reg(dst, src), Con8or32(imm)); | |
| 7523 ins_pipe(ialu_reg_reg_alu0); | |
| 7524 %} | |
| 7525 | |
| 7526 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 7527 %{ | |
| 7528 match(Set dst (MulL dst (LoadL src))); | |
| 7529 effect(KILL cr); | |
| 7530 | |
| 7531 ins_cost(350); | |
| 7532 format %{ "imulq $dst, $src\t# long" %} | |
| 7533 opcode(0x0F, 0xAF); | |
| 7534 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src)); | |
| 7535 ins_pipe(ialu_reg_mem_alu0); | |
| 7536 %} | |
| 7537 | |
| 7538 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr) | |
| 7539 %{ | |
| 7540 match(Set dst (MulL (LoadL src) imm)); | |
| 7541 effect(KILL cr); | |
| 7542 | |
| 7543 ins_cost(300); | |
| 7544 format %{ "imulq $dst, $src, $imm\t# long" %} | |
| 7545 opcode(0x69); /* 69 /r id */ | |
| 7546 ins_encode(REX_reg_mem_wide(dst, src), | |
| 7547 OpcSE(imm), reg_mem(dst, src), Con8or32(imm)); | |
| 7548 ins_pipe(ialu_reg_mem_alu0); | |
| 7549 %} | |
| 7550 | |
| 145 | 7551 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr) |
| 7552 %{ | |
| 7553 match(Set dst (MulHiL src rax)); | |
| 7554 effect(USE_KILL rax, KILL cr); | |
| 7555 | |
| 7556 ins_cost(300); | |
| 7557 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %} | |
| 7558 opcode(0xF7, 0x5); /* Opcode F7 /5 */ | |
| 7559 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src)); | |
| 7560 ins_pipe(ialu_reg_reg_alu0); | |
| 7561 %} | |
| 7562 | |
| 0 | 7563 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div, |
| 7564 rFlagsReg cr) | |
| 7565 %{ | |
| 7566 match(Set rax (DivI rax div)); | |
| 7567 effect(KILL rdx, KILL cr); | |
| 7568 | |
| 7569 ins_cost(30*100+10*100); // XXX | |
| 7570 format %{ "cmpl rax, 0x80000000\t# idiv\n\t" | |
| 7571 "jne,s normal\n\t" | |
| 7572 "xorl rdx, rdx\n\t" | |
| 7573 "cmpl $div, -1\n\t" | |
| 7574 "je,s done\n" | |
| 7575 "normal: cdql\n\t" | |
| 7576 "idivl $div\n" | |
| 7577 "done:" %} | |
| 7578 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 7579 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div)); | |
| 7580 ins_pipe(ialu_reg_reg_alu0); | |
| 7581 %} | |
| 7582 | |
| 7583 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div, | |
| 7584 rFlagsReg cr) | |
| 7585 %{ | |
| 7586 match(Set rax (DivL rax div)); | |
| 7587 effect(KILL rdx, KILL cr); | |
| 7588 | |
| 7589 ins_cost(30*100+10*100); // XXX | |
| 7590 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t" | |
| 7591 "cmpq rax, rdx\n\t" | |
| 7592 "jne,s normal\n\t" | |
| 7593 "xorl rdx, rdx\n\t" | |
| 7594 "cmpq $div, -1\n\t" | |
| 7595 "je,s done\n" | |
| 7596 "normal: cdqq\n\t" | |
| 7597 "idivq $div\n" | |
| 7598 "done:" %} | |
| 7599 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 7600 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div)); | |
| 7601 ins_pipe(ialu_reg_reg_alu0); | |
| 7602 %} | |
| 7603 | |
| 7604 // Integer DIVMOD with Register, both quotient and mod results | |
| 7605 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div, | |
| 7606 rFlagsReg cr) | |
| 7607 %{ | |
| 7608 match(DivModI rax div); | |
| 7609 effect(KILL cr); | |
| 7610 | |
| 7611 ins_cost(30*100+10*100); // XXX | |
| 7612 format %{ "cmpl rax, 0x80000000\t# idiv\n\t" | |
| 7613 "jne,s normal\n\t" | |
| 7614 "xorl rdx, rdx\n\t" | |
| 7615 "cmpl $div, -1\n\t" | |
| 7616 "je,s done\n" | |
| 7617 "normal: cdql\n\t" | |
| 7618 "idivl $div\n" | |
| 7619 "done:" %} | |
| 7620 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 7621 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div)); | |
| 7622 ins_pipe(pipe_slow); | |
| 7623 %} | |
| 7624 | |
| 7625 // Long DIVMOD with Register, both quotient and mod results | |
| 7626 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div, | |
| 7627 rFlagsReg cr) | |
| 7628 %{ | |
| 7629 match(DivModL rax div); | |
| 7630 effect(KILL cr); | |
| 7631 | |
| 7632 ins_cost(30*100+10*100); // XXX | |
| 7633 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t" | |
| 7634 "cmpq rax, rdx\n\t" | |
| 7635 "jne,s normal\n\t" | |
| 7636 "xorl rdx, rdx\n\t" | |
| 7637 "cmpq $div, -1\n\t" | |
| 7638 "je,s done\n" | |
| 7639 "normal: cdqq\n\t" | |
| 7640 "idivq $div\n" | |
| 7641 "done:" %} | |
| 7642 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 7643 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div)); | |
| 7644 ins_pipe(pipe_slow); | |
| 7645 %} | |
| 7646 | |
| 7647 //----------- DivL-By-Constant-Expansions-------------------------------------- | |
| 7648 // DivI cases are handled by the compiler | |
| 7649 | |
| 605 | 7650 // Magic constant, reciprocal of 10 |
| 0 | 7651 instruct loadConL_0x6666666666666667(rRegL dst) |
| 7652 %{ | |
| 7653 effect(DEF dst); | |
| 7654 | |
| 7655 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %} | |
| 7656 ins_encode(load_immL(dst, 0x6666666666666667)); | |
| 7657 ins_pipe(ialu_reg); | |
| 7658 %} | |
| 7659 | |
| 7660 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr) | |
| 7661 %{ | |
| 7662 effect(DEF dst, USE src, USE_KILL rax, KILL cr); | |
| 7663 | |
| 7664 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %} | |
| 7665 opcode(0xF7, 0x5); /* Opcode F7 /5 */ | |
| 7666 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src)); | |
| 7667 ins_pipe(ialu_reg_reg_alu0); | |
| 7668 %} | |
| 7669 | |
| 7670 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr) | |
| 7671 %{ | |
| 7672 effect(USE_DEF dst, KILL cr); | |
| 7673 | |
| 7674 format %{ "sarq $dst, #63\t# Used in div-by-10" %} | |
| 7675 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 7676 ins_encode(reg_opc_imm_wide(dst, 0x3F)); | |
| 7677 ins_pipe(ialu_reg); | |
| 7678 %} | |
| 7679 | |
| 7680 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr) | |
| 7681 %{ | |
| 7682 effect(USE_DEF dst, KILL cr); | |
| 7683 | |
| 7684 format %{ "sarq $dst, #2\t# Used in div-by-10" %} | |
| 7685 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 7686 ins_encode(reg_opc_imm_wide(dst, 0x2)); | |
| 7687 ins_pipe(ialu_reg); | |
| 7688 %} | |
| 7689 | |
| 7690 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div) | |
| 7691 %{ | |
| 7692 match(Set dst (DivL src div)); | |
| 7693 | |
| 7694 ins_cost((5+8)*100); | |
| 7695 expand %{ | |
| 7696 rax_RegL rax; // Killed temp | |
| 7697 rFlagsReg cr; // Killed | |
| 7698 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667 | |
| 7699 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src | |
| 7700 sarL_rReg_63(src, cr); // sarq src, 63 | |
| 7701 sarL_rReg_2(dst, cr); // sarq rdx, 2 | |
| 7702 subL_rReg(dst, src, cr); // subl rdx, src | |
| 7703 %} | |
| 7704 %} | |
| 7705 | |
| 7706 //----------------------------------------------------------------------------- | |
| 7707 | |
| 7708 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div, | |
| 7709 rFlagsReg cr) | |
| 7710 %{ | |
| 7711 match(Set rdx (ModI rax div)); | |
| 7712 effect(KILL rax, KILL cr); | |
| 7713 | |
| 7714 ins_cost(300); // XXX | |
| 7715 format %{ "cmpl rax, 0x80000000\t# irem\n\t" | |
| 7716 "jne,s normal\n\t" | |
| 7717 "xorl rdx, rdx\n\t" | |
| 7718 "cmpl $div, -1\n\t" | |
| 7719 "je,s done\n" | |
| 7720 "normal: cdql\n\t" | |
| 7721 "idivl $div\n" | |
| 7722 "done:" %} | |
| 7723 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 7724 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div)); | |
| 7725 ins_pipe(ialu_reg_reg_alu0); | |
| 7726 %} | |
| 7727 | |
| 7728 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div, | |
| 7729 rFlagsReg cr) | |
| 7730 %{ | |
| 7731 match(Set rdx (ModL rax div)); | |
| 7732 effect(KILL rax, KILL cr); | |
| 7733 | |
| 7734 ins_cost(300); // XXX | |
| 7735 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t" | |
| 7736 "cmpq rax, rdx\n\t" | |
| 7737 "jne,s normal\n\t" | |
| 7738 "xorl rdx, rdx\n\t" | |
| 7739 "cmpq $div, -1\n\t" | |
| 7740 "je,s done\n" | |
| 7741 "normal: cdqq\n\t" | |
| 7742 "idivq $div\n" | |
| 7743 "done:" %} | |
| 7744 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 7745 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div)); | |
| 7746 ins_pipe(ialu_reg_reg_alu0); | |
| 7747 %} | |
| 7748 | |
| 7749 // Integer Shift Instructions | |
| 7750 // Shift Left by one | |
| 7751 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr) | |
| 7752 %{ | |
| 7753 match(Set dst (LShiftI dst shift)); | |
| 7754 effect(KILL cr); | |
| 7755 | |
| 7756 format %{ "sall $dst, $shift" %} | |
| 7757 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 7758 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 7759 ins_pipe(ialu_reg); | |
| 7760 %} | |
| 7761 | |
| 7762 // Shift Left by one | |
| 7763 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 7764 %{ | |
| 7765 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift))); | |
| 7766 effect(KILL cr); | |
| 7767 | |
| 7768 format %{ "sall $dst, $shift\t" %} | |
| 7769 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 7770 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 7771 ins_pipe(ialu_mem_imm); | |
| 7772 %} | |
| 7773 | |
| 7774 // Shift Left by 8-bit immediate | |
| 7775 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) | |
| 7776 %{ | |
| 7777 match(Set dst (LShiftI dst shift)); | |
| 7778 effect(KILL cr); | |
| 7779 | |
| 7780 format %{ "sall $dst, $shift" %} | |
| 7781 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 7782 ins_encode(reg_opc_imm(dst, shift)); | |
| 7783 ins_pipe(ialu_reg); | |
| 7784 %} | |
| 7785 | |
| 7786 // Shift Left by 8-bit immediate | |
| 7787 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 7788 %{ | |
| 7789 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift))); | |
| 7790 effect(KILL cr); | |
| 7791 | |
| 7792 format %{ "sall $dst, $shift" %} | |
| 7793 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 7794 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 7795 ins_pipe(ialu_mem_imm); | |
| 7796 %} | |
| 7797 | |
| 7798 // Shift Left by variable | |
| 7799 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 7800 %{ | |
| 7801 match(Set dst (LShiftI dst shift)); | |
| 7802 effect(KILL cr); | |
| 7803 | |
| 7804 format %{ "sall $dst, $shift" %} | |
| 7805 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 7806 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 7807 ins_pipe(ialu_reg_reg); | |
| 7808 %} | |
| 7809 | |
| 7810 // Shift Left by variable | |
| 7811 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 7812 %{ | |
| 7813 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift))); | |
| 7814 effect(KILL cr); | |
| 7815 | |
| 7816 format %{ "sall $dst, $shift" %} | |
| 7817 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 7818 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 7819 ins_pipe(ialu_mem_reg); | |
| 7820 %} | |
| 7821 | |
| 7822 // Arithmetic shift right by one | |
| 7823 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr) | |
| 7824 %{ | |
| 7825 match(Set dst (RShiftI dst shift)); | |
| 7826 effect(KILL cr); | |
| 7827 | |
| 7828 format %{ "sarl $dst, $shift" %} | |
| 7829 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 7830 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 7831 ins_pipe(ialu_reg); | |
| 7832 %} | |
| 7833 | |
| 7834 // Arithmetic shift right by one | |
| 7835 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 7836 %{ | |
| 7837 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 7838 effect(KILL cr); | |
| 7839 | |
| 7840 format %{ "sarl $dst, $shift" %} | |
| 7841 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 7842 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 7843 ins_pipe(ialu_mem_imm); | |
| 7844 %} | |
| 7845 | |
| 7846 // Arithmetic Shift Right by 8-bit immediate | |
| 7847 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) | |
| 7848 %{ | |
| 7849 match(Set dst (RShiftI dst shift)); | |
| 7850 effect(KILL cr); | |
| 7851 | |
| 7852 format %{ "sarl $dst, $shift" %} | |
| 7853 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 7854 ins_encode(reg_opc_imm(dst, shift)); | |
| 7855 ins_pipe(ialu_mem_imm); | |
| 7856 %} | |
| 7857 | |
| 7858 // Arithmetic Shift Right by 8-bit immediate | |
| 7859 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 7860 %{ | |
| 7861 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 7862 effect(KILL cr); | |
| 7863 | |
| 7864 format %{ "sarl $dst, $shift" %} | |
| 7865 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 7866 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 7867 ins_pipe(ialu_mem_imm); | |
| 7868 %} | |
| 7869 | |
| 7870 // Arithmetic Shift Right by variable | |
| 7871 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 7872 %{ | |
| 7873 match(Set dst (RShiftI dst shift)); | |
| 7874 effect(KILL cr); | |
| 7875 | |
| 7876 format %{ "sarl $dst, $shift" %} | |
| 7877 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 7878 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 7879 ins_pipe(ialu_reg_reg); | |
| 7880 %} | |
| 7881 | |
| 7882 // Arithmetic Shift Right by variable | |
| 7883 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 7884 %{ | |
| 7885 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 7886 effect(KILL cr); | |
| 7887 | |
| 7888 format %{ "sarl $dst, $shift" %} | |
| 7889 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 7890 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 7891 ins_pipe(ialu_mem_reg); | |
| 7892 %} | |
| 7893 | |
| 7894 // Logical shift right by one | |
| 7895 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr) | |
| 7896 %{ | |
| 7897 match(Set dst (URShiftI dst shift)); | |
| 7898 effect(KILL cr); | |
| 7899 | |
| 7900 format %{ "shrl $dst, $shift" %} | |
| 7901 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 7902 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 7903 ins_pipe(ialu_reg); | |
| 7904 %} | |
| 7905 | |
| 7906 // Logical shift right by one | |
| 7907 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 7908 %{ | |
| 7909 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift))); | |
| 7910 effect(KILL cr); | |
| 7911 | |
| 7912 format %{ "shrl $dst, $shift" %} | |
| 7913 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 7914 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 7915 ins_pipe(ialu_mem_imm); | |
| 7916 %} | |
| 7917 | |
| 7918 // Logical Shift Right by 8-bit immediate | |
| 7919 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) | |
| 7920 %{ | |
| 7921 match(Set dst (URShiftI dst shift)); | |
| 7922 effect(KILL cr); | |
| 7923 | |
| 7924 format %{ "shrl $dst, $shift" %} | |
| 7925 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 7926 ins_encode(reg_opc_imm(dst, shift)); | |
| 7927 ins_pipe(ialu_reg); | |
| 7928 %} | |
| 7929 | |
| 7930 // Logical Shift Right by 8-bit immediate | |
| 7931 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 7932 %{ | |
| 7933 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift))); | |
| 7934 effect(KILL cr); | |
| 7935 | |
| 7936 format %{ "shrl $dst, $shift" %} | |
| 7937 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 7938 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 7939 ins_pipe(ialu_mem_imm); | |
| 7940 %} | |
| 7941 | |
| 7942 // Logical Shift Right by variable | |
| 7943 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 7944 %{ | |
| 7945 match(Set dst (URShiftI dst shift)); | |
| 7946 effect(KILL cr); | |
| 7947 | |
| 7948 format %{ "shrl $dst, $shift" %} | |
| 7949 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 7950 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 7951 ins_pipe(ialu_reg_reg); | |
| 7952 %} | |
| 7953 | |
| 7954 // Logical Shift Right by variable | |
| 7955 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 7956 %{ | |
| 7957 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift))); | |
| 7958 effect(KILL cr); | |
| 7959 | |
| 7960 format %{ "shrl $dst, $shift" %} | |
| 7961 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 7962 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 7963 ins_pipe(ialu_mem_reg); | |
| 7964 %} | |
| 7965 | |
| 7966 // Long Shift Instructions | |
| 7967 // Shift Left by one | |
| 7968 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr) | |
| 7969 %{ | |
| 7970 match(Set dst (LShiftL dst shift)); | |
| 7971 effect(KILL cr); | |
| 7972 | |
| 7973 format %{ "salq $dst, $shift" %} | |
| 7974 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 7975 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 7976 ins_pipe(ialu_reg); | |
| 7977 %} | |
| 7978 | |
| 7979 // Shift Left by one | |
| 7980 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 7981 %{ | |
| 7982 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift))); | |
| 7983 effect(KILL cr); | |
| 7984 | |
| 7985 format %{ "salq $dst, $shift" %} | |
| 7986 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 7987 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 7988 ins_pipe(ialu_mem_imm); | |
| 7989 %} | |
| 7990 | |
| 7991 // Shift Left by 8-bit immediate | |
| 7992 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr) | |
| 7993 %{ | |
| 7994 match(Set dst (LShiftL dst shift)); | |
| 7995 effect(KILL cr); | |
| 7996 | |
| 7997 format %{ "salq $dst, $shift" %} | |
| 7998 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 7999 ins_encode(reg_opc_imm_wide(dst, shift)); | |
| 8000 ins_pipe(ialu_reg); | |
| 8001 %} | |
| 8002 | |
| 8003 // Shift Left by 8-bit immediate | |
| 8004 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 8005 %{ | |
| 8006 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift))); | |
| 8007 effect(KILL cr); | |
| 8008 | |
| 8009 format %{ "salq $dst, $shift" %} | |
| 8010 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 8011 ins_encode(REX_mem_wide(dst), OpcP, | |
| 8012 RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 8013 ins_pipe(ialu_mem_imm); | |
| 8014 %} | |
| 8015 | |
| 8016 // Shift Left by variable | |
| 8017 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 8018 %{ | |
| 8019 match(Set dst (LShiftL dst shift)); | |
| 8020 effect(KILL cr); | |
| 8021 | |
| 8022 format %{ "salq $dst, $shift" %} | |
| 8023 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 8024 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8025 ins_pipe(ialu_reg_reg); | |
| 8026 %} | |
| 8027 | |
| 8028 // Shift Left by variable | |
| 8029 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 8030 %{ | |
| 8031 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift))); | |
| 8032 effect(KILL cr); | |
| 8033 | |
| 8034 format %{ "salq $dst, $shift" %} | |
| 8035 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 8036 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8037 ins_pipe(ialu_mem_reg); | |
| 8038 %} | |
| 8039 | |
| 8040 // Arithmetic shift right by one | |
| 8041 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr) | |
| 8042 %{ | |
| 8043 match(Set dst (RShiftL dst shift)); | |
| 8044 effect(KILL cr); | |
| 8045 | |
| 8046 format %{ "sarq $dst, $shift" %} | |
| 8047 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 8048 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8049 ins_pipe(ialu_reg); | |
| 8050 %} | |
| 8051 | |
| 8052 // Arithmetic shift right by one | |
| 8053 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 8054 %{ | |
| 8055 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift))); | |
| 8056 effect(KILL cr); | |
| 8057 | |
| 8058 format %{ "sarq $dst, $shift" %} | |
| 8059 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 8060 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8061 ins_pipe(ialu_mem_imm); | |
| 8062 %} | |
| 8063 | |
| 8064 // Arithmetic Shift Right by 8-bit immediate | |
| 8065 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr) | |
| 8066 %{ | |
| 8067 match(Set dst (RShiftL dst shift)); | |
| 8068 effect(KILL cr); | |
| 8069 | |
| 8070 format %{ "sarq $dst, $shift" %} | |
| 8071 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8072 ins_encode(reg_opc_imm_wide(dst, shift)); | |
| 8073 ins_pipe(ialu_mem_imm); | |
| 8074 %} | |
| 8075 | |
| 8076 // Arithmetic Shift Right by 8-bit immediate | |
| 8077 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 8078 %{ | |
| 8079 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift))); | |
| 8080 effect(KILL cr); | |
| 8081 | |
| 8082 format %{ "sarq $dst, $shift" %} | |
| 8083 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8084 ins_encode(REX_mem_wide(dst), OpcP, | |
| 8085 RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 8086 ins_pipe(ialu_mem_imm); | |
| 8087 %} | |
| 8088 | |
| 8089 // Arithmetic Shift Right by variable | |
| 8090 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 8091 %{ | |
| 8092 match(Set dst (RShiftL dst shift)); | |
| 8093 effect(KILL cr); | |
| 8094 | |
| 8095 format %{ "sarq $dst, $shift" %} | |
| 8096 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 8097 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8098 ins_pipe(ialu_reg_reg); | |
| 8099 %} | |
| 8100 | |
| 8101 // Arithmetic Shift Right by variable | |
| 8102 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 8103 %{ | |
| 8104 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift))); | |
| 8105 effect(KILL cr); | |
| 8106 | |
| 8107 format %{ "sarq $dst, $shift" %} | |
| 8108 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 8109 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8110 ins_pipe(ialu_mem_reg); | |
| 8111 %} | |
| 8112 | |
| 8113 // Logical shift right by one | |
| 8114 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr) | |
| 8115 %{ | |
| 8116 match(Set dst (URShiftL dst shift)); | |
| 8117 effect(KILL cr); | |
| 8118 | |
| 8119 format %{ "shrq $dst, $shift" %} | |
| 8120 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 8121 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst )); | |
| 8122 ins_pipe(ialu_reg); | |
| 8123 %} | |
| 8124 | |
| 8125 // Logical shift right by one | |
| 8126 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 8127 %{ | |
| 8128 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift))); | |
| 8129 effect(KILL cr); | |
| 8130 | |
| 8131 format %{ "shrq $dst, $shift" %} | |
| 8132 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 8133 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8134 ins_pipe(ialu_mem_imm); | |
| 8135 %} | |
| 8136 | |
| 8137 // Logical Shift Right by 8-bit immediate | |
| 8138 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr) | |
| 8139 %{ | |
| 8140 match(Set dst (URShiftL dst shift)); | |
| 8141 effect(KILL cr); | |
| 8142 | |
| 8143 format %{ "shrq $dst, $shift" %} | |
| 8144 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 8145 ins_encode(reg_opc_imm_wide(dst, shift)); | |
| 8146 ins_pipe(ialu_reg); | |
| 8147 %} | |
| 8148 | |
|
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|
8149 |
| 0 | 8150 // Logical Shift Right by 8-bit immediate |
| 8151 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 8152 %{ | |
| 8153 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift))); | |
| 8154 effect(KILL cr); | |
| 8155 | |
| 8156 format %{ "shrq $dst, $shift" %} | |
| 8157 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 8158 ins_encode(REX_mem_wide(dst), OpcP, | |
| 8159 RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 8160 ins_pipe(ialu_mem_imm); | |
| 8161 %} | |
| 8162 | |
| 8163 // Logical Shift Right by variable | |
| 8164 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 8165 %{ | |
| 8166 match(Set dst (URShiftL dst shift)); | |
| 8167 effect(KILL cr); | |
| 8168 | |
| 8169 format %{ "shrq $dst, $shift" %} | |
| 8170 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 8171 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8172 ins_pipe(ialu_reg_reg); | |
| 8173 %} | |
| 8174 | |
| 8175 // Logical Shift Right by variable | |
| 8176 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 8177 %{ | |
| 8178 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift))); | |
| 8179 effect(KILL cr); | |
| 8180 | |
| 8181 format %{ "shrq $dst, $shift" %} | |
| 8182 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 8183 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8184 ins_pipe(ialu_mem_reg); | |
| 8185 %} | |
| 8186 | |
| 8187 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24. | |
| 8188 // This idiom is used by the compiler for the i2b bytecode. | |
| 8189 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour) | |
| 8190 %{ | |
| 8191 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour)); | |
| 8192 | |
| 8193 format %{ "movsbl $dst, $src\t# i2b" %} | |
| 8194 opcode(0x0F, 0xBE); | |
| 8195 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 8196 ins_pipe(ialu_reg_reg); | |
| 8197 %} | |
| 8198 | |
| 8199 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16. | |
| 8200 // This idiom is used by the compiler the i2s bytecode. | |
| 8201 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen) | |
| 8202 %{ | |
| 8203 match(Set dst (RShiftI (LShiftI src sixteen) sixteen)); | |
| 8204 | |
| 8205 format %{ "movswl $dst, $src\t# i2s" %} | |
| 8206 opcode(0x0F, 0xBF); | |
| 8207 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 8208 ins_pipe(ialu_reg_reg); | |
| 8209 %} | |
| 8210 | |
| 8211 // ROL/ROR instructions | |
| 8212 | |
| 8213 // ROL expand | |
| 8214 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{ | |
| 8215 effect(KILL cr, USE_DEF dst); | |
| 8216 | |
| 8217 format %{ "roll $dst" %} | |
| 8218 opcode(0xD1, 0x0); /* Opcode D1 /0 */ | |
| 8219 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8220 ins_pipe(ialu_reg); | |
| 8221 %} | |
| 8222 | |
| 8223 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{ | |
| 8224 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8225 | |
| 8226 format %{ "roll $dst, $shift" %} | |
| 8227 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */ | |
| 8228 ins_encode( reg_opc_imm(dst, shift) ); | |
| 8229 ins_pipe(ialu_reg); | |
| 8230 %} | |
| 8231 | |
| 8232 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 8233 %{ | |
| 8234 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8235 | |
| 8236 format %{ "roll $dst, $shift" %} | |
| 8237 opcode(0xD3, 0x0); /* Opcode D3 /0 */ | |
| 8238 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8239 ins_pipe(ialu_reg_reg); | |
| 8240 %} | |
| 8241 // end of ROL expand | |
| 8242 | |
| 8243 // Rotate Left by one | |
| 8244 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr) | |
| 8245 %{ | |
| 8246 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift))); | |
| 8247 | |
| 8248 expand %{ | |
| 8249 rolI_rReg_imm1(dst, cr); | |
| 8250 %} | |
| 8251 %} | |
| 8252 | |
| 8253 // Rotate Left by 8-bit immediate | |
| 8254 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr) | |
| 8255 %{ | |
| 8256 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); | |
| 8257 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift))); | |
| 8258 | |
| 8259 expand %{ | |
| 8260 rolI_rReg_imm8(dst, lshift, cr); | |
| 8261 %} | |
| 8262 %} | |
| 8263 | |
| 8264 // Rotate Left by variable | |
| 8265 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
| 8266 %{ | |
| 8267 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift)))); | |
| 8268 | |
| 8269 expand %{ | |
| 8270 rolI_rReg_CL(dst, shift, cr); | |
| 8271 %} | |
| 8272 %} | |
| 8273 | |
| 8274 // Rotate Left by variable | |
| 8275 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr) | |
| 8276 %{ | |
| 8277 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift)))); | |
| 8278 | |
| 8279 expand %{ | |
| 8280 rolI_rReg_CL(dst, shift, cr); | |
| 8281 %} | |
| 8282 %} | |
| 8283 | |
| 8284 // ROR expand | |
| 8285 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr) | |
| 8286 %{ | |
| 8287 effect(USE_DEF dst, KILL cr); | |
| 8288 | |
| 8289 format %{ "rorl $dst" %} | |
| 8290 opcode(0xD1, 0x1); /* D1 /1 */ | |
| 8291 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8292 ins_pipe(ialu_reg); | |
| 8293 %} | |
| 8294 | |
| 8295 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) | |
| 8296 %{ | |
| 8297 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8298 | |
| 8299 format %{ "rorl $dst, $shift" %} | |
| 8300 opcode(0xC1, 0x1); /* C1 /1 ib */ | |
| 8301 ins_encode(reg_opc_imm(dst, shift)); | |
| 8302 ins_pipe(ialu_reg); | |
| 8303 %} | |
| 8304 | |
| 8305 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 8306 %{ | |
| 8307 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8308 | |
| 8309 format %{ "rorl $dst, $shift" %} | |
| 8310 opcode(0xD3, 0x1); /* D3 /1 */ | |
| 8311 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8312 ins_pipe(ialu_reg_reg); | |
| 8313 %} | |
| 8314 // end of ROR expand | |
| 8315 | |
| 8316 // Rotate Right by one | |
| 8317 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr) | |
| 8318 %{ | |
| 8319 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift))); | |
| 8320 | |
| 8321 expand %{ | |
| 8322 rorI_rReg_imm1(dst, cr); | |
| 8323 %} | |
| 8324 %} | |
| 8325 | |
| 8326 // Rotate Right by 8-bit immediate | |
| 8327 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr) | |
| 8328 %{ | |
| 8329 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); | |
| 8330 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift))); | |
| 8331 | |
| 8332 expand %{ | |
| 8333 rorI_rReg_imm8(dst, rshift, cr); | |
| 8334 %} | |
| 8335 %} | |
| 8336 | |
| 8337 // Rotate Right by variable | |
| 8338 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
| 8339 %{ | |
| 8340 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift)))); | |
| 8341 | |
| 8342 expand %{ | |
| 8343 rorI_rReg_CL(dst, shift, cr); | |
| 8344 %} | |
| 8345 %} | |
| 8346 | |
| 8347 // Rotate Right by variable | |
| 8348 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr) | |
| 8349 %{ | |
| 8350 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift)))); | |
| 8351 | |
| 8352 expand %{ | |
| 8353 rorI_rReg_CL(dst, shift, cr); | |
| 8354 %} | |
| 8355 %} | |
| 8356 | |
| 8357 // for long rotate | |
| 8358 // ROL expand | |
| 8359 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{ | |
| 8360 effect(USE_DEF dst, KILL cr); | |
| 8361 | |
| 8362 format %{ "rolq $dst" %} | |
| 8363 opcode(0xD1, 0x0); /* Opcode D1 /0 */ | |
| 8364 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8365 ins_pipe(ialu_reg); | |
| 8366 %} | |
| 8367 | |
| 8368 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{ | |
| 8369 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8370 | |
| 8371 format %{ "rolq $dst, $shift" %} | |
| 8372 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */ | |
| 8373 ins_encode( reg_opc_imm_wide(dst, shift) ); | |
| 8374 ins_pipe(ialu_reg); | |
| 8375 %} | |
| 8376 | |
| 8377 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 8378 %{ | |
| 8379 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8380 | |
| 8381 format %{ "rolq $dst, $shift" %} | |
| 8382 opcode(0xD3, 0x0); /* Opcode D3 /0 */ | |
| 8383 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8384 ins_pipe(ialu_reg_reg); | |
| 8385 %} | |
| 8386 // end of ROL expand | |
| 8387 | |
| 8388 // Rotate Left by one | |
| 8389 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr) | |
| 8390 %{ | |
| 8391 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift))); | |
| 8392 | |
| 8393 expand %{ | |
| 8394 rolL_rReg_imm1(dst, cr); | |
| 8395 %} | |
| 8396 %} | |
| 8397 | |
| 8398 // Rotate Left by 8-bit immediate | |
| 8399 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr) | |
| 8400 %{ | |
| 8401 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f)); | |
| 8402 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift))); | |
| 8403 | |
| 8404 expand %{ | |
| 8405 rolL_rReg_imm8(dst, lshift, cr); | |
| 8406 %} | |
| 8407 %} | |
| 8408 | |
| 8409 // Rotate Left by variable | |
| 8410 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
| 8411 %{ | |
| 8412 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift)))); | |
| 8413 | |
| 8414 expand %{ | |
| 8415 rolL_rReg_CL(dst, shift, cr); | |
| 8416 %} | |
| 8417 %} | |
| 8418 | |
| 8419 // Rotate Left by variable | |
| 8420 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr) | |
| 8421 %{ | |
| 8422 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift)))); | |
| 8423 | |
| 8424 expand %{ | |
| 8425 rolL_rReg_CL(dst, shift, cr); | |
| 8426 %} | |
| 8427 %} | |
| 8428 | |
| 8429 // ROR expand | |
| 8430 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr) | |
| 8431 %{ | |
| 8432 effect(USE_DEF dst, KILL cr); | |
| 8433 | |
| 8434 format %{ "rorq $dst" %} | |
| 8435 opcode(0xD1, 0x1); /* D1 /1 */ | |
| 8436 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8437 ins_pipe(ialu_reg); | |
| 8438 %} | |
| 8439 | |
| 8440 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) | |
| 8441 %{ | |
| 8442 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8443 | |
| 8444 format %{ "rorq $dst, $shift" %} | |
| 8445 opcode(0xC1, 0x1); /* C1 /1 ib */ | |
| 8446 ins_encode(reg_opc_imm_wide(dst, shift)); | |
| 8447 ins_pipe(ialu_reg); | |
| 8448 %} | |
| 8449 | |
| 8450 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 8451 %{ | |
| 8452 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8453 | |
| 8454 format %{ "rorq $dst, $shift" %} | |
| 8455 opcode(0xD3, 0x1); /* D3 /1 */ | |
| 8456 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8457 ins_pipe(ialu_reg_reg); | |
| 8458 %} | |
| 8459 // end of ROR expand | |
| 8460 | |
| 8461 // Rotate Right by one | |
| 8462 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr) | |
| 8463 %{ | |
| 8464 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift))); | |
| 8465 | |
| 8466 expand %{ | |
| 8467 rorL_rReg_imm1(dst, cr); | |
| 8468 %} | |
| 8469 %} | |
| 8470 | |
| 8471 // Rotate Right by 8-bit immediate | |
| 8472 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr) | |
| 8473 %{ | |
| 8474 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f)); | |
| 8475 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift))); | |
| 8476 | |
| 8477 expand %{ | |
| 8478 rorL_rReg_imm8(dst, rshift, cr); | |
| 8479 %} | |
| 8480 %} | |
| 8481 | |
| 8482 // Rotate Right by variable | |
| 8483 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
| 8484 %{ | |
| 8485 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift)))); | |
| 8486 | |
| 8487 expand %{ | |
| 8488 rorL_rReg_CL(dst, shift, cr); | |
| 8489 %} | |
| 8490 %} | |
| 8491 | |
| 8492 // Rotate Right by variable | |
| 8493 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr) | |
| 8494 %{ | |
| 8495 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift)))); | |
| 8496 | |
| 8497 expand %{ | |
| 8498 rorL_rReg_CL(dst, shift, cr); | |
| 8499 %} | |
| 8500 %} | |
| 8501 | |
| 8502 // Logical Instructions | |
| 8503 | |
| 8504 // Integer Logical Instructions | |
| 8505 | |
| 8506 // And Instructions | |
| 8507 // And Register with Register | |
| 8508 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 8509 %{ | |
| 8510 match(Set dst (AndI dst src)); | |
| 8511 effect(KILL cr); | |
| 8512 | |
| 8513 format %{ "andl $dst, $src\t# int" %} | |
| 8514 opcode(0x23); | |
| 8515 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 8516 ins_pipe(ialu_reg_reg); | |
| 8517 %} | |
| 8518 | |
| 8519 // And Register with Immediate 255 | |
| 8520 instruct andI_rReg_imm255(rRegI dst, immI_255 src) | |
| 8521 %{ | |
| 8522 match(Set dst (AndI dst src)); | |
| 8523 | |
| 8524 format %{ "movzbl $dst, $dst\t# int & 0xFF" %} | |
| 8525 opcode(0x0F, 0xB6); | |
| 8526 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 8527 ins_pipe(ialu_reg); | |
| 8528 %} | |
| 8529 | |
| 8530 // And Register with Immediate 255 and promote to long | |
| 8531 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask) | |
| 8532 %{ | |
| 8533 match(Set dst (ConvI2L (AndI src mask))); | |
| 8534 | |
| 8535 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %} | |
| 8536 opcode(0x0F, 0xB6); | |
| 8537 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 8538 ins_pipe(ialu_reg); | |
| 8539 %} | |
| 8540 | |
| 8541 // And Register with Immediate 65535 | |
| 8542 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src) | |
| 8543 %{ | |
| 8544 match(Set dst (AndI dst src)); | |
| 8545 | |
| 8546 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %} | |
| 8547 opcode(0x0F, 0xB7); | |
| 8548 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 8549 ins_pipe(ialu_reg); | |
| 8550 %} | |
| 8551 | |
| 8552 // And Register with Immediate 65535 and promote to long | |
| 8553 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask) | |
| 8554 %{ | |
| 8555 match(Set dst (ConvI2L (AndI src mask))); | |
| 8556 | |
| 8557 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %} | |
| 8558 opcode(0x0F, 0xB7); | |
| 8559 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 8560 ins_pipe(ialu_reg); | |
| 8561 %} | |
| 8562 | |
| 8563 // And Register with Immediate | |
| 8564 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 8565 %{ | |
| 8566 match(Set dst (AndI dst src)); | |
| 8567 effect(KILL cr); | |
| 8568 | |
| 8569 format %{ "andl $dst, $src\t# int" %} | |
| 8570 opcode(0x81, 0x04); /* Opcode 81 /4 */ | |
| 8571 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 8572 ins_pipe(ialu_reg); | |
| 8573 %} | |
| 8574 | |
| 8575 // And Register with Memory | |
| 8576 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 8577 %{ | |
| 8578 match(Set dst (AndI dst (LoadI src))); | |
| 8579 effect(KILL cr); | |
| 8580 | |
| 8581 ins_cost(125); | |
| 8582 format %{ "andl $dst, $src\t# int" %} | |
| 8583 opcode(0x23); | |
| 8584 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 8585 ins_pipe(ialu_reg_mem); | |
| 8586 %} | |
| 8587 | |
| 8588 // And Memory with Register | |
| 8589 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 8590 %{ | |
| 8591 match(Set dst (StoreI dst (AndI (LoadI dst) src))); | |
| 8592 effect(KILL cr); | |
| 8593 | |
| 8594 ins_cost(150); | |
| 8595 format %{ "andl $dst, $src\t# int" %} | |
| 8596 opcode(0x21); /* Opcode 21 /r */ | |
| 8597 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 8598 ins_pipe(ialu_mem_reg); | |
| 8599 %} | |
| 8600 | |
| 8601 // And Memory with Immediate | |
| 8602 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 8603 %{ | |
| 8604 match(Set dst (StoreI dst (AndI (LoadI dst) src))); | |
| 8605 effect(KILL cr); | |
| 8606 | |
| 8607 ins_cost(125); | |
| 8608 format %{ "andl $dst, $src\t# int" %} | |
| 8609 opcode(0x81, 0x4); /* Opcode 81 /4 id */ | |
| 8610 ins_encode(REX_mem(dst), OpcSE(src), | |
| 8611 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 8612 ins_pipe(ialu_mem_imm); | |
| 8613 %} | |
| 8614 | |
| 8615 // Or Instructions | |
| 8616 // Or Register with Register | |
| 8617 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 8618 %{ | |
| 8619 match(Set dst (OrI dst src)); | |
| 8620 effect(KILL cr); | |
| 8621 | |
| 8622 format %{ "orl $dst, $src\t# int" %} | |
| 8623 opcode(0x0B); | |
| 8624 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 8625 ins_pipe(ialu_reg_reg); | |
| 8626 %} | |
| 8627 | |
| 8628 // Or Register with Immediate | |
| 8629 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 8630 %{ | |
| 8631 match(Set dst (OrI dst src)); | |
| 8632 effect(KILL cr); | |
| 8633 | |
| 8634 format %{ "orl $dst, $src\t# int" %} | |
| 8635 opcode(0x81, 0x01); /* Opcode 81 /1 id */ | |
| 8636 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 8637 ins_pipe(ialu_reg); | |
| 8638 %} | |
| 8639 | |
| 8640 // Or Register with Memory | |
| 8641 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 8642 %{ | |
| 8643 match(Set dst (OrI dst (LoadI src))); | |
| 8644 effect(KILL cr); | |
| 8645 | |
| 8646 ins_cost(125); | |
| 8647 format %{ "orl $dst, $src\t# int" %} | |
| 8648 opcode(0x0B); | |
| 8649 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 8650 ins_pipe(ialu_reg_mem); | |
| 8651 %} | |
| 8652 | |
| 8653 // Or Memory with Register | |
| 8654 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 8655 %{ | |
| 8656 match(Set dst (StoreI dst (OrI (LoadI dst) src))); | |
| 8657 effect(KILL cr); | |
| 8658 | |
| 8659 ins_cost(150); | |
| 8660 format %{ "orl $dst, $src\t# int" %} | |
| 8661 opcode(0x09); /* Opcode 09 /r */ | |
| 8662 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 8663 ins_pipe(ialu_mem_reg); | |
| 8664 %} | |
| 8665 | |
| 8666 // Or Memory with Immediate | |
| 8667 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 8668 %{ | |
| 8669 match(Set dst (StoreI dst (OrI (LoadI dst) src))); | |
| 8670 effect(KILL cr); | |
| 8671 | |
| 8672 ins_cost(125); | |
| 8673 format %{ "orl $dst, $src\t# int" %} | |
| 8674 opcode(0x81, 0x1); /* Opcode 81 /1 id */ | |
| 8675 ins_encode(REX_mem(dst), OpcSE(src), | |
| 8676 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 8677 ins_pipe(ialu_mem_imm); | |
| 8678 %} | |
| 8679 | |
| 8680 // Xor Instructions | |
| 8681 // Xor Register with Register | |
| 8682 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 8683 %{ | |
| 8684 match(Set dst (XorI dst src)); | |
| 8685 effect(KILL cr); | |
| 8686 | |
| 8687 format %{ "xorl $dst, $src\t# int" %} | |
| 8688 opcode(0x33); | |
| 8689 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 8690 ins_pipe(ialu_reg_reg); | |
| 8691 %} | |
| 8692 | |
| 403 | 8693 // Xor Register with Immediate -1 |
| 8694 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{ | |
|
2404
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2401
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changeset
|
8695 match(Set dst (XorI dst imm)); |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
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changeset
|
8696 |
|
b40d4fa697bf
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iveresov
parents:
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changeset
|
8697 format %{ "not $dst" %} |
| 403 | 8698 ins_encode %{ |
| 8699 __ notl($dst$$Register); | |
| 8700 %} | |
| 8701 ins_pipe(ialu_reg); | |
| 8702 %} | |
| 8703 | |
| 0 | 8704 // Xor Register with Immediate |
| 8705 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 8706 %{ | |
| 8707 match(Set dst (XorI dst src)); | |
| 8708 effect(KILL cr); | |
| 8709 | |
| 8710 format %{ "xorl $dst, $src\t# int" %} | |
| 8711 opcode(0x81, 0x06); /* Opcode 81 /6 id */ | |
| 8712 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 8713 ins_pipe(ialu_reg); | |
| 8714 %} | |
| 8715 | |
| 8716 // Xor Register with Memory | |
| 8717 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 8718 %{ | |
| 8719 match(Set dst (XorI dst (LoadI src))); | |
| 8720 effect(KILL cr); | |
| 8721 | |
| 8722 ins_cost(125); | |
| 8723 format %{ "xorl $dst, $src\t# int" %} | |
| 8724 opcode(0x33); | |
| 8725 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 8726 ins_pipe(ialu_reg_mem); | |
| 8727 %} | |
| 8728 | |
| 8729 // Xor Memory with Register | |
| 8730 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 8731 %{ | |
| 8732 match(Set dst (StoreI dst (XorI (LoadI dst) src))); | |
| 8733 effect(KILL cr); | |
| 8734 | |
| 8735 ins_cost(150); | |
| 8736 format %{ "xorl $dst, $src\t# int" %} | |
| 8737 opcode(0x31); /* Opcode 31 /r */ | |
| 8738 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 8739 ins_pipe(ialu_mem_reg); | |
| 8740 %} | |
| 8741 | |
| 8742 // Xor Memory with Immediate | |
| 8743 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 8744 %{ | |
| 8745 match(Set dst (StoreI dst (XorI (LoadI dst) src))); | |
| 8746 effect(KILL cr); | |
| 8747 | |
| 8748 ins_cost(125); | |
| 8749 format %{ "xorl $dst, $src\t# int" %} | |
| 8750 opcode(0x81, 0x6); /* Opcode 81 /6 id */ | |
| 8751 ins_encode(REX_mem(dst), OpcSE(src), | |
| 8752 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 8753 ins_pipe(ialu_mem_imm); | |
| 8754 %} | |
| 8755 | |
| 8756 | |
| 8757 // Long Logical Instructions | |
| 8758 | |
| 8759 // And Instructions | |
| 8760 // And Register with Register | |
| 8761 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 8762 %{ | |
| 8763 match(Set dst (AndL dst src)); | |
| 8764 effect(KILL cr); | |
| 8765 | |
| 8766 format %{ "andq $dst, $src\t# long" %} | |
| 8767 opcode(0x23); | |
| 8768 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 8769 ins_pipe(ialu_reg_reg); | |
| 8770 %} | |
| 8771 | |
| 8772 // And Register with Immediate 255 | |
| 8773 instruct andL_rReg_imm255(rRegL dst, immL_255 src) | |
| 8774 %{ | |
| 8775 match(Set dst (AndL dst src)); | |
| 8776 | |
|
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8777 format %{ "movzbq $dst, $dst\t# long & 0xFF" %} |
| 0 | 8778 opcode(0x0F, 0xB6); |
| 8779 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 8780 ins_pipe(ialu_reg); | |
| 8781 %} | |
| 8782 | |
| 8783 // And Register with Immediate 65535 | |
|
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8784 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src) |
| 0 | 8785 %{ |
| 8786 match(Set dst (AndL dst src)); | |
| 8787 | |
| 8788 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %} | |
| 8789 opcode(0x0F, 0xB7); | |
| 8790 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 8791 ins_pipe(ialu_reg); | |
| 8792 %} | |
| 8793 | |
| 8794 // And Register with Immediate | |
| 8795 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
| 8796 %{ | |
| 8797 match(Set dst (AndL dst src)); | |
| 8798 effect(KILL cr); | |
| 8799 | |
| 8800 format %{ "andq $dst, $src\t# long" %} | |
| 8801 opcode(0x81, 0x04); /* Opcode 81 /4 */ | |
| 8802 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 8803 ins_pipe(ialu_reg); | |
| 8804 %} | |
| 8805 | |
| 8806 // And Register with Memory | |
| 8807 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 8808 %{ | |
| 8809 match(Set dst (AndL dst (LoadL src))); | |
| 8810 effect(KILL cr); | |
| 8811 | |
| 8812 ins_cost(125); | |
| 8813 format %{ "andq $dst, $src\t# long" %} | |
| 8814 opcode(0x23); | |
| 8815 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 8816 ins_pipe(ialu_reg_mem); | |
| 8817 %} | |
| 8818 | |
| 8819 // And Memory with Register | |
| 8820 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 8821 %{ | |
| 8822 match(Set dst (StoreL dst (AndL (LoadL dst) src))); | |
| 8823 effect(KILL cr); | |
| 8824 | |
| 8825 ins_cost(150); | |
| 8826 format %{ "andq $dst, $src\t# long" %} | |
| 8827 opcode(0x21); /* Opcode 21 /r */ | |
| 8828 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 8829 ins_pipe(ialu_mem_reg); | |
| 8830 %} | |
| 8831 | |
| 8832 // And Memory with Immediate | |
| 8833 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 8834 %{ | |
| 8835 match(Set dst (StoreL dst (AndL (LoadL dst) src))); | |
| 8836 effect(KILL cr); | |
| 8837 | |
| 8838 ins_cost(125); | |
| 8839 format %{ "andq $dst, $src\t# long" %} | |
| 8840 opcode(0x81, 0x4); /* Opcode 81 /4 id */ | |
| 8841 ins_encode(REX_mem_wide(dst), OpcSE(src), | |
| 8842 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 8843 ins_pipe(ialu_mem_imm); | |
| 8844 %} | |
| 8845 | |
| 8846 // Or Instructions | |
| 8847 // Or Register with Register | |
| 8848 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 8849 %{ | |
| 8850 match(Set dst (OrL dst src)); | |
| 8851 effect(KILL cr); | |
| 8852 | |
| 8853 format %{ "orq $dst, $src\t# long" %} | |
| 8854 opcode(0x0B); | |
| 8855 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 8856 ins_pipe(ialu_reg_reg); | |
| 8857 %} | |
| 8858 | |
|
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8859 // Use any_RegP to match R15 (TLS register) without spilling. |
|
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8860 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{ |
|
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8861 match(Set dst (OrL dst (CastP2X src))); |
|
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8862 effect(KILL cr); |
|
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8863 |
|
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|
8864 format %{ "orq $dst, $src\t# long" %} |
|
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|
8865 opcode(0x0B); |
|
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8866 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); |
|
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|
8867 ins_pipe(ialu_reg_reg); |
|
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|
8868 %} |
|
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|
8869 |
|
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|
8870 |
| 0 | 8871 // Or Register with Immediate |
| 8872 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
| 8873 %{ | |
| 8874 match(Set dst (OrL dst src)); | |
| 8875 effect(KILL cr); | |
| 8876 | |
| 8877 format %{ "orq $dst, $src\t# long" %} | |
| 8878 opcode(0x81, 0x01); /* Opcode 81 /1 id */ | |
| 8879 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 8880 ins_pipe(ialu_reg); | |
| 8881 %} | |
| 8882 | |
| 8883 // Or Register with Memory | |
| 8884 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 8885 %{ | |
| 8886 match(Set dst (OrL dst (LoadL src))); | |
| 8887 effect(KILL cr); | |
| 8888 | |
| 8889 ins_cost(125); | |
| 8890 format %{ "orq $dst, $src\t# long" %} | |
| 8891 opcode(0x0B); | |
| 8892 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 8893 ins_pipe(ialu_reg_mem); | |
| 8894 %} | |
| 8895 | |
| 8896 // Or Memory with Register | |
| 8897 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 8898 %{ | |
| 8899 match(Set dst (StoreL dst (OrL (LoadL dst) src))); | |
| 8900 effect(KILL cr); | |
| 8901 | |
| 8902 ins_cost(150); | |
| 8903 format %{ "orq $dst, $src\t# long" %} | |
| 8904 opcode(0x09); /* Opcode 09 /r */ | |
| 8905 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 8906 ins_pipe(ialu_mem_reg); | |
| 8907 %} | |
| 8908 | |
| 8909 // Or Memory with Immediate | |
| 8910 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 8911 %{ | |
| 8912 match(Set dst (StoreL dst (OrL (LoadL dst) src))); | |
| 8913 effect(KILL cr); | |
| 8914 | |
| 8915 ins_cost(125); | |
| 8916 format %{ "orq $dst, $src\t# long" %} | |
| 8917 opcode(0x81, 0x1); /* Opcode 81 /1 id */ | |
| 8918 ins_encode(REX_mem_wide(dst), OpcSE(src), | |
| 8919 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 8920 ins_pipe(ialu_mem_imm); | |
| 8921 %} | |
| 8922 | |
| 8923 // Xor Instructions | |
| 8924 // Xor Register with Register | |
| 8925 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 8926 %{ | |
| 8927 match(Set dst (XorL dst src)); | |
| 8928 effect(KILL cr); | |
| 8929 | |
| 8930 format %{ "xorq $dst, $src\t# long" %} | |
| 8931 opcode(0x33); | |
| 8932 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 8933 ins_pipe(ialu_reg_reg); | |
| 8934 %} | |
| 8935 | |
| 403 | 8936 // Xor Register with Immediate -1 |
| 8937 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{ | |
|
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8938 match(Set dst (XorL dst imm)); |
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8939 |
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8940 format %{ "notq $dst" %} |
| 403 | 8941 ins_encode %{ |
| 8942 __ notq($dst$$Register); | |
| 8943 %} | |
| 8944 ins_pipe(ialu_reg); | |
| 8945 %} | |
| 8946 | |
| 0 | 8947 // Xor Register with Immediate |
| 8948 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
| 8949 %{ | |
| 8950 match(Set dst (XorL dst src)); | |
| 8951 effect(KILL cr); | |
| 8952 | |
| 8953 format %{ "xorq $dst, $src\t# long" %} | |
| 8954 opcode(0x81, 0x06); /* Opcode 81 /6 id */ | |
| 8955 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 8956 ins_pipe(ialu_reg); | |
| 8957 %} | |
| 8958 | |
| 8959 // Xor Register with Memory | |
| 8960 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 8961 %{ | |
| 8962 match(Set dst (XorL dst (LoadL src))); | |
| 8963 effect(KILL cr); | |
| 8964 | |
| 8965 ins_cost(125); | |
| 8966 format %{ "xorq $dst, $src\t# long" %} | |
| 8967 opcode(0x33); | |
| 8968 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 8969 ins_pipe(ialu_reg_mem); | |
| 8970 %} | |
| 8971 | |
| 8972 // Xor Memory with Register | |
| 8973 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 8974 %{ | |
| 8975 match(Set dst (StoreL dst (XorL (LoadL dst) src))); | |
| 8976 effect(KILL cr); | |
| 8977 | |
| 8978 ins_cost(150); | |
| 8979 format %{ "xorq $dst, $src\t# long" %} | |
| 8980 opcode(0x31); /* Opcode 31 /r */ | |
| 8981 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 8982 ins_pipe(ialu_mem_reg); | |
| 8983 %} | |
| 8984 | |
| 8985 // Xor Memory with Immediate | |
| 8986 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 8987 %{ | |
| 8988 match(Set dst (StoreL dst (XorL (LoadL dst) src))); | |
| 8989 effect(KILL cr); | |
| 8990 | |
| 8991 ins_cost(125); | |
| 8992 format %{ "xorq $dst, $src\t# long" %} | |
| 8993 opcode(0x81, 0x6); /* Opcode 81 /6 id */ | |
| 8994 ins_encode(REX_mem_wide(dst), OpcSE(src), | |
| 8995 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 8996 ins_pipe(ialu_mem_imm); | |
| 8997 %} | |
| 8998 | |
| 8999 // Convert Int to Boolean | |
| 9000 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr) | |
| 9001 %{ | |
| 9002 match(Set dst (Conv2B src)); | |
| 9003 effect(KILL cr); | |
| 9004 | |
| 9005 format %{ "testl $src, $src\t# ci2b\n\t" | |
| 9006 "setnz $dst\n\t" | |
| 9007 "movzbl $dst, $dst" %} | |
| 9008 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl | |
| 9009 setNZ_reg(dst), | |
| 9010 REX_reg_breg(dst, dst), // movzbl | |
| 9011 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst)); | |
| 9012 ins_pipe(pipe_slow); // XXX | |
| 9013 %} | |
| 9014 | |
| 9015 // Convert Pointer to Boolean | |
| 9016 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr) | |
| 9017 %{ | |
| 9018 match(Set dst (Conv2B src)); | |
| 9019 effect(KILL cr); | |
| 9020 | |
| 9021 format %{ "testq $src, $src\t# cp2b\n\t" | |
| 9022 "setnz $dst\n\t" | |
| 9023 "movzbl $dst, $dst" %} | |
| 9024 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq | |
| 9025 setNZ_reg(dst), | |
| 9026 REX_reg_breg(dst, dst), // movzbl | |
| 9027 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst)); | |
| 9028 ins_pipe(pipe_slow); // XXX | |
| 9029 %} | |
| 9030 | |
| 9031 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr) | |
| 9032 %{ | |
| 9033 match(Set dst (CmpLTMask p q)); | |
| 9034 effect(KILL cr); | |
| 9035 | |
| 9154 | 9036 ins_cost(400); |
| 0 | 9037 format %{ "cmpl $p, $q\t# cmpLTMask\n\t" |
| 9038 "setlt $dst\n\t" | |
| 9039 "movzbl $dst, $dst\n\t" | |
| 9040 "negl $dst" %} | |
| 9041 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl | |
| 9042 setLT_reg(dst), | |
| 9043 REX_reg_breg(dst, dst), // movzbl | |
| 9044 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst), | |
| 9045 neg_reg(dst)); | |
| 9046 ins_pipe(pipe_slow); | |
| 9047 %} | |
| 9048 | |
| 9049 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr) | |
| 9050 %{ | |
| 9051 match(Set dst (CmpLTMask dst zero)); | |
| 9052 effect(KILL cr); | |
| 9053 | |
| 9154 | 9054 ins_cost(100); |
| 0 | 9055 format %{ "sarl $dst, #31\t# cmpLTMask0" %} |
| 9154 | 9056 ins_encode %{ |
| 9057 __ sarl($dst$$Register, 31); | |
| 9058 %} | |
| 0 | 9059 ins_pipe(ialu_reg); |
| 9060 %} | |
| 9061 | |
| 9154 | 9062 /* Better to save a register than avoid a branch */ |
| 9063 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr) | |
| 0 | 9064 %{ |
| 9065 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); | |
| 9154 | 9066 effect(KILL cr); |
| 9067 ins_cost(300); | |
| 9068 format %{ "subl $p,$q\t# cadd_cmpLTMask\n\t" | |
| 9069 "jge done\n\t" | |
| 9070 "addl $p,$y\n" | |
| 9071 "done: " %} | |
|
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9072 ins_encode %{ |
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9073 Register Rp = $p$$Register; |
|
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9074 Register Rq = $q$$Register; |
|
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9075 Register Ry = $y$$Register; |
| 9154 | 9076 Label done; |
|
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9077 __ subl(Rp, Rq); |
| 9154 | 9078 __ jccb(Assembler::greaterEqual, done); |
| 9079 __ addl(Rp, Ry); | |
| 9080 __ bind(done); | |
|
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9081 %} |
| 0 | 9082 ins_pipe(pipe_cmplt); |
| 9083 %} | |
| 9084 | |
| 9154 | 9085 /* Better to save a register than avoid a branch */ |
| 9086 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr) | |
| 9087 %{ | |
| 9088 match(Set y (AndI (CmpLTMask p q) y)); | |
| 9089 effect(KILL cr); | |
| 9090 | |
| 9091 ins_cost(300); | |
| 9092 | |
| 9093 format %{ "cmpl $p, $q\t# and_cmpLTMask\n\t" | |
| 9094 "jlt done\n\t" | |
| 9095 "xorl $y, $y\n" | |
| 9096 "done: " %} | |
| 9097 ins_encode %{ | |
| 9098 Register Rp = $p$$Register; | |
| 9099 Register Rq = $q$$Register; | |
| 9100 Register Ry = $y$$Register; | |
| 9101 Label done; | |
| 9102 __ cmpl(Rp, Rq); | |
| 9103 __ jccb(Assembler::less, done); | |
| 9104 __ xorl(Ry, Ry); | |
| 9105 __ bind(done); | |
| 9106 %} | |
| 9107 ins_pipe(pipe_cmplt); | |
| 9108 %} | |
| 9109 | |
| 9110 | |
| 0 | 9111 //---------- FP Instructions------------------------------------------------ |
| 9112 | |
| 9113 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2) | |
| 9114 %{ | |
| 9115 match(Set cr (CmpF src1 src2)); | |
| 9116 | |
| 9117 ins_cost(145); | |
| 9118 format %{ "ucomiss $src1, $src2\n\t" | |
| 9119 "jnp,s exit\n\t" | |
| 9120 "pushfq\t# saw NaN, set CF\n\t" | |
| 9121 "andq [rsp], #0xffffff2b\n\t" | |
| 9122 "popfq\n" | |
| 4759 | 9123 "exit:" %} |
| 9124 ins_encode %{ | |
| 9125 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9126 emit_cmpfp_fixup(_masm); | |
| 9127 %} | |
| 0 | 9128 ins_pipe(pipe_slow); |
| 9129 %} | |
| 9130 | |
|
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9131 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{ |
|
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|
9132 match(Set cr (CmpF src1 src2)); |
|
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|
9133 |
| 4759 | 9134 ins_cost(100); |
|
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changeset
|
9135 format %{ "ucomiss $src1, $src2" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9136 ins_encode %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9137 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9138 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9139 ins_pipe(pipe_slow); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9140 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9141 |
| 0 | 9142 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2) |
| 9143 %{ | |
| 9144 match(Set cr (CmpF src1 (LoadF src2))); | |
| 9145 | |
| 9146 ins_cost(145); | |
| 9147 format %{ "ucomiss $src1, $src2\n\t" | |
| 9148 "jnp,s exit\n\t" | |
| 9149 "pushfq\t# saw NaN, set CF\n\t" | |
| 9150 "andq [rsp], #0xffffff2b\n\t" | |
| 9151 "popfq\n" | |
| 4759 | 9152 "exit:" %} |
| 9153 ins_encode %{ | |
| 9154 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 9155 emit_cmpfp_fixup(_masm); | |
| 9156 %} | |
| 0 | 9157 ins_pipe(pipe_slow); |
| 9158 %} | |
| 9159 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9160 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9161 match(Set cr (CmpF src1 (LoadF src2))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9162 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9163 ins_cost(100); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9164 format %{ "ucomiss $src1, $src2" %} |
| 4759 | 9165 ins_encode %{ |
| 9166 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 9167 %} | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9168 ins_pipe(pipe_slow); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9169 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9170 |
| 2008 | 9171 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{ |
| 9172 match(Set cr (CmpF src con)); | |
| 0 | 9173 |
| 9174 ins_cost(145); | |
| 2008 | 9175 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t" |
| 0 | 9176 "jnp,s exit\n\t" |
| 9177 "pushfq\t# saw NaN, set CF\n\t" | |
| 9178 "andq [rsp], #0xffffff2b\n\t" | |
| 9179 "popfq\n" | |
| 4759 | 9180 "exit:" %} |
| 2008 | 9181 ins_encode %{ |
| 9182 __ ucomiss($src$$XMMRegister, $constantaddress($con)); | |
| 3783 | 9183 emit_cmpfp_fixup(_masm); |
| 2008 | 9184 %} |
| 9185 ins_pipe(pipe_slow); | |
| 9186 %} | |
| 9187 | |
| 9188 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{ | |
| 9189 match(Set cr (CmpF src con)); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9190 ins_cost(100); |
| 2008 | 9191 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %} |
| 9192 ins_encode %{ | |
| 9193 __ ucomiss($src$$XMMRegister, $constantaddress($con)); | |
| 9194 %} | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9195 ins_pipe(pipe_slow); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9196 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9197 |
| 0 | 9198 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2) |
| 9199 %{ | |
| 9200 match(Set cr (CmpD src1 src2)); | |
| 9201 | |
| 9202 ins_cost(145); | |
| 9203 format %{ "ucomisd $src1, $src2\n\t" | |
| 9204 "jnp,s exit\n\t" | |
| 9205 "pushfq\t# saw NaN, set CF\n\t" | |
| 9206 "andq [rsp], #0xffffff2b\n\t" | |
| 9207 "popfq\n" | |
| 4759 | 9208 "exit:" %} |
| 9209 ins_encode %{ | |
| 9210 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9211 emit_cmpfp_fixup(_masm); | |
| 9212 %} | |
| 0 | 9213 ins_pipe(pipe_slow); |
| 9214 %} | |
| 9215 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9216 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9217 match(Set cr (CmpD src1 src2)); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9218 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9219 ins_cost(100); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9220 format %{ "ucomisd $src1, $src2 test" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9221 ins_encode %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9222 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9223 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9224 ins_pipe(pipe_slow); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9225 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9226 |
| 0 | 9227 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2) |
| 9228 %{ | |
| 9229 match(Set cr (CmpD src1 (LoadD src2))); | |
| 9230 | |
| 9231 ins_cost(145); | |
| 9232 format %{ "ucomisd $src1, $src2\n\t" | |
| 9233 "jnp,s exit\n\t" | |
| 9234 "pushfq\t# saw NaN, set CF\n\t" | |
| 9235 "andq [rsp], #0xffffff2b\n\t" | |
| 9236 "popfq\n" | |
| 4759 | 9237 "exit:" %} |
| 9238 ins_encode %{ | |
| 9239 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9240 emit_cmpfp_fixup(_masm); | |
| 9241 %} | |
| 0 | 9242 ins_pipe(pipe_slow); |
| 9243 %} | |
| 9244 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9245 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9246 match(Set cr (CmpD src1 (LoadD src2))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9247 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9248 ins_cost(100); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9249 format %{ "ucomisd $src1, $src2" %} |
| 4759 | 9250 ins_encode %{ |
| 9251 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9252 %} | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
9253 ins_pipe(pipe_slow); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9254 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9255 |
| 2008 | 9256 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{ |
| 9257 match(Set cr (CmpD src con)); | |
| 0 | 9258 |
| 9259 ins_cost(145); | |
| 2008 | 9260 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 9261 "jnp,s exit\n\t" |
| 9262 "pushfq\t# saw NaN, set CF\n\t" | |
| 9263 "andq [rsp], #0xffffff2b\n\t" | |
| 9264 "popfq\n" | |
| 4759 | 9265 "exit:" %} |
| 2008 | 9266 ins_encode %{ |
| 9267 __ ucomisd($src$$XMMRegister, $constantaddress($con)); | |
| 3783 | 9268 emit_cmpfp_fixup(_masm); |
| 2008 | 9269 %} |
| 9270 ins_pipe(pipe_slow); | |
| 9271 %} | |
| 9272 | |
| 9273 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{ | |
| 9274 match(Set cr (CmpD src con)); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9275 ins_cost(100); |
| 2008 | 9276 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %} |
| 9277 ins_encode %{ | |
| 9278 __ ucomisd($src$$XMMRegister, $constantaddress($con)); | |
| 9279 %} | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9280 ins_pipe(pipe_slow); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9281 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9282 |
| 0 | 9283 // Compare into -1,0,1 |
| 9284 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr) | |
| 9285 %{ | |
| 9286 match(Set dst (CmpF3 src1 src2)); | |
| 9287 effect(KILL cr); | |
| 9288 | |
| 9289 ins_cost(275); | |
| 9290 format %{ "ucomiss $src1, $src2\n\t" | |
| 9291 "movl $dst, #-1\n\t" | |
| 9292 "jp,s done\n\t" | |
| 9293 "jb,s done\n\t" | |
| 9294 "setne $dst\n\t" | |
| 9295 "movzbl $dst, $dst\n" | |
| 9296 "done:" %} | |
| 4759 | 9297 ins_encode %{ |
| 9298 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9299 emit_cmpfp3(_masm, $dst$$Register); | |
| 9300 %} | |
| 0 | 9301 ins_pipe(pipe_slow); |
| 9302 %} | |
| 9303 | |
| 9304 // Compare into -1,0,1 | |
| 9305 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr) | |
| 9306 %{ | |
| 9307 match(Set dst (CmpF3 src1 (LoadF src2))); | |
| 9308 effect(KILL cr); | |
| 9309 | |
| 9310 ins_cost(275); | |
| 9311 format %{ "ucomiss $src1, $src2\n\t" | |
| 9312 "movl $dst, #-1\n\t" | |
| 9313 "jp,s done\n\t" | |
| 9314 "jb,s done\n\t" | |
| 9315 "setne $dst\n\t" | |
| 9316 "movzbl $dst, $dst\n" | |
| 9317 "done:" %} | |
| 4759 | 9318 ins_encode %{ |
| 9319 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 9320 emit_cmpfp3(_masm, $dst$$Register); | |
| 9321 %} | |
| 0 | 9322 ins_pipe(pipe_slow); |
| 9323 %} | |
| 9324 | |
| 9325 // Compare into -1,0,1 | |
| 2008 | 9326 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{ |
| 9327 match(Set dst (CmpF3 src con)); | |
| 0 | 9328 effect(KILL cr); |
| 9329 | |
| 9330 ins_cost(275); | |
| 2008 | 9331 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t" |
| 0 | 9332 "movl $dst, #-1\n\t" |
| 9333 "jp,s done\n\t" | |
| 9334 "jb,s done\n\t" | |
| 9335 "setne $dst\n\t" | |
| 9336 "movzbl $dst, $dst\n" | |
| 9337 "done:" %} | |
| 2008 | 9338 ins_encode %{ |
| 9339 __ ucomiss($src$$XMMRegister, $constantaddress($con)); | |
| 4759 | 9340 emit_cmpfp3(_masm, $dst$$Register); |
| 2008 | 9341 %} |
| 0 | 9342 ins_pipe(pipe_slow); |
| 9343 %} | |
| 9344 | |
| 9345 // Compare into -1,0,1 | |
| 9346 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr) | |
| 9347 %{ | |
| 9348 match(Set dst (CmpD3 src1 src2)); | |
| 9349 effect(KILL cr); | |
| 9350 | |
| 9351 ins_cost(275); | |
| 9352 format %{ "ucomisd $src1, $src2\n\t" | |
| 9353 "movl $dst, #-1\n\t" | |
| 9354 "jp,s done\n\t" | |
| 9355 "jb,s done\n\t" | |
| 9356 "setne $dst\n\t" | |
| 9357 "movzbl $dst, $dst\n" | |
| 9358 "done:" %} | |
| 4759 | 9359 ins_encode %{ |
| 9360 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9361 emit_cmpfp3(_masm, $dst$$Register); | |
| 9362 %} | |
| 0 | 9363 ins_pipe(pipe_slow); |
| 9364 %} | |
| 9365 | |
| 9366 // Compare into -1,0,1 | |
| 9367 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr) | |
| 9368 %{ | |
| 9369 match(Set dst (CmpD3 src1 (LoadD src2))); | |
| 9370 effect(KILL cr); | |
| 9371 | |
| 9372 ins_cost(275); | |
| 9373 format %{ "ucomisd $src1, $src2\n\t" | |
| 9374 "movl $dst, #-1\n\t" | |
| 9375 "jp,s done\n\t" | |
| 9376 "jb,s done\n\t" | |
| 9377 "setne $dst\n\t" | |
| 9378 "movzbl $dst, $dst\n" | |
| 9379 "done:" %} | |
| 4759 | 9380 ins_encode %{ |
| 9381 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9382 emit_cmpfp3(_masm, $dst$$Register); | |
| 9383 %} | |
| 0 | 9384 ins_pipe(pipe_slow); |
| 9385 %} | |
| 9386 | |
| 9387 // Compare into -1,0,1 | |
| 2008 | 9388 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{ |
| 9389 match(Set dst (CmpD3 src con)); | |
| 0 | 9390 effect(KILL cr); |
| 9391 | |
| 9392 ins_cost(275); | |
| 2008 | 9393 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 9394 "movl $dst, #-1\n\t" |
| 9395 "jp,s done\n\t" | |
| 9396 "jb,s done\n\t" | |
| 9397 "setne $dst\n\t" | |
| 9398 "movzbl $dst, $dst\n" | |
| 9399 "done:" %} | |
| 2008 | 9400 ins_encode %{ |
| 9401 __ ucomisd($src$$XMMRegister, $constantaddress($con)); | |
| 4759 | 9402 emit_cmpfp3(_masm, $dst$$Register); |
| 2008 | 9403 %} |
| 0 | 9404 ins_pipe(pipe_slow); |
| 9405 %} | |
| 9406 | |
| 9407 // -----------Trig and Trancendental Instructions------------------------------ | |
| 9408 instruct cosD_reg(regD dst) %{ | |
| 9409 match(Set dst (CosD dst)); | |
| 9410 | |
| 9411 format %{ "dcos $dst\n\t" %} | |
| 9412 opcode(0xD9, 0xFF); | |
| 9413 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) ); | |
| 9414 ins_pipe( pipe_slow ); | |
| 9415 %} | |
| 9416 | |
| 9417 instruct sinD_reg(regD dst) %{ | |
| 9418 match(Set dst (SinD dst)); | |
| 9419 | |
| 9420 format %{ "dsin $dst\n\t" %} | |
| 9421 opcode(0xD9, 0xFE); | |
| 9422 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) ); | |
| 9423 ins_pipe( pipe_slow ); | |
| 9424 %} | |
| 9425 | |
| 9426 instruct tanD_reg(regD dst) %{ | |
| 9427 match(Set dst (TanD dst)); | |
| 9428 | |
| 9429 format %{ "dtan $dst\n\t" %} | |
| 9430 ins_encode( Push_SrcXD(dst), | |
| 9431 Opcode(0xD9), Opcode(0xF2), //fptan | |
| 9432 Opcode(0xDD), Opcode(0xD8), //fstp st | |
| 9433 Push_ResultXD(dst) ); | |
| 9434 ins_pipe( pipe_slow ); | |
| 9435 %} | |
| 9436 | |
| 9437 instruct log10D_reg(regD dst) %{ | |
| 9438 // The source and result Double operands in XMM registers | |
| 9439 match(Set dst (Log10D dst)); | |
| 9440 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number | |
| 9441 // fyl2x ; compute log_10(2) * log_2(x) | |
| 9442 format %{ "fldlg2\t\t\t#Log10\n\t" | |
| 9443 "fyl2x\t\t\t# Q=Log10*Log_2(x)\n\t" | |
| 9444 %} | |
| 9445 ins_encode(Opcode(0xD9), Opcode(0xEC), // fldlg2 | |
| 9446 Push_SrcXD(dst), | |
| 9447 Opcode(0xD9), Opcode(0xF1), // fyl2x | |
| 9448 Push_ResultXD(dst)); | |
| 9449 | |
| 9450 ins_pipe( pipe_slow ); | |
| 9451 %} | |
| 9452 | |
| 9453 instruct logD_reg(regD dst) %{ | |
| 9454 // The source and result Double operands in XMM registers | |
| 9455 match(Set dst (LogD dst)); | |
| 9456 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number | |
| 9457 // fyl2x ; compute log_e(2) * log_2(x) | |
| 9458 format %{ "fldln2\t\t\t#Log_e\n\t" | |
| 9459 "fyl2x\t\t\t# Q=Log_e*Log_2(x)\n\t" | |
| 9460 %} | |
| 9461 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 | |
| 9462 Push_SrcXD(dst), | |
| 9463 Opcode(0xD9), Opcode(0xF1), // fyl2x | |
| 9464 Push_ResultXD(dst)); | |
| 9465 ins_pipe( pipe_slow ); | |
| 9466 %} | |
| 9467 | |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9468 instruct powD_reg(regD dst, regD src0, regD src1, rax_RegI rax, rdx_RegI rdx, rcx_RegI rcx, rFlagsReg cr) %{ |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9469 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9470 effect(KILL rax, KILL rdx, KILL rcx, KILL cr); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9471 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
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|
9472 ins_encode %{ |
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9473 __ subptr(rsp, 8); |
|
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|
9474 __ movdbl(Address(rsp, 0), $src1$$XMMRegister); |
|
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|
9475 __ fld_d(Address(rsp, 0)); |
|
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9476 __ movdbl(Address(rsp, 0), $src0$$XMMRegister); |
|
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|
9477 __ fld_d(Address(rsp, 0)); |
|
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9478 __ fast_pow(); |
|
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|
9479 __ fstp_d(Address(rsp, 0)); |
|
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9480 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); |
|
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|
9481 __ addptr(rsp, 8); |
|
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|
9482 %} |
|
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|
9483 ins_pipe( pipe_slow ); |
|
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|
9484 %} |
|
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|
9485 |
|
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|
9486 instruct expD_reg(regD dst, regD src, rax_RegI rax, rdx_RegI rdx, rcx_RegI rcx, rFlagsReg cr) %{ |
|
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|
9487 match(Set dst (ExpD src)); |
|
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|
9488 effect(KILL rax, KILL rcx, KILL rdx, KILL cr); |
|
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9489 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %} |
|
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|
9490 ins_encode %{ |
|
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|
9491 __ subptr(rsp, 8); |
|
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|
9492 __ movdbl(Address(rsp, 0), $src$$XMMRegister); |
|
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|
9493 __ fld_d(Address(rsp, 0)); |
|
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|
9494 __ fast_exp(); |
|
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|
9495 __ fstp_d(Address(rsp, 0)); |
|
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|
9496 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); |
|
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|
9497 __ addptr(rsp, 8); |
|
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|
9498 %} |
|
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|
9499 ins_pipe( pipe_slow ); |
|
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|
9500 %} |
| 0 | 9501 |
| 9502 //----------Arithmetic Conversion Instructions--------------------------------- | |
| 9503 | |
| 9504 instruct roundFloat_nop(regF dst) | |
| 9505 %{ | |
| 9506 match(Set dst (RoundFloat dst)); | |
| 9507 | |
| 9508 ins_cost(0); | |
| 9509 ins_encode(); | |
| 9510 ins_pipe(empty); | |
| 9511 %} | |
| 9512 | |
| 9513 instruct roundDouble_nop(regD dst) | |
| 9514 %{ | |
| 9515 match(Set dst (RoundDouble dst)); | |
| 9516 | |
| 9517 ins_cost(0); | |
| 9518 ins_encode(); | |
| 9519 ins_pipe(empty); | |
| 9520 %} | |
| 9521 | |
| 9522 instruct convF2D_reg_reg(regD dst, regF src) | |
| 9523 %{ | |
| 9524 match(Set dst (ConvF2D src)); | |
| 9525 | |
| 9526 format %{ "cvtss2sd $dst, $src" %} | |
| 4759 | 9527 ins_encode %{ |
| 9528 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister); | |
| 9529 %} | |
| 0 | 9530 ins_pipe(pipe_slow); // XXX |
| 9531 %} | |
| 9532 | |
| 9533 instruct convF2D_reg_mem(regD dst, memory src) | |
| 9534 %{ | |
| 9535 match(Set dst (ConvF2D (LoadF src))); | |
| 9536 | |
| 9537 format %{ "cvtss2sd $dst, $src" %} | |
| 4759 | 9538 ins_encode %{ |
| 9539 __ cvtss2sd ($dst$$XMMRegister, $src$$Address); | |
| 9540 %} | |
| 0 | 9541 ins_pipe(pipe_slow); // XXX |
| 9542 %} | |
| 9543 | |
| 9544 instruct convD2F_reg_reg(regF dst, regD src) | |
| 9545 %{ | |
| 9546 match(Set dst (ConvD2F src)); | |
| 9547 | |
| 9548 format %{ "cvtsd2ss $dst, $src" %} | |
| 4759 | 9549 ins_encode %{ |
| 9550 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister); | |
| 9551 %} | |
| 0 | 9552 ins_pipe(pipe_slow); // XXX |
| 9553 %} | |
| 9554 | |
| 9555 instruct convD2F_reg_mem(regF dst, memory src) | |
| 9556 %{ | |
| 9557 match(Set dst (ConvD2F (LoadD src))); | |
| 9558 | |
| 9559 format %{ "cvtsd2ss $dst, $src" %} | |
| 4759 | 9560 ins_encode %{ |
| 9561 __ cvtsd2ss ($dst$$XMMRegister, $src$$Address); | |
| 9562 %} | |
| 0 | 9563 ins_pipe(pipe_slow); // XXX |
| 9564 %} | |
| 9565 | |
| 9566 // XXX do mem variants | |
| 9567 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr) | |
| 9568 %{ | |
| 9569 match(Set dst (ConvF2I src)); | |
| 9570 effect(KILL cr); | |
| 9571 | |
| 9572 format %{ "cvttss2sil $dst, $src\t# f2i\n\t" | |
| 9573 "cmpl $dst, #0x80000000\n\t" | |
| 9574 "jne,s done\n\t" | |
| 9575 "subq rsp, #8\n\t" | |
| 9576 "movss [rsp], $src\n\t" | |
| 9577 "call f2i_fixup\n\t" | |
| 9578 "popq $dst\n" | |
| 9579 "done: "%} | |
| 4759 | 9580 ins_encode %{ |
| 9581 Label done; | |
| 9582 __ cvttss2sil($dst$$Register, $src$$XMMRegister); | |
| 9583 __ cmpl($dst$$Register, 0x80000000); | |
| 9584 __ jccb(Assembler::notEqual, done); | |
| 9585 __ subptr(rsp, 8); | |
| 9586 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 9587 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup()))); | |
| 9588 __ pop($dst$$Register); | |
| 9589 __ bind(done); | |
| 9590 %} | |
| 0 | 9591 ins_pipe(pipe_slow); |
| 9592 %} | |
| 9593 | |
| 9594 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr) | |
| 9595 %{ | |
| 9596 match(Set dst (ConvF2L src)); | |
| 9597 effect(KILL cr); | |
| 9598 | |
| 9599 format %{ "cvttss2siq $dst, $src\t# f2l\n\t" | |
| 9600 "cmpq $dst, [0x8000000000000000]\n\t" | |
| 9601 "jne,s done\n\t" | |
| 9602 "subq rsp, #8\n\t" | |
| 9603 "movss [rsp], $src\n\t" | |
| 9604 "call f2l_fixup\n\t" | |
| 9605 "popq $dst\n" | |
| 9606 "done: "%} | |
| 4759 | 9607 ins_encode %{ |
| 9608 Label done; | |
| 9609 __ cvttss2siq($dst$$Register, $src$$XMMRegister); | |
| 9610 __ cmp64($dst$$Register, | |
| 9611 ExternalAddress((address) StubRoutines::x86::double_sign_flip())); | |
| 9612 __ jccb(Assembler::notEqual, done); | |
| 9613 __ subptr(rsp, 8); | |
| 9614 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 9615 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup()))); | |
| 9616 __ pop($dst$$Register); | |
| 9617 __ bind(done); | |
| 9618 %} | |
| 0 | 9619 ins_pipe(pipe_slow); |
| 9620 %} | |
| 9621 | |
| 9622 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr) | |
| 9623 %{ | |
| 9624 match(Set dst (ConvD2I src)); | |
| 9625 effect(KILL cr); | |
| 9626 | |
| 9627 format %{ "cvttsd2sil $dst, $src\t# d2i\n\t" | |
| 9628 "cmpl $dst, #0x80000000\n\t" | |
| 9629 "jne,s done\n\t" | |
| 9630 "subq rsp, #8\n\t" | |
| 9631 "movsd [rsp], $src\n\t" | |
| 9632 "call d2i_fixup\n\t" | |
| 9633 "popq $dst\n" | |
| 9634 "done: "%} | |
| 4759 | 9635 ins_encode %{ |
| 9636 Label done; | |
| 9637 __ cvttsd2sil($dst$$Register, $src$$XMMRegister); | |
| 9638 __ cmpl($dst$$Register, 0x80000000); | |
| 9639 __ jccb(Assembler::notEqual, done); | |
| 9640 __ subptr(rsp, 8); | |
| 9641 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 9642 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup()))); | |
| 9643 __ pop($dst$$Register); | |
| 9644 __ bind(done); | |
| 9645 %} | |
| 0 | 9646 ins_pipe(pipe_slow); |
| 9647 %} | |
| 9648 | |
| 9649 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr) | |
| 9650 %{ | |
| 9651 match(Set dst (ConvD2L src)); | |
| 9652 effect(KILL cr); | |
| 9653 | |
| 9654 format %{ "cvttsd2siq $dst, $src\t# d2l\n\t" | |
| 9655 "cmpq $dst, [0x8000000000000000]\n\t" | |
| 9656 "jne,s done\n\t" | |
| 9657 "subq rsp, #8\n\t" | |
| 9658 "movsd [rsp], $src\n\t" | |
| 9659 "call d2l_fixup\n\t" | |
| 9660 "popq $dst\n" | |
| 9661 "done: "%} | |
| 4759 | 9662 ins_encode %{ |
| 9663 Label done; | |
| 9664 __ cvttsd2siq($dst$$Register, $src$$XMMRegister); | |
| 9665 __ cmp64($dst$$Register, | |
| 9666 ExternalAddress((address) StubRoutines::x86::double_sign_flip())); | |
| 9667 __ jccb(Assembler::notEqual, done); | |
| 9668 __ subptr(rsp, 8); | |
| 9669 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 9670 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup()))); | |
| 9671 __ pop($dst$$Register); | |
| 9672 __ bind(done); | |
| 9673 %} | |
| 0 | 9674 ins_pipe(pipe_slow); |
| 9675 %} | |
| 9676 | |
| 9677 instruct convI2F_reg_reg(regF dst, rRegI src) | |
| 9678 %{ | |
| 71 | 9679 predicate(!UseXmmI2F); |
| 0 | 9680 match(Set dst (ConvI2F src)); |
| 9681 | |
| 9682 format %{ "cvtsi2ssl $dst, $src\t# i2f" %} | |
| 4759 | 9683 ins_encode %{ |
| 9684 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register); | |
| 9685 %} | |
| 0 | 9686 ins_pipe(pipe_slow); // XXX |
| 9687 %} | |
| 9688 | |
| 9689 instruct convI2F_reg_mem(regF dst, memory src) | |
| 9690 %{ | |
| 9691 match(Set dst (ConvI2F (LoadI src))); | |
| 9692 | |
| 9693 format %{ "cvtsi2ssl $dst, $src\t# i2f" %} | |
| 4759 | 9694 ins_encode %{ |
| 9695 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address); | |
| 9696 %} | |
| 0 | 9697 ins_pipe(pipe_slow); // XXX |
| 9698 %} | |
| 9699 | |
| 9700 instruct convI2D_reg_reg(regD dst, rRegI src) | |
| 9701 %{ | |
| 71 | 9702 predicate(!UseXmmI2D); |
| 0 | 9703 match(Set dst (ConvI2D src)); |
| 9704 | |
| 9705 format %{ "cvtsi2sdl $dst, $src\t# i2d" %} | |
| 4759 | 9706 ins_encode %{ |
| 9707 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register); | |
| 9708 %} | |
| 0 | 9709 ins_pipe(pipe_slow); // XXX |
| 9710 %} | |
| 9711 | |
| 9712 instruct convI2D_reg_mem(regD dst, memory src) | |
| 9713 %{ | |
| 9714 match(Set dst (ConvI2D (LoadI src))); | |
| 9715 | |
| 9716 format %{ "cvtsi2sdl $dst, $src\t# i2d" %} | |
| 4759 | 9717 ins_encode %{ |
| 9718 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address); | |
| 9719 %} | |
| 0 | 9720 ins_pipe(pipe_slow); // XXX |
| 9721 %} | |
| 9722 | |
| 71 | 9723 instruct convXI2F_reg(regF dst, rRegI src) |
| 9724 %{ | |
| 9725 predicate(UseXmmI2F); | |
| 9726 match(Set dst (ConvI2F src)); | |
| 9727 | |
| 9728 format %{ "movdl $dst, $src\n\t" | |
| 9729 "cvtdq2psl $dst, $dst\t# i2f" %} | |
| 9730 ins_encode %{ | |
| 9731 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 9732 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister); | |
| 9733 %} | |
| 9734 ins_pipe(pipe_slow); // XXX | |
| 9735 %} | |
| 9736 | |
| 9737 instruct convXI2D_reg(regD dst, rRegI src) | |
| 9738 %{ | |
| 9739 predicate(UseXmmI2D); | |
| 9740 match(Set dst (ConvI2D src)); | |
| 9741 | |
| 9742 format %{ "movdl $dst, $src\n\t" | |
| 9743 "cvtdq2pdl $dst, $dst\t# i2d" %} | |
| 9744 ins_encode %{ | |
| 9745 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 9746 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister); | |
| 9747 %} | |
| 9748 ins_pipe(pipe_slow); // XXX | |
| 9749 %} | |
| 9750 | |
| 0 | 9751 instruct convL2F_reg_reg(regF dst, rRegL src) |
| 9752 %{ | |
| 9753 match(Set dst (ConvL2F src)); | |
| 9754 | |
| 9755 format %{ "cvtsi2ssq $dst, $src\t# l2f" %} | |
| 4759 | 9756 ins_encode %{ |
| 9757 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register); | |
| 9758 %} | |
| 0 | 9759 ins_pipe(pipe_slow); // XXX |
| 9760 %} | |
| 9761 | |
| 9762 instruct convL2F_reg_mem(regF dst, memory src) | |
| 9763 %{ | |
| 9764 match(Set dst (ConvL2F (LoadL src))); | |
| 9765 | |
| 9766 format %{ "cvtsi2ssq $dst, $src\t# l2f" %} | |
| 4759 | 9767 ins_encode %{ |
| 9768 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address); | |
| 9769 %} | |
| 0 | 9770 ins_pipe(pipe_slow); // XXX |
| 9771 %} | |
| 9772 | |
| 9773 instruct convL2D_reg_reg(regD dst, rRegL src) | |
| 9774 %{ | |
| 9775 match(Set dst (ConvL2D src)); | |
| 9776 | |
| 9777 format %{ "cvtsi2sdq $dst, $src\t# l2d" %} | |
| 4759 | 9778 ins_encode %{ |
| 9779 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register); | |
| 9780 %} | |
| 0 | 9781 ins_pipe(pipe_slow); // XXX |
| 9782 %} | |
| 9783 | |
| 9784 instruct convL2D_reg_mem(regD dst, memory src) | |
| 9785 %{ | |
| 9786 match(Set dst (ConvL2D (LoadL src))); | |
| 9787 | |
| 9788 format %{ "cvtsi2sdq $dst, $src\t# l2d" %} | |
| 4759 | 9789 ins_encode %{ |
| 9790 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address); | |
| 9791 %} | |
| 0 | 9792 ins_pipe(pipe_slow); // XXX |
| 9793 %} | |
| 9794 | |
| 9795 instruct convI2L_reg_reg(rRegL dst, rRegI src) | |
| 9796 %{ | |
| 9797 match(Set dst (ConvI2L src)); | |
| 9798 | |
| 9799 ins_cost(125); | |
| 9800 format %{ "movslq $dst, $src\t# i2l" %} | |
| 824 | 9801 ins_encode %{ |
| 9802 __ movslq($dst$$Register, $src$$Register); | |
| 9803 %} | |
| 0 | 9804 ins_pipe(ialu_reg_reg); |
| 9805 %} | |
| 9806 | |
| 9807 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src) | |
| 9808 // %{ | |
| 9809 // match(Set dst (ConvI2L src)); | |
| 9810 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 && | |
| 9811 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0); | |
| 9812 // predicate(((const TypeNode*) n)->type()->is_long()->_hi == | |
| 9813 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi && | |
| 9814 // ((const TypeNode*) n)->type()->is_long()->_lo == | |
| 9815 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo); | |
| 9816 | |
| 9817 // format %{ "movl $dst, $src\t# unsigned i2l" %} | |
| 9818 // ins_encode(enc_copy(dst, src)); | |
| 9819 // // opcode(0x63); // needs REX.W | |
| 9820 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src)); | |
| 9821 // ins_pipe(ialu_reg_reg); | |
| 9822 // %} | |
| 9823 | |
| 9824 // Zero-extend convert int to long | |
| 9825 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask) | |
| 9826 %{ | |
| 9827 match(Set dst (AndL (ConvI2L src) mask)); | |
| 9828 | |
| 9829 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %} | |
| 4759 | 9830 ins_encode %{ |
| 9831 if ($dst$$reg != $src$$reg) { | |
| 9832 __ movl($dst$$Register, $src$$Register); | |
| 9833 } | |
| 9834 %} | |
| 0 | 9835 ins_pipe(ialu_reg_reg); |
| 9836 %} | |
| 9837 | |
| 9838 // Zero-extend convert int to long | |
| 9839 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask) | |
| 9840 %{ | |
| 9841 match(Set dst (AndL (ConvI2L (LoadI src)) mask)); | |
| 9842 | |
| 9843 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %} | |
| 4759 | 9844 ins_encode %{ |
| 9845 __ movl($dst$$Register, $src$$Address); | |
| 9846 %} | |
| 0 | 9847 ins_pipe(ialu_reg_mem); |
| 9848 %} | |
| 9849 | |
| 9850 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask) | |
| 9851 %{ | |
| 9852 match(Set dst (AndL src mask)); | |
| 9853 | |
| 9854 format %{ "movl $dst, $src\t# zero-extend long" %} | |
| 4759 | 9855 ins_encode %{ |
| 9856 __ movl($dst$$Register, $src$$Register); | |
| 9857 %} | |
| 0 | 9858 ins_pipe(ialu_reg_reg); |
| 9859 %} | |
| 9860 | |
| 9861 instruct convL2I_reg_reg(rRegI dst, rRegL src) | |
| 9862 %{ | |
| 9863 match(Set dst (ConvL2I src)); | |
| 9864 | |
| 9865 format %{ "movl $dst, $src\t# l2i" %} | |
| 4759 | 9866 ins_encode %{ |
| 9867 __ movl($dst$$Register, $src$$Register); | |
| 9868 %} | |
| 0 | 9869 ins_pipe(ialu_reg_reg); |
| 9870 %} | |
| 9871 | |
| 9872 | |
| 9873 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{ | |
| 9874 match(Set dst (MoveF2I src)); | |
| 9875 effect(DEF dst, USE src); | |
| 9876 | |
| 9877 ins_cost(125); | |
| 9878 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %} | |
| 4759 | 9879 ins_encode %{ |
| 9880 __ movl($dst$$Register, Address(rsp, $src$$disp)); | |
| 9881 %} | |
| 0 | 9882 ins_pipe(ialu_reg_mem); |
| 9883 %} | |
| 9884 | |
| 9885 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ | |
| 9886 match(Set dst (MoveI2F src)); | |
| 9887 effect(DEF dst, USE src); | |
| 9888 | |
| 9889 ins_cost(125); | |
| 9890 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %} | |
| 4759 | 9891 ins_encode %{ |
| 9892 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 9893 %} | |
| 0 | 9894 ins_pipe(pipe_slow); |
| 9895 %} | |
| 9896 | |
| 9897 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{ | |
| 9898 match(Set dst (MoveD2L src)); | |
| 9899 effect(DEF dst, USE src); | |
| 9900 | |
| 9901 ins_cost(125); | |
| 9902 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %} | |
| 4759 | 9903 ins_encode %{ |
| 9904 __ movq($dst$$Register, Address(rsp, $src$$disp)); | |
| 9905 %} | |
| 0 | 9906 ins_pipe(ialu_reg_mem); |
| 9907 %} | |
| 9908 | |
| 9909 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{ | |
| 9910 predicate(!UseXmmLoadAndClearUpper); | |
| 9911 match(Set dst (MoveL2D src)); | |
| 9912 effect(DEF dst, USE src); | |
| 9913 | |
| 9914 ins_cost(125); | |
| 9915 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %} | |
| 4759 | 9916 ins_encode %{ |
| 9917 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 9918 %} | |
| 0 | 9919 ins_pipe(pipe_slow); |
| 9920 %} | |
| 9921 | |
| 9922 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ | |
| 9923 predicate(UseXmmLoadAndClearUpper); | |
| 9924 match(Set dst (MoveL2D src)); | |
| 9925 effect(DEF dst, USE src); | |
| 9926 | |
| 9927 ins_cost(125); | |
| 9928 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %} | |
| 4759 | 9929 ins_encode %{ |
| 9930 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 9931 %} | |
| 0 | 9932 ins_pipe(pipe_slow); |
| 9933 %} | |
| 9934 | |
| 9935 | |
| 9936 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ | |
| 9937 match(Set dst (MoveF2I src)); | |
| 9938 effect(DEF dst, USE src); | |
| 9939 | |
| 9940 ins_cost(95); // XXX | |
| 9941 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %} | |
| 4759 | 9942 ins_encode %{ |
| 9943 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister); | |
| 9944 %} | |
| 0 | 9945 ins_pipe(pipe_slow); |
| 9946 %} | |
| 9947 | |
| 9948 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{ | |
| 9949 match(Set dst (MoveI2F src)); | |
| 9950 effect(DEF dst, USE src); | |
| 9951 | |
| 9952 ins_cost(100); | |
| 9953 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %} | |
| 4759 | 9954 ins_encode %{ |
| 9955 __ movl(Address(rsp, $dst$$disp), $src$$Register); | |
| 9956 %} | |
| 0 | 9957 ins_pipe( ialu_mem_reg ); |
| 9958 %} | |
| 9959 | |
| 9960 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ | |
| 9961 match(Set dst (MoveD2L src)); | |
| 9962 effect(DEF dst, USE src); | |
| 9963 | |
| 9964 ins_cost(95); // XXX | |
| 9965 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %} | |
| 4759 | 9966 ins_encode %{ |
| 9967 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister); | |
| 9968 %} | |
| 0 | 9969 ins_pipe(pipe_slow); |
| 9970 %} | |
| 9971 | |
| 9972 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{ | |
| 9973 match(Set dst (MoveL2D src)); | |
| 9974 effect(DEF dst, USE src); | |
| 9975 | |
| 9976 ins_cost(100); | |
| 9977 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %} | |
| 4759 | 9978 ins_encode %{ |
| 9979 __ movq(Address(rsp, $dst$$disp), $src$$Register); | |
| 9980 %} | |
| 0 | 9981 ins_pipe(ialu_mem_reg); |
| 9982 %} | |
| 9983 | |
| 9984 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{ | |
| 9985 match(Set dst (MoveF2I src)); | |
| 9986 effect(DEF dst, USE src); | |
| 9987 ins_cost(85); | |
| 9988 format %{ "movd $dst,$src\t# MoveF2I" %} | |
| 4759 | 9989 ins_encode %{ |
| 9990 __ movdl($dst$$Register, $src$$XMMRegister); | |
| 9991 %} | |
| 0 | 9992 ins_pipe( pipe_slow ); |
| 9993 %} | |
| 9994 | |
| 9995 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{ | |
| 9996 match(Set dst (MoveD2L src)); | |
| 9997 effect(DEF dst, USE src); | |
| 9998 ins_cost(85); | |
| 9999 format %{ "movd $dst,$src\t# MoveD2L" %} | |
| 4759 | 10000 ins_encode %{ |
| 10001 __ movdq($dst$$Register, $src$$XMMRegister); | |
| 10002 %} | |
| 0 | 10003 ins_pipe( pipe_slow ); |
| 10004 %} | |
| 10005 | |
| 10006 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{ | |
| 10007 match(Set dst (MoveI2F src)); | |
| 10008 effect(DEF dst, USE src); | |
|
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10009 ins_cost(100); |
| 0 | 10010 format %{ "movd $dst,$src\t# MoveI2F" %} |
| 4759 | 10011 ins_encode %{ |
| 10012 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 10013 %} | |
| 0 | 10014 ins_pipe( pipe_slow ); |
| 10015 %} | |
| 10016 | |
| 10017 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{ | |
| 10018 match(Set dst (MoveL2D src)); | |
| 10019 effect(DEF dst, USE src); | |
|
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10020 ins_cost(100); |
| 0 | 10021 format %{ "movd $dst,$src\t# MoveL2D" %} |
| 4759 | 10022 ins_encode %{ |
| 10023 __ movdq($dst$$XMMRegister, $src$$Register); | |
| 10024 %} | |
| 0 | 10025 ins_pipe( pipe_slow ); |
| 10026 %} | |
| 10027 | |
| 10028 | |
| 10029 // ======================================================================= | |
| 10030 // fast clearing of an array | |
| 10031 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy, | |
| 10032 rFlagsReg cr) | |
| 10033 %{ | |
|
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10034 predicate(!UseFastStosb); |
| 0 | 10035 match(Set dummy (ClearArray cnt base)); |
| 10036 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr); | |
| 10037 | |
|
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10038 format %{ "xorq rax, rax\t# ClearArray:\n\t" |
|
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10039 "rep stosq\t# Store rax to *rdi++ while rcx--" %} |
|
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10040 ins_encode %{ |
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10041 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register); |
|
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10042 %} |
| 0 | 10043 ins_pipe(pipe_slow); |
| 10044 %} | |
| 10045 | |
|
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10046 instruct rep_fast_stosb(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy, |
|
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10047 rFlagsReg cr) |
|
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10048 %{ |
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10049 predicate(UseFastStosb); |
|
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10050 match(Set dummy (ClearArray cnt base)); |
|
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10051 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr); |
|
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10052 format %{ "xorq rax, rax\t# ClearArray:\n\t" |
|
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10053 "shlq rcx,3\t# Convert doublewords to bytes\n\t" |
|
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10054 "rep stosb\t# Store rax to *rdi++ while rcx--" %} |
|
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10055 ins_encode %{ |
|
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10056 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register); |
|
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10057 %} |
|
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10058 ins_pipe( pipe_slow ); |
|
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|
10059 %} |
|
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|
10060 |
| 2262 | 10061 instruct string_compare(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2, |
| 10062 rax_RegI result, regD tmp1, rFlagsReg cr) | |
|
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10063 %{ |
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10064 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); |
| 2262 | 10065 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr); |
| 10066 | |
| 10067 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %} | |
|
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10068 ins_encode %{ |
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10069 __ string_compare($str1$$Register, $str2$$Register, |
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10070 $cnt1$$Register, $cnt2$$Register, $result$$Register, |
| 2262 | 10071 $tmp1$$XMMRegister); |
|
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10072 %} |
| 681 | 10073 ins_pipe( pipe_slow ); |
| 10074 %} | |
| 10075 | |
|
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10076 // fast search of substring with known size. |
|
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10077 instruct string_indexof_con(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2, |
|
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10078 rbx_RegI result, regD vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr) |
|
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10079 %{ |
|
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10080 predicate(UseSSE42Intrinsics); |
|
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10081 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2))); |
|
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10082 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr); |
|
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10083 |
|
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10084 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %} |
|
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10085 ins_encode %{ |
|
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10086 int icnt2 = (int)$int_cnt2$$constant; |
|
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10087 if (icnt2 >= 8) { |
|
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10088 // IndexOf for constant substrings with size >= 8 elements |
|
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10089 // which don't need to be loaded through stack. |
|
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10090 __ string_indexofC8($str1$$Register, $str2$$Register, |
|
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10091 $cnt1$$Register, $cnt2$$Register, |
|
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10092 icnt2, $result$$Register, |
|
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10093 $vec$$XMMRegister, $tmp$$Register); |
|
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10094 } else { |
|
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10095 // Small strings are loaded through stack if they cross page boundary. |
|
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10096 __ string_indexof($str1$$Register, $str2$$Register, |
|
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10097 $cnt1$$Register, $cnt2$$Register, |
|
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10098 icnt2, $result$$Register, |
|
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10099 $vec$$XMMRegister, $tmp$$Register); |
|
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10100 } |
|
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|
10101 %} |
|
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|
10102 ins_pipe( pipe_slow ); |
|
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10103 %} |
|
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10104 |
|
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10105 instruct string_indexof(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2, |
|
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10106 rbx_RegI result, regD vec, rcx_RegI tmp, rFlagsReg cr) |
| 681 | 10107 %{ |
| 10108 predicate(UseSSE42Intrinsics); | |
|
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10109 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2))); |
|
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10110 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr); |
|
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10111 |
|
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10112 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %} |
|
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10113 ins_encode %{ |
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10114 __ string_indexof($str1$$Register, $str2$$Register, |
|
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10115 $cnt1$$Register, $cnt2$$Register, |
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10116 (-1), $result$$Register, |
|
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10117 $vec$$XMMRegister, $tmp$$Register); |
|
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10118 %} |
| 681 | 10119 ins_pipe( pipe_slow ); |
| 10120 %} | |
| 10121 | |
| 10122 // fast string equals | |
|
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10123 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result, |
|
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10124 regD tmp1, regD tmp2, rbx_RegI tmp3, rFlagsReg cr) |
|
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10125 %{ |
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10126 match(Set result (StrEquals (Binary str1 str2) cnt)); |
|
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10127 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr); |
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10128 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10129 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10130 ins_encode %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10131 __ char_arrays_equals(false, $str1$$Register, $str2$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10132 $cnt$$Register, $result$$Register, $tmp3$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10133 $tmp1$$XMMRegister, $tmp2$$XMMRegister); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10134 %} |
| 0 | 10135 ins_pipe( pipe_slow ); |
| 10136 %} | |
| 10137 | |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
168
diff
changeset
|
10138 // fast array equals |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10139 instruct array_equals(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10140 regD tmp1, regD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr) |
| 681 | 10141 %{ |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
168
diff
changeset
|
10142 match(Set result (AryEq ary1 ary2)); |
| 681 | 10143 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr); |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
168
diff
changeset
|
10144 //ins_cost(300); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
168
diff
changeset
|
10145 |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10146 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10147 ins_encode %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10148 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10149 $tmp3$$Register, $result$$Register, $tmp4$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10150 $tmp1$$XMMRegister, $tmp2$$XMMRegister); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10151 %} |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
168
diff
changeset
|
10152 ins_pipe( pipe_slow ); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
168
diff
changeset
|
10153 %} |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
168
diff
changeset
|
10154 |
|
7637
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10155 // encode char[] to byte[] in ISO_8859_1 |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10156 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len, |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10157 regD tmp1, regD tmp2, regD tmp3, regD tmp4, |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10158 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{ |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10159 match(Set result (EncodeISOArray src (Binary dst len))); |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10160 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr); |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10161 |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10162 format %{ "Encode array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %} |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10163 ins_encode %{ |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10164 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register, |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10165 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister, |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10166 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register); |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10167 %} |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10168 ins_pipe( pipe_slow ); |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10169 %} |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10170 |
|
17726
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10171 //----------Overflow Math Instructions----------------------------------------- |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10172 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10173 instruct overflowAddI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2) |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10174 %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10175 match(Set cr (OverflowAddI op1 op2)); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10176 effect(DEF cr, USE_KILL op1, USE op2); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10177 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10178 format %{ "addl $op1, $op2\t# overflow check int" %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10179 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10180 ins_encode %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10181 __ addl($op1$$Register, $op2$$Register); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10182 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10183 ins_pipe(ialu_reg_reg); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10184 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10185 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10186 instruct overflowAddI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2) |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10187 %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10188 match(Set cr (OverflowAddI op1 op2)); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10189 effect(DEF cr, USE_KILL op1, USE op2); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10190 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10191 format %{ "addl $op1, $op2\t# overflow check int" %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10192 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10193 ins_encode %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10194 __ addl($op1$$Register, $op2$$constant); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10195 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10196 ins_pipe(ialu_reg_reg); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10197 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10198 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10199 instruct overflowAddL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2) |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10200 %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10201 match(Set cr (OverflowAddL op1 op2)); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10202 effect(DEF cr, USE_KILL op1, USE op2); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10203 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10204 format %{ "addq $op1, $op2\t# overflow check long" %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10205 ins_encode %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10206 __ addq($op1$$Register, $op2$$Register); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10207 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10208 ins_pipe(ialu_reg_reg); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10209 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10210 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10211 instruct overflowAddL_rReg_imm(rFlagsReg cr, rax_RegL op1, immL32 op2) |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10212 %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10213 match(Set cr (OverflowAddL op1 op2)); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10214 effect(DEF cr, USE_KILL op1, USE op2); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10215 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10216 format %{ "addq $op1, $op2\t# overflow check long" %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10217 ins_encode %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10218 __ addq($op1$$Register, $op2$$constant); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10219 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10220 ins_pipe(ialu_reg_reg); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10221 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10222 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10223 instruct overflowSubI_rReg(rFlagsReg cr, rRegI op1, rRegI op2) |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10224 %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10225 match(Set cr (OverflowSubI op1 op2)); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10226 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10227 format %{ "cmpl $op1, $op2\t# overflow check int" %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10228 ins_encode %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10229 __ cmpl($op1$$Register, $op2$$Register); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10230 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10231 ins_pipe(ialu_reg_reg); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10232 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10233 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10234 instruct overflowSubI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2) |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10235 %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10236 match(Set cr (OverflowSubI op1 op2)); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10237 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10238 format %{ "cmpl $op1, $op2\t# overflow check int" %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10239 ins_encode %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10240 __ cmpl($op1$$Register, $op2$$constant); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10241 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10242 ins_pipe(ialu_reg_reg); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10243 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10244 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10245 instruct overflowSubL_rReg(rFlagsReg cr, rRegL op1, rRegL op2) |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10246 %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10247 match(Set cr (OverflowSubL op1 op2)); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10248 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10249 format %{ "cmpq $op1, $op2\t# overflow check long" %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10250 ins_encode %{ |
|
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8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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|
10251 __ cmpq($op1$$Register, $op2$$Register); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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diff
changeset
|
10252 %} |
|
085b304a1cc5
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|
10253 ins_pipe(ialu_reg_reg); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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|
10254 %} |
|
085b304a1cc5
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rbackman
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diff
changeset
|
10255 |
|
085b304a1cc5
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rbackman
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|
10256 instruct overflowSubL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2) |
|
085b304a1cc5
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rbackman
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|
10257 %{ |
|
085b304a1cc5
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|
10258 match(Set cr (OverflowSubL op1 op2)); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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|
10259 |
|
085b304a1cc5
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rbackman
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|
10260 format %{ "cmpq $op1, $op2\t# overflow check long" %} |
|
085b304a1cc5
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changeset
|
10261 ins_encode %{ |
|
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|
10262 __ cmpq($op1$$Register, $op2$$constant); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
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parents:
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|
10263 %} |
|
085b304a1cc5
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|
10264 ins_pipe(ialu_reg_reg); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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diff
changeset
|
10265 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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diff
changeset
|
10266 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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diff
changeset
|
10267 instruct overflowNegI_rReg(rFlagsReg cr, immI0 zero, rax_RegI op2) |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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|
10268 %{ |
|
085b304a1cc5
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|
10269 match(Set cr (OverflowSubI zero op2)); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
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changeset
|
10270 effect(DEF cr, USE_KILL op2); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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diff
changeset
|
10271 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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diff
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|
10272 format %{ "negl $op2\t# overflow check int" %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
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diff
changeset
|
10273 ins_encode %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
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diff
changeset
|
10274 __ negl($op2$$Register); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
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diff
changeset
|
10275 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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17714
diff
changeset
|
10276 ins_pipe(ialu_reg_reg); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
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diff
changeset
|
10277 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10278 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10279 instruct overflowNegL_rReg(rFlagsReg cr, immL0 zero, rax_RegL op2) |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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diff
changeset
|
10280 %{ |
|
085b304a1cc5
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rbackman
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diff
changeset
|
10281 match(Set cr (OverflowSubL zero op2)); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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diff
changeset
|
10282 effect(DEF cr, USE_KILL op2); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
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diff
changeset
|
10283 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10284 format %{ "negq $op2\t# overflow check long" %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10285 ins_encode %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10286 __ negq($op2$$Register); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
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diff
changeset
|
10287 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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17714
diff
changeset
|
10288 ins_pipe(ialu_reg_reg); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
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diff
changeset
|
10289 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10290 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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17714
diff
changeset
|
10291 instruct overflowMulI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2) |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
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changeset
|
10292 %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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diff
changeset
|
10293 match(Set cr (OverflowMulI op1 op2)); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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diff
changeset
|
10294 effect(DEF cr, USE_KILL op1, USE op2); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
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diff
changeset
|
10295 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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diff
changeset
|
10296 format %{ "imull $op1, $op2\t# overflow check int" %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
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diff
changeset
|
10297 ins_encode %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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diff
changeset
|
10298 __ imull($op1$$Register, $op2$$Register); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
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diff
changeset
|
10299 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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diff
changeset
|
10300 ins_pipe(ialu_reg_reg_alu0); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10301 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10302 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10303 instruct overflowMulI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2, rRegI tmp) |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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diff
changeset
|
10304 %{ |
|
085b304a1cc5
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rbackman
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17714
diff
changeset
|
10305 match(Set cr (OverflowMulI op1 op2)); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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changeset
|
10306 effect(DEF cr, TEMP tmp, USE op1, USE op2); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
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diff
changeset
|
10307 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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diff
changeset
|
10308 format %{ "imull $tmp, $op1, $op2\t# overflow check int" %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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diff
changeset
|
10309 ins_encode %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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diff
changeset
|
10310 __ imull($tmp$$Register, $op1$$Register, $op2$$constant); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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diff
changeset
|
10311 %} |
|
085b304a1cc5
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rbackman
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diff
changeset
|
10312 ins_pipe(ialu_reg_reg_alu0); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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diff
changeset
|
10313 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10314 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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diff
changeset
|
10315 instruct overflowMulL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2) |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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changeset
|
10316 %{ |
|
085b304a1cc5
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rbackman
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diff
changeset
|
10317 match(Set cr (OverflowMulL op1 op2)); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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changeset
|
10318 effect(DEF cr, USE_KILL op1, USE op2); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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diff
changeset
|
10319 |
|
085b304a1cc5
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rbackman
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diff
changeset
|
10320 format %{ "imulq $op1, $op2\t# overflow check long" %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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diff
changeset
|
10321 ins_encode %{ |
|
085b304a1cc5
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rbackman
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diff
changeset
|
10322 __ imulq($op1$$Register, $op2$$Register); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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diff
changeset
|
10323 %} |
|
085b304a1cc5
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rbackman
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diff
changeset
|
10324 ins_pipe(ialu_reg_reg_alu0); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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diff
changeset
|
10325 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10326 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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diff
changeset
|
10327 instruct overflowMulL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2, rRegL tmp) |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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|
10328 %{ |
|
085b304a1cc5
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rbackman
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diff
changeset
|
10329 match(Set cr (OverflowMulL op1 op2)); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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changeset
|
10330 effect(DEF cr, TEMP tmp, USE op1, USE op2); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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diff
changeset
|
10331 |
|
085b304a1cc5
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rbackman
parents:
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diff
changeset
|
10332 format %{ "imulq $tmp, $op1, $op2\t# overflow check long" %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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diff
changeset
|
10333 ins_encode %{ |
|
085b304a1cc5
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diff
changeset
|
10334 __ imulq($tmp$$Register, $op1$$Register, $op2$$constant); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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changeset
|
10335 %} |
|
085b304a1cc5
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rbackman
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diff
changeset
|
10336 ins_pipe(ialu_reg_reg_alu0); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
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diff
changeset
|
10337 %} |
|
085b304a1cc5
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rbackman
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diff
changeset
|
10338 |
|
7637
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
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7474
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|
10339 |
| 0 | 10340 //----------Control Flow Instructions------------------------------------------ |
| 10341 // Signed compare Instructions | |
| 10342 | |
| 10343 // XXX more variants!! | |
| 10344 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2) | |
| 10345 %{ | |
| 10346 match(Set cr (CmpI op1 op2)); | |
| 10347 effect(DEF cr, USE op1, USE op2); | |
| 10348 | |
| 10349 format %{ "cmpl $op1, $op2" %} | |
| 10350 opcode(0x3B); /* Opcode 3B /r */ | |
| 10351 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2)); | |
| 10352 ins_pipe(ialu_cr_reg_reg); | |
| 10353 %} | |
| 10354 | |
| 10355 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2) | |
| 10356 %{ | |
| 10357 match(Set cr (CmpI op1 op2)); | |
| 10358 | |
| 10359 format %{ "cmpl $op1, $op2" %} | |
| 10360 opcode(0x81, 0x07); /* Opcode 81 /7 */ | |
| 10361 ins_encode(OpcSErm(op1, op2), Con8or32(op2)); | |
| 10362 ins_pipe(ialu_cr_reg_imm); | |
| 10363 %} | |
| 10364 | |
| 10365 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2) | |
| 10366 %{ | |
| 10367 match(Set cr (CmpI op1 (LoadI op2))); | |
| 10368 | |
| 10369 ins_cost(500); // XXX | |
| 10370 format %{ "cmpl $op1, $op2" %} | |
| 10371 opcode(0x3B); /* Opcode 3B /r */ | |
| 10372 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 10373 ins_pipe(ialu_cr_reg_mem); | |
| 10374 %} | |
| 10375 | |
| 10376 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero) | |
| 10377 %{ | |
| 10378 match(Set cr (CmpI src zero)); | |
| 10379 | |
| 10380 format %{ "testl $src, $src" %} | |
| 10381 opcode(0x85); | |
| 10382 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src)); | |
| 10383 ins_pipe(ialu_cr_reg_imm); | |
| 10384 %} | |
| 10385 | |
| 10386 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero) | |
| 10387 %{ | |
| 10388 match(Set cr (CmpI (AndI src con) zero)); | |
| 10389 | |
| 10390 format %{ "testl $src, $con" %} | |
| 10391 opcode(0xF7, 0x00); | |
| 10392 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con)); | |
| 10393 ins_pipe(ialu_cr_reg_imm); | |
| 10394 %} | |
| 10395 | |
| 10396 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero) | |
| 10397 %{ | |
| 10398 match(Set cr (CmpI (AndI src (LoadI mem)) zero)); | |
| 10399 | |
| 10400 format %{ "testl $src, $mem" %} | |
| 10401 opcode(0x85); | |
| 10402 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
| 10403 ins_pipe(ialu_cr_reg_mem); | |
| 10404 %} | |
| 10405 | |
| 10406 // Unsigned compare Instructions; really, same as signed except they | |
| 10407 // produce an rFlagsRegU instead of rFlagsReg. | |
| 10408 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2) | |
| 10409 %{ | |
| 10410 match(Set cr (CmpU op1 op2)); | |
| 10411 | |
| 10412 format %{ "cmpl $op1, $op2\t# unsigned" %} | |
| 10413 opcode(0x3B); /* Opcode 3B /r */ | |
| 10414 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2)); | |
| 10415 ins_pipe(ialu_cr_reg_reg); | |
| 10416 %} | |
| 10417 | |
| 10418 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2) | |
| 10419 %{ | |
| 10420 match(Set cr (CmpU op1 op2)); | |
| 10421 | |
| 10422 format %{ "cmpl $op1, $op2\t# unsigned" %} | |
| 10423 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 10424 ins_encode(OpcSErm(op1, op2), Con8or32(op2)); | |
| 10425 ins_pipe(ialu_cr_reg_imm); | |
| 10426 %} | |
| 10427 | |
| 10428 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2) | |
| 10429 %{ | |
| 10430 match(Set cr (CmpU op1 (LoadI op2))); | |
| 10431 | |
| 10432 ins_cost(500); // XXX | |
| 10433 format %{ "cmpl $op1, $op2\t# unsigned" %} | |
| 10434 opcode(0x3B); /* Opcode 3B /r */ | |
| 10435 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 10436 ins_pipe(ialu_cr_reg_mem); | |
| 10437 %} | |
| 10438 | |
| 10439 // // // Cisc-spilled version of cmpU_rReg | |
| 10440 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2) | |
| 10441 // //%{ | |
| 10442 // // match(Set cr (CmpU (LoadI op1) op2)); | |
| 10443 // // | |
| 10444 // // format %{ "CMPu $op1,$op2" %} | |
| 10445 // // ins_cost(500); | |
| 10446 // // opcode(0x39); /* Opcode 39 /r */ | |
| 10447 // // ins_encode( OpcP, reg_mem( op1, op2) ); | |
| 10448 // //%} | |
| 10449 | |
| 10450 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero) | |
| 10451 %{ | |
| 10452 match(Set cr (CmpU src zero)); | |
| 10453 | |
| 10454 format %{ "testl $src, $src\t# unsigned" %} | |
| 10455 opcode(0x85); | |
| 10456 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src)); | |
| 10457 ins_pipe(ialu_cr_reg_imm); | |
| 10458 %} | |
| 10459 | |
| 10460 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2) | |
| 10461 %{ | |
| 10462 match(Set cr (CmpP op1 op2)); | |
| 10463 | |
| 10464 format %{ "cmpq $op1, $op2\t# ptr" %} | |
| 10465 opcode(0x3B); /* Opcode 3B /r */ | |
| 10466 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2)); | |
| 10467 ins_pipe(ialu_cr_reg_reg); | |
| 10468 %} | |
| 10469 | |
| 10470 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2) | |
| 10471 %{ | |
| 10472 match(Set cr (CmpP op1 (LoadP op2))); | |
| 10473 | |
| 10474 ins_cost(500); // XXX | |
| 10475 format %{ "cmpq $op1, $op2\t# ptr" %} | |
| 10476 opcode(0x3B); /* Opcode 3B /r */ | |
| 10477 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 10478 ins_pipe(ialu_cr_reg_mem); | |
| 10479 %} | |
| 10480 | |
| 10481 // // // Cisc-spilled version of cmpP_rReg | |
| 10482 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2) | |
| 10483 // //%{ | |
| 10484 // // match(Set cr (CmpP (LoadP op1) op2)); | |
| 10485 // // | |
| 10486 // // format %{ "CMPu $op1,$op2" %} | |
| 10487 // // ins_cost(500); | |
| 10488 // // opcode(0x39); /* Opcode 39 /r */ | |
| 10489 // // ins_encode( OpcP, reg_mem( op1, op2) ); | |
| 10490 // //%} | |
| 10491 | |
| 10492 // XXX this is generalized by compP_rReg_mem??? | |
| 10493 // Compare raw pointer (used in out-of-heap check). | |
| 10494 // Only works because non-oop pointers must be raw pointers | |
| 10495 // and raw pointers have no anti-dependencies. | |
| 10496 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2) | |
| 10497 %{ | |
|
6725
da91efe96a93
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|
10498 predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none); |
| 0 | 10499 match(Set cr (CmpP op1 (LoadP op2))); |
| 10500 | |
| 10501 format %{ "cmpq $op1, $op2\t# raw ptr" %} | |
| 10502 opcode(0x3B); /* Opcode 3B /r */ | |
| 10503 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 10504 ins_pipe(ialu_cr_reg_mem); | |
| 10505 %} | |
| 10506 | |
| 10507 // This will generate a signed flags result. This should be OK since | |
| 10508 // any compare to a zero should be eq/neq. | |
| 10509 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero) | |
| 10510 %{ | |
| 10511 match(Set cr (CmpP src zero)); | |
| 10512 | |
| 10513 format %{ "testq $src, $src\t# ptr" %} | |
| 10514 opcode(0x85); | |
| 10515 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src)); | |
| 10516 ins_pipe(ialu_cr_reg_imm); | |
| 10517 %} | |
| 10518 | |
| 10519 // This will generate a signed flags result. This should be OK since | |
| 10520 // any compare to a zero should be eq/neq. | |
|
642
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|
10521 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero) |
|
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|
10522 %{ |
|
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|
10523 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL)); |
| 0 | 10524 match(Set cr (CmpP (LoadP op) zero)); |
| 10525 | |
| 10526 ins_cost(500); // XXX | |
| 10527 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %} | |
| 10528 opcode(0xF7); /* Opcode F7 /0 */ | |
| 10529 ins_encode(REX_mem_wide(op), | |
| 10530 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF)); | |
| 10531 ins_pipe(ialu_cr_reg_imm); | |
| 10532 %} | |
| 10533 | |
|
642
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|
10534 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero) |
|
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|
10535 %{ |
|
6848
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|
10536 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL)); |
|
642
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|
10537 match(Set cr (CmpP (LoadP mem) zero)); |
|
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|
10538 |
|
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|
10539 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %} |
|
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|
10540 ins_encode %{ |
|
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|
10541 __ cmpq(r12, $mem$$Address); |
|
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|
10542 %} |
|
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|
10543 ins_pipe(ialu_cr_reg_mem); |
|
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|
10544 %} |
|
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|
10545 |
|
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|
10546 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2) |
|
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|
10547 %{ |
|
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|
10548 match(Set cr (CmpN op1 op2)); |
|
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|
10549 |
|
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|
10550 format %{ "cmpl $op1, $op2\t# compressed ptr" %} |
|
642
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|
10551 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %} |
|
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|
10552 ins_pipe(ialu_cr_reg_reg); |
|
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|
10553 %} |
|
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|
10554 |
|
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|
10555 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem) |
|
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|
10556 %{ |
|
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|
10557 match(Set cr (CmpN src (LoadN mem))); |
|
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|
10558 |
|
642
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changeset
|
10559 format %{ "cmpl $src, $mem\t# compressed ptr" %} |
|
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changeset
|
10560 ins_encode %{ |
|
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|
10561 __ cmpl($src$$Register, $mem$$Address); |
|
660978a2a31a
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|
10562 %} |
|
660978a2a31a
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diff
changeset
|
10563 ins_pipe(ialu_cr_reg_mem); |
|
660978a2a31a
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kvn
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624
diff
changeset
|
10564 %} |
|
660978a2a31a
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kvn
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624
diff
changeset
|
10565 |
|
660978a2a31a
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kvn
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624
diff
changeset
|
10566 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{ |
|
660978a2a31a
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kvn
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624
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|
10567 match(Set cr (CmpN op1 op2)); |
|
660978a2a31a
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kvn
parents:
624
diff
changeset
|
10568 |
|
660978a2a31a
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kvn
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624
diff
changeset
|
10569 format %{ "cmpl $op1, $op2\t# compressed ptr" %} |
|
164
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163
diff
changeset
|
10570 ins_encode %{ |
|
642
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624
diff
changeset
|
10571 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant); |
|
660978a2a31a
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kvn
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|
10572 %} |
|
660978a2a31a
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624
diff
changeset
|
10573 ins_pipe(ialu_cr_reg_imm); |
|
660978a2a31a
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kvn
parents:
624
diff
changeset
|
10574 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
10575 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
10576 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
10577 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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624
diff
changeset
|
10578 match(Set cr (CmpN src (LoadN mem))); |
|
660978a2a31a
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kvn
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624
diff
changeset
|
10579 |
|
660978a2a31a
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diff
changeset
|
10580 format %{ "cmpl $mem, $src\t# compressed ptr" %} |
|
660978a2a31a
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kvn
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diff
changeset
|
10581 ins_encode %{ |
|
660978a2a31a
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changeset
|
10582 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant); |
|
164
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|
10583 %} |
|
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|
10584 ins_pipe(ialu_cr_reg_mem); |
|
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|
10585 %} |
|
c436414a719e
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163
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changeset
|
10586 |
|
6848
8e47bac5643a
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diff
changeset
|
10587 instruct compN_rReg_imm_klass(rFlagsRegU cr, rRegN op1, immNKlass op2) %{ |
|
8e47bac5643a
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roland
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6795
diff
changeset
|
10588 match(Set cr (CmpN op1 op2)); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
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6795
diff
changeset
|
10589 |
|
8e47bac5643a
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roland
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6795
diff
changeset
|
10590 format %{ "cmpl $op1, $op2\t# compressed klass ptr" %} |
|
8e47bac5643a
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roland
parents:
6795
diff
changeset
|
10591 ins_encode %{ |
|
8e47bac5643a
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6795
diff
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|
10592 __ cmp_narrow_klass($op1$$Register, (Klass*)$op2$$constant); |
|
8e47bac5643a
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roland
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6795
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changeset
|
10593 %} |
|
8e47bac5643a
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diff
changeset
|
10594 ins_pipe(ialu_cr_reg_imm); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
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6795
diff
changeset
|
10595 %} |
|
8e47bac5643a
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6795
diff
changeset
|
10596 |
|
8e47bac5643a
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6795
diff
changeset
|
10597 instruct compN_mem_imm_klass(rFlagsRegU cr, memory mem, immNKlass src) |
|
8e47bac5643a
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roland
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|
10598 %{ |
|
8e47bac5643a
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diff
changeset
|
10599 match(Set cr (CmpN src (LoadNKlass mem))); |
|
8e47bac5643a
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6795
diff
changeset
|
10600 |
|
8e47bac5643a
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changeset
|
10601 format %{ "cmpl $mem, $src\t# compressed klass ptr" %} |
|
8e47bac5643a
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diff
changeset
|
10602 ins_encode %{ |
|
8e47bac5643a
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|
10603 __ cmp_narrow_klass($mem$$Address, (Klass*)$src$$constant); |
|
8e47bac5643a
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changeset
|
10604 %} |
|
8e47bac5643a
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changeset
|
10605 ins_pipe(ialu_cr_reg_mem); |
|
8e47bac5643a
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diff
changeset
|
10606 %} |
|
8e47bac5643a
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changeset
|
10607 |
|
113
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|
10608 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{ |
|
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|
10609 match(Set cr (CmpN src zero)); |
|
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|
10610 |
|
164
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|
10611 format %{ "testl $src, $src\t# compressed ptr" %} |
|
113
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|
10612 ins_encode %{ __ testl($src$$Register, $src$$Register); %} |
|
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|
10613 ins_pipe(ialu_cr_reg_imm); |
|
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|
10614 %} |
|
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|
10615 |
|
642
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changeset
|
10616 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero) |
|
660978a2a31a
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changeset
|
10617 %{ |
|
660978a2a31a
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changeset
|
10618 predicate(Universe::narrow_oop_base() != NULL); |
|
164
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|
10619 match(Set cr (CmpN (LoadN mem) zero)); |
|
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|
10620 |
|
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|
10621 ins_cost(500); // XXX |
|
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|
10622 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %} |
|
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changeset
|
10623 ins_encode %{ |
|
642
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changeset
|
10624 __ cmpl($mem$$Address, (int)0xFFFFFFFF); |
|
660978a2a31a
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changeset
|
10625 %} |
|
660978a2a31a
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changeset
|
10626 ins_pipe(ialu_cr_reg_mem); |
|
660978a2a31a
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changeset
|
10627 %} |
|
660978a2a31a
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changeset
|
10628 |
|
660978a2a31a
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|
10629 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero) |
|
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|
10630 %{ |
|
6848
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|
10631 predicate(Universe::narrow_oop_base() == NULL && (Universe::narrow_klass_base() == NULL)); |
|
642
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|
10632 match(Set cr (CmpN (LoadN mem) zero)); |
|
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|
10633 |
|
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|
10634 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %} |
|
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|
10635 ins_encode %{ |
|
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|
10636 __ cmpl(r12, $mem$$Address); |
|
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|
10637 %} |
|
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|
10638 ins_pipe(ialu_cr_reg_mem); |
|
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10639 %} |
|
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|
10640 |
| 0 | 10641 // Yanked all unsigned pointer compare operations. |
| 10642 // Pointer compares are done with CmpP which is already unsigned. | |
| 10643 | |
| 10644 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2) | |
| 10645 %{ | |
| 10646 match(Set cr (CmpL op1 op2)); | |
| 10647 | |
| 10648 format %{ "cmpq $op1, $op2" %} | |
| 10649 opcode(0x3B); /* Opcode 3B /r */ | |
| 10650 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2)); | |
| 10651 ins_pipe(ialu_cr_reg_reg); | |
| 10652 %} | |
| 10653 | |
| 10654 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2) | |
| 10655 %{ | |
| 10656 match(Set cr (CmpL op1 op2)); | |
| 10657 | |
| 10658 format %{ "cmpq $op1, $op2" %} | |
| 10659 opcode(0x81, 0x07); /* Opcode 81 /7 */ | |
| 10660 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2)); | |
| 10661 ins_pipe(ialu_cr_reg_imm); | |
| 10662 %} | |
| 10663 | |
| 10664 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2) | |
| 10665 %{ | |
| 10666 match(Set cr (CmpL op1 (LoadL op2))); | |
| 10667 | |
| 10668 format %{ "cmpq $op1, $op2" %} | |
| 10669 opcode(0x3B); /* Opcode 3B /r */ | |
| 10670 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 10671 ins_pipe(ialu_cr_reg_mem); | |
| 10672 %} | |
| 10673 | |
| 10674 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero) | |
| 10675 %{ | |
| 10676 match(Set cr (CmpL src zero)); | |
| 10677 | |
| 10678 format %{ "testq $src, $src" %} | |
| 10679 opcode(0x85); | |
| 10680 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src)); | |
| 10681 ins_pipe(ialu_cr_reg_imm); | |
| 10682 %} | |
| 10683 | |
| 10684 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero) | |
| 10685 %{ | |
| 10686 match(Set cr (CmpL (AndL src con) zero)); | |
| 10687 | |
| 10688 format %{ "testq $src, $con\t# long" %} | |
| 10689 opcode(0xF7, 0x00); | |
| 10690 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con)); | |
| 10691 ins_pipe(ialu_cr_reg_imm); | |
| 10692 %} | |
| 10693 | |
| 10694 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero) | |
| 10695 %{ | |
| 10696 match(Set cr (CmpL (AndL src (LoadL mem)) zero)); | |
| 10697 | |
| 10698 format %{ "testq $src, $mem" %} | |
| 10699 opcode(0x85); | |
| 10700 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem)); | |
| 10701 ins_pipe(ialu_cr_reg_mem); | |
| 10702 %} | |
| 10703 | |
| 10704 // Manifest a CmpL result in an integer register. Very painful. | |
| 10705 // This is the test to avoid. | |
| 10706 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags) | |
| 10707 %{ | |
| 10708 match(Set dst (CmpL3 src1 src2)); | |
| 10709 effect(KILL flags); | |
| 10710 | |
| 10711 ins_cost(275); // XXX | |
| 10712 format %{ "cmpq $src1, $src2\t# CmpL3\n\t" | |
| 10713 "movl $dst, -1\n\t" | |
| 10714 "jl,s done\n\t" | |
| 10715 "setne $dst\n\t" | |
| 10716 "movzbl $dst, $dst\n\t" | |
| 10717 "done:" %} | |
| 10718 ins_encode(cmpl3_flag(src1, src2, dst)); | |
| 10719 ins_pipe(pipe_slow); | |
| 10720 %} | |
| 10721 | |
| 10722 //----------Max and Min-------------------------------------------------------- | |
| 10723 // Min Instructions | |
| 10724 | |
| 10725 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr) | |
| 10726 %{ | |
| 10727 effect(USE_DEF dst, USE src, USE cr); | |
| 10728 | |
| 10729 format %{ "cmovlgt $dst, $src\t# min" %} | |
| 10730 opcode(0x0F, 0x4F); | |
| 10731 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 10732 ins_pipe(pipe_cmov_reg); | |
| 10733 %} | |
| 10734 | |
| 10735 | |
| 10736 instruct minI_rReg(rRegI dst, rRegI src) | |
| 10737 %{ | |
| 10738 match(Set dst (MinI dst src)); | |
| 10739 | |
| 10740 ins_cost(200); | |
| 10741 expand %{ | |
| 10742 rFlagsReg cr; | |
| 10743 compI_rReg(cr, dst, src); | |
| 10744 cmovI_reg_g(dst, src, cr); | |
| 10745 %} | |
| 10746 %} | |
| 10747 | |
| 10748 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr) | |
| 10749 %{ | |
| 10750 effect(USE_DEF dst, USE src, USE cr); | |
| 10751 | |
| 10752 format %{ "cmovllt $dst, $src\t# max" %} | |
| 10753 opcode(0x0F, 0x4C); | |
| 10754 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 10755 ins_pipe(pipe_cmov_reg); | |
| 10756 %} | |
| 10757 | |
| 10758 | |
| 10759 instruct maxI_rReg(rRegI dst, rRegI src) | |
| 10760 %{ | |
| 10761 match(Set dst (MaxI dst src)); | |
| 10762 | |
| 10763 ins_cost(200); | |
| 10764 expand %{ | |
| 10765 rFlagsReg cr; | |
| 10766 compI_rReg(cr, dst, src); | |
| 10767 cmovI_reg_l(dst, src, cr); | |
| 10768 %} | |
| 10769 %} | |
| 10770 | |
| 10771 // ============================================================================ | |
| 10772 // Branch Instructions | |
| 10773 | |
| 10774 // Jump Direct - Label defines a relative address from JMP+1 | |
| 10775 instruct jmpDir(label labl) | |
| 10776 %{ | |
| 10777 match(Goto); | |
| 10778 effect(USE labl); | |
| 10779 | |
| 10780 ins_cost(300); | |
| 10781 format %{ "jmp $labl" %} | |
| 10782 size(5); | |
| 3851 | 10783 ins_encode %{ |
| 10784 Label* L = $labl$$label; | |
| 10785 __ jmp(*L, false); // Always long jump | |
| 10786 %} | |
| 0 | 10787 ins_pipe(pipe_jmp); |
| 10788 %} | |
| 10789 | |
| 10790 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 10791 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl) | |
| 10792 %{ | |
| 10793 match(If cop cr); | |
| 10794 effect(USE labl); | |
| 10795 | |
| 10796 ins_cost(300); | |
| 10797 format %{ "j$cop $labl" %} | |
| 10798 size(6); | |
| 3851 | 10799 ins_encode %{ |
| 10800 Label* L = $labl$$label; | |
| 10801 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 10802 %} | |
| 0 | 10803 ins_pipe(pipe_jcc); |
| 10804 %} | |
| 10805 | |
| 10806 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 10807 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl) | |
| 10808 %{ | |
| 10809 match(CountedLoopEnd cop cr); | |
| 10810 effect(USE labl); | |
| 10811 | |
| 10812 ins_cost(300); | |
| 10813 format %{ "j$cop $labl\t# loop end" %} | |
| 10814 size(6); | |
| 3851 | 10815 ins_encode %{ |
| 10816 Label* L = $labl$$label; | |
| 10817 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 10818 %} | |
| 0 | 10819 ins_pipe(pipe_jcc); |
| 10820 %} | |
| 10821 | |
| 10822 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
|
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10823 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
| 0 | 10824 match(CountedLoopEnd cop cmp); |
| 10825 effect(USE labl); | |
| 10826 | |
| 10827 ins_cost(300); | |
| 10828 format %{ "j$cop,u $labl\t# loop end" %} | |
| 10829 size(6); | |
| 3851 | 10830 ins_encode %{ |
| 10831 Label* L = $labl$$label; | |
| 10832 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 10833 %} | |
| 0 | 10834 ins_pipe(pipe_jcc); |
| 10835 %} | |
| 10836 | |
|
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|
10837 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
|
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|
10838 match(CountedLoopEnd cop cmp); |
|
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|
10839 effect(USE labl); |
|
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|
10840 |
|
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|
10841 ins_cost(200); |
|
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|
10842 format %{ "j$cop,u $labl\t# loop end" %} |
|
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|
10843 size(6); |
| 3851 | 10844 ins_encode %{ |
| 10845 Label* L = $labl$$label; | |
| 10846 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 10847 %} | |
|
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|
10848 ins_pipe(pipe_jcc); |
|
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|
10849 %} |
|
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|
10850 |
| 0 | 10851 // Jump Direct Conditional - using unsigned comparison |
|
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|
10852 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
| 0 | 10853 match(If cop cmp); |
| 10854 effect(USE labl); | |
| 10855 | |
| 10856 ins_cost(300); | |
|
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|
10857 format %{ "j$cop,u $labl" %} |
|
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|
10858 size(6); |
| 3851 | 10859 ins_encode %{ |
| 10860 Label* L = $labl$$label; | |
| 10861 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 10862 %} | |
|
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|
10863 ins_pipe(pipe_jcc); |
|
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|
10864 %} |
|
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changeset
|
10865 |
|
4d9884b01ba6
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changeset
|
10866 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
|
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|
10867 match(If cop cmp); |
|
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changeset
|
10868 effect(USE labl); |
|
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diff
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|
10869 |
|
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|
10870 ins_cost(200); |
|
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|
10871 format %{ "j$cop,u $labl" %} |
| 0 | 10872 size(6); |
| 3851 | 10873 ins_encode %{ |
| 10874 Label* L = $labl$$label; | |
| 10875 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 10876 %} | |
| 0 | 10877 ins_pipe(pipe_jcc); |
| 10878 %} | |
| 10879 | |
|
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|
10880 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{ |
|
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|
10881 match(If cop cmp); |
|
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|
10882 effect(USE labl); |
|
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diff
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|
10883 |
|
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|
10884 ins_cost(200); |
|
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|
10885 format %{ $$template |
|
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|
10886 if ($cop$$cmpcode == Assembler::notEqual) { |
|
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|
10887 $$emit$$"jp,u $labl\n\t" |
|
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|
10888 $$emit$$"j$cop,u $labl" |
|
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|
10889 } else { |
|
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|
10890 $$emit$$"jp,u done\n\t" |
|
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|
10891 $$emit$$"j$cop,u $labl\n\t" |
|
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|
10892 $$emit$$"done:" |
|
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|
10893 } |
|
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|
10894 %} |
|
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|
10895 ins_encode %{ |
|
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|
10896 Label* l = $labl$$label; |
|
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|
10897 if ($cop$$cmpcode == Assembler::notEqual) { |
| 3851 | 10898 __ jcc(Assembler::parity, *l, false); |
| 10899 __ jcc(Assembler::notEqual, *l, false); | |
|
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10900 } else if ($cop$$cmpcode == Assembler::equal) { |
| 3851 | 10901 Label done; |
| 10902 __ jccb(Assembler::parity, done); | |
| 10903 __ jcc(Assembler::equal, *l, false); | |
| 10904 __ bind(done); | |
|
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|
10905 } else { |
|
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|
10906 ShouldNotReachHere(); |
|
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|
10907 } |
|
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|
10908 %} |
|
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|
10909 ins_pipe(pipe_jcc); |
|
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|
10910 %} |
|
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|
10911 |
| 0 | 10912 // ============================================================================ |
| 10913 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary | |
| 10914 // superklass array for an instance of the superklass. Set a hidden | |
| 10915 // internal cache on a hit (cache is checked with exposed code in | |
| 10916 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The | |
| 10917 // encoding ALSO sets flags. | |
| 10918 | |
| 10919 instruct partialSubtypeCheck(rdi_RegP result, | |
| 10920 rsi_RegP sub, rax_RegP super, rcx_RegI rcx, | |
| 10921 rFlagsReg cr) | |
| 10922 %{ | |
| 10923 match(Set result (PartialSubtypeCheck sub super)); | |
| 10924 effect(KILL rcx, KILL cr); | |
| 10925 | |
| 10926 ins_cost(1100); // slightly larger than the next version | |
|
4762
069ab3f976d3
7118863: Move sizeof(klassOopDesc) into the *Klass::*_offset_in_bytes() functions
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parents:
4761
diff
changeset
|
10927 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t" |
|
6725
da91efe96a93
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parents:
6614
diff
changeset
|
10928 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t" |
|
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10929 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t" |
| 0 | 10930 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t" |
| 10931 "jne,s miss\t\t# Missed: rdi not-zero\n\t" | |
|
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|
10932 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t" |
| 0 | 10933 "xorq $result, $result\t\t Hit: rdi zero\n\t" |
| 10934 "miss:\t" %} | |
| 10935 | |
| 10936 opcode(0x1); // Force a XOR of RDI | |
| 10937 ins_encode(enc_PartialSubtypeCheck()); | |
| 10938 ins_pipe(pipe_slow); | |
| 10939 %} | |
| 10940 | |
| 10941 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr, | |
| 10942 rsi_RegP sub, rax_RegP super, rcx_RegI rcx, | |
| 10943 immP0 zero, | |
| 10944 rdi_RegP result) | |
| 10945 %{ | |
| 10946 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero)); | |
| 10947 effect(KILL rcx, KILL result); | |
| 10948 | |
| 10949 ins_cost(1000); | |
|
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|
10950 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t" |
|
6725
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10951 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t" |
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10952 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t" |
| 0 | 10953 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t" |
| 10954 "jne,s miss\t\t# Missed: flags nz\n\t" | |
|
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|
10955 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t" |
| 0 | 10956 "miss:\t" %} |
| 10957 | |
| 10958 opcode(0x0); // No need to XOR RDI | |
| 10959 ins_encode(enc_PartialSubtypeCheck()); | |
| 10960 ins_pipe(pipe_slow); | |
| 10961 %} | |
| 10962 | |
| 10963 // ============================================================================ | |
| 10964 // Branch Instructions -- short offset versions | |
| 10965 // | |
| 10966 // These instructions are used to replace jumps of a long offset (the default | |
| 10967 // match) with jumps of a shorter offset. These instructions are all tagged | |
| 10968 // with the ins_short_branch attribute, which causes the ADLC to suppress the | |
| 10969 // match rules in general matching. Instead, the ADLC generates a conversion | |
| 10970 // method in the MachNode which can be used to do in-place replacement of the | |
| 10971 // long variant with the shorter variant. The compiler will determine if a | |
| 10972 // branch can be taken by the is_short_branch_offset() predicate in the machine | |
| 10973 // specific code section of the file. | |
| 10974 | |
| 10975 // Jump Direct - Label defines a relative address from JMP+1 | |
|
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|
10976 instruct jmpDir_short(label labl) %{ |
| 0 | 10977 match(Goto); |
| 10978 effect(USE labl); | |
| 10979 | |
| 10980 ins_cost(300); | |
| 10981 format %{ "jmp,s $labl" %} | |
| 10982 size(2); | |
| 3851 | 10983 ins_encode %{ |
| 10984 Label* L = $labl$$label; | |
| 10985 __ jmpb(*L); | |
| 10986 %} | |
| 0 | 10987 ins_pipe(pipe_jmp); |
| 10988 ins_short_branch(1); | |
| 10989 %} | |
| 10990 | |
| 10991 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
|
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|
10992 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{ |
| 0 | 10993 match(If cop cr); |
| 10994 effect(USE labl); | |
| 10995 | |
| 10996 ins_cost(300); | |
| 10997 format %{ "j$cop,s $labl" %} | |
| 10998 size(2); | |
| 3851 | 10999 ins_encode %{ |
| 11000 Label* L = $labl$$label; | |
| 11001 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11002 %} | |
| 0 | 11003 ins_pipe(pipe_jcc); |
| 11004 ins_short_branch(1); | |
| 11005 %} | |
| 11006 | |
| 11007 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
|
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11008 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{ |
| 0 | 11009 match(CountedLoopEnd cop cr); |
| 11010 effect(USE labl); | |
| 11011 | |
| 11012 ins_cost(300); | |
|
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|
11013 format %{ "j$cop,s $labl\t# loop end" %} |
| 0 | 11014 size(2); |
| 3851 | 11015 ins_encode %{ |
| 11016 Label* L = $labl$$label; | |
| 11017 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11018 %} | |
| 0 | 11019 ins_pipe(pipe_jcc); |
| 11020 ins_short_branch(1); | |
| 11021 %} | |
| 11022 | |
| 11023 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
|
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|
11024 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
|
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11025 match(CountedLoopEnd cop cmp); |
|
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|
11026 effect(USE labl); |
|
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|
11027 |
|
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|
11028 ins_cost(300); |
|
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|
11029 format %{ "j$cop,us $labl\t# loop end" %} |
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11030 size(2); |
| 3851 | 11031 ins_encode %{ |
| 11032 Label* L = $labl$$label; | |
| 11033 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11034 %} | |
|
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|
11035 ins_pipe(pipe_jcc); |
|
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|
11036 ins_short_branch(1); |
|
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|
11037 %} |
|
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|
11038 |
|
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|
11039 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
| 0 | 11040 match(CountedLoopEnd cop cmp); |
| 11041 effect(USE labl); | |
| 11042 | |
| 11043 ins_cost(300); | |
|
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|
11044 format %{ "j$cop,us $labl\t# loop end" %} |
|
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|
11045 size(2); |
| 3851 | 11046 ins_encode %{ |
| 11047 Label* L = $labl$$label; | |
| 11048 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11049 %} | |
|
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|
11050 ins_pipe(pipe_jcc); |
|
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|
11051 ins_short_branch(1); |
|
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|
11052 %} |
|
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|
11053 |
|
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|
11054 // Jump Direct Conditional - using unsigned comparison |
|
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|
11055 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
|
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|
11056 match(If cop cmp); |
|
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|
11057 effect(USE labl); |
|
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|
11058 |
|
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|
11059 ins_cost(300); |
| 0 | 11060 format %{ "j$cop,us $labl" %} |
| 11061 size(2); | |
| 3851 | 11062 ins_encode %{ |
| 11063 Label* L = $labl$$label; | |
| 11064 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11065 %} | |
| 0 | 11066 ins_pipe(pipe_jcc); |
| 11067 ins_short_branch(1); | |
| 11068 %} | |
| 11069 | |
|
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|
11070 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
| 0 | 11071 match(If cop cmp); |
| 11072 effect(USE labl); | |
| 11073 | |
| 11074 ins_cost(300); | |
| 11075 format %{ "j$cop,us $labl" %} | |
| 11076 size(2); | |
| 3851 | 11077 ins_encode %{ |
| 11078 Label* L = $labl$$label; | |
| 11079 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11080 %} | |
| 0 | 11081 ins_pipe(pipe_jcc); |
| 11082 ins_short_branch(1); | |
| 11083 %} | |
| 11084 | |
|
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|
11085 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{ |
|
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|
11086 match(If cop cmp); |
|
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|
11087 effect(USE labl); |
|
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|
11088 |
|
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|
11089 ins_cost(300); |
|
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|
11090 format %{ $$template |
|
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|
11091 if ($cop$$cmpcode == Assembler::notEqual) { |
|
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|
11092 $$emit$$"jp,u,s $labl\n\t" |
|
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|
11093 $$emit$$"j$cop,u,s $labl" |
|
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|
11094 } else { |
|
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|
11095 $$emit$$"jp,u,s done\n\t" |
|
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|
11096 $$emit$$"j$cop,u,s $labl\n\t" |
|
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|
11097 $$emit$$"done:" |
|
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|
11098 } |
|
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|
11099 %} |
|
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|
11100 size(4); |
|
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|
11101 ins_encode %{ |
|
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|
11102 Label* l = $labl$$label; |
|
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|
11103 if ($cop$$cmpcode == Assembler::notEqual) { |
| 3851 | 11104 __ jccb(Assembler::parity, *l); |
| 11105 __ jccb(Assembler::notEqual, *l); | |
|
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|
11106 } else if ($cop$$cmpcode == Assembler::equal) { |
| 3851 | 11107 Label done; |
| 11108 __ jccb(Assembler::parity, done); | |
| 11109 __ jccb(Assembler::equal, *l); | |
| 11110 __ bind(done); | |
|
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|
11111 } else { |
| 3851 | 11112 ShouldNotReachHere(); |
| 11113 } | |
|
415
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|
11114 %} |
|
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|
11115 ins_pipe(pipe_jcc); |
|
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|
11116 ins_short_branch(1); |
|
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|
11117 %} |
|
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|
11118 |
| 0 | 11119 // ============================================================================ |
| 11120 // inlined locking and unlocking | |
| 11121 | |
|
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|
11122 instruct cmpFastLock(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr) %{ |
| 0 | 11123 match(Set cr (FastLock object box)); |
| 4777 | 11124 effect(TEMP tmp, TEMP scr, USE_KILL box); |
| 0 | 11125 ins_cost(300); |
| 4777 | 11126 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %} |
|
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|
11127 ins_encode %{ |
|
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|
11128 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register, $scr$$Register, _counters); |
|
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|
11129 %} |
| 0 | 11130 ins_pipe(pipe_slow); |
| 11131 %} | |
| 11132 | |
|
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|
11133 instruct cmpFastUnlock(rFlagsReg cr, rRegP object, rax_RegP box, rRegP tmp) %{ |
| 0 | 11134 match(Set cr (FastUnlock object box)); |
| 4777 | 11135 effect(TEMP tmp, USE_KILL box); |
| 0 | 11136 ins_cost(300); |
| 4777 | 11137 format %{ "fastunlock $object,$box\t! kills $box,$tmp" %} |
|
17714
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|
11138 ins_encode %{ |
|
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|
11139 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register); |
|
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|
11140 %} |
| 0 | 11141 ins_pipe(pipe_slow); |
| 11142 %} | |
| 11143 | |
| 11144 | |
| 11145 // ============================================================================ | |
| 11146 // Safepoint Instructions | |
| 11147 instruct safePoint_poll(rFlagsReg cr) | |
| 11148 %{ | |
|
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|
11149 predicate(!Assembler::is_polling_page_far()); |
| 0 | 11150 match(SafePoint); |
| 11151 effect(KILL cr); | |
| 11152 | |
|
2404
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|
11153 format %{ "testl rax, [rip + #offset_to_poll_page]\t" |
| 0 | 11154 "# Safepoint: poll for GC" %} |
| 11155 ins_cost(125); | |
|
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|
11156 ins_encode %{ |
|
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|
11157 AddressLiteral addr(os::get_polling_page(), relocInfo::poll_type); |
|
b40d4fa697bf
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iveresov
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|
11158 __ testl(rax, addr); |
|
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|
11159 %} |
|
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|
11160 ins_pipe(ialu_reg_mem); |
|
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|
11161 %} |
|
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|
11162 |
|
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11163 instruct safePoint_poll_far(rFlagsReg cr, rRegP poll) |
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11164 %{ |
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11165 predicate(Assembler::is_polling_page_far()); |
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11166 match(SafePoint poll); |
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11167 effect(KILL cr, USE poll); |
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11168 |
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11169 format %{ "testl rax, [$poll]\t" |
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11170 "# Safepoint: poll for GC" %} |
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11171 ins_cost(125); |
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11172 ins_encode %{ |
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11173 __ relocate(relocInfo::poll_type); |
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11174 __ testl(rax, Address($poll$$Register, 0)); |
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11175 %} |
| 0 | 11176 ins_pipe(ialu_reg_mem); |
| 11177 %} | |
| 11178 | |
| 11179 // ============================================================================ | |
| 11180 // Procedure Call/Return Instructions | |
| 11181 // Call Java Static Instruction | |
| 11182 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 11183 // compute_padding() functions will have to be adjusted. | |
|
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11184 instruct CallStaticJavaDirect(method meth) %{ |
| 0 | 11185 match(CallStaticJava); |
|
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11186 predicate(!((CallStaticJavaNode*) n)->is_method_handle_invoke()); |
| 0 | 11187 effect(USE meth); |
| 11188 | |
| 11189 ins_cost(300); | |
| 11190 format %{ "call,static " %} | |
| 11191 opcode(0xE8); /* E8 cd */ | |
|
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11192 ins_encode(clear_avx, Java_Static_Call(meth), call_epilog); |
| 0 | 11193 ins_pipe(pipe_slow); |
| 11194 ins_alignment(4); | |
| 11195 %} | |
| 11196 | |
|
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11197 // Call Java Static Instruction (method handle version) |
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11198 // Note: If this code changes, the corresponding ret_addr_offset() and |
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11199 // compute_padding() functions will have to be adjusted. |
| 1567 | 11200 instruct CallStaticJavaHandle(method meth, rbp_RegP rbp_mh_SP_save) %{ |
|
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11201 match(CallStaticJava); |
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11202 predicate(((CallStaticJavaNode*) n)->is_method_handle_invoke()); |
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11203 effect(USE meth); |
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11204 // RBP is saved by all callees (for interpreter stack correction). |
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11205 // We use it here for a similar purpose, in {preserve,restore}_SP. |
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11206 |
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11207 ins_cost(300); |
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11208 format %{ "call,static/MethodHandle " %} |
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11209 opcode(0xE8); /* E8 cd */ |
|
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11210 ins_encode(clear_avx, preserve_SP, |
|
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11211 Java_Static_Call(meth), |
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11212 restore_SP, |
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11213 call_epilog); |
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11214 ins_pipe(pipe_slow); |
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11215 ins_alignment(4); |
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11216 %} |
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11217 |
| 0 | 11218 // Call Java Dynamic Instruction |
| 11219 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 11220 // compute_padding() functions will have to be adjusted. | |
| 11221 instruct CallDynamicJavaDirect(method meth) | |
| 11222 %{ | |
| 11223 match(CallDynamicJava); | |
| 11224 effect(USE meth); | |
| 11225 | |
| 11226 ins_cost(300); | |
| 11227 format %{ "movq rax, #Universe::non_oop_word()\n\t" | |
| 11228 "call,dynamic " %} | |
|
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11229 ins_encode(clear_avx, Java_Dynamic_Call(meth), call_epilog); |
| 0 | 11230 ins_pipe(pipe_slow); |
| 11231 ins_alignment(4); | |
| 11232 %} | |
| 11233 | |
| 11234 // Call Runtime Instruction | |
| 11235 instruct CallRuntimeDirect(method meth) | |
| 11236 %{ | |
| 11237 match(CallRuntime); | |
| 11238 effect(USE meth); | |
| 11239 | |
| 11240 ins_cost(300); | |
| 11241 format %{ "call,runtime " %} | |
|
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11242 ins_encode(clear_avx, Java_To_Runtime(meth)); |
| 0 | 11243 ins_pipe(pipe_slow); |
| 11244 %} | |
| 11245 | |
| 11246 // Call runtime without safepoint | |
| 11247 instruct CallLeafDirect(method meth) | |
| 11248 %{ | |
| 11249 match(CallLeaf); | |
| 11250 effect(USE meth); | |
| 11251 | |
| 11252 ins_cost(300); | |
| 11253 format %{ "call_leaf,runtime " %} | |
|
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11254 ins_encode(clear_avx, Java_To_Runtime(meth)); |
| 0 | 11255 ins_pipe(pipe_slow); |
| 11256 %} | |
| 11257 | |
| 11258 // Call runtime without safepoint | |
| 11259 instruct CallLeafNoFPDirect(method meth) | |
| 11260 %{ | |
| 11261 match(CallLeafNoFP); | |
| 11262 effect(USE meth); | |
| 11263 | |
| 11264 ins_cost(300); | |
| 11265 format %{ "call_leaf_nofp,runtime " %} | |
| 11266 ins_encode(Java_To_Runtime(meth)); | |
| 11267 ins_pipe(pipe_slow); | |
| 11268 %} | |
| 11269 | |
| 11270 // Return Instruction | |
| 11271 // Remove the return address & jump to it. | |
| 11272 // Notice: We always emit a nop after a ret to make sure there is room | |
| 11273 // for safepoint patching | |
| 11274 instruct Ret() | |
| 11275 %{ | |
| 11276 match(Return); | |
| 11277 | |
| 11278 format %{ "ret" %} | |
| 11279 opcode(0xC3); | |
| 11280 ins_encode(OpcP); | |
| 11281 ins_pipe(pipe_jmp); | |
| 11282 %} | |
| 11283 | |
| 11284 // Tail Call; Jump from runtime stub to Java code. | |
| 11285 // Also known as an 'interprocedural jump'. | |
| 11286 // Target of jump will eventually return to caller. | |
| 11287 // TailJump below removes the return address. | |
| 11288 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop) | |
| 11289 %{ | |
| 11290 match(TailCall jump_target method_oop); | |
| 11291 | |
| 11292 ins_cost(300); | |
| 11293 format %{ "jmp $jump_target\t# rbx holds method oop" %} | |
| 11294 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 11295 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target)); | |
| 11296 ins_pipe(pipe_jmp); | |
| 11297 %} | |
| 11298 | |
| 11299 // Tail Jump; remove the return address; jump to target. | |
| 11300 // TailCall above leaves the return address around. | |
| 11301 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop) | |
| 11302 %{ | |
| 11303 match(TailJump jump_target ex_oop); | |
| 11304 | |
| 11305 ins_cost(300); | |
| 11306 format %{ "popq rdx\t# pop return address\n\t" | |
| 11307 "jmp $jump_target" %} | |
| 11308 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 11309 ins_encode(Opcode(0x5a), // popq rdx | |
| 11310 REX_reg(jump_target), OpcP, reg_opc(jump_target)); | |
| 11311 ins_pipe(pipe_jmp); | |
| 11312 %} | |
| 11313 | |
| 11314 // Create exception oop: created by stack-crawling runtime code. | |
| 11315 // Created exception is now available to this handler, and is setup | |
| 11316 // just prior to jumping to this handler. No code emitted. | |
| 11317 instruct CreateException(rax_RegP ex_oop) | |
| 11318 %{ | |
| 11319 match(Set ex_oop (CreateEx)); | |
| 11320 | |
| 11321 size(0); | |
| 11322 // use the following format syntax | |
| 11323 format %{ "# exception oop is in rax; no code emitted" %} | |
| 11324 ins_encode(); | |
| 11325 ins_pipe(empty); | |
| 11326 %} | |
| 11327 | |
| 11328 // Rethrow exception: | |
| 11329 // The exception oop will come in the first argument position. | |
| 11330 // Then JUMP (not call) to the rethrow stub code. | |
| 11331 instruct RethrowException() | |
| 11332 %{ | |
| 11333 match(Rethrow); | |
| 11334 | |
| 11335 // use the following format syntax | |
| 11336 format %{ "jmp rethrow_stub" %} | |
| 11337 ins_encode(enc_rethrow); | |
| 11338 ins_pipe(pipe_jmp); | |
| 11339 %} | |
| 11340 | |
| 11341 | |
| 4950 | 11342 // ============================================================================ |
| 11343 // This name is KNOWN by the ADLC and cannot be changed. | |
| 11344 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type | |
| 11345 // for this guy. | |
| 11346 instruct tlsLoadP(r15_RegP dst) %{ | |
| 11347 match(Set dst (ThreadLocal)); | |
| 11348 effect(DEF dst); | |
| 11349 | |
| 11350 size(0); | |
| 11351 format %{ "# TLS is in R15" %} | |
| 11352 ins_encode( /*empty encoding*/ ); | |
| 11353 ins_pipe(ialu_reg_reg); | |
| 11354 %} | |
| 11355 | |
| 11356 | |
| 0 | 11357 //----------PEEPHOLE RULES----------------------------------------------------- |
| 11358 // These must follow all instruction definitions as they use the names | |
| 11359 // defined in the instructions definitions. | |
| 11360 // | |
| 605 | 11361 // peepmatch ( root_instr_name [preceding_instruction]* ); |
| 0 | 11362 // |
| 11363 // peepconstraint %{ | |
| 11364 // (instruction_number.operand_name relational_op instruction_number.operand_name | |
| 11365 // [, ...] ); | |
| 11366 // // instruction numbers are zero-based using left to right order in peepmatch | |
| 11367 // | |
| 11368 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); | |
| 11369 // // provide an instruction_number.operand_name for each operand that appears | |
| 11370 // // in the replacement instruction's match rule | |
| 11371 // | |
| 11372 // ---------VM FLAGS--------------------------------------------------------- | |
| 11373 // | |
| 11374 // All peephole optimizations can be turned off using -XX:-OptoPeephole | |
| 11375 // | |
| 11376 // Each peephole rule is given an identifying number starting with zero and | |
| 11377 // increasing by one in the order seen by the parser. An individual peephole | |
| 11378 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# | |
| 11379 // on the command-line. | |
| 11380 // | |
| 11381 // ---------CURRENT LIMITATIONS---------------------------------------------- | |
| 11382 // | |
| 11383 // Only match adjacent instructions in same basic block | |
| 11384 // Only equality constraints | |
| 11385 // Only constraints between operands, not (0.dest_reg == RAX_enc) | |
| 11386 // Only one replacement instruction | |
| 11387 // | |
| 11388 // ---------EXAMPLE---------------------------------------------------------- | |
| 11389 // | |
| 11390 // // pertinent parts of existing instructions in architecture description | |
| 11391 // instruct movI(rRegI dst, rRegI src) | |
| 11392 // %{ | |
| 11393 // match(Set dst (CopyI src)); | |
| 11394 // %} | |
| 11395 // | |
| 11396 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr) | |
| 11397 // %{ | |
| 11398 // match(Set dst (AddI dst src)); | |
| 11399 // effect(KILL cr); | |
| 11400 // %} | |
| 11401 // | |
| 11402 // // Change (inc mov) to lea | |
| 11403 // peephole %{ | |
| 11404 // // increment preceeded by register-register move | |
| 11405 // peepmatch ( incI_rReg movI ); | |
| 11406 // // require that the destination register of the increment | |
| 11407 // // match the destination register of the move | |
| 11408 // peepconstraint ( 0.dst == 1.dst ); | |
| 11409 // // construct a replacement instruction that sets | |
| 11410 // // the destination to ( move's source register + one ) | |
| 11411 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) ); | |
| 11412 // %} | |
| 11413 // | |
| 11414 | |
| 11415 // Implementation no longer uses movX instructions since | |
| 11416 // machine-independent system no longer uses CopyX nodes. | |
| 11417 // | |
| 11418 // peephole | |
| 11419 // %{ | |
| 11420 // peepmatch (incI_rReg movI); | |
| 11421 // peepconstraint (0.dst == 1.dst); | |
| 11422 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src)); | |
| 11423 // %} | |
| 11424 | |
| 11425 // peephole | |
| 11426 // %{ | |
| 11427 // peepmatch (decI_rReg movI); | |
| 11428 // peepconstraint (0.dst == 1.dst); | |
| 11429 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src)); | |
| 11430 // %} | |
| 11431 | |
| 11432 // peephole | |
| 11433 // %{ | |
| 11434 // peepmatch (addI_rReg_imm movI); | |
| 11435 // peepconstraint (0.dst == 1.dst); | |
| 11436 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src)); | |
| 11437 // %} | |
| 11438 | |
| 11439 // peephole | |
| 11440 // %{ | |
| 11441 // peepmatch (incL_rReg movL); | |
| 11442 // peepconstraint (0.dst == 1.dst); | |
| 11443 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src)); | |
| 11444 // %} | |
| 11445 | |
| 11446 // peephole | |
| 11447 // %{ | |
| 11448 // peepmatch (decL_rReg movL); | |
| 11449 // peepconstraint (0.dst == 1.dst); | |
| 11450 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src)); | |
| 11451 // %} | |
| 11452 | |
| 11453 // peephole | |
| 11454 // %{ | |
| 11455 // peepmatch (addL_rReg_imm movL); | |
| 11456 // peepconstraint (0.dst == 1.dst); | |
| 11457 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src)); | |
| 11458 // %} | |
| 11459 | |
| 11460 // peephole | |
| 11461 // %{ | |
| 11462 // peepmatch (addP_rReg_imm movP); | |
| 11463 // peepconstraint (0.dst == 1.dst); | |
| 11464 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src)); | |
| 11465 // %} | |
| 11466 | |
| 11467 // // Change load of spilled value to only a spill | |
| 11468 // instruct storeI(memory mem, rRegI src) | |
| 11469 // %{ | |
| 11470 // match(Set mem (StoreI mem src)); | |
| 11471 // %} | |
| 11472 // | |
| 11473 // instruct loadI(rRegI dst, memory mem) | |
| 11474 // %{ | |
| 11475 // match(Set dst (LoadI mem)); | |
| 11476 // %} | |
| 11477 // | |
| 11478 | |
| 11479 peephole | |
| 11480 %{ | |
| 11481 peepmatch (loadI storeI); | |
| 11482 peepconstraint (1.src == 0.dst, 1.mem == 0.mem); | |
| 11483 peepreplace (storeI(1.mem 1.mem 1.src)); | |
| 11484 %} | |
| 11485 | |
| 11486 peephole | |
| 11487 %{ | |
| 11488 peepmatch (loadL storeL); | |
| 11489 peepconstraint (1.src == 0.dst, 1.mem == 0.mem); | |
| 11490 peepreplace (storeL(1.mem 1.mem 1.src)); | |
| 11491 %} | |
| 11492 | |
| 11493 //----------SMARTSPILL RULES--------------------------------------------------- | |
| 11494 // These must follow all instruction definitions as they use the names | |
| 11495 // defined in the instructions definitions. |