Mercurial > hg > truffle
annotate src/cpu/x86/vm/x86_64.ad @ 17714:4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
Summary: Consolidated C2 x86 locking code in one place in macroAssembler_x86.cpp.
Reviewed-by: roland
| author | kvn |
|---|---|
| date | Mon, 24 Feb 2014 15:12:26 -0800 |
| parents | 984401824c5e |
| children | 085b304a1cc5 |
| rev | line source |
|---|---|
| 0 | 1 // |
| 9154 | 2 // Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 // | |
| 5 // This code is free software; you can redistribute it and/or modify it | |
| 6 // under the terms of the GNU General Public License version 2 only, as | |
| 7 // published by the Free Software Foundation. | |
| 8 // | |
| 9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 // version 2 for more details (a copy is included in the LICENSE file that | |
| 13 // accompanied this code). | |
| 14 // | |
| 15 // You should have received a copy of the GNU General Public License version | |
| 16 // 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 // | |
|
1552
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1396
diff
changeset
|
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
|
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1396
diff
changeset
|
20 // or visit www.oracle.com if you need additional information or have any |
|
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1396
diff
changeset
|
21 // questions. |
| 0 | 22 // |
| 23 // | |
| 24 | |
| 25 // AMD64 Architecture Description File | |
| 26 | |
| 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ | |
| 28 // This information is used by the matcher and the register allocator to | |
| 29 // describe individual registers and classes of registers within the target | |
| 30 // archtecture. | |
| 31 | |
| 32 register %{ | |
| 33 //----------Architecture Description Register Definitions---------------------- | |
| 34 // General Registers | |
| 35 // "reg_def" name ( register save type, C convention save type, | |
| 36 // ideal register type, encoding ); | |
| 37 // Register Save Types: | |
| 38 // | |
| 39 // NS = No-Save: The register allocator assumes that these registers | |
| 40 // can be used without saving upon entry to the method, & | |
| 41 // that they do not need to be saved at call sites. | |
| 42 // | |
| 43 // SOC = Save-On-Call: The register allocator assumes that these registers | |
| 44 // can be used without saving upon entry to the method, | |
| 45 // but that they must be saved at call sites. | |
| 46 // | |
| 47 // SOE = Save-On-Entry: The register allocator assumes that these registers | |
| 48 // must be saved before using them upon entry to the | |
| 49 // method, but they do not need to be saved at call | |
| 50 // sites. | |
| 51 // | |
| 52 // AS = Always-Save: The register allocator assumes that these registers | |
| 53 // must be saved before using them upon entry to the | |
| 54 // method, & that they must be saved at call sites. | |
| 55 // | |
| 56 // Ideal Register Type is used to determine how to save & restore a | |
| 57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get | |
| 58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. | |
| 59 // | |
| 60 // The encoding number is the actual bit-pattern placed into the opcodes. | |
| 61 | |
| 62 // General Registers | |
| 63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when | |
| 64 // used as byte registers) | |
| 65 | |
| 66 // Previously set RBX, RSI, and RDI as save-on-entry for java code | |
| 67 // Turn off SOE in java-code due to frequent use of uncommon-traps. | |
| 68 // Now that allocator is better, turn on RSI and RDI as SOE registers. | |
| 69 | |
| 70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg()); | |
| 71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next()); | |
| 72 | |
| 73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg()); | |
| 74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next()); | |
| 75 | |
| 76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg()); | |
| 77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next()); | |
| 78 | |
| 79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg()); | |
| 80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next()); | |
| 81 | |
| 82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg()); | |
| 83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next()); | |
| 84 | |
| 85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code | |
| 86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg()); | |
| 87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next()); | |
| 88 | |
| 89 #ifdef _WIN64 | |
| 90 | |
| 91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg()); | |
| 92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next()); | |
| 93 | |
| 94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg()); | |
| 95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next()); | |
| 96 | |
| 97 #else | |
| 98 | |
| 99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg()); | |
| 100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next()); | |
| 101 | |
| 102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg()); | |
| 103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next()); | |
| 104 | |
| 105 #endif | |
| 106 | |
| 107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg()); | |
| 108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next()); | |
| 109 | |
| 110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg()); | |
| 111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next()); | |
| 112 | |
| 113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg()); | |
| 114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next()); | |
| 115 | |
| 116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg()); | |
| 117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next()); | |
| 118 | |
| 119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg()); | |
| 120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next()); | |
| 121 | |
| 122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg()); | |
| 123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next()); | |
| 124 | |
| 125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg()); | |
| 126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next()); | |
| 127 | |
| 128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg()); | |
| 129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next()); | |
| 130 | |
| 131 | |
| 132 // Floating Point Registers | |
| 133 | |
| 134 // Specify priority of register selection within phases of register | |
| 135 // allocation. Highest priority is first. A useful heuristic is to | |
| 136 // give registers a low priority when they are required by machine | |
| 137 // instructions, like EAX and EDX on I486, and choose no-save registers | |
| 138 // before save-on-call, & save-on-call before save-on-entry. Registers | |
| 139 // which participate in fixed calling sequences should come last. | |
| 140 // Registers which are used as pairs must fall on an even boundary. | |
| 141 | |
| 142 alloc_class chunk0(R10, R10_H, | |
| 143 R11, R11_H, | |
| 144 R8, R8_H, | |
| 145 R9, R9_H, | |
| 146 R12, R12_H, | |
| 147 RCX, RCX_H, | |
| 148 RBX, RBX_H, | |
| 149 RDI, RDI_H, | |
| 150 RDX, RDX_H, | |
| 151 RSI, RSI_H, | |
| 152 RAX, RAX_H, | |
| 153 RBP, RBP_H, | |
| 154 R13, R13_H, | |
| 155 R14, R14_H, | |
| 156 R15, R15_H, | |
| 157 RSP, RSP_H); | |
| 158 | |
| 159 | |
| 160 //----------Architecture Description Register Classes-------------------------- | |
| 161 // Several register classes are automatically defined based upon information in | |
| 162 // this architecture description. | |
| 163 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ ) | |
| 164 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ ) | |
| 165 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ ) | |
| 166 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) | |
| 167 // | |
| 168 | |
| 169 // Class for all pointer registers (including RSP) | |
| 170 reg_class any_reg(RAX, RAX_H, | |
| 171 RDX, RDX_H, | |
| 172 RBP, RBP_H, | |
| 173 RDI, RDI_H, | |
| 174 RSI, RSI_H, | |
| 175 RCX, RCX_H, | |
| 176 RBX, RBX_H, | |
| 177 RSP, RSP_H, | |
| 178 R8, R8_H, | |
| 179 R9, R9_H, | |
| 180 R10, R10_H, | |
| 181 R11, R11_H, | |
| 182 R12, R12_H, | |
| 183 R13, R13_H, | |
| 184 R14, R14_H, | |
| 185 R15, R15_H); | |
| 186 | |
| 187 // Class for all pointer registers except RSP | |
| 188 reg_class ptr_reg(RAX, RAX_H, | |
| 189 RDX, RDX_H, | |
| 190 RBP, RBP_H, | |
| 191 RDI, RDI_H, | |
| 192 RSI, RSI_H, | |
| 193 RCX, RCX_H, | |
| 194 RBX, RBX_H, | |
| 195 R8, R8_H, | |
| 196 R9, R9_H, | |
| 197 R10, R10_H, | |
| 198 R11, R11_H, | |
| 199 R13, R13_H, | |
| 200 R14, R14_H); | |
| 201 | |
| 202 // Class for all pointer registers except RAX and RSP | |
| 203 reg_class ptr_no_rax_reg(RDX, RDX_H, | |
| 204 RBP, RBP_H, | |
| 205 RDI, RDI_H, | |
| 206 RSI, RSI_H, | |
| 207 RCX, RCX_H, | |
| 208 RBX, RBX_H, | |
| 209 R8, R8_H, | |
| 210 R9, R9_H, | |
| 211 R10, R10_H, | |
| 212 R11, R11_H, | |
| 213 R13, R13_H, | |
| 214 R14, R14_H); | |
| 215 | |
| 216 reg_class ptr_no_rbp_reg(RDX, RDX_H, | |
| 217 RAX, RAX_H, | |
| 218 RDI, RDI_H, | |
| 219 RSI, RSI_H, | |
| 220 RCX, RCX_H, | |
| 221 RBX, RBX_H, | |
| 222 R8, R8_H, | |
| 223 R9, R9_H, | |
| 224 R10, R10_H, | |
| 225 R11, R11_H, | |
| 226 R13, R13_H, | |
| 227 R14, R14_H); | |
| 228 | |
| 229 // Class for all pointer registers except RAX, RBX and RSP | |
| 230 reg_class ptr_no_rax_rbx_reg(RDX, RDX_H, | |
| 231 RBP, RBP_H, | |
| 232 RDI, RDI_H, | |
| 233 RSI, RSI_H, | |
| 234 RCX, RCX_H, | |
| 235 R8, R8_H, | |
| 236 R9, R9_H, | |
| 237 R10, R10_H, | |
| 238 R11, R11_H, | |
| 239 R13, R13_H, | |
| 240 R14, R14_H); | |
| 241 | |
| 242 // Singleton class for RAX pointer register | |
| 243 reg_class ptr_rax_reg(RAX, RAX_H); | |
| 244 | |
| 245 // Singleton class for RBX pointer register | |
| 246 reg_class ptr_rbx_reg(RBX, RBX_H); | |
| 247 | |
| 248 // Singleton class for RSI pointer register | |
| 249 reg_class ptr_rsi_reg(RSI, RSI_H); | |
| 250 | |
| 251 // Singleton class for RDI pointer register | |
| 252 reg_class ptr_rdi_reg(RDI, RDI_H); | |
| 253 | |
| 254 // Singleton class for RBP pointer register | |
| 255 reg_class ptr_rbp_reg(RBP, RBP_H); | |
| 256 | |
| 257 // Singleton class for stack pointer | |
| 258 reg_class ptr_rsp_reg(RSP, RSP_H); | |
| 259 | |
| 260 // Singleton class for TLS pointer | |
| 261 reg_class ptr_r15_reg(R15, R15_H); | |
| 262 | |
| 263 // Class for all long registers (except RSP) | |
| 264 reg_class long_reg(RAX, RAX_H, | |
| 265 RDX, RDX_H, | |
| 266 RBP, RBP_H, | |
| 267 RDI, RDI_H, | |
| 268 RSI, RSI_H, | |
| 269 RCX, RCX_H, | |
| 270 RBX, RBX_H, | |
| 271 R8, R8_H, | |
| 272 R9, R9_H, | |
| 273 R10, R10_H, | |
| 274 R11, R11_H, | |
| 275 R13, R13_H, | |
| 276 R14, R14_H); | |
| 277 | |
| 278 // Class for all long registers except RAX, RDX (and RSP) | |
| 279 reg_class long_no_rax_rdx_reg(RBP, RBP_H, | |
| 280 RDI, RDI_H, | |
| 281 RSI, RSI_H, | |
| 282 RCX, RCX_H, | |
| 283 RBX, RBX_H, | |
| 284 R8, R8_H, | |
| 285 R9, R9_H, | |
| 286 R10, R10_H, | |
| 287 R11, R11_H, | |
| 288 R13, R13_H, | |
| 289 R14, R14_H); | |
| 290 | |
| 291 // Class for all long registers except RCX (and RSP) | |
| 292 reg_class long_no_rcx_reg(RBP, RBP_H, | |
| 293 RDI, RDI_H, | |
| 294 RSI, RSI_H, | |
| 295 RAX, RAX_H, | |
| 296 RDX, RDX_H, | |
| 297 RBX, RBX_H, | |
| 298 R8, R8_H, | |
| 299 R9, R9_H, | |
| 300 R10, R10_H, | |
| 301 R11, R11_H, | |
| 302 R13, R13_H, | |
| 303 R14, R14_H); | |
| 304 | |
| 305 // Class for all long registers except RAX (and RSP) | |
| 306 reg_class long_no_rax_reg(RBP, RBP_H, | |
| 307 RDX, RDX_H, | |
| 308 RDI, RDI_H, | |
| 309 RSI, RSI_H, | |
| 310 RCX, RCX_H, | |
| 311 RBX, RBX_H, | |
| 312 R8, R8_H, | |
| 313 R9, R9_H, | |
| 314 R10, R10_H, | |
| 315 R11, R11_H, | |
| 316 R13, R13_H, | |
| 317 R14, R14_H); | |
| 318 | |
| 319 // Singleton class for RAX long register | |
| 320 reg_class long_rax_reg(RAX, RAX_H); | |
| 321 | |
| 322 // Singleton class for RCX long register | |
| 323 reg_class long_rcx_reg(RCX, RCX_H); | |
| 324 | |
| 325 // Singleton class for RDX long register | |
| 326 reg_class long_rdx_reg(RDX, RDX_H); | |
| 327 | |
| 328 // Class for all int registers (except RSP) | |
| 329 reg_class int_reg(RAX, | |
| 330 RDX, | |
| 331 RBP, | |
| 332 RDI, | |
| 333 RSI, | |
| 334 RCX, | |
| 335 RBX, | |
| 336 R8, | |
| 337 R9, | |
| 338 R10, | |
| 339 R11, | |
| 340 R13, | |
| 341 R14); | |
| 342 | |
| 343 // Class for all int registers except RCX (and RSP) | |
| 344 reg_class int_no_rcx_reg(RAX, | |
| 345 RDX, | |
| 346 RBP, | |
| 347 RDI, | |
| 348 RSI, | |
| 349 RBX, | |
| 350 R8, | |
| 351 R9, | |
| 352 R10, | |
| 353 R11, | |
| 354 R13, | |
| 355 R14); | |
| 356 | |
| 357 // Class for all int registers except RAX, RDX (and RSP) | |
| 358 reg_class int_no_rax_rdx_reg(RBP, | |
| 304 | 359 RDI, |
| 0 | 360 RSI, |
| 361 RCX, | |
| 362 RBX, | |
| 363 R8, | |
| 364 R9, | |
| 365 R10, | |
| 366 R11, | |
| 367 R13, | |
| 368 R14); | |
| 369 | |
| 370 // Singleton class for RAX int register | |
| 371 reg_class int_rax_reg(RAX); | |
| 372 | |
| 373 // Singleton class for RBX int register | |
| 374 reg_class int_rbx_reg(RBX); | |
| 375 | |
| 376 // Singleton class for RCX int register | |
| 377 reg_class int_rcx_reg(RCX); | |
| 378 | |
| 379 // Singleton class for RCX int register | |
| 380 reg_class int_rdx_reg(RDX); | |
| 381 | |
| 382 // Singleton class for RCX int register | |
| 383 reg_class int_rdi_reg(RDI); | |
| 384 | |
| 385 // Singleton class for instruction pointer | |
| 386 // reg_class ip_reg(RIP); | |
| 387 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
388 %} |
| 0 | 389 |
| 390 //----------SOURCE BLOCK------------------------------------------------------- | |
| 391 // This is a block of C++ code which provides values, functions, and | |
| 392 // definitions necessary in the rest of the architecture description | |
| 393 source %{ | |
| 304 | 394 #define RELOC_IMM64 Assembler::imm_operand |
| 0 | 395 #define RELOC_DISP32 Assembler::disp32_operand |
| 396 | |
| 397 #define __ _masm. | |
| 398 | |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
399 static int preserve_SP_size() { |
| 4759 | 400 return 3; // rex.w, op, rm(reg/reg) |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
401 } |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
402 static int clear_avx_size() { |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
403 return (Compile::current()->max_vector_size() > 16) ? 3 : 0; // vzeroupper |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
404 } |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
405 |
| 0 | 406 // !!!!! Special hack to get all types of calls to specify the byte offset |
| 407 // from the start of the call to the point where the return address | |
| 408 // will point. | |
| 409 int MachCallStaticJavaNode::ret_addr_offset() | |
| 410 { | |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
411 int offset = 5; // 5 bytes from start of call to where return address points |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
412 offset += clear_avx_size(); |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
413 if (_method_handle_invoke) |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
414 offset += preserve_SP_size(); |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
415 return offset; |
| 0 | 416 } |
| 417 | |
| 418 int MachCallDynamicJavaNode::ret_addr_offset() | |
| 419 { | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
420 int offset = 15; // 15 bytes from start of call to where return address points |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
421 offset += clear_avx_size(); |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
422 return offset; |
| 0 | 423 } |
| 424 | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
425 int MachCallRuntimeNode::ret_addr_offset() { |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
426 int offset = 13; // movq r10,#addr; callq (r10) |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
427 offset += clear_avx_size(); |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
428 return offset; |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
429 } |
| 0 | 430 |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
431 // Indicate if the safepoint node needs the polling page as an input, |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
432 // it does if the polling page is more than disp32 away. |
| 0 | 433 bool SafePointNode::needs_polling_address_input() |
| 434 { | |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
435 return Assembler::is_polling_page_far(); |
| 0 | 436 } |
| 437 | |
| 438 // | |
| 439 // Compute padding required for nodes which need alignment | |
| 440 // | |
| 441 | |
| 442 // The address of the call instruction needs to be 4-byte aligned to | |
| 443 // ensure that it does not span a cache line so that it can be patched. | |
| 444 int CallStaticJavaDirectNode::compute_padding(int current_offset) const | |
| 445 { | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
446 current_offset += clear_avx_size(); // skip vzeroupper |
| 0 | 447 current_offset += 1; // skip call opcode byte |
| 448 return round_to(current_offset, alignment_required()) - current_offset; | |
| 449 } | |
| 450 | |
| 451 // The address of the call instruction needs to be 4-byte aligned to | |
| 452 // ensure that it does not span a cache line so that it can be patched. | |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
453 int CallStaticJavaHandleNode::compute_padding(int current_offset) const |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
454 { |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
455 current_offset += preserve_SP_size(); // skip mov rbp, rsp |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
456 current_offset += clear_avx_size(); // skip vzeroupper |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
457 current_offset += 1; // skip call opcode byte |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
458 return round_to(current_offset, alignment_required()) - current_offset; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
459 } |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
460 |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
461 // The address of the call instruction needs to be 4-byte aligned to |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
462 // ensure that it does not span a cache line so that it can be patched. |
| 0 | 463 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const |
| 464 { | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
465 current_offset += clear_avx_size(); // skip vzeroupper |
| 0 | 466 current_offset += 11; // skip movq instruction + call opcode byte |
| 467 return round_to(current_offset, alignment_required()) - current_offset; | |
| 468 } | |
| 469 | |
| 470 // EMIT_RM() | |
| 1748 | 471 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) { |
| 0 | 472 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3); |
| 1748 | 473 cbuf.insts()->emit_int8(c); |
| 0 | 474 } |
| 475 | |
| 476 // EMIT_CC() | |
| 1748 | 477 void emit_cc(CodeBuffer &cbuf, int f1, int f2) { |
| 0 | 478 unsigned char c = (unsigned char) (f1 | f2); |
| 1748 | 479 cbuf.insts()->emit_int8(c); |
| 0 | 480 } |
| 481 | |
| 482 // EMIT_OPCODE() | |
| 1748 | 483 void emit_opcode(CodeBuffer &cbuf, int code) { |
| 484 cbuf.insts()->emit_int8((unsigned char) code); | |
| 0 | 485 } |
| 486 | |
| 487 // EMIT_OPCODE() w/ relocation information | |
| 488 void emit_opcode(CodeBuffer &cbuf, | |
| 489 int code, relocInfo::relocType reloc, int offset, int format) | |
| 490 { | |
| 1748 | 491 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format); |
| 0 | 492 emit_opcode(cbuf, code); |
| 493 } | |
| 494 | |
| 495 // EMIT_D8() | |
| 1748 | 496 void emit_d8(CodeBuffer &cbuf, int d8) { |
| 497 cbuf.insts()->emit_int8((unsigned char) d8); | |
| 0 | 498 } |
| 499 | |
| 500 // EMIT_D16() | |
| 1748 | 501 void emit_d16(CodeBuffer &cbuf, int d16) { |
| 502 cbuf.insts()->emit_int16(d16); | |
| 0 | 503 } |
| 504 | |
| 505 // EMIT_D32() | |
| 1748 | 506 void emit_d32(CodeBuffer &cbuf, int d32) { |
| 507 cbuf.insts()->emit_int32(d32); | |
| 0 | 508 } |
| 509 | |
| 510 // EMIT_D64() | |
| 1748 | 511 void emit_d64(CodeBuffer &cbuf, int64_t d64) { |
| 512 cbuf.insts()->emit_int64(d64); | |
| 0 | 513 } |
| 514 | |
| 515 // emit 32 bit value and construct relocation entry from relocInfo::relocType | |
| 516 void emit_d32_reloc(CodeBuffer& cbuf, | |
| 517 int d32, | |
| 518 relocInfo::relocType reloc, | |
| 519 int format) | |
| 520 { | |
| 521 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc"); | |
| 1748 | 522 cbuf.relocate(cbuf.insts_mark(), reloc, format); |
| 523 cbuf.insts()->emit_int32(d32); | |
| 0 | 524 } |
| 525 | |
| 526 // emit 32 bit value and construct relocation entry from RelocationHolder | |
| 1748 | 527 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) { |
| 0 | 528 #ifdef ASSERT |
| 529 if (rspec.reloc()->type() == relocInfo::oop_type && | |
| 530 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) { | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
531 assert(Universe::heap()->is_in_reserved((address)(intptr_t)d32), "should be real oop"); |
|
12316
190899198332
7195622: CheckUnhandledOops has limited usefulness now
hseigel
parents:
12226
diff
changeset
|
532 assert(cast_to_oop((intptr_t)d32)->is_oop() && (ScavengeRootsInCode || !cast_to_oop((intptr_t)d32)->is_scavengable()), "cannot embed scavengable oops in code"); |
| 0 | 533 } |
| 534 #endif | |
| 1748 | 535 cbuf.relocate(cbuf.insts_mark(), rspec, format); |
| 536 cbuf.insts()->emit_int32(d32); | |
| 0 | 537 } |
| 538 | |
| 539 void emit_d32_reloc(CodeBuffer& cbuf, address addr) { | |
| 1748 | 540 address next_ip = cbuf.insts_end() + 4; |
| 0 | 541 emit_d32_reloc(cbuf, (int) (addr - next_ip), |
| 542 external_word_Relocation::spec(addr), | |
| 543 RELOC_DISP32); | |
| 544 } | |
| 545 | |
| 546 | |
| 547 // emit 64 bit value and construct relocation entry from relocInfo::relocType | |
| 1748 | 548 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) { |
| 549 cbuf.relocate(cbuf.insts_mark(), reloc, format); | |
| 550 cbuf.insts()->emit_int64(d64); | |
| 0 | 551 } |
| 552 | |
| 553 // emit 64 bit value and construct relocation entry from RelocationHolder | |
| 1748 | 554 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) { |
| 0 | 555 #ifdef ASSERT |
| 556 if (rspec.reloc()->type() == relocInfo::oop_type && | |
| 557 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) { | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
558 assert(Universe::heap()->is_in_reserved((address)d64), "should be real oop"); |
|
12316
190899198332
7195622: CheckUnhandledOops has limited usefulness now
hseigel
parents:
12226
diff
changeset
|
559 assert(cast_to_oop(d64)->is_oop() && (ScavengeRootsInCode || !cast_to_oop(d64)->is_scavengable()), |
|
989
148e5441d916
6863023: need non-perm oops in code cache for JSR 292
jrose
parents:
986
diff
changeset
|
560 "cannot embed scavengable oops in code"); |
| 0 | 561 } |
| 562 #endif | |
| 1748 | 563 cbuf.relocate(cbuf.insts_mark(), rspec, format); |
| 564 cbuf.insts()->emit_int64(d64); | |
| 0 | 565 } |
| 566 | |
| 567 // Access stack slot for load or store | |
| 568 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) | |
| 569 { | |
| 570 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src]) | |
| 571 if (-0x80 <= disp && disp < 0x80) { | |
| 572 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte | |
| 573 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte | |
| 574 emit_d8(cbuf, disp); // Displacement // R/M byte | |
| 575 } else { | |
| 576 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte | |
| 577 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte | |
| 578 emit_d32(cbuf, disp); // Displacement // R/M byte | |
| 579 } | |
| 580 } | |
| 581 | |
| 582 // rRegI ereg, memory mem) %{ // emit_reg_mem | |
| 583 void encode_RegMem(CodeBuffer &cbuf, | |
| 584 int reg, | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
585 int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) |
| 0 | 586 { |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
587 assert(disp_reloc == relocInfo::none, "cannot have disp"); |
| 0 | 588 int regenc = reg & 7; |
| 589 int baseenc = base & 7; | |
| 590 int indexenc = index & 7; | |
| 591 | |
| 592 // There is no index & no scale, use form without SIB byte | |
| 593 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) { | |
| 594 // If no displacement, mode is 0x0; unless base is [RBP] or [R13] | |
| 595 if (disp == 0 && base != RBP_enc && base != R13_enc) { | |
| 596 emit_rm(cbuf, 0x0, regenc, baseenc); // * | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
597 } else if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) { |
| 0 | 598 // If 8-bit displacement, mode 0x1 |
| 599 emit_rm(cbuf, 0x1, regenc, baseenc); // * | |
| 600 emit_d8(cbuf, disp); | |
| 601 } else { | |
| 602 // If 32-bit displacement | |
| 603 if (base == -1) { // Special flag for absolute address | |
| 604 emit_rm(cbuf, 0x0, regenc, 0x5); // * | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
605 if (disp_reloc != relocInfo::none) { |
| 0 | 606 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32); |
| 607 } else { | |
| 608 emit_d32(cbuf, disp); | |
| 609 } | |
| 610 } else { | |
| 611 // Normal base + offset | |
| 612 emit_rm(cbuf, 0x2, regenc, baseenc); // * | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
613 if (disp_reloc != relocInfo::none) { |
| 0 | 614 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32); |
| 615 } else { | |
| 616 emit_d32(cbuf, disp); | |
| 617 } | |
| 618 } | |
| 619 } | |
| 620 } else { | |
| 621 // Else, encode with the SIB byte | |
| 622 // If no displacement, mode is 0x0; unless base is [RBP] or [R13] | |
| 623 if (disp == 0 && base != RBP_enc && base != R13_enc) { | |
| 624 // If no displacement | |
| 625 emit_rm(cbuf, 0x0, regenc, 0x4); // * | |
| 626 emit_rm(cbuf, scale, indexenc, baseenc); | |
| 627 } else { | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
628 if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) { |
| 0 | 629 // If 8-bit displacement, mode 0x1 |
| 630 emit_rm(cbuf, 0x1, regenc, 0x4); // * | |
| 631 emit_rm(cbuf, scale, indexenc, baseenc); | |
| 632 emit_d8(cbuf, disp); | |
| 633 } else { | |
| 634 // If 32-bit displacement | |
| 635 if (base == 0x04 ) { | |
| 636 emit_rm(cbuf, 0x2, regenc, 0x4); | |
| 637 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid??? | |
| 638 } else { | |
| 639 emit_rm(cbuf, 0x2, regenc, 0x4); | |
| 640 emit_rm(cbuf, scale, indexenc, baseenc); // * | |
| 641 } | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
642 if (disp_reloc != relocInfo::none) { |
| 0 | 643 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32); |
| 644 } else { | |
| 645 emit_d32(cbuf, disp); | |
| 646 } | |
| 647 } | |
| 648 } | |
| 649 } | |
| 650 } | |
| 651 | |
| 3783 | 652 // This could be in MacroAssembler but it's fairly C2 specific |
| 653 void emit_cmpfp_fixup(MacroAssembler& _masm) { | |
| 654 Label exit; | |
| 655 __ jccb(Assembler::noParity, exit); | |
| 656 __ pushf(); | |
| 4759 | 657 // |
| 658 // comiss/ucomiss instructions set ZF,PF,CF flags and | |
| 659 // zero OF,AF,SF for NaN values. | |
| 660 // Fixup flags by zeroing ZF,PF so that compare of NaN | |
| 661 // values returns 'less than' result (CF is set). | |
| 662 // Leave the rest of flags unchanged. | |
| 663 // | |
| 664 // 7 6 5 4 3 2 1 0 | |
| 665 // |S|Z|r|A|r|P|r|C| (r - reserved bit) | |
| 666 // 0 0 1 0 1 0 1 1 (0x2B) | |
| 667 // | |
| 3783 | 668 __ andq(Address(rsp, 0), 0xffffff2b); |
| 669 __ popf(); | |
| 670 __ bind(exit); | |
| 4759 | 671 } |
| 672 | |
| 673 void emit_cmpfp3(MacroAssembler& _masm, Register dst) { | |
| 674 Label done; | |
| 675 __ movl(dst, -1); | |
| 676 __ jcc(Assembler::parity, done); | |
| 677 __ jcc(Assembler::below, done); | |
| 678 __ setb(Assembler::notEqual, dst); | |
| 679 __ movzbl(dst, dst); | |
| 680 __ bind(done); | |
| 3783 | 681 } |
| 682 | |
| 0 | 683 |
| 684 //============================================================================= | |
| 2008 | 685 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty; |
| 686 | |
|
4114
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
687 int Compile::ConstantTable::calculate_table_base_offset() const { |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
688 return 0; // absolute addressing, no offset |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
689 } |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
690 |
| 2008 | 691 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { |
| 692 // Empty encoding | |
| 693 } | |
| 694 | |
| 695 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const { | |
| 696 return 0; | |
| 697 } | |
| 698 | |
| 699 #ifndef PRODUCT | |
| 700 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { | |
| 701 st->print("# MachConstantBaseNode (empty encoding)"); | |
| 702 } | |
| 703 #endif | |
| 704 | |
| 705 | |
| 706 //============================================================================= | |
| 0 | 707 #ifndef PRODUCT |
|
4947
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
708 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const { |
| 0 | 709 Compile* C = ra_->C; |
| 710 | |
| 711 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 712 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
|
4947
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
713 // Remove wordSize for return addr which is already pushed. |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
714 framesize -= wordSize; |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
715 |
| 0 | 716 if (C->need_stack_bang(framesize)) { |
|
4947
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
717 framesize -= wordSize; |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
718 st->print("# stack bang"); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
719 st->print("\n\t"); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
720 st->print("pushq rbp\t# Save rbp"); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
721 if (framesize) { |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
722 st->print("\n\t"); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
723 st->print("subq rsp, #%d\t# Create frame",framesize); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
724 } |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
725 } else { |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
726 st->print("subq rsp, #%d\t# Create frame",framesize); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
727 st->print("\n\t"); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
728 framesize -= wordSize; |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
729 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize); |
| 0 | 730 } |
| 731 | |
| 732 if (VerifyStackAtCalls) { | |
|
4947
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
733 st->print("\n\t"); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
734 framesize -= wordSize; |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
735 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
736 #ifdef ASSERT |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
737 st->print("\n\t"); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
738 st->print("# stack alignment check"); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
739 #endif |
| 0 | 740 } |
|
4947
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
741 st->cr(); |
| 0 | 742 } |
| 743 #endif | |
| 744 | |
|
4947
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
745 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { |
| 0 | 746 Compile* C = ra_->C; |
|
4947
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
747 MacroAssembler _masm(&cbuf); |
| 0 | 748 |
| 749 int framesize = C->frame_slots() << LogBytesPerInt; | |
|
4947
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
750 |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4777
diff
changeset
|
751 __ verified_entry(framesize, C->need_stack_bang(framesize), false); |
| 0 | 752 |
| 1748 | 753 C->set_frame_complete(cbuf.insts_size()); |
| 0 | 754 |
|
4114
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
755 if (C->has_mach_constant_base_node()) { |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
756 // NOTE: We set the table base offset here because users might be |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
757 // emitted before MachConstantBaseNode. |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
758 Compile::ConstantTable& constant_table = C->constant_table(); |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
759 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset()); |
|
6729bbc1fcd6
7003454: order constants in constant table by number of references in code
twisti
parents:
4047
diff
changeset
|
760 } |
| 0 | 761 } |
| 762 | |
| 763 uint MachPrologNode::size(PhaseRegAlloc* ra_) const | |
| 764 { | |
| 765 return MachNode::size(ra_); // too many variables; just compute it | |
| 766 // the hard way | |
| 767 } | |
| 768 | |
| 769 int MachPrologNode::reloc() const | |
| 770 { | |
| 771 return 0; // a large enough number | |
| 772 } | |
| 773 | |
| 774 //============================================================================= | |
| 775 #ifndef PRODUCT | |
| 776 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const | |
| 777 { | |
| 778 Compile* C = ra_->C; | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
779 if (C->max_vector_size() > 16) { |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
780 st->print("vzeroupper"); |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
781 st->cr(); st->print("\t"); |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
782 } |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
783 |
| 0 | 784 int framesize = C->frame_slots() << LogBytesPerInt; |
| 785 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 786 // Remove word for return adr already pushed | |
| 787 // and RBP | |
| 788 framesize -= 2*wordSize; | |
| 789 | |
| 790 if (framesize) { | |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
791 st->print_cr("addq rsp, %d\t# Destroy frame", framesize); |
| 0 | 792 st->print("\t"); |
| 793 } | |
| 794 | |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
795 st->print_cr("popq rbp"); |
| 0 | 796 if (do_polling() && C->is_method_compilation()) { |
| 797 st->print("\t"); | |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
798 if (Assembler::is_polling_page_far()) { |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
799 st->print_cr("movq rscratch1, #polling_page_address\n\t" |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
800 "testl rax, [rscratch1]\t" |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
801 "# Safepoint: poll for GC"); |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
802 } else { |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
803 st->print_cr("testl rax, [rip + #offset_to_poll_page]\t" |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
804 "# Safepoint: poll for GC"); |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
805 } |
| 0 | 806 } |
| 807 } | |
| 808 #endif | |
| 809 | |
| 810 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const | |
| 811 { | |
| 812 Compile* C = ra_->C; | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
813 if (C->max_vector_size() > 16) { |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
814 // Clear upper bits of YMM registers when current compiled code uses |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
815 // wide vectors to avoid AVX <-> SSE transition penalty during call. |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
816 MacroAssembler _masm(&cbuf); |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
817 __ vzeroupper(); |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
818 } |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
819 |
| 0 | 820 int framesize = C->frame_slots() << LogBytesPerInt; |
| 821 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 822 // Remove word for return adr already pushed | |
| 823 // and RBP | |
| 824 framesize -= 2*wordSize; | |
| 825 | |
| 826 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here | |
| 827 | |
| 828 if (framesize) { | |
| 829 emit_opcode(cbuf, Assembler::REX_W); | |
| 830 if (framesize < 0x80) { | |
| 831 emit_opcode(cbuf, 0x83); // addq rsp, #framesize | |
| 832 emit_rm(cbuf, 0x3, 0x00, RSP_enc); | |
| 833 emit_d8(cbuf, framesize); | |
| 834 } else { | |
| 835 emit_opcode(cbuf, 0x81); // addq rsp, #framesize | |
| 836 emit_rm(cbuf, 0x3, 0x00, RSP_enc); | |
| 837 emit_d32(cbuf, framesize); | |
| 838 } | |
| 839 } | |
| 840 | |
| 841 // popq rbp | |
| 842 emit_opcode(cbuf, 0x58 | RBP_enc); | |
| 843 | |
| 844 if (do_polling() && C->is_method_compilation()) { | |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
845 MacroAssembler _masm(&cbuf); |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
846 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type); |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
847 if (Assembler::is_polling_page_far()) { |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
848 __ lea(rscratch1, polling_page); |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
849 __ relocate(relocInfo::poll_return_type); |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
850 __ testl(rax, Address(rscratch1, 0)); |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
851 } else { |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
852 __ testl(rax, polling_page); |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
853 } |
| 0 | 854 } |
| 855 } | |
| 856 | |
| 857 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const | |
| 858 { | |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
859 return MachNode::size(ra_); // too many variables; just compute it |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
860 // the hard way |
| 0 | 861 } |
| 862 | |
| 863 int MachEpilogNode::reloc() const | |
| 864 { | |
| 865 return 2; // a large enough number | |
| 866 } | |
| 867 | |
| 868 const Pipeline* MachEpilogNode::pipeline() const | |
| 869 { | |
| 870 return MachNode::pipeline_class(); | |
| 871 } | |
| 872 | |
| 873 int MachEpilogNode::safepoint_offset() const | |
| 874 { | |
| 875 return 0; | |
| 876 } | |
| 877 | |
| 878 //============================================================================= | |
| 879 | |
| 880 enum RC { | |
| 881 rc_bad, | |
| 882 rc_int, | |
| 883 rc_float, | |
| 884 rc_stack | |
| 885 }; | |
| 886 | |
| 887 static enum RC rc_class(OptoReg::Name reg) | |
| 888 { | |
| 889 if( !OptoReg::is_valid(reg) ) return rc_bad; | |
| 890 | |
| 891 if (OptoReg::is_stack(reg)) return rc_stack; | |
| 892 | |
| 893 VMReg r = OptoReg::as_VMReg(reg); | |
| 894 | |
| 895 if (r->is_Register()) return rc_int; | |
| 896 | |
| 897 assert(r->is_XMMRegister(), "must be"); | |
| 898 return rc_float; | |
| 899 } | |
| 900 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
901 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad. |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
902 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
903 int src_hi, int dst_hi, uint ireg, outputStream* st); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
904 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
905 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load, |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
906 int stack_offset, int reg, uint ireg, outputStream* st); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
907 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
908 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset, |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
909 int dst_offset, uint ireg, outputStream* st) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
910 if (cbuf) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
911 MacroAssembler _masm(cbuf); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
912 switch (ireg) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
913 case Op_VecS: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
914 __ movq(Address(rsp, -8), rax); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
915 __ movl(rax, Address(rsp, src_offset)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
916 __ movl(Address(rsp, dst_offset), rax); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
917 __ movq(rax, Address(rsp, -8)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
918 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
919 case Op_VecD: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
920 __ pushq(Address(rsp, src_offset)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
921 __ popq (Address(rsp, dst_offset)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
922 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
923 case Op_VecX: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
924 __ pushq(Address(rsp, src_offset)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
925 __ popq (Address(rsp, dst_offset)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
926 __ pushq(Address(rsp, src_offset+8)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
927 __ popq (Address(rsp, dst_offset+8)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
928 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
929 case Op_VecY: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
930 __ vmovdqu(Address(rsp, -32), xmm0); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
931 __ vmovdqu(xmm0, Address(rsp, src_offset)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
932 __ vmovdqu(Address(rsp, dst_offset), xmm0); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
933 __ vmovdqu(xmm0, Address(rsp, -32)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
934 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
935 default: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
936 ShouldNotReachHere(); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
937 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
938 #ifndef PRODUCT |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
939 } else { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
940 switch (ireg) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
941 case Op_VecS: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
942 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
943 "movl rax, [rsp + #%d]\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
944 "movl [rsp + #%d], rax\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
945 "movq rax, [rsp - #8]", |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
946 src_offset, dst_offset); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
947 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
948 case Op_VecD: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
949 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
950 "popq [rsp + #%d]", |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
951 src_offset, dst_offset); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
952 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
953 case Op_VecX: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
954 st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
955 "popq [rsp + #%d]\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
956 "pushq [rsp + #%d]\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
957 "popq [rsp + #%d]", |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
958 src_offset, dst_offset, src_offset+8, dst_offset+8); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
959 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
960 case Op_VecY: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
961 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
962 "vmovdqu xmm0, [rsp + #%d]\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
963 "vmovdqu [rsp + #%d], xmm0\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
964 "vmovdqu xmm0, [rsp - #32]", |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
965 src_offset, dst_offset); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
966 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
967 default: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
968 ShouldNotReachHere(); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
969 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
970 #endif |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
971 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
972 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
973 |
| 0 | 974 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf, |
| 975 PhaseRegAlloc* ra_, | |
| 976 bool do_size, | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
977 outputStream* st) const { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
978 assert(cbuf != NULL || st != NULL, "sanity"); |
| 0 | 979 // Get registers to move |
| 980 OptoReg::Name src_second = ra_->get_reg_second(in(1)); | |
| 981 OptoReg::Name src_first = ra_->get_reg_first(in(1)); | |
| 982 OptoReg::Name dst_second = ra_->get_reg_second(this); | |
| 983 OptoReg::Name dst_first = ra_->get_reg_first(this); | |
| 984 | |
| 985 enum RC src_second_rc = rc_class(src_second); | |
| 986 enum RC src_first_rc = rc_class(src_first); | |
| 987 enum RC dst_second_rc = rc_class(dst_second); | |
| 988 enum RC dst_first_rc = rc_class(dst_first); | |
| 989 | |
| 990 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), | |
| 991 "must move at least 1 register" ); | |
| 992 | |
| 993 if (src_first == dst_first && src_second == dst_second) { | |
| 994 // Self copy, no move | |
| 995 return 0; | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
996 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
997 if (bottom_type()->isa_vect() != NULL) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
998 uint ireg = ideal_reg(); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
999 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity"); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1000 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity"); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1001 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1002 // mem -> mem |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1003 int src_offset = ra_->reg2offset(src_first); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1004 int dst_offset = ra_->reg2offset(dst_first); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1005 vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1006 } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1007 vec_mov_helper(cbuf, false, src_first, dst_first, src_second, dst_second, ireg, st); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1008 } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1009 int stack_offset = ra_->reg2offset(dst_first); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1010 vec_spill_helper(cbuf, false, false, stack_offset, src_first, ireg, st); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1011 } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1012 int stack_offset = ra_->reg2offset(src_first); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1013 vec_spill_helper(cbuf, false, true, stack_offset, dst_first, ireg, st); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1014 } else { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1015 ShouldNotReachHere(); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1016 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1017 return 0; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1018 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1019 if (src_first_rc == rc_stack) { |
| 0 | 1020 // mem -> |
| 1021 if (dst_first_rc == rc_stack) { | |
| 1022 // mem -> mem | |
| 1023 assert(src_second != dst_first, "overlap"); | |
| 1024 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1025 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1026 // 64-bit | |
| 1027 int src_offset = ra_->reg2offset(src_first); | |
| 1028 int dst_offset = ra_->reg2offset(dst_first); | |
| 1029 if (cbuf) { | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1030 MacroAssembler _masm(cbuf); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1031 __ pushq(Address(rsp, src_offset)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1032 __ popq (Address(rsp, dst_offset)); |
| 0 | 1033 #ifndef PRODUCT |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1034 } else { |
| 0 | 1035 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t" |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1036 "popq [rsp + #%d]", |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1037 src_offset, dst_offset); |
| 0 | 1038 #endif |
| 1039 } | |
| 1040 } else { | |
| 1041 // 32-bit | |
| 1042 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1043 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1044 // No pushl/popl, so: | |
| 1045 int src_offset = ra_->reg2offset(src_first); | |
| 1046 int dst_offset = ra_->reg2offset(dst_first); | |
| 1047 if (cbuf) { | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1048 MacroAssembler _masm(cbuf); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1049 __ movq(Address(rsp, -8), rax); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1050 __ movl(rax, Address(rsp, src_offset)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1051 __ movl(Address(rsp, dst_offset), rax); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1052 __ movq(rax, Address(rsp, -8)); |
| 0 | 1053 #ifndef PRODUCT |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1054 } else { |
| 0 | 1055 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t" |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1056 "movl rax, [rsp + #%d]\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1057 "movl [rsp + #%d], rax\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1058 "movq rax, [rsp - #8]", |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1059 src_offset, dst_offset); |
| 0 | 1060 #endif |
| 1061 } | |
| 1062 } | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1063 return 0; |
| 0 | 1064 } else if (dst_first_rc == rc_int) { |
| 1065 // mem -> gpr | |
| 1066 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1067 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1068 // 64-bit | |
| 1069 int offset = ra_->reg2offset(src_first); | |
| 1070 if (cbuf) { | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1071 MacroAssembler _masm(cbuf); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1072 __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset)); |
| 0 | 1073 #ifndef PRODUCT |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1074 } else { |
| 0 | 1075 st->print("movq %s, [rsp + #%d]\t# spill", |
| 1076 Matcher::regName[dst_first], | |
| 1077 offset); | |
| 1078 #endif | |
| 1079 } | |
| 1080 } else { | |
| 1081 // 32-bit | |
| 1082 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1083 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1084 int offset = ra_->reg2offset(src_first); | |
| 1085 if (cbuf) { | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1086 MacroAssembler _masm(cbuf); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1087 __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset)); |
| 0 | 1088 #ifndef PRODUCT |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1089 } else { |
| 0 | 1090 st->print("movl %s, [rsp + #%d]\t# spill", |
| 1091 Matcher::regName[dst_first], | |
| 1092 offset); | |
| 1093 #endif | |
| 1094 } | |
| 1095 } | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1096 return 0; |
| 0 | 1097 } else if (dst_first_rc == rc_float) { |
| 1098 // mem-> xmm | |
| 1099 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1100 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1101 // 64-bit | |
| 1102 int offset = ra_->reg2offset(src_first); | |
| 1103 if (cbuf) { | |
| 4759 | 1104 MacroAssembler _masm(cbuf); |
| 1105 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset)); | |
| 0 | 1106 #ifndef PRODUCT |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1107 } else { |
| 0 | 1108 st->print("%s %s, [rsp + #%d]\t# spill", |
| 1109 UseXmmLoadAndClearUpper ? "movsd " : "movlpd", | |
| 1110 Matcher::regName[dst_first], | |
| 1111 offset); | |
| 1112 #endif | |
| 1113 } | |
| 1114 } else { | |
| 1115 // 32-bit | |
| 1116 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1117 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1118 int offset = ra_->reg2offset(src_first); | |
| 1119 if (cbuf) { | |
| 4759 | 1120 MacroAssembler _masm(cbuf); |
| 1121 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset)); | |
| 0 | 1122 #ifndef PRODUCT |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1123 } else { |
| 0 | 1124 st->print("movss %s, [rsp + #%d]\t# spill", |
| 1125 Matcher::regName[dst_first], | |
| 1126 offset); | |
| 1127 #endif | |
| 1128 } | |
| 1129 } | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1130 return 0; |
| 0 | 1131 } |
| 1132 } else if (src_first_rc == rc_int) { | |
| 1133 // gpr -> | |
| 1134 if (dst_first_rc == rc_stack) { | |
| 1135 // gpr -> mem | |
| 1136 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1137 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1138 // 64-bit | |
| 1139 int offset = ra_->reg2offset(dst_first); | |
| 1140 if (cbuf) { | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1141 MacroAssembler _masm(cbuf); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1142 __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first])); |
| 0 | 1143 #ifndef PRODUCT |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1144 } else { |
| 0 | 1145 st->print("movq [rsp + #%d], %s\t# spill", |
| 1146 offset, | |
| 1147 Matcher::regName[src_first]); | |
| 1148 #endif | |
| 1149 } | |
| 1150 } else { | |
| 1151 // 32-bit | |
| 1152 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1153 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1154 int offset = ra_->reg2offset(dst_first); | |
| 1155 if (cbuf) { | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1156 MacroAssembler _masm(cbuf); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1157 __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first])); |
| 0 | 1158 #ifndef PRODUCT |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1159 } else { |
| 0 | 1160 st->print("movl [rsp + #%d], %s\t# spill", |
| 1161 offset, | |
| 1162 Matcher::regName[src_first]); | |
| 1163 #endif | |
| 1164 } | |
| 1165 } | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1166 return 0; |
| 0 | 1167 } else if (dst_first_rc == rc_int) { |
| 1168 // gpr -> gpr | |
| 1169 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1170 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1171 // 64-bit | |
| 1172 if (cbuf) { | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1173 MacroAssembler _masm(cbuf); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1174 __ movq(as_Register(Matcher::_regEncode[dst_first]), |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1175 as_Register(Matcher::_regEncode[src_first])); |
| 0 | 1176 #ifndef PRODUCT |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1177 } else { |
| 0 | 1178 st->print("movq %s, %s\t# spill", |
| 1179 Matcher::regName[dst_first], | |
| 1180 Matcher::regName[src_first]); | |
| 1181 #endif | |
| 1182 } | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1183 return 0; |
| 0 | 1184 } else { |
| 1185 // 32-bit | |
| 1186 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1187 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1188 if (cbuf) { | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1189 MacroAssembler _masm(cbuf); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1190 __ movl(as_Register(Matcher::_regEncode[dst_first]), |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1191 as_Register(Matcher::_regEncode[src_first])); |
| 0 | 1192 #ifndef PRODUCT |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1193 } else { |
| 0 | 1194 st->print("movl %s, %s\t# spill", |
| 1195 Matcher::regName[dst_first], | |
| 1196 Matcher::regName[src_first]); | |
| 1197 #endif | |
| 1198 } | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1199 return 0; |
| 0 | 1200 } |
| 1201 } else if (dst_first_rc == rc_float) { | |
| 1202 // gpr -> xmm | |
| 1203 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1204 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1205 // 64-bit | |
| 1206 if (cbuf) { | |
| 4759 | 1207 MacroAssembler _masm(cbuf); |
| 1208 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first])); | |
| 0 | 1209 #ifndef PRODUCT |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1210 } else { |
| 0 | 1211 st->print("movdq %s, %s\t# spill", |
| 1212 Matcher::regName[dst_first], | |
| 1213 Matcher::regName[src_first]); | |
| 1214 #endif | |
| 1215 } | |
| 1216 } else { | |
| 1217 // 32-bit | |
| 1218 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1219 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1220 if (cbuf) { | |
| 4759 | 1221 MacroAssembler _masm(cbuf); |
| 1222 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first])); | |
| 0 | 1223 #ifndef PRODUCT |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1224 } else { |
| 0 | 1225 st->print("movdl %s, %s\t# spill", |
| 1226 Matcher::regName[dst_first], | |
| 1227 Matcher::regName[src_first]); | |
| 1228 #endif | |
| 1229 } | |
| 1230 } | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1231 return 0; |
| 0 | 1232 } |
| 1233 } else if (src_first_rc == rc_float) { | |
| 1234 // xmm -> | |
| 1235 if (dst_first_rc == rc_stack) { | |
| 1236 // xmm -> mem | |
| 1237 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1238 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1239 // 64-bit | |
| 1240 int offset = ra_->reg2offset(dst_first); | |
| 1241 if (cbuf) { | |
| 4759 | 1242 MacroAssembler _masm(cbuf); |
| 1243 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first])); | |
| 0 | 1244 #ifndef PRODUCT |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1245 } else { |
| 0 | 1246 st->print("movsd [rsp + #%d], %s\t# spill", |
| 1247 offset, | |
| 1248 Matcher::regName[src_first]); | |
| 1249 #endif | |
| 1250 } | |
| 1251 } else { | |
| 1252 // 32-bit | |
| 1253 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1254 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1255 int offset = ra_->reg2offset(dst_first); | |
| 1256 if (cbuf) { | |
| 4759 | 1257 MacroAssembler _masm(cbuf); |
| 1258 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first])); | |
| 0 | 1259 #ifndef PRODUCT |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1260 } else { |
| 0 | 1261 st->print("movss [rsp + #%d], %s\t# spill", |
| 1262 offset, | |
| 1263 Matcher::regName[src_first]); | |
| 1264 #endif | |
| 1265 } | |
| 1266 } | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1267 return 0; |
| 0 | 1268 } else if (dst_first_rc == rc_int) { |
| 1269 // xmm -> gpr | |
| 1270 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1271 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1272 // 64-bit | |
| 1273 if (cbuf) { | |
| 4759 | 1274 MacroAssembler _masm(cbuf); |
| 1275 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first])); | |
| 0 | 1276 #ifndef PRODUCT |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1277 } else { |
| 0 | 1278 st->print("movdq %s, %s\t# spill", |
| 1279 Matcher::regName[dst_first], | |
| 1280 Matcher::regName[src_first]); | |
| 1281 #endif | |
| 1282 } | |
| 1283 } else { | |
| 1284 // 32-bit | |
| 1285 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1286 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1287 if (cbuf) { | |
| 4759 | 1288 MacroAssembler _masm(cbuf); |
| 1289 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first])); | |
| 0 | 1290 #ifndef PRODUCT |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1291 } else { |
| 0 | 1292 st->print("movdl %s, %s\t# spill", |
| 1293 Matcher::regName[dst_first], | |
| 1294 Matcher::regName[src_first]); | |
| 1295 #endif | |
| 1296 } | |
| 1297 } | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1298 return 0; |
| 0 | 1299 } else if (dst_first_rc == rc_float) { |
| 1300 // xmm -> xmm | |
| 1301 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1302 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1303 // 64-bit | |
| 1304 if (cbuf) { | |
| 4759 | 1305 MacroAssembler _masm(cbuf); |
| 1306 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first])); | |
| 0 | 1307 #ifndef PRODUCT |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1308 } else { |
| 0 | 1309 st->print("%s %s, %s\t# spill", |
| 1310 UseXmmRegToRegMoveAll ? "movapd" : "movsd ", | |
| 1311 Matcher::regName[dst_first], | |
| 1312 Matcher::regName[src_first]); | |
| 1313 #endif | |
| 1314 } | |
| 1315 } else { | |
| 1316 // 32-bit | |
| 1317 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1318 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1319 if (cbuf) { | |
| 4759 | 1320 MacroAssembler _masm(cbuf); |
| 1321 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first])); | |
| 0 | 1322 #ifndef PRODUCT |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1323 } else { |
| 0 | 1324 st->print("%s %s, %s\t# spill", |
| 1325 UseXmmRegToRegMoveAll ? "movaps" : "movss ", | |
| 1326 Matcher::regName[dst_first], | |
| 1327 Matcher::regName[src_first]); | |
| 1328 #endif | |
| 1329 } | |
| 1330 } | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1331 return 0; |
| 0 | 1332 } |
| 1333 } | |
| 1334 | |
| 1335 assert(0," foo "); | |
| 1336 Unimplemented(); | |
| 1337 return 0; | |
| 1338 } | |
| 1339 | |
| 1340 #ifndef PRODUCT | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1341 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const { |
| 0 | 1342 implementation(NULL, ra_, false, st); |
| 1343 } | |
| 1344 #endif | |
| 1345 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1346 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { |
| 0 | 1347 implementation(&cbuf, ra_, false, NULL); |
| 1348 } | |
| 1349 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1350 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1351 return MachNode::size(ra_); |
| 0 | 1352 } |
| 1353 | |
| 1354 //============================================================================= | |
| 1355 #ifndef PRODUCT | |
| 1356 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const | |
| 1357 { | |
| 1358 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1359 int reg = ra_->get_reg_first(this); | |
| 1360 st->print("leaq %s, [rsp + #%d]\t# box lock", | |
| 1361 Matcher::regName[reg], offset); | |
| 1362 } | |
| 1363 #endif | |
| 1364 | |
| 1365 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const | |
| 1366 { | |
| 1367 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1368 int reg = ra_->get_encode(this); | |
| 1369 if (offset >= 0x80) { | |
| 1370 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR); | |
| 1371 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1372 emit_rm(cbuf, 0x2, reg & 7, 0x04); | |
| 1373 emit_rm(cbuf, 0x0, 0x04, RSP_enc); | |
| 1374 emit_d32(cbuf, offset); | |
| 1375 } else { | |
| 1376 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR); | |
| 1377 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1378 emit_rm(cbuf, 0x1, reg & 7, 0x04); | |
| 1379 emit_rm(cbuf, 0x0, 0x04, RSP_enc); | |
| 1380 emit_d8(cbuf, offset); | |
| 1381 } | |
| 1382 } | |
| 1383 | |
| 1384 uint BoxLockNode::size(PhaseRegAlloc *ra_) const | |
| 1385 { | |
| 1386 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1387 return (offset < 0x80) ? 5 : 8; // REX | |
| 1388 } | |
| 1389 | |
| 1390 //============================================================================= | |
| 1391 #ifndef PRODUCT | |
| 1392 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const | |
| 1393 { | |
|
12226
7944aba7ba41
8015107: NPG: Use consistent naming for metaspace concepts
ehelin
parents:
12056
diff
changeset
|
1394 if (UseCompressedClassPointers) { |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1567
diff
changeset
|
1395 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass"); |
|
12056
740e263c80c6
8003424: Enable Class Data Sharing for CompressedOops
hseigel
parents:
10171
diff
changeset
|
1396 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1"); |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1567
diff
changeset
|
1397 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check"); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
1398 } else { |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1567
diff
changeset
|
1399 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t" |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1567
diff
changeset
|
1400 "# Inline cache check"); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
1401 } |
| 0 | 1402 st->print_cr("\tjne SharedRuntime::_ic_miss_stub"); |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1567
diff
changeset
|
1403 st->print_cr("\tnop\t# nops to align entry point"); |
| 0 | 1404 } |
| 1405 #endif | |
| 1406 | |
| 1407 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const | |
| 1408 { | |
| 1409 MacroAssembler masm(&cbuf); | |
| 1748 | 1410 uint insts_size = cbuf.insts_size(); |
|
12226
7944aba7ba41
8015107: NPG: Use consistent naming for metaspace concepts
ehelin
parents:
12056
diff
changeset
|
1411 if (UseCompressedClassPointers) { |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
1412 masm.load_klass(rscratch1, j_rarg0); |
| 304 | 1413 masm.cmpptr(rax, rscratch1); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
1414 } else { |
| 304 | 1415 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes())); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
1416 } |
| 0 | 1417 |
| 1418 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub())); | |
| 1419 | |
| 1420 /* WARNING these NOPs are critical so that verified entry point is properly | |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1567
diff
changeset
|
1421 4 bytes aligned for patching by NativeJump::patch_verified_entry() */ |
| 1748 | 1422 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3); |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1567
diff
changeset
|
1423 if (OptoBreakpoint) { |
| 0 | 1424 // Leave space for int3 |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1567
diff
changeset
|
1425 nops_cnt -= 1; |
| 0 | 1426 } |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1567
diff
changeset
|
1427 nops_cnt &= 0x3; // Do not add nops if code is aligned. |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1567
diff
changeset
|
1428 if (nops_cnt > 0) |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1567
diff
changeset
|
1429 masm.nop(nops_cnt); |
| 0 | 1430 } |
| 1431 | |
| 1432 uint MachUEPNode::size(PhaseRegAlloc* ra_) const | |
| 1433 { | |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1567
diff
changeset
|
1434 return MachNode::size(ra_); // too many variables; just compute it |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1567
diff
changeset
|
1435 // the hard way |
| 0 | 1436 } |
| 1437 | |
| 1438 | |
| 1439 //============================================================================= | |
| 1440 uint size_exception_handler() | |
| 1441 { | |
| 1442 // NativeCall instruction size is the same as NativeJump. | |
| 1443 // Note that this value is also credited (in output.cpp) to | |
| 1444 // the size of the code section. | |
| 1445 return NativeJump::instruction_size; | |
| 1446 } | |
| 1447 | |
| 1448 // Emit exception handler code. | |
| 1449 int emit_exception_handler(CodeBuffer& cbuf) | |
| 1450 { | |
| 1451 | |
| 1748 | 1452 // Note that the code buffer's insts_mark is always relative to insts. |
| 0 | 1453 // That's why we must use the macroassembler to generate a handler. |
| 1454 MacroAssembler _masm(&cbuf); | |
| 1455 address base = | |
| 1456 __ start_a_stub(size_exception_handler()); | |
| 1457 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1458 int offset = __ offset(); | |
| 1748 | 1459 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point())); |
| 0 | 1460 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); |
| 1461 __ end_a_stub(); | |
| 1462 return offset; | |
| 1463 } | |
| 1464 | |
| 1465 uint size_deopt_handler() | |
| 1466 { | |
| 1467 // three 5 byte instructions | |
| 1468 return 15; | |
| 1469 } | |
| 1470 | |
| 1471 // Emit deopt handler code. | |
| 1472 int emit_deopt_handler(CodeBuffer& cbuf) | |
| 1473 { | |
| 1474 | |
| 1748 | 1475 // Note that the code buffer's insts_mark is always relative to insts. |
| 0 | 1476 // That's why we must use the macroassembler to generate a handler. |
| 1477 MacroAssembler _masm(&cbuf); | |
| 1478 address base = | |
| 1479 __ start_a_stub(size_deopt_handler()); | |
| 1480 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1481 int offset = __ offset(); | |
| 1482 address the_pc = (address) __ pc(); | |
| 1483 Label next; | |
| 1484 // push a "the_pc" on the stack without destroying any registers | |
| 1485 // as they all may be live. | |
| 1486 | |
| 1487 // push address of "next" | |
| 1488 __ call(next, relocInfo::none); // reloc none is fine since it is a disp32 | |
| 1489 __ bind(next); | |
| 1490 // adjust it so it matches "the_pc" | |
| 304 | 1491 __ subptr(Address(rsp, 0), __ offset() - offset); |
| 0 | 1492 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); |
| 1493 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); | |
| 1494 __ end_a_stub(); | |
| 1495 return offset; | |
| 1496 } | |
| 1497 | |
| 1498 int Matcher::regnum_to_fpu_offset(int regnum) | |
| 1499 { | |
| 1500 return regnum - 32; // The FP registers are in the second chunk | |
| 1501 } | |
| 1502 | |
| 1503 // This is UltraSparc specific, true just means we have fast l2f conversion | |
| 1504 const bool Matcher::convL2FSupported(void) { | |
| 1505 return true; | |
| 1506 } | |
| 1507 | |
| 1508 // Is this branch offset short enough that a short branch can be used? | |
| 1509 // | |
| 1510 // NOTE: If the platform does not provide any short branch variants, then | |
| 1511 // this method should return false for offset 0. | |
| 3851 | 1512 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { |
| 1513 // The passed offset is relative to address of the branch. | |
| 1514 // On 86 a branch displacement is calculated relative to address | |
| 1515 // of a next instruction. | |
| 1516 offset -= br_size; | |
| 1517 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1518 // the short version of jmpConUCF2 contains multiple branches, |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1519 // making the reach slightly less |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1520 if (rule == jmpConUCF2_rule) |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1521 return (-126 <= offset && offset <= 125); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
1522 return (-128 <= offset && offset <= 127); |
| 0 | 1523 } |
| 1524 | |
| 1525 const bool Matcher::isSimpleConstant64(jlong value) { | |
| 1526 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. | |
| 1527 //return value == (int) value; // Cf. storeImmL and immL32. | |
| 1528 | |
| 1529 // Probably always true, even if a temp register is required. | |
| 1530 return true; | |
| 1531 } | |
| 1532 | |
| 1533 // The ecx parameter to rep stosq for the ClearArray node is in words. | |
| 1534 const bool Matcher::init_array_count_is_in_bytes = false; | |
| 1535 | |
| 1536 // Threshold size for cleararray. | |
| 1537 const int Matcher::init_array_short_size = 8 * BytesPerLong; | |
| 1538 | |
| 4047 | 1539 // No additional cost for CMOVL. |
| 1540 const int Matcher::long_cmove_cost() { return 0; } | |
| 1541 | |
| 1542 // No CMOVF/CMOVD with SSE2 | |
| 1543 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; } | |
| 1544 | |
| 0 | 1545 // Should the Matcher clone shifts on addressing modes, expecting them |
| 1546 // to be subsumed into complex addressing expressions or compute them | |
| 1547 // into registers? True for Intel but false for most RISCs | |
| 1548 const bool Matcher::clone_shift_expressions = true; | |
| 1549 | |
|
2401
7e88bdae86ec
7029017: Additional architecture support for c2 compiler
roland
parents:
2320
diff
changeset
|
1550 // Do we need to mask the count passed to shift instructions or does |
|
7e88bdae86ec
7029017: Additional architecture support for c2 compiler
roland
parents:
2320
diff
changeset
|
1551 // the cpu only look at the lower 5/6 bits anyway? |
|
7e88bdae86ec
7029017: Additional architecture support for c2 compiler
roland
parents:
2320
diff
changeset
|
1552 const bool Matcher::need_masked_shift_count = false; |
|
7e88bdae86ec
7029017: Additional architecture support for c2 compiler
roland
parents:
2320
diff
changeset
|
1553 |
|
1575
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1571
diff
changeset
|
1554 bool Matcher::narrow_oop_use_complex_address() { |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1571
diff
changeset
|
1555 assert(UseCompressedOops, "only for compressed oops code"); |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1571
diff
changeset
|
1556 return (LogMinObjAlignmentInBytes <= 3); |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1571
diff
changeset
|
1557 } |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1571
diff
changeset
|
1558 |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
1559 bool Matcher::narrow_klass_use_complex_address() { |
|
12226
7944aba7ba41
8015107: NPG: Use consistent naming for metaspace concepts
ehelin
parents:
12056
diff
changeset
|
1560 assert(UseCompressedClassPointers, "only for compressed klass code"); |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
1561 return (LogKlassAlignmentInBytes <= 3); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
1562 } |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
1563 |
| 0 | 1564 // Is it better to copy float constants, or load them directly from |
| 1565 // memory? Intel can load a float constant from a direct address, | |
| 1566 // requiring no extra registers. Most RISCs will have to materialize | |
| 1567 // an address into a register first, so they would do better to copy | |
| 1568 // the constant from stack. | |
| 1569 const bool Matcher::rematerialize_float_constants = true; // XXX | |
| 1570 | |
| 1571 // If CPU can load and store mis-aligned doubles directly then no | |
| 1572 // fixup is needed. Else we split the double into 2 integer pieces | |
| 1573 // and move it piece-by-piece. Only happens when passing doubles into | |
| 1574 // C code as the Java calling convention forces doubles to be aligned. | |
| 1575 const bool Matcher::misaligned_doubles_ok = true; | |
| 1576 | |
| 1577 // No-op on amd64 | |
| 1578 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {} | |
| 1579 | |
| 1580 // Advertise here if the CPU requires explicit rounding operations to | |
| 1581 // implement the UseStrictFP mode. | |
| 1582 const bool Matcher::strict_fp_requires_explicit_rounding = true; | |
| 1583 | |
|
1274
2883969d09e7
6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
parents:
1137
diff
changeset
|
1584 // Are floats conerted to double when stored to stack during deoptimization? |
|
2883969d09e7
6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
parents:
1137
diff
changeset
|
1585 // On x64 it is stored without convertion so we can use normal access. |
|
2883969d09e7
6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
parents:
1137
diff
changeset
|
1586 bool Matcher::float_in_double() { return false; } |
|
2883969d09e7
6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
parents:
1137
diff
changeset
|
1587 |
| 0 | 1588 // Do ints take an entire long register or just half? |
| 1589 const bool Matcher::int_in_long = true; | |
| 1590 | |
| 1591 // Return whether or not this register is ever used as an argument. | |
| 1592 // This function is used on startup to build the trampoline stubs in | |
| 1593 // generateOptoStub. Registers not mentioned will be killed by the VM | |
| 1594 // call in the trampoline, and arguments in those registers not be | |
| 1595 // available to the callee. | |
| 1596 bool Matcher::can_be_java_arg(int reg) | |
| 1597 { | |
| 1598 return | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1599 reg == RDI_num || reg == RDI_H_num || |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1600 reg == RSI_num || reg == RSI_H_num || |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1601 reg == RDX_num || reg == RDX_H_num || |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1602 reg == RCX_num || reg == RCX_H_num || |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1603 reg == R8_num || reg == R8_H_num || |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1604 reg == R9_num || reg == R9_H_num || |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1605 reg == R12_num || reg == R12_H_num || |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1606 reg == XMM0_num || reg == XMM0b_num || |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1607 reg == XMM1_num || reg == XMM1b_num || |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1608 reg == XMM2_num || reg == XMM2b_num || |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1609 reg == XMM3_num || reg == XMM3b_num || |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1610 reg == XMM4_num || reg == XMM4b_num || |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1611 reg == XMM5_num || reg == XMM5b_num || |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1612 reg == XMM6_num || reg == XMM6b_num || |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
1613 reg == XMM7_num || reg == XMM7b_num; |
| 0 | 1614 } |
| 1615 | |
| 1616 bool Matcher::is_spillable_arg(int reg) | |
| 1617 { | |
| 1618 return can_be_java_arg(reg); | |
| 1619 } | |
| 1620 | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1827
diff
changeset
|
1621 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) { |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1827
diff
changeset
|
1622 // In 64 bit mode a code which use multiply when |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1827
diff
changeset
|
1623 // devisor is constant is faster than hardware |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1827
diff
changeset
|
1624 // DIV instruction (it uses MulHiL). |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1827
diff
changeset
|
1625 return false; |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1827
diff
changeset
|
1626 } |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1827
diff
changeset
|
1627 |
| 0 | 1628 // Register for DIVI projection of divmodI |
| 1629 RegMask Matcher::divI_proj_mask() { | |
|
4121
db2e64ca2d5a
7090968: Allow adlc register class to depend on runtime conditions
roland
parents:
4114
diff
changeset
|
1630 return INT_RAX_REG_mask(); |
| 0 | 1631 } |
| 1632 | |
| 1633 // Register for MODI projection of divmodI | |
| 1634 RegMask Matcher::modI_proj_mask() { | |
|
4121
db2e64ca2d5a
7090968: Allow adlc register class to depend on runtime conditions
roland
parents:
4114
diff
changeset
|
1635 return INT_RDX_REG_mask(); |
| 0 | 1636 } |
| 1637 | |
| 1638 // Register for DIVL projection of divmodL | |
| 1639 RegMask Matcher::divL_proj_mask() { | |
|
4121
db2e64ca2d5a
7090968: Allow adlc register class to depend on runtime conditions
roland
parents:
4114
diff
changeset
|
1640 return LONG_RAX_REG_mask(); |
| 0 | 1641 } |
| 1642 | |
| 1643 // Register for MODL projection of divmodL | |
| 1644 RegMask Matcher::modL_proj_mask() { | |
|
4121
db2e64ca2d5a
7090968: Allow adlc register class to depend on runtime conditions
roland
parents:
4114
diff
changeset
|
1645 return LONG_RDX_REG_mask(); |
| 0 | 1646 } |
| 1647 | |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
1648 const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
|
4121
db2e64ca2d5a
7090968: Allow adlc register class to depend on runtime conditions
roland
parents:
4114
diff
changeset
|
1649 return PTR_RBP_REG_mask(); |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
1650 } |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
1651 |
| 12323 | 1652 const RegMask Matcher::mathExactI_result_proj_mask() { |
| 1653 return INT_RAX_REG_mask(); | |
| 1654 } | |
| 1655 | |
|
12972
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
1656 const RegMask Matcher::mathExactL_result_proj_mask() { |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
1657 return LONG_RAX_REG_mask(); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
1658 } |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
1659 |
| 12323 | 1660 const RegMask Matcher::mathExactI_flags_proj_mask() { |
| 1661 return INT_FLAGS_mask(); | |
| 1662 } | |
| 1663 | |
| 0 | 1664 %} |
| 1665 | |
| 1666 //----------ENCODING BLOCK----------------------------------------------------- | |
| 1667 // This block specifies the encoding classes used by the compiler to | |
| 1668 // output byte streams. Encoding classes are parameterized macros | |
| 1669 // used by Machine Instruction Nodes in order to generate the bit | |
| 1670 // encoding of the instruction. Operands specify their base encoding | |
| 1671 // interface with the interface keyword. There are currently | |
| 1672 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, & | |
| 1673 // COND_INTER. REG_INTER causes an operand to generate a function | |
| 1674 // which returns its register number when queried. CONST_INTER causes | |
| 1675 // an operand to generate a function which returns the value of the | |
| 1676 // constant when queried. MEMORY_INTER causes an operand to generate | |
| 1677 // four functions which return the Base Register, the Index Register, | |
| 1678 // the Scale Value, and the Offset Value of the operand when queried. | |
| 1679 // COND_INTER causes an operand to generate six functions which return | |
| 1680 // the encoding code (ie - encoding bits for the instruction) | |
| 1681 // associated with each basic boolean condition for a conditional | |
| 1682 // instruction. | |
| 1683 // | |
| 1684 // Instructions specify two basic values for encoding. Again, a | |
| 1685 // function is available to check if the constant displacement is an | |
| 1686 // oop. They use the ins_encode keyword to specify their encoding | |
| 1687 // classes (which must be a sequence of enc_class names, and their | |
| 1688 // parameters, specified in the encoding block), and they use the | |
| 1689 // opcode keyword to specify, in order, their primary, secondary, and | |
| 1690 // tertiary opcode. Only the opcode sections which a particular | |
| 1691 // instruction needs for encoding need to be specified. | |
| 1692 encode %{ | |
| 1693 // Build emit functions for each basic byte or larger field in the | |
| 1694 // intel encoding scheme (opcode, rm, sib, immediate), and call them | |
| 1695 // from C++ code in the enc_class source block. Emit functions will | |
| 1696 // live in the main source block for now. In future, we can | |
| 1697 // generalize this by adding a syntax that specifies the sizes of | |
| 1698 // fields in an order, so that the adlc can build the emit functions | |
| 1699 // automagically | |
| 1700 | |
| 1701 // Emit primary opcode | |
| 1702 enc_class OpcP | |
| 1703 %{ | |
| 1704 emit_opcode(cbuf, $primary); | |
| 1705 %} | |
| 1706 | |
| 1707 // Emit secondary opcode | |
| 1708 enc_class OpcS | |
| 1709 %{ | |
| 1710 emit_opcode(cbuf, $secondary); | |
| 1711 %} | |
| 1712 | |
| 1713 // Emit tertiary opcode | |
| 1714 enc_class OpcT | |
| 1715 %{ | |
| 1716 emit_opcode(cbuf, $tertiary); | |
| 1717 %} | |
| 1718 | |
| 1719 // Emit opcode directly | |
| 1720 enc_class Opcode(immI d8) | |
| 1721 %{ | |
| 1722 emit_opcode(cbuf, $d8$$constant); | |
| 1723 %} | |
| 1724 | |
| 1725 // Emit size prefix | |
| 1726 enc_class SizePrefix | |
| 1727 %{ | |
| 1728 emit_opcode(cbuf, 0x66); | |
| 1729 %} | |
| 1730 | |
| 1731 enc_class reg(rRegI reg) | |
| 1732 %{ | |
| 1733 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7); | |
| 1734 %} | |
| 1735 | |
| 1736 enc_class reg_reg(rRegI dst, rRegI src) | |
| 1737 %{ | |
| 1738 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7); | |
| 1739 %} | |
| 1740 | |
| 1741 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src) | |
| 1742 %{ | |
| 1743 emit_opcode(cbuf, $opcode$$constant); | |
| 1744 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7); | |
| 1745 %} | |
| 1746 | |
| 1747 enc_class cdql_enc(no_rax_rdx_RegI div) | |
| 1748 %{ | |
| 1749 // Full implementation of Java idiv and irem; checks for | |
| 1750 // special case as described in JVM spec., p.243 & p.271. | |
| 1751 // | |
| 1752 // normal case special case | |
| 1753 // | |
| 1754 // input : rax: dividend min_int | |
| 1755 // reg: divisor -1 | |
| 1756 // | |
| 1757 // output: rax: quotient (= rax idiv reg) min_int | |
| 1758 // rdx: remainder (= rax irem reg) 0 | |
| 1759 // | |
| 1760 // Code sequnce: | |
| 1761 // | |
| 1762 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax | |
| 1763 // 5: 75 07/08 jne e <normal> | |
| 1764 // 7: 33 d2 xor %edx,%edx | |
| 1765 // [div >= 8 -> offset + 1] | |
| 1766 // [REX_B] | |
| 1767 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div | |
| 1768 // c: 74 03/04 je 11 <done> | |
| 1769 // 000000000000000e <normal>: | |
| 1770 // e: 99 cltd | |
| 1771 // [div >= 8 -> offset + 1] | |
| 1772 // [REX_B] | |
| 1773 // f: f7 f9 idiv $div | |
| 1774 // 0000000000000011 <done>: | |
| 1775 | |
| 1776 // cmp $0x80000000,%eax | |
| 1777 emit_opcode(cbuf, 0x3d); | |
| 1778 emit_d8(cbuf, 0x00); | |
| 1779 emit_d8(cbuf, 0x00); | |
| 1780 emit_d8(cbuf, 0x00); | |
| 1781 emit_d8(cbuf, 0x80); | |
| 1782 | |
| 1783 // jne e <normal> | |
| 1784 emit_opcode(cbuf, 0x75); | |
| 1785 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08); | |
| 1786 | |
| 1787 // xor %edx,%edx | |
| 1788 emit_opcode(cbuf, 0x33); | |
| 1789 emit_d8(cbuf, 0xD2); | |
| 1790 | |
| 1791 // cmp $0xffffffffffffffff,%ecx | |
| 1792 if ($div$$reg >= 8) { | |
| 1793 emit_opcode(cbuf, Assembler::REX_B); | |
| 1794 } | |
| 1795 emit_opcode(cbuf, 0x83); | |
| 1796 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7); | |
| 1797 emit_d8(cbuf, 0xFF); | |
| 1798 | |
| 1799 // je 11 <done> | |
| 1800 emit_opcode(cbuf, 0x74); | |
| 1801 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04); | |
| 1802 | |
| 1803 // <normal> | |
| 1804 // cltd | |
| 1805 emit_opcode(cbuf, 0x99); | |
| 1806 | |
| 1807 // idivl (note: must be emitted by the user of this rule) | |
| 1808 // <done> | |
| 1809 %} | |
| 1810 | |
| 1811 enc_class cdqq_enc(no_rax_rdx_RegL div) | |
| 1812 %{ | |
| 1813 // Full implementation of Java ldiv and lrem; checks for | |
| 1814 // special case as described in JVM spec., p.243 & p.271. | |
| 1815 // | |
| 1816 // normal case special case | |
| 1817 // | |
| 1818 // input : rax: dividend min_long | |
| 1819 // reg: divisor -1 | |
| 1820 // | |
| 1821 // output: rax: quotient (= rax idiv reg) min_long | |
| 1822 // rdx: remainder (= rax irem reg) 0 | |
| 1823 // | |
| 1824 // Code sequnce: | |
| 1825 // | |
| 1826 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx | |
| 1827 // 7: 00 00 80 | |
| 1828 // a: 48 39 d0 cmp %rdx,%rax | |
| 1829 // d: 75 08 jne 17 <normal> | |
| 1830 // f: 33 d2 xor %edx,%edx | |
| 1831 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div | |
| 1832 // 15: 74 05 je 1c <done> | |
| 1833 // 0000000000000017 <normal>: | |
| 1834 // 17: 48 99 cqto | |
| 1835 // 19: 48 f7 f9 idiv $div | |
| 1836 // 000000000000001c <done>: | |
| 1837 | |
| 1838 // mov $0x8000000000000000,%rdx | |
| 1839 emit_opcode(cbuf, Assembler::REX_W); | |
| 1840 emit_opcode(cbuf, 0xBA); | |
| 1841 emit_d8(cbuf, 0x00); | |
| 1842 emit_d8(cbuf, 0x00); | |
| 1843 emit_d8(cbuf, 0x00); | |
| 1844 emit_d8(cbuf, 0x00); | |
| 1845 emit_d8(cbuf, 0x00); | |
| 1846 emit_d8(cbuf, 0x00); | |
| 1847 emit_d8(cbuf, 0x00); | |
| 1848 emit_d8(cbuf, 0x80); | |
| 1849 | |
| 1850 // cmp %rdx,%rax | |
| 1851 emit_opcode(cbuf, Assembler::REX_W); | |
| 1852 emit_opcode(cbuf, 0x39); | |
| 1853 emit_d8(cbuf, 0xD0); | |
| 1854 | |
| 1855 // jne 17 <normal> | |
| 1856 emit_opcode(cbuf, 0x75); | |
| 1857 emit_d8(cbuf, 0x08); | |
| 1858 | |
| 1859 // xor %edx,%edx | |
| 1860 emit_opcode(cbuf, 0x33); | |
| 1861 emit_d8(cbuf, 0xD2); | |
| 1862 | |
| 1863 // cmp $0xffffffffffffffff,$div | |
| 1864 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB); | |
| 1865 emit_opcode(cbuf, 0x83); | |
| 1866 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7); | |
| 1867 emit_d8(cbuf, 0xFF); | |
| 1868 | |
| 1869 // je 1e <done> | |
| 1870 emit_opcode(cbuf, 0x74); | |
| 1871 emit_d8(cbuf, 0x05); | |
| 1872 | |
| 1873 // <normal> | |
| 1874 // cqto | |
| 1875 emit_opcode(cbuf, Assembler::REX_W); | |
| 1876 emit_opcode(cbuf, 0x99); | |
| 1877 | |
| 1878 // idivq (note: must be emitted by the user of this rule) | |
| 1879 // <done> | |
| 1880 %} | |
| 1881 | |
| 1882 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension | |
| 1883 enc_class OpcSE(immI imm) | |
| 1884 %{ | |
| 1885 // Emit primary opcode and set sign-extend bit | |
| 1886 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1887 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
| 1888 emit_opcode(cbuf, $primary | 0x02); | |
| 1889 } else { | |
| 1890 // 32-bit immediate | |
| 1891 emit_opcode(cbuf, $primary); | |
| 1892 } | |
| 1893 %} | |
| 1894 | |
| 1895 enc_class OpcSErm(rRegI dst, immI imm) | |
| 1896 %{ | |
| 1897 // OpcSEr/m | |
| 1898 int dstenc = $dst$$reg; | |
| 1899 if (dstenc >= 8) { | |
| 1900 emit_opcode(cbuf, Assembler::REX_B); | |
| 1901 dstenc -= 8; | |
| 1902 } | |
| 1903 // Emit primary opcode and set sign-extend bit | |
| 1904 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1905 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
| 1906 emit_opcode(cbuf, $primary | 0x02); | |
| 1907 } else { | |
| 1908 // 32-bit immediate | |
| 1909 emit_opcode(cbuf, $primary); | |
| 1910 } | |
| 1911 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 1912 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
| 1913 %} | |
| 1914 | |
| 1915 enc_class OpcSErm_wide(rRegL dst, immI imm) | |
| 1916 %{ | |
| 1917 // OpcSEr/m | |
| 1918 int dstenc = $dst$$reg; | |
| 1919 if (dstenc < 8) { | |
| 1920 emit_opcode(cbuf, Assembler::REX_W); | |
| 1921 } else { | |
| 1922 emit_opcode(cbuf, Assembler::REX_WB); | |
| 1923 dstenc -= 8; | |
| 1924 } | |
| 1925 // Emit primary opcode and set sign-extend bit | |
| 1926 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1927 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
| 1928 emit_opcode(cbuf, $primary | 0x02); | |
| 1929 } else { | |
| 1930 // 32-bit immediate | |
| 1931 emit_opcode(cbuf, $primary); | |
| 1932 } | |
| 1933 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 1934 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
| 1935 %} | |
| 1936 | |
| 1937 enc_class Con8or32(immI imm) | |
| 1938 %{ | |
| 1939 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1940 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
| 1941 $$$emit8$imm$$constant; | |
| 1942 } else { | |
| 1943 // 32-bit immediate | |
| 1944 $$$emit32$imm$$constant; | |
| 1945 } | |
| 1946 %} | |
| 1947 | |
| 1948 enc_class opc2_reg(rRegI dst) | |
| 1949 %{ | |
| 1950 // BSWAP | |
| 1951 emit_cc(cbuf, $secondary, $dst$$reg); | |
| 1952 %} | |
| 1953 | |
| 1954 enc_class opc3_reg(rRegI dst) | |
| 1955 %{ | |
| 1956 // BSWAP | |
| 1957 emit_cc(cbuf, $tertiary, $dst$$reg); | |
| 1958 %} | |
| 1959 | |
| 1960 enc_class reg_opc(rRegI div) | |
| 1961 %{ | |
| 1962 // INC, DEC, IDIV, IMOD, JMP indirect, ... | |
| 1963 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7); | |
| 1964 %} | |
| 1965 | |
| 1966 enc_class enc_cmov(cmpOp cop) | |
| 1967 %{ | |
| 1968 // CMOV | |
| 1969 $$$emit8$primary; | |
| 1970 emit_cc(cbuf, $secondary, $cop$$cmpcode); | |
| 1971 %} | |
| 1972 | |
| 1973 enc_class enc_PartialSubtypeCheck() | |
| 1974 %{ | |
| 1975 Register Rrdi = as_Register(RDI_enc); // result register | |
| 1976 Register Rrax = as_Register(RAX_enc); // super class | |
| 1977 Register Rrcx = as_Register(RCX_enc); // killed | |
| 1978 Register Rrsi = as_Register(RSI_enc); // sub class | |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1979 Label miss; |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1980 const bool set_cond_codes = true; |
| 0 | 1981 |
| 1982 MacroAssembler _masm(&cbuf); | |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1983 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1984 NULL, &miss, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
1985 /*set_cond_codes:*/ true); |
| 0 | 1986 if ($primary) { |
| 304 | 1987 __ xorptr(Rrdi, Rrdi); |
| 0 | 1988 } |
| 1989 __ bind(miss); | |
| 1990 %} | |
| 1991 | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
1992 enc_class clear_avx %{ |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
1993 debug_only(int off0 = cbuf.insts_size()); |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
1994 if (ra_->C->max_vector_size() > 16) { |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
1995 // Clear upper bits of YMM registers when current compiled code uses |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
1996 // wide vectors to avoid AVX <-> SSE transition penalty during call. |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
1997 MacroAssembler _masm(&cbuf); |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
1998 __ vzeroupper(); |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
1999 } |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
2000 debug_only(int off1 = cbuf.insts_size()); |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
2001 assert(off1 - off0 == clear_avx_size(), "correct size prediction"); |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
2002 %} |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
2003 |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
2004 enc_class Java_To_Runtime(method meth) %{ |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
2005 // No relocation needed |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
2006 MacroAssembler _masm(&cbuf); |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
2007 __ mov64(r10, (int64_t) $meth$$method); |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
2008 __ call(r10); |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
2009 %} |
|
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
2010 |
| 0 | 2011 enc_class Java_To_Interpreter(method meth) |
| 2012 %{ | |
| 2013 // CALL Java_To_Interpreter | |
| 2014 // This is the instruction starting address for relocation info. | |
| 1748 | 2015 cbuf.set_insts_mark(); |
| 0 | 2016 $$$emit8$primary; |
| 2017 // CALL directly to the runtime | |
| 2018 emit_d32_reloc(cbuf, | |
| 1748 | 2019 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4), |
| 0 | 2020 runtime_call_Relocation::spec(), |
| 2021 RELOC_DISP32); | |
| 2022 %} | |
| 2023 | |
| 2024 enc_class Java_Static_Call(method meth) | |
| 2025 %{ | |
| 2026 // JAVA STATIC CALL | |
| 2027 // CALL to fixup routine. Fixup routine uses ScopeDesc info to | |
| 2028 // determine who we intended to call. | |
| 1748 | 2029 cbuf.set_insts_mark(); |
| 0 | 2030 $$$emit8$primary; |
| 2031 | |
| 2032 if (!_method) { | |
| 2033 emit_d32_reloc(cbuf, | |
| 1748 | 2034 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4), |
| 0 | 2035 runtime_call_Relocation::spec(), |
| 2036 RELOC_DISP32); | |
| 2037 } else if (_optimized_virtual) { | |
| 2038 emit_d32_reloc(cbuf, | |
| 1748 | 2039 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4), |
| 0 | 2040 opt_virtual_call_Relocation::spec(), |
| 2041 RELOC_DISP32); | |
| 2042 } else { | |
| 2043 emit_d32_reloc(cbuf, | |
| 1748 | 2044 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4), |
| 0 | 2045 static_call_Relocation::spec(), |
| 2046 RELOC_DISP32); | |
| 2047 } | |
| 2048 if (_method) { | |
|
10168
a6e09d6dd8e5
8003853: specify offset of IC load in java_to_interp stub
dlong
parents:
8873
diff
changeset
|
2049 // Emit stub for static call. |
|
a6e09d6dd8e5
8003853: specify offset of IC load in java_to_interp stub
dlong
parents:
8873
diff
changeset
|
2050 CompiledStaticCall::emit_to_interp_stub(cbuf); |
| 0 | 2051 } |
| 2052 %} | |
| 2053 | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
2054 enc_class Java_Dynamic_Call(method meth) %{ |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
2055 MacroAssembler _masm(&cbuf); |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
2056 __ ic_call((address)$meth$$method); |
| 0 | 2057 %} |
| 2058 | |
| 2059 enc_class Java_Compiled_Call(method meth) | |
| 2060 %{ | |
| 2061 // JAVA COMPILED CALL | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
2062 int disp = in_bytes(Method:: from_compiled_offset()); |
| 0 | 2063 |
| 2064 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!! | |
| 2065 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small"); | |
| 2066 | |
| 2067 // callq *disp(%rax) | |
| 1748 | 2068 cbuf.set_insts_mark(); |
| 0 | 2069 $$$emit8$primary; |
| 2070 if (disp < 0x80) { | |
| 2071 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte | |
| 2072 emit_d8(cbuf, disp); // Displacement | |
| 2073 } else { | |
| 2074 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte | |
| 2075 emit_d32(cbuf, disp); // Displacement | |
| 2076 } | |
| 2077 %} | |
| 2078 | |
| 2079 enc_class reg_opc_imm(rRegI dst, immI8 shift) | |
| 2080 %{ | |
| 2081 // SAL, SAR, SHR | |
| 2082 int dstenc = $dst$$reg; | |
| 2083 if (dstenc >= 8) { | |
| 2084 emit_opcode(cbuf, Assembler::REX_B); | |
| 2085 dstenc -= 8; | |
| 2086 } | |
| 2087 $$$emit8$primary; | |
| 2088 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
| 2089 $$$emit8$shift$$constant; | |
| 2090 %} | |
| 2091 | |
| 2092 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift) | |
| 2093 %{ | |
| 2094 // SAL, SAR, SHR | |
| 2095 int dstenc = $dst$$reg; | |
| 2096 if (dstenc < 8) { | |
| 2097 emit_opcode(cbuf, Assembler::REX_W); | |
| 2098 } else { | |
| 2099 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2100 dstenc -= 8; | |
| 2101 } | |
| 2102 $$$emit8$primary; | |
| 2103 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
| 2104 $$$emit8$shift$$constant; | |
| 2105 %} | |
| 2106 | |
| 2107 enc_class load_immI(rRegI dst, immI src) | |
| 2108 %{ | |
| 2109 int dstenc = $dst$$reg; | |
| 2110 if (dstenc >= 8) { | |
| 2111 emit_opcode(cbuf, Assembler::REX_B); | |
| 2112 dstenc -= 8; | |
| 2113 } | |
| 2114 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2115 $$$emit32$src$$constant; | |
| 2116 %} | |
| 2117 | |
| 2118 enc_class load_immL(rRegL dst, immL src) | |
| 2119 %{ | |
| 2120 int dstenc = $dst$$reg; | |
| 2121 if (dstenc < 8) { | |
| 2122 emit_opcode(cbuf, Assembler::REX_W); | |
| 2123 } else { | |
| 2124 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2125 dstenc -= 8; | |
| 2126 } | |
| 2127 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2128 emit_d64(cbuf, $src$$constant); | |
| 2129 %} | |
| 2130 | |
| 2131 enc_class load_immUL32(rRegL dst, immUL32 src) | |
| 2132 %{ | |
| 2133 // same as load_immI, but this time we care about zeroes in the high word | |
| 2134 int dstenc = $dst$$reg; | |
| 2135 if (dstenc >= 8) { | |
| 2136 emit_opcode(cbuf, Assembler::REX_B); | |
| 2137 dstenc -= 8; | |
| 2138 } | |
| 2139 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2140 $$$emit32$src$$constant; | |
| 2141 %} | |
| 2142 | |
| 2143 enc_class load_immL32(rRegL dst, immL32 src) | |
| 2144 %{ | |
| 2145 int dstenc = $dst$$reg; | |
| 2146 if (dstenc < 8) { | |
| 2147 emit_opcode(cbuf, Assembler::REX_W); | |
| 2148 } else { | |
| 2149 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2150 dstenc -= 8; | |
| 2151 } | |
| 2152 emit_opcode(cbuf, 0xC7); | |
| 2153 emit_rm(cbuf, 0x03, 0x00, dstenc); | |
| 2154 $$$emit32$src$$constant; | |
| 2155 %} | |
| 2156 | |
| 2157 enc_class load_immP31(rRegP dst, immP32 src) | |
| 2158 %{ | |
| 2159 // same as load_immI, but this time we care about zeroes in the high word | |
| 2160 int dstenc = $dst$$reg; | |
| 2161 if (dstenc >= 8) { | |
| 2162 emit_opcode(cbuf, Assembler::REX_B); | |
| 2163 dstenc -= 8; | |
| 2164 } | |
| 2165 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2166 $$$emit32$src$$constant; | |
| 2167 %} | |
| 2168 | |
| 2169 enc_class load_immP(rRegP dst, immP src) | |
| 2170 %{ | |
| 2171 int dstenc = $dst$$reg; | |
| 2172 if (dstenc < 8) { | |
| 2173 emit_opcode(cbuf, Assembler::REX_W); | |
| 2174 } else { | |
| 2175 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2176 dstenc -= 8; | |
| 2177 } | |
| 2178 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2179 // This next line should be generated from ADLC | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
2180 if ($src->constant_reloc() != relocInfo::none) { |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
2181 emit_d64_reloc(cbuf, $src$$constant, $src->constant_reloc(), RELOC_IMM64); |
| 0 | 2182 } else { |
| 2183 emit_d64(cbuf, $src$$constant); | |
| 2184 } | |
| 2185 %} | |
| 2186 | |
| 2187 enc_class Con32(immI src) | |
| 2188 %{ | |
| 2189 // Output immediate | |
| 2190 $$$emit32$src$$constant; | |
| 2191 %} | |
| 2192 | |
| 2193 enc_class Con32F_as_bits(immF src) | |
| 2194 %{ | |
| 2195 // Output Float immediate bits | |
| 2196 jfloat jf = $src$$constant; | |
| 2197 jint jf_as_bits = jint_cast(jf); | |
| 2198 emit_d32(cbuf, jf_as_bits); | |
| 2199 %} | |
| 2200 | |
| 2201 enc_class Con16(immI src) | |
| 2202 %{ | |
| 2203 // Output immediate | |
| 2204 $$$emit16$src$$constant; | |
| 2205 %} | |
| 2206 | |
| 2207 // How is this different from Con32??? XXX | |
| 2208 enc_class Con_d32(immI src) | |
| 2209 %{ | |
| 2210 emit_d32(cbuf,$src$$constant); | |
| 2211 %} | |
| 2212 | |
| 2213 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI) | |
| 2214 // Output immediate memory reference | |
| 2215 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 ); | |
| 2216 emit_d32(cbuf, 0x00); | |
| 2217 %} | |
| 2218 | |
| 2219 enc_class lock_prefix() | |
| 2220 %{ | |
| 2221 if (os::is_MP()) { | |
| 2222 emit_opcode(cbuf, 0xF0); // lock | |
| 2223 } | |
| 2224 %} | |
| 2225 | |
| 2226 enc_class REX_mem(memory mem) | |
| 2227 %{ | |
| 2228 if ($mem$$base >= 8) { | |
| 2229 if ($mem$$index < 8) { | |
| 2230 emit_opcode(cbuf, Assembler::REX_B); | |
| 2231 } else { | |
| 2232 emit_opcode(cbuf, Assembler::REX_XB); | |
| 2233 } | |
| 2234 } else { | |
| 2235 if ($mem$$index >= 8) { | |
| 2236 emit_opcode(cbuf, Assembler::REX_X); | |
| 2237 } | |
| 2238 } | |
| 2239 %} | |
| 2240 | |
| 2241 enc_class REX_mem_wide(memory mem) | |
| 2242 %{ | |
| 2243 if ($mem$$base >= 8) { | |
| 2244 if ($mem$$index < 8) { | |
| 2245 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2246 } else { | |
| 2247 emit_opcode(cbuf, Assembler::REX_WXB); | |
| 2248 } | |
| 2249 } else { | |
| 2250 if ($mem$$index < 8) { | |
| 2251 emit_opcode(cbuf, Assembler::REX_W); | |
| 2252 } else { | |
| 2253 emit_opcode(cbuf, Assembler::REX_WX); | |
| 2254 } | |
| 2255 } | |
| 2256 %} | |
| 2257 | |
| 2258 // for byte regs | |
| 2259 enc_class REX_breg(rRegI reg) | |
| 2260 %{ | |
| 2261 if ($reg$$reg >= 4) { | |
| 2262 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B); | |
| 2263 } | |
| 2264 %} | |
| 2265 | |
| 2266 // for byte regs | |
| 2267 enc_class REX_reg_breg(rRegI dst, rRegI src) | |
| 2268 %{ | |
| 2269 if ($dst$$reg < 8) { | |
| 2270 if ($src$$reg >= 4) { | |
| 2271 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B); | |
| 2272 } | |
| 2273 } else { | |
| 2274 if ($src$$reg < 8) { | |
| 2275 emit_opcode(cbuf, Assembler::REX_R); | |
| 2276 } else { | |
| 2277 emit_opcode(cbuf, Assembler::REX_RB); | |
| 2278 } | |
| 2279 } | |
| 2280 %} | |
| 2281 | |
| 2282 // for byte regs | |
| 2283 enc_class REX_breg_mem(rRegI reg, memory mem) | |
| 2284 %{ | |
| 2285 if ($reg$$reg < 8) { | |
| 2286 if ($mem$$base < 8) { | |
| 2287 if ($mem$$index >= 8) { | |
| 2288 emit_opcode(cbuf, Assembler::REX_X); | |
| 2289 } else if ($reg$$reg >= 4) { | |
| 2290 emit_opcode(cbuf, Assembler::REX); | |
| 2291 } | |
| 2292 } else { | |
| 2293 if ($mem$$index < 8) { | |
| 2294 emit_opcode(cbuf, Assembler::REX_B); | |
| 2295 } else { | |
| 2296 emit_opcode(cbuf, Assembler::REX_XB); | |
| 2297 } | |
| 2298 } | |
| 2299 } else { | |
| 2300 if ($mem$$base < 8) { | |
| 2301 if ($mem$$index < 8) { | |
| 2302 emit_opcode(cbuf, Assembler::REX_R); | |
| 2303 } else { | |
| 2304 emit_opcode(cbuf, Assembler::REX_RX); | |
| 2305 } | |
| 2306 } else { | |
| 2307 if ($mem$$index < 8) { | |
| 2308 emit_opcode(cbuf, Assembler::REX_RB); | |
| 2309 } else { | |
| 2310 emit_opcode(cbuf, Assembler::REX_RXB); | |
| 2311 } | |
| 2312 } | |
| 2313 } | |
| 2314 %} | |
| 2315 | |
| 2316 enc_class REX_reg(rRegI reg) | |
| 2317 %{ | |
| 2318 if ($reg$$reg >= 8) { | |
| 2319 emit_opcode(cbuf, Assembler::REX_B); | |
| 2320 } | |
| 2321 %} | |
| 2322 | |
| 2323 enc_class REX_reg_wide(rRegI reg) | |
| 2324 %{ | |
| 2325 if ($reg$$reg < 8) { | |
| 2326 emit_opcode(cbuf, Assembler::REX_W); | |
| 2327 } else { | |
| 2328 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2329 } | |
| 2330 %} | |
| 2331 | |
| 2332 enc_class REX_reg_reg(rRegI dst, rRegI src) | |
| 2333 %{ | |
| 2334 if ($dst$$reg < 8) { | |
| 2335 if ($src$$reg >= 8) { | |
| 2336 emit_opcode(cbuf, Assembler::REX_B); | |
| 2337 } | |
| 2338 } else { | |
| 2339 if ($src$$reg < 8) { | |
| 2340 emit_opcode(cbuf, Assembler::REX_R); | |
| 2341 } else { | |
| 2342 emit_opcode(cbuf, Assembler::REX_RB); | |
| 2343 } | |
| 2344 } | |
| 2345 %} | |
| 2346 | |
| 2347 enc_class REX_reg_reg_wide(rRegI dst, rRegI src) | |
| 2348 %{ | |
| 2349 if ($dst$$reg < 8) { | |
| 2350 if ($src$$reg < 8) { | |
| 2351 emit_opcode(cbuf, Assembler::REX_W); | |
| 2352 } else { | |
| 2353 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2354 } | |
| 2355 } else { | |
| 2356 if ($src$$reg < 8) { | |
| 2357 emit_opcode(cbuf, Assembler::REX_WR); | |
| 2358 } else { | |
| 2359 emit_opcode(cbuf, Assembler::REX_WRB); | |
| 2360 } | |
| 2361 } | |
| 2362 %} | |
| 2363 | |
| 2364 enc_class REX_reg_mem(rRegI reg, memory mem) | |
| 2365 %{ | |
| 2366 if ($reg$$reg < 8) { | |
| 2367 if ($mem$$base < 8) { | |
| 2368 if ($mem$$index >= 8) { | |
| 2369 emit_opcode(cbuf, Assembler::REX_X); | |
| 2370 } | |
| 2371 } else { | |
| 2372 if ($mem$$index < 8) { | |
| 2373 emit_opcode(cbuf, Assembler::REX_B); | |
| 2374 } else { | |
| 2375 emit_opcode(cbuf, Assembler::REX_XB); | |
| 2376 } | |
| 2377 } | |
| 2378 } else { | |
| 2379 if ($mem$$base < 8) { | |
| 2380 if ($mem$$index < 8) { | |
| 2381 emit_opcode(cbuf, Assembler::REX_R); | |
| 2382 } else { | |
| 2383 emit_opcode(cbuf, Assembler::REX_RX); | |
| 2384 } | |
| 2385 } else { | |
| 2386 if ($mem$$index < 8) { | |
| 2387 emit_opcode(cbuf, Assembler::REX_RB); | |
| 2388 } else { | |
| 2389 emit_opcode(cbuf, Assembler::REX_RXB); | |
| 2390 } | |
| 2391 } | |
| 2392 } | |
| 2393 %} | |
| 2394 | |
| 2395 enc_class REX_reg_mem_wide(rRegL reg, memory mem) | |
| 2396 %{ | |
| 2397 if ($reg$$reg < 8) { | |
| 2398 if ($mem$$base < 8) { | |
| 2399 if ($mem$$index < 8) { | |
| 2400 emit_opcode(cbuf, Assembler::REX_W); | |
| 2401 } else { | |
| 2402 emit_opcode(cbuf, Assembler::REX_WX); | |
| 2403 } | |
| 2404 } else { | |
| 2405 if ($mem$$index < 8) { | |
| 2406 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2407 } else { | |
| 2408 emit_opcode(cbuf, Assembler::REX_WXB); | |
| 2409 } | |
| 2410 } | |
| 2411 } else { | |
| 2412 if ($mem$$base < 8) { | |
| 2413 if ($mem$$index < 8) { | |
| 2414 emit_opcode(cbuf, Assembler::REX_WR); | |
| 2415 } else { | |
| 2416 emit_opcode(cbuf, Assembler::REX_WRX); | |
| 2417 } | |
| 2418 } else { | |
| 2419 if ($mem$$index < 8) { | |
| 2420 emit_opcode(cbuf, Assembler::REX_WRB); | |
| 2421 } else { | |
| 2422 emit_opcode(cbuf, Assembler::REX_WRXB); | |
| 2423 } | |
| 2424 } | |
| 2425 } | |
| 2426 %} | |
| 2427 | |
| 2428 enc_class reg_mem(rRegI ereg, memory mem) | |
| 2429 %{ | |
| 2430 // High registers handle in encode_RegMem | |
| 2431 int reg = $ereg$$reg; | |
| 2432 int base = $mem$$base; | |
| 2433 int index = $mem$$index; | |
| 2434 int scale = $mem$$scale; | |
| 2435 int disp = $mem$$disp; | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
2436 relocInfo::relocType disp_reloc = $mem->disp_reloc(); |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
2437 |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
2438 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc); |
| 0 | 2439 %} |
| 2440 | |
| 2441 enc_class RM_opc_mem(immI rm_opcode, memory mem) | |
| 2442 %{ | |
| 2443 int rm_byte_opcode = $rm_opcode$$constant; | |
| 2444 | |
| 2445 // High registers handle in encode_RegMem | |
| 2446 int base = $mem$$base; | |
| 2447 int index = $mem$$index; | |
| 2448 int scale = $mem$$scale; | |
| 2449 int displace = $mem$$disp; | |
| 2450 | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
2451 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when |
| 0 | 2452 // working with static |
| 2453 // globals | |
| 2454 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
2455 disp_reloc); |
| 0 | 2456 %} |
| 2457 | |
| 2458 enc_class reg_lea(rRegI dst, rRegI src0, immI src1) | |
| 2459 %{ | |
| 2460 int reg_encoding = $dst$$reg; | |
| 2461 int base = $src0$$reg; // 0xFFFFFFFF indicates no base | |
| 2462 int index = 0x04; // 0x04 indicates no index | |
| 2463 int scale = 0x00; // 0x00 indicates no scale | |
| 2464 int displace = $src1$$constant; // 0x00 indicates no displacement | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
2465 relocInfo::relocType disp_reloc = relocInfo::none; |
| 0 | 2466 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
2467 disp_reloc); |
| 0 | 2468 %} |
| 2469 | |
| 2470 enc_class neg_reg(rRegI dst) | |
| 2471 %{ | |
| 2472 int dstenc = $dst$$reg; | |
| 2473 if (dstenc >= 8) { | |
| 2474 emit_opcode(cbuf, Assembler::REX_B); | |
| 2475 dstenc -= 8; | |
| 2476 } | |
| 2477 // NEG $dst | |
| 2478 emit_opcode(cbuf, 0xF7); | |
| 2479 emit_rm(cbuf, 0x3, 0x03, dstenc); | |
| 2480 %} | |
| 2481 | |
| 2482 enc_class neg_reg_wide(rRegI dst) | |
| 2483 %{ | |
| 2484 int dstenc = $dst$$reg; | |
| 2485 if (dstenc < 8) { | |
| 2486 emit_opcode(cbuf, Assembler::REX_W); | |
| 2487 } else { | |
| 2488 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2489 dstenc -= 8; | |
| 2490 } | |
| 2491 // NEG $dst | |
| 2492 emit_opcode(cbuf, 0xF7); | |
| 2493 emit_rm(cbuf, 0x3, 0x03, dstenc); | |
| 2494 %} | |
| 2495 | |
| 2496 enc_class setLT_reg(rRegI dst) | |
| 2497 %{ | |
| 2498 int dstenc = $dst$$reg; | |
| 2499 if (dstenc >= 8) { | |
| 2500 emit_opcode(cbuf, Assembler::REX_B); | |
| 2501 dstenc -= 8; | |
| 2502 } else if (dstenc >= 4) { | |
| 2503 emit_opcode(cbuf, Assembler::REX); | |
| 2504 } | |
| 2505 // SETLT $dst | |
| 2506 emit_opcode(cbuf, 0x0F); | |
| 2507 emit_opcode(cbuf, 0x9C); | |
| 2508 emit_rm(cbuf, 0x3, 0x0, dstenc); | |
| 2509 %} | |
| 2510 | |
| 2511 enc_class setNZ_reg(rRegI dst) | |
| 2512 %{ | |
| 2513 int dstenc = $dst$$reg; | |
| 2514 if (dstenc >= 8) { | |
| 2515 emit_opcode(cbuf, Assembler::REX_B); | |
| 2516 dstenc -= 8; | |
| 2517 } else if (dstenc >= 4) { | |
| 2518 emit_opcode(cbuf, Assembler::REX); | |
| 2519 } | |
| 2520 // SETNZ $dst | |
| 2521 emit_opcode(cbuf, 0x0F); | |
| 2522 emit_opcode(cbuf, 0x95); | |
| 2523 emit_rm(cbuf, 0x3, 0x0, dstenc); | |
| 2524 %} | |
| 2525 | |
| 2526 | |
| 2527 // Compare the lonogs and set -1, 0, or 1 into dst | |
| 2528 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst) | |
| 2529 %{ | |
| 2530 int src1enc = $src1$$reg; | |
| 2531 int src2enc = $src2$$reg; | |
| 2532 int dstenc = $dst$$reg; | |
| 2533 | |
| 2534 // cmpq $src1, $src2 | |
| 2535 if (src1enc < 8) { | |
| 2536 if (src2enc < 8) { | |
| 2537 emit_opcode(cbuf, Assembler::REX_W); | |
| 2538 } else { | |
| 2539 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2540 } | |
| 2541 } else { | |
| 2542 if (src2enc < 8) { | |
| 2543 emit_opcode(cbuf, Assembler::REX_WR); | |
| 2544 } else { | |
| 2545 emit_opcode(cbuf, Assembler::REX_WRB); | |
| 2546 } | |
| 2547 } | |
| 2548 emit_opcode(cbuf, 0x3B); | |
| 2549 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7); | |
| 2550 | |
| 2551 // movl $dst, -1 | |
| 2552 if (dstenc >= 8) { | |
| 2553 emit_opcode(cbuf, Assembler::REX_B); | |
| 2554 } | |
| 2555 emit_opcode(cbuf, 0xB8 | (dstenc & 7)); | |
| 2556 emit_d32(cbuf, -1); | |
| 2557 | |
| 2558 // jl,s done | |
| 2559 emit_opcode(cbuf, 0x7C); | |
| 2560 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08); | |
| 2561 | |
| 2562 // setne $dst | |
| 2563 if (dstenc >= 4) { | |
| 2564 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B); | |
| 2565 } | |
| 2566 emit_opcode(cbuf, 0x0F); | |
| 2567 emit_opcode(cbuf, 0x95); | |
| 2568 emit_opcode(cbuf, 0xC0 | (dstenc & 7)); | |
| 2569 | |
| 2570 // movzbl $dst, $dst | |
| 2571 if (dstenc >= 4) { | |
| 2572 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB); | |
| 2573 } | |
| 2574 emit_opcode(cbuf, 0x0F); | |
| 2575 emit_opcode(cbuf, 0xB6); | |
| 2576 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7); | |
| 2577 %} | |
| 2578 | |
| 2579 enc_class Push_ResultXD(regD dst) %{ | |
| 4759 | 2580 MacroAssembler _masm(&cbuf); |
| 2581 __ fstp_d(Address(rsp, 0)); | |
| 2582 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); | |
| 2583 __ addptr(rsp, 8); | |
| 0 | 2584 %} |
| 2585 | |
| 2586 enc_class Push_SrcXD(regD src) %{ | |
| 2587 MacroAssembler _masm(&cbuf); | |
| 4759 | 2588 __ subptr(rsp, 8); |
| 2589 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 2590 __ fld_d(Address(rsp, 0)); | |
| 2591 %} | |
| 2592 | |
| 0 | 2593 |
| 2594 enc_class enc_rethrow() | |
| 2595 %{ | |
| 1748 | 2596 cbuf.set_insts_mark(); |
| 0 | 2597 emit_opcode(cbuf, 0xE9); // jmp entry |
| 2598 emit_d32_reloc(cbuf, | |
| 1748 | 2599 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4), |
| 0 | 2600 runtime_call_Relocation::spec(), |
| 2601 RELOC_DISP32); | |
| 2602 %} | |
| 2603 | |
| 2604 %} | |
| 2605 | |
| 2606 | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
2607 |
| 0 | 2608 //----------FRAME-------------------------------------------------------------- |
| 2609 // Definition of frame structure and management information. | |
| 2610 // | |
| 2611 // S T A C K L A Y O U T Allocators stack-slot number | |
| 2612 // | (to get allocators register number | |
| 2613 // G Owned by | | v add OptoReg::stack0()) | |
| 2614 // r CALLER | | | |
| 2615 // o | +--------+ pad to even-align allocators stack-slot | |
| 2616 // w V | pad0 | numbers; owned by CALLER | |
| 2617 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned | |
| 2618 // h ^ | in | 5 | |
| 2619 // | | args | 4 Holes in incoming args owned by SELF | |
| 2620 // | | | | 3 | |
| 2621 // | | +--------+ | |
| 2622 // V | | old out| Empty on Intel, window on Sparc | |
| 2623 // | old |preserve| Must be even aligned. | |
| 2624 // | SP-+--------+----> Matcher::_old_SP, even aligned | |
| 2625 // | | in | 3 area for Intel ret address | |
| 2626 // Owned by |preserve| Empty on Sparc. | |
| 2627 // SELF +--------+ | |
| 2628 // | | pad2 | 2 pad to align old SP | |
| 2629 // | +--------+ 1 | |
| 2630 // | | locks | 0 | |
| 2631 // | +--------+----> OptoReg::stack0(), even aligned | |
| 2632 // | | pad1 | 11 pad to align new SP | |
| 2633 // | +--------+ | |
| 2634 // | | | 10 | |
| 2635 // | | spills | 9 spills | |
| 2636 // V | | 8 (pad0 slot for callee) | |
| 2637 // -----------+--------+----> Matcher::_out_arg_limit, unaligned | |
| 2638 // ^ | out | 7 | |
| 2639 // | | args | 6 Holes in outgoing args owned by CALLEE | |
| 2640 // Owned by +--------+ | |
| 2641 // CALLEE | new out| 6 Empty on Intel, window on Sparc | |
| 2642 // | new |preserve| Must be even-aligned. | |
| 2643 // | SP-+--------+----> Matcher::_new_SP, even aligned | |
| 2644 // | | | | |
| 2645 // | |
| 2646 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is | |
| 2647 // known from SELF's arguments and the Java calling convention. | |
| 2648 // Region 6-7 is determined per call site. | |
| 2649 // Note 2: If the calling convention leaves holes in the incoming argument | |
| 2650 // area, those holes are owned by SELF. Holes in the outgoing area | |
| 2651 // are owned by the CALLEE. Holes should not be nessecary in the | |
| 2652 // incoming area, as the Java calling convention is completely under | |
| 2653 // the control of the AD file. Doubles can be sorted and packed to | |
| 2654 // avoid holes. Holes in the outgoing arguments may be nessecary for | |
| 2655 // varargs C calling conventions. | |
| 2656 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is | |
| 2657 // even aligned with pad0 as needed. | |
| 2658 // Region 6 is even aligned. Region 6-7 is NOT even aligned; | |
| 2659 // region 6-11 is even aligned; it may be padded out more so that | |
| 2660 // the region from SP to FP meets the minimum stack alignment. | |
| 2661 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack | |
| 2662 // alignment. Region 11, pad1, may be dynamically extended so that | |
| 2663 // SP meets the minimum alignment. | |
| 2664 | |
| 2665 frame | |
| 2666 %{ | |
| 2667 // What direction does stack grow in (assumed to be same for C & Java) | |
| 2668 stack_direction(TOWARDS_LOW); | |
| 2669 | |
| 2670 // These three registers define part of the calling convention | |
| 2671 // between compiled code and the interpreter. | |
| 2672 inline_cache_reg(RAX); // Inline Cache Register | |
| 2673 interpreter_method_oop_reg(RBX); // Method Oop Register when | |
| 2674 // calling interpreter | |
| 2675 | |
| 2676 // Optional: name the operand used by cisc-spilling to access | |
| 2677 // [stack_pointer + offset] | |
| 2678 cisc_spilling_operand_name(indOffset32); | |
| 2679 | |
| 2680 // Number of stack slots consumed by locking an object | |
| 2681 sync_stack_slots(2); | |
| 2682 | |
| 2683 // Compiled code's Frame Pointer | |
| 2684 frame_pointer(RSP); | |
| 2685 | |
| 2686 // Interpreter stores its frame pointer in a register which is | |
| 2687 // stored to the stack by I2CAdaptors. | |
| 2688 // I2CAdaptors convert from interpreted java to compiled java. | |
| 2689 interpreter_frame_pointer(RBP); | |
| 2690 | |
| 2691 // Stack alignment requirement | |
| 2692 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes) | |
| 2693 | |
| 2694 // Number of stack slots between incoming argument block and the start of | |
| 2695 // a new frame. The PROLOG must add this many slots to the stack. The | |
| 2696 // EPILOG must remove this many slots. amd64 needs two slots for | |
| 2697 // return address. | |
| 2698 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls); | |
| 2699 | |
| 2700 // Number of outgoing stack slots killed above the out_preserve_stack_slots | |
| 2701 // for calls to C. Supports the var-args backing area for register parms. | |
| 2702 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt); | |
| 2703 | |
| 2704 // The after-PROLOG location of the return address. Location of | |
| 2705 // return address specifies a type (REG or STACK) and a number | |
| 2706 // representing the register number (i.e. - use a register name) or | |
| 2707 // stack slot. | |
| 2708 // Ret Addr is on stack in slot 0 if no locks or verification or alignment. | |
| 2709 // Otherwise, it is above the locks and verification slot and alignment word | |
| 2710 return_addr(STACK - 2 + | |
| 4950 | 2711 round_to((Compile::current()->in_preserve_stack_slots() + |
| 2712 Compile::current()->fixed_slots()), | |
| 2713 stack_alignment_in_slots())); | |
| 0 | 2714 |
| 2715 // Body of function which returns an integer array locating | |
| 2716 // arguments either in registers or in stack slots. Passed an array | |
| 2717 // of ideal registers called "sig" and a "length" count. Stack-slot | |
| 2718 // offsets are based on outgoing arguments, i.e. a CALLER setting up | |
| 2719 // arguments for a CALLEE. Incoming stack arguments are | |
| 2720 // automatically biased by the preserve_stack_slots field above. | |
| 2721 | |
| 2722 calling_convention | |
| 2723 %{ | |
| 2724 // No difference between ingoing/outgoing just pass false | |
| 2725 SharedRuntime::java_calling_convention(sig_bt, regs, length, false); | |
| 2726 %} | |
| 2727 | |
| 2728 c_calling_convention | |
| 2729 %{ | |
| 2730 // This is obviously always outgoing | |
| 2731 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); | |
| 2732 %} | |
| 2733 | |
| 2734 // Location of compiled Java return values. Same as C for now. | |
| 2735 return_value | |
| 2736 %{ | |
| 2737 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, | |
| 2738 "only return normal values"); | |
| 2739 | |
| 2740 static const int lo[Op_RegL + 1] = { | |
| 2741 0, | |
| 2742 0, | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
2743 RAX_num, // Op_RegN |
| 0 | 2744 RAX_num, // Op_RegI |
| 2745 RAX_num, // Op_RegP | |
| 2746 XMM0_num, // Op_RegF | |
| 2747 XMM0_num, // Op_RegD | |
| 2748 RAX_num // Op_RegL | |
| 2749 }; | |
| 2750 static const int hi[Op_RegL + 1] = { | |
| 2751 0, | |
| 2752 0, | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
2753 OptoReg::Bad, // Op_RegN |
| 0 | 2754 OptoReg::Bad, // Op_RegI |
| 2755 RAX_H_num, // Op_RegP | |
| 2756 OptoReg::Bad, // Op_RegF | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
2757 XMM0b_num, // Op_RegD |
| 0 | 2758 RAX_H_num // Op_RegL |
| 2759 }; | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
2760 // Excluded flags and vector registers. |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
2761 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 5, "missing type"); |
| 0 | 2762 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]); |
| 2763 %} | |
| 2764 %} | |
| 2765 | |
| 2766 //----------ATTRIBUTES--------------------------------------------------------- | |
| 2767 //----------Operand Attributes------------------------------------------------- | |
| 2768 op_attrib op_cost(0); // Required cost attribute | |
| 2769 | |
| 2770 //----------Instruction Attributes--------------------------------------------- | |
| 2771 ins_attrib ins_cost(100); // Required cost attribute | |
| 2772 ins_attrib ins_size(8); // Required size attribute (in bits) | |
| 2773 ins_attrib ins_short_branch(0); // Required flag: is this instruction | |
| 2774 // a non-matching short branch variant | |
| 2775 // of some long branch? | |
| 2776 ins_attrib ins_alignment(1); // Required alignment attribute (must | |
| 2777 // be a power of 2) specifies the | |
| 2778 // alignment that some part of the | |
| 2779 // instruction (not necessarily the | |
| 2780 // start) requires. If > 1, a | |
| 2781 // compute_padding() function must be | |
| 2782 // provided for the instruction | |
| 2783 | |
| 2784 //----------OPERANDS----------------------------------------------------------- | |
| 2785 // Operand definitions must precede instruction definitions for correct parsing | |
| 2786 // in the ADLC because operands constitute user defined types which are used in | |
| 2787 // instruction definitions. | |
| 2788 | |
| 2789 //----------Simple Operands---------------------------------------------------- | |
| 2790 // Immediate Operands | |
| 2791 // Integer Immediate | |
| 2792 operand immI() | |
| 2793 %{ | |
| 2794 match(ConI); | |
| 2795 | |
| 2796 op_cost(10); | |
| 2797 format %{ %} | |
| 2798 interface(CONST_INTER); | |
| 2799 %} | |
| 2800 | |
| 2801 // Constant for test vs zero | |
| 2802 operand immI0() | |
| 2803 %{ | |
| 2804 predicate(n->get_int() == 0); | |
| 2805 match(ConI); | |
| 2806 | |
| 2807 op_cost(0); | |
| 2808 format %{ %} | |
| 2809 interface(CONST_INTER); | |
| 2810 %} | |
| 2811 | |
| 2812 // Constant for increment | |
| 2813 operand immI1() | |
| 2814 %{ | |
| 2815 predicate(n->get_int() == 1); | |
| 2816 match(ConI); | |
| 2817 | |
| 2818 op_cost(0); | |
| 2819 format %{ %} | |
| 2820 interface(CONST_INTER); | |
| 2821 %} | |
| 2822 | |
| 2823 // Constant for decrement | |
| 2824 operand immI_M1() | |
| 2825 %{ | |
| 2826 predicate(n->get_int() == -1); | |
| 2827 match(ConI); | |
| 2828 | |
| 2829 op_cost(0); | |
| 2830 format %{ %} | |
| 2831 interface(CONST_INTER); | |
| 2832 %} | |
| 2833 | |
| 2834 // Valid scale values for addressing modes | |
| 2835 operand immI2() | |
| 2836 %{ | |
| 2837 predicate(0 <= n->get_int() && (n->get_int() <= 3)); | |
| 2838 match(ConI); | |
| 2839 | |
| 2840 format %{ %} | |
| 2841 interface(CONST_INTER); | |
| 2842 %} | |
| 2843 | |
| 2844 operand immI8() | |
| 2845 %{ | |
| 2846 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80)); | |
| 2847 match(ConI); | |
| 2848 | |
| 2849 op_cost(5); | |
| 2850 format %{ %} | |
| 2851 interface(CONST_INTER); | |
| 2852 %} | |
| 2853 | |
| 2854 operand immI16() | |
| 2855 %{ | |
| 2856 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767)); | |
| 2857 match(ConI); | |
| 2858 | |
| 2859 op_cost(10); | |
| 2860 format %{ %} | |
| 2861 interface(CONST_INTER); | |
| 2862 %} | |
| 2863 | |
|
17506
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
12972
diff
changeset
|
2864 // Int Immediate non-negative |
|
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
12972
diff
changeset
|
2865 operand immU31() |
|
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
12972
diff
changeset
|
2866 %{ |
|
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
12972
diff
changeset
|
2867 predicate(n->get_int() >= 0); |
|
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
12972
diff
changeset
|
2868 match(ConI); |
|
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
12972
diff
changeset
|
2869 |
|
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
12972
diff
changeset
|
2870 op_cost(0); |
|
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
12972
diff
changeset
|
2871 format %{ %} |
|
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
12972
diff
changeset
|
2872 interface(CONST_INTER); |
|
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
12972
diff
changeset
|
2873 %} |
|
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
12972
diff
changeset
|
2874 |
| 0 | 2875 // Constant for long shifts |
| 2876 operand immI_32() | |
| 2877 %{ | |
| 2878 predicate( n->get_int() == 32 ); | |
| 2879 match(ConI); | |
| 2880 | |
| 2881 op_cost(0); | |
| 2882 format %{ %} | |
| 2883 interface(CONST_INTER); | |
| 2884 %} | |
| 2885 | |
| 2886 // Constant for long shifts | |
| 2887 operand immI_64() | |
| 2888 %{ | |
| 2889 predicate( n->get_int() == 64 ); | |
| 2890 match(ConI); | |
| 2891 | |
| 2892 op_cost(0); | |
| 2893 format %{ %} | |
| 2894 interface(CONST_INTER); | |
| 2895 %} | |
| 2896 | |
| 2897 // Pointer Immediate | |
| 2898 operand immP() | |
| 2899 %{ | |
| 2900 match(ConP); | |
| 2901 | |
| 2902 op_cost(10); | |
| 2903 format %{ %} | |
| 2904 interface(CONST_INTER); | |
| 2905 %} | |
| 2906 | |
| 2907 // NULL Pointer Immediate | |
| 2908 operand immP0() | |
| 2909 %{ | |
| 2910 predicate(n->get_ptr() == 0); | |
| 2911 match(ConP); | |
| 2912 | |
| 2913 op_cost(5); | |
| 2914 format %{ %} | |
| 2915 interface(CONST_INTER); | |
| 2916 %} | |
| 2917 | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
2918 // Pointer Immediate |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
2919 operand immN() %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
2920 match(ConN); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
2921 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
2922 op_cost(10); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
2923 format %{ %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
2924 interface(CONST_INTER); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
2925 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
2926 |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
2927 operand immNKlass() %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
2928 match(ConNKlass); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
2929 |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
2930 op_cost(10); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
2931 format %{ %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
2932 interface(CONST_INTER); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
2933 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
2934 |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
2935 // NULL Pointer Immediate |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
2936 operand immN0() %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
2937 predicate(n->get_narrowcon() == 0); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
2938 match(ConN); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
2939 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
2940 op_cost(5); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
2941 format %{ %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
2942 interface(CONST_INTER); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
2943 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
2944 |
| 0 | 2945 operand immP31() |
| 2946 %{ | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
2947 predicate(n->as_Type()->type()->reloc() == relocInfo::none |
| 0 | 2948 && (n->get_ptr() >> 31) == 0); |
| 2949 match(ConP); | |
| 2950 | |
| 2951 op_cost(5); | |
| 2952 format %{ %} | |
| 2953 interface(CONST_INTER); | |
| 2954 %} | |
| 2955 | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
2956 |
| 0 | 2957 // Long Immediate |
| 2958 operand immL() | |
| 2959 %{ | |
| 2960 match(ConL); | |
| 2961 | |
| 2962 op_cost(20); | |
| 2963 format %{ %} | |
| 2964 interface(CONST_INTER); | |
| 2965 %} | |
| 2966 | |
| 2967 // Long Immediate 8-bit | |
| 2968 operand immL8() | |
| 2969 %{ | |
| 2970 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L); | |
| 2971 match(ConL); | |
| 2972 | |
| 2973 op_cost(5); | |
| 2974 format %{ %} | |
| 2975 interface(CONST_INTER); | |
| 2976 %} | |
| 2977 | |
| 2978 // Long Immediate 32-bit unsigned | |
| 2979 operand immUL32() | |
| 2980 %{ | |
| 2981 predicate(n->get_long() == (unsigned int) (n->get_long())); | |
| 2982 match(ConL); | |
| 2983 | |
| 2984 op_cost(10); | |
| 2985 format %{ %} | |
| 2986 interface(CONST_INTER); | |
| 2987 %} | |
| 2988 | |
| 2989 // Long Immediate 32-bit signed | |
| 2990 operand immL32() | |
| 2991 %{ | |
| 2992 predicate(n->get_long() == (int) (n->get_long())); | |
| 2993 match(ConL); | |
| 2994 | |
| 2995 op_cost(15); | |
| 2996 format %{ %} | |
| 2997 interface(CONST_INTER); | |
| 2998 %} | |
| 2999 | |
| 3000 // Long Immediate zero | |
| 3001 operand immL0() | |
| 3002 %{ | |
| 3003 predicate(n->get_long() == 0L); | |
| 3004 match(ConL); | |
| 3005 | |
| 3006 op_cost(10); | |
| 3007 format %{ %} | |
| 3008 interface(CONST_INTER); | |
| 3009 %} | |
| 3010 | |
| 3011 // Constant for increment | |
| 3012 operand immL1() | |
| 3013 %{ | |
| 3014 predicate(n->get_long() == 1); | |
| 3015 match(ConL); | |
| 3016 | |
| 3017 format %{ %} | |
| 3018 interface(CONST_INTER); | |
| 3019 %} | |
| 3020 | |
| 3021 // Constant for decrement | |
| 3022 operand immL_M1() | |
| 3023 %{ | |
| 3024 predicate(n->get_long() == -1); | |
| 3025 match(ConL); | |
| 3026 | |
| 3027 format %{ %} | |
| 3028 interface(CONST_INTER); | |
| 3029 %} | |
| 3030 | |
| 3031 // Long Immediate: the value 10 | |
| 3032 operand immL10() | |
| 3033 %{ | |
| 3034 predicate(n->get_long() == 10); | |
| 3035 match(ConL); | |
| 3036 | |
| 3037 format %{ %} | |
| 3038 interface(CONST_INTER); | |
| 3039 %} | |
| 3040 | |
| 3041 // Long immediate from 0 to 127. | |
| 3042 // Used for a shorter form of long mul by 10. | |
| 3043 operand immL_127() | |
| 3044 %{ | |
| 3045 predicate(0 <= n->get_long() && n->get_long() < 0x80); | |
| 3046 match(ConL); | |
| 3047 | |
| 3048 op_cost(10); | |
| 3049 format %{ %} | |
| 3050 interface(CONST_INTER); | |
| 3051 %} | |
| 3052 | |
| 3053 // Long Immediate: low 32-bit mask | |
| 3054 operand immL_32bits() | |
| 3055 %{ | |
| 3056 predicate(n->get_long() == 0xFFFFFFFFL); | |
| 3057 match(ConL); | |
| 3058 op_cost(20); | |
| 3059 | |
| 3060 format %{ %} | |
| 3061 interface(CONST_INTER); | |
| 3062 %} | |
| 3063 | |
| 3064 // Float Immediate zero | |
| 3065 operand immF0() | |
| 3066 %{ | |
| 3067 predicate(jint_cast(n->getf()) == 0); | |
| 3068 match(ConF); | |
| 3069 | |
| 3070 op_cost(5); | |
| 3071 format %{ %} | |
| 3072 interface(CONST_INTER); | |
| 3073 %} | |
| 3074 | |
| 3075 // Float Immediate | |
| 3076 operand immF() | |
| 3077 %{ | |
| 3078 match(ConF); | |
| 3079 | |
| 3080 op_cost(15); | |
| 3081 format %{ %} | |
| 3082 interface(CONST_INTER); | |
| 3083 %} | |
| 3084 | |
| 3085 // Double Immediate zero | |
| 3086 operand immD0() | |
| 3087 %{ | |
| 3088 predicate(jlong_cast(n->getd()) == 0); | |
| 3089 match(ConD); | |
| 3090 | |
| 3091 op_cost(5); | |
| 3092 format %{ %} | |
| 3093 interface(CONST_INTER); | |
| 3094 %} | |
| 3095 | |
| 3096 // Double Immediate | |
| 3097 operand immD() | |
| 3098 %{ | |
| 3099 match(ConD); | |
| 3100 | |
| 3101 op_cost(15); | |
| 3102 format %{ %} | |
| 3103 interface(CONST_INTER); | |
| 3104 %} | |
| 3105 | |
| 3106 // Immediates for special shifts (sign extend) | |
| 3107 | |
| 3108 // Constants for increment | |
| 3109 operand immI_16() | |
| 3110 %{ | |
| 3111 predicate(n->get_int() == 16); | |
| 3112 match(ConI); | |
| 3113 | |
| 3114 format %{ %} | |
| 3115 interface(CONST_INTER); | |
| 3116 %} | |
| 3117 | |
| 3118 operand immI_24() | |
| 3119 %{ | |
| 3120 predicate(n->get_int() == 24); | |
| 3121 match(ConI); | |
| 3122 | |
| 3123 format %{ %} | |
| 3124 interface(CONST_INTER); | |
| 3125 %} | |
| 3126 | |
| 3127 // Constant for byte-wide masking | |
| 3128 operand immI_255() | |
| 3129 %{ | |
| 3130 predicate(n->get_int() == 255); | |
| 3131 match(ConI); | |
| 3132 | |
| 3133 format %{ %} | |
| 3134 interface(CONST_INTER); | |
| 3135 %} | |
| 3136 | |
| 3137 // Constant for short-wide masking | |
| 3138 operand immI_65535() | |
| 3139 %{ | |
| 3140 predicate(n->get_int() == 65535); | |
| 3141 match(ConI); | |
| 3142 | |
| 3143 format %{ %} | |
| 3144 interface(CONST_INTER); | |
| 3145 %} | |
| 3146 | |
| 3147 // Constant for byte-wide masking | |
| 3148 operand immL_255() | |
| 3149 %{ | |
| 3150 predicate(n->get_long() == 255); | |
| 3151 match(ConL); | |
| 3152 | |
| 3153 format %{ %} | |
| 3154 interface(CONST_INTER); | |
| 3155 %} | |
| 3156 | |
| 3157 // Constant for short-wide masking | |
| 3158 operand immL_65535() | |
| 3159 %{ | |
| 3160 predicate(n->get_long() == 65535); | |
| 3161 match(ConL); | |
| 3162 | |
| 3163 format %{ %} | |
| 3164 interface(CONST_INTER); | |
| 3165 %} | |
| 3166 | |
| 3167 // Register Operands | |
| 3168 // Integer Register | |
| 3169 operand rRegI() | |
| 3170 %{ | |
| 3171 constraint(ALLOC_IN_RC(int_reg)); | |
| 3172 match(RegI); | |
| 3173 | |
| 3174 match(rax_RegI); | |
| 3175 match(rbx_RegI); | |
| 3176 match(rcx_RegI); | |
| 3177 match(rdx_RegI); | |
| 3178 match(rdi_RegI); | |
| 3179 | |
| 3180 format %{ %} | |
| 3181 interface(REG_INTER); | |
| 3182 %} | |
| 3183 | |
| 3184 // Special Registers | |
| 3185 operand rax_RegI() | |
| 3186 %{ | |
| 3187 constraint(ALLOC_IN_RC(int_rax_reg)); | |
| 3188 match(RegI); | |
| 3189 match(rRegI); | |
| 3190 | |
| 3191 format %{ "RAX" %} | |
| 3192 interface(REG_INTER); | |
| 3193 %} | |
| 3194 | |
| 3195 // Special Registers | |
| 3196 operand rbx_RegI() | |
| 3197 %{ | |
| 3198 constraint(ALLOC_IN_RC(int_rbx_reg)); | |
| 3199 match(RegI); | |
| 3200 match(rRegI); | |
| 3201 | |
| 3202 format %{ "RBX" %} | |
| 3203 interface(REG_INTER); | |
| 3204 %} | |
| 3205 | |
| 3206 operand rcx_RegI() | |
| 3207 %{ | |
| 3208 constraint(ALLOC_IN_RC(int_rcx_reg)); | |
| 3209 match(RegI); | |
| 3210 match(rRegI); | |
| 3211 | |
| 3212 format %{ "RCX" %} | |
| 3213 interface(REG_INTER); | |
| 3214 %} | |
| 3215 | |
| 3216 operand rdx_RegI() | |
| 3217 %{ | |
| 3218 constraint(ALLOC_IN_RC(int_rdx_reg)); | |
| 3219 match(RegI); | |
| 3220 match(rRegI); | |
| 3221 | |
| 3222 format %{ "RDX" %} | |
| 3223 interface(REG_INTER); | |
| 3224 %} | |
| 3225 | |
| 3226 operand rdi_RegI() | |
| 3227 %{ | |
| 3228 constraint(ALLOC_IN_RC(int_rdi_reg)); | |
| 3229 match(RegI); | |
| 3230 match(rRegI); | |
| 3231 | |
| 3232 format %{ "RDI" %} | |
| 3233 interface(REG_INTER); | |
| 3234 %} | |
| 3235 | |
| 3236 operand no_rcx_RegI() | |
| 3237 %{ | |
| 3238 constraint(ALLOC_IN_RC(int_no_rcx_reg)); | |
| 3239 match(RegI); | |
| 3240 match(rax_RegI); | |
| 3241 match(rbx_RegI); | |
| 3242 match(rdx_RegI); | |
| 3243 match(rdi_RegI); | |
| 3244 | |
| 3245 format %{ %} | |
| 3246 interface(REG_INTER); | |
| 3247 %} | |
| 3248 | |
| 3249 operand no_rax_rdx_RegI() | |
| 3250 %{ | |
| 3251 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg)); | |
| 3252 match(RegI); | |
| 3253 match(rbx_RegI); | |
| 3254 match(rcx_RegI); | |
| 3255 match(rdi_RegI); | |
| 3256 | |
| 3257 format %{ %} | |
| 3258 interface(REG_INTER); | |
| 3259 %} | |
| 3260 | |
| 3261 // Pointer Register | |
| 3262 operand any_RegP() | |
| 3263 %{ | |
| 3264 constraint(ALLOC_IN_RC(any_reg)); | |
| 3265 match(RegP); | |
| 3266 match(rax_RegP); | |
| 3267 match(rbx_RegP); | |
| 3268 match(rdi_RegP); | |
| 3269 match(rsi_RegP); | |
| 3270 match(rbp_RegP); | |
| 3271 match(r15_RegP); | |
| 3272 match(rRegP); | |
| 3273 | |
| 3274 format %{ %} | |
| 3275 interface(REG_INTER); | |
| 3276 %} | |
| 3277 | |
| 3278 operand rRegP() | |
| 3279 %{ | |
| 3280 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3281 match(RegP); | |
| 3282 match(rax_RegP); | |
| 3283 match(rbx_RegP); | |
| 3284 match(rdi_RegP); | |
| 3285 match(rsi_RegP); | |
| 3286 match(rbp_RegP); | |
| 3287 match(r15_RegP); // See Q&A below about r15_RegP. | |
| 3288 | |
| 3289 format %{ %} | |
| 3290 interface(REG_INTER); | |
| 3291 %} | |
| 3292 | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
3293 operand rRegN() %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
3294 constraint(ALLOC_IN_RC(int_reg)); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
3295 match(RegN); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
3296 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
3297 format %{ %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
3298 interface(REG_INTER); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
3299 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
3300 |
| 0 | 3301 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP? |
| 3302 // Answer: Operand match rules govern the DFA as it processes instruction inputs. | |
| 3303 // It's fine for an instruction input which expects rRegP to match a r15_RegP. | |
| 3304 // The output of an instruction is controlled by the allocator, which respects | |
| 3305 // register class masks, not match rules. Unless an instruction mentions | |
| 3306 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered | |
| 3307 // by the allocator as an input. | |
| 3308 | |
| 3309 operand no_rax_RegP() | |
| 3310 %{ | |
| 3311 constraint(ALLOC_IN_RC(ptr_no_rax_reg)); | |
| 3312 match(RegP); | |
| 3313 match(rbx_RegP); | |
| 3314 match(rsi_RegP); | |
| 3315 match(rdi_RegP); | |
| 3316 | |
| 3317 format %{ %} | |
| 3318 interface(REG_INTER); | |
| 3319 %} | |
| 3320 | |
| 3321 operand no_rbp_RegP() | |
| 3322 %{ | |
| 3323 constraint(ALLOC_IN_RC(ptr_no_rbp_reg)); | |
| 3324 match(RegP); | |
| 3325 match(rbx_RegP); | |
| 3326 match(rsi_RegP); | |
| 3327 match(rdi_RegP); | |
| 3328 | |
| 3329 format %{ %} | |
| 3330 interface(REG_INTER); | |
| 3331 %} | |
| 3332 | |
| 3333 operand no_rax_rbx_RegP() | |
| 3334 %{ | |
| 3335 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg)); | |
| 3336 match(RegP); | |
| 3337 match(rsi_RegP); | |
| 3338 match(rdi_RegP); | |
| 3339 | |
| 3340 format %{ %} | |
| 3341 interface(REG_INTER); | |
| 3342 %} | |
| 3343 | |
| 3344 // Special Registers | |
| 3345 // Return a pointer value | |
| 3346 operand rax_RegP() | |
| 3347 %{ | |
| 3348 constraint(ALLOC_IN_RC(ptr_rax_reg)); | |
| 3349 match(RegP); | |
| 3350 match(rRegP); | |
| 3351 | |
| 3352 format %{ %} | |
| 3353 interface(REG_INTER); | |
| 3354 %} | |
| 3355 | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
3356 // Special Registers |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
3357 // Return a compressed pointer value |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
3358 operand rax_RegN() |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
3359 %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
3360 constraint(ALLOC_IN_RC(int_rax_reg)); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
3361 match(RegN); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
3362 match(rRegN); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
3363 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
3364 format %{ %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
3365 interface(REG_INTER); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
3366 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
3367 |
| 0 | 3368 // Used in AtomicAdd |
| 3369 operand rbx_RegP() | |
| 3370 %{ | |
| 3371 constraint(ALLOC_IN_RC(ptr_rbx_reg)); | |
| 3372 match(RegP); | |
| 3373 match(rRegP); | |
| 3374 | |
| 3375 format %{ %} | |
| 3376 interface(REG_INTER); | |
| 3377 %} | |
| 3378 | |
| 3379 operand rsi_RegP() | |
| 3380 %{ | |
| 3381 constraint(ALLOC_IN_RC(ptr_rsi_reg)); | |
| 3382 match(RegP); | |
| 3383 match(rRegP); | |
| 3384 | |
| 3385 format %{ %} | |
| 3386 interface(REG_INTER); | |
| 3387 %} | |
| 3388 | |
| 3389 // Used in rep stosq | |
| 3390 operand rdi_RegP() | |
| 3391 %{ | |
| 3392 constraint(ALLOC_IN_RC(ptr_rdi_reg)); | |
| 3393 match(RegP); | |
| 3394 match(rRegP); | |
| 3395 | |
| 3396 format %{ %} | |
| 3397 interface(REG_INTER); | |
| 3398 %} | |
| 3399 | |
| 3400 operand rbp_RegP() | |
| 3401 %{ | |
| 3402 constraint(ALLOC_IN_RC(ptr_rbp_reg)); | |
| 3403 match(RegP); | |
| 3404 match(rRegP); | |
| 3405 | |
| 3406 format %{ %} | |
| 3407 interface(REG_INTER); | |
| 3408 %} | |
| 3409 | |
| 3410 operand r15_RegP() | |
| 3411 %{ | |
| 3412 constraint(ALLOC_IN_RC(ptr_r15_reg)); | |
| 3413 match(RegP); | |
| 3414 match(rRegP); | |
| 3415 | |
| 3416 format %{ %} | |
| 3417 interface(REG_INTER); | |
| 3418 %} | |
| 3419 | |
| 3420 operand rRegL() | |
| 3421 %{ | |
| 3422 constraint(ALLOC_IN_RC(long_reg)); | |
| 3423 match(RegL); | |
| 3424 match(rax_RegL); | |
| 3425 match(rdx_RegL); | |
| 3426 | |
| 3427 format %{ %} | |
| 3428 interface(REG_INTER); | |
| 3429 %} | |
| 3430 | |
| 3431 // Special Registers | |
| 3432 operand no_rax_rdx_RegL() | |
| 3433 %{ | |
| 3434 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg)); | |
| 3435 match(RegL); | |
| 3436 match(rRegL); | |
| 3437 | |
| 3438 format %{ %} | |
| 3439 interface(REG_INTER); | |
| 3440 %} | |
| 3441 | |
| 3442 operand no_rax_RegL() | |
| 3443 %{ | |
| 3444 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg)); | |
| 3445 match(RegL); | |
| 3446 match(rRegL); | |
| 3447 match(rdx_RegL); | |
| 3448 | |
| 3449 format %{ %} | |
| 3450 interface(REG_INTER); | |
| 3451 %} | |
| 3452 | |
| 3453 operand no_rcx_RegL() | |
| 3454 %{ | |
| 3455 constraint(ALLOC_IN_RC(long_no_rcx_reg)); | |
| 3456 match(RegL); | |
| 3457 match(rRegL); | |
| 3458 | |
| 3459 format %{ %} | |
| 3460 interface(REG_INTER); | |
| 3461 %} | |
| 3462 | |
| 3463 operand rax_RegL() | |
| 3464 %{ | |
| 3465 constraint(ALLOC_IN_RC(long_rax_reg)); | |
| 3466 match(RegL); | |
| 3467 match(rRegL); | |
| 3468 | |
| 3469 format %{ "RAX" %} | |
| 3470 interface(REG_INTER); | |
| 3471 %} | |
| 3472 | |
| 3473 operand rcx_RegL() | |
| 3474 %{ | |
| 3475 constraint(ALLOC_IN_RC(long_rcx_reg)); | |
| 3476 match(RegL); | |
| 3477 match(rRegL); | |
| 3478 | |
| 3479 format %{ %} | |
| 3480 interface(REG_INTER); | |
| 3481 %} | |
| 3482 | |
| 3483 operand rdx_RegL() | |
| 3484 %{ | |
| 3485 constraint(ALLOC_IN_RC(long_rdx_reg)); | |
| 3486 match(RegL); | |
| 3487 match(rRegL); | |
| 3488 | |
| 3489 format %{ %} | |
| 3490 interface(REG_INTER); | |
| 3491 %} | |
| 3492 | |
| 3493 // Flags register, used as output of compare instructions | |
| 3494 operand rFlagsReg() | |
| 3495 %{ | |
| 3496 constraint(ALLOC_IN_RC(int_flags)); | |
| 3497 match(RegFlags); | |
| 3498 | |
| 3499 format %{ "RFLAGS" %} | |
| 3500 interface(REG_INTER); | |
| 3501 %} | |
| 3502 | |
| 3503 // Flags register, used as output of FLOATING POINT compare instructions | |
| 3504 operand rFlagsRegU() | |
| 3505 %{ | |
| 3506 constraint(ALLOC_IN_RC(int_flags)); | |
| 3507 match(RegFlags); | |
| 3508 | |
| 3509 format %{ "RFLAGS_U" %} | |
| 3510 interface(REG_INTER); | |
| 3511 %} | |
| 3512 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3513 operand rFlagsRegUCF() %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3514 constraint(ALLOC_IN_RC(int_flags)); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3515 match(RegFlags); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3516 predicate(false); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3517 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3518 format %{ "RFLAGS_U_CF" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3519 interface(REG_INTER); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3520 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3521 |
| 0 | 3522 // Float register operands |
| 3523 operand regF() | |
| 3524 %{ | |
| 3525 constraint(ALLOC_IN_RC(float_reg)); | |
| 3526 match(RegF); | |
| 3527 | |
| 3528 format %{ %} | |
| 3529 interface(REG_INTER); | |
| 3530 %} | |
| 3531 | |
| 3532 // Double register operands | |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
3533 operand regD() |
| 0 | 3534 %{ |
| 3535 constraint(ALLOC_IN_RC(double_reg)); | |
| 3536 match(RegD); | |
| 3537 | |
| 3538 format %{ %} | |
| 3539 interface(REG_INTER); | |
| 3540 %} | |
| 3541 | |
| 3542 //----------Memory Operands---------------------------------------------------- | |
| 3543 // Direct Memory Operand | |
| 3544 // operand direct(immP addr) | |
| 3545 // %{ | |
| 3546 // match(addr); | |
| 3547 | |
| 3548 // format %{ "[$addr]" %} | |
| 3549 // interface(MEMORY_INTER) %{ | |
| 3550 // base(0xFFFFFFFF); | |
| 3551 // index(0x4); | |
| 3552 // scale(0x0); | |
| 3553 // disp($addr); | |
| 3554 // %} | |
| 3555 // %} | |
| 3556 | |
| 3557 // Indirect Memory Operand | |
| 3558 operand indirect(any_RegP reg) | |
| 3559 %{ | |
| 3560 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3561 match(reg); | |
| 3562 | |
| 3563 format %{ "[$reg]" %} | |
| 3564 interface(MEMORY_INTER) %{ | |
| 3565 base($reg); | |
| 3566 index(0x4); | |
| 3567 scale(0x0); | |
| 3568 disp(0x0); | |
| 3569 %} | |
| 3570 %} | |
| 3571 | |
| 3572 // Indirect Memory Plus Short Offset Operand | |
| 3573 operand indOffset8(any_RegP reg, immL8 off) | |
| 3574 %{ | |
| 3575 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3576 match(AddP reg off); | |
| 3577 | |
| 3578 format %{ "[$reg + $off (8-bit)]" %} | |
| 3579 interface(MEMORY_INTER) %{ | |
| 3580 base($reg); | |
| 3581 index(0x4); | |
| 3582 scale(0x0); | |
| 3583 disp($off); | |
| 3584 %} | |
| 3585 %} | |
| 3586 | |
| 3587 // Indirect Memory Plus Long Offset Operand | |
| 3588 operand indOffset32(any_RegP reg, immL32 off) | |
| 3589 %{ | |
| 3590 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3591 match(AddP reg off); | |
| 3592 | |
| 3593 format %{ "[$reg + $off (32-bit)]" %} | |
| 3594 interface(MEMORY_INTER) %{ | |
| 3595 base($reg); | |
| 3596 index(0x4); | |
| 3597 scale(0x0); | |
| 3598 disp($off); | |
| 3599 %} | |
| 3600 %} | |
| 3601 | |
| 3602 // Indirect Memory Plus Index Register Plus Offset Operand | |
| 3603 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off) | |
| 3604 %{ | |
| 3605 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3606 match(AddP (AddP reg lreg) off); | |
| 3607 | |
| 3608 op_cost(10); | |
| 3609 format %{"[$reg + $off + $lreg]" %} | |
| 3610 interface(MEMORY_INTER) %{ | |
| 3611 base($reg); | |
| 3612 index($lreg); | |
| 3613 scale(0x0); | |
| 3614 disp($off); | |
| 3615 %} | |
| 3616 %} | |
| 3617 | |
| 3618 // Indirect Memory Plus Index Register Plus Offset Operand | |
| 3619 operand indIndex(any_RegP reg, rRegL lreg) | |
| 3620 %{ | |
| 3621 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3622 match(AddP reg lreg); | |
| 3623 | |
| 3624 op_cost(10); | |
| 3625 format %{"[$reg + $lreg]" %} | |
| 3626 interface(MEMORY_INTER) %{ | |
| 3627 base($reg); | |
| 3628 index($lreg); | |
| 3629 scale(0x0); | |
| 3630 disp(0x0); | |
| 3631 %} | |
| 3632 %} | |
| 3633 | |
| 3634 // Indirect Memory Times Scale Plus Index Register | |
| 3635 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale) | |
| 3636 %{ | |
| 3637 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3638 match(AddP reg (LShiftL lreg scale)); | |
| 3639 | |
| 3640 op_cost(10); | |
| 3641 format %{"[$reg + $lreg << $scale]" %} | |
| 3642 interface(MEMORY_INTER) %{ | |
| 3643 base($reg); | |
| 3644 index($lreg); | |
| 3645 scale($scale); | |
| 3646 disp(0x0); | |
| 3647 %} | |
| 3648 %} | |
| 3649 | |
| 3650 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand | |
| 3651 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale) | |
| 3652 %{ | |
| 3653 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3654 match(AddP (AddP reg (LShiftL lreg scale)) off); | |
| 3655 | |
| 3656 op_cost(10); | |
| 3657 format %{"[$reg + $off + $lreg << $scale]" %} | |
| 3658 interface(MEMORY_INTER) %{ | |
| 3659 base($reg); | |
| 3660 index($lreg); | |
| 3661 scale($scale); | |
| 3662 disp($off); | |
| 3663 %} | |
| 3664 %} | |
| 3665 | |
| 3666 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand | |
| 3667 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale) | |
| 3668 %{ | |
| 3669 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3670 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0); | |
| 3671 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off); | |
| 3672 | |
| 3673 op_cost(10); | |
| 3674 format %{"[$reg + $off + $idx << $scale]" %} | |
| 3675 interface(MEMORY_INTER) %{ | |
| 3676 base($reg); | |
| 3677 index($idx); | |
| 3678 scale($scale); | |
| 3679 disp($off); | |
| 3680 %} | |
| 3681 %} | |
| 3682 | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3683 // Indirect Narrow Oop Plus Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3684 // Note: x86 architecture doesn't support "scale * index + offset" without a base |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3685 // we can't free r12 even with Universe::narrow_oop_base() == NULL. |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3686 operand indCompressedOopOffset(rRegN reg, immL32 off) %{ |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1567
diff
changeset
|
3687 predicate(UseCompressedOops && (Universe::narrow_oop_shift() == Address::times_8)); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3688 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3689 match(AddP (DecodeN reg) off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3690 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3691 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3692 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3693 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3694 base(0xc); // R12 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3695 index($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3696 scale(0x3); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3697 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3698 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3699 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3700 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3701 // Indirect Memory Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3702 operand indirectNarrow(rRegN reg) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3703 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3704 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3705 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3706 match(DecodeN reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3707 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3708 format %{ "[$reg]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3709 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3710 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3711 index(0x4); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3712 scale(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3713 disp(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3714 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3715 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3716 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3717 // Indirect Memory Plus Short Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3718 operand indOffset8Narrow(rRegN reg, immL8 off) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3719 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3720 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3721 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3722 match(AddP (DecodeN reg) off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3723 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3724 format %{ "[$reg + $off (8-bit)]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3725 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3726 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3727 index(0x4); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3728 scale(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3729 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3730 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3731 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3732 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3733 // Indirect Memory Plus Long Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3734 operand indOffset32Narrow(rRegN reg, immL32 off) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3735 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3736 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3737 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3738 match(AddP (DecodeN reg) off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3739 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3740 format %{ "[$reg + $off (32-bit)]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3741 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3742 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3743 index(0x4); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3744 scale(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3745 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3746 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3747 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3748 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3749 // Indirect Memory Plus Index Register Plus Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3750 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3751 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3752 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3753 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3754 match(AddP (AddP (DecodeN reg) lreg) off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3755 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3756 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3757 format %{"[$reg + $off + $lreg]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3758 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3759 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3760 index($lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3761 scale(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3762 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3763 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3764 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3765 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3766 // Indirect Memory Plus Index Register Plus Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3767 operand indIndexNarrow(rRegN reg, rRegL lreg) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3768 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3769 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3770 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3771 match(AddP (DecodeN reg) lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3772 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3773 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3774 format %{"[$reg + $lreg]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3775 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3776 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3777 index($lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3778 scale(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3779 disp(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3780 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3781 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3782 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3783 // Indirect Memory Times Scale Plus Index Register |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3784 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3785 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3786 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3787 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3788 match(AddP (DecodeN reg) (LShiftL lreg scale)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3789 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3790 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3791 format %{"[$reg + $lreg << $scale]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3792 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3793 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3794 index($lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3795 scale($scale); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3796 disp(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3797 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3798 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3799 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3800 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3801 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3802 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3803 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3804 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3805 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3806 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3807 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3808 format %{"[$reg + $off + $lreg << $scale]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3809 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3810 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3811 index($lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3812 scale($scale); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3813 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3814 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3815 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3816 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3817 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3818 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3819 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3820 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3821 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3822 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3823 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3824 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3825 format %{"[$reg + $off + $idx << $scale]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3826 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3827 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3828 index($idx); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3829 scale($scale); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3830 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3831 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3832 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3833 |
| 0 | 3834 //----------Special Memory Operands-------------------------------------------- |
| 3835 // Stack Slot Operand - This operand is used for loading and storing temporary | |
| 3836 // values on the stack where a match requires a value to | |
| 3837 // flow through memory. | |
| 3838 operand stackSlotP(sRegP reg) | |
| 3839 %{ | |
| 3840 constraint(ALLOC_IN_RC(stack_slots)); | |
| 3841 // No match rule because this operand is only generated in matching | |
| 3842 | |
| 3843 format %{ "[$reg]" %} | |
| 3844 interface(MEMORY_INTER) %{ | |
| 3845 base(0x4); // RSP | |
| 3846 index(0x4); // No Index | |
| 3847 scale(0x0); // No Scale | |
| 3848 disp($reg); // Stack Offset | |
| 3849 %} | |
| 3850 %} | |
| 3851 | |
| 3852 operand stackSlotI(sRegI reg) | |
| 3853 %{ | |
| 3854 constraint(ALLOC_IN_RC(stack_slots)); | |
| 3855 // No match rule because this operand is only generated in matching | |
| 3856 | |
| 3857 format %{ "[$reg]" %} | |
| 3858 interface(MEMORY_INTER) %{ | |
| 3859 base(0x4); // RSP | |
| 3860 index(0x4); // No Index | |
| 3861 scale(0x0); // No Scale | |
| 3862 disp($reg); // Stack Offset | |
| 3863 %} | |
| 3864 %} | |
| 3865 | |
| 3866 operand stackSlotF(sRegF reg) | |
| 3867 %{ | |
| 3868 constraint(ALLOC_IN_RC(stack_slots)); | |
| 3869 // No match rule because this operand is only generated in matching | |
| 3870 | |
| 3871 format %{ "[$reg]" %} | |
| 3872 interface(MEMORY_INTER) %{ | |
| 3873 base(0x4); // RSP | |
| 3874 index(0x4); // No Index | |
| 3875 scale(0x0); // No Scale | |
| 3876 disp($reg); // Stack Offset | |
| 3877 %} | |
| 3878 %} | |
| 3879 | |
| 3880 operand stackSlotD(sRegD reg) | |
| 3881 %{ | |
| 3882 constraint(ALLOC_IN_RC(stack_slots)); | |
| 3883 // No match rule because this operand is only generated in matching | |
| 3884 | |
| 3885 format %{ "[$reg]" %} | |
| 3886 interface(MEMORY_INTER) %{ | |
| 3887 base(0x4); // RSP | |
| 3888 index(0x4); // No Index | |
| 3889 scale(0x0); // No Scale | |
| 3890 disp($reg); // Stack Offset | |
| 3891 %} | |
| 3892 %} | |
| 3893 operand stackSlotL(sRegL reg) | |
| 3894 %{ | |
| 3895 constraint(ALLOC_IN_RC(stack_slots)); | |
| 3896 // No match rule because this operand is only generated in matching | |
| 3897 | |
| 3898 format %{ "[$reg]" %} | |
| 3899 interface(MEMORY_INTER) %{ | |
| 3900 base(0x4); // RSP | |
| 3901 index(0x4); // No Index | |
| 3902 scale(0x0); // No Scale | |
| 3903 disp($reg); // Stack Offset | |
| 3904 %} | |
| 3905 %} | |
| 3906 | |
| 3907 //----------Conditional Branch Operands---------------------------------------- | |
| 3908 // Comparison Op - This is the operation of the comparison, and is limited to | |
| 3909 // the following set of codes: | |
| 3910 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) | |
| 3911 // | |
| 3912 // Other attributes of the comparison, such as unsignedness, are specified | |
| 3913 // by the comparison instruction that sets a condition code flags register. | |
| 3914 // That result is represented by a flags operand whose subtype is appropriate | |
| 3915 // to the unsignedness (etc.) of the comparison. | |
| 3916 // | |
| 3917 // Later, the instruction which matches both the Comparison Op (a Bool) and | |
| 3918 // the flags (produced by the Cmp) specifies the coding of the comparison op | |
| 3919 // by matching a specific subtype of Bool operand below, such as cmpOpU. | |
| 3920 | |
| 3921 // Comparision Code | |
| 3922 operand cmpOp() | |
| 3923 %{ | |
| 3924 match(Bool); | |
| 3925 | |
| 3926 format %{ "" %} | |
| 3927 interface(COND_INTER) %{ | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3928 equal(0x4, "e"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3929 not_equal(0x5, "ne"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3930 less(0xC, "l"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3931 greater_equal(0xD, "ge"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3932 less_equal(0xE, "le"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3933 greater(0xF, "g"); |
| 12323 | 3934 overflow(0x0, "o"); |
| 3935 no_overflow(0x1, "no"); | |
| 0 | 3936 %} |
| 3937 %} | |
| 3938 | |
| 3939 // Comparison Code, unsigned compare. Used by FP also, with | |
| 3940 // C2 (unordered) turned into GT or LT already. The other bits | |
| 3941 // C0 and C3 are turned into Carry & Zero flags. | |
| 3942 operand cmpOpU() | |
| 3943 %{ | |
| 3944 match(Bool); | |
| 3945 | |
| 3946 format %{ "" %} | |
| 3947 interface(COND_INTER) %{ | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3948 equal(0x4, "e"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3949 not_equal(0x5, "ne"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3950 less(0x2, "b"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3951 greater_equal(0x3, "nb"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3952 less_equal(0x6, "be"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3953 greater(0x7, "nbe"); |
| 12323 | 3954 overflow(0x0, "o"); |
| 3955 no_overflow(0x1, "no"); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3956 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3957 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3958 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3959 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3960 // Floating comparisons that don't require any fixup for the unordered case |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3961 operand cmpOpUCF() %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3962 match(Bool); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3963 predicate(n->as_Bool()->_test._test == BoolTest::lt || |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3964 n->as_Bool()->_test._test == BoolTest::ge || |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3965 n->as_Bool()->_test._test == BoolTest::le || |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3966 n->as_Bool()->_test._test == BoolTest::gt); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3967 format %{ "" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3968 interface(COND_INTER) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3969 equal(0x4, "e"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3970 not_equal(0x5, "ne"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3971 less(0x2, "b"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3972 greater_equal(0x3, "nb"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3973 less_equal(0x6, "be"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3974 greater(0x7, "nbe"); |
| 12323 | 3975 overflow(0x0, "o"); |
| 3976 no_overflow(0x1, "no"); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3977 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3978 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3979 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3980 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3981 // Floating comparisons that can be fixed up with extra conditional jumps |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3982 operand cmpOpUCF2() %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3983 match(Bool); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3984 predicate(n->as_Bool()->_test._test == BoolTest::ne || |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3985 n->as_Bool()->_test._test == BoolTest::eq); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3986 format %{ "" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3987 interface(COND_INTER) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3988 equal(0x4, "e"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3989 not_equal(0x5, "ne"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3990 less(0x2, "b"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3991 greater_equal(0x3, "nb"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3992 less_equal(0x6, "be"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
3993 greater(0x7, "nbe"); |
| 12323 | 3994 overflow(0x0, "o"); |
| 3995 no_overflow(0x1, "no"); | |
| 0 | 3996 %} |
| 3997 %} | |
| 3998 | |
| 3999 | |
| 4000 //----------OPERAND CLASSES---------------------------------------------------- | |
| 4001 // Operand Classes are groups of operands that are used as to simplify | |
| 605 | 4002 // instruction definitions by not requiring the AD writer to specify separate |
| 0 | 4003 // instructions for every form of operand when the instruction accepts |
| 4004 // multiple operand types with the same basic encoding and format. The classic | |
| 4005 // case of this is memory operands. | |
| 4006 | |
| 4007 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex, | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
4008 indIndexScale, indIndexScaleOffset, indPosIndexScaleOffset, |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4009 indCompressedOopOffset, |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4010 indirectNarrow, indOffset8Narrow, indOffset32Narrow, |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4011 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow, |
|
12056
740e263c80c6
8003424: Enable Class Data Sharing for CompressedOops
hseigel
parents:
10171
diff
changeset
|
4012 indIndexScaleOffsetNarrow, indPosIndexScaleOffsetNarrow); |
| 0 | 4013 |
| 4014 //----------PIPELINE----------------------------------------------------------- | |
| 4015 // Rules which define the behavior of the target architectures pipeline. | |
| 4016 pipeline %{ | |
| 4017 | |
| 4018 //----------ATTRIBUTES--------------------------------------------------------- | |
| 4019 attributes %{ | |
| 4020 variable_size_instructions; // Fixed size instructions | |
| 4021 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle | |
| 4022 instruction_unit_size = 1; // An instruction is 1 bytes long | |
| 4023 instruction_fetch_unit_size = 16; // The processor fetches one line | |
| 4024 instruction_fetch_units = 1; // of 16 bytes | |
| 4025 | |
| 4026 // List of nop instructions | |
| 4027 nops( MachNop ); | |
| 4028 %} | |
| 4029 | |
| 4030 //----------RESOURCES---------------------------------------------------------- | |
| 4031 // Resources are the functional units available to the machine | |
| 4032 | |
| 4033 // Generic P2/P3 pipeline | |
| 4034 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of | |
| 4035 // 3 instructions decoded per cycle. | |
| 4036 // 2 load/store ops per cycle, 1 branch, 1 FPU, | |
| 4037 // 3 ALU op, only ALU0 handles mul instructions. | |
| 4038 resources( D0, D1, D2, DECODE = D0 | D1 | D2, | |
| 4039 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2, | |
| 4040 BR, FPU, | |
| 4041 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2); | |
| 4042 | |
| 4043 //----------PIPELINE DESCRIPTION----------------------------------------------- | |
| 4044 // Pipeline Description specifies the stages in the machine's pipeline | |
| 4045 | |
| 4046 // Generic P2/P3 pipeline | |
| 4047 pipe_desc(S0, S1, S2, S3, S4, S5); | |
| 4048 | |
| 4049 //----------PIPELINE CLASSES--------------------------------------------------- | |
| 4050 // Pipeline Classes describe the stages in which input and output are | |
| 4051 // referenced by the hardware pipeline. | |
| 4052 | |
| 4053 // Naming convention: ialu or fpu | |
| 4054 // Then: _reg | |
| 4055 // Then: _reg if there is a 2nd register | |
| 4056 // Then: _long if it's a pair of instructions implementing a long | |
| 4057 // Then: _fat if it requires the big decoder | |
| 4058 // Or: _mem if it requires the big decoder and a memory unit. | |
| 4059 | |
| 4060 // Integer ALU reg operation | |
| 4061 pipe_class ialu_reg(rRegI dst) | |
| 4062 %{ | |
| 4063 single_instruction; | |
| 4064 dst : S4(write); | |
| 4065 dst : S3(read); | |
| 4066 DECODE : S0; // any decoder | |
| 4067 ALU : S3; // any alu | |
| 4068 %} | |
| 4069 | |
| 4070 // Long ALU reg operation | |
| 4071 pipe_class ialu_reg_long(rRegL dst) | |
| 4072 %{ | |
| 4073 instruction_count(2); | |
| 4074 dst : S4(write); | |
| 4075 dst : S3(read); | |
| 4076 DECODE : S0(2); // any 2 decoders | |
| 4077 ALU : S3(2); // both alus | |
| 4078 %} | |
| 4079 | |
| 4080 // Integer ALU reg operation using big decoder | |
| 4081 pipe_class ialu_reg_fat(rRegI dst) | |
| 4082 %{ | |
| 4083 single_instruction; | |
| 4084 dst : S4(write); | |
| 4085 dst : S3(read); | |
| 4086 D0 : S0; // big decoder only | |
| 4087 ALU : S3; // any alu | |
| 4088 %} | |
| 4089 | |
| 4090 // Long ALU reg operation using big decoder | |
| 4091 pipe_class ialu_reg_long_fat(rRegL dst) | |
| 4092 %{ | |
| 4093 instruction_count(2); | |
| 4094 dst : S4(write); | |
| 4095 dst : S3(read); | |
| 4096 D0 : S0(2); // big decoder only; twice | |
| 4097 ALU : S3(2); // any 2 alus | |
| 4098 %} | |
| 4099 | |
| 4100 // Integer ALU reg-reg operation | |
| 4101 pipe_class ialu_reg_reg(rRegI dst, rRegI src) | |
| 4102 %{ | |
| 4103 single_instruction; | |
| 4104 dst : S4(write); | |
| 4105 src : S3(read); | |
| 4106 DECODE : S0; // any decoder | |
| 4107 ALU : S3; // any alu | |
| 4108 %} | |
| 4109 | |
| 4110 // Long ALU reg-reg operation | |
| 4111 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src) | |
| 4112 %{ | |
| 4113 instruction_count(2); | |
| 4114 dst : S4(write); | |
| 4115 src : S3(read); | |
| 4116 DECODE : S0(2); // any 2 decoders | |
| 4117 ALU : S3(2); // both alus | |
| 4118 %} | |
| 4119 | |
| 4120 // Integer ALU reg-reg operation | |
| 4121 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) | |
| 4122 %{ | |
| 4123 single_instruction; | |
| 4124 dst : S4(write); | |
| 4125 src : S3(read); | |
| 4126 D0 : S0; // big decoder only | |
| 4127 ALU : S3; // any alu | |
| 4128 %} | |
| 4129 | |
| 4130 // Long ALU reg-reg operation | |
| 4131 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src) | |
| 4132 %{ | |
| 4133 instruction_count(2); | |
| 4134 dst : S4(write); | |
| 4135 src : S3(read); | |
| 4136 D0 : S0(2); // big decoder only; twice | |
| 4137 ALU : S3(2); // both alus | |
| 4138 %} | |
| 4139 | |
| 4140 // Integer ALU reg-mem operation | |
| 4141 pipe_class ialu_reg_mem(rRegI dst, memory mem) | |
| 4142 %{ | |
| 4143 single_instruction; | |
| 4144 dst : S5(write); | |
| 4145 mem : S3(read); | |
| 4146 D0 : S0; // big decoder only | |
| 4147 ALU : S4; // any alu | |
| 4148 MEM : S3; // any mem | |
| 4149 %} | |
| 4150 | |
| 4151 // Integer mem operation (prefetch) | |
| 4152 pipe_class ialu_mem(memory mem) | |
| 4153 %{ | |
| 4154 single_instruction; | |
| 4155 mem : S3(read); | |
| 4156 D0 : S0; // big decoder only | |
| 4157 MEM : S3; // any mem | |
| 4158 %} | |
| 4159 | |
| 4160 // Integer Store to Memory | |
| 4161 pipe_class ialu_mem_reg(memory mem, rRegI src) | |
| 4162 %{ | |
| 4163 single_instruction; | |
| 4164 mem : S3(read); | |
| 4165 src : S5(read); | |
| 4166 D0 : S0; // big decoder only | |
| 4167 ALU : S4; // any alu | |
| 4168 MEM : S3; | |
| 4169 %} | |
| 4170 | |
| 4171 // // Long Store to Memory | |
| 4172 // pipe_class ialu_mem_long_reg(memory mem, rRegL src) | |
| 4173 // %{ | |
| 4174 // instruction_count(2); | |
| 4175 // mem : S3(read); | |
| 4176 // src : S5(read); | |
| 4177 // D0 : S0(2); // big decoder only; twice | |
| 4178 // ALU : S4(2); // any 2 alus | |
| 4179 // MEM : S3(2); // Both mems | |
| 4180 // %} | |
| 4181 | |
| 4182 // Integer Store to Memory | |
| 4183 pipe_class ialu_mem_imm(memory mem) | |
| 4184 %{ | |
| 4185 single_instruction; | |
| 4186 mem : S3(read); | |
| 4187 D0 : S0; // big decoder only | |
| 4188 ALU : S4; // any alu | |
| 4189 MEM : S3; | |
| 4190 %} | |
| 4191 | |
| 4192 // Integer ALU0 reg-reg operation | |
| 4193 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) | |
| 4194 %{ | |
| 4195 single_instruction; | |
| 4196 dst : S4(write); | |
| 4197 src : S3(read); | |
| 4198 D0 : S0; // Big decoder only | |
| 4199 ALU0 : S3; // only alu0 | |
| 4200 %} | |
| 4201 | |
| 4202 // Integer ALU0 reg-mem operation | |
| 4203 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) | |
| 4204 %{ | |
| 4205 single_instruction; | |
| 4206 dst : S5(write); | |
| 4207 mem : S3(read); | |
| 4208 D0 : S0; // big decoder only | |
| 4209 ALU0 : S4; // ALU0 only | |
| 4210 MEM : S3; // any mem | |
| 4211 %} | |
| 4212 | |
| 4213 // Integer ALU reg-reg operation | |
| 4214 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2) | |
| 4215 %{ | |
| 4216 single_instruction; | |
| 4217 cr : S4(write); | |
| 4218 src1 : S3(read); | |
| 4219 src2 : S3(read); | |
| 4220 DECODE : S0; // any decoder | |
| 4221 ALU : S3; // any alu | |
| 4222 %} | |
| 4223 | |
| 4224 // Integer ALU reg-imm operation | |
| 4225 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1) | |
| 4226 %{ | |
| 4227 single_instruction; | |
| 4228 cr : S4(write); | |
| 4229 src1 : S3(read); | |
| 4230 DECODE : S0; // any decoder | |
| 4231 ALU : S3; // any alu | |
| 4232 %} | |
| 4233 | |
| 4234 // Integer ALU reg-mem operation | |
| 4235 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2) | |
| 4236 %{ | |
| 4237 single_instruction; | |
| 4238 cr : S4(write); | |
| 4239 src1 : S3(read); | |
| 4240 src2 : S3(read); | |
| 4241 D0 : S0; // big decoder only | |
| 4242 ALU : S4; // any alu | |
| 4243 MEM : S3; | |
| 4244 %} | |
| 4245 | |
| 4246 // Conditional move reg-reg | |
| 4247 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y) | |
| 4248 %{ | |
| 4249 instruction_count(4); | |
| 4250 y : S4(read); | |
| 4251 q : S3(read); | |
| 4252 p : S3(read); | |
| 4253 DECODE : S0(4); // any decoder | |
| 4254 %} | |
| 4255 | |
| 4256 // Conditional move reg-reg | |
| 4257 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr) | |
| 4258 %{ | |
| 4259 single_instruction; | |
| 4260 dst : S4(write); | |
| 4261 src : S3(read); | |
| 4262 cr : S3(read); | |
| 4263 DECODE : S0; // any decoder | |
| 4264 %} | |
| 4265 | |
| 4266 // Conditional move reg-mem | |
| 4267 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src) | |
| 4268 %{ | |
| 4269 single_instruction; | |
| 4270 dst : S4(write); | |
| 4271 src : S3(read); | |
| 4272 cr : S3(read); | |
| 4273 DECODE : S0; // any decoder | |
| 4274 MEM : S3; | |
| 4275 %} | |
| 4276 | |
| 4277 // Conditional move reg-reg long | |
| 4278 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src) | |
| 4279 %{ | |
| 4280 single_instruction; | |
| 4281 dst : S4(write); | |
| 4282 src : S3(read); | |
| 4283 cr : S3(read); | |
| 4284 DECODE : S0(2); // any 2 decoders | |
| 4285 %} | |
| 4286 | |
| 4287 // XXX | |
| 4288 // // Conditional move double reg-reg | |
| 4289 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src) | |
| 4290 // %{ | |
| 4291 // single_instruction; | |
| 4292 // dst : S4(write); | |
| 4293 // src : S3(read); | |
| 4294 // cr : S3(read); | |
| 4295 // DECODE : S0; // any decoder | |
| 4296 // %} | |
| 4297 | |
| 4298 // Float reg-reg operation | |
| 4299 pipe_class fpu_reg(regD dst) | |
| 4300 %{ | |
| 4301 instruction_count(2); | |
| 4302 dst : S3(read); | |
| 4303 DECODE : S0(2); // any 2 decoders | |
| 4304 FPU : S3; | |
| 4305 %} | |
| 4306 | |
| 4307 // Float reg-reg operation | |
| 4308 pipe_class fpu_reg_reg(regD dst, regD src) | |
| 4309 %{ | |
| 4310 instruction_count(2); | |
| 4311 dst : S4(write); | |
| 4312 src : S3(read); | |
| 4313 DECODE : S0(2); // any 2 decoders | |
| 4314 FPU : S3; | |
| 4315 %} | |
| 4316 | |
| 4317 // Float reg-reg operation | |
| 4318 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2) | |
| 4319 %{ | |
| 4320 instruction_count(3); | |
| 4321 dst : S4(write); | |
| 4322 src1 : S3(read); | |
| 4323 src2 : S3(read); | |
| 4324 DECODE : S0(3); // any 3 decoders | |
| 4325 FPU : S3(2); | |
| 4326 %} | |
| 4327 | |
| 4328 // Float reg-reg operation | |
| 4329 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3) | |
| 4330 %{ | |
| 4331 instruction_count(4); | |
| 4332 dst : S4(write); | |
| 4333 src1 : S3(read); | |
| 4334 src2 : S3(read); | |
| 4335 src3 : S3(read); | |
| 4336 DECODE : S0(4); // any 3 decoders | |
| 4337 FPU : S3(2); | |
| 4338 %} | |
| 4339 | |
| 4340 // Float reg-reg operation | |
| 4341 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3) | |
| 4342 %{ | |
| 4343 instruction_count(4); | |
| 4344 dst : S4(write); | |
| 4345 src1 : S3(read); | |
| 4346 src2 : S3(read); | |
| 4347 src3 : S3(read); | |
| 4348 DECODE : S1(3); // any 3 decoders | |
| 4349 D0 : S0; // Big decoder only | |
| 4350 FPU : S3(2); | |
| 4351 MEM : S3; | |
| 4352 %} | |
| 4353 | |
| 4354 // Float reg-mem operation | |
| 4355 pipe_class fpu_reg_mem(regD dst, memory mem) | |
| 4356 %{ | |
| 4357 instruction_count(2); | |
| 4358 dst : S5(write); | |
| 4359 mem : S3(read); | |
| 4360 D0 : S0; // big decoder only | |
| 4361 DECODE : S1; // any decoder for FPU POP | |
| 4362 FPU : S4; | |
| 4363 MEM : S3; // any mem | |
| 4364 %} | |
| 4365 | |
| 4366 // Float reg-mem operation | |
| 4367 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem) | |
| 4368 %{ | |
| 4369 instruction_count(3); | |
| 4370 dst : S5(write); | |
| 4371 src1 : S3(read); | |
| 4372 mem : S3(read); | |
| 4373 D0 : S0; // big decoder only | |
| 4374 DECODE : S1(2); // any decoder for FPU POP | |
| 4375 FPU : S4; | |
| 4376 MEM : S3; // any mem | |
| 4377 %} | |
| 4378 | |
| 4379 // Float mem-reg operation | |
| 4380 pipe_class fpu_mem_reg(memory mem, regD src) | |
| 4381 %{ | |
| 4382 instruction_count(2); | |
| 4383 src : S5(read); | |
| 4384 mem : S3(read); | |
| 4385 DECODE : S0; // any decoder for FPU PUSH | |
| 4386 D0 : S1; // big decoder only | |
| 4387 FPU : S4; | |
| 4388 MEM : S3; // any mem | |
| 4389 %} | |
| 4390 | |
| 4391 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2) | |
| 4392 %{ | |
| 4393 instruction_count(3); | |
| 4394 src1 : S3(read); | |
| 4395 src2 : S3(read); | |
| 4396 mem : S3(read); | |
| 4397 DECODE : S0(2); // any decoder for FPU PUSH | |
| 4398 D0 : S1; // big decoder only | |
| 4399 FPU : S4; | |
| 4400 MEM : S3; // any mem | |
| 4401 %} | |
| 4402 | |
| 4403 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2) | |
| 4404 %{ | |
| 4405 instruction_count(3); | |
| 4406 src1 : S3(read); | |
| 4407 src2 : S3(read); | |
| 4408 mem : S4(read); | |
| 4409 DECODE : S0; // any decoder for FPU PUSH | |
| 4410 D0 : S0(2); // big decoder only | |
| 4411 FPU : S4; | |
| 4412 MEM : S3(2); // any mem | |
| 4413 %} | |
| 4414 | |
| 4415 pipe_class fpu_mem_mem(memory dst, memory src1) | |
| 4416 %{ | |
| 4417 instruction_count(2); | |
| 4418 src1 : S3(read); | |
| 4419 dst : S4(read); | |
| 4420 D0 : S0(2); // big decoder only | |
| 4421 MEM : S3(2); // any mem | |
| 4422 %} | |
| 4423 | |
| 4424 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) | |
| 4425 %{ | |
| 4426 instruction_count(3); | |
| 4427 src1 : S3(read); | |
| 4428 src2 : S3(read); | |
| 4429 dst : S4(read); | |
| 4430 D0 : S0(3); // big decoder only | |
| 4431 FPU : S4; | |
| 4432 MEM : S3(3); // any mem | |
| 4433 %} | |
| 4434 | |
| 4435 pipe_class fpu_mem_reg_con(memory mem, regD src1) | |
| 4436 %{ | |
| 4437 instruction_count(3); | |
| 4438 src1 : S4(read); | |
| 4439 mem : S4(read); | |
| 4440 DECODE : S0; // any decoder for FPU PUSH | |
| 4441 D0 : S0(2); // big decoder only | |
| 4442 FPU : S4; | |
| 4443 MEM : S3(2); // any mem | |
| 4444 %} | |
| 4445 | |
| 4446 // Float load constant | |
| 4447 pipe_class fpu_reg_con(regD dst) | |
| 4448 %{ | |
| 4449 instruction_count(2); | |
| 4450 dst : S5(write); | |
| 4451 D0 : S0; // big decoder only for the load | |
| 4452 DECODE : S1; // any decoder for FPU POP | |
| 4453 FPU : S4; | |
| 4454 MEM : S3; // any mem | |
| 4455 %} | |
| 4456 | |
| 4457 // Float load constant | |
| 4458 pipe_class fpu_reg_reg_con(regD dst, regD src) | |
| 4459 %{ | |
| 4460 instruction_count(3); | |
| 4461 dst : S5(write); | |
| 4462 src : S3(read); | |
| 4463 D0 : S0; // big decoder only for the load | |
| 4464 DECODE : S1(2); // any decoder for FPU POP | |
| 4465 FPU : S4; | |
| 4466 MEM : S3; // any mem | |
| 4467 %} | |
| 4468 | |
| 4469 // UnConditional branch | |
| 4470 pipe_class pipe_jmp(label labl) | |
| 4471 %{ | |
| 4472 single_instruction; | |
| 4473 BR : S3; | |
| 4474 %} | |
| 4475 | |
| 4476 // Conditional branch | |
| 4477 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl) | |
| 4478 %{ | |
| 4479 single_instruction; | |
| 4480 cr : S1(read); | |
| 4481 BR : S3; | |
| 4482 %} | |
| 4483 | |
| 4484 // Allocation idiom | |
| 4485 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr) | |
| 4486 %{ | |
| 4487 instruction_count(1); force_serialization; | |
| 4488 fixed_latency(6); | |
| 4489 heap_ptr : S3(read); | |
| 4490 DECODE : S0(3); | |
| 4491 D0 : S2; | |
| 4492 MEM : S3; | |
| 4493 ALU : S3(2); | |
| 4494 dst : S5(write); | |
| 4495 BR : S5; | |
| 4496 %} | |
| 4497 | |
| 4498 // Generic big/slow expanded idiom | |
| 4499 pipe_class pipe_slow() | |
| 4500 %{ | |
| 4501 instruction_count(10); multiple_bundles; force_serialization; | |
| 4502 fixed_latency(100); | |
| 4503 D0 : S0(2); | |
| 4504 MEM : S3(2); | |
| 4505 %} | |
| 4506 | |
| 4507 // The real do-nothing guy | |
| 4508 pipe_class empty() | |
| 4509 %{ | |
| 4510 instruction_count(0); | |
| 4511 %} | |
| 4512 | |
| 4513 // Define the class for the Nop node | |
| 4514 define | |
| 4515 %{ | |
| 4516 MachNop = empty; | |
| 4517 %} | |
| 4518 | |
| 4519 %} | |
| 4520 | |
| 4521 //----------INSTRUCTIONS------------------------------------------------------- | |
| 4522 // | |
| 4523 // match -- States which machine-independent subtree may be replaced | |
| 4524 // by this instruction. | |
| 4525 // ins_cost -- The estimated cost of this instruction is used by instruction | |
| 4526 // selection to identify a minimum cost tree of machine | |
| 4527 // instructions that matches a tree of machine-independent | |
| 4528 // instructions. | |
| 4529 // format -- A string providing the disassembly for this instruction. | |
| 4530 // The value of an instruction's operand may be inserted | |
| 4531 // by referring to it with a '$' prefix. | |
| 4532 // opcode -- Three instruction opcodes may be provided. These are referred | |
| 4533 // to within an encode class as $primary, $secondary, and $tertiary | |
| 4534 // rrspectively. The primary opcode is commonly used to | |
| 4535 // indicate the type of machine instruction, while secondary | |
| 4536 // and tertiary are often used for prefix options or addressing | |
| 4537 // modes. | |
| 4538 // ins_encode -- A list of encode classes with parameters. The encode class | |
| 4539 // name must have been defined in an 'enc_class' specification | |
| 4540 // in the encode section of the architecture description. | |
| 4541 | |
| 4542 | |
| 4543 //----------Load/Store/Move Instructions--------------------------------------- | |
| 4544 //----------Load Instructions-------------------------------------------------- | |
| 4545 | |
| 4546 // Load Byte (8 bit signed) | |
| 4547 instruct loadB(rRegI dst, memory mem) | |
| 4548 %{ | |
| 4549 match(Set dst (LoadB mem)); | |
| 4550 | |
| 4551 ins_cost(125); | |
| 4552 format %{ "movsbl $dst, $mem\t# byte" %} | |
| 624 | 4553 |
| 4554 ins_encode %{ | |
| 4555 __ movsbl($dst$$Register, $mem$$Address); | |
| 4556 %} | |
| 4557 | |
| 0 | 4558 ins_pipe(ialu_reg_mem); |
| 4559 %} | |
| 4560 | |
| 624 | 4561 // Load Byte (8 bit signed) into Long Register |
| 4562 instruct loadB2L(rRegL dst, memory mem) | |
| 4563 %{ | |
| 4564 match(Set dst (ConvI2L (LoadB mem))); | |
| 4565 | |
| 4566 ins_cost(125); | |
| 4567 format %{ "movsbq $dst, $mem\t# byte -> long" %} | |
| 4568 | |
| 4569 ins_encode %{ | |
| 4570 __ movsbq($dst$$Register, $mem$$Address); | |
| 4571 %} | |
| 4572 | |
| 4573 ins_pipe(ialu_reg_mem); | |
| 4574 %} | |
| 4575 | |
| 4576 // Load Unsigned Byte (8 bit UNsigned) | |
| 4577 instruct loadUB(rRegI dst, memory mem) | |
| 4578 %{ | |
| 4579 match(Set dst (LoadUB mem)); | |
| 0 | 4580 |
| 4581 ins_cost(125); | |
| 4582 format %{ "movzbl $dst, $mem\t# ubyte" %} | |
| 624 | 4583 |
| 4584 ins_encode %{ | |
| 4585 __ movzbl($dst$$Register, $mem$$Address); | |
| 4586 %} | |
| 4587 | |
| 0 | 4588 ins_pipe(ialu_reg_mem); |
| 4589 %} | |
| 4590 | |
| 624 | 4591 // Load Unsigned Byte (8 bit UNsigned) into Long Register |
| 4592 instruct loadUB2L(rRegL dst, memory mem) | |
| 4593 %{ | |
| 4594 match(Set dst (ConvI2L (LoadUB mem))); | |
| 4595 | |
| 4596 ins_cost(125); | |
| 4597 format %{ "movzbq $dst, $mem\t# ubyte -> long" %} | |
| 4598 | |
| 4599 ins_encode %{ | |
| 4600 __ movzbq($dst$$Register, $mem$$Address); | |
| 4601 %} | |
| 4602 | |
| 4603 ins_pipe(ialu_reg_mem); | |
| 4604 %} | |
| 0 | 4605 |
| 824 | 4606 // Load Unsigned Byte (8 bit UNsigned) with a 8-bit mask into Long Register |
| 4607 instruct loadUB2L_immI8(rRegL dst, memory mem, immI8 mask, rFlagsReg cr) %{ | |
| 4608 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); | |
| 4609 effect(KILL cr); | |
| 4610 | |
| 4611 format %{ "movzbq $dst, $mem\t# ubyte & 8-bit mask -> long\n\t" | |
| 4612 "andl $dst, $mask" %} | |
| 4613 ins_encode %{ | |
| 4614 Register Rdst = $dst$$Register; | |
| 4615 __ movzbq(Rdst, $mem$$Address); | |
| 4616 __ andl(Rdst, $mask$$constant); | |
| 4617 %} | |
| 4618 ins_pipe(ialu_reg_mem); | |
| 4619 %} | |
| 4620 | |
| 0 | 4621 // Load Short (16 bit signed) |
| 4622 instruct loadS(rRegI dst, memory mem) | |
| 4623 %{ | |
| 4624 match(Set dst (LoadS mem)); | |
| 4625 | |
| 624 | 4626 ins_cost(125); |
| 0 | 4627 format %{ "movswl $dst, $mem\t# short" %} |
| 624 | 4628 |
| 4629 ins_encode %{ | |
| 4630 __ movswl($dst$$Register, $mem$$Address); | |
| 4631 %} | |
| 4632 | |
| 0 | 4633 ins_pipe(ialu_reg_mem); |
| 4634 %} | |
| 4635 | |
| 785 | 4636 // Load Short (16 bit signed) to Byte (8 bit signed) |
| 4637 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{ | |
| 4638 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); | |
| 4639 | |
| 4640 ins_cost(125); | |
| 4641 format %{ "movsbl $dst, $mem\t# short -> byte" %} | |
| 4642 ins_encode %{ | |
| 4643 __ movsbl($dst$$Register, $mem$$Address); | |
| 4644 %} | |
| 4645 ins_pipe(ialu_reg_mem); | |
| 4646 %} | |
| 4647 | |
| 624 | 4648 // Load Short (16 bit signed) into Long Register |
| 4649 instruct loadS2L(rRegL dst, memory mem) | |
| 4650 %{ | |
| 4651 match(Set dst (ConvI2L (LoadS mem))); | |
| 4652 | |
| 4653 ins_cost(125); | |
| 4654 format %{ "movswq $dst, $mem\t# short -> long" %} | |
| 4655 | |
| 4656 ins_encode %{ | |
| 4657 __ movswq($dst$$Register, $mem$$Address); | |
| 4658 %} | |
| 4659 | |
| 4660 ins_pipe(ialu_reg_mem); | |
| 4661 %} | |
| 0 | 4662 |
|
558
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents:
420
diff
changeset
|
4663 // Load Unsigned Short/Char (16 bit UNsigned) |
|
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents:
420
diff
changeset
|
4664 instruct loadUS(rRegI dst, memory mem) |
|
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents:
420
diff
changeset
|
4665 %{ |
|
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents:
420
diff
changeset
|
4666 match(Set dst (LoadUS mem)); |
| 0 | 4667 |
| 4668 ins_cost(125); | |
|
558
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents:
420
diff
changeset
|
4669 format %{ "movzwl $dst, $mem\t# ushort/char" %} |
| 624 | 4670 |
| 4671 ins_encode %{ | |
| 4672 __ movzwl($dst$$Register, $mem$$Address); | |
| 4673 %} | |
| 4674 | |
| 0 | 4675 ins_pipe(ialu_reg_mem); |
| 4676 %} | |
| 4677 | |
| 785 | 4678 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) |
| 4679 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{ | |
| 4680 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); | |
| 4681 | |
| 4682 ins_cost(125); | |
| 4683 format %{ "movsbl $dst, $mem\t# ushort -> byte" %} | |
| 4684 ins_encode %{ | |
| 4685 __ movsbl($dst$$Register, $mem$$Address); | |
| 4686 %} | |
| 4687 ins_pipe(ialu_reg_mem); | |
| 4688 %} | |
| 4689 | |
| 624 | 4690 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register |
| 4691 instruct loadUS2L(rRegL dst, memory mem) | |
| 4692 %{ | |
| 4693 match(Set dst (ConvI2L (LoadUS mem))); | |
| 4694 | |
| 4695 ins_cost(125); | |
| 4696 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %} | |
| 4697 | |
| 4698 ins_encode %{ | |
| 4699 __ movzwq($dst$$Register, $mem$$Address); | |
| 4700 %} | |
| 4701 | |
| 4702 ins_pipe(ialu_reg_mem); | |
| 4703 %} | |
| 0 | 4704 |
| 824 | 4705 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register |
| 4706 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{ | |
| 4707 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 4708 | |
| 4709 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %} | |
| 4710 ins_encode %{ | |
| 4711 __ movzbq($dst$$Register, $mem$$Address); | |
| 4712 %} | |
| 4713 ins_pipe(ialu_reg_mem); | |
| 4714 %} | |
| 4715 | |
| 4716 // Load Unsigned Short/Char (16 bit UNsigned) with mask into Long Register | |
| 4717 instruct loadUS2L_immI16(rRegL dst, memory mem, immI16 mask, rFlagsReg cr) %{ | |
| 4718 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 4719 effect(KILL cr); | |
| 4720 | |
| 4721 format %{ "movzwq $dst, $mem\t# ushort/char & 16-bit mask -> long\n\t" | |
| 4722 "andl $dst, $mask" %} | |
| 4723 ins_encode %{ | |
| 4724 Register Rdst = $dst$$Register; | |
| 4725 __ movzwq(Rdst, $mem$$Address); | |
| 4726 __ andl(Rdst, $mask$$constant); | |
| 4727 %} | |
| 4728 ins_pipe(ialu_reg_mem); | |
| 4729 %} | |
| 4730 | |
| 0 | 4731 // Load Integer |
| 4732 instruct loadI(rRegI dst, memory mem) | |
| 4733 %{ | |
| 4734 match(Set dst (LoadI mem)); | |
| 4735 | |
| 624 | 4736 ins_cost(125); |
| 0 | 4737 format %{ "movl $dst, $mem\t# int" %} |
| 624 | 4738 |
| 4739 ins_encode %{ | |
| 4740 __ movl($dst$$Register, $mem$$Address); | |
| 4741 %} | |
| 4742 | |
| 4743 ins_pipe(ialu_reg_mem); | |
| 4744 %} | |
| 4745 | |
| 785 | 4746 // Load Integer (32 bit signed) to Byte (8 bit signed) |
| 4747 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{ | |
| 4748 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); | |
| 4749 | |
| 4750 ins_cost(125); | |
| 4751 format %{ "movsbl $dst, $mem\t# int -> byte" %} | |
| 4752 ins_encode %{ | |
| 4753 __ movsbl($dst$$Register, $mem$$Address); | |
| 4754 %} | |
| 4755 ins_pipe(ialu_reg_mem); | |
| 4756 %} | |
| 4757 | |
| 4758 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned) | |
| 4759 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{ | |
| 4760 match(Set dst (AndI (LoadI mem) mask)); | |
| 4761 | |
| 4762 ins_cost(125); | |
| 4763 format %{ "movzbl $dst, $mem\t# int -> ubyte" %} | |
| 4764 ins_encode %{ | |
| 4765 __ movzbl($dst$$Register, $mem$$Address); | |
| 4766 %} | |
| 4767 ins_pipe(ialu_reg_mem); | |
| 4768 %} | |
| 4769 | |
| 4770 // Load Integer (32 bit signed) to Short (16 bit signed) | |
| 4771 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{ | |
| 4772 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); | |
| 4773 | |
| 4774 ins_cost(125); | |
| 4775 format %{ "movswl $dst, $mem\t# int -> short" %} | |
| 4776 ins_encode %{ | |
| 4777 __ movswl($dst$$Register, $mem$$Address); | |
| 4778 %} | |
| 4779 ins_pipe(ialu_reg_mem); | |
| 4780 %} | |
| 4781 | |
| 4782 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned) | |
| 4783 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{ | |
| 4784 match(Set dst (AndI (LoadI mem) mask)); | |
| 4785 | |
| 4786 ins_cost(125); | |
| 4787 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %} | |
| 4788 ins_encode %{ | |
| 4789 __ movzwl($dst$$Register, $mem$$Address); | |
| 4790 %} | |
| 4791 ins_pipe(ialu_reg_mem); | |
| 4792 %} | |
| 4793 | |
| 624 | 4794 // Load Integer into Long Register |
| 4795 instruct loadI2L(rRegL dst, memory mem) | |
| 4796 %{ | |
| 4797 match(Set dst (ConvI2L (LoadI mem))); | |
| 4798 | |
| 4799 ins_cost(125); | |
| 4800 format %{ "movslq $dst, $mem\t# int -> long" %} | |
| 4801 | |
| 4802 ins_encode %{ | |
| 4803 __ movslq($dst$$Register, $mem$$Address); | |
| 4804 %} | |
| 4805 | |
| 4806 ins_pipe(ialu_reg_mem); | |
| 4807 %} | |
| 4808 | |
| 824 | 4809 // Load Integer with mask 0xFF into Long Register |
| 4810 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{ | |
| 4811 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 4812 | |
| 4813 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %} | |
| 4814 ins_encode %{ | |
| 4815 __ movzbq($dst$$Register, $mem$$Address); | |
| 4816 %} | |
| 4817 ins_pipe(ialu_reg_mem); | |
| 4818 %} | |
| 4819 | |
| 4820 // Load Integer with mask 0xFFFF into Long Register | |
| 4821 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{ | |
| 4822 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 4823 | |
| 4824 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %} | |
| 4825 ins_encode %{ | |
| 4826 __ movzwq($dst$$Register, $mem$$Address); | |
| 4827 %} | |
| 4828 ins_pipe(ialu_reg_mem); | |
| 4829 %} | |
| 4830 | |
|
17506
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
12972
diff
changeset
|
4831 // Load Integer with a 31-bit mask into Long Register |
|
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
12972
diff
changeset
|
4832 instruct loadI2L_immU31(rRegL dst, memory mem, immU31 mask, rFlagsReg cr) %{ |
| 824 | 4833 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); |
| 4834 effect(KILL cr); | |
| 4835 | |
|
17506
984401824c5e
8031743: C2: loadI2L_immI broken for negative memory values
iveresov
parents:
12972
diff
changeset
|
4836 format %{ "movl $dst, $mem\t# int & 31-bit mask -> long\n\t" |
| 824 | 4837 "andl $dst, $mask" %} |
| 4838 ins_encode %{ | |
| 4839 Register Rdst = $dst$$Register; | |
| 4840 __ movl(Rdst, $mem$$Address); | |
| 4841 __ andl(Rdst, $mask$$constant); | |
| 4842 %} | |
| 4843 ins_pipe(ialu_reg_mem); | |
| 4844 %} | |
| 4845 | |
| 624 | 4846 // Load Unsigned Integer into Long Register |
| 6849 | 4847 instruct loadUI2L(rRegL dst, memory mem, immL_32bits mask) |
| 4848 %{ | |
| 4849 match(Set dst (AndL (ConvI2L (LoadI mem)) mask)); | |
| 624 | 4850 |
| 4851 ins_cost(125); | |
| 4852 format %{ "movl $dst, $mem\t# uint -> long" %} | |
| 4853 | |
| 4854 ins_encode %{ | |
| 4855 __ movl($dst$$Register, $mem$$Address); | |
| 4856 %} | |
| 4857 | |
| 0 | 4858 ins_pipe(ialu_reg_mem); |
| 4859 %} | |
| 4860 | |
| 4861 // Load Long | |
| 4862 instruct loadL(rRegL dst, memory mem) | |
| 4863 %{ | |
| 4864 match(Set dst (LoadL mem)); | |
| 4865 | |
| 624 | 4866 ins_cost(125); |
| 0 | 4867 format %{ "movq $dst, $mem\t# long" %} |
| 624 | 4868 |
| 4869 ins_encode %{ | |
| 4870 __ movq($dst$$Register, $mem$$Address); | |
| 4871 %} | |
| 4872 | |
| 0 | 4873 ins_pipe(ialu_reg_mem); // XXX |
| 4874 %} | |
| 4875 | |
| 4876 // Load Range | |
| 4877 instruct loadRange(rRegI dst, memory mem) | |
| 4878 %{ | |
| 4879 match(Set dst (LoadRange mem)); | |
| 4880 | |
| 4881 ins_cost(125); // XXX | |
| 4882 format %{ "movl $dst, $mem\t# range" %} | |
| 4883 opcode(0x8B); | |
| 4884 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 4885 ins_pipe(ialu_reg_mem); | |
| 4886 %} | |
| 4887 | |
| 4888 // Load Pointer | |
| 4889 instruct loadP(rRegP dst, memory mem) | |
| 4890 %{ | |
| 4891 match(Set dst (LoadP mem)); | |
| 4892 | |
| 4893 ins_cost(125); // XXX | |
| 4894 format %{ "movq $dst, $mem\t# ptr" %} | |
| 4895 opcode(0x8B); | |
| 4896 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 4897 ins_pipe(ialu_reg_mem); // XXX | |
| 4898 %} | |
| 4899 | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
4900 // Load Compressed Pointer |
| 163 | 4901 instruct loadN(rRegN dst, memory mem) |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
4902 %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
4903 match(Set dst (LoadN mem)); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
4904 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
4905 ins_cost(125); // XXX |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
4906 format %{ "movl $dst, $mem\t# compressed ptr" %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
4907 ins_encode %{ |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4908 __ movl($dst$$Register, $mem$$Address); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
4909 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
4910 ins_pipe(ialu_reg_mem); // XXX |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
4911 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
4912 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
4913 |
| 0 | 4914 // Load Klass Pointer |
| 4915 instruct loadKlass(rRegP dst, memory mem) | |
| 4916 %{ | |
| 4917 match(Set dst (LoadKlass mem)); | |
| 4918 | |
| 4919 ins_cost(125); // XXX | |
| 4920 format %{ "movq $dst, $mem\t# class" %} | |
| 4921 opcode(0x8B); | |
| 4922 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 4923 ins_pipe(ialu_reg_mem); // XXX | |
| 4924 %} | |
| 4925 | |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
4926 // Load narrow Klass Pointer |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
4927 instruct loadNKlass(rRegN dst, memory mem) |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
4928 %{ |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
4929 match(Set dst (LoadNKlass mem)); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
4930 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
4931 ins_cost(125); // XXX |
|
182
44abbb0d4c18
6709093: Compressed Oops: reduce size of compiled methods
kvn
parents:
169
diff
changeset
|
4932 format %{ "movl $dst, $mem\t# compressed klass ptr" %} |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
4933 ins_encode %{ |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4934 __ movl($dst$$Register, $mem$$Address); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
4935 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
4936 ins_pipe(ialu_reg_mem); // XXX |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
4937 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
4938 |
| 0 | 4939 // Load Float |
| 4940 instruct loadF(regF dst, memory mem) | |
| 4941 %{ | |
| 4942 match(Set dst (LoadF mem)); | |
| 4943 | |
| 4944 ins_cost(145); // XXX | |
| 4945 format %{ "movss $dst, $mem\t# float" %} | |
| 4759 | 4946 ins_encode %{ |
| 4947 __ movflt($dst$$XMMRegister, $mem$$Address); | |
| 4948 %} | |
| 0 | 4949 ins_pipe(pipe_slow); // XXX |
| 4950 %} | |
| 4951 | |
| 4952 // Load Double | |
| 4953 instruct loadD_partial(regD dst, memory mem) | |
| 4954 %{ | |
| 4955 predicate(!UseXmmLoadAndClearUpper); | |
| 4956 match(Set dst (LoadD mem)); | |
| 4957 | |
| 4958 ins_cost(145); // XXX | |
| 4959 format %{ "movlpd $dst, $mem\t# double" %} | |
| 4759 | 4960 ins_encode %{ |
| 4961 __ movdbl($dst$$XMMRegister, $mem$$Address); | |
| 4962 %} | |
| 0 | 4963 ins_pipe(pipe_slow); // XXX |
| 4964 %} | |
| 4965 | |
| 4966 instruct loadD(regD dst, memory mem) | |
| 4967 %{ | |
| 4968 predicate(UseXmmLoadAndClearUpper); | |
| 4969 match(Set dst (LoadD mem)); | |
| 4970 | |
| 4971 ins_cost(145); // XXX | |
| 4972 format %{ "movsd $dst, $mem\t# double" %} | |
| 4759 | 4973 ins_encode %{ |
| 4974 __ movdbl($dst$$XMMRegister, $mem$$Address); | |
| 4975 %} | |
| 0 | 4976 ins_pipe(pipe_slow); // XXX |
| 4977 %} | |
| 4978 | |
| 4979 // Load Effective Address | |
| 4980 instruct leaP8(rRegP dst, indOffset8 mem) | |
| 4981 %{ | |
| 4982 match(Set dst mem); | |
| 4983 | |
| 4984 ins_cost(110); // XXX | |
| 4985 format %{ "leaq $dst, $mem\t# ptr 8" %} | |
| 4986 opcode(0x8D); | |
| 4987 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 4988 ins_pipe(ialu_reg_reg_fat); | |
| 4989 %} | |
| 4990 | |
| 4991 instruct leaP32(rRegP dst, indOffset32 mem) | |
| 4992 %{ | |
| 4993 match(Set dst mem); | |
| 4994 | |
| 4995 ins_cost(110); | |
| 4996 format %{ "leaq $dst, $mem\t# ptr 32" %} | |
| 4997 opcode(0x8D); | |
| 4998 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 4999 ins_pipe(ialu_reg_reg_fat); | |
| 5000 %} | |
| 5001 | |
| 5002 // instruct leaPIdx(rRegP dst, indIndex mem) | |
| 5003 // %{ | |
| 5004 // match(Set dst mem); | |
| 5005 | |
| 5006 // ins_cost(110); | |
| 5007 // format %{ "leaq $dst, $mem\t# ptr idx" %} | |
| 5008 // opcode(0x8D); | |
| 5009 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5010 // ins_pipe(ialu_reg_reg_fat); | |
| 5011 // %} | |
| 5012 | |
| 5013 instruct leaPIdxOff(rRegP dst, indIndexOffset mem) | |
| 5014 %{ | |
| 5015 match(Set dst mem); | |
| 5016 | |
| 5017 ins_cost(110); | |
| 5018 format %{ "leaq $dst, $mem\t# ptr idxoff" %} | |
| 5019 opcode(0x8D); | |
| 5020 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5021 ins_pipe(ialu_reg_reg_fat); | |
| 5022 %} | |
| 5023 | |
| 5024 instruct leaPIdxScale(rRegP dst, indIndexScale mem) | |
| 5025 %{ | |
| 5026 match(Set dst mem); | |
| 5027 | |
| 5028 ins_cost(110); | |
| 5029 format %{ "leaq $dst, $mem\t# ptr idxscale" %} | |
| 5030 opcode(0x8D); | |
| 5031 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5032 ins_pipe(ialu_reg_reg_fat); | |
| 5033 %} | |
| 5034 | |
| 5035 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem) | |
| 5036 %{ | |
| 5037 match(Set dst mem); | |
| 5038 | |
| 5039 ins_cost(110); | |
| 5040 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %} | |
| 5041 opcode(0x8D); | |
| 5042 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5043 ins_pipe(ialu_reg_reg_fat); | |
| 5044 %} | |
| 5045 | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5046 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5047 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5048 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5049 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5050 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5051 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5052 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5053 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5054 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5055 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5056 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5057 // Load Effective Address which uses Narrow (32-bits) oop |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5058 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5059 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5060 predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5061 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5062 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5063 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5064 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5065 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5066 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5067 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5068 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5069 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5070 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5071 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5072 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5073 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5074 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5075 ins_cost(110); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5076 format %{ "leaq $dst, $mem\t# ptr off8narrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5077 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5078 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5079 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5080 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5081 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5082 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5083 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5084 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5085 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5086 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5087 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5088 format %{ "leaq $dst, $mem\t# ptr off32narrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5089 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5090 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5091 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5092 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5093 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5094 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5095 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5096 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5097 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5098 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5099 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5100 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5101 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5102 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5103 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5104 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5105 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5106 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5107 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5108 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5109 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5110 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5111 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5112 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5113 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5114 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5115 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5116 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5117 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5118 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5119 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5120 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5121 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5122 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5123 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5124 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5125 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5126 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5127 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5128 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5129 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5130 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5131 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5132 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5133 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5134 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5135 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5136 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5137 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5138 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5139 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5140 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5141 |
| 0 | 5142 instruct loadConI(rRegI dst, immI src) |
| 5143 %{ | |
| 5144 match(Set dst src); | |
| 5145 | |
| 5146 format %{ "movl $dst, $src\t# int" %} | |
| 5147 ins_encode(load_immI(dst, src)); | |
| 5148 ins_pipe(ialu_reg_fat); // XXX | |
| 5149 %} | |
| 5150 | |
| 5151 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr) | |
| 5152 %{ | |
| 5153 match(Set dst src); | |
| 5154 effect(KILL cr); | |
| 5155 | |
| 5156 ins_cost(50); | |
| 5157 format %{ "xorl $dst, $dst\t# int" %} | |
| 5158 opcode(0x33); /* + rd */ | |
| 5159 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst)); | |
| 5160 ins_pipe(ialu_reg); | |
| 5161 %} | |
| 5162 | |
| 5163 instruct loadConL(rRegL dst, immL src) | |
| 5164 %{ | |
| 5165 match(Set dst src); | |
| 5166 | |
| 5167 ins_cost(150); | |
| 5168 format %{ "movq $dst, $src\t# long" %} | |
| 5169 ins_encode(load_immL(dst, src)); | |
| 5170 ins_pipe(ialu_reg); | |
| 5171 %} | |
| 5172 | |
| 5173 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr) | |
| 5174 %{ | |
| 5175 match(Set dst src); | |
| 5176 effect(KILL cr); | |
| 5177 | |
| 5178 ins_cost(50); | |
| 5179 format %{ "xorl $dst, $dst\t# long" %} | |
| 5180 opcode(0x33); /* + rd */ | |
| 5181 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst)); | |
| 5182 ins_pipe(ialu_reg); // XXX | |
| 5183 %} | |
| 5184 | |
| 5185 instruct loadConUL32(rRegL dst, immUL32 src) | |
| 5186 %{ | |
| 5187 match(Set dst src); | |
| 5188 | |
| 5189 ins_cost(60); | |
| 5190 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %} | |
| 5191 ins_encode(load_immUL32(dst, src)); | |
| 5192 ins_pipe(ialu_reg); | |
| 5193 %} | |
| 5194 | |
| 5195 instruct loadConL32(rRegL dst, immL32 src) | |
| 5196 %{ | |
| 5197 match(Set dst src); | |
| 5198 | |
| 5199 ins_cost(70); | |
| 5200 format %{ "movq $dst, $src\t# long (32-bit)" %} | |
| 5201 ins_encode(load_immL32(dst, src)); | |
| 5202 ins_pipe(ialu_reg); | |
| 5203 %} | |
| 5204 | |
| 2008 | 5205 instruct loadConP(rRegP dst, immP con) %{ |
| 5206 match(Set dst con); | |
| 5207 | |
| 5208 format %{ "movq $dst, $con\t# ptr" %} | |
| 5209 ins_encode(load_immP(dst, con)); | |
| 0 | 5210 ins_pipe(ialu_reg_fat); // XXX |
| 5211 %} | |
| 5212 | |
| 5213 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr) | |
| 5214 %{ | |
| 5215 match(Set dst src); | |
| 5216 effect(KILL cr); | |
| 5217 | |
| 5218 ins_cost(50); | |
| 5219 format %{ "xorl $dst, $dst\t# ptr" %} | |
| 5220 opcode(0x33); /* + rd */ | |
| 5221 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst)); | |
| 5222 ins_pipe(ialu_reg); | |
| 5223 %} | |
| 5224 | |
| 5225 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr) | |
| 5226 %{ | |
| 5227 match(Set dst src); | |
| 5228 effect(KILL cr); | |
| 5229 | |
| 5230 ins_cost(60); | |
| 5231 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %} | |
| 5232 ins_encode(load_immP31(dst, src)); | |
| 5233 ins_pipe(ialu_reg); | |
| 5234 %} | |
| 5235 | |
| 2008 | 5236 instruct loadConF(regF dst, immF con) %{ |
| 5237 match(Set dst con); | |
| 0 | 5238 ins_cost(125); |
| 2008 | 5239 format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %} |
| 5240 ins_encode %{ | |
| 5241 __ movflt($dst$$XMMRegister, $constantaddress($con)); | |
| 5242 %} | |
| 0 | 5243 ins_pipe(pipe_slow); |
| 5244 %} | |
| 5245 | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5246 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5247 match(Set dst src); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5248 effect(KILL cr); |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
5249 format %{ "xorq $dst, $src\t# compressed NULL ptr" %} |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5250 ins_encode %{ |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5251 __ xorq($dst$$Register, $dst$$Register); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5252 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5253 ins_pipe(ialu_reg); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5254 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5255 |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
5256 instruct loadConN(rRegN dst, immN src) %{ |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5257 match(Set dst src); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5258 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5259 ins_cost(125); |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
5260 format %{ "movl $dst, $src\t# compressed ptr" %} |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5261 ins_encode %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5262 address con = (address)$src$$constant; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5263 if (con == NULL) { |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5264 ShouldNotReachHere(); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5265 } else { |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5266 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5267 } |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5268 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5269 ins_pipe(ialu_reg_fat); // XXX |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5270 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5271 |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5272 instruct loadConNKlass(rRegN dst, immNKlass src) %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5273 match(Set dst src); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5274 |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5275 ins_cost(125); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5276 format %{ "movl $dst, $src\t# compressed klass ptr" %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5277 ins_encode %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5278 address con = (address)$src$$constant; |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5279 if (con == NULL) { |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5280 ShouldNotReachHere(); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5281 } else { |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5282 __ set_narrow_klass($dst$$Register, (Klass*)$src$$constant); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5283 } |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5284 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5285 ins_pipe(ialu_reg_fat); // XXX |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5286 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5287 |
| 0 | 5288 instruct loadConF0(regF dst, immF0 src) |
| 5289 %{ | |
| 5290 match(Set dst src); | |
| 5291 ins_cost(100); | |
| 5292 | |
| 5293 format %{ "xorps $dst, $dst\t# float 0.0" %} | |
| 4759 | 5294 ins_encode %{ |
| 5295 __ xorps($dst$$XMMRegister, $dst$$XMMRegister); | |
| 5296 %} | |
| 0 | 5297 ins_pipe(pipe_slow); |
| 5298 %} | |
| 5299 | |
| 5300 // Use the same format since predicate() can not be used here. | |
| 2008 | 5301 instruct loadConD(regD dst, immD con) %{ |
| 5302 match(Set dst con); | |
| 0 | 5303 ins_cost(125); |
| 2008 | 5304 format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %} |
| 5305 ins_encode %{ | |
| 5306 __ movdbl($dst$$XMMRegister, $constantaddress($con)); | |
| 5307 %} | |
| 0 | 5308 ins_pipe(pipe_slow); |
| 5309 %} | |
| 5310 | |
| 5311 instruct loadConD0(regD dst, immD0 src) | |
| 5312 %{ | |
| 5313 match(Set dst src); | |
| 5314 ins_cost(100); | |
| 5315 | |
| 5316 format %{ "xorpd $dst, $dst\t# double 0.0" %} | |
| 4759 | 5317 ins_encode %{ |
| 5318 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister); | |
| 5319 %} | |
| 0 | 5320 ins_pipe(pipe_slow); |
| 5321 %} | |
| 5322 | |
| 5323 instruct loadSSI(rRegI dst, stackSlotI src) | |
| 5324 %{ | |
| 5325 match(Set dst src); | |
| 5326 | |
| 5327 ins_cost(125); | |
| 5328 format %{ "movl $dst, $src\t# int stk" %} | |
| 5329 opcode(0x8B); | |
| 5330 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 5331 ins_pipe(ialu_reg_mem); | |
| 5332 %} | |
| 5333 | |
| 5334 instruct loadSSL(rRegL dst, stackSlotL src) | |
| 5335 %{ | |
| 5336 match(Set dst src); | |
| 5337 | |
| 5338 ins_cost(125); | |
| 5339 format %{ "movq $dst, $src\t# long stk" %} | |
| 5340 opcode(0x8B); | |
| 5341 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 5342 ins_pipe(ialu_reg_mem); | |
| 5343 %} | |
| 5344 | |
| 5345 instruct loadSSP(rRegP dst, stackSlotP src) | |
| 5346 %{ | |
| 5347 match(Set dst src); | |
| 5348 | |
| 5349 ins_cost(125); | |
| 5350 format %{ "movq $dst, $src\t# ptr stk" %} | |
| 5351 opcode(0x8B); | |
| 5352 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 5353 ins_pipe(ialu_reg_mem); | |
| 5354 %} | |
| 5355 | |
| 5356 instruct loadSSF(regF dst, stackSlotF src) | |
| 5357 %{ | |
| 5358 match(Set dst src); | |
| 5359 | |
| 5360 ins_cost(125); | |
| 5361 format %{ "movss $dst, $src\t# float stk" %} | |
| 4759 | 5362 ins_encode %{ |
| 5363 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 5364 %} | |
| 0 | 5365 ins_pipe(pipe_slow); // XXX |
| 5366 %} | |
| 5367 | |
| 5368 // Use the same format since predicate() can not be used here. | |
| 5369 instruct loadSSD(regD dst, stackSlotD src) | |
| 5370 %{ | |
| 5371 match(Set dst src); | |
| 5372 | |
| 5373 ins_cost(125); | |
| 5374 format %{ "movsd $dst, $src\t# double stk" %} | |
| 5375 ins_encode %{ | |
| 5376 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 5377 %} | |
| 5378 ins_pipe(pipe_slow); // XXX | |
| 5379 %} | |
| 5380 | |
| 5381 // Prefetch instructions. | |
| 5382 // Must be safe to execute with invalid address (cannot fault). | |
| 5383 | |
| 5384 instruct prefetchr( memory mem ) %{ | |
| 5385 predicate(ReadPrefetchInstr==3); | |
| 5386 match(PrefetchRead mem); | |
| 5387 ins_cost(125); | |
| 5388 | |
| 5389 format %{ "PREFETCHR $mem\t# Prefetch into level 1 cache" %} | |
| 3854 | 5390 ins_encode %{ |
| 5391 __ prefetchr($mem$$Address); | |
| 5392 %} | |
| 0 | 5393 ins_pipe(ialu_mem); |
| 5394 %} | |
| 5395 | |
| 5396 instruct prefetchrNTA( memory mem ) %{ | |
| 5397 predicate(ReadPrefetchInstr==0); | |
| 5398 match(PrefetchRead mem); | |
| 5399 ins_cost(125); | |
| 5400 | |
| 5401 format %{ "PREFETCHNTA $mem\t# Prefetch into non-temporal cache for read" %} | |
| 3854 | 5402 ins_encode %{ |
| 5403 __ prefetchnta($mem$$Address); | |
| 5404 %} | |
| 0 | 5405 ins_pipe(ialu_mem); |
| 5406 %} | |
| 5407 | |
| 5408 instruct prefetchrT0( memory mem ) %{ | |
| 5409 predicate(ReadPrefetchInstr==1); | |
| 5410 match(PrefetchRead mem); | |
| 5411 ins_cost(125); | |
| 5412 | |
| 5413 format %{ "PREFETCHT0 $mem\t# prefetch into L1 and L2 caches for read" %} | |
| 3854 | 5414 ins_encode %{ |
| 5415 __ prefetcht0($mem$$Address); | |
| 5416 %} | |
| 0 | 5417 ins_pipe(ialu_mem); |
| 5418 %} | |
| 5419 | |
| 5420 instruct prefetchrT2( memory mem ) %{ | |
| 5421 predicate(ReadPrefetchInstr==2); | |
| 5422 match(PrefetchRead mem); | |
| 5423 ins_cost(125); | |
| 5424 | |
| 5425 format %{ "PREFETCHT2 $mem\t# prefetch into L2 caches for read" %} | |
| 3854 | 5426 ins_encode %{ |
| 5427 __ prefetcht2($mem$$Address); | |
| 5428 %} | |
| 0 | 5429 ins_pipe(ialu_mem); |
| 5430 %} | |
| 5431 | |
| 5432 instruct prefetchwNTA( memory mem ) %{ | |
| 5433 match(PrefetchWrite mem); | |
| 5434 ins_cost(125); | |
| 5435 | |
| 5436 format %{ "PREFETCHNTA $mem\t# Prefetch to non-temporal cache for write" %} | |
| 3854 | 5437 ins_encode %{ |
| 5438 __ prefetchnta($mem$$Address); | |
| 5439 %} | |
| 0 | 5440 ins_pipe(ialu_mem); |
| 5441 %} | |
| 5442 | |
| 3854 | 5443 // Prefetch instructions for allocation. |
| 5444 | |
| 5445 instruct prefetchAlloc( memory mem ) %{ | |
| 5446 predicate(AllocatePrefetchInstr==3); | |
| 5447 match(PrefetchAllocation mem); | |
| 5448 ins_cost(125); | |
| 5449 | |
| 5450 format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %} | |
| 5451 ins_encode %{ | |
| 5452 __ prefetchw($mem$$Address); | |
| 5453 %} | |
| 5454 ins_pipe(ialu_mem); | |
| 5455 %} | |
| 5456 | |
| 5457 instruct prefetchAllocNTA( memory mem ) %{ | |
| 5458 predicate(AllocatePrefetchInstr==0); | |
| 5459 match(PrefetchAllocation mem); | |
| 0 | 5460 ins_cost(125); |
| 5461 | |
| 3854 | 5462 format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %} |
| 5463 ins_encode %{ | |
| 5464 __ prefetchnta($mem$$Address); | |
| 5465 %} | |
| 0 | 5466 ins_pipe(ialu_mem); |
| 5467 %} | |
| 5468 | |
| 3854 | 5469 instruct prefetchAllocT0( memory mem ) %{ |
| 5470 predicate(AllocatePrefetchInstr==1); | |
| 5471 match(PrefetchAllocation mem); | |
| 0 | 5472 ins_cost(125); |
| 5473 | |
| 3854 | 5474 format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %} |
| 5475 ins_encode %{ | |
| 5476 __ prefetcht0($mem$$Address); | |
| 5477 %} | |
| 5478 ins_pipe(ialu_mem); | |
| 5479 %} | |
| 5480 | |
| 5481 instruct prefetchAllocT2( memory mem ) %{ | |
| 5482 predicate(AllocatePrefetchInstr==2); | |
| 5483 match(PrefetchAllocation mem); | |
| 5484 ins_cost(125); | |
| 5485 | |
| 5486 format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %} | |
| 5487 ins_encode %{ | |
| 5488 __ prefetcht2($mem$$Address); | |
| 5489 %} | |
| 0 | 5490 ins_pipe(ialu_mem); |
| 5491 %} | |
| 5492 | |
| 5493 //----------Store Instructions------------------------------------------------- | |
| 5494 | |
| 5495 // Store Byte | |
| 5496 instruct storeB(memory mem, rRegI src) | |
| 5497 %{ | |
| 5498 match(Set mem (StoreB mem src)); | |
| 5499 | |
| 5500 ins_cost(125); // XXX | |
| 5501 format %{ "movb $mem, $src\t# byte" %} | |
| 5502 opcode(0x88); | |
| 5503 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
| 5504 ins_pipe(ialu_mem_reg); | |
| 5505 %} | |
| 5506 | |
| 5507 // Store Char/Short | |
| 5508 instruct storeC(memory mem, rRegI src) | |
| 5509 %{ | |
| 5510 match(Set mem (StoreC mem src)); | |
| 5511 | |
| 5512 ins_cost(125); // XXX | |
| 5513 format %{ "movw $mem, $src\t# char/short" %} | |
| 5514 opcode(0x89); | |
| 5515 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
| 5516 ins_pipe(ialu_mem_reg); | |
| 5517 %} | |
| 5518 | |
| 5519 // Store Integer | |
| 5520 instruct storeI(memory mem, rRegI src) | |
| 5521 %{ | |
| 5522 match(Set mem (StoreI mem src)); | |
| 5523 | |
| 5524 ins_cost(125); // XXX | |
| 5525 format %{ "movl $mem, $src\t# int" %} | |
| 5526 opcode(0x89); | |
| 5527 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
| 5528 ins_pipe(ialu_mem_reg); | |
| 5529 %} | |
| 5530 | |
| 5531 // Store Long | |
| 5532 instruct storeL(memory mem, rRegL src) | |
| 5533 %{ | |
| 5534 match(Set mem (StoreL mem src)); | |
| 5535 | |
| 5536 ins_cost(125); // XXX | |
| 5537 format %{ "movq $mem, $src\t# long" %} | |
| 5538 opcode(0x89); | |
| 5539 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem)); | |
| 5540 ins_pipe(ialu_mem_reg); // XXX | |
| 5541 %} | |
| 5542 | |
| 5543 // Store Pointer | |
| 5544 instruct storeP(memory mem, any_RegP src) | |
| 5545 %{ | |
| 5546 match(Set mem (StoreP mem src)); | |
| 5547 | |
| 5548 ins_cost(125); // XXX | |
| 5549 format %{ "movq $mem, $src\t# ptr" %} | |
| 5550 opcode(0x89); | |
| 5551 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem)); | |
| 5552 ins_pipe(ialu_mem_reg); | |
| 5553 %} | |
| 5554 | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5555 instruct storeImmP0(memory mem, immP0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5556 %{ |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5557 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL)); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5558 match(Set mem (StoreP mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5559 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5560 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5561 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5562 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5563 __ movq($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5564 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5565 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5566 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5567 |
| 0 | 5568 // Store NULL Pointer, mark word, or other simple pointer constant. |
| 5569 instruct storeImmP(memory mem, immP31 src) | |
| 5570 %{ | |
| 5571 match(Set mem (StoreP mem src)); | |
| 5572 | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5573 ins_cost(150); // XXX |
| 0 | 5574 format %{ "movq $mem, $src\t# ptr" %} |
| 5575 opcode(0xC7); /* C7 /0 */ | |
| 5576 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); | |
| 5577 ins_pipe(ialu_mem_imm); | |
| 5578 %} | |
| 5579 | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5580 // Store Compressed Pointer |
| 163 | 5581 instruct storeN(memory mem, rRegN src) |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5582 %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5583 match(Set mem (StoreN mem src)); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5584 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5585 ins_cost(125); // XXX |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
5586 format %{ "movl $mem, $src\t# compressed ptr" %} |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5587 ins_encode %{ |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5588 __ movl($mem$$Address, $src$$Register); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5589 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5590 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5591 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5592 |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5593 instruct storeNKlass(memory mem, rRegN src) |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5594 %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5595 match(Set mem (StoreNKlass mem src)); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5596 |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5597 ins_cost(125); // XXX |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5598 format %{ "movl $mem, $src\t# compressed klass ptr" %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5599 ins_encode %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5600 __ movl($mem$$Address, $src$$Register); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5601 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5602 ins_pipe(ialu_mem_reg); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5603 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5604 |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5605 instruct storeImmN0(memory mem, immN0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5606 %{ |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5607 predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_klass_base() == NULL); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5608 match(Set mem (StoreN mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5609 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5610 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5611 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5612 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5613 __ movl($mem$$Address, r12); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5614 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5615 ins_pipe(ialu_mem_reg); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5616 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5617 |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5618 instruct storeImmN(memory mem, immN src) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5619 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5620 match(Set mem (StoreN mem src)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5621 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5622 ins_cost(150); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5623 format %{ "movl $mem, $src\t# compressed ptr" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5624 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5625 address con = (address)$src$$constant; |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5626 if (con == NULL) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5627 __ movl($mem$$Address, (int32_t)0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5628 } else { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5629 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5630 } |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5631 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5632 ins_pipe(ialu_mem_imm); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5633 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5634 |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5635 instruct storeImmNKlass(memory mem, immNKlass src) |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5636 %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5637 match(Set mem (StoreNKlass mem src)); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5638 |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5639 ins_cost(150); // XXX |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5640 format %{ "movl $mem, $src\t# compressed klass ptr" %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5641 ins_encode %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5642 __ set_narrow_klass($mem$$Address, (Klass*)$src$$constant); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5643 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5644 ins_pipe(ialu_mem_imm); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5645 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5646 |
| 0 | 5647 // Store Integer Immediate |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5648 instruct storeImmI0(memory mem, immI0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5649 %{ |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5650 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL)); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5651 match(Set mem (StoreI mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5652 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5653 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5654 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5655 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5656 __ movl($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5657 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5658 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5659 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5660 |
| 0 | 5661 instruct storeImmI(memory mem, immI src) |
| 5662 %{ | |
| 5663 match(Set mem (StoreI mem src)); | |
| 5664 | |
| 5665 ins_cost(150); | |
| 5666 format %{ "movl $mem, $src\t# int" %} | |
| 5667 opcode(0xC7); /* C7 /0 */ | |
| 5668 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); | |
| 5669 ins_pipe(ialu_mem_imm); | |
| 5670 %} | |
| 5671 | |
| 5672 // Store Long Immediate | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5673 instruct storeImmL0(memory mem, immL0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5674 %{ |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5675 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL)); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5676 match(Set mem (StoreL mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5677 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5678 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5679 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5680 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5681 __ movq($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5682 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5683 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5684 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5685 |
| 0 | 5686 instruct storeImmL(memory mem, immL32 src) |
| 5687 %{ | |
| 5688 match(Set mem (StoreL mem src)); | |
| 5689 | |
| 5690 ins_cost(150); | |
| 5691 format %{ "movq $mem, $src\t# long" %} | |
| 5692 opcode(0xC7); /* C7 /0 */ | |
| 5693 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); | |
| 5694 ins_pipe(ialu_mem_imm); | |
| 5695 %} | |
| 5696 | |
| 5697 // Store Short/Char Immediate | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5698 instruct storeImmC0(memory mem, immI0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5699 %{ |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5700 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL)); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5701 match(Set mem (StoreC mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5702 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5703 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5704 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5705 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5706 __ movw($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5707 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5708 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5709 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5710 |
| 0 | 5711 instruct storeImmI16(memory mem, immI16 src) |
| 5712 %{ | |
| 5713 predicate(UseStoreImmI16); | |
| 5714 match(Set mem (StoreC mem src)); | |
| 5715 | |
| 5716 ins_cost(150); | |
| 5717 format %{ "movw $mem, $src\t# short/char" %} | |
| 5718 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */ | |
| 5719 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src)); | |
| 5720 ins_pipe(ialu_mem_imm); | |
| 5721 %} | |
| 5722 | |
| 5723 // Store Byte Immediate | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5724 instruct storeImmB0(memory mem, immI0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5725 %{ |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5726 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL)); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5727 match(Set mem (StoreB mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5728 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5729 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5730 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5731 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5732 __ movb($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5733 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5734 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5735 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5736 |
| 0 | 5737 instruct storeImmB(memory mem, immI8 src) |
| 5738 %{ | |
| 5739 match(Set mem (StoreB mem src)); | |
| 5740 | |
| 5741 ins_cost(150); // XXX | |
| 5742 format %{ "movb $mem, $src\t# byte" %} | |
| 5743 opcode(0xC6); /* C6 /0 */ | |
| 5744 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src)); | |
| 5745 ins_pipe(ialu_mem_imm); | |
| 5746 %} | |
| 5747 | |
| 5748 // Store CMS card-mark Immediate | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5749 instruct storeImmCM0_reg(memory mem, immI0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5750 %{ |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5751 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL)); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5752 match(Set mem (StoreCM mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5753 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5754 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5755 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5756 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5757 __ movb($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5758 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5759 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5760 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5761 |
| 0 | 5762 instruct storeImmCM0(memory mem, immI0 src) |
| 5763 %{ | |
| 5764 match(Set mem (StoreCM mem src)); | |
| 5765 | |
| 5766 ins_cost(150); // XXX | |
| 5767 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %} | |
| 5768 opcode(0xC6); /* C6 /0 */ | |
| 5769 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src)); | |
| 5770 ins_pipe(ialu_mem_imm); | |
| 5771 %} | |
| 5772 | |
| 5773 // Store Float | |
| 5774 instruct storeF(memory mem, regF src) | |
| 5775 %{ | |
| 5776 match(Set mem (StoreF mem src)); | |
| 5777 | |
| 5778 ins_cost(95); // XXX | |
| 5779 format %{ "movss $mem, $src\t# float" %} | |
| 4759 | 5780 ins_encode %{ |
| 5781 __ movflt($mem$$Address, $src$$XMMRegister); | |
| 5782 %} | |
| 0 | 5783 ins_pipe(pipe_slow); // XXX |
| 5784 %} | |
| 5785 | |
| 5786 // Store immediate Float value (it is faster than store from XMM register) | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5787 instruct storeF0(memory mem, immF0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5788 %{ |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5789 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL)); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5790 match(Set mem (StoreF mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5791 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5792 ins_cost(25); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5793 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5794 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5795 __ movl($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5796 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5797 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5798 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5799 |
| 0 | 5800 instruct storeF_imm(memory mem, immF src) |
| 5801 %{ | |
| 5802 match(Set mem (StoreF mem src)); | |
| 5803 | |
| 5804 ins_cost(50); | |
| 5805 format %{ "movl $mem, $src\t# float" %} | |
| 5806 opcode(0xC7); /* C7 /0 */ | |
| 5807 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src)); | |
| 5808 ins_pipe(ialu_mem_imm); | |
| 5809 %} | |
| 5810 | |
| 5811 // Store Double | |
| 5812 instruct storeD(memory mem, regD src) | |
| 5813 %{ | |
| 5814 match(Set mem (StoreD mem src)); | |
| 5815 | |
| 5816 ins_cost(95); // XXX | |
| 5817 format %{ "movsd $mem, $src\t# double" %} | |
| 4759 | 5818 ins_encode %{ |
| 5819 __ movdbl($mem$$Address, $src$$XMMRegister); | |
| 5820 %} | |
| 0 | 5821 ins_pipe(pipe_slow); // XXX |
| 5822 %} | |
| 5823 | |
| 5824 // Store immediate double 0.0 (it is faster than store from XMM register) | |
| 5825 instruct storeD0_imm(memory mem, immD0 src) | |
| 5826 %{ | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5827 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL)); |
| 0 | 5828 match(Set mem (StoreD mem src)); |
| 5829 | |
| 5830 ins_cost(50); | |
| 5831 format %{ "movq $mem, $src\t# double 0." %} | |
| 5832 opcode(0xC7); /* C7 /0 */ | |
| 5833 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src)); | |
| 5834 ins_pipe(ialu_mem_imm); | |
| 5835 %} | |
| 5836 | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5837 instruct storeD0(memory mem, immD0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5838 %{ |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5839 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL)); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5840 match(Set mem (StoreD mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5841 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5842 ins_cost(25); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5843 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5844 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5845 __ movq($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5846 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5847 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5848 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5849 |
| 0 | 5850 instruct storeSSI(stackSlotI dst, rRegI src) |
| 5851 %{ | |
| 5852 match(Set dst src); | |
| 5853 | |
| 5854 ins_cost(100); | |
| 5855 format %{ "movl $dst, $src\t# int stk" %} | |
| 5856 opcode(0x89); | |
| 5857 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 5858 ins_pipe( ialu_mem_reg ); | |
| 5859 %} | |
| 5860 | |
| 5861 instruct storeSSL(stackSlotL dst, rRegL src) | |
| 5862 %{ | |
| 5863 match(Set dst src); | |
| 5864 | |
| 5865 ins_cost(100); | |
| 5866 format %{ "movq $dst, $src\t# long stk" %} | |
| 5867 opcode(0x89); | |
| 5868 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 5869 ins_pipe(ialu_mem_reg); | |
| 5870 %} | |
| 5871 | |
| 5872 instruct storeSSP(stackSlotP dst, rRegP src) | |
| 5873 %{ | |
| 5874 match(Set dst src); | |
| 5875 | |
| 5876 ins_cost(100); | |
| 5877 format %{ "movq $dst, $src\t# ptr stk" %} | |
| 5878 opcode(0x89); | |
| 5879 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 5880 ins_pipe(ialu_mem_reg); | |
| 5881 %} | |
| 5882 | |
| 5883 instruct storeSSF(stackSlotF dst, regF src) | |
| 5884 %{ | |
| 5885 match(Set dst src); | |
| 5886 | |
| 5887 ins_cost(95); // XXX | |
| 5888 format %{ "movss $dst, $src\t# float stk" %} | |
| 4759 | 5889 ins_encode %{ |
| 5890 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister); | |
| 5891 %} | |
| 0 | 5892 ins_pipe(pipe_slow); // XXX |
| 5893 %} | |
| 5894 | |
| 5895 instruct storeSSD(stackSlotD dst, regD src) | |
| 5896 %{ | |
| 5897 match(Set dst src); | |
| 5898 | |
| 5899 ins_cost(95); // XXX | |
| 5900 format %{ "movsd $dst, $src\t# double stk" %} | |
| 4759 | 5901 ins_encode %{ |
| 5902 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister); | |
| 5903 %} | |
| 0 | 5904 ins_pipe(pipe_slow); // XXX |
| 5905 %} | |
| 5906 | |
| 5907 //----------BSWAP Instructions------------------------------------------------- | |
| 5908 instruct bytes_reverse_int(rRegI dst) %{ | |
| 5909 match(Set dst (ReverseBytesI dst)); | |
| 5910 | |
| 5911 format %{ "bswapl $dst" %} | |
| 5912 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */ | |
| 5913 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) ); | |
| 5914 ins_pipe( ialu_reg ); | |
| 5915 %} | |
| 5916 | |
| 5917 instruct bytes_reverse_long(rRegL dst) %{ | |
| 5918 match(Set dst (ReverseBytesL dst)); | |
| 5919 | |
| 5920 format %{ "bswapq $dst" %} | |
| 5921 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */ | |
| 5922 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) ); | |
| 5923 ins_pipe( ialu_reg); | |
| 5924 %} | |
| 5925 | |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
5926 instruct bytes_reverse_unsigned_short(rRegI dst, rFlagsReg cr) %{ |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5927 match(Set dst (ReverseBytesUS dst)); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
5928 effect(KILL cr); |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5929 |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
5930 format %{ "bswapl $dst\n\t" |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5931 "shrl $dst,16\n\t" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5932 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5933 __ bswapl($dst$$Register); |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
5934 __ shrl($dst$$Register, 16); |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5935 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5936 ins_pipe( ialu_reg ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5937 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5938 |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
5939 instruct bytes_reverse_short(rRegI dst, rFlagsReg cr) %{ |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5940 match(Set dst (ReverseBytesS dst)); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
5941 effect(KILL cr); |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5942 |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
5943 format %{ "bswapl $dst\n\t" |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5944 "sar $dst,16\n\t" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5945 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5946 __ bswapl($dst$$Register); |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
5947 __ sarl($dst$$Register, 16); |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5948 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5949 ins_pipe( ialu_reg ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5950 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5951 |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5952 //---------- Zeros Count Instructions ------------------------------------------ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5953 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5954 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5955 predicate(UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5956 match(Set dst (CountLeadingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5957 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5958 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5959 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5960 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5961 __ lzcntl($dst$$Register, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5962 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5963 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5964 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5965 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5966 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5967 predicate(!UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5968 match(Set dst (CountLeadingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5969 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5970 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5971 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5972 "jnz skip\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5973 "movl $dst, -1\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5974 "skip:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5975 "negl $dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5976 "addl $dst, 31" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5977 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5978 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5979 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5980 Label skip; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5981 __ bsrl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5982 __ jccb(Assembler::notZero, skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5983 __ movl(Rdst, -1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5984 __ bind(skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5985 __ negl(Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5986 __ addl(Rdst, BitsPerInt - 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5987 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5988 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5989 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5990 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5991 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5992 predicate(UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5993 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5994 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5995 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5996 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5997 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5998 __ lzcntq($dst$$Register, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5999 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6000 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6001 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6002 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6003 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6004 predicate(!UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6005 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6006 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6007 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6008 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6009 "jnz skip\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6010 "movl $dst, -1\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6011 "skip:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6012 "negl $dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6013 "addl $dst, 63" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6014 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6015 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6016 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6017 Label skip; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6018 __ bsrq(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6019 __ jccb(Assembler::notZero, skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6020 __ movl(Rdst, -1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6021 __ bind(skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6022 __ negl(Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6023 __ addl(Rdst, BitsPerLong - 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6024 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6025 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6026 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6027 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6028 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6029 match(Set dst (CountTrailingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6030 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6031 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6032 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6033 "jnz done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6034 "movl $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6035 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6036 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6037 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6038 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6039 __ bsfl(Rdst, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6040 __ jccb(Assembler::notZero, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6041 __ movl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6042 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6043 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6044 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6045 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6046 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6047 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6048 match(Set dst (CountTrailingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6049 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6050 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6051 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6052 "jnz done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6053 "movl $dst, 64\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6054 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6055 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6056 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6057 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6058 __ bsfq(Rdst, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6059 __ jccb(Assembler::notZero, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6060 __ movl(Rdst, BitsPerLong); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6061 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6062 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6063 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6064 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6065 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6066 |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6067 //---------- Population Count Instructions ------------------------------------- |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6068 |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6069 instruct popCountI(rRegI dst, rRegI src, rFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6070 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6071 match(Set dst (PopCountI src)); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6072 effect(KILL cr); |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6073 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6074 format %{ "popcnt $dst, $src" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6075 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6076 __ popcntl($dst$$Register, $src$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6077 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6078 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6079 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6080 |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6081 instruct popCountI_mem(rRegI dst, memory mem, rFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6082 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6083 match(Set dst (PopCountI (LoadI mem))); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6084 effect(KILL cr); |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6085 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6086 format %{ "popcnt $dst, $mem" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6087 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6088 __ popcntl($dst$$Register, $mem$$Address); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6089 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6090 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6091 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6092 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6093 // Note: Long.bitCount(long) returns an int. |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6094 instruct popCountL(rRegI dst, rRegL src, rFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6095 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6096 match(Set dst (PopCountL src)); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6097 effect(KILL cr); |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6098 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6099 format %{ "popcnt $dst, $src" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6100 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6101 __ popcntq($dst$$Register, $src$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6102 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6103 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6104 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6105 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6106 // Note: Long.bitCount(long) returns an int. |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6107 instruct popCountL_mem(rRegI dst, memory mem, rFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6108 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6109 match(Set dst (PopCountL (LoadL mem))); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6110 effect(KILL cr); |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6111 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6112 format %{ "popcnt $dst, $mem" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6113 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6114 __ popcntq($dst$$Register, $mem$$Address); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6115 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6116 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6117 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6118 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6119 |
| 0 | 6120 //----------MemBar Instructions----------------------------------------------- |
| 6121 // Memory barrier flavors | |
| 6122 | |
| 6123 instruct membar_acquire() | |
| 6124 %{ | |
| 6125 match(MemBarAcquire); | |
| 6126 ins_cost(0); | |
| 6127 | |
| 6128 size(0); | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6129 format %{ "MEMBAR-acquire ! (empty encoding)" %} |
| 0 | 6130 ins_encode(); |
| 6131 ins_pipe(empty); | |
| 6132 %} | |
| 6133 | |
| 6134 instruct membar_acquire_lock() | |
| 6135 %{ | |
|
3849
f1c12354c3f7
7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents:
3842
diff
changeset
|
6136 match(MemBarAcquireLock); |
| 0 | 6137 ins_cost(0); |
| 6138 | |
| 6139 size(0); | |
| 6140 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %} | |
| 6141 ins_encode(); | |
| 6142 ins_pipe(empty); | |
| 6143 %} | |
| 6144 | |
| 6145 instruct membar_release() | |
| 6146 %{ | |
| 6147 match(MemBarRelease); | |
| 6148 ins_cost(0); | |
| 6149 | |
| 6150 size(0); | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6151 format %{ "MEMBAR-release ! (empty encoding)" %} |
| 0 | 6152 ins_encode(); |
| 6153 ins_pipe(empty); | |
| 6154 %} | |
| 6155 | |
| 6156 instruct membar_release_lock() | |
| 6157 %{ | |
|
3849
f1c12354c3f7
7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents:
3842
diff
changeset
|
6158 match(MemBarReleaseLock); |
| 0 | 6159 ins_cost(0); |
| 6160 | |
| 6161 size(0); | |
| 6162 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %} | |
| 6163 ins_encode(); | |
| 6164 ins_pipe(empty); | |
| 6165 %} | |
| 6166 | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6167 instruct membar_volatile(rFlagsReg cr) %{ |
| 0 | 6168 match(MemBarVolatile); |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6169 effect(KILL cr); |
| 0 | 6170 ins_cost(400); |
| 6171 | |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
6172 format %{ |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6173 $$template |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6174 if (os::is_MP()) { |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6175 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile" |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6176 } else { |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6177 $$emit$$"MEMBAR-volatile ! (empty encoding)" |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6178 } |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6179 %} |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6180 ins_encode %{ |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6181 __ membar(Assembler::StoreLoad); |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6182 %} |
| 0 | 6183 ins_pipe(pipe_slow); |
| 6184 %} | |
| 6185 | |
| 6186 instruct unnecessary_membar_volatile() | |
| 6187 %{ | |
| 6188 match(MemBarVolatile); | |
| 6189 predicate(Matcher::post_store_load_barrier(n)); | |
| 6190 ins_cost(0); | |
| 6191 | |
| 6192 size(0); | |
| 6193 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %} | |
| 6194 ins_encode(); | |
| 6195 ins_pipe(empty); | |
| 6196 %} | |
| 6197 | |
|
4763
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6198 instruct membar_storestore() %{ |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6199 match(MemBarStoreStore); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6200 ins_cost(0); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6201 |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6202 size(0); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6203 format %{ "MEMBAR-storestore (empty encoding)" %} |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6204 ins_encode( ); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6205 ins_pipe(empty); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6206 %} |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6207 |
| 0 | 6208 //----------Move Instructions-------------------------------------------------- |
| 6209 | |
| 6210 instruct castX2P(rRegP dst, rRegL src) | |
| 6211 %{ | |
| 6212 match(Set dst (CastX2P src)); | |
| 6213 | |
| 6214 format %{ "movq $dst, $src\t# long->ptr" %} | |
| 4759 | 6215 ins_encode %{ |
| 6216 if ($dst$$reg != $src$$reg) { | |
| 6217 __ movptr($dst$$Register, $src$$Register); | |
| 6218 } | |
| 6219 %} | |
| 0 | 6220 ins_pipe(ialu_reg_reg); // XXX |
| 6221 %} | |
| 6222 | |
| 6223 instruct castP2X(rRegL dst, rRegP src) | |
| 6224 %{ | |
| 6225 match(Set dst (CastP2X src)); | |
| 6226 | |
| 6227 format %{ "movq $dst, $src\t# ptr -> long" %} | |
| 4759 | 6228 ins_encode %{ |
| 6229 if ($dst$$reg != $src$$reg) { | |
| 6230 __ movptr($dst$$Register, $src$$Register); | |
| 6231 } | |
| 6232 %} | |
| 0 | 6233 ins_pipe(ialu_reg_reg); // XXX |
| 6234 %} | |
| 6235 | |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6236 // Convert oop into int for vectors alignment masking |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6237 instruct convP2I(rRegI dst, rRegP src) |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6238 %{ |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6239 match(Set dst (ConvL2I (CastP2X src))); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6240 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6241 format %{ "movl $dst, $src\t# ptr -> int" %} |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6242 ins_encode %{ |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6243 __ movl($dst$$Register, $src$$Register); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6244 %} |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6245 ins_pipe(ialu_reg_reg); // XXX |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6246 %} |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6247 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6248 // Convert compressed oop into int for vectors alignment masking |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6249 // in case of 32bit oops (heap < 4Gb). |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6250 instruct convN2I(rRegI dst, rRegN src) |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6251 %{ |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6252 predicate(Universe::narrow_oop_shift() == 0); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6253 match(Set dst (ConvL2I (CastP2X (DecodeN src)))); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6254 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6255 format %{ "movl $dst, $src\t# compressed ptr -> int" %} |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6256 ins_encode %{ |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6257 __ movl($dst$$Register, $src$$Register); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6258 %} |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6259 ins_pipe(ialu_reg_reg); // XXX |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6260 %} |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6261 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6262 // Convert oop pointer into compressed form |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6263 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{ |
|
221
1e026f8da827
6710487: More than half of JDI Regression tests hang with COOPs in -Xcomp mode
kvn
parents:
182
diff
changeset
|
6264 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6265 match(Set dst (EncodeP src)); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6266 effect(KILL cr); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6267 format %{ "encode_heap_oop $dst,$src" %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6268 ins_encode %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6269 Register s = $src$$Register; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6270 Register d = $dst$$Register; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6271 if (s != d) { |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6272 __ movq(d, s); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6273 } |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6274 __ encode_heap_oop(d); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6275 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6276 ins_pipe(ialu_reg_long); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6277 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6278 |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6279 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{ |
|
221
1e026f8da827
6710487: More than half of JDI Regression tests hang with COOPs in -Xcomp mode
kvn
parents:
182
diff
changeset
|
6280 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6281 match(Set dst (EncodeP src)); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6282 effect(KILL cr); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6283 format %{ "encode_heap_oop_not_null $dst,$src" %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6284 ins_encode %{ |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6285 __ encode_heap_oop_not_null($dst$$Register, $src$$Register); |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6286 %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6287 ins_pipe(ialu_reg_long); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6288 %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6289 |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6290 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{ |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
6291 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull && |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
6292 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6293 match(Set dst (DecodeN src)); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6294 effect(KILL cr); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6295 format %{ "decode_heap_oop $dst,$src" %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6296 ins_encode %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6297 Register s = $src$$Register; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6298 Register d = $dst$$Register; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6299 if (s != d) { |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6300 __ movq(d, s); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6301 } |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6302 __ decode_heap_oop(d); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6303 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6304 ins_pipe(ialu_reg_long); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6305 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6306 |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1567
diff
changeset
|
6307 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{ |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
6308 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull || |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
6309 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant); |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6310 match(Set dst (DecodeN src)); |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1567
diff
changeset
|
6311 effect(KILL cr); |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6312 format %{ "decode_heap_oop_not_null $dst,$src" %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6313 ins_encode %{ |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6314 Register s = $src$$Register; |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6315 Register d = $dst$$Register; |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6316 if (s != d) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6317 __ decode_heap_oop_not_null(d, s); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6318 } else { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6319 __ decode_heap_oop_not_null(d); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6320 } |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6321 %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6322 ins_pipe(ialu_reg_long); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6323 %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6324 |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6325 instruct encodeKlass_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6326 match(Set dst (EncodePKlass src)); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6327 effect(KILL cr); |
|
12056
740e263c80c6
8003424: Enable Class Data Sharing for CompressedOops
hseigel
parents:
10171
diff
changeset
|
6328 format %{ "encode_klass_not_null $dst,$src" %} |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6329 ins_encode %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6330 __ encode_klass_not_null($dst$$Register, $src$$Register); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6331 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6332 ins_pipe(ialu_reg_long); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6333 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6334 |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6335 instruct decodeKlass_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6336 match(Set dst (DecodeNKlass src)); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6337 effect(KILL cr); |
|
12056
740e263c80c6
8003424: Enable Class Data Sharing for CompressedOops
hseigel
parents:
10171
diff
changeset
|
6338 format %{ "decode_klass_not_null $dst,$src" %} |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6339 ins_encode %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6340 Register s = $src$$Register; |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6341 Register d = $dst$$Register; |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6342 if (s != d) { |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6343 __ decode_klass_not_null(d, s); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6344 } else { |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6345 __ decode_klass_not_null(d); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6346 } |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6347 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6348 ins_pipe(ialu_reg_long); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6349 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6350 |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6351 |
| 0 | 6352 //----------Conditional Move--------------------------------------------------- |
| 6353 // Jump | |
| 6354 // dummy instruction for generating temp registers | |
| 6355 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{ | |
| 6356 match(Jump (LShiftL switch_val shift)); | |
| 6357 ins_cost(350); | |
| 6358 predicate(false); | |
| 6359 effect(TEMP dest); | |
| 6360 | |
| 2008 | 6361 format %{ "leaq $dest, [$constantaddress]\n\t" |
| 0 | 6362 "jmp [$dest + $switch_val << $shift]\n\t" %} |
| 2008 | 6363 ins_encode %{ |
| 6364 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10 | |
| 6365 // to do that and the compiler is using that register as one it can allocate. | |
| 6366 // So we build it all by hand. | |
| 6367 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant); | |
| 6368 // ArrayAddress dispatch(table, index); | |
| 6369 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant); | |
| 6370 __ lea($dest$$Register, $constantaddress); | |
| 6371 __ jmp(dispatch); | |
| 6372 %} | |
| 0 | 6373 ins_pipe(pipe_jmp); |
| 6374 %} | |
| 6375 | |
| 6376 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{ | |
| 6377 match(Jump (AddL (LShiftL switch_val shift) offset)); | |
| 6378 ins_cost(350); | |
| 6379 effect(TEMP dest); | |
| 6380 | |
| 2008 | 6381 format %{ "leaq $dest, [$constantaddress]\n\t" |
| 0 | 6382 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %} |
| 2008 | 6383 ins_encode %{ |
| 6384 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10 | |
| 6385 // to do that and the compiler is using that register as one it can allocate. | |
| 6386 // So we build it all by hand. | |
| 6387 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant); | |
| 6388 // ArrayAddress dispatch(table, index); | |
| 6389 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant); | |
| 6390 __ lea($dest$$Register, $constantaddress); | |
| 6391 __ jmp(dispatch); | |
| 6392 %} | |
| 0 | 6393 ins_pipe(pipe_jmp); |
| 6394 %} | |
| 6395 | |
| 6396 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{ | |
| 6397 match(Jump switch_val); | |
| 6398 ins_cost(350); | |
| 6399 effect(TEMP dest); | |
| 6400 | |
| 2008 | 6401 format %{ "leaq $dest, [$constantaddress]\n\t" |
| 0 | 6402 "jmp [$dest + $switch_val]\n\t" %} |
| 2008 | 6403 ins_encode %{ |
| 6404 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10 | |
| 6405 // to do that and the compiler is using that register as one it can allocate. | |
| 6406 // So we build it all by hand. | |
| 6407 // Address index(noreg, switch_reg, Address::times_1); | |
| 6408 // ArrayAddress dispatch(table, index); | |
| 6409 Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1); | |
| 6410 __ lea($dest$$Register, $constantaddress); | |
| 6411 __ jmp(dispatch); | |
| 6412 %} | |
| 0 | 6413 ins_pipe(pipe_jmp); |
| 6414 %} | |
| 6415 | |
| 6416 // Conditional move | |
| 6417 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop) | |
| 6418 %{ | |
| 6419 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 6420 | |
| 6421 ins_cost(200); // XXX | |
| 6422 format %{ "cmovl$cop $dst, $src\t# signed, int" %} | |
| 6423 opcode(0x0F, 0x40); | |
| 6424 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 6425 ins_pipe(pipe_cmov_reg); | |
| 6426 %} | |
| 6427 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6428 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{ |
| 0 | 6429 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); |
| 6430 | |
| 6431 ins_cost(200); // XXX | |
| 6432 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %} | |
| 6433 opcode(0x0F, 0x40); | |
| 6434 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 6435 ins_pipe(pipe_cmov_reg); | |
| 6436 %} | |
| 6437 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6438 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6439 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6440 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6441 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6442 cmovI_regU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6443 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6444 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6445 |
| 0 | 6446 // Conditional move |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6447 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{ |
| 0 | 6448 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); |
| 6449 | |
| 6450 ins_cost(250); // XXX | |
| 6451 format %{ "cmovl$cop $dst, $src\t# signed, int" %} | |
| 6452 opcode(0x0F, 0x40); | |
| 6453 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
| 6454 ins_pipe(pipe_cmov_mem); | |
| 6455 %} | |
| 6456 | |
| 6457 // Conditional move | |
| 6458 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src) | |
| 6459 %{ | |
| 6460 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); | |
| 6461 | |
| 6462 ins_cost(250); // XXX | |
| 6463 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %} | |
| 6464 opcode(0x0F, 0x40); | |
| 6465 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
| 6466 ins_pipe(pipe_cmov_mem); | |
| 6467 %} | |
| 6468 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6469 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6470 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6471 ins_cost(250); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6472 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6473 cmovI_memU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6474 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6475 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6476 |
| 0 | 6477 // Conditional move |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6478 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop) |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6479 %{ |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6480 match(Set dst (CMoveN (Binary cop cr) (Binary dst src))); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6481 |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6482 ins_cost(200); // XXX |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6483 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6484 opcode(0x0F, 0x40); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6485 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6486 ins_pipe(pipe_cmov_reg); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6487 %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6488 |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6489 // Conditional move |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6490 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src) |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6491 %{ |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6492 match(Set dst (CMoveN (Binary cop cr) (Binary dst src))); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6493 |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6494 ins_cost(200); // XXX |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6495 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6496 opcode(0x0F, 0x40); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6497 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6498 ins_pipe(pipe_cmov_reg); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6499 %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6500 |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6501 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6502 match(Set dst (CMoveN (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6503 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6504 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6505 cmovN_regU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6506 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6507 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6508 |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6509 // Conditional move |
| 0 | 6510 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop) |
| 6511 %{ | |
| 6512 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 6513 | |
| 6514 ins_cost(200); // XXX | |
| 6515 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %} | |
| 6516 opcode(0x0F, 0x40); | |
| 6517 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 6518 ins_pipe(pipe_cmov_reg); // XXX | |
| 6519 %} | |
| 6520 | |
| 6521 // Conditional move | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6522 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src) |
| 0 | 6523 %{ |
| 6524 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 6525 | |
| 6526 ins_cost(200); // XXX | |
| 6527 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %} | |
| 6528 opcode(0x0F, 0x40); | |
| 6529 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 6530 ins_pipe(pipe_cmov_reg); // XXX | |
| 6531 %} | |
| 6532 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6533 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6534 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6535 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6536 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6537 cmovP_regU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6538 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6539 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6540 |
| 0 | 6541 // DISABLED: Requires the ADLC to emit a bottom_type call that |
| 6542 // correctly meets the two pointer arguments; one is an incoming | |
| 6543 // register but the other is a memory operand. ALSO appears to | |
| 6544 // be buggy with implicit null checks. | |
| 6545 // | |
| 6546 //// Conditional move | |
| 6547 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src) | |
| 6548 //%{ | |
| 6549 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 6550 // ins_cost(250); | |
| 6551 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 6552 // opcode(0x0F,0x40); | |
| 6553 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) ); | |
| 6554 // ins_pipe( pipe_cmov_mem ); | |
| 6555 //%} | |
| 6556 // | |
| 6557 //// Conditional move | |
| 6558 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src) | |
| 6559 //%{ | |
| 6560 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 6561 // ins_cost(250); | |
| 6562 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 6563 // opcode(0x0F,0x40); | |
| 6564 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) ); | |
| 6565 // ins_pipe( pipe_cmov_mem ); | |
| 6566 //%} | |
| 6567 | |
| 6568 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src) | |
| 6569 %{ | |
| 6570 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 6571 | |
| 6572 ins_cost(200); // XXX | |
| 6573 format %{ "cmovq$cop $dst, $src\t# signed, long" %} | |
| 6574 opcode(0x0F, 0x40); | |
| 6575 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 6576 ins_pipe(pipe_cmov_reg); // XXX | |
| 6577 %} | |
| 6578 | |
| 6579 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src) | |
| 6580 %{ | |
| 6581 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src)))); | |
| 6582 | |
| 6583 ins_cost(200); // XXX | |
| 6584 format %{ "cmovq$cop $dst, $src\t# signed, long" %} | |
| 6585 opcode(0x0F, 0x40); | |
| 6586 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
| 6587 ins_pipe(pipe_cmov_mem); // XXX | |
| 6588 %} | |
| 6589 | |
| 6590 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src) | |
| 6591 %{ | |
| 6592 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 6593 | |
| 6594 ins_cost(200); // XXX | |
| 6595 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %} | |
| 6596 opcode(0x0F, 0x40); | |
| 6597 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 6598 ins_pipe(pipe_cmov_reg); // XXX | |
| 6599 %} | |
| 6600 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6601 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6602 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6603 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6604 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6605 cmovL_regU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6606 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6607 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6608 |
| 0 | 6609 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src) |
| 6610 %{ | |
| 6611 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src)))); | |
| 6612 | |
| 6613 ins_cost(200); // XXX | |
| 6614 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %} | |
| 6615 opcode(0x0F, 0x40); | |
| 6616 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
| 6617 ins_pipe(pipe_cmov_mem); // XXX | |
| 6618 %} | |
| 6619 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6620 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6621 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src)))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6622 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6623 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6624 cmovL_memU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6625 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6626 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6627 |
| 0 | 6628 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src) |
| 6629 %{ | |
| 6630 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 6631 | |
| 6632 ins_cost(200); // XXX | |
| 6633 format %{ "jn$cop skip\t# signed cmove float\n\t" | |
| 6634 "movss $dst, $src\n" | |
| 6635 "skip:" %} | |
| 4759 | 6636 ins_encode %{ |
| 6637 Label Lskip; | |
| 6638 // Invert sense of branch from sense of CMOV | |
| 6639 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
| 6640 __ movflt($dst$$XMMRegister, $src$$XMMRegister); | |
| 6641 __ bind(Lskip); | |
| 6642 %} | |
| 0 | 6643 ins_pipe(pipe_slow); |
| 6644 %} | |
| 6645 | |
| 6646 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src) | |
| 6647 // %{ | |
| 6648 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src)))); | |
| 6649 | |
| 6650 // ins_cost(200); // XXX | |
| 6651 // format %{ "jn$cop skip\t# signed cmove float\n\t" | |
| 6652 // "movss $dst, $src\n" | |
| 6653 // "skip:" %} | |
| 6654 // ins_encode(enc_cmovf_mem_branch(cop, dst, src)); | |
| 6655 // ins_pipe(pipe_slow); | |
| 6656 // %} | |
| 6657 | |
| 6658 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src) | |
| 6659 %{ | |
| 6660 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 6661 | |
| 6662 ins_cost(200); // XXX | |
| 6663 format %{ "jn$cop skip\t# unsigned cmove float\n\t" | |
| 6664 "movss $dst, $src\n" | |
| 6665 "skip:" %} | |
| 4759 | 6666 ins_encode %{ |
| 6667 Label Lskip; | |
| 6668 // Invert sense of branch from sense of CMOV | |
| 6669 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
| 6670 __ movflt($dst$$XMMRegister, $src$$XMMRegister); | |
| 6671 __ bind(Lskip); | |
| 6672 %} | |
| 0 | 6673 ins_pipe(pipe_slow); |
| 6674 %} | |
| 6675 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6676 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6677 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6678 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6679 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6680 cmovF_regU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6681 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6682 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6683 |
| 0 | 6684 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src) |
| 6685 %{ | |
| 6686 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 6687 | |
| 6688 ins_cost(200); // XXX | |
| 6689 format %{ "jn$cop skip\t# signed cmove double\n\t" | |
| 6690 "movsd $dst, $src\n" | |
| 6691 "skip:" %} | |
| 4759 | 6692 ins_encode %{ |
| 6693 Label Lskip; | |
| 6694 // Invert sense of branch from sense of CMOV | |
| 6695 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
| 6696 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); | |
| 6697 __ bind(Lskip); | |
| 6698 %} | |
| 0 | 6699 ins_pipe(pipe_slow); |
| 6700 %} | |
| 6701 | |
| 6702 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src) | |
| 6703 %{ | |
| 6704 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 6705 | |
| 6706 ins_cost(200); // XXX | |
| 6707 format %{ "jn$cop skip\t# unsigned cmove double\n\t" | |
| 6708 "movsd $dst, $src\n" | |
| 6709 "skip:" %} | |
| 4759 | 6710 ins_encode %{ |
| 6711 Label Lskip; | |
| 6712 // Invert sense of branch from sense of CMOV | |
| 6713 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
| 6714 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); | |
| 6715 __ bind(Lskip); | |
| 6716 %} | |
| 0 | 6717 ins_pipe(pipe_slow); |
| 6718 %} | |
| 6719 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6720 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6721 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6722 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6723 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6724 cmovD_regU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6725 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6726 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6727 |
| 0 | 6728 //----------Arithmetic Instructions-------------------------------------------- |
| 6729 //----------Addition Instructions---------------------------------------------- | |
| 6730 | |
| 12323 | 6731 instruct addExactI_rReg(rax_RegI dst, rRegI src, rFlagsReg cr) |
| 6732 %{ | |
| 6733 match(AddExactI dst src); | |
| 6734 effect(DEF cr); | |
| 6735 | |
| 6736 format %{ "addl $dst, $src\t# addExact int" %} | |
| 6737 ins_encode %{ | |
| 6738 __ addl($dst$$Register, $src$$Register); | |
| 6739 %} | |
| 6740 ins_pipe(ialu_reg_reg); | |
| 6741 %} | |
| 6742 | |
| 6743 instruct addExactI_rReg_imm(rax_RegI dst, immI src, rFlagsReg cr) | |
| 6744 %{ | |
| 6745 match(AddExactI dst src); | |
| 6746 effect(DEF cr); | |
| 6747 | |
| 6748 format %{ "addl $dst, $src\t# addExact int" %} | |
| 6749 ins_encode %{ | |
| 6750 __ addl($dst$$Register, $src$$constant); | |
| 6751 %} | |
| 6752 ins_pipe(ialu_reg_reg); | |
| 6753 %} | |
| 6754 | |
|
12972
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6755 instruct addExactI_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr) |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6756 %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6757 match(AddExactI dst (LoadI src)); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6758 effect(DEF cr); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6759 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6760 ins_cost(125); // XXX |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6761 format %{ "addl $dst, $src\t# addExact int" %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6762 ins_encode %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6763 __ addl($dst$$Register, $src$$Address); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6764 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6765 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6766 ins_pipe(ialu_reg_mem); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6767 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6768 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6769 instruct addExactL_rReg(rax_RegL dst, rRegL src, rFlagsReg cr) |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6770 %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6771 match(AddExactL dst src); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6772 effect(DEF cr); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6773 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6774 format %{ "addq $dst, $src\t# addExact long" %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6775 ins_encode %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6776 __ addq($dst$$Register, $src$$Register); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6777 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6778 ins_pipe(ialu_reg_reg); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6779 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6780 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6781 instruct addExactL_rReg_imm(rax_RegL dst, immL32 src, rFlagsReg cr) |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6782 %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6783 match(AddExactL dst src); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6784 effect(DEF cr); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6785 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6786 format %{ "addq $dst, $src\t# addExact long" %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6787 ins_encode %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6788 __ addq($dst$$Register, $src$$constant); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6789 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6790 ins_pipe(ialu_reg_reg); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6791 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6792 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6793 instruct addExactL_rReg_mem(rax_RegL dst, memory src, rFlagsReg cr) |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6794 %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6795 match(AddExactL dst (LoadL src)); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6796 effect(DEF cr); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6797 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6798 ins_cost(125); // XXX |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6799 format %{ "addq $dst, $src\t# addExact long" %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6800 ins_encode %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6801 __ addq($dst$$Register, $src$$Address); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6802 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6803 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6804 ins_pipe(ialu_reg_mem); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6805 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
6806 |
| 0 | 6807 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr) |
| 6808 %{ | |
| 6809 match(Set dst (AddI dst src)); | |
| 6810 effect(KILL cr); | |
| 6811 | |
| 6812 format %{ "addl $dst, $src\t# int" %} | |
| 6813 opcode(0x03); | |
| 6814 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 6815 ins_pipe(ialu_reg_reg); | |
| 6816 %} | |
| 6817 | |
| 6818 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 6819 %{ | |
| 6820 match(Set dst (AddI dst src)); | |
| 6821 effect(KILL cr); | |
| 6822 | |
| 6823 format %{ "addl $dst, $src\t# int" %} | |
| 6824 opcode(0x81, 0x00); /* /0 id */ | |
| 6825 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 6826 ins_pipe( ialu_reg ); | |
| 6827 %} | |
| 6828 | |
| 6829 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 6830 %{ | |
| 6831 match(Set dst (AddI dst (LoadI src))); | |
| 6832 effect(KILL cr); | |
| 6833 | |
| 6834 ins_cost(125); // XXX | |
| 6835 format %{ "addl $dst, $src\t# int" %} | |
| 6836 opcode(0x03); | |
| 6837 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 6838 ins_pipe(ialu_reg_mem); | |
| 6839 %} | |
| 6840 | |
| 6841 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 6842 %{ | |
| 6843 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 6844 effect(KILL cr); | |
| 6845 | |
| 6846 ins_cost(150); // XXX | |
| 6847 format %{ "addl $dst, $src\t# int" %} | |
| 6848 opcode(0x01); /* Opcode 01 /r */ | |
| 6849 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 6850 ins_pipe(ialu_mem_reg); | |
| 6851 %} | |
| 6852 | |
| 6853 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 6854 %{ | |
| 6855 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 6856 effect(KILL cr); | |
| 6857 | |
| 6858 ins_cost(125); // XXX | |
| 6859 format %{ "addl $dst, $src\t# int" %} | |
| 6860 opcode(0x81); /* Opcode 81 /0 id */ | |
| 6861 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src)); | |
| 6862 ins_pipe(ialu_mem_imm); | |
| 6863 %} | |
| 6864 | |
| 6865 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr) | |
| 6866 %{ | |
| 6867 predicate(UseIncDec); | |
| 6868 match(Set dst (AddI dst src)); | |
| 6869 effect(KILL cr); | |
| 6870 | |
| 6871 format %{ "incl $dst\t# int" %} | |
| 6872 opcode(0xFF, 0x00); // FF /0 | |
| 6873 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 6874 ins_pipe(ialu_reg); | |
| 6875 %} | |
| 6876 | |
| 6877 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr) | |
| 6878 %{ | |
| 6879 predicate(UseIncDec); | |
| 6880 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 6881 effect(KILL cr); | |
| 6882 | |
| 6883 ins_cost(125); // XXX | |
| 6884 format %{ "incl $dst\t# int" %} | |
| 6885 opcode(0xFF); /* Opcode FF /0 */ | |
| 6886 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst)); | |
| 6887 ins_pipe(ialu_mem_imm); | |
| 6888 %} | |
| 6889 | |
| 6890 // XXX why does that use AddI | |
| 6891 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr) | |
| 6892 %{ | |
| 6893 predicate(UseIncDec); | |
| 6894 match(Set dst (AddI dst src)); | |
| 6895 effect(KILL cr); | |
| 6896 | |
| 6897 format %{ "decl $dst\t# int" %} | |
| 6898 opcode(0xFF, 0x01); // FF /1 | |
| 6899 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 6900 ins_pipe(ialu_reg); | |
| 6901 %} | |
| 6902 | |
| 6903 // XXX why does that use AddI | |
| 6904 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr) | |
| 6905 %{ | |
| 6906 predicate(UseIncDec); | |
| 6907 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 6908 effect(KILL cr); | |
| 6909 | |
| 6910 ins_cost(125); // XXX | |
| 6911 format %{ "decl $dst\t# int" %} | |
| 6912 opcode(0xFF); /* Opcode FF /1 */ | |
| 6913 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst)); | |
| 6914 ins_pipe(ialu_mem_imm); | |
| 6915 %} | |
| 6916 | |
| 6917 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1) | |
| 6918 %{ | |
| 6919 match(Set dst (AddI src0 src1)); | |
| 6920 | |
| 6921 ins_cost(110); | |
| 6922 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %} | |
| 6923 opcode(0x8D); /* 0x8D /r */ | |
| 6924 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX | |
| 6925 ins_pipe(ialu_reg_reg); | |
| 6926 %} | |
| 6927 | |
| 6928 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 6929 %{ | |
| 6930 match(Set dst (AddL dst src)); | |
| 6931 effect(KILL cr); | |
| 6932 | |
| 6933 format %{ "addq $dst, $src\t# long" %} | |
| 6934 opcode(0x03); | |
| 6935 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 6936 ins_pipe(ialu_reg_reg); | |
| 6937 %} | |
| 6938 | |
| 6939 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
| 6940 %{ | |
| 6941 match(Set dst (AddL dst src)); | |
| 6942 effect(KILL cr); | |
| 6943 | |
| 6944 format %{ "addq $dst, $src\t# long" %} | |
| 6945 opcode(0x81, 0x00); /* /0 id */ | |
| 6946 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 6947 ins_pipe( ialu_reg ); | |
| 6948 %} | |
| 6949 | |
| 6950 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 6951 %{ | |
| 6952 match(Set dst (AddL dst (LoadL src))); | |
| 6953 effect(KILL cr); | |
| 6954 | |
| 6955 ins_cost(125); // XXX | |
| 6956 format %{ "addq $dst, $src\t# long" %} | |
| 6957 opcode(0x03); | |
| 6958 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 6959 ins_pipe(ialu_reg_mem); | |
| 6960 %} | |
| 6961 | |
| 6962 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 6963 %{ | |
| 6964 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
| 6965 effect(KILL cr); | |
| 6966 | |
| 6967 ins_cost(150); // XXX | |
| 6968 format %{ "addq $dst, $src\t# long" %} | |
| 6969 opcode(0x01); /* Opcode 01 /r */ | |
| 6970 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 6971 ins_pipe(ialu_mem_reg); | |
| 6972 %} | |
| 6973 | |
| 6974 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 6975 %{ | |
| 6976 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
| 6977 effect(KILL cr); | |
| 6978 | |
| 6979 ins_cost(125); // XXX | |
| 6980 format %{ "addq $dst, $src\t# long" %} | |
| 6981 opcode(0x81); /* Opcode 81 /0 id */ | |
| 6982 ins_encode(REX_mem_wide(dst), | |
| 6983 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src)); | |
| 6984 ins_pipe(ialu_mem_imm); | |
| 6985 %} | |
| 6986 | |
| 6987 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr) | |
| 6988 %{ | |
| 6989 predicate(UseIncDec); | |
| 6990 match(Set dst (AddL dst src)); | |
| 6991 effect(KILL cr); | |
| 6992 | |
| 6993 format %{ "incq $dst\t# long" %} | |
| 6994 opcode(0xFF, 0x00); // FF /0 | |
| 6995 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 6996 ins_pipe(ialu_reg); | |
| 6997 %} | |
| 6998 | |
| 6999 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr) | |
| 7000 %{ | |
| 7001 predicate(UseIncDec); | |
| 7002 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
| 7003 effect(KILL cr); | |
| 7004 | |
| 7005 ins_cost(125); // XXX | |
| 7006 format %{ "incq $dst\t# long" %} | |
| 7007 opcode(0xFF); /* Opcode FF /0 */ | |
| 7008 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst)); | |
| 7009 ins_pipe(ialu_mem_imm); | |
| 7010 %} | |
| 7011 | |
| 7012 // XXX why does that use AddL | |
| 7013 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr) | |
| 7014 %{ | |
| 7015 predicate(UseIncDec); | |
| 7016 match(Set dst (AddL dst src)); | |
| 7017 effect(KILL cr); | |
| 7018 | |
| 7019 format %{ "decq $dst\t# long" %} | |
| 7020 opcode(0xFF, 0x01); // FF /1 | |
| 7021 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 7022 ins_pipe(ialu_reg); | |
| 7023 %} | |
| 7024 | |
| 7025 // XXX why does that use AddL | |
| 7026 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr) | |
| 7027 %{ | |
| 7028 predicate(UseIncDec); | |
| 7029 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
| 7030 effect(KILL cr); | |
| 7031 | |
| 7032 ins_cost(125); // XXX | |
| 7033 format %{ "decq $dst\t# long" %} | |
| 7034 opcode(0xFF); /* Opcode FF /1 */ | |
| 7035 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst)); | |
| 7036 ins_pipe(ialu_mem_imm); | |
| 7037 %} | |
| 7038 | |
| 7039 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1) | |
| 7040 %{ | |
| 7041 match(Set dst (AddL src0 src1)); | |
| 7042 | |
| 7043 ins_cost(110); | |
| 7044 format %{ "leaq $dst, [$src0 + $src1]\t# long" %} | |
| 7045 opcode(0x8D); /* 0x8D /r */ | |
| 7046 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX | |
| 7047 ins_pipe(ialu_reg_reg); | |
| 7048 %} | |
| 7049 | |
| 7050 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr) | |
| 7051 %{ | |
| 7052 match(Set dst (AddP dst src)); | |
| 7053 effect(KILL cr); | |
| 7054 | |
| 7055 format %{ "addq $dst, $src\t# ptr" %} | |
| 7056 opcode(0x03); | |
| 7057 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 7058 ins_pipe(ialu_reg_reg); | |
| 7059 %} | |
| 7060 | |
| 7061 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr) | |
| 7062 %{ | |
| 7063 match(Set dst (AddP dst src)); | |
| 7064 effect(KILL cr); | |
| 7065 | |
| 7066 format %{ "addq $dst, $src\t# ptr" %} | |
| 7067 opcode(0x81, 0x00); /* /0 id */ | |
| 7068 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 7069 ins_pipe( ialu_reg ); | |
| 7070 %} | |
| 7071 | |
| 7072 // XXX addP mem ops ???? | |
| 7073 | |
| 7074 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1) | |
| 7075 %{ | |
| 7076 match(Set dst (AddP src0 src1)); | |
| 7077 | |
| 7078 ins_cost(110); | |
| 7079 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %} | |
| 7080 opcode(0x8D); /* 0x8D /r */ | |
| 7081 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX | |
| 7082 ins_pipe(ialu_reg_reg); | |
| 7083 %} | |
| 7084 | |
| 7085 instruct checkCastPP(rRegP dst) | |
| 7086 %{ | |
| 7087 match(Set dst (CheckCastPP dst)); | |
| 7088 | |
| 7089 size(0); | |
| 7090 format %{ "# checkcastPP of $dst" %} | |
| 7091 ins_encode(/* empty encoding */); | |
| 7092 ins_pipe(empty); | |
| 7093 %} | |
| 7094 | |
| 7095 instruct castPP(rRegP dst) | |
| 7096 %{ | |
| 7097 match(Set dst (CastPP dst)); | |
| 7098 | |
| 7099 size(0); | |
| 7100 format %{ "# castPP of $dst" %} | |
| 7101 ins_encode(/* empty encoding */); | |
| 7102 ins_pipe(empty); | |
| 7103 %} | |
| 7104 | |
| 7105 instruct castII(rRegI dst) | |
| 7106 %{ | |
| 7107 match(Set dst (CastII dst)); | |
| 7108 | |
| 7109 size(0); | |
| 7110 format %{ "# castII of $dst" %} | |
| 7111 ins_encode(/* empty encoding */); | |
| 7112 ins_cost(0); | |
| 7113 ins_pipe(empty); | |
| 7114 %} | |
| 7115 | |
| 7116 // LoadP-locked same as a regular LoadP when used with compare-swap | |
| 7117 instruct loadPLocked(rRegP dst, memory mem) | |
| 7118 %{ | |
| 7119 match(Set dst (LoadPLocked mem)); | |
| 7120 | |
| 7121 ins_cost(125); // XXX | |
| 7122 format %{ "movq $dst, $mem\t# ptr locked" %} | |
| 7123 opcode(0x8B); | |
| 7124 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 7125 ins_pipe(ialu_reg_mem); // XXX | |
| 7126 %} | |
| 7127 | |
| 7128 // Conditional-store of the updated heap-top. | |
| 7129 // Used during allocation of the shared heap. | |
| 7130 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel. | |
| 7131 | |
| 7132 instruct storePConditional(memory heap_top_ptr, | |
| 7133 rax_RegP oldval, rRegP newval, | |
| 7134 rFlagsReg cr) | |
| 7135 %{ | |
| 7136 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval))); | |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
7137 |
| 0 | 7138 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) " |
| 7139 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %} | |
| 7140 opcode(0x0F, 0xB1); | |
| 7141 ins_encode(lock_prefix, | |
| 7142 REX_reg_mem_wide(newval, heap_top_ptr), | |
| 7143 OpcP, OpcS, | |
| 7144 reg_mem(newval, heap_top_ptr)); | |
| 7145 ins_pipe(pipe_cmpxchg); | |
| 7146 %} | |
| 7147 | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7148 // Conditional-store of an int value. |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7149 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG. |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7150 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr) |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7151 %{ |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7152 match(Set cr (StoreIConditional mem (Binary oldval newval))); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7153 effect(KILL oldval); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7154 |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7155 format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %} |
| 0 | 7156 opcode(0x0F, 0xB1); |
| 7157 ins_encode(lock_prefix, | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7158 REX_reg_mem(newval, mem), |
| 0 | 7159 OpcP, OpcS, |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7160 reg_mem(newval, mem)); |
| 0 | 7161 ins_pipe(pipe_cmpxchg); |
| 7162 %} | |
| 7163 | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7164 // Conditional-store of a long value. |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7165 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG. |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7166 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr) |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7167 %{ |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7168 match(Set cr (StoreLConditional mem (Binary oldval newval))); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7169 effect(KILL oldval); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7170 |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7171 format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %} |
| 0 | 7172 opcode(0x0F, 0xB1); |
| 7173 ins_encode(lock_prefix, | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7174 REX_reg_mem_wide(newval, mem), |
| 0 | 7175 OpcP, OpcS, |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7176 reg_mem(newval, mem)); |
| 0 | 7177 ins_pipe(pipe_cmpxchg); |
| 7178 %} | |
| 7179 | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7180 |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7181 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them |
| 0 | 7182 instruct compareAndSwapP(rRegI res, |
| 7183 memory mem_ptr, | |
| 7184 rax_RegP oldval, rRegP newval, | |
| 7185 rFlagsReg cr) | |
| 7186 %{ | |
|
6795
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7187 predicate(VM_Version::supports_cx8()); |
| 0 | 7188 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); |
| 7189 effect(KILL cr, KILL oldval); | |
| 7190 | |
| 7191 format %{ "cmpxchgq $mem_ptr,$newval\t# " | |
| 7192 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" | |
| 7193 "sete $res\n\t" | |
| 7194 "movzbl $res, $res" %} | |
| 7195 opcode(0x0F, 0xB1); | |
| 7196 ins_encode(lock_prefix, | |
| 7197 REX_reg_mem_wide(newval, mem_ptr), | |
| 7198 OpcP, OpcS, | |
| 7199 reg_mem(newval, mem_ptr), | |
| 7200 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete | |
| 7201 REX_reg_breg(res, res), // movzbl | |
| 7202 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); | |
| 7203 ins_pipe( pipe_cmpxchg ); | |
| 7204 %} | |
| 7205 | |
| 7206 instruct compareAndSwapL(rRegI res, | |
| 7207 memory mem_ptr, | |
| 7208 rax_RegL oldval, rRegL newval, | |
| 7209 rFlagsReg cr) | |
| 7210 %{ | |
|
6795
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7211 predicate(VM_Version::supports_cx8()); |
| 0 | 7212 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); |
| 7213 effect(KILL cr, KILL oldval); | |
| 7214 | |
| 7215 format %{ "cmpxchgq $mem_ptr,$newval\t# " | |
| 7216 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" | |
| 7217 "sete $res\n\t" | |
| 7218 "movzbl $res, $res" %} | |
| 7219 opcode(0x0F, 0xB1); | |
| 7220 ins_encode(lock_prefix, | |
| 7221 REX_reg_mem_wide(newval, mem_ptr), | |
| 7222 OpcP, OpcS, | |
| 7223 reg_mem(newval, mem_ptr), | |
| 7224 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete | |
| 7225 REX_reg_breg(res, res), // movzbl | |
| 7226 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); | |
| 7227 ins_pipe( pipe_cmpxchg ); | |
| 7228 %} | |
| 7229 | |
| 7230 instruct compareAndSwapI(rRegI res, | |
| 7231 memory mem_ptr, | |
| 7232 rax_RegI oldval, rRegI newval, | |
| 7233 rFlagsReg cr) | |
| 7234 %{ | |
| 7235 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); | |
| 7236 effect(KILL cr, KILL oldval); | |
| 7237 | |
| 7238 format %{ "cmpxchgl $mem_ptr,$newval\t# " | |
| 7239 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" | |
| 7240 "sete $res\n\t" | |
| 7241 "movzbl $res, $res" %} | |
| 7242 opcode(0x0F, 0xB1); | |
| 7243 ins_encode(lock_prefix, | |
| 7244 REX_reg_mem(newval, mem_ptr), | |
| 7245 OpcP, OpcS, | |
| 7246 reg_mem(newval, mem_ptr), | |
| 7247 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete | |
| 7248 REX_reg_breg(res, res), // movzbl | |
| 7249 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); | |
| 7250 ins_pipe( pipe_cmpxchg ); | |
| 7251 %} | |
| 7252 | |
| 7253 | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
7254 instruct compareAndSwapN(rRegI res, |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
7255 memory mem_ptr, |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
7256 rax_RegN oldval, rRegN newval, |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
7257 rFlagsReg cr) %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
7258 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
7259 effect(KILL cr, KILL oldval); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
7260 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
7261 format %{ "cmpxchgl $mem_ptr,$newval\t# " |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
7262 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
7263 "sete $res\n\t" |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
7264 "movzbl $res, $res" %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
7265 opcode(0x0F, 0xB1); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
7266 ins_encode(lock_prefix, |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
7267 REX_reg_mem(newval, mem_ptr), |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
7268 OpcP, OpcS, |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
7269 reg_mem(newval, mem_ptr), |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
7270 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
7271 REX_reg_breg(res, res), // movzbl |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
7272 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
7273 ins_pipe( pipe_cmpxchg ); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
7274 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
7275 |
|
6795
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7276 instruct xaddI_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7277 predicate(n->as_LoadStore()->result_not_used()); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7278 match(Set dummy (GetAndAddI mem add)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7279 effect(KILL cr); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7280 format %{ "ADDL [$mem],$add" %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7281 ins_encode %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7282 if (os::is_MP()) { __ lock(); } |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7283 __ addl($mem$$Address, $add$$constant); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7284 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7285 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7286 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7287 |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7288 instruct xaddI( memory mem, rRegI newval, rFlagsReg cr) %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7289 match(Set newval (GetAndAddI mem newval)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7290 effect(KILL cr); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7291 format %{ "XADDL [$mem],$newval" %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7292 ins_encode %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7293 if (os::is_MP()) { __ lock(); } |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7294 __ xaddl($mem$$Address, $newval$$Register); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7295 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7296 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7297 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7298 |
|
10139
35c15dad89ea
8011901: Unsafe.getAndAddLong(obj, off, delta) does not work properly with long deltas
roland
parents:
9154
diff
changeset
|
7299 instruct xaddL_no_res( memory mem, Universe dummy, immL32 add, rFlagsReg cr) %{ |
|
6795
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7300 predicate(n->as_LoadStore()->result_not_used()); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7301 match(Set dummy (GetAndAddL mem add)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7302 effect(KILL cr); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7303 format %{ "ADDQ [$mem],$add" %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7304 ins_encode %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7305 if (os::is_MP()) { __ lock(); } |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7306 __ addq($mem$$Address, $add$$constant); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7307 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7308 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7309 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7310 |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7311 instruct xaddL( memory mem, rRegL newval, rFlagsReg cr) %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7312 match(Set newval (GetAndAddL mem newval)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7313 effect(KILL cr); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7314 format %{ "XADDQ [$mem],$newval" %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7315 ins_encode %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7316 if (os::is_MP()) { __ lock(); } |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7317 __ xaddq($mem$$Address, $newval$$Register); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7318 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7319 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7320 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7321 |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7322 instruct xchgI( memory mem, rRegI newval) %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7323 match(Set newval (GetAndSetI mem newval)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7324 format %{ "XCHGL $newval,[$mem]" %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7325 ins_encode %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7326 __ xchgl($newval$$Register, $mem$$Address); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7327 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7328 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7329 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7330 |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7331 instruct xchgL( memory mem, rRegL newval) %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7332 match(Set newval (GetAndSetL mem newval)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7333 format %{ "XCHGL $newval,[$mem]" %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7334 ins_encode %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7335 __ xchgq($newval$$Register, $mem$$Address); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7336 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7337 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7338 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7339 |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7340 instruct xchgP( memory mem, rRegP newval) %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7341 match(Set newval (GetAndSetP mem newval)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7342 format %{ "XCHGQ $newval,[$mem]" %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7343 ins_encode %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7344 __ xchgq($newval$$Register, $mem$$Address); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7345 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7346 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7347 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7348 |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7349 instruct xchgN( memory mem, rRegN newval) %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7350 match(Set newval (GetAndSetN mem newval)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7351 format %{ "XCHGL $newval,$mem]" %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7352 ins_encode %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7353 __ xchgl($newval$$Register, $mem$$Address); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7354 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7355 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7356 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7357 |
| 0 | 7358 //----------Subtraction Instructions------------------------------------------- |
| 7359 | |
| 7360 // Integer Subtraction Instructions | |
| 7361 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 7362 %{ | |
| 7363 match(Set dst (SubI dst src)); | |
| 7364 effect(KILL cr); | |
| 7365 | |
| 7366 format %{ "subl $dst, $src\t# int" %} | |
| 7367 opcode(0x2B); | |
| 7368 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 7369 ins_pipe(ialu_reg_reg); | |
| 7370 %} | |
| 7371 | |
| 7372 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 7373 %{ | |
| 7374 match(Set dst (SubI dst src)); | |
| 7375 effect(KILL cr); | |
| 7376 | |
| 7377 format %{ "subl $dst, $src\t# int" %} | |
| 7378 opcode(0x81, 0x05); /* Opcode 81 /5 */ | |
| 7379 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 7380 ins_pipe(ialu_reg); | |
| 7381 %} | |
| 7382 | |
| 7383 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 7384 %{ | |
| 7385 match(Set dst (SubI dst (LoadI src))); | |
| 7386 effect(KILL cr); | |
| 7387 | |
| 7388 ins_cost(125); | |
| 7389 format %{ "subl $dst, $src\t# int" %} | |
| 7390 opcode(0x2B); | |
| 7391 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 7392 ins_pipe(ialu_reg_mem); | |
| 7393 %} | |
| 7394 | |
| 7395 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 7396 %{ | |
| 7397 match(Set dst (StoreI dst (SubI (LoadI dst) src))); | |
| 7398 effect(KILL cr); | |
| 7399 | |
| 7400 ins_cost(150); | |
| 7401 format %{ "subl $dst, $src\t# int" %} | |
| 7402 opcode(0x29); /* Opcode 29 /r */ | |
| 7403 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 7404 ins_pipe(ialu_mem_reg); | |
| 7405 %} | |
| 7406 | |
| 7407 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 7408 %{ | |
| 7409 match(Set dst (StoreI dst (SubI (LoadI dst) src))); | |
| 7410 effect(KILL cr); | |
| 7411 | |
| 7412 ins_cost(125); // XXX | |
| 7413 format %{ "subl $dst, $src\t# int" %} | |
| 7414 opcode(0x81); /* Opcode 81 /5 id */ | |
| 7415 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src)); | |
| 7416 ins_pipe(ialu_mem_imm); | |
| 7417 %} | |
| 7418 | |
|
12972
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7419 instruct subExactI_rReg(rax_RegI dst, rRegI src, rFlagsReg cr) |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7420 %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7421 match(SubExactI dst src); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7422 effect(DEF cr); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7423 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7424 format %{ "subl $dst, $src\t# subExact int" %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7425 ins_encode %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7426 __ subl($dst$$Register, $src$$Register); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7427 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7428 ins_pipe(ialu_reg_reg); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7429 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7430 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7431 instruct subExactI_rReg_imm(rax_RegI dst, immI src, rFlagsReg cr) |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7432 %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7433 match(SubExactI dst src); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7434 effect(DEF cr); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7435 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7436 format %{ "subl $dst, $src\t# subExact int" %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7437 ins_encode %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7438 __ subl($dst$$Register, $src$$constant); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7439 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7440 ins_pipe(ialu_reg_reg); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7441 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7442 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7443 instruct subExactI_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr) |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7444 %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7445 match(SubExactI dst (LoadI src)); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7446 effect(DEF cr); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7447 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7448 ins_cost(125); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7449 format %{ "subl $dst, $src\t# subExact int" %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7450 ins_encode %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7451 __ subl($dst$$Register, $src$$Address); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7452 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7453 ins_pipe(ialu_reg_mem); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7454 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7455 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7456 instruct subExactL_rReg(rax_RegL dst, rRegL src, rFlagsReg cr) |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7457 %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7458 match(SubExactL dst src); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7459 effect(DEF cr); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7460 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7461 format %{ "subq $dst, $src\t# subExact long" %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7462 ins_encode %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7463 __ subq($dst$$Register, $src$$Register); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7464 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7465 ins_pipe(ialu_reg_reg); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7466 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7467 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7468 instruct subExactL_rReg_imm(rax_RegL dst, immL32 src, rFlagsReg cr) |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7469 %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7470 match(SubExactL dst (LoadL src)); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7471 effect(DEF cr); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7472 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7473 format %{ "subq $dst, $src\t# subExact long" %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7474 ins_encode %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7475 __ subq($dst$$Register, $src$$constant); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7476 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7477 ins_pipe(ialu_reg_reg); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7478 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7479 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7480 instruct subExactL_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr) |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7481 %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7482 match(SubExactI dst src); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7483 effect(DEF cr); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7484 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7485 ins_cost(125); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7486 format %{ "subq $dst, $src\t# subExact long" %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7487 ins_encode %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7488 __ subq($dst$$Register, $src$$Address); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7489 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7490 ins_pipe(ialu_reg_mem); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7491 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7492 |
| 0 | 7493 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr) |
| 7494 %{ | |
| 7495 match(Set dst (SubL dst src)); | |
| 7496 effect(KILL cr); | |
| 7497 | |
| 7498 format %{ "subq $dst, $src\t# long" %} | |
| 7499 opcode(0x2B); | |
| 7500 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 7501 ins_pipe(ialu_reg_reg); | |
| 7502 %} | |
| 7503 | |
| 7504 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr) | |
| 7505 %{ | |
| 7506 match(Set dst (SubL dst src)); | |
| 7507 effect(KILL cr); | |
| 7508 | |
| 7509 format %{ "subq $dst, $src\t# long" %} | |
| 7510 opcode(0x81, 0x05); /* Opcode 81 /5 */ | |
| 7511 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 7512 ins_pipe(ialu_reg); | |
| 7513 %} | |
| 7514 | |
| 7515 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 7516 %{ | |
| 7517 match(Set dst (SubL dst (LoadL src))); | |
| 7518 effect(KILL cr); | |
| 7519 | |
| 7520 ins_cost(125); | |
| 7521 format %{ "subq $dst, $src\t# long" %} | |
| 7522 opcode(0x2B); | |
| 7523 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 7524 ins_pipe(ialu_reg_mem); | |
| 7525 %} | |
| 7526 | |
| 7527 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 7528 %{ | |
| 7529 match(Set dst (StoreL dst (SubL (LoadL dst) src))); | |
| 7530 effect(KILL cr); | |
| 7531 | |
| 7532 ins_cost(150); | |
| 7533 format %{ "subq $dst, $src\t# long" %} | |
| 7534 opcode(0x29); /* Opcode 29 /r */ | |
| 7535 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 7536 ins_pipe(ialu_mem_reg); | |
| 7537 %} | |
| 7538 | |
| 7539 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 7540 %{ | |
| 7541 match(Set dst (StoreL dst (SubL (LoadL dst) src))); | |
| 7542 effect(KILL cr); | |
| 7543 | |
| 7544 ins_cost(125); // XXX | |
| 7545 format %{ "subq $dst, $src\t# long" %} | |
| 7546 opcode(0x81); /* Opcode 81 /5 id */ | |
| 7547 ins_encode(REX_mem_wide(dst), | |
| 7548 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src)); | |
| 7549 ins_pipe(ialu_mem_imm); | |
| 7550 %} | |
| 7551 | |
| 7552 // Subtract from a pointer | |
| 7553 // XXX hmpf??? | |
| 7554 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr) | |
| 7555 %{ | |
| 7556 match(Set dst (AddP dst (SubI zero src))); | |
| 7557 effect(KILL cr); | |
| 7558 | |
| 7559 format %{ "subq $dst, $src\t# ptr - int" %} | |
| 7560 opcode(0x2B); | |
| 7561 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 7562 ins_pipe(ialu_reg_reg); | |
| 7563 %} | |
| 7564 | |
| 7565 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr) | |
| 7566 %{ | |
| 7567 match(Set dst (SubI zero dst)); | |
| 7568 effect(KILL cr); | |
| 7569 | |
| 7570 format %{ "negl $dst\t# int" %} | |
| 7571 opcode(0xF7, 0x03); // Opcode F7 /3 | |
| 7572 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 7573 ins_pipe(ialu_reg); | |
| 7574 %} | |
| 7575 | |
| 7576 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr) | |
| 7577 %{ | |
| 7578 match(Set dst (StoreI dst (SubI zero (LoadI dst)))); | |
| 7579 effect(KILL cr); | |
| 7580 | |
| 7581 format %{ "negl $dst\t# int" %} | |
| 7582 opcode(0xF7, 0x03); // Opcode F7 /3 | |
| 7583 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 7584 ins_pipe(ialu_reg); | |
| 7585 %} | |
| 7586 | |
| 7587 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr) | |
| 7588 %{ | |
| 7589 match(Set dst (SubL zero dst)); | |
| 7590 effect(KILL cr); | |
| 7591 | |
| 7592 format %{ "negq $dst\t# long" %} | |
| 7593 opcode(0xF7, 0x03); // Opcode F7 /3 | |
| 7594 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 7595 ins_pipe(ialu_reg); | |
| 7596 %} | |
| 7597 | |
| 7598 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr) | |
| 7599 %{ | |
| 7600 match(Set dst (StoreL dst (SubL zero (LoadL dst)))); | |
| 7601 effect(KILL cr); | |
| 7602 | |
| 7603 format %{ "negq $dst\t# long" %} | |
| 7604 opcode(0xF7, 0x03); // Opcode F7 /3 | |
| 7605 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 7606 ins_pipe(ialu_reg); | |
| 7607 %} | |
| 7608 | |
|
12972
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7609 instruct negExactI_rReg(rax_RegI dst, rFlagsReg cr) |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7610 %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7611 match(NegExactI dst); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7612 effect(KILL cr); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7613 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7614 format %{ "negl $dst\t# negExact int" %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7615 ins_encode %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7616 __ negl($dst$$Register); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7617 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7618 ins_pipe(ialu_reg); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7619 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7620 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7621 instruct negExactL_rReg(rax_RegL dst, rFlagsReg cr) |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7622 %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7623 match(NegExactL dst); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7624 effect(KILL cr); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7625 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7626 format %{ "negq $dst\t# negExact long" %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7627 ins_encode %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7628 __ negq($dst$$Register); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7629 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7630 ins_pipe(ialu_reg); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7631 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7632 |
| 0 | 7633 |
| 7634 //----------Multiplication/Division Instructions------------------------------- | |
| 7635 // Integer Multiplication Instructions | |
| 7636 // Multiply Register | |
| 7637 | |
| 7638 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 7639 %{ | |
| 7640 match(Set dst (MulI dst src)); | |
| 7641 effect(KILL cr); | |
| 7642 | |
| 7643 ins_cost(300); | |
| 7644 format %{ "imull $dst, $src\t# int" %} | |
| 7645 opcode(0x0F, 0xAF); | |
| 7646 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 7647 ins_pipe(ialu_reg_reg_alu0); | |
| 7648 %} | |
| 7649 | |
| 7650 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr) | |
| 7651 %{ | |
| 7652 match(Set dst (MulI src imm)); | |
| 7653 effect(KILL cr); | |
| 7654 | |
| 7655 ins_cost(300); | |
| 7656 format %{ "imull $dst, $src, $imm\t# int" %} | |
| 7657 opcode(0x69); /* 69 /r id */ | |
| 7658 ins_encode(REX_reg_reg(dst, src), | |
| 7659 OpcSE(imm), reg_reg(dst, src), Con8or32(imm)); | |
| 7660 ins_pipe(ialu_reg_reg_alu0); | |
| 7661 %} | |
| 7662 | |
| 7663 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 7664 %{ | |
| 7665 match(Set dst (MulI dst (LoadI src))); | |
| 7666 effect(KILL cr); | |
| 7667 | |
| 7668 ins_cost(350); | |
| 7669 format %{ "imull $dst, $src\t# int" %} | |
| 7670 opcode(0x0F, 0xAF); | |
| 7671 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src)); | |
| 7672 ins_pipe(ialu_reg_mem_alu0); | |
| 7673 %} | |
| 7674 | |
| 7675 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr) | |
| 7676 %{ | |
| 7677 match(Set dst (MulI (LoadI src) imm)); | |
| 7678 effect(KILL cr); | |
| 7679 | |
| 7680 ins_cost(300); | |
| 7681 format %{ "imull $dst, $src, $imm\t# int" %} | |
| 7682 opcode(0x69); /* 69 /r id */ | |
| 7683 ins_encode(REX_reg_mem(dst, src), | |
| 7684 OpcSE(imm), reg_mem(dst, src), Con8or32(imm)); | |
| 7685 ins_pipe(ialu_reg_mem_alu0); | |
| 7686 %} | |
| 7687 | |
| 7688 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 7689 %{ | |
| 7690 match(Set dst (MulL dst src)); | |
| 7691 effect(KILL cr); | |
| 7692 | |
| 7693 ins_cost(300); | |
| 7694 format %{ "imulq $dst, $src\t# long" %} | |
| 7695 opcode(0x0F, 0xAF); | |
| 7696 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 7697 ins_pipe(ialu_reg_reg_alu0); | |
| 7698 %} | |
| 7699 | |
| 7700 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr) | |
| 7701 %{ | |
| 7702 match(Set dst (MulL src imm)); | |
| 7703 effect(KILL cr); | |
| 7704 | |
| 7705 ins_cost(300); | |
| 7706 format %{ "imulq $dst, $src, $imm\t# long" %} | |
| 7707 opcode(0x69); /* 69 /r id */ | |
| 7708 ins_encode(REX_reg_reg_wide(dst, src), | |
| 7709 OpcSE(imm), reg_reg(dst, src), Con8or32(imm)); | |
| 7710 ins_pipe(ialu_reg_reg_alu0); | |
| 7711 %} | |
| 7712 | |
| 7713 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 7714 %{ | |
| 7715 match(Set dst (MulL dst (LoadL src))); | |
| 7716 effect(KILL cr); | |
| 7717 | |
| 7718 ins_cost(350); | |
| 7719 format %{ "imulq $dst, $src\t# long" %} | |
| 7720 opcode(0x0F, 0xAF); | |
| 7721 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src)); | |
| 7722 ins_pipe(ialu_reg_mem_alu0); | |
| 7723 %} | |
| 7724 | |
| 7725 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr) | |
| 7726 %{ | |
| 7727 match(Set dst (MulL (LoadL src) imm)); | |
| 7728 effect(KILL cr); | |
| 7729 | |
| 7730 ins_cost(300); | |
| 7731 format %{ "imulq $dst, $src, $imm\t# long" %} | |
| 7732 opcode(0x69); /* 69 /r id */ | |
| 7733 ins_encode(REX_reg_mem_wide(dst, src), | |
| 7734 OpcSE(imm), reg_mem(dst, src), Con8or32(imm)); | |
| 7735 ins_pipe(ialu_reg_mem_alu0); | |
| 7736 %} | |
| 7737 | |
| 145 | 7738 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr) |
| 7739 %{ | |
| 7740 match(Set dst (MulHiL src rax)); | |
| 7741 effect(USE_KILL rax, KILL cr); | |
| 7742 | |
| 7743 ins_cost(300); | |
| 7744 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %} | |
| 7745 opcode(0xF7, 0x5); /* Opcode F7 /5 */ | |
| 7746 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src)); | |
| 7747 ins_pipe(ialu_reg_reg_alu0); | |
| 7748 %} | |
| 7749 | |
|
12972
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7750 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7751 instruct mulExactI_rReg(rax_RegI dst, rRegI src, rFlagsReg cr) |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7752 %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7753 match(MulExactI dst src); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7754 effect(DEF cr); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7755 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7756 ins_cost(300); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7757 format %{ "imull $dst, $src\t# mulExact int" %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7758 ins_encode %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7759 __ imull($dst$$Register, $src$$Register); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7760 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7761 ins_pipe(ialu_reg_reg_alu0); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7762 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7763 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7764 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7765 instruct mulExactI_rReg_imm(rax_RegI dst, rRegI src, immI imm, rFlagsReg cr) |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7766 %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7767 match(MulExactI src imm); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7768 effect(DEF cr); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7769 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7770 ins_cost(300); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7771 format %{ "imull $dst, $src, $imm\t# mulExact int" %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7772 ins_encode %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7773 __ imull($dst$$Register, $src$$Register, $imm$$constant); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7774 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7775 ins_pipe(ialu_reg_reg_alu0); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7776 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7777 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7778 instruct mulExactI_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr) |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7779 %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7780 match(MulExactI dst (LoadI src)); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7781 effect(DEF cr); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7782 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7783 ins_cost(350); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7784 format %{ "imull $dst, $src\t# mulExact int" %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7785 ins_encode %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7786 __ imull($dst$$Register, $src$$Address); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7787 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7788 ins_pipe(ialu_reg_mem_alu0); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7789 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7790 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7791 instruct mulExactL_rReg(rax_RegL dst, rRegL src, rFlagsReg cr) |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7792 %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7793 match(MulExactL dst src); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7794 effect(DEF cr); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7795 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7796 ins_cost(300); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7797 format %{ "imulq $dst, $src\t# mulExact long" %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7798 ins_encode %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7799 __ imulq($dst$$Register, $src$$Register); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7800 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7801 ins_pipe(ialu_reg_reg_alu0); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7802 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7803 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7804 instruct mulExactL_rReg_imm(rax_RegL dst, rRegL src, immL32 imm, rFlagsReg cr) |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7805 %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7806 match(MulExactL src imm); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7807 effect(DEF cr); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7808 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7809 ins_cost(300); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7810 format %{ "imulq $dst, $src, $imm\t# mulExact long" %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7811 ins_encode %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7812 __ imulq($dst$$Register, $src$$Register, $imm$$constant); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7813 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7814 ins_pipe(ialu_reg_reg_alu0); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7815 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7816 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7817 instruct mulExactL_rReg_mem(rax_RegL dst, memory src, rFlagsReg cr) |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7818 %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7819 match(MulExactL dst (LoadL src)); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7820 effect(DEF cr); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7821 |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7822 ins_cost(350); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7823 format %{ "imulq $dst, $src\t# mulExact long" %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7824 ins_encode %{ |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7825 __ imulq($dst$$Register, $src$$Address); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7826 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7827 ins_pipe(ialu_reg_mem_alu0); |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7828 %} |
|
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7829 |
| 0 | 7830 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div, |
| 7831 rFlagsReg cr) | |
| 7832 %{ | |
| 7833 match(Set rax (DivI rax div)); | |
| 7834 effect(KILL rdx, KILL cr); | |
| 7835 | |
| 7836 ins_cost(30*100+10*100); // XXX | |
| 7837 format %{ "cmpl rax, 0x80000000\t# idiv\n\t" | |
| 7838 "jne,s normal\n\t" | |
| 7839 "xorl rdx, rdx\n\t" | |
| 7840 "cmpl $div, -1\n\t" | |
| 7841 "je,s done\n" | |
| 7842 "normal: cdql\n\t" | |
| 7843 "idivl $div\n" | |
| 7844 "done:" %} | |
| 7845 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 7846 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div)); | |
| 7847 ins_pipe(ialu_reg_reg_alu0); | |
| 7848 %} | |
| 7849 | |
| 7850 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div, | |
| 7851 rFlagsReg cr) | |
| 7852 %{ | |
| 7853 match(Set rax (DivL rax div)); | |
| 7854 effect(KILL rdx, KILL cr); | |
| 7855 | |
| 7856 ins_cost(30*100+10*100); // XXX | |
| 7857 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t" | |
| 7858 "cmpq rax, rdx\n\t" | |
| 7859 "jne,s normal\n\t" | |
| 7860 "xorl rdx, rdx\n\t" | |
| 7861 "cmpq $div, -1\n\t" | |
| 7862 "je,s done\n" | |
| 7863 "normal: cdqq\n\t" | |
| 7864 "idivq $div\n" | |
| 7865 "done:" %} | |
| 7866 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 7867 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div)); | |
| 7868 ins_pipe(ialu_reg_reg_alu0); | |
| 7869 %} | |
| 7870 | |
| 7871 // Integer DIVMOD with Register, both quotient and mod results | |
| 7872 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div, | |
| 7873 rFlagsReg cr) | |
| 7874 %{ | |
| 7875 match(DivModI rax div); | |
| 7876 effect(KILL cr); | |
| 7877 | |
| 7878 ins_cost(30*100+10*100); // XXX | |
| 7879 format %{ "cmpl rax, 0x80000000\t# idiv\n\t" | |
| 7880 "jne,s normal\n\t" | |
| 7881 "xorl rdx, rdx\n\t" | |
| 7882 "cmpl $div, -1\n\t" | |
| 7883 "je,s done\n" | |
| 7884 "normal: cdql\n\t" | |
| 7885 "idivl $div\n" | |
| 7886 "done:" %} | |
| 7887 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 7888 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div)); | |
| 7889 ins_pipe(pipe_slow); | |
| 7890 %} | |
| 7891 | |
| 7892 // Long DIVMOD with Register, both quotient and mod results | |
| 7893 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div, | |
| 7894 rFlagsReg cr) | |
| 7895 %{ | |
| 7896 match(DivModL rax div); | |
| 7897 effect(KILL cr); | |
| 7898 | |
| 7899 ins_cost(30*100+10*100); // XXX | |
| 7900 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t" | |
| 7901 "cmpq rax, rdx\n\t" | |
| 7902 "jne,s normal\n\t" | |
| 7903 "xorl rdx, rdx\n\t" | |
| 7904 "cmpq $div, -1\n\t" | |
| 7905 "je,s done\n" | |
| 7906 "normal: cdqq\n\t" | |
| 7907 "idivq $div\n" | |
| 7908 "done:" %} | |
| 7909 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 7910 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div)); | |
| 7911 ins_pipe(pipe_slow); | |
| 7912 %} | |
| 7913 | |
| 7914 //----------- DivL-By-Constant-Expansions-------------------------------------- | |
| 7915 // DivI cases are handled by the compiler | |
| 7916 | |
| 605 | 7917 // Magic constant, reciprocal of 10 |
| 0 | 7918 instruct loadConL_0x6666666666666667(rRegL dst) |
| 7919 %{ | |
| 7920 effect(DEF dst); | |
| 7921 | |
| 7922 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %} | |
| 7923 ins_encode(load_immL(dst, 0x6666666666666667)); | |
| 7924 ins_pipe(ialu_reg); | |
| 7925 %} | |
| 7926 | |
| 7927 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr) | |
| 7928 %{ | |
| 7929 effect(DEF dst, USE src, USE_KILL rax, KILL cr); | |
| 7930 | |
| 7931 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %} | |
| 7932 opcode(0xF7, 0x5); /* Opcode F7 /5 */ | |
| 7933 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src)); | |
| 7934 ins_pipe(ialu_reg_reg_alu0); | |
| 7935 %} | |
| 7936 | |
| 7937 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr) | |
| 7938 %{ | |
| 7939 effect(USE_DEF dst, KILL cr); | |
| 7940 | |
| 7941 format %{ "sarq $dst, #63\t# Used in div-by-10" %} | |
| 7942 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 7943 ins_encode(reg_opc_imm_wide(dst, 0x3F)); | |
| 7944 ins_pipe(ialu_reg); | |
| 7945 %} | |
| 7946 | |
| 7947 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr) | |
| 7948 %{ | |
| 7949 effect(USE_DEF dst, KILL cr); | |
| 7950 | |
| 7951 format %{ "sarq $dst, #2\t# Used in div-by-10" %} | |
| 7952 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 7953 ins_encode(reg_opc_imm_wide(dst, 0x2)); | |
| 7954 ins_pipe(ialu_reg); | |
| 7955 %} | |
| 7956 | |
| 7957 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div) | |
| 7958 %{ | |
| 7959 match(Set dst (DivL src div)); | |
| 7960 | |
| 7961 ins_cost((5+8)*100); | |
| 7962 expand %{ | |
| 7963 rax_RegL rax; // Killed temp | |
| 7964 rFlagsReg cr; // Killed | |
| 7965 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667 | |
| 7966 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src | |
| 7967 sarL_rReg_63(src, cr); // sarq src, 63 | |
| 7968 sarL_rReg_2(dst, cr); // sarq rdx, 2 | |
| 7969 subL_rReg(dst, src, cr); // subl rdx, src | |
| 7970 %} | |
| 7971 %} | |
| 7972 | |
| 7973 //----------------------------------------------------------------------------- | |
| 7974 | |
| 7975 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div, | |
| 7976 rFlagsReg cr) | |
| 7977 %{ | |
| 7978 match(Set rdx (ModI rax div)); | |
| 7979 effect(KILL rax, KILL cr); | |
| 7980 | |
| 7981 ins_cost(300); // XXX | |
| 7982 format %{ "cmpl rax, 0x80000000\t# irem\n\t" | |
| 7983 "jne,s normal\n\t" | |
| 7984 "xorl rdx, rdx\n\t" | |
| 7985 "cmpl $div, -1\n\t" | |
| 7986 "je,s done\n" | |
| 7987 "normal: cdql\n\t" | |
| 7988 "idivl $div\n" | |
| 7989 "done:" %} | |
| 7990 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 7991 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div)); | |
| 7992 ins_pipe(ialu_reg_reg_alu0); | |
| 7993 %} | |
| 7994 | |
| 7995 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div, | |
| 7996 rFlagsReg cr) | |
| 7997 %{ | |
| 7998 match(Set rdx (ModL rax div)); | |
| 7999 effect(KILL rax, KILL cr); | |
| 8000 | |
| 8001 ins_cost(300); // XXX | |
| 8002 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t" | |
| 8003 "cmpq rax, rdx\n\t" | |
| 8004 "jne,s normal\n\t" | |
| 8005 "xorl rdx, rdx\n\t" | |
| 8006 "cmpq $div, -1\n\t" | |
| 8007 "je,s done\n" | |
| 8008 "normal: cdqq\n\t" | |
| 8009 "idivq $div\n" | |
| 8010 "done:" %} | |
| 8011 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8012 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div)); | |
| 8013 ins_pipe(ialu_reg_reg_alu0); | |
| 8014 %} | |
| 8015 | |
| 8016 // Integer Shift Instructions | |
| 8017 // Shift Left by one | |
| 8018 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr) | |
| 8019 %{ | |
| 8020 match(Set dst (LShiftI dst shift)); | |
| 8021 effect(KILL cr); | |
| 8022 | |
| 8023 format %{ "sall $dst, $shift" %} | |
| 8024 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 8025 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8026 ins_pipe(ialu_reg); | |
| 8027 %} | |
| 8028 | |
| 8029 // Shift Left by one | |
| 8030 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 8031 %{ | |
| 8032 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift))); | |
| 8033 effect(KILL cr); | |
| 8034 | |
| 8035 format %{ "sall $dst, $shift\t" %} | |
| 8036 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 8037 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8038 ins_pipe(ialu_mem_imm); | |
| 8039 %} | |
| 8040 | |
| 8041 // Shift Left by 8-bit immediate | |
| 8042 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) | |
| 8043 %{ | |
| 8044 match(Set dst (LShiftI dst shift)); | |
| 8045 effect(KILL cr); | |
| 8046 | |
| 8047 format %{ "sall $dst, $shift" %} | |
| 8048 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 8049 ins_encode(reg_opc_imm(dst, shift)); | |
| 8050 ins_pipe(ialu_reg); | |
| 8051 %} | |
| 8052 | |
| 8053 // Shift Left by 8-bit immediate | |
| 8054 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 8055 %{ | |
| 8056 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift))); | |
| 8057 effect(KILL cr); | |
| 8058 | |
| 8059 format %{ "sall $dst, $shift" %} | |
| 8060 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 8061 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 8062 ins_pipe(ialu_mem_imm); | |
| 8063 %} | |
| 8064 | |
| 8065 // Shift Left by variable | |
| 8066 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 8067 %{ | |
| 8068 match(Set dst (LShiftI dst shift)); | |
| 8069 effect(KILL cr); | |
| 8070 | |
| 8071 format %{ "sall $dst, $shift" %} | |
| 8072 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 8073 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8074 ins_pipe(ialu_reg_reg); | |
| 8075 %} | |
| 8076 | |
| 8077 // Shift Left by variable | |
| 8078 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 8079 %{ | |
| 8080 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift))); | |
| 8081 effect(KILL cr); | |
| 8082 | |
| 8083 format %{ "sall $dst, $shift" %} | |
| 8084 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 8085 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8086 ins_pipe(ialu_mem_reg); | |
| 8087 %} | |
| 8088 | |
| 8089 // Arithmetic shift right by one | |
| 8090 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr) | |
| 8091 %{ | |
| 8092 match(Set dst (RShiftI dst shift)); | |
| 8093 effect(KILL cr); | |
| 8094 | |
| 8095 format %{ "sarl $dst, $shift" %} | |
| 8096 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 8097 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8098 ins_pipe(ialu_reg); | |
| 8099 %} | |
| 8100 | |
| 8101 // Arithmetic shift right by one | |
| 8102 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 8103 %{ | |
| 8104 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 8105 effect(KILL cr); | |
| 8106 | |
| 8107 format %{ "sarl $dst, $shift" %} | |
| 8108 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 8109 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8110 ins_pipe(ialu_mem_imm); | |
| 8111 %} | |
| 8112 | |
| 8113 // Arithmetic Shift Right by 8-bit immediate | |
| 8114 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) | |
| 8115 %{ | |
| 8116 match(Set dst (RShiftI dst shift)); | |
| 8117 effect(KILL cr); | |
| 8118 | |
| 8119 format %{ "sarl $dst, $shift" %} | |
| 8120 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8121 ins_encode(reg_opc_imm(dst, shift)); | |
| 8122 ins_pipe(ialu_mem_imm); | |
| 8123 %} | |
| 8124 | |
| 8125 // Arithmetic Shift Right by 8-bit immediate | |
| 8126 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 8127 %{ | |
| 8128 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 8129 effect(KILL cr); | |
| 8130 | |
| 8131 format %{ "sarl $dst, $shift" %} | |
| 8132 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8133 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 8134 ins_pipe(ialu_mem_imm); | |
| 8135 %} | |
| 8136 | |
| 8137 // Arithmetic Shift Right by variable | |
| 8138 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 8139 %{ | |
| 8140 match(Set dst (RShiftI dst shift)); | |
| 8141 effect(KILL cr); | |
| 8142 | |
| 8143 format %{ "sarl $dst, $shift" %} | |
| 8144 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 8145 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8146 ins_pipe(ialu_reg_reg); | |
| 8147 %} | |
| 8148 | |
| 8149 // Arithmetic Shift Right by variable | |
| 8150 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 8151 %{ | |
| 8152 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 8153 effect(KILL cr); | |
| 8154 | |
| 8155 format %{ "sarl $dst, $shift" %} | |
| 8156 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 8157 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8158 ins_pipe(ialu_mem_reg); | |
| 8159 %} | |
| 8160 | |
| 8161 // Logical shift right by one | |
| 8162 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr) | |
| 8163 %{ | |
| 8164 match(Set dst (URShiftI dst shift)); | |
| 8165 effect(KILL cr); | |
| 8166 | |
| 8167 format %{ "shrl $dst, $shift" %} | |
| 8168 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 8169 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8170 ins_pipe(ialu_reg); | |
| 8171 %} | |
| 8172 | |
| 8173 // Logical shift right by one | |
| 8174 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 8175 %{ | |
| 8176 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift))); | |
| 8177 effect(KILL cr); | |
| 8178 | |
| 8179 format %{ "shrl $dst, $shift" %} | |
| 8180 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 8181 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8182 ins_pipe(ialu_mem_imm); | |
| 8183 %} | |
| 8184 | |
| 8185 // Logical Shift Right by 8-bit immediate | |
| 8186 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) | |
| 8187 %{ | |
| 8188 match(Set dst (URShiftI dst shift)); | |
| 8189 effect(KILL cr); | |
| 8190 | |
| 8191 format %{ "shrl $dst, $shift" %} | |
| 8192 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 8193 ins_encode(reg_opc_imm(dst, shift)); | |
| 8194 ins_pipe(ialu_reg); | |
| 8195 %} | |
| 8196 | |
| 8197 // Logical Shift Right by 8-bit immediate | |
| 8198 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 8199 %{ | |
| 8200 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift))); | |
| 8201 effect(KILL cr); | |
| 8202 | |
| 8203 format %{ "shrl $dst, $shift" %} | |
| 8204 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 8205 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 8206 ins_pipe(ialu_mem_imm); | |
| 8207 %} | |
| 8208 | |
| 8209 // Logical Shift Right by variable | |
| 8210 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 8211 %{ | |
| 8212 match(Set dst (URShiftI dst shift)); | |
| 8213 effect(KILL cr); | |
| 8214 | |
| 8215 format %{ "shrl $dst, $shift" %} | |
| 8216 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 8217 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8218 ins_pipe(ialu_reg_reg); | |
| 8219 %} | |
| 8220 | |
| 8221 // Logical Shift Right by variable | |
| 8222 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 8223 %{ | |
| 8224 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift))); | |
| 8225 effect(KILL cr); | |
| 8226 | |
| 8227 format %{ "shrl $dst, $shift" %} | |
| 8228 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 8229 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8230 ins_pipe(ialu_mem_reg); | |
| 8231 %} | |
| 8232 | |
| 8233 // Long Shift Instructions | |
| 8234 // Shift Left by one | |
| 8235 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr) | |
| 8236 %{ | |
| 8237 match(Set dst (LShiftL dst shift)); | |
| 8238 effect(KILL cr); | |
| 8239 | |
| 8240 format %{ "salq $dst, $shift" %} | |
| 8241 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 8242 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8243 ins_pipe(ialu_reg); | |
| 8244 %} | |
| 8245 | |
| 8246 // Shift Left by one | |
| 8247 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 8248 %{ | |
| 8249 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift))); | |
| 8250 effect(KILL cr); | |
| 8251 | |
| 8252 format %{ "salq $dst, $shift" %} | |
| 8253 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 8254 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8255 ins_pipe(ialu_mem_imm); | |
| 8256 %} | |
| 8257 | |
| 8258 // Shift Left by 8-bit immediate | |
| 8259 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr) | |
| 8260 %{ | |
| 8261 match(Set dst (LShiftL dst shift)); | |
| 8262 effect(KILL cr); | |
| 8263 | |
| 8264 format %{ "salq $dst, $shift" %} | |
| 8265 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 8266 ins_encode(reg_opc_imm_wide(dst, shift)); | |
| 8267 ins_pipe(ialu_reg); | |
| 8268 %} | |
| 8269 | |
| 8270 // Shift Left by 8-bit immediate | |
| 8271 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 8272 %{ | |
| 8273 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift))); | |
| 8274 effect(KILL cr); | |
| 8275 | |
| 8276 format %{ "salq $dst, $shift" %} | |
| 8277 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 8278 ins_encode(REX_mem_wide(dst), OpcP, | |
| 8279 RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 8280 ins_pipe(ialu_mem_imm); | |
| 8281 %} | |
| 8282 | |
| 8283 // Shift Left by variable | |
| 8284 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 8285 %{ | |
| 8286 match(Set dst (LShiftL dst shift)); | |
| 8287 effect(KILL cr); | |
| 8288 | |
| 8289 format %{ "salq $dst, $shift" %} | |
| 8290 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 8291 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8292 ins_pipe(ialu_reg_reg); | |
| 8293 %} | |
| 8294 | |
| 8295 // Shift Left by variable | |
| 8296 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 8297 %{ | |
| 8298 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift))); | |
| 8299 effect(KILL cr); | |
| 8300 | |
| 8301 format %{ "salq $dst, $shift" %} | |
| 8302 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 8303 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8304 ins_pipe(ialu_mem_reg); | |
| 8305 %} | |
| 8306 | |
| 8307 // Arithmetic shift right by one | |
| 8308 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr) | |
| 8309 %{ | |
| 8310 match(Set dst (RShiftL dst shift)); | |
| 8311 effect(KILL cr); | |
| 8312 | |
| 8313 format %{ "sarq $dst, $shift" %} | |
| 8314 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 8315 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8316 ins_pipe(ialu_reg); | |
| 8317 %} | |
| 8318 | |
| 8319 // Arithmetic shift right by one | |
| 8320 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 8321 %{ | |
| 8322 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift))); | |
| 8323 effect(KILL cr); | |
| 8324 | |
| 8325 format %{ "sarq $dst, $shift" %} | |
| 8326 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 8327 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8328 ins_pipe(ialu_mem_imm); | |
| 8329 %} | |
| 8330 | |
| 8331 // Arithmetic Shift Right by 8-bit immediate | |
| 8332 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr) | |
| 8333 %{ | |
| 8334 match(Set dst (RShiftL dst shift)); | |
| 8335 effect(KILL cr); | |
| 8336 | |
| 8337 format %{ "sarq $dst, $shift" %} | |
| 8338 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8339 ins_encode(reg_opc_imm_wide(dst, shift)); | |
| 8340 ins_pipe(ialu_mem_imm); | |
| 8341 %} | |
| 8342 | |
| 8343 // Arithmetic Shift Right by 8-bit immediate | |
| 8344 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 8345 %{ | |
| 8346 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift))); | |
| 8347 effect(KILL cr); | |
| 8348 | |
| 8349 format %{ "sarq $dst, $shift" %} | |
| 8350 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8351 ins_encode(REX_mem_wide(dst), OpcP, | |
| 8352 RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 8353 ins_pipe(ialu_mem_imm); | |
| 8354 %} | |
| 8355 | |
| 8356 // Arithmetic Shift Right by variable | |
| 8357 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 8358 %{ | |
| 8359 match(Set dst (RShiftL dst shift)); | |
| 8360 effect(KILL cr); | |
| 8361 | |
| 8362 format %{ "sarq $dst, $shift" %} | |
| 8363 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 8364 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8365 ins_pipe(ialu_reg_reg); | |
| 8366 %} | |
| 8367 | |
| 8368 // Arithmetic Shift Right by variable | |
| 8369 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 8370 %{ | |
| 8371 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift))); | |
| 8372 effect(KILL cr); | |
| 8373 | |
| 8374 format %{ "sarq $dst, $shift" %} | |
| 8375 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 8376 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8377 ins_pipe(ialu_mem_reg); | |
| 8378 %} | |
| 8379 | |
| 8380 // Logical shift right by one | |
| 8381 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr) | |
| 8382 %{ | |
| 8383 match(Set dst (URShiftL dst shift)); | |
| 8384 effect(KILL cr); | |
| 8385 | |
| 8386 format %{ "shrq $dst, $shift" %} | |
| 8387 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 8388 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst )); | |
| 8389 ins_pipe(ialu_reg); | |
| 8390 %} | |
| 8391 | |
| 8392 // Logical shift right by one | |
| 8393 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 8394 %{ | |
| 8395 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift))); | |
| 8396 effect(KILL cr); | |
| 8397 | |
| 8398 format %{ "shrq $dst, $shift" %} | |
| 8399 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 8400 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8401 ins_pipe(ialu_mem_imm); | |
| 8402 %} | |
| 8403 | |
| 8404 // Logical Shift Right by 8-bit immediate | |
| 8405 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr) | |
| 8406 %{ | |
| 8407 match(Set dst (URShiftL dst shift)); | |
| 8408 effect(KILL cr); | |
| 8409 | |
| 8410 format %{ "shrq $dst, $shift" %} | |
| 8411 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 8412 ins_encode(reg_opc_imm_wide(dst, shift)); | |
| 8413 ins_pipe(ialu_reg); | |
| 8414 %} | |
| 8415 | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
8416 |
| 0 | 8417 // Logical Shift Right by 8-bit immediate |
| 8418 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 8419 %{ | |
| 8420 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift))); | |
| 8421 effect(KILL cr); | |
| 8422 | |
| 8423 format %{ "shrq $dst, $shift" %} | |
| 8424 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 8425 ins_encode(REX_mem_wide(dst), OpcP, | |
| 8426 RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 8427 ins_pipe(ialu_mem_imm); | |
| 8428 %} | |
| 8429 | |
| 8430 // Logical Shift Right by variable | |
| 8431 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 8432 %{ | |
| 8433 match(Set dst (URShiftL dst shift)); | |
| 8434 effect(KILL cr); | |
| 8435 | |
| 8436 format %{ "shrq $dst, $shift" %} | |
| 8437 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 8438 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8439 ins_pipe(ialu_reg_reg); | |
| 8440 %} | |
| 8441 | |
| 8442 // Logical Shift Right by variable | |
| 8443 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 8444 %{ | |
| 8445 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift))); | |
| 8446 effect(KILL cr); | |
| 8447 | |
| 8448 format %{ "shrq $dst, $shift" %} | |
| 8449 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 8450 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8451 ins_pipe(ialu_mem_reg); | |
| 8452 %} | |
| 8453 | |
| 8454 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24. | |
| 8455 // This idiom is used by the compiler for the i2b bytecode. | |
| 8456 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour) | |
| 8457 %{ | |
| 8458 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour)); | |
| 8459 | |
| 8460 format %{ "movsbl $dst, $src\t# i2b" %} | |
| 8461 opcode(0x0F, 0xBE); | |
| 8462 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 8463 ins_pipe(ialu_reg_reg); | |
| 8464 %} | |
| 8465 | |
| 8466 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16. | |
| 8467 // This idiom is used by the compiler the i2s bytecode. | |
| 8468 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen) | |
| 8469 %{ | |
| 8470 match(Set dst (RShiftI (LShiftI src sixteen) sixteen)); | |
| 8471 | |
| 8472 format %{ "movswl $dst, $src\t# i2s" %} | |
| 8473 opcode(0x0F, 0xBF); | |
| 8474 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 8475 ins_pipe(ialu_reg_reg); | |
| 8476 %} | |
| 8477 | |
| 8478 // ROL/ROR instructions | |
| 8479 | |
| 8480 // ROL expand | |
| 8481 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{ | |
| 8482 effect(KILL cr, USE_DEF dst); | |
| 8483 | |
| 8484 format %{ "roll $dst" %} | |
| 8485 opcode(0xD1, 0x0); /* Opcode D1 /0 */ | |
| 8486 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8487 ins_pipe(ialu_reg); | |
| 8488 %} | |
| 8489 | |
| 8490 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{ | |
| 8491 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8492 | |
| 8493 format %{ "roll $dst, $shift" %} | |
| 8494 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */ | |
| 8495 ins_encode( reg_opc_imm(dst, shift) ); | |
| 8496 ins_pipe(ialu_reg); | |
| 8497 %} | |
| 8498 | |
| 8499 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 8500 %{ | |
| 8501 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8502 | |
| 8503 format %{ "roll $dst, $shift" %} | |
| 8504 opcode(0xD3, 0x0); /* Opcode D3 /0 */ | |
| 8505 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8506 ins_pipe(ialu_reg_reg); | |
| 8507 %} | |
| 8508 // end of ROL expand | |
| 8509 | |
| 8510 // Rotate Left by one | |
| 8511 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr) | |
| 8512 %{ | |
| 8513 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift))); | |
| 8514 | |
| 8515 expand %{ | |
| 8516 rolI_rReg_imm1(dst, cr); | |
| 8517 %} | |
| 8518 %} | |
| 8519 | |
| 8520 // Rotate Left by 8-bit immediate | |
| 8521 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr) | |
| 8522 %{ | |
| 8523 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); | |
| 8524 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift))); | |
| 8525 | |
| 8526 expand %{ | |
| 8527 rolI_rReg_imm8(dst, lshift, cr); | |
| 8528 %} | |
| 8529 %} | |
| 8530 | |
| 8531 // Rotate Left by variable | |
| 8532 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
| 8533 %{ | |
| 8534 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift)))); | |
| 8535 | |
| 8536 expand %{ | |
| 8537 rolI_rReg_CL(dst, shift, cr); | |
| 8538 %} | |
| 8539 %} | |
| 8540 | |
| 8541 // Rotate Left by variable | |
| 8542 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr) | |
| 8543 %{ | |
| 8544 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift)))); | |
| 8545 | |
| 8546 expand %{ | |
| 8547 rolI_rReg_CL(dst, shift, cr); | |
| 8548 %} | |
| 8549 %} | |
| 8550 | |
| 8551 // ROR expand | |
| 8552 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr) | |
| 8553 %{ | |
| 8554 effect(USE_DEF dst, KILL cr); | |
| 8555 | |
| 8556 format %{ "rorl $dst" %} | |
| 8557 opcode(0xD1, 0x1); /* D1 /1 */ | |
| 8558 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8559 ins_pipe(ialu_reg); | |
| 8560 %} | |
| 8561 | |
| 8562 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) | |
| 8563 %{ | |
| 8564 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8565 | |
| 8566 format %{ "rorl $dst, $shift" %} | |
| 8567 opcode(0xC1, 0x1); /* C1 /1 ib */ | |
| 8568 ins_encode(reg_opc_imm(dst, shift)); | |
| 8569 ins_pipe(ialu_reg); | |
| 8570 %} | |
| 8571 | |
| 8572 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 8573 %{ | |
| 8574 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8575 | |
| 8576 format %{ "rorl $dst, $shift" %} | |
| 8577 opcode(0xD3, 0x1); /* D3 /1 */ | |
| 8578 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8579 ins_pipe(ialu_reg_reg); | |
| 8580 %} | |
| 8581 // end of ROR expand | |
| 8582 | |
| 8583 // Rotate Right by one | |
| 8584 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr) | |
| 8585 %{ | |
| 8586 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift))); | |
| 8587 | |
| 8588 expand %{ | |
| 8589 rorI_rReg_imm1(dst, cr); | |
| 8590 %} | |
| 8591 %} | |
| 8592 | |
| 8593 // Rotate Right by 8-bit immediate | |
| 8594 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr) | |
| 8595 %{ | |
| 8596 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); | |
| 8597 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift))); | |
| 8598 | |
| 8599 expand %{ | |
| 8600 rorI_rReg_imm8(dst, rshift, cr); | |
| 8601 %} | |
| 8602 %} | |
| 8603 | |
| 8604 // Rotate Right by variable | |
| 8605 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
| 8606 %{ | |
| 8607 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift)))); | |
| 8608 | |
| 8609 expand %{ | |
| 8610 rorI_rReg_CL(dst, shift, cr); | |
| 8611 %} | |
| 8612 %} | |
| 8613 | |
| 8614 // Rotate Right by variable | |
| 8615 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr) | |
| 8616 %{ | |
| 8617 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift)))); | |
| 8618 | |
| 8619 expand %{ | |
| 8620 rorI_rReg_CL(dst, shift, cr); | |
| 8621 %} | |
| 8622 %} | |
| 8623 | |
| 8624 // for long rotate | |
| 8625 // ROL expand | |
| 8626 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{ | |
| 8627 effect(USE_DEF dst, KILL cr); | |
| 8628 | |
| 8629 format %{ "rolq $dst" %} | |
| 8630 opcode(0xD1, 0x0); /* Opcode D1 /0 */ | |
| 8631 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8632 ins_pipe(ialu_reg); | |
| 8633 %} | |
| 8634 | |
| 8635 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{ | |
| 8636 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8637 | |
| 8638 format %{ "rolq $dst, $shift" %} | |
| 8639 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */ | |
| 8640 ins_encode( reg_opc_imm_wide(dst, shift) ); | |
| 8641 ins_pipe(ialu_reg); | |
| 8642 %} | |
| 8643 | |
| 8644 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 8645 %{ | |
| 8646 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8647 | |
| 8648 format %{ "rolq $dst, $shift" %} | |
| 8649 opcode(0xD3, 0x0); /* Opcode D3 /0 */ | |
| 8650 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8651 ins_pipe(ialu_reg_reg); | |
| 8652 %} | |
| 8653 // end of ROL expand | |
| 8654 | |
| 8655 // Rotate Left by one | |
| 8656 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr) | |
| 8657 %{ | |
| 8658 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift))); | |
| 8659 | |
| 8660 expand %{ | |
| 8661 rolL_rReg_imm1(dst, cr); | |
| 8662 %} | |
| 8663 %} | |
| 8664 | |
| 8665 // Rotate Left by 8-bit immediate | |
| 8666 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr) | |
| 8667 %{ | |
| 8668 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f)); | |
| 8669 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift))); | |
| 8670 | |
| 8671 expand %{ | |
| 8672 rolL_rReg_imm8(dst, lshift, cr); | |
| 8673 %} | |
| 8674 %} | |
| 8675 | |
| 8676 // Rotate Left by variable | |
| 8677 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
| 8678 %{ | |
| 8679 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift)))); | |
| 8680 | |
| 8681 expand %{ | |
| 8682 rolL_rReg_CL(dst, shift, cr); | |
| 8683 %} | |
| 8684 %} | |
| 8685 | |
| 8686 // Rotate Left by variable | |
| 8687 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr) | |
| 8688 %{ | |
| 8689 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift)))); | |
| 8690 | |
| 8691 expand %{ | |
| 8692 rolL_rReg_CL(dst, shift, cr); | |
| 8693 %} | |
| 8694 %} | |
| 8695 | |
| 8696 // ROR expand | |
| 8697 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr) | |
| 8698 %{ | |
| 8699 effect(USE_DEF dst, KILL cr); | |
| 8700 | |
| 8701 format %{ "rorq $dst" %} | |
| 8702 opcode(0xD1, 0x1); /* D1 /1 */ | |
| 8703 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8704 ins_pipe(ialu_reg); | |
| 8705 %} | |
| 8706 | |
| 8707 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) | |
| 8708 %{ | |
| 8709 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8710 | |
| 8711 format %{ "rorq $dst, $shift" %} | |
| 8712 opcode(0xC1, 0x1); /* C1 /1 ib */ | |
| 8713 ins_encode(reg_opc_imm_wide(dst, shift)); | |
| 8714 ins_pipe(ialu_reg); | |
| 8715 %} | |
| 8716 | |
| 8717 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 8718 %{ | |
| 8719 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8720 | |
| 8721 format %{ "rorq $dst, $shift" %} | |
| 8722 opcode(0xD3, 0x1); /* D3 /1 */ | |
| 8723 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8724 ins_pipe(ialu_reg_reg); | |
| 8725 %} | |
| 8726 // end of ROR expand | |
| 8727 | |
| 8728 // Rotate Right by one | |
| 8729 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr) | |
| 8730 %{ | |
| 8731 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift))); | |
| 8732 | |
| 8733 expand %{ | |
| 8734 rorL_rReg_imm1(dst, cr); | |
| 8735 %} | |
| 8736 %} | |
| 8737 | |
| 8738 // Rotate Right by 8-bit immediate | |
| 8739 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr) | |
| 8740 %{ | |
| 8741 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f)); | |
| 8742 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift))); | |
| 8743 | |
| 8744 expand %{ | |
| 8745 rorL_rReg_imm8(dst, rshift, cr); | |
| 8746 %} | |
| 8747 %} | |
| 8748 | |
| 8749 // Rotate Right by variable | |
| 8750 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
| 8751 %{ | |
| 8752 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift)))); | |
| 8753 | |
| 8754 expand %{ | |
| 8755 rorL_rReg_CL(dst, shift, cr); | |
| 8756 %} | |
| 8757 %} | |
| 8758 | |
| 8759 // Rotate Right by variable | |
| 8760 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr) | |
| 8761 %{ | |
| 8762 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift)))); | |
| 8763 | |
| 8764 expand %{ | |
| 8765 rorL_rReg_CL(dst, shift, cr); | |
| 8766 %} | |
| 8767 %} | |
| 8768 | |
| 8769 // Logical Instructions | |
| 8770 | |
| 8771 // Integer Logical Instructions | |
| 8772 | |
| 8773 // And Instructions | |
| 8774 // And Register with Register | |
| 8775 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 8776 %{ | |
| 8777 match(Set dst (AndI dst src)); | |
| 8778 effect(KILL cr); | |
| 8779 | |
| 8780 format %{ "andl $dst, $src\t# int" %} | |
| 8781 opcode(0x23); | |
| 8782 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 8783 ins_pipe(ialu_reg_reg); | |
| 8784 %} | |
| 8785 | |
| 8786 // And Register with Immediate 255 | |
| 8787 instruct andI_rReg_imm255(rRegI dst, immI_255 src) | |
| 8788 %{ | |
| 8789 match(Set dst (AndI dst src)); | |
| 8790 | |
| 8791 format %{ "movzbl $dst, $dst\t# int & 0xFF" %} | |
| 8792 opcode(0x0F, 0xB6); | |
| 8793 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 8794 ins_pipe(ialu_reg); | |
| 8795 %} | |
| 8796 | |
| 8797 // And Register with Immediate 255 and promote to long | |
| 8798 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask) | |
| 8799 %{ | |
| 8800 match(Set dst (ConvI2L (AndI src mask))); | |
| 8801 | |
| 8802 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %} | |
| 8803 opcode(0x0F, 0xB6); | |
| 8804 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 8805 ins_pipe(ialu_reg); | |
| 8806 %} | |
| 8807 | |
| 8808 // And Register with Immediate 65535 | |
| 8809 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src) | |
| 8810 %{ | |
| 8811 match(Set dst (AndI dst src)); | |
| 8812 | |
| 8813 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %} | |
| 8814 opcode(0x0F, 0xB7); | |
| 8815 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 8816 ins_pipe(ialu_reg); | |
| 8817 %} | |
| 8818 | |
| 8819 // And Register with Immediate 65535 and promote to long | |
| 8820 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask) | |
| 8821 %{ | |
| 8822 match(Set dst (ConvI2L (AndI src mask))); | |
| 8823 | |
| 8824 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %} | |
| 8825 opcode(0x0F, 0xB7); | |
| 8826 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 8827 ins_pipe(ialu_reg); | |
| 8828 %} | |
| 8829 | |
| 8830 // And Register with Immediate | |
| 8831 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 8832 %{ | |
| 8833 match(Set dst (AndI dst src)); | |
| 8834 effect(KILL cr); | |
| 8835 | |
| 8836 format %{ "andl $dst, $src\t# int" %} | |
| 8837 opcode(0x81, 0x04); /* Opcode 81 /4 */ | |
| 8838 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 8839 ins_pipe(ialu_reg); | |
| 8840 %} | |
| 8841 | |
| 8842 // And Register with Memory | |
| 8843 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 8844 %{ | |
| 8845 match(Set dst (AndI dst (LoadI src))); | |
| 8846 effect(KILL cr); | |
| 8847 | |
| 8848 ins_cost(125); | |
| 8849 format %{ "andl $dst, $src\t# int" %} | |
| 8850 opcode(0x23); | |
| 8851 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 8852 ins_pipe(ialu_reg_mem); | |
| 8853 %} | |
| 8854 | |
| 8855 // And Memory with Register | |
| 8856 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 8857 %{ | |
| 8858 match(Set dst (StoreI dst (AndI (LoadI dst) src))); | |
| 8859 effect(KILL cr); | |
| 8860 | |
| 8861 ins_cost(150); | |
| 8862 format %{ "andl $dst, $src\t# int" %} | |
| 8863 opcode(0x21); /* Opcode 21 /r */ | |
| 8864 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 8865 ins_pipe(ialu_mem_reg); | |
| 8866 %} | |
| 8867 | |
| 8868 // And Memory with Immediate | |
| 8869 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 8870 %{ | |
| 8871 match(Set dst (StoreI dst (AndI (LoadI dst) src))); | |
| 8872 effect(KILL cr); | |
| 8873 | |
| 8874 ins_cost(125); | |
| 8875 format %{ "andl $dst, $src\t# int" %} | |
| 8876 opcode(0x81, 0x4); /* Opcode 81 /4 id */ | |
| 8877 ins_encode(REX_mem(dst), OpcSE(src), | |
| 8878 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 8879 ins_pipe(ialu_mem_imm); | |
| 8880 %} | |
| 8881 | |
| 8882 // Or Instructions | |
| 8883 // Or Register with Register | |
| 8884 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 8885 %{ | |
| 8886 match(Set dst (OrI dst src)); | |
| 8887 effect(KILL cr); | |
| 8888 | |
| 8889 format %{ "orl $dst, $src\t# int" %} | |
| 8890 opcode(0x0B); | |
| 8891 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 8892 ins_pipe(ialu_reg_reg); | |
| 8893 %} | |
| 8894 | |
| 8895 // Or Register with Immediate | |
| 8896 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 8897 %{ | |
| 8898 match(Set dst (OrI dst src)); | |
| 8899 effect(KILL cr); | |
| 8900 | |
| 8901 format %{ "orl $dst, $src\t# int" %} | |
| 8902 opcode(0x81, 0x01); /* Opcode 81 /1 id */ | |
| 8903 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 8904 ins_pipe(ialu_reg); | |
| 8905 %} | |
| 8906 | |
| 8907 // Or Register with Memory | |
| 8908 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 8909 %{ | |
| 8910 match(Set dst (OrI dst (LoadI src))); | |
| 8911 effect(KILL cr); | |
| 8912 | |
| 8913 ins_cost(125); | |
| 8914 format %{ "orl $dst, $src\t# int" %} | |
| 8915 opcode(0x0B); | |
| 8916 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 8917 ins_pipe(ialu_reg_mem); | |
| 8918 %} | |
| 8919 | |
| 8920 // Or Memory with Register | |
| 8921 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 8922 %{ | |
| 8923 match(Set dst (StoreI dst (OrI (LoadI dst) src))); | |
| 8924 effect(KILL cr); | |
| 8925 | |
| 8926 ins_cost(150); | |
| 8927 format %{ "orl $dst, $src\t# int" %} | |
| 8928 opcode(0x09); /* Opcode 09 /r */ | |
| 8929 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 8930 ins_pipe(ialu_mem_reg); | |
| 8931 %} | |
| 8932 | |
| 8933 // Or Memory with Immediate | |
| 8934 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 8935 %{ | |
| 8936 match(Set dst (StoreI dst (OrI (LoadI dst) src))); | |
| 8937 effect(KILL cr); | |
| 8938 | |
| 8939 ins_cost(125); | |
| 8940 format %{ "orl $dst, $src\t# int" %} | |
| 8941 opcode(0x81, 0x1); /* Opcode 81 /1 id */ | |
| 8942 ins_encode(REX_mem(dst), OpcSE(src), | |
| 8943 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 8944 ins_pipe(ialu_mem_imm); | |
| 8945 %} | |
| 8946 | |
| 8947 // Xor Instructions | |
| 8948 // Xor Register with Register | |
| 8949 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 8950 %{ | |
| 8951 match(Set dst (XorI dst src)); | |
| 8952 effect(KILL cr); | |
| 8953 | |
| 8954 format %{ "xorl $dst, $src\t# int" %} | |
| 8955 opcode(0x33); | |
| 8956 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 8957 ins_pipe(ialu_reg_reg); | |
| 8958 %} | |
| 8959 | |
| 403 | 8960 // Xor Register with Immediate -1 |
| 8961 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{ | |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
8962 match(Set dst (XorI dst imm)); |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
8963 |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
8964 format %{ "not $dst" %} |
| 403 | 8965 ins_encode %{ |
| 8966 __ notl($dst$$Register); | |
| 8967 %} | |
| 8968 ins_pipe(ialu_reg); | |
| 8969 %} | |
| 8970 | |
| 0 | 8971 // Xor Register with Immediate |
| 8972 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 8973 %{ | |
| 8974 match(Set dst (XorI dst src)); | |
| 8975 effect(KILL cr); | |
| 8976 | |
| 8977 format %{ "xorl $dst, $src\t# int" %} | |
| 8978 opcode(0x81, 0x06); /* Opcode 81 /6 id */ | |
| 8979 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 8980 ins_pipe(ialu_reg); | |
| 8981 %} | |
| 8982 | |
| 8983 // Xor Register with Memory | |
| 8984 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 8985 %{ | |
| 8986 match(Set dst (XorI dst (LoadI src))); | |
| 8987 effect(KILL cr); | |
| 8988 | |
| 8989 ins_cost(125); | |
| 8990 format %{ "xorl $dst, $src\t# int" %} | |
| 8991 opcode(0x33); | |
| 8992 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 8993 ins_pipe(ialu_reg_mem); | |
| 8994 %} | |
| 8995 | |
| 8996 // Xor Memory with Register | |
| 8997 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 8998 %{ | |
| 8999 match(Set dst (StoreI dst (XorI (LoadI dst) src))); | |
| 9000 effect(KILL cr); | |
| 9001 | |
| 9002 ins_cost(150); | |
| 9003 format %{ "xorl $dst, $src\t# int" %} | |
| 9004 opcode(0x31); /* Opcode 31 /r */ | |
| 9005 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 9006 ins_pipe(ialu_mem_reg); | |
| 9007 %} | |
| 9008 | |
| 9009 // Xor Memory with Immediate | |
| 9010 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 9011 %{ | |
| 9012 match(Set dst (StoreI dst (XorI (LoadI dst) src))); | |
| 9013 effect(KILL cr); | |
| 9014 | |
| 9015 ins_cost(125); | |
| 9016 format %{ "xorl $dst, $src\t# int" %} | |
| 9017 opcode(0x81, 0x6); /* Opcode 81 /6 id */ | |
| 9018 ins_encode(REX_mem(dst), OpcSE(src), | |
| 9019 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 9020 ins_pipe(ialu_mem_imm); | |
| 9021 %} | |
| 9022 | |
| 9023 | |
| 9024 // Long Logical Instructions | |
| 9025 | |
| 9026 // And Instructions | |
| 9027 // And Register with Register | |
| 9028 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 9029 %{ | |
| 9030 match(Set dst (AndL dst src)); | |
| 9031 effect(KILL cr); | |
| 9032 | |
| 9033 format %{ "andq $dst, $src\t# long" %} | |
| 9034 opcode(0x23); | |
| 9035 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 9036 ins_pipe(ialu_reg_reg); | |
| 9037 %} | |
| 9038 | |
| 9039 // And Register with Immediate 255 | |
| 9040 instruct andL_rReg_imm255(rRegL dst, immL_255 src) | |
| 9041 %{ | |
| 9042 match(Set dst (AndL dst src)); | |
| 9043 | |
|
569
2cacccded90f
6805950: Typos in andL_rReg_imm instructions in x86_64.ad
twisti
parents:
558
diff
changeset
|
9044 format %{ "movzbq $dst, $dst\t# long & 0xFF" %} |
| 0 | 9045 opcode(0x0F, 0xB6); |
| 9046 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 9047 ins_pipe(ialu_reg); | |
| 9048 %} | |
| 9049 | |
| 9050 // And Register with Immediate 65535 | |
|
569
2cacccded90f
6805950: Typos in andL_rReg_imm instructions in x86_64.ad
twisti
parents:
558
diff
changeset
|
9051 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src) |
| 0 | 9052 %{ |
| 9053 match(Set dst (AndL dst src)); | |
| 9054 | |
| 9055 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %} | |
| 9056 opcode(0x0F, 0xB7); | |
| 9057 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 9058 ins_pipe(ialu_reg); | |
| 9059 %} | |
| 9060 | |
| 9061 // And Register with Immediate | |
| 9062 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
| 9063 %{ | |
| 9064 match(Set dst (AndL dst src)); | |
| 9065 effect(KILL cr); | |
| 9066 | |
| 9067 format %{ "andq $dst, $src\t# long" %} | |
| 9068 opcode(0x81, 0x04); /* Opcode 81 /4 */ | |
| 9069 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 9070 ins_pipe(ialu_reg); | |
| 9071 %} | |
| 9072 | |
| 9073 // And Register with Memory | |
| 9074 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 9075 %{ | |
| 9076 match(Set dst (AndL dst (LoadL src))); | |
| 9077 effect(KILL cr); | |
| 9078 | |
| 9079 ins_cost(125); | |
| 9080 format %{ "andq $dst, $src\t# long" %} | |
| 9081 opcode(0x23); | |
| 9082 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 9083 ins_pipe(ialu_reg_mem); | |
| 9084 %} | |
| 9085 | |
| 9086 // And Memory with Register | |
| 9087 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 9088 %{ | |
| 9089 match(Set dst (StoreL dst (AndL (LoadL dst) src))); | |
| 9090 effect(KILL cr); | |
| 9091 | |
| 9092 ins_cost(150); | |
| 9093 format %{ "andq $dst, $src\t# long" %} | |
| 9094 opcode(0x21); /* Opcode 21 /r */ | |
| 9095 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 9096 ins_pipe(ialu_mem_reg); | |
| 9097 %} | |
| 9098 | |
| 9099 // And Memory with Immediate | |
| 9100 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 9101 %{ | |
| 9102 match(Set dst (StoreL dst (AndL (LoadL dst) src))); | |
| 9103 effect(KILL cr); | |
| 9104 | |
| 9105 ins_cost(125); | |
| 9106 format %{ "andq $dst, $src\t# long" %} | |
| 9107 opcode(0x81, 0x4); /* Opcode 81 /4 id */ | |
| 9108 ins_encode(REX_mem_wide(dst), OpcSE(src), | |
| 9109 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 9110 ins_pipe(ialu_mem_imm); | |
| 9111 %} | |
| 9112 | |
| 9113 // Or Instructions | |
| 9114 // Or Register with Register | |
| 9115 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 9116 %{ | |
| 9117 match(Set dst (OrL dst src)); | |
| 9118 effect(KILL cr); | |
| 9119 | |
| 9120 format %{ "orq $dst, $src\t# long" %} | |
| 9121 opcode(0x0B); | |
| 9122 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 9123 ins_pipe(ialu_reg_reg); | |
| 9124 %} | |
| 9125 | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
9126 // Use any_RegP to match R15 (TLS register) without spilling. |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
9127 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{ |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
9128 match(Set dst (OrL dst (CastP2X src))); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
9129 effect(KILL cr); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
9130 |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
9131 format %{ "orq $dst, $src\t# long" %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
9132 opcode(0x0B); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
9133 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
9134 ins_pipe(ialu_reg_reg); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
9135 %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
9136 |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
9137 |
| 0 | 9138 // Or Register with Immediate |
| 9139 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
| 9140 %{ | |
| 9141 match(Set dst (OrL dst src)); | |
| 9142 effect(KILL cr); | |
| 9143 | |
| 9144 format %{ "orq $dst, $src\t# long" %} | |
| 9145 opcode(0x81, 0x01); /* Opcode 81 /1 id */ | |
| 9146 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 9147 ins_pipe(ialu_reg); | |
| 9148 %} | |
| 9149 | |
| 9150 // Or Register with Memory | |
| 9151 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 9152 %{ | |
| 9153 match(Set dst (OrL dst (LoadL src))); | |
| 9154 effect(KILL cr); | |
| 9155 | |
| 9156 ins_cost(125); | |
| 9157 format %{ "orq $dst, $src\t# long" %} | |
| 9158 opcode(0x0B); | |
| 9159 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 9160 ins_pipe(ialu_reg_mem); | |
| 9161 %} | |
| 9162 | |
| 9163 // Or Memory with Register | |
| 9164 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 9165 %{ | |
| 9166 match(Set dst (StoreL dst (OrL (LoadL dst) src))); | |
| 9167 effect(KILL cr); | |
| 9168 | |
| 9169 ins_cost(150); | |
| 9170 format %{ "orq $dst, $src\t# long" %} | |
| 9171 opcode(0x09); /* Opcode 09 /r */ | |
| 9172 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 9173 ins_pipe(ialu_mem_reg); | |
| 9174 %} | |
| 9175 | |
| 9176 // Or Memory with Immediate | |
| 9177 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 9178 %{ | |
| 9179 match(Set dst (StoreL dst (OrL (LoadL dst) src))); | |
| 9180 effect(KILL cr); | |
| 9181 | |
| 9182 ins_cost(125); | |
| 9183 format %{ "orq $dst, $src\t# long" %} | |
| 9184 opcode(0x81, 0x1); /* Opcode 81 /1 id */ | |
| 9185 ins_encode(REX_mem_wide(dst), OpcSE(src), | |
| 9186 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 9187 ins_pipe(ialu_mem_imm); | |
| 9188 %} | |
| 9189 | |
| 9190 // Xor Instructions | |
| 9191 // Xor Register with Register | |
| 9192 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 9193 %{ | |
| 9194 match(Set dst (XorL dst src)); | |
| 9195 effect(KILL cr); | |
| 9196 | |
| 9197 format %{ "xorq $dst, $src\t# long" %} | |
| 9198 opcode(0x33); | |
| 9199 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 9200 ins_pipe(ialu_reg_reg); | |
| 9201 %} | |
| 9202 | |
| 403 | 9203 // Xor Register with Immediate -1 |
| 9204 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{ | |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
9205 match(Set dst (XorL dst imm)); |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
9206 |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
9207 format %{ "notq $dst" %} |
| 403 | 9208 ins_encode %{ |
| 9209 __ notq($dst$$Register); | |
| 9210 %} | |
| 9211 ins_pipe(ialu_reg); | |
| 9212 %} | |
| 9213 | |
| 0 | 9214 // Xor Register with Immediate |
| 9215 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
| 9216 %{ | |
| 9217 match(Set dst (XorL dst src)); | |
| 9218 effect(KILL cr); | |
| 9219 | |
| 9220 format %{ "xorq $dst, $src\t# long" %} | |
| 9221 opcode(0x81, 0x06); /* Opcode 81 /6 id */ | |
| 9222 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 9223 ins_pipe(ialu_reg); | |
| 9224 %} | |
| 9225 | |
| 9226 // Xor Register with Memory | |
| 9227 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 9228 %{ | |
| 9229 match(Set dst (XorL dst (LoadL src))); | |
| 9230 effect(KILL cr); | |
| 9231 | |
| 9232 ins_cost(125); | |
| 9233 format %{ "xorq $dst, $src\t# long" %} | |
| 9234 opcode(0x33); | |
| 9235 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 9236 ins_pipe(ialu_reg_mem); | |
| 9237 %} | |
| 9238 | |
| 9239 // Xor Memory with Register | |
| 9240 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 9241 %{ | |
| 9242 match(Set dst (StoreL dst (XorL (LoadL dst) src))); | |
| 9243 effect(KILL cr); | |
| 9244 | |
| 9245 ins_cost(150); | |
| 9246 format %{ "xorq $dst, $src\t# long" %} | |
| 9247 opcode(0x31); /* Opcode 31 /r */ | |
| 9248 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 9249 ins_pipe(ialu_mem_reg); | |
| 9250 %} | |
| 9251 | |
| 9252 // Xor Memory with Immediate | |
| 9253 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 9254 %{ | |
| 9255 match(Set dst (StoreL dst (XorL (LoadL dst) src))); | |
| 9256 effect(KILL cr); | |
| 9257 | |
| 9258 ins_cost(125); | |
| 9259 format %{ "xorq $dst, $src\t# long" %} | |
| 9260 opcode(0x81, 0x6); /* Opcode 81 /6 id */ | |
| 9261 ins_encode(REX_mem_wide(dst), OpcSE(src), | |
| 9262 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 9263 ins_pipe(ialu_mem_imm); | |
| 9264 %} | |
| 9265 | |
| 9266 // Convert Int to Boolean | |
| 9267 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr) | |
| 9268 %{ | |
| 9269 match(Set dst (Conv2B src)); | |
| 9270 effect(KILL cr); | |
| 9271 | |
| 9272 format %{ "testl $src, $src\t# ci2b\n\t" | |
| 9273 "setnz $dst\n\t" | |
| 9274 "movzbl $dst, $dst" %} | |
| 9275 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl | |
| 9276 setNZ_reg(dst), | |
| 9277 REX_reg_breg(dst, dst), // movzbl | |
| 9278 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst)); | |
| 9279 ins_pipe(pipe_slow); // XXX | |
| 9280 %} | |
| 9281 | |
| 9282 // Convert Pointer to Boolean | |
| 9283 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr) | |
| 9284 %{ | |
| 9285 match(Set dst (Conv2B src)); | |
| 9286 effect(KILL cr); | |
| 9287 | |
| 9288 format %{ "testq $src, $src\t# cp2b\n\t" | |
| 9289 "setnz $dst\n\t" | |
| 9290 "movzbl $dst, $dst" %} | |
| 9291 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq | |
| 9292 setNZ_reg(dst), | |
| 9293 REX_reg_breg(dst, dst), // movzbl | |
| 9294 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst)); | |
| 9295 ins_pipe(pipe_slow); // XXX | |
| 9296 %} | |
| 9297 | |
| 9298 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr) | |
| 9299 %{ | |
| 9300 match(Set dst (CmpLTMask p q)); | |
| 9301 effect(KILL cr); | |
| 9302 | |
| 9154 | 9303 ins_cost(400); |
| 0 | 9304 format %{ "cmpl $p, $q\t# cmpLTMask\n\t" |
| 9305 "setlt $dst\n\t" | |
| 9306 "movzbl $dst, $dst\n\t" | |
| 9307 "negl $dst" %} | |
| 9308 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl | |
| 9309 setLT_reg(dst), | |
| 9310 REX_reg_breg(dst, dst), // movzbl | |
| 9311 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst), | |
| 9312 neg_reg(dst)); | |
| 9313 ins_pipe(pipe_slow); | |
| 9314 %} | |
| 9315 | |
| 9316 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr) | |
| 9317 %{ | |
| 9318 match(Set dst (CmpLTMask dst zero)); | |
| 9319 effect(KILL cr); | |
| 9320 | |
| 9154 | 9321 ins_cost(100); |
| 0 | 9322 format %{ "sarl $dst, #31\t# cmpLTMask0" %} |
| 9154 | 9323 ins_encode %{ |
| 9324 __ sarl($dst$$Register, 31); | |
| 9325 %} | |
| 0 | 9326 ins_pipe(ialu_reg); |
| 9327 %} | |
| 9328 | |
| 9154 | 9329 /* Better to save a register than avoid a branch */ |
| 9330 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr) | |
| 0 | 9331 %{ |
| 9332 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); | |
| 9154 | 9333 effect(KILL cr); |
| 9334 ins_cost(300); | |
| 9335 format %{ "subl $p,$q\t# cadd_cmpLTMask\n\t" | |
| 9336 "jge done\n\t" | |
| 9337 "addl $p,$y\n" | |
| 9338 "done: " %} | |
|
3738
c7c81f18c834
7048332: Cadd_cmpLTMask doesn't handle 64-bit tmp register properly
kvn
parents:
2404
diff
changeset
|
9339 ins_encode %{ |
|
c7c81f18c834
7048332: Cadd_cmpLTMask doesn't handle 64-bit tmp register properly
kvn
parents:
2404
diff
changeset
|
9340 Register Rp = $p$$Register; |
|
c7c81f18c834
7048332: Cadd_cmpLTMask doesn't handle 64-bit tmp register properly
kvn
parents:
2404
diff
changeset
|
9341 Register Rq = $q$$Register; |
|
c7c81f18c834
7048332: Cadd_cmpLTMask doesn't handle 64-bit tmp register properly
kvn
parents:
2404
diff
changeset
|
9342 Register Ry = $y$$Register; |
| 9154 | 9343 Label done; |
|
3738
c7c81f18c834
7048332: Cadd_cmpLTMask doesn't handle 64-bit tmp register properly
kvn
parents:
2404
diff
changeset
|
9344 __ subl(Rp, Rq); |
| 9154 | 9345 __ jccb(Assembler::greaterEqual, done); |
| 9346 __ addl(Rp, Ry); | |
| 9347 __ bind(done); | |
|
3738
c7c81f18c834
7048332: Cadd_cmpLTMask doesn't handle 64-bit tmp register properly
kvn
parents:
2404
diff
changeset
|
9348 %} |
| 0 | 9349 ins_pipe(pipe_cmplt); |
| 9350 %} | |
| 9351 | |
| 9154 | 9352 /* Better to save a register than avoid a branch */ |
| 9353 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr) | |
| 9354 %{ | |
| 9355 match(Set y (AndI (CmpLTMask p q) y)); | |
| 9356 effect(KILL cr); | |
| 9357 | |
| 9358 ins_cost(300); | |
| 9359 | |
| 9360 format %{ "cmpl $p, $q\t# and_cmpLTMask\n\t" | |
| 9361 "jlt done\n\t" | |
| 9362 "xorl $y, $y\n" | |
| 9363 "done: " %} | |
| 9364 ins_encode %{ | |
| 9365 Register Rp = $p$$Register; | |
| 9366 Register Rq = $q$$Register; | |
| 9367 Register Ry = $y$$Register; | |
| 9368 Label done; | |
| 9369 __ cmpl(Rp, Rq); | |
| 9370 __ jccb(Assembler::less, done); | |
| 9371 __ xorl(Ry, Ry); | |
| 9372 __ bind(done); | |
| 9373 %} | |
| 9374 ins_pipe(pipe_cmplt); | |
| 9375 %} | |
| 9376 | |
| 9377 | |
| 0 | 9378 //---------- FP Instructions------------------------------------------------ |
| 9379 | |
| 9380 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2) | |
| 9381 %{ | |
| 9382 match(Set cr (CmpF src1 src2)); | |
| 9383 | |
| 9384 ins_cost(145); | |
| 9385 format %{ "ucomiss $src1, $src2\n\t" | |
| 9386 "jnp,s exit\n\t" | |
| 9387 "pushfq\t# saw NaN, set CF\n\t" | |
| 9388 "andq [rsp], #0xffffff2b\n\t" | |
| 9389 "popfq\n" | |
| 4759 | 9390 "exit:" %} |
| 9391 ins_encode %{ | |
| 9392 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9393 emit_cmpfp_fixup(_masm); | |
| 9394 %} | |
| 0 | 9395 ins_pipe(pipe_slow); |
| 9396 %} | |
| 9397 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9398 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9399 match(Set cr (CmpF src1 src2)); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9400 |
| 4759 | 9401 ins_cost(100); |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9402 format %{ "ucomiss $src1, $src2" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9403 ins_encode %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9404 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9405 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9406 ins_pipe(pipe_slow); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9407 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9408 |
| 0 | 9409 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2) |
| 9410 %{ | |
| 9411 match(Set cr (CmpF src1 (LoadF src2))); | |
| 9412 | |
| 9413 ins_cost(145); | |
| 9414 format %{ "ucomiss $src1, $src2\n\t" | |
| 9415 "jnp,s exit\n\t" | |
| 9416 "pushfq\t# saw NaN, set CF\n\t" | |
| 9417 "andq [rsp], #0xffffff2b\n\t" | |
| 9418 "popfq\n" | |
| 4759 | 9419 "exit:" %} |
| 9420 ins_encode %{ | |
| 9421 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 9422 emit_cmpfp_fixup(_masm); | |
| 9423 %} | |
| 0 | 9424 ins_pipe(pipe_slow); |
| 9425 %} | |
| 9426 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9427 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9428 match(Set cr (CmpF src1 (LoadF src2))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9429 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9430 ins_cost(100); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9431 format %{ "ucomiss $src1, $src2" %} |
| 4759 | 9432 ins_encode %{ |
| 9433 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 9434 %} | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9435 ins_pipe(pipe_slow); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9436 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9437 |
| 2008 | 9438 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{ |
| 9439 match(Set cr (CmpF src con)); | |
| 0 | 9440 |
| 9441 ins_cost(145); | |
| 2008 | 9442 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t" |
| 0 | 9443 "jnp,s exit\n\t" |
| 9444 "pushfq\t# saw NaN, set CF\n\t" | |
| 9445 "andq [rsp], #0xffffff2b\n\t" | |
| 9446 "popfq\n" | |
| 4759 | 9447 "exit:" %} |
| 2008 | 9448 ins_encode %{ |
| 9449 __ ucomiss($src$$XMMRegister, $constantaddress($con)); | |
| 3783 | 9450 emit_cmpfp_fixup(_masm); |
| 2008 | 9451 %} |
| 9452 ins_pipe(pipe_slow); | |
| 9453 %} | |
| 9454 | |
| 9455 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{ | |
| 9456 match(Set cr (CmpF src con)); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9457 ins_cost(100); |
| 2008 | 9458 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %} |
| 9459 ins_encode %{ | |
| 9460 __ ucomiss($src$$XMMRegister, $constantaddress($con)); | |
| 9461 %} | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9462 ins_pipe(pipe_slow); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9463 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9464 |
| 0 | 9465 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2) |
| 9466 %{ | |
| 9467 match(Set cr (CmpD src1 src2)); | |
| 9468 | |
| 9469 ins_cost(145); | |
| 9470 format %{ "ucomisd $src1, $src2\n\t" | |
| 9471 "jnp,s exit\n\t" | |
| 9472 "pushfq\t# saw NaN, set CF\n\t" | |
| 9473 "andq [rsp], #0xffffff2b\n\t" | |
| 9474 "popfq\n" | |
| 4759 | 9475 "exit:" %} |
| 9476 ins_encode %{ | |
| 9477 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9478 emit_cmpfp_fixup(_masm); | |
| 9479 %} | |
| 0 | 9480 ins_pipe(pipe_slow); |
| 9481 %} | |
| 9482 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9483 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9484 match(Set cr (CmpD src1 src2)); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9485 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9486 ins_cost(100); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9487 format %{ "ucomisd $src1, $src2 test" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9488 ins_encode %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9489 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9490 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9491 ins_pipe(pipe_slow); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9492 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9493 |
| 0 | 9494 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2) |
| 9495 %{ | |
| 9496 match(Set cr (CmpD src1 (LoadD src2))); | |
| 9497 | |
| 9498 ins_cost(145); | |
| 9499 format %{ "ucomisd $src1, $src2\n\t" | |
| 9500 "jnp,s exit\n\t" | |
| 9501 "pushfq\t# saw NaN, set CF\n\t" | |
| 9502 "andq [rsp], #0xffffff2b\n\t" | |
| 9503 "popfq\n" | |
| 4759 | 9504 "exit:" %} |
| 9505 ins_encode %{ | |
| 9506 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9507 emit_cmpfp_fixup(_masm); | |
| 9508 %} | |
| 0 | 9509 ins_pipe(pipe_slow); |
| 9510 %} | |
| 9511 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9512 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9513 match(Set cr (CmpD src1 (LoadD src2))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9514 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9515 ins_cost(100); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9516 format %{ "ucomisd $src1, $src2" %} |
| 4759 | 9517 ins_encode %{ |
| 9518 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9519 %} | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9520 ins_pipe(pipe_slow); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9521 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9522 |
| 2008 | 9523 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{ |
| 9524 match(Set cr (CmpD src con)); | |
| 0 | 9525 |
| 9526 ins_cost(145); | |
| 2008 | 9527 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 9528 "jnp,s exit\n\t" |
| 9529 "pushfq\t# saw NaN, set CF\n\t" | |
| 9530 "andq [rsp], #0xffffff2b\n\t" | |
| 9531 "popfq\n" | |
| 4759 | 9532 "exit:" %} |
| 2008 | 9533 ins_encode %{ |
| 9534 __ ucomisd($src$$XMMRegister, $constantaddress($con)); | |
| 3783 | 9535 emit_cmpfp_fixup(_masm); |
| 2008 | 9536 %} |
| 9537 ins_pipe(pipe_slow); | |
| 9538 %} | |
| 9539 | |
| 9540 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{ | |
| 9541 match(Set cr (CmpD src con)); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9542 ins_cost(100); |
| 2008 | 9543 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %} |
| 9544 ins_encode %{ | |
| 9545 __ ucomisd($src$$XMMRegister, $constantaddress($con)); | |
| 9546 %} | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9547 ins_pipe(pipe_slow); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9548 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9549 |
| 0 | 9550 // Compare into -1,0,1 |
| 9551 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr) | |
| 9552 %{ | |
| 9553 match(Set dst (CmpF3 src1 src2)); | |
| 9554 effect(KILL cr); | |
| 9555 | |
| 9556 ins_cost(275); | |
| 9557 format %{ "ucomiss $src1, $src2\n\t" | |
| 9558 "movl $dst, #-1\n\t" | |
| 9559 "jp,s done\n\t" | |
| 9560 "jb,s done\n\t" | |
| 9561 "setne $dst\n\t" | |
| 9562 "movzbl $dst, $dst\n" | |
| 9563 "done:" %} | |
| 4759 | 9564 ins_encode %{ |
| 9565 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9566 emit_cmpfp3(_masm, $dst$$Register); | |
| 9567 %} | |
| 0 | 9568 ins_pipe(pipe_slow); |
| 9569 %} | |
| 9570 | |
| 9571 // Compare into -1,0,1 | |
| 9572 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr) | |
| 9573 %{ | |
| 9574 match(Set dst (CmpF3 src1 (LoadF src2))); | |
| 9575 effect(KILL cr); | |
| 9576 | |
| 9577 ins_cost(275); | |
| 9578 format %{ "ucomiss $src1, $src2\n\t" | |
| 9579 "movl $dst, #-1\n\t" | |
| 9580 "jp,s done\n\t" | |
| 9581 "jb,s done\n\t" | |
| 9582 "setne $dst\n\t" | |
| 9583 "movzbl $dst, $dst\n" | |
| 9584 "done:" %} | |
| 4759 | 9585 ins_encode %{ |
| 9586 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 9587 emit_cmpfp3(_masm, $dst$$Register); | |
| 9588 %} | |
| 0 | 9589 ins_pipe(pipe_slow); |
| 9590 %} | |
| 9591 | |
| 9592 // Compare into -1,0,1 | |
| 2008 | 9593 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{ |
| 9594 match(Set dst (CmpF3 src con)); | |
| 0 | 9595 effect(KILL cr); |
| 9596 | |
| 9597 ins_cost(275); | |
| 2008 | 9598 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t" |
| 0 | 9599 "movl $dst, #-1\n\t" |
| 9600 "jp,s done\n\t" | |
| 9601 "jb,s done\n\t" | |
| 9602 "setne $dst\n\t" | |
| 9603 "movzbl $dst, $dst\n" | |
| 9604 "done:" %} | |
| 2008 | 9605 ins_encode %{ |
| 9606 __ ucomiss($src$$XMMRegister, $constantaddress($con)); | |
| 4759 | 9607 emit_cmpfp3(_masm, $dst$$Register); |
| 2008 | 9608 %} |
| 0 | 9609 ins_pipe(pipe_slow); |
| 9610 %} | |
| 9611 | |
| 9612 // Compare into -1,0,1 | |
| 9613 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr) | |
| 9614 %{ | |
| 9615 match(Set dst (CmpD3 src1 src2)); | |
| 9616 effect(KILL cr); | |
| 9617 | |
| 9618 ins_cost(275); | |
| 9619 format %{ "ucomisd $src1, $src2\n\t" | |
| 9620 "movl $dst, #-1\n\t" | |
| 9621 "jp,s done\n\t" | |
| 9622 "jb,s done\n\t" | |
| 9623 "setne $dst\n\t" | |
| 9624 "movzbl $dst, $dst\n" | |
| 9625 "done:" %} | |
| 4759 | 9626 ins_encode %{ |
| 9627 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9628 emit_cmpfp3(_masm, $dst$$Register); | |
| 9629 %} | |
| 0 | 9630 ins_pipe(pipe_slow); |
| 9631 %} | |
| 9632 | |
| 9633 // Compare into -1,0,1 | |
| 9634 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr) | |
| 9635 %{ | |
| 9636 match(Set dst (CmpD3 src1 (LoadD src2))); | |
| 9637 effect(KILL cr); | |
| 9638 | |
| 9639 ins_cost(275); | |
| 9640 format %{ "ucomisd $src1, $src2\n\t" | |
| 9641 "movl $dst, #-1\n\t" | |
| 9642 "jp,s done\n\t" | |
| 9643 "jb,s done\n\t" | |
| 9644 "setne $dst\n\t" | |
| 9645 "movzbl $dst, $dst\n" | |
| 9646 "done:" %} | |
| 4759 | 9647 ins_encode %{ |
| 9648 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9649 emit_cmpfp3(_masm, $dst$$Register); | |
| 9650 %} | |
| 0 | 9651 ins_pipe(pipe_slow); |
| 9652 %} | |
| 9653 | |
| 9654 // Compare into -1,0,1 | |
| 2008 | 9655 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{ |
| 9656 match(Set dst (CmpD3 src con)); | |
| 0 | 9657 effect(KILL cr); |
| 9658 | |
| 9659 ins_cost(275); | |
| 2008 | 9660 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 9661 "movl $dst, #-1\n\t" |
| 9662 "jp,s done\n\t" | |
| 9663 "jb,s done\n\t" | |
| 9664 "setne $dst\n\t" | |
| 9665 "movzbl $dst, $dst\n" | |
| 9666 "done:" %} | |
| 2008 | 9667 ins_encode %{ |
| 9668 __ ucomisd($src$$XMMRegister, $constantaddress($con)); | |
| 4759 | 9669 emit_cmpfp3(_masm, $dst$$Register); |
| 2008 | 9670 %} |
| 0 | 9671 ins_pipe(pipe_slow); |
| 9672 %} | |
| 9673 | |
| 9674 // -----------Trig and Trancendental Instructions------------------------------ | |
| 9675 instruct cosD_reg(regD dst) %{ | |
| 9676 match(Set dst (CosD dst)); | |
| 9677 | |
| 9678 format %{ "dcos $dst\n\t" %} | |
| 9679 opcode(0xD9, 0xFF); | |
| 9680 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) ); | |
| 9681 ins_pipe( pipe_slow ); | |
| 9682 %} | |
| 9683 | |
| 9684 instruct sinD_reg(regD dst) %{ | |
| 9685 match(Set dst (SinD dst)); | |
| 9686 | |
| 9687 format %{ "dsin $dst\n\t" %} | |
| 9688 opcode(0xD9, 0xFE); | |
| 9689 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) ); | |
| 9690 ins_pipe( pipe_slow ); | |
| 9691 %} | |
| 9692 | |
| 9693 instruct tanD_reg(regD dst) %{ | |
| 9694 match(Set dst (TanD dst)); | |
| 9695 | |
| 9696 format %{ "dtan $dst\n\t" %} | |
| 9697 ins_encode( Push_SrcXD(dst), | |
| 9698 Opcode(0xD9), Opcode(0xF2), //fptan | |
| 9699 Opcode(0xDD), Opcode(0xD8), //fstp st | |
| 9700 Push_ResultXD(dst) ); | |
| 9701 ins_pipe( pipe_slow ); | |
| 9702 %} | |
| 9703 | |
| 9704 instruct log10D_reg(regD dst) %{ | |
| 9705 // The source and result Double operands in XMM registers | |
| 9706 match(Set dst (Log10D dst)); | |
| 9707 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number | |
| 9708 // fyl2x ; compute log_10(2) * log_2(x) | |
| 9709 format %{ "fldlg2\t\t\t#Log10\n\t" | |
| 9710 "fyl2x\t\t\t# Q=Log10*Log_2(x)\n\t" | |
| 9711 %} | |
| 9712 ins_encode(Opcode(0xD9), Opcode(0xEC), // fldlg2 | |
| 9713 Push_SrcXD(dst), | |
| 9714 Opcode(0xD9), Opcode(0xF1), // fyl2x | |
| 9715 Push_ResultXD(dst)); | |
| 9716 | |
| 9717 ins_pipe( pipe_slow ); | |
| 9718 %} | |
| 9719 | |
| 9720 instruct logD_reg(regD dst) %{ | |
| 9721 // The source and result Double operands in XMM registers | |
| 9722 match(Set dst (LogD dst)); | |
| 9723 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number | |
| 9724 // fyl2x ; compute log_e(2) * log_2(x) | |
| 9725 format %{ "fldln2\t\t\t#Log_e\n\t" | |
| 9726 "fyl2x\t\t\t# Q=Log_e*Log_2(x)\n\t" | |
| 9727 %} | |
| 9728 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 | |
| 9729 Push_SrcXD(dst), | |
| 9730 Opcode(0xD9), Opcode(0xF1), // fyl2x | |
| 9731 Push_ResultXD(dst)); | |
| 9732 ins_pipe( pipe_slow ); | |
| 9733 %} | |
| 9734 | |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9735 instruct powD_reg(regD dst, regD src0, regD src1, rax_RegI rax, rdx_RegI rdx, rcx_RegI rcx, rFlagsReg cr) %{ |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9736 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9737 effect(KILL rax, KILL rdx, KILL rcx, KILL cr); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9738 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9739 ins_encode %{ |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9740 __ subptr(rsp, 8); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9741 __ movdbl(Address(rsp, 0), $src1$$XMMRegister); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9742 __ fld_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9743 __ movdbl(Address(rsp, 0), $src0$$XMMRegister); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9744 __ fld_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9745 __ fast_pow(); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9746 __ fstp_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9747 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9748 __ addptr(rsp, 8); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9749 %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9750 ins_pipe( pipe_slow ); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9751 %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9752 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9753 instruct expD_reg(regD dst, regD src, rax_RegI rax, rdx_RegI rdx, rcx_RegI rcx, rFlagsReg cr) %{ |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9754 match(Set dst (ExpD src)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9755 effect(KILL rax, KILL rcx, KILL rdx, KILL cr); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9756 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9757 ins_encode %{ |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9758 __ subptr(rsp, 8); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9759 __ movdbl(Address(rsp, 0), $src$$XMMRegister); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9760 __ fld_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9761 __ fast_exp(); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9762 __ fstp_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9763 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9764 __ addptr(rsp, 8); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9765 %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9766 ins_pipe( pipe_slow ); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9767 %} |
| 0 | 9768 |
| 9769 //----------Arithmetic Conversion Instructions--------------------------------- | |
| 9770 | |
| 9771 instruct roundFloat_nop(regF dst) | |
| 9772 %{ | |
| 9773 match(Set dst (RoundFloat dst)); | |
| 9774 | |
| 9775 ins_cost(0); | |
| 9776 ins_encode(); | |
| 9777 ins_pipe(empty); | |
| 9778 %} | |
| 9779 | |
| 9780 instruct roundDouble_nop(regD dst) | |
| 9781 %{ | |
| 9782 match(Set dst (RoundDouble dst)); | |
| 9783 | |
| 9784 ins_cost(0); | |
| 9785 ins_encode(); | |
| 9786 ins_pipe(empty); | |
| 9787 %} | |
| 9788 | |
| 9789 instruct convF2D_reg_reg(regD dst, regF src) | |
| 9790 %{ | |
| 9791 match(Set dst (ConvF2D src)); | |
| 9792 | |
| 9793 format %{ "cvtss2sd $dst, $src" %} | |
| 4759 | 9794 ins_encode %{ |
| 9795 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister); | |
| 9796 %} | |
| 0 | 9797 ins_pipe(pipe_slow); // XXX |
| 9798 %} | |
| 9799 | |
| 9800 instruct convF2D_reg_mem(regD dst, memory src) | |
| 9801 %{ | |
| 9802 match(Set dst (ConvF2D (LoadF src))); | |
| 9803 | |
| 9804 format %{ "cvtss2sd $dst, $src" %} | |
| 4759 | 9805 ins_encode %{ |
| 9806 __ cvtss2sd ($dst$$XMMRegister, $src$$Address); | |
| 9807 %} | |
| 0 | 9808 ins_pipe(pipe_slow); // XXX |
| 9809 %} | |
| 9810 | |
| 9811 instruct convD2F_reg_reg(regF dst, regD src) | |
| 9812 %{ | |
| 9813 match(Set dst (ConvD2F src)); | |
| 9814 | |
| 9815 format %{ "cvtsd2ss $dst, $src" %} | |
| 4759 | 9816 ins_encode %{ |
| 9817 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister); | |
| 9818 %} | |
| 0 | 9819 ins_pipe(pipe_slow); // XXX |
| 9820 %} | |
| 9821 | |
| 9822 instruct convD2F_reg_mem(regF dst, memory src) | |
| 9823 %{ | |
| 9824 match(Set dst (ConvD2F (LoadD src))); | |
| 9825 | |
| 9826 format %{ "cvtsd2ss $dst, $src" %} | |
| 4759 | 9827 ins_encode %{ |
| 9828 __ cvtsd2ss ($dst$$XMMRegister, $src$$Address); | |
| 9829 %} | |
| 0 | 9830 ins_pipe(pipe_slow); // XXX |
| 9831 %} | |
| 9832 | |
| 9833 // XXX do mem variants | |
| 9834 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr) | |
| 9835 %{ | |
| 9836 match(Set dst (ConvF2I src)); | |
| 9837 effect(KILL cr); | |
| 9838 | |
| 9839 format %{ "cvttss2sil $dst, $src\t# f2i\n\t" | |
| 9840 "cmpl $dst, #0x80000000\n\t" | |
| 9841 "jne,s done\n\t" | |
| 9842 "subq rsp, #8\n\t" | |
| 9843 "movss [rsp], $src\n\t" | |
| 9844 "call f2i_fixup\n\t" | |
| 9845 "popq $dst\n" | |
| 9846 "done: "%} | |
| 4759 | 9847 ins_encode %{ |
| 9848 Label done; | |
| 9849 __ cvttss2sil($dst$$Register, $src$$XMMRegister); | |
| 9850 __ cmpl($dst$$Register, 0x80000000); | |
| 9851 __ jccb(Assembler::notEqual, done); | |
| 9852 __ subptr(rsp, 8); | |
| 9853 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 9854 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup()))); | |
| 9855 __ pop($dst$$Register); | |
| 9856 __ bind(done); | |
| 9857 %} | |
| 0 | 9858 ins_pipe(pipe_slow); |
| 9859 %} | |
| 9860 | |
| 9861 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr) | |
| 9862 %{ | |
| 9863 match(Set dst (ConvF2L src)); | |
| 9864 effect(KILL cr); | |
| 9865 | |
| 9866 format %{ "cvttss2siq $dst, $src\t# f2l\n\t" | |
| 9867 "cmpq $dst, [0x8000000000000000]\n\t" | |
| 9868 "jne,s done\n\t" | |
| 9869 "subq rsp, #8\n\t" | |
| 9870 "movss [rsp], $src\n\t" | |
| 9871 "call f2l_fixup\n\t" | |
| 9872 "popq $dst\n" | |
| 9873 "done: "%} | |
| 4759 | 9874 ins_encode %{ |
| 9875 Label done; | |
| 9876 __ cvttss2siq($dst$$Register, $src$$XMMRegister); | |
| 9877 __ cmp64($dst$$Register, | |
| 9878 ExternalAddress((address) StubRoutines::x86::double_sign_flip())); | |
| 9879 __ jccb(Assembler::notEqual, done); | |
| 9880 __ subptr(rsp, 8); | |
| 9881 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 9882 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup()))); | |
| 9883 __ pop($dst$$Register); | |
| 9884 __ bind(done); | |
| 9885 %} | |
| 0 | 9886 ins_pipe(pipe_slow); |
| 9887 %} | |
| 9888 | |
| 9889 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr) | |
| 9890 %{ | |
| 9891 match(Set dst (ConvD2I src)); | |
| 9892 effect(KILL cr); | |
| 9893 | |
| 9894 format %{ "cvttsd2sil $dst, $src\t# d2i\n\t" | |
| 9895 "cmpl $dst, #0x80000000\n\t" | |
| 9896 "jne,s done\n\t" | |
| 9897 "subq rsp, #8\n\t" | |
| 9898 "movsd [rsp], $src\n\t" | |
| 9899 "call d2i_fixup\n\t" | |
| 9900 "popq $dst\n" | |
| 9901 "done: "%} | |
| 4759 | 9902 ins_encode %{ |
| 9903 Label done; | |
| 9904 __ cvttsd2sil($dst$$Register, $src$$XMMRegister); | |
| 9905 __ cmpl($dst$$Register, 0x80000000); | |
| 9906 __ jccb(Assembler::notEqual, done); | |
| 9907 __ subptr(rsp, 8); | |
| 9908 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 9909 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup()))); | |
| 9910 __ pop($dst$$Register); | |
| 9911 __ bind(done); | |
| 9912 %} | |
| 0 | 9913 ins_pipe(pipe_slow); |
| 9914 %} | |
| 9915 | |
| 9916 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr) | |
| 9917 %{ | |
| 9918 match(Set dst (ConvD2L src)); | |
| 9919 effect(KILL cr); | |
| 9920 | |
| 9921 format %{ "cvttsd2siq $dst, $src\t# d2l\n\t" | |
| 9922 "cmpq $dst, [0x8000000000000000]\n\t" | |
| 9923 "jne,s done\n\t" | |
| 9924 "subq rsp, #8\n\t" | |
| 9925 "movsd [rsp], $src\n\t" | |
| 9926 "call d2l_fixup\n\t" | |
| 9927 "popq $dst\n" | |
| 9928 "done: "%} | |
| 4759 | 9929 ins_encode %{ |
| 9930 Label done; | |
| 9931 __ cvttsd2siq($dst$$Register, $src$$XMMRegister); | |
| 9932 __ cmp64($dst$$Register, | |
| 9933 ExternalAddress((address) StubRoutines::x86::double_sign_flip())); | |
| 9934 __ jccb(Assembler::notEqual, done); | |
| 9935 __ subptr(rsp, 8); | |
| 9936 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 9937 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup()))); | |
| 9938 __ pop($dst$$Register); | |
| 9939 __ bind(done); | |
| 9940 %} | |
| 0 | 9941 ins_pipe(pipe_slow); |
| 9942 %} | |
| 9943 | |
| 9944 instruct convI2F_reg_reg(regF dst, rRegI src) | |
| 9945 %{ | |
| 71 | 9946 predicate(!UseXmmI2F); |
| 0 | 9947 match(Set dst (ConvI2F src)); |
| 9948 | |
| 9949 format %{ "cvtsi2ssl $dst, $src\t# i2f" %} | |
| 4759 | 9950 ins_encode %{ |
| 9951 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register); | |
| 9952 %} | |
| 0 | 9953 ins_pipe(pipe_slow); // XXX |
| 9954 %} | |
| 9955 | |
| 9956 instruct convI2F_reg_mem(regF dst, memory src) | |
| 9957 %{ | |
| 9958 match(Set dst (ConvI2F (LoadI src))); | |
| 9959 | |
| 9960 format %{ "cvtsi2ssl $dst, $src\t# i2f" %} | |
| 4759 | 9961 ins_encode %{ |
| 9962 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address); | |
| 9963 %} | |
| 0 | 9964 ins_pipe(pipe_slow); // XXX |
| 9965 %} | |
| 9966 | |
| 9967 instruct convI2D_reg_reg(regD dst, rRegI src) | |
| 9968 %{ | |
| 71 | 9969 predicate(!UseXmmI2D); |
| 0 | 9970 match(Set dst (ConvI2D src)); |
| 9971 | |
| 9972 format %{ "cvtsi2sdl $dst, $src\t# i2d" %} | |
| 4759 | 9973 ins_encode %{ |
| 9974 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register); | |
| 9975 %} | |
| 0 | 9976 ins_pipe(pipe_slow); // XXX |
| 9977 %} | |
| 9978 | |
| 9979 instruct convI2D_reg_mem(regD dst, memory src) | |
| 9980 %{ | |
| 9981 match(Set dst (ConvI2D (LoadI src))); | |
| 9982 | |
| 9983 format %{ "cvtsi2sdl $dst, $src\t# i2d" %} | |
| 4759 | 9984 ins_encode %{ |
| 9985 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address); | |
| 9986 %} | |
| 0 | 9987 ins_pipe(pipe_slow); // XXX |
| 9988 %} | |
| 9989 | |
| 71 | 9990 instruct convXI2F_reg(regF dst, rRegI src) |
| 9991 %{ | |
| 9992 predicate(UseXmmI2F); | |
| 9993 match(Set dst (ConvI2F src)); | |
| 9994 | |
| 9995 format %{ "movdl $dst, $src\n\t" | |
| 9996 "cvtdq2psl $dst, $dst\t# i2f" %} | |
| 9997 ins_encode %{ | |
| 9998 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 9999 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister); | |
| 10000 %} | |
| 10001 ins_pipe(pipe_slow); // XXX | |
| 10002 %} | |
| 10003 | |
| 10004 instruct convXI2D_reg(regD dst, rRegI src) | |
| 10005 %{ | |
| 10006 predicate(UseXmmI2D); | |
| 10007 match(Set dst (ConvI2D src)); | |
| 10008 | |
| 10009 format %{ "movdl $dst, $src\n\t" | |
| 10010 "cvtdq2pdl $dst, $dst\t# i2d" %} | |
| 10011 ins_encode %{ | |
| 10012 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 10013 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister); | |
| 10014 %} | |
| 10015 ins_pipe(pipe_slow); // XXX | |
| 10016 %} | |
| 10017 | |
| 0 | 10018 instruct convL2F_reg_reg(regF dst, rRegL src) |
| 10019 %{ | |
| 10020 match(Set dst (ConvL2F src)); | |
| 10021 | |
| 10022 format %{ "cvtsi2ssq $dst, $src\t# l2f" %} | |
| 4759 | 10023 ins_encode %{ |
| 10024 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register); | |
| 10025 %} | |
| 0 | 10026 ins_pipe(pipe_slow); // XXX |
| 10027 %} | |
| 10028 | |
| 10029 instruct convL2F_reg_mem(regF dst, memory src) | |
| 10030 %{ | |
| 10031 match(Set dst (ConvL2F (LoadL src))); | |
| 10032 | |
| 10033 format %{ "cvtsi2ssq $dst, $src\t# l2f" %} | |
| 4759 | 10034 ins_encode %{ |
| 10035 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address); | |
| 10036 %} | |
| 0 | 10037 ins_pipe(pipe_slow); // XXX |
| 10038 %} | |
| 10039 | |
| 10040 instruct convL2D_reg_reg(regD dst, rRegL src) | |
| 10041 %{ | |
| 10042 match(Set dst (ConvL2D src)); | |
| 10043 | |
| 10044 format %{ "cvtsi2sdq $dst, $src\t# l2d" %} | |
| 4759 | 10045 ins_encode %{ |
| 10046 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register); | |
| 10047 %} | |
| 0 | 10048 ins_pipe(pipe_slow); // XXX |
| 10049 %} | |
| 10050 | |
| 10051 instruct convL2D_reg_mem(regD dst, memory src) | |
| 10052 %{ | |
| 10053 match(Set dst (ConvL2D (LoadL src))); | |
| 10054 | |
| 10055 format %{ "cvtsi2sdq $dst, $src\t# l2d" %} | |
| 4759 | 10056 ins_encode %{ |
| 10057 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address); | |
| 10058 %} | |
| 0 | 10059 ins_pipe(pipe_slow); // XXX |
| 10060 %} | |
| 10061 | |
| 10062 instruct convI2L_reg_reg(rRegL dst, rRegI src) | |
| 10063 %{ | |
| 10064 match(Set dst (ConvI2L src)); | |
| 10065 | |
| 10066 ins_cost(125); | |
| 10067 format %{ "movslq $dst, $src\t# i2l" %} | |
| 824 | 10068 ins_encode %{ |
| 10069 __ movslq($dst$$Register, $src$$Register); | |
| 10070 %} | |
| 0 | 10071 ins_pipe(ialu_reg_reg); |
| 10072 %} | |
| 10073 | |
| 10074 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src) | |
| 10075 // %{ | |
| 10076 // match(Set dst (ConvI2L src)); | |
| 10077 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 && | |
| 10078 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0); | |
| 10079 // predicate(((const TypeNode*) n)->type()->is_long()->_hi == | |
| 10080 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi && | |
| 10081 // ((const TypeNode*) n)->type()->is_long()->_lo == | |
| 10082 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo); | |
| 10083 | |
| 10084 // format %{ "movl $dst, $src\t# unsigned i2l" %} | |
| 10085 // ins_encode(enc_copy(dst, src)); | |
| 10086 // // opcode(0x63); // needs REX.W | |
| 10087 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src)); | |
| 10088 // ins_pipe(ialu_reg_reg); | |
| 10089 // %} | |
| 10090 | |
| 10091 // Zero-extend convert int to long | |
| 10092 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask) | |
| 10093 %{ | |
| 10094 match(Set dst (AndL (ConvI2L src) mask)); | |
| 10095 | |
| 10096 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %} | |
| 4759 | 10097 ins_encode %{ |
| 10098 if ($dst$$reg != $src$$reg) { | |
| 10099 __ movl($dst$$Register, $src$$Register); | |
| 10100 } | |
| 10101 %} | |
| 0 | 10102 ins_pipe(ialu_reg_reg); |
| 10103 %} | |
| 10104 | |
| 10105 // Zero-extend convert int to long | |
| 10106 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask) | |
| 10107 %{ | |
| 10108 match(Set dst (AndL (ConvI2L (LoadI src)) mask)); | |
| 10109 | |
| 10110 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %} | |
| 4759 | 10111 ins_encode %{ |
| 10112 __ movl($dst$$Register, $src$$Address); | |
| 10113 %} | |
| 0 | 10114 ins_pipe(ialu_reg_mem); |
| 10115 %} | |
| 10116 | |
| 10117 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask) | |
| 10118 %{ | |
| 10119 match(Set dst (AndL src mask)); | |
| 10120 | |
| 10121 format %{ "movl $dst, $src\t# zero-extend long" %} | |
| 4759 | 10122 ins_encode %{ |
| 10123 __ movl($dst$$Register, $src$$Register); | |
| 10124 %} | |
| 0 | 10125 ins_pipe(ialu_reg_reg); |
| 10126 %} | |
| 10127 | |
| 10128 instruct convL2I_reg_reg(rRegI dst, rRegL src) | |
| 10129 %{ | |
| 10130 match(Set dst (ConvL2I src)); | |
| 10131 | |
| 10132 format %{ "movl $dst, $src\t# l2i" %} | |
| 4759 | 10133 ins_encode %{ |
| 10134 __ movl($dst$$Register, $src$$Register); | |
| 10135 %} | |
| 0 | 10136 ins_pipe(ialu_reg_reg); |
| 10137 %} | |
| 10138 | |
| 10139 | |
| 10140 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{ | |
| 10141 match(Set dst (MoveF2I src)); | |
| 10142 effect(DEF dst, USE src); | |
| 10143 | |
| 10144 ins_cost(125); | |
| 10145 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %} | |
| 4759 | 10146 ins_encode %{ |
| 10147 __ movl($dst$$Register, Address(rsp, $src$$disp)); | |
| 10148 %} | |
| 0 | 10149 ins_pipe(ialu_reg_mem); |
| 10150 %} | |
| 10151 | |
| 10152 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ | |
| 10153 match(Set dst (MoveI2F src)); | |
| 10154 effect(DEF dst, USE src); | |
| 10155 | |
| 10156 ins_cost(125); | |
| 10157 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %} | |
| 4759 | 10158 ins_encode %{ |
| 10159 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 10160 %} | |
| 0 | 10161 ins_pipe(pipe_slow); |
| 10162 %} | |
| 10163 | |
| 10164 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{ | |
| 10165 match(Set dst (MoveD2L src)); | |
| 10166 effect(DEF dst, USE src); | |
| 10167 | |
| 10168 ins_cost(125); | |
| 10169 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %} | |
| 4759 | 10170 ins_encode %{ |
| 10171 __ movq($dst$$Register, Address(rsp, $src$$disp)); | |
| 10172 %} | |
| 0 | 10173 ins_pipe(ialu_reg_mem); |
| 10174 %} | |
| 10175 | |
| 10176 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{ | |
| 10177 predicate(!UseXmmLoadAndClearUpper); | |
| 10178 match(Set dst (MoveL2D src)); | |
| 10179 effect(DEF dst, USE src); | |
| 10180 | |
| 10181 ins_cost(125); | |
| 10182 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %} | |
| 4759 | 10183 ins_encode %{ |
| 10184 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 10185 %} | |
| 0 | 10186 ins_pipe(pipe_slow); |
| 10187 %} | |
| 10188 | |
| 10189 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ | |
| 10190 predicate(UseXmmLoadAndClearUpper); | |
| 10191 match(Set dst (MoveL2D src)); | |
| 10192 effect(DEF dst, USE src); | |
| 10193 | |
| 10194 ins_cost(125); | |
| 10195 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %} | |
| 4759 | 10196 ins_encode %{ |
| 10197 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 10198 %} | |
| 0 | 10199 ins_pipe(pipe_slow); |
| 10200 %} | |
| 10201 | |
| 10202 | |
| 10203 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ | |
| 10204 match(Set dst (MoveF2I src)); | |
| 10205 effect(DEF dst, USE src); | |
| 10206 | |
| 10207 ins_cost(95); // XXX | |
| 10208 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %} | |
| 4759 | 10209 ins_encode %{ |
| 10210 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister); | |
| 10211 %} | |
| 0 | 10212 ins_pipe(pipe_slow); |
| 10213 %} | |
| 10214 | |
| 10215 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{ | |
| 10216 match(Set dst (MoveI2F src)); | |
| 10217 effect(DEF dst, USE src); | |
| 10218 | |
| 10219 ins_cost(100); | |
| 10220 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %} | |
| 4759 | 10221 ins_encode %{ |
| 10222 __ movl(Address(rsp, $dst$$disp), $src$$Register); | |
| 10223 %} | |
| 0 | 10224 ins_pipe( ialu_mem_reg ); |
| 10225 %} | |
| 10226 | |
| 10227 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ | |
| 10228 match(Set dst (MoveD2L src)); | |
| 10229 effect(DEF dst, USE src); | |
| 10230 | |
| 10231 ins_cost(95); // XXX | |
| 10232 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %} | |
| 4759 | 10233 ins_encode %{ |
| 10234 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister); | |
| 10235 %} | |
| 0 | 10236 ins_pipe(pipe_slow); |
| 10237 %} | |
| 10238 | |
| 10239 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{ | |
| 10240 match(Set dst (MoveL2D src)); | |
| 10241 effect(DEF dst, USE src); | |
| 10242 | |
| 10243 ins_cost(100); | |
| 10244 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %} | |
| 4759 | 10245 ins_encode %{ |
| 10246 __ movq(Address(rsp, $dst$$disp), $src$$Register); | |
| 10247 %} | |
| 0 | 10248 ins_pipe(ialu_mem_reg); |
| 10249 %} | |
| 10250 | |
| 10251 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{ | |
| 10252 match(Set dst (MoveF2I src)); | |
| 10253 effect(DEF dst, USE src); | |
| 10254 ins_cost(85); | |
| 10255 format %{ "movd $dst,$src\t# MoveF2I" %} | |
| 4759 | 10256 ins_encode %{ |
| 10257 __ movdl($dst$$Register, $src$$XMMRegister); | |
| 10258 %} | |
| 0 | 10259 ins_pipe( pipe_slow ); |
| 10260 %} | |
| 10261 | |
| 10262 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{ | |
| 10263 match(Set dst (MoveD2L src)); | |
| 10264 effect(DEF dst, USE src); | |
| 10265 ins_cost(85); | |
| 10266 format %{ "movd $dst,$src\t# MoveD2L" %} | |
| 4759 | 10267 ins_encode %{ |
| 10268 __ movdq($dst$$Register, $src$$XMMRegister); | |
| 10269 %} | |
| 0 | 10270 ins_pipe( pipe_slow ); |
| 10271 %} | |
| 10272 | |
| 10273 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{ | |
| 10274 match(Set dst (MoveI2F src)); | |
| 10275 effect(DEF dst, USE src); | |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
10276 ins_cost(100); |
| 0 | 10277 format %{ "movd $dst,$src\t# MoveI2F" %} |
| 4759 | 10278 ins_encode %{ |
| 10279 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 10280 %} | |
| 0 | 10281 ins_pipe( pipe_slow ); |
| 10282 %} | |
| 10283 | |
| 10284 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{ | |
| 10285 match(Set dst (MoveL2D src)); | |
| 10286 effect(DEF dst, USE src); | |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
10287 ins_cost(100); |
| 0 | 10288 format %{ "movd $dst,$src\t# MoveL2D" %} |
| 4759 | 10289 ins_encode %{ |
| 10290 __ movdq($dst$$XMMRegister, $src$$Register); | |
| 10291 %} | |
| 0 | 10292 ins_pipe( pipe_slow ); |
| 10293 %} | |
| 10294 | |
| 10295 | |
| 10296 // ======================================================================= | |
| 10297 // fast clearing of an array | |
| 10298 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy, | |
| 10299 rFlagsReg cr) | |
| 10300 %{ | |
|
7474
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6849
diff
changeset
|
10301 predicate(!UseFastStosb); |
| 0 | 10302 match(Set dummy (ClearArray cnt base)); |
| 10303 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr); | |
| 10304 | |
|
7474
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6849
diff
changeset
|
10305 format %{ "xorq rax, rax\t# ClearArray:\n\t" |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6849
diff
changeset
|
10306 "rep stosq\t# Store rax to *rdi++ while rcx--" %} |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6849
diff
changeset
|
10307 ins_encode %{ |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6849
diff
changeset
|
10308 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register); |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6849
diff
changeset
|
10309 %} |
| 0 | 10310 ins_pipe(pipe_slow); |
| 10311 %} | |
| 10312 | |
|
7474
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6849
diff
changeset
|
10313 instruct rep_fast_stosb(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy, |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6849
diff
changeset
|
10314 rFlagsReg cr) |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6849
diff
changeset
|
10315 %{ |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6849
diff
changeset
|
10316 predicate(UseFastStosb); |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6849
diff
changeset
|
10317 match(Set dummy (ClearArray cnt base)); |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6849
diff
changeset
|
10318 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr); |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6849
diff
changeset
|
10319 format %{ "xorq rax, rax\t# ClearArray:\n\t" |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6849
diff
changeset
|
10320 "shlq rcx,3\t# Convert doublewords to bytes\n\t" |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6849
diff
changeset
|
10321 "rep stosb\t# Store rax to *rdi++ while rcx--" %} |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6849
diff
changeset
|
10322 ins_encode %{ |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6849
diff
changeset
|
10323 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register); |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6849
diff
changeset
|
10324 %} |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6849
diff
changeset
|
10325 ins_pipe( pipe_slow ); |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6849
diff
changeset
|
10326 %} |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6849
diff
changeset
|
10327 |
| 2262 | 10328 instruct string_compare(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2, |
| 10329 rax_RegI result, regD tmp1, rFlagsReg cr) | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10330 %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10331 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); |
| 2262 | 10332 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr); |
| 10333 | |
| 10334 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %} | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10335 ins_encode %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10336 __ string_compare($str1$$Register, $str2$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10337 $cnt1$$Register, $cnt2$$Register, $result$$Register, |
| 2262 | 10338 $tmp1$$XMMRegister); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10339 %} |
| 681 | 10340 ins_pipe( pipe_slow ); |
| 10341 %} | |
| 10342 | |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10343 // fast search of substring with known size. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10344 instruct string_indexof_con(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10345 rbx_RegI result, regD vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr) |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10346 %{ |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10347 predicate(UseSSE42Intrinsics); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10348 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2))); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10349 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10350 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10351 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %} |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10352 ins_encode %{ |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10353 int icnt2 = (int)$int_cnt2$$constant; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10354 if (icnt2 >= 8) { |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10355 // IndexOf for constant substrings with size >= 8 elements |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10356 // which don't need to be loaded through stack. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10357 __ string_indexofC8($str1$$Register, $str2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10358 $cnt1$$Register, $cnt2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10359 icnt2, $result$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10360 $vec$$XMMRegister, $tmp$$Register); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10361 } else { |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10362 // Small strings are loaded through stack if they cross page boundary. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10363 __ string_indexof($str1$$Register, $str2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10364 $cnt1$$Register, $cnt2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10365 icnt2, $result$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10366 $vec$$XMMRegister, $tmp$$Register); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10367 } |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10368 %} |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10369 ins_pipe( pipe_slow ); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10370 %} |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10371 |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10372 instruct string_indexof(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2, |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10373 rbx_RegI result, regD vec, rcx_RegI tmp, rFlagsReg cr) |
| 681 | 10374 %{ |
| 10375 predicate(UseSSE42Intrinsics); | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10376 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2))); |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10377 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10378 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10379 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %} |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10380 ins_encode %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10381 __ string_indexof($str1$$Register, $str2$$Register, |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10382 $cnt1$$Register, $cnt2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10383 (-1), $result$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10384 $vec$$XMMRegister, $tmp$$Register); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10385 %} |
| 681 | 10386 ins_pipe( pipe_slow ); |
| 10387 %} | |
| 10388 | |
| 10389 // fast string equals | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10390 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10391 regD tmp1, regD tmp2, rbx_RegI tmp3, rFlagsReg cr) |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10392 %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10393 match(Set result (StrEquals (Binary str1 str2) cnt)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10394 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10395 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10396 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10397 ins_encode %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10398 __ char_arrays_equals(false, $str1$$Register, $str2$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10399 $cnt$$Register, $result$$Register, $tmp3$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10400 $tmp1$$XMMRegister, $tmp2$$XMMRegister); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10401 %} |
| 0 | 10402 ins_pipe( pipe_slow ); |
| 10403 %} | |
| 10404 | |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
168
diff
changeset
|
10405 // fast array equals |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10406 instruct array_equals(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10407 regD tmp1, regD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr) |
| 681 | 10408 %{ |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
168
diff
changeset
|
10409 match(Set result (AryEq ary1 ary2)); |
| 681 | 10410 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr); |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
168
diff
changeset
|
10411 //ins_cost(300); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
168
diff
changeset
|
10412 |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10413 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10414 ins_encode %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10415 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10416 $tmp3$$Register, $result$$Register, $tmp4$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10417 $tmp1$$XMMRegister, $tmp2$$XMMRegister); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10418 %} |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
168
diff
changeset
|
10419 ins_pipe( pipe_slow ); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
168
diff
changeset
|
10420 %} |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
168
diff
changeset
|
10421 |
|
7637
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10422 // encode char[] to byte[] in ISO_8859_1 |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10423 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len, |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10424 regD tmp1, regD tmp2, regD tmp3, regD tmp4, |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10425 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{ |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10426 match(Set result (EncodeISOArray src (Binary dst len))); |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10427 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr); |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10428 |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10429 format %{ "Encode array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %} |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10430 ins_encode %{ |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10431 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register, |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10432 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister, |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10433 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register); |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10434 %} |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10435 ins_pipe( pipe_slow ); |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10436 %} |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10437 |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10438 |
| 0 | 10439 //----------Control Flow Instructions------------------------------------------ |
| 10440 // Signed compare Instructions | |
| 10441 | |
| 10442 // XXX more variants!! | |
| 10443 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2) | |
| 10444 %{ | |
| 10445 match(Set cr (CmpI op1 op2)); | |
| 10446 effect(DEF cr, USE op1, USE op2); | |
| 10447 | |
| 10448 format %{ "cmpl $op1, $op2" %} | |
| 10449 opcode(0x3B); /* Opcode 3B /r */ | |
| 10450 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2)); | |
| 10451 ins_pipe(ialu_cr_reg_reg); | |
| 10452 %} | |
| 10453 | |
| 10454 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2) | |
| 10455 %{ | |
| 10456 match(Set cr (CmpI op1 op2)); | |
| 10457 | |
| 10458 format %{ "cmpl $op1, $op2" %} | |
| 10459 opcode(0x81, 0x07); /* Opcode 81 /7 */ | |
| 10460 ins_encode(OpcSErm(op1, op2), Con8or32(op2)); | |
| 10461 ins_pipe(ialu_cr_reg_imm); | |
| 10462 %} | |
| 10463 | |
| 10464 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2) | |
| 10465 %{ | |
| 10466 match(Set cr (CmpI op1 (LoadI op2))); | |
| 10467 | |
| 10468 ins_cost(500); // XXX | |
| 10469 format %{ "cmpl $op1, $op2" %} | |
| 10470 opcode(0x3B); /* Opcode 3B /r */ | |
| 10471 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 10472 ins_pipe(ialu_cr_reg_mem); | |
| 10473 %} | |
| 10474 | |
| 10475 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero) | |
| 10476 %{ | |
| 10477 match(Set cr (CmpI src zero)); | |
| 10478 | |
| 10479 format %{ "testl $src, $src" %} | |
| 10480 opcode(0x85); | |
| 10481 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src)); | |
| 10482 ins_pipe(ialu_cr_reg_imm); | |
| 10483 %} | |
| 10484 | |
| 10485 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero) | |
| 10486 %{ | |
| 10487 match(Set cr (CmpI (AndI src con) zero)); | |
| 10488 | |
| 10489 format %{ "testl $src, $con" %} | |
| 10490 opcode(0xF7, 0x00); | |
| 10491 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con)); | |
| 10492 ins_pipe(ialu_cr_reg_imm); | |
| 10493 %} | |
| 10494 | |
| 10495 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero) | |
| 10496 %{ | |
| 10497 match(Set cr (CmpI (AndI src (LoadI mem)) zero)); | |
| 10498 | |
| 10499 format %{ "testl $src, $mem" %} | |
| 10500 opcode(0x85); | |
| 10501 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
| 10502 ins_pipe(ialu_cr_reg_mem); | |
| 10503 %} | |
| 10504 | |
| 10505 // Unsigned compare Instructions; really, same as signed except they | |
| 10506 // produce an rFlagsRegU instead of rFlagsReg. | |
| 10507 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2) | |
| 10508 %{ | |
| 10509 match(Set cr (CmpU op1 op2)); | |
| 10510 | |
| 10511 format %{ "cmpl $op1, $op2\t# unsigned" %} | |
| 10512 opcode(0x3B); /* Opcode 3B /r */ | |
| 10513 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2)); | |
| 10514 ins_pipe(ialu_cr_reg_reg); | |
| 10515 %} | |
| 10516 | |
| 10517 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2) | |
| 10518 %{ | |
| 10519 match(Set cr (CmpU op1 op2)); | |
| 10520 | |
| 10521 format %{ "cmpl $op1, $op2\t# unsigned" %} | |
| 10522 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 10523 ins_encode(OpcSErm(op1, op2), Con8or32(op2)); | |
| 10524 ins_pipe(ialu_cr_reg_imm); | |
| 10525 %} | |
| 10526 | |
| 10527 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2) | |
| 10528 %{ | |
| 10529 match(Set cr (CmpU op1 (LoadI op2))); | |
| 10530 | |
| 10531 ins_cost(500); // XXX | |
| 10532 format %{ "cmpl $op1, $op2\t# unsigned" %} | |
| 10533 opcode(0x3B); /* Opcode 3B /r */ | |
| 10534 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 10535 ins_pipe(ialu_cr_reg_mem); | |
| 10536 %} | |
| 10537 | |
| 10538 // // // Cisc-spilled version of cmpU_rReg | |
| 10539 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2) | |
| 10540 // //%{ | |
| 10541 // // match(Set cr (CmpU (LoadI op1) op2)); | |
| 10542 // // | |
| 10543 // // format %{ "CMPu $op1,$op2" %} | |
| 10544 // // ins_cost(500); | |
| 10545 // // opcode(0x39); /* Opcode 39 /r */ | |
| 10546 // // ins_encode( OpcP, reg_mem( op1, op2) ); | |
| 10547 // //%} | |
| 10548 | |
| 10549 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero) | |
| 10550 %{ | |
| 10551 match(Set cr (CmpU src zero)); | |
| 10552 | |
| 10553 format %{ "testl $src, $src\t# unsigned" %} | |
| 10554 opcode(0x85); | |
| 10555 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src)); | |
| 10556 ins_pipe(ialu_cr_reg_imm); | |
| 10557 %} | |
| 10558 | |
| 10559 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2) | |
| 10560 %{ | |
| 10561 match(Set cr (CmpP op1 op2)); | |
| 10562 | |
| 10563 format %{ "cmpq $op1, $op2\t# ptr" %} | |
| 10564 opcode(0x3B); /* Opcode 3B /r */ | |
| 10565 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2)); | |
| 10566 ins_pipe(ialu_cr_reg_reg); | |
| 10567 %} | |
| 10568 | |
| 10569 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2) | |
| 10570 %{ | |
| 10571 match(Set cr (CmpP op1 (LoadP op2))); | |
| 10572 | |
| 10573 ins_cost(500); // XXX | |
| 10574 format %{ "cmpq $op1, $op2\t# ptr" %} | |
| 10575 opcode(0x3B); /* Opcode 3B /r */ | |
| 10576 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 10577 ins_pipe(ialu_cr_reg_mem); | |
| 10578 %} | |
| 10579 | |
| 10580 // // // Cisc-spilled version of cmpP_rReg | |
| 10581 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2) | |
| 10582 // //%{ | |
| 10583 // // match(Set cr (CmpP (LoadP op1) op2)); | |
| 10584 // // | |
| 10585 // // format %{ "CMPu $op1,$op2" %} | |
| 10586 // // ins_cost(500); | |
| 10587 // // opcode(0x39); /* Opcode 39 /r */ | |
| 10588 // // ins_encode( OpcP, reg_mem( op1, op2) ); | |
| 10589 // //%} | |
| 10590 | |
| 10591 // XXX this is generalized by compP_rReg_mem??? | |
| 10592 // Compare raw pointer (used in out-of-heap check). | |
| 10593 // Only works because non-oop pointers must be raw pointers | |
| 10594 // and raw pointers have no anti-dependencies. | |
| 10595 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2) | |
| 10596 %{ | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
10597 predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none); |
| 0 | 10598 match(Set cr (CmpP op1 (LoadP op2))); |
| 10599 | |
| 10600 format %{ "cmpq $op1, $op2\t# raw ptr" %} | |
| 10601 opcode(0x3B); /* Opcode 3B /r */ | |
| 10602 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 10603 ins_pipe(ialu_cr_reg_mem); | |
| 10604 %} | |
| 10605 | |
| 10606 // This will generate a signed flags result. This should be OK since | |
| 10607 // any compare to a zero should be eq/neq. | |
| 10608 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero) | |
| 10609 %{ | |
| 10610 match(Set cr (CmpP src zero)); | |
| 10611 | |
| 10612 format %{ "testq $src, $src\t# ptr" %} | |
| 10613 opcode(0x85); | |
| 10614 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src)); | |
| 10615 ins_pipe(ialu_cr_reg_imm); | |
| 10616 %} | |
| 10617 | |
| 10618 // This will generate a signed flags result. This should be OK since | |
| 10619 // any compare to a zero should be eq/neq. | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10620 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10621 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10622 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL)); |
| 0 | 10623 match(Set cr (CmpP (LoadP op) zero)); |
| 10624 | |
| 10625 ins_cost(500); // XXX | |
| 10626 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %} | |
| 10627 opcode(0xF7); /* Opcode F7 /0 */ | |
| 10628 ins_encode(REX_mem_wide(op), | |
| 10629 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF)); | |
| 10630 ins_pipe(ialu_cr_reg_imm); | |
| 10631 %} | |
| 10632 | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10633 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10634 %{ |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
10635 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL)); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10636 match(Set cr (CmpP (LoadP mem) zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10637 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10638 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10639 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10640 __ cmpq(r12, $mem$$Address); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10641 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10642 ins_pipe(ialu_cr_reg_mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10643 %} |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
10644 |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
10645 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2) |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
10646 %{ |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
10647 match(Set cr (CmpN op1 op2)); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
10648 |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
10649 format %{ "cmpl $op1, $op2\t# compressed ptr" %} |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10650 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %} |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
10651 ins_pipe(ialu_cr_reg_reg); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
10652 %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
10653 |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
10654 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem) |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
10655 %{ |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
10656 match(Set cr (CmpN src (LoadN mem))); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
10657 |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10658 format %{ "cmpl $src, $mem\t# compressed ptr" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10659 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10660 __ cmpl($src$$Register, $mem$$Address); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10661 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10662 ins_pipe(ialu_cr_reg_mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10663 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10664 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10665 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10666 match(Set cr (CmpN op1 op2)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10667 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10668 format %{ "cmpl $op1, $op2\t# compressed ptr" %} |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
10669 ins_encode %{ |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10670 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10671 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10672 ins_pipe(ialu_cr_reg_imm); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10673 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10674 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10675 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10676 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10677 match(Set cr (CmpN src (LoadN mem))); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10678 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10679 format %{ "cmpl $mem, $src\t# compressed ptr" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10680 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10681 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant); |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
10682 %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
10683 ins_pipe(ialu_cr_reg_mem); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
10684 %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
10685 |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
10686 instruct compN_rReg_imm_klass(rFlagsRegU cr, rRegN op1, immNKlass op2) %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
10687 match(Set cr (CmpN op1 op2)); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
10688 |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
10689 format %{ "cmpl $op1, $op2\t# compressed klass ptr" %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
10690 ins_encode %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
10691 __ cmp_narrow_klass($op1$$Register, (Klass*)$op2$$constant); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
10692 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
10693 ins_pipe(ialu_cr_reg_imm); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
10694 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
10695 |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
10696 instruct compN_mem_imm_klass(rFlagsRegU cr, memory mem, immNKlass src) |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
10697 %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
10698 match(Set cr (CmpN src (LoadNKlass mem))); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
10699 |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
10700 format %{ "cmpl $mem, $src\t# compressed klass ptr" %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
10701 ins_encode %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
10702 __ cmp_narrow_klass($mem$$Address, (Klass*)$src$$constant); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
10703 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
10704 ins_pipe(ialu_cr_reg_mem); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
10705 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
10706 |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
10707 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
10708 match(Set cr (CmpN src zero)); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
10709 |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
10710 format %{ "testl $src, $src\t# compressed ptr" %} |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
10711 ins_encode %{ __ testl($src$$Register, $src$$Register); %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
10712 ins_pipe(ialu_cr_reg_imm); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
10713 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
10714 |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10715 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10716 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10717 predicate(Universe::narrow_oop_base() != NULL); |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
10718 match(Set cr (CmpN (LoadN mem) zero)); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
10719 |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
10720 ins_cost(500); // XXX |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
10721 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
10722 ins_encode %{ |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10723 __ cmpl($mem$$Address, (int)0xFFFFFFFF); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10724 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10725 ins_pipe(ialu_cr_reg_mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10726 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10727 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10728 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10729 %{ |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
10730 predicate(Universe::narrow_oop_base() == NULL && (Universe::narrow_klass_base() == NULL)); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10731 match(Set cr (CmpN (LoadN mem) zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10732 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10733 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10734 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10735 __ cmpl(r12, $mem$$Address); |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
10736 %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
10737 ins_pipe(ialu_cr_reg_mem); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
10738 %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
10739 |
| 0 | 10740 // Yanked all unsigned pointer compare operations. |
| 10741 // Pointer compares are done with CmpP which is already unsigned. | |
| 10742 | |
| 10743 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2) | |
| 10744 %{ | |
| 10745 match(Set cr (CmpL op1 op2)); | |
| 10746 | |
| 10747 format %{ "cmpq $op1, $op2" %} | |
| 10748 opcode(0x3B); /* Opcode 3B /r */ | |
| 10749 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2)); | |
| 10750 ins_pipe(ialu_cr_reg_reg); | |
| 10751 %} | |
| 10752 | |
| 10753 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2) | |
| 10754 %{ | |
| 10755 match(Set cr (CmpL op1 op2)); | |
| 10756 | |
| 10757 format %{ "cmpq $op1, $op2" %} | |
| 10758 opcode(0x81, 0x07); /* Opcode 81 /7 */ | |
| 10759 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2)); | |
| 10760 ins_pipe(ialu_cr_reg_imm); | |
| 10761 %} | |
| 10762 | |
| 10763 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2) | |
| 10764 %{ | |
| 10765 match(Set cr (CmpL op1 (LoadL op2))); | |
| 10766 | |
| 10767 format %{ "cmpq $op1, $op2" %} | |
| 10768 opcode(0x3B); /* Opcode 3B /r */ | |
| 10769 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 10770 ins_pipe(ialu_cr_reg_mem); | |
| 10771 %} | |
| 10772 | |
| 10773 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero) | |
| 10774 %{ | |
| 10775 match(Set cr (CmpL src zero)); | |
| 10776 | |
| 10777 format %{ "testq $src, $src" %} | |
| 10778 opcode(0x85); | |
| 10779 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src)); | |
| 10780 ins_pipe(ialu_cr_reg_imm); | |
| 10781 %} | |
| 10782 | |
| 10783 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero) | |
| 10784 %{ | |
| 10785 match(Set cr (CmpL (AndL src con) zero)); | |
| 10786 | |
| 10787 format %{ "testq $src, $con\t# long" %} | |
| 10788 opcode(0xF7, 0x00); | |
| 10789 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con)); | |
| 10790 ins_pipe(ialu_cr_reg_imm); | |
| 10791 %} | |
| 10792 | |
| 10793 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero) | |
| 10794 %{ | |
| 10795 match(Set cr (CmpL (AndL src (LoadL mem)) zero)); | |
| 10796 | |
| 10797 format %{ "testq $src, $mem" %} | |
| 10798 opcode(0x85); | |
| 10799 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem)); | |
| 10800 ins_pipe(ialu_cr_reg_mem); | |
| 10801 %} | |
| 10802 | |
| 10803 // Manifest a CmpL result in an integer register. Very painful. | |
| 10804 // This is the test to avoid. | |
| 10805 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags) | |
| 10806 %{ | |
| 10807 match(Set dst (CmpL3 src1 src2)); | |
| 10808 effect(KILL flags); | |
| 10809 | |
| 10810 ins_cost(275); // XXX | |
| 10811 format %{ "cmpq $src1, $src2\t# CmpL3\n\t" | |
| 10812 "movl $dst, -1\n\t" | |
| 10813 "jl,s done\n\t" | |
| 10814 "setne $dst\n\t" | |
| 10815 "movzbl $dst, $dst\n\t" | |
| 10816 "done:" %} | |
| 10817 ins_encode(cmpl3_flag(src1, src2, dst)); | |
| 10818 ins_pipe(pipe_slow); | |
| 10819 %} | |
| 10820 | |
| 10821 //----------Max and Min-------------------------------------------------------- | |
| 10822 // Min Instructions | |
| 10823 | |
| 10824 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr) | |
| 10825 %{ | |
| 10826 effect(USE_DEF dst, USE src, USE cr); | |
| 10827 | |
| 10828 format %{ "cmovlgt $dst, $src\t# min" %} | |
| 10829 opcode(0x0F, 0x4F); | |
| 10830 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 10831 ins_pipe(pipe_cmov_reg); | |
| 10832 %} | |
| 10833 | |
| 10834 | |
| 10835 instruct minI_rReg(rRegI dst, rRegI src) | |
| 10836 %{ | |
| 10837 match(Set dst (MinI dst src)); | |
| 10838 | |
| 10839 ins_cost(200); | |
| 10840 expand %{ | |
| 10841 rFlagsReg cr; | |
| 10842 compI_rReg(cr, dst, src); | |
| 10843 cmovI_reg_g(dst, src, cr); | |
| 10844 %} | |
| 10845 %} | |
| 10846 | |
| 10847 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr) | |
| 10848 %{ | |
| 10849 effect(USE_DEF dst, USE src, USE cr); | |
| 10850 | |
| 10851 format %{ "cmovllt $dst, $src\t# max" %} | |
| 10852 opcode(0x0F, 0x4C); | |
| 10853 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 10854 ins_pipe(pipe_cmov_reg); | |
| 10855 %} | |
| 10856 | |
| 10857 | |
| 10858 instruct maxI_rReg(rRegI dst, rRegI src) | |
| 10859 %{ | |
| 10860 match(Set dst (MaxI dst src)); | |
| 10861 | |
| 10862 ins_cost(200); | |
| 10863 expand %{ | |
| 10864 rFlagsReg cr; | |
| 10865 compI_rReg(cr, dst, src); | |
| 10866 cmovI_reg_l(dst, src, cr); | |
| 10867 %} | |
| 10868 %} | |
| 10869 | |
| 10870 // ============================================================================ | |
| 10871 // Branch Instructions | |
| 10872 | |
| 10873 // Jump Direct - Label defines a relative address from JMP+1 | |
| 10874 instruct jmpDir(label labl) | |
| 10875 %{ | |
| 10876 match(Goto); | |
| 10877 effect(USE labl); | |
| 10878 | |
| 10879 ins_cost(300); | |
| 10880 format %{ "jmp $labl" %} | |
| 10881 size(5); | |
| 3851 | 10882 ins_encode %{ |
| 10883 Label* L = $labl$$label; | |
| 10884 __ jmp(*L, false); // Always long jump | |
| 10885 %} | |
| 0 | 10886 ins_pipe(pipe_jmp); |
| 10887 %} | |
| 10888 | |
| 10889 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 10890 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl) | |
| 10891 %{ | |
| 10892 match(If cop cr); | |
| 10893 effect(USE labl); | |
| 10894 | |
| 10895 ins_cost(300); | |
| 10896 format %{ "j$cop $labl" %} | |
| 10897 size(6); | |
| 3851 | 10898 ins_encode %{ |
| 10899 Label* L = $labl$$label; | |
| 10900 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 10901 %} | |
| 0 | 10902 ins_pipe(pipe_jcc); |
| 10903 %} | |
| 10904 | |
| 10905 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 10906 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl) | |
| 10907 %{ | |
| 10908 match(CountedLoopEnd cop cr); | |
| 10909 effect(USE labl); | |
| 10910 | |
| 10911 ins_cost(300); | |
| 10912 format %{ "j$cop $labl\t# loop end" %} | |
| 10913 size(6); | |
| 3851 | 10914 ins_encode %{ |
| 10915 Label* L = $labl$$label; | |
| 10916 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 10917 %} | |
| 0 | 10918 ins_pipe(pipe_jcc); |
| 10919 %} | |
| 10920 | |
| 10921 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10922 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
| 0 | 10923 match(CountedLoopEnd cop cmp); |
| 10924 effect(USE labl); | |
| 10925 | |
| 10926 ins_cost(300); | |
| 10927 format %{ "j$cop,u $labl\t# loop end" %} | |
| 10928 size(6); | |
| 3851 | 10929 ins_encode %{ |
| 10930 Label* L = $labl$$label; | |
| 10931 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 10932 %} | |
| 0 | 10933 ins_pipe(pipe_jcc); |
| 10934 %} | |
| 10935 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10936 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10937 match(CountedLoopEnd cop cmp); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10938 effect(USE labl); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10939 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10940 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10941 format %{ "j$cop,u $labl\t# loop end" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10942 size(6); |
| 3851 | 10943 ins_encode %{ |
| 10944 Label* L = $labl$$label; | |
| 10945 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 10946 %} | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10947 ins_pipe(pipe_jcc); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10948 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10949 |
| 0 | 10950 // Jump Direct Conditional - using unsigned comparison |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10951 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
| 0 | 10952 match(If cop cmp); |
| 10953 effect(USE labl); | |
| 10954 | |
| 10955 ins_cost(300); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10956 format %{ "j$cop,u $labl" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10957 size(6); |
| 3851 | 10958 ins_encode %{ |
| 10959 Label* L = $labl$$label; | |
| 10960 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 10961 %} | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10962 ins_pipe(pipe_jcc); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10963 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10964 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10965 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10966 match(If cop cmp); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10967 effect(USE labl); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10968 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10969 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10970 format %{ "j$cop,u $labl" %} |
| 0 | 10971 size(6); |
| 3851 | 10972 ins_encode %{ |
| 10973 Label* L = $labl$$label; | |
| 10974 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 10975 %} | |
| 0 | 10976 ins_pipe(pipe_jcc); |
| 10977 %} | |
| 10978 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10979 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10980 match(If cop cmp); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10981 effect(USE labl); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10982 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10983 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10984 format %{ $$template |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10985 if ($cop$$cmpcode == Assembler::notEqual) { |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10986 $$emit$$"jp,u $labl\n\t" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10987 $$emit$$"j$cop,u $labl" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10988 } else { |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10989 $$emit$$"jp,u done\n\t" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10990 $$emit$$"j$cop,u $labl\n\t" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10991 $$emit$$"done:" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10992 } |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10993 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10994 ins_encode %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10995 Label* l = $labl$$label; |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10996 if ($cop$$cmpcode == Assembler::notEqual) { |
| 3851 | 10997 __ jcc(Assembler::parity, *l, false); |
| 10998 __ jcc(Assembler::notEqual, *l, false); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10999 } else if ($cop$$cmpcode == Assembler::equal) { |
| 3851 | 11000 Label done; |
| 11001 __ jccb(Assembler::parity, done); | |
| 11002 __ jcc(Assembler::equal, *l, false); | |
| 11003 __ bind(done); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11004 } else { |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11005 ShouldNotReachHere(); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11006 } |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11007 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11008 ins_pipe(pipe_jcc); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11009 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11010 |
| 0 | 11011 // ============================================================================ |
| 11012 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary | |
| 11013 // superklass array for an instance of the superklass. Set a hidden | |
| 11014 // internal cache on a hit (cache is checked with exposed code in | |
| 11015 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The | |
| 11016 // encoding ALSO sets flags. | |
| 11017 | |
| 11018 instruct partialSubtypeCheck(rdi_RegP result, | |
| 11019 rsi_RegP sub, rax_RegP super, rcx_RegI rcx, | |
| 11020 rFlagsReg cr) | |
| 11021 %{ | |
| 11022 match(Set result (PartialSubtypeCheck sub super)); | |
| 11023 effect(KILL rcx, KILL cr); | |
| 11024 | |
| 11025 ins_cost(1100); // slightly larger than the next version | |
|
4762
069ab3f976d3
7118863: Move sizeof(klassOopDesc) into the *Klass::*_offset_in_bytes() functions
stefank
parents:
4761
diff
changeset
|
11026 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t" |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
11027 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t" |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
11028 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t" |
| 0 | 11029 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t" |
| 11030 "jne,s miss\t\t# Missed: rdi not-zero\n\t" | |
|
4762
069ab3f976d3
7118863: Move sizeof(klassOopDesc) into the *Klass::*_offset_in_bytes() functions
stefank
parents:
4761
diff
changeset
|
11031 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t" |
| 0 | 11032 "xorq $result, $result\t\t Hit: rdi zero\n\t" |
| 11033 "miss:\t" %} | |
| 11034 | |
| 11035 opcode(0x1); // Force a XOR of RDI | |
| 11036 ins_encode(enc_PartialSubtypeCheck()); | |
| 11037 ins_pipe(pipe_slow); | |
| 11038 %} | |
| 11039 | |
| 11040 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr, | |
| 11041 rsi_RegP sub, rax_RegP super, rcx_RegI rcx, | |
| 11042 immP0 zero, | |
| 11043 rdi_RegP result) | |
| 11044 %{ | |
| 11045 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero)); | |
| 11046 effect(KILL rcx, KILL result); | |
| 11047 | |
| 11048 ins_cost(1000); | |
|
4762
069ab3f976d3
7118863: Move sizeof(klassOopDesc) into the *Klass::*_offset_in_bytes() functions
stefank
parents:
4761
diff
changeset
|
11049 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t" |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
11050 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t" |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
11051 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t" |
| 0 | 11052 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t" |
| 11053 "jne,s miss\t\t# Missed: flags nz\n\t" | |
|
4762
069ab3f976d3
7118863: Move sizeof(klassOopDesc) into the *Klass::*_offset_in_bytes() functions
stefank
parents:
4761
diff
changeset
|
11054 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t" |
| 0 | 11055 "miss:\t" %} |
| 11056 | |
| 11057 opcode(0x0); // No need to XOR RDI | |
| 11058 ins_encode(enc_PartialSubtypeCheck()); | |
| 11059 ins_pipe(pipe_slow); | |
| 11060 %} | |
| 11061 | |
| 11062 // ============================================================================ | |
| 11063 // Branch Instructions -- short offset versions | |
| 11064 // | |
| 11065 // These instructions are used to replace jumps of a long offset (the default | |
| 11066 // match) with jumps of a shorter offset. These instructions are all tagged | |
| 11067 // with the ins_short_branch attribute, which causes the ADLC to suppress the | |
| 11068 // match rules in general matching. Instead, the ADLC generates a conversion | |
| 11069 // method in the MachNode which can be used to do in-place replacement of the | |
| 11070 // long variant with the shorter variant. The compiler will determine if a | |
| 11071 // branch can be taken by the is_short_branch_offset() predicate in the machine | |
| 11072 // specific code section of the file. | |
| 11073 | |
| 11074 // Jump Direct - Label defines a relative address from JMP+1 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11075 instruct jmpDir_short(label labl) %{ |
| 0 | 11076 match(Goto); |
| 11077 effect(USE labl); | |
| 11078 | |
| 11079 ins_cost(300); | |
| 11080 format %{ "jmp,s $labl" %} | |
| 11081 size(2); | |
| 3851 | 11082 ins_encode %{ |
| 11083 Label* L = $labl$$label; | |
| 11084 __ jmpb(*L); | |
| 11085 %} | |
| 0 | 11086 ins_pipe(pipe_jmp); |
| 11087 ins_short_branch(1); | |
| 11088 %} | |
| 11089 | |
| 11090 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11091 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{ |
| 0 | 11092 match(If cop cr); |
| 11093 effect(USE labl); | |
| 11094 | |
| 11095 ins_cost(300); | |
| 11096 format %{ "j$cop,s $labl" %} | |
| 11097 size(2); | |
| 3851 | 11098 ins_encode %{ |
| 11099 Label* L = $labl$$label; | |
| 11100 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11101 %} | |
| 0 | 11102 ins_pipe(pipe_jcc); |
| 11103 ins_short_branch(1); | |
| 11104 %} | |
| 11105 | |
| 11106 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11107 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{ |
| 0 | 11108 match(CountedLoopEnd cop cr); |
| 11109 effect(USE labl); | |
| 11110 | |
| 11111 ins_cost(300); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11112 format %{ "j$cop,s $labl\t# loop end" %} |
| 0 | 11113 size(2); |
| 3851 | 11114 ins_encode %{ |
| 11115 Label* L = $labl$$label; | |
| 11116 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11117 %} | |
| 0 | 11118 ins_pipe(pipe_jcc); |
| 11119 ins_short_branch(1); | |
| 11120 %} | |
| 11121 | |
| 11122 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11123 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11124 match(CountedLoopEnd cop cmp); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11125 effect(USE labl); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11126 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11127 ins_cost(300); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11128 format %{ "j$cop,us $labl\t# loop end" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11129 size(2); |
| 3851 | 11130 ins_encode %{ |
| 11131 Label* L = $labl$$label; | |
| 11132 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11133 %} | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11134 ins_pipe(pipe_jcc); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11135 ins_short_branch(1); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11136 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11137 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11138 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
| 0 | 11139 match(CountedLoopEnd cop cmp); |
| 11140 effect(USE labl); | |
| 11141 | |
| 11142 ins_cost(300); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11143 format %{ "j$cop,us $labl\t# loop end" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11144 size(2); |
| 3851 | 11145 ins_encode %{ |
| 11146 Label* L = $labl$$label; | |
| 11147 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11148 %} | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11149 ins_pipe(pipe_jcc); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11150 ins_short_branch(1); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11151 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11152 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11153 // Jump Direct Conditional - using unsigned comparison |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11154 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11155 match(If cop cmp); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11156 effect(USE labl); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11157 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11158 ins_cost(300); |
| 0 | 11159 format %{ "j$cop,us $labl" %} |
| 11160 size(2); | |
| 3851 | 11161 ins_encode %{ |
| 11162 Label* L = $labl$$label; | |
| 11163 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11164 %} | |
| 0 | 11165 ins_pipe(pipe_jcc); |
| 11166 ins_short_branch(1); | |
| 11167 %} | |
| 11168 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11169 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
| 0 | 11170 match(If cop cmp); |
| 11171 effect(USE labl); | |
| 11172 | |
| 11173 ins_cost(300); | |
| 11174 format %{ "j$cop,us $labl" %} | |
| 11175 size(2); | |
| 3851 | 11176 ins_encode %{ |
| 11177 Label* L = $labl$$label; | |
| 11178 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11179 %} | |
| 0 | 11180 ins_pipe(pipe_jcc); |
| 11181 ins_short_branch(1); | |
| 11182 %} | |
| 11183 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11184 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11185 match(If cop cmp); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11186 effect(USE labl); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11187 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11188 ins_cost(300); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11189 format %{ $$template |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11190 if ($cop$$cmpcode == Assembler::notEqual) { |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11191 $$emit$$"jp,u,s $labl\n\t" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11192 $$emit$$"j$cop,u,s $labl" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11193 } else { |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11194 $$emit$$"jp,u,s done\n\t" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11195 $$emit$$"j$cop,u,s $labl\n\t" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11196 $$emit$$"done:" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11197 } |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11198 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11199 size(4); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11200 ins_encode %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11201 Label* l = $labl$$label; |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11202 if ($cop$$cmpcode == Assembler::notEqual) { |
| 3851 | 11203 __ jccb(Assembler::parity, *l); |
| 11204 __ jccb(Assembler::notEqual, *l); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11205 } else if ($cop$$cmpcode == Assembler::equal) { |
| 3851 | 11206 Label done; |
| 11207 __ jccb(Assembler::parity, done); | |
| 11208 __ jccb(Assembler::equal, *l); | |
| 11209 __ bind(done); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11210 } else { |
| 3851 | 11211 ShouldNotReachHere(); |
| 11212 } | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11213 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11214 ins_pipe(pipe_jcc); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11215 ins_short_branch(1); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11216 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11217 |
| 0 | 11218 // ============================================================================ |
| 11219 // inlined locking and unlocking | |
| 11220 | |
|
17714
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
kvn
parents:
17506
diff
changeset
|
11221 instruct cmpFastLock(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr) %{ |
| 0 | 11222 match(Set cr (FastLock object box)); |
| 4777 | 11223 effect(TEMP tmp, TEMP scr, USE_KILL box); |
| 0 | 11224 ins_cost(300); |
| 4777 | 11225 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %} |
|
17714
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
kvn
parents:
17506
diff
changeset
|
11226 ins_encode %{ |
|
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
kvn
parents:
17506
diff
changeset
|
11227 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register, $scr$$Register, _counters); |
|
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
kvn
parents:
17506
diff
changeset
|
11228 %} |
| 0 | 11229 ins_pipe(pipe_slow); |
| 11230 %} | |
| 11231 | |
|
17714
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
kvn
parents:
17506
diff
changeset
|
11232 instruct cmpFastUnlock(rFlagsReg cr, rRegP object, rax_RegP box, rRegP tmp) %{ |
| 0 | 11233 match(Set cr (FastUnlock object box)); |
| 4777 | 11234 effect(TEMP tmp, USE_KILL box); |
| 0 | 11235 ins_cost(300); |
| 4777 | 11236 format %{ "fastunlock $object,$box\t! kills $box,$tmp" %} |
|
17714
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
kvn
parents:
17506
diff
changeset
|
11237 ins_encode %{ |
|
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
kvn
parents:
17506
diff
changeset
|
11238 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register); |
|
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
kvn
parents:
17506
diff
changeset
|
11239 %} |
| 0 | 11240 ins_pipe(pipe_slow); |
| 11241 %} | |
| 11242 | |
| 11243 | |
| 11244 // ============================================================================ | |
| 11245 // Safepoint Instructions | |
| 11246 instruct safePoint_poll(rFlagsReg cr) | |
| 11247 %{ | |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
11248 predicate(!Assembler::is_polling_page_far()); |
| 0 | 11249 match(SafePoint); |
| 11250 effect(KILL cr); | |
| 11251 | |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
11252 format %{ "testl rax, [rip + #offset_to_poll_page]\t" |
| 0 | 11253 "# Safepoint: poll for GC" %} |
| 11254 ins_cost(125); | |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
11255 ins_encode %{ |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
11256 AddressLiteral addr(os::get_polling_page(), relocInfo::poll_type); |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
11257 __ testl(rax, addr); |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
11258 %} |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
11259 ins_pipe(ialu_reg_mem); |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
11260 %} |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
11261 |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
11262 instruct safePoint_poll_far(rFlagsReg cr, rRegP poll) |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
11263 %{ |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
11264 predicate(Assembler::is_polling_page_far()); |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
11265 match(SafePoint poll); |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
11266 effect(KILL cr, USE poll); |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
11267 |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
11268 format %{ "testl rax, [$poll]\t" |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
11269 "# Safepoint: poll for GC" %} |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
11270 ins_cost(125); |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
11271 ins_encode %{ |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
11272 __ relocate(relocInfo::poll_type); |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
11273 __ testl(rax, Address($poll$$Register, 0)); |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
11274 %} |
| 0 | 11275 ins_pipe(ialu_reg_mem); |
| 11276 %} | |
| 11277 | |
| 11278 // ============================================================================ | |
| 11279 // Procedure Call/Return Instructions | |
| 11280 // Call Java Static Instruction | |
| 11281 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 11282 // compute_padding() functions will have to be adjusted. | |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
11283 instruct CallStaticJavaDirect(method meth) %{ |
| 0 | 11284 match(CallStaticJava); |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
11285 predicate(!((CallStaticJavaNode*) n)->is_method_handle_invoke()); |
| 0 | 11286 effect(USE meth); |
| 11287 | |
| 11288 ins_cost(300); | |
| 11289 format %{ "call,static " %} | |
| 11290 opcode(0xE8); /* E8 cd */ | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
11291 ins_encode(clear_avx, Java_Static_Call(meth), call_epilog); |
| 0 | 11292 ins_pipe(pipe_slow); |
| 11293 ins_alignment(4); | |
| 11294 %} | |
| 11295 | |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
11296 // Call Java Static Instruction (method handle version) |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
11297 // Note: If this code changes, the corresponding ret_addr_offset() and |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
11298 // compute_padding() functions will have to be adjusted. |
| 1567 | 11299 instruct CallStaticJavaHandle(method meth, rbp_RegP rbp_mh_SP_save) %{ |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
11300 match(CallStaticJava); |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
11301 predicate(((CallStaticJavaNode*) n)->is_method_handle_invoke()); |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
11302 effect(USE meth); |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
11303 // RBP is saved by all callees (for interpreter stack correction). |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
11304 // We use it here for a similar purpose, in {preserve,restore}_SP. |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
11305 |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
11306 ins_cost(300); |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
11307 format %{ "call,static/MethodHandle " %} |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
11308 opcode(0xE8); /* E8 cd */ |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
11309 ins_encode(clear_avx, preserve_SP, |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
11310 Java_Static_Call(meth), |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
11311 restore_SP, |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
11312 call_epilog); |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
11313 ins_pipe(pipe_slow); |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
11314 ins_alignment(4); |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
11315 %} |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
11316 |
| 0 | 11317 // Call Java Dynamic Instruction |
| 11318 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 11319 // compute_padding() functions will have to be adjusted. | |
| 11320 instruct CallDynamicJavaDirect(method meth) | |
| 11321 %{ | |
| 11322 match(CallDynamicJava); | |
| 11323 effect(USE meth); | |
| 11324 | |
| 11325 ins_cost(300); | |
| 11326 format %{ "movq rax, #Universe::non_oop_word()\n\t" | |
| 11327 "call,dynamic " %} | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
11328 ins_encode(clear_avx, Java_Dynamic_Call(meth), call_epilog); |
| 0 | 11329 ins_pipe(pipe_slow); |
| 11330 ins_alignment(4); | |
| 11331 %} | |
| 11332 | |
| 11333 // Call Runtime Instruction | |
| 11334 instruct CallRuntimeDirect(method meth) | |
| 11335 %{ | |
| 11336 match(CallRuntime); | |
| 11337 effect(USE meth); | |
| 11338 | |
| 11339 ins_cost(300); | |
| 11340 format %{ "call,runtime " %} | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
11341 ins_encode(clear_avx, Java_To_Runtime(meth)); |
| 0 | 11342 ins_pipe(pipe_slow); |
| 11343 %} | |
| 11344 | |
| 11345 // Call runtime without safepoint | |
| 11346 instruct CallLeafDirect(method meth) | |
| 11347 %{ | |
| 11348 match(CallLeaf); | |
| 11349 effect(USE meth); | |
| 11350 | |
| 11351 ins_cost(300); | |
| 11352 format %{ "call_leaf,runtime " %} | |
|
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
7637
diff
changeset
|
11353 ins_encode(clear_avx, Java_To_Runtime(meth)); |
| 0 | 11354 ins_pipe(pipe_slow); |
| 11355 %} | |
| 11356 | |
| 11357 // Call runtime without safepoint | |
| 11358 instruct CallLeafNoFPDirect(method meth) | |
| 11359 %{ | |
| 11360 match(CallLeafNoFP); | |
| 11361 effect(USE meth); | |
| 11362 | |
| 11363 ins_cost(300); | |
| 11364 format %{ "call_leaf_nofp,runtime " %} | |
| 11365 ins_encode(Java_To_Runtime(meth)); | |
| 11366 ins_pipe(pipe_slow); | |
| 11367 %} | |
| 11368 | |
| 11369 // Return Instruction | |
| 11370 // Remove the return address & jump to it. | |
| 11371 // Notice: We always emit a nop after a ret to make sure there is room | |
| 11372 // for safepoint patching | |
| 11373 instruct Ret() | |
| 11374 %{ | |
| 11375 match(Return); | |
| 11376 | |
| 11377 format %{ "ret" %} | |
| 11378 opcode(0xC3); | |
| 11379 ins_encode(OpcP); | |
| 11380 ins_pipe(pipe_jmp); | |
| 11381 %} | |
| 11382 | |
| 11383 // Tail Call; Jump from runtime stub to Java code. | |
| 11384 // Also known as an 'interprocedural jump'. | |
| 11385 // Target of jump will eventually return to caller. | |
| 11386 // TailJump below removes the return address. | |
| 11387 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop) | |
| 11388 %{ | |
| 11389 match(TailCall jump_target method_oop); | |
| 11390 | |
| 11391 ins_cost(300); | |
| 11392 format %{ "jmp $jump_target\t# rbx holds method oop" %} | |
| 11393 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 11394 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target)); | |
| 11395 ins_pipe(pipe_jmp); | |
| 11396 %} | |
| 11397 | |
| 11398 // Tail Jump; remove the return address; jump to target. | |
| 11399 // TailCall above leaves the return address around. | |
| 11400 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop) | |
| 11401 %{ | |
| 11402 match(TailJump jump_target ex_oop); | |
| 11403 | |
| 11404 ins_cost(300); | |
| 11405 format %{ "popq rdx\t# pop return address\n\t" | |
| 11406 "jmp $jump_target" %} | |
| 11407 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 11408 ins_encode(Opcode(0x5a), // popq rdx | |
| 11409 REX_reg(jump_target), OpcP, reg_opc(jump_target)); | |
| 11410 ins_pipe(pipe_jmp); | |
| 11411 %} | |
| 11412 | |
| 11413 // Create exception oop: created by stack-crawling runtime code. | |
| 11414 // Created exception is now available to this handler, and is setup | |
| 11415 // just prior to jumping to this handler. No code emitted. | |
| 11416 instruct CreateException(rax_RegP ex_oop) | |
| 11417 %{ | |
| 11418 match(Set ex_oop (CreateEx)); | |
| 11419 | |
| 11420 size(0); | |
| 11421 // use the following format syntax | |
| 11422 format %{ "# exception oop is in rax; no code emitted" %} | |
| 11423 ins_encode(); | |
| 11424 ins_pipe(empty); | |
| 11425 %} | |
| 11426 | |
| 11427 // Rethrow exception: | |
| 11428 // The exception oop will come in the first argument position. | |
| 11429 // Then JUMP (not call) to the rethrow stub code. | |
| 11430 instruct RethrowException() | |
| 11431 %{ | |
| 11432 match(Rethrow); | |
| 11433 | |
| 11434 // use the following format syntax | |
| 11435 format %{ "jmp rethrow_stub" %} | |
| 11436 ins_encode(enc_rethrow); | |
| 11437 ins_pipe(pipe_jmp); | |
| 11438 %} | |
| 11439 | |
| 11440 | |
| 4950 | 11441 // ============================================================================ |
| 11442 // This name is KNOWN by the ADLC and cannot be changed. | |
| 11443 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type | |
| 11444 // for this guy. | |
| 11445 instruct tlsLoadP(r15_RegP dst) %{ | |
| 11446 match(Set dst (ThreadLocal)); | |
| 11447 effect(DEF dst); | |
| 11448 | |
| 11449 size(0); | |
| 11450 format %{ "# TLS is in R15" %} | |
| 11451 ins_encode( /*empty encoding*/ ); | |
| 11452 ins_pipe(ialu_reg_reg); | |
| 11453 %} | |
| 11454 | |
| 11455 | |
| 0 | 11456 //----------PEEPHOLE RULES----------------------------------------------------- |
| 11457 // These must follow all instruction definitions as they use the names | |
| 11458 // defined in the instructions definitions. | |
| 11459 // | |
| 605 | 11460 // peepmatch ( root_instr_name [preceding_instruction]* ); |
| 0 | 11461 // |
| 11462 // peepconstraint %{ | |
| 11463 // (instruction_number.operand_name relational_op instruction_number.operand_name | |
| 11464 // [, ...] ); | |
| 11465 // // instruction numbers are zero-based using left to right order in peepmatch | |
| 11466 // | |
| 11467 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); | |
| 11468 // // provide an instruction_number.operand_name for each operand that appears | |
| 11469 // // in the replacement instruction's match rule | |
| 11470 // | |
| 11471 // ---------VM FLAGS--------------------------------------------------------- | |
| 11472 // | |
| 11473 // All peephole optimizations can be turned off using -XX:-OptoPeephole | |
| 11474 // | |
| 11475 // Each peephole rule is given an identifying number starting with zero and | |
| 11476 // increasing by one in the order seen by the parser. An individual peephole | |
| 11477 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# | |
| 11478 // on the command-line. | |
| 11479 // | |
| 11480 // ---------CURRENT LIMITATIONS---------------------------------------------- | |
| 11481 // | |
| 11482 // Only match adjacent instructions in same basic block | |
| 11483 // Only equality constraints | |
| 11484 // Only constraints between operands, not (0.dest_reg == RAX_enc) | |
| 11485 // Only one replacement instruction | |
| 11486 // | |
| 11487 // ---------EXAMPLE---------------------------------------------------------- | |
| 11488 // | |
| 11489 // // pertinent parts of existing instructions in architecture description | |
| 11490 // instruct movI(rRegI dst, rRegI src) | |
| 11491 // %{ | |
| 11492 // match(Set dst (CopyI src)); | |
| 11493 // %} | |
| 11494 // | |
| 11495 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr) | |
| 11496 // %{ | |
| 11497 // match(Set dst (AddI dst src)); | |
| 11498 // effect(KILL cr); | |
| 11499 // %} | |
| 11500 // | |
| 11501 // // Change (inc mov) to lea | |
| 11502 // peephole %{ | |
| 11503 // // increment preceeded by register-register move | |
| 11504 // peepmatch ( incI_rReg movI ); | |
| 11505 // // require that the destination register of the increment | |
| 11506 // // match the destination register of the move | |
| 11507 // peepconstraint ( 0.dst == 1.dst ); | |
| 11508 // // construct a replacement instruction that sets | |
| 11509 // // the destination to ( move's source register + one ) | |
| 11510 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) ); | |
| 11511 // %} | |
| 11512 // | |
| 11513 | |
| 11514 // Implementation no longer uses movX instructions since | |
| 11515 // machine-independent system no longer uses CopyX nodes. | |
| 11516 // | |
| 11517 // peephole | |
| 11518 // %{ | |
| 11519 // peepmatch (incI_rReg movI); | |
| 11520 // peepconstraint (0.dst == 1.dst); | |
| 11521 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src)); | |
| 11522 // %} | |
| 11523 | |
| 11524 // peephole | |
| 11525 // %{ | |
| 11526 // peepmatch (decI_rReg movI); | |
| 11527 // peepconstraint (0.dst == 1.dst); | |
| 11528 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src)); | |
| 11529 // %} | |
| 11530 | |
| 11531 // peephole | |
| 11532 // %{ | |
| 11533 // peepmatch (addI_rReg_imm movI); | |
| 11534 // peepconstraint (0.dst == 1.dst); | |
| 11535 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src)); | |
| 11536 // %} | |
| 11537 | |
| 11538 // peephole | |
| 11539 // %{ | |
| 11540 // peepmatch (incL_rReg movL); | |
| 11541 // peepconstraint (0.dst == 1.dst); | |
| 11542 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src)); | |
| 11543 // %} | |
| 11544 | |
| 11545 // peephole | |
| 11546 // %{ | |
| 11547 // peepmatch (decL_rReg movL); | |
| 11548 // peepconstraint (0.dst == 1.dst); | |
| 11549 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src)); | |
| 11550 // %} | |
| 11551 | |
| 11552 // peephole | |
| 11553 // %{ | |
| 11554 // peepmatch (addL_rReg_imm movL); | |
| 11555 // peepconstraint (0.dst == 1.dst); | |
| 11556 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src)); | |
| 11557 // %} | |
| 11558 | |
| 11559 // peephole | |
| 11560 // %{ | |
| 11561 // peepmatch (addP_rReg_imm movP); | |
| 11562 // peepconstraint (0.dst == 1.dst); | |
| 11563 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src)); | |
| 11564 // %} | |
| 11565 | |
| 11566 // // Change load of spilled value to only a spill | |
| 11567 // instruct storeI(memory mem, rRegI src) | |
| 11568 // %{ | |
| 11569 // match(Set mem (StoreI mem src)); | |
| 11570 // %} | |
| 11571 // | |
| 11572 // instruct loadI(rRegI dst, memory mem) | |
| 11573 // %{ | |
| 11574 // match(Set dst (LoadI mem)); | |
| 11575 // %} | |
| 11576 // | |
| 11577 | |
| 11578 peephole | |
| 11579 %{ | |
| 11580 peepmatch (loadI storeI); | |
| 11581 peepconstraint (1.src == 0.dst, 1.mem == 0.mem); | |
| 11582 peepreplace (storeI(1.mem 1.mem 1.src)); | |
| 11583 %} | |
| 11584 | |
| 11585 peephole | |
| 11586 %{ | |
| 11587 peepmatch (loadL storeL); | |
| 11588 peepconstraint (1.src == 0.dst, 1.mem == 0.mem); | |
| 11589 peepreplace (storeL(1.mem 1.mem 1.src)); | |
| 11590 %} | |
| 11591 | |
| 11592 //----------SMARTSPILL RULES--------------------------------------------------- | |
| 11593 // These must follow all instruction definitions as they use the names | |
| 11594 // defined in the instructions definitions. |