Mercurial > hg > truffle
annotate src/cpu/x86/vm/x86_64.ad @ 9154:886d1fd67dc3
6443505: Ideal() function for CmpLTMask
Summary: Repair wrong code generation, added new matching rule
Reviewed-by: kvn, twisti
| author | drchase |
|---|---|
| date | Fri, 12 Apr 2013 19:14:47 -0700 |
| parents | 8be1318fbe77 |
| children | 35c15dad89ea e10e43e58e92 |
| rev | line source |
|---|---|
| 0 | 1 // |
| 9154 | 2 // Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 // | |
| 5 // This code is free software; you can redistribute it and/or modify it | |
| 6 // under the terms of the GNU General Public License version 2 only, as | |
| 7 // published by the Free Software Foundation. | |
| 8 // | |
| 9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 // version 2 for more details (a copy is included in the LICENSE file that | |
| 13 // accompanied this code). | |
| 14 // | |
| 15 // You should have received a copy of the GNU General Public License version | |
| 16 // 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 // | |
|
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19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 // or visit www.oracle.com if you need additional information or have any |
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21 // questions. |
| 0 | 22 // |
| 23 // | |
| 24 | |
| 25 // AMD64 Architecture Description File | |
| 26 | |
| 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ | |
| 28 // This information is used by the matcher and the register allocator to | |
| 29 // describe individual registers and classes of registers within the target | |
| 30 // archtecture. | |
| 31 | |
| 32 register %{ | |
| 33 //----------Architecture Description Register Definitions---------------------- | |
| 34 // General Registers | |
| 35 // "reg_def" name ( register save type, C convention save type, | |
| 36 // ideal register type, encoding ); | |
| 37 // Register Save Types: | |
| 38 // | |
| 39 // NS = No-Save: The register allocator assumes that these registers | |
| 40 // can be used without saving upon entry to the method, & | |
| 41 // that they do not need to be saved at call sites. | |
| 42 // | |
| 43 // SOC = Save-On-Call: The register allocator assumes that these registers | |
| 44 // can be used without saving upon entry to the method, | |
| 45 // but that they must be saved at call sites. | |
| 46 // | |
| 47 // SOE = Save-On-Entry: The register allocator assumes that these registers | |
| 48 // must be saved before using them upon entry to the | |
| 49 // method, but they do not need to be saved at call | |
| 50 // sites. | |
| 51 // | |
| 52 // AS = Always-Save: The register allocator assumes that these registers | |
| 53 // must be saved before using them upon entry to the | |
| 54 // method, & that they must be saved at call sites. | |
| 55 // | |
| 56 // Ideal Register Type is used to determine how to save & restore a | |
| 57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get | |
| 58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. | |
| 59 // | |
| 60 // The encoding number is the actual bit-pattern placed into the opcodes. | |
| 61 | |
| 62 // General Registers | |
| 63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when | |
| 64 // used as byte registers) | |
| 65 | |
| 66 // Previously set RBX, RSI, and RDI as save-on-entry for java code | |
| 67 // Turn off SOE in java-code due to frequent use of uncommon-traps. | |
| 68 // Now that allocator is better, turn on RSI and RDI as SOE registers. | |
| 69 | |
| 70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg()); | |
| 71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next()); | |
| 72 | |
| 73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg()); | |
| 74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next()); | |
| 75 | |
| 76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg()); | |
| 77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next()); | |
| 78 | |
| 79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg()); | |
| 80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next()); | |
| 81 | |
| 82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg()); | |
| 83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next()); | |
| 84 | |
| 85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code | |
| 86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg()); | |
| 87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next()); | |
| 88 | |
| 89 #ifdef _WIN64 | |
| 90 | |
| 91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg()); | |
| 92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next()); | |
| 93 | |
| 94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg()); | |
| 95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next()); | |
| 96 | |
| 97 #else | |
| 98 | |
| 99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg()); | |
| 100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next()); | |
| 101 | |
| 102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg()); | |
| 103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next()); | |
| 104 | |
| 105 #endif | |
| 106 | |
| 107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg()); | |
| 108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next()); | |
| 109 | |
| 110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg()); | |
| 111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next()); | |
| 112 | |
| 113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg()); | |
| 114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next()); | |
| 115 | |
| 116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg()); | |
| 117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next()); | |
| 118 | |
| 119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg()); | |
| 120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next()); | |
| 121 | |
| 122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg()); | |
| 123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next()); | |
| 124 | |
| 125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg()); | |
| 126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next()); | |
| 127 | |
| 128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg()); | |
| 129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next()); | |
| 130 | |
| 131 | |
| 132 // Floating Point Registers | |
| 133 | |
| 134 // Specify priority of register selection within phases of register | |
| 135 // allocation. Highest priority is first. A useful heuristic is to | |
| 136 // give registers a low priority when they are required by machine | |
| 137 // instructions, like EAX and EDX on I486, and choose no-save registers | |
| 138 // before save-on-call, & save-on-call before save-on-entry. Registers | |
| 139 // which participate in fixed calling sequences should come last. | |
| 140 // Registers which are used as pairs must fall on an even boundary. | |
| 141 | |
| 142 alloc_class chunk0(R10, R10_H, | |
| 143 R11, R11_H, | |
| 144 R8, R8_H, | |
| 145 R9, R9_H, | |
| 146 R12, R12_H, | |
| 147 RCX, RCX_H, | |
| 148 RBX, RBX_H, | |
| 149 RDI, RDI_H, | |
| 150 RDX, RDX_H, | |
| 151 RSI, RSI_H, | |
| 152 RAX, RAX_H, | |
| 153 RBP, RBP_H, | |
| 154 R13, R13_H, | |
| 155 R14, R14_H, | |
| 156 R15, R15_H, | |
| 157 RSP, RSP_H); | |
| 158 | |
| 159 | |
| 160 //----------Architecture Description Register Classes-------------------------- | |
| 161 // Several register classes are automatically defined based upon information in | |
| 162 // this architecture description. | |
| 163 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ ) | |
| 164 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ ) | |
| 165 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ ) | |
| 166 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) | |
| 167 // | |
| 168 | |
| 169 // Class for all pointer registers (including RSP) | |
| 170 reg_class any_reg(RAX, RAX_H, | |
| 171 RDX, RDX_H, | |
| 172 RBP, RBP_H, | |
| 173 RDI, RDI_H, | |
| 174 RSI, RSI_H, | |
| 175 RCX, RCX_H, | |
| 176 RBX, RBX_H, | |
| 177 RSP, RSP_H, | |
| 178 R8, R8_H, | |
| 179 R9, R9_H, | |
| 180 R10, R10_H, | |
| 181 R11, R11_H, | |
| 182 R12, R12_H, | |
| 183 R13, R13_H, | |
| 184 R14, R14_H, | |
| 185 R15, R15_H); | |
| 186 | |
| 187 // Class for all pointer registers except RSP | |
| 188 reg_class ptr_reg(RAX, RAX_H, | |
| 189 RDX, RDX_H, | |
| 190 RBP, RBP_H, | |
| 191 RDI, RDI_H, | |
| 192 RSI, RSI_H, | |
| 193 RCX, RCX_H, | |
| 194 RBX, RBX_H, | |
| 195 R8, R8_H, | |
| 196 R9, R9_H, | |
| 197 R10, R10_H, | |
| 198 R11, R11_H, | |
| 199 R13, R13_H, | |
| 200 R14, R14_H); | |
| 201 | |
| 202 // Class for all pointer registers except RAX and RSP | |
| 203 reg_class ptr_no_rax_reg(RDX, RDX_H, | |
| 204 RBP, RBP_H, | |
| 205 RDI, RDI_H, | |
| 206 RSI, RSI_H, | |
| 207 RCX, RCX_H, | |
| 208 RBX, RBX_H, | |
| 209 R8, R8_H, | |
| 210 R9, R9_H, | |
| 211 R10, R10_H, | |
| 212 R11, R11_H, | |
| 213 R13, R13_H, | |
| 214 R14, R14_H); | |
| 215 | |
| 216 reg_class ptr_no_rbp_reg(RDX, RDX_H, | |
| 217 RAX, RAX_H, | |
| 218 RDI, RDI_H, | |
| 219 RSI, RSI_H, | |
| 220 RCX, RCX_H, | |
| 221 RBX, RBX_H, | |
| 222 R8, R8_H, | |
| 223 R9, R9_H, | |
| 224 R10, R10_H, | |
| 225 R11, R11_H, | |
| 226 R13, R13_H, | |
| 227 R14, R14_H); | |
| 228 | |
| 229 // Class for all pointer registers except RAX, RBX and RSP | |
| 230 reg_class ptr_no_rax_rbx_reg(RDX, RDX_H, | |
| 231 RBP, RBP_H, | |
| 232 RDI, RDI_H, | |
| 233 RSI, RSI_H, | |
| 234 RCX, RCX_H, | |
| 235 R8, R8_H, | |
| 236 R9, R9_H, | |
| 237 R10, R10_H, | |
| 238 R11, R11_H, | |
| 239 R13, R13_H, | |
| 240 R14, R14_H); | |
| 241 | |
| 242 // Singleton class for RAX pointer register | |
| 243 reg_class ptr_rax_reg(RAX, RAX_H); | |
| 244 | |
| 245 // Singleton class for RBX pointer register | |
| 246 reg_class ptr_rbx_reg(RBX, RBX_H); | |
| 247 | |
| 248 // Singleton class for RSI pointer register | |
| 249 reg_class ptr_rsi_reg(RSI, RSI_H); | |
| 250 | |
| 251 // Singleton class for RDI pointer register | |
| 252 reg_class ptr_rdi_reg(RDI, RDI_H); | |
| 253 | |
| 254 // Singleton class for RBP pointer register | |
| 255 reg_class ptr_rbp_reg(RBP, RBP_H); | |
| 256 | |
| 257 // Singleton class for stack pointer | |
| 258 reg_class ptr_rsp_reg(RSP, RSP_H); | |
| 259 | |
| 260 // Singleton class for TLS pointer | |
| 261 reg_class ptr_r15_reg(R15, R15_H); | |
| 262 | |
| 263 // Class for all long registers (except RSP) | |
| 264 reg_class long_reg(RAX, RAX_H, | |
| 265 RDX, RDX_H, | |
| 266 RBP, RBP_H, | |
| 267 RDI, RDI_H, | |
| 268 RSI, RSI_H, | |
| 269 RCX, RCX_H, | |
| 270 RBX, RBX_H, | |
| 271 R8, R8_H, | |
| 272 R9, R9_H, | |
| 273 R10, R10_H, | |
| 274 R11, R11_H, | |
| 275 R13, R13_H, | |
| 276 R14, R14_H); | |
| 277 | |
| 278 // Class for all long registers except RAX, RDX (and RSP) | |
| 279 reg_class long_no_rax_rdx_reg(RBP, RBP_H, | |
| 280 RDI, RDI_H, | |
| 281 RSI, RSI_H, | |
| 282 RCX, RCX_H, | |
| 283 RBX, RBX_H, | |
| 284 R8, R8_H, | |
| 285 R9, R9_H, | |
| 286 R10, R10_H, | |
| 287 R11, R11_H, | |
| 288 R13, R13_H, | |
| 289 R14, R14_H); | |
| 290 | |
| 291 // Class for all long registers except RCX (and RSP) | |
| 292 reg_class long_no_rcx_reg(RBP, RBP_H, | |
| 293 RDI, RDI_H, | |
| 294 RSI, RSI_H, | |
| 295 RAX, RAX_H, | |
| 296 RDX, RDX_H, | |
| 297 RBX, RBX_H, | |
| 298 R8, R8_H, | |
| 299 R9, R9_H, | |
| 300 R10, R10_H, | |
| 301 R11, R11_H, | |
| 302 R13, R13_H, | |
| 303 R14, R14_H); | |
| 304 | |
| 305 // Class for all long registers except RAX (and RSP) | |
| 306 reg_class long_no_rax_reg(RBP, RBP_H, | |
| 307 RDX, RDX_H, | |
| 308 RDI, RDI_H, | |
| 309 RSI, RSI_H, | |
| 310 RCX, RCX_H, | |
| 311 RBX, RBX_H, | |
| 312 R8, R8_H, | |
| 313 R9, R9_H, | |
| 314 R10, R10_H, | |
| 315 R11, R11_H, | |
| 316 R13, R13_H, | |
| 317 R14, R14_H); | |
| 318 | |
| 319 // Singleton class for RAX long register | |
| 320 reg_class long_rax_reg(RAX, RAX_H); | |
| 321 | |
| 322 // Singleton class for RCX long register | |
| 323 reg_class long_rcx_reg(RCX, RCX_H); | |
| 324 | |
| 325 // Singleton class for RDX long register | |
| 326 reg_class long_rdx_reg(RDX, RDX_H); | |
| 327 | |
| 328 // Class for all int registers (except RSP) | |
| 329 reg_class int_reg(RAX, | |
| 330 RDX, | |
| 331 RBP, | |
| 332 RDI, | |
| 333 RSI, | |
| 334 RCX, | |
| 335 RBX, | |
| 336 R8, | |
| 337 R9, | |
| 338 R10, | |
| 339 R11, | |
| 340 R13, | |
| 341 R14); | |
| 342 | |
| 343 // Class for all int registers except RCX (and RSP) | |
| 344 reg_class int_no_rcx_reg(RAX, | |
| 345 RDX, | |
| 346 RBP, | |
| 347 RDI, | |
| 348 RSI, | |
| 349 RBX, | |
| 350 R8, | |
| 351 R9, | |
| 352 R10, | |
| 353 R11, | |
| 354 R13, | |
| 355 R14); | |
| 356 | |
| 357 // Class for all int registers except RAX, RDX (and RSP) | |
| 358 reg_class int_no_rax_rdx_reg(RBP, | |
| 304 | 359 RDI, |
| 0 | 360 RSI, |
| 361 RCX, | |
| 362 RBX, | |
| 363 R8, | |
| 364 R9, | |
| 365 R10, | |
| 366 R11, | |
| 367 R13, | |
| 368 R14); | |
| 369 | |
| 370 // Singleton class for RAX int register | |
| 371 reg_class int_rax_reg(RAX); | |
| 372 | |
| 373 // Singleton class for RBX int register | |
| 374 reg_class int_rbx_reg(RBX); | |
| 375 | |
| 376 // Singleton class for RCX int register | |
| 377 reg_class int_rcx_reg(RCX); | |
| 378 | |
| 379 // Singleton class for RCX int register | |
| 380 reg_class int_rdx_reg(RDX); | |
| 381 | |
| 382 // Singleton class for RCX int register | |
| 383 reg_class int_rdi_reg(RDI); | |
| 384 | |
| 385 // Singleton class for instruction pointer | |
| 386 // reg_class ip_reg(RIP); | |
| 387 | |
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388 %} |
| 0 | 389 |
| 390 //----------SOURCE BLOCK------------------------------------------------------- | |
| 391 // This is a block of C++ code which provides values, functions, and | |
| 392 // definitions necessary in the rest of the architecture description | |
| 393 source %{ | |
| 304 | 394 #define RELOC_IMM64 Assembler::imm_operand |
| 0 | 395 #define RELOC_DISP32 Assembler::disp32_operand |
| 396 | |
| 397 #define __ _masm. | |
| 398 | |
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399 static int preserve_SP_size() { |
| 4759 | 400 return 3; // rex.w, op, rm(reg/reg) |
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401 } |
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402 static int clear_avx_size() { |
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403 return (Compile::current()->max_vector_size() > 16) ? 3 : 0; // vzeroupper |
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404 } |
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405 |
| 0 | 406 // !!!!! Special hack to get all types of calls to specify the byte offset |
| 407 // from the start of the call to the point where the return address | |
| 408 // will point. | |
| 409 int MachCallStaticJavaNode::ret_addr_offset() | |
| 410 { | |
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411 int offset = 5; // 5 bytes from start of call to where return address points |
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412 offset += clear_avx_size(); |
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413 if (_method_handle_invoke) |
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414 offset += preserve_SP_size(); |
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415 return offset; |
| 0 | 416 } |
| 417 | |
| 418 int MachCallDynamicJavaNode::ret_addr_offset() | |
| 419 { | |
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420 int offset = 15; // 15 bytes from start of call to where return address points |
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421 offset += clear_avx_size(); |
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422 return offset; |
| 0 | 423 } |
| 424 | |
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425 int MachCallRuntimeNode::ret_addr_offset() { |
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426 int offset = 13; // movq r10,#addr; callq (r10) |
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427 offset += clear_avx_size(); |
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428 return offset; |
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429 } |
| 0 | 430 |
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431 // Indicate if the safepoint node needs the polling page as an input, |
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432 // it does if the polling page is more than disp32 away. |
| 0 | 433 bool SafePointNode::needs_polling_address_input() |
| 434 { | |
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435 return Assembler::is_polling_page_far(); |
| 0 | 436 } |
| 437 | |
| 438 // | |
| 439 // Compute padding required for nodes which need alignment | |
| 440 // | |
| 441 | |
| 442 // The address of the call instruction needs to be 4-byte aligned to | |
| 443 // ensure that it does not span a cache line so that it can be patched. | |
| 444 int CallStaticJavaDirectNode::compute_padding(int current_offset) const | |
| 445 { | |
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446 current_offset += clear_avx_size(); // skip vzeroupper |
| 0 | 447 current_offset += 1; // skip call opcode byte |
| 448 return round_to(current_offset, alignment_required()) - current_offset; | |
| 449 } | |
| 450 | |
| 451 // The address of the call instruction needs to be 4-byte aligned to | |
| 452 // ensure that it does not span a cache line so that it can be patched. | |
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453 int CallStaticJavaHandleNode::compute_padding(int current_offset) const |
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454 { |
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455 current_offset += preserve_SP_size(); // skip mov rbp, rsp |
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456 current_offset += clear_avx_size(); // skip vzeroupper |
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457 current_offset += 1; // skip call opcode byte |
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458 return round_to(current_offset, alignment_required()) - current_offset; |
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459 } |
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460 |
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461 // The address of the call instruction needs to be 4-byte aligned to |
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462 // ensure that it does not span a cache line so that it can be patched. |
| 0 | 463 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const |
| 464 { | |
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465 current_offset += clear_avx_size(); // skip vzeroupper |
| 0 | 466 current_offset += 11; // skip movq instruction + call opcode byte |
| 467 return round_to(current_offset, alignment_required()) - current_offset; | |
| 468 } | |
| 469 | |
| 470 // EMIT_RM() | |
| 1748 | 471 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) { |
| 0 | 472 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3); |
| 1748 | 473 cbuf.insts()->emit_int8(c); |
| 0 | 474 } |
| 475 | |
| 476 // EMIT_CC() | |
| 1748 | 477 void emit_cc(CodeBuffer &cbuf, int f1, int f2) { |
| 0 | 478 unsigned char c = (unsigned char) (f1 | f2); |
| 1748 | 479 cbuf.insts()->emit_int8(c); |
| 0 | 480 } |
| 481 | |
| 482 // EMIT_OPCODE() | |
| 1748 | 483 void emit_opcode(CodeBuffer &cbuf, int code) { |
| 484 cbuf.insts()->emit_int8((unsigned char) code); | |
| 0 | 485 } |
| 486 | |
| 487 // EMIT_OPCODE() w/ relocation information | |
| 488 void emit_opcode(CodeBuffer &cbuf, | |
| 489 int code, relocInfo::relocType reloc, int offset, int format) | |
| 490 { | |
| 1748 | 491 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format); |
| 0 | 492 emit_opcode(cbuf, code); |
| 493 } | |
| 494 | |
| 495 // EMIT_D8() | |
| 1748 | 496 void emit_d8(CodeBuffer &cbuf, int d8) { |
| 497 cbuf.insts()->emit_int8((unsigned char) d8); | |
| 0 | 498 } |
| 499 | |
| 500 // EMIT_D16() | |
| 1748 | 501 void emit_d16(CodeBuffer &cbuf, int d16) { |
| 502 cbuf.insts()->emit_int16(d16); | |
| 0 | 503 } |
| 504 | |
| 505 // EMIT_D32() | |
| 1748 | 506 void emit_d32(CodeBuffer &cbuf, int d32) { |
| 507 cbuf.insts()->emit_int32(d32); | |
| 0 | 508 } |
| 509 | |
| 510 // EMIT_D64() | |
| 1748 | 511 void emit_d64(CodeBuffer &cbuf, int64_t d64) { |
| 512 cbuf.insts()->emit_int64(d64); | |
| 0 | 513 } |
| 514 | |
| 515 // emit 32 bit value and construct relocation entry from relocInfo::relocType | |
| 516 void emit_d32_reloc(CodeBuffer& cbuf, | |
| 517 int d32, | |
| 518 relocInfo::relocType reloc, | |
| 519 int format) | |
| 520 { | |
| 521 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc"); | |
| 1748 | 522 cbuf.relocate(cbuf.insts_mark(), reloc, format); |
| 523 cbuf.insts()->emit_int32(d32); | |
| 0 | 524 } |
| 525 | |
| 526 // emit 32 bit value and construct relocation entry from RelocationHolder | |
| 1748 | 527 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) { |
| 0 | 528 #ifdef ASSERT |
| 529 if (rspec.reloc()->type() == relocInfo::oop_type && | |
| 530 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) { | |
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531 assert(Universe::heap()->is_in_reserved((address)(intptr_t)d32), "should be real oop"); |
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532 assert(oop((intptr_t)d32)->is_oop() && (ScavengeRootsInCode || !oop((intptr_t)d32)->is_scavengable()), "cannot embed scavengable oops in code"); |
| 0 | 533 } |
| 534 #endif | |
| 1748 | 535 cbuf.relocate(cbuf.insts_mark(), rspec, format); |
| 536 cbuf.insts()->emit_int32(d32); | |
| 0 | 537 } |
| 538 | |
| 539 void emit_d32_reloc(CodeBuffer& cbuf, address addr) { | |
| 1748 | 540 address next_ip = cbuf.insts_end() + 4; |
| 0 | 541 emit_d32_reloc(cbuf, (int) (addr - next_ip), |
| 542 external_word_Relocation::spec(addr), | |
| 543 RELOC_DISP32); | |
| 544 } | |
| 545 | |
| 546 | |
| 547 // emit 64 bit value and construct relocation entry from relocInfo::relocType | |
| 1748 | 548 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) { |
| 549 cbuf.relocate(cbuf.insts_mark(), reloc, format); | |
| 550 cbuf.insts()->emit_int64(d64); | |
| 0 | 551 } |
| 552 | |
| 553 // emit 64 bit value and construct relocation entry from RelocationHolder | |
| 1748 | 554 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) { |
| 0 | 555 #ifdef ASSERT |
| 556 if (rspec.reloc()->type() == relocInfo::oop_type && | |
| 557 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) { | |
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558 assert(Universe::heap()->is_in_reserved((address)d64), "should be real oop"); |
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559 assert(oop(d64)->is_oop() && (ScavengeRootsInCode || !oop(d64)->is_scavengable()), |
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560 "cannot embed scavengable oops in code"); |
| 0 | 561 } |
| 562 #endif | |
| 1748 | 563 cbuf.relocate(cbuf.insts_mark(), rspec, format); |
| 564 cbuf.insts()->emit_int64(d64); | |
| 0 | 565 } |
| 566 | |
| 567 // Access stack slot for load or store | |
| 568 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) | |
| 569 { | |
| 570 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src]) | |
| 571 if (-0x80 <= disp && disp < 0x80) { | |
| 572 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte | |
| 573 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte | |
| 574 emit_d8(cbuf, disp); // Displacement // R/M byte | |
| 575 } else { | |
| 576 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte | |
| 577 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte | |
| 578 emit_d32(cbuf, disp); // Displacement // R/M byte | |
| 579 } | |
| 580 } | |
| 581 | |
| 582 // rRegI ereg, memory mem) %{ // emit_reg_mem | |
| 583 void encode_RegMem(CodeBuffer &cbuf, | |
| 584 int reg, | |
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585 int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) |
| 0 | 586 { |
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587 assert(disp_reloc == relocInfo::none, "cannot have disp"); |
| 0 | 588 int regenc = reg & 7; |
| 589 int baseenc = base & 7; | |
| 590 int indexenc = index & 7; | |
| 591 | |
| 592 // There is no index & no scale, use form without SIB byte | |
| 593 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) { | |
| 594 // If no displacement, mode is 0x0; unless base is [RBP] or [R13] | |
| 595 if (disp == 0 && base != RBP_enc && base != R13_enc) { | |
| 596 emit_rm(cbuf, 0x0, regenc, baseenc); // * | |
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597 } else if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) { |
| 0 | 598 // If 8-bit displacement, mode 0x1 |
| 599 emit_rm(cbuf, 0x1, regenc, baseenc); // * | |
| 600 emit_d8(cbuf, disp); | |
| 601 } else { | |
| 602 // If 32-bit displacement | |
| 603 if (base == -1) { // Special flag for absolute address | |
| 604 emit_rm(cbuf, 0x0, regenc, 0x5); // * | |
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605 if (disp_reloc != relocInfo::none) { |
| 0 | 606 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32); |
| 607 } else { | |
| 608 emit_d32(cbuf, disp); | |
| 609 } | |
| 610 } else { | |
| 611 // Normal base + offset | |
| 612 emit_rm(cbuf, 0x2, regenc, baseenc); // * | |
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613 if (disp_reloc != relocInfo::none) { |
| 0 | 614 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32); |
| 615 } else { | |
| 616 emit_d32(cbuf, disp); | |
| 617 } | |
| 618 } | |
| 619 } | |
| 620 } else { | |
| 621 // Else, encode with the SIB byte | |
| 622 // If no displacement, mode is 0x0; unless base is [RBP] or [R13] | |
| 623 if (disp == 0 && base != RBP_enc && base != R13_enc) { | |
| 624 // If no displacement | |
| 625 emit_rm(cbuf, 0x0, regenc, 0x4); // * | |
| 626 emit_rm(cbuf, scale, indexenc, baseenc); | |
| 627 } else { | |
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628 if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) { |
| 0 | 629 // If 8-bit displacement, mode 0x1 |
| 630 emit_rm(cbuf, 0x1, regenc, 0x4); // * | |
| 631 emit_rm(cbuf, scale, indexenc, baseenc); | |
| 632 emit_d8(cbuf, disp); | |
| 633 } else { | |
| 634 // If 32-bit displacement | |
| 635 if (base == 0x04 ) { | |
| 636 emit_rm(cbuf, 0x2, regenc, 0x4); | |
| 637 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid??? | |
| 638 } else { | |
| 639 emit_rm(cbuf, 0x2, regenc, 0x4); | |
| 640 emit_rm(cbuf, scale, indexenc, baseenc); // * | |
| 641 } | |
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642 if (disp_reloc != relocInfo::none) { |
| 0 | 643 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32); |
| 644 } else { | |
| 645 emit_d32(cbuf, disp); | |
| 646 } | |
| 647 } | |
| 648 } | |
| 649 } | |
| 650 } | |
| 651 | |
| 3783 | 652 // This could be in MacroAssembler but it's fairly C2 specific |
| 653 void emit_cmpfp_fixup(MacroAssembler& _masm) { | |
| 654 Label exit; | |
| 655 __ jccb(Assembler::noParity, exit); | |
| 656 __ pushf(); | |
| 4759 | 657 // |
| 658 // comiss/ucomiss instructions set ZF,PF,CF flags and | |
| 659 // zero OF,AF,SF for NaN values. | |
| 660 // Fixup flags by zeroing ZF,PF so that compare of NaN | |
| 661 // values returns 'less than' result (CF is set). | |
| 662 // Leave the rest of flags unchanged. | |
| 663 // | |
| 664 // 7 6 5 4 3 2 1 0 | |
| 665 // |S|Z|r|A|r|P|r|C| (r - reserved bit) | |
| 666 // 0 0 1 0 1 0 1 1 (0x2B) | |
| 667 // | |
| 3783 | 668 __ andq(Address(rsp, 0), 0xffffff2b); |
| 669 __ popf(); | |
| 670 __ bind(exit); | |
| 4759 | 671 } |
| 672 | |
| 673 void emit_cmpfp3(MacroAssembler& _masm, Register dst) { | |
| 674 Label done; | |
| 675 __ movl(dst, -1); | |
| 676 __ jcc(Assembler::parity, done); | |
| 677 __ jcc(Assembler::below, done); | |
| 678 __ setb(Assembler::notEqual, dst); | |
| 679 __ movzbl(dst, dst); | |
| 680 __ bind(done); | |
| 3783 | 681 } |
| 682 | |
| 0 | 683 |
| 684 //============================================================================= | |
| 2008 | 685 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty; |
| 686 | |
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687 int Compile::ConstantTable::calculate_table_base_offset() const { |
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688 return 0; // absolute addressing, no offset |
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689 } |
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690 |
| 2008 | 691 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { |
| 692 // Empty encoding | |
| 693 } | |
| 694 | |
| 695 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const { | |
| 696 return 0; | |
| 697 } | |
| 698 | |
| 699 #ifndef PRODUCT | |
| 700 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { | |
| 701 st->print("# MachConstantBaseNode (empty encoding)"); | |
| 702 } | |
| 703 #endif | |
| 704 | |
| 705 | |
| 706 //============================================================================= | |
| 0 | 707 #ifndef PRODUCT |
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708 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const { |
| 0 | 709 Compile* C = ra_->C; |
| 710 | |
| 711 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 712 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
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713 // Remove wordSize for return addr which is already pushed. |
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714 framesize -= wordSize; |
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715 |
| 0 | 716 if (C->need_stack_bang(framesize)) { |
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717 framesize -= wordSize; |
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718 st->print("# stack bang"); |
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719 st->print("\n\t"); |
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720 st->print("pushq rbp\t# Save rbp"); |
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721 if (framesize) { |
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722 st->print("\n\t"); |
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723 st->print("subq rsp, #%d\t# Create frame",framesize); |
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724 } |
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725 } else { |
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726 st->print("subq rsp, #%d\t# Create frame",framesize); |
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727 st->print("\n\t"); |
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728 framesize -= wordSize; |
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729 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize); |
| 0 | 730 } |
| 731 | |
| 732 if (VerifyStackAtCalls) { | |
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733 st->print("\n\t"); |
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734 framesize -= wordSize; |
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735 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize); |
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736 #ifdef ASSERT |
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737 st->print("\n\t"); |
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738 st->print("# stack alignment check"); |
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739 #endif |
| 0 | 740 } |
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741 st->cr(); |
| 0 | 742 } |
| 743 #endif | |
| 744 | |
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745 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { |
| 0 | 746 Compile* C = ra_->C; |
|
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747 MacroAssembler _masm(&cbuf); |
| 0 | 748 |
| 749 int framesize = C->frame_slots() << LogBytesPerInt; | |
|
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750 |
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751 __ verified_entry(framesize, C->need_stack_bang(framesize), false); |
| 0 | 752 |
| 1748 | 753 C->set_frame_complete(cbuf.insts_size()); |
| 0 | 754 |
|
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755 if (C->has_mach_constant_base_node()) { |
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756 // NOTE: We set the table base offset here because users might be |
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757 // emitted before MachConstantBaseNode. |
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758 Compile::ConstantTable& constant_table = C->constant_table(); |
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759 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset()); |
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760 } |
| 0 | 761 } |
| 762 | |
| 763 uint MachPrologNode::size(PhaseRegAlloc* ra_) const | |
| 764 { | |
| 765 return MachNode::size(ra_); // too many variables; just compute it | |
| 766 // the hard way | |
| 767 } | |
| 768 | |
| 769 int MachPrologNode::reloc() const | |
| 770 { | |
| 771 return 0; // a large enough number | |
| 772 } | |
| 773 | |
| 774 //============================================================================= | |
| 775 #ifndef PRODUCT | |
| 776 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const | |
| 777 { | |
| 778 Compile* C = ra_->C; | |
|
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779 if (C->max_vector_size() > 16) { |
|
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780 st->print("vzeroupper"); |
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781 st->cr(); st->print("\t"); |
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782 } |
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783 |
| 0 | 784 int framesize = C->frame_slots() << LogBytesPerInt; |
| 785 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 786 // Remove word for return adr already pushed | |
| 787 // and RBP | |
| 788 framesize -= 2*wordSize; | |
| 789 | |
| 790 if (framesize) { | |
|
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791 st->print_cr("addq rsp, %d\t# Destroy frame", framesize); |
| 0 | 792 st->print("\t"); |
| 793 } | |
| 794 | |
|
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795 st->print_cr("popq rbp"); |
| 0 | 796 if (do_polling() && C->is_method_compilation()) { |
| 797 st->print("\t"); | |
|
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798 if (Assembler::is_polling_page_far()) { |
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799 st->print_cr("movq rscratch1, #polling_page_address\n\t" |
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800 "testl rax, [rscratch1]\t" |
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801 "# Safepoint: poll for GC"); |
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802 } else { |
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803 st->print_cr("testl rax, [rip + #offset_to_poll_page]\t" |
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804 "# Safepoint: poll for GC"); |
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805 } |
| 0 | 806 } |
| 807 } | |
| 808 #endif | |
| 809 | |
| 810 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const | |
| 811 { | |
| 812 Compile* C = ra_->C; | |
|
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813 if (C->max_vector_size() > 16) { |
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814 // Clear upper bits of YMM registers when current compiled code uses |
|
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815 // wide vectors to avoid AVX <-> SSE transition penalty during call. |
|
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816 MacroAssembler _masm(&cbuf); |
|
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|
817 __ vzeroupper(); |
|
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|
818 } |
|
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|
819 |
| 0 | 820 int framesize = C->frame_slots() << LogBytesPerInt; |
| 821 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 822 // Remove word for return adr already pushed | |
| 823 // and RBP | |
| 824 framesize -= 2*wordSize; | |
| 825 | |
| 826 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here | |
| 827 | |
| 828 if (framesize) { | |
| 829 emit_opcode(cbuf, Assembler::REX_W); | |
| 830 if (framesize < 0x80) { | |
| 831 emit_opcode(cbuf, 0x83); // addq rsp, #framesize | |
| 832 emit_rm(cbuf, 0x3, 0x00, RSP_enc); | |
| 833 emit_d8(cbuf, framesize); | |
| 834 } else { | |
| 835 emit_opcode(cbuf, 0x81); // addq rsp, #framesize | |
| 836 emit_rm(cbuf, 0x3, 0x00, RSP_enc); | |
| 837 emit_d32(cbuf, framesize); | |
| 838 } | |
| 839 } | |
| 840 | |
| 841 // popq rbp | |
| 842 emit_opcode(cbuf, 0x58 | RBP_enc); | |
| 843 | |
| 844 if (do_polling() && C->is_method_compilation()) { | |
|
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|
845 MacroAssembler _masm(&cbuf); |
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846 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type); |
|
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847 if (Assembler::is_polling_page_far()) { |
|
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|
848 __ lea(rscratch1, polling_page); |
|
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|
849 __ relocate(relocInfo::poll_return_type); |
|
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850 __ testl(rax, Address(rscratch1, 0)); |
|
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851 } else { |
|
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|
852 __ testl(rax, polling_page); |
|
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|
853 } |
| 0 | 854 } |
| 855 } | |
| 856 | |
| 857 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const | |
| 858 { | |
|
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|
859 return MachNode::size(ra_); // too many variables; just compute it |
|
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|
860 // the hard way |
| 0 | 861 } |
| 862 | |
| 863 int MachEpilogNode::reloc() const | |
| 864 { | |
| 865 return 2; // a large enough number | |
| 866 } | |
| 867 | |
| 868 const Pipeline* MachEpilogNode::pipeline() const | |
| 869 { | |
| 870 return MachNode::pipeline_class(); | |
| 871 } | |
| 872 | |
| 873 int MachEpilogNode::safepoint_offset() const | |
| 874 { | |
| 875 return 0; | |
| 876 } | |
| 877 | |
| 878 //============================================================================= | |
| 879 | |
| 880 enum RC { | |
| 881 rc_bad, | |
| 882 rc_int, | |
| 883 rc_float, | |
| 884 rc_stack | |
| 885 }; | |
| 886 | |
| 887 static enum RC rc_class(OptoReg::Name reg) | |
| 888 { | |
| 889 if( !OptoReg::is_valid(reg) ) return rc_bad; | |
| 890 | |
| 891 if (OptoReg::is_stack(reg)) return rc_stack; | |
| 892 | |
| 893 VMReg r = OptoReg::as_VMReg(reg); | |
| 894 | |
| 895 if (r->is_Register()) return rc_int; | |
| 896 | |
| 897 assert(r->is_XMMRegister(), "must be"); | |
| 898 return rc_float; | |
| 899 } | |
| 900 | |
|
6179
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7119644: Increase superword's vector size up to 256 bits
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|
901 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad. |
|
8c92982cbbc4
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|
902 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, |
|
8c92982cbbc4
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|
903 int src_hi, int dst_hi, uint ireg, outputStream* st); |
|
8c92982cbbc4
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kvn
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|
904 |
|
8c92982cbbc4
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changeset
|
905 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load, |
|
8c92982cbbc4
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|
906 int stack_offset, int reg, uint ireg, outputStream* st); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
907 |
|
8c92982cbbc4
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|
908 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset, |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
909 int dst_offset, uint ireg, outputStream* st) { |
|
8c92982cbbc4
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|
910 if (cbuf) { |
|
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changeset
|
911 MacroAssembler _masm(cbuf); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
912 switch (ireg) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
913 case Op_VecS: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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parents:
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changeset
|
914 __ movq(Address(rsp, -8), rax); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
915 __ movl(rax, Address(rsp, src_offset)); |
|
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changeset
|
916 __ movl(Address(rsp, dst_offset), rax); |
|
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|
917 __ movq(rax, Address(rsp, -8)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
918 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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changeset
|
919 case Op_VecD: |
|
8c92982cbbc4
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changeset
|
920 __ pushq(Address(rsp, src_offset)); |
|
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|
921 __ popq (Address(rsp, dst_offset)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
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changeset
|
922 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
923 case Op_VecX: |
|
8c92982cbbc4
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|
924 __ pushq(Address(rsp, src_offset)); |
|
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|
925 __ popq (Address(rsp, dst_offset)); |
|
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|
926 __ pushq(Address(rsp, src_offset+8)); |
|
8c92982cbbc4
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|
927 __ popq (Address(rsp, dst_offset+8)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
928 break; |
|
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7119644: Increase superword's vector size up to 256 bits
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|
929 case Op_VecY: |
|
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|
930 __ vmovdqu(Address(rsp, -32), xmm0); |
|
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|
931 __ vmovdqu(xmm0, Address(rsp, src_offset)); |
|
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|
932 __ vmovdqu(Address(rsp, dst_offset), xmm0); |
|
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|
933 __ vmovdqu(xmm0, Address(rsp, -32)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
934 break; |
|
8c92982cbbc4
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|
935 default: |
|
8c92982cbbc4
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|
936 ShouldNotReachHere(); |
|
8c92982cbbc4
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|
937 } |
|
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|
938 #ifndef PRODUCT |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
939 } else { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
940 switch (ireg) { |
|
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7119644: Increase superword's vector size up to 256 bits
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|
941 case Op_VecS: |
|
8c92982cbbc4
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|
942 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t" |
|
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|
943 "movl rax, [rsp + #%d]\n\t" |
|
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|
944 "movl [rsp + #%d], rax\n\t" |
|
8c92982cbbc4
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|
945 "movq rax, [rsp - #8]", |
|
8c92982cbbc4
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|
946 src_offset, dst_offset); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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changeset
|
947 break; |
|
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7119644: Increase superword's vector size up to 256 bits
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changeset
|
948 case Op_VecD: |
|
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|
949 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t" |
|
8c92982cbbc4
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|
950 "popq [rsp + #%d]", |
|
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|
951 src_offset, dst_offset); |
|
8c92982cbbc4
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changeset
|
952 break; |
|
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|
953 case Op_VecX: |
|
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|
954 st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t" |
|
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955 "popq [rsp + #%d]\n\t" |
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956 "pushq [rsp + #%d]\n\t" |
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957 "popq [rsp + #%d]", |
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958 src_offset, dst_offset, src_offset+8, dst_offset+8); |
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959 break; |
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960 case Op_VecY: |
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961 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t" |
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962 "vmovdqu xmm0, [rsp + #%d]\n\t" |
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963 "vmovdqu [rsp + #%d], xmm0\n\t" |
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964 "vmovdqu xmm0, [rsp - #32]", |
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965 src_offset, dst_offset); |
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966 break; |
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967 default: |
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968 ShouldNotReachHere(); |
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969 } |
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970 #endif |
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971 } |
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972 } |
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973 |
| 0 | 974 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf, |
| 975 PhaseRegAlloc* ra_, | |
| 976 bool do_size, | |
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977 outputStream* st) const { |
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978 assert(cbuf != NULL || st != NULL, "sanity"); |
| 0 | 979 // Get registers to move |
| 980 OptoReg::Name src_second = ra_->get_reg_second(in(1)); | |
| 981 OptoReg::Name src_first = ra_->get_reg_first(in(1)); | |
| 982 OptoReg::Name dst_second = ra_->get_reg_second(this); | |
| 983 OptoReg::Name dst_first = ra_->get_reg_first(this); | |
| 984 | |
| 985 enum RC src_second_rc = rc_class(src_second); | |
| 986 enum RC src_first_rc = rc_class(src_first); | |
| 987 enum RC dst_second_rc = rc_class(dst_second); | |
| 988 enum RC dst_first_rc = rc_class(dst_first); | |
| 989 | |
| 990 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), | |
| 991 "must move at least 1 register" ); | |
| 992 | |
| 993 if (src_first == dst_first && src_second == dst_second) { | |
| 994 // Self copy, no move | |
| 995 return 0; | |
|
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996 } |
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997 if (bottom_type()->isa_vect() != NULL) { |
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998 uint ireg = ideal_reg(); |
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999 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity"); |
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1000 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity"); |
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1001 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { |
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1002 // mem -> mem |
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1003 int src_offset = ra_->reg2offset(src_first); |
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1004 int dst_offset = ra_->reg2offset(dst_first); |
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1005 vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st); |
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1006 } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) { |
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1007 vec_mov_helper(cbuf, false, src_first, dst_first, src_second, dst_second, ireg, st); |
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1008 } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) { |
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1009 int stack_offset = ra_->reg2offset(dst_first); |
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1010 vec_spill_helper(cbuf, false, false, stack_offset, src_first, ireg, st); |
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1011 } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) { |
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1012 int stack_offset = ra_->reg2offset(src_first); |
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1013 vec_spill_helper(cbuf, false, true, stack_offset, dst_first, ireg, st); |
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1014 } else { |
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1015 ShouldNotReachHere(); |
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1016 } |
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1017 return 0; |
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1018 } |
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1019 if (src_first_rc == rc_stack) { |
| 0 | 1020 // mem -> |
| 1021 if (dst_first_rc == rc_stack) { | |
| 1022 // mem -> mem | |
| 1023 assert(src_second != dst_first, "overlap"); | |
| 1024 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1025 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1026 // 64-bit | |
| 1027 int src_offset = ra_->reg2offset(src_first); | |
| 1028 int dst_offset = ra_->reg2offset(dst_first); | |
| 1029 if (cbuf) { | |
|
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1030 MacroAssembler _masm(cbuf); |
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1031 __ pushq(Address(rsp, src_offset)); |
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1032 __ popq (Address(rsp, dst_offset)); |
| 0 | 1033 #ifndef PRODUCT |
|
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1034 } else { |
| 0 | 1035 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t" |
|
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1036 "popq [rsp + #%d]", |
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1037 src_offset, dst_offset); |
| 0 | 1038 #endif |
| 1039 } | |
| 1040 } else { | |
| 1041 // 32-bit | |
| 1042 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1043 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1044 // No pushl/popl, so: | |
| 1045 int src_offset = ra_->reg2offset(src_first); | |
| 1046 int dst_offset = ra_->reg2offset(dst_first); | |
| 1047 if (cbuf) { | |
|
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1048 MacroAssembler _masm(cbuf); |
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1049 __ movq(Address(rsp, -8), rax); |
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1050 __ movl(rax, Address(rsp, src_offset)); |
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1051 __ movl(Address(rsp, dst_offset), rax); |
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1052 __ movq(rax, Address(rsp, -8)); |
| 0 | 1053 #ifndef PRODUCT |
|
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1054 } else { |
| 0 | 1055 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t" |
|
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1056 "movl rax, [rsp + #%d]\n\t" |
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1057 "movl [rsp + #%d], rax\n\t" |
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1058 "movq rax, [rsp - #8]", |
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1059 src_offset, dst_offset); |
| 0 | 1060 #endif |
| 1061 } | |
| 1062 } | |
|
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1063 return 0; |
| 0 | 1064 } else if (dst_first_rc == rc_int) { |
| 1065 // mem -> gpr | |
| 1066 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1067 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1068 // 64-bit | |
| 1069 int offset = ra_->reg2offset(src_first); | |
| 1070 if (cbuf) { | |
|
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1071 MacroAssembler _masm(cbuf); |
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1072 __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset)); |
| 0 | 1073 #ifndef PRODUCT |
|
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1074 } else { |
| 0 | 1075 st->print("movq %s, [rsp + #%d]\t# spill", |
| 1076 Matcher::regName[dst_first], | |
| 1077 offset); | |
| 1078 #endif | |
| 1079 } | |
| 1080 } else { | |
| 1081 // 32-bit | |
| 1082 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1083 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1084 int offset = ra_->reg2offset(src_first); | |
| 1085 if (cbuf) { | |
|
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1086 MacroAssembler _masm(cbuf); |
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1087 __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset)); |
| 0 | 1088 #ifndef PRODUCT |
|
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1089 } else { |
| 0 | 1090 st->print("movl %s, [rsp + #%d]\t# spill", |
| 1091 Matcher::regName[dst_first], | |
| 1092 offset); | |
| 1093 #endif | |
| 1094 } | |
| 1095 } | |
|
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1096 return 0; |
| 0 | 1097 } else if (dst_first_rc == rc_float) { |
| 1098 // mem-> xmm | |
| 1099 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1100 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1101 // 64-bit | |
| 1102 int offset = ra_->reg2offset(src_first); | |
| 1103 if (cbuf) { | |
| 4759 | 1104 MacroAssembler _masm(cbuf); |
| 1105 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset)); | |
| 0 | 1106 #ifndef PRODUCT |
|
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1107 } else { |
| 0 | 1108 st->print("%s %s, [rsp + #%d]\t# spill", |
| 1109 UseXmmLoadAndClearUpper ? "movsd " : "movlpd", | |
| 1110 Matcher::regName[dst_first], | |
| 1111 offset); | |
| 1112 #endif | |
| 1113 } | |
| 1114 } else { | |
| 1115 // 32-bit | |
| 1116 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1117 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1118 int offset = ra_->reg2offset(src_first); | |
| 1119 if (cbuf) { | |
| 4759 | 1120 MacroAssembler _masm(cbuf); |
| 1121 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset)); | |
| 0 | 1122 #ifndef PRODUCT |
|
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1123 } else { |
| 0 | 1124 st->print("movss %s, [rsp + #%d]\t# spill", |
| 1125 Matcher::regName[dst_first], | |
| 1126 offset); | |
| 1127 #endif | |
| 1128 } | |
| 1129 } | |
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1130 return 0; |
| 0 | 1131 } |
| 1132 } else if (src_first_rc == rc_int) { | |
| 1133 // gpr -> | |
| 1134 if (dst_first_rc == rc_stack) { | |
| 1135 // gpr -> mem | |
| 1136 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1137 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1138 // 64-bit | |
| 1139 int offset = ra_->reg2offset(dst_first); | |
| 1140 if (cbuf) { | |
|
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1141 MacroAssembler _masm(cbuf); |
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1142 __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first])); |
| 0 | 1143 #ifndef PRODUCT |
|
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1144 } else { |
| 0 | 1145 st->print("movq [rsp + #%d], %s\t# spill", |
| 1146 offset, | |
| 1147 Matcher::regName[src_first]); | |
| 1148 #endif | |
| 1149 } | |
| 1150 } else { | |
| 1151 // 32-bit | |
| 1152 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1153 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1154 int offset = ra_->reg2offset(dst_first); | |
| 1155 if (cbuf) { | |
|
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1156 MacroAssembler _masm(cbuf); |
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1157 __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first])); |
| 0 | 1158 #ifndef PRODUCT |
|
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1159 } else { |
| 0 | 1160 st->print("movl [rsp + #%d], %s\t# spill", |
| 1161 offset, | |
| 1162 Matcher::regName[src_first]); | |
| 1163 #endif | |
| 1164 } | |
| 1165 } | |
|
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1166 return 0; |
| 0 | 1167 } else if (dst_first_rc == rc_int) { |
| 1168 // gpr -> gpr | |
| 1169 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1170 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1171 // 64-bit | |
| 1172 if (cbuf) { | |
|
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1173 MacroAssembler _masm(cbuf); |
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1174 __ movq(as_Register(Matcher::_regEncode[dst_first]), |
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1175 as_Register(Matcher::_regEncode[src_first])); |
| 0 | 1176 #ifndef PRODUCT |
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1177 } else { |
| 0 | 1178 st->print("movq %s, %s\t# spill", |
| 1179 Matcher::regName[dst_first], | |
| 1180 Matcher::regName[src_first]); | |
| 1181 #endif | |
| 1182 } | |
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1183 return 0; |
| 0 | 1184 } else { |
| 1185 // 32-bit | |
| 1186 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1187 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1188 if (cbuf) { | |
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1189 MacroAssembler _masm(cbuf); |
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1190 __ movl(as_Register(Matcher::_regEncode[dst_first]), |
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1191 as_Register(Matcher::_regEncode[src_first])); |
| 0 | 1192 #ifndef PRODUCT |
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1193 } else { |
| 0 | 1194 st->print("movl %s, %s\t# spill", |
| 1195 Matcher::regName[dst_first], | |
| 1196 Matcher::regName[src_first]); | |
| 1197 #endif | |
| 1198 } | |
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1199 return 0; |
| 0 | 1200 } |
| 1201 } else if (dst_first_rc == rc_float) { | |
| 1202 // gpr -> xmm | |
| 1203 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1204 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1205 // 64-bit | |
| 1206 if (cbuf) { | |
| 4759 | 1207 MacroAssembler _masm(cbuf); |
| 1208 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first])); | |
| 0 | 1209 #ifndef PRODUCT |
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1210 } else { |
| 0 | 1211 st->print("movdq %s, %s\t# spill", |
| 1212 Matcher::regName[dst_first], | |
| 1213 Matcher::regName[src_first]); | |
| 1214 #endif | |
| 1215 } | |
| 1216 } else { | |
| 1217 // 32-bit | |
| 1218 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1219 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1220 if (cbuf) { | |
| 4759 | 1221 MacroAssembler _masm(cbuf); |
| 1222 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first])); | |
| 0 | 1223 #ifndef PRODUCT |
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1224 } else { |
| 0 | 1225 st->print("movdl %s, %s\t# spill", |
| 1226 Matcher::regName[dst_first], | |
| 1227 Matcher::regName[src_first]); | |
| 1228 #endif | |
| 1229 } | |
| 1230 } | |
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1231 return 0; |
| 0 | 1232 } |
| 1233 } else if (src_first_rc == rc_float) { | |
| 1234 // xmm -> | |
| 1235 if (dst_first_rc == rc_stack) { | |
| 1236 // xmm -> mem | |
| 1237 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1238 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1239 // 64-bit | |
| 1240 int offset = ra_->reg2offset(dst_first); | |
| 1241 if (cbuf) { | |
| 4759 | 1242 MacroAssembler _masm(cbuf); |
| 1243 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first])); | |
| 0 | 1244 #ifndef PRODUCT |
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1245 } else { |
| 0 | 1246 st->print("movsd [rsp + #%d], %s\t# spill", |
| 1247 offset, | |
| 1248 Matcher::regName[src_first]); | |
| 1249 #endif | |
| 1250 } | |
| 1251 } else { | |
| 1252 // 32-bit | |
| 1253 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1254 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1255 int offset = ra_->reg2offset(dst_first); | |
| 1256 if (cbuf) { | |
| 4759 | 1257 MacroAssembler _masm(cbuf); |
| 1258 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first])); | |
| 0 | 1259 #ifndef PRODUCT |
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1260 } else { |
| 0 | 1261 st->print("movss [rsp + #%d], %s\t# spill", |
| 1262 offset, | |
| 1263 Matcher::regName[src_first]); | |
| 1264 #endif | |
| 1265 } | |
| 1266 } | |
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1267 return 0; |
| 0 | 1268 } else if (dst_first_rc == rc_int) { |
| 1269 // xmm -> gpr | |
| 1270 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1271 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1272 // 64-bit | |
| 1273 if (cbuf) { | |
| 4759 | 1274 MacroAssembler _masm(cbuf); |
| 1275 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first])); | |
| 0 | 1276 #ifndef PRODUCT |
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1277 } else { |
| 0 | 1278 st->print("movdq %s, %s\t# spill", |
| 1279 Matcher::regName[dst_first], | |
| 1280 Matcher::regName[src_first]); | |
| 1281 #endif | |
| 1282 } | |
| 1283 } else { | |
| 1284 // 32-bit | |
| 1285 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1286 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1287 if (cbuf) { | |
| 4759 | 1288 MacroAssembler _masm(cbuf); |
| 1289 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first])); | |
| 0 | 1290 #ifndef PRODUCT |
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1291 } else { |
| 0 | 1292 st->print("movdl %s, %s\t# spill", |
| 1293 Matcher::regName[dst_first], | |
| 1294 Matcher::regName[src_first]); | |
| 1295 #endif | |
| 1296 } | |
| 1297 } | |
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1298 return 0; |
| 0 | 1299 } else if (dst_first_rc == rc_float) { |
| 1300 // xmm -> xmm | |
| 1301 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1302 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1303 // 64-bit | |
| 1304 if (cbuf) { | |
| 4759 | 1305 MacroAssembler _masm(cbuf); |
| 1306 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first])); | |
| 0 | 1307 #ifndef PRODUCT |
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1308 } else { |
| 0 | 1309 st->print("%s %s, %s\t# spill", |
| 1310 UseXmmRegToRegMoveAll ? "movapd" : "movsd ", | |
| 1311 Matcher::regName[dst_first], | |
| 1312 Matcher::regName[src_first]); | |
| 1313 #endif | |
| 1314 } | |
| 1315 } else { | |
| 1316 // 32-bit | |
| 1317 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1318 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1319 if (cbuf) { | |
| 4759 | 1320 MacroAssembler _masm(cbuf); |
| 1321 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first])); | |
| 0 | 1322 #ifndef PRODUCT |
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1323 } else { |
| 0 | 1324 st->print("%s %s, %s\t# spill", |
| 1325 UseXmmRegToRegMoveAll ? "movaps" : "movss ", | |
| 1326 Matcher::regName[dst_first], | |
| 1327 Matcher::regName[src_first]); | |
| 1328 #endif | |
| 1329 } | |
| 1330 } | |
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1331 return 0; |
| 0 | 1332 } |
| 1333 } | |
| 1334 | |
| 1335 assert(0," foo "); | |
| 1336 Unimplemented(); | |
| 1337 return 0; | |
| 1338 } | |
| 1339 | |
| 1340 #ifndef PRODUCT | |
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1341 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const { |
| 0 | 1342 implementation(NULL, ra_, false, st); |
| 1343 } | |
| 1344 #endif | |
| 1345 | |
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1346 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { |
| 0 | 1347 implementation(&cbuf, ra_, false, NULL); |
| 1348 } | |
| 1349 | |
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1350 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { |
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1351 return MachNode::size(ra_); |
| 0 | 1352 } |
| 1353 | |
| 1354 //============================================================================= | |
| 1355 #ifndef PRODUCT | |
| 1356 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const | |
| 1357 { | |
| 1358 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1359 int reg = ra_->get_reg_first(this); | |
| 1360 st->print("leaq %s, [rsp + #%d]\t# box lock", | |
| 1361 Matcher::regName[reg], offset); | |
| 1362 } | |
| 1363 #endif | |
| 1364 | |
| 1365 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const | |
| 1366 { | |
| 1367 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1368 int reg = ra_->get_encode(this); | |
| 1369 if (offset >= 0x80) { | |
| 1370 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR); | |
| 1371 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1372 emit_rm(cbuf, 0x2, reg & 7, 0x04); | |
| 1373 emit_rm(cbuf, 0x0, 0x04, RSP_enc); | |
| 1374 emit_d32(cbuf, offset); | |
| 1375 } else { | |
| 1376 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR); | |
| 1377 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1378 emit_rm(cbuf, 0x1, reg & 7, 0x04); | |
| 1379 emit_rm(cbuf, 0x0, 0x04, RSP_enc); | |
| 1380 emit_d8(cbuf, offset); | |
| 1381 } | |
| 1382 } | |
| 1383 | |
| 1384 uint BoxLockNode::size(PhaseRegAlloc *ra_) const | |
| 1385 { | |
| 1386 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1387 return (offset < 0x80) ? 5 : 8; // REX | |
| 1388 } | |
| 1389 | |
| 1390 //============================================================================= | |
| 1391 | |
| 1392 // emit call stub, compiled java to interpreter | |
| 1393 void emit_java_to_interp(CodeBuffer& cbuf) | |
| 1394 { | |
| 1395 // Stub is fixed up when the corresponding call is converted from | |
| 1396 // calling compiled code to calling interpreted code. | |
| 1397 // movq rbx, 0 | |
| 1398 // jmp -5 # to self | |
| 1399 | |
| 1748 | 1400 address mark = cbuf.insts_mark(); // get mark within main instrs section |
| 1401 | |
| 1402 // Note that the code buffer's insts_mark is always relative to insts. | |
| 0 | 1403 // That's why we must use the macroassembler to generate a stub. |
| 1404 MacroAssembler _masm(&cbuf); | |
| 1405 | |
| 1406 address base = | |
| 1407 __ start_a_stub(Compile::MAX_stubs_size); | |
| 1408 if (base == NULL) return; // CodeBuffer::expand failed | |
| 1409 // static stub relocation stores the instruction address of the call | |
| 1410 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM64); | |
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1411 // static stub relocation also tags the Method* in the code-stream. |
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1412 __ mov_metadata(rbx, (Metadata*) NULL); // method is zapped till fixup time |
| 304 | 1413 // This is recognized as unresolved by relocs/nativeinst/ic code |
| 0 | 1414 __ jump(RuntimeAddress(__ pc())); |
| 1415 | |
| 1748 | 1416 // Update current stubs pointer and restore insts_end. |
| 0 | 1417 __ end_a_stub(); |
| 1418 } | |
| 1419 | |
| 1420 // size of call stub, compiled java to interpretor | |
| 1421 uint size_java_to_interp() | |
| 1422 { | |
| 1423 return 15; // movq (1+1+8); jmp (1+4) | |
| 1424 } | |
| 1425 | |
| 1426 // relocation entries for call stub, compiled java to interpretor | |
| 1427 uint reloc_java_to_interp() | |
| 1428 { | |
| 1429 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call | |
| 1430 } | |
| 1431 | |
| 1432 //============================================================================= | |
| 1433 #ifndef PRODUCT | |
| 1434 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const | |
| 1435 { | |
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1436 if (UseCompressedKlassPointers) { |
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1437 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass"); |
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1438 if (Universe::narrow_klass_shift() != 0) { |
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1439 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1"); |
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1440 } |
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1441 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check"); |
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1442 } else { |
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1443 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t" |
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1444 "# Inline cache check"); |
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1445 } |
| 0 | 1446 st->print_cr("\tjne SharedRuntime::_ic_miss_stub"); |
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1447 st->print_cr("\tnop\t# nops to align entry point"); |
| 0 | 1448 } |
| 1449 #endif | |
| 1450 | |
| 1451 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const | |
| 1452 { | |
| 1453 MacroAssembler masm(&cbuf); | |
| 1748 | 1454 uint insts_size = cbuf.insts_size(); |
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1455 if (UseCompressedKlassPointers) { |
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1456 masm.load_klass(rscratch1, j_rarg0); |
| 304 | 1457 masm.cmpptr(rax, rscratch1); |
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1458 } else { |
| 304 | 1459 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes())); |
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1460 } |
| 0 | 1461 |
| 1462 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub())); | |
| 1463 | |
| 1464 /* WARNING these NOPs are critical so that verified entry point is properly | |
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1465 4 bytes aligned for patching by NativeJump::patch_verified_entry() */ |
| 1748 | 1466 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3); |
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1467 if (OptoBreakpoint) { |
| 0 | 1468 // Leave space for int3 |
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1469 nops_cnt -= 1; |
| 0 | 1470 } |
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1471 nops_cnt &= 0x3; // Do not add nops if code is aligned. |
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1472 if (nops_cnt > 0) |
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1473 masm.nop(nops_cnt); |
| 0 | 1474 } |
| 1475 | |
| 1476 uint MachUEPNode::size(PhaseRegAlloc* ra_) const | |
| 1477 { | |
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1478 return MachNode::size(ra_); // too many variables; just compute it |
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1479 // the hard way |
| 0 | 1480 } |
| 1481 | |
| 1482 | |
| 1483 //============================================================================= | |
| 1484 uint size_exception_handler() | |
| 1485 { | |
| 1486 // NativeCall instruction size is the same as NativeJump. | |
| 1487 // Note that this value is also credited (in output.cpp) to | |
| 1488 // the size of the code section. | |
| 1489 return NativeJump::instruction_size; | |
| 1490 } | |
| 1491 | |
| 1492 // Emit exception handler code. | |
| 1493 int emit_exception_handler(CodeBuffer& cbuf) | |
| 1494 { | |
| 1495 | |
| 1748 | 1496 // Note that the code buffer's insts_mark is always relative to insts. |
| 0 | 1497 // That's why we must use the macroassembler to generate a handler. |
| 1498 MacroAssembler _masm(&cbuf); | |
| 1499 address base = | |
| 1500 __ start_a_stub(size_exception_handler()); | |
| 1501 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1502 int offset = __ offset(); | |
| 1748 | 1503 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point())); |
| 0 | 1504 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); |
| 1505 __ end_a_stub(); | |
| 1506 return offset; | |
| 1507 } | |
| 1508 | |
| 1509 uint size_deopt_handler() | |
| 1510 { | |
| 1511 // three 5 byte instructions | |
| 1512 return 15; | |
| 1513 } | |
| 1514 | |
| 1515 // Emit deopt handler code. | |
| 1516 int emit_deopt_handler(CodeBuffer& cbuf) | |
| 1517 { | |
| 1518 | |
| 1748 | 1519 // Note that the code buffer's insts_mark is always relative to insts. |
| 0 | 1520 // That's why we must use the macroassembler to generate a handler. |
| 1521 MacroAssembler _masm(&cbuf); | |
| 1522 address base = | |
| 1523 __ start_a_stub(size_deopt_handler()); | |
| 1524 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1525 int offset = __ offset(); | |
| 1526 address the_pc = (address) __ pc(); | |
| 1527 Label next; | |
| 1528 // push a "the_pc" on the stack without destroying any registers | |
| 1529 // as they all may be live. | |
| 1530 | |
| 1531 // push address of "next" | |
| 1532 __ call(next, relocInfo::none); // reloc none is fine since it is a disp32 | |
| 1533 __ bind(next); | |
| 1534 // adjust it so it matches "the_pc" | |
| 304 | 1535 __ subptr(Address(rsp, 0), __ offset() - offset); |
| 0 | 1536 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); |
| 1537 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); | |
| 1538 __ end_a_stub(); | |
| 1539 return offset; | |
| 1540 } | |
| 1541 | |
| 1542 int Matcher::regnum_to_fpu_offset(int regnum) | |
| 1543 { | |
| 1544 return regnum - 32; // The FP registers are in the second chunk | |
| 1545 } | |
| 1546 | |
| 1547 // This is UltraSparc specific, true just means we have fast l2f conversion | |
| 1548 const bool Matcher::convL2FSupported(void) { | |
| 1549 return true; | |
| 1550 } | |
| 1551 | |
| 1552 // Is this branch offset short enough that a short branch can be used? | |
| 1553 // | |
| 1554 // NOTE: If the platform does not provide any short branch variants, then | |
| 1555 // this method should return false for offset 0. | |
| 3851 | 1556 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { |
| 1557 // The passed offset is relative to address of the branch. | |
| 1558 // On 86 a branch displacement is calculated relative to address | |
| 1559 // of a next instruction. | |
| 1560 offset -= br_size; | |
| 1561 | |
|
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1562 // the short version of jmpConUCF2 contains multiple branches, |
|
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1563 // making the reach slightly less |
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|
1564 if (rule == jmpConUCF2_rule) |
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1565 return (-126 <= offset && offset <= 125); |
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1566 return (-128 <= offset && offset <= 127); |
| 0 | 1567 } |
| 1568 | |
| 1569 const bool Matcher::isSimpleConstant64(jlong value) { | |
| 1570 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. | |
| 1571 //return value == (int) value; // Cf. storeImmL and immL32. | |
| 1572 | |
| 1573 // Probably always true, even if a temp register is required. | |
| 1574 return true; | |
| 1575 } | |
| 1576 | |
| 1577 // The ecx parameter to rep stosq for the ClearArray node is in words. | |
| 1578 const bool Matcher::init_array_count_is_in_bytes = false; | |
| 1579 | |
| 1580 // Threshold size for cleararray. | |
| 1581 const int Matcher::init_array_short_size = 8 * BytesPerLong; | |
| 1582 | |
| 4047 | 1583 // No additional cost for CMOVL. |
| 1584 const int Matcher::long_cmove_cost() { return 0; } | |
| 1585 | |
| 1586 // No CMOVF/CMOVD with SSE2 | |
| 1587 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; } | |
| 1588 | |
| 0 | 1589 // Should the Matcher clone shifts on addressing modes, expecting them |
| 1590 // to be subsumed into complex addressing expressions or compute them | |
| 1591 // into registers? True for Intel but false for most RISCs | |
| 1592 const bool Matcher::clone_shift_expressions = true; | |
| 1593 | |
|
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1594 // Do we need to mask the count passed to shift instructions or does |
|
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|
1595 // the cpu only look at the lower 5/6 bits anyway? |
|
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|
1596 const bool Matcher::need_masked_shift_count = false; |
|
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|
1597 |
|
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|
1598 bool Matcher::narrow_oop_use_complex_address() { |
|
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|
1599 assert(UseCompressedOops, "only for compressed oops code"); |
|
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|
1600 return (LogMinObjAlignmentInBytes <= 3); |
|
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|
1601 } |
|
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|
1602 |
|
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|
1603 bool Matcher::narrow_klass_use_complex_address() { |
|
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|
1604 assert(UseCompressedKlassPointers, "only for compressed klass code"); |
|
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|
1605 return (LogKlassAlignmentInBytes <= 3); |
|
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|
1606 } |
|
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|
1607 |
| 0 | 1608 // Is it better to copy float constants, or load them directly from |
| 1609 // memory? Intel can load a float constant from a direct address, | |
| 1610 // requiring no extra registers. Most RISCs will have to materialize | |
| 1611 // an address into a register first, so they would do better to copy | |
| 1612 // the constant from stack. | |
| 1613 const bool Matcher::rematerialize_float_constants = true; // XXX | |
| 1614 | |
| 1615 // If CPU can load and store mis-aligned doubles directly then no | |
| 1616 // fixup is needed. Else we split the double into 2 integer pieces | |
| 1617 // and move it piece-by-piece. Only happens when passing doubles into | |
| 1618 // C code as the Java calling convention forces doubles to be aligned. | |
| 1619 const bool Matcher::misaligned_doubles_ok = true; | |
| 1620 | |
| 1621 // No-op on amd64 | |
| 1622 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {} | |
| 1623 | |
| 1624 // Advertise here if the CPU requires explicit rounding operations to | |
| 1625 // implement the UseStrictFP mode. | |
| 1626 const bool Matcher::strict_fp_requires_explicit_rounding = true; | |
| 1627 | |
|
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|
1628 // Are floats conerted to double when stored to stack during deoptimization? |
|
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|
1629 // On x64 it is stored without convertion so we can use normal access. |
|
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|
1630 bool Matcher::float_in_double() { return false; } |
|
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|
1631 |
| 0 | 1632 // Do ints take an entire long register or just half? |
| 1633 const bool Matcher::int_in_long = true; | |
| 1634 | |
| 1635 // Return whether or not this register is ever used as an argument. | |
| 1636 // This function is used on startup to build the trampoline stubs in | |
| 1637 // generateOptoStub. Registers not mentioned will be killed by the VM | |
| 1638 // call in the trampoline, and arguments in those registers not be | |
| 1639 // available to the callee. | |
| 1640 bool Matcher::can_be_java_arg(int reg) | |
| 1641 { | |
| 1642 return | |
|
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1643 reg == RDI_num || reg == RDI_H_num || |
|
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|
1644 reg == RSI_num || reg == RSI_H_num || |
|
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|
1645 reg == RDX_num || reg == RDX_H_num || |
|
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|
1646 reg == RCX_num || reg == RCX_H_num || |
|
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|
1647 reg == R8_num || reg == R8_H_num || |
|
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|
1648 reg == R9_num || reg == R9_H_num || |
|
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|
1649 reg == R12_num || reg == R12_H_num || |
|
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|
1650 reg == XMM0_num || reg == XMM0b_num || |
|
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|
1651 reg == XMM1_num || reg == XMM1b_num || |
|
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|
1652 reg == XMM2_num || reg == XMM2b_num || |
|
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|
1653 reg == XMM3_num || reg == XMM3b_num || |
|
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|
1654 reg == XMM4_num || reg == XMM4b_num || |
|
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|
1655 reg == XMM5_num || reg == XMM5b_num || |
|
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|
1656 reg == XMM6_num || reg == XMM6b_num || |
|
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|
1657 reg == XMM7_num || reg == XMM7b_num; |
| 0 | 1658 } |
| 1659 | |
| 1660 bool Matcher::is_spillable_arg(int reg) | |
| 1661 { | |
| 1662 return can_be_java_arg(reg); | |
| 1663 } | |
| 1664 | |
|
1914
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|
1665 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) { |
|
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|
1666 // In 64 bit mode a code which use multiply when |
|
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|
1667 // devisor is constant is faster than hardware |
|
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|
1668 // DIV instruction (it uses MulHiL). |
|
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|
1669 return false; |
|
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|
1670 } |
|
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|
1671 |
| 0 | 1672 // Register for DIVI projection of divmodI |
| 1673 RegMask Matcher::divI_proj_mask() { | |
|
4121
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|
1674 return INT_RAX_REG_mask(); |
| 0 | 1675 } |
| 1676 | |
| 1677 // Register for MODI projection of divmodI | |
| 1678 RegMask Matcher::modI_proj_mask() { | |
|
4121
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|
1679 return INT_RDX_REG_mask(); |
| 0 | 1680 } |
| 1681 | |
| 1682 // Register for DIVL projection of divmodL | |
| 1683 RegMask Matcher::divL_proj_mask() { | |
|
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|
1684 return LONG_RAX_REG_mask(); |
| 0 | 1685 } |
| 1686 | |
| 1687 // Register for MODL projection of divmodL | |
| 1688 RegMask Matcher::modL_proj_mask() { | |
|
4121
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|
1689 return LONG_RDX_REG_mask(); |
| 0 | 1690 } |
| 1691 | |
|
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|
1692 const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
|
4121
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|
1693 return PTR_RBP_REG_mask(); |
|
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|
1694 } |
|
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|
1695 |
| 0 | 1696 %} |
| 1697 | |
| 1698 //----------ENCODING BLOCK----------------------------------------------------- | |
| 1699 // This block specifies the encoding classes used by the compiler to | |
| 1700 // output byte streams. Encoding classes are parameterized macros | |
| 1701 // used by Machine Instruction Nodes in order to generate the bit | |
| 1702 // encoding of the instruction. Operands specify their base encoding | |
| 1703 // interface with the interface keyword. There are currently | |
| 1704 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, & | |
| 1705 // COND_INTER. REG_INTER causes an operand to generate a function | |
| 1706 // which returns its register number when queried. CONST_INTER causes | |
| 1707 // an operand to generate a function which returns the value of the | |
| 1708 // constant when queried. MEMORY_INTER causes an operand to generate | |
| 1709 // four functions which return the Base Register, the Index Register, | |
| 1710 // the Scale Value, and the Offset Value of the operand when queried. | |
| 1711 // COND_INTER causes an operand to generate six functions which return | |
| 1712 // the encoding code (ie - encoding bits for the instruction) | |
| 1713 // associated with each basic boolean condition for a conditional | |
| 1714 // instruction. | |
| 1715 // | |
| 1716 // Instructions specify two basic values for encoding. Again, a | |
| 1717 // function is available to check if the constant displacement is an | |
| 1718 // oop. They use the ins_encode keyword to specify their encoding | |
| 1719 // classes (which must be a sequence of enc_class names, and their | |
| 1720 // parameters, specified in the encoding block), and they use the | |
| 1721 // opcode keyword to specify, in order, their primary, secondary, and | |
| 1722 // tertiary opcode. Only the opcode sections which a particular | |
| 1723 // instruction needs for encoding need to be specified. | |
| 1724 encode %{ | |
| 1725 // Build emit functions for each basic byte or larger field in the | |
| 1726 // intel encoding scheme (opcode, rm, sib, immediate), and call them | |
| 1727 // from C++ code in the enc_class source block. Emit functions will | |
| 1728 // live in the main source block for now. In future, we can | |
| 1729 // generalize this by adding a syntax that specifies the sizes of | |
| 1730 // fields in an order, so that the adlc can build the emit functions | |
| 1731 // automagically | |
| 1732 | |
| 1733 // Emit primary opcode | |
| 1734 enc_class OpcP | |
| 1735 %{ | |
| 1736 emit_opcode(cbuf, $primary); | |
| 1737 %} | |
| 1738 | |
| 1739 // Emit secondary opcode | |
| 1740 enc_class OpcS | |
| 1741 %{ | |
| 1742 emit_opcode(cbuf, $secondary); | |
| 1743 %} | |
| 1744 | |
| 1745 // Emit tertiary opcode | |
| 1746 enc_class OpcT | |
| 1747 %{ | |
| 1748 emit_opcode(cbuf, $tertiary); | |
| 1749 %} | |
| 1750 | |
| 1751 // Emit opcode directly | |
| 1752 enc_class Opcode(immI d8) | |
| 1753 %{ | |
| 1754 emit_opcode(cbuf, $d8$$constant); | |
| 1755 %} | |
| 1756 | |
| 1757 // Emit size prefix | |
| 1758 enc_class SizePrefix | |
| 1759 %{ | |
| 1760 emit_opcode(cbuf, 0x66); | |
| 1761 %} | |
| 1762 | |
| 1763 enc_class reg(rRegI reg) | |
| 1764 %{ | |
| 1765 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7); | |
| 1766 %} | |
| 1767 | |
| 1768 enc_class reg_reg(rRegI dst, rRegI src) | |
| 1769 %{ | |
| 1770 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7); | |
| 1771 %} | |
| 1772 | |
| 1773 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src) | |
| 1774 %{ | |
| 1775 emit_opcode(cbuf, $opcode$$constant); | |
| 1776 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7); | |
| 1777 %} | |
| 1778 | |
| 1779 enc_class cdql_enc(no_rax_rdx_RegI div) | |
| 1780 %{ | |
| 1781 // Full implementation of Java idiv and irem; checks for | |
| 1782 // special case as described in JVM spec., p.243 & p.271. | |
| 1783 // | |
| 1784 // normal case special case | |
| 1785 // | |
| 1786 // input : rax: dividend min_int | |
| 1787 // reg: divisor -1 | |
| 1788 // | |
| 1789 // output: rax: quotient (= rax idiv reg) min_int | |
| 1790 // rdx: remainder (= rax irem reg) 0 | |
| 1791 // | |
| 1792 // Code sequnce: | |
| 1793 // | |
| 1794 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax | |
| 1795 // 5: 75 07/08 jne e <normal> | |
| 1796 // 7: 33 d2 xor %edx,%edx | |
| 1797 // [div >= 8 -> offset + 1] | |
| 1798 // [REX_B] | |
| 1799 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div | |
| 1800 // c: 74 03/04 je 11 <done> | |
| 1801 // 000000000000000e <normal>: | |
| 1802 // e: 99 cltd | |
| 1803 // [div >= 8 -> offset + 1] | |
| 1804 // [REX_B] | |
| 1805 // f: f7 f9 idiv $div | |
| 1806 // 0000000000000011 <done>: | |
| 1807 | |
| 1808 // cmp $0x80000000,%eax | |
| 1809 emit_opcode(cbuf, 0x3d); | |
| 1810 emit_d8(cbuf, 0x00); | |
| 1811 emit_d8(cbuf, 0x00); | |
| 1812 emit_d8(cbuf, 0x00); | |
| 1813 emit_d8(cbuf, 0x80); | |
| 1814 | |
| 1815 // jne e <normal> | |
| 1816 emit_opcode(cbuf, 0x75); | |
| 1817 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08); | |
| 1818 | |
| 1819 // xor %edx,%edx | |
| 1820 emit_opcode(cbuf, 0x33); | |
| 1821 emit_d8(cbuf, 0xD2); | |
| 1822 | |
| 1823 // cmp $0xffffffffffffffff,%ecx | |
| 1824 if ($div$$reg >= 8) { | |
| 1825 emit_opcode(cbuf, Assembler::REX_B); | |
| 1826 } | |
| 1827 emit_opcode(cbuf, 0x83); | |
| 1828 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7); | |
| 1829 emit_d8(cbuf, 0xFF); | |
| 1830 | |
| 1831 // je 11 <done> | |
| 1832 emit_opcode(cbuf, 0x74); | |
| 1833 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04); | |
| 1834 | |
| 1835 // <normal> | |
| 1836 // cltd | |
| 1837 emit_opcode(cbuf, 0x99); | |
| 1838 | |
| 1839 // idivl (note: must be emitted by the user of this rule) | |
| 1840 // <done> | |
| 1841 %} | |
| 1842 | |
| 1843 enc_class cdqq_enc(no_rax_rdx_RegL div) | |
| 1844 %{ | |
| 1845 // Full implementation of Java ldiv and lrem; checks for | |
| 1846 // special case as described in JVM spec., p.243 & p.271. | |
| 1847 // | |
| 1848 // normal case special case | |
| 1849 // | |
| 1850 // input : rax: dividend min_long | |
| 1851 // reg: divisor -1 | |
| 1852 // | |
| 1853 // output: rax: quotient (= rax idiv reg) min_long | |
| 1854 // rdx: remainder (= rax irem reg) 0 | |
| 1855 // | |
| 1856 // Code sequnce: | |
| 1857 // | |
| 1858 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx | |
| 1859 // 7: 00 00 80 | |
| 1860 // a: 48 39 d0 cmp %rdx,%rax | |
| 1861 // d: 75 08 jne 17 <normal> | |
| 1862 // f: 33 d2 xor %edx,%edx | |
| 1863 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div | |
| 1864 // 15: 74 05 je 1c <done> | |
| 1865 // 0000000000000017 <normal>: | |
| 1866 // 17: 48 99 cqto | |
| 1867 // 19: 48 f7 f9 idiv $div | |
| 1868 // 000000000000001c <done>: | |
| 1869 | |
| 1870 // mov $0x8000000000000000,%rdx | |
| 1871 emit_opcode(cbuf, Assembler::REX_W); | |
| 1872 emit_opcode(cbuf, 0xBA); | |
| 1873 emit_d8(cbuf, 0x00); | |
| 1874 emit_d8(cbuf, 0x00); | |
| 1875 emit_d8(cbuf, 0x00); | |
| 1876 emit_d8(cbuf, 0x00); | |
| 1877 emit_d8(cbuf, 0x00); | |
| 1878 emit_d8(cbuf, 0x00); | |
| 1879 emit_d8(cbuf, 0x00); | |
| 1880 emit_d8(cbuf, 0x80); | |
| 1881 | |
| 1882 // cmp %rdx,%rax | |
| 1883 emit_opcode(cbuf, Assembler::REX_W); | |
| 1884 emit_opcode(cbuf, 0x39); | |
| 1885 emit_d8(cbuf, 0xD0); | |
| 1886 | |
| 1887 // jne 17 <normal> | |
| 1888 emit_opcode(cbuf, 0x75); | |
| 1889 emit_d8(cbuf, 0x08); | |
| 1890 | |
| 1891 // xor %edx,%edx | |
| 1892 emit_opcode(cbuf, 0x33); | |
| 1893 emit_d8(cbuf, 0xD2); | |
| 1894 | |
| 1895 // cmp $0xffffffffffffffff,$div | |
| 1896 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB); | |
| 1897 emit_opcode(cbuf, 0x83); | |
| 1898 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7); | |
| 1899 emit_d8(cbuf, 0xFF); | |
| 1900 | |
| 1901 // je 1e <done> | |
| 1902 emit_opcode(cbuf, 0x74); | |
| 1903 emit_d8(cbuf, 0x05); | |
| 1904 | |
| 1905 // <normal> | |
| 1906 // cqto | |
| 1907 emit_opcode(cbuf, Assembler::REX_W); | |
| 1908 emit_opcode(cbuf, 0x99); | |
| 1909 | |
| 1910 // idivq (note: must be emitted by the user of this rule) | |
| 1911 // <done> | |
| 1912 %} | |
| 1913 | |
| 1914 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension | |
| 1915 enc_class OpcSE(immI imm) | |
| 1916 %{ | |
| 1917 // Emit primary opcode and set sign-extend bit | |
| 1918 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1919 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
| 1920 emit_opcode(cbuf, $primary | 0x02); | |
| 1921 } else { | |
| 1922 // 32-bit immediate | |
| 1923 emit_opcode(cbuf, $primary); | |
| 1924 } | |
| 1925 %} | |
| 1926 | |
| 1927 enc_class OpcSErm(rRegI dst, immI imm) | |
| 1928 %{ | |
| 1929 // OpcSEr/m | |
| 1930 int dstenc = $dst$$reg; | |
| 1931 if (dstenc >= 8) { | |
| 1932 emit_opcode(cbuf, Assembler::REX_B); | |
| 1933 dstenc -= 8; | |
| 1934 } | |
| 1935 // Emit primary opcode and set sign-extend bit | |
| 1936 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1937 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
| 1938 emit_opcode(cbuf, $primary | 0x02); | |
| 1939 } else { | |
| 1940 // 32-bit immediate | |
| 1941 emit_opcode(cbuf, $primary); | |
| 1942 } | |
| 1943 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 1944 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
| 1945 %} | |
| 1946 | |
| 1947 enc_class OpcSErm_wide(rRegL dst, immI imm) | |
| 1948 %{ | |
| 1949 // OpcSEr/m | |
| 1950 int dstenc = $dst$$reg; | |
| 1951 if (dstenc < 8) { | |
| 1952 emit_opcode(cbuf, Assembler::REX_W); | |
| 1953 } else { | |
| 1954 emit_opcode(cbuf, Assembler::REX_WB); | |
| 1955 dstenc -= 8; | |
| 1956 } | |
| 1957 // Emit primary opcode and set sign-extend bit | |
| 1958 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1959 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
| 1960 emit_opcode(cbuf, $primary | 0x02); | |
| 1961 } else { | |
| 1962 // 32-bit immediate | |
| 1963 emit_opcode(cbuf, $primary); | |
| 1964 } | |
| 1965 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 1966 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
| 1967 %} | |
| 1968 | |
| 1969 enc_class Con8or32(immI imm) | |
| 1970 %{ | |
| 1971 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1972 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
| 1973 $$$emit8$imm$$constant; | |
| 1974 } else { | |
| 1975 // 32-bit immediate | |
| 1976 $$$emit32$imm$$constant; | |
| 1977 } | |
| 1978 %} | |
| 1979 | |
| 1980 enc_class opc2_reg(rRegI dst) | |
| 1981 %{ | |
| 1982 // BSWAP | |
| 1983 emit_cc(cbuf, $secondary, $dst$$reg); | |
| 1984 %} | |
| 1985 | |
| 1986 enc_class opc3_reg(rRegI dst) | |
| 1987 %{ | |
| 1988 // BSWAP | |
| 1989 emit_cc(cbuf, $tertiary, $dst$$reg); | |
| 1990 %} | |
| 1991 | |
| 1992 enc_class reg_opc(rRegI div) | |
| 1993 %{ | |
| 1994 // INC, DEC, IDIV, IMOD, JMP indirect, ... | |
| 1995 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7); | |
| 1996 %} | |
| 1997 | |
| 1998 enc_class enc_cmov(cmpOp cop) | |
| 1999 %{ | |
| 2000 // CMOV | |
| 2001 $$$emit8$primary; | |
| 2002 emit_cc(cbuf, $secondary, $cop$$cmpcode); | |
| 2003 %} | |
| 2004 | |
| 2005 enc_class enc_PartialSubtypeCheck() | |
| 2006 %{ | |
| 2007 Register Rrdi = as_Register(RDI_enc); // result register | |
| 2008 Register Rrax = as_Register(RAX_enc); // super class | |
| 2009 Register Rrcx = as_Register(RCX_enc); // killed | |
| 2010 Register Rrsi = as_Register(RSI_enc); // sub class | |
|
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2011 Label miss; |
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2012 const bool set_cond_codes = true; |
| 0 | 2013 |
| 2014 MacroAssembler _masm(&cbuf); | |
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2015 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi, |
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2016 NULL, &miss, |
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2017 /*set_cond_codes:*/ true); |
| 0 | 2018 if ($primary) { |
| 304 | 2019 __ xorptr(Rrdi, Rrdi); |
| 0 | 2020 } |
| 2021 __ bind(miss); | |
| 2022 %} | |
| 2023 | |
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2024 enc_class clear_avx %{ |
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2025 debug_only(int off0 = cbuf.insts_size()); |
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2026 if (ra_->C->max_vector_size() > 16) { |
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2027 // Clear upper bits of YMM registers when current compiled code uses |
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2028 // wide vectors to avoid AVX <-> SSE transition penalty during call. |
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2029 MacroAssembler _masm(&cbuf); |
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2030 __ vzeroupper(); |
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2031 } |
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2032 debug_only(int off1 = cbuf.insts_size()); |
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2033 assert(off1 - off0 == clear_avx_size(), "correct size prediction"); |
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2034 %} |
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2035 |
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2036 enc_class Java_To_Runtime(method meth) %{ |
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2037 // No relocation needed |
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2038 MacroAssembler _masm(&cbuf); |
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2039 __ mov64(r10, (int64_t) $meth$$method); |
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2040 __ call(r10); |
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2041 %} |
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2042 |
| 0 | 2043 enc_class Java_To_Interpreter(method meth) |
| 2044 %{ | |
| 2045 // CALL Java_To_Interpreter | |
| 2046 // This is the instruction starting address for relocation info. | |
| 1748 | 2047 cbuf.set_insts_mark(); |
| 0 | 2048 $$$emit8$primary; |
| 2049 // CALL directly to the runtime | |
| 2050 emit_d32_reloc(cbuf, | |
| 1748 | 2051 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4), |
| 0 | 2052 runtime_call_Relocation::spec(), |
| 2053 RELOC_DISP32); | |
| 2054 %} | |
| 2055 | |
| 2056 enc_class Java_Static_Call(method meth) | |
| 2057 %{ | |
| 2058 // JAVA STATIC CALL | |
| 2059 // CALL to fixup routine. Fixup routine uses ScopeDesc info to | |
| 2060 // determine who we intended to call. | |
| 1748 | 2061 cbuf.set_insts_mark(); |
| 0 | 2062 $$$emit8$primary; |
| 2063 | |
| 2064 if (!_method) { | |
| 2065 emit_d32_reloc(cbuf, | |
| 1748 | 2066 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4), |
| 0 | 2067 runtime_call_Relocation::spec(), |
| 2068 RELOC_DISP32); | |
| 2069 } else if (_optimized_virtual) { | |
| 2070 emit_d32_reloc(cbuf, | |
| 1748 | 2071 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4), |
| 0 | 2072 opt_virtual_call_Relocation::spec(), |
| 2073 RELOC_DISP32); | |
| 2074 } else { | |
| 2075 emit_d32_reloc(cbuf, | |
| 1748 | 2076 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4), |
| 0 | 2077 static_call_Relocation::spec(), |
| 2078 RELOC_DISP32); | |
| 2079 } | |
| 2080 if (_method) { | |
| 2081 // Emit stub for static call | |
| 2082 emit_java_to_interp(cbuf); | |
| 2083 } | |
| 2084 %} | |
| 2085 | |
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2086 enc_class Java_Dynamic_Call(method meth) %{ |
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2087 MacroAssembler _masm(&cbuf); |
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2088 __ ic_call((address)$meth$$method); |
| 0 | 2089 %} |
| 2090 | |
| 2091 enc_class Java_Compiled_Call(method meth) | |
| 2092 %{ | |
| 2093 // JAVA COMPILED CALL | |
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2094 int disp = in_bytes(Method:: from_compiled_offset()); |
| 0 | 2095 |
| 2096 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!! | |
| 2097 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small"); | |
| 2098 | |
| 2099 // callq *disp(%rax) | |
| 1748 | 2100 cbuf.set_insts_mark(); |
| 0 | 2101 $$$emit8$primary; |
| 2102 if (disp < 0x80) { | |
| 2103 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte | |
| 2104 emit_d8(cbuf, disp); // Displacement | |
| 2105 } else { | |
| 2106 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte | |
| 2107 emit_d32(cbuf, disp); // Displacement | |
| 2108 } | |
| 2109 %} | |
| 2110 | |
| 2111 enc_class reg_opc_imm(rRegI dst, immI8 shift) | |
| 2112 %{ | |
| 2113 // SAL, SAR, SHR | |
| 2114 int dstenc = $dst$$reg; | |
| 2115 if (dstenc >= 8) { | |
| 2116 emit_opcode(cbuf, Assembler::REX_B); | |
| 2117 dstenc -= 8; | |
| 2118 } | |
| 2119 $$$emit8$primary; | |
| 2120 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
| 2121 $$$emit8$shift$$constant; | |
| 2122 %} | |
| 2123 | |
| 2124 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift) | |
| 2125 %{ | |
| 2126 // SAL, SAR, SHR | |
| 2127 int dstenc = $dst$$reg; | |
| 2128 if (dstenc < 8) { | |
| 2129 emit_opcode(cbuf, Assembler::REX_W); | |
| 2130 } else { | |
| 2131 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2132 dstenc -= 8; | |
| 2133 } | |
| 2134 $$$emit8$primary; | |
| 2135 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
| 2136 $$$emit8$shift$$constant; | |
| 2137 %} | |
| 2138 | |
| 2139 enc_class load_immI(rRegI dst, immI src) | |
| 2140 %{ | |
| 2141 int dstenc = $dst$$reg; | |
| 2142 if (dstenc >= 8) { | |
| 2143 emit_opcode(cbuf, Assembler::REX_B); | |
| 2144 dstenc -= 8; | |
| 2145 } | |
| 2146 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2147 $$$emit32$src$$constant; | |
| 2148 %} | |
| 2149 | |
| 2150 enc_class load_immL(rRegL dst, immL src) | |
| 2151 %{ | |
| 2152 int dstenc = $dst$$reg; | |
| 2153 if (dstenc < 8) { | |
| 2154 emit_opcode(cbuf, Assembler::REX_W); | |
| 2155 } else { | |
| 2156 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2157 dstenc -= 8; | |
| 2158 } | |
| 2159 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2160 emit_d64(cbuf, $src$$constant); | |
| 2161 %} | |
| 2162 | |
| 2163 enc_class load_immUL32(rRegL dst, immUL32 src) | |
| 2164 %{ | |
| 2165 // same as load_immI, but this time we care about zeroes in the high word | |
| 2166 int dstenc = $dst$$reg; | |
| 2167 if (dstenc >= 8) { | |
| 2168 emit_opcode(cbuf, Assembler::REX_B); | |
| 2169 dstenc -= 8; | |
| 2170 } | |
| 2171 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2172 $$$emit32$src$$constant; | |
| 2173 %} | |
| 2174 | |
| 2175 enc_class load_immL32(rRegL dst, immL32 src) | |
| 2176 %{ | |
| 2177 int dstenc = $dst$$reg; | |
| 2178 if (dstenc < 8) { | |
| 2179 emit_opcode(cbuf, Assembler::REX_W); | |
| 2180 } else { | |
| 2181 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2182 dstenc -= 8; | |
| 2183 } | |
| 2184 emit_opcode(cbuf, 0xC7); | |
| 2185 emit_rm(cbuf, 0x03, 0x00, dstenc); | |
| 2186 $$$emit32$src$$constant; | |
| 2187 %} | |
| 2188 | |
| 2189 enc_class load_immP31(rRegP dst, immP32 src) | |
| 2190 %{ | |
| 2191 // same as load_immI, but this time we care about zeroes in the high word | |
| 2192 int dstenc = $dst$$reg; | |
| 2193 if (dstenc >= 8) { | |
| 2194 emit_opcode(cbuf, Assembler::REX_B); | |
| 2195 dstenc -= 8; | |
| 2196 } | |
| 2197 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2198 $$$emit32$src$$constant; | |
| 2199 %} | |
| 2200 | |
| 2201 enc_class load_immP(rRegP dst, immP src) | |
| 2202 %{ | |
| 2203 int dstenc = $dst$$reg; | |
| 2204 if (dstenc < 8) { | |
| 2205 emit_opcode(cbuf, Assembler::REX_W); | |
| 2206 } else { | |
| 2207 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2208 dstenc -= 8; | |
| 2209 } | |
| 2210 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2211 // This next line should be generated from ADLC | |
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2212 if ($src->constant_reloc() != relocInfo::none) { |
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2213 emit_d64_reloc(cbuf, $src$$constant, $src->constant_reloc(), RELOC_IMM64); |
| 0 | 2214 } else { |
| 2215 emit_d64(cbuf, $src$$constant); | |
| 2216 } | |
| 2217 %} | |
| 2218 | |
| 2219 enc_class Con32(immI src) | |
| 2220 %{ | |
| 2221 // Output immediate | |
| 2222 $$$emit32$src$$constant; | |
| 2223 %} | |
| 2224 | |
| 2225 enc_class Con64(immL src) | |
| 2226 %{ | |
| 2227 // Output immediate | |
| 2228 emit_d64($src$$constant); | |
| 2229 %} | |
| 2230 | |
| 2231 enc_class Con32F_as_bits(immF src) | |
| 2232 %{ | |
| 2233 // Output Float immediate bits | |
| 2234 jfloat jf = $src$$constant; | |
| 2235 jint jf_as_bits = jint_cast(jf); | |
| 2236 emit_d32(cbuf, jf_as_bits); | |
| 2237 %} | |
| 2238 | |
| 2239 enc_class Con16(immI src) | |
| 2240 %{ | |
| 2241 // Output immediate | |
| 2242 $$$emit16$src$$constant; | |
| 2243 %} | |
| 2244 | |
| 2245 // How is this different from Con32??? XXX | |
| 2246 enc_class Con_d32(immI src) | |
| 2247 %{ | |
| 2248 emit_d32(cbuf,$src$$constant); | |
| 2249 %} | |
| 2250 | |
| 2251 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI) | |
| 2252 // Output immediate memory reference | |
| 2253 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 ); | |
| 2254 emit_d32(cbuf, 0x00); | |
| 2255 %} | |
| 2256 | |
| 2257 enc_class lock_prefix() | |
| 2258 %{ | |
| 2259 if (os::is_MP()) { | |
| 2260 emit_opcode(cbuf, 0xF0); // lock | |
| 2261 } | |
| 2262 %} | |
| 2263 | |
| 2264 enc_class REX_mem(memory mem) | |
| 2265 %{ | |
| 2266 if ($mem$$base >= 8) { | |
| 2267 if ($mem$$index < 8) { | |
| 2268 emit_opcode(cbuf, Assembler::REX_B); | |
| 2269 } else { | |
| 2270 emit_opcode(cbuf, Assembler::REX_XB); | |
| 2271 } | |
| 2272 } else { | |
| 2273 if ($mem$$index >= 8) { | |
| 2274 emit_opcode(cbuf, Assembler::REX_X); | |
| 2275 } | |
| 2276 } | |
| 2277 %} | |
| 2278 | |
| 2279 enc_class REX_mem_wide(memory mem) | |
| 2280 %{ | |
| 2281 if ($mem$$base >= 8) { | |
| 2282 if ($mem$$index < 8) { | |
| 2283 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2284 } else { | |
| 2285 emit_opcode(cbuf, Assembler::REX_WXB); | |
| 2286 } | |
| 2287 } else { | |
| 2288 if ($mem$$index < 8) { | |
| 2289 emit_opcode(cbuf, Assembler::REX_W); | |
| 2290 } else { | |
| 2291 emit_opcode(cbuf, Assembler::REX_WX); | |
| 2292 } | |
| 2293 } | |
| 2294 %} | |
| 2295 | |
| 2296 // for byte regs | |
| 2297 enc_class REX_breg(rRegI reg) | |
| 2298 %{ | |
| 2299 if ($reg$$reg >= 4) { | |
| 2300 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B); | |
| 2301 } | |
| 2302 %} | |
| 2303 | |
| 2304 // for byte regs | |
| 2305 enc_class REX_reg_breg(rRegI dst, rRegI src) | |
| 2306 %{ | |
| 2307 if ($dst$$reg < 8) { | |
| 2308 if ($src$$reg >= 4) { | |
| 2309 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B); | |
| 2310 } | |
| 2311 } else { | |
| 2312 if ($src$$reg < 8) { | |
| 2313 emit_opcode(cbuf, Assembler::REX_R); | |
| 2314 } else { | |
| 2315 emit_opcode(cbuf, Assembler::REX_RB); | |
| 2316 } | |
| 2317 } | |
| 2318 %} | |
| 2319 | |
| 2320 // for byte regs | |
| 2321 enc_class REX_breg_mem(rRegI reg, memory mem) | |
| 2322 %{ | |
| 2323 if ($reg$$reg < 8) { | |
| 2324 if ($mem$$base < 8) { | |
| 2325 if ($mem$$index >= 8) { | |
| 2326 emit_opcode(cbuf, Assembler::REX_X); | |
| 2327 } else if ($reg$$reg >= 4) { | |
| 2328 emit_opcode(cbuf, Assembler::REX); | |
| 2329 } | |
| 2330 } else { | |
| 2331 if ($mem$$index < 8) { | |
| 2332 emit_opcode(cbuf, Assembler::REX_B); | |
| 2333 } else { | |
| 2334 emit_opcode(cbuf, Assembler::REX_XB); | |
| 2335 } | |
| 2336 } | |
| 2337 } else { | |
| 2338 if ($mem$$base < 8) { | |
| 2339 if ($mem$$index < 8) { | |
| 2340 emit_opcode(cbuf, Assembler::REX_R); | |
| 2341 } else { | |
| 2342 emit_opcode(cbuf, Assembler::REX_RX); | |
| 2343 } | |
| 2344 } else { | |
| 2345 if ($mem$$index < 8) { | |
| 2346 emit_opcode(cbuf, Assembler::REX_RB); | |
| 2347 } else { | |
| 2348 emit_opcode(cbuf, Assembler::REX_RXB); | |
| 2349 } | |
| 2350 } | |
| 2351 } | |
| 2352 %} | |
| 2353 | |
| 2354 enc_class REX_reg(rRegI reg) | |
| 2355 %{ | |
| 2356 if ($reg$$reg >= 8) { | |
| 2357 emit_opcode(cbuf, Assembler::REX_B); | |
| 2358 } | |
| 2359 %} | |
| 2360 | |
| 2361 enc_class REX_reg_wide(rRegI reg) | |
| 2362 %{ | |
| 2363 if ($reg$$reg < 8) { | |
| 2364 emit_opcode(cbuf, Assembler::REX_W); | |
| 2365 } else { | |
| 2366 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2367 } | |
| 2368 %} | |
| 2369 | |
| 2370 enc_class REX_reg_reg(rRegI dst, rRegI src) | |
| 2371 %{ | |
| 2372 if ($dst$$reg < 8) { | |
| 2373 if ($src$$reg >= 8) { | |
| 2374 emit_opcode(cbuf, Assembler::REX_B); | |
| 2375 } | |
| 2376 } else { | |
| 2377 if ($src$$reg < 8) { | |
| 2378 emit_opcode(cbuf, Assembler::REX_R); | |
| 2379 } else { | |
| 2380 emit_opcode(cbuf, Assembler::REX_RB); | |
| 2381 } | |
| 2382 } | |
| 2383 %} | |
| 2384 | |
| 2385 enc_class REX_reg_reg_wide(rRegI dst, rRegI src) | |
| 2386 %{ | |
| 2387 if ($dst$$reg < 8) { | |
| 2388 if ($src$$reg < 8) { | |
| 2389 emit_opcode(cbuf, Assembler::REX_W); | |
| 2390 } else { | |
| 2391 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2392 } | |
| 2393 } else { | |
| 2394 if ($src$$reg < 8) { | |
| 2395 emit_opcode(cbuf, Assembler::REX_WR); | |
| 2396 } else { | |
| 2397 emit_opcode(cbuf, Assembler::REX_WRB); | |
| 2398 } | |
| 2399 } | |
| 2400 %} | |
| 2401 | |
| 2402 enc_class REX_reg_mem(rRegI reg, memory mem) | |
| 2403 %{ | |
| 2404 if ($reg$$reg < 8) { | |
| 2405 if ($mem$$base < 8) { | |
| 2406 if ($mem$$index >= 8) { | |
| 2407 emit_opcode(cbuf, Assembler::REX_X); | |
| 2408 } | |
| 2409 } else { | |
| 2410 if ($mem$$index < 8) { | |
| 2411 emit_opcode(cbuf, Assembler::REX_B); | |
| 2412 } else { | |
| 2413 emit_opcode(cbuf, Assembler::REX_XB); | |
| 2414 } | |
| 2415 } | |
| 2416 } else { | |
| 2417 if ($mem$$base < 8) { | |
| 2418 if ($mem$$index < 8) { | |
| 2419 emit_opcode(cbuf, Assembler::REX_R); | |
| 2420 } else { | |
| 2421 emit_opcode(cbuf, Assembler::REX_RX); | |
| 2422 } | |
| 2423 } else { | |
| 2424 if ($mem$$index < 8) { | |
| 2425 emit_opcode(cbuf, Assembler::REX_RB); | |
| 2426 } else { | |
| 2427 emit_opcode(cbuf, Assembler::REX_RXB); | |
| 2428 } | |
| 2429 } | |
| 2430 } | |
| 2431 %} | |
| 2432 | |
| 2433 enc_class REX_reg_mem_wide(rRegL reg, memory mem) | |
| 2434 %{ | |
| 2435 if ($reg$$reg < 8) { | |
| 2436 if ($mem$$base < 8) { | |
| 2437 if ($mem$$index < 8) { | |
| 2438 emit_opcode(cbuf, Assembler::REX_W); | |
| 2439 } else { | |
| 2440 emit_opcode(cbuf, Assembler::REX_WX); | |
| 2441 } | |
| 2442 } else { | |
| 2443 if ($mem$$index < 8) { | |
| 2444 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2445 } else { | |
| 2446 emit_opcode(cbuf, Assembler::REX_WXB); | |
| 2447 } | |
| 2448 } | |
| 2449 } else { | |
| 2450 if ($mem$$base < 8) { | |
| 2451 if ($mem$$index < 8) { | |
| 2452 emit_opcode(cbuf, Assembler::REX_WR); | |
| 2453 } else { | |
| 2454 emit_opcode(cbuf, Assembler::REX_WRX); | |
| 2455 } | |
| 2456 } else { | |
| 2457 if ($mem$$index < 8) { | |
| 2458 emit_opcode(cbuf, Assembler::REX_WRB); | |
| 2459 } else { | |
| 2460 emit_opcode(cbuf, Assembler::REX_WRXB); | |
| 2461 } | |
| 2462 } | |
| 2463 } | |
| 2464 %} | |
| 2465 | |
| 2466 enc_class reg_mem(rRegI ereg, memory mem) | |
| 2467 %{ | |
| 2468 // High registers handle in encode_RegMem | |
| 2469 int reg = $ereg$$reg; | |
| 2470 int base = $mem$$base; | |
| 2471 int index = $mem$$index; | |
| 2472 int scale = $mem$$scale; | |
| 2473 int disp = $mem$$disp; | |
|
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2474 relocInfo::relocType disp_reloc = $mem->disp_reloc(); |
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2475 |
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2476 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc); |
| 0 | 2477 %} |
| 2478 | |
| 2479 enc_class RM_opc_mem(immI rm_opcode, memory mem) | |
| 2480 %{ | |
| 2481 int rm_byte_opcode = $rm_opcode$$constant; | |
| 2482 | |
| 2483 // High registers handle in encode_RegMem | |
| 2484 int base = $mem$$base; | |
| 2485 int index = $mem$$index; | |
| 2486 int scale = $mem$$scale; | |
| 2487 int displace = $mem$$disp; | |
| 2488 | |
|
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2489 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when |
| 0 | 2490 // working with static |
| 2491 // globals | |
| 2492 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, | |
|
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2493 disp_reloc); |
| 0 | 2494 %} |
| 2495 | |
| 2496 enc_class reg_lea(rRegI dst, rRegI src0, immI src1) | |
| 2497 %{ | |
| 2498 int reg_encoding = $dst$$reg; | |
| 2499 int base = $src0$$reg; // 0xFFFFFFFF indicates no base | |
| 2500 int index = 0x04; // 0x04 indicates no index | |
| 2501 int scale = 0x00; // 0x00 indicates no scale | |
| 2502 int displace = $src1$$constant; // 0x00 indicates no displacement | |
|
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2503 relocInfo::relocType disp_reloc = relocInfo::none; |
| 0 | 2504 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, |
|
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2505 disp_reloc); |
| 0 | 2506 %} |
| 2507 | |
| 2508 enc_class neg_reg(rRegI dst) | |
| 2509 %{ | |
| 2510 int dstenc = $dst$$reg; | |
| 2511 if (dstenc >= 8) { | |
| 2512 emit_opcode(cbuf, Assembler::REX_B); | |
| 2513 dstenc -= 8; | |
| 2514 } | |
| 2515 // NEG $dst | |
| 2516 emit_opcode(cbuf, 0xF7); | |
| 2517 emit_rm(cbuf, 0x3, 0x03, dstenc); | |
| 2518 %} | |
| 2519 | |
| 2520 enc_class neg_reg_wide(rRegI dst) | |
| 2521 %{ | |
| 2522 int dstenc = $dst$$reg; | |
| 2523 if (dstenc < 8) { | |
| 2524 emit_opcode(cbuf, Assembler::REX_W); | |
| 2525 } else { | |
| 2526 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2527 dstenc -= 8; | |
| 2528 } | |
| 2529 // NEG $dst | |
| 2530 emit_opcode(cbuf, 0xF7); | |
| 2531 emit_rm(cbuf, 0x3, 0x03, dstenc); | |
| 2532 %} | |
| 2533 | |
| 2534 enc_class setLT_reg(rRegI dst) | |
| 2535 %{ | |
| 2536 int dstenc = $dst$$reg; | |
| 2537 if (dstenc >= 8) { | |
| 2538 emit_opcode(cbuf, Assembler::REX_B); | |
| 2539 dstenc -= 8; | |
| 2540 } else if (dstenc >= 4) { | |
| 2541 emit_opcode(cbuf, Assembler::REX); | |
| 2542 } | |
| 2543 // SETLT $dst | |
| 2544 emit_opcode(cbuf, 0x0F); | |
| 2545 emit_opcode(cbuf, 0x9C); | |
| 2546 emit_rm(cbuf, 0x3, 0x0, dstenc); | |
| 2547 %} | |
| 2548 | |
| 2549 enc_class setNZ_reg(rRegI dst) | |
| 2550 %{ | |
| 2551 int dstenc = $dst$$reg; | |
| 2552 if (dstenc >= 8) { | |
| 2553 emit_opcode(cbuf, Assembler::REX_B); | |
| 2554 dstenc -= 8; | |
| 2555 } else if (dstenc >= 4) { | |
| 2556 emit_opcode(cbuf, Assembler::REX); | |
| 2557 } | |
| 2558 // SETNZ $dst | |
| 2559 emit_opcode(cbuf, 0x0F); | |
| 2560 emit_opcode(cbuf, 0x95); | |
| 2561 emit_rm(cbuf, 0x3, 0x0, dstenc); | |
| 2562 %} | |
| 2563 | |
| 2564 | |
| 2565 // Compare the lonogs and set -1, 0, or 1 into dst | |
| 2566 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst) | |
| 2567 %{ | |
| 2568 int src1enc = $src1$$reg; | |
| 2569 int src2enc = $src2$$reg; | |
| 2570 int dstenc = $dst$$reg; | |
| 2571 | |
| 2572 // cmpq $src1, $src2 | |
| 2573 if (src1enc < 8) { | |
| 2574 if (src2enc < 8) { | |
| 2575 emit_opcode(cbuf, Assembler::REX_W); | |
| 2576 } else { | |
| 2577 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2578 } | |
| 2579 } else { | |
| 2580 if (src2enc < 8) { | |
| 2581 emit_opcode(cbuf, Assembler::REX_WR); | |
| 2582 } else { | |
| 2583 emit_opcode(cbuf, Assembler::REX_WRB); | |
| 2584 } | |
| 2585 } | |
| 2586 emit_opcode(cbuf, 0x3B); | |
| 2587 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7); | |
| 2588 | |
| 2589 // movl $dst, -1 | |
| 2590 if (dstenc >= 8) { | |
| 2591 emit_opcode(cbuf, Assembler::REX_B); | |
| 2592 } | |
| 2593 emit_opcode(cbuf, 0xB8 | (dstenc & 7)); | |
| 2594 emit_d32(cbuf, -1); | |
| 2595 | |
| 2596 // jl,s done | |
| 2597 emit_opcode(cbuf, 0x7C); | |
| 2598 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08); | |
| 2599 | |
| 2600 // setne $dst | |
| 2601 if (dstenc >= 4) { | |
| 2602 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B); | |
| 2603 } | |
| 2604 emit_opcode(cbuf, 0x0F); | |
| 2605 emit_opcode(cbuf, 0x95); | |
| 2606 emit_opcode(cbuf, 0xC0 | (dstenc & 7)); | |
| 2607 | |
| 2608 // movzbl $dst, $dst | |
| 2609 if (dstenc >= 4) { | |
| 2610 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB); | |
| 2611 } | |
| 2612 emit_opcode(cbuf, 0x0F); | |
| 2613 emit_opcode(cbuf, 0xB6); | |
| 2614 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7); | |
| 2615 %} | |
| 2616 | |
| 2617 enc_class Push_ResultXD(regD dst) %{ | |
| 4759 | 2618 MacroAssembler _masm(&cbuf); |
| 2619 __ fstp_d(Address(rsp, 0)); | |
| 2620 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); | |
| 2621 __ addptr(rsp, 8); | |
| 0 | 2622 %} |
| 2623 | |
| 2624 enc_class Push_SrcXD(regD src) %{ | |
| 2625 MacroAssembler _masm(&cbuf); | |
| 4759 | 2626 __ subptr(rsp, 8); |
| 2627 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 2628 __ fld_d(Address(rsp, 0)); | |
| 2629 %} | |
| 2630 | |
| 0 | 2631 |
| 2632 // obj: object to lock | |
| 2633 // box: box address (header location) -- killed | |
| 2634 // tmp: rax -- killed | |
| 2635 // scr: rbx -- killed | |
| 2636 // | |
| 2637 // What follows is a direct transliteration of fast_lock() and fast_unlock() | |
| 2638 // from i486.ad. See that file for comments. | |
| 2639 // TODO: where possible switch from movq (r, 0) to movl(r,0) and | |
| 2640 // use the shorter encoding. (Movl clears the high-order 32-bits). | |
| 2641 | |
| 2642 | |
| 2643 enc_class Fast_Lock(rRegP obj, rRegP box, rax_RegI tmp, rRegP scr) | |
| 2644 %{ | |
| 2645 Register objReg = as_Register((int)$obj$$reg); | |
| 2646 Register boxReg = as_Register((int)$box$$reg); | |
| 2647 Register tmpReg = as_Register($tmp$$reg); | |
| 2648 Register scrReg = as_Register($scr$$reg); | |
| 2649 MacroAssembler masm(&cbuf); | |
| 2650 | |
| 2651 // Verify uniqueness of register assignments -- necessary but not sufficient | |
| 2652 assert (objReg != boxReg && objReg != tmpReg && | |
| 2653 objReg != scrReg && tmpReg != scrReg, "invariant") ; | |
| 2654 | |
| 2655 if (_counters != NULL) { | |
| 2656 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr())); | |
| 2657 } | |
| 2658 if (EmitSync & 1) { | |
| 304 | 2659 // Without cast to int32_t a movptr will destroy r10 which is typically obj |
|
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2660 masm.movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ; |
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2661 masm.cmpptr(rsp, (int32_t)NULL_WORD) ; |
| 0 | 2662 } else |
| 2663 if (EmitSync & 2) { | |
| 2664 Label DONE_LABEL; | |
| 2665 if (UseBiasedLocking) { | |
| 2666 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument. | |
| 2667 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters); | |
| 2668 } | |
| 304 | 2669 // QQQ was movl... |
| 2670 masm.movptr(tmpReg, 0x1); | |
| 2671 masm.orptr(tmpReg, Address(objReg, 0)); | |
| 2672 masm.movptr(Address(boxReg, 0), tmpReg); | |
| 0 | 2673 if (os::is_MP()) { |
| 2674 masm.lock(); | |
| 2675 } | |
| 304 | 2676 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg |
| 0 | 2677 masm.jcc(Assembler::equal, DONE_LABEL); |
| 2678 | |
| 2679 // Recursive locking | |
| 304 | 2680 masm.subptr(tmpReg, rsp); |
| 2681 masm.andptr(tmpReg, 7 - os::vm_page_size()); | |
| 2682 masm.movptr(Address(boxReg, 0), tmpReg); | |
| 0 | 2683 |
| 2684 masm.bind(DONE_LABEL); | |
| 2685 masm.nop(); // avoid branch to branch | |
| 2686 } else { | |
| 2687 Label DONE_LABEL, IsInflated, Egress; | |
| 2688 | |
|
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2689 masm.movptr(tmpReg, Address(objReg, 0)) ; |
| 304 | 2690 masm.testl (tmpReg, 0x02) ; // inflated vs stack-locked|neutral|biased |
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2691 masm.jcc (Assembler::notZero, IsInflated) ; |
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2692 |
| 0 | 2693 // it's stack-locked, biased or neutral |
| 2694 // TODO: optimize markword triage order to reduce the number of | |
| 2695 // conditional branches in the most common cases. | |
| 2696 // Beware -- there's a subtle invariant that fetch of the markword | |
| 2697 // at [FETCH], below, will never observe a biased encoding (*101b). | |
| 2698 // If this invariant is not held we'll suffer exclusion (safety) failure. | |
| 2699 | |
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2700 if (UseBiasedLocking && !UseOptoBiasInlining) { |
| 0 | 2701 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, true, DONE_LABEL, NULL, _counters); |
| 304 | 2702 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH] |
| 0 | 2703 } |
| 2704 | |
| 304 | 2705 // was q will it destroy high? |
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2706 masm.orl (tmpReg, 1) ; |
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2707 masm.movptr(Address(boxReg, 0), tmpReg) ; |
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2708 if (os::is_MP()) { masm.lock(); } |
| 304 | 2709 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg |
| 0 | 2710 if (_counters != NULL) { |
| 2711 masm.cond_inc32(Assembler::equal, | |
| 2712 ExternalAddress((address) _counters->fast_path_entry_count_addr())); | |
| 2713 } | |
| 2714 masm.jcc (Assembler::equal, DONE_LABEL); | |
| 2715 | |
| 2716 // Recursive locking | |
| 304 | 2717 masm.subptr(tmpReg, rsp); |
| 2718 masm.andptr(tmpReg, 7 - os::vm_page_size()); | |
| 2719 masm.movptr(Address(boxReg, 0), tmpReg); | |
| 0 | 2720 if (_counters != NULL) { |
| 2721 masm.cond_inc32(Assembler::equal, | |
| 2722 ExternalAddress((address) _counters->fast_path_entry_count_addr())); | |
| 2723 } | |
| 2724 masm.jmp (DONE_LABEL) ; | |
| 2725 | |
| 2726 masm.bind (IsInflated) ; | |
| 2727 // It's inflated | |
| 2728 | |
| 2729 // TODO: someday avoid the ST-before-CAS penalty by | |
| 2730 // relocating (deferring) the following ST. | |
| 2731 // We should also think about trying a CAS without having | |
| 2732 // fetched _owner. If the CAS is successful we may | |
| 2733 // avoid an RTO->RTS upgrade on the $line. | |
| 304 | 2734 // Without cast to int32_t a movptr will destroy r10 which is typically obj |
|
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2735 masm.movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ; |
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2736 |
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2737 masm.mov (boxReg, tmpReg) ; |
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2738 masm.movptr (tmpReg, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
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2739 masm.testptr(tmpReg, tmpReg) ; |
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2740 masm.jcc (Assembler::notZero, DONE_LABEL) ; |
| 0 | 2741 |
| 2742 // It's inflated and appears unlocked | |
|
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2743 if (os::is_MP()) { masm.lock(); } |
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2744 masm.cmpxchgptr(r15_thread, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
| 0 | 2745 // Intentional fall-through into DONE_LABEL ... |
| 2746 | |
| 2747 masm.bind (DONE_LABEL) ; | |
| 2748 masm.nop () ; // avoid jmp to jmp | |
| 2749 } | |
| 2750 %} | |
| 2751 | |
| 2752 // obj: object to unlock | |
| 2753 // box: box address (displaced header location), killed | |
| 2754 // RBX: killed tmp; cannot be obj nor box | |
| 2755 enc_class Fast_Unlock(rRegP obj, rax_RegP box, rRegP tmp) | |
| 2756 %{ | |
| 2757 | |
| 2758 Register objReg = as_Register($obj$$reg); | |
| 2759 Register boxReg = as_Register($box$$reg); | |
| 2760 Register tmpReg = as_Register($tmp$$reg); | |
| 2761 MacroAssembler masm(&cbuf); | |
| 2762 | |
|
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2763 if (EmitSync & 4) { |
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2764 masm.cmpptr(rsp, 0) ; |
| 0 | 2765 } else |
| 2766 if (EmitSync & 8) { | |
| 2767 Label DONE_LABEL; | |
| 2768 if (UseBiasedLocking) { | |
| 2769 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); | |
| 2770 } | |
| 2771 | |
| 2772 // Check whether the displaced header is 0 | |
| 2773 //(=> recursive unlock) | |
| 304 | 2774 masm.movptr(tmpReg, Address(boxReg, 0)); |
| 2775 masm.testptr(tmpReg, tmpReg); | |
| 0 | 2776 masm.jcc(Assembler::zero, DONE_LABEL); |
| 2777 | |
| 2778 // If not recursive lock, reset the header to displaced header | |
| 2779 if (os::is_MP()) { | |
| 2780 masm.lock(); | |
| 2781 } | |
| 304 | 2782 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box |
| 0 | 2783 masm.bind(DONE_LABEL); |
| 2784 masm.nop(); // avoid branch to branch | |
| 2785 } else { | |
| 2786 Label DONE_LABEL, Stacked, CheckSucc ; | |
| 2787 | |
|
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2788 if (UseBiasedLocking && !UseOptoBiasInlining) { |
| 0 | 2789 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); |
| 2790 } | |
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2791 |
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2792 masm.movptr(tmpReg, Address(objReg, 0)) ; |
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2793 masm.cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD) ; |
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2794 masm.jcc (Assembler::zero, DONE_LABEL) ; |
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2795 masm.testl (tmpReg, 0x02) ; |
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2796 masm.jcc (Assembler::zero, Stacked) ; |
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2797 |
| 0 | 2798 // It's inflated |
|
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2799 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
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2800 masm.xorptr(boxReg, r15_thread) ; |
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2801 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ; |
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2802 masm.jcc (Assembler::notZero, DONE_LABEL) ; |
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2803 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ; |
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2804 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ; |
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2805 masm.jcc (Assembler::notZero, CheckSucc) ; |
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2806 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ; |
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2807 masm.jmp (DONE_LABEL) ; |
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2808 |
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2809 if ((EmitSync & 65536) == 0) { |
| 0 | 2810 Label LSuccess, LGoSlowPath ; |
| 2811 masm.bind (CheckSucc) ; | |
| 304 | 2812 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ; |
| 0 | 2813 masm.jcc (Assembler::zero, LGoSlowPath) ; |
| 2814 | |
| 2815 // I'd much rather use lock:andl m->_owner, 0 as it's faster than the | |
| 2816 // the explicit ST;MEMBAR combination, but masm doesn't currently support | |
| 2817 // "ANDQ M,IMM". Don't use MFENCE here. lock:add to TOS, xchg, etc | |
| 2818 // are all faster when the write buffer is populated. | |
| 304 | 2819 masm.movptr (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ; |
| 0 | 2820 if (os::is_MP()) { |
| 304 | 2821 masm.lock () ; masm.addl (Address(rsp, 0), 0) ; |
| 0 | 2822 } |
| 304 | 2823 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ; |
| 0 | 2824 masm.jcc (Assembler::notZero, LSuccess) ; |
| 2825 | |
| 304 | 2826 masm.movptr (boxReg, (int32_t)NULL_WORD) ; // box is really EAX |
| 0 | 2827 if (os::is_MP()) { masm.lock(); } |
| 304 | 2828 masm.cmpxchgptr(r15_thread, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)); |
| 0 | 2829 masm.jcc (Assembler::notEqual, LSuccess) ; |
| 2830 // Intentional fall-through into slow-path | |
| 2831 | |
| 2832 masm.bind (LGoSlowPath) ; | |
| 2833 masm.orl (boxReg, 1) ; // set ICC.ZF=0 to indicate failure | |
| 2834 masm.jmp (DONE_LABEL) ; | |
| 2835 | |
| 2836 masm.bind (LSuccess) ; | |
| 2837 masm.testl (boxReg, 0) ; // set ICC.ZF=1 to indicate success | |
| 2838 masm.jmp (DONE_LABEL) ; | |
| 2839 } | |
| 2840 | |
|
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2841 masm.bind (Stacked) ; |
| 304 | 2842 masm.movptr(tmpReg, Address (boxReg, 0)) ; // re-fetch |
|
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2843 if (os::is_MP()) { masm.lock(); } |
| 304 | 2844 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box |
| 0 | 2845 |
| 2846 if (EmitSync & 65536) { | |
| 2847 masm.bind (CheckSucc) ; | |
| 2848 } | |
| 2849 masm.bind(DONE_LABEL); | |
| 2850 if (EmitSync & 32768) { | |
| 2851 masm.nop(); // avoid branch to branch | |
| 2852 } | |
| 2853 } | |
| 2854 %} | |
| 2855 | |
|
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2856 |
| 0 | 2857 enc_class enc_rethrow() |
| 2858 %{ | |
| 1748 | 2859 cbuf.set_insts_mark(); |
| 0 | 2860 emit_opcode(cbuf, 0xE9); // jmp entry |
| 2861 emit_d32_reloc(cbuf, | |
| 1748 | 2862 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4), |
| 0 | 2863 runtime_call_Relocation::spec(), |
| 2864 RELOC_DISP32); | |
| 2865 %} | |
| 2866 | |
| 2867 %} | |
| 2868 | |
| 2869 | |
|
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2870 |
| 0 | 2871 //----------FRAME-------------------------------------------------------------- |
| 2872 // Definition of frame structure and management information. | |
| 2873 // | |
| 2874 // S T A C K L A Y O U T Allocators stack-slot number | |
| 2875 // | (to get allocators register number | |
| 2876 // G Owned by | | v add OptoReg::stack0()) | |
| 2877 // r CALLER | | | |
| 2878 // o | +--------+ pad to even-align allocators stack-slot | |
| 2879 // w V | pad0 | numbers; owned by CALLER | |
| 2880 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned | |
| 2881 // h ^ | in | 5 | |
| 2882 // | | args | 4 Holes in incoming args owned by SELF | |
| 2883 // | | | | 3 | |
| 2884 // | | +--------+ | |
| 2885 // V | | old out| Empty on Intel, window on Sparc | |
| 2886 // | old |preserve| Must be even aligned. | |
| 2887 // | SP-+--------+----> Matcher::_old_SP, even aligned | |
| 2888 // | | in | 3 area for Intel ret address | |
| 2889 // Owned by |preserve| Empty on Sparc. | |
| 2890 // SELF +--------+ | |
| 2891 // | | pad2 | 2 pad to align old SP | |
| 2892 // | +--------+ 1 | |
| 2893 // | | locks | 0 | |
| 2894 // | +--------+----> OptoReg::stack0(), even aligned | |
| 2895 // | | pad1 | 11 pad to align new SP | |
| 2896 // | +--------+ | |
| 2897 // | | | 10 | |
| 2898 // | | spills | 9 spills | |
| 2899 // V | | 8 (pad0 slot for callee) | |
| 2900 // -----------+--------+----> Matcher::_out_arg_limit, unaligned | |
| 2901 // ^ | out | 7 | |
| 2902 // | | args | 6 Holes in outgoing args owned by CALLEE | |
| 2903 // Owned by +--------+ | |
| 2904 // CALLEE | new out| 6 Empty on Intel, window on Sparc | |
| 2905 // | new |preserve| Must be even-aligned. | |
| 2906 // | SP-+--------+----> Matcher::_new_SP, even aligned | |
| 2907 // | | | | |
| 2908 // | |
| 2909 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is | |
| 2910 // known from SELF's arguments and the Java calling convention. | |
| 2911 // Region 6-7 is determined per call site. | |
| 2912 // Note 2: If the calling convention leaves holes in the incoming argument | |
| 2913 // area, those holes are owned by SELF. Holes in the outgoing area | |
| 2914 // are owned by the CALLEE. Holes should not be nessecary in the | |
| 2915 // incoming area, as the Java calling convention is completely under | |
| 2916 // the control of the AD file. Doubles can be sorted and packed to | |
| 2917 // avoid holes. Holes in the outgoing arguments may be nessecary for | |
| 2918 // varargs C calling conventions. | |
| 2919 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is | |
| 2920 // even aligned with pad0 as needed. | |
| 2921 // Region 6 is even aligned. Region 6-7 is NOT even aligned; | |
| 2922 // region 6-11 is even aligned; it may be padded out more so that | |
| 2923 // the region from SP to FP meets the minimum stack alignment. | |
| 2924 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack | |
| 2925 // alignment. Region 11, pad1, may be dynamically extended so that | |
| 2926 // SP meets the minimum alignment. | |
| 2927 | |
| 2928 frame | |
| 2929 %{ | |
| 2930 // What direction does stack grow in (assumed to be same for C & Java) | |
| 2931 stack_direction(TOWARDS_LOW); | |
| 2932 | |
| 2933 // These three registers define part of the calling convention | |
| 2934 // between compiled code and the interpreter. | |
| 2935 inline_cache_reg(RAX); // Inline Cache Register | |
| 2936 interpreter_method_oop_reg(RBX); // Method Oop Register when | |
| 2937 // calling interpreter | |
| 2938 | |
| 2939 // Optional: name the operand used by cisc-spilling to access | |
| 2940 // [stack_pointer + offset] | |
| 2941 cisc_spilling_operand_name(indOffset32); | |
| 2942 | |
| 2943 // Number of stack slots consumed by locking an object | |
| 2944 sync_stack_slots(2); | |
| 2945 | |
| 2946 // Compiled code's Frame Pointer | |
| 2947 frame_pointer(RSP); | |
| 2948 | |
| 2949 // Interpreter stores its frame pointer in a register which is | |
| 2950 // stored to the stack by I2CAdaptors. | |
| 2951 // I2CAdaptors convert from interpreted java to compiled java. | |
| 2952 interpreter_frame_pointer(RBP); | |
| 2953 | |
| 2954 // Stack alignment requirement | |
| 2955 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes) | |
| 2956 | |
| 2957 // Number of stack slots between incoming argument block and the start of | |
| 2958 // a new frame. The PROLOG must add this many slots to the stack. The | |
| 2959 // EPILOG must remove this many slots. amd64 needs two slots for | |
| 2960 // return address. | |
| 2961 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls); | |
| 2962 | |
| 2963 // Number of outgoing stack slots killed above the out_preserve_stack_slots | |
| 2964 // for calls to C. Supports the var-args backing area for register parms. | |
| 2965 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt); | |
| 2966 | |
| 2967 // The after-PROLOG location of the return address. Location of | |
| 2968 // return address specifies a type (REG or STACK) and a number | |
| 2969 // representing the register number (i.e. - use a register name) or | |
| 2970 // stack slot. | |
| 2971 // Ret Addr is on stack in slot 0 if no locks or verification or alignment. | |
| 2972 // Otherwise, it is above the locks and verification slot and alignment word | |
| 2973 return_addr(STACK - 2 + | |
| 4950 | 2974 round_to((Compile::current()->in_preserve_stack_slots() + |
| 2975 Compile::current()->fixed_slots()), | |
| 2976 stack_alignment_in_slots())); | |
| 0 | 2977 |
| 2978 // Body of function which returns an integer array locating | |
| 2979 // arguments either in registers or in stack slots. Passed an array | |
| 2980 // of ideal registers called "sig" and a "length" count. Stack-slot | |
| 2981 // offsets are based on outgoing arguments, i.e. a CALLER setting up | |
| 2982 // arguments for a CALLEE. Incoming stack arguments are | |
| 2983 // automatically biased by the preserve_stack_slots field above. | |
| 2984 | |
| 2985 calling_convention | |
| 2986 %{ | |
| 2987 // No difference between ingoing/outgoing just pass false | |
| 2988 SharedRuntime::java_calling_convention(sig_bt, regs, length, false); | |
| 2989 %} | |
| 2990 | |
| 2991 c_calling_convention | |
| 2992 %{ | |
| 2993 // This is obviously always outgoing | |
| 2994 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); | |
| 2995 %} | |
| 2996 | |
| 2997 // Location of compiled Java return values. Same as C for now. | |
| 2998 return_value | |
| 2999 %{ | |
| 3000 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, | |
| 3001 "only return normal values"); | |
| 3002 | |
| 3003 static const int lo[Op_RegL + 1] = { | |
| 3004 0, | |
| 3005 0, | |
|
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3006 RAX_num, // Op_RegN |
| 0 | 3007 RAX_num, // Op_RegI |
| 3008 RAX_num, // Op_RegP | |
| 3009 XMM0_num, // Op_RegF | |
| 3010 XMM0_num, // Op_RegD | |
| 3011 RAX_num // Op_RegL | |
| 3012 }; | |
| 3013 static const int hi[Op_RegL + 1] = { | |
| 3014 0, | |
| 3015 0, | |
|
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3016 OptoReg::Bad, // Op_RegN |
| 0 | 3017 OptoReg::Bad, // Op_RegI |
| 3018 RAX_H_num, // Op_RegP | |
| 3019 OptoReg::Bad, // Op_RegF | |
|
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3020 XMM0b_num, // Op_RegD |
| 0 | 3021 RAX_H_num // Op_RegL |
| 3022 }; | |
|
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3023 // Excluded flags and vector registers. |
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3024 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 5, "missing type"); |
| 0 | 3025 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]); |
| 3026 %} | |
| 3027 %} | |
| 3028 | |
| 3029 //----------ATTRIBUTES--------------------------------------------------------- | |
| 3030 //----------Operand Attributes------------------------------------------------- | |
| 3031 op_attrib op_cost(0); // Required cost attribute | |
| 3032 | |
| 3033 //----------Instruction Attributes--------------------------------------------- | |
| 3034 ins_attrib ins_cost(100); // Required cost attribute | |
| 3035 ins_attrib ins_size(8); // Required size attribute (in bits) | |
| 3036 ins_attrib ins_short_branch(0); // Required flag: is this instruction | |
| 3037 // a non-matching short branch variant | |
| 3038 // of some long branch? | |
| 3039 ins_attrib ins_alignment(1); // Required alignment attribute (must | |
| 3040 // be a power of 2) specifies the | |
| 3041 // alignment that some part of the | |
| 3042 // instruction (not necessarily the | |
| 3043 // start) requires. If > 1, a | |
| 3044 // compute_padding() function must be | |
| 3045 // provided for the instruction | |
| 3046 | |
| 3047 //----------OPERANDS----------------------------------------------------------- | |
| 3048 // Operand definitions must precede instruction definitions for correct parsing | |
| 3049 // in the ADLC because operands constitute user defined types which are used in | |
| 3050 // instruction definitions. | |
| 3051 | |
| 3052 //----------Simple Operands---------------------------------------------------- | |
| 3053 // Immediate Operands | |
| 3054 // Integer Immediate | |
| 3055 operand immI() | |
| 3056 %{ | |
| 3057 match(ConI); | |
| 3058 | |
| 3059 op_cost(10); | |
| 3060 format %{ %} | |
| 3061 interface(CONST_INTER); | |
| 3062 %} | |
| 3063 | |
| 3064 // Constant for test vs zero | |
| 3065 operand immI0() | |
| 3066 %{ | |
| 3067 predicate(n->get_int() == 0); | |
| 3068 match(ConI); | |
| 3069 | |
| 3070 op_cost(0); | |
| 3071 format %{ %} | |
| 3072 interface(CONST_INTER); | |
| 3073 %} | |
| 3074 | |
| 3075 // Constant for increment | |
| 3076 operand immI1() | |
| 3077 %{ | |
| 3078 predicate(n->get_int() == 1); | |
| 3079 match(ConI); | |
| 3080 | |
| 3081 op_cost(0); | |
| 3082 format %{ %} | |
| 3083 interface(CONST_INTER); | |
| 3084 %} | |
| 3085 | |
| 3086 // Constant for decrement | |
| 3087 operand immI_M1() | |
| 3088 %{ | |
| 3089 predicate(n->get_int() == -1); | |
| 3090 match(ConI); | |
| 3091 | |
| 3092 op_cost(0); | |
| 3093 format %{ %} | |
| 3094 interface(CONST_INTER); | |
| 3095 %} | |
| 3096 | |
| 3097 // Valid scale values for addressing modes | |
| 3098 operand immI2() | |
| 3099 %{ | |
| 3100 predicate(0 <= n->get_int() && (n->get_int() <= 3)); | |
| 3101 match(ConI); | |
| 3102 | |
| 3103 format %{ %} | |
| 3104 interface(CONST_INTER); | |
| 3105 %} | |
| 3106 | |
| 3107 operand immI8() | |
| 3108 %{ | |
| 3109 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80)); | |
| 3110 match(ConI); | |
| 3111 | |
| 3112 op_cost(5); | |
| 3113 format %{ %} | |
| 3114 interface(CONST_INTER); | |
| 3115 %} | |
| 3116 | |
| 3117 operand immI16() | |
| 3118 %{ | |
| 3119 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767)); | |
| 3120 match(ConI); | |
| 3121 | |
| 3122 op_cost(10); | |
| 3123 format %{ %} | |
| 3124 interface(CONST_INTER); | |
| 3125 %} | |
| 3126 | |
| 3127 // Constant for long shifts | |
| 3128 operand immI_32() | |
| 3129 %{ | |
| 3130 predicate( n->get_int() == 32 ); | |
| 3131 match(ConI); | |
| 3132 | |
| 3133 op_cost(0); | |
| 3134 format %{ %} | |
| 3135 interface(CONST_INTER); | |
| 3136 %} | |
| 3137 | |
| 3138 // Constant for long shifts | |
| 3139 operand immI_64() | |
| 3140 %{ | |
| 3141 predicate( n->get_int() == 64 ); | |
| 3142 match(ConI); | |
| 3143 | |
| 3144 op_cost(0); | |
| 3145 format %{ %} | |
| 3146 interface(CONST_INTER); | |
| 3147 %} | |
| 3148 | |
| 3149 // Pointer Immediate | |
| 3150 operand immP() | |
| 3151 %{ | |
| 3152 match(ConP); | |
| 3153 | |
| 3154 op_cost(10); | |
| 3155 format %{ %} | |
| 3156 interface(CONST_INTER); | |
| 3157 %} | |
| 3158 | |
| 3159 // NULL Pointer Immediate | |
| 3160 operand immP0() | |
| 3161 %{ | |
| 3162 predicate(n->get_ptr() == 0); | |
| 3163 match(ConP); | |
| 3164 | |
| 3165 op_cost(5); | |
| 3166 format %{ %} | |
| 3167 interface(CONST_INTER); | |
| 3168 %} | |
| 3169 | |
|
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3170 // Pointer Immediate |
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3171 operand immN() %{ |
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3172 match(ConN); |
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3173 |
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3174 op_cost(10); |
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3175 format %{ %} |
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3176 interface(CONST_INTER); |
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3177 %} |
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3178 |
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3179 operand immNKlass() %{ |
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3180 match(ConNKlass); |
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3181 |
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3182 op_cost(10); |
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3183 format %{ %} |
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3184 interface(CONST_INTER); |
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3185 %} |
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3186 |
|
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3187 // NULL Pointer Immediate |
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3188 operand immN0() %{ |
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3189 predicate(n->get_narrowcon() == 0); |
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3190 match(ConN); |
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3191 |
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3192 op_cost(5); |
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3193 format %{ %} |
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3194 interface(CONST_INTER); |
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3195 %} |
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3196 |
| 0 | 3197 operand immP31() |
| 3198 %{ | |
|
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3199 predicate(n->as_Type()->type()->reloc() == relocInfo::none |
| 0 | 3200 && (n->get_ptr() >> 31) == 0); |
| 3201 match(ConP); | |
| 3202 | |
| 3203 op_cost(5); | |
| 3204 format %{ %} | |
| 3205 interface(CONST_INTER); | |
| 3206 %} | |
| 3207 | |
|
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3208 |
| 0 | 3209 // Long Immediate |
| 3210 operand immL() | |
| 3211 %{ | |
| 3212 match(ConL); | |
| 3213 | |
| 3214 op_cost(20); | |
| 3215 format %{ %} | |
| 3216 interface(CONST_INTER); | |
| 3217 %} | |
| 3218 | |
| 3219 // Long Immediate 8-bit | |
| 3220 operand immL8() | |
| 3221 %{ | |
| 3222 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L); | |
| 3223 match(ConL); | |
| 3224 | |
| 3225 op_cost(5); | |
| 3226 format %{ %} | |
| 3227 interface(CONST_INTER); | |
| 3228 %} | |
| 3229 | |
| 3230 // Long Immediate 32-bit unsigned | |
| 3231 operand immUL32() | |
| 3232 %{ | |
| 3233 predicate(n->get_long() == (unsigned int) (n->get_long())); | |
| 3234 match(ConL); | |
| 3235 | |
| 3236 op_cost(10); | |
| 3237 format %{ %} | |
| 3238 interface(CONST_INTER); | |
| 3239 %} | |
| 3240 | |
| 3241 // Long Immediate 32-bit signed | |
| 3242 operand immL32() | |
| 3243 %{ | |
| 3244 predicate(n->get_long() == (int) (n->get_long())); | |
| 3245 match(ConL); | |
| 3246 | |
| 3247 op_cost(15); | |
| 3248 format %{ %} | |
| 3249 interface(CONST_INTER); | |
| 3250 %} | |
| 3251 | |
| 3252 // Long Immediate zero | |
| 3253 operand immL0() | |
| 3254 %{ | |
| 3255 predicate(n->get_long() == 0L); | |
| 3256 match(ConL); | |
| 3257 | |
| 3258 op_cost(10); | |
| 3259 format %{ %} | |
| 3260 interface(CONST_INTER); | |
| 3261 %} | |
| 3262 | |
| 3263 // Constant for increment | |
| 3264 operand immL1() | |
| 3265 %{ | |
| 3266 predicate(n->get_long() == 1); | |
| 3267 match(ConL); | |
| 3268 | |
| 3269 format %{ %} | |
| 3270 interface(CONST_INTER); | |
| 3271 %} | |
| 3272 | |
| 3273 // Constant for decrement | |
| 3274 operand immL_M1() | |
| 3275 %{ | |
| 3276 predicate(n->get_long() == -1); | |
| 3277 match(ConL); | |
| 3278 | |
| 3279 format %{ %} | |
| 3280 interface(CONST_INTER); | |
| 3281 %} | |
| 3282 | |
| 3283 // Long Immediate: the value 10 | |
| 3284 operand immL10() | |
| 3285 %{ | |
| 3286 predicate(n->get_long() == 10); | |
| 3287 match(ConL); | |
| 3288 | |
| 3289 format %{ %} | |
| 3290 interface(CONST_INTER); | |
| 3291 %} | |
| 3292 | |
| 3293 // Long immediate from 0 to 127. | |
| 3294 // Used for a shorter form of long mul by 10. | |
| 3295 operand immL_127() | |
| 3296 %{ | |
| 3297 predicate(0 <= n->get_long() && n->get_long() < 0x80); | |
| 3298 match(ConL); | |
| 3299 | |
| 3300 op_cost(10); | |
| 3301 format %{ %} | |
| 3302 interface(CONST_INTER); | |
| 3303 %} | |
| 3304 | |
| 3305 // Long Immediate: low 32-bit mask | |
| 3306 operand immL_32bits() | |
| 3307 %{ | |
| 3308 predicate(n->get_long() == 0xFFFFFFFFL); | |
| 3309 match(ConL); | |
| 3310 op_cost(20); | |
| 3311 | |
| 3312 format %{ %} | |
| 3313 interface(CONST_INTER); | |
| 3314 %} | |
| 3315 | |
| 3316 // Float Immediate zero | |
| 3317 operand immF0() | |
| 3318 %{ | |
| 3319 predicate(jint_cast(n->getf()) == 0); | |
| 3320 match(ConF); | |
| 3321 | |
| 3322 op_cost(5); | |
| 3323 format %{ %} | |
| 3324 interface(CONST_INTER); | |
| 3325 %} | |
| 3326 | |
| 3327 // Float Immediate | |
| 3328 operand immF() | |
| 3329 %{ | |
| 3330 match(ConF); | |
| 3331 | |
| 3332 op_cost(15); | |
| 3333 format %{ %} | |
| 3334 interface(CONST_INTER); | |
| 3335 %} | |
| 3336 | |
| 3337 // Double Immediate zero | |
| 3338 operand immD0() | |
| 3339 %{ | |
| 3340 predicate(jlong_cast(n->getd()) == 0); | |
| 3341 match(ConD); | |
| 3342 | |
| 3343 op_cost(5); | |
| 3344 format %{ %} | |
| 3345 interface(CONST_INTER); | |
| 3346 %} | |
| 3347 | |
| 3348 // Double Immediate | |
| 3349 operand immD() | |
| 3350 %{ | |
| 3351 match(ConD); | |
| 3352 | |
| 3353 op_cost(15); | |
| 3354 format %{ %} | |
| 3355 interface(CONST_INTER); | |
| 3356 %} | |
| 3357 | |
| 3358 // Immediates for special shifts (sign extend) | |
| 3359 | |
| 3360 // Constants for increment | |
| 3361 operand immI_16() | |
| 3362 %{ | |
| 3363 predicate(n->get_int() == 16); | |
| 3364 match(ConI); | |
| 3365 | |
| 3366 format %{ %} | |
| 3367 interface(CONST_INTER); | |
| 3368 %} | |
| 3369 | |
| 3370 operand immI_24() | |
| 3371 %{ | |
| 3372 predicate(n->get_int() == 24); | |
| 3373 match(ConI); | |
| 3374 | |
| 3375 format %{ %} | |
| 3376 interface(CONST_INTER); | |
| 3377 %} | |
| 3378 | |
| 3379 // Constant for byte-wide masking | |
| 3380 operand immI_255() | |
| 3381 %{ | |
| 3382 predicate(n->get_int() == 255); | |
| 3383 match(ConI); | |
| 3384 | |
| 3385 format %{ %} | |
| 3386 interface(CONST_INTER); | |
| 3387 %} | |
| 3388 | |
| 3389 // Constant for short-wide masking | |
| 3390 operand immI_65535() | |
| 3391 %{ | |
| 3392 predicate(n->get_int() == 65535); | |
| 3393 match(ConI); | |
| 3394 | |
| 3395 format %{ %} | |
| 3396 interface(CONST_INTER); | |
| 3397 %} | |
| 3398 | |
| 3399 // Constant for byte-wide masking | |
| 3400 operand immL_255() | |
| 3401 %{ | |
| 3402 predicate(n->get_long() == 255); | |
| 3403 match(ConL); | |
| 3404 | |
| 3405 format %{ %} | |
| 3406 interface(CONST_INTER); | |
| 3407 %} | |
| 3408 | |
| 3409 // Constant for short-wide masking | |
| 3410 operand immL_65535() | |
| 3411 %{ | |
| 3412 predicate(n->get_long() == 65535); | |
| 3413 match(ConL); | |
| 3414 | |
| 3415 format %{ %} | |
| 3416 interface(CONST_INTER); | |
| 3417 %} | |
| 3418 | |
| 3419 // Register Operands | |
| 3420 // Integer Register | |
| 3421 operand rRegI() | |
| 3422 %{ | |
| 3423 constraint(ALLOC_IN_RC(int_reg)); | |
| 3424 match(RegI); | |
| 3425 | |
| 3426 match(rax_RegI); | |
| 3427 match(rbx_RegI); | |
| 3428 match(rcx_RegI); | |
| 3429 match(rdx_RegI); | |
| 3430 match(rdi_RegI); | |
| 3431 | |
| 3432 format %{ %} | |
| 3433 interface(REG_INTER); | |
| 3434 %} | |
| 3435 | |
| 3436 // Special Registers | |
| 3437 operand rax_RegI() | |
| 3438 %{ | |
| 3439 constraint(ALLOC_IN_RC(int_rax_reg)); | |
| 3440 match(RegI); | |
| 3441 match(rRegI); | |
| 3442 | |
| 3443 format %{ "RAX" %} | |
| 3444 interface(REG_INTER); | |
| 3445 %} | |
| 3446 | |
| 3447 // Special Registers | |
| 3448 operand rbx_RegI() | |
| 3449 %{ | |
| 3450 constraint(ALLOC_IN_RC(int_rbx_reg)); | |
| 3451 match(RegI); | |
| 3452 match(rRegI); | |
| 3453 | |
| 3454 format %{ "RBX" %} | |
| 3455 interface(REG_INTER); | |
| 3456 %} | |
| 3457 | |
| 3458 operand rcx_RegI() | |
| 3459 %{ | |
| 3460 constraint(ALLOC_IN_RC(int_rcx_reg)); | |
| 3461 match(RegI); | |
| 3462 match(rRegI); | |
| 3463 | |
| 3464 format %{ "RCX" %} | |
| 3465 interface(REG_INTER); | |
| 3466 %} | |
| 3467 | |
| 3468 operand rdx_RegI() | |
| 3469 %{ | |
| 3470 constraint(ALLOC_IN_RC(int_rdx_reg)); | |
| 3471 match(RegI); | |
| 3472 match(rRegI); | |
| 3473 | |
| 3474 format %{ "RDX" %} | |
| 3475 interface(REG_INTER); | |
| 3476 %} | |
| 3477 | |
| 3478 operand rdi_RegI() | |
| 3479 %{ | |
| 3480 constraint(ALLOC_IN_RC(int_rdi_reg)); | |
| 3481 match(RegI); | |
| 3482 match(rRegI); | |
| 3483 | |
| 3484 format %{ "RDI" %} | |
| 3485 interface(REG_INTER); | |
| 3486 %} | |
| 3487 | |
| 3488 operand no_rcx_RegI() | |
| 3489 %{ | |
| 3490 constraint(ALLOC_IN_RC(int_no_rcx_reg)); | |
| 3491 match(RegI); | |
| 3492 match(rax_RegI); | |
| 3493 match(rbx_RegI); | |
| 3494 match(rdx_RegI); | |
| 3495 match(rdi_RegI); | |
| 3496 | |
| 3497 format %{ %} | |
| 3498 interface(REG_INTER); | |
| 3499 %} | |
| 3500 | |
| 3501 operand no_rax_rdx_RegI() | |
| 3502 %{ | |
| 3503 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg)); | |
| 3504 match(RegI); | |
| 3505 match(rbx_RegI); | |
| 3506 match(rcx_RegI); | |
| 3507 match(rdi_RegI); | |
| 3508 | |
| 3509 format %{ %} | |
| 3510 interface(REG_INTER); | |
| 3511 %} | |
| 3512 | |
| 3513 // Pointer Register | |
| 3514 operand any_RegP() | |
| 3515 %{ | |
| 3516 constraint(ALLOC_IN_RC(any_reg)); | |
| 3517 match(RegP); | |
| 3518 match(rax_RegP); | |
| 3519 match(rbx_RegP); | |
| 3520 match(rdi_RegP); | |
| 3521 match(rsi_RegP); | |
| 3522 match(rbp_RegP); | |
| 3523 match(r15_RegP); | |
| 3524 match(rRegP); | |
| 3525 | |
| 3526 format %{ %} | |
| 3527 interface(REG_INTER); | |
| 3528 %} | |
| 3529 | |
| 3530 operand rRegP() | |
| 3531 %{ | |
| 3532 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3533 match(RegP); | |
| 3534 match(rax_RegP); | |
| 3535 match(rbx_RegP); | |
| 3536 match(rdi_RegP); | |
| 3537 match(rsi_RegP); | |
| 3538 match(rbp_RegP); | |
| 3539 match(r15_RegP); // See Q&A below about r15_RegP. | |
| 3540 | |
| 3541 format %{ %} | |
| 3542 interface(REG_INTER); | |
| 3543 %} | |
| 3544 | |
|
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3545 operand rRegN() %{ |
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3546 constraint(ALLOC_IN_RC(int_reg)); |
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3547 match(RegN); |
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3548 |
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3549 format %{ %} |
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3550 interface(REG_INTER); |
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3551 %} |
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3552 |
| 0 | 3553 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP? |
| 3554 // Answer: Operand match rules govern the DFA as it processes instruction inputs. | |
| 3555 // It's fine for an instruction input which expects rRegP to match a r15_RegP. | |
| 3556 // The output of an instruction is controlled by the allocator, which respects | |
| 3557 // register class masks, not match rules. Unless an instruction mentions | |
| 3558 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered | |
| 3559 // by the allocator as an input. | |
| 3560 | |
| 3561 operand no_rax_RegP() | |
| 3562 %{ | |
| 3563 constraint(ALLOC_IN_RC(ptr_no_rax_reg)); | |
| 3564 match(RegP); | |
| 3565 match(rbx_RegP); | |
| 3566 match(rsi_RegP); | |
| 3567 match(rdi_RegP); | |
| 3568 | |
| 3569 format %{ %} | |
| 3570 interface(REG_INTER); | |
| 3571 %} | |
| 3572 | |
| 3573 operand no_rbp_RegP() | |
| 3574 %{ | |
| 3575 constraint(ALLOC_IN_RC(ptr_no_rbp_reg)); | |
| 3576 match(RegP); | |
| 3577 match(rbx_RegP); | |
| 3578 match(rsi_RegP); | |
| 3579 match(rdi_RegP); | |
| 3580 | |
| 3581 format %{ %} | |
| 3582 interface(REG_INTER); | |
| 3583 %} | |
| 3584 | |
| 3585 operand no_rax_rbx_RegP() | |
| 3586 %{ | |
| 3587 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg)); | |
| 3588 match(RegP); | |
| 3589 match(rsi_RegP); | |
| 3590 match(rdi_RegP); | |
| 3591 | |
| 3592 format %{ %} | |
| 3593 interface(REG_INTER); | |
| 3594 %} | |
| 3595 | |
| 3596 // Special Registers | |
| 3597 // Return a pointer value | |
| 3598 operand rax_RegP() | |
| 3599 %{ | |
| 3600 constraint(ALLOC_IN_RC(ptr_rax_reg)); | |
| 3601 match(RegP); | |
| 3602 match(rRegP); | |
| 3603 | |
| 3604 format %{ %} | |
| 3605 interface(REG_INTER); | |
| 3606 %} | |
| 3607 | |
|
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3608 // Special Registers |
|
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3609 // Return a compressed pointer value |
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3610 operand rax_RegN() |
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3611 %{ |
|
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3612 constraint(ALLOC_IN_RC(int_rax_reg)); |
|
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3613 match(RegN); |
|
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|
3614 match(rRegN); |
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|
3615 |
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|
3616 format %{ %} |
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3617 interface(REG_INTER); |
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3618 %} |
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|
3619 |
| 0 | 3620 // Used in AtomicAdd |
| 3621 operand rbx_RegP() | |
| 3622 %{ | |
| 3623 constraint(ALLOC_IN_RC(ptr_rbx_reg)); | |
| 3624 match(RegP); | |
| 3625 match(rRegP); | |
| 3626 | |
| 3627 format %{ %} | |
| 3628 interface(REG_INTER); | |
| 3629 %} | |
| 3630 | |
| 3631 operand rsi_RegP() | |
| 3632 %{ | |
| 3633 constraint(ALLOC_IN_RC(ptr_rsi_reg)); | |
| 3634 match(RegP); | |
| 3635 match(rRegP); | |
| 3636 | |
| 3637 format %{ %} | |
| 3638 interface(REG_INTER); | |
| 3639 %} | |
| 3640 | |
| 3641 // Used in rep stosq | |
| 3642 operand rdi_RegP() | |
| 3643 %{ | |
| 3644 constraint(ALLOC_IN_RC(ptr_rdi_reg)); | |
| 3645 match(RegP); | |
| 3646 match(rRegP); | |
| 3647 | |
| 3648 format %{ %} | |
| 3649 interface(REG_INTER); | |
| 3650 %} | |
| 3651 | |
| 3652 operand rbp_RegP() | |
| 3653 %{ | |
| 3654 constraint(ALLOC_IN_RC(ptr_rbp_reg)); | |
| 3655 match(RegP); | |
| 3656 match(rRegP); | |
| 3657 | |
| 3658 format %{ %} | |
| 3659 interface(REG_INTER); | |
| 3660 %} | |
| 3661 | |
| 3662 operand r15_RegP() | |
| 3663 %{ | |
| 3664 constraint(ALLOC_IN_RC(ptr_r15_reg)); | |
| 3665 match(RegP); | |
| 3666 match(rRegP); | |
| 3667 | |
| 3668 format %{ %} | |
| 3669 interface(REG_INTER); | |
| 3670 %} | |
| 3671 | |
| 3672 operand rRegL() | |
| 3673 %{ | |
| 3674 constraint(ALLOC_IN_RC(long_reg)); | |
| 3675 match(RegL); | |
| 3676 match(rax_RegL); | |
| 3677 match(rdx_RegL); | |
| 3678 | |
| 3679 format %{ %} | |
| 3680 interface(REG_INTER); | |
| 3681 %} | |
| 3682 | |
| 3683 // Special Registers | |
| 3684 operand no_rax_rdx_RegL() | |
| 3685 %{ | |
| 3686 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg)); | |
| 3687 match(RegL); | |
| 3688 match(rRegL); | |
| 3689 | |
| 3690 format %{ %} | |
| 3691 interface(REG_INTER); | |
| 3692 %} | |
| 3693 | |
| 3694 operand no_rax_RegL() | |
| 3695 %{ | |
| 3696 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg)); | |
| 3697 match(RegL); | |
| 3698 match(rRegL); | |
| 3699 match(rdx_RegL); | |
| 3700 | |
| 3701 format %{ %} | |
| 3702 interface(REG_INTER); | |
| 3703 %} | |
| 3704 | |
| 3705 operand no_rcx_RegL() | |
| 3706 %{ | |
| 3707 constraint(ALLOC_IN_RC(long_no_rcx_reg)); | |
| 3708 match(RegL); | |
| 3709 match(rRegL); | |
| 3710 | |
| 3711 format %{ %} | |
| 3712 interface(REG_INTER); | |
| 3713 %} | |
| 3714 | |
| 3715 operand rax_RegL() | |
| 3716 %{ | |
| 3717 constraint(ALLOC_IN_RC(long_rax_reg)); | |
| 3718 match(RegL); | |
| 3719 match(rRegL); | |
| 3720 | |
| 3721 format %{ "RAX" %} | |
| 3722 interface(REG_INTER); | |
| 3723 %} | |
| 3724 | |
| 3725 operand rcx_RegL() | |
| 3726 %{ | |
| 3727 constraint(ALLOC_IN_RC(long_rcx_reg)); | |
| 3728 match(RegL); | |
| 3729 match(rRegL); | |
| 3730 | |
| 3731 format %{ %} | |
| 3732 interface(REG_INTER); | |
| 3733 %} | |
| 3734 | |
| 3735 operand rdx_RegL() | |
| 3736 %{ | |
| 3737 constraint(ALLOC_IN_RC(long_rdx_reg)); | |
| 3738 match(RegL); | |
| 3739 match(rRegL); | |
| 3740 | |
| 3741 format %{ %} | |
| 3742 interface(REG_INTER); | |
| 3743 %} | |
| 3744 | |
| 3745 // Flags register, used as output of compare instructions | |
| 3746 operand rFlagsReg() | |
| 3747 %{ | |
| 3748 constraint(ALLOC_IN_RC(int_flags)); | |
| 3749 match(RegFlags); | |
| 3750 | |
| 3751 format %{ "RFLAGS" %} | |
| 3752 interface(REG_INTER); | |
| 3753 %} | |
| 3754 | |
| 3755 // Flags register, used as output of FLOATING POINT compare instructions | |
| 3756 operand rFlagsRegU() | |
| 3757 %{ | |
| 3758 constraint(ALLOC_IN_RC(int_flags)); | |
| 3759 match(RegFlags); | |
| 3760 | |
| 3761 format %{ "RFLAGS_U" %} | |
| 3762 interface(REG_INTER); | |
| 3763 %} | |
| 3764 | |
|
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3765 operand rFlagsRegUCF() %{ |
|
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|
3766 constraint(ALLOC_IN_RC(int_flags)); |
|
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|
3767 match(RegFlags); |
|
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|
3768 predicate(false); |
|
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|
3769 |
|
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|
3770 format %{ "RFLAGS_U_CF" %} |
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|
3771 interface(REG_INTER); |
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|
3772 %} |
|
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|
3773 |
| 0 | 3774 // Float register operands |
| 3775 operand regF() | |
| 3776 %{ | |
| 3777 constraint(ALLOC_IN_RC(float_reg)); | |
| 3778 match(RegF); | |
| 3779 | |
| 3780 format %{ %} | |
| 3781 interface(REG_INTER); | |
| 3782 %} | |
| 3783 | |
| 3784 // Double register operands | |
|
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|
3785 operand regD() |
| 0 | 3786 %{ |
| 3787 constraint(ALLOC_IN_RC(double_reg)); | |
| 3788 match(RegD); | |
| 3789 | |
| 3790 format %{ %} | |
| 3791 interface(REG_INTER); | |
| 3792 %} | |
| 3793 | |
| 3794 //----------Memory Operands---------------------------------------------------- | |
| 3795 // Direct Memory Operand | |
| 3796 // operand direct(immP addr) | |
| 3797 // %{ | |
| 3798 // match(addr); | |
| 3799 | |
| 3800 // format %{ "[$addr]" %} | |
| 3801 // interface(MEMORY_INTER) %{ | |
| 3802 // base(0xFFFFFFFF); | |
| 3803 // index(0x4); | |
| 3804 // scale(0x0); | |
| 3805 // disp($addr); | |
| 3806 // %} | |
| 3807 // %} | |
| 3808 | |
| 3809 // Indirect Memory Operand | |
| 3810 operand indirect(any_RegP reg) | |
| 3811 %{ | |
| 3812 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3813 match(reg); | |
| 3814 | |
| 3815 format %{ "[$reg]" %} | |
| 3816 interface(MEMORY_INTER) %{ | |
| 3817 base($reg); | |
| 3818 index(0x4); | |
| 3819 scale(0x0); | |
| 3820 disp(0x0); | |
| 3821 %} | |
| 3822 %} | |
| 3823 | |
| 3824 // Indirect Memory Plus Short Offset Operand | |
| 3825 operand indOffset8(any_RegP reg, immL8 off) | |
| 3826 %{ | |
| 3827 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3828 match(AddP reg off); | |
| 3829 | |
| 3830 format %{ "[$reg + $off (8-bit)]" %} | |
| 3831 interface(MEMORY_INTER) %{ | |
| 3832 base($reg); | |
| 3833 index(0x4); | |
| 3834 scale(0x0); | |
| 3835 disp($off); | |
| 3836 %} | |
| 3837 %} | |
| 3838 | |
| 3839 // Indirect Memory Plus Long Offset Operand | |
| 3840 operand indOffset32(any_RegP reg, immL32 off) | |
| 3841 %{ | |
| 3842 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3843 match(AddP reg off); | |
| 3844 | |
| 3845 format %{ "[$reg + $off (32-bit)]" %} | |
| 3846 interface(MEMORY_INTER) %{ | |
| 3847 base($reg); | |
| 3848 index(0x4); | |
| 3849 scale(0x0); | |
| 3850 disp($off); | |
| 3851 %} | |
| 3852 %} | |
| 3853 | |
| 3854 // Indirect Memory Plus Index Register Plus Offset Operand | |
| 3855 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off) | |
| 3856 %{ | |
| 3857 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3858 match(AddP (AddP reg lreg) off); | |
| 3859 | |
| 3860 op_cost(10); | |
| 3861 format %{"[$reg + $off + $lreg]" %} | |
| 3862 interface(MEMORY_INTER) %{ | |
| 3863 base($reg); | |
| 3864 index($lreg); | |
| 3865 scale(0x0); | |
| 3866 disp($off); | |
| 3867 %} | |
| 3868 %} | |
| 3869 | |
| 3870 // Indirect Memory Plus Index Register Plus Offset Operand | |
| 3871 operand indIndex(any_RegP reg, rRegL lreg) | |
| 3872 %{ | |
| 3873 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3874 match(AddP reg lreg); | |
| 3875 | |
| 3876 op_cost(10); | |
| 3877 format %{"[$reg + $lreg]" %} | |
| 3878 interface(MEMORY_INTER) %{ | |
| 3879 base($reg); | |
| 3880 index($lreg); | |
| 3881 scale(0x0); | |
| 3882 disp(0x0); | |
| 3883 %} | |
| 3884 %} | |
| 3885 | |
| 3886 // Indirect Memory Times Scale Plus Index Register | |
| 3887 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale) | |
| 3888 %{ | |
| 3889 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3890 match(AddP reg (LShiftL lreg scale)); | |
| 3891 | |
| 3892 op_cost(10); | |
| 3893 format %{"[$reg + $lreg << $scale]" %} | |
| 3894 interface(MEMORY_INTER) %{ | |
| 3895 base($reg); | |
| 3896 index($lreg); | |
| 3897 scale($scale); | |
| 3898 disp(0x0); | |
| 3899 %} | |
| 3900 %} | |
| 3901 | |
| 3902 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand | |
| 3903 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale) | |
| 3904 %{ | |
| 3905 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3906 match(AddP (AddP reg (LShiftL lreg scale)) off); | |
| 3907 | |
| 3908 op_cost(10); | |
| 3909 format %{"[$reg + $off + $lreg << $scale]" %} | |
| 3910 interface(MEMORY_INTER) %{ | |
| 3911 base($reg); | |
| 3912 index($lreg); | |
| 3913 scale($scale); | |
| 3914 disp($off); | |
| 3915 %} | |
| 3916 %} | |
| 3917 | |
| 3918 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand | |
| 3919 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale) | |
| 3920 %{ | |
| 3921 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3922 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0); | |
| 3923 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off); | |
| 3924 | |
| 3925 op_cost(10); | |
| 3926 format %{"[$reg + $off + $idx << $scale]" %} | |
| 3927 interface(MEMORY_INTER) %{ | |
| 3928 base($reg); | |
| 3929 index($idx); | |
| 3930 scale($scale); | |
| 3931 disp($off); | |
| 3932 %} | |
| 3933 %} | |
| 3934 | |
|
642
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3935 // Indirect Narrow Oop Plus Offset Operand |
|
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|
3936 // Note: x86 architecture doesn't support "scale * index + offset" without a base |
|
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3937 // we can't free r12 even with Universe::narrow_oop_base() == NULL. |
|
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|
3938 operand indCompressedOopOffset(rRegN reg, immL32 off) %{ |
|
1571
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|
3939 predicate(UseCompressedOops && (Universe::narrow_oop_shift() == Address::times_8)); |
|
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|
3940 constraint(ALLOC_IN_RC(ptr_reg)); |
|
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|
3941 match(AddP (DecodeN reg) off); |
|
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|
3942 |
|
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|
3943 op_cost(10); |
|
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|
3944 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %} |
|
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|
3945 interface(MEMORY_INTER) %{ |
|
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|
3946 base(0xc); // R12 |
|
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3947 index($reg); |
|
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|
3948 scale(0x3); |
|
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|
3949 disp($off); |
|
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|
3950 %} |
|
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|
3951 %} |
|
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|
3952 |
|
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|
3953 // Indirect Memory Operand |
|
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3954 operand indirectNarrow(rRegN reg) |
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|
3955 %{ |
|
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|
3956 predicate(Universe::narrow_oop_shift() == 0); |
|
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|
3957 constraint(ALLOC_IN_RC(ptr_reg)); |
|
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|
3958 match(DecodeN reg); |
|
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|
3959 |
|
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|
3960 format %{ "[$reg]" %} |
|
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|
3961 interface(MEMORY_INTER) %{ |
|
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|
3962 base($reg); |
|
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|
3963 index(0x4); |
|
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|
3964 scale(0x0); |
|
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|
3965 disp(0x0); |
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|
3966 %} |
|
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|
3967 %} |
|
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|
3968 |
|
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|
3969 // Indirect Memory Plus Short Offset Operand |
|
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|
3970 operand indOffset8Narrow(rRegN reg, immL8 off) |
|
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|
3971 %{ |
|
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|
3972 predicate(Universe::narrow_oop_shift() == 0); |
|
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|
3973 constraint(ALLOC_IN_RC(ptr_reg)); |
|
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3974 match(AddP (DecodeN reg) off); |
|
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|
3975 |
|
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changeset
|
3976 format %{ "[$reg + $off (8-bit)]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3977 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3978 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3979 index(0x4); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3980 scale(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3981 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3982 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3983 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3984 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3985 // Indirect Memory Plus Long Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3986 operand indOffset32Narrow(rRegN reg, immL32 off) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3987 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3988 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3989 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3990 match(AddP (DecodeN reg) off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3991 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3992 format %{ "[$reg + $off (32-bit)]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3993 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3994 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3995 index(0x4); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3996 scale(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3997 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3998 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3999 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4000 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4001 // Indirect Memory Plus Index Register Plus Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4002 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4003 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4004 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4005 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4006 match(AddP (AddP (DecodeN reg) lreg) off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4007 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4008 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4009 format %{"[$reg + $off + $lreg]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4010 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4011 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4012 index($lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4013 scale(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4014 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4015 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4016 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4017 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4018 // Indirect Memory Plus Index Register Plus Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4019 operand indIndexNarrow(rRegN reg, rRegL lreg) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4020 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4021 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4022 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4023 match(AddP (DecodeN reg) lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4024 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4025 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4026 format %{"[$reg + $lreg]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4027 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4028 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4029 index($lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4030 scale(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4031 disp(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4032 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4033 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4034 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4035 // Indirect Memory Times Scale Plus Index Register |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4036 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4037 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4038 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4039 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4040 match(AddP (DecodeN reg) (LShiftL lreg scale)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4041 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4042 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4043 format %{"[$reg + $lreg << $scale]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4044 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4045 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4046 index($lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4047 scale($scale); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4048 disp(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4049 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4050 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4051 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4052 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4053 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4054 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4055 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4056 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4057 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4058 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4059 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4060 format %{"[$reg + $off + $lreg << $scale]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4061 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4062 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4063 index($lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4064 scale($scale); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4065 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4066 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4067 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4068 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4069 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4070 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4071 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4072 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4073 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4074 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4075 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4076 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4077 format %{"[$reg + $off + $idx << $scale]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4078 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4079 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4080 index($idx); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4081 scale($scale); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4082 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4083 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4084 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4085 |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4086 operand indirectNarrowKlass(rRegN reg) |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4087 %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4088 predicate(Universe::narrow_klass_shift() == 0); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4089 constraint(ALLOC_IN_RC(ptr_reg)); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4090 match(DecodeNKlass reg); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4091 |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4092 format %{ "[$reg]" %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4093 interface(MEMORY_INTER) %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4094 base($reg); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4095 index(0x4); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4096 scale(0x0); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4097 disp(0x0); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4098 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4099 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4100 |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4101 operand indOffset8NarrowKlass(rRegN reg, immL8 off) |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4102 %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4103 predicate(Universe::narrow_klass_shift() == 0); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4104 constraint(ALLOC_IN_RC(ptr_reg)); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4105 match(AddP (DecodeNKlass reg) off); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4106 |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4107 format %{ "[$reg + $off (8-bit)]" %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4108 interface(MEMORY_INTER) %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4109 base($reg); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4110 index(0x4); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4111 scale(0x0); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4112 disp($off); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4113 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4114 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4115 |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4116 operand indOffset32NarrowKlass(rRegN reg, immL32 off) |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4117 %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4118 predicate(Universe::narrow_klass_shift() == 0); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4119 constraint(ALLOC_IN_RC(ptr_reg)); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4120 match(AddP (DecodeNKlass reg) off); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4121 |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4122 format %{ "[$reg + $off (32-bit)]" %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4123 interface(MEMORY_INTER) %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4124 base($reg); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4125 index(0x4); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4126 scale(0x0); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4127 disp($off); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4128 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4129 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4130 |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4131 operand indIndexOffsetNarrowKlass(rRegN reg, rRegL lreg, immL32 off) |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4132 %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4133 predicate(Universe::narrow_klass_shift() == 0); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4134 constraint(ALLOC_IN_RC(ptr_reg)); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4135 match(AddP (AddP (DecodeNKlass reg) lreg) off); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4136 |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4137 op_cost(10); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4138 format %{"[$reg + $off + $lreg]" %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4139 interface(MEMORY_INTER) %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4140 base($reg); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4141 index($lreg); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4142 scale(0x0); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4143 disp($off); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4144 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4145 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4146 |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4147 operand indIndexNarrowKlass(rRegN reg, rRegL lreg) |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4148 %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4149 predicate(Universe::narrow_klass_shift() == 0); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4150 constraint(ALLOC_IN_RC(ptr_reg)); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4151 match(AddP (DecodeNKlass reg) lreg); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4152 |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4153 op_cost(10); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4154 format %{"[$reg + $lreg]" %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4155 interface(MEMORY_INTER) %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4156 base($reg); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4157 index($lreg); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4158 scale(0x0); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4159 disp(0x0); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4160 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4161 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4162 |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4163 operand indIndexScaleNarrowKlass(rRegN reg, rRegL lreg, immI2 scale) |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4164 %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4165 predicate(Universe::narrow_klass_shift() == 0); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4166 constraint(ALLOC_IN_RC(ptr_reg)); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4167 match(AddP (DecodeNKlass reg) (LShiftL lreg scale)); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4168 |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4169 op_cost(10); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4170 format %{"[$reg + $lreg << $scale]" %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4171 interface(MEMORY_INTER) %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4172 base($reg); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4173 index($lreg); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4174 scale($scale); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4175 disp(0x0); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4176 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4177 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4178 |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4179 operand indIndexScaleOffsetNarrowKlass(rRegN reg, immL32 off, rRegL lreg, immI2 scale) |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4180 %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4181 predicate(Universe::narrow_klass_shift() == 0); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4182 constraint(ALLOC_IN_RC(ptr_reg)); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4183 match(AddP (AddP (DecodeNKlass reg) (LShiftL lreg scale)) off); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4184 |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4185 op_cost(10); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4186 format %{"[$reg + $off + $lreg << $scale]" %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4187 interface(MEMORY_INTER) %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4188 base($reg); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4189 index($lreg); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4190 scale($scale); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4191 disp($off); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4192 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4193 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4194 |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4195 operand indCompressedKlassOffset(rRegN reg, immL32 off) %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4196 predicate(UseCompressedKlassPointers && (Universe::narrow_klass_shift() == Address::times_8)); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4197 constraint(ALLOC_IN_RC(ptr_reg)); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4198 match(AddP (DecodeNKlass reg) off); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4199 |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4200 op_cost(10); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4201 format %{"[R12 + $reg << 3 + $off] (compressed klass addressing)" %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4202 interface(MEMORY_INTER) %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4203 base(0xc); // R12 |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4204 index($reg); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4205 scale(0x3); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4206 disp($off); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4207 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4208 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4209 |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4210 operand indPosIndexScaleOffsetNarrowKlass(rRegN reg, immL32 off, rRegI idx, immI2 scale) |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4211 %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4212 constraint(ALLOC_IN_RC(ptr_reg)); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4213 predicate(Universe::narrow_klass_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4214 match(AddP (AddP (DecodeNKlass reg) (LShiftL (ConvI2L idx) scale)) off); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4215 |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4216 op_cost(10); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4217 format %{"[$reg + $off + $idx << $scale]" %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4218 interface(MEMORY_INTER) %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4219 base($reg); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4220 index($idx); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4221 scale($scale); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4222 disp($off); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4223 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
4224 %} |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4225 |
| 0 | 4226 //----------Special Memory Operands-------------------------------------------- |
| 4227 // Stack Slot Operand - This operand is used for loading and storing temporary | |
| 4228 // values on the stack where a match requires a value to | |
| 4229 // flow through memory. | |
| 4230 operand stackSlotP(sRegP reg) | |
| 4231 %{ | |
| 4232 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4233 // No match rule because this operand is only generated in matching | |
| 4234 | |
| 4235 format %{ "[$reg]" %} | |
| 4236 interface(MEMORY_INTER) %{ | |
| 4237 base(0x4); // RSP | |
| 4238 index(0x4); // No Index | |
| 4239 scale(0x0); // No Scale | |
| 4240 disp($reg); // Stack Offset | |
| 4241 %} | |
| 4242 %} | |
| 4243 | |
| 4244 operand stackSlotI(sRegI reg) | |
| 4245 %{ | |
| 4246 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4247 // No match rule because this operand is only generated in matching | |
| 4248 | |
| 4249 format %{ "[$reg]" %} | |
| 4250 interface(MEMORY_INTER) %{ | |
| 4251 base(0x4); // RSP | |
| 4252 index(0x4); // No Index | |
| 4253 scale(0x0); // No Scale | |
| 4254 disp($reg); // Stack Offset | |
| 4255 %} | |
| 4256 %} | |
| 4257 | |
| 4258 operand stackSlotF(sRegF reg) | |
| 4259 %{ | |
| 4260 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4261 // No match rule because this operand is only generated in matching | |
| 4262 | |
| 4263 format %{ "[$reg]" %} | |
| 4264 interface(MEMORY_INTER) %{ | |
| 4265 base(0x4); // RSP | |
| 4266 index(0x4); // No Index | |
| 4267 scale(0x0); // No Scale | |
| 4268 disp($reg); // Stack Offset | |
| 4269 %} | |
| 4270 %} | |
| 4271 | |
| 4272 operand stackSlotD(sRegD reg) | |
| 4273 %{ | |
| 4274 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4275 // No match rule because this operand is only generated in matching | |
| 4276 | |
| 4277 format %{ "[$reg]" %} | |
| 4278 interface(MEMORY_INTER) %{ | |
| 4279 base(0x4); // RSP | |
| 4280 index(0x4); // No Index | |
| 4281 scale(0x0); // No Scale | |
| 4282 disp($reg); // Stack Offset | |
| 4283 %} | |
| 4284 %} | |
| 4285 operand stackSlotL(sRegL reg) | |
| 4286 %{ | |
| 4287 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4288 // No match rule because this operand is only generated in matching | |
| 4289 | |
| 4290 format %{ "[$reg]" %} | |
| 4291 interface(MEMORY_INTER) %{ | |
| 4292 base(0x4); // RSP | |
| 4293 index(0x4); // No Index | |
| 4294 scale(0x0); // No Scale | |
| 4295 disp($reg); // Stack Offset | |
| 4296 %} | |
| 4297 %} | |
| 4298 | |
| 4299 //----------Conditional Branch Operands---------------------------------------- | |
| 4300 // Comparison Op - This is the operation of the comparison, and is limited to | |
| 4301 // the following set of codes: | |
| 4302 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) | |
| 4303 // | |
| 4304 // Other attributes of the comparison, such as unsignedness, are specified | |
| 4305 // by the comparison instruction that sets a condition code flags register. | |
| 4306 // That result is represented by a flags operand whose subtype is appropriate | |
| 4307 // to the unsignedness (etc.) of the comparison. | |
| 4308 // | |
| 4309 // Later, the instruction which matches both the Comparison Op (a Bool) and | |
| 4310 // the flags (produced by the Cmp) specifies the coding of the comparison op | |
| 4311 // by matching a specific subtype of Bool operand below, such as cmpOpU. | |
| 4312 | |
| 4313 // Comparision Code | |
| 4314 operand cmpOp() | |
| 4315 %{ | |
| 4316 match(Bool); | |
| 4317 | |
| 4318 format %{ "" %} | |
| 4319 interface(COND_INTER) %{ | |
|
415
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|
4320 equal(0x4, "e"); |
|
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|
4321 not_equal(0x5, "ne"); |
|
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|
4322 less(0xC, "l"); |
|
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|
4323 greater_equal(0xD, "ge"); |
|
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|
4324 less_equal(0xE, "le"); |
|
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|
4325 greater(0xF, "g"); |
| 0 | 4326 %} |
| 4327 %} | |
| 4328 | |
| 4329 // Comparison Code, unsigned compare. Used by FP also, with | |
| 4330 // C2 (unordered) turned into GT or LT already. The other bits | |
| 4331 // C0 and C3 are turned into Carry & Zero flags. | |
| 4332 operand cmpOpU() | |
| 4333 %{ | |
| 4334 match(Bool); | |
| 4335 | |
| 4336 format %{ "" %} | |
| 4337 interface(COND_INTER) %{ | |
|
415
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|
4338 equal(0x4, "e"); |
|
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|
4339 not_equal(0x5, "ne"); |
|
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|
4340 less(0x2, "b"); |
|
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|
4341 greater_equal(0x3, "nb"); |
|
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|
4342 less_equal(0x6, "be"); |
|
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|
4343 greater(0x7, "nbe"); |
|
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|
4344 %} |
|
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|
4345 %} |
|
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|
4346 |
|
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changeset
|
4347 |
|
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|
4348 // Floating comparisons that don't require any fixup for the unordered case |
|
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|
4349 operand cmpOpUCF() %{ |
|
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|
4350 match(Bool); |
|
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|
4351 predicate(n->as_Bool()->_test._test == BoolTest::lt || |
|
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|
4352 n->as_Bool()->_test._test == BoolTest::ge || |
|
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|
4353 n->as_Bool()->_test._test == BoolTest::le || |
|
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|
4354 n->as_Bool()->_test._test == BoolTest::gt); |
|
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|
4355 format %{ "" %} |
|
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diff
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|
4356 interface(COND_INTER) %{ |
|
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diff
changeset
|
4357 equal(0x4, "e"); |
|
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diff
changeset
|
4358 not_equal(0x5, "ne"); |
|
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diff
changeset
|
4359 less(0x2, "b"); |
|
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diff
changeset
|
4360 greater_equal(0x3, "nb"); |
|
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changeset
|
4361 less_equal(0x6, "be"); |
|
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|
4362 greater(0x7, "nbe"); |
|
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|
4363 %} |
|
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|
4364 %} |
|
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|
4365 |
|
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|
4366 |
|
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|
4367 // Floating comparisons that can be fixed up with extra conditional jumps |
|
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|
4368 operand cmpOpUCF2() %{ |
|
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|
4369 match(Bool); |
|
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|
4370 predicate(n->as_Bool()->_test._test == BoolTest::ne || |
|
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|
4371 n->as_Bool()->_test._test == BoolTest::eq); |
|
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|
4372 format %{ "" %} |
|
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|
4373 interface(COND_INTER) %{ |
|
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|
4374 equal(0x4, "e"); |
|
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|
4375 not_equal(0x5, "ne"); |
|
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|
4376 less(0x2, "b"); |
|
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|
4377 greater_equal(0x3, "nb"); |
|
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|
4378 less_equal(0x6, "be"); |
|
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|
4379 greater(0x7, "nbe"); |
| 0 | 4380 %} |
| 4381 %} | |
| 4382 | |
| 4383 | |
| 4384 //----------OPERAND CLASSES---------------------------------------------------- | |
| 4385 // Operand Classes are groups of operands that are used as to simplify | |
| 605 | 4386 // instruction definitions by not requiring the AD writer to specify separate |
| 0 | 4387 // instructions for every form of operand when the instruction accepts |
| 4388 // multiple operand types with the same basic encoding and format. The classic | |
| 4389 // case of this is memory operands. | |
| 4390 | |
| 4391 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex, | |
|
113
ba764ed4b6f2
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diff
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|
4392 indIndexScale, indIndexScaleOffset, indPosIndexScaleOffset, |
|
642
660978a2a31a
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kvn
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624
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|
4393 indCompressedOopOffset, |
|
660978a2a31a
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|
4394 indirectNarrow, indOffset8Narrow, indOffset32Narrow, |
|
660978a2a31a
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|
4395 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow, |
|
6848
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|
4396 indIndexScaleOffsetNarrow, indPosIndexScaleOffsetNarrow, |
|
8e47bac5643a
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diff
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|
4397 indCompressedKlassOffset, |
|
8e47bac5643a
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|
4398 indirectNarrowKlass, indOffset8NarrowKlass, indOffset32NarrowKlass, |
|
8e47bac5643a
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|
4399 indIndexOffsetNarrowKlass, indIndexNarrowKlass, indIndexScaleNarrowKlass, |
|
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|
4400 indIndexScaleOffsetNarrowKlass, indPosIndexScaleOffsetNarrowKlass); |
| 0 | 4401 |
| 4402 //----------PIPELINE----------------------------------------------------------- | |
| 4403 // Rules which define the behavior of the target architectures pipeline. | |
| 4404 pipeline %{ | |
| 4405 | |
| 4406 //----------ATTRIBUTES--------------------------------------------------------- | |
| 4407 attributes %{ | |
| 4408 variable_size_instructions; // Fixed size instructions | |
| 4409 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle | |
| 4410 instruction_unit_size = 1; // An instruction is 1 bytes long | |
| 4411 instruction_fetch_unit_size = 16; // The processor fetches one line | |
| 4412 instruction_fetch_units = 1; // of 16 bytes | |
| 4413 | |
| 4414 // List of nop instructions | |
| 4415 nops( MachNop ); | |
| 4416 %} | |
| 4417 | |
| 4418 //----------RESOURCES---------------------------------------------------------- | |
| 4419 // Resources are the functional units available to the machine | |
| 4420 | |
| 4421 // Generic P2/P3 pipeline | |
| 4422 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of | |
| 4423 // 3 instructions decoded per cycle. | |
| 4424 // 2 load/store ops per cycle, 1 branch, 1 FPU, | |
| 4425 // 3 ALU op, only ALU0 handles mul instructions. | |
| 4426 resources( D0, D1, D2, DECODE = D0 | D1 | D2, | |
| 4427 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2, | |
| 4428 BR, FPU, | |
| 4429 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2); | |
| 4430 | |
| 4431 //----------PIPELINE DESCRIPTION----------------------------------------------- | |
| 4432 // Pipeline Description specifies the stages in the machine's pipeline | |
| 4433 | |
| 4434 // Generic P2/P3 pipeline | |
| 4435 pipe_desc(S0, S1, S2, S3, S4, S5); | |
| 4436 | |
| 4437 //----------PIPELINE CLASSES--------------------------------------------------- | |
| 4438 // Pipeline Classes describe the stages in which input and output are | |
| 4439 // referenced by the hardware pipeline. | |
| 4440 | |
| 4441 // Naming convention: ialu or fpu | |
| 4442 // Then: _reg | |
| 4443 // Then: _reg if there is a 2nd register | |
| 4444 // Then: _long if it's a pair of instructions implementing a long | |
| 4445 // Then: _fat if it requires the big decoder | |
| 4446 // Or: _mem if it requires the big decoder and a memory unit. | |
| 4447 | |
| 4448 // Integer ALU reg operation | |
| 4449 pipe_class ialu_reg(rRegI dst) | |
| 4450 %{ | |
| 4451 single_instruction; | |
| 4452 dst : S4(write); | |
| 4453 dst : S3(read); | |
| 4454 DECODE : S0; // any decoder | |
| 4455 ALU : S3; // any alu | |
| 4456 %} | |
| 4457 | |
| 4458 // Long ALU reg operation | |
| 4459 pipe_class ialu_reg_long(rRegL dst) | |
| 4460 %{ | |
| 4461 instruction_count(2); | |
| 4462 dst : S4(write); | |
| 4463 dst : S3(read); | |
| 4464 DECODE : S0(2); // any 2 decoders | |
| 4465 ALU : S3(2); // both alus | |
| 4466 %} | |
| 4467 | |
| 4468 // Integer ALU reg operation using big decoder | |
| 4469 pipe_class ialu_reg_fat(rRegI dst) | |
| 4470 %{ | |
| 4471 single_instruction; | |
| 4472 dst : S4(write); | |
| 4473 dst : S3(read); | |
| 4474 D0 : S0; // big decoder only | |
| 4475 ALU : S3; // any alu | |
| 4476 %} | |
| 4477 | |
| 4478 // Long ALU reg operation using big decoder | |
| 4479 pipe_class ialu_reg_long_fat(rRegL dst) | |
| 4480 %{ | |
| 4481 instruction_count(2); | |
| 4482 dst : S4(write); | |
| 4483 dst : S3(read); | |
| 4484 D0 : S0(2); // big decoder only; twice | |
| 4485 ALU : S3(2); // any 2 alus | |
| 4486 %} | |
| 4487 | |
| 4488 // Integer ALU reg-reg operation | |
| 4489 pipe_class ialu_reg_reg(rRegI dst, rRegI src) | |
| 4490 %{ | |
| 4491 single_instruction; | |
| 4492 dst : S4(write); | |
| 4493 src : S3(read); | |
| 4494 DECODE : S0; // any decoder | |
| 4495 ALU : S3; // any alu | |
| 4496 %} | |
| 4497 | |
| 4498 // Long ALU reg-reg operation | |
| 4499 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src) | |
| 4500 %{ | |
| 4501 instruction_count(2); | |
| 4502 dst : S4(write); | |
| 4503 src : S3(read); | |
| 4504 DECODE : S0(2); // any 2 decoders | |
| 4505 ALU : S3(2); // both alus | |
| 4506 %} | |
| 4507 | |
| 4508 // Integer ALU reg-reg operation | |
| 4509 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) | |
| 4510 %{ | |
| 4511 single_instruction; | |
| 4512 dst : S4(write); | |
| 4513 src : S3(read); | |
| 4514 D0 : S0; // big decoder only | |
| 4515 ALU : S3; // any alu | |
| 4516 %} | |
| 4517 | |
| 4518 // Long ALU reg-reg operation | |
| 4519 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src) | |
| 4520 %{ | |
| 4521 instruction_count(2); | |
| 4522 dst : S4(write); | |
| 4523 src : S3(read); | |
| 4524 D0 : S0(2); // big decoder only; twice | |
| 4525 ALU : S3(2); // both alus | |
| 4526 %} | |
| 4527 | |
| 4528 // Integer ALU reg-mem operation | |
| 4529 pipe_class ialu_reg_mem(rRegI dst, memory mem) | |
| 4530 %{ | |
| 4531 single_instruction; | |
| 4532 dst : S5(write); | |
| 4533 mem : S3(read); | |
| 4534 D0 : S0; // big decoder only | |
| 4535 ALU : S4; // any alu | |
| 4536 MEM : S3; // any mem | |
| 4537 %} | |
| 4538 | |
| 4539 // Integer mem operation (prefetch) | |
| 4540 pipe_class ialu_mem(memory mem) | |
| 4541 %{ | |
| 4542 single_instruction; | |
| 4543 mem : S3(read); | |
| 4544 D0 : S0; // big decoder only | |
| 4545 MEM : S3; // any mem | |
| 4546 %} | |
| 4547 | |
| 4548 // Integer Store to Memory | |
| 4549 pipe_class ialu_mem_reg(memory mem, rRegI src) | |
| 4550 %{ | |
| 4551 single_instruction; | |
| 4552 mem : S3(read); | |
| 4553 src : S5(read); | |
| 4554 D0 : S0; // big decoder only | |
| 4555 ALU : S4; // any alu | |
| 4556 MEM : S3; | |
| 4557 %} | |
| 4558 | |
| 4559 // // Long Store to Memory | |
| 4560 // pipe_class ialu_mem_long_reg(memory mem, rRegL src) | |
| 4561 // %{ | |
| 4562 // instruction_count(2); | |
| 4563 // mem : S3(read); | |
| 4564 // src : S5(read); | |
| 4565 // D0 : S0(2); // big decoder only; twice | |
| 4566 // ALU : S4(2); // any 2 alus | |
| 4567 // MEM : S3(2); // Both mems | |
| 4568 // %} | |
| 4569 | |
| 4570 // Integer Store to Memory | |
| 4571 pipe_class ialu_mem_imm(memory mem) | |
| 4572 %{ | |
| 4573 single_instruction; | |
| 4574 mem : S3(read); | |
| 4575 D0 : S0; // big decoder only | |
| 4576 ALU : S4; // any alu | |
| 4577 MEM : S3; | |
| 4578 %} | |
| 4579 | |
| 4580 // Integer ALU0 reg-reg operation | |
| 4581 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) | |
| 4582 %{ | |
| 4583 single_instruction; | |
| 4584 dst : S4(write); | |
| 4585 src : S3(read); | |
| 4586 D0 : S0; // Big decoder only | |
| 4587 ALU0 : S3; // only alu0 | |
| 4588 %} | |
| 4589 | |
| 4590 // Integer ALU0 reg-mem operation | |
| 4591 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) | |
| 4592 %{ | |
| 4593 single_instruction; | |
| 4594 dst : S5(write); | |
| 4595 mem : S3(read); | |
| 4596 D0 : S0; // big decoder only | |
| 4597 ALU0 : S4; // ALU0 only | |
| 4598 MEM : S3; // any mem | |
| 4599 %} | |
| 4600 | |
| 4601 // Integer ALU reg-reg operation | |
| 4602 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2) | |
| 4603 %{ | |
| 4604 single_instruction; | |
| 4605 cr : S4(write); | |
| 4606 src1 : S3(read); | |
| 4607 src2 : S3(read); | |
| 4608 DECODE : S0; // any decoder | |
| 4609 ALU : S3; // any alu | |
| 4610 %} | |
| 4611 | |
| 4612 // Integer ALU reg-imm operation | |
| 4613 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1) | |
| 4614 %{ | |
| 4615 single_instruction; | |
| 4616 cr : S4(write); | |
| 4617 src1 : S3(read); | |
| 4618 DECODE : S0; // any decoder | |
| 4619 ALU : S3; // any alu | |
| 4620 %} | |
| 4621 | |
| 4622 // Integer ALU reg-mem operation | |
| 4623 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2) | |
| 4624 %{ | |
| 4625 single_instruction; | |
| 4626 cr : S4(write); | |
| 4627 src1 : S3(read); | |
| 4628 src2 : S3(read); | |
| 4629 D0 : S0; // big decoder only | |
| 4630 ALU : S4; // any alu | |
| 4631 MEM : S3; | |
| 4632 %} | |
| 4633 | |
| 4634 // Conditional move reg-reg | |
| 4635 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y) | |
| 4636 %{ | |
| 4637 instruction_count(4); | |
| 4638 y : S4(read); | |
| 4639 q : S3(read); | |
| 4640 p : S3(read); | |
| 4641 DECODE : S0(4); // any decoder | |
| 4642 %} | |
| 4643 | |
| 4644 // Conditional move reg-reg | |
| 4645 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr) | |
| 4646 %{ | |
| 4647 single_instruction; | |
| 4648 dst : S4(write); | |
| 4649 src : S3(read); | |
| 4650 cr : S3(read); | |
| 4651 DECODE : S0; // any decoder | |
| 4652 %} | |
| 4653 | |
| 4654 // Conditional move reg-mem | |
| 4655 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src) | |
| 4656 %{ | |
| 4657 single_instruction; | |
| 4658 dst : S4(write); | |
| 4659 src : S3(read); | |
| 4660 cr : S3(read); | |
| 4661 DECODE : S0; // any decoder | |
| 4662 MEM : S3; | |
| 4663 %} | |
| 4664 | |
| 4665 // Conditional move reg-reg long | |
| 4666 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src) | |
| 4667 %{ | |
| 4668 single_instruction; | |
| 4669 dst : S4(write); | |
| 4670 src : S3(read); | |
| 4671 cr : S3(read); | |
| 4672 DECODE : S0(2); // any 2 decoders | |
| 4673 %} | |
| 4674 | |
| 4675 // XXX | |
| 4676 // // Conditional move double reg-reg | |
| 4677 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src) | |
| 4678 // %{ | |
| 4679 // single_instruction; | |
| 4680 // dst : S4(write); | |
| 4681 // src : S3(read); | |
| 4682 // cr : S3(read); | |
| 4683 // DECODE : S0; // any decoder | |
| 4684 // %} | |
| 4685 | |
| 4686 // Float reg-reg operation | |
| 4687 pipe_class fpu_reg(regD dst) | |
| 4688 %{ | |
| 4689 instruction_count(2); | |
| 4690 dst : S3(read); | |
| 4691 DECODE : S0(2); // any 2 decoders | |
| 4692 FPU : S3; | |
| 4693 %} | |
| 4694 | |
| 4695 // Float reg-reg operation | |
| 4696 pipe_class fpu_reg_reg(regD dst, regD src) | |
| 4697 %{ | |
| 4698 instruction_count(2); | |
| 4699 dst : S4(write); | |
| 4700 src : S3(read); | |
| 4701 DECODE : S0(2); // any 2 decoders | |
| 4702 FPU : S3; | |
| 4703 %} | |
| 4704 | |
| 4705 // Float reg-reg operation | |
| 4706 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2) | |
| 4707 %{ | |
| 4708 instruction_count(3); | |
| 4709 dst : S4(write); | |
| 4710 src1 : S3(read); | |
| 4711 src2 : S3(read); | |
| 4712 DECODE : S0(3); // any 3 decoders | |
| 4713 FPU : S3(2); | |
| 4714 %} | |
| 4715 | |
| 4716 // Float reg-reg operation | |
| 4717 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3) | |
| 4718 %{ | |
| 4719 instruction_count(4); | |
| 4720 dst : S4(write); | |
| 4721 src1 : S3(read); | |
| 4722 src2 : S3(read); | |
| 4723 src3 : S3(read); | |
| 4724 DECODE : S0(4); // any 3 decoders | |
| 4725 FPU : S3(2); | |
| 4726 %} | |
| 4727 | |
| 4728 // Float reg-reg operation | |
| 4729 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3) | |
| 4730 %{ | |
| 4731 instruction_count(4); | |
| 4732 dst : S4(write); | |
| 4733 src1 : S3(read); | |
| 4734 src2 : S3(read); | |
| 4735 src3 : S3(read); | |
| 4736 DECODE : S1(3); // any 3 decoders | |
| 4737 D0 : S0; // Big decoder only | |
| 4738 FPU : S3(2); | |
| 4739 MEM : S3; | |
| 4740 %} | |
| 4741 | |
| 4742 // Float reg-mem operation | |
| 4743 pipe_class fpu_reg_mem(regD dst, memory mem) | |
| 4744 %{ | |
| 4745 instruction_count(2); | |
| 4746 dst : S5(write); | |
| 4747 mem : S3(read); | |
| 4748 D0 : S0; // big decoder only | |
| 4749 DECODE : S1; // any decoder for FPU POP | |
| 4750 FPU : S4; | |
| 4751 MEM : S3; // any mem | |
| 4752 %} | |
| 4753 | |
| 4754 // Float reg-mem operation | |
| 4755 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem) | |
| 4756 %{ | |
| 4757 instruction_count(3); | |
| 4758 dst : S5(write); | |
| 4759 src1 : S3(read); | |
| 4760 mem : S3(read); | |
| 4761 D0 : S0; // big decoder only | |
| 4762 DECODE : S1(2); // any decoder for FPU POP | |
| 4763 FPU : S4; | |
| 4764 MEM : S3; // any mem | |
| 4765 %} | |
| 4766 | |
| 4767 // Float mem-reg operation | |
| 4768 pipe_class fpu_mem_reg(memory mem, regD src) | |
| 4769 %{ | |
| 4770 instruction_count(2); | |
| 4771 src : S5(read); | |
| 4772 mem : S3(read); | |
| 4773 DECODE : S0; // any decoder for FPU PUSH | |
| 4774 D0 : S1; // big decoder only | |
| 4775 FPU : S4; | |
| 4776 MEM : S3; // any mem | |
| 4777 %} | |
| 4778 | |
| 4779 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2) | |
| 4780 %{ | |
| 4781 instruction_count(3); | |
| 4782 src1 : S3(read); | |
| 4783 src2 : S3(read); | |
| 4784 mem : S3(read); | |
| 4785 DECODE : S0(2); // any decoder for FPU PUSH | |
| 4786 D0 : S1; // big decoder only | |
| 4787 FPU : S4; | |
| 4788 MEM : S3; // any mem | |
| 4789 %} | |
| 4790 | |
| 4791 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2) | |
| 4792 %{ | |
| 4793 instruction_count(3); | |
| 4794 src1 : S3(read); | |
| 4795 src2 : S3(read); | |
| 4796 mem : S4(read); | |
| 4797 DECODE : S0; // any decoder for FPU PUSH | |
| 4798 D0 : S0(2); // big decoder only | |
| 4799 FPU : S4; | |
| 4800 MEM : S3(2); // any mem | |
| 4801 %} | |
| 4802 | |
| 4803 pipe_class fpu_mem_mem(memory dst, memory src1) | |
| 4804 %{ | |
| 4805 instruction_count(2); | |
| 4806 src1 : S3(read); | |
| 4807 dst : S4(read); | |
| 4808 D0 : S0(2); // big decoder only | |
| 4809 MEM : S3(2); // any mem | |
| 4810 %} | |
| 4811 | |
| 4812 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) | |
| 4813 %{ | |
| 4814 instruction_count(3); | |
| 4815 src1 : S3(read); | |
| 4816 src2 : S3(read); | |
| 4817 dst : S4(read); | |
| 4818 D0 : S0(3); // big decoder only | |
| 4819 FPU : S4; | |
| 4820 MEM : S3(3); // any mem | |
| 4821 %} | |
| 4822 | |
| 4823 pipe_class fpu_mem_reg_con(memory mem, regD src1) | |
| 4824 %{ | |
| 4825 instruction_count(3); | |
| 4826 src1 : S4(read); | |
| 4827 mem : S4(read); | |
| 4828 DECODE : S0; // any decoder for FPU PUSH | |
| 4829 D0 : S0(2); // big decoder only | |
| 4830 FPU : S4; | |
| 4831 MEM : S3(2); // any mem | |
| 4832 %} | |
| 4833 | |
| 4834 // Float load constant | |
| 4835 pipe_class fpu_reg_con(regD dst) | |
| 4836 %{ | |
| 4837 instruction_count(2); | |
| 4838 dst : S5(write); | |
| 4839 D0 : S0; // big decoder only for the load | |
| 4840 DECODE : S1; // any decoder for FPU POP | |
| 4841 FPU : S4; | |
| 4842 MEM : S3; // any mem | |
| 4843 %} | |
| 4844 | |
| 4845 // Float load constant | |
| 4846 pipe_class fpu_reg_reg_con(regD dst, regD src) | |
| 4847 %{ | |
| 4848 instruction_count(3); | |
| 4849 dst : S5(write); | |
| 4850 src : S3(read); | |
| 4851 D0 : S0; // big decoder only for the load | |
| 4852 DECODE : S1(2); // any decoder for FPU POP | |
| 4853 FPU : S4; | |
| 4854 MEM : S3; // any mem | |
| 4855 %} | |
| 4856 | |
| 4857 // UnConditional branch | |
| 4858 pipe_class pipe_jmp(label labl) | |
| 4859 %{ | |
| 4860 single_instruction; | |
| 4861 BR : S3; | |
| 4862 %} | |
| 4863 | |
| 4864 // Conditional branch | |
| 4865 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl) | |
| 4866 %{ | |
| 4867 single_instruction; | |
| 4868 cr : S1(read); | |
| 4869 BR : S3; | |
| 4870 %} | |
| 4871 | |
| 4872 // Allocation idiom | |
| 4873 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr) | |
| 4874 %{ | |
| 4875 instruction_count(1); force_serialization; | |
| 4876 fixed_latency(6); | |
| 4877 heap_ptr : S3(read); | |
| 4878 DECODE : S0(3); | |
| 4879 D0 : S2; | |
| 4880 MEM : S3; | |
| 4881 ALU : S3(2); | |
| 4882 dst : S5(write); | |
| 4883 BR : S5; | |
| 4884 %} | |
| 4885 | |
| 4886 // Generic big/slow expanded idiom | |
| 4887 pipe_class pipe_slow() | |
| 4888 %{ | |
| 4889 instruction_count(10); multiple_bundles; force_serialization; | |
| 4890 fixed_latency(100); | |
| 4891 D0 : S0(2); | |
| 4892 MEM : S3(2); | |
| 4893 %} | |
| 4894 | |
| 4895 // The real do-nothing guy | |
| 4896 pipe_class empty() | |
| 4897 %{ | |
| 4898 instruction_count(0); | |
| 4899 %} | |
| 4900 | |
| 4901 // Define the class for the Nop node | |
| 4902 define | |
| 4903 %{ | |
| 4904 MachNop = empty; | |
| 4905 %} | |
| 4906 | |
| 4907 %} | |
| 4908 | |
| 4909 //----------INSTRUCTIONS------------------------------------------------------- | |
| 4910 // | |
| 4911 // match -- States which machine-independent subtree may be replaced | |
| 4912 // by this instruction. | |
| 4913 // ins_cost -- The estimated cost of this instruction is used by instruction | |
| 4914 // selection to identify a minimum cost tree of machine | |
| 4915 // instructions that matches a tree of machine-independent | |
| 4916 // instructions. | |
| 4917 // format -- A string providing the disassembly for this instruction. | |
| 4918 // The value of an instruction's operand may be inserted | |
| 4919 // by referring to it with a '$' prefix. | |
| 4920 // opcode -- Three instruction opcodes may be provided. These are referred | |
| 4921 // to within an encode class as $primary, $secondary, and $tertiary | |
| 4922 // rrspectively. The primary opcode is commonly used to | |
| 4923 // indicate the type of machine instruction, while secondary | |
| 4924 // and tertiary are often used for prefix options or addressing | |
| 4925 // modes. | |
| 4926 // ins_encode -- A list of encode classes with parameters. The encode class | |
| 4927 // name must have been defined in an 'enc_class' specification | |
| 4928 // in the encode section of the architecture description. | |
| 4929 | |
| 4930 | |
| 4931 //----------Load/Store/Move Instructions--------------------------------------- | |
| 4932 //----------Load Instructions-------------------------------------------------- | |
| 4933 | |
| 4934 // Load Byte (8 bit signed) | |
| 4935 instruct loadB(rRegI dst, memory mem) | |
| 4936 %{ | |
| 4937 match(Set dst (LoadB mem)); | |
| 4938 | |
| 4939 ins_cost(125); | |
| 4940 format %{ "movsbl $dst, $mem\t# byte" %} | |
| 624 | 4941 |
| 4942 ins_encode %{ | |
| 4943 __ movsbl($dst$$Register, $mem$$Address); | |
| 4944 %} | |
| 4945 | |
| 0 | 4946 ins_pipe(ialu_reg_mem); |
| 4947 %} | |
| 4948 | |
| 624 | 4949 // Load Byte (8 bit signed) into Long Register |
| 4950 instruct loadB2L(rRegL dst, memory mem) | |
| 4951 %{ | |
| 4952 match(Set dst (ConvI2L (LoadB mem))); | |
| 4953 | |
| 4954 ins_cost(125); | |
| 4955 format %{ "movsbq $dst, $mem\t# byte -> long" %} | |
| 4956 | |
| 4957 ins_encode %{ | |
| 4958 __ movsbq($dst$$Register, $mem$$Address); | |
| 4959 %} | |
| 4960 | |
| 4961 ins_pipe(ialu_reg_mem); | |
| 4962 %} | |
| 4963 | |
| 4964 // Load Unsigned Byte (8 bit UNsigned) | |
| 4965 instruct loadUB(rRegI dst, memory mem) | |
| 4966 %{ | |
| 4967 match(Set dst (LoadUB mem)); | |
| 0 | 4968 |
| 4969 ins_cost(125); | |
| 4970 format %{ "movzbl $dst, $mem\t# ubyte" %} | |
| 624 | 4971 |
| 4972 ins_encode %{ | |
| 4973 __ movzbl($dst$$Register, $mem$$Address); | |
| 4974 %} | |
| 4975 | |
| 0 | 4976 ins_pipe(ialu_reg_mem); |
| 4977 %} | |
| 4978 | |
| 624 | 4979 // Load Unsigned Byte (8 bit UNsigned) into Long Register |
| 4980 instruct loadUB2L(rRegL dst, memory mem) | |
| 4981 %{ | |
| 4982 match(Set dst (ConvI2L (LoadUB mem))); | |
| 4983 | |
| 4984 ins_cost(125); | |
| 4985 format %{ "movzbq $dst, $mem\t# ubyte -> long" %} | |
| 4986 | |
| 4987 ins_encode %{ | |
| 4988 __ movzbq($dst$$Register, $mem$$Address); | |
| 4989 %} | |
| 4990 | |
| 4991 ins_pipe(ialu_reg_mem); | |
| 4992 %} | |
| 0 | 4993 |
| 824 | 4994 // Load Unsigned Byte (8 bit UNsigned) with a 8-bit mask into Long Register |
| 4995 instruct loadUB2L_immI8(rRegL dst, memory mem, immI8 mask, rFlagsReg cr) %{ | |
| 4996 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); | |
| 4997 effect(KILL cr); | |
| 4998 | |
| 4999 format %{ "movzbq $dst, $mem\t# ubyte & 8-bit mask -> long\n\t" | |
| 5000 "andl $dst, $mask" %} | |
| 5001 ins_encode %{ | |
| 5002 Register Rdst = $dst$$Register; | |
| 5003 __ movzbq(Rdst, $mem$$Address); | |
| 5004 __ andl(Rdst, $mask$$constant); | |
| 5005 %} | |
| 5006 ins_pipe(ialu_reg_mem); | |
| 5007 %} | |
| 5008 | |
| 0 | 5009 // Load Short (16 bit signed) |
| 5010 instruct loadS(rRegI dst, memory mem) | |
| 5011 %{ | |
| 5012 match(Set dst (LoadS mem)); | |
| 5013 | |
| 624 | 5014 ins_cost(125); |
| 0 | 5015 format %{ "movswl $dst, $mem\t# short" %} |
| 624 | 5016 |
| 5017 ins_encode %{ | |
| 5018 __ movswl($dst$$Register, $mem$$Address); | |
| 5019 %} | |
| 5020 | |
| 0 | 5021 ins_pipe(ialu_reg_mem); |
| 5022 %} | |
| 5023 | |
| 785 | 5024 // Load Short (16 bit signed) to Byte (8 bit signed) |
| 5025 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{ | |
| 5026 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); | |
| 5027 | |
| 5028 ins_cost(125); | |
| 5029 format %{ "movsbl $dst, $mem\t# short -> byte" %} | |
| 5030 ins_encode %{ | |
| 5031 __ movsbl($dst$$Register, $mem$$Address); | |
| 5032 %} | |
| 5033 ins_pipe(ialu_reg_mem); | |
| 5034 %} | |
| 5035 | |
| 624 | 5036 // Load Short (16 bit signed) into Long Register |
| 5037 instruct loadS2L(rRegL dst, memory mem) | |
| 5038 %{ | |
| 5039 match(Set dst (ConvI2L (LoadS mem))); | |
| 5040 | |
| 5041 ins_cost(125); | |
| 5042 format %{ "movswq $dst, $mem\t# short -> long" %} | |
| 5043 | |
| 5044 ins_encode %{ | |
| 5045 __ movswq($dst$$Register, $mem$$Address); | |
| 5046 %} | |
| 5047 | |
| 5048 ins_pipe(ialu_reg_mem); | |
| 5049 %} | |
| 0 | 5050 |
|
558
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|
5051 // Load Unsigned Short/Char (16 bit UNsigned) |
|
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
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diff
changeset
|
5052 instruct loadUS(rRegI dst, memory mem) |
|
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents:
420
diff
changeset
|
5053 %{ |
|
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents:
420
diff
changeset
|
5054 match(Set dst (LoadUS mem)); |
| 0 | 5055 |
| 5056 ins_cost(125); | |
|
558
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6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
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parents:
420
diff
changeset
|
5057 format %{ "movzwl $dst, $mem\t# ushort/char" %} |
| 624 | 5058 |
| 5059 ins_encode %{ | |
| 5060 __ movzwl($dst$$Register, $mem$$Address); | |
| 5061 %} | |
| 5062 | |
| 0 | 5063 ins_pipe(ialu_reg_mem); |
| 5064 %} | |
| 5065 | |
| 785 | 5066 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) |
| 5067 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{ | |
| 5068 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); | |
| 5069 | |
| 5070 ins_cost(125); | |
| 5071 format %{ "movsbl $dst, $mem\t# ushort -> byte" %} | |
| 5072 ins_encode %{ | |
| 5073 __ movsbl($dst$$Register, $mem$$Address); | |
| 5074 %} | |
| 5075 ins_pipe(ialu_reg_mem); | |
| 5076 %} | |
| 5077 | |
| 624 | 5078 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register |
| 5079 instruct loadUS2L(rRegL dst, memory mem) | |
| 5080 %{ | |
| 5081 match(Set dst (ConvI2L (LoadUS mem))); | |
| 5082 | |
| 5083 ins_cost(125); | |
| 5084 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %} | |
| 5085 | |
| 5086 ins_encode %{ | |
| 5087 __ movzwq($dst$$Register, $mem$$Address); | |
| 5088 %} | |
| 5089 | |
| 5090 ins_pipe(ialu_reg_mem); | |
| 5091 %} | |
| 0 | 5092 |
| 824 | 5093 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register |
| 5094 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{ | |
| 5095 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5096 | |
| 5097 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %} | |
| 5098 ins_encode %{ | |
| 5099 __ movzbq($dst$$Register, $mem$$Address); | |
| 5100 %} | |
| 5101 ins_pipe(ialu_reg_mem); | |
| 5102 %} | |
| 5103 | |
| 5104 // Load Unsigned Short/Char (16 bit UNsigned) with mask into Long Register | |
| 5105 instruct loadUS2L_immI16(rRegL dst, memory mem, immI16 mask, rFlagsReg cr) %{ | |
| 5106 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5107 effect(KILL cr); | |
| 5108 | |
| 5109 format %{ "movzwq $dst, $mem\t# ushort/char & 16-bit mask -> long\n\t" | |
| 5110 "andl $dst, $mask" %} | |
| 5111 ins_encode %{ | |
| 5112 Register Rdst = $dst$$Register; | |
| 5113 __ movzwq(Rdst, $mem$$Address); | |
| 5114 __ andl(Rdst, $mask$$constant); | |
| 5115 %} | |
| 5116 ins_pipe(ialu_reg_mem); | |
| 5117 %} | |
| 5118 | |
| 0 | 5119 // Load Integer |
| 5120 instruct loadI(rRegI dst, memory mem) | |
| 5121 %{ | |
| 5122 match(Set dst (LoadI mem)); | |
| 5123 | |
| 624 | 5124 ins_cost(125); |
| 0 | 5125 format %{ "movl $dst, $mem\t# int" %} |
| 624 | 5126 |
| 5127 ins_encode %{ | |
| 5128 __ movl($dst$$Register, $mem$$Address); | |
| 5129 %} | |
| 5130 | |
| 5131 ins_pipe(ialu_reg_mem); | |
| 5132 %} | |
| 5133 | |
| 785 | 5134 // Load Integer (32 bit signed) to Byte (8 bit signed) |
| 5135 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{ | |
| 5136 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); | |
| 5137 | |
| 5138 ins_cost(125); | |
| 5139 format %{ "movsbl $dst, $mem\t# int -> byte" %} | |
| 5140 ins_encode %{ | |
| 5141 __ movsbl($dst$$Register, $mem$$Address); | |
| 5142 %} | |
| 5143 ins_pipe(ialu_reg_mem); | |
| 5144 %} | |
| 5145 | |
| 5146 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned) | |
| 5147 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{ | |
| 5148 match(Set dst (AndI (LoadI mem) mask)); | |
| 5149 | |
| 5150 ins_cost(125); | |
| 5151 format %{ "movzbl $dst, $mem\t# int -> ubyte" %} | |
| 5152 ins_encode %{ | |
| 5153 __ movzbl($dst$$Register, $mem$$Address); | |
| 5154 %} | |
| 5155 ins_pipe(ialu_reg_mem); | |
| 5156 %} | |
| 5157 | |
| 5158 // Load Integer (32 bit signed) to Short (16 bit signed) | |
| 5159 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{ | |
| 5160 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); | |
| 5161 | |
| 5162 ins_cost(125); | |
| 5163 format %{ "movswl $dst, $mem\t# int -> short" %} | |
| 5164 ins_encode %{ | |
| 5165 __ movswl($dst$$Register, $mem$$Address); | |
| 5166 %} | |
| 5167 ins_pipe(ialu_reg_mem); | |
| 5168 %} | |
| 5169 | |
| 5170 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned) | |
| 5171 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{ | |
| 5172 match(Set dst (AndI (LoadI mem) mask)); | |
| 5173 | |
| 5174 ins_cost(125); | |
| 5175 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %} | |
| 5176 ins_encode %{ | |
| 5177 __ movzwl($dst$$Register, $mem$$Address); | |
| 5178 %} | |
| 5179 ins_pipe(ialu_reg_mem); | |
| 5180 %} | |
| 5181 | |
| 624 | 5182 // Load Integer into Long Register |
| 5183 instruct loadI2L(rRegL dst, memory mem) | |
| 5184 %{ | |
| 5185 match(Set dst (ConvI2L (LoadI mem))); | |
| 5186 | |
| 5187 ins_cost(125); | |
| 5188 format %{ "movslq $dst, $mem\t# int -> long" %} | |
| 5189 | |
| 5190 ins_encode %{ | |
| 5191 __ movslq($dst$$Register, $mem$$Address); | |
| 5192 %} | |
| 5193 | |
| 5194 ins_pipe(ialu_reg_mem); | |
| 5195 %} | |
| 5196 | |
| 824 | 5197 // Load Integer with mask 0xFF into Long Register |
| 5198 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{ | |
| 5199 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5200 | |
| 5201 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %} | |
| 5202 ins_encode %{ | |
| 5203 __ movzbq($dst$$Register, $mem$$Address); | |
| 5204 %} | |
| 5205 ins_pipe(ialu_reg_mem); | |
| 5206 %} | |
| 5207 | |
| 5208 // Load Integer with mask 0xFFFF into Long Register | |
| 5209 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{ | |
| 5210 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5211 | |
| 5212 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %} | |
| 5213 ins_encode %{ | |
| 5214 __ movzwq($dst$$Register, $mem$$Address); | |
| 5215 %} | |
| 5216 ins_pipe(ialu_reg_mem); | |
| 5217 %} | |
| 5218 | |
| 5219 // Load Integer with a 32-bit mask into Long Register | |
| 5220 instruct loadI2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{ | |
| 5221 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5222 effect(KILL cr); | |
| 5223 | |
| 5224 format %{ "movl $dst, $mem\t# int & 32-bit mask -> long\n\t" | |
| 5225 "andl $dst, $mask" %} | |
| 5226 ins_encode %{ | |
| 5227 Register Rdst = $dst$$Register; | |
| 5228 __ movl(Rdst, $mem$$Address); | |
| 5229 __ andl(Rdst, $mask$$constant); | |
| 5230 %} | |
| 5231 ins_pipe(ialu_reg_mem); | |
| 5232 %} | |
| 5233 | |
| 624 | 5234 // Load Unsigned Integer into Long Register |
| 6849 | 5235 instruct loadUI2L(rRegL dst, memory mem, immL_32bits mask) |
| 5236 %{ | |
| 5237 match(Set dst (AndL (ConvI2L (LoadI mem)) mask)); | |
| 624 | 5238 |
| 5239 ins_cost(125); | |
| 5240 format %{ "movl $dst, $mem\t# uint -> long" %} | |
| 5241 | |
| 5242 ins_encode %{ | |
| 5243 __ movl($dst$$Register, $mem$$Address); | |
| 5244 %} | |
| 5245 | |
| 0 | 5246 ins_pipe(ialu_reg_mem); |
| 5247 %} | |
| 5248 | |
| 5249 // Load Long | |
| 5250 instruct loadL(rRegL dst, memory mem) | |
| 5251 %{ | |
| 5252 match(Set dst (LoadL mem)); | |
| 5253 | |
| 624 | 5254 ins_cost(125); |
| 0 | 5255 format %{ "movq $dst, $mem\t# long" %} |
| 624 | 5256 |
| 5257 ins_encode %{ | |
| 5258 __ movq($dst$$Register, $mem$$Address); | |
| 5259 %} | |
| 5260 | |
| 0 | 5261 ins_pipe(ialu_reg_mem); // XXX |
| 5262 %} | |
| 5263 | |
| 5264 // Load Range | |
| 5265 instruct loadRange(rRegI dst, memory mem) | |
| 5266 %{ | |
| 5267 match(Set dst (LoadRange mem)); | |
| 5268 | |
| 5269 ins_cost(125); // XXX | |
| 5270 format %{ "movl $dst, $mem\t# range" %} | |
| 5271 opcode(0x8B); | |
| 5272 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5273 ins_pipe(ialu_reg_mem); | |
| 5274 %} | |
| 5275 | |
| 5276 // Load Pointer | |
| 5277 instruct loadP(rRegP dst, memory mem) | |
| 5278 %{ | |
| 5279 match(Set dst (LoadP mem)); | |
| 5280 | |
| 5281 ins_cost(125); // XXX | |
| 5282 format %{ "movq $dst, $mem\t# ptr" %} | |
| 5283 opcode(0x8B); | |
| 5284 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5285 ins_pipe(ialu_reg_mem); // XXX | |
| 5286 %} | |
| 5287 | |
|
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5288 // Load Compressed Pointer |
| 163 | 5289 instruct loadN(rRegN dst, memory mem) |
|
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5290 %{ |
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5291 match(Set dst (LoadN mem)); |
|
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5292 |
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5293 ins_cost(125); // XXX |
|
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5294 format %{ "movl $dst, $mem\t# compressed ptr" %} |
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5295 ins_encode %{ |
|
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5296 __ movl($dst$$Register, $mem$$Address); |
|
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5297 %} |
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5298 ins_pipe(ialu_reg_mem); // XXX |
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5299 %} |
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5300 |
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5301 |
| 0 | 5302 // Load Klass Pointer |
| 5303 instruct loadKlass(rRegP dst, memory mem) | |
| 5304 %{ | |
| 5305 match(Set dst (LoadKlass mem)); | |
| 5306 | |
| 5307 ins_cost(125); // XXX | |
| 5308 format %{ "movq $dst, $mem\t# class" %} | |
| 5309 opcode(0x8B); | |
| 5310 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5311 ins_pipe(ialu_reg_mem); // XXX | |
| 5312 %} | |
| 5313 | |
|
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5314 // Load narrow Klass Pointer |
|
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5315 instruct loadNKlass(rRegN dst, memory mem) |
|
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5316 %{ |
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5317 match(Set dst (LoadNKlass mem)); |
|
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5318 |
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|
5319 ins_cost(125); // XXX |
|
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5320 format %{ "movl $dst, $mem\t# compressed klass ptr" %} |
|
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5321 ins_encode %{ |
|
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5322 __ movl($dst$$Register, $mem$$Address); |
|
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5323 %} |
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|
5324 ins_pipe(ialu_reg_mem); // XXX |
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5325 %} |
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5326 |
| 0 | 5327 // Load Float |
| 5328 instruct loadF(regF dst, memory mem) | |
| 5329 %{ | |
| 5330 match(Set dst (LoadF mem)); | |
| 5331 | |
| 5332 ins_cost(145); // XXX | |
| 5333 format %{ "movss $dst, $mem\t# float" %} | |
| 4759 | 5334 ins_encode %{ |
| 5335 __ movflt($dst$$XMMRegister, $mem$$Address); | |
| 5336 %} | |
| 0 | 5337 ins_pipe(pipe_slow); // XXX |
| 5338 %} | |
| 5339 | |
| 5340 // Load Double | |
| 5341 instruct loadD_partial(regD dst, memory mem) | |
| 5342 %{ | |
| 5343 predicate(!UseXmmLoadAndClearUpper); | |
| 5344 match(Set dst (LoadD mem)); | |
| 5345 | |
| 5346 ins_cost(145); // XXX | |
| 5347 format %{ "movlpd $dst, $mem\t# double" %} | |
| 4759 | 5348 ins_encode %{ |
| 5349 __ movdbl($dst$$XMMRegister, $mem$$Address); | |
| 5350 %} | |
| 0 | 5351 ins_pipe(pipe_slow); // XXX |
| 5352 %} | |
| 5353 | |
| 5354 instruct loadD(regD dst, memory mem) | |
| 5355 %{ | |
| 5356 predicate(UseXmmLoadAndClearUpper); | |
| 5357 match(Set dst (LoadD mem)); | |
| 5358 | |
| 5359 ins_cost(145); // XXX | |
| 5360 format %{ "movsd $dst, $mem\t# double" %} | |
| 4759 | 5361 ins_encode %{ |
| 5362 __ movdbl($dst$$XMMRegister, $mem$$Address); | |
| 5363 %} | |
| 0 | 5364 ins_pipe(pipe_slow); // XXX |
| 5365 %} | |
| 5366 | |
| 5367 // Load Effective Address | |
| 5368 instruct leaP8(rRegP dst, indOffset8 mem) | |
| 5369 %{ | |
| 5370 match(Set dst mem); | |
| 5371 | |
| 5372 ins_cost(110); // XXX | |
| 5373 format %{ "leaq $dst, $mem\t# ptr 8" %} | |
| 5374 opcode(0x8D); | |
| 5375 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5376 ins_pipe(ialu_reg_reg_fat); | |
| 5377 %} | |
| 5378 | |
| 5379 instruct leaP32(rRegP dst, indOffset32 mem) | |
| 5380 %{ | |
| 5381 match(Set dst mem); | |
| 5382 | |
| 5383 ins_cost(110); | |
| 5384 format %{ "leaq $dst, $mem\t# ptr 32" %} | |
| 5385 opcode(0x8D); | |
| 5386 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5387 ins_pipe(ialu_reg_reg_fat); | |
| 5388 %} | |
| 5389 | |
| 5390 // instruct leaPIdx(rRegP dst, indIndex mem) | |
| 5391 // %{ | |
| 5392 // match(Set dst mem); | |
| 5393 | |
| 5394 // ins_cost(110); | |
| 5395 // format %{ "leaq $dst, $mem\t# ptr idx" %} | |
| 5396 // opcode(0x8D); | |
| 5397 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5398 // ins_pipe(ialu_reg_reg_fat); | |
| 5399 // %} | |
| 5400 | |
| 5401 instruct leaPIdxOff(rRegP dst, indIndexOffset mem) | |
| 5402 %{ | |
| 5403 match(Set dst mem); | |
| 5404 | |
| 5405 ins_cost(110); | |
| 5406 format %{ "leaq $dst, $mem\t# ptr idxoff" %} | |
| 5407 opcode(0x8D); | |
| 5408 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5409 ins_pipe(ialu_reg_reg_fat); | |
| 5410 %} | |
| 5411 | |
| 5412 instruct leaPIdxScale(rRegP dst, indIndexScale mem) | |
| 5413 %{ | |
| 5414 match(Set dst mem); | |
| 5415 | |
| 5416 ins_cost(110); | |
| 5417 format %{ "leaq $dst, $mem\t# ptr idxscale" %} | |
| 5418 opcode(0x8D); | |
| 5419 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5420 ins_pipe(ialu_reg_reg_fat); | |
| 5421 %} | |
| 5422 | |
| 5423 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem) | |
| 5424 %{ | |
| 5425 match(Set dst mem); | |
| 5426 | |
| 5427 ins_cost(110); | |
| 5428 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %} | |
| 5429 opcode(0x8D); | |
| 5430 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5431 ins_pipe(ialu_reg_reg_fat); | |
| 5432 %} | |
| 5433 | |
|
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5434 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem) |
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5435 %{ |
|
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|
5436 match(Set dst mem); |
|
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|
5437 |
|
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|
5438 ins_cost(110); |
|
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|
5439 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %} |
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5440 opcode(0x8D); |
|
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5441 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
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5442 ins_pipe(ialu_reg_reg_fat); |
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5443 %} |
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5444 |
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5445 // Load Effective Address which uses Narrow (32-bits) oop |
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5446 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem) |
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5447 %{ |
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5448 predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0)); |
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5449 match(Set dst mem); |
|
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|
5450 |
|
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5451 ins_cost(110); |
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5452 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %} |
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5453 opcode(0x8D); |
|
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5454 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
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5455 ins_pipe(ialu_reg_reg_fat); |
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5456 %} |
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5457 |
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5458 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem) |
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5459 %{ |
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5460 predicate(Universe::narrow_oop_shift() == 0); |
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5461 match(Set dst mem); |
|
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|
5462 |
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5463 ins_cost(110); // XXX |
|
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5464 format %{ "leaq $dst, $mem\t# ptr off8narrow" %} |
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5465 opcode(0x8D); |
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5466 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
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5467 ins_pipe(ialu_reg_reg_fat); |
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5468 %} |
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5469 |
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5470 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5471 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5472 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5473 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5474 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5475 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5476 format %{ "leaq $dst, $mem\t# ptr off32narrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5477 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5478 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5479 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5480 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5481 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5482 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5483 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5484 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5485 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5486 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5487 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5488 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5489 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5490 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5491 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5492 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5493 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5494 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5495 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5496 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5497 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5498 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5499 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5500 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5501 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5502 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5503 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5504 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5505 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5506 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5507 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5508 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5509 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5510 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5511 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5512 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5513 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5514 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5515 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5516 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5517 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5518 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5519 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5520 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5521 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5522 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5523 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5524 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5525 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5526 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5527 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5528 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5529 |
| 0 | 5530 instruct loadConI(rRegI dst, immI src) |
| 5531 %{ | |
| 5532 match(Set dst src); | |
| 5533 | |
| 5534 format %{ "movl $dst, $src\t# int" %} | |
| 5535 ins_encode(load_immI(dst, src)); | |
| 5536 ins_pipe(ialu_reg_fat); // XXX | |
| 5537 %} | |
| 5538 | |
| 5539 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr) | |
| 5540 %{ | |
| 5541 match(Set dst src); | |
| 5542 effect(KILL cr); | |
| 5543 | |
| 5544 ins_cost(50); | |
| 5545 format %{ "xorl $dst, $dst\t# int" %} | |
| 5546 opcode(0x33); /* + rd */ | |
| 5547 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst)); | |
| 5548 ins_pipe(ialu_reg); | |
| 5549 %} | |
| 5550 | |
| 5551 instruct loadConL(rRegL dst, immL src) | |
| 5552 %{ | |
| 5553 match(Set dst src); | |
| 5554 | |
| 5555 ins_cost(150); | |
| 5556 format %{ "movq $dst, $src\t# long" %} | |
| 5557 ins_encode(load_immL(dst, src)); | |
| 5558 ins_pipe(ialu_reg); | |
| 5559 %} | |
| 5560 | |
| 5561 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr) | |
| 5562 %{ | |
| 5563 match(Set dst src); | |
| 5564 effect(KILL cr); | |
| 5565 | |
| 5566 ins_cost(50); | |
| 5567 format %{ "xorl $dst, $dst\t# long" %} | |
| 5568 opcode(0x33); /* + rd */ | |
| 5569 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst)); | |
| 5570 ins_pipe(ialu_reg); // XXX | |
| 5571 %} | |
| 5572 | |
| 5573 instruct loadConUL32(rRegL dst, immUL32 src) | |
| 5574 %{ | |
| 5575 match(Set dst src); | |
| 5576 | |
| 5577 ins_cost(60); | |
| 5578 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %} | |
| 5579 ins_encode(load_immUL32(dst, src)); | |
| 5580 ins_pipe(ialu_reg); | |
| 5581 %} | |
| 5582 | |
| 5583 instruct loadConL32(rRegL dst, immL32 src) | |
| 5584 %{ | |
| 5585 match(Set dst src); | |
| 5586 | |
| 5587 ins_cost(70); | |
| 5588 format %{ "movq $dst, $src\t# long (32-bit)" %} | |
| 5589 ins_encode(load_immL32(dst, src)); | |
| 5590 ins_pipe(ialu_reg); | |
| 5591 %} | |
| 5592 | |
| 2008 | 5593 instruct loadConP(rRegP dst, immP con) %{ |
| 5594 match(Set dst con); | |
| 5595 | |
| 5596 format %{ "movq $dst, $con\t# ptr" %} | |
| 5597 ins_encode(load_immP(dst, con)); | |
| 0 | 5598 ins_pipe(ialu_reg_fat); // XXX |
| 5599 %} | |
| 5600 | |
| 5601 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr) | |
| 5602 %{ | |
| 5603 match(Set dst src); | |
| 5604 effect(KILL cr); | |
| 5605 | |
| 5606 ins_cost(50); | |
| 5607 format %{ "xorl $dst, $dst\t# ptr" %} | |
| 5608 opcode(0x33); /* + rd */ | |
| 5609 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst)); | |
| 5610 ins_pipe(ialu_reg); | |
| 5611 %} | |
| 5612 | |
| 5613 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr) | |
| 5614 %{ | |
| 5615 match(Set dst src); | |
| 5616 effect(KILL cr); | |
| 5617 | |
| 5618 ins_cost(60); | |
| 5619 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %} | |
| 5620 ins_encode(load_immP31(dst, src)); | |
| 5621 ins_pipe(ialu_reg); | |
| 5622 %} | |
| 5623 | |
| 2008 | 5624 instruct loadConF(regF dst, immF con) %{ |
| 5625 match(Set dst con); | |
| 0 | 5626 ins_cost(125); |
| 2008 | 5627 format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %} |
| 5628 ins_encode %{ | |
| 5629 __ movflt($dst$$XMMRegister, $constantaddress($con)); | |
| 5630 %} | |
| 0 | 5631 ins_pipe(pipe_slow); |
| 5632 %} | |
| 5633 | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5634 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5635 match(Set dst src); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5636 effect(KILL cr); |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
5637 format %{ "xorq $dst, $src\t# compressed NULL ptr" %} |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5638 ins_encode %{ |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5639 __ xorq($dst$$Register, $dst$$Register); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5640 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5641 ins_pipe(ialu_reg); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5642 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5643 |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
5644 instruct loadConN(rRegN dst, immN src) %{ |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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parents:
71
diff
changeset
|
5645 match(Set dst src); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5646 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5647 ins_cost(125); |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
5648 format %{ "movl $dst, $src\t# compressed ptr" %} |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5649 ins_encode %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5650 address con = (address)$src$$constant; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5651 if (con == NULL) { |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5652 ShouldNotReachHere(); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5653 } else { |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5654 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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71
diff
changeset
|
5655 } |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5656 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5657 ins_pipe(ialu_reg_fat); // XXX |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5658 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5659 |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5660 instruct loadConNKlass(rRegN dst, immNKlass src) %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5661 match(Set dst src); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5662 |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5663 ins_cost(125); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5664 format %{ "movl $dst, $src\t# compressed klass ptr" %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5665 ins_encode %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5666 address con = (address)$src$$constant; |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5667 if (con == NULL) { |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5668 ShouldNotReachHere(); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5669 } else { |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5670 __ set_narrow_klass($dst$$Register, (Klass*)$src$$constant); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5671 } |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5672 %} |
|
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|
5673 ins_pipe(ialu_reg_fat); // XXX |
|
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|
5674 %} |
|
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|
5675 |
| 0 | 5676 instruct loadConF0(regF dst, immF0 src) |
| 5677 %{ | |
| 5678 match(Set dst src); | |
| 5679 ins_cost(100); | |
| 5680 | |
| 5681 format %{ "xorps $dst, $dst\t# float 0.0" %} | |
| 4759 | 5682 ins_encode %{ |
| 5683 __ xorps($dst$$XMMRegister, $dst$$XMMRegister); | |
| 5684 %} | |
| 0 | 5685 ins_pipe(pipe_slow); |
| 5686 %} | |
| 5687 | |
| 5688 // Use the same format since predicate() can not be used here. | |
| 2008 | 5689 instruct loadConD(regD dst, immD con) %{ |
| 5690 match(Set dst con); | |
| 0 | 5691 ins_cost(125); |
| 2008 | 5692 format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %} |
| 5693 ins_encode %{ | |
| 5694 __ movdbl($dst$$XMMRegister, $constantaddress($con)); | |
| 5695 %} | |
| 0 | 5696 ins_pipe(pipe_slow); |
| 5697 %} | |
| 5698 | |
| 5699 instruct loadConD0(regD dst, immD0 src) | |
| 5700 %{ | |
| 5701 match(Set dst src); | |
| 5702 ins_cost(100); | |
| 5703 | |
| 5704 format %{ "xorpd $dst, $dst\t# double 0.0" %} | |
| 4759 | 5705 ins_encode %{ |
| 5706 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister); | |
| 5707 %} | |
| 0 | 5708 ins_pipe(pipe_slow); |
| 5709 %} | |
| 5710 | |
| 5711 instruct loadSSI(rRegI dst, stackSlotI src) | |
| 5712 %{ | |
| 5713 match(Set dst src); | |
| 5714 | |
| 5715 ins_cost(125); | |
| 5716 format %{ "movl $dst, $src\t# int stk" %} | |
| 5717 opcode(0x8B); | |
| 5718 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 5719 ins_pipe(ialu_reg_mem); | |
| 5720 %} | |
| 5721 | |
| 5722 instruct loadSSL(rRegL dst, stackSlotL src) | |
| 5723 %{ | |
| 5724 match(Set dst src); | |
| 5725 | |
| 5726 ins_cost(125); | |
| 5727 format %{ "movq $dst, $src\t# long stk" %} | |
| 5728 opcode(0x8B); | |
| 5729 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 5730 ins_pipe(ialu_reg_mem); | |
| 5731 %} | |
| 5732 | |
| 5733 instruct loadSSP(rRegP dst, stackSlotP src) | |
| 5734 %{ | |
| 5735 match(Set dst src); | |
| 5736 | |
| 5737 ins_cost(125); | |
| 5738 format %{ "movq $dst, $src\t# ptr stk" %} | |
| 5739 opcode(0x8B); | |
| 5740 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 5741 ins_pipe(ialu_reg_mem); | |
| 5742 %} | |
| 5743 | |
| 5744 instruct loadSSF(regF dst, stackSlotF src) | |
| 5745 %{ | |
| 5746 match(Set dst src); | |
| 5747 | |
| 5748 ins_cost(125); | |
| 5749 format %{ "movss $dst, $src\t# float stk" %} | |
| 4759 | 5750 ins_encode %{ |
| 5751 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 5752 %} | |
| 0 | 5753 ins_pipe(pipe_slow); // XXX |
| 5754 %} | |
| 5755 | |
| 5756 // Use the same format since predicate() can not be used here. | |
| 5757 instruct loadSSD(regD dst, stackSlotD src) | |
| 5758 %{ | |
| 5759 match(Set dst src); | |
| 5760 | |
| 5761 ins_cost(125); | |
| 5762 format %{ "movsd $dst, $src\t# double stk" %} | |
| 5763 ins_encode %{ | |
| 5764 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 5765 %} | |
| 5766 ins_pipe(pipe_slow); // XXX | |
| 5767 %} | |
| 5768 | |
| 5769 // Prefetch instructions. | |
| 5770 // Must be safe to execute with invalid address (cannot fault). | |
| 5771 | |
| 5772 instruct prefetchr( memory mem ) %{ | |
| 5773 predicate(ReadPrefetchInstr==3); | |
| 5774 match(PrefetchRead mem); | |
| 5775 ins_cost(125); | |
| 5776 | |
| 5777 format %{ "PREFETCHR $mem\t# Prefetch into level 1 cache" %} | |
| 3854 | 5778 ins_encode %{ |
| 5779 __ prefetchr($mem$$Address); | |
| 5780 %} | |
| 0 | 5781 ins_pipe(ialu_mem); |
| 5782 %} | |
| 5783 | |
| 5784 instruct prefetchrNTA( memory mem ) %{ | |
| 5785 predicate(ReadPrefetchInstr==0); | |
| 5786 match(PrefetchRead mem); | |
| 5787 ins_cost(125); | |
| 5788 | |
| 5789 format %{ "PREFETCHNTA $mem\t# Prefetch into non-temporal cache for read" %} | |
| 3854 | 5790 ins_encode %{ |
| 5791 __ prefetchnta($mem$$Address); | |
| 5792 %} | |
| 0 | 5793 ins_pipe(ialu_mem); |
| 5794 %} | |
| 5795 | |
| 5796 instruct prefetchrT0( memory mem ) %{ | |
| 5797 predicate(ReadPrefetchInstr==1); | |
| 5798 match(PrefetchRead mem); | |
| 5799 ins_cost(125); | |
| 5800 | |
| 5801 format %{ "PREFETCHT0 $mem\t# prefetch into L1 and L2 caches for read" %} | |
| 3854 | 5802 ins_encode %{ |
| 5803 __ prefetcht0($mem$$Address); | |
| 5804 %} | |
| 0 | 5805 ins_pipe(ialu_mem); |
| 5806 %} | |
| 5807 | |
| 5808 instruct prefetchrT2( memory mem ) %{ | |
| 5809 predicate(ReadPrefetchInstr==2); | |
| 5810 match(PrefetchRead mem); | |
| 5811 ins_cost(125); | |
| 5812 | |
| 5813 format %{ "PREFETCHT2 $mem\t# prefetch into L2 caches for read" %} | |
| 3854 | 5814 ins_encode %{ |
| 5815 __ prefetcht2($mem$$Address); | |
| 5816 %} | |
| 0 | 5817 ins_pipe(ialu_mem); |
| 5818 %} | |
| 5819 | |
| 5820 instruct prefetchwNTA( memory mem ) %{ | |
| 5821 match(PrefetchWrite mem); | |
| 5822 ins_cost(125); | |
| 5823 | |
| 5824 format %{ "PREFETCHNTA $mem\t# Prefetch to non-temporal cache for write" %} | |
| 3854 | 5825 ins_encode %{ |
| 5826 __ prefetchnta($mem$$Address); | |
| 5827 %} | |
| 0 | 5828 ins_pipe(ialu_mem); |
| 5829 %} | |
| 5830 | |
| 3854 | 5831 // Prefetch instructions for allocation. |
| 5832 | |
| 5833 instruct prefetchAlloc( memory mem ) %{ | |
| 5834 predicate(AllocatePrefetchInstr==3); | |
| 5835 match(PrefetchAllocation mem); | |
| 5836 ins_cost(125); | |
| 5837 | |
| 5838 format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %} | |
| 5839 ins_encode %{ | |
| 5840 __ prefetchw($mem$$Address); | |
| 5841 %} | |
| 5842 ins_pipe(ialu_mem); | |
| 5843 %} | |
| 5844 | |
| 5845 instruct prefetchAllocNTA( memory mem ) %{ | |
| 5846 predicate(AllocatePrefetchInstr==0); | |
| 5847 match(PrefetchAllocation mem); | |
| 0 | 5848 ins_cost(125); |
| 5849 | |
| 3854 | 5850 format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %} |
| 5851 ins_encode %{ | |
| 5852 __ prefetchnta($mem$$Address); | |
| 5853 %} | |
| 0 | 5854 ins_pipe(ialu_mem); |
| 5855 %} | |
| 5856 | |
| 3854 | 5857 instruct prefetchAllocT0( memory mem ) %{ |
| 5858 predicate(AllocatePrefetchInstr==1); | |
| 5859 match(PrefetchAllocation mem); | |
| 0 | 5860 ins_cost(125); |
| 5861 | |
| 3854 | 5862 format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %} |
| 5863 ins_encode %{ | |
| 5864 __ prefetcht0($mem$$Address); | |
| 5865 %} | |
| 5866 ins_pipe(ialu_mem); | |
| 5867 %} | |
| 5868 | |
| 5869 instruct prefetchAllocT2( memory mem ) %{ | |
| 5870 predicate(AllocatePrefetchInstr==2); | |
| 5871 match(PrefetchAllocation mem); | |
| 5872 ins_cost(125); | |
| 5873 | |
| 5874 format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %} | |
| 5875 ins_encode %{ | |
| 5876 __ prefetcht2($mem$$Address); | |
| 5877 %} | |
| 0 | 5878 ins_pipe(ialu_mem); |
| 5879 %} | |
| 5880 | |
| 5881 //----------Store Instructions------------------------------------------------- | |
| 5882 | |
| 5883 // Store Byte | |
| 5884 instruct storeB(memory mem, rRegI src) | |
| 5885 %{ | |
| 5886 match(Set mem (StoreB mem src)); | |
| 5887 | |
| 5888 ins_cost(125); // XXX | |
| 5889 format %{ "movb $mem, $src\t# byte" %} | |
| 5890 opcode(0x88); | |
| 5891 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
| 5892 ins_pipe(ialu_mem_reg); | |
| 5893 %} | |
| 5894 | |
| 5895 // Store Char/Short | |
| 5896 instruct storeC(memory mem, rRegI src) | |
| 5897 %{ | |
| 5898 match(Set mem (StoreC mem src)); | |
| 5899 | |
| 5900 ins_cost(125); // XXX | |
| 5901 format %{ "movw $mem, $src\t# char/short" %} | |
| 5902 opcode(0x89); | |
| 5903 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
| 5904 ins_pipe(ialu_mem_reg); | |
| 5905 %} | |
| 5906 | |
| 5907 // Store Integer | |
| 5908 instruct storeI(memory mem, rRegI src) | |
| 5909 %{ | |
| 5910 match(Set mem (StoreI mem src)); | |
| 5911 | |
| 5912 ins_cost(125); // XXX | |
| 5913 format %{ "movl $mem, $src\t# int" %} | |
| 5914 opcode(0x89); | |
| 5915 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
| 5916 ins_pipe(ialu_mem_reg); | |
| 5917 %} | |
| 5918 | |
| 5919 // Store Long | |
| 5920 instruct storeL(memory mem, rRegL src) | |
| 5921 %{ | |
| 5922 match(Set mem (StoreL mem src)); | |
| 5923 | |
| 5924 ins_cost(125); // XXX | |
| 5925 format %{ "movq $mem, $src\t# long" %} | |
| 5926 opcode(0x89); | |
| 5927 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem)); | |
| 5928 ins_pipe(ialu_mem_reg); // XXX | |
| 5929 %} | |
| 5930 | |
| 5931 // Store Pointer | |
| 5932 instruct storeP(memory mem, any_RegP src) | |
| 5933 %{ | |
| 5934 match(Set mem (StoreP mem src)); | |
| 5935 | |
| 5936 ins_cost(125); // XXX | |
| 5937 format %{ "movq $mem, $src\t# ptr" %} | |
| 5938 opcode(0x89); | |
| 5939 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem)); | |
| 5940 ins_pipe(ialu_mem_reg); | |
| 5941 %} | |
| 5942 | |
|
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5943 instruct storeImmP0(memory mem, immP0 zero) |
|
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|
5944 %{ |
|
6848
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|
5945 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL)); |
|
642
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5946 match(Set mem (StoreP mem zero)); |
|
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|
5947 |
|
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|
5948 ins_cost(125); // XXX |
|
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|
5949 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %} |
|
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5950 ins_encode %{ |
|
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|
5951 __ movq($mem$$Address, r12); |
|
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|
5952 %} |
|
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|
5953 ins_pipe(ialu_mem_reg); |
|
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|
5954 %} |
|
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|
5955 |
| 0 | 5956 // Store NULL Pointer, mark word, or other simple pointer constant. |
| 5957 instruct storeImmP(memory mem, immP31 src) | |
| 5958 %{ | |
| 5959 match(Set mem (StoreP mem src)); | |
| 5960 | |
|
642
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|
5961 ins_cost(150); // XXX |
| 0 | 5962 format %{ "movq $mem, $src\t# ptr" %} |
| 5963 opcode(0xC7); /* C7 /0 */ | |
| 5964 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); | |
| 5965 ins_pipe(ialu_mem_imm); | |
| 5966 %} | |
| 5967 | |
|
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5968 // Store Compressed Pointer |
| 163 | 5969 instruct storeN(memory mem, rRegN src) |
|
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5970 %{ |
|
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|
5971 match(Set mem (StoreN mem src)); |
|
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|
5972 |
|
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|
5973 ins_cost(125); // XXX |
|
164
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|
5974 format %{ "movl $mem, $src\t# compressed ptr" %} |
|
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5975 ins_encode %{ |
|
642
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|
5976 __ movl($mem$$Address, $src$$Register); |
|
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|
5977 %} |
|
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|
5978 ins_pipe(ialu_mem_reg); |
|
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|
5979 %} |
|
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|
5980 |
|
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|
5981 instruct storeNKlass(memory mem, rRegN src) |
|
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|
5982 %{ |
|
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|
5983 match(Set mem (StoreNKlass mem src)); |
|
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|
5984 |
|
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|
5985 ins_cost(125); // XXX |
|
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|
5986 format %{ "movl $mem, $src\t# compressed klass ptr" %} |
|
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|
5987 ins_encode %{ |
|
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|
5988 __ movl($mem$$Address, $src$$Register); |
|
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|
5989 %} |
|
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|
5990 ins_pipe(ialu_mem_reg); |
|
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|
5991 %} |
|
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|
5992 |
|
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5993 instruct storeImmN0(memory mem, immN0 zero) |
|
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5994 %{ |
|
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|
5995 predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_klass_base() == NULL); |
|
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5996 match(Set mem (StoreN mem zero)); |
|
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|
5997 |
|
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|
5998 ins_cost(125); // XXX |
|
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5999 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %} |
|
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6000 ins_encode %{ |
|
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6001 __ movl($mem$$Address, r12); |
|
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6002 %} |
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6003 ins_pipe(ialu_mem_reg); |
|
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6004 %} |
|
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6005 |
|
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6006 instruct storeImmN(memory mem, immN src) |
|
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|
6007 %{ |
|
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|
6008 match(Set mem (StoreN mem src)); |
|
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|
6009 |
|
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|
6010 ins_cost(150); // XXX |
|
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|
6011 format %{ "movl $mem, $src\t# compressed ptr" %} |
|
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|
6012 ins_encode %{ |
|
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|
6013 address con = (address)$src$$constant; |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6014 if (con == NULL) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6015 __ movl($mem$$Address, (int32_t)0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6016 } else { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6017 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6018 } |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6019 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6020 ins_pipe(ialu_mem_imm); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6021 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6022 |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6023 instruct storeImmNKlass(memory mem, immNKlass src) |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6024 %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6025 match(Set mem (StoreNKlass mem src)); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6026 |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6027 ins_cost(150); // XXX |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6028 format %{ "movl $mem, $src\t# compressed klass ptr" %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6029 ins_encode %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6030 __ set_narrow_klass($mem$$Address, (Klass*)$src$$constant); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6031 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6032 ins_pipe(ialu_mem_imm); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6033 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6034 |
| 0 | 6035 // Store Integer Immediate |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6036 instruct storeImmI0(memory mem, immI0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6037 %{ |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6038 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL)); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6039 match(Set mem (StoreI mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6040 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6041 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6042 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6043 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6044 __ movl($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6045 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6046 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6047 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6048 |
| 0 | 6049 instruct storeImmI(memory mem, immI src) |
| 6050 %{ | |
| 6051 match(Set mem (StoreI mem src)); | |
| 6052 | |
| 6053 ins_cost(150); | |
| 6054 format %{ "movl $mem, $src\t# int" %} | |
| 6055 opcode(0xC7); /* C7 /0 */ | |
| 6056 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); | |
| 6057 ins_pipe(ialu_mem_imm); | |
| 6058 %} | |
| 6059 | |
| 6060 // Store Long Immediate | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6061 instruct storeImmL0(memory mem, immL0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6062 %{ |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6063 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL)); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6064 match(Set mem (StoreL mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6065 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6066 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6067 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6068 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6069 __ movq($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6070 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6071 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6072 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6073 |
| 0 | 6074 instruct storeImmL(memory mem, immL32 src) |
| 6075 %{ | |
| 6076 match(Set mem (StoreL mem src)); | |
| 6077 | |
| 6078 ins_cost(150); | |
| 6079 format %{ "movq $mem, $src\t# long" %} | |
| 6080 opcode(0xC7); /* C7 /0 */ | |
| 6081 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); | |
| 6082 ins_pipe(ialu_mem_imm); | |
| 6083 %} | |
| 6084 | |
| 6085 // Store Short/Char Immediate | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6086 instruct storeImmC0(memory mem, immI0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6087 %{ |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6088 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL)); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6089 match(Set mem (StoreC mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6090 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6091 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6092 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6093 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6094 __ movw($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6095 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6096 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6097 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6098 |
| 0 | 6099 instruct storeImmI16(memory mem, immI16 src) |
| 6100 %{ | |
| 6101 predicate(UseStoreImmI16); | |
| 6102 match(Set mem (StoreC mem src)); | |
| 6103 | |
| 6104 ins_cost(150); | |
| 6105 format %{ "movw $mem, $src\t# short/char" %} | |
| 6106 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */ | |
| 6107 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src)); | |
| 6108 ins_pipe(ialu_mem_imm); | |
| 6109 %} | |
| 6110 | |
| 6111 // Store Byte Immediate | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6112 instruct storeImmB0(memory mem, immI0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6113 %{ |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6114 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL)); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6115 match(Set mem (StoreB mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6116 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6117 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6118 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6119 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6120 __ movb($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6121 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6122 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6123 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6124 |
| 0 | 6125 instruct storeImmB(memory mem, immI8 src) |
| 6126 %{ | |
| 6127 match(Set mem (StoreB mem src)); | |
| 6128 | |
| 6129 ins_cost(150); // XXX | |
| 6130 format %{ "movb $mem, $src\t# byte" %} | |
| 6131 opcode(0xC6); /* C6 /0 */ | |
| 6132 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src)); | |
| 6133 ins_pipe(ialu_mem_imm); | |
| 6134 %} | |
| 6135 | |
| 6136 // Store CMS card-mark Immediate | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6137 instruct storeImmCM0_reg(memory mem, immI0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6138 %{ |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6139 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL)); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6140 match(Set mem (StoreCM mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6141 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6142 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6143 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6144 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6145 __ movb($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6146 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6147 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6148 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6149 |
| 0 | 6150 instruct storeImmCM0(memory mem, immI0 src) |
| 6151 %{ | |
| 6152 match(Set mem (StoreCM mem src)); | |
| 6153 | |
| 6154 ins_cost(150); // XXX | |
| 6155 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %} | |
| 6156 opcode(0xC6); /* C6 /0 */ | |
| 6157 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src)); | |
| 6158 ins_pipe(ialu_mem_imm); | |
| 6159 %} | |
| 6160 | |
| 6161 // Store Float | |
| 6162 instruct storeF(memory mem, regF src) | |
| 6163 %{ | |
| 6164 match(Set mem (StoreF mem src)); | |
| 6165 | |
| 6166 ins_cost(95); // XXX | |
| 6167 format %{ "movss $mem, $src\t# float" %} | |
| 4759 | 6168 ins_encode %{ |
| 6169 __ movflt($mem$$Address, $src$$XMMRegister); | |
| 6170 %} | |
| 0 | 6171 ins_pipe(pipe_slow); // XXX |
| 6172 %} | |
| 6173 | |
| 6174 // Store immediate Float value (it is faster than store from XMM register) | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6175 instruct storeF0(memory mem, immF0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6176 %{ |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6177 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL)); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6178 match(Set mem (StoreF mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6179 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6180 ins_cost(25); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6181 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6182 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6183 __ movl($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6184 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6185 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6186 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6187 |
| 0 | 6188 instruct storeF_imm(memory mem, immF src) |
| 6189 %{ | |
| 6190 match(Set mem (StoreF mem src)); | |
| 6191 | |
| 6192 ins_cost(50); | |
| 6193 format %{ "movl $mem, $src\t# float" %} | |
| 6194 opcode(0xC7); /* C7 /0 */ | |
| 6195 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src)); | |
| 6196 ins_pipe(ialu_mem_imm); | |
| 6197 %} | |
| 6198 | |
| 6199 // Store Double | |
| 6200 instruct storeD(memory mem, regD src) | |
| 6201 %{ | |
| 6202 match(Set mem (StoreD mem src)); | |
| 6203 | |
| 6204 ins_cost(95); // XXX | |
| 6205 format %{ "movsd $mem, $src\t# double" %} | |
| 4759 | 6206 ins_encode %{ |
| 6207 __ movdbl($mem$$Address, $src$$XMMRegister); | |
| 6208 %} | |
| 0 | 6209 ins_pipe(pipe_slow); // XXX |
| 6210 %} | |
| 6211 | |
| 6212 // Store immediate double 0.0 (it is faster than store from XMM register) | |
| 6213 instruct storeD0_imm(memory mem, immD0 src) | |
| 6214 %{ | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6215 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL)); |
| 0 | 6216 match(Set mem (StoreD mem src)); |
| 6217 | |
| 6218 ins_cost(50); | |
| 6219 format %{ "movq $mem, $src\t# double 0." %} | |
| 6220 opcode(0xC7); /* C7 /0 */ | |
| 6221 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src)); | |
| 6222 ins_pipe(ialu_mem_imm); | |
| 6223 %} | |
| 6224 | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6225 instruct storeD0(memory mem, immD0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6226 %{ |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6227 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL)); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6228 match(Set mem (StoreD mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6229 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6230 ins_cost(25); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6231 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6232 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6233 __ movq($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6234 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6235 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6236 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6237 |
| 0 | 6238 instruct storeSSI(stackSlotI dst, rRegI src) |
| 6239 %{ | |
| 6240 match(Set dst src); | |
| 6241 | |
| 6242 ins_cost(100); | |
| 6243 format %{ "movl $dst, $src\t# int stk" %} | |
| 6244 opcode(0x89); | |
| 6245 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 6246 ins_pipe( ialu_mem_reg ); | |
| 6247 %} | |
| 6248 | |
| 6249 instruct storeSSL(stackSlotL dst, rRegL src) | |
| 6250 %{ | |
| 6251 match(Set dst src); | |
| 6252 | |
| 6253 ins_cost(100); | |
| 6254 format %{ "movq $dst, $src\t# long stk" %} | |
| 6255 opcode(0x89); | |
| 6256 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 6257 ins_pipe(ialu_mem_reg); | |
| 6258 %} | |
| 6259 | |
| 6260 instruct storeSSP(stackSlotP dst, rRegP src) | |
| 6261 %{ | |
| 6262 match(Set dst src); | |
| 6263 | |
| 6264 ins_cost(100); | |
| 6265 format %{ "movq $dst, $src\t# ptr stk" %} | |
| 6266 opcode(0x89); | |
| 6267 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 6268 ins_pipe(ialu_mem_reg); | |
| 6269 %} | |
| 6270 | |
| 6271 instruct storeSSF(stackSlotF dst, regF src) | |
| 6272 %{ | |
| 6273 match(Set dst src); | |
| 6274 | |
| 6275 ins_cost(95); // XXX | |
| 6276 format %{ "movss $dst, $src\t# float stk" %} | |
| 4759 | 6277 ins_encode %{ |
| 6278 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister); | |
| 6279 %} | |
| 0 | 6280 ins_pipe(pipe_slow); // XXX |
| 6281 %} | |
| 6282 | |
| 6283 instruct storeSSD(stackSlotD dst, regD src) | |
| 6284 %{ | |
| 6285 match(Set dst src); | |
| 6286 | |
| 6287 ins_cost(95); // XXX | |
| 6288 format %{ "movsd $dst, $src\t# double stk" %} | |
| 4759 | 6289 ins_encode %{ |
| 6290 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister); | |
| 6291 %} | |
| 0 | 6292 ins_pipe(pipe_slow); // XXX |
| 6293 %} | |
| 6294 | |
| 6295 //----------BSWAP Instructions------------------------------------------------- | |
| 6296 instruct bytes_reverse_int(rRegI dst) %{ | |
| 6297 match(Set dst (ReverseBytesI dst)); | |
| 6298 | |
| 6299 format %{ "bswapl $dst" %} | |
| 6300 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */ | |
| 6301 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) ); | |
| 6302 ins_pipe( ialu_reg ); | |
| 6303 %} | |
| 6304 | |
| 6305 instruct bytes_reverse_long(rRegL dst) %{ | |
| 6306 match(Set dst (ReverseBytesL dst)); | |
| 6307 | |
| 6308 format %{ "bswapq $dst" %} | |
| 6309 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */ | |
| 6310 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) ); | |
| 6311 ins_pipe( ialu_reg); | |
| 6312 %} | |
| 6313 | |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6314 instruct bytes_reverse_unsigned_short(rRegI dst, rFlagsReg cr) %{ |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6315 match(Set dst (ReverseBytesUS dst)); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6316 effect(KILL cr); |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6317 |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
6318 format %{ "bswapl $dst\n\t" |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6319 "shrl $dst,16\n\t" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6320 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6321 __ bswapl($dst$$Register); |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
6322 __ shrl($dst$$Register, 16); |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6323 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6324 ins_pipe( ialu_reg ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6325 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6326 |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6327 instruct bytes_reverse_short(rRegI dst, rFlagsReg cr) %{ |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6328 match(Set dst (ReverseBytesS dst)); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6329 effect(KILL cr); |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6330 |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
6331 format %{ "bswapl $dst\n\t" |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6332 "sar $dst,16\n\t" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6333 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6334 __ bswapl($dst$$Register); |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
6335 __ sarl($dst$$Register, 16); |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6336 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6337 ins_pipe( ialu_reg ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6338 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6339 |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6340 //---------- Zeros Count Instructions ------------------------------------------ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6341 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6342 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6343 predicate(UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6344 match(Set dst (CountLeadingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6345 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6346 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6347 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6348 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6349 __ lzcntl($dst$$Register, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6350 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6351 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6352 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6353 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6354 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6355 predicate(!UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6356 match(Set dst (CountLeadingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6357 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6358 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6359 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6360 "jnz skip\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6361 "movl $dst, -1\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6362 "skip:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6363 "negl $dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6364 "addl $dst, 31" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6365 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6366 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6367 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6368 Label skip; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6369 __ bsrl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6370 __ jccb(Assembler::notZero, skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6371 __ movl(Rdst, -1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6372 __ bind(skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6373 __ negl(Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6374 __ addl(Rdst, BitsPerInt - 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6375 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6376 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6377 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6378 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6379 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6380 predicate(UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6381 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6382 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6383 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6384 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6385 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6386 __ lzcntq($dst$$Register, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6387 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6388 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6389 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6390 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6391 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6392 predicate(!UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6393 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6394 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6395 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6396 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6397 "jnz skip\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6398 "movl $dst, -1\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6399 "skip:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6400 "negl $dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6401 "addl $dst, 63" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6402 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6403 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6404 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6405 Label skip; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6406 __ bsrq(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6407 __ jccb(Assembler::notZero, skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6408 __ movl(Rdst, -1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6409 __ bind(skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6410 __ negl(Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6411 __ addl(Rdst, BitsPerLong - 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6412 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6413 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6414 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6415 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6416 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6417 match(Set dst (CountTrailingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6418 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6419 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6420 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6421 "jnz done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6422 "movl $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6423 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6424 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6425 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6426 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6427 __ bsfl(Rdst, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6428 __ jccb(Assembler::notZero, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6429 __ movl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6430 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6431 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6432 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6433 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6434 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6435 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6436 match(Set dst (CountTrailingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6437 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6438 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6439 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6440 "jnz done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6441 "movl $dst, 64\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6442 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6443 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6444 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6445 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6446 __ bsfq(Rdst, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6447 __ jccb(Assembler::notZero, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6448 __ movl(Rdst, BitsPerLong); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6449 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6450 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6451 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6452 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6453 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6454 |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6455 //---------- Population Count Instructions ------------------------------------- |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6456 |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6457 instruct popCountI(rRegI dst, rRegI src, rFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6458 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6459 match(Set dst (PopCountI src)); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6460 effect(KILL cr); |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6461 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6462 format %{ "popcnt $dst, $src" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6463 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6464 __ popcntl($dst$$Register, $src$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6465 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6466 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6467 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6468 |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6469 instruct popCountI_mem(rRegI dst, memory mem, rFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6470 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6471 match(Set dst (PopCountI (LoadI mem))); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6472 effect(KILL cr); |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6473 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6474 format %{ "popcnt $dst, $mem" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6475 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6476 __ popcntl($dst$$Register, $mem$$Address); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6477 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6478 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6479 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6480 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6481 // Note: Long.bitCount(long) returns an int. |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6482 instruct popCountL(rRegI dst, rRegL src, rFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6483 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6484 match(Set dst (PopCountL src)); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6485 effect(KILL cr); |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6486 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6487 format %{ "popcnt $dst, $src" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6488 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6489 __ popcntq($dst$$Register, $src$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6490 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6491 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6492 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6493 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6494 // Note: Long.bitCount(long) returns an int. |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6495 instruct popCountL_mem(rRegI dst, memory mem, rFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6496 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6497 match(Set dst (PopCountL (LoadL mem))); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6498 effect(KILL cr); |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6499 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6500 format %{ "popcnt $dst, $mem" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6501 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6502 __ popcntq($dst$$Register, $mem$$Address); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6503 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6504 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6505 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6506 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6507 |
| 0 | 6508 //----------MemBar Instructions----------------------------------------------- |
| 6509 // Memory barrier flavors | |
| 6510 | |
| 6511 instruct membar_acquire() | |
| 6512 %{ | |
| 6513 match(MemBarAcquire); | |
| 6514 ins_cost(0); | |
| 6515 | |
| 6516 size(0); | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6517 format %{ "MEMBAR-acquire ! (empty encoding)" %} |
| 0 | 6518 ins_encode(); |
| 6519 ins_pipe(empty); | |
| 6520 %} | |
| 6521 | |
| 6522 instruct membar_acquire_lock() | |
| 6523 %{ | |
|
3849
f1c12354c3f7
7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents:
3842
diff
changeset
|
6524 match(MemBarAcquireLock); |
| 0 | 6525 ins_cost(0); |
| 6526 | |
| 6527 size(0); | |
| 6528 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %} | |
| 6529 ins_encode(); | |
| 6530 ins_pipe(empty); | |
| 6531 %} | |
| 6532 | |
| 6533 instruct membar_release() | |
| 6534 %{ | |
| 6535 match(MemBarRelease); | |
| 6536 ins_cost(0); | |
| 6537 | |
| 6538 size(0); | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6539 format %{ "MEMBAR-release ! (empty encoding)" %} |
| 0 | 6540 ins_encode(); |
| 6541 ins_pipe(empty); | |
| 6542 %} | |
| 6543 | |
| 6544 instruct membar_release_lock() | |
| 6545 %{ | |
|
3849
f1c12354c3f7
7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents:
3842
diff
changeset
|
6546 match(MemBarReleaseLock); |
| 0 | 6547 ins_cost(0); |
| 6548 | |
| 6549 size(0); | |
| 6550 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %} | |
| 6551 ins_encode(); | |
| 6552 ins_pipe(empty); | |
| 6553 %} | |
| 6554 | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6555 instruct membar_volatile(rFlagsReg cr) %{ |
| 0 | 6556 match(MemBarVolatile); |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6557 effect(KILL cr); |
| 0 | 6558 ins_cost(400); |
| 6559 | |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
6560 format %{ |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6561 $$template |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6562 if (os::is_MP()) { |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6563 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile" |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6564 } else { |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6565 $$emit$$"MEMBAR-volatile ! (empty encoding)" |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6566 } |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6567 %} |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6568 ins_encode %{ |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6569 __ membar(Assembler::StoreLoad); |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6570 %} |
| 0 | 6571 ins_pipe(pipe_slow); |
| 6572 %} | |
| 6573 | |
| 6574 instruct unnecessary_membar_volatile() | |
| 6575 %{ | |
| 6576 match(MemBarVolatile); | |
| 6577 predicate(Matcher::post_store_load_barrier(n)); | |
| 6578 ins_cost(0); | |
| 6579 | |
| 6580 size(0); | |
| 6581 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %} | |
| 6582 ins_encode(); | |
| 6583 ins_pipe(empty); | |
| 6584 %} | |
| 6585 | |
|
4763
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6586 instruct membar_storestore() %{ |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6587 match(MemBarStoreStore); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6588 ins_cost(0); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6589 |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6590 size(0); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6591 format %{ "MEMBAR-storestore (empty encoding)" %} |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6592 ins_encode( ); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6593 ins_pipe(empty); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6594 %} |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6595 |
| 0 | 6596 //----------Move Instructions-------------------------------------------------- |
| 6597 | |
| 6598 instruct castX2P(rRegP dst, rRegL src) | |
| 6599 %{ | |
| 6600 match(Set dst (CastX2P src)); | |
| 6601 | |
| 6602 format %{ "movq $dst, $src\t# long->ptr" %} | |
| 4759 | 6603 ins_encode %{ |
| 6604 if ($dst$$reg != $src$$reg) { | |
| 6605 __ movptr($dst$$Register, $src$$Register); | |
| 6606 } | |
| 6607 %} | |
| 0 | 6608 ins_pipe(ialu_reg_reg); // XXX |
| 6609 %} | |
| 6610 | |
| 6611 instruct castP2X(rRegL dst, rRegP src) | |
| 6612 %{ | |
| 6613 match(Set dst (CastP2X src)); | |
| 6614 | |
| 6615 format %{ "movq $dst, $src\t# ptr -> long" %} | |
| 4759 | 6616 ins_encode %{ |
| 6617 if ($dst$$reg != $src$$reg) { | |
| 6618 __ movptr($dst$$Register, $src$$Register); | |
| 6619 } | |
| 6620 %} | |
| 0 | 6621 ins_pipe(ialu_reg_reg); // XXX |
| 6622 %} | |
| 6623 | |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6624 // Convert oop into int for vectors alignment masking |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6625 instruct convP2I(rRegI dst, rRegP src) |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6626 %{ |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6627 match(Set dst (ConvL2I (CastP2X src))); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6628 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6629 format %{ "movl $dst, $src\t# ptr -> int" %} |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6630 ins_encode %{ |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6631 __ movl($dst$$Register, $src$$Register); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6632 %} |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6633 ins_pipe(ialu_reg_reg); // XXX |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6634 %} |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6635 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6636 // Convert compressed oop into int for vectors alignment masking |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6637 // in case of 32bit oops (heap < 4Gb). |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6638 instruct convN2I(rRegI dst, rRegN src) |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6639 %{ |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6640 predicate(Universe::narrow_oop_shift() == 0); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6641 match(Set dst (ConvL2I (CastP2X (DecodeN src)))); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6642 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6643 format %{ "movl $dst, $src\t# compressed ptr -> int" %} |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6644 ins_encode %{ |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6645 __ movl($dst$$Register, $src$$Register); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6646 %} |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6647 ins_pipe(ialu_reg_reg); // XXX |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6648 %} |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6649 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6650 // Convert oop pointer into compressed form |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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71
diff
changeset
|
6651 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{ |
|
221
1e026f8da827
6710487: More than half of JDI Regression tests hang with COOPs in -Xcomp mode
kvn
parents:
182
diff
changeset
|
6652 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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71
diff
changeset
|
6653 match(Set dst (EncodeP src)); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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71
diff
changeset
|
6654 effect(KILL cr); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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71
diff
changeset
|
6655 format %{ "encode_heap_oop $dst,$src" %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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71
diff
changeset
|
6656 ins_encode %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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71
diff
changeset
|
6657 Register s = $src$$Register; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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71
diff
changeset
|
6658 Register d = $dst$$Register; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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71
diff
changeset
|
6659 if (s != d) { |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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71
diff
changeset
|
6660 __ movq(d, s); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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71
diff
changeset
|
6661 } |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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71
diff
changeset
|
6662 __ encode_heap_oop(d); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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71
diff
changeset
|
6663 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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71
diff
changeset
|
6664 ins_pipe(ialu_reg_long); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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71
diff
changeset
|
6665 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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71
diff
changeset
|
6666 |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6667 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{ |
|
221
1e026f8da827
6710487: More than half of JDI Regression tests hang with COOPs in -Xcomp mode
kvn
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182
diff
changeset
|
6668 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6669 match(Set dst (EncodeP src)); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6670 effect(KILL cr); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6671 format %{ "encode_heap_oop_not_null $dst,$src" %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6672 ins_encode %{ |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6673 __ encode_heap_oop_not_null($dst$$Register, $src$$Register); |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6674 %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6675 ins_pipe(ialu_reg_long); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6676 %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6677 |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6678 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{ |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
6679 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull && |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
6680 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant); |
|
113
ba764ed4b6f2
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coleenp
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71
diff
changeset
|
6681 match(Set dst (DecodeN src)); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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71
diff
changeset
|
6682 effect(KILL cr); |
|
ba764ed4b6f2
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coleenp
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71
diff
changeset
|
6683 format %{ "decode_heap_oop $dst,$src" %} |
|
ba764ed4b6f2
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71
diff
changeset
|
6684 ins_encode %{ |
|
ba764ed4b6f2
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coleenp
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71
diff
changeset
|
6685 Register s = $src$$Register; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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71
diff
changeset
|
6686 Register d = $dst$$Register; |
|
ba764ed4b6f2
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coleenp
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71
diff
changeset
|
6687 if (s != d) { |
|
ba764ed4b6f2
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71
diff
changeset
|
6688 __ movq(d, s); |
|
ba764ed4b6f2
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coleenp
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71
diff
changeset
|
6689 } |
|
ba764ed4b6f2
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71
diff
changeset
|
6690 __ decode_heap_oop(d); |
|
ba764ed4b6f2
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71
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|
6691 %} |
|
ba764ed4b6f2
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coleenp
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71
diff
changeset
|
6692 ins_pipe(ialu_reg_long); |
|
ba764ed4b6f2
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71
diff
changeset
|
6693 %} |
|
ba764ed4b6f2
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71
diff
changeset
|
6694 |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1567
diff
changeset
|
6695 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{ |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
6696 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull || |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
6697 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant); |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6698 match(Set dst (DecodeN src)); |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1567
diff
changeset
|
6699 effect(KILL cr); |
|
124
b130b98db9cf
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kvn
parents:
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diff
changeset
|
6700 format %{ "decode_heap_oop_not_null $dst,$src" %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6701 ins_encode %{ |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6702 Register s = $src$$Register; |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6703 Register d = $dst$$Register; |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6704 if (s != d) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6705 __ decode_heap_oop_not_null(d, s); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6706 } else { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6707 __ decode_heap_oop_not_null(d); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6708 } |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6709 %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6710 ins_pipe(ialu_reg_long); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6711 %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6712 |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6713 instruct encodeKlass_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6714 match(Set dst (EncodePKlass src)); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6715 effect(KILL cr); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6716 format %{ "encode_heap_oop_not_null $dst,$src" %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6717 ins_encode %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6718 __ encode_klass_not_null($dst$$Register, $src$$Register); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6719 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6720 ins_pipe(ialu_reg_long); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6721 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6722 |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6723 instruct decodeKlass_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6724 match(Set dst (DecodeNKlass src)); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6725 effect(KILL cr); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6726 format %{ "decode_heap_oop_not_null $dst,$src" %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6727 ins_encode %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6728 Register s = $src$$Register; |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6729 Register d = $dst$$Register; |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6730 if (s != d) { |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6731 __ decode_klass_not_null(d, s); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6732 } else { |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6733 __ decode_klass_not_null(d); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6734 } |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6735 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6736 ins_pipe(ialu_reg_long); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6737 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6738 |
|
113
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71
diff
changeset
|
6739 |
| 0 | 6740 //----------Conditional Move--------------------------------------------------- |
| 6741 // Jump | |
| 6742 // dummy instruction for generating temp registers | |
| 6743 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{ | |
| 6744 match(Jump (LShiftL switch_val shift)); | |
| 6745 ins_cost(350); | |
| 6746 predicate(false); | |
| 6747 effect(TEMP dest); | |
| 6748 | |
| 2008 | 6749 format %{ "leaq $dest, [$constantaddress]\n\t" |
| 0 | 6750 "jmp [$dest + $switch_val << $shift]\n\t" %} |
| 2008 | 6751 ins_encode %{ |
| 6752 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10 | |
| 6753 // to do that and the compiler is using that register as one it can allocate. | |
| 6754 // So we build it all by hand. | |
| 6755 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant); | |
| 6756 // ArrayAddress dispatch(table, index); | |
| 6757 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant); | |
| 6758 __ lea($dest$$Register, $constantaddress); | |
| 6759 __ jmp(dispatch); | |
| 6760 %} | |
| 0 | 6761 ins_pipe(pipe_jmp); |
| 6762 %} | |
| 6763 | |
| 6764 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{ | |
| 6765 match(Jump (AddL (LShiftL switch_val shift) offset)); | |
| 6766 ins_cost(350); | |
| 6767 effect(TEMP dest); | |
| 6768 | |
| 2008 | 6769 format %{ "leaq $dest, [$constantaddress]\n\t" |
| 0 | 6770 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %} |
| 2008 | 6771 ins_encode %{ |
| 6772 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10 | |
| 6773 // to do that and the compiler is using that register as one it can allocate. | |
| 6774 // So we build it all by hand. | |
| 6775 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant); | |
| 6776 // ArrayAddress dispatch(table, index); | |
| 6777 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant); | |
| 6778 __ lea($dest$$Register, $constantaddress); | |
| 6779 __ jmp(dispatch); | |
| 6780 %} | |
| 0 | 6781 ins_pipe(pipe_jmp); |
| 6782 %} | |
| 6783 | |
| 6784 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{ | |
| 6785 match(Jump switch_val); | |
| 6786 ins_cost(350); | |
| 6787 effect(TEMP dest); | |
| 6788 | |
| 2008 | 6789 format %{ "leaq $dest, [$constantaddress]\n\t" |
| 0 | 6790 "jmp [$dest + $switch_val]\n\t" %} |
| 2008 | 6791 ins_encode %{ |
| 6792 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10 | |
| 6793 // to do that and the compiler is using that register as one it can allocate. | |
| 6794 // So we build it all by hand. | |
| 6795 // Address index(noreg, switch_reg, Address::times_1); | |
| 6796 // ArrayAddress dispatch(table, index); | |
| 6797 Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1); | |
| 6798 __ lea($dest$$Register, $constantaddress); | |
| 6799 __ jmp(dispatch); | |
| 6800 %} | |
| 0 | 6801 ins_pipe(pipe_jmp); |
| 6802 %} | |
| 6803 | |
| 6804 // Conditional move | |
| 6805 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop) | |
| 6806 %{ | |
| 6807 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 6808 | |
| 6809 ins_cost(200); // XXX | |
| 6810 format %{ "cmovl$cop $dst, $src\t# signed, int" %} | |
| 6811 opcode(0x0F, 0x40); | |
| 6812 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 6813 ins_pipe(pipe_cmov_reg); | |
| 6814 %} | |
| 6815 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6816 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{ |
| 0 | 6817 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); |
| 6818 | |
| 6819 ins_cost(200); // XXX | |
| 6820 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %} | |
| 6821 opcode(0x0F, 0x40); | |
| 6822 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 6823 ins_pipe(pipe_cmov_reg); | |
| 6824 %} | |
| 6825 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6826 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6827 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6828 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6829 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6830 cmovI_regU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6831 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6832 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6833 |
| 0 | 6834 // Conditional move |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6835 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{ |
| 0 | 6836 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); |
| 6837 | |
| 6838 ins_cost(250); // XXX | |
| 6839 format %{ "cmovl$cop $dst, $src\t# signed, int" %} | |
| 6840 opcode(0x0F, 0x40); | |
| 6841 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
| 6842 ins_pipe(pipe_cmov_mem); | |
| 6843 %} | |
| 6844 | |
| 6845 // Conditional move | |
| 6846 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src) | |
| 6847 %{ | |
| 6848 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); | |
| 6849 | |
| 6850 ins_cost(250); // XXX | |
| 6851 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %} | |
| 6852 opcode(0x0F, 0x40); | |
| 6853 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
| 6854 ins_pipe(pipe_cmov_mem); | |
| 6855 %} | |
| 6856 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6857 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6858 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6859 ins_cost(250); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6860 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6861 cmovI_memU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6862 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6863 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6864 |
| 0 | 6865 // Conditional move |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6866 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop) |
|
c436414a719e
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163
diff
changeset
|
6867 %{ |
|
c436414a719e
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163
diff
changeset
|
6868 match(Set dst (CMoveN (Binary cop cr) (Binary dst src))); |
|
c436414a719e
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kvn
parents:
163
diff
changeset
|
6869 |
|
c436414a719e
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kvn
parents:
163
diff
changeset
|
6870 ins_cost(200); // XXX |
|
c436414a719e
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kvn
parents:
163
diff
changeset
|
6871 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6872 opcode(0x0F, 0x40); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6873 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6874 ins_pipe(pipe_cmov_reg); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6875 %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6876 |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6877 // Conditional move |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6878 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src) |
|
164
c436414a719e
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163
diff
changeset
|
6879 %{ |
|
c436414a719e
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kvn
parents:
163
diff
changeset
|
6880 match(Set dst (CMoveN (Binary cop cr) (Binary dst src))); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6881 |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6882 ins_cost(200); // XXX |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6883 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6884 opcode(0x0F, 0x40); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6885 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6886 ins_pipe(pipe_cmov_reg); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6887 %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6888 |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6889 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6890 match(Set dst (CMoveN (Binary cop cr) (Binary dst src))); |
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6891 ins_cost(200); |
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|
6892 expand %{ |
|
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|
6893 cmovN_regU(cop, cr, dst, src); |
|
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|
6894 %} |
|
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|
6895 %} |
|
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|
6896 |
|
164
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|
6897 // Conditional move |
| 0 | 6898 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop) |
| 6899 %{ | |
| 6900 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 6901 | |
| 6902 ins_cost(200); // XXX | |
| 6903 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %} | |
| 6904 opcode(0x0F, 0x40); | |
| 6905 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 6906 ins_pipe(pipe_cmov_reg); // XXX | |
| 6907 %} | |
| 6908 | |
| 6909 // Conditional move | |
|
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6910 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src) |
| 0 | 6911 %{ |
| 6912 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 6913 | |
| 6914 ins_cost(200); // XXX | |
| 6915 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %} | |
| 6916 opcode(0x0F, 0x40); | |
| 6917 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 6918 ins_pipe(pipe_cmov_reg); // XXX | |
| 6919 %} | |
| 6920 | |
|
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6921 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{ |
|
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6922 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); |
|
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6923 ins_cost(200); |
|
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|
6924 expand %{ |
|
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|
6925 cmovP_regU(cop, cr, dst, src); |
|
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|
6926 %} |
|
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|
6927 %} |
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|
6928 |
| 0 | 6929 // DISABLED: Requires the ADLC to emit a bottom_type call that |
| 6930 // correctly meets the two pointer arguments; one is an incoming | |
| 6931 // register but the other is a memory operand. ALSO appears to | |
| 6932 // be buggy with implicit null checks. | |
| 6933 // | |
| 6934 //// Conditional move | |
| 6935 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src) | |
| 6936 //%{ | |
| 6937 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 6938 // ins_cost(250); | |
| 6939 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 6940 // opcode(0x0F,0x40); | |
| 6941 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) ); | |
| 6942 // ins_pipe( pipe_cmov_mem ); | |
| 6943 //%} | |
| 6944 // | |
| 6945 //// Conditional move | |
| 6946 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src) | |
| 6947 //%{ | |
| 6948 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 6949 // ins_cost(250); | |
| 6950 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 6951 // opcode(0x0F,0x40); | |
| 6952 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) ); | |
| 6953 // ins_pipe( pipe_cmov_mem ); | |
| 6954 //%} | |
| 6955 | |
| 6956 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src) | |
| 6957 %{ | |
| 6958 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 6959 | |
| 6960 ins_cost(200); // XXX | |
| 6961 format %{ "cmovq$cop $dst, $src\t# signed, long" %} | |
| 6962 opcode(0x0F, 0x40); | |
| 6963 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 6964 ins_pipe(pipe_cmov_reg); // XXX | |
| 6965 %} | |
| 6966 | |
| 6967 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src) | |
| 6968 %{ | |
| 6969 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src)))); | |
| 6970 | |
| 6971 ins_cost(200); // XXX | |
| 6972 format %{ "cmovq$cop $dst, $src\t# signed, long" %} | |
| 6973 opcode(0x0F, 0x40); | |
| 6974 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
| 6975 ins_pipe(pipe_cmov_mem); // XXX | |
| 6976 %} | |
| 6977 | |
| 6978 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src) | |
| 6979 %{ | |
| 6980 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 6981 | |
| 6982 ins_cost(200); // XXX | |
| 6983 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %} | |
| 6984 opcode(0x0F, 0x40); | |
| 6985 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 6986 ins_pipe(pipe_cmov_reg); // XXX | |
| 6987 %} | |
| 6988 | |
|
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6989 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{ |
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6990 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); |
|
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6991 ins_cost(200); |
|
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|
6992 expand %{ |
|
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|
6993 cmovL_regU(cop, cr, dst, src); |
|
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|
6994 %} |
|
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|
6995 %} |
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|
6996 |
| 0 | 6997 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src) |
| 6998 %{ | |
| 6999 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src)))); | |
| 7000 | |
| 7001 ins_cost(200); // XXX | |
| 7002 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %} | |
| 7003 opcode(0x0F, 0x40); | |
| 7004 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
| 7005 ins_pipe(pipe_cmov_mem); // XXX | |
| 7006 %} | |
| 7007 | |
|
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7008 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{ |
|
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7009 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src)))); |
|
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|
7010 ins_cost(200); |
|
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|
7011 expand %{ |
|
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|
7012 cmovL_memU(cop, cr, dst, src); |
|
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|
7013 %} |
|
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|
7014 %} |
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|
7015 |
| 0 | 7016 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src) |
| 7017 %{ | |
| 7018 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 7019 | |
| 7020 ins_cost(200); // XXX | |
| 7021 format %{ "jn$cop skip\t# signed cmove float\n\t" | |
| 7022 "movss $dst, $src\n" | |
| 7023 "skip:" %} | |
| 4759 | 7024 ins_encode %{ |
| 7025 Label Lskip; | |
| 7026 // Invert sense of branch from sense of CMOV | |
| 7027 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
| 7028 __ movflt($dst$$XMMRegister, $src$$XMMRegister); | |
| 7029 __ bind(Lskip); | |
| 7030 %} | |
| 0 | 7031 ins_pipe(pipe_slow); |
| 7032 %} | |
| 7033 | |
| 7034 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src) | |
| 7035 // %{ | |
| 7036 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src)))); | |
| 7037 | |
| 7038 // ins_cost(200); // XXX | |
| 7039 // format %{ "jn$cop skip\t# signed cmove float\n\t" | |
| 7040 // "movss $dst, $src\n" | |
| 7041 // "skip:" %} | |
| 7042 // ins_encode(enc_cmovf_mem_branch(cop, dst, src)); | |
| 7043 // ins_pipe(pipe_slow); | |
| 7044 // %} | |
| 7045 | |
| 7046 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src) | |
| 7047 %{ | |
| 7048 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 7049 | |
| 7050 ins_cost(200); // XXX | |
| 7051 format %{ "jn$cop skip\t# unsigned cmove float\n\t" | |
| 7052 "movss $dst, $src\n" | |
| 7053 "skip:" %} | |
| 4759 | 7054 ins_encode %{ |
| 7055 Label Lskip; | |
| 7056 // Invert sense of branch from sense of CMOV | |
| 7057 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
| 7058 __ movflt($dst$$XMMRegister, $src$$XMMRegister); | |
| 7059 __ bind(Lskip); | |
| 7060 %} | |
| 0 | 7061 ins_pipe(pipe_slow); |
| 7062 %} | |
| 7063 | |
|
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7064 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{ |
|
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|
7065 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); |
|
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|
7066 ins_cost(200); |
|
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|
7067 expand %{ |
|
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|
7068 cmovF_regU(cop, cr, dst, src); |
|
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|
7069 %} |
|
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|
7070 %} |
|
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|
7071 |
| 0 | 7072 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src) |
| 7073 %{ | |
| 7074 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 7075 | |
| 7076 ins_cost(200); // XXX | |
| 7077 format %{ "jn$cop skip\t# signed cmove double\n\t" | |
| 7078 "movsd $dst, $src\n" | |
| 7079 "skip:" %} | |
| 4759 | 7080 ins_encode %{ |
| 7081 Label Lskip; | |
| 7082 // Invert sense of branch from sense of CMOV | |
| 7083 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
| 7084 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); | |
| 7085 __ bind(Lskip); | |
| 7086 %} | |
| 0 | 7087 ins_pipe(pipe_slow); |
| 7088 %} | |
| 7089 | |
| 7090 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src) | |
| 7091 %{ | |
| 7092 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 7093 | |
| 7094 ins_cost(200); // XXX | |
| 7095 format %{ "jn$cop skip\t# unsigned cmove double\n\t" | |
| 7096 "movsd $dst, $src\n" | |
| 7097 "skip:" %} | |
| 4759 | 7098 ins_encode %{ |
| 7099 Label Lskip; | |
| 7100 // Invert sense of branch from sense of CMOV | |
| 7101 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
| 7102 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); | |
| 7103 __ bind(Lskip); | |
| 7104 %} | |
| 0 | 7105 ins_pipe(pipe_slow); |
| 7106 %} | |
| 7107 | |
|
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|
7108 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{ |
|
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|
7109 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); |
|
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|
7110 ins_cost(200); |
|
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|
7111 expand %{ |
|
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|
7112 cmovD_regU(cop, cr, dst, src); |
|
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|
7113 %} |
|
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|
7114 %} |
|
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|
7115 |
| 0 | 7116 //----------Arithmetic Instructions-------------------------------------------- |
| 7117 //----------Addition Instructions---------------------------------------------- | |
| 7118 | |
| 7119 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 7120 %{ | |
| 7121 match(Set dst (AddI dst src)); | |
| 7122 effect(KILL cr); | |
| 7123 | |
| 7124 format %{ "addl $dst, $src\t# int" %} | |
| 7125 opcode(0x03); | |
| 7126 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 7127 ins_pipe(ialu_reg_reg); | |
| 7128 %} | |
| 7129 | |
| 7130 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 7131 %{ | |
| 7132 match(Set dst (AddI dst src)); | |
| 7133 effect(KILL cr); | |
| 7134 | |
| 7135 format %{ "addl $dst, $src\t# int" %} | |
| 7136 opcode(0x81, 0x00); /* /0 id */ | |
| 7137 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 7138 ins_pipe( ialu_reg ); | |
| 7139 %} | |
| 7140 | |
| 7141 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 7142 %{ | |
| 7143 match(Set dst (AddI dst (LoadI src))); | |
| 7144 effect(KILL cr); | |
| 7145 | |
| 7146 ins_cost(125); // XXX | |
| 7147 format %{ "addl $dst, $src\t# int" %} | |
| 7148 opcode(0x03); | |
| 7149 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 7150 ins_pipe(ialu_reg_mem); | |
| 7151 %} | |
| 7152 | |
| 7153 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 7154 %{ | |
| 7155 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7156 effect(KILL cr); | |
| 7157 | |
| 7158 ins_cost(150); // XXX | |
| 7159 format %{ "addl $dst, $src\t# int" %} | |
| 7160 opcode(0x01); /* Opcode 01 /r */ | |
| 7161 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 7162 ins_pipe(ialu_mem_reg); | |
| 7163 %} | |
| 7164 | |
| 7165 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 7166 %{ | |
| 7167 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7168 effect(KILL cr); | |
| 7169 | |
| 7170 ins_cost(125); // XXX | |
| 7171 format %{ "addl $dst, $src\t# int" %} | |
| 7172 opcode(0x81); /* Opcode 81 /0 id */ | |
| 7173 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src)); | |
| 7174 ins_pipe(ialu_mem_imm); | |
| 7175 %} | |
| 7176 | |
| 7177 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr) | |
| 7178 %{ | |
| 7179 predicate(UseIncDec); | |
| 7180 match(Set dst (AddI dst src)); | |
| 7181 effect(KILL cr); | |
| 7182 | |
| 7183 format %{ "incl $dst\t# int" %} | |
| 7184 opcode(0xFF, 0x00); // FF /0 | |
| 7185 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 7186 ins_pipe(ialu_reg); | |
| 7187 %} | |
| 7188 | |
| 7189 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr) | |
| 7190 %{ | |
| 7191 predicate(UseIncDec); | |
| 7192 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7193 effect(KILL cr); | |
| 7194 | |
| 7195 ins_cost(125); // XXX | |
| 7196 format %{ "incl $dst\t# int" %} | |
| 7197 opcode(0xFF); /* Opcode FF /0 */ | |
| 7198 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst)); | |
| 7199 ins_pipe(ialu_mem_imm); | |
| 7200 %} | |
| 7201 | |
| 7202 // XXX why does that use AddI | |
| 7203 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr) | |
| 7204 %{ | |
| 7205 predicate(UseIncDec); | |
| 7206 match(Set dst (AddI dst src)); | |
| 7207 effect(KILL cr); | |
| 7208 | |
| 7209 format %{ "decl $dst\t# int" %} | |
| 7210 opcode(0xFF, 0x01); // FF /1 | |
| 7211 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 7212 ins_pipe(ialu_reg); | |
| 7213 %} | |
| 7214 | |
| 7215 // XXX why does that use AddI | |
| 7216 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr) | |
| 7217 %{ | |
| 7218 predicate(UseIncDec); | |
| 7219 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7220 effect(KILL cr); | |
| 7221 | |
| 7222 ins_cost(125); // XXX | |
| 7223 format %{ "decl $dst\t# int" %} | |
| 7224 opcode(0xFF); /* Opcode FF /1 */ | |
| 7225 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst)); | |
| 7226 ins_pipe(ialu_mem_imm); | |
| 7227 %} | |
| 7228 | |
| 7229 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1) | |
| 7230 %{ | |
| 7231 match(Set dst (AddI src0 src1)); | |
| 7232 | |
| 7233 ins_cost(110); | |
| 7234 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %} | |
| 7235 opcode(0x8D); /* 0x8D /r */ | |
| 7236 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX | |
| 7237 ins_pipe(ialu_reg_reg); | |
| 7238 %} | |
| 7239 | |
| 7240 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 7241 %{ | |
| 7242 match(Set dst (AddL dst src)); | |
| 7243 effect(KILL cr); | |
| 7244 | |
| 7245 format %{ "addq $dst, $src\t# long" %} | |
| 7246 opcode(0x03); | |
| 7247 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 7248 ins_pipe(ialu_reg_reg); | |
| 7249 %} | |
| 7250 | |
| 7251 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
| 7252 %{ | |
| 7253 match(Set dst (AddL dst src)); | |
| 7254 effect(KILL cr); | |
| 7255 | |
| 7256 format %{ "addq $dst, $src\t# long" %} | |
| 7257 opcode(0x81, 0x00); /* /0 id */ | |
| 7258 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 7259 ins_pipe( ialu_reg ); | |
| 7260 %} | |
| 7261 | |
| 7262 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 7263 %{ | |
| 7264 match(Set dst (AddL dst (LoadL src))); | |
| 7265 effect(KILL cr); | |
| 7266 | |
| 7267 ins_cost(125); // XXX | |
| 7268 format %{ "addq $dst, $src\t# long" %} | |
| 7269 opcode(0x03); | |
| 7270 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 7271 ins_pipe(ialu_reg_mem); | |
| 7272 %} | |
| 7273 | |
| 7274 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 7275 %{ | |
| 7276 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
| 7277 effect(KILL cr); | |
| 7278 | |
| 7279 ins_cost(150); // XXX | |
| 7280 format %{ "addq $dst, $src\t# long" %} | |
| 7281 opcode(0x01); /* Opcode 01 /r */ | |
| 7282 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 7283 ins_pipe(ialu_mem_reg); | |
| 7284 %} | |
| 7285 | |
| 7286 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 7287 %{ | |
| 7288 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
| 7289 effect(KILL cr); | |
| 7290 | |
| 7291 ins_cost(125); // XXX | |
| 7292 format %{ "addq $dst, $src\t# long" %} | |
| 7293 opcode(0x81); /* Opcode 81 /0 id */ | |
| 7294 ins_encode(REX_mem_wide(dst), | |
| 7295 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src)); | |
| 7296 ins_pipe(ialu_mem_imm); | |
| 7297 %} | |
| 7298 | |
| 7299 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr) | |
| 7300 %{ | |
| 7301 predicate(UseIncDec); | |
| 7302 match(Set dst (AddL dst src)); | |
| 7303 effect(KILL cr); | |
| 7304 | |
| 7305 format %{ "incq $dst\t# long" %} | |
| 7306 opcode(0xFF, 0x00); // FF /0 | |
| 7307 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 7308 ins_pipe(ialu_reg); | |
| 7309 %} | |
| 7310 | |
| 7311 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr) | |
| 7312 %{ | |
| 7313 predicate(UseIncDec); | |
| 7314 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
| 7315 effect(KILL cr); | |
| 7316 | |
| 7317 ins_cost(125); // XXX | |
| 7318 format %{ "incq $dst\t# long" %} | |
| 7319 opcode(0xFF); /* Opcode FF /0 */ | |
| 7320 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst)); | |
| 7321 ins_pipe(ialu_mem_imm); | |
| 7322 %} | |
| 7323 | |
| 7324 // XXX why does that use AddL | |
| 7325 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr) | |
| 7326 %{ | |
| 7327 predicate(UseIncDec); | |
| 7328 match(Set dst (AddL dst src)); | |
| 7329 effect(KILL cr); | |
| 7330 | |
| 7331 format %{ "decq $dst\t# long" %} | |
| 7332 opcode(0xFF, 0x01); // FF /1 | |
| 7333 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 7334 ins_pipe(ialu_reg); | |
| 7335 %} | |
| 7336 | |
| 7337 // XXX why does that use AddL | |
| 7338 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr) | |
| 7339 %{ | |
| 7340 predicate(UseIncDec); | |
| 7341 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
| 7342 effect(KILL cr); | |
| 7343 | |
| 7344 ins_cost(125); // XXX | |
| 7345 format %{ "decq $dst\t# long" %} | |
| 7346 opcode(0xFF); /* Opcode FF /1 */ | |
| 7347 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst)); | |
| 7348 ins_pipe(ialu_mem_imm); | |
| 7349 %} | |
| 7350 | |
| 7351 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1) | |
| 7352 %{ | |
| 7353 match(Set dst (AddL src0 src1)); | |
| 7354 | |
| 7355 ins_cost(110); | |
| 7356 format %{ "leaq $dst, [$src0 + $src1]\t# long" %} | |
| 7357 opcode(0x8D); /* 0x8D /r */ | |
| 7358 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX | |
| 7359 ins_pipe(ialu_reg_reg); | |
| 7360 %} | |
| 7361 | |
| 7362 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr) | |
| 7363 %{ | |
| 7364 match(Set dst (AddP dst src)); | |
| 7365 effect(KILL cr); | |
| 7366 | |
| 7367 format %{ "addq $dst, $src\t# ptr" %} | |
| 7368 opcode(0x03); | |
| 7369 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 7370 ins_pipe(ialu_reg_reg); | |
| 7371 %} | |
| 7372 | |
| 7373 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr) | |
| 7374 %{ | |
| 7375 match(Set dst (AddP dst src)); | |
| 7376 effect(KILL cr); | |
| 7377 | |
| 7378 format %{ "addq $dst, $src\t# ptr" %} | |
| 7379 opcode(0x81, 0x00); /* /0 id */ | |
| 7380 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 7381 ins_pipe( ialu_reg ); | |
| 7382 %} | |
| 7383 | |
| 7384 // XXX addP mem ops ???? | |
| 7385 | |
| 7386 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1) | |
| 7387 %{ | |
| 7388 match(Set dst (AddP src0 src1)); | |
| 7389 | |
| 7390 ins_cost(110); | |
| 7391 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %} | |
| 7392 opcode(0x8D); /* 0x8D /r */ | |
| 7393 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX | |
| 7394 ins_pipe(ialu_reg_reg); | |
| 7395 %} | |
| 7396 | |
| 7397 instruct checkCastPP(rRegP dst) | |
| 7398 %{ | |
| 7399 match(Set dst (CheckCastPP dst)); | |
| 7400 | |
| 7401 size(0); | |
| 7402 format %{ "# checkcastPP of $dst" %} | |
| 7403 ins_encode(/* empty encoding */); | |
| 7404 ins_pipe(empty); | |
| 7405 %} | |
| 7406 | |
| 7407 instruct castPP(rRegP dst) | |
| 7408 %{ | |
| 7409 match(Set dst (CastPP dst)); | |
| 7410 | |
| 7411 size(0); | |
| 7412 format %{ "# castPP of $dst" %} | |
| 7413 ins_encode(/* empty encoding */); | |
| 7414 ins_pipe(empty); | |
| 7415 %} | |
| 7416 | |
| 7417 instruct castII(rRegI dst) | |
| 7418 %{ | |
| 7419 match(Set dst (CastII dst)); | |
| 7420 | |
| 7421 size(0); | |
| 7422 format %{ "# castII of $dst" %} | |
| 7423 ins_encode(/* empty encoding */); | |
| 7424 ins_cost(0); | |
| 7425 ins_pipe(empty); | |
| 7426 %} | |
| 7427 | |
| 7428 // LoadP-locked same as a regular LoadP when used with compare-swap | |
| 7429 instruct loadPLocked(rRegP dst, memory mem) | |
| 7430 %{ | |
| 7431 match(Set dst (LoadPLocked mem)); | |
| 7432 | |
| 7433 ins_cost(125); // XXX | |
| 7434 format %{ "movq $dst, $mem\t# ptr locked" %} | |
| 7435 opcode(0x8B); | |
| 7436 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 7437 ins_pipe(ialu_reg_mem); // XXX | |
| 7438 %} | |
| 7439 | |
| 7440 // Conditional-store of the updated heap-top. | |
| 7441 // Used during allocation of the shared heap. | |
| 7442 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel. | |
| 7443 | |
| 7444 instruct storePConditional(memory heap_top_ptr, | |
| 7445 rax_RegP oldval, rRegP newval, | |
| 7446 rFlagsReg cr) | |
| 7447 %{ | |
| 7448 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval))); | |
|
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7449 |
| 0 | 7450 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) " |
| 7451 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %} | |
| 7452 opcode(0x0F, 0xB1); | |
| 7453 ins_encode(lock_prefix, | |
| 7454 REX_reg_mem_wide(newval, heap_top_ptr), | |
| 7455 OpcP, OpcS, | |
| 7456 reg_mem(newval, heap_top_ptr)); | |
| 7457 ins_pipe(pipe_cmpxchg); | |
| 7458 %} | |
| 7459 | |
|
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7460 // Conditional-store of an int value. |
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7461 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG. |
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7462 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr) |
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7463 %{ |
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7464 match(Set cr (StoreIConditional mem (Binary oldval newval))); |
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7465 effect(KILL oldval); |
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7466 |
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7467 format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %} |
| 0 | 7468 opcode(0x0F, 0xB1); |
| 7469 ins_encode(lock_prefix, | |
|
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7470 REX_reg_mem(newval, mem), |
| 0 | 7471 OpcP, OpcS, |
|
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7472 reg_mem(newval, mem)); |
| 0 | 7473 ins_pipe(pipe_cmpxchg); |
| 7474 %} | |
| 7475 | |
|
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7476 // Conditional-store of a long value. |
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7477 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG. |
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7478 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr) |
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7479 %{ |
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7480 match(Set cr (StoreLConditional mem (Binary oldval newval))); |
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7481 effect(KILL oldval); |
|
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7482 |
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7483 format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %} |
| 0 | 7484 opcode(0x0F, 0xB1); |
| 7485 ins_encode(lock_prefix, | |
|
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7486 REX_reg_mem_wide(newval, mem), |
| 0 | 7487 OpcP, OpcS, |
|
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7488 reg_mem(newval, mem)); |
| 0 | 7489 ins_pipe(pipe_cmpxchg); |
| 7490 %} | |
| 7491 | |
|
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7492 |
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7493 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them |
| 0 | 7494 instruct compareAndSwapP(rRegI res, |
| 7495 memory mem_ptr, | |
| 7496 rax_RegP oldval, rRegP newval, | |
| 7497 rFlagsReg cr) | |
| 7498 %{ | |
|
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7499 predicate(VM_Version::supports_cx8()); |
| 0 | 7500 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); |
| 7501 effect(KILL cr, KILL oldval); | |
| 7502 | |
| 7503 format %{ "cmpxchgq $mem_ptr,$newval\t# " | |
| 7504 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" | |
| 7505 "sete $res\n\t" | |
| 7506 "movzbl $res, $res" %} | |
| 7507 opcode(0x0F, 0xB1); | |
| 7508 ins_encode(lock_prefix, | |
| 7509 REX_reg_mem_wide(newval, mem_ptr), | |
| 7510 OpcP, OpcS, | |
| 7511 reg_mem(newval, mem_ptr), | |
| 7512 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete | |
| 7513 REX_reg_breg(res, res), // movzbl | |
| 7514 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); | |
| 7515 ins_pipe( pipe_cmpxchg ); | |
| 7516 %} | |
| 7517 | |
| 7518 instruct compareAndSwapL(rRegI res, | |
| 7519 memory mem_ptr, | |
| 7520 rax_RegL oldval, rRegL newval, | |
| 7521 rFlagsReg cr) | |
| 7522 %{ | |
|
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7523 predicate(VM_Version::supports_cx8()); |
| 0 | 7524 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); |
| 7525 effect(KILL cr, KILL oldval); | |
| 7526 | |
| 7527 format %{ "cmpxchgq $mem_ptr,$newval\t# " | |
| 7528 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" | |
| 7529 "sete $res\n\t" | |
| 7530 "movzbl $res, $res" %} | |
| 7531 opcode(0x0F, 0xB1); | |
| 7532 ins_encode(lock_prefix, | |
| 7533 REX_reg_mem_wide(newval, mem_ptr), | |
| 7534 OpcP, OpcS, | |
| 7535 reg_mem(newval, mem_ptr), | |
| 7536 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete | |
| 7537 REX_reg_breg(res, res), // movzbl | |
| 7538 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); | |
| 7539 ins_pipe( pipe_cmpxchg ); | |
| 7540 %} | |
| 7541 | |
| 7542 instruct compareAndSwapI(rRegI res, | |
| 7543 memory mem_ptr, | |
| 7544 rax_RegI oldval, rRegI newval, | |
| 7545 rFlagsReg cr) | |
| 7546 %{ | |
| 7547 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); | |
| 7548 effect(KILL cr, KILL oldval); | |
| 7549 | |
| 7550 format %{ "cmpxchgl $mem_ptr,$newval\t# " | |
| 7551 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" | |
| 7552 "sete $res\n\t" | |
| 7553 "movzbl $res, $res" %} | |
| 7554 opcode(0x0F, 0xB1); | |
| 7555 ins_encode(lock_prefix, | |
| 7556 REX_reg_mem(newval, mem_ptr), | |
| 7557 OpcP, OpcS, | |
| 7558 reg_mem(newval, mem_ptr), | |
| 7559 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete | |
| 7560 REX_reg_breg(res, res), // movzbl | |
| 7561 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); | |
| 7562 ins_pipe( pipe_cmpxchg ); | |
| 7563 %} | |
| 7564 | |
| 7565 | |
|
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7566 instruct compareAndSwapN(rRegI res, |
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7567 memory mem_ptr, |
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7568 rax_RegN oldval, rRegN newval, |
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7569 rFlagsReg cr) %{ |
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7570 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); |
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7571 effect(KILL cr, KILL oldval); |
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7572 |
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7573 format %{ "cmpxchgl $mem_ptr,$newval\t# " |
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7574 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" |
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7575 "sete $res\n\t" |
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7576 "movzbl $res, $res" %} |
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7577 opcode(0x0F, 0xB1); |
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7578 ins_encode(lock_prefix, |
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|
7579 REX_reg_mem(newval, mem_ptr), |
|
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|
7580 OpcP, OpcS, |
|
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diff
changeset
|
7581 reg_mem(newval, mem_ptr), |
|
ba764ed4b6f2
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71
diff
changeset
|
7582 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete |
|
ba764ed4b6f2
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71
diff
changeset
|
7583 REX_reg_breg(res, res), // movzbl |
|
ba764ed4b6f2
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coleenp
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71
diff
changeset
|
7584 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); |
|
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diff
changeset
|
7585 ins_pipe( pipe_cmpxchg ); |
|
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|
7586 %} |
|
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71
diff
changeset
|
7587 |
|
6795
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7588 instruct xaddI_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7589 predicate(n->as_LoadStore()->result_not_used()); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7590 match(Set dummy (GetAndAddI mem add)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7591 effect(KILL cr); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7592 format %{ "ADDL [$mem],$add" %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7593 ins_encode %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7594 if (os::is_MP()) { __ lock(); } |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7595 __ addl($mem$$Address, $add$$constant); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7596 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
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6725
diff
changeset
|
7597 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7598 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7599 |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7600 instruct xaddI( memory mem, rRegI newval, rFlagsReg cr) %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7601 match(Set newval (GetAndAddI mem newval)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7602 effect(KILL cr); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7603 format %{ "XADDL [$mem],$newval" %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7604 ins_encode %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7605 if (os::is_MP()) { __ lock(); } |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7606 __ xaddl($mem$$Address, $newval$$Register); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7607 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7608 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7609 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7610 |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7611 instruct xaddL_no_res( memory mem, Universe dummy, immL add, rFlagsReg cr) %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7612 predicate(n->as_LoadStore()->result_not_used()); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7613 match(Set dummy (GetAndAddL mem add)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7614 effect(KILL cr); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7615 format %{ "ADDQ [$mem],$add" %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7616 ins_encode %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7617 if (os::is_MP()) { __ lock(); } |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7618 __ addq($mem$$Address, $add$$constant); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7619 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7620 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7621 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7622 |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7623 instruct xaddL( memory mem, rRegL newval, rFlagsReg cr) %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7624 match(Set newval (GetAndAddL mem newval)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7625 effect(KILL cr); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7626 format %{ "XADDQ [$mem],$newval" %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7627 ins_encode %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7628 if (os::is_MP()) { __ lock(); } |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7629 __ xaddq($mem$$Address, $newval$$Register); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7630 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7631 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7632 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7633 |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7634 instruct xchgI( memory mem, rRegI newval) %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7635 match(Set newval (GetAndSetI mem newval)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7636 format %{ "XCHGL $newval,[$mem]" %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7637 ins_encode %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7638 __ xchgl($newval$$Register, $mem$$Address); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7639 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7640 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7641 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7642 |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7643 instruct xchgL( memory mem, rRegL newval) %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7644 match(Set newval (GetAndSetL mem newval)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7645 format %{ "XCHGL $newval,[$mem]" %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7646 ins_encode %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7647 __ xchgq($newval$$Register, $mem$$Address); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7648 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7649 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7650 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7651 |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7652 instruct xchgP( memory mem, rRegP newval) %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7653 match(Set newval (GetAndSetP mem newval)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7654 format %{ "XCHGQ $newval,[$mem]" %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7655 ins_encode %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7656 __ xchgq($newval$$Register, $mem$$Address); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7657 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7658 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7659 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7660 |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7661 instruct xchgN( memory mem, rRegN newval) %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7662 match(Set newval (GetAndSetN mem newval)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7663 format %{ "XCHGL $newval,$mem]" %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7664 ins_encode %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7665 __ xchgl($newval$$Register, $mem$$Address); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7666 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7667 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7668 %} |
|
7eca5de9e0b6
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roland
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6725
diff
changeset
|
7669 |
| 0 | 7670 //----------Subtraction Instructions------------------------------------------- |
| 7671 | |
| 7672 // Integer Subtraction Instructions | |
| 7673 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 7674 %{ | |
| 7675 match(Set dst (SubI dst src)); | |
| 7676 effect(KILL cr); | |
| 7677 | |
| 7678 format %{ "subl $dst, $src\t# int" %} | |
| 7679 opcode(0x2B); | |
| 7680 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 7681 ins_pipe(ialu_reg_reg); | |
| 7682 %} | |
| 7683 | |
| 7684 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 7685 %{ | |
| 7686 match(Set dst (SubI dst src)); | |
| 7687 effect(KILL cr); | |
| 7688 | |
| 7689 format %{ "subl $dst, $src\t# int" %} | |
| 7690 opcode(0x81, 0x05); /* Opcode 81 /5 */ | |
| 7691 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 7692 ins_pipe(ialu_reg); | |
| 7693 %} | |
| 7694 | |
| 7695 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 7696 %{ | |
| 7697 match(Set dst (SubI dst (LoadI src))); | |
| 7698 effect(KILL cr); | |
| 7699 | |
| 7700 ins_cost(125); | |
| 7701 format %{ "subl $dst, $src\t# int" %} | |
| 7702 opcode(0x2B); | |
| 7703 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 7704 ins_pipe(ialu_reg_mem); | |
| 7705 %} | |
| 7706 | |
| 7707 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 7708 %{ | |
| 7709 match(Set dst (StoreI dst (SubI (LoadI dst) src))); | |
| 7710 effect(KILL cr); | |
| 7711 | |
| 7712 ins_cost(150); | |
| 7713 format %{ "subl $dst, $src\t# int" %} | |
| 7714 opcode(0x29); /* Opcode 29 /r */ | |
| 7715 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 7716 ins_pipe(ialu_mem_reg); | |
| 7717 %} | |
| 7718 | |
| 7719 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 7720 %{ | |
| 7721 match(Set dst (StoreI dst (SubI (LoadI dst) src))); | |
| 7722 effect(KILL cr); | |
| 7723 | |
| 7724 ins_cost(125); // XXX | |
| 7725 format %{ "subl $dst, $src\t# int" %} | |
| 7726 opcode(0x81); /* Opcode 81 /5 id */ | |
| 7727 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src)); | |
| 7728 ins_pipe(ialu_mem_imm); | |
| 7729 %} | |
| 7730 | |
| 7731 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 7732 %{ | |
| 7733 match(Set dst (SubL dst src)); | |
| 7734 effect(KILL cr); | |
| 7735 | |
| 7736 format %{ "subq $dst, $src\t# long" %} | |
| 7737 opcode(0x2B); | |
| 7738 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 7739 ins_pipe(ialu_reg_reg); | |
| 7740 %} | |
| 7741 | |
| 7742 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr) | |
| 7743 %{ | |
| 7744 match(Set dst (SubL dst src)); | |
| 7745 effect(KILL cr); | |
| 7746 | |
| 7747 format %{ "subq $dst, $src\t# long" %} | |
| 7748 opcode(0x81, 0x05); /* Opcode 81 /5 */ | |
| 7749 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 7750 ins_pipe(ialu_reg); | |
| 7751 %} | |
| 7752 | |
| 7753 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 7754 %{ | |
| 7755 match(Set dst (SubL dst (LoadL src))); | |
| 7756 effect(KILL cr); | |
| 7757 | |
| 7758 ins_cost(125); | |
| 7759 format %{ "subq $dst, $src\t# long" %} | |
| 7760 opcode(0x2B); | |
| 7761 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 7762 ins_pipe(ialu_reg_mem); | |
| 7763 %} | |
| 7764 | |
| 7765 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 7766 %{ | |
| 7767 match(Set dst (StoreL dst (SubL (LoadL dst) src))); | |
| 7768 effect(KILL cr); | |
| 7769 | |
| 7770 ins_cost(150); | |
| 7771 format %{ "subq $dst, $src\t# long" %} | |
| 7772 opcode(0x29); /* Opcode 29 /r */ | |
| 7773 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 7774 ins_pipe(ialu_mem_reg); | |
| 7775 %} | |
| 7776 | |
| 7777 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 7778 %{ | |
| 7779 match(Set dst (StoreL dst (SubL (LoadL dst) src))); | |
| 7780 effect(KILL cr); | |
| 7781 | |
| 7782 ins_cost(125); // XXX | |
| 7783 format %{ "subq $dst, $src\t# long" %} | |
| 7784 opcode(0x81); /* Opcode 81 /5 id */ | |
| 7785 ins_encode(REX_mem_wide(dst), | |
| 7786 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src)); | |
| 7787 ins_pipe(ialu_mem_imm); | |
| 7788 %} | |
| 7789 | |
| 7790 // Subtract from a pointer | |
| 7791 // XXX hmpf??? | |
| 7792 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr) | |
| 7793 %{ | |
| 7794 match(Set dst (AddP dst (SubI zero src))); | |
| 7795 effect(KILL cr); | |
| 7796 | |
| 7797 format %{ "subq $dst, $src\t# ptr - int" %} | |
| 7798 opcode(0x2B); | |
| 7799 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 7800 ins_pipe(ialu_reg_reg); | |
| 7801 %} | |
| 7802 | |
| 7803 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr) | |
| 7804 %{ | |
| 7805 match(Set dst (SubI zero dst)); | |
| 7806 effect(KILL cr); | |
| 7807 | |
| 7808 format %{ "negl $dst\t# int" %} | |
| 7809 opcode(0xF7, 0x03); // Opcode F7 /3 | |
| 7810 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 7811 ins_pipe(ialu_reg); | |
| 7812 %} | |
| 7813 | |
| 7814 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr) | |
| 7815 %{ | |
| 7816 match(Set dst (StoreI dst (SubI zero (LoadI dst)))); | |
| 7817 effect(KILL cr); | |
| 7818 | |
| 7819 format %{ "negl $dst\t# int" %} | |
| 7820 opcode(0xF7, 0x03); // Opcode F7 /3 | |
| 7821 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 7822 ins_pipe(ialu_reg); | |
| 7823 %} | |
| 7824 | |
| 7825 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr) | |
| 7826 %{ | |
| 7827 match(Set dst (SubL zero dst)); | |
| 7828 effect(KILL cr); | |
| 7829 | |
| 7830 format %{ "negq $dst\t# long" %} | |
| 7831 opcode(0xF7, 0x03); // Opcode F7 /3 | |
| 7832 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 7833 ins_pipe(ialu_reg); | |
| 7834 %} | |
| 7835 | |
| 7836 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr) | |
| 7837 %{ | |
| 7838 match(Set dst (StoreL dst (SubL zero (LoadL dst)))); | |
| 7839 effect(KILL cr); | |
| 7840 | |
| 7841 format %{ "negq $dst\t# long" %} | |
| 7842 opcode(0xF7, 0x03); // Opcode F7 /3 | |
| 7843 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 7844 ins_pipe(ialu_reg); | |
| 7845 %} | |
| 7846 | |
| 7847 | |
| 7848 //----------Multiplication/Division Instructions------------------------------- | |
| 7849 // Integer Multiplication Instructions | |
| 7850 // Multiply Register | |
| 7851 | |
| 7852 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 7853 %{ | |
| 7854 match(Set dst (MulI dst src)); | |
| 7855 effect(KILL cr); | |
| 7856 | |
| 7857 ins_cost(300); | |
| 7858 format %{ "imull $dst, $src\t# int" %} | |
| 7859 opcode(0x0F, 0xAF); | |
| 7860 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 7861 ins_pipe(ialu_reg_reg_alu0); | |
| 7862 %} | |
| 7863 | |
| 7864 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr) | |
| 7865 %{ | |
| 7866 match(Set dst (MulI src imm)); | |
| 7867 effect(KILL cr); | |
| 7868 | |
| 7869 ins_cost(300); | |
| 7870 format %{ "imull $dst, $src, $imm\t# int" %} | |
| 7871 opcode(0x69); /* 69 /r id */ | |
| 7872 ins_encode(REX_reg_reg(dst, src), | |
| 7873 OpcSE(imm), reg_reg(dst, src), Con8or32(imm)); | |
| 7874 ins_pipe(ialu_reg_reg_alu0); | |
| 7875 %} | |
| 7876 | |
| 7877 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 7878 %{ | |
| 7879 match(Set dst (MulI dst (LoadI src))); | |
| 7880 effect(KILL cr); | |
| 7881 | |
| 7882 ins_cost(350); | |
| 7883 format %{ "imull $dst, $src\t# int" %} | |
| 7884 opcode(0x0F, 0xAF); | |
| 7885 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src)); | |
| 7886 ins_pipe(ialu_reg_mem_alu0); | |
| 7887 %} | |
| 7888 | |
| 7889 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr) | |
| 7890 %{ | |
| 7891 match(Set dst (MulI (LoadI src) imm)); | |
| 7892 effect(KILL cr); | |
| 7893 | |
| 7894 ins_cost(300); | |
| 7895 format %{ "imull $dst, $src, $imm\t# int" %} | |
| 7896 opcode(0x69); /* 69 /r id */ | |
| 7897 ins_encode(REX_reg_mem(dst, src), | |
| 7898 OpcSE(imm), reg_mem(dst, src), Con8or32(imm)); | |
| 7899 ins_pipe(ialu_reg_mem_alu0); | |
| 7900 %} | |
| 7901 | |
| 7902 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 7903 %{ | |
| 7904 match(Set dst (MulL dst src)); | |
| 7905 effect(KILL cr); | |
| 7906 | |
| 7907 ins_cost(300); | |
| 7908 format %{ "imulq $dst, $src\t# long" %} | |
| 7909 opcode(0x0F, 0xAF); | |
| 7910 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 7911 ins_pipe(ialu_reg_reg_alu0); | |
| 7912 %} | |
| 7913 | |
| 7914 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr) | |
| 7915 %{ | |
| 7916 match(Set dst (MulL src imm)); | |
| 7917 effect(KILL cr); | |
| 7918 | |
| 7919 ins_cost(300); | |
| 7920 format %{ "imulq $dst, $src, $imm\t# long" %} | |
| 7921 opcode(0x69); /* 69 /r id */ | |
| 7922 ins_encode(REX_reg_reg_wide(dst, src), | |
| 7923 OpcSE(imm), reg_reg(dst, src), Con8or32(imm)); | |
| 7924 ins_pipe(ialu_reg_reg_alu0); | |
| 7925 %} | |
| 7926 | |
| 7927 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 7928 %{ | |
| 7929 match(Set dst (MulL dst (LoadL src))); | |
| 7930 effect(KILL cr); | |
| 7931 | |
| 7932 ins_cost(350); | |
| 7933 format %{ "imulq $dst, $src\t# long" %} | |
| 7934 opcode(0x0F, 0xAF); | |
| 7935 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src)); | |
| 7936 ins_pipe(ialu_reg_mem_alu0); | |
| 7937 %} | |
| 7938 | |
| 7939 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr) | |
| 7940 %{ | |
| 7941 match(Set dst (MulL (LoadL src) imm)); | |
| 7942 effect(KILL cr); | |
| 7943 | |
| 7944 ins_cost(300); | |
| 7945 format %{ "imulq $dst, $src, $imm\t# long" %} | |
| 7946 opcode(0x69); /* 69 /r id */ | |
| 7947 ins_encode(REX_reg_mem_wide(dst, src), | |
| 7948 OpcSE(imm), reg_mem(dst, src), Con8or32(imm)); | |
| 7949 ins_pipe(ialu_reg_mem_alu0); | |
| 7950 %} | |
| 7951 | |
| 145 | 7952 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr) |
| 7953 %{ | |
| 7954 match(Set dst (MulHiL src rax)); | |
| 7955 effect(USE_KILL rax, KILL cr); | |
| 7956 | |
| 7957 ins_cost(300); | |
| 7958 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %} | |
| 7959 opcode(0xF7, 0x5); /* Opcode F7 /5 */ | |
| 7960 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src)); | |
| 7961 ins_pipe(ialu_reg_reg_alu0); | |
| 7962 %} | |
| 7963 | |
| 0 | 7964 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div, |
| 7965 rFlagsReg cr) | |
| 7966 %{ | |
| 7967 match(Set rax (DivI rax div)); | |
| 7968 effect(KILL rdx, KILL cr); | |
| 7969 | |
| 7970 ins_cost(30*100+10*100); // XXX | |
| 7971 format %{ "cmpl rax, 0x80000000\t# idiv\n\t" | |
| 7972 "jne,s normal\n\t" | |
| 7973 "xorl rdx, rdx\n\t" | |
| 7974 "cmpl $div, -1\n\t" | |
| 7975 "je,s done\n" | |
| 7976 "normal: cdql\n\t" | |
| 7977 "idivl $div\n" | |
| 7978 "done:" %} | |
| 7979 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 7980 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div)); | |
| 7981 ins_pipe(ialu_reg_reg_alu0); | |
| 7982 %} | |
| 7983 | |
| 7984 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div, | |
| 7985 rFlagsReg cr) | |
| 7986 %{ | |
| 7987 match(Set rax (DivL rax div)); | |
| 7988 effect(KILL rdx, KILL cr); | |
| 7989 | |
| 7990 ins_cost(30*100+10*100); // XXX | |
| 7991 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t" | |
| 7992 "cmpq rax, rdx\n\t" | |
| 7993 "jne,s normal\n\t" | |
| 7994 "xorl rdx, rdx\n\t" | |
| 7995 "cmpq $div, -1\n\t" | |
| 7996 "je,s done\n" | |
| 7997 "normal: cdqq\n\t" | |
| 7998 "idivq $div\n" | |
| 7999 "done:" %} | |
| 8000 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8001 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div)); | |
| 8002 ins_pipe(ialu_reg_reg_alu0); | |
| 8003 %} | |
| 8004 | |
| 8005 // Integer DIVMOD with Register, both quotient and mod results | |
| 8006 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div, | |
| 8007 rFlagsReg cr) | |
| 8008 %{ | |
| 8009 match(DivModI rax div); | |
| 8010 effect(KILL cr); | |
| 8011 | |
| 8012 ins_cost(30*100+10*100); // XXX | |
| 8013 format %{ "cmpl rax, 0x80000000\t# idiv\n\t" | |
| 8014 "jne,s normal\n\t" | |
| 8015 "xorl rdx, rdx\n\t" | |
| 8016 "cmpl $div, -1\n\t" | |
| 8017 "je,s done\n" | |
| 8018 "normal: cdql\n\t" | |
| 8019 "idivl $div\n" | |
| 8020 "done:" %} | |
| 8021 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8022 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div)); | |
| 8023 ins_pipe(pipe_slow); | |
| 8024 %} | |
| 8025 | |
| 8026 // Long DIVMOD with Register, both quotient and mod results | |
| 8027 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div, | |
| 8028 rFlagsReg cr) | |
| 8029 %{ | |
| 8030 match(DivModL rax div); | |
| 8031 effect(KILL cr); | |
| 8032 | |
| 8033 ins_cost(30*100+10*100); // XXX | |
| 8034 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t" | |
| 8035 "cmpq rax, rdx\n\t" | |
| 8036 "jne,s normal\n\t" | |
| 8037 "xorl rdx, rdx\n\t" | |
| 8038 "cmpq $div, -1\n\t" | |
| 8039 "je,s done\n" | |
| 8040 "normal: cdqq\n\t" | |
| 8041 "idivq $div\n" | |
| 8042 "done:" %} | |
| 8043 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8044 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div)); | |
| 8045 ins_pipe(pipe_slow); | |
| 8046 %} | |
| 8047 | |
| 8048 //----------- DivL-By-Constant-Expansions-------------------------------------- | |
| 8049 // DivI cases are handled by the compiler | |
| 8050 | |
| 605 | 8051 // Magic constant, reciprocal of 10 |
| 0 | 8052 instruct loadConL_0x6666666666666667(rRegL dst) |
| 8053 %{ | |
| 8054 effect(DEF dst); | |
| 8055 | |
| 8056 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %} | |
| 8057 ins_encode(load_immL(dst, 0x6666666666666667)); | |
| 8058 ins_pipe(ialu_reg); | |
| 8059 %} | |
| 8060 | |
| 8061 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr) | |
| 8062 %{ | |
| 8063 effect(DEF dst, USE src, USE_KILL rax, KILL cr); | |
| 8064 | |
| 8065 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %} | |
| 8066 opcode(0xF7, 0x5); /* Opcode F7 /5 */ | |
| 8067 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src)); | |
| 8068 ins_pipe(ialu_reg_reg_alu0); | |
| 8069 %} | |
| 8070 | |
| 8071 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr) | |
| 8072 %{ | |
| 8073 effect(USE_DEF dst, KILL cr); | |
| 8074 | |
| 8075 format %{ "sarq $dst, #63\t# Used in div-by-10" %} | |
| 8076 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8077 ins_encode(reg_opc_imm_wide(dst, 0x3F)); | |
| 8078 ins_pipe(ialu_reg); | |
| 8079 %} | |
| 8080 | |
| 8081 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr) | |
| 8082 %{ | |
| 8083 effect(USE_DEF dst, KILL cr); | |
| 8084 | |
| 8085 format %{ "sarq $dst, #2\t# Used in div-by-10" %} | |
| 8086 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8087 ins_encode(reg_opc_imm_wide(dst, 0x2)); | |
| 8088 ins_pipe(ialu_reg); | |
| 8089 %} | |
| 8090 | |
| 8091 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div) | |
| 8092 %{ | |
| 8093 match(Set dst (DivL src div)); | |
| 8094 | |
| 8095 ins_cost((5+8)*100); | |
| 8096 expand %{ | |
| 8097 rax_RegL rax; // Killed temp | |
| 8098 rFlagsReg cr; // Killed | |
| 8099 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667 | |
| 8100 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src | |
| 8101 sarL_rReg_63(src, cr); // sarq src, 63 | |
| 8102 sarL_rReg_2(dst, cr); // sarq rdx, 2 | |
| 8103 subL_rReg(dst, src, cr); // subl rdx, src | |
| 8104 %} | |
| 8105 %} | |
| 8106 | |
| 8107 //----------------------------------------------------------------------------- | |
| 8108 | |
| 8109 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div, | |
| 8110 rFlagsReg cr) | |
| 8111 %{ | |
| 8112 match(Set rdx (ModI rax div)); | |
| 8113 effect(KILL rax, KILL cr); | |
| 8114 | |
| 8115 ins_cost(300); // XXX | |
| 8116 format %{ "cmpl rax, 0x80000000\t# irem\n\t" | |
| 8117 "jne,s normal\n\t" | |
| 8118 "xorl rdx, rdx\n\t" | |
| 8119 "cmpl $div, -1\n\t" | |
| 8120 "je,s done\n" | |
| 8121 "normal: cdql\n\t" | |
| 8122 "idivl $div\n" | |
| 8123 "done:" %} | |
| 8124 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8125 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div)); | |
| 8126 ins_pipe(ialu_reg_reg_alu0); | |
| 8127 %} | |
| 8128 | |
| 8129 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div, | |
| 8130 rFlagsReg cr) | |
| 8131 %{ | |
| 8132 match(Set rdx (ModL rax div)); | |
| 8133 effect(KILL rax, KILL cr); | |
| 8134 | |
| 8135 ins_cost(300); // XXX | |
| 8136 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t" | |
| 8137 "cmpq rax, rdx\n\t" | |
| 8138 "jne,s normal\n\t" | |
| 8139 "xorl rdx, rdx\n\t" | |
| 8140 "cmpq $div, -1\n\t" | |
| 8141 "je,s done\n" | |
| 8142 "normal: cdqq\n\t" | |
| 8143 "idivq $div\n" | |
| 8144 "done:" %} | |
| 8145 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8146 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div)); | |
| 8147 ins_pipe(ialu_reg_reg_alu0); | |
| 8148 %} | |
| 8149 | |
| 8150 // Integer Shift Instructions | |
| 8151 // Shift Left by one | |
| 8152 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr) | |
| 8153 %{ | |
| 8154 match(Set dst (LShiftI dst shift)); | |
| 8155 effect(KILL cr); | |
| 8156 | |
| 8157 format %{ "sall $dst, $shift" %} | |
| 8158 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 8159 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8160 ins_pipe(ialu_reg); | |
| 8161 %} | |
| 8162 | |
| 8163 // Shift Left by one | |
| 8164 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 8165 %{ | |
| 8166 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift))); | |
| 8167 effect(KILL cr); | |
| 8168 | |
| 8169 format %{ "sall $dst, $shift\t" %} | |
| 8170 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 8171 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8172 ins_pipe(ialu_mem_imm); | |
| 8173 %} | |
| 8174 | |
| 8175 // Shift Left by 8-bit immediate | |
| 8176 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) | |
| 8177 %{ | |
| 8178 match(Set dst (LShiftI dst shift)); | |
| 8179 effect(KILL cr); | |
| 8180 | |
| 8181 format %{ "sall $dst, $shift" %} | |
| 8182 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 8183 ins_encode(reg_opc_imm(dst, shift)); | |
| 8184 ins_pipe(ialu_reg); | |
| 8185 %} | |
| 8186 | |
| 8187 // Shift Left by 8-bit immediate | |
| 8188 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 8189 %{ | |
| 8190 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift))); | |
| 8191 effect(KILL cr); | |
| 8192 | |
| 8193 format %{ "sall $dst, $shift" %} | |
| 8194 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 8195 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 8196 ins_pipe(ialu_mem_imm); | |
| 8197 %} | |
| 8198 | |
| 8199 // Shift Left by variable | |
| 8200 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 8201 %{ | |
| 8202 match(Set dst (LShiftI dst shift)); | |
| 8203 effect(KILL cr); | |
| 8204 | |
| 8205 format %{ "sall $dst, $shift" %} | |
| 8206 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 8207 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8208 ins_pipe(ialu_reg_reg); | |
| 8209 %} | |
| 8210 | |
| 8211 // Shift Left by variable | |
| 8212 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 8213 %{ | |
| 8214 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift))); | |
| 8215 effect(KILL cr); | |
| 8216 | |
| 8217 format %{ "sall $dst, $shift" %} | |
| 8218 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 8219 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8220 ins_pipe(ialu_mem_reg); | |
| 8221 %} | |
| 8222 | |
| 8223 // Arithmetic shift right by one | |
| 8224 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr) | |
| 8225 %{ | |
| 8226 match(Set dst (RShiftI dst shift)); | |
| 8227 effect(KILL cr); | |
| 8228 | |
| 8229 format %{ "sarl $dst, $shift" %} | |
| 8230 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 8231 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8232 ins_pipe(ialu_reg); | |
| 8233 %} | |
| 8234 | |
| 8235 // Arithmetic shift right by one | |
| 8236 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 8237 %{ | |
| 8238 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 8239 effect(KILL cr); | |
| 8240 | |
| 8241 format %{ "sarl $dst, $shift" %} | |
| 8242 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 8243 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8244 ins_pipe(ialu_mem_imm); | |
| 8245 %} | |
| 8246 | |
| 8247 // Arithmetic Shift Right by 8-bit immediate | |
| 8248 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) | |
| 8249 %{ | |
| 8250 match(Set dst (RShiftI dst shift)); | |
| 8251 effect(KILL cr); | |
| 8252 | |
| 8253 format %{ "sarl $dst, $shift" %} | |
| 8254 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8255 ins_encode(reg_opc_imm(dst, shift)); | |
| 8256 ins_pipe(ialu_mem_imm); | |
| 8257 %} | |
| 8258 | |
| 8259 // Arithmetic Shift Right by 8-bit immediate | |
| 8260 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 8261 %{ | |
| 8262 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 8263 effect(KILL cr); | |
| 8264 | |
| 8265 format %{ "sarl $dst, $shift" %} | |
| 8266 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8267 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 8268 ins_pipe(ialu_mem_imm); | |
| 8269 %} | |
| 8270 | |
| 8271 // Arithmetic Shift Right by variable | |
| 8272 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 8273 %{ | |
| 8274 match(Set dst (RShiftI dst shift)); | |
| 8275 effect(KILL cr); | |
| 8276 | |
| 8277 format %{ "sarl $dst, $shift" %} | |
| 8278 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 8279 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8280 ins_pipe(ialu_reg_reg); | |
| 8281 %} | |
| 8282 | |
| 8283 // Arithmetic Shift Right by variable | |
| 8284 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 8285 %{ | |
| 8286 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 8287 effect(KILL cr); | |
| 8288 | |
| 8289 format %{ "sarl $dst, $shift" %} | |
| 8290 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 8291 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8292 ins_pipe(ialu_mem_reg); | |
| 8293 %} | |
| 8294 | |
| 8295 // Logical shift right by one | |
| 8296 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr) | |
| 8297 %{ | |
| 8298 match(Set dst (URShiftI dst shift)); | |
| 8299 effect(KILL cr); | |
| 8300 | |
| 8301 format %{ "shrl $dst, $shift" %} | |
| 8302 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 8303 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8304 ins_pipe(ialu_reg); | |
| 8305 %} | |
| 8306 | |
| 8307 // Logical shift right by one | |
| 8308 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 8309 %{ | |
| 8310 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift))); | |
| 8311 effect(KILL cr); | |
| 8312 | |
| 8313 format %{ "shrl $dst, $shift" %} | |
| 8314 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 8315 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8316 ins_pipe(ialu_mem_imm); | |
| 8317 %} | |
| 8318 | |
| 8319 // Logical Shift Right by 8-bit immediate | |
| 8320 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) | |
| 8321 %{ | |
| 8322 match(Set dst (URShiftI dst shift)); | |
| 8323 effect(KILL cr); | |
| 8324 | |
| 8325 format %{ "shrl $dst, $shift" %} | |
| 8326 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 8327 ins_encode(reg_opc_imm(dst, shift)); | |
| 8328 ins_pipe(ialu_reg); | |
| 8329 %} | |
| 8330 | |
| 8331 // Logical Shift Right by 8-bit immediate | |
| 8332 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 8333 %{ | |
| 8334 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift))); | |
| 8335 effect(KILL cr); | |
| 8336 | |
| 8337 format %{ "shrl $dst, $shift" %} | |
| 8338 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 8339 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 8340 ins_pipe(ialu_mem_imm); | |
| 8341 %} | |
| 8342 | |
| 8343 // Logical Shift Right by variable | |
| 8344 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 8345 %{ | |
| 8346 match(Set dst (URShiftI dst shift)); | |
| 8347 effect(KILL cr); | |
| 8348 | |
| 8349 format %{ "shrl $dst, $shift" %} | |
| 8350 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 8351 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8352 ins_pipe(ialu_reg_reg); | |
| 8353 %} | |
| 8354 | |
| 8355 // Logical Shift Right by variable | |
| 8356 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 8357 %{ | |
| 8358 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift))); | |
| 8359 effect(KILL cr); | |
| 8360 | |
| 8361 format %{ "shrl $dst, $shift" %} | |
| 8362 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 8363 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8364 ins_pipe(ialu_mem_reg); | |
| 8365 %} | |
| 8366 | |
| 8367 // Long Shift Instructions | |
| 8368 // Shift Left by one | |
| 8369 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr) | |
| 8370 %{ | |
| 8371 match(Set dst (LShiftL dst shift)); | |
| 8372 effect(KILL cr); | |
| 8373 | |
| 8374 format %{ "salq $dst, $shift" %} | |
| 8375 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 8376 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8377 ins_pipe(ialu_reg); | |
| 8378 %} | |
| 8379 | |
| 8380 // Shift Left by one | |
| 8381 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 8382 %{ | |
| 8383 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift))); | |
| 8384 effect(KILL cr); | |
| 8385 | |
| 8386 format %{ "salq $dst, $shift" %} | |
| 8387 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 8388 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8389 ins_pipe(ialu_mem_imm); | |
| 8390 %} | |
| 8391 | |
| 8392 // Shift Left by 8-bit immediate | |
| 8393 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr) | |
| 8394 %{ | |
| 8395 match(Set dst (LShiftL dst shift)); | |
| 8396 effect(KILL cr); | |
| 8397 | |
| 8398 format %{ "salq $dst, $shift" %} | |
| 8399 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 8400 ins_encode(reg_opc_imm_wide(dst, shift)); | |
| 8401 ins_pipe(ialu_reg); | |
| 8402 %} | |
| 8403 | |
| 8404 // Shift Left by 8-bit immediate | |
| 8405 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 8406 %{ | |
| 8407 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift))); | |
| 8408 effect(KILL cr); | |
| 8409 | |
| 8410 format %{ "salq $dst, $shift" %} | |
| 8411 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 8412 ins_encode(REX_mem_wide(dst), OpcP, | |
| 8413 RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 8414 ins_pipe(ialu_mem_imm); | |
| 8415 %} | |
| 8416 | |
| 8417 // Shift Left by variable | |
| 8418 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 8419 %{ | |
| 8420 match(Set dst (LShiftL dst shift)); | |
| 8421 effect(KILL cr); | |
| 8422 | |
| 8423 format %{ "salq $dst, $shift" %} | |
| 8424 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 8425 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8426 ins_pipe(ialu_reg_reg); | |
| 8427 %} | |
| 8428 | |
| 8429 // Shift Left by variable | |
| 8430 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 8431 %{ | |
| 8432 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift))); | |
| 8433 effect(KILL cr); | |
| 8434 | |
| 8435 format %{ "salq $dst, $shift" %} | |
| 8436 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 8437 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8438 ins_pipe(ialu_mem_reg); | |
| 8439 %} | |
| 8440 | |
| 8441 // Arithmetic shift right by one | |
| 8442 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr) | |
| 8443 %{ | |
| 8444 match(Set dst (RShiftL dst shift)); | |
| 8445 effect(KILL cr); | |
| 8446 | |
| 8447 format %{ "sarq $dst, $shift" %} | |
| 8448 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 8449 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8450 ins_pipe(ialu_reg); | |
| 8451 %} | |
| 8452 | |
| 8453 // Arithmetic shift right by one | |
| 8454 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 8455 %{ | |
| 8456 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift))); | |
| 8457 effect(KILL cr); | |
| 8458 | |
| 8459 format %{ "sarq $dst, $shift" %} | |
| 8460 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 8461 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8462 ins_pipe(ialu_mem_imm); | |
| 8463 %} | |
| 8464 | |
| 8465 // Arithmetic Shift Right by 8-bit immediate | |
| 8466 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr) | |
| 8467 %{ | |
| 8468 match(Set dst (RShiftL dst shift)); | |
| 8469 effect(KILL cr); | |
| 8470 | |
| 8471 format %{ "sarq $dst, $shift" %} | |
| 8472 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8473 ins_encode(reg_opc_imm_wide(dst, shift)); | |
| 8474 ins_pipe(ialu_mem_imm); | |
| 8475 %} | |
| 8476 | |
| 8477 // Arithmetic Shift Right by 8-bit immediate | |
| 8478 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 8479 %{ | |
| 8480 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift))); | |
| 8481 effect(KILL cr); | |
| 8482 | |
| 8483 format %{ "sarq $dst, $shift" %} | |
| 8484 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8485 ins_encode(REX_mem_wide(dst), OpcP, | |
| 8486 RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 8487 ins_pipe(ialu_mem_imm); | |
| 8488 %} | |
| 8489 | |
| 8490 // Arithmetic Shift Right by variable | |
| 8491 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 8492 %{ | |
| 8493 match(Set dst (RShiftL dst shift)); | |
| 8494 effect(KILL cr); | |
| 8495 | |
| 8496 format %{ "sarq $dst, $shift" %} | |
| 8497 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 8498 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8499 ins_pipe(ialu_reg_reg); | |
| 8500 %} | |
| 8501 | |
| 8502 // Arithmetic Shift Right by variable | |
| 8503 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 8504 %{ | |
| 8505 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift))); | |
| 8506 effect(KILL cr); | |
| 8507 | |
| 8508 format %{ "sarq $dst, $shift" %} | |
| 8509 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 8510 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8511 ins_pipe(ialu_mem_reg); | |
| 8512 %} | |
| 8513 | |
| 8514 // Logical shift right by one | |
| 8515 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr) | |
| 8516 %{ | |
| 8517 match(Set dst (URShiftL dst shift)); | |
| 8518 effect(KILL cr); | |
| 8519 | |
| 8520 format %{ "shrq $dst, $shift" %} | |
| 8521 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 8522 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst )); | |
| 8523 ins_pipe(ialu_reg); | |
| 8524 %} | |
| 8525 | |
| 8526 // Logical shift right by one | |
| 8527 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 8528 %{ | |
| 8529 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift))); | |
| 8530 effect(KILL cr); | |
| 8531 | |
| 8532 format %{ "shrq $dst, $shift" %} | |
| 8533 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 8534 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8535 ins_pipe(ialu_mem_imm); | |
| 8536 %} | |
| 8537 | |
| 8538 // Logical Shift Right by 8-bit immediate | |
| 8539 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr) | |
| 8540 %{ | |
| 8541 match(Set dst (URShiftL dst shift)); | |
| 8542 effect(KILL cr); | |
| 8543 | |
| 8544 format %{ "shrq $dst, $shift" %} | |
| 8545 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 8546 ins_encode(reg_opc_imm_wide(dst, shift)); | |
| 8547 ins_pipe(ialu_reg); | |
| 8548 %} | |
| 8549 | |
|
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|
8550 |
| 0 | 8551 // Logical Shift Right by 8-bit immediate |
| 8552 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 8553 %{ | |
| 8554 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift))); | |
| 8555 effect(KILL cr); | |
| 8556 | |
| 8557 format %{ "shrq $dst, $shift" %} | |
| 8558 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 8559 ins_encode(REX_mem_wide(dst), OpcP, | |
| 8560 RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 8561 ins_pipe(ialu_mem_imm); | |
| 8562 %} | |
| 8563 | |
| 8564 // Logical Shift Right by variable | |
| 8565 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 8566 %{ | |
| 8567 match(Set dst (URShiftL dst shift)); | |
| 8568 effect(KILL cr); | |
| 8569 | |
| 8570 format %{ "shrq $dst, $shift" %} | |
| 8571 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 8572 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8573 ins_pipe(ialu_reg_reg); | |
| 8574 %} | |
| 8575 | |
| 8576 // Logical Shift Right by variable | |
| 8577 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 8578 %{ | |
| 8579 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift))); | |
| 8580 effect(KILL cr); | |
| 8581 | |
| 8582 format %{ "shrq $dst, $shift" %} | |
| 8583 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 8584 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8585 ins_pipe(ialu_mem_reg); | |
| 8586 %} | |
| 8587 | |
| 8588 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24. | |
| 8589 // This idiom is used by the compiler for the i2b bytecode. | |
| 8590 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour) | |
| 8591 %{ | |
| 8592 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour)); | |
| 8593 | |
| 8594 format %{ "movsbl $dst, $src\t# i2b" %} | |
| 8595 opcode(0x0F, 0xBE); | |
| 8596 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 8597 ins_pipe(ialu_reg_reg); | |
| 8598 %} | |
| 8599 | |
| 8600 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16. | |
| 8601 // This idiom is used by the compiler the i2s bytecode. | |
| 8602 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen) | |
| 8603 %{ | |
| 8604 match(Set dst (RShiftI (LShiftI src sixteen) sixteen)); | |
| 8605 | |
| 8606 format %{ "movswl $dst, $src\t# i2s" %} | |
| 8607 opcode(0x0F, 0xBF); | |
| 8608 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 8609 ins_pipe(ialu_reg_reg); | |
| 8610 %} | |
| 8611 | |
| 8612 // ROL/ROR instructions | |
| 8613 | |
| 8614 // ROL expand | |
| 8615 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{ | |
| 8616 effect(KILL cr, USE_DEF dst); | |
| 8617 | |
| 8618 format %{ "roll $dst" %} | |
| 8619 opcode(0xD1, 0x0); /* Opcode D1 /0 */ | |
| 8620 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8621 ins_pipe(ialu_reg); | |
| 8622 %} | |
| 8623 | |
| 8624 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{ | |
| 8625 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8626 | |
| 8627 format %{ "roll $dst, $shift" %} | |
| 8628 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */ | |
| 8629 ins_encode( reg_opc_imm(dst, shift) ); | |
| 8630 ins_pipe(ialu_reg); | |
| 8631 %} | |
| 8632 | |
| 8633 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 8634 %{ | |
| 8635 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8636 | |
| 8637 format %{ "roll $dst, $shift" %} | |
| 8638 opcode(0xD3, 0x0); /* Opcode D3 /0 */ | |
| 8639 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8640 ins_pipe(ialu_reg_reg); | |
| 8641 %} | |
| 8642 // end of ROL expand | |
| 8643 | |
| 8644 // Rotate Left by one | |
| 8645 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr) | |
| 8646 %{ | |
| 8647 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift))); | |
| 8648 | |
| 8649 expand %{ | |
| 8650 rolI_rReg_imm1(dst, cr); | |
| 8651 %} | |
| 8652 %} | |
| 8653 | |
| 8654 // Rotate Left by 8-bit immediate | |
| 8655 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr) | |
| 8656 %{ | |
| 8657 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); | |
| 8658 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift))); | |
| 8659 | |
| 8660 expand %{ | |
| 8661 rolI_rReg_imm8(dst, lshift, cr); | |
| 8662 %} | |
| 8663 %} | |
| 8664 | |
| 8665 // Rotate Left by variable | |
| 8666 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
| 8667 %{ | |
| 8668 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift)))); | |
| 8669 | |
| 8670 expand %{ | |
| 8671 rolI_rReg_CL(dst, shift, cr); | |
| 8672 %} | |
| 8673 %} | |
| 8674 | |
| 8675 // Rotate Left by variable | |
| 8676 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr) | |
| 8677 %{ | |
| 8678 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift)))); | |
| 8679 | |
| 8680 expand %{ | |
| 8681 rolI_rReg_CL(dst, shift, cr); | |
| 8682 %} | |
| 8683 %} | |
| 8684 | |
| 8685 // ROR expand | |
| 8686 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr) | |
| 8687 %{ | |
| 8688 effect(USE_DEF dst, KILL cr); | |
| 8689 | |
| 8690 format %{ "rorl $dst" %} | |
| 8691 opcode(0xD1, 0x1); /* D1 /1 */ | |
| 8692 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8693 ins_pipe(ialu_reg); | |
| 8694 %} | |
| 8695 | |
| 8696 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) | |
| 8697 %{ | |
| 8698 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8699 | |
| 8700 format %{ "rorl $dst, $shift" %} | |
| 8701 opcode(0xC1, 0x1); /* C1 /1 ib */ | |
| 8702 ins_encode(reg_opc_imm(dst, shift)); | |
| 8703 ins_pipe(ialu_reg); | |
| 8704 %} | |
| 8705 | |
| 8706 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 8707 %{ | |
| 8708 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8709 | |
| 8710 format %{ "rorl $dst, $shift" %} | |
| 8711 opcode(0xD3, 0x1); /* D3 /1 */ | |
| 8712 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8713 ins_pipe(ialu_reg_reg); | |
| 8714 %} | |
| 8715 // end of ROR expand | |
| 8716 | |
| 8717 // Rotate Right by one | |
| 8718 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr) | |
| 8719 %{ | |
| 8720 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift))); | |
| 8721 | |
| 8722 expand %{ | |
| 8723 rorI_rReg_imm1(dst, cr); | |
| 8724 %} | |
| 8725 %} | |
| 8726 | |
| 8727 // Rotate Right by 8-bit immediate | |
| 8728 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr) | |
| 8729 %{ | |
| 8730 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); | |
| 8731 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift))); | |
| 8732 | |
| 8733 expand %{ | |
| 8734 rorI_rReg_imm8(dst, rshift, cr); | |
| 8735 %} | |
| 8736 %} | |
| 8737 | |
| 8738 // Rotate Right by variable | |
| 8739 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
| 8740 %{ | |
| 8741 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift)))); | |
| 8742 | |
| 8743 expand %{ | |
| 8744 rorI_rReg_CL(dst, shift, cr); | |
| 8745 %} | |
| 8746 %} | |
| 8747 | |
| 8748 // Rotate Right by variable | |
| 8749 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr) | |
| 8750 %{ | |
| 8751 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift)))); | |
| 8752 | |
| 8753 expand %{ | |
| 8754 rorI_rReg_CL(dst, shift, cr); | |
| 8755 %} | |
| 8756 %} | |
| 8757 | |
| 8758 // for long rotate | |
| 8759 // ROL expand | |
| 8760 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{ | |
| 8761 effect(USE_DEF dst, KILL cr); | |
| 8762 | |
| 8763 format %{ "rolq $dst" %} | |
| 8764 opcode(0xD1, 0x0); /* Opcode D1 /0 */ | |
| 8765 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8766 ins_pipe(ialu_reg); | |
| 8767 %} | |
| 8768 | |
| 8769 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{ | |
| 8770 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8771 | |
| 8772 format %{ "rolq $dst, $shift" %} | |
| 8773 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */ | |
| 8774 ins_encode( reg_opc_imm_wide(dst, shift) ); | |
| 8775 ins_pipe(ialu_reg); | |
| 8776 %} | |
| 8777 | |
| 8778 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 8779 %{ | |
| 8780 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8781 | |
| 8782 format %{ "rolq $dst, $shift" %} | |
| 8783 opcode(0xD3, 0x0); /* Opcode D3 /0 */ | |
| 8784 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8785 ins_pipe(ialu_reg_reg); | |
| 8786 %} | |
| 8787 // end of ROL expand | |
| 8788 | |
| 8789 // Rotate Left by one | |
| 8790 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr) | |
| 8791 %{ | |
| 8792 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift))); | |
| 8793 | |
| 8794 expand %{ | |
| 8795 rolL_rReg_imm1(dst, cr); | |
| 8796 %} | |
| 8797 %} | |
| 8798 | |
| 8799 // Rotate Left by 8-bit immediate | |
| 8800 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr) | |
| 8801 %{ | |
| 8802 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f)); | |
| 8803 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift))); | |
| 8804 | |
| 8805 expand %{ | |
| 8806 rolL_rReg_imm8(dst, lshift, cr); | |
| 8807 %} | |
| 8808 %} | |
| 8809 | |
| 8810 // Rotate Left by variable | |
| 8811 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
| 8812 %{ | |
| 8813 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift)))); | |
| 8814 | |
| 8815 expand %{ | |
| 8816 rolL_rReg_CL(dst, shift, cr); | |
| 8817 %} | |
| 8818 %} | |
| 8819 | |
| 8820 // Rotate Left by variable | |
| 8821 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr) | |
| 8822 %{ | |
| 8823 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift)))); | |
| 8824 | |
| 8825 expand %{ | |
| 8826 rolL_rReg_CL(dst, shift, cr); | |
| 8827 %} | |
| 8828 %} | |
| 8829 | |
| 8830 // ROR expand | |
| 8831 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr) | |
| 8832 %{ | |
| 8833 effect(USE_DEF dst, KILL cr); | |
| 8834 | |
| 8835 format %{ "rorq $dst" %} | |
| 8836 opcode(0xD1, 0x1); /* D1 /1 */ | |
| 8837 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8838 ins_pipe(ialu_reg); | |
| 8839 %} | |
| 8840 | |
| 8841 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) | |
| 8842 %{ | |
| 8843 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8844 | |
| 8845 format %{ "rorq $dst, $shift" %} | |
| 8846 opcode(0xC1, 0x1); /* C1 /1 ib */ | |
| 8847 ins_encode(reg_opc_imm_wide(dst, shift)); | |
| 8848 ins_pipe(ialu_reg); | |
| 8849 %} | |
| 8850 | |
| 8851 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 8852 %{ | |
| 8853 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8854 | |
| 8855 format %{ "rorq $dst, $shift" %} | |
| 8856 opcode(0xD3, 0x1); /* D3 /1 */ | |
| 8857 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8858 ins_pipe(ialu_reg_reg); | |
| 8859 %} | |
| 8860 // end of ROR expand | |
| 8861 | |
| 8862 // Rotate Right by one | |
| 8863 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr) | |
| 8864 %{ | |
| 8865 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift))); | |
| 8866 | |
| 8867 expand %{ | |
| 8868 rorL_rReg_imm1(dst, cr); | |
| 8869 %} | |
| 8870 %} | |
| 8871 | |
| 8872 // Rotate Right by 8-bit immediate | |
| 8873 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr) | |
| 8874 %{ | |
| 8875 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f)); | |
| 8876 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift))); | |
| 8877 | |
| 8878 expand %{ | |
| 8879 rorL_rReg_imm8(dst, rshift, cr); | |
| 8880 %} | |
| 8881 %} | |
| 8882 | |
| 8883 // Rotate Right by variable | |
| 8884 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
| 8885 %{ | |
| 8886 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift)))); | |
| 8887 | |
| 8888 expand %{ | |
| 8889 rorL_rReg_CL(dst, shift, cr); | |
| 8890 %} | |
| 8891 %} | |
| 8892 | |
| 8893 // Rotate Right by variable | |
| 8894 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr) | |
| 8895 %{ | |
| 8896 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift)))); | |
| 8897 | |
| 8898 expand %{ | |
| 8899 rorL_rReg_CL(dst, shift, cr); | |
| 8900 %} | |
| 8901 %} | |
| 8902 | |
| 8903 // Logical Instructions | |
| 8904 | |
| 8905 // Integer Logical Instructions | |
| 8906 | |
| 8907 // And Instructions | |
| 8908 // And Register with Register | |
| 8909 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 8910 %{ | |
| 8911 match(Set dst (AndI dst src)); | |
| 8912 effect(KILL cr); | |
| 8913 | |
| 8914 format %{ "andl $dst, $src\t# int" %} | |
| 8915 opcode(0x23); | |
| 8916 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 8917 ins_pipe(ialu_reg_reg); | |
| 8918 %} | |
| 8919 | |
| 8920 // And Register with Immediate 255 | |
| 8921 instruct andI_rReg_imm255(rRegI dst, immI_255 src) | |
| 8922 %{ | |
| 8923 match(Set dst (AndI dst src)); | |
| 8924 | |
| 8925 format %{ "movzbl $dst, $dst\t# int & 0xFF" %} | |
| 8926 opcode(0x0F, 0xB6); | |
| 8927 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 8928 ins_pipe(ialu_reg); | |
| 8929 %} | |
| 8930 | |
| 8931 // And Register with Immediate 255 and promote to long | |
| 8932 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask) | |
| 8933 %{ | |
| 8934 match(Set dst (ConvI2L (AndI src mask))); | |
| 8935 | |
| 8936 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %} | |
| 8937 opcode(0x0F, 0xB6); | |
| 8938 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 8939 ins_pipe(ialu_reg); | |
| 8940 %} | |
| 8941 | |
| 8942 // And Register with Immediate 65535 | |
| 8943 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src) | |
| 8944 %{ | |
| 8945 match(Set dst (AndI dst src)); | |
| 8946 | |
| 8947 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %} | |
| 8948 opcode(0x0F, 0xB7); | |
| 8949 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 8950 ins_pipe(ialu_reg); | |
| 8951 %} | |
| 8952 | |
| 8953 // And Register with Immediate 65535 and promote to long | |
| 8954 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask) | |
| 8955 %{ | |
| 8956 match(Set dst (ConvI2L (AndI src mask))); | |
| 8957 | |
| 8958 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %} | |
| 8959 opcode(0x0F, 0xB7); | |
| 8960 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 8961 ins_pipe(ialu_reg); | |
| 8962 %} | |
| 8963 | |
| 8964 // And Register with Immediate | |
| 8965 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 8966 %{ | |
| 8967 match(Set dst (AndI dst src)); | |
| 8968 effect(KILL cr); | |
| 8969 | |
| 8970 format %{ "andl $dst, $src\t# int" %} | |
| 8971 opcode(0x81, 0x04); /* Opcode 81 /4 */ | |
| 8972 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 8973 ins_pipe(ialu_reg); | |
| 8974 %} | |
| 8975 | |
| 8976 // And Register with Memory | |
| 8977 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 8978 %{ | |
| 8979 match(Set dst (AndI dst (LoadI src))); | |
| 8980 effect(KILL cr); | |
| 8981 | |
| 8982 ins_cost(125); | |
| 8983 format %{ "andl $dst, $src\t# int" %} | |
| 8984 opcode(0x23); | |
| 8985 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 8986 ins_pipe(ialu_reg_mem); | |
| 8987 %} | |
| 8988 | |
| 8989 // And Memory with Register | |
| 8990 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 8991 %{ | |
| 8992 match(Set dst (StoreI dst (AndI (LoadI dst) src))); | |
| 8993 effect(KILL cr); | |
| 8994 | |
| 8995 ins_cost(150); | |
| 8996 format %{ "andl $dst, $src\t# int" %} | |
| 8997 opcode(0x21); /* Opcode 21 /r */ | |
| 8998 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 8999 ins_pipe(ialu_mem_reg); | |
| 9000 %} | |
| 9001 | |
| 9002 // And Memory with Immediate | |
| 9003 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 9004 %{ | |
| 9005 match(Set dst (StoreI dst (AndI (LoadI dst) src))); | |
| 9006 effect(KILL cr); | |
| 9007 | |
| 9008 ins_cost(125); | |
| 9009 format %{ "andl $dst, $src\t# int" %} | |
| 9010 opcode(0x81, 0x4); /* Opcode 81 /4 id */ | |
| 9011 ins_encode(REX_mem(dst), OpcSE(src), | |
| 9012 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 9013 ins_pipe(ialu_mem_imm); | |
| 9014 %} | |
| 9015 | |
| 9016 // Or Instructions | |
| 9017 // Or Register with Register | |
| 9018 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 9019 %{ | |
| 9020 match(Set dst (OrI dst src)); | |
| 9021 effect(KILL cr); | |
| 9022 | |
| 9023 format %{ "orl $dst, $src\t# int" %} | |
| 9024 opcode(0x0B); | |
| 9025 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 9026 ins_pipe(ialu_reg_reg); | |
| 9027 %} | |
| 9028 | |
| 9029 // Or Register with Immediate | |
| 9030 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 9031 %{ | |
| 9032 match(Set dst (OrI dst src)); | |
| 9033 effect(KILL cr); | |
| 9034 | |
| 9035 format %{ "orl $dst, $src\t# int" %} | |
| 9036 opcode(0x81, 0x01); /* Opcode 81 /1 id */ | |
| 9037 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 9038 ins_pipe(ialu_reg); | |
| 9039 %} | |
| 9040 | |
| 9041 // Or Register with Memory | |
| 9042 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 9043 %{ | |
| 9044 match(Set dst (OrI dst (LoadI src))); | |
| 9045 effect(KILL cr); | |
| 9046 | |
| 9047 ins_cost(125); | |
| 9048 format %{ "orl $dst, $src\t# int" %} | |
| 9049 opcode(0x0B); | |
| 9050 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 9051 ins_pipe(ialu_reg_mem); | |
| 9052 %} | |
| 9053 | |
| 9054 // Or Memory with Register | |
| 9055 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 9056 %{ | |
| 9057 match(Set dst (StoreI dst (OrI (LoadI dst) src))); | |
| 9058 effect(KILL cr); | |
| 9059 | |
| 9060 ins_cost(150); | |
| 9061 format %{ "orl $dst, $src\t# int" %} | |
| 9062 opcode(0x09); /* Opcode 09 /r */ | |
| 9063 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 9064 ins_pipe(ialu_mem_reg); | |
| 9065 %} | |
| 9066 | |
| 9067 // Or Memory with Immediate | |
| 9068 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 9069 %{ | |
| 9070 match(Set dst (StoreI dst (OrI (LoadI dst) src))); | |
| 9071 effect(KILL cr); | |
| 9072 | |
| 9073 ins_cost(125); | |
| 9074 format %{ "orl $dst, $src\t# int" %} | |
| 9075 opcode(0x81, 0x1); /* Opcode 81 /1 id */ | |
| 9076 ins_encode(REX_mem(dst), OpcSE(src), | |
| 9077 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 9078 ins_pipe(ialu_mem_imm); | |
| 9079 %} | |
| 9080 | |
| 9081 // Xor Instructions | |
| 9082 // Xor Register with Register | |
| 9083 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 9084 %{ | |
| 9085 match(Set dst (XorI dst src)); | |
| 9086 effect(KILL cr); | |
| 9087 | |
| 9088 format %{ "xorl $dst, $src\t# int" %} | |
| 9089 opcode(0x33); | |
| 9090 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 9091 ins_pipe(ialu_reg_reg); | |
| 9092 %} | |
| 9093 | |
| 403 | 9094 // Xor Register with Immediate -1 |
| 9095 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{ | |
|
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9096 match(Set dst (XorI dst imm)); |
|
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9097 |
|
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9098 format %{ "not $dst" %} |
| 403 | 9099 ins_encode %{ |
| 9100 __ notl($dst$$Register); | |
| 9101 %} | |
| 9102 ins_pipe(ialu_reg); | |
| 9103 %} | |
| 9104 | |
| 0 | 9105 // Xor Register with Immediate |
| 9106 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 9107 %{ | |
| 9108 match(Set dst (XorI dst src)); | |
| 9109 effect(KILL cr); | |
| 9110 | |
| 9111 format %{ "xorl $dst, $src\t# int" %} | |
| 9112 opcode(0x81, 0x06); /* Opcode 81 /6 id */ | |
| 9113 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 9114 ins_pipe(ialu_reg); | |
| 9115 %} | |
| 9116 | |
| 9117 // Xor Register with Memory | |
| 9118 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 9119 %{ | |
| 9120 match(Set dst (XorI dst (LoadI src))); | |
| 9121 effect(KILL cr); | |
| 9122 | |
| 9123 ins_cost(125); | |
| 9124 format %{ "xorl $dst, $src\t# int" %} | |
| 9125 opcode(0x33); | |
| 9126 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 9127 ins_pipe(ialu_reg_mem); | |
| 9128 %} | |
| 9129 | |
| 9130 // Xor Memory with Register | |
| 9131 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 9132 %{ | |
| 9133 match(Set dst (StoreI dst (XorI (LoadI dst) src))); | |
| 9134 effect(KILL cr); | |
| 9135 | |
| 9136 ins_cost(150); | |
| 9137 format %{ "xorl $dst, $src\t# int" %} | |
| 9138 opcode(0x31); /* Opcode 31 /r */ | |
| 9139 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 9140 ins_pipe(ialu_mem_reg); | |
| 9141 %} | |
| 9142 | |
| 9143 // Xor Memory with Immediate | |
| 9144 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 9145 %{ | |
| 9146 match(Set dst (StoreI dst (XorI (LoadI dst) src))); | |
| 9147 effect(KILL cr); | |
| 9148 | |
| 9149 ins_cost(125); | |
| 9150 format %{ "xorl $dst, $src\t# int" %} | |
| 9151 opcode(0x81, 0x6); /* Opcode 81 /6 id */ | |
| 9152 ins_encode(REX_mem(dst), OpcSE(src), | |
| 9153 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 9154 ins_pipe(ialu_mem_imm); | |
| 9155 %} | |
| 9156 | |
| 9157 | |
| 9158 // Long Logical Instructions | |
| 9159 | |
| 9160 // And Instructions | |
| 9161 // And Register with Register | |
| 9162 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 9163 %{ | |
| 9164 match(Set dst (AndL dst src)); | |
| 9165 effect(KILL cr); | |
| 9166 | |
| 9167 format %{ "andq $dst, $src\t# long" %} | |
| 9168 opcode(0x23); | |
| 9169 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 9170 ins_pipe(ialu_reg_reg); | |
| 9171 %} | |
| 9172 | |
| 9173 // And Register with Immediate 255 | |
| 9174 instruct andL_rReg_imm255(rRegL dst, immL_255 src) | |
| 9175 %{ | |
| 9176 match(Set dst (AndL dst src)); | |
| 9177 | |
|
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9178 format %{ "movzbq $dst, $dst\t# long & 0xFF" %} |
| 0 | 9179 opcode(0x0F, 0xB6); |
| 9180 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 9181 ins_pipe(ialu_reg); | |
| 9182 %} | |
| 9183 | |
| 9184 // And Register with Immediate 65535 | |
|
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9185 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src) |
| 0 | 9186 %{ |
| 9187 match(Set dst (AndL dst src)); | |
| 9188 | |
| 9189 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %} | |
| 9190 opcode(0x0F, 0xB7); | |
| 9191 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 9192 ins_pipe(ialu_reg); | |
| 9193 %} | |
| 9194 | |
| 9195 // And Register with Immediate | |
| 9196 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
| 9197 %{ | |
| 9198 match(Set dst (AndL dst src)); | |
| 9199 effect(KILL cr); | |
| 9200 | |
| 9201 format %{ "andq $dst, $src\t# long" %} | |
| 9202 opcode(0x81, 0x04); /* Opcode 81 /4 */ | |
| 9203 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 9204 ins_pipe(ialu_reg); | |
| 9205 %} | |
| 9206 | |
| 9207 // And Register with Memory | |
| 9208 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 9209 %{ | |
| 9210 match(Set dst (AndL dst (LoadL src))); | |
| 9211 effect(KILL cr); | |
| 9212 | |
| 9213 ins_cost(125); | |
| 9214 format %{ "andq $dst, $src\t# long" %} | |
| 9215 opcode(0x23); | |
| 9216 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 9217 ins_pipe(ialu_reg_mem); | |
| 9218 %} | |
| 9219 | |
| 9220 // And Memory with Register | |
| 9221 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 9222 %{ | |
| 9223 match(Set dst (StoreL dst (AndL (LoadL dst) src))); | |
| 9224 effect(KILL cr); | |
| 9225 | |
| 9226 ins_cost(150); | |
| 9227 format %{ "andq $dst, $src\t# long" %} | |
| 9228 opcode(0x21); /* Opcode 21 /r */ | |
| 9229 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 9230 ins_pipe(ialu_mem_reg); | |
| 9231 %} | |
| 9232 | |
| 9233 // And Memory with Immediate | |
| 9234 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 9235 %{ | |
| 9236 match(Set dst (StoreL dst (AndL (LoadL dst) src))); | |
| 9237 effect(KILL cr); | |
| 9238 | |
| 9239 ins_cost(125); | |
| 9240 format %{ "andq $dst, $src\t# long" %} | |
| 9241 opcode(0x81, 0x4); /* Opcode 81 /4 id */ | |
| 9242 ins_encode(REX_mem_wide(dst), OpcSE(src), | |
| 9243 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 9244 ins_pipe(ialu_mem_imm); | |
| 9245 %} | |
| 9246 | |
| 9247 // Or Instructions | |
| 9248 // Or Register with Register | |
| 9249 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 9250 %{ | |
| 9251 match(Set dst (OrL dst src)); | |
| 9252 effect(KILL cr); | |
| 9253 | |
| 9254 format %{ "orq $dst, $src\t# long" %} | |
| 9255 opcode(0x0B); | |
| 9256 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 9257 ins_pipe(ialu_reg_reg); | |
| 9258 %} | |
| 9259 | |
|
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|
9260 // Use any_RegP to match R15 (TLS register) without spilling. |
|
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|
9261 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{ |
|
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|
9262 match(Set dst (OrL dst (CastP2X src))); |
|
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|
9263 effect(KILL cr); |
|
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6462850: generate biased locking code in C2 ideal graph
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|
9264 |
|
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diff
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|
9265 format %{ "orq $dst, $src\t# long" %} |
|
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|
9266 opcode(0x0B); |
|
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diff
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|
9267 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); |
|
a1980da045cc
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|
9268 ins_pipe(ialu_reg_reg); |
|
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6462850: generate biased locking code in C2 ideal graph
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diff
changeset
|
9269 %} |
|
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diff
changeset
|
9270 |
|
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|
9271 |
| 0 | 9272 // Or Register with Immediate |
| 9273 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
| 9274 %{ | |
| 9275 match(Set dst (OrL dst src)); | |
| 9276 effect(KILL cr); | |
| 9277 | |
| 9278 format %{ "orq $dst, $src\t# long" %} | |
| 9279 opcode(0x81, 0x01); /* Opcode 81 /1 id */ | |
| 9280 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 9281 ins_pipe(ialu_reg); | |
| 9282 %} | |
| 9283 | |
| 9284 // Or Register with Memory | |
| 9285 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 9286 %{ | |
| 9287 match(Set dst (OrL dst (LoadL src))); | |
| 9288 effect(KILL cr); | |
| 9289 | |
| 9290 ins_cost(125); | |
| 9291 format %{ "orq $dst, $src\t# long" %} | |
| 9292 opcode(0x0B); | |
| 9293 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 9294 ins_pipe(ialu_reg_mem); | |
| 9295 %} | |
| 9296 | |
| 9297 // Or Memory with Register | |
| 9298 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 9299 %{ | |
| 9300 match(Set dst (StoreL dst (OrL (LoadL dst) src))); | |
| 9301 effect(KILL cr); | |
| 9302 | |
| 9303 ins_cost(150); | |
| 9304 format %{ "orq $dst, $src\t# long" %} | |
| 9305 opcode(0x09); /* Opcode 09 /r */ | |
| 9306 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 9307 ins_pipe(ialu_mem_reg); | |
| 9308 %} | |
| 9309 | |
| 9310 // Or Memory with Immediate | |
| 9311 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 9312 %{ | |
| 9313 match(Set dst (StoreL dst (OrL (LoadL dst) src))); | |
| 9314 effect(KILL cr); | |
| 9315 | |
| 9316 ins_cost(125); | |
| 9317 format %{ "orq $dst, $src\t# long" %} | |
| 9318 opcode(0x81, 0x1); /* Opcode 81 /1 id */ | |
| 9319 ins_encode(REX_mem_wide(dst), OpcSE(src), | |
| 9320 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 9321 ins_pipe(ialu_mem_imm); | |
| 9322 %} | |
| 9323 | |
| 9324 // Xor Instructions | |
| 9325 // Xor Register with Register | |
| 9326 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 9327 %{ | |
| 9328 match(Set dst (XorL dst src)); | |
| 9329 effect(KILL cr); | |
| 9330 | |
| 9331 format %{ "xorq $dst, $src\t# long" %} | |
| 9332 opcode(0x33); | |
| 9333 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 9334 ins_pipe(ialu_reg_reg); | |
| 9335 %} | |
| 9336 | |
| 403 | 9337 // Xor Register with Immediate -1 |
| 9338 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{ | |
|
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|
9339 match(Set dst (XorL dst imm)); |
|
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|
9340 |
|
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|
9341 format %{ "notq $dst" %} |
| 403 | 9342 ins_encode %{ |
| 9343 __ notq($dst$$Register); | |
| 9344 %} | |
| 9345 ins_pipe(ialu_reg); | |
| 9346 %} | |
| 9347 | |
| 0 | 9348 // Xor Register with Immediate |
| 9349 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
| 9350 %{ | |
| 9351 match(Set dst (XorL dst src)); | |
| 9352 effect(KILL cr); | |
| 9353 | |
| 9354 format %{ "xorq $dst, $src\t# long" %} | |
| 9355 opcode(0x81, 0x06); /* Opcode 81 /6 id */ | |
| 9356 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 9357 ins_pipe(ialu_reg); | |
| 9358 %} | |
| 9359 | |
| 9360 // Xor Register with Memory | |
| 9361 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 9362 %{ | |
| 9363 match(Set dst (XorL dst (LoadL src))); | |
| 9364 effect(KILL cr); | |
| 9365 | |
| 9366 ins_cost(125); | |
| 9367 format %{ "xorq $dst, $src\t# long" %} | |
| 9368 opcode(0x33); | |
| 9369 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 9370 ins_pipe(ialu_reg_mem); | |
| 9371 %} | |
| 9372 | |
| 9373 // Xor Memory with Register | |
| 9374 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 9375 %{ | |
| 9376 match(Set dst (StoreL dst (XorL (LoadL dst) src))); | |
| 9377 effect(KILL cr); | |
| 9378 | |
| 9379 ins_cost(150); | |
| 9380 format %{ "xorq $dst, $src\t# long" %} | |
| 9381 opcode(0x31); /* Opcode 31 /r */ | |
| 9382 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 9383 ins_pipe(ialu_mem_reg); | |
| 9384 %} | |
| 9385 | |
| 9386 // Xor Memory with Immediate | |
| 9387 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 9388 %{ | |
| 9389 match(Set dst (StoreL dst (XorL (LoadL dst) src))); | |
| 9390 effect(KILL cr); | |
| 9391 | |
| 9392 ins_cost(125); | |
| 9393 format %{ "xorq $dst, $src\t# long" %} | |
| 9394 opcode(0x81, 0x6); /* Opcode 81 /6 id */ | |
| 9395 ins_encode(REX_mem_wide(dst), OpcSE(src), | |
| 9396 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 9397 ins_pipe(ialu_mem_imm); | |
| 9398 %} | |
| 9399 | |
| 9400 // Convert Int to Boolean | |
| 9401 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr) | |
| 9402 %{ | |
| 9403 match(Set dst (Conv2B src)); | |
| 9404 effect(KILL cr); | |
| 9405 | |
| 9406 format %{ "testl $src, $src\t# ci2b\n\t" | |
| 9407 "setnz $dst\n\t" | |
| 9408 "movzbl $dst, $dst" %} | |
| 9409 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl | |
| 9410 setNZ_reg(dst), | |
| 9411 REX_reg_breg(dst, dst), // movzbl | |
| 9412 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst)); | |
| 9413 ins_pipe(pipe_slow); // XXX | |
| 9414 %} | |
| 9415 | |
| 9416 // Convert Pointer to Boolean | |
| 9417 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr) | |
| 9418 %{ | |
| 9419 match(Set dst (Conv2B src)); | |
| 9420 effect(KILL cr); | |
| 9421 | |
| 9422 format %{ "testq $src, $src\t# cp2b\n\t" | |
| 9423 "setnz $dst\n\t" | |
| 9424 "movzbl $dst, $dst" %} | |
| 9425 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq | |
| 9426 setNZ_reg(dst), | |
| 9427 REX_reg_breg(dst, dst), // movzbl | |
| 9428 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst)); | |
| 9429 ins_pipe(pipe_slow); // XXX | |
| 9430 %} | |
| 9431 | |
| 9432 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr) | |
| 9433 %{ | |
| 9434 match(Set dst (CmpLTMask p q)); | |
| 9435 effect(KILL cr); | |
| 9436 | |
| 9154 | 9437 ins_cost(400); |
| 0 | 9438 format %{ "cmpl $p, $q\t# cmpLTMask\n\t" |
| 9439 "setlt $dst\n\t" | |
| 9440 "movzbl $dst, $dst\n\t" | |
| 9441 "negl $dst" %} | |
| 9442 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl | |
| 9443 setLT_reg(dst), | |
| 9444 REX_reg_breg(dst, dst), // movzbl | |
| 9445 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst), | |
| 9446 neg_reg(dst)); | |
| 9447 ins_pipe(pipe_slow); | |
| 9448 %} | |
| 9449 | |
| 9450 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr) | |
| 9451 %{ | |
| 9452 match(Set dst (CmpLTMask dst zero)); | |
| 9453 effect(KILL cr); | |
| 9454 | |
| 9154 | 9455 ins_cost(100); |
| 0 | 9456 format %{ "sarl $dst, #31\t# cmpLTMask0" %} |
| 9154 | 9457 ins_encode %{ |
| 9458 __ sarl($dst$$Register, 31); | |
| 9459 %} | |
| 0 | 9460 ins_pipe(ialu_reg); |
| 9461 %} | |
| 9462 | |
| 9154 | 9463 /* Better to save a register than avoid a branch */ |
| 9464 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr) | |
| 0 | 9465 %{ |
| 9466 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); | |
| 9154 | 9467 effect(KILL cr); |
| 9468 ins_cost(300); | |
| 9469 format %{ "subl $p,$q\t# cadd_cmpLTMask\n\t" | |
| 9470 "jge done\n\t" | |
| 9471 "addl $p,$y\n" | |
| 9472 "done: " %} | |
|
3738
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|
9473 ins_encode %{ |
|
c7c81f18c834
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diff
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|
9474 Register Rp = $p$$Register; |
|
c7c81f18c834
7048332: Cadd_cmpLTMask doesn't handle 64-bit tmp register properly
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|
9475 Register Rq = $q$$Register; |
|
c7c81f18c834
7048332: Cadd_cmpLTMask doesn't handle 64-bit tmp register properly
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diff
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|
9476 Register Ry = $y$$Register; |
| 9154 | 9477 Label done; |
|
3738
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diff
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|
9478 __ subl(Rp, Rq); |
| 9154 | 9479 __ jccb(Assembler::greaterEqual, done); |
| 9480 __ addl(Rp, Ry); | |
| 9481 __ bind(done); | |
|
3738
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|
9482 %} |
| 0 | 9483 ins_pipe(pipe_cmplt); |
| 9484 %} | |
| 9485 | |
| 9154 | 9486 /* Better to save a register than avoid a branch */ |
| 9487 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr) | |
| 9488 %{ | |
| 9489 match(Set y (AndI (CmpLTMask p q) y)); | |
| 9490 effect(KILL cr); | |
| 9491 | |
| 9492 ins_cost(300); | |
| 9493 | |
| 9494 format %{ "cmpl $p, $q\t# and_cmpLTMask\n\t" | |
| 9495 "jlt done\n\t" | |
| 9496 "xorl $y, $y\n" | |
| 9497 "done: " %} | |
| 9498 ins_encode %{ | |
| 9499 Register Rp = $p$$Register; | |
| 9500 Register Rq = $q$$Register; | |
| 9501 Register Ry = $y$$Register; | |
| 9502 Label done; | |
| 9503 __ cmpl(Rp, Rq); | |
| 9504 __ jccb(Assembler::less, done); | |
| 9505 __ xorl(Ry, Ry); | |
| 9506 __ bind(done); | |
| 9507 %} | |
| 9508 ins_pipe(pipe_cmplt); | |
| 9509 %} | |
| 9510 | |
| 9511 | |
| 0 | 9512 //---------- FP Instructions------------------------------------------------ |
| 9513 | |
| 9514 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2) | |
| 9515 %{ | |
| 9516 match(Set cr (CmpF src1 src2)); | |
| 9517 | |
| 9518 ins_cost(145); | |
| 9519 format %{ "ucomiss $src1, $src2\n\t" | |
| 9520 "jnp,s exit\n\t" | |
| 9521 "pushfq\t# saw NaN, set CF\n\t" | |
| 9522 "andq [rsp], #0xffffff2b\n\t" | |
| 9523 "popfq\n" | |
| 4759 | 9524 "exit:" %} |
| 9525 ins_encode %{ | |
| 9526 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9527 emit_cmpfp_fixup(_masm); | |
| 9528 %} | |
| 0 | 9529 ins_pipe(pipe_slow); |
| 9530 %} | |
| 9531 | |
|
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|
9532 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{ |
|
4d9884b01ba6
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|
9533 match(Set cr (CmpF src1 src2)); |
|
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diff
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|
9534 |
| 4759 | 9535 ins_cost(100); |
|
415
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|
9536 format %{ "ucomiss $src1, $src2" %} |
|
4d9884b01ba6
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403
diff
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|
9537 ins_encode %{ |
|
4d9884b01ba6
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403
diff
changeset
|
9538 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); |
|
4d9884b01ba6
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diff
changeset
|
9539 %} |
|
4d9884b01ba6
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403
diff
changeset
|
9540 ins_pipe(pipe_slow); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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diff
changeset
|
9541 %} |
|
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diff
changeset
|
9542 |
| 0 | 9543 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2) |
| 9544 %{ | |
| 9545 match(Set cr (CmpF src1 (LoadF src2))); | |
| 9546 | |
| 9547 ins_cost(145); | |
| 9548 format %{ "ucomiss $src1, $src2\n\t" | |
| 9549 "jnp,s exit\n\t" | |
| 9550 "pushfq\t# saw NaN, set CF\n\t" | |
| 9551 "andq [rsp], #0xffffff2b\n\t" | |
| 9552 "popfq\n" | |
| 4759 | 9553 "exit:" %} |
| 9554 ins_encode %{ | |
| 9555 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 9556 emit_cmpfp_fixup(_masm); | |
| 9557 %} | |
| 0 | 9558 ins_pipe(pipe_slow); |
| 9559 %} | |
| 9560 | |
|
415
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changeset
|
9561 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{ |
|
4d9884b01ba6
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|
9562 match(Set cr (CmpF src1 (LoadF src2))); |
|
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403
diff
changeset
|
9563 |
|
4d9884b01ba6
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diff
changeset
|
9564 ins_cost(100); |
|
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diff
changeset
|
9565 format %{ "ucomiss $src1, $src2" %} |
| 4759 | 9566 ins_encode %{ |
| 9567 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 9568 %} | |
|
415
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changeset
|
9569 ins_pipe(pipe_slow); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9570 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9571 |
| 2008 | 9572 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{ |
| 9573 match(Set cr (CmpF src con)); | |
| 0 | 9574 |
| 9575 ins_cost(145); | |
| 2008 | 9576 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t" |
| 0 | 9577 "jnp,s exit\n\t" |
| 9578 "pushfq\t# saw NaN, set CF\n\t" | |
| 9579 "andq [rsp], #0xffffff2b\n\t" | |
| 9580 "popfq\n" | |
| 4759 | 9581 "exit:" %} |
| 2008 | 9582 ins_encode %{ |
| 9583 __ ucomiss($src$$XMMRegister, $constantaddress($con)); | |
| 3783 | 9584 emit_cmpfp_fixup(_masm); |
| 2008 | 9585 %} |
| 9586 ins_pipe(pipe_slow); | |
| 9587 %} | |
| 9588 | |
| 9589 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{ | |
| 9590 match(Set cr (CmpF src con)); | |
|
415
4d9884b01ba6
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never
parents:
403
diff
changeset
|
9591 ins_cost(100); |
| 2008 | 9592 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %} |
| 9593 ins_encode %{ | |
| 9594 __ ucomiss($src$$XMMRegister, $constantaddress($con)); | |
| 9595 %} | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9596 ins_pipe(pipe_slow); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9597 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9598 |
| 0 | 9599 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2) |
| 9600 %{ | |
| 9601 match(Set cr (CmpD src1 src2)); | |
| 9602 | |
| 9603 ins_cost(145); | |
| 9604 format %{ "ucomisd $src1, $src2\n\t" | |
| 9605 "jnp,s exit\n\t" | |
| 9606 "pushfq\t# saw NaN, set CF\n\t" | |
| 9607 "andq [rsp], #0xffffff2b\n\t" | |
| 9608 "popfq\n" | |
| 4759 | 9609 "exit:" %} |
| 9610 ins_encode %{ | |
| 9611 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9612 emit_cmpfp_fixup(_masm); | |
| 9613 %} | |
| 0 | 9614 ins_pipe(pipe_slow); |
| 9615 %} | |
| 9616 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9617 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9618 match(Set cr (CmpD src1 src2)); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9619 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9620 ins_cost(100); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9621 format %{ "ucomisd $src1, $src2 test" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9622 ins_encode %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9623 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9624 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9625 ins_pipe(pipe_slow); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9626 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9627 |
| 0 | 9628 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2) |
| 9629 %{ | |
| 9630 match(Set cr (CmpD src1 (LoadD src2))); | |
| 9631 | |
| 9632 ins_cost(145); | |
| 9633 format %{ "ucomisd $src1, $src2\n\t" | |
| 9634 "jnp,s exit\n\t" | |
| 9635 "pushfq\t# saw NaN, set CF\n\t" | |
| 9636 "andq [rsp], #0xffffff2b\n\t" | |
| 9637 "popfq\n" | |
| 4759 | 9638 "exit:" %} |
| 9639 ins_encode %{ | |
| 9640 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9641 emit_cmpfp_fixup(_masm); | |
| 9642 %} | |
| 0 | 9643 ins_pipe(pipe_slow); |
| 9644 %} | |
| 9645 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9646 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9647 match(Set cr (CmpD src1 (LoadD src2))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9648 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9649 ins_cost(100); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9650 format %{ "ucomisd $src1, $src2" %} |
| 4759 | 9651 ins_encode %{ |
| 9652 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9653 %} | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9654 ins_pipe(pipe_slow); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9655 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9656 |
| 2008 | 9657 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{ |
| 9658 match(Set cr (CmpD src con)); | |
| 0 | 9659 |
| 9660 ins_cost(145); | |
| 2008 | 9661 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 9662 "jnp,s exit\n\t" |
| 9663 "pushfq\t# saw NaN, set CF\n\t" | |
| 9664 "andq [rsp], #0xffffff2b\n\t" | |
| 9665 "popfq\n" | |
| 4759 | 9666 "exit:" %} |
| 2008 | 9667 ins_encode %{ |
| 9668 __ ucomisd($src$$XMMRegister, $constantaddress($con)); | |
| 3783 | 9669 emit_cmpfp_fixup(_masm); |
| 2008 | 9670 %} |
| 9671 ins_pipe(pipe_slow); | |
| 9672 %} | |
| 9673 | |
| 9674 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{ | |
| 9675 match(Set cr (CmpD src con)); | |
|
415
4d9884b01ba6
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never
parents:
403
diff
changeset
|
9676 ins_cost(100); |
| 2008 | 9677 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %} |
| 9678 ins_encode %{ | |
| 9679 __ ucomisd($src$$XMMRegister, $constantaddress($con)); | |
| 9680 %} | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9681 ins_pipe(pipe_slow); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9682 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
9683 |
| 0 | 9684 // Compare into -1,0,1 |
| 9685 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr) | |
| 9686 %{ | |
| 9687 match(Set dst (CmpF3 src1 src2)); | |
| 9688 effect(KILL cr); | |
| 9689 | |
| 9690 ins_cost(275); | |
| 9691 format %{ "ucomiss $src1, $src2\n\t" | |
| 9692 "movl $dst, #-1\n\t" | |
| 9693 "jp,s done\n\t" | |
| 9694 "jb,s done\n\t" | |
| 9695 "setne $dst\n\t" | |
| 9696 "movzbl $dst, $dst\n" | |
| 9697 "done:" %} | |
| 4759 | 9698 ins_encode %{ |
| 9699 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9700 emit_cmpfp3(_masm, $dst$$Register); | |
| 9701 %} | |
| 0 | 9702 ins_pipe(pipe_slow); |
| 9703 %} | |
| 9704 | |
| 9705 // Compare into -1,0,1 | |
| 9706 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr) | |
| 9707 %{ | |
| 9708 match(Set dst (CmpF3 src1 (LoadF src2))); | |
| 9709 effect(KILL cr); | |
| 9710 | |
| 9711 ins_cost(275); | |
| 9712 format %{ "ucomiss $src1, $src2\n\t" | |
| 9713 "movl $dst, #-1\n\t" | |
| 9714 "jp,s done\n\t" | |
| 9715 "jb,s done\n\t" | |
| 9716 "setne $dst\n\t" | |
| 9717 "movzbl $dst, $dst\n" | |
| 9718 "done:" %} | |
| 4759 | 9719 ins_encode %{ |
| 9720 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 9721 emit_cmpfp3(_masm, $dst$$Register); | |
| 9722 %} | |
| 0 | 9723 ins_pipe(pipe_slow); |
| 9724 %} | |
| 9725 | |
| 9726 // Compare into -1,0,1 | |
| 2008 | 9727 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{ |
| 9728 match(Set dst (CmpF3 src con)); | |
| 0 | 9729 effect(KILL cr); |
| 9730 | |
| 9731 ins_cost(275); | |
| 2008 | 9732 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t" |
| 0 | 9733 "movl $dst, #-1\n\t" |
| 9734 "jp,s done\n\t" | |
| 9735 "jb,s done\n\t" | |
| 9736 "setne $dst\n\t" | |
| 9737 "movzbl $dst, $dst\n" | |
| 9738 "done:" %} | |
| 2008 | 9739 ins_encode %{ |
| 9740 __ ucomiss($src$$XMMRegister, $constantaddress($con)); | |
| 4759 | 9741 emit_cmpfp3(_masm, $dst$$Register); |
| 2008 | 9742 %} |
| 0 | 9743 ins_pipe(pipe_slow); |
| 9744 %} | |
| 9745 | |
| 9746 // Compare into -1,0,1 | |
| 9747 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr) | |
| 9748 %{ | |
| 9749 match(Set dst (CmpD3 src1 src2)); | |
| 9750 effect(KILL cr); | |
| 9751 | |
| 9752 ins_cost(275); | |
| 9753 format %{ "ucomisd $src1, $src2\n\t" | |
| 9754 "movl $dst, #-1\n\t" | |
| 9755 "jp,s done\n\t" | |
| 9756 "jb,s done\n\t" | |
| 9757 "setne $dst\n\t" | |
| 9758 "movzbl $dst, $dst\n" | |
| 9759 "done:" %} | |
| 4759 | 9760 ins_encode %{ |
| 9761 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9762 emit_cmpfp3(_masm, $dst$$Register); | |
| 9763 %} | |
| 0 | 9764 ins_pipe(pipe_slow); |
| 9765 %} | |
| 9766 | |
| 9767 // Compare into -1,0,1 | |
| 9768 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr) | |
| 9769 %{ | |
| 9770 match(Set dst (CmpD3 src1 (LoadD src2))); | |
| 9771 effect(KILL cr); | |
| 9772 | |
| 9773 ins_cost(275); | |
| 9774 format %{ "ucomisd $src1, $src2\n\t" | |
| 9775 "movl $dst, #-1\n\t" | |
| 9776 "jp,s done\n\t" | |
| 9777 "jb,s done\n\t" | |
| 9778 "setne $dst\n\t" | |
| 9779 "movzbl $dst, $dst\n" | |
| 9780 "done:" %} | |
| 4759 | 9781 ins_encode %{ |
| 9782 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9783 emit_cmpfp3(_masm, $dst$$Register); | |
| 9784 %} | |
| 0 | 9785 ins_pipe(pipe_slow); |
| 9786 %} | |
| 9787 | |
| 9788 // Compare into -1,0,1 | |
| 2008 | 9789 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{ |
| 9790 match(Set dst (CmpD3 src con)); | |
| 0 | 9791 effect(KILL cr); |
| 9792 | |
| 9793 ins_cost(275); | |
| 2008 | 9794 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 9795 "movl $dst, #-1\n\t" |
| 9796 "jp,s done\n\t" | |
| 9797 "jb,s done\n\t" | |
| 9798 "setne $dst\n\t" | |
| 9799 "movzbl $dst, $dst\n" | |
| 9800 "done:" %} | |
| 2008 | 9801 ins_encode %{ |
| 9802 __ ucomisd($src$$XMMRegister, $constantaddress($con)); | |
| 4759 | 9803 emit_cmpfp3(_masm, $dst$$Register); |
| 2008 | 9804 %} |
| 0 | 9805 ins_pipe(pipe_slow); |
| 9806 %} | |
| 9807 | |
| 9808 // -----------Trig and Trancendental Instructions------------------------------ | |
| 9809 instruct cosD_reg(regD dst) %{ | |
| 9810 match(Set dst (CosD dst)); | |
| 9811 | |
| 9812 format %{ "dcos $dst\n\t" %} | |
| 9813 opcode(0xD9, 0xFF); | |
| 9814 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) ); | |
| 9815 ins_pipe( pipe_slow ); | |
| 9816 %} | |
| 9817 | |
| 9818 instruct sinD_reg(regD dst) %{ | |
| 9819 match(Set dst (SinD dst)); | |
| 9820 | |
| 9821 format %{ "dsin $dst\n\t" %} | |
| 9822 opcode(0xD9, 0xFE); | |
| 9823 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) ); | |
| 9824 ins_pipe( pipe_slow ); | |
| 9825 %} | |
| 9826 | |
| 9827 instruct tanD_reg(regD dst) %{ | |
| 9828 match(Set dst (TanD dst)); | |
| 9829 | |
| 9830 format %{ "dtan $dst\n\t" %} | |
| 9831 ins_encode( Push_SrcXD(dst), | |
| 9832 Opcode(0xD9), Opcode(0xF2), //fptan | |
| 9833 Opcode(0xDD), Opcode(0xD8), //fstp st | |
| 9834 Push_ResultXD(dst) ); | |
| 9835 ins_pipe( pipe_slow ); | |
| 9836 %} | |
| 9837 | |
| 9838 instruct log10D_reg(regD dst) %{ | |
| 9839 // The source and result Double operands in XMM registers | |
| 9840 match(Set dst (Log10D dst)); | |
| 9841 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number | |
| 9842 // fyl2x ; compute log_10(2) * log_2(x) | |
| 9843 format %{ "fldlg2\t\t\t#Log10\n\t" | |
| 9844 "fyl2x\t\t\t# Q=Log10*Log_2(x)\n\t" | |
| 9845 %} | |
| 9846 ins_encode(Opcode(0xD9), Opcode(0xEC), // fldlg2 | |
| 9847 Push_SrcXD(dst), | |
| 9848 Opcode(0xD9), Opcode(0xF1), // fyl2x | |
| 9849 Push_ResultXD(dst)); | |
| 9850 | |
| 9851 ins_pipe( pipe_slow ); | |
| 9852 %} | |
| 9853 | |
| 9854 instruct logD_reg(regD dst) %{ | |
| 9855 // The source and result Double operands in XMM registers | |
| 9856 match(Set dst (LogD dst)); | |
| 9857 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number | |
| 9858 // fyl2x ; compute log_e(2) * log_2(x) | |
| 9859 format %{ "fldln2\t\t\t#Log_e\n\t" | |
| 9860 "fyl2x\t\t\t# Q=Log_e*Log_2(x)\n\t" | |
| 9861 %} | |
| 9862 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 | |
| 9863 Push_SrcXD(dst), | |
| 9864 Opcode(0xD9), Opcode(0xF1), // fyl2x | |
| 9865 Push_ResultXD(dst)); | |
| 9866 ins_pipe( pipe_slow ); | |
| 9867 %} | |
| 9868 | |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9869 instruct powD_reg(regD dst, regD src0, regD src1, rax_RegI rax, rdx_RegI rdx, rcx_RegI rcx, rFlagsReg cr) %{ |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9870 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9871 effect(KILL rax, KILL rdx, KILL rcx, KILL cr); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9872 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9873 ins_encode %{ |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9874 __ subptr(rsp, 8); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9875 __ movdbl(Address(rsp, 0), $src1$$XMMRegister); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9876 __ fld_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9877 __ movdbl(Address(rsp, 0), $src0$$XMMRegister); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9878 __ fld_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9879 __ fast_pow(); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9880 __ fstp_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9881 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9882 __ addptr(rsp, 8); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9883 %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9884 ins_pipe( pipe_slow ); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9885 %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9886 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9887 instruct expD_reg(regD dst, regD src, rax_RegI rax, rdx_RegI rdx, rcx_RegI rcx, rFlagsReg cr) %{ |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9888 match(Set dst (ExpD src)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
9889 effect(KILL rax, KILL rcx, KILL rdx, KILL cr); |
|
6759698e3140
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9890 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %} |
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9891 ins_encode %{ |
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9892 __ subptr(rsp, 8); |
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9893 __ movdbl(Address(rsp, 0), $src$$XMMRegister); |
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9894 __ fld_d(Address(rsp, 0)); |
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9895 __ fast_exp(); |
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9896 __ fstp_d(Address(rsp, 0)); |
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9897 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); |
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9898 __ addptr(rsp, 8); |
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9899 %} |
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9900 ins_pipe( pipe_slow ); |
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9901 %} |
| 0 | 9902 |
| 9903 //----------Arithmetic Conversion Instructions--------------------------------- | |
| 9904 | |
| 9905 instruct roundFloat_nop(regF dst) | |
| 9906 %{ | |
| 9907 match(Set dst (RoundFloat dst)); | |
| 9908 | |
| 9909 ins_cost(0); | |
| 9910 ins_encode(); | |
| 9911 ins_pipe(empty); | |
| 9912 %} | |
| 9913 | |
| 9914 instruct roundDouble_nop(regD dst) | |
| 9915 %{ | |
| 9916 match(Set dst (RoundDouble dst)); | |
| 9917 | |
| 9918 ins_cost(0); | |
| 9919 ins_encode(); | |
| 9920 ins_pipe(empty); | |
| 9921 %} | |
| 9922 | |
| 9923 instruct convF2D_reg_reg(regD dst, regF src) | |
| 9924 %{ | |
| 9925 match(Set dst (ConvF2D src)); | |
| 9926 | |
| 9927 format %{ "cvtss2sd $dst, $src" %} | |
| 4759 | 9928 ins_encode %{ |
| 9929 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister); | |
| 9930 %} | |
| 0 | 9931 ins_pipe(pipe_slow); // XXX |
| 9932 %} | |
| 9933 | |
| 9934 instruct convF2D_reg_mem(regD dst, memory src) | |
| 9935 %{ | |
| 9936 match(Set dst (ConvF2D (LoadF src))); | |
| 9937 | |
| 9938 format %{ "cvtss2sd $dst, $src" %} | |
| 4759 | 9939 ins_encode %{ |
| 9940 __ cvtss2sd ($dst$$XMMRegister, $src$$Address); | |
| 9941 %} | |
| 0 | 9942 ins_pipe(pipe_slow); // XXX |
| 9943 %} | |
| 9944 | |
| 9945 instruct convD2F_reg_reg(regF dst, regD src) | |
| 9946 %{ | |
| 9947 match(Set dst (ConvD2F src)); | |
| 9948 | |
| 9949 format %{ "cvtsd2ss $dst, $src" %} | |
| 4759 | 9950 ins_encode %{ |
| 9951 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister); | |
| 9952 %} | |
| 0 | 9953 ins_pipe(pipe_slow); // XXX |
| 9954 %} | |
| 9955 | |
| 9956 instruct convD2F_reg_mem(regF dst, memory src) | |
| 9957 %{ | |
| 9958 match(Set dst (ConvD2F (LoadD src))); | |
| 9959 | |
| 9960 format %{ "cvtsd2ss $dst, $src" %} | |
| 4759 | 9961 ins_encode %{ |
| 9962 __ cvtsd2ss ($dst$$XMMRegister, $src$$Address); | |
| 9963 %} | |
| 0 | 9964 ins_pipe(pipe_slow); // XXX |
| 9965 %} | |
| 9966 | |
| 9967 // XXX do mem variants | |
| 9968 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr) | |
| 9969 %{ | |
| 9970 match(Set dst (ConvF2I src)); | |
| 9971 effect(KILL cr); | |
| 9972 | |
| 9973 format %{ "cvttss2sil $dst, $src\t# f2i\n\t" | |
| 9974 "cmpl $dst, #0x80000000\n\t" | |
| 9975 "jne,s done\n\t" | |
| 9976 "subq rsp, #8\n\t" | |
| 9977 "movss [rsp], $src\n\t" | |
| 9978 "call f2i_fixup\n\t" | |
| 9979 "popq $dst\n" | |
| 9980 "done: "%} | |
| 4759 | 9981 ins_encode %{ |
| 9982 Label done; | |
| 9983 __ cvttss2sil($dst$$Register, $src$$XMMRegister); | |
| 9984 __ cmpl($dst$$Register, 0x80000000); | |
| 9985 __ jccb(Assembler::notEqual, done); | |
| 9986 __ subptr(rsp, 8); | |
| 9987 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 9988 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup()))); | |
| 9989 __ pop($dst$$Register); | |
| 9990 __ bind(done); | |
| 9991 %} | |
| 0 | 9992 ins_pipe(pipe_slow); |
| 9993 %} | |
| 9994 | |
| 9995 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr) | |
| 9996 %{ | |
| 9997 match(Set dst (ConvF2L src)); | |
| 9998 effect(KILL cr); | |
| 9999 | |
| 10000 format %{ "cvttss2siq $dst, $src\t# f2l\n\t" | |
| 10001 "cmpq $dst, [0x8000000000000000]\n\t" | |
| 10002 "jne,s done\n\t" | |
| 10003 "subq rsp, #8\n\t" | |
| 10004 "movss [rsp], $src\n\t" | |
| 10005 "call f2l_fixup\n\t" | |
| 10006 "popq $dst\n" | |
| 10007 "done: "%} | |
| 4759 | 10008 ins_encode %{ |
| 10009 Label done; | |
| 10010 __ cvttss2siq($dst$$Register, $src$$XMMRegister); | |
| 10011 __ cmp64($dst$$Register, | |
| 10012 ExternalAddress((address) StubRoutines::x86::double_sign_flip())); | |
| 10013 __ jccb(Assembler::notEqual, done); | |
| 10014 __ subptr(rsp, 8); | |
| 10015 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 10016 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup()))); | |
| 10017 __ pop($dst$$Register); | |
| 10018 __ bind(done); | |
| 10019 %} | |
| 0 | 10020 ins_pipe(pipe_slow); |
| 10021 %} | |
| 10022 | |
| 10023 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr) | |
| 10024 %{ | |
| 10025 match(Set dst (ConvD2I src)); | |
| 10026 effect(KILL cr); | |
| 10027 | |
| 10028 format %{ "cvttsd2sil $dst, $src\t# d2i\n\t" | |
| 10029 "cmpl $dst, #0x80000000\n\t" | |
| 10030 "jne,s done\n\t" | |
| 10031 "subq rsp, #8\n\t" | |
| 10032 "movsd [rsp], $src\n\t" | |
| 10033 "call d2i_fixup\n\t" | |
| 10034 "popq $dst\n" | |
| 10035 "done: "%} | |
| 4759 | 10036 ins_encode %{ |
| 10037 Label done; | |
| 10038 __ cvttsd2sil($dst$$Register, $src$$XMMRegister); | |
| 10039 __ cmpl($dst$$Register, 0x80000000); | |
| 10040 __ jccb(Assembler::notEqual, done); | |
| 10041 __ subptr(rsp, 8); | |
| 10042 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 10043 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup()))); | |
| 10044 __ pop($dst$$Register); | |
| 10045 __ bind(done); | |
| 10046 %} | |
| 0 | 10047 ins_pipe(pipe_slow); |
| 10048 %} | |
| 10049 | |
| 10050 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr) | |
| 10051 %{ | |
| 10052 match(Set dst (ConvD2L src)); | |
| 10053 effect(KILL cr); | |
| 10054 | |
| 10055 format %{ "cvttsd2siq $dst, $src\t# d2l\n\t" | |
| 10056 "cmpq $dst, [0x8000000000000000]\n\t" | |
| 10057 "jne,s done\n\t" | |
| 10058 "subq rsp, #8\n\t" | |
| 10059 "movsd [rsp], $src\n\t" | |
| 10060 "call d2l_fixup\n\t" | |
| 10061 "popq $dst\n" | |
| 10062 "done: "%} | |
| 4759 | 10063 ins_encode %{ |
| 10064 Label done; | |
| 10065 __ cvttsd2siq($dst$$Register, $src$$XMMRegister); | |
| 10066 __ cmp64($dst$$Register, | |
| 10067 ExternalAddress((address) StubRoutines::x86::double_sign_flip())); | |
| 10068 __ jccb(Assembler::notEqual, done); | |
| 10069 __ subptr(rsp, 8); | |
| 10070 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 10071 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup()))); | |
| 10072 __ pop($dst$$Register); | |
| 10073 __ bind(done); | |
| 10074 %} | |
| 0 | 10075 ins_pipe(pipe_slow); |
| 10076 %} | |
| 10077 | |
| 10078 instruct convI2F_reg_reg(regF dst, rRegI src) | |
| 10079 %{ | |
| 71 | 10080 predicate(!UseXmmI2F); |
| 0 | 10081 match(Set dst (ConvI2F src)); |
| 10082 | |
| 10083 format %{ "cvtsi2ssl $dst, $src\t# i2f" %} | |
| 4759 | 10084 ins_encode %{ |
| 10085 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register); | |
| 10086 %} | |
| 0 | 10087 ins_pipe(pipe_slow); // XXX |
| 10088 %} | |
| 10089 | |
| 10090 instruct convI2F_reg_mem(regF dst, memory src) | |
| 10091 %{ | |
| 10092 match(Set dst (ConvI2F (LoadI src))); | |
| 10093 | |
| 10094 format %{ "cvtsi2ssl $dst, $src\t# i2f" %} | |
| 4759 | 10095 ins_encode %{ |
| 10096 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address); | |
| 10097 %} | |
| 0 | 10098 ins_pipe(pipe_slow); // XXX |
| 10099 %} | |
| 10100 | |
| 10101 instruct convI2D_reg_reg(regD dst, rRegI src) | |
| 10102 %{ | |
| 71 | 10103 predicate(!UseXmmI2D); |
| 0 | 10104 match(Set dst (ConvI2D src)); |
| 10105 | |
| 10106 format %{ "cvtsi2sdl $dst, $src\t# i2d" %} | |
| 4759 | 10107 ins_encode %{ |
| 10108 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register); | |
| 10109 %} | |
| 0 | 10110 ins_pipe(pipe_slow); // XXX |
| 10111 %} | |
| 10112 | |
| 10113 instruct convI2D_reg_mem(regD dst, memory src) | |
| 10114 %{ | |
| 10115 match(Set dst (ConvI2D (LoadI src))); | |
| 10116 | |
| 10117 format %{ "cvtsi2sdl $dst, $src\t# i2d" %} | |
| 4759 | 10118 ins_encode %{ |
| 10119 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address); | |
| 10120 %} | |
| 0 | 10121 ins_pipe(pipe_slow); // XXX |
| 10122 %} | |
| 10123 | |
| 71 | 10124 instruct convXI2F_reg(regF dst, rRegI src) |
| 10125 %{ | |
| 10126 predicate(UseXmmI2F); | |
| 10127 match(Set dst (ConvI2F src)); | |
| 10128 | |
| 10129 format %{ "movdl $dst, $src\n\t" | |
| 10130 "cvtdq2psl $dst, $dst\t# i2f" %} | |
| 10131 ins_encode %{ | |
| 10132 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 10133 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister); | |
| 10134 %} | |
| 10135 ins_pipe(pipe_slow); // XXX | |
| 10136 %} | |
| 10137 | |
| 10138 instruct convXI2D_reg(regD dst, rRegI src) | |
| 10139 %{ | |
| 10140 predicate(UseXmmI2D); | |
| 10141 match(Set dst (ConvI2D src)); | |
| 10142 | |
| 10143 format %{ "movdl $dst, $src\n\t" | |
| 10144 "cvtdq2pdl $dst, $dst\t# i2d" %} | |
| 10145 ins_encode %{ | |
| 10146 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 10147 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister); | |
| 10148 %} | |
| 10149 ins_pipe(pipe_slow); // XXX | |
| 10150 %} | |
| 10151 | |
| 0 | 10152 instruct convL2F_reg_reg(regF dst, rRegL src) |
| 10153 %{ | |
| 10154 match(Set dst (ConvL2F src)); | |
| 10155 | |
| 10156 format %{ "cvtsi2ssq $dst, $src\t# l2f" %} | |
| 4759 | 10157 ins_encode %{ |
| 10158 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register); | |
| 10159 %} | |
| 0 | 10160 ins_pipe(pipe_slow); // XXX |
| 10161 %} | |
| 10162 | |
| 10163 instruct convL2F_reg_mem(regF dst, memory src) | |
| 10164 %{ | |
| 10165 match(Set dst (ConvL2F (LoadL src))); | |
| 10166 | |
| 10167 format %{ "cvtsi2ssq $dst, $src\t# l2f" %} | |
| 4759 | 10168 ins_encode %{ |
| 10169 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address); | |
| 10170 %} | |
| 0 | 10171 ins_pipe(pipe_slow); // XXX |
| 10172 %} | |
| 10173 | |
| 10174 instruct convL2D_reg_reg(regD dst, rRegL src) | |
| 10175 %{ | |
| 10176 match(Set dst (ConvL2D src)); | |
| 10177 | |
| 10178 format %{ "cvtsi2sdq $dst, $src\t# l2d" %} | |
| 4759 | 10179 ins_encode %{ |
| 10180 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register); | |
| 10181 %} | |
| 0 | 10182 ins_pipe(pipe_slow); // XXX |
| 10183 %} | |
| 10184 | |
| 10185 instruct convL2D_reg_mem(regD dst, memory src) | |
| 10186 %{ | |
| 10187 match(Set dst (ConvL2D (LoadL src))); | |
| 10188 | |
| 10189 format %{ "cvtsi2sdq $dst, $src\t# l2d" %} | |
| 4759 | 10190 ins_encode %{ |
| 10191 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address); | |
| 10192 %} | |
| 0 | 10193 ins_pipe(pipe_slow); // XXX |
| 10194 %} | |
| 10195 | |
| 10196 instruct convI2L_reg_reg(rRegL dst, rRegI src) | |
| 10197 %{ | |
| 10198 match(Set dst (ConvI2L src)); | |
| 10199 | |
| 10200 ins_cost(125); | |
| 10201 format %{ "movslq $dst, $src\t# i2l" %} | |
| 824 | 10202 ins_encode %{ |
| 10203 __ movslq($dst$$Register, $src$$Register); | |
| 10204 %} | |
| 0 | 10205 ins_pipe(ialu_reg_reg); |
| 10206 %} | |
| 10207 | |
| 10208 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src) | |
| 10209 // %{ | |
| 10210 // match(Set dst (ConvI2L src)); | |
| 10211 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 && | |
| 10212 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0); | |
| 10213 // predicate(((const TypeNode*) n)->type()->is_long()->_hi == | |
| 10214 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi && | |
| 10215 // ((const TypeNode*) n)->type()->is_long()->_lo == | |
| 10216 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo); | |
| 10217 | |
| 10218 // format %{ "movl $dst, $src\t# unsigned i2l" %} | |
| 10219 // ins_encode(enc_copy(dst, src)); | |
| 10220 // // opcode(0x63); // needs REX.W | |
| 10221 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src)); | |
| 10222 // ins_pipe(ialu_reg_reg); | |
| 10223 // %} | |
| 10224 | |
| 10225 // Zero-extend convert int to long | |
| 10226 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask) | |
| 10227 %{ | |
| 10228 match(Set dst (AndL (ConvI2L src) mask)); | |
| 10229 | |
| 10230 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %} | |
| 4759 | 10231 ins_encode %{ |
| 10232 if ($dst$$reg != $src$$reg) { | |
| 10233 __ movl($dst$$Register, $src$$Register); | |
| 10234 } | |
| 10235 %} | |
| 0 | 10236 ins_pipe(ialu_reg_reg); |
| 10237 %} | |
| 10238 | |
| 10239 // Zero-extend convert int to long | |
| 10240 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask) | |
| 10241 %{ | |
| 10242 match(Set dst (AndL (ConvI2L (LoadI src)) mask)); | |
| 10243 | |
| 10244 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %} | |
| 4759 | 10245 ins_encode %{ |
| 10246 __ movl($dst$$Register, $src$$Address); | |
| 10247 %} | |
| 0 | 10248 ins_pipe(ialu_reg_mem); |
| 10249 %} | |
| 10250 | |
| 10251 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask) | |
| 10252 %{ | |
| 10253 match(Set dst (AndL src mask)); | |
| 10254 | |
| 10255 format %{ "movl $dst, $src\t# zero-extend long" %} | |
| 4759 | 10256 ins_encode %{ |
| 10257 __ movl($dst$$Register, $src$$Register); | |
| 10258 %} | |
| 0 | 10259 ins_pipe(ialu_reg_reg); |
| 10260 %} | |
| 10261 | |
| 10262 instruct convL2I_reg_reg(rRegI dst, rRegL src) | |
| 10263 %{ | |
| 10264 match(Set dst (ConvL2I src)); | |
| 10265 | |
| 10266 format %{ "movl $dst, $src\t# l2i" %} | |
| 4759 | 10267 ins_encode %{ |
| 10268 __ movl($dst$$Register, $src$$Register); | |
| 10269 %} | |
| 0 | 10270 ins_pipe(ialu_reg_reg); |
| 10271 %} | |
| 10272 | |
| 10273 | |
| 10274 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{ | |
| 10275 match(Set dst (MoveF2I src)); | |
| 10276 effect(DEF dst, USE src); | |
| 10277 | |
| 10278 ins_cost(125); | |
| 10279 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %} | |
| 4759 | 10280 ins_encode %{ |
| 10281 __ movl($dst$$Register, Address(rsp, $src$$disp)); | |
| 10282 %} | |
| 0 | 10283 ins_pipe(ialu_reg_mem); |
| 10284 %} | |
| 10285 | |
| 10286 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ | |
| 10287 match(Set dst (MoveI2F src)); | |
| 10288 effect(DEF dst, USE src); | |
| 10289 | |
| 10290 ins_cost(125); | |
| 10291 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %} | |
| 4759 | 10292 ins_encode %{ |
| 10293 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 10294 %} | |
| 0 | 10295 ins_pipe(pipe_slow); |
| 10296 %} | |
| 10297 | |
| 10298 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{ | |
| 10299 match(Set dst (MoveD2L src)); | |
| 10300 effect(DEF dst, USE src); | |
| 10301 | |
| 10302 ins_cost(125); | |
| 10303 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %} | |
| 4759 | 10304 ins_encode %{ |
| 10305 __ movq($dst$$Register, Address(rsp, $src$$disp)); | |
| 10306 %} | |
| 0 | 10307 ins_pipe(ialu_reg_mem); |
| 10308 %} | |
| 10309 | |
| 10310 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{ | |
| 10311 predicate(!UseXmmLoadAndClearUpper); | |
| 10312 match(Set dst (MoveL2D src)); | |
| 10313 effect(DEF dst, USE src); | |
| 10314 | |
| 10315 ins_cost(125); | |
| 10316 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %} | |
| 4759 | 10317 ins_encode %{ |
| 10318 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 10319 %} | |
| 0 | 10320 ins_pipe(pipe_slow); |
| 10321 %} | |
| 10322 | |
| 10323 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ | |
| 10324 predicate(UseXmmLoadAndClearUpper); | |
| 10325 match(Set dst (MoveL2D src)); | |
| 10326 effect(DEF dst, USE src); | |
| 10327 | |
| 10328 ins_cost(125); | |
| 10329 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %} | |
| 4759 | 10330 ins_encode %{ |
| 10331 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 10332 %} | |
| 0 | 10333 ins_pipe(pipe_slow); |
| 10334 %} | |
| 10335 | |
| 10336 | |
| 10337 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ | |
| 10338 match(Set dst (MoveF2I src)); | |
| 10339 effect(DEF dst, USE src); | |
| 10340 | |
| 10341 ins_cost(95); // XXX | |
| 10342 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %} | |
| 4759 | 10343 ins_encode %{ |
| 10344 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister); | |
| 10345 %} | |
| 0 | 10346 ins_pipe(pipe_slow); |
| 10347 %} | |
| 10348 | |
| 10349 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{ | |
| 10350 match(Set dst (MoveI2F src)); | |
| 10351 effect(DEF dst, USE src); | |
| 10352 | |
| 10353 ins_cost(100); | |
| 10354 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %} | |
| 4759 | 10355 ins_encode %{ |
| 10356 __ movl(Address(rsp, $dst$$disp), $src$$Register); | |
| 10357 %} | |
| 0 | 10358 ins_pipe( ialu_mem_reg ); |
| 10359 %} | |
| 10360 | |
| 10361 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ | |
| 10362 match(Set dst (MoveD2L src)); | |
| 10363 effect(DEF dst, USE src); | |
| 10364 | |
| 10365 ins_cost(95); // XXX | |
| 10366 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %} | |
| 4759 | 10367 ins_encode %{ |
| 10368 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister); | |
| 10369 %} | |
| 0 | 10370 ins_pipe(pipe_slow); |
| 10371 %} | |
| 10372 | |
| 10373 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{ | |
| 10374 match(Set dst (MoveL2D src)); | |
| 10375 effect(DEF dst, USE src); | |
| 10376 | |
| 10377 ins_cost(100); | |
| 10378 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %} | |
| 4759 | 10379 ins_encode %{ |
| 10380 __ movq(Address(rsp, $dst$$disp), $src$$Register); | |
| 10381 %} | |
| 0 | 10382 ins_pipe(ialu_mem_reg); |
| 10383 %} | |
| 10384 | |
| 10385 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{ | |
| 10386 match(Set dst (MoveF2I src)); | |
| 10387 effect(DEF dst, USE src); | |
| 10388 ins_cost(85); | |
| 10389 format %{ "movd $dst,$src\t# MoveF2I" %} | |
| 4759 | 10390 ins_encode %{ |
| 10391 __ movdl($dst$$Register, $src$$XMMRegister); | |
| 10392 %} | |
| 0 | 10393 ins_pipe( pipe_slow ); |
| 10394 %} | |
| 10395 | |
| 10396 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{ | |
| 10397 match(Set dst (MoveD2L src)); | |
| 10398 effect(DEF dst, USE src); | |
| 10399 ins_cost(85); | |
| 10400 format %{ "movd $dst,$src\t# MoveD2L" %} | |
| 4759 | 10401 ins_encode %{ |
| 10402 __ movdq($dst$$Register, $src$$XMMRegister); | |
| 10403 %} | |
| 0 | 10404 ins_pipe( pipe_slow ); |
| 10405 %} | |
| 10406 | |
| 10407 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{ | |
| 10408 match(Set dst (MoveI2F src)); | |
| 10409 effect(DEF dst, USE src); | |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
10410 ins_cost(100); |
| 0 | 10411 format %{ "movd $dst,$src\t# MoveI2F" %} |
| 4759 | 10412 ins_encode %{ |
| 10413 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 10414 %} | |
| 0 | 10415 ins_pipe( pipe_slow ); |
| 10416 %} | |
| 10417 | |
| 10418 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{ | |
| 10419 match(Set dst (MoveL2D src)); | |
| 10420 effect(DEF dst, USE src); | |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
10421 ins_cost(100); |
| 0 | 10422 format %{ "movd $dst,$src\t# MoveL2D" %} |
| 4759 | 10423 ins_encode %{ |
| 10424 __ movdq($dst$$XMMRegister, $src$$Register); | |
| 10425 %} | |
| 0 | 10426 ins_pipe( pipe_slow ); |
| 10427 %} | |
| 10428 | |
| 10429 | |
| 10430 // ======================================================================= | |
| 10431 // fast clearing of an array | |
| 10432 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy, | |
| 10433 rFlagsReg cr) | |
| 10434 %{ | |
|
7474
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6849
diff
changeset
|
10435 predicate(!UseFastStosb); |
| 0 | 10436 match(Set dummy (ClearArray cnt base)); |
| 10437 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr); | |
| 10438 | |
|
7474
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6849
diff
changeset
|
10439 format %{ "xorq rax, rax\t# ClearArray:\n\t" |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6849
diff
changeset
|
10440 "rep stosq\t# Store rax to *rdi++ while rcx--" %} |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6849
diff
changeset
|
10441 ins_encode %{ |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6849
diff
changeset
|
10442 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register); |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6849
diff
changeset
|
10443 %} |
| 0 | 10444 ins_pipe(pipe_slow); |
| 10445 %} | |
| 10446 | |
|
7474
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6849
diff
changeset
|
10447 instruct rep_fast_stosb(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy, |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6849
diff
changeset
|
10448 rFlagsReg cr) |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6849
diff
changeset
|
10449 %{ |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6849
diff
changeset
|
10450 predicate(UseFastStosb); |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6849
diff
changeset
|
10451 match(Set dummy (ClearArray cnt base)); |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6849
diff
changeset
|
10452 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr); |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6849
diff
changeset
|
10453 format %{ "xorq rax, rax\t# ClearArray:\n\t" |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6849
diff
changeset
|
10454 "shlq rcx,3\t# Convert doublewords to bytes\n\t" |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6849
diff
changeset
|
10455 "rep stosb\t# Store rax to *rdi++ while rcx--" %} |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6849
diff
changeset
|
10456 ins_encode %{ |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6849
diff
changeset
|
10457 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register); |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6849
diff
changeset
|
10458 %} |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6849
diff
changeset
|
10459 ins_pipe( pipe_slow ); |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6849
diff
changeset
|
10460 %} |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6849
diff
changeset
|
10461 |
| 2262 | 10462 instruct string_compare(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2, |
| 10463 rax_RegI result, regD tmp1, rFlagsReg cr) | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10464 %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10465 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); |
| 2262 | 10466 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr); |
| 10467 | |
| 10468 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %} | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10469 ins_encode %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10470 __ string_compare($str1$$Register, $str2$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10471 $cnt1$$Register, $cnt2$$Register, $result$$Register, |
| 2262 | 10472 $tmp1$$XMMRegister); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10473 %} |
| 681 | 10474 ins_pipe( pipe_slow ); |
| 10475 %} | |
| 10476 | |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10477 // fast search of substring with known size. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10478 instruct string_indexof_con(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10479 rbx_RegI result, regD vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr) |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10480 %{ |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10481 predicate(UseSSE42Intrinsics); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10482 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2))); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10483 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10484 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10485 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %} |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10486 ins_encode %{ |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10487 int icnt2 = (int)$int_cnt2$$constant; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10488 if (icnt2 >= 8) { |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10489 // IndexOf for constant substrings with size >= 8 elements |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10490 // which don't need to be loaded through stack. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10491 __ string_indexofC8($str1$$Register, $str2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10492 $cnt1$$Register, $cnt2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10493 icnt2, $result$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10494 $vec$$XMMRegister, $tmp$$Register); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10495 } else { |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10496 // Small strings are loaded through stack if they cross page boundary. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10497 __ string_indexof($str1$$Register, $str2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10498 $cnt1$$Register, $cnt2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10499 icnt2, $result$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10500 $vec$$XMMRegister, $tmp$$Register); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10501 } |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10502 %} |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10503 ins_pipe( pipe_slow ); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10504 %} |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10505 |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10506 instruct string_indexof(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2, |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10507 rbx_RegI result, regD vec, rcx_RegI tmp, rFlagsReg cr) |
| 681 | 10508 %{ |
| 10509 predicate(UseSSE42Intrinsics); | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10510 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2))); |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10511 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10512 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10513 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %} |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10514 ins_encode %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10515 __ string_indexof($str1$$Register, $str2$$Register, |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10516 $cnt1$$Register, $cnt2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10517 (-1), $result$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10518 $vec$$XMMRegister, $tmp$$Register); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10519 %} |
| 681 | 10520 ins_pipe( pipe_slow ); |
| 10521 %} | |
| 10522 | |
| 10523 // fast string equals | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10524 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10525 regD tmp1, regD tmp2, rbx_RegI tmp3, rFlagsReg cr) |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10526 %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10527 match(Set result (StrEquals (Binary str1 str2) cnt)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10528 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10529 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10530 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10531 ins_encode %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10532 __ char_arrays_equals(false, $str1$$Register, $str2$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10533 $cnt$$Register, $result$$Register, $tmp3$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10534 $tmp1$$XMMRegister, $tmp2$$XMMRegister); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10535 %} |
| 0 | 10536 ins_pipe( pipe_slow ); |
| 10537 %} | |
| 10538 | |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
168
diff
changeset
|
10539 // fast array equals |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10540 instruct array_equals(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10541 regD tmp1, regD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr) |
| 681 | 10542 %{ |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
168
diff
changeset
|
10543 match(Set result (AryEq ary1 ary2)); |
| 681 | 10544 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr); |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
168
diff
changeset
|
10545 //ins_cost(300); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
168
diff
changeset
|
10546 |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10547 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10548 ins_encode %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10549 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10550 $tmp3$$Register, $result$$Register, $tmp4$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
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824
diff
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|
10551 $tmp1$$XMMRegister, $tmp2$$XMMRegister); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
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824
diff
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|
10552 %} |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
168
diff
changeset
|
10553 ins_pipe( pipe_slow ); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
168
diff
changeset
|
10554 %} |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
168
diff
changeset
|
10555 |
|
7637
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10556 // encode char[] to byte[] in ISO_8859_1 |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10557 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len, |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10558 regD tmp1, regD tmp2, regD tmp3, regD tmp4, |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10559 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{ |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10560 match(Set result (EncodeISOArray src (Binary dst len))); |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10561 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr); |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10562 |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10563 format %{ "Encode array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %} |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10564 ins_encode %{ |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10565 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register, |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10566 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister, |
|
b30b3c2a0cf2
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kvn
parents:
7474
diff
changeset
|
10567 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register); |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10568 %} |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10569 ins_pipe( pipe_slow ); |
|
b30b3c2a0cf2
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kvn
parents:
7474
diff
changeset
|
10570 %} |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10571 |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
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diff
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|
10572 |
| 0 | 10573 //----------Control Flow Instructions------------------------------------------ |
| 10574 // Signed compare Instructions | |
| 10575 | |
| 10576 // XXX more variants!! | |
| 10577 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2) | |
| 10578 %{ | |
| 10579 match(Set cr (CmpI op1 op2)); | |
| 10580 effect(DEF cr, USE op1, USE op2); | |
| 10581 | |
| 10582 format %{ "cmpl $op1, $op2" %} | |
| 10583 opcode(0x3B); /* Opcode 3B /r */ | |
| 10584 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2)); | |
| 10585 ins_pipe(ialu_cr_reg_reg); | |
| 10586 %} | |
| 10587 | |
| 10588 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2) | |
| 10589 %{ | |
| 10590 match(Set cr (CmpI op1 op2)); | |
| 10591 | |
| 10592 format %{ "cmpl $op1, $op2" %} | |
| 10593 opcode(0x81, 0x07); /* Opcode 81 /7 */ | |
| 10594 ins_encode(OpcSErm(op1, op2), Con8or32(op2)); | |
| 10595 ins_pipe(ialu_cr_reg_imm); | |
| 10596 %} | |
| 10597 | |
| 10598 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2) | |
| 10599 %{ | |
| 10600 match(Set cr (CmpI op1 (LoadI op2))); | |
| 10601 | |
| 10602 ins_cost(500); // XXX | |
| 10603 format %{ "cmpl $op1, $op2" %} | |
| 10604 opcode(0x3B); /* Opcode 3B /r */ | |
| 10605 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 10606 ins_pipe(ialu_cr_reg_mem); | |
| 10607 %} | |
| 10608 | |
| 10609 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero) | |
| 10610 %{ | |
| 10611 match(Set cr (CmpI src zero)); | |
| 10612 | |
| 10613 format %{ "testl $src, $src" %} | |
| 10614 opcode(0x85); | |
| 10615 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src)); | |
| 10616 ins_pipe(ialu_cr_reg_imm); | |
| 10617 %} | |
| 10618 | |
| 10619 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero) | |
| 10620 %{ | |
| 10621 match(Set cr (CmpI (AndI src con) zero)); | |
| 10622 | |
| 10623 format %{ "testl $src, $con" %} | |
| 10624 opcode(0xF7, 0x00); | |
| 10625 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con)); | |
| 10626 ins_pipe(ialu_cr_reg_imm); | |
| 10627 %} | |
| 10628 | |
| 10629 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero) | |
| 10630 %{ | |
| 10631 match(Set cr (CmpI (AndI src (LoadI mem)) zero)); | |
| 10632 | |
| 10633 format %{ "testl $src, $mem" %} | |
| 10634 opcode(0x85); | |
| 10635 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
| 10636 ins_pipe(ialu_cr_reg_mem); | |
| 10637 %} | |
| 10638 | |
| 10639 // Unsigned compare Instructions; really, same as signed except they | |
| 10640 // produce an rFlagsRegU instead of rFlagsReg. | |
| 10641 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2) | |
| 10642 %{ | |
| 10643 match(Set cr (CmpU op1 op2)); | |
| 10644 | |
| 10645 format %{ "cmpl $op1, $op2\t# unsigned" %} | |
| 10646 opcode(0x3B); /* Opcode 3B /r */ | |
| 10647 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2)); | |
| 10648 ins_pipe(ialu_cr_reg_reg); | |
| 10649 %} | |
| 10650 | |
| 10651 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2) | |
| 10652 %{ | |
| 10653 match(Set cr (CmpU op1 op2)); | |
| 10654 | |
| 10655 format %{ "cmpl $op1, $op2\t# unsigned" %} | |
| 10656 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 10657 ins_encode(OpcSErm(op1, op2), Con8or32(op2)); | |
| 10658 ins_pipe(ialu_cr_reg_imm); | |
| 10659 %} | |
| 10660 | |
| 10661 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2) | |
| 10662 %{ | |
| 10663 match(Set cr (CmpU op1 (LoadI op2))); | |
| 10664 | |
| 10665 ins_cost(500); // XXX | |
| 10666 format %{ "cmpl $op1, $op2\t# unsigned" %} | |
| 10667 opcode(0x3B); /* Opcode 3B /r */ | |
| 10668 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 10669 ins_pipe(ialu_cr_reg_mem); | |
| 10670 %} | |
| 10671 | |
| 10672 // // // Cisc-spilled version of cmpU_rReg | |
| 10673 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2) | |
| 10674 // //%{ | |
| 10675 // // match(Set cr (CmpU (LoadI op1) op2)); | |
| 10676 // // | |
| 10677 // // format %{ "CMPu $op1,$op2" %} | |
| 10678 // // ins_cost(500); | |
| 10679 // // opcode(0x39); /* Opcode 39 /r */ | |
| 10680 // // ins_encode( OpcP, reg_mem( op1, op2) ); | |
| 10681 // //%} | |
| 10682 | |
| 10683 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero) | |
| 10684 %{ | |
| 10685 match(Set cr (CmpU src zero)); | |
| 10686 | |
| 10687 format %{ "testl $src, $src\t# unsigned" %} | |
| 10688 opcode(0x85); | |
| 10689 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src)); | |
| 10690 ins_pipe(ialu_cr_reg_imm); | |
| 10691 %} | |
| 10692 | |
| 10693 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2) | |
| 10694 %{ | |
| 10695 match(Set cr (CmpP op1 op2)); | |
| 10696 | |
| 10697 format %{ "cmpq $op1, $op2\t# ptr" %} | |
| 10698 opcode(0x3B); /* Opcode 3B /r */ | |
| 10699 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2)); | |
| 10700 ins_pipe(ialu_cr_reg_reg); | |
| 10701 %} | |
| 10702 | |
| 10703 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2) | |
| 10704 %{ | |
| 10705 match(Set cr (CmpP op1 (LoadP op2))); | |
| 10706 | |
| 10707 ins_cost(500); // XXX | |
| 10708 format %{ "cmpq $op1, $op2\t# ptr" %} | |
| 10709 opcode(0x3B); /* Opcode 3B /r */ | |
| 10710 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 10711 ins_pipe(ialu_cr_reg_mem); | |
| 10712 %} | |
| 10713 | |
| 10714 // // // Cisc-spilled version of cmpP_rReg | |
| 10715 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2) | |
| 10716 // //%{ | |
| 10717 // // match(Set cr (CmpP (LoadP op1) op2)); | |
| 10718 // // | |
| 10719 // // format %{ "CMPu $op1,$op2" %} | |
| 10720 // // ins_cost(500); | |
| 10721 // // opcode(0x39); /* Opcode 39 /r */ | |
| 10722 // // ins_encode( OpcP, reg_mem( op1, op2) ); | |
| 10723 // //%} | |
| 10724 | |
| 10725 // XXX this is generalized by compP_rReg_mem??? | |
| 10726 // Compare raw pointer (used in out-of-heap check). | |
| 10727 // Only works because non-oop pointers must be raw pointers | |
| 10728 // and raw pointers have no anti-dependencies. | |
| 10729 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2) | |
| 10730 %{ | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
10731 predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none); |
| 0 | 10732 match(Set cr (CmpP op1 (LoadP op2))); |
| 10733 | |
| 10734 format %{ "cmpq $op1, $op2\t# raw ptr" %} | |
| 10735 opcode(0x3B); /* Opcode 3B /r */ | |
| 10736 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 10737 ins_pipe(ialu_cr_reg_mem); | |
| 10738 %} | |
| 10739 | |
| 10740 // This will generate a signed flags result. This should be OK since | |
| 10741 // any compare to a zero should be eq/neq. | |
| 10742 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero) | |
| 10743 %{ | |
| 10744 match(Set cr (CmpP src zero)); | |
| 10745 | |
| 10746 format %{ "testq $src, $src\t# ptr" %} | |
| 10747 opcode(0x85); | |
| 10748 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src)); | |
| 10749 ins_pipe(ialu_cr_reg_imm); | |
| 10750 %} | |
| 10751 | |
| 10752 // This will generate a signed flags result. This should be OK since | |
| 10753 // any compare to a zero should be eq/neq. | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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624
diff
changeset
|
10754 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
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|
10755 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10756 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL)); |
| 0 | 10757 match(Set cr (CmpP (LoadP op) zero)); |
| 10758 | |
| 10759 ins_cost(500); // XXX | |
| 10760 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %} | |
| 10761 opcode(0xF7); /* Opcode F7 /0 */ | |
| 10762 ins_encode(REX_mem_wide(op), | |
| 10763 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF)); | |
| 10764 ins_pipe(ialu_cr_reg_imm); | |
| 10765 %} | |
| 10766 | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10767 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10768 %{ |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
10769 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL)); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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624
diff
changeset
|
10770 match(Set cr (CmpP (LoadP mem) zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10771 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
10772 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
10773 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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624
diff
changeset
|
10774 __ cmpq(r12, $mem$$Address); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
10775 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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624
diff
changeset
|
10776 ins_pipe(ialu_cr_reg_mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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624
diff
changeset
|
10777 %} |
|
164
c436414a719e
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163
diff
changeset
|
10778 |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
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163
diff
changeset
|
10779 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2) |
|
c436414a719e
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|
10780 %{ |
|
c436414a719e
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163
diff
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|
10781 match(Set cr (CmpN op1 op2)); |
|
c436414a719e
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diff
changeset
|
10782 |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
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163
diff
changeset
|
10783 format %{ "cmpl $op1, $op2\t# compressed ptr" %} |
|
642
660978a2a31a
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624
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changeset
|
10784 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %} |
|
164
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changeset
|
10785 ins_pipe(ialu_cr_reg_reg); |
|
c436414a719e
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|
10786 %} |
|
c436414a719e
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diff
changeset
|
10787 |
|
c436414a719e
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163
diff
changeset
|
10788 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem) |
|
c436414a719e
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|
10789 %{ |
|
c436414a719e
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163
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|
10790 match(Set cr (CmpN src (LoadN mem))); |
|
c436414a719e
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diff
changeset
|
10791 |
|
642
660978a2a31a
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diff
changeset
|
10792 format %{ "cmpl $src, $mem\t# compressed ptr" %} |
|
660978a2a31a
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kvn
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diff
changeset
|
10793 ins_encode %{ |
|
660978a2a31a
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diff
changeset
|
10794 __ cmpl($src$$Register, $mem$$Address); |
|
660978a2a31a
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kvn
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diff
changeset
|
10795 %} |
|
660978a2a31a
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diff
changeset
|
10796 ins_pipe(ialu_cr_reg_mem); |
|
660978a2a31a
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diff
changeset
|
10797 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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diff
changeset
|
10798 |
|
660978a2a31a
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kvn
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diff
changeset
|
10799 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{ |
|
660978a2a31a
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changeset
|
10800 match(Set cr (CmpN op1 op2)); |
|
660978a2a31a
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diff
changeset
|
10801 |
|
660978a2a31a
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diff
changeset
|
10802 format %{ "cmpl $op1, $op2\t# compressed ptr" %} |
|
164
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10803 ins_encode %{ |
|
642
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|
10804 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant); |
|
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|
10805 %} |
|
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|
10806 ins_pipe(ialu_cr_reg_imm); |
|
660978a2a31a
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624
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|
10807 %} |
|
660978a2a31a
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diff
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|
10808 |
|
660978a2a31a
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624
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|
10809 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src) |
|
660978a2a31a
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|
10810 %{ |
|
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|
10811 match(Set cr (CmpN src (LoadN mem))); |
|
660978a2a31a
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|
10812 |
|
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|
10813 format %{ "cmpl $mem, $src\t# compressed ptr" %} |
|
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|
10814 ins_encode %{ |
|
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|
10815 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant); |
|
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10816 %} |
|
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|
10817 ins_pipe(ialu_cr_reg_mem); |
|
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|
10818 %} |
|
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|
10819 |
|
6848
8e47bac5643a
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diff
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|
10820 instruct compN_rReg_imm_klass(rFlagsRegU cr, rRegN op1, immNKlass op2) %{ |
|
8e47bac5643a
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diff
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|
10821 match(Set cr (CmpN op1 op2)); |
|
8e47bac5643a
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roland
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diff
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|
10822 |
|
8e47bac5643a
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diff
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|
10823 format %{ "cmpl $op1, $op2\t# compressed klass ptr" %} |
|
8e47bac5643a
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roland
parents:
6795
diff
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|
10824 ins_encode %{ |
|
8e47bac5643a
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6795
diff
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|
10825 __ cmp_narrow_klass($op1$$Register, (Klass*)$op2$$constant); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
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6795
diff
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|
10826 %} |
|
8e47bac5643a
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6795
diff
changeset
|
10827 ins_pipe(ialu_cr_reg_imm); |
|
8e47bac5643a
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roland
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6795
diff
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|
10828 %} |
|
8e47bac5643a
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roland
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6795
diff
changeset
|
10829 |
|
8e47bac5643a
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6795
diff
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|
10830 instruct compN_mem_imm_klass(rFlagsRegU cr, memory mem, immNKlass src) |
|
8e47bac5643a
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roland
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6795
diff
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|
10831 %{ |
|
8e47bac5643a
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diff
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|
10832 match(Set cr (CmpN src (LoadNKlass mem))); |
|
8e47bac5643a
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6795
diff
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|
10833 |
|
8e47bac5643a
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diff
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|
10834 format %{ "cmpl $mem, $src\t# compressed klass ptr" %} |
|
8e47bac5643a
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roland
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6795
diff
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|
10835 ins_encode %{ |
|
8e47bac5643a
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6795
diff
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|
10836 __ cmp_narrow_klass($mem$$Address, (Klass*)$src$$constant); |
|
8e47bac5643a
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roland
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6795
diff
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|
10837 %} |
|
8e47bac5643a
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diff
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|
10838 ins_pipe(ialu_cr_reg_mem); |
|
8e47bac5643a
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roland
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6795
diff
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|
10839 %} |
|
8e47bac5643a
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diff
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|
10840 |
|
113
ba764ed4b6f2
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71
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|
10841 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{ |
|
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|
10842 match(Set cr (CmpN src zero)); |
|
ba764ed4b6f2
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|
10843 |
|
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|
10844 format %{ "testl $src, $src\t# compressed ptr" %} |
|
113
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|
10845 ins_encode %{ __ testl($src$$Register, $src$$Register); %} |
|
ba764ed4b6f2
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|
10846 ins_pipe(ialu_cr_reg_imm); |
|
ba764ed4b6f2
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71
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|
10847 %} |
|
ba764ed4b6f2
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|
10848 |
|
642
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624
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|
10849 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero) |
|
660978a2a31a
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|
10850 %{ |
|
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|
10851 predicate(Universe::narrow_oop_base() != NULL); |
|
164
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|
10852 match(Set cr (CmpN (LoadN mem) zero)); |
|
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|
10853 |
|
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|
10854 ins_cost(500); // XXX |
|
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|
10855 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %} |
|
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|
10856 ins_encode %{ |
|
642
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|
10857 __ cmpl($mem$$Address, (int)0xFFFFFFFF); |
|
660978a2a31a
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|
10858 %} |
|
660978a2a31a
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|
10859 ins_pipe(ialu_cr_reg_mem); |
|
660978a2a31a
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624
diff
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|
10860 %} |
|
660978a2a31a
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624
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|
10861 |
|
660978a2a31a
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624
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changeset
|
10862 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero) |
|
660978a2a31a
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|
10863 %{ |
|
6848
8e47bac5643a
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roland
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diff
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|
10864 predicate(Universe::narrow_oop_base() == NULL && (Universe::narrow_klass_base() == NULL)); |
|
642
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|
10865 match(Set cr (CmpN (LoadN mem) zero)); |
|
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624
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|
10866 |
|
660978a2a31a
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|
10867 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %} |
|
660978a2a31a
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kvn
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|
10868 ins_encode %{ |
|
660978a2a31a
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diff
changeset
|
10869 __ cmpl(r12, $mem$$Address); |
|
164
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|
10870 %} |
|
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163
diff
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|
10871 ins_pipe(ialu_cr_reg_mem); |
|
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|
10872 %} |
|
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|
10873 |
| 0 | 10874 // Yanked all unsigned pointer compare operations. |
| 10875 // Pointer compares are done with CmpP which is already unsigned. | |
| 10876 | |
| 10877 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2) | |
| 10878 %{ | |
| 10879 match(Set cr (CmpL op1 op2)); | |
| 10880 | |
| 10881 format %{ "cmpq $op1, $op2" %} | |
| 10882 opcode(0x3B); /* Opcode 3B /r */ | |
| 10883 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2)); | |
| 10884 ins_pipe(ialu_cr_reg_reg); | |
| 10885 %} | |
| 10886 | |
| 10887 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2) | |
| 10888 %{ | |
| 10889 match(Set cr (CmpL op1 op2)); | |
| 10890 | |
| 10891 format %{ "cmpq $op1, $op2" %} | |
| 10892 opcode(0x81, 0x07); /* Opcode 81 /7 */ | |
| 10893 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2)); | |
| 10894 ins_pipe(ialu_cr_reg_imm); | |
| 10895 %} | |
| 10896 | |
| 10897 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2) | |
| 10898 %{ | |
| 10899 match(Set cr (CmpL op1 (LoadL op2))); | |
| 10900 | |
| 10901 format %{ "cmpq $op1, $op2" %} | |
| 10902 opcode(0x3B); /* Opcode 3B /r */ | |
| 10903 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 10904 ins_pipe(ialu_cr_reg_mem); | |
| 10905 %} | |
| 10906 | |
| 10907 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero) | |
| 10908 %{ | |
| 10909 match(Set cr (CmpL src zero)); | |
| 10910 | |
| 10911 format %{ "testq $src, $src" %} | |
| 10912 opcode(0x85); | |
| 10913 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src)); | |
| 10914 ins_pipe(ialu_cr_reg_imm); | |
| 10915 %} | |
| 10916 | |
| 10917 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero) | |
| 10918 %{ | |
| 10919 match(Set cr (CmpL (AndL src con) zero)); | |
| 10920 | |
| 10921 format %{ "testq $src, $con\t# long" %} | |
| 10922 opcode(0xF7, 0x00); | |
| 10923 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con)); | |
| 10924 ins_pipe(ialu_cr_reg_imm); | |
| 10925 %} | |
| 10926 | |
| 10927 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero) | |
| 10928 %{ | |
| 10929 match(Set cr (CmpL (AndL src (LoadL mem)) zero)); | |
| 10930 | |
| 10931 format %{ "testq $src, $mem" %} | |
| 10932 opcode(0x85); | |
| 10933 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem)); | |
| 10934 ins_pipe(ialu_cr_reg_mem); | |
| 10935 %} | |
| 10936 | |
| 10937 // Manifest a CmpL result in an integer register. Very painful. | |
| 10938 // This is the test to avoid. | |
| 10939 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags) | |
| 10940 %{ | |
| 10941 match(Set dst (CmpL3 src1 src2)); | |
| 10942 effect(KILL flags); | |
| 10943 | |
| 10944 ins_cost(275); // XXX | |
| 10945 format %{ "cmpq $src1, $src2\t# CmpL3\n\t" | |
| 10946 "movl $dst, -1\n\t" | |
| 10947 "jl,s done\n\t" | |
| 10948 "setne $dst\n\t" | |
| 10949 "movzbl $dst, $dst\n\t" | |
| 10950 "done:" %} | |
| 10951 ins_encode(cmpl3_flag(src1, src2, dst)); | |
| 10952 ins_pipe(pipe_slow); | |
| 10953 %} | |
| 10954 | |
| 10955 //----------Max and Min-------------------------------------------------------- | |
| 10956 // Min Instructions | |
| 10957 | |
| 10958 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr) | |
| 10959 %{ | |
| 10960 effect(USE_DEF dst, USE src, USE cr); | |
| 10961 | |
| 10962 format %{ "cmovlgt $dst, $src\t# min" %} | |
| 10963 opcode(0x0F, 0x4F); | |
| 10964 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 10965 ins_pipe(pipe_cmov_reg); | |
| 10966 %} | |
| 10967 | |
| 10968 | |
| 10969 instruct minI_rReg(rRegI dst, rRegI src) | |
| 10970 %{ | |
| 10971 match(Set dst (MinI dst src)); | |
| 10972 | |
| 10973 ins_cost(200); | |
| 10974 expand %{ | |
| 10975 rFlagsReg cr; | |
| 10976 compI_rReg(cr, dst, src); | |
| 10977 cmovI_reg_g(dst, src, cr); | |
| 10978 %} | |
| 10979 %} | |
| 10980 | |
| 10981 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr) | |
| 10982 %{ | |
| 10983 effect(USE_DEF dst, USE src, USE cr); | |
| 10984 | |
| 10985 format %{ "cmovllt $dst, $src\t# max" %} | |
| 10986 opcode(0x0F, 0x4C); | |
| 10987 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 10988 ins_pipe(pipe_cmov_reg); | |
| 10989 %} | |
| 10990 | |
| 10991 | |
| 10992 instruct maxI_rReg(rRegI dst, rRegI src) | |
| 10993 %{ | |
| 10994 match(Set dst (MaxI dst src)); | |
| 10995 | |
| 10996 ins_cost(200); | |
| 10997 expand %{ | |
| 10998 rFlagsReg cr; | |
| 10999 compI_rReg(cr, dst, src); | |
| 11000 cmovI_reg_l(dst, src, cr); | |
| 11001 %} | |
| 11002 %} | |
| 11003 | |
| 11004 // ============================================================================ | |
| 11005 // Branch Instructions | |
| 11006 | |
| 11007 // Jump Direct - Label defines a relative address from JMP+1 | |
| 11008 instruct jmpDir(label labl) | |
| 11009 %{ | |
| 11010 match(Goto); | |
| 11011 effect(USE labl); | |
| 11012 | |
| 11013 ins_cost(300); | |
| 11014 format %{ "jmp $labl" %} | |
| 11015 size(5); | |
| 3851 | 11016 ins_encode %{ |
| 11017 Label* L = $labl$$label; | |
| 11018 __ jmp(*L, false); // Always long jump | |
| 11019 %} | |
| 0 | 11020 ins_pipe(pipe_jmp); |
| 11021 %} | |
| 11022 | |
| 11023 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 11024 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl) | |
| 11025 %{ | |
| 11026 match(If cop cr); | |
| 11027 effect(USE labl); | |
| 11028 | |
| 11029 ins_cost(300); | |
| 11030 format %{ "j$cop $labl" %} | |
| 11031 size(6); | |
| 3851 | 11032 ins_encode %{ |
| 11033 Label* L = $labl$$label; | |
| 11034 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 11035 %} | |
| 0 | 11036 ins_pipe(pipe_jcc); |
| 11037 %} | |
| 11038 | |
| 11039 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 11040 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl) | |
| 11041 %{ | |
| 11042 match(CountedLoopEnd cop cr); | |
| 11043 effect(USE labl); | |
| 11044 | |
| 11045 ins_cost(300); | |
| 11046 format %{ "j$cop $labl\t# loop end" %} | |
| 11047 size(6); | |
| 3851 | 11048 ins_encode %{ |
| 11049 Label* L = $labl$$label; | |
| 11050 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 11051 %} | |
| 0 | 11052 ins_pipe(pipe_jcc); |
| 11053 %} | |
| 11054 | |
| 11055 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
|
415
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|
11056 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
| 0 | 11057 match(CountedLoopEnd cop cmp); |
| 11058 effect(USE labl); | |
| 11059 | |
| 11060 ins_cost(300); | |
| 11061 format %{ "j$cop,u $labl\t# loop end" %} | |
| 11062 size(6); | |
| 3851 | 11063 ins_encode %{ |
| 11064 Label* L = $labl$$label; | |
| 11065 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 11066 %} | |
| 0 | 11067 ins_pipe(pipe_jcc); |
| 11068 %} | |
| 11069 | |
|
415
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parents:
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diff
changeset
|
11070 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
|
4d9884b01ba6
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|
11071 match(CountedLoopEnd cop cmp); |
|
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11072 effect(USE labl); |
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|
11073 |
|
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|
11074 ins_cost(200); |
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11075 format %{ "j$cop,u $labl\t# loop end" %} |
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11076 size(6); |
| 3851 | 11077 ins_encode %{ |
| 11078 Label* L = $labl$$label; | |
| 11079 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 11080 %} | |
|
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|
11081 ins_pipe(pipe_jcc); |
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|
11082 %} |
|
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|
11083 |
| 0 | 11084 // Jump Direct Conditional - using unsigned comparison |
|
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11085 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
| 0 | 11086 match(If cop cmp); |
| 11087 effect(USE labl); | |
| 11088 | |
| 11089 ins_cost(300); | |
|
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11090 format %{ "j$cop,u $labl" %} |
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11091 size(6); |
| 3851 | 11092 ins_encode %{ |
| 11093 Label* L = $labl$$label; | |
| 11094 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 11095 %} | |
|
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|
11096 ins_pipe(pipe_jcc); |
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11097 %} |
|
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11098 |
|
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11099 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
|
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11100 match(If cop cmp); |
|
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11101 effect(USE labl); |
|
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11102 |
|
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|
11103 ins_cost(200); |
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11104 format %{ "j$cop,u $labl" %} |
| 0 | 11105 size(6); |
| 3851 | 11106 ins_encode %{ |
| 11107 Label* L = $labl$$label; | |
| 11108 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 11109 %} | |
| 0 | 11110 ins_pipe(pipe_jcc); |
| 11111 %} | |
| 11112 | |
|
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11113 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{ |
|
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11114 match(If cop cmp); |
|
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11115 effect(USE labl); |
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11116 |
|
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|
11117 ins_cost(200); |
|
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|
11118 format %{ $$template |
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11119 if ($cop$$cmpcode == Assembler::notEqual) { |
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11120 $$emit$$"jp,u $labl\n\t" |
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11121 $$emit$$"j$cop,u $labl" |
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11122 } else { |
|
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11123 $$emit$$"jp,u done\n\t" |
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11124 $$emit$$"j$cop,u $labl\n\t" |
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11125 $$emit$$"done:" |
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|
11126 } |
|
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|
11127 %} |
|
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|
11128 ins_encode %{ |
|
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|
11129 Label* l = $labl$$label; |
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11130 if ($cop$$cmpcode == Assembler::notEqual) { |
| 3851 | 11131 __ jcc(Assembler::parity, *l, false); |
| 11132 __ jcc(Assembler::notEqual, *l, false); | |
|
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11133 } else if ($cop$$cmpcode == Assembler::equal) { |
| 3851 | 11134 Label done; |
| 11135 __ jccb(Assembler::parity, done); | |
| 11136 __ jcc(Assembler::equal, *l, false); | |
| 11137 __ bind(done); | |
|
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11138 } else { |
|
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|
11139 ShouldNotReachHere(); |
|
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|
11140 } |
|
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|
11141 %} |
|
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|
11142 ins_pipe(pipe_jcc); |
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11143 %} |
|
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|
11144 |
| 0 | 11145 // ============================================================================ |
| 11146 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary | |
| 11147 // superklass array for an instance of the superklass. Set a hidden | |
| 11148 // internal cache on a hit (cache is checked with exposed code in | |
| 11149 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The | |
| 11150 // encoding ALSO sets flags. | |
| 11151 | |
| 11152 instruct partialSubtypeCheck(rdi_RegP result, | |
| 11153 rsi_RegP sub, rax_RegP super, rcx_RegI rcx, | |
| 11154 rFlagsReg cr) | |
| 11155 %{ | |
| 11156 match(Set result (PartialSubtypeCheck sub super)); | |
| 11157 effect(KILL rcx, KILL cr); | |
| 11158 | |
| 11159 ins_cost(1100); // slightly larger than the next version | |
|
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|
11160 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t" |
|
6725
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11161 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t" |
|
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11162 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t" |
| 0 | 11163 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t" |
| 11164 "jne,s miss\t\t# Missed: rdi not-zero\n\t" | |
|
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11165 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t" |
| 0 | 11166 "xorq $result, $result\t\t Hit: rdi zero\n\t" |
| 11167 "miss:\t" %} | |
| 11168 | |
| 11169 opcode(0x1); // Force a XOR of RDI | |
| 11170 ins_encode(enc_PartialSubtypeCheck()); | |
| 11171 ins_pipe(pipe_slow); | |
| 11172 %} | |
| 11173 | |
| 11174 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr, | |
| 11175 rsi_RegP sub, rax_RegP super, rcx_RegI rcx, | |
| 11176 immP0 zero, | |
| 11177 rdi_RegP result) | |
| 11178 %{ | |
| 11179 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero)); | |
| 11180 effect(KILL rcx, KILL result); | |
| 11181 | |
| 11182 ins_cost(1000); | |
|
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|
11183 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t" |
|
6725
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11184 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t" |
|
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11185 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t" |
| 0 | 11186 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t" |
| 11187 "jne,s miss\t\t# Missed: flags nz\n\t" | |
|
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|
11188 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t" |
| 0 | 11189 "miss:\t" %} |
| 11190 | |
| 11191 opcode(0x0); // No need to XOR RDI | |
| 11192 ins_encode(enc_PartialSubtypeCheck()); | |
| 11193 ins_pipe(pipe_slow); | |
| 11194 %} | |
| 11195 | |
| 11196 // ============================================================================ | |
| 11197 // Branch Instructions -- short offset versions | |
| 11198 // | |
| 11199 // These instructions are used to replace jumps of a long offset (the default | |
| 11200 // match) with jumps of a shorter offset. These instructions are all tagged | |
| 11201 // with the ins_short_branch attribute, which causes the ADLC to suppress the | |
| 11202 // match rules in general matching. Instead, the ADLC generates a conversion | |
| 11203 // method in the MachNode which can be used to do in-place replacement of the | |
| 11204 // long variant with the shorter variant. The compiler will determine if a | |
| 11205 // branch can be taken by the is_short_branch_offset() predicate in the machine | |
| 11206 // specific code section of the file. | |
| 11207 | |
| 11208 // Jump Direct - Label defines a relative address from JMP+1 | |
|
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|
11209 instruct jmpDir_short(label labl) %{ |
| 0 | 11210 match(Goto); |
| 11211 effect(USE labl); | |
| 11212 | |
| 11213 ins_cost(300); | |
| 11214 format %{ "jmp,s $labl" %} | |
| 11215 size(2); | |
| 3851 | 11216 ins_encode %{ |
| 11217 Label* L = $labl$$label; | |
| 11218 __ jmpb(*L); | |
| 11219 %} | |
| 0 | 11220 ins_pipe(pipe_jmp); |
| 11221 ins_short_branch(1); | |
| 11222 %} | |
| 11223 | |
| 11224 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
|
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|
11225 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{ |
| 0 | 11226 match(If cop cr); |
| 11227 effect(USE labl); | |
| 11228 | |
| 11229 ins_cost(300); | |
| 11230 format %{ "j$cop,s $labl" %} | |
| 11231 size(2); | |
| 3851 | 11232 ins_encode %{ |
| 11233 Label* L = $labl$$label; | |
| 11234 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11235 %} | |
| 0 | 11236 ins_pipe(pipe_jcc); |
| 11237 ins_short_branch(1); | |
| 11238 %} | |
| 11239 | |
| 11240 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
|
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|
11241 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{ |
| 0 | 11242 match(CountedLoopEnd cop cr); |
| 11243 effect(USE labl); | |
| 11244 | |
| 11245 ins_cost(300); | |
|
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|
11246 format %{ "j$cop,s $labl\t# loop end" %} |
| 0 | 11247 size(2); |
| 3851 | 11248 ins_encode %{ |
| 11249 Label* L = $labl$$label; | |
| 11250 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11251 %} | |
| 0 | 11252 ins_pipe(pipe_jcc); |
| 11253 ins_short_branch(1); | |
| 11254 %} | |
| 11255 | |
| 11256 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
|
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|
11257 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
|
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|
11258 match(CountedLoopEnd cop cmp); |
|
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|
11259 effect(USE labl); |
|
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|
11260 |
|
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|
11261 ins_cost(300); |
|
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|
11262 format %{ "j$cop,us $labl\t# loop end" %} |
|
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|
11263 size(2); |
| 3851 | 11264 ins_encode %{ |
| 11265 Label* L = $labl$$label; | |
| 11266 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11267 %} | |
|
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|
11268 ins_pipe(pipe_jcc); |
|
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|
11269 ins_short_branch(1); |
|
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|
11270 %} |
|
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|
11271 |
|
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|
11272 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
| 0 | 11273 match(CountedLoopEnd cop cmp); |
| 11274 effect(USE labl); | |
| 11275 | |
| 11276 ins_cost(300); | |
|
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|
11277 format %{ "j$cop,us $labl\t# loop end" %} |
|
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|
11278 size(2); |
| 3851 | 11279 ins_encode %{ |
| 11280 Label* L = $labl$$label; | |
| 11281 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11282 %} | |
|
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|
11283 ins_pipe(pipe_jcc); |
|
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|
11284 ins_short_branch(1); |
|
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|
11285 %} |
|
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|
11286 |
|
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changeset
|
11287 // Jump Direct Conditional - using unsigned comparison |
|
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|
11288 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
|
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|
11289 match(If cop cmp); |
|
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|
11290 effect(USE labl); |
|
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|
11291 |
|
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|
11292 ins_cost(300); |
| 0 | 11293 format %{ "j$cop,us $labl" %} |
| 11294 size(2); | |
| 3851 | 11295 ins_encode %{ |
| 11296 Label* L = $labl$$label; | |
| 11297 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11298 %} | |
| 0 | 11299 ins_pipe(pipe_jcc); |
| 11300 ins_short_branch(1); | |
| 11301 %} | |
| 11302 | |
|
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|
11303 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
| 0 | 11304 match(If cop cmp); |
| 11305 effect(USE labl); | |
| 11306 | |
| 11307 ins_cost(300); | |
| 11308 format %{ "j$cop,us $labl" %} | |
| 11309 size(2); | |
| 3851 | 11310 ins_encode %{ |
| 11311 Label* L = $labl$$label; | |
| 11312 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11313 %} | |
| 0 | 11314 ins_pipe(pipe_jcc); |
| 11315 ins_short_branch(1); | |
| 11316 %} | |
| 11317 | |
|
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11318 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{ |
|
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|
11319 match(If cop cmp); |
|
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|
11320 effect(USE labl); |
|
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|
11321 |
|
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|
11322 ins_cost(300); |
|
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|
11323 format %{ $$template |
|
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|
11324 if ($cop$$cmpcode == Assembler::notEqual) { |
|
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|
11325 $$emit$$"jp,u,s $labl\n\t" |
|
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|
11326 $$emit$$"j$cop,u,s $labl" |
|
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|
11327 } else { |
|
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|
11328 $$emit$$"jp,u,s done\n\t" |
|
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|
11329 $$emit$$"j$cop,u,s $labl\n\t" |
|
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|
11330 $$emit$$"done:" |
|
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|
11331 } |
|
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|
11332 %} |
|
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|
11333 size(4); |
|
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|
11334 ins_encode %{ |
|
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|
11335 Label* l = $labl$$label; |
|
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|
11336 if ($cop$$cmpcode == Assembler::notEqual) { |
| 3851 | 11337 __ jccb(Assembler::parity, *l); |
| 11338 __ jccb(Assembler::notEqual, *l); | |
|
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|
11339 } else if ($cop$$cmpcode == Assembler::equal) { |
| 3851 | 11340 Label done; |
| 11341 __ jccb(Assembler::parity, done); | |
| 11342 __ jccb(Assembler::equal, *l); | |
| 11343 __ bind(done); | |
|
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|
11344 } else { |
| 3851 | 11345 ShouldNotReachHere(); |
| 11346 } | |
|
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|
11347 %} |
|
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|
11348 ins_pipe(pipe_jcc); |
|
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|
11349 ins_short_branch(1); |
|
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|
11350 %} |
|
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|
11351 |
| 0 | 11352 // ============================================================================ |
| 11353 // inlined locking and unlocking | |
| 11354 | |
| 11355 instruct cmpFastLock(rFlagsReg cr, | |
| 4777 | 11356 rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr) |
| 0 | 11357 %{ |
| 11358 match(Set cr (FastLock object box)); | |
| 4777 | 11359 effect(TEMP tmp, TEMP scr, USE_KILL box); |
| 0 | 11360 |
| 11361 ins_cost(300); | |
| 4777 | 11362 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %} |
| 0 | 11363 ins_encode(Fast_Lock(object, box, tmp, scr)); |
| 11364 ins_pipe(pipe_slow); | |
| 11365 %} | |
| 11366 | |
| 11367 instruct cmpFastUnlock(rFlagsReg cr, | |
| 11368 rRegP object, rax_RegP box, rRegP tmp) | |
| 11369 %{ | |
| 11370 match(Set cr (FastUnlock object box)); | |
| 4777 | 11371 effect(TEMP tmp, USE_KILL box); |
| 0 | 11372 |
| 11373 ins_cost(300); | |
| 4777 | 11374 format %{ "fastunlock $object,$box\t! kills $box,$tmp" %} |
| 0 | 11375 ins_encode(Fast_Unlock(object, box, tmp)); |
| 11376 ins_pipe(pipe_slow); | |
| 11377 %} | |
| 11378 | |
| 11379 | |
| 11380 // ============================================================================ | |
| 11381 // Safepoint Instructions | |
| 11382 instruct safePoint_poll(rFlagsReg cr) | |
| 11383 %{ | |
|
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11384 predicate(!Assembler::is_polling_page_far()); |
| 0 | 11385 match(SafePoint); |
| 11386 effect(KILL cr); | |
| 11387 | |
|
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|
11388 format %{ "testl rax, [rip + #offset_to_poll_page]\t" |
| 0 | 11389 "# Safepoint: poll for GC" %} |
| 11390 ins_cost(125); | |
|
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|
11391 ins_encode %{ |
|
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|
11392 AddressLiteral addr(os::get_polling_page(), relocInfo::poll_type); |
|
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|
11393 __ testl(rax, addr); |
|
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|
11394 %} |
|
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|
11395 ins_pipe(ialu_reg_mem); |
|
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|
11396 %} |
|
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|
11397 |
|
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|
11398 instruct safePoint_poll_far(rFlagsReg cr, rRegP poll) |
|
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|
11399 %{ |
|
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|
11400 predicate(Assembler::is_polling_page_far()); |
|
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|
11401 match(SafePoint poll); |
|
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|
11402 effect(KILL cr, USE poll); |
|
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|
11403 |
|
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|
11404 format %{ "testl rax, [$poll]\t" |
|
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|
11405 "# Safepoint: poll for GC" %} |
|
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|
11406 ins_cost(125); |
|
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|
11407 ins_encode %{ |
|
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|
11408 __ relocate(relocInfo::poll_type); |
|
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|
11409 __ testl(rax, Address($poll$$Register, 0)); |
|
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|
11410 %} |
| 0 | 11411 ins_pipe(ialu_reg_mem); |
| 11412 %} | |
| 11413 | |
| 11414 // ============================================================================ | |
| 11415 // Procedure Call/Return Instructions | |
| 11416 // Call Java Static Instruction | |
| 11417 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 11418 // compute_padding() functions will have to be adjusted. | |
|
1137
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|
11419 instruct CallStaticJavaDirect(method meth) %{ |
| 0 | 11420 match(CallStaticJava); |
|
1137
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|
11421 predicate(!((CallStaticJavaNode*) n)->is_method_handle_invoke()); |
| 0 | 11422 effect(USE meth); |
| 11423 | |
| 11424 ins_cost(300); | |
| 11425 format %{ "call,static " %} | |
| 11426 opcode(0xE8); /* E8 cd */ | |
|
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|
11427 ins_encode(clear_avx, Java_Static_Call(meth), call_epilog); |
| 0 | 11428 ins_pipe(pipe_slow); |
| 11429 ins_alignment(4); | |
| 11430 %} | |
| 11431 | |
|
1137
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|
11432 // Call Java Static Instruction (method handle version) |
|
97125851f396
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|
11433 // Note: If this code changes, the corresponding ret_addr_offset() and |
|
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|
11434 // compute_padding() functions will have to be adjusted. |
| 1567 | 11435 instruct CallStaticJavaHandle(method meth, rbp_RegP rbp_mh_SP_save) %{ |
|
1137
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|
11436 match(CallStaticJava); |
|
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|
11437 predicate(((CallStaticJavaNode*) n)->is_method_handle_invoke()); |
|
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|
11438 effect(USE meth); |
|
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|
11439 // RBP is saved by all callees (for interpreter stack correction). |
|
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|
11440 // We use it here for a similar purpose, in {preserve,restore}_SP. |
|
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|
11441 |
|
97125851f396
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|
11442 ins_cost(300); |
|
97125851f396
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|
11443 format %{ "call,static/MethodHandle " %} |
|
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|
11444 opcode(0xE8); /* E8 cd */ |
|
8873
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|
11445 ins_encode(clear_avx, preserve_SP, |
|
1137
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|
11446 Java_Static_Call(meth), |
|
97125851f396
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|
11447 restore_SP, |
|
97125851f396
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|
11448 call_epilog); |
|
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|
11449 ins_pipe(pipe_slow); |
|
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|
11450 ins_alignment(4); |
|
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|
11451 %} |
|
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|
11452 |
| 0 | 11453 // Call Java Dynamic Instruction |
| 11454 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 11455 // compute_padding() functions will have to be adjusted. | |
| 11456 instruct CallDynamicJavaDirect(method meth) | |
| 11457 %{ | |
| 11458 match(CallDynamicJava); | |
| 11459 effect(USE meth); | |
| 11460 | |
| 11461 ins_cost(300); | |
| 11462 format %{ "movq rax, #Universe::non_oop_word()\n\t" | |
| 11463 "call,dynamic " %} | |
|
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|
11464 ins_encode(clear_avx, Java_Dynamic_Call(meth), call_epilog); |
| 0 | 11465 ins_pipe(pipe_slow); |
| 11466 ins_alignment(4); | |
| 11467 %} | |
| 11468 | |
| 11469 // Call Runtime Instruction | |
| 11470 instruct CallRuntimeDirect(method meth) | |
| 11471 %{ | |
| 11472 match(CallRuntime); | |
| 11473 effect(USE meth); | |
| 11474 | |
| 11475 ins_cost(300); | |
| 11476 format %{ "call,runtime " %} | |
|
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|
11477 ins_encode(clear_avx, Java_To_Runtime(meth)); |
| 0 | 11478 ins_pipe(pipe_slow); |
| 11479 %} | |
| 11480 | |
| 11481 // Call runtime without safepoint | |
| 11482 instruct CallLeafDirect(method meth) | |
| 11483 %{ | |
| 11484 match(CallLeaf); | |
| 11485 effect(USE meth); | |
| 11486 | |
| 11487 ins_cost(300); | |
| 11488 format %{ "call_leaf,runtime " %} | |
|
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|
11489 ins_encode(clear_avx, Java_To_Runtime(meth)); |
| 0 | 11490 ins_pipe(pipe_slow); |
| 11491 %} | |
| 11492 | |
| 11493 // Call runtime without safepoint | |
| 11494 instruct CallLeafNoFPDirect(method meth) | |
| 11495 %{ | |
| 11496 match(CallLeafNoFP); | |
| 11497 effect(USE meth); | |
| 11498 | |
| 11499 ins_cost(300); | |
| 11500 format %{ "call_leaf_nofp,runtime " %} | |
| 11501 ins_encode(Java_To_Runtime(meth)); | |
| 11502 ins_pipe(pipe_slow); | |
| 11503 %} | |
| 11504 | |
| 11505 // Return Instruction | |
| 11506 // Remove the return address & jump to it. | |
| 11507 // Notice: We always emit a nop after a ret to make sure there is room | |
| 11508 // for safepoint patching | |
| 11509 instruct Ret() | |
| 11510 %{ | |
| 11511 match(Return); | |
| 11512 | |
| 11513 format %{ "ret" %} | |
| 11514 opcode(0xC3); | |
| 11515 ins_encode(OpcP); | |
| 11516 ins_pipe(pipe_jmp); | |
| 11517 %} | |
| 11518 | |
| 11519 // Tail Call; Jump from runtime stub to Java code. | |
| 11520 // Also known as an 'interprocedural jump'. | |
| 11521 // Target of jump will eventually return to caller. | |
| 11522 // TailJump below removes the return address. | |
| 11523 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop) | |
| 11524 %{ | |
| 11525 match(TailCall jump_target method_oop); | |
| 11526 | |
| 11527 ins_cost(300); | |
| 11528 format %{ "jmp $jump_target\t# rbx holds method oop" %} | |
| 11529 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 11530 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target)); | |
| 11531 ins_pipe(pipe_jmp); | |
| 11532 %} | |
| 11533 | |
| 11534 // Tail Jump; remove the return address; jump to target. | |
| 11535 // TailCall above leaves the return address around. | |
| 11536 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop) | |
| 11537 %{ | |
| 11538 match(TailJump jump_target ex_oop); | |
| 11539 | |
| 11540 ins_cost(300); | |
| 11541 format %{ "popq rdx\t# pop return address\n\t" | |
| 11542 "jmp $jump_target" %} | |
| 11543 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 11544 ins_encode(Opcode(0x5a), // popq rdx | |
| 11545 REX_reg(jump_target), OpcP, reg_opc(jump_target)); | |
| 11546 ins_pipe(pipe_jmp); | |
| 11547 %} | |
| 11548 | |
| 11549 // Create exception oop: created by stack-crawling runtime code. | |
| 11550 // Created exception is now available to this handler, and is setup | |
| 11551 // just prior to jumping to this handler. No code emitted. | |
| 11552 instruct CreateException(rax_RegP ex_oop) | |
| 11553 %{ | |
| 11554 match(Set ex_oop (CreateEx)); | |
| 11555 | |
| 11556 size(0); | |
| 11557 // use the following format syntax | |
| 11558 format %{ "# exception oop is in rax; no code emitted" %} | |
| 11559 ins_encode(); | |
| 11560 ins_pipe(empty); | |
| 11561 %} | |
| 11562 | |
| 11563 // Rethrow exception: | |
| 11564 // The exception oop will come in the first argument position. | |
| 11565 // Then JUMP (not call) to the rethrow stub code. | |
| 11566 instruct RethrowException() | |
| 11567 %{ | |
| 11568 match(Rethrow); | |
| 11569 | |
| 11570 // use the following format syntax | |
| 11571 format %{ "jmp rethrow_stub" %} | |
| 11572 ins_encode(enc_rethrow); | |
| 11573 ins_pipe(pipe_jmp); | |
| 11574 %} | |
| 11575 | |
| 11576 | |
| 4950 | 11577 // ============================================================================ |
| 11578 // This name is KNOWN by the ADLC and cannot be changed. | |
| 11579 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type | |
| 11580 // for this guy. | |
| 11581 instruct tlsLoadP(r15_RegP dst) %{ | |
| 11582 match(Set dst (ThreadLocal)); | |
| 11583 effect(DEF dst); | |
| 11584 | |
| 11585 size(0); | |
| 11586 format %{ "# TLS is in R15" %} | |
| 11587 ins_encode( /*empty encoding*/ ); | |
| 11588 ins_pipe(ialu_reg_reg); | |
| 11589 %} | |
| 11590 | |
| 11591 | |
| 0 | 11592 //----------PEEPHOLE RULES----------------------------------------------------- |
| 11593 // These must follow all instruction definitions as they use the names | |
| 11594 // defined in the instructions definitions. | |
| 11595 // | |
| 605 | 11596 // peepmatch ( root_instr_name [preceding_instruction]* ); |
| 0 | 11597 // |
| 11598 // peepconstraint %{ | |
| 11599 // (instruction_number.operand_name relational_op instruction_number.operand_name | |
| 11600 // [, ...] ); | |
| 11601 // // instruction numbers are zero-based using left to right order in peepmatch | |
| 11602 // | |
| 11603 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); | |
| 11604 // // provide an instruction_number.operand_name for each operand that appears | |
| 11605 // // in the replacement instruction's match rule | |
| 11606 // | |
| 11607 // ---------VM FLAGS--------------------------------------------------------- | |
| 11608 // | |
| 11609 // All peephole optimizations can be turned off using -XX:-OptoPeephole | |
| 11610 // | |
| 11611 // Each peephole rule is given an identifying number starting with zero and | |
| 11612 // increasing by one in the order seen by the parser. An individual peephole | |
| 11613 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# | |
| 11614 // on the command-line. | |
| 11615 // | |
| 11616 // ---------CURRENT LIMITATIONS---------------------------------------------- | |
| 11617 // | |
| 11618 // Only match adjacent instructions in same basic block | |
| 11619 // Only equality constraints | |
| 11620 // Only constraints between operands, not (0.dest_reg == RAX_enc) | |
| 11621 // Only one replacement instruction | |
| 11622 // | |
| 11623 // ---------EXAMPLE---------------------------------------------------------- | |
| 11624 // | |
| 11625 // // pertinent parts of existing instructions in architecture description | |
| 11626 // instruct movI(rRegI dst, rRegI src) | |
| 11627 // %{ | |
| 11628 // match(Set dst (CopyI src)); | |
| 11629 // %} | |
| 11630 // | |
| 11631 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr) | |
| 11632 // %{ | |
| 11633 // match(Set dst (AddI dst src)); | |
| 11634 // effect(KILL cr); | |
| 11635 // %} | |
| 11636 // | |
| 11637 // // Change (inc mov) to lea | |
| 11638 // peephole %{ | |
| 11639 // // increment preceeded by register-register move | |
| 11640 // peepmatch ( incI_rReg movI ); | |
| 11641 // // require that the destination register of the increment | |
| 11642 // // match the destination register of the move | |
| 11643 // peepconstraint ( 0.dst == 1.dst ); | |
| 11644 // // construct a replacement instruction that sets | |
| 11645 // // the destination to ( move's source register + one ) | |
| 11646 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) ); | |
| 11647 // %} | |
| 11648 // | |
| 11649 | |
| 11650 // Implementation no longer uses movX instructions since | |
| 11651 // machine-independent system no longer uses CopyX nodes. | |
| 11652 // | |
| 11653 // peephole | |
| 11654 // %{ | |
| 11655 // peepmatch (incI_rReg movI); | |
| 11656 // peepconstraint (0.dst == 1.dst); | |
| 11657 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src)); | |
| 11658 // %} | |
| 11659 | |
| 11660 // peephole | |
| 11661 // %{ | |
| 11662 // peepmatch (decI_rReg movI); | |
| 11663 // peepconstraint (0.dst == 1.dst); | |
| 11664 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src)); | |
| 11665 // %} | |
| 11666 | |
| 11667 // peephole | |
| 11668 // %{ | |
| 11669 // peepmatch (addI_rReg_imm movI); | |
| 11670 // peepconstraint (0.dst == 1.dst); | |
| 11671 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src)); | |
| 11672 // %} | |
| 11673 | |
| 11674 // peephole | |
| 11675 // %{ | |
| 11676 // peepmatch (incL_rReg movL); | |
| 11677 // peepconstraint (0.dst == 1.dst); | |
| 11678 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src)); | |
| 11679 // %} | |
| 11680 | |
| 11681 // peephole | |
| 11682 // %{ | |
| 11683 // peepmatch (decL_rReg movL); | |
| 11684 // peepconstraint (0.dst == 1.dst); | |
| 11685 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src)); | |
| 11686 // %} | |
| 11687 | |
| 11688 // peephole | |
| 11689 // %{ | |
| 11690 // peepmatch (addL_rReg_imm movL); | |
| 11691 // peepconstraint (0.dst == 1.dst); | |
| 11692 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src)); | |
| 11693 // %} | |
| 11694 | |
| 11695 // peephole | |
| 11696 // %{ | |
| 11697 // peepmatch (addP_rReg_imm movP); | |
| 11698 // peepconstraint (0.dst == 1.dst); | |
| 11699 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src)); | |
| 11700 // %} | |
| 11701 | |
| 11702 // // Change load of spilled value to only a spill | |
| 11703 // instruct storeI(memory mem, rRegI src) | |
| 11704 // %{ | |
| 11705 // match(Set mem (StoreI mem src)); | |
| 11706 // %} | |
| 11707 // | |
| 11708 // instruct loadI(rRegI dst, memory mem) | |
| 11709 // %{ | |
| 11710 // match(Set dst (LoadI mem)); | |
| 11711 // %} | |
| 11712 // | |
| 11713 | |
| 11714 peephole | |
| 11715 %{ | |
| 11716 peepmatch (loadI storeI); | |
| 11717 peepconstraint (1.src == 0.dst, 1.mem == 0.mem); | |
| 11718 peepreplace (storeI(1.mem 1.mem 1.src)); | |
| 11719 %} | |
| 11720 | |
| 11721 peephole | |
| 11722 %{ | |
| 11723 peepmatch (loadL storeL); | |
| 11724 peepconstraint (1.src == 0.dst, 1.mem == 0.mem); | |
| 11725 peepreplace (storeL(1.mem 1.mem 1.src)); | |
| 11726 %} | |
| 11727 | |
| 11728 //----------SMARTSPILL RULES--------------------------------------------------- | |
| 11729 // These must follow all instruction definitions as they use the names | |
| 11730 // defined in the instructions definitions. |