Mercurial > hg > truffle
comparison src/cpu/x86/vm/x86_64.ad @ 785:2056494941db
6814842: Load shortening optimizations
Summary: 6797305 handles load widening but no shortening which should be covered here.
Reviewed-by: never, kvn
author | twisti |
---|---|
date | Wed, 13 May 2009 00:45:22 -0700 |
parents | 93c14e5562c4 |
children | 18a08a7e16b5 |
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784:b2934faac289 | 785:2056494941db |
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6457 %} | 6457 %} |
6458 | 6458 |
6459 ins_pipe(ialu_reg_mem); | 6459 ins_pipe(ialu_reg_mem); |
6460 %} | 6460 %} |
6461 | 6461 |
6462 // Load Short (16 bit signed) to Byte (8 bit signed) | |
6463 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{ | |
6464 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); | |
6465 | |
6466 ins_cost(125); | |
6467 format %{ "movsbl $dst, $mem\t# short -> byte" %} | |
6468 ins_encode %{ | |
6469 __ movsbl($dst$$Register, $mem$$Address); | |
6470 %} | |
6471 ins_pipe(ialu_reg_mem); | |
6472 %} | |
6473 | |
6462 // Load Short (16 bit signed) into Long Register | 6474 // Load Short (16 bit signed) into Long Register |
6463 instruct loadS2L(rRegL dst, memory mem) | 6475 instruct loadS2L(rRegL dst, memory mem) |
6464 %{ | 6476 %{ |
6465 match(Set dst (ConvI2L (LoadS mem))); | 6477 match(Set dst (ConvI2L (LoadS mem))); |
6466 | 6478 |
6487 %} | 6499 %} |
6488 | 6500 |
6489 ins_pipe(ialu_reg_mem); | 6501 ins_pipe(ialu_reg_mem); |
6490 %} | 6502 %} |
6491 | 6503 |
6504 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) | |
6505 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{ | |
6506 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); | |
6507 | |
6508 ins_cost(125); | |
6509 format %{ "movsbl $dst, $mem\t# ushort -> byte" %} | |
6510 ins_encode %{ | |
6511 __ movsbl($dst$$Register, $mem$$Address); | |
6512 %} | |
6513 ins_pipe(ialu_reg_mem); | |
6514 %} | |
6515 | |
6492 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register | 6516 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register |
6493 instruct loadUS2L(rRegL dst, memory mem) | 6517 instruct loadUS2L(rRegL dst, memory mem) |
6494 %{ | 6518 %{ |
6495 match(Set dst (ConvI2L (LoadUS mem))); | 6519 match(Set dst (ConvI2L (LoadUS mem))); |
6496 | 6520 |
6514 | 6538 |
6515 ins_encode %{ | 6539 ins_encode %{ |
6516 __ movl($dst$$Register, $mem$$Address); | 6540 __ movl($dst$$Register, $mem$$Address); |
6517 %} | 6541 %} |
6518 | 6542 |
6543 ins_pipe(ialu_reg_mem); | |
6544 %} | |
6545 | |
6546 // Load Integer (32 bit signed) to Byte (8 bit signed) | |
6547 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{ | |
6548 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); | |
6549 | |
6550 ins_cost(125); | |
6551 format %{ "movsbl $dst, $mem\t# int -> byte" %} | |
6552 ins_encode %{ | |
6553 __ movsbl($dst$$Register, $mem$$Address); | |
6554 %} | |
6555 ins_pipe(ialu_reg_mem); | |
6556 %} | |
6557 | |
6558 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned) | |
6559 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{ | |
6560 match(Set dst (AndI (LoadI mem) mask)); | |
6561 | |
6562 ins_cost(125); | |
6563 format %{ "movzbl $dst, $mem\t# int -> ubyte" %} | |
6564 ins_encode %{ | |
6565 __ movzbl($dst$$Register, $mem$$Address); | |
6566 %} | |
6567 ins_pipe(ialu_reg_mem); | |
6568 %} | |
6569 | |
6570 // Load Integer (32 bit signed) to Short (16 bit signed) | |
6571 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{ | |
6572 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); | |
6573 | |
6574 ins_cost(125); | |
6575 format %{ "movswl $dst, $mem\t# int -> short" %} | |
6576 ins_encode %{ | |
6577 __ movswl($dst$$Register, $mem$$Address); | |
6578 %} | |
6579 ins_pipe(ialu_reg_mem); | |
6580 %} | |
6581 | |
6582 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned) | |
6583 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{ | |
6584 match(Set dst (AndI (LoadI mem) mask)); | |
6585 | |
6586 ins_cost(125); | |
6587 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %} | |
6588 ins_encode %{ | |
6589 __ movzwl($dst$$Register, $mem$$Address); | |
6590 %} | |
6519 ins_pipe(ialu_reg_mem); | 6591 ins_pipe(ialu_reg_mem); |
6520 %} | 6592 %} |
6521 | 6593 |
6522 // Load Integer into Long Register | 6594 // Load Integer into Long Register |
6523 instruct loadI2L(rRegL dst, memory mem) | 6595 instruct loadI2L(rRegL dst, memory mem) |