Mercurial > hg > truffle
comparison src/cpu/sparc/vm/sharedRuntime_sparc.cpp @ 6790:2cb2f30450c7
7196262: JSR 292: java/lang/invoke/PrivateInvokeTest.java fails on solaris-sparc
Reviewed-by: kvn, jrose, bdelsart
author | twisti |
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date | Mon, 17 Sep 2012 12:57:58 -0700 |
parents | 8a02ca5e5576 |
children | 137868b7aa6f |
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6749:a6fe94b9759f | 6790:2cb2f30450c7 |
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362 | 362 |
363 | 363 |
364 // --------------------------------------------------------------------------- | 364 // --------------------------------------------------------------------------- |
365 // The compiled Java calling convention. The Java convention always passes | 365 // The compiled Java calling convention. The Java convention always passes |
366 // 64-bit values in adjacent aligned locations (either registers or stack), | 366 // 64-bit values in adjacent aligned locations (either registers or stack), |
367 // floats in float registers and doubles in aligned float pairs. Values are | 367 // floats in float registers and doubles in aligned float pairs. There is |
368 // packed in the registers. There is no backing varargs store for values in | 368 // no backing varargs store for values in registers. |
369 // registers. In the 32-bit build, longs are passed in G1 and G4 (cannot be | 369 // In the 32-bit build, longs are passed on the stack (cannot be |
370 // passed in I's, because longs in I's get their heads chopped off at | 370 // passed in I's, because longs in I's get their heads chopped off at |
371 // interrupt). | 371 // interrupt). |
372 int SharedRuntime::java_calling_convention(const BasicType *sig_bt, | 372 int SharedRuntime::java_calling_convention(const BasicType *sig_bt, |
373 VMRegPair *regs, | 373 VMRegPair *regs, |
374 int total_args_passed, | 374 int total_args_passed, |
375 int is_outgoing) { | 375 int is_outgoing) { |
376 assert(F31->as_VMReg()->is_reg(), "overlapping stack/register numbers"); | 376 assert(F31->as_VMReg()->is_reg(), "overlapping stack/register numbers"); |
377 | 377 |
378 // Convention is to pack the first 6 int/oop args into the first 6 registers | |
379 // (I0-I5), extras spill to the stack. Then pack the first 8 float args | |
380 // into F0-F7, extras spill to the stack. Then pad all register sets to | |
381 // align. Then put longs and doubles into the same registers as they fit, | |
382 // else spill to the stack. | |
383 const int int_reg_max = SPARC_ARGS_IN_REGS_NUM; | 378 const int int_reg_max = SPARC_ARGS_IN_REGS_NUM; |
384 const int flt_reg_max = 8; | 379 const int flt_reg_max = 8; |
385 // | 380 |
386 // Where 32-bit 1-reg longs start being passed | |
387 // In tiered we must pass on stack because c1 can't use a "pair" in a single reg. | |
388 // So make it look like we've filled all the G regs that c2 wants to use. | |
389 Register g_reg = TieredCompilation ? noreg : G1; | |
390 | |
391 // Count int/oop and float args. See how many stack slots we'll need and | |
392 // where the longs & doubles will go. | |
393 int int_reg_cnt = 0; | |
394 int flt_reg_cnt = 0; | |
395 // int stk_reg_pairs = frame::register_save_words*(wordSize>>2); | |
396 // int stk_reg_pairs = SharedRuntime::out_preserve_stack_slots(); | |
397 int stk_reg_pairs = 0; | |
398 for (int i = 0; i < total_args_passed; i++) { | |
399 switch (sig_bt[i]) { | |
400 case T_LONG: // LP64, longs compete with int args | |
401 assert(sig_bt[i+1] == T_VOID, ""); | |
402 #ifdef _LP64 | |
403 if (int_reg_cnt < int_reg_max) int_reg_cnt++; | |
404 #endif | |
405 break; | |
406 case T_OBJECT: | |
407 case T_ARRAY: | |
408 case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address | |
409 if (int_reg_cnt < int_reg_max) int_reg_cnt++; | |
410 #ifndef _LP64 | |
411 else stk_reg_pairs++; | |
412 #endif | |
413 break; | |
414 case T_INT: | |
415 case T_SHORT: | |
416 case T_CHAR: | |
417 case T_BYTE: | |
418 case T_BOOLEAN: | |
419 if (int_reg_cnt < int_reg_max) int_reg_cnt++; | |
420 else stk_reg_pairs++; | |
421 break; | |
422 case T_FLOAT: | |
423 if (flt_reg_cnt < flt_reg_max) flt_reg_cnt++; | |
424 else stk_reg_pairs++; | |
425 break; | |
426 case T_DOUBLE: | |
427 assert(sig_bt[i+1] == T_VOID, ""); | |
428 break; | |
429 case T_VOID: | |
430 break; | |
431 default: | |
432 ShouldNotReachHere(); | |
433 } | |
434 } | |
435 | |
436 // This is where the longs/doubles start on the stack. | |
437 stk_reg_pairs = (stk_reg_pairs+1) & ~1; // Round | |
438 | |
439 int flt_reg_pairs = (flt_reg_cnt+1) & ~1; | |
440 | |
441 // int stk_reg = frame::register_save_words*(wordSize>>2); | |
442 // int stk_reg = SharedRuntime::out_preserve_stack_slots(); | |
443 int stk_reg = 0; | |
444 int int_reg = 0; | 381 int int_reg = 0; |
445 int flt_reg = 0; | 382 int flt_reg = 0; |
446 | 383 int slot = 0; |
447 // Now do the signature layout | 384 |
448 for (int i = 0; i < total_args_passed; i++) { | 385 for (int i = 0; i < total_args_passed; i++) { |
449 switch (sig_bt[i]) { | 386 switch (sig_bt[i]) { |
450 case T_INT: | 387 case T_INT: |
451 case T_SHORT: | 388 case T_SHORT: |
452 case T_CHAR: | 389 case T_CHAR: |
459 #endif // _LP64 | 396 #endif // _LP64 |
460 if (int_reg < int_reg_max) { | 397 if (int_reg < int_reg_max) { |
461 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++); | 398 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++); |
462 regs[i].set1(r->as_VMReg()); | 399 regs[i].set1(r->as_VMReg()); |
463 } else { | 400 } else { |
464 regs[i].set1(VMRegImpl::stack2reg(stk_reg++)); | 401 regs[i].set1(VMRegImpl::stack2reg(slot++)); |
465 } | 402 } |
466 break; | 403 break; |
467 | 404 |
468 #ifdef _LP64 | 405 #ifdef _LP64 |
406 case T_LONG: | |
407 assert(sig_bt[i+1] == T_VOID, "expecting VOID in other half"); | |
408 // fall-through | |
469 case T_OBJECT: | 409 case T_OBJECT: |
470 case T_ARRAY: | 410 case T_ARRAY: |
471 case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address | 411 case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address |
472 if (int_reg < int_reg_max) { | 412 if (int_reg < int_reg_max) { |
473 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++); | 413 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++); |
474 regs[i].set2(r->as_VMReg()); | 414 regs[i].set2(r->as_VMReg()); |
475 } else { | 415 } else { |
476 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs)); | 416 slot = round_to(slot, 2); // align |
477 stk_reg_pairs += 2; | 417 regs[i].set2(VMRegImpl::stack2reg(slot)); |
418 slot += 2; | |
478 } | 419 } |
479 break; | 420 break; |
480 #endif // _LP64 | 421 #else |
481 | |
482 case T_LONG: | 422 case T_LONG: |
483 assert(sig_bt[i+1] == T_VOID, "expecting VOID in other half"); | 423 assert(sig_bt[i+1] == T_VOID, "expecting VOID in other half"); |
484 #ifdef _LP64 | 424 // On 32-bit SPARC put longs always on the stack to keep the pressure off |
485 if (int_reg < int_reg_max) { | 425 // integer argument registers. They should be used for oops. |
486 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++); | 426 slot = round_to(slot, 2); // align |
487 regs[i].set2(r->as_VMReg()); | 427 regs[i].set2(VMRegImpl::stack2reg(slot)); |
488 } else { | 428 slot += 2; |
489 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs)); | 429 #endif |
490 stk_reg_pairs += 2; | |
491 } | |
492 #else | |
493 #ifdef COMPILER2 | |
494 // For 32-bit build, can't pass longs in O-regs because they become | |
495 // I-regs and get trashed. Use G-regs instead. G1 and G4 are almost | |
496 // spare and available. This convention isn't used by the Sparc ABI or | |
497 // anywhere else. If we're tiered then we don't use G-regs because c1 | |
498 // can't deal with them as a "pair". (Tiered makes this code think g's are filled) | |
499 // G0: zero | |
500 // G1: 1st Long arg | |
501 // G2: global allocated to TLS | |
502 // G3: used in inline cache check | |
503 // G4: 2nd Long arg | |
504 // G5: used in inline cache check | |
505 // G6: used by OS | |
506 // G7: used by OS | |
507 | |
508 if (g_reg == G1) { | |
509 regs[i].set2(G1->as_VMReg()); // This long arg in G1 | |
510 g_reg = G4; // Where the next arg goes | |
511 } else if (g_reg == G4) { | |
512 regs[i].set2(G4->as_VMReg()); // The 2nd long arg in G4 | |
513 g_reg = noreg; // No more longs in registers | |
514 } else { | |
515 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs)); | |
516 stk_reg_pairs += 2; | |
517 } | |
518 #else // COMPILER2 | |
519 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs)); | |
520 stk_reg_pairs += 2; | |
521 #endif // COMPILER2 | |
522 #endif // _LP64 | |
523 break; | 430 break; |
524 | 431 |
525 case T_FLOAT: | 432 case T_FLOAT: |
526 if (flt_reg < flt_reg_max) regs[i].set1(as_FloatRegister(flt_reg++)->as_VMReg()); | 433 if (flt_reg < flt_reg_max) { |
527 else regs[i].set1(VMRegImpl::stack2reg(stk_reg++)); | 434 FloatRegister r = as_FloatRegister(flt_reg++); |
435 regs[i].set1(r->as_VMReg()); | |
436 } else { | |
437 regs[i].set1(VMRegImpl::stack2reg(slot++)); | |
438 } | |
528 break; | 439 break; |
440 | |
529 case T_DOUBLE: | 441 case T_DOUBLE: |
530 assert(sig_bt[i+1] == T_VOID, "expecting half"); | 442 assert(sig_bt[i+1] == T_VOID, "expecting half"); |
531 if (flt_reg_pairs + 1 < flt_reg_max) { | 443 if (round_to(flt_reg, 2) + 1 < flt_reg_max) { |
532 regs[i].set2(as_FloatRegister(flt_reg_pairs)->as_VMReg()); | 444 flt_reg = round_to(flt_reg, 2); // align |
533 flt_reg_pairs += 2; | 445 FloatRegister r = as_FloatRegister(flt_reg); |
446 regs[i].set2(r->as_VMReg()); | |
447 flt_reg += 2; | |
534 } else { | 448 } else { |
535 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs)); | 449 slot = round_to(slot, 2); // align |
536 stk_reg_pairs += 2; | 450 regs[i].set2(VMRegImpl::stack2reg(slot)); |
451 slot += 2; | |
537 } | 452 } |
538 break; | 453 break; |
539 case T_VOID: regs[i].set_bad(); break; // Halves of longs & doubles | 454 |
455 case T_VOID: | |
456 regs[i].set_bad(); // Halves of longs & doubles | |
457 break; | |
458 | |
540 default: | 459 default: |
541 ShouldNotReachHere(); | 460 fatal(err_msg_res("unknown basic type %d", sig_bt[i])); |
461 break; | |
542 } | 462 } |
543 } | 463 } |
544 | 464 |
545 // retun the amount of stack space these arguments will need. | 465 // retun the amount of stack space these arguments will need. |
546 return stk_reg_pairs; | 466 return slot; |
547 | |
548 } | 467 } |
549 | 468 |
550 // Helper class mostly to avoid passing masm everywhere, and handle | 469 // Helper class mostly to avoid passing masm everywhere, and handle |
551 // store displacement overflow logic. | 470 // store displacement overflow logic. |
552 class AdapterGenerator { | 471 class AdapterGenerator { |
599 // Patch the callers callsite with entry to compiled code if it exists. | 518 // Patch the callers callsite with entry to compiled code if it exists. |
600 void AdapterGenerator::patch_callers_callsite() { | 519 void AdapterGenerator::patch_callers_callsite() { |
601 Label L; | 520 Label L; |
602 __ ld_ptr(G5_method, in_bytes(Method::code_offset()), G3_scratch); | 521 __ ld_ptr(G5_method, in_bytes(Method::code_offset()), G3_scratch); |
603 __ br_null(G3_scratch, false, Assembler::pt, L); | 522 __ br_null(G3_scratch, false, Assembler::pt, L); |
604 // Schedule the branch target address early. | 523 __ delayed()->nop(); |
605 __ delayed()->ld_ptr(G5_method, in_bytes(Method::interpreter_entry_offset()), G3_scratch); | |
606 // Call into the VM to patch the caller, then jump to compiled callee | 524 // Call into the VM to patch the caller, then jump to compiled callee |
607 __ save_frame(4); // Args in compiled layout; do not blow them | 525 __ save_frame(4); // Args in compiled layout; do not blow them |
608 | 526 |
609 // Must save all the live Gregs the list is: | 527 // Must save all the live Gregs the list is: |
610 // G1: 1st Long arg (32bit build) | 528 // G1: 1st Long arg (32bit build) |
643 __ delayed()->mov(G2_thread, L7_thread_cache); | 561 __ delayed()->mov(G2_thread, L7_thread_cache); |
644 __ mov(L7_thread_cache, G2_thread); | 562 __ mov(L7_thread_cache, G2_thread); |
645 __ ldx(FP, -8 + STACK_BIAS, G1); | 563 __ ldx(FP, -8 + STACK_BIAS, G1); |
646 __ ldx(FP, -16 + STACK_BIAS, G4); | 564 __ ldx(FP, -16 + STACK_BIAS, G4); |
647 __ mov(L5, G5_method); | 565 __ mov(L5, G5_method); |
648 __ ld_ptr(G5_method, in_bytes(Method::interpreter_entry_offset()), G3_scratch); | |
649 #endif /* _LP64 */ | 566 #endif /* _LP64 */ |
650 | 567 |
651 __ restore(); // Restore args | 568 __ restore(); // Restore args |
652 __ bind(L); | 569 __ bind(L); |
653 } | 570 } |
724 int total_args_passed, | 641 int total_args_passed, |
725 // VMReg max_arg, | 642 // VMReg max_arg, |
726 int comp_args_on_stack, // VMRegStackSlots | 643 int comp_args_on_stack, // VMRegStackSlots |
727 const BasicType *sig_bt, | 644 const BasicType *sig_bt, |
728 const VMRegPair *regs, | 645 const VMRegPair *regs, |
729 Label& skip_fixup) { | 646 Label& L_skip_fixup) { |
730 | 647 |
731 // Before we get into the guts of the C2I adapter, see if we should be here | 648 // Before we get into the guts of the C2I adapter, see if we should be here |
732 // at all. We've come from compiled code and are attempting to jump to the | 649 // at all. We've come from compiled code and are attempting to jump to the |
733 // interpreter, which means the caller made a static call to get here | 650 // interpreter, which means the caller made a static call to get here |
734 // (vcalls always get a compiled target if there is one). Check for a | 651 // (vcalls always get a compiled target if there is one). Check for a |
745 // call and not bother building another interpreter arg area. We don't | 662 // call and not bother building another interpreter arg area. We don't |
746 // do that at this point. | 663 // do that at this point. |
747 | 664 |
748 patch_callers_callsite(); | 665 patch_callers_callsite(); |
749 | 666 |
750 __ bind(skip_fixup); | 667 __ bind(L_skip_fixup); |
751 | 668 |
752 // Since all args are passed on the stack, total_args_passed*wordSize is the | 669 // Since all args are passed on the stack, total_args_passed*wordSize is the |
753 // space we need. Add in varargs area needed by the interpreter. Round up | 670 // space we need. Add in varargs area needed by the interpreter. Round up |
754 // to stack alignment. | 671 // to stack alignment. |
755 const int arg_size = total_args_passed * Interpreter::stackElementSize; | 672 const int arg_size = total_args_passed * Interpreter::stackElementSize; |
756 const int varargs_area = | 673 const int varargs_area = |
757 (frame::varargs_offset - frame::register_save_words)*wordSize; | 674 (frame::varargs_offset - frame::register_save_words)*wordSize; |
758 const int extraspace = round_to(arg_size + varargs_area, 2*wordSize); | 675 const int extraspace = round_to(arg_size + varargs_area, 2*wordSize); |
759 | 676 |
760 int bias = STACK_BIAS; | 677 const int bias = STACK_BIAS; |
761 const int interp_arg_offset = frame::varargs_offset*wordSize + | 678 const int interp_arg_offset = frame::varargs_offset*wordSize + |
762 (total_args_passed-1)*Interpreter::stackElementSize; | 679 (total_args_passed-1)*Interpreter::stackElementSize; |
763 | 680 |
764 Register base = SP; | 681 const Register base = SP; |
765 | 682 |
766 #ifdef _LP64 | 683 // Make some extra space on the stack. |
767 // In the 64bit build because of wider slots and STACKBIAS we can run | 684 __ sub(SP, __ ensure_simm13_or_reg(extraspace, G3_scratch), SP); |
768 // out of bits in the displacement to do loads and stores. Use g3 as | |
769 // temporary displacement. | |
770 if (!Assembler::is_simm13(extraspace)) { | |
771 __ set(extraspace, G3_scratch); | |
772 __ sub(SP, G3_scratch, SP); | |
773 } else { | |
774 __ sub(SP, extraspace, SP); | |
775 } | |
776 set_Rdisp(G3_scratch); | 685 set_Rdisp(G3_scratch); |
777 #else | 686 |
778 __ sub(SP, extraspace, SP); | 687 // Write the args into the outgoing interpreter space. |
779 #endif // _LP64 | 688 for (int i = 0; i < total_args_passed; i++) { |
780 | |
781 // First write G1 (if used) to where ever it must go | |
782 for (int i=0; i<total_args_passed; i++) { | |
783 const int st_off = interp_arg_offset - (i*Interpreter::stackElementSize) + bias; | |
784 VMReg r_1 = regs[i].first(); | |
785 VMReg r_2 = regs[i].second(); | |
786 if (r_1 == G1_scratch->as_VMReg()) { | |
787 if (sig_bt[i] == T_OBJECT || sig_bt[i] == T_ARRAY) { | |
788 store_c2i_object(G1_scratch, base, st_off); | |
789 } else if (sig_bt[i] == T_LONG) { | |
790 assert(!TieredCompilation, "should not use register args for longs"); | |
791 store_c2i_long(G1_scratch, base, st_off, false); | |
792 } else { | |
793 store_c2i_int(G1_scratch, base, st_off); | |
794 } | |
795 } | |
796 } | |
797 | |
798 // Now write the args into the outgoing interpreter space | |
799 for (int i=0; i<total_args_passed; i++) { | |
800 const int st_off = interp_arg_offset - (i*Interpreter::stackElementSize) + bias; | 689 const int st_off = interp_arg_offset - (i*Interpreter::stackElementSize) + bias; |
801 VMReg r_1 = regs[i].first(); | 690 VMReg r_1 = regs[i].first(); |
802 VMReg r_2 = regs[i].second(); | 691 VMReg r_2 = regs[i].second(); |
803 if (!r_1->is_valid()) { | 692 if (!r_1->is_valid()) { |
804 assert(!r_2->is_valid(), ""); | 693 assert(!r_2->is_valid(), ""); |
805 continue; | 694 continue; |
806 } | 695 } |
807 // Skip G1 if found as we did it first in order to free it up | |
808 if (r_1 == G1_scratch->as_VMReg()) { | |
809 continue; | |
810 } | |
811 #ifdef ASSERT | |
812 bool G1_forced = false; | |
813 #endif // ASSERT | |
814 if (r_1->is_stack()) { // Pretend stack targets are loaded into G1 | 696 if (r_1->is_stack()) { // Pretend stack targets are loaded into G1 |
815 #ifdef _LP64 | 697 RegisterOrConstant ld_off = reg2offset(r_1) + extraspace + bias; |
816 Register ld_off = Rdisp; | 698 ld_off = __ ensure_simm13_or_reg(ld_off, Rdisp); |
817 __ set(reg2offset(r_1) + extraspace + bias, ld_off); | |
818 #else | |
819 int ld_off = reg2offset(r_1) + extraspace + bias; | |
820 #endif // _LP64 | |
821 #ifdef ASSERT | |
822 G1_forced = true; | |
823 #endif // ASSERT | |
824 r_1 = G1_scratch->as_VMReg();// as part of the load/store shuffle | 699 r_1 = G1_scratch->as_VMReg();// as part of the load/store shuffle |
825 if (!r_2->is_valid()) __ ld (base, ld_off, G1_scratch); | 700 if (!r_2->is_valid()) __ ld (base, ld_off, G1_scratch); |
826 else __ ldx(base, ld_off, G1_scratch); | 701 else __ ldx(base, ld_off, G1_scratch); |
827 } | 702 } |
828 | 703 |
829 if (r_1->is_Register()) { | 704 if (r_1->is_Register()) { |
830 Register r = r_1->as_Register()->after_restore(); | 705 Register r = r_1->as_Register()->after_restore(); |
831 if (sig_bt[i] == T_OBJECT || sig_bt[i] == T_ARRAY) { | 706 if (sig_bt[i] == T_OBJECT || sig_bt[i] == T_ARRAY) { |
832 store_c2i_object(r, base, st_off); | 707 store_c2i_object(r, base, st_off); |
833 } else if (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) { | 708 } else if (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) { |
834 #ifndef _LP64 | |
835 if (TieredCompilation) { | |
836 assert(G1_forced || sig_bt[i] != T_LONG, "should not use register args for longs"); | |
837 } | |
838 #endif // _LP64 | |
839 store_c2i_long(r, base, st_off, r_2->is_stack()); | 709 store_c2i_long(r, base, st_off, r_2->is_stack()); |
840 } else { | 710 } else { |
841 store_c2i_int(r, base, st_off); | 711 store_c2i_int(r, base, st_off); |
842 } | 712 } |
843 } else { | 713 } else { |
849 store_c2i_double(r_2, r_1, base, st_off); | 719 store_c2i_double(r_2, r_1, base, st_off); |
850 } | 720 } |
851 } | 721 } |
852 } | 722 } |
853 | 723 |
854 #ifdef _LP64 | 724 // Load the interpreter entry point. |
855 // Need to reload G3_scratch, used for temporary displacements. | |
856 __ ld_ptr(G5_method, in_bytes(Method::interpreter_entry_offset()), G3_scratch); | 725 __ ld_ptr(G5_method, in_bytes(Method::interpreter_entry_offset()), G3_scratch); |
857 | 726 |
858 // Pass O5_savedSP as an argument to the interpreter. | 727 // Pass O5_savedSP as an argument to the interpreter. |
859 // The interpreter will restore SP to this value before returning. | 728 // The interpreter will restore SP to this value before returning. |
860 __ set(extraspace, G1); | 729 __ add(SP, __ ensure_simm13_or_reg(extraspace, G1), O5_savedSP); |
861 __ add(SP, G1, O5_savedSP); | |
862 #else | |
863 // Pass O5_savedSP as an argument to the interpreter. | |
864 // The interpreter will restore SP to this value before returning. | |
865 __ add(SP, extraspace, O5_savedSP); | |
866 #endif // _LP64 | |
867 | 730 |
868 __ mov((frame::varargs_offset)*wordSize - | 731 __ mov((frame::varargs_offset)*wordSize - |
869 1*Interpreter::stackElementSize+bias+BytesPerWord, G1); | 732 1*Interpreter::stackElementSize+bias+BytesPerWord, G1); |
870 // Jump to the interpreter just as if interpreter was doing it. | 733 // Jump to the interpreter just as if interpreter was doing it. |
871 __ jmpl(G3_scratch, 0, G0); | 734 __ jmpl(G3_scratch, 0, G0); |
969 // O7 - Valid return address | 832 // O7 - Valid return address |
970 // L0-L7, I0-I7 - Caller's temps (no frame pushed yet) | 833 // L0-L7, I0-I7 - Caller's temps (no frame pushed yet) |
971 | 834 |
972 // Outputs: | 835 // Outputs: |
973 // G2_thread - TLS | 836 // G2_thread - TLS |
974 // G1, G4 - Outgoing long args in 32-bit build | |
975 // O0-O5 - Outgoing args in compiled layout | 837 // O0-O5 - Outgoing args in compiled layout |
976 // O6 - Adjusted or restored SP | 838 // O6 - Adjusted or restored SP |
977 // O7 - Valid return address | 839 // O7 - Valid return address |
978 // L0-L7, I0-I7 - Caller's temps (no frame pushed yet) | 840 // L0-L7, I0-I7 - Caller's temps (no frame pushed yet) |
979 // F0-F7 - more outgoing args | 841 // F0-F7 - more outgoing args |
1014 // : java stack : | 876 // : java stack : |
1015 // | | | 877 // | | |
1016 // +--------------+ <--- start of outgoing args | 878 // +--------------+ <--- start of outgoing args |
1017 // | pad, align | | | 879 // | pad, align | | |
1018 // +--------------+ | | 880 // +--------------+ | |
1019 // | ints, floats | |---Outgoing stack args, packed low. | 881 // | ints, longs, | | |
1020 // +--------------+ | First few args in registers. | 882 // | floats, | |---Outgoing stack args. |
1021 // : doubles : | | 883 // : doubles : | First few args in registers. |
1022 // | longs | | | 884 // | | | |
1023 // +--------------+ <--- SP' + 16*wordsize | 885 // +--------------+ <--- SP' + 16*wordsize |
1024 // | | | 886 // | | |
1025 // : window : | 887 // : window : |
1026 // | | | 888 // | | |
1027 // +--------------+ <--- SP' | 889 // +--------------+ <--- SP' |
1031 // FOR COMPILED CODE AND THE FRAME SLIGHTLY GROWN. | 893 // FOR COMPILED CODE AND THE FRAME SLIGHTLY GROWN. |
1032 | 894 |
1033 // Cut-out for having no stack args. Since up to 6 args are passed | 895 // Cut-out for having no stack args. Since up to 6 args are passed |
1034 // in registers, we will commonly have no stack args. | 896 // in registers, we will commonly have no stack args. |
1035 if (comp_args_on_stack > 0) { | 897 if (comp_args_on_stack > 0) { |
1036 | |
1037 // Convert VMReg stack slots to words. | 898 // Convert VMReg stack slots to words. |
1038 int comp_words_on_stack = round_to(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize)>>LogBytesPerWord; | 899 int comp_words_on_stack = round_to(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize)>>LogBytesPerWord; |
1039 // Round up to miminum stack alignment, in wordSize | 900 // Round up to miminum stack alignment, in wordSize |
1040 comp_words_on_stack = round_to(comp_words_on_stack, 2); | 901 comp_words_on_stack = round_to(comp_words_on_stack, 2); |
1041 // Now compute the distance from Lesp to SP. This calculation does not | 902 // Now compute the distance from Lesp to SP. This calculation does not |
1042 // include the space for total_args_passed because Lesp has not yet popped | 903 // include the space for total_args_passed because Lesp has not yet popped |
1043 // the arguments. | 904 // the arguments. |
1044 __ sub(SP, (comp_words_on_stack)*wordSize, SP); | 905 __ sub(SP, (comp_words_on_stack)*wordSize, SP); |
1045 } | 906 } |
1046 | 907 |
1047 // Will jump to the compiled code just as if compiled code was doing it. | |
1048 // Pre-load the register-jump target early, to schedule it better. | |
1049 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3); | |
1050 | |
1051 // Now generate the shuffle code. Pick up all register args and move the | 908 // Now generate the shuffle code. Pick up all register args and move the |
1052 // rest through G1_scratch. | 909 // rest through G1_scratch. |
1053 for (int i=0; i<total_args_passed; i++) { | 910 for (int i = 0; i < total_args_passed; i++) { |
1054 if (sig_bt[i] == T_VOID) { | 911 if (sig_bt[i] == T_VOID) { |
1055 // Longs and doubles are passed in native word order, but misaligned | 912 // Longs and doubles are passed in native word order, but misaligned |
1056 // in the 32-bit build. | 913 // in the 32-bit build. |
1057 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half"); | 914 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half"); |
1058 continue; | 915 continue; |
1086 // data is passed in only 1 slot. | 943 // data is passed in only 1 slot. |
1087 RegisterOrConstant slot = (sig_bt[i] == T_LONG) ? | 944 RegisterOrConstant slot = (sig_bt[i] == T_LONG) ? |
1088 next_arg_slot(ld_off) : arg_slot(ld_off); | 945 next_arg_slot(ld_off) : arg_slot(ld_off); |
1089 __ ldx(Gargs, slot, r); | 946 __ ldx(Gargs, slot, r); |
1090 #else | 947 #else |
1091 // Need to load a 64-bit value into G1/G4, but G1/G4 is being used in the | 948 fatal("longs should be on stack"); |
1092 // stack shuffle. Load the first 2 longs into G1/G4 later. | |
1093 #endif | 949 #endif |
1094 } | 950 } |
1095 } else { | 951 } else { |
1096 assert(r_1->is_FloatRegister(), ""); | 952 assert(r_1->is_FloatRegister(), ""); |
1097 if (!r_2->is_valid()) { | 953 if (!r_2->is_valid()) { |
1098 __ ldf(FloatRegisterImpl::S, Gargs, arg_slot(ld_off), r_1->as_FloatRegister()); | 954 __ ldf(FloatRegisterImpl::S, Gargs, arg_slot(ld_off), r_1->as_FloatRegister()); |
1099 } else { | 955 } else { |
1100 #ifdef _LP64 | 956 #ifdef _LP64 |
1101 // In V9, doubles are given 2 64-bit slots in the interpreter, but the | 957 // In V9, doubles are given 2 64-bit slots in the interpreter, but the |
1102 // data is passed in only 1 slot. This code also handles longs that | 958 // data is passed in only 1 slot. This code also handles longs that |
1103 // are passed on the stack, but need a stack-to-stack move through a | 959 // are passed on the stack, but need a stack-to-stack move through a |
1104 // spare float register. | 960 // spare float register. |
1105 RegisterOrConstant slot = (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) ? | 961 RegisterOrConstant slot = (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) ? |
1106 next_arg_slot(ld_off) : arg_slot(ld_off); | 962 next_arg_slot(ld_off) : arg_slot(ld_off); |
1107 __ ldf(FloatRegisterImpl::D, Gargs, slot, r_1->as_FloatRegister()); | 963 __ ldf(FloatRegisterImpl::D, Gargs, slot, r_1->as_FloatRegister()); |
1108 #else | 964 #else |
1109 // Need to marshal 64-bit value from misaligned Lesp loads | 965 // Need to marshal 64-bit value from misaligned Lesp loads |
1110 __ ldf(FloatRegisterImpl::S, Gargs, next_arg_slot(ld_off), r_1->as_FloatRegister()); | 966 __ ldf(FloatRegisterImpl::S, Gargs, next_arg_slot(ld_off), r_1->as_FloatRegister()); |
1111 __ ldf(FloatRegisterImpl::S, Gargs, arg_slot(ld_off), r_2->as_FloatRegister()); | 967 __ ldf(FloatRegisterImpl::S, Gargs, arg_slot(ld_off), r_2->as_FloatRegister()); |
1112 #endif | 968 #endif |
1113 } | 969 } |
1114 } | 970 } |
1115 // Was the argument really intended to be on the stack, but was loaded | 971 // Was the argument really intended to be on the stack, but was loaded |
1116 // into F8/F9? | 972 // into F8/F9? |
1122 RegisterOrConstant slot = __ ensure_simm13_or_reg(st_off, Rdisp); | 978 RegisterOrConstant slot = __ ensure_simm13_or_reg(st_off, Rdisp); |
1123 if (!r_2->is_valid()) __ stf(FloatRegisterImpl::S, r_1->as_FloatRegister(), SP, slot); | 979 if (!r_2->is_valid()) __ stf(FloatRegisterImpl::S, r_1->as_FloatRegister(), SP, slot); |
1124 else __ stf(FloatRegisterImpl::D, r_1->as_FloatRegister(), SP, slot); | 980 else __ stf(FloatRegisterImpl::D, r_1->as_FloatRegister(), SP, slot); |
1125 } | 981 } |
1126 } | 982 } |
1127 bool made_space = false; | |
1128 #ifndef _LP64 | |
1129 // May need to pick up a few long args in G1/G4 | |
1130 bool g4_crushed = false; | |
1131 bool g3_crushed = false; | |
1132 for (int i=0; i<total_args_passed; i++) { | |
1133 if (regs[i].first()->is_Register() && regs[i].second()->is_valid()) { | |
1134 // Load in argument order going down | |
1135 int ld_off = (total_args_passed-i)*Interpreter::stackElementSize; | |
1136 // Need to marshal 64-bit value from misaligned Lesp loads | |
1137 Register r = regs[i].first()->as_Register()->after_restore(); | |
1138 if (r == G1 || r == G4) { | |
1139 assert(!g4_crushed, "ordering problem"); | |
1140 if (r == G4){ | |
1141 g4_crushed = true; | |
1142 __ lduw(Gargs, arg_slot(ld_off) , G3_scratch); // Load lo bits | |
1143 __ ld (Gargs, next_arg_slot(ld_off), r); // Load hi bits | |
1144 } else { | |
1145 // better schedule this way | |
1146 __ ld (Gargs, next_arg_slot(ld_off), r); // Load hi bits | |
1147 __ lduw(Gargs, arg_slot(ld_off) , G3_scratch); // Load lo bits | |
1148 } | |
1149 g3_crushed = true; | |
1150 __ sllx(r, 32, r); | |
1151 __ or3(G3_scratch, r, r); | |
1152 } else { | |
1153 assert(r->is_out(), "longs passed in two O registers"); | |
1154 __ ld (Gargs, arg_slot(ld_off) , r->successor()); // Load lo bits | |
1155 __ ld (Gargs, next_arg_slot(ld_off), r); // Load hi bits | |
1156 } | |
1157 } | |
1158 } | |
1159 #endif | |
1160 | 983 |
1161 // Jump to the compiled code just as if compiled code was doing it. | 984 // Jump to the compiled code just as if compiled code was doing it. |
1162 // | 985 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3); |
1163 #ifndef _LP64 | 986 |
1164 if (g3_crushed) { | 987 // 6243940 We might end up in handle_wrong_method if |
1165 // Rats load was wasted, at least it is in cache... | 988 // the callee is deoptimized as we race thru here. If that |
1166 __ ld_ptr(G5_method, Method::from_compiled_offset(), G3); | 989 // happens we don't want to take a safepoint because the |
1167 } | 990 // caller frame will look interpreted and arguments are now |
1168 #endif /* _LP64 */ | 991 // "compiled" so it is much better to make this transition |
1169 | 992 // invisible to the stack walking code. Unfortunately if |
1170 // 6243940 We might end up in handle_wrong_method if | 993 // we try and find the callee by normal means a safepoint |
1171 // the callee is deoptimized as we race thru here. If that | 994 // is possible. So we stash the desired callee in the thread |
1172 // happens we don't want to take a safepoint because the | 995 // and the vm will find there should this case occur. |
1173 // caller frame will look interpreted and arguments are now | 996 Address callee_target_addr(G2_thread, JavaThread::callee_target_offset()); |
1174 // "compiled" so it is much better to make this transition | 997 __ st_ptr(G5_method, callee_target_addr); |
1175 // invisible to the stack walking code. Unfortunately if | 998 |
1176 // we try and find the callee by normal means a safepoint | 999 if (StressNonEntrant) { |
1177 // is possible. So we stash the desired callee in the thread | 1000 // Open a big window for deopt failure |
1178 // and the vm will find there should this case occur. | 1001 __ save_frame(0); |
1179 Address callee_target_addr(G2_thread, JavaThread::callee_target_offset()); | 1002 __ mov(G0, L0); |
1180 __ st_ptr(G5_method, callee_target_addr); | 1003 Label loop; |
1181 | 1004 __ bind(loop); |
1182 if (StressNonEntrant) { | 1005 __ sub(L0, 1, L0); |
1183 // Open a big window for deopt failure | 1006 __ br_null_short(L0, Assembler::pt, loop); |
1184 __ save_frame(0); | 1007 __ restore(); |
1185 __ mov(G0, L0); | 1008 } |
1186 Label loop; | 1009 |
1187 __ bind(loop); | 1010 __ jmpl(G3, 0, G0); |
1188 __ sub(L0, 1, L0); | 1011 __ delayed()->nop(); |
1189 __ br_null_short(L0, Assembler::pt, loop); | |
1190 | |
1191 __ restore(); | |
1192 } | |
1193 | |
1194 | |
1195 __ jmpl(G3, 0, G0); | |
1196 __ delayed()->nop(); | |
1197 } | 1012 } |
1198 | 1013 |
1199 // --------------------------------------------------------------- | 1014 // --------------------------------------------------------------- |
1200 AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm, | 1015 AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm, |
1201 int total_args_passed, | 1016 int total_args_passed, |
1219 // finally end in a jump to the generic interpreter entry point. On exit | 1034 // finally end in a jump to the generic interpreter entry point. On exit |
1220 // from the interpreter, the interpreter will restore our SP (lest the | 1035 // from the interpreter, the interpreter will restore our SP (lest the |
1221 // compiled code, which relys solely on SP and not FP, get sick). | 1036 // compiled code, which relys solely on SP and not FP, get sick). |
1222 | 1037 |
1223 address c2i_unverified_entry = __ pc(); | 1038 address c2i_unverified_entry = __ pc(); |
1224 Label skip_fixup; | 1039 Label L_skip_fixup; |
1225 { | 1040 { |
1226 #if !defined(_LP64) && defined(COMPILER2) | 1041 Register R_temp = G1; // another scratch register |
1227 Register R_temp = L0; // another scratch register | |
1228 #else | |
1229 Register R_temp = G1; // another scratch register | |
1230 #endif | |
1231 | 1042 |
1232 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub()); | 1043 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub()); |
1233 | 1044 |
1234 __ verify_oop(O0); | 1045 __ verify_oop(O0); |
1235 __ load_klass(O0, G3_scratch); | 1046 __ load_klass(O0, G3_scratch); |
1236 | 1047 |
1237 #if !defined(_LP64) && defined(COMPILER2) | |
1238 __ save(SP, -frame::register_save_words*wordSize, SP); | |
1239 __ ld_ptr(G5_method, CompiledICHolder::holder_klass_offset(), R_temp); | 1048 __ ld_ptr(G5_method, CompiledICHolder::holder_klass_offset(), R_temp); |
1240 __ cmp(G3_scratch, R_temp); | 1049 __ cmp(G3_scratch, R_temp); |
1241 __ restore(); | |
1242 #else | |
1243 __ ld_ptr(G5_method, CompiledICHolder::holder_klass_offset(), R_temp); | |
1244 __ cmp(G3_scratch, R_temp); | |
1245 #endif | |
1246 | 1050 |
1247 Label ok, ok2; | 1051 Label ok, ok2; |
1248 __ brx(Assembler::equal, false, Assembler::pt, ok); | 1052 __ brx(Assembler::equal, false, Assembler::pt, ok); |
1249 __ delayed()->ld_ptr(G5_method, CompiledICHolder::holder_method_offset(), G5_method); | 1053 __ delayed()->ld_ptr(G5_method, CompiledICHolder::holder_method_offset(), G5_method); |
1250 __ jump_to(ic_miss, G3_scratch); | 1054 __ jump_to(ic_miss, G3_scratch); |
1254 // Method might have been compiled since the call site was patched to | 1058 // Method might have been compiled since the call site was patched to |
1255 // interpreted if that is the case treat it as a miss so we can get | 1059 // interpreted if that is the case treat it as a miss so we can get |
1256 // the call site corrected. | 1060 // the call site corrected. |
1257 __ ld_ptr(G5_method, in_bytes(Method::code_offset()), G3_scratch); | 1061 __ ld_ptr(G5_method, in_bytes(Method::code_offset()), G3_scratch); |
1258 __ bind(ok2); | 1062 __ bind(ok2); |
1259 __ br_null(G3_scratch, false, Assembler::pt, skip_fixup); | 1063 __ br_null(G3_scratch, false, Assembler::pt, L_skip_fixup); |
1260 __ delayed()->ld_ptr(G5_method, in_bytes(Method::interpreter_entry_offset()), G3_scratch); | 1064 __ delayed()->nop(); |
1261 __ jump_to(ic_miss, G3_scratch); | 1065 __ jump_to(ic_miss, G3_scratch); |
1262 __ delayed()->nop(); | 1066 __ delayed()->nop(); |
1263 | 1067 |
1264 } | 1068 } |
1265 | 1069 |
1266 address c2i_entry = __ pc(); | 1070 address c2i_entry = __ pc(); |
1267 | 1071 |
1268 agen.gen_c2i_adapter(total_args_passed, comp_args_on_stack, sig_bt, regs, skip_fixup); | 1072 agen.gen_c2i_adapter(total_args_passed, comp_args_on_stack, sig_bt, regs, L_skip_fixup); |
1269 | 1073 |
1270 __ flush(); | 1074 __ flush(); |
1271 return AdapterHandlerLibrary::new_entry(fingerprint, i2c_entry, c2i_entry, c2i_unverified_entry); | 1075 return AdapterHandlerLibrary::new_entry(fingerprint, i2c_entry, c2i_entry, c2i_unverified_entry); |
1272 | 1076 |
1273 } | 1077 } |
1983 move32_64(masm, reg64_to_VMRegPair(G0), length_arg); | 1787 move32_64(masm, reg64_to_VMRegPair(G0), length_arg); |
1984 __ bind(done); | 1788 __ bind(done); |
1985 } | 1789 } |
1986 | 1790 |
1987 static void verify_oop_args(MacroAssembler* masm, | 1791 static void verify_oop_args(MacroAssembler* masm, |
1988 int total_args_passed, | 1792 methodHandle method, |
1989 const BasicType* sig_bt, | 1793 const BasicType* sig_bt, |
1990 const VMRegPair* regs) { | 1794 const VMRegPair* regs) { |
1991 Register temp_reg = G5_method; // not part of any compiled calling seq | 1795 Register temp_reg = G5_method; // not part of any compiled calling seq |
1992 if (VerifyOops) { | 1796 if (VerifyOops) { |
1993 for (int i = 0; i < total_args_passed; i++) { | 1797 for (int i = 0; i < method->size_of_parameters(); i++) { |
1994 if (sig_bt[i] == T_OBJECT || | 1798 if (sig_bt[i] == T_OBJECT || |
1995 sig_bt[i] == T_ARRAY) { | 1799 sig_bt[i] == T_ARRAY) { |
1996 VMReg r = regs[i].first(); | 1800 VMReg r = regs[i].first(); |
1997 assert(r->is_valid(), "bad oop arg"); | 1801 assert(r->is_valid(), "bad oop arg"); |
1998 if (r->is_stack()) { | 1802 if (r->is_stack()) { |
2007 } | 1811 } |
2008 } | 1812 } |
2009 } | 1813 } |
2010 | 1814 |
2011 static void gen_special_dispatch(MacroAssembler* masm, | 1815 static void gen_special_dispatch(MacroAssembler* masm, |
2012 int total_args_passed, | 1816 methodHandle method, |
2013 int comp_args_on_stack, | |
2014 vmIntrinsics::ID special_dispatch, | |
2015 const BasicType* sig_bt, | 1817 const BasicType* sig_bt, |
2016 const VMRegPair* regs) { | 1818 const VMRegPair* regs) { |
2017 verify_oop_args(masm, total_args_passed, sig_bt, regs); | 1819 verify_oop_args(masm, method, sig_bt, regs); |
1820 vmIntrinsics::ID iid = method->intrinsic_id(); | |
2018 | 1821 |
2019 // Now write the args into the outgoing interpreter space | 1822 // Now write the args into the outgoing interpreter space |
2020 bool has_receiver = false; | 1823 bool has_receiver = false; |
2021 Register receiver_reg = noreg; | 1824 Register receiver_reg = noreg; |
2022 int member_arg_pos = -1; | 1825 int member_arg_pos = -1; |
2023 Register member_reg = noreg; | 1826 Register member_reg = noreg; |
2024 int ref_kind = MethodHandles::signature_polymorphic_intrinsic_ref_kind(special_dispatch); | 1827 int ref_kind = MethodHandles::signature_polymorphic_intrinsic_ref_kind(iid); |
2025 if (ref_kind != 0) { | 1828 if (ref_kind != 0) { |
2026 member_arg_pos = total_args_passed - 1; // trailing MemberName argument | 1829 member_arg_pos = method->size_of_parameters() - 1; // trailing MemberName argument |
2027 member_reg = G5_method; // known to be free at this point | 1830 member_reg = G5_method; // known to be free at this point |
2028 has_receiver = MethodHandles::ref_kind_has_receiver(ref_kind); | 1831 has_receiver = MethodHandles::ref_kind_has_receiver(ref_kind); |
2029 } else if (special_dispatch == vmIntrinsics::_invokeBasic) { | 1832 } else if (iid == vmIntrinsics::_invokeBasic) { |
2030 has_receiver = true; | 1833 has_receiver = true; |
2031 } else { | 1834 } else { |
2032 fatal(err_msg("special_dispatch=%d", special_dispatch)); | 1835 fatal(err_msg_res("unexpected intrinsic id %d", iid)); |
2033 } | 1836 } |
2034 | 1837 |
2035 if (member_reg != noreg) { | 1838 if (member_reg != noreg) { |
2036 // Load the member_arg into register, if necessary. | 1839 // Load the member_arg into register, if necessary. |
2037 assert(member_arg_pos >= 0 && member_arg_pos < total_args_passed, "oob"); | 1840 SharedRuntime::check_member_name_argument_is_last_argument(method, sig_bt, regs); |
2038 assert(sig_bt[member_arg_pos] == T_OBJECT, "dispatch argument must be an object"); | |
2039 VMReg r = regs[member_arg_pos].first(); | 1841 VMReg r = regs[member_arg_pos].first(); |
2040 assert(r->is_valid(), "bad member arg"); | |
2041 if (r->is_stack()) { | 1842 if (r->is_stack()) { |
2042 RegisterOrConstant ld_off = reg2offset(r) + STACK_BIAS; | 1843 RegisterOrConstant ld_off = reg2offset(r) + STACK_BIAS; |
2043 ld_off = __ ensure_simm13_or_reg(ld_off, member_reg); | 1844 ld_off = __ ensure_simm13_or_reg(ld_off, member_reg); |
2044 __ ld_ptr(SP, ld_off, member_reg); | 1845 __ ld_ptr(SP, ld_off, member_reg); |
2045 } else { | 1846 } else { |
2048 } | 1849 } |
2049 } | 1850 } |
2050 | 1851 |
2051 if (has_receiver) { | 1852 if (has_receiver) { |
2052 // Make sure the receiver is loaded into a register. | 1853 // Make sure the receiver is loaded into a register. |
2053 assert(total_args_passed > 0, "oob"); | 1854 assert(method->size_of_parameters() > 0, "oob"); |
2054 assert(sig_bt[0] == T_OBJECT, "receiver argument must be an object"); | 1855 assert(sig_bt[0] == T_OBJECT, "receiver argument must be an object"); |
2055 VMReg r = regs[0].first(); | 1856 VMReg r = regs[0].first(); |
2056 assert(r->is_valid(), "bad receiver arg"); | 1857 assert(r->is_valid(), "bad receiver arg"); |
2057 if (r->is_stack()) { | 1858 if (r->is_stack()) { |
2058 // Porting note: This assumes that compiled calling conventions always | 1859 // Porting note: This assumes that compiled calling conventions always |
2059 // pass the receiver oop in a register. If this is not true on some | 1860 // pass the receiver oop in a register. If this is not true on some |
2060 // platform, pick a temp and load the receiver from stack. | 1861 // platform, pick a temp and load the receiver from stack. |
2061 assert(false, "receiver always in a register"); | 1862 fatal("receiver always in a register"); |
2062 receiver_reg = G3_scratch; // known to be free at this point | 1863 receiver_reg = G3_scratch; // known to be free at this point |
2063 RegisterOrConstant ld_off = reg2offset(r) + STACK_BIAS; | 1864 RegisterOrConstant ld_off = reg2offset(r) + STACK_BIAS; |
2064 ld_off = __ ensure_simm13_or_reg(ld_off, member_reg); | 1865 ld_off = __ ensure_simm13_or_reg(ld_off, member_reg); |
2065 __ ld_ptr(SP, ld_off, receiver_reg); | 1866 __ ld_ptr(SP, ld_off, receiver_reg); |
2066 } else { | 1867 } else { |
2068 receiver_reg = r->as_Register(); | 1869 receiver_reg = r->as_Register(); |
2069 } | 1870 } |
2070 } | 1871 } |
2071 | 1872 |
2072 // Figure out which address we are really jumping to: | 1873 // Figure out which address we are really jumping to: |
2073 MethodHandles::generate_method_handle_dispatch(masm, special_dispatch, | 1874 MethodHandles::generate_method_handle_dispatch(masm, iid, |
2074 receiver_reg, member_reg, /*for_compiler_entry:*/ true); | 1875 receiver_reg, member_reg, /*for_compiler_entry:*/ true); |
2075 } | 1876 } |
2076 | 1877 |
2077 // --------------------------------------------------------------------------- | 1878 // --------------------------------------------------------------------------- |
2078 // Generate a native wrapper for a given method. The method takes arguments | 1879 // Generate a native wrapper for a given method. The method takes arguments |
2101 // call into JVM and possible unlock the JNI critical | 1902 // call into JVM and possible unlock the JNI critical |
2102 // if a GC was suppressed while in the critical native. | 1903 // if a GC was suppressed while in the critical native. |
2103 // transition back to thread_in_Java | 1904 // transition back to thread_in_Java |
2104 // return to caller | 1905 // return to caller |
2105 // | 1906 // |
2106 nmethod *SharedRuntime::generate_native_wrapper(MacroAssembler* masm, | 1907 nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm, |
2107 methodHandle method, | 1908 methodHandle method, |
2108 int compile_id, | 1909 int compile_id, |
2109 int total_in_args, | |
2110 int comp_args_on_stack, // in VMRegStackSlots | |
2111 BasicType* in_sig_bt, | 1910 BasicType* in_sig_bt, |
2112 VMRegPair* in_regs, | 1911 VMRegPair* in_regs, |
2113 BasicType ret_type) { | 1912 BasicType ret_type) { |
2114 if (method->is_method_handle_intrinsic()) { | 1913 if (method->is_method_handle_intrinsic()) { |
2115 vmIntrinsics::ID iid = method->intrinsic_id(); | 1914 vmIntrinsics::ID iid = method->intrinsic_id(); |
2116 intptr_t start = (intptr_t)__ pc(); | 1915 intptr_t start = (intptr_t)__ pc(); |
2117 int vep_offset = ((intptr_t)__ pc()) - start; | 1916 int vep_offset = ((intptr_t)__ pc()) - start; |
2118 gen_special_dispatch(masm, | 1917 gen_special_dispatch(masm, |
2119 total_in_args, | 1918 method, |
2120 comp_args_on_stack, | |
2121 method->intrinsic_id(), | |
2122 in_sig_bt, | 1919 in_sig_bt, |
2123 in_regs); | 1920 in_regs); |
2124 int frame_complete = ((intptr_t)__ pc()) - start; // not complete, period | 1921 int frame_complete = ((intptr_t)__ pc()) - start; // not complete, period |
2125 __ flush(); | 1922 __ flush(); |
2126 int stack_slots = SharedRuntime::out_preserve_stack_slots(); // no out slots at all, actually | 1923 int stack_slots = SharedRuntime::out_preserve_stack_slots(); // no out slots at all, actually |
2218 // on entry to the wrapper. We need to convert these args to where | 2015 // on entry to the wrapper. We need to convert these args to where |
2219 // the jni function will expect them. To figure out where they go | 2016 // the jni function will expect them. To figure out where they go |
2220 // we convert the java signature to a C signature by inserting | 2017 // we convert the java signature to a C signature by inserting |
2221 // the hidden arguments as arg[0] and possibly arg[1] (static method) | 2018 // the hidden arguments as arg[0] and possibly arg[1] (static method) |
2222 | 2019 |
2020 const int total_in_args = method->size_of_parameters(); | |
2223 int total_c_args = total_in_args; | 2021 int total_c_args = total_in_args; |
2224 int total_save_slots = 6 * VMRegImpl::slots_per_word; | 2022 int total_save_slots = 6 * VMRegImpl::slots_per_word; |
2225 if (!is_critical_native) { | 2023 if (!is_critical_native) { |
2226 total_c_args += 1; | 2024 total_c_args += 1; |
2227 if (method->is_static()) { | 2025 if (method->is_static()) { |