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comparison src/cpu/x86/vm/assembler_x86.cpp @ 624:337400e7a5dd

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6797305: Add LoadUB and LoadUI opcode class Summary: Add a LoadUB (unsigned byte) and LoadUI (unsigned int) opcode class so we have these load optimizations in the first place and do not need to handle them in the matcher. Reviewed-by: never, kvn
author twisti
date Mon, 09 Mar 2009 03:17:11 -0700
parents 9adddb8c0fc8
children 7bb995fbd3c0 660978a2a31a
comparison
equal deleted inserted replaced
623:9adddb8c0fc8 624:337400e7a5dd
1 /* 1 /*
2 * Copyright 1997-2008 Sun Microsystems, Inc. All Rights Reserved. 2 * Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 * 4 *
5 * This code is free software; you can redistribute it and/or modify it 5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as 6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation. 7 * published by the Free Software Foundation.
127 127
128 128
129 // Convert the raw encoding form into the form expected by the constructor for 129 // Convert the raw encoding form into the form expected by the constructor for
130 // Address. An index of 4 (rsp) corresponds to having no index, so convert 130 // Address. An index of 4 (rsp) corresponds to having no index, so convert
131 // that to noreg for the Address constructor. 131 // that to noreg for the Address constructor.
132 Address Address::make_raw(int base, int index, int scale, int disp) { 132 Address Address::make_raw(int base, int index, int scale, int disp, bool disp_is_oop) {
133 RelocationHolder rspec;
134 if (disp_is_oop) {
135 rspec = Relocation::spec_simple(relocInfo::oop_type);
136 }
133 bool valid_index = index != rsp->encoding(); 137 bool valid_index = index != rsp->encoding();
134 if (valid_index) { 138 if (valid_index) {
135 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp)); 139 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
140 madr._rspec = rspec;
136 return madr; 141 return madr;
137 } else { 142 } else {
138 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp)); 143 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
144 madr._rspec = rspec;
139 return madr; 145 return madr;
140 } 146 }
141 } 147 }
142 148
143 // Implementation of Assembler 149 // Implementation of Assembler
3890 prefixq(dst, src); 3896 prefixq(dst, src);
3891 emit_byte(0x89); 3897 emit_byte(0x89);
3892 emit_operand(src, dst); 3898 emit_operand(src, dst);
3893 } 3899 }
3894 3900
3901 void Assembler::movsbq(Register dst, Address src) {
3902 InstructionMark im(this);
3903 prefixq(src, dst);
3904 emit_byte(0x0F);
3905 emit_byte(0xBE);
3906 emit_operand(dst, src);
3907 }
3908
3909 void Assembler::movsbq(Register dst, Register src) {
3910 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3911 emit_byte(0x0F);
3912 emit_byte(0xBE);
3913 emit_byte(0xC0 | encode);
3914 }
3915
3895 void Assembler::movslq(Register dst, int32_t imm32) { 3916 void Assembler::movslq(Register dst, int32_t imm32) {
3896 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx) 3917 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
3897 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx) 3918 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
3898 // as a result we shouldn't use until tested at runtime... 3919 // as a result we shouldn't use until tested at runtime...
3899 ShouldNotReachHere(); 3920 ShouldNotReachHere();
3920 } 3941 }
3921 3942
3922 void Assembler::movslq(Register dst, Register src) { 3943 void Assembler::movslq(Register dst, Register src) {
3923 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 3944 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3924 emit_byte(0x63); 3945 emit_byte(0x63);
3946 emit_byte(0xC0 | encode);
3947 }
3948
3949 void Assembler::movswq(Register dst, Address src) {
3950 InstructionMark im(this);
3951 prefixq(src, dst);
3952 emit_byte(0x0F);
3953 emit_byte(0xBF);
3954 emit_operand(dst, src);
3955 }
3956
3957 void Assembler::movswq(Register dst, Register src) {
3958 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3959 emit_byte(0x0F);
3960 emit_byte(0xBF);
3961 emit_byte(0xC0 | encode);
3962 }
3963
3964 void Assembler::movzbq(Register dst, Address src) {
3965 InstructionMark im(this);
3966 prefixq(src, dst);
3967 emit_byte(0x0F);
3968 emit_byte(0xB6);
3969 emit_operand(dst, src);
3970 }
3971
3972 void Assembler::movzbq(Register dst, Register src) {
3973 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3974 emit_byte(0x0F);
3975 emit_byte(0xB6);
3976 emit_byte(0xC0 | encode);
3977 }
3978
3979 void Assembler::movzwq(Register dst, Address src) {
3980 InstructionMark im(this);
3981 prefixq(src, dst);
3982 emit_byte(0x0F);
3983 emit_byte(0xB7);
3984 emit_operand(dst, src);
3985 }
3986
3987 void Assembler::movzwq(Register dst, Register src) {
3988 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3989 emit_byte(0x0F);
3990 emit_byte(0xB7);
3925 emit_byte(0xC0 | encode); 3991 emit_byte(0xC0 | encode);
3926 } 3992 }
3927 3993
3928 void Assembler::negq(Register dst) { 3994 void Assembler::negq(Register dst) {
3929 int encode = prefixq_and_encode(dst->encoding()); 3995 int encode = prefixq_and_encode(dst->encoding());