Mercurial > hg > truffle
annotate src/cpu/x86/vm/assembler_x86.cpp @ 624:337400e7a5dd
6797305: Add LoadUB and LoadUI opcode class
Summary: Add a LoadUB (unsigned byte) and LoadUI (unsigned int) opcode class so we have these load optimizations in the first place and do not need to handle them in the matcher.
Reviewed-by: never, kvn
| author | twisti |
|---|---|
| date | Mon, 09 Mar 2009 03:17:11 -0700 |
| parents | 9adddb8c0fc8 |
| children | 7bb995fbd3c0 660978a2a31a |
| rev | line source |
|---|---|
| 0 | 1 /* |
| 624 | 2 * Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved. |
| 0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
| 19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 20 * CA 95054 USA or visit www.sun.com if you need additional information or | |
| 21 * have any questions. | |
| 22 * | |
| 23 */ | |
| 24 | |
| 25 #include "incls/_precompiled.incl" | |
| 304 | 26 #include "incls/_assembler_x86.cpp.incl" |
| 0 | 27 |
| 28 // Implementation of AddressLiteral | |
| 29 | |
| 30 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) { | |
| 31 _is_lval = false; | |
| 32 _target = target; | |
| 33 switch (rtype) { | |
| 34 case relocInfo::oop_type: | |
| 35 // Oops are a special case. Normally they would be their own section | |
| 36 // but in cases like icBuffer they are literals in the code stream that | |
| 37 // we don't have a section for. We use none so that we get a literal address | |
| 38 // which is always patchable. | |
| 39 break; | |
| 40 case relocInfo::external_word_type: | |
| 41 _rspec = external_word_Relocation::spec(target); | |
| 42 break; | |
| 43 case relocInfo::internal_word_type: | |
| 44 _rspec = internal_word_Relocation::spec(target); | |
| 45 break; | |
| 46 case relocInfo::opt_virtual_call_type: | |
| 47 _rspec = opt_virtual_call_Relocation::spec(); | |
| 48 break; | |
| 49 case relocInfo::static_call_type: | |
| 50 _rspec = static_call_Relocation::spec(); | |
| 51 break; | |
| 52 case relocInfo::runtime_call_type: | |
| 53 _rspec = runtime_call_Relocation::spec(); | |
| 54 break; | |
| 55 case relocInfo::poll_type: | |
| 56 case relocInfo::poll_return_type: | |
| 57 _rspec = Relocation::spec_simple(rtype); | |
| 58 break; | |
| 59 case relocInfo::none: | |
| 60 break; | |
| 61 default: | |
| 62 ShouldNotReachHere(); | |
| 63 break; | |
| 64 } | |
| 65 } | |
| 66 | |
| 67 // Implementation of Address | |
| 68 | |
| 304 | 69 #ifdef _LP64 |
| 70 | |
| 0 | 71 Address Address::make_array(ArrayAddress adr) { |
| 72 // Not implementable on 64bit machines | |
| 73 // Should have been handled higher up the call chain. | |
| 74 ShouldNotReachHere(); | |
| 304 | 75 return Address(); |
| 76 } | |
| 77 | |
| 78 // exceedingly dangerous constructor | |
| 79 Address::Address(int disp, address loc, relocInfo::relocType rtype) { | |
| 80 _base = noreg; | |
| 81 _index = noreg; | |
| 82 _scale = no_scale; | |
| 83 _disp = disp; | |
| 84 switch (rtype) { | |
| 85 case relocInfo::external_word_type: | |
| 86 _rspec = external_word_Relocation::spec(loc); | |
| 87 break; | |
| 88 case relocInfo::internal_word_type: | |
| 89 _rspec = internal_word_Relocation::spec(loc); | |
| 90 break; | |
| 91 case relocInfo::runtime_call_type: | |
| 92 // HMM | |
| 93 _rspec = runtime_call_Relocation::spec(); | |
| 94 break; | |
| 95 case relocInfo::poll_type: | |
| 96 case relocInfo::poll_return_type: | |
| 97 _rspec = Relocation::spec_simple(rtype); | |
| 98 break; | |
| 99 case relocInfo::none: | |
| 100 break; | |
| 101 default: | |
| 102 ShouldNotReachHere(); | |
| 103 } | |
| 104 } | |
| 105 #else // LP64 | |
| 106 | |
| 107 Address Address::make_array(ArrayAddress adr) { | |
| 0 | 108 AddressLiteral base = adr.base(); |
| 109 Address index = adr.index(); | |
| 110 assert(index._disp == 0, "must not have disp"); // maybe it can? | |
| 111 Address array(index._base, index._index, index._scale, (intptr_t) base.target()); | |
| 112 array._rspec = base._rspec; | |
| 113 return array; | |
| 304 | 114 } |
| 0 | 115 |
| 116 // exceedingly dangerous constructor | |
| 117 Address::Address(address loc, RelocationHolder spec) { | |
| 118 _base = noreg; | |
| 119 _index = noreg; | |
| 120 _scale = no_scale; | |
| 121 _disp = (intptr_t) loc; | |
| 122 _rspec = spec; | |
| 123 } | |
| 304 | 124 |
| 0 | 125 #endif // _LP64 |
| 126 | |
| 304 | 127 |
| 128 | |
| 0 | 129 // Convert the raw encoding form into the form expected by the constructor for |
| 130 // Address. An index of 4 (rsp) corresponds to having no index, so convert | |
| 131 // that to noreg for the Address constructor. | |
| 624 | 132 Address Address::make_raw(int base, int index, int scale, int disp, bool disp_is_oop) { |
| 133 RelocationHolder rspec; | |
| 134 if (disp_is_oop) { | |
| 135 rspec = Relocation::spec_simple(relocInfo::oop_type); | |
| 136 } | |
| 0 | 137 bool valid_index = index != rsp->encoding(); |
| 138 if (valid_index) { | |
| 139 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp)); | |
| 624 | 140 madr._rspec = rspec; |
| 0 | 141 return madr; |
| 142 } else { | |
| 143 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp)); | |
| 624 | 144 madr._rspec = rspec; |
| 0 | 145 return madr; |
| 146 } | |
| 147 } | |
| 148 | |
| 149 // Implementation of Assembler | |
| 150 | |
| 151 int AbstractAssembler::code_fill_byte() { | |
| 152 return (u_char)'\xF4'; // hlt | |
| 153 } | |
| 154 | |
| 155 // make this go away someday | |
| 156 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) { | |
| 157 if (rtype == relocInfo::none) | |
| 158 emit_long(data); | |
| 159 else emit_data(data, Relocation::spec_simple(rtype), format); | |
| 160 } | |
| 161 | |
| 162 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) { | |
| 304 | 163 assert(imm_operand == 0, "default format must be immediate in this file"); |
| 0 | 164 assert(inst_mark() != NULL, "must be inside InstructionMark"); |
| 165 if (rspec.type() != relocInfo::none) { | |
| 166 #ifdef ASSERT | |
| 167 check_relocation(rspec, format); | |
| 168 #endif | |
| 169 // Do not use AbstractAssembler::relocate, which is not intended for | |
| 170 // embedded words. Instead, relocate to the enclosing instruction. | |
| 171 | |
| 172 // hack. call32 is too wide for mask so use disp32 | |
| 173 if (format == call32_operand) | |
| 174 code_section()->relocate(inst_mark(), rspec, disp32_operand); | |
| 175 else | |
| 176 code_section()->relocate(inst_mark(), rspec, format); | |
| 177 } | |
| 178 emit_long(data); | |
| 179 } | |
| 180 | |
| 304 | 181 static int encode(Register r) { |
| 182 int enc = r->encoding(); | |
| 183 if (enc >= 8) { | |
| 184 enc -= 8; | |
| 185 } | |
| 186 return enc; | |
| 187 } | |
| 188 | |
| 189 static int encode(XMMRegister r) { | |
| 190 int enc = r->encoding(); | |
| 191 if (enc >= 8) { | |
| 192 enc -= 8; | |
| 193 } | |
| 194 return enc; | |
| 195 } | |
| 0 | 196 |
| 197 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) { | |
| 198 assert(dst->has_byte_register(), "must have byte register"); | |
| 199 assert(isByte(op1) && isByte(op2), "wrong opcode"); | |
| 200 assert(isByte(imm8), "not a byte"); | |
| 201 assert((op1 & 0x01) == 0, "should be 8bit operation"); | |
| 202 emit_byte(op1); | |
| 304 | 203 emit_byte(op2 | encode(dst)); |
| 0 | 204 emit_byte(imm8); |
| 205 } | |
| 206 | |
| 207 | |
| 304 | 208 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) { |
| 0 | 209 assert(isByte(op1) && isByte(op2), "wrong opcode"); |
| 210 assert((op1 & 0x01) == 1, "should be 32bit operation"); | |
| 211 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); | |
| 212 if (is8bit(imm32)) { | |
| 213 emit_byte(op1 | 0x02); // set sign bit | |
| 304 | 214 emit_byte(op2 | encode(dst)); |
| 0 | 215 emit_byte(imm32 & 0xFF); |
| 216 } else { | |
| 217 emit_byte(op1); | |
| 304 | 218 emit_byte(op2 | encode(dst)); |
| 0 | 219 emit_long(imm32); |
| 220 } | |
| 221 } | |
| 222 | |
| 223 // immediate-to-memory forms | |
| 304 | 224 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) { |
| 0 | 225 assert((op1 & 0x01) == 1, "should be 32bit operation"); |
| 226 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); | |
| 227 if (is8bit(imm32)) { | |
| 228 emit_byte(op1 | 0x02); // set sign bit | |
| 304 | 229 emit_operand(rm, adr, 1); |
| 0 | 230 emit_byte(imm32 & 0xFF); |
| 231 } else { | |
| 232 emit_byte(op1); | |
| 304 | 233 emit_operand(rm, adr, 4); |
| 0 | 234 emit_long(imm32); |
| 235 } | |
| 236 } | |
| 237 | |
| 238 void Assembler::emit_arith(int op1, int op2, Register dst, jobject obj) { | |
| 304 | 239 LP64_ONLY(ShouldNotReachHere()); |
| 0 | 240 assert(isByte(op1) && isByte(op2), "wrong opcode"); |
| 241 assert((op1 & 0x01) == 1, "should be 32bit operation"); | |
| 242 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); | |
| 243 InstructionMark im(this); | |
| 244 emit_byte(op1); | |
| 304 | 245 emit_byte(op2 | encode(dst)); |
| 246 emit_data((intptr_t)obj, relocInfo::oop_type, 0); | |
| 0 | 247 } |
| 248 | |
| 249 | |
| 250 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) { | |
| 251 assert(isByte(op1) && isByte(op2), "wrong opcode"); | |
| 252 emit_byte(op1); | |
| 304 | 253 emit_byte(op2 | encode(dst) << 3 | encode(src)); |
| 254 } | |
| 255 | |
| 256 | |
| 257 void Assembler::emit_operand(Register reg, Register base, Register index, | |
| 258 Address::ScaleFactor scale, int disp, | |
| 259 RelocationHolder const& rspec, | |
| 260 int rip_relative_correction) { | |
| 0 | 261 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type(); |
| 304 | 262 |
| 263 // Encode the registers as needed in the fields they are used in | |
| 264 | |
| 265 int regenc = encode(reg) << 3; | |
| 266 int indexenc = index->is_valid() ? encode(index) << 3 : 0; | |
| 267 int baseenc = base->is_valid() ? encode(base) : 0; | |
| 268 | |
| 0 | 269 if (base->is_valid()) { |
| 270 if (index->is_valid()) { | |
| 271 assert(scale != Address::no_scale, "inconsistent address"); | |
| 272 // [base + index*scale + disp] | |
| 304 | 273 if (disp == 0 && rtype == relocInfo::none && |
| 274 base != rbp LP64_ONLY(&& base != r13)) { | |
| 0 | 275 // [base + index*scale] |
| 276 // [00 reg 100][ss index base] | |
| 277 assert(index != rsp, "illegal addressing mode"); | |
| 304 | 278 emit_byte(0x04 | regenc); |
| 279 emit_byte(scale << 6 | indexenc | baseenc); | |
| 0 | 280 } else if (is8bit(disp) && rtype == relocInfo::none) { |
| 281 // [base + index*scale + imm8] | |
| 282 // [01 reg 100][ss index base] imm8 | |
| 283 assert(index != rsp, "illegal addressing mode"); | |
| 304 | 284 emit_byte(0x44 | regenc); |
| 285 emit_byte(scale << 6 | indexenc | baseenc); | |
| 0 | 286 emit_byte(disp & 0xFF); |
| 287 } else { | |
| 304 | 288 // [base + index*scale + disp32] |
| 289 // [10 reg 100][ss index base] disp32 | |
| 0 | 290 assert(index != rsp, "illegal addressing mode"); |
| 304 | 291 emit_byte(0x84 | regenc); |
| 292 emit_byte(scale << 6 | indexenc | baseenc); | |
| 0 | 293 emit_data(disp, rspec, disp32_operand); |
| 294 } | |
| 304 | 295 } else if (base == rsp LP64_ONLY(|| base == r12)) { |
| 296 // [rsp + disp] | |
| 0 | 297 if (disp == 0 && rtype == relocInfo::none) { |
| 304 | 298 // [rsp] |
| 0 | 299 // [00 reg 100][00 100 100] |
| 304 | 300 emit_byte(0x04 | regenc); |
| 0 | 301 emit_byte(0x24); |
| 302 } else if (is8bit(disp) && rtype == relocInfo::none) { | |
| 304 | 303 // [rsp + imm8] |
| 304 // [01 reg 100][00 100 100] disp8 | |
| 305 emit_byte(0x44 | regenc); | |
| 0 | 306 emit_byte(0x24); |
| 307 emit_byte(disp & 0xFF); | |
| 308 } else { | |
| 304 | 309 // [rsp + imm32] |
| 310 // [10 reg 100][00 100 100] disp32 | |
| 311 emit_byte(0x84 | regenc); | |
| 0 | 312 emit_byte(0x24); |
| 313 emit_data(disp, rspec, disp32_operand); | |
| 314 } | |
| 315 } else { | |
| 316 // [base + disp] | |
| 304 | 317 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode"); |
| 318 if (disp == 0 && rtype == relocInfo::none && | |
| 319 base != rbp LP64_ONLY(&& base != r13)) { | |
| 0 | 320 // [base] |
| 321 // [00 reg base] | |
| 304 | 322 emit_byte(0x00 | regenc | baseenc); |
| 0 | 323 } else if (is8bit(disp) && rtype == relocInfo::none) { |
| 304 | 324 // [base + disp8] |
| 325 // [01 reg base] disp8 | |
| 326 emit_byte(0x40 | regenc | baseenc); | |
| 0 | 327 emit_byte(disp & 0xFF); |
| 328 } else { | |
| 304 | 329 // [base + disp32] |
| 330 // [10 reg base] disp32 | |
| 331 emit_byte(0x80 | regenc | baseenc); | |
| 0 | 332 emit_data(disp, rspec, disp32_operand); |
| 333 } | |
| 334 } | |
| 335 } else { | |
| 336 if (index->is_valid()) { | |
| 337 assert(scale != Address::no_scale, "inconsistent address"); | |
| 338 // [index*scale + disp] | |
| 304 | 339 // [00 reg 100][ss index 101] disp32 |
| 0 | 340 assert(index != rsp, "illegal addressing mode"); |
| 304 | 341 emit_byte(0x04 | regenc); |
| 342 emit_byte(scale << 6 | indexenc | 0x05); | |
| 0 | 343 emit_data(disp, rspec, disp32_operand); |
| 304 | 344 } else if (rtype != relocInfo::none ) { |
| 345 // [disp] (64bit) RIP-RELATIVE (32bit) abs | |
| 346 // [00 000 101] disp32 | |
| 347 | |
| 348 emit_byte(0x05 | regenc); | |
| 349 // Note that the RIP-rel. correction applies to the generated | |
| 350 // disp field, but _not_ to the target address in the rspec. | |
| 351 | |
| 352 // disp was created by converting the target address minus the pc | |
| 353 // at the start of the instruction. That needs more correction here. | |
| 354 // intptr_t disp = target - next_ip; | |
| 355 assert(inst_mark() != NULL, "must be inside InstructionMark"); | |
| 356 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction; | |
| 357 int64_t adjusted = disp; | |
| 358 // Do rip-rel adjustment for 64bit | |
| 359 LP64_ONLY(adjusted -= (next_ip - inst_mark())); | |
| 360 assert(is_simm32(adjusted), | |
| 361 "must be 32bit offset (RIP relative address)"); | |
| 362 emit_data((int32_t) adjusted, rspec, disp32_operand); | |
| 363 | |
| 0 | 364 } else { |
| 304 | 365 // 32bit never did this, did everything as the rip-rel/disp code above |
| 366 // [disp] ABSOLUTE | |
| 367 // [00 reg 100][00 100 101] disp32 | |
| 368 emit_byte(0x04 | regenc); | |
| 369 emit_byte(0x25); | |
| 0 | 370 emit_data(disp, rspec, disp32_operand); |
| 371 } | |
| 372 } | |
| 373 } | |
| 374 | |
| 304 | 375 void Assembler::emit_operand(XMMRegister reg, Register base, Register index, |
| 376 Address::ScaleFactor scale, int disp, | |
| 377 RelocationHolder const& rspec) { | |
| 378 emit_operand((Register)reg, base, index, scale, disp, rspec); | |
| 379 } | |
| 380 | |
| 0 | 381 // Secret local extension to Assembler::WhichOperand: |
| 382 #define end_pc_operand (_WhichOperand_limit) | |
| 383 | |
| 384 address Assembler::locate_operand(address inst, WhichOperand which) { | |
| 385 // Decode the given instruction, and return the address of | |
| 386 // an embedded 32-bit operand word. | |
| 387 | |
| 388 // If "which" is disp32_operand, selects the displacement portion | |
| 389 // of an effective address specifier. | |
| 304 | 390 // If "which" is imm64_operand, selects the trailing immediate constant. |
| 0 | 391 // If "which" is call32_operand, selects the displacement of a call or jump. |
| 392 // Caller is responsible for ensuring that there is such an operand, | |
| 304 | 393 // and that it is 32/64 bits wide. |
| 0 | 394 |
| 395 // If "which" is end_pc_operand, find the end of the instruction. | |
| 396 | |
| 397 address ip = inst; | |
| 304 | 398 bool is_64bit = false; |
| 399 | |
| 400 debug_only(bool has_disp32 = false); | |
| 401 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn | |
| 402 | |
| 403 again_after_prefix: | |
| 0 | 404 switch (0xFF & *ip++) { |
| 405 | |
| 406 // These convenience macros generate groups of "case" labels for the switch. | |
| 304 | 407 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3 |
| 408 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \ | |
| 0 | 409 case (x)+4: case (x)+5: case (x)+6: case (x)+7 |
| 304 | 410 #define REP16(x) REP8((x)+0): \ |
| 0 | 411 case REP8((x)+8) |
| 412 | |
| 413 case CS_segment: | |
| 414 case SS_segment: | |
| 415 case DS_segment: | |
| 416 case ES_segment: | |
| 417 case FS_segment: | |
| 418 case GS_segment: | |
| 304 | 419 // Seems dubious |
| 420 LP64_ONLY(assert(false, "shouldn't have that prefix")); | |
| 0 | 421 assert(ip == inst+1, "only one prefix allowed"); |
| 422 goto again_after_prefix; | |
| 423 | |
| 304 | 424 case 0x67: |
| 425 case REX: | |
| 426 case REX_B: | |
| 427 case REX_X: | |
| 428 case REX_XB: | |
| 429 case REX_R: | |
| 430 case REX_RB: | |
| 431 case REX_RX: | |
| 432 case REX_RXB: | |
| 433 NOT_LP64(assert(false, "64bit prefixes")); | |
| 434 goto again_after_prefix; | |
| 435 | |
| 436 case REX_W: | |
| 437 case REX_WB: | |
| 438 case REX_WX: | |
| 439 case REX_WXB: | |
| 440 case REX_WR: | |
| 441 case REX_WRB: | |
| 442 case REX_WRX: | |
| 443 case REX_WRXB: | |
| 444 NOT_LP64(assert(false, "64bit prefixes")); | |
| 445 is_64bit = true; | |
| 446 goto again_after_prefix; | |
| 447 | |
| 448 case 0xFF: // pushq a; decl a; incl a; call a; jmp a | |
| 0 | 449 case 0x88: // movb a, r |
| 450 case 0x89: // movl a, r | |
| 451 case 0x8A: // movb r, a | |
| 452 case 0x8B: // movl r, a | |
| 453 case 0x8F: // popl a | |
| 304 | 454 debug_only(has_disp32 = true); |
| 0 | 455 break; |
| 456 | |
| 304 | 457 case 0x68: // pushq #32 |
| 458 if (which == end_pc_operand) { | |
| 459 return ip + 4; | |
| 460 } | |
| 461 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate"); | |
| 0 | 462 return ip; // not produced by emit_operand |
| 463 | |
| 464 case 0x66: // movw ... (size prefix) | |
| 304 | 465 again_after_size_prefix2: |
| 0 | 466 switch (0xFF & *ip++) { |
| 304 | 467 case REX: |
| 468 case REX_B: | |
| 469 case REX_X: | |
| 470 case REX_XB: | |
| 471 case REX_R: | |
| 472 case REX_RB: | |
| 473 case REX_RX: | |
| 474 case REX_RXB: | |
| 475 case REX_W: | |
| 476 case REX_WB: | |
| 477 case REX_WX: | |
| 478 case REX_WXB: | |
| 479 case REX_WR: | |
| 480 case REX_WRB: | |
| 481 case REX_WRX: | |
| 482 case REX_WRXB: | |
| 483 NOT_LP64(assert(false, "64bit prefix found")); | |
| 484 goto again_after_size_prefix2; | |
| 0 | 485 case 0x8B: // movw r, a |
| 486 case 0x89: // movw a, r | |
| 304 | 487 debug_only(has_disp32 = true); |
| 0 | 488 break; |
| 489 case 0xC7: // movw a, #16 | |
| 304 | 490 debug_only(has_disp32 = true); |
| 0 | 491 tail_size = 2; // the imm16 |
| 492 break; | |
| 493 case 0x0F: // several SSE/SSE2 variants | |
| 494 ip--; // reparse the 0x0F | |
| 495 goto again_after_prefix; | |
| 496 default: | |
| 497 ShouldNotReachHere(); | |
| 498 } | |
| 499 break; | |
| 500 | |
| 304 | 501 case REP8(0xB8): // movl/q r, #32/#64(oop?) |
| 502 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4); | |
| 503 // these asserts are somewhat nonsensical | |
| 504 #ifndef _LP64 | |
| 505 assert(which == imm_operand || which == disp32_operand, ""); | |
| 506 #else | |
| 507 assert((which == call32_operand || which == imm_operand) && is_64bit || | |
| 508 which == narrow_oop_operand && !is_64bit, ""); | |
| 509 #endif // _LP64 | |
| 0 | 510 return ip; |
| 511 | |
| 512 case 0x69: // imul r, a, #32 | |
| 513 case 0xC7: // movl a, #32(oop?) | |
| 514 tail_size = 4; | |
| 304 | 515 debug_only(has_disp32 = true); // has both kinds of operands! |
| 0 | 516 break; |
| 517 | |
| 518 case 0x0F: // movx..., etc. | |
| 519 switch (0xFF & *ip++) { | |
| 520 case 0x12: // movlps | |
| 521 case 0x28: // movaps | |
| 522 case 0x2E: // ucomiss | |
| 523 case 0x2F: // comiss | |
| 524 case 0x54: // andps | |
| 525 case 0x55: // andnps | |
| 526 case 0x56: // orps | |
| 527 case 0x57: // xorps | |
| 528 case 0x6E: // movd | |
| 529 case 0x7E: // movd | |
| 530 case 0xAE: // ldmxcsr a | |
| 304 | 531 // 64bit side says it these have both operands but that doesn't |
| 532 // appear to be true | |
| 533 debug_only(has_disp32 = true); | |
| 0 | 534 break; |
| 535 | |
| 536 case 0xAD: // shrd r, a, %cl | |
| 537 case 0xAF: // imul r, a | |
| 304 | 538 case 0xBE: // movsbl r, a (movsxb) |
| 539 case 0xBF: // movswl r, a (movsxw) | |
| 540 case 0xB6: // movzbl r, a (movzxb) | |
| 541 case 0xB7: // movzwl r, a (movzxw) | |
| 0 | 542 case REP16(0x40): // cmovl cc, r, a |
| 543 case 0xB0: // cmpxchgb | |
| 544 case 0xB1: // cmpxchg | |
| 545 case 0xC1: // xaddl | |
| 546 case 0xC7: // cmpxchg8 | |
| 547 case REP16(0x90): // setcc a | |
| 304 | 548 debug_only(has_disp32 = true); |
| 0 | 549 // fall out of the switch to decode the address |
| 550 break; | |
| 304 | 551 |
| 0 | 552 case 0xAC: // shrd r, a, #8 |
| 304 | 553 debug_only(has_disp32 = true); |
| 0 | 554 tail_size = 1; // the imm8 |
| 555 break; | |
| 304 | 556 |
| 0 | 557 case REP16(0x80): // jcc rdisp32 |
| 558 if (which == end_pc_operand) return ip + 4; | |
| 304 | 559 assert(which == call32_operand, "jcc has no disp32 or imm"); |
| 0 | 560 return ip; |
| 561 default: | |
| 562 ShouldNotReachHere(); | |
| 563 } | |
| 564 break; | |
| 565 | |
| 566 case 0x81: // addl a, #32; addl r, #32 | |
| 567 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl | |
| 304 | 568 // on 32bit in the case of cmpl, the imm might be an oop |
| 0 | 569 tail_size = 4; |
| 304 | 570 debug_only(has_disp32 = true); // has both kinds of operands! |
| 0 | 571 break; |
| 572 | |
| 573 case 0x83: // addl a, #8; addl r, #8 | |
| 574 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl | |
| 304 | 575 debug_only(has_disp32 = true); // has both kinds of operands! |
| 0 | 576 tail_size = 1; |
| 577 break; | |
| 578 | |
| 579 case 0x9B: | |
| 580 switch (0xFF & *ip++) { | |
| 581 case 0xD9: // fnstcw a | |
| 304 | 582 debug_only(has_disp32 = true); |
| 0 | 583 break; |
| 584 default: | |
| 585 ShouldNotReachHere(); | |
| 586 } | |
| 587 break; | |
| 588 | |
| 589 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a | |
| 590 case REP4(0x10): // adc... | |
| 591 case REP4(0x20): // and... | |
| 592 case REP4(0x30): // xor... | |
| 593 case REP4(0x08): // or... | |
| 594 case REP4(0x18): // sbb... | |
| 595 case REP4(0x28): // sub... | |
| 304 | 596 case 0xF7: // mull a |
| 597 case 0x8D: // lea r, a | |
| 598 case 0x87: // xchg r, a | |
| 0 | 599 case REP4(0x38): // cmp... |
| 304 | 600 case 0x85: // test r, a |
| 601 debug_only(has_disp32 = true); // has both kinds of operands! | |
| 0 | 602 break; |
| 603 | |
| 604 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8 | |
| 605 case 0xC6: // movb a, #8 | |
| 606 case 0x80: // cmpb a, #8 | |
| 607 case 0x6B: // imul r, a, #8 | |
| 304 | 608 debug_only(has_disp32 = true); // has both kinds of operands! |
| 0 | 609 tail_size = 1; // the imm8 |
| 610 break; | |
| 611 | |
| 612 case 0xE8: // call rdisp32 | |
| 613 case 0xE9: // jmp rdisp32 | |
| 614 if (which == end_pc_operand) return ip + 4; | |
| 304 | 615 assert(which == call32_operand, "call has no disp32 or imm"); |
| 0 | 616 return ip; |
| 617 | |
| 618 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1 | |
| 619 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl | |
| 620 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a | |
| 621 case 0xDD: // fld_d a; fst_d a; fstp_d a | |
| 622 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a | |
| 623 case 0xDF: // fild_d a; fistp_d a | |
| 624 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a | |
| 625 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a | |
| 626 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a | |
| 304 | 627 debug_only(has_disp32 = true); |
| 0 | 628 break; |
| 629 | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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630 case 0xF0: // Lock |
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6462850: generate biased locking code in C2 ideal graph
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631 assert(os::is_MP(), "only on MP"); |
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6462850: generate biased locking code in C2 ideal graph
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632 goto again_after_prefix; |
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a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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|
633 |
| 0 | 634 case 0xF3: // For SSE |
| 635 case 0xF2: // For SSE2 | |
| 304 | 636 switch (0xFF & *ip++) { |
| 637 case REX: | |
| 638 case REX_B: | |
| 639 case REX_X: | |
| 640 case REX_XB: | |
| 641 case REX_R: | |
| 642 case REX_RB: | |
| 643 case REX_RX: | |
| 644 case REX_RXB: | |
| 645 case REX_W: | |
| 646 case REX_WB: | |
| 647 case REX_WX: | |
| 648 case REX_WXB: | |
| 649 case REX_WR: | |
| 650 case REX_WRB: | |
| 651 case REX_WRX: | |
| 652 case REX_WRXB: | |
| 653 NOT_LP64(assert(false, "found 64bit prefix")); | |
| 654 ip++; | |
| 655 default: | |
| 656 ip++; | |
| 657 } | |
| 658 debug_only(has_disp32 = true); // has both kinds of operands! | |
| 0 | 659 break; |
| 660 | |
| 661 default: | |
| 662 ShouldNotReachHere(); | |
| 663 | |
| 304 | 664 #undef REP8 |
| 665 #undef REP16 | |
| 0 | 666 } |
| 667 | |
| 668 assert(which != call32_operand, "instruction is not a call, jmp, or jcc"); | |
| 304 | 669 #ifdef _LP64 |
| 670 assert(which != imm_operand, "instruction is not a movq reg, imm64"); | |
| 671 #else | |
| 672 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field"); | |
| 673 assert(which != imm_operand || has_disp32, "instruction has no imm32 field"); | |
| 674 #endif // LP64 | |
| 675 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field"); | |
| 0 | 676 |
| 677 // parse the output of emit_operand | |
| 678 int op2 = 0xFF & *ip++; | |
| 679 int base = op2 & 0x07; | |
| 680 int op3 = -1; | |
| 681 const int b100 = 4; | |
| 682 const int b101 = 5; | |
| 683 if (base == b100 && (op2 >> 6) != 3) { | |
| 684 op3 = 0xFF & *ip++; | |
| 685 base = op3 & 0x07; // refetch the base | |
| 686 } | |
| 687 // now ip points at the disp (if any) | |
| 688 | |
| 689 switch (op2 >> 6) { | |
| 690 case 0: | |
| 691 // [00 reg 100][ss index base] | |
| 304 | 692 // [00 reg 100][00 100 esp] |
| 0 | 693 // [00 reg base] |
| 694 // [00 reg 100][ss index 101][disp32] | |
| 695 // [00 reg 101] [disp32] | |
| 696 | |
| 697 if (base == b101) { | |
| 698 if (which == disp32_operand) | |
| 699 return ip; // caller wants the disp32 | |
| 700 ip += 4; // skip the disp32 | |
| 701 } | |
| 702 break; | |
| 703 | |
| 704 case 1: | |
| 705 // [01 reg 100][ss index base][disp8] | |
| 304 | 706 // [01 reg 100][00 100 esp][disp8] |
| 0 | 707 // [01 reg base] [disp8] |
| 708 ip += 1; // skip the disp8 | |
| 709 break; | |
| 710 | |
| 711 case 2: | |
| 712 // [10 reg 100][ss index base][disp32] | |
| 304 | 713 // [10 reg 100][00 100 esp][disp32] |
| 0 | 714 // [10 reg base] [disp32] |
| 715 if (which == disp32_operand) | |
| 716 return ip; // caller wants the disp32 | |
| 717 ip += 4; // skip the disp32 | |
| 718 break; | |
| 719 | |
| 720 case 3: | |
| 721 // [11 reg base] (not a memory addressing mode) | |
| 722 break; | |
| 723 } | |
| 724 | |
| 725 if (which == end_pc_operand) { | |
| 726 return ip + tail_size; | |
| 727 } | |
| 728 | |
| 304 | 729 #ifdef _LP64 |
| 730 assert(false, "fix locate_operand"); | |
| 731 #else | |
| 732 assert(which == imm_operand, "instruction has only an imm field"); | |
| 733 #endif // LP64 | |
| 0 | 734 return ip; |
| 735 } | |
| 736 | |
| 737 address Assembler::locate_next_instruction(address inst) { | |
| 738 // Secretly share code with locate_operand: | |
| 739 return locate_operand(inst, end_pc_operand); | |
| 740 } | |
| 741 | |
| 742 | |
| 743 #ifdef ASSERT | |
| 744 void Assembler::check_relocation(RelocationHolder const& rspec, int format) { | |
| 745 address inst = inst_mark(); | |
| 746 assert(inst != NULL && inst < pc(), "must point to beginning of instruction"); | |
| 747 address opnd; | |
| 748 | |
| 749 Relocation* r = rspec.reloc(); | |
| 750 if (r->type() == relocInfo::none) { | |
| 751 return; | |
| 752 } else if (r->is_call() || format == call32_operand) { | |
| 753 // assert(format == imm32_operand, "cannot specify a nonzero format"); | |
| 754 opnd = locate_operand(inst, call32_operand); | |
| 755 } else if (r->is_data()) { | |
| 304 | 756 assert(format == imm_operand || format == disp32_operand |
| 757 LP64_ONLY(|| format == narrow_oop_operand), "format ok"); | |
| 0 | 758 opnd = locate_operand(inst, (WhichOperand)format); |
| 759 } else { | |
| 304 | 760 assert(format == imm_operand, "cannot specify a format"); |
| 0 | 761 return; |
| 762 } | |
| 763 assert(opnd == pc(), "must put operand where relocs can find it"); | |
| 764 } | |
| 304 | 765 #endif // ASSERT |
| 766 | |
| 767 void Assembler::emit_operand32(Register reg, Address adr) { | |
| 768 assert(reg->encoding() < 8, "no extended registers"); | |
| 769 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); | |
| 770 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |
| 771 adr._rspec); | |
| 772 } | |
| 773 | |
| 774 void Assembler::emit_operand(Register reg, Address adr, | |
| 775 int rip_relative_correction) { | |
| 776 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |
| 777 adr._rspec, | |
| 778 rip_relative_correction); | |
| 779 } | |
| 780 | |
| 781 void Assembler::emit_operand(XMMRegister reg, Address adr) { | |
| 782 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |
| 783 adr._rspec); | |
| 784 } | |
| 785 | |
| 786 // MMX operations | |
| 787 void Assembler::emit_operand(MMXRegister reg, Address adr) { | |
| 788 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); | |
| 789 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); | |
| 790 } | |
| 791 | |
| 792 // work around gcc (3.2.1-7a) bug | |
| 793 void Assembler::emit_operand(Address adr, MMXRegister reg) { | |
| 794 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); | |
| 795 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); | |
| 0 | 796 } |
| 797 | |
| 798 | |
| 799 void Assembler::emit_farith(int b1, int b2, int i) { | |
| 800 assert(isByte(b1) && isByte(b2), "wrong opcode"); | |
| 801 assert(0 <= i && i < 8, "illegal stack offset"); | |
| 802 emit_byte(b1); | |
| 803 emit_byte(b2 + i); | |
| 804 } | |
| 805 | |
| 806 | |
| 304 | 807 // Now the Assembler instruction (identical for 32/64 bits) |
| 808 | |
| 809 void Assembler::adcl(Register dst, int32_t imm32) { | |
| 810 prefix(dst); | |
| 0 | 811 emit_arith(0x81, 0xD0, dst, imm32); |
| 812 } | |
| 813 | |
| 814 void Assembler::adcl(Register dst, Address src) { | |
| 815 InstructionMark im(this); | |
| 304 | 816 prefix(src, dst); |
| 0 | 817 emit_byte(0x13); |
| 818 emit_operand(dst, src); | |
| 819 } | |
| 820 | |
| 821 void Assembler::adcl(Register dst, Register src) { | |
| 304 | 822 (void) prefix_and_encode(dst->encoding(), src->encoding()); |
| 0 | 823 emit_arith(0x13, 0xC0, dst, src); |
| 824 } | |
| 825 | |
| 304 | 826 void Assembler::addl(Address dst, int32_t imm32) { |
| 827 InstructionMark im(this); | |
| 828 prefix(dst); | |
| 829 emit_arith_operand(0x81, rax, dst, imm32); | |
| 830 } | |
| 0 | 831 |
| 832 void Assembler::addl(Address dst, Register src) { | |
| 833 InstructionMark im(this); | |
| 304 | 834 prefix(dst, src); |
| 0 | 835 emit_byte(0x01); |
| 836 emit_operand(src, dst); | |
| 837 } | |
| 838 | |
| 304 | 839 void Assembler::addl(Register dst, int32_t imm32) { |
| 840 prefix(dst); | |
| 0 | 841 emit_arith(0x81, 0xC0, dst, imm32); |
| 842 } | |
| 843 | |
| 844 void Assembler::addl(Register dst, Address src) { | |
| 845 InstructionMark im(this); | |
| 304 | 846 prefix(src, dst); |
| 0 | 847 emit_byte(0x03); |
| 848 emit_operand(dst, src); | |
| 849 } | |
| 850 | |
| 851 void Assembler::addl(Register dst, Register src) { | |
| 304 | 852 (void) prefix_and_encode(dst->encoding(), src->encoding()); |
| 0 | 853 emit_arith(0x03, 0xC0, dst, src); |
| 854 } | |
| 855 | |
| 856 void Assembler::addr_nop_4() { | |
| 857 // 4 bytes: NOP DWORD PTR [EAX+0] | |
| 858 emit_byte(0x0F); | |
| 859 emit_byte(0x1F); | |
| 860 emit_byte(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc); | |
| 861 emit_byte(0); // 8-bits offset (1 byte) | |
| 862 } | |
| 863 | |
| 864 void Assembler::addr_nop_5() { | |
| 865 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset | |
| 866 emit_byte(0x0F); | |
| 867 emit_byte(0x1F); | |
| 868 emit_byte(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4); | |
| 869 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); | |
| 870 emit_byte(0); // 8-bits offset (1 byte) | |
| 871 } | |
| 872 | |
| 873 void Assembler::addr_nop_7() { | |
| 874 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset | |
| 875 emit_byte(0x0F); | |
| 876 emit_byte(0x1F); | |
| 877 emit_byte(0x80); // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc); | |
| 878 emit_long(0); // 32-bits offset (4 bytes) | |
| 879 } | |
| 880 | |
| 881 void Assembler::addr_nop_8() { | |
| 882 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset | |
| 883 emit_byte(0x0F); | |
| 884 emit_byte(0x1F); | |
| 885 emit_byte(0x84); // emit_rm(cbuf, 0x2, EAX_enc, 0x4); | |
| 886 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); | |
| 887 emit_long(0); // 32-bits offset (4 bytes) | |
| 888 } | |
| 889 | |
| 304 | 890 void Assembler::addsd(XMMRegister dst, XMMRegister src) { |
| 891 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 892 emit_byte(0xF2); | |
| 893 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 894 emit_byte(0x0F); | |
| 895 emit_byte(0x58); | |
| 896 emit_byte(0xC0 | encode); | |
| 897 } | |
| 898 | |
| 899 void Assembler::addsd(XMMRegister dst, Address src) { | |
| 900 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 901 InstructionMark im(this); | |
| 902 emit_byte(0xF2); | |
| 903 prefix(src, dst); | |
| 904 emit_byte(0x0F); | |
| 905 emit_byte(0x58); | |
| 906 emit_operand(dst, src); | |
| 907 } | |
| 908 | |
| 909 void Assembler::addss(XMMRegister dst, XMMRegister src) { | |
| 910 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 911 emit_byte(0xF3); | |
| 912 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 913 emit_byte(0x0F); | |
| 914 emit_byte(0x58); | |
| 915 emit_byte(0xC0 | encode); | |
| 916 } | |
| 917 | |
| 918 void Assembler::addss(XMMRegister dst, Address src) { | |
| 919 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 920 InstructionMark im(this); | |
| 921 emit_byte(0xF3); | |
| 922 prefix(src, dst); | |
| 923 emit_byte(0x0F); | |
| 924 emit_byte(0x58); | |
| 925 emit_operand(dst, src); | |
| 926 } | |
| 927 | |
| 928 void Assembler::andl(Register dst, int32_t imm32) { | |
| 929 prefix(dst); | |
| 930 emit_arith(0x81, 0xE0, dst, imm32); | |
| 931 } | |
| 932 | |
| 933 void Assembler::andl(Register dst, Address src) { | |
| 934 InstructionMark im(this); | |
| 935 prefix(src, dst); | |
| 936 emit_byte(0x23); | |
| 937 emit_operand(dst, src); | |
| 938 } | |
| 939 | |
| 940 void Assembler::andl(Register dst, Register src) { | |
| 941 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 942 emit_arith(0x23, 0xC0, dst, src); | |
| 943 } | |
| 944 | |
| 945 void Assembler::andpd(XMMRegister dst, Address src) { | |
| 946 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 947 InstructionMark im(this); | |
| 948 emit_byte(0x66); | |
| 949 prefix(src, dst); | |
| 950 emit_byte(0x0F); | |
| 951 emit_byte(0x54); | |
| 952 emit_operand(dst, src); | |
| 953 } | |
| 954 | |
| 955 void Assembler::bswapl(Register reg) { // bswap | |
| 956 int encode = prefix_and_encode(reg->encoding()); | |
| 957 emit_byte(0x0F); | |
| 958 emit_byte(0xC8 | encode); | |
| 959 } | |
| 960 | |
| 961 void Assembler::call(Label& L, relocInfo::relocType rtype) { | |
| 962 // suspect disp32 is always good | |
| 963 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand); | |
| 964 | |
| 965 if (L.is_bound()) { | |
| 966 const int long_size = 5; | |
| 967 int offs = (int)( target(L) - pc() ); | |
| 968 assert(offs <= 0, "assembler error"); | |
| 969 InstructionMark im(this); | |
| 970 // 1110 1000 #32-bit disp | |
| 971 emit_byte(0xE8); | |
| 972 emit_data(offs - long_size, rtype, operand); | |
| 973 } else { | |
| 974 InstructionMark im(this); | |
| 975 // 1110 1000 #32-bit disp | |
| 976 L.add_patch_at(code(), locator()); | |
| 977 | |
| 978 emit_byte(0xE8); | |
| 979 emit_data(int(0), rtype, operand); | |
| 980 } | |
| 981 } | |
| 982 | |
| 983 void Assembler::call(Register dst) { | |
| 984 // This was originally using a 32bit register encoding | |
| 985 // and surely we want 64bit! | |
| 986 // this is a 32bit encoding but in 64bit mode the default | |
| 987 // operand size is 64bit so there is no need for the | |
| 988 // wide prefix. So prefix only happens if we use the | |
| 989 // new registers. Much like push/pop. | |
| 990 int x = offset(); | |
| 991 // this may be true but dbx disassembles it as if it | |
| 992 // were 32bits... | |
| 993 // int encode = prefix_and_encode(dst->encoding()); | |
| 994 // if (offset() != x) assert(dst->encoding() >= 8, "what?"); | |
| 995 int encode = prefixq_and_encode(dst->encoding()); | |
| 996 | |
| 997 emit_byte(0xFF); | |
| 998 emit_byte(0xD0 | encode); | |
| 999 } | |
| 1000 | |
| 1001 | |
| 1002 void Assembler::call(Address adr) { | |
| 1003 InstructionMark im(this); | |
| 1004 prefix(adr); | |
| 1005 emit_byte(0xFF); | |
| 1006 emit_operand(rdx, adr); | |
| 1007 } | |
| 1008 | |
| 1009 void Assembler::call_literal(address entry, RelocationHolder const& rspec) { | |
| 1010 assert(entry != NULL, "call most probably wrong"); | |
| 1011 InstructionMark im(this); | |
| 1012 emit_byte(0xE8); | |
| 1013 intptr_t disp = entry - (_code_pos + sizeof(int32_t)); | |
| 1014 assert(is_simm32(disp), "must be 32bit offset (call2)"); | |
| 1015 // Technically, should use call32_operand, but this format is | |
| 1016 // implied by the fact that we're emitting a call instruction. | |
| 1017 | |
| 1018 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand); | |
| 1019 emit_data((int) disp, rspec, operand); | |
| 1020 } | |
| 1021 | |
| 1022 void Assembler::cdql() { | |
| 1023 emit_byte(0x99); | |
| 1024 } | |
| 1025 | |
| 1026 void Assembler::cmovl(Condition cc, Register dst, Register src) { | |
| 1027 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); | |
| 1028 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1029 emit_byte(0x0F); | |
| 1030 emit_byte(0x40 | cc); | |
| 1031 emit_byte(0xC0 | encode); | |
| 1032 } | |
| 1033 | |
| 1034 | |
| 1035 void Assembler::cmovl(Condition cc, Register dst, Address src) { | |
| 1036 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); | |
| 1037 prefix(src, dst); | |
| 1038 emit_byte(0x0F); | |
| 1039 emit_byte(0x40 | cc); | |
| 1040 emit_operand(dst, src); | |
| 1041 } | |
| 1042 | |
| 1043 void Assembler::cmpb(Address dst, int imm8) { | |
| 1044 InstructionMark im(this); | |
| 1045 prefix(dst); | |
| 1046 emit_byte(0x80); | |
| 1047 emit_operand(rdi, dst, 1); | |
| 1048 emit_byte(imm8); | |
| 1049 } | |
| 1050 | |
| 1051 void Assembler::cmpl(Address dst, int32_t imm32) { | |
| 1052 InstructionMark im(this); | |
| 1053 prefix(dst); | |
| 1054 emit_byte(0x81); | |
| 1055 emit_operand(rdi, dst, 4); | |
| 1056 emit_long(imm32); | |
| 1057 } | |
| 1058 | |
| 1059 void Assembler::cmpl(Register dst, int32_t imm32) { | |
| 1060 prefix(dst); | |
| 1061 emit_arith(0x81, 0xF8, dst, imm32); | |
| 1062 } | |
| 1063 | |
| 1064 void Assembler::cmpl(Register dst, Register src) { | |
| 1065 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1066 emit_arith(0x3B, 0xC0, dst, src); | |
| 1067 } | |
| 1068 | |
| 1069 | |
| 1070 void Assembler::cmpl(Register dst, Address src) { | |
| 1071 InstructionMark im(this); | |
| 1072 prefix(src, dst); | |
| 1073 emit_byte(0x3B); | |
| 1074 emit_operand(dst, src); | |
| 1075 } | |
| 1076 | |
| 1077 void Assembler::cmpw(Address dst, int imm16) { | |
| 1078 InstructionMark im(this); | |
| 1079 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers"); | |
| 1080 emit_byte(0x66); | |
| 1081 emit_byte(0x81); | |
| 1082 emit_operand(rdi, dst, 2); | |
| 1083 emit_word(imm16); | |
| 1084 } | |
| 1085 | |
| 1086 // The 32-bit cmpxchg compares the value at adr with the contents of rax, | |
| 1087 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,. | |
| 1088 // The ZF is set if the compared values were equal, and cleared otherwise. | |
| 1089 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg | |
| 1090 if (Atomics & 2) { | |
| 1091 // caveat: no instructionmark, so this isn't relocatable. | |
| 1092 // Emit a synthetic, non-atomic, CAS equivalent. | |
| 1093 // Beware. The synthetic form sets all ICCs, not just ZF. | |
| 1094 // cmpxchg r,[m] is equivalent to rax, = CAS (m, rax, r) | |
| 1095 cmpl(rax, adr); | |
| 1096 movl(rax, adr); | |
| 1097 if (reg != rax) { | |
| 1098 Label L ; | |
| 1099 jcc(Assembler::notEqual, L); | |
| 1100 movl(adr, reg); | |
| 1101 bind(L); | |
| 1102 } | |
| 1103 } else { | |
| 1104 InstructionMark im(this); | |
| 1105 prefix(adr, reg); | |
| 1106 emit_byte(0x0F); | |
| 1107 emit_byte(0xB1); | |
| 1108 emit_operand(reg, adr); | |
| 1109 } | |
| 1110 } | |
| 1111 | |
| 1112 void Assembler::comisd(XMMRegister dst, Address src) { | |
| 1113 // NOTE: dbx seems to decode this as comiss even though the | |
| 1114 // 0x66 is there. Strangly ucomisd comes out correct | |
| 1115 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1116 emit_byte(0x66); | |
| 1117 comiss(dst, src); | |
| 1118 } | |
| 1119 | |
| 1120 void Assembler::comiss(XMMRegister dst, Address src) { | |
| 1121 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1122 | |
| 1123 InstructionMark im(this); | |
| 1124 prefix(src, dst); | |
| 1125 emit_byte(0x0F); | |
| 1126 emit_byte(0x2F); | |
| 1127 emit_operand(dst, src); | |
| 1128 } | |
| 1129 | |
| 1130 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) { | |
| 1131 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1132 emit_byte(0xF3); | |
| 1133 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1134 emit_byte(0x0F); | |
| 1135 emit_byte(0xE6); | |
| 1136 emit_byte(0xC0 | encode); | |
| 1137 } | |
| 1138 | |
| 1139 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) { | |
| 1140 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1141 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1142 emit_byte(0x0F); | |
| 1143 emit_byte(0x5B); | |
| 1144 emit_byte(0xC0 | encode); | |
| 1145 } | |
| 1146 | |
| 1147 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) { | |
| 1148 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1149 emit_byte(0xF2); | |
| 1150 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1151 emit_byte(0x0F); | |
| 1152 emit_byte(0x5A); | |
| 1153 emit_byte(0xC0 | encode); | |
| 1154 } | |
| 1155 | |
| 1156 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) { | |
| 1157 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1158 emit_byte(0xF2); | |
| 1159 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1160 emit_byte(0x0F); | |
| 1161 emit_byte(0x2A); | |
| 1162 emit_byte(0xC0 | encode); | |
| 1163 } | |
| 1164 | |
| 1165 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) { | |
| 1166 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1167 emit_byte(0xF3); | |
| 1168 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1169 emit_byte(0x0F); | |
| 1170 emit_byte(0x2A); | |
| 1171 emit_byte(0xC0 | encode); | |
| 1172 } | |
| 1173 | |
| 1174 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) { | |
| 1175 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1176 emit_byte(0xF3); | |
| 1177 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1178 emit_byte(0x0F); | |
| 1179 emit_byte(0x5A); | |
| 1180 emit_byte(0xC0 | encode); | |
| 1181 } | |
| 1182 | |
| 1183 void Assembler::cvttsd2sil(Register dst, XMMRegister src) { | |
| 1184 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1185 emit_byte(0xF2); | |
| 1186 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1187 emit_byte(0x0F); | |
| 1188 emit_byte(0x2C); | |
| 1189 emit_byte(0xC0 | encode); | |
| 1190 } | |
| 1191 | |
| 1192 void Assembler::cvttss2sil(Register dst, XMMRegister src) { | |
| 1193 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1194 emit_byte(0xF3); | |
| 1195 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1196 emit_byte(0x0F); | |
| 1197 emit_byte(0x2C); | |
| 1198 emit_byte(0xC0 | encode); | |
| 1199 } | |
| 1200 | |
| 1201 void Assembler::decl(Address dst) { | |
| 1202 // Don't use it directly. Use MacroAssembler::decrement() instead. | |
| 1203 InstructionMark im(this); | |
| 1204 prefix(dst); | |
| 1205 emit_byte(0xFF); | |
| 1206 emit_operand(rcx, dst); | |
| 1207 } | |
| 1208 | |
| 1209 void Assembler::divsd(XMMRegister dst, Address src) { | |
| 1210 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1211 InstructionMark im(this); | |
| 1212 emit_byte(0xF2); | |
| 1213 prefix(src, dst); | |
| 1214 emit_byte(0x0F); | |
| 1215 emit_byte(0x5E); | |
| 1216 emit_operand(dst, src); | |
| 1217 } | |
| 1218 | |
| 1219 void Assembler::divsd(XMMRegister dst, XMMRegister src) { | |
| 1220 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1221 emit_byte(0xF2); | |
| 1222 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1223 emit_byte(0x0F); | |
| 1224 emit_byte(0x5E); | |
| 1225 emit_byte(0xC0 | encode); | |
| 1226 } | |
| 1227 | |
| 1228 void Assembler::divss(XMMRegister dst, Address src) { | |
| 1229 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1230 InstructionMark im(this); | |
| 1231 emit_byte(0xF3); | |
| 1232 prefix(src, dst); | |
| 1233 emit_byte(0x0F); | |
| 1234 emit_byte(0x5E); | |
| 1235 emit_operand(dst, src); | |
| 1236 } | |
| 1237 | |
| 1238 void Assembler::divss(XMMRegister dst, XMMRegister src) { | |
| 1239 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1240 emit_byte(0xF3); | |
| 1241 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1242 emit_byte(0x0F); | |
| 1243 emit_byte(0x5E); | |
| 1244 emit_byte(0xC0 | encode); | |
| 1245 } | |
| 1246 | |
| 1247 void Assembler::emms() { | |
| 1248 NOT_LP64(assert(VM_Version::supports_mmx(), "")); | |
| 1249 emit_byte(0x0F); | |
| 1250 emit_byte(0x77); | |
| 1251 } | |
| 1252 | |
| 1253 void Assembler::hlt() { | |
| 1254 emit_byte(0xF4); | |
| 1255 } | |
| 1256 | |
| 1257 void Assembler::idivl(Register src) { | |
| 1258 int encode = prefix_and_encode(src->encoding()); | |
| 1259 emit_byte(0xF7); | |
| 1260 emit_byte(0xF8 | encode); | |
| 1261 } | |
| 1262 | |
| 1263 void Assembler::imull(Register dst, Register src) { | |
| 1264 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1265 emit_byte(0x0F); | |
| 1266 emit_byte(0xAF); | |
| 1267 emit_byte(0xC0 | encode); | |
| 1268 } | |
| 1269 | |
| 1270 | |
| 1271 void Assembler::imull(Register dst, Register src, int value) { | |
| 1272 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1273 if (is8bit(value)) { | |
| 1274 emit_byte(0x6B); | |
| 1275 emit_byte(0xC0 | encode); | |
| 1276 emit_byte(value); | |
| 1277 } else { | |
| 1278 emit_byte(0x69); | |
| 1279 emit_byte(0xC0 | encode); | |
| 1280 emit_long(value); | |
| 1281 } | |
| 1282 } | |
| 1283 | |
| 1284 void Assembler::incl(Address dst) { | |
| 1285 // Don't use it directly. Use MacroAssembler::increment() instead. | |
| 1286 InstructionMark im(this); | |
| 1287 prefix(dst); | |
| 1288 emit_byte(0xFF); | |
| 1289 emit_operand(rax, dst); | |
| 1290 } | |
| 1291 | |
| 1292 void Assembler::jcc(Condition cc, Label& L, relocInfo::relocType rtype) { | |
| 1293 InstructionMark im(this); | |
| 1294 relocate(rtype); | |
| 1295 assert((0 <= cc) && (cc < 16), "illegal cc"); | |
| 1296 if (L.is_bound()) { | |
| 1297 address dst = target(L); | |
| 1298 assert(dst != NULL, "jcc most probably wrong"); | |
| 1299 | |
| 1300 const int short_size = 2; | |
| 1301 const int long_size = 6; | |
| 1302 intptr_t offs = (intptr_t)dst - (intptr_t)_code_pos; | |
| 1303 if (rtype == relocInfo::none && is8bit(offs - short_size)) { | |
| 1304 // 0111 tttn #8-bit disp | |
| 1305 emit_byte(0x70 | cc); | |
| 1306 emit_byte((offs - short_size) & 0xFF); | |
| 1307 } else { | |
| 1308 // 0000 1111 1000 tttn #32-bit disp | |
| 1309 assert(is_simm32(offs - long_size), | |
| 1310 "must be 32bit offset (call4)"); | |
| 1311 emit_byte(0x0F); | |
| 1312 emit_byte(0x80 | cc); | |
| 1313 emit_long(offs - long_size); | |
| 1314 } | |
| 1315 } else { | |
| 1316 // Note: could eliminate cond. jumps to this jump if condition | |
| 1317 // is the same however, seems to be rather unlikely case. | |
| 1318 // Note: use jccb() if label to be bound is very close to get | |
| 1319 // an 8-bit displacement | |
| 1320 L.add_patch_at(code(), locator()); | |
| 1321 emit_byte(0x0F); | |
| 1322 emit_byte(0x80 | cc); | |
| 1323 emit_long(0); | |
| 1324 } | |
| 1325 } | |
| 1326 | |
| 1327 void Assembler::jccb(Condition cc, Label& L) { | |
| 1328 if (L.is_bound()) { | |
| 1329 const int short_size = 2; | |
| 1330 address entry = target(L); | |
| 1331 assert(is8bit((intptr_t)entry - ((intptr_t)_code_pos + short_size)), | |
| 1332 "Dispacement too large for a short jmp"); | |
| 1333 intptr_t offs = (intptr_t)entry - (intptr_t)_code_pos; | |
| 1334 // 0111 tttn #8-bit disp | |
| 1335 emit_byte(0x70 | cc); | |
| 1336 emit_byte((offs - short_size) & 0xFF); | |
| 1337 } else { | |
| 1338 InstructionMark im(this); | |
| 1339 L.add_patch_at(code(), locator()); | |
| 1340 emit_byte(0x70 | cc); | |
| 1341 emit_byte(0); | |
| 1342 } | |
| 1343 } | |
| 1344 | |
| 1345 void Assembler::jmp(Address adr) { | |
| 1346 InstructionMark im(this); | |
| 1347 prefix(adr); | |
| 1348 emit_byte(0xFF); | |
| 1349 emit_operand(rsp, adr); | |
| 1350 } | |
| 1351 | |
| 1352 void Assembler::jmp(Label& L, relocInfo::relocType rtype) { | |
| 1353 if (L.is_bound()) { | |
| 1354 address entry = target(L); | |
| 1355 assert(entry != NULL, "jmp most probably wrong"); | |
| 1356 InstructionMark im(this); | |
| 1357 const int short_size = 2; | |
| 1358 const int long_size = 5; | |
| 1359 intptr_t offs = entry - _code_pos; | |
| 1360 if (rtype == relocInfo::none && is8bit(offs - short_size)) { | |
| 1361 emit_byte(0xEB); | |
| 1362 emit_byte((offs - short_size) & 0xFF); | |
| 1363 } else { | |
| 1364 emit_byte(0xE9); | |
| 1365 emit_long(offs - long_size); | |
| 1366 } | |
| 1367 } else { | |
| 1368 // By default, forward jumps are always 32-bit displacements, since | |
| 1369 // we can't yet know where the label will be bound. If you're sure that | |
| 1370 // the forward jump will not run beyond 256 bytes, use jmpb to | |
| 1371 // force an 8-bit displacement. | |
| 1372 InstructionMark im(this); | |
| 1373 relocate(rtype); | |
| 1374 L.add_patch_at(code(), locator()); | |
| 1375 emit_byte(0xE9); | |
| 1376 emit_long(0); | |
| 1377 } | |
| 1378 } | |
| 1379 | |
| 1380 void Assembler::jmp(Register entry) { | |
| 1381 int encode = prefix_and_encode(entry->encoding()); | |
| 1382 emit_byte(0xFF); | |
| 1383 emit_byte(0xE0 | encode); | |
| 1384 } | |
| 1385 | |
| 1386 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) { | |
| 1387 InstructionMark im(this); | |
| 1388 emit_byte(0xE9); | |
| 1389 assert(dest != NULL, "must have a target"); | |
| 1390 intptr_t disp = dest - (_code_pos + sizeof(int32_t)); | |
| 1391 assert(is_simm32(disp), "must be 32bit offset (jmp)"); | |
| 1392 emit_data(disp, rspec.reloc(), call32_operand); | |
| 1393 } | |
| 1394 | |
| 1395 void Assembler::jmpb(Label& L) { | |
| 1396 if (L.is_bound()) { | |
| 1397 const int short_size = 2; | |
| 1398 address entry = target(L); | |
| 1399 assert(is8bit((entry - _code_pos) + short_size), | |
| 1400 "Dispacement too large for a short jmp"); | |
| 1401 assert(entry != NULL, "jmp most probably wrong"); | |
| 1402 intptr_t offs = entry - _code_pos; | |
| 1403 emit_byte(0xEB); | |
| 1404 emit_byte((offs - short_size) & 0xFF); | |
| 1405 } else { | |
| 1406 InstructionMark im(this); | |
| 1407 L.add_patch_at(code(), locator()); | |
| 1408 emit_byte(0xEB); | |
| 1409 emit_byte(0); | |
| 1410 } | |
| 1411 } | |
| 1412 | |
| 1413 void Assembler::ldmxcsr( Address src) { | |
| 1414 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1415 InstructionMark im(this); | |
| 1416 prefix(src); | |
| 1417 emit_byte(0x0F); | |
| 1418 emit_byte(0xAE); | |
| 1419 emit_operand(as_Register(2), src); | |
| 1420 } | |
| 1421 | |
| 1422 void Assembler::leal(Register dst, Address src) { | |
| 1423 InstructionMark im(this); | |
| 1424 #ifdef _LP64 | |
| 1425 emit_byte(0x67); // addr32 | |
| 1426 prefix(src, dst); | |
| 1427 #endif // LP64 | |
| 1428 emit_byte(0x8D); | |
| 1429 emit_operand(dst, src); | |
| 1430 } | |
| 1431 | |
| 1432 void Assembler::lock() { | |
| 1433 if (Atomics & 1) { | |
| 1434 // Emit either nothing, a NOP, or a NOP: prefix | |
| 1435 emit_byte(0x90) ; | |
| 1436 } else { | |
| 1437 emit_byte(0xF0); | |
| 1438 } | |
| 1439 } | |
| 1440 | |
| 1441 // Serializes memory. | |
| 1442 void Assembler::mfence() { | |
| 1443 // Memory barriers are only needed on multiprocessors | |
| 1444 if (os::is_MP()) { | |
| 1445 if( LP64_ONLY(true ||) VM_Version::supports_sse2() ) { | |
| 1446 emit_byte( 0x0F ); // MFENCE; faster blows no regs | |
| 1447 emit_byte( 0xAE ); | |
| 1448 emit_byte( 0xF0 ); | |
| 1449 } else { | |
| 1450 // All usable chips support "locked" instructions which suffice | |
| 1451 // as barriers, and are much faster than the alternative of | |
| 1452 // using cpuid instruction. We use here a locked add [esp],0. | |
| 1453 // This is conveniently otherwise a no-op except for blowing | |
| 1454 // flags (which we save and restore.) | |
| 1455 pushf(); // Save eflags register | |
| 1456 lock(); | |
| 1457 addl(Address(rsp, 0), 0);// Assert the lock# signal here | |
| 1458 popf(); // Restore eflags register | |
| 1459 } | |
| 1460 } | |
| 1461 } | |
| 1462 | |
| 1463 void Assembler::mov(Register dst, Register src) { | |
| 1464 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
| 1465 } | |
| 1466 | |
| 1467 void Assembler::movapd(XMMRegister dst, XMMRegister src) { | |
| 1468 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1469 int dstenc = dst->encoding(); | |
| 1470 int srcenc = src->encoding(); | |
| 1471 emit_byte(0x66); | |
| 1472 if (dstenc < 8) { | |
| 1473 if (srcenc >= 8) { | |
| 1474 prefix(REX_B); | |
| 1475 srcenc -= 8; | |
| 1476 } | |
| 1477 } else { | |
| 1478 if (srcenc < 8) { | |
| 1479 prefix(REX_R); | |
| 1480 } else { | |
| 1481 prefix(REX_RB); | |
| 1482 srcenc -= 8; | |
| 1483 } | |
| 1484 dstenc -= 8; | |
| 1485 } | |
| 1486 emit_byte(0x0F); | |
| 1487 emit_byte(0x28); | |
| 1488 emit_byte(0xC0 | dstenc << 3 | srcenc); | |
| 1489 } | |
| 1490 | |
| 1491 void Assembler::movaps(XMMRegister dst, XMMRegister src) { | |
| 1492 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1493 int dstenc = dst->encoding(); | |
| 1494 int srcenc = src->encoding(); | |
| 1495 if (dstenc < 8) { | |
| 1496 if (srcenc >= 8) { | |
| 1497 prefix(REX_B); | |
| 1498 srcenc -= 8; | |
| 1499 } | |
| 1500 } else { | |
| 1501 if (srcenc < 8) { | |
| 1502 prefix(REX_R); | |
| 1503 } else { | |
| 1504 prefix(REX_RB); | |
| 1505 srcenc -= 8; | |
| 1506 } | |
| 1507 dstenc -= 8; | |
| 1508 } | |
| 1509 emit_byte(0x0F); | |
| 1510 emit_byte(0x28); | |
| 1511 emit_byte(0xC0 | dstenc << 3 | srcenc); | |
| 1512 } | |
| 1513 | |
| 1514 void Assembler::movb(Register dst, Address src) { | |
| 1515 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); | |
| 1516 InstructionMark im(this); | |
| 1517 prefix(src, dst, true); | |
| 1518 emit_byte(0x8A); | |
| 1519 emit_operand(dst, src); | |
| 1520 } | |
| 1521 | |
| 1522 | |
| 1523 void Assembler::movb(Address dst, int imm8) { | |
| 1524 InstructionMark im(this); | |
| 1525 prefix(dst); | |
| 1526 emit_byte(0xC6); | |
| 1527 emit_operand(rax, dst, 1); | |
| 1528 emit_byte(imm8); | |
| 1529 } | |
| 1530 | |
| 1531 | |
| 1532 void Assembler::movb(Address dst, Register src) { | |
| 1533 assert(src->has_byte_register(), "must have byte register"); | |
| 1534 InstructionMark im(this); | |
| 1535 prefix(dst, src, true); | |
| 1536 emit_byte(0x88); | |
| 1537 emit_operand(src, dst); | |
| 1538 } | |
| 1539 | |
| 1540 void Assembler::movdl(XMMRegister dst, Register src) { | |
| 1541 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1542 emit_byte(0x66); | |
| 1543 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1544 emit_byte(0x0F); | |
| 1545 emit_byte(0x6E); | |
| 1546 emit_byte(0xC0 | encode); | |
| 1547 } | |
| 1548 | |
| 1549 void Assembler::movdl(Register dst, XMMRegister src) { | |
| 1550 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1551 emit_byte(0x66); | |
| 1552 // swap src/dst to get correct prefix | |
| 1553 int encode = prefix_and_encode(src->encoding(), dst->encoding()); | |
| 1554 emit_byte(0x0F); | |
| 1555 emit_byte(0x7E); | |
| 1556 emit_byte(0xC0 | encode); | |
| 1557 } | |
| 1558 | |
| 1559 void Assembler::movdqa(XMMRegister dst, Address src) { | |
| 1560 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1561 InstructionMark im(this); | |
| 1562 emit_byte(0x66); | |
| 1563 prefix(src, dst); | |
| 1564 emit_byte(0x0F); | |
| 1565 emit_byte(0x6F); | |
| 1566 emit_operand(dst, src); | |
| 1567 } | |
| 1568 | |
| 1569 void Assembler::movdqa(XMMRegister dst, XMMRegister src) { | |
| 1570 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1571 emit_byte(0x66); | |
| 1572 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 1573 emit_byte(0x0F); | |
| 1574 emit_byte(0x6F); | |
| 1575 emit_byte(0xC0 | encode); | |
| 1576 } | |
| 1577 | |
| 1578 void Assembler::movdqa(Address dst, XMMRegister src) { | |
| 1579 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1580 InstructionMark im(this); | |
| 1581 emit_byte(0x66); | |
| 1582 prefix(dst, src); | |
| 1583 emit_byte(0x0F); | |
| 1584 emit_byte(0x7F); | |
| 1585 emit_operand(src, dst); | |
| 1586 } | |
| 1587 | |
| 405 | 1588 void Assembler::movdqu(XMMRegister dst, Address src) { |
| 1589 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1590 InstructionMark im(this); | |
| 1591 emit_byte(0xF3); | |
| 1592 prefix(src, dst); | |
| 1593 emit_byte(0x0F); | |
| 1594 emit_byte(0x6F); | |
| 1595 emit_operand(dst, src); | |
| 1596 } | |
| 1597 | |
| 1598 void Assembler::movdqu(XMMRegister dst, XMMRegister src) { | |
| 1599 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1600 emit_byte(0xF3); | |
| 1601 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 1602 emit_byte(0x0F); | |
| 1603 emit_byte(0x6F); | |
| 1604 emit_byte(0xC0 | encode); | |
| 1605 } | |
| 1606 | |
| 1607 void Assembler::movdqu(Address dst, XMMRegister src) { | |
| 1608 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1609 InstructionMark im(this); | |
| 1610 emit_byte(0xF3); | |
| 1611 prefix(dst, src); | |
| 1612 emit_byte(0x0F); | |
| 1613 emit_byte(0x7F); | |
| 1614 emit_operand(src, dst); | |
| 1615 } | |
| 1616 | |
| 304 | 1617 // Uses zero extension on 64bit |
| 1618 | |
| 1619 void Assembler::movl(Register dst, int32_t imm32) { | |
| 1620 int encode = prefix_and_encode(dst->encoding()); | |
| 1621 emit_byte(0xB8 | encode); | |
| 1622 emit_long(imm32); | |
| 1623 } | |
| 1624 | |
| 1625 void Assembler::movl(Register dst, Register src) { | |
| 1626 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1627 emit_byte(0x8B); | |
| 1628 emit_byte(0xC0 | encode); | |
| 1629 } | |
| 1630 | |
| 1631 void Assembler::movl(Register dst, Address src) { | |
| 1632 InstructionMark im(this); | |
| 1633 prefix(src, dst); | |
| 1634 emit_byte(0x8B); | |
| 1635 emit_operand(dst, src); | |
| 1636 } | |
| 1637 | |
| 1638 void Assembler::movl(Address dst, int32_t imm32) { | |
| 1639 InstructionMark im(this); | |
| 1640 prefix(dst); | |
| 1641 emit_byte(0xC7); | |
| 1642 emit_operand(rax, dst, 4); | |
| 1643 emit_long(imm32); | |
| 1644 } | |
| 1645 | |
| 1646 void Assembler::movl(Address dst, Register src) { | |
| 1647 InstructionMark im(this); | |
| 1648 prefix(dst, src); | |
| 1649 emit_byte(0x89); | |
| 1650 emit_operand(src, dst); | |
| 1651 } | |
| 1652 | |
| 1653 // New cpus require to use movsd and movss to avoid partial register stall | |
| 1654 // when loading from memory. But for old Opteron use movlpd instead of movsd. | |
| 1655 // The selection is done in MacroAssembler::movdbl() and movflt(). | |
| 1656 void Assembler::movlpd(XMMRegister dst, Address src) { | |
| 1657 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1658 InstructionMark im(this); | |
| 1659 emit_byte(0x66); | |
| 1660 prefix(src, dst); | |
| 1661 emit_byte(0x0F); | |
| 1662 emit_byte(0x12); | |
| 1663 emit_operand(dst, src); | |
| 1664 } | |
| 1665 | |
| 1666 void Assembler::movq( MMXRegister dst, Address src ) { | |
| 1667 assert( VM_Version::supports_mmx(), "" ); | |
| 1668 emit_byte(0x0F); | |
| 1669 emit_byte(0x6F); | |
| 1670 emit_operand(dst, src); | |
| 1671 } | |
| 1672 | |
| 1673 void Assembler::movq( Address dst, MMXRegister src ) { | |
| 1674 assert( VM_Version::supports_mmx(), "" ); | |
| 1675 emit_byte(0x0F); | |
| 1676 emit_byte(0x7F); | |
| 1677 // workaround gcc (3.2.1-7a) bug | |
| 1678 // In that version of gcc with only an emit_operand(MMX, Address) | |
| 1679 // gcc will tail jump and try and reverse the parameters completely | |
| 1680 // obliterating dst in the process. By having a version available | |
| 1681 // that doesn't need to swap the args at the tail jump the bug is | |
| 1682 // avoided. | |
| 1683 emit_operand(dst, src); | |
| 1684 } | |
| 1685 | |
| 1686 void Assembler::movq(XMMRegister dst, Address src) { | |
| 1687 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1688 InstructionMark im(this); | |
| 1689 emit_byte(0xF3); | |
| 1690 prefix(src, dst); | |
| 1691 emit_byte(0x0F); | |
| 1692 emit_byte(0x7E); | |
| 1693 emit_operand(dst, src); | |
| 1694 } | |
| 1695 | |
| 1696 void Assembler::movq(Address dst, XMMRegister src) { | |
| 1697 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1698 InstructionMark im(this); | |
| 1699 emit_byte(0x66); | |
| 1700 prefix(dst, src); | |
| 1701 emit_byte(0x0F); | |
| 1702 emit_byte(0xD6); | |
| 1703 emit_operand(src, dst); | |
| 1704 } | |
| 1705 | |
| 1706 void Assembler::movsbl(Register dst, Address src) { // movsxb | |
| 1707 InstructionMark im(this); | |
| 1708 prefix(src, dst); | |
| 1709 emit_byte(0x0F); | |
| 1710 emit_byte(0xBE); | |
| 1711 emit_operand(dst, src); | |
| 1712 } | |
| 1713 | |
| 1714 void Assembler::movsbl(Register dst, Register src) { // movsxb | |
| 1715 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); | |
| 1716 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true); | |
| 1717 emit_byte(0x0F); | |
| 1718 emit_byte(0xBE); | |
| 1719 emit_byte(0xC0 | encode); | |
| 1720 } | |
| 1721 | |
| 1722 void Assembler::movsd(XMMRegister dst, XMMRegister src) { | |
| 1723 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1724 emit_byte(0xF2); | |
| 1725 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1726 emit_byte(0x0F); | |
| 1727 emit_byte(0x10); | |
| 1728 emit_byte(0xC0 | encode); | |
| 1729 } | |
| 1730 | |
| 1731 void Assembler::movsd(XMMRegister dst, Address src) { | |
| 1732 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1733 InstructionMark im(this); | |
| 1734 emit_byte(0xF2); | |
| 1735 prefix(src, dst); | |
| 1736 emit_byte(0x0F); | |
| 1737 emit_byte(0x10); | |
| 1738 emit_operand(dst, src); | |
| 1739 } | |
| 1740 | |
| 1741 void Assembler::movsd(Address dst, XMMRegister src) { | |
| 1742 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1743 InstructionMark im(this); | |
| 1744 emit_byte(0xF2); | |
| 1745 prefix(dst, src); | |
| 1746 emit_byte(0x0F); | |
| 1747 emit_byte(0x11); | |
| 1748 emit_operand(src, dst); | |
| 1749 } | |
| 1750 | |
| 1751 void Assembler::movss(XMMRegister dst, XMMRegister src) { | |
| 1752 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1753 emit_byte(0xF3); | |
| 1754 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1755 emit_byte(0x0F); | |
| 1756 emit_byte(0x10); | |
| 1757 emit_byte(0xC0 | encode); | |
| 1758 } | |
| 1759 | |
| 1760 void Assembler::movss(XMMRegister dst, Address src) { | |
| 1761 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1762 InstructionMark im(this); | |
| 1763 emit_byte(0xF3); | |
| 1764 prefix(src, dst); | |
| 1765 emit_byte(0x0F); | |
| 1766 emit_byte(0x10); | |
| 1767 emit_operand(dst, src); | |
| 1768 } | |
| 1769 | |
| 1770 void Assembler::movss(Address dst, XMMRegister src) { | |
| 1771 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1772 InstructionMark im(this); | |
| 1773 emit_byte(0xF3); | |
| 1774 prefix(dst, src); | |
| 1775 emit_byte(0x0F); | |
| 1776 emit_byte(0x11); | |
| 1777 emit_operand(src, dst); | |
| 1778 } | |
| 1779 | |
| 1780 void Assembler::movswl(Register dst, Address src) { // movsxw | |
| 1781 InstructionMark im(this); | |
| 1782 prefix(src, dst); | |
| 1783 emit_byte(0x0F); | |
| 1784 emit_byte(0xBF); | |
| 1785 emit_operand(dst, src); | |
| 1786 } | |
| 1787 | |
| 1788 void Assembler::movswl(Register dst, Register src) { // movsxw | |
| 1789 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1790 emit_byte(0x0F); | |
| 1791 emit_byte(0xBF); | |
| 1792 emit_byte(0xC0 | encode); | |
| 1793 } | |
| 1794 | |
| 1795 void Assembler::movw(Address dst, int imm16) { | |
| 1796 InstructionMark im(this); | |
| 1797 | |
| 1798 emit_byte(0x66); // switch to 16-bit mode | |
| 1799 prefix(dst); | |
| 1800 emit_byte(0xC7); | |
| 1801 emit_operand(rax, dst, 2); | |
| 1802 emit_word(imm16); | |
| 1803 } | |
| 1804 | |
| 1805 void Assembler::movw(Register dst, Address src) { | |
| 1806 InstructionMark im(this); | |
| 1807 emit_byte(0x66); | |
| 1808 prefix(src, dst); | |
| 1809 emit_byte(0x8B); | |
| 1810 emit_operand(dst, src); | |
| 1811 } | |
| 1812 | |
| 1813 void Assembler::movw(Address dst, Register src) { | |
| 1814 InstructionMark im(this); | |
| 1815 emit_byte(0x66); | |
| 1816 prefix(dst, src); | |
| 1817 emit_byte(0x89); | |
| 1818 emit_operand(src, dst); | |
| 1819 } | |
| 1820 | |
| 1821 void Assembler::movzbl(Register dst, Address src) { // movzxb | |
| 1822 InstructionMark im(this); | |
| 1823 prefix(src, dst); | |
| 1824 emit_byte(0x0F); | |
| 1825 emit_byte(0xB6); | |
| 1826 emit_operand(dst, src); | |
| 1827 } | |
| 1828 | |
| 1829 void Assembler::movzbl(Register dst, Register src) { // movzxb | |
| 1830 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); | |
| 1831 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true); | |
| 1832 emit_byte(0x0F); | |
| 1833 emit_byte(0xB6); | |
| 1834 emit_byte(0xC0 | encode); | |
| 1835 } | |
| 1836 | |
| 1837 void Assembler::movzwl(Register dst, Address src) { // movzxw | |
| 1838 InstructionMark im(this); | |
| 1839 prefix(src, dst); | |
| 1840 emit_byte(0x0F); | |
| 1841 emit_byte(0xB7); | |
| 1842 emit_operand(dst, src); | |
| 1843 } | |
| 1844 | |
| 1845 void Assembler::movzwl(Register dst, Register src) { // movzxw | |
| 1846 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1847 emit_byte(0x0F); | |
| 1848 emit_byte(0xB7); | |
| 1849 emit_byte(0xC0 | encode); | |
| 1850 } | |
| 1851 | |
| 1852 void Assembler::mull(Address src) { | |
| 1853 InstructionMark im(this); | |
| 1854 prefix(src); | |
| 1855 emit_byte(0xF7); | |
| 1856 emit_operand(rsp, src); | |
| 1857 } | |
| 1858 | |
| 1859 void Assembler::mull(Register src) { | |
| 1860 int encode = prefix_and_encode(src->encoding()); | |
| 1861 emit_byte(0xF7); | |
| 1862 emit_byte(0xE0 | encode); | |
| 1863 } | |
| 1864 | |
| 1865 void Assembler::mulsd(XMMRegister dst, Address src) { | |
| 1866 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1867 InstructionMark im(this); | |
| 1868 emit_byte(0xF2); | |
| 1869 prefix(src, dst); | |
| 1870 emit_byte(0x0F); | |
| 1871 emit_byte(0x59); | |
| 1872 emit_operand(dst, src); | |
| 1873 } | |
| 1874 | |
| 1875 void Assembler::mulsd(XMMRegister dst, XMMRegister src) { | |
| 1876 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1877 emit_byte(0xF2); | |
| 1878 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1879 emit_byte(0x0F); | |
| 1880 emit_byte(0x59); | |
| 1881 emit_byte(0xC0 | encode); | |
| 1882 } | |
| 1883 | |
| 1884 void Assembler::mulss(XMMRegister dst, Address src) { | |
| 1885 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1886 InstructionMark im(this); | |
| 1887 emit_byte(0xF3); | |
| 1888 prefix(src, dst); | |
| 1889 emit_byte(0x0F); | |
| 1890 emit_byte(0x59); | |
| 1891 emit_operand(dst, src); | |
| 1892 } | |
| 1893 | |
| 1894 void Assembler::mulss(XMMRegister dst, XMMRegister src) { | |
| 1895 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1896 emit_byte(0xF3); | |
| 1897 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1898 emit_byte(0x0F); | |
| 1899 emit_byte(0x59); | |
| 1900 emit_byte(0xC0 | encode); | |
| 1901 } | |
| 1902 | |
| 1903 void Assembler::negl(Register dst) { | |
| 1904 int encode = prefix_and_encode(dst->encoding()); | |
| 1905 emit_byte(0xF7); | |
| 1906 emit_byte(0xD8 | encode); | |
| 1907 } | |
| 1908 | |
| 0 | 1909 void Assembler::nop(int i) { |
| 304 | 1910 #ifdef ASSERT |
| 0 | 1911 assert(i > 0, " "); |
| 304 | 1912 // The fancy nops aren't currently recognized by debuggers making it a |
| 1913 // pain to disassemble code while debugging. If asserts are on clearly | |
| 1914 // speed is not an issue so simply use the single byte traditional nop | |
| 1915 // to do alignment. | |
| 1916 | |
| 1917 for (; i > 0 ; i--) emit_byte(0x90); | |
| 1918 return; | |
| 1919 | |
| 1920 #endif // ASSERT | |
| 1921 | |
| 0 | 1922 if (UseAddressNop && VM_Version::is_intel()) { |
| 1923 // | |
| 1924 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel | |
| 1925 // 1: 0x90 | |
| 1926 // 2: 0x66 0x90 | |
| 1927 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) | |
| 1928 // 4: 0x0F 0x1F 0x40 0x00 | |
| 1929 // 5: 0x0F 0x1F 0x44 0x00 0x00 | |
| 1930 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
| 1931 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
| 1932 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 1933 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 1934 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 1935 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 1936 | |
| 1937 // The rest coding is Intel specific - don't use consecutive address nops | |
| 1938 | |
| 1939 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
| 1940 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
| 1941 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
| 1942 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
| 1943 | |
| 1944 while(i >= 15) { | |
| 1945 // For Intel don't generate consecutive addess nops (mix with regular nops) | |
| 1946 i -= 15; | |
| 1947 emit_byte(0x66); // size prefix | |
| 1948 emit_byte(0x66); // size prefix | |
| 1949 emit_byte(0x66); // size prefix | |
| 1950 addr_nop_8(); | |
| 1951 emit_byte(0x66); // size prefix | |
| 1952 emit_byte(0x66); // size prefix | |
| 1953 emit_byte(0x66); // size prefix | |
| 1954 emit_byte(0x90); // nop | |
| 1955 } | |
| 1956 switch (i) { | |
| 1957 case 14: | |
| 1958 emit_byte(0x66); // size prefix | |
| 1959 case 13: | |
| 1960 emit_byte(0x66); // size prefix | |
| 1961 case 12: | |
| 1962 addr_nop_8(); | |
| 1963 emit_byte(0x66); // size prefix | |
| 1964 emit_byte(0x66); // size prefix | |
| 1965 emit_byte(0x66); // size prefix | |
| 1966 emit_byte(0x90); // nop | |
| 1967 break; | |
| 1968 case 11: | |
| 1969 emit_byte(0x66); // size prefix | |
| 1970 case 10: | |
| 1971 emit_byte(0x66); // size prefix | |
| 1972 case 9: | |
| 1973 emit_byte(0x66); // size prefix | |
| 1974 case 8: | |
| 1975 addr_nop_8(); | |
| 1976 break; | |
| 1977 case 7: | |
| 1978 addr_nop_7(); | |
| 1979 break; | |
| 1980 case 6: | |
| 1981 emit_byte(0x66); // size prefix | |
| 1982 case 5: | |
| 1983 addr_nop_5(); | |
| 1984 break; | |
| 1985 case 4: | |
| 1986 addr_nop_4(); | |
| 1987 break; | |
| 1988 case 3: | |
| 1989 // Don't use "0x0F 0x1F 0x00" - need patching safe padding | |
| 1990 emit_byte(0x66); // size prefix | |
| 1991 case 2: | |
| 1992 emit_byte(0x66); // size prefix | |
| 1993 case 1: | |
| 1994 emit_byte(0x90); // nop | |
| 1995 break; | |
| 1996 default: | |
| 1997 assert(i == 0, " "); | |
| 1998 } | |
| 1999 return; | |
| 2000 } | |
| 2001 if (UseAddressNop && VM_Version::is_amd()) { | |
| 2002 // | |
| 2003 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD. | |
| 2004 // 1: 0x90 | |
| 2005 // 2: 0x66 0x90 | |
| 2006 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) | |
| 2007 // 4: 0x0F 0x1F 0x40 0x00 | |
| 2008 // 5: 0x0F 0x1F 0x44 0x00 0x00 | |
| 2009 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
| 2010 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
| 2011 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 2012 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 2013 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 2014 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 2015 | |
| 2016 // The rest coding is AMD specific - use consecutive address nops | |
| 2017 | |
| 2018 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
| 2019 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
| 2020 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
| 2021 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
| 2022 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 2023 // Size prefixes (0x66) are added for larger sizes | |
| 2024 | |
| 2025 while(i >= 22) { | |
| 2026 i -= 11; | |
| 2027 emit_byte(0x66); // size prefix | |
| 2028 emit_byte(0x66); // size prefix | |
| 2029 emit_byte(0x66); // size prefix | |
| 2030 addr_nop_8(); | |
| 2031 } | |
| 2032 // Generate first nop for size between 21-12 | |
| 2033 switch (i) { | |
| 2034 case 21: | |
| 2035 i -= 1; | |
| 2036 emit_byte(0x66); // size prefix | |
| 2037 case 20: | |
| 2038 case 19: | |
| 2039 i -= 1; | |
| 2040 emit_byte(0x66); // size prefix | |
| 2041 case 18: | |
| 2042 case 17: | |
| 2043 i -= 1; | |
| 2044 emit_byte(0x66); // size prefix | |
| 2045 case 16: | |
| 2046 case 15: | |
| 2047 i -= 8; | |
| 2048 addr_nop_8(); | |
| 2049 break; | |
| 2050 case 14: | |
| 2051 case 13: | |
| 2052 i -= 7; | |
| 2053 addr_nop_7(); | |
| 2054 break; | |
| 2055 case 12: | |
| 2056 i -= 6; | |
| 2057 emit_byte(0x66); // size prefix | |
| 2058 addr_nop_5(); | |
| 2059 break; | |
| 2060 default: | |
| 2061 assert(i < 12, " "); | |
| 2062 } | |
| 2063 | |
| 2064 // Generate second nop for size between 11-1 | |
| 2065 switch (i) { | |
| 2066 case 11: | |
| 2067 emit_byte(0x66); // size prefix | |
| 2068 case 10: | |
| 2069 emit_byte(0x66); // size prefix | |
| 2070 case 9: | |
| 2071 emit_byte(0x66); // size prefix | |
| 2072 case 8: | |
| 2073 addr_nop_8(); | |
| 2074 break; | |
| 2075 case 7: | |
| 2076 addr_nop_7(); | |
| 2077 break; | |
| 2078 case 6: | |
| 2079 emit_byte(0x66); // size prefix | |
| 2080 case 5: | |
| 2081 addr_nop_5(); | |
| 2082 break; | |
| 2083 case 4: | |
| 2084 addr_nop_4(); | |
| 2085 break; | |
| 2086 case 3: | |
| 2087 // Don't use "0x0F 0x1F 0x00" - need patching safe padding | |
| 2088 emit_byte(0x66); // size prefix | |
| 2089 case 2: | |
| 2090 emit_byte(0x66); // size prefix | |
| 2091 case 1: | |
| 2092 emit_byte(0x90); // nop | |
| 2093 break; | |
| 2094 default: | |
| 2095 assert(i == 0, " "); | |
| 2096 } | |
| 2097 return; | |
| 2098 } | |
| 2099 | |
| 2100 // Using nops with size prefixes "0x66 0x90". | |
| 2101 // From AMD Optimization Guide: | |
| 2102 // 1: 0x90 | |
| 2103 // 2: 0x66 0x90 | |
| 2104 // 3: 0x66 0x66 0x90 | |
| 2105 // 4: 0x66 0x66 0x66 0x90 | |
| 2106 // 5: 0x66 0x66 0x90 0x66 0x90 | |
| 2107 // 6: 0x66 0x66 0x90 0x66 0x66 0x90 | |
| 2108 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 | |
| 2109 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90 | |
| 2110 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 | |
| 2111 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 | |
| 2112 // | |
| 2113 while(i > 12) { | |
| 2114 i -= 4; | |
| 2115 emit_byte(0x66); // size prefix | |
| 2116 emit_byte(0x66); | |
| 2117 emit_byte(0x66); | |
| 2118 emit_byte(0x90); // nop | |
| 2119 } | |
| 2120 // 1 - 12 nops | |
| 2121 if(i > 8) { | |
| 2122 if(i > 9) { | |
| 2123 i -= 1; | |
| 2124 emit_byte(0x66); | |
| 2125 } | |
| 2126 i -= 3; | |
| 2127 emit_byte(0x66); | |
| 2128 emit_byte(0x66); | |
| 2129 emit_byte(0x90); | |
| 2130 } | |
| 2131 // 1 - 8 nops | |
| 2132 if(i > 4) { | |
| 2133 if(i > 6) { | |
| 2134 i -= 1; | |
| 2135 emit_byte(0x66); | |
| 2136 } | |
| 2137 i -= 3; | |
| 2138 emit_byte(0x66); | |
| 2139 emit_byte(0x66); | |
| 2140 emit_byte(0x90); | |
| 2141 } | |
| 2142 switch (i) { | |
| 2143 case 4: | |
| 2144 emit_byte(0x66); | |
| 2145 case 3: | |
| 2146 emit_byte(0x66); | |
| 2147 case 2: | |
| 2148 emit_byte(0x66); | |
| 2149 case 1: | |
| 2150 emit_byte(0x90); | |
| 2151 break; | |
| 2152 default: | |
| 2153 assert(i == 0, " "); | |
| 2154 } | |
| 2155 } | |
| 2156 | |
| 304 | 2157 void Assembler::notl(Register dst) { |
| 2158 int encode = prefix_and_encode(dst->encoding()); | |
| 2159 emit_byte(0xF7); | |
| 2160 emit_byte(0xD0 | encode ); | |
| 2161 } | |
| 2162 | |
| 2163 void Assembler::orl(Address dst, int32_t imm32) { | |
| 2164 InstructionMark im(this); | |
| 2165 prefix(dst); | |
| 2166 emit_byte(0x81); | |
| 2167 emit_operand(rcx, dst, 4); | |
| 2168 emit_long(imm32); | |
| 2169 } | |
| 2170 | |
| 2171 void Assembler::orl(Register dst, int32_t imm32) { | |
| 2172 prefix(dst); | |
| 2173 emit_arith(0x81, 0xC8, dst, imm32); | |
| 2174 } | |
| 2175 | |
| 2176 | |
| 2177 void Assembler::orl(Register dst, Address src) { | |
| 2178 InstructionMark im(this); | |
| 2179 prefix(src, dst); | |
| 2180 emit_byte(0x0B); | |
| 2181 emit_operand(dst, src); | |
| 2182 } | |
| 2183 | |
| 2184 | |
| 2185 void Assembler::orl(Register dst, Register src) { | |
| 2186 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2187 emit_arith(0x0B, 0xC0, dst, src); | |
| 2188 } | |
| 2189 | |
| 2190 // generic | |
| 2191 void Assembler::pop(Register dst) { | |
| 2192 int encode = prefix_and_encode(dst->encoding()); | |
| 2193 emit_byte(0x58 | encode); | |
| 2194 } | |
| 2195 | |
| 2196 void Assembler::popf() { | |
| 2197 emit_byte(0x9D); | |
| 2198 } | |
| 2199 | |
| 2200 void Assembler::popl(Address dst) { | |
| 2201 // NOTE: this will adjust stack by 8byte on 64bits | |
| 2202 InstructionMark im(this); | |
| 2203 prefix(dst); | |
| 2204 emit_byte(0x8F); | |
| 2205 emit_operand(rax, dst); | |
| 2206 } | |
| 2207 | |
| 2208 void Assembler::prefetch_prefix(Address src) { | |
| 2209 prefix(src); | |
| 2210 emit_byte(0x0F); | |
| 2211 } | |
| 2212 | |
| 2213 void Assembler::prefetchnta(Address src) { | |
| 2214 NOT_LP64(assert(VM_Version::supports_sse2(), "must support")); | |
| 2215 InstructionMark im(this); | |
| 2216 prefetch_prefix(src); | |
| 2217 emit_byte(0x18); | |
| 2218 emit_operand(rax, src); // 0, src | |
| 2219 } | |
| 2220 | |
| 2221 void Assembler::prefetchr(Address src) { | |
| 2222 NOT_LP64(assert(VM_Version::supports_3dnow(), "must support")); | |
| 2223 InstructionMark im(this); | |
| 2224 prefetch_prefix(src); | |
| 2225 emit_byte(0x0D); | |
| 2226 emit_operand(rax, src); // 0, src | |
| 2227 } | |
| 2228 | |
| 2229 void Assembler::prefetcht0(Address src) { | |
| 2230 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |
| 2231 InstructionMark im(this); | |
| 2232 prefetch_prefix(src); | |
| 2233 emit_byte(0x18); | |
| 2234 emit_operand(rcx, src); // 1, src | |
| 2235 } | |
| 2236 | |
| 2237 void Assembler::prefetcht1(Address src) { | |
| 2238 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |
| 2239 InstructionMark im(this); | |
| 2240 prefetch_prefix(src); | |
| 2241 emit_byte(0x18); | |
| 2242 emit_operand(rdx, src); // 2, src | |
| 2243 } | |
| 2244 | |
| 2245 void Assembler::prefetcht2(Address src) { | |
| 2246 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |
| 2247 InstructionMark im(this); | |
| 2248 prefetch_prefix(src); | |
| 2249 emit_byte(0x18); | |
| 2250 emit_operand(rbx, src); // 3, src | |
| 2251 } | |
| 2252 | |
| 2253 void Assembler::prefetchw(Address src) { | |
| 2254 NOT_LP64(assert(VM_Version::supports_3dnow(), "must support")); | |
| 2255 InstructionMark im(this); | |
| 2256 prefetch_prefix(src); | |
| 2257 emit_byte(0x0D); | |
| 2258 emit_operand(rcx, src); // 1, src | |
| 2259 } | |
| 2260 | |
| 2261 void Assembler::prefix(Prefix p) { | |
| 2262 a_byte(p); | |
| 2263 } | |
| 2264 | |
| 2265 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) { | |
| 2266 assert(isByte(mode), "invalid value"); | |
| 2267 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2268 | |
| 2269 emit_byte(0x66); | |
| 2270 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2271 emit_byte(0x0F); | |
| 2272 emit_byte(0x70); | |
| 2273 emit_byte(0xC0 | encode); | |
| 2274 emit_byte(mode & 0xFF); | |
| 2275 | |
| 2276 } | |
| 2277 | |
| 2278 void Assembler::pshufd(XMMRegister dst, Address src, int mode) { | |
| 2279 assert(isByte(mode), "invalid value"); | |
| 2280 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2281 | |
| 2282 InstructionMark im(this); | |
| 2283 emit_byte(0x66); | |
| 2284 prefix(src, dst); | |
| 2285 emit_byte(0x0F); | |
| 2286 emit_byte(0x70); | |
| 2287 emit_operand(dst, src); | |
| 2288 emit_byte(mode & 0xFF); | |
| 2289 } | |
| 2290 | |
| 2291 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) { | |
| 2292 assert(isByte(mode), "invalid value"); | |
| 2293 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2294 | |
| 2295 emit_byte(0xF2); | |
| 2296 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2297 emit_byte(0x0F); | |
| 2298 emit_byte(0x70); | |
| 2299 emit_byte(0xC0 | encode); | |
| 2300 emit_byte(mode & 0xFF); | |
| 2301 } | |
| 2302 | |
| 2303 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) { | |
| 2304 assert(isByte(mode), "invalid value"); | |
| 2305 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2306 | |
| 2307 InstructionMark im(this); | |
| 2308 emit_byte(0xF2); | |
| 2309 prefix(src, dst); // QQ new | |
| 2310 emit_byte(0x0F); | |
| 2311 emit_byte(0x70); | |
| 2312 emit_operand(dst, src); | |
| 2313 emit_byte(mode & 0xFF); | |
| 2314 } | |
| 2315 | |
| 2316 void Assembler::psrlq(XMMRegister dst, int shift) { | |
| 2317 // HMM Table D-1 says sse2 or mmx | |
| 2318 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 2319 | |
| 2320 int encode = prefixq_and_encode(xmm2->encoding(), dst->encoding()); | |
| 2321 emit_byte(0x66); | |
| 2322 emit_byte(0x0F); | |
| 2323 emit_byte(0x73); | |
| 2324 emit_byte(0xC0 | encode); | |
| 2325 emit_byte(shift); | |
| 2326 } | |
| 2327 | |
| 2328 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) { | |
| 2329 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2330 emit_byte(0x66); | |
| 2331 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2332 emit_byte(0x0F); | |
| 2333 emit_byte(0x60); | |
| 2334 emit_byte(0xC0 | encode); | |
| 2335 } | |
| 2336 | |
| 2337 void Assembler::push(int32_t imm32) { | |
| 2338 // in 64bits we push 64bits onto the stack but only | |
| 2339 // take a 32bit immediate | |
| 2340 emit_byte(0x68); | |
| 2341 emit_long(imm32); | |
| 2342 } | |
| 2343 | |
| 2344 void Assembler::push(Register src) { | |
| 2345 int encode = prefix_and_encode(src->encoding()); | |
| 2346 | |
| 2347 emit_byte(0x50 | encode); | |
| 2348 } | |
| 2349 | |
| 2350 void Assembler::pushf() { | |
| 2351 emit_byte(0x9C); | |
| 2352 } | |
| 2353 | |
| 2354 void Assembler::pushl(Address src) { | |
| 2355 // Note this will push 64bit on 64bit | |
| 2356 InstructionMark im(this); | |
| 2357 prefix(src); | |
| 2358 emit_byte(0xFF); | |
| 2359 emit_operand(rsi, src); | |
| 2360 } | |
| 2361 | |
| 2362 void Assembler::pxor(XMMRegister dst, Address src) { | |
| 2363 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2364 InstructionMark im(this); | |
| 2365 emit_byte(0x66); | |
| 2366 prefix(src, dst); | |
| 2367 emit_byte(0x0F); | |
| 2368 emit_byte(0xEF); | |
| 2369 emit_operand(dst, src); | |
| 2370 } | |
| 2371 | |
| 2372 void Assembler::pxor(XMMRegister dst, XMMRegister src) { | |
| 2373 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2374 InstructionMark im(this); | |
| 2375 emit_byte(0x66); | |
| 2376 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2377 emit_byte(0x0F); | |
| 2378 emit_byte(0xEF); | |
| 2379 emit_byte(0xC0 | encode); | |
| 2380 } | |
| 2381 | |
| 2382 void Assembler::rcll(Register dst, int imm8) { | |
| 2383 assert(isShiftCount(imm8), "illegal shift count"); | |
| 2384 int encode = prefix_and_encode(dst->encoding()); | |
| 2385 if (imm8 == 1) { | |
| 2386 emit_byte(0xD1); | |
| 2387 emit_byte(0xD0 | encode); | |
| 2388 } else { | |
| 2389 emit_byte(0xC1); | |
| 2390 emit_byte(0xD0 | encode); | |
| 2391 emit_byte(imm8); | |
| 2392 } | |
| 2393 } | |
| 2394 | |
| 2395 // copies data from [esi] to [edi] using rcx pointer sized words | |
| 2396 // generic | |
| 2397 void Assembler::rep_mov() { | |
| 2398 emit_byte(0xF3); | |
| 2399 // MOVSQ | |
| 2400 LP64_ONLY(prefix(REX_W)); | |
| 2401 emit_byte(0xA5); | |
| 2402 } | |
| 2403 | |
| 2404 // sets rcx pointer sized words with rax, value at [edi] | |
| 2405 // generic | |
| 2406 void Assembler::rep_set() { // rep_set | |
| 2407 emit_byte(0xF3); | |
| 2408 // STOSQ | |
| 2409 LP64_ONLY(prefix(REX_W)); | |
| 2410 emit_byte(0xAB); | |
| 2411 } | |
| 2412 | |
| 2413 // scans rcx pointer sized words at [edi] for occurance of rax, | |
| 2414 // generic | |
| 2415 void Assembler::repne_scan() { // repne_scan | |
| 2416 emit_byte(0xF2); | |
| 2417 // SCASQ | |
| 2418 LP64_ONLY(prefix(REX_W)); | |
| 2419 emit_byte(0xAF); | |
| 2420 } | |
| 2421 | |
| 2422 #ifdef _LP64 | |
| 2423 // scans rcx 4 byte words at [edi] for occurance of rax, | |
| 2424 // generic | |
| 2425 void Assembler::repne_scanl() { // repne_scan | |
| 2426 emit_byte(0xF2); | |
| 2427 // SCASL | |
| 2428 emit_byte(0xAF); | |
| 2429 } | |
| 2430 #endif | |
| 2431 | |
| 0 | 2432 void Assembler::ret(int imm16) { |
| 2433 if (imm16 == 0) { | |
| 2434 emit_byte(0xC3); | |
| 2435 } else { | |
| 2436 emit_byte(0xC2); | |
| 2437 emit_word(imm16); | |
| 2438 } | |
| 2439 } | |
| 2440 | |
| 304 | 2441 void Assembler::sahf() { |
| 2442 #ifdef _LP64 | |
| 2443 // Not supported in 64bit mode | |
| 2444 ShouldNotReachHere(); | |
| 2445 #endif | |
| 2446 emit_byte(0x9E); | |
| 2447 } | |
| 2448 | |
| 2449 void Assembler::sarl(Register dst, int imm8) { | |
| 2450 int encode = prefix_and_encode(dst->encoding()); | |
| 2451 assert(isShiftCount(imm8), "illegal shift count"); | |
| 2452 if (imm8 == 1) { | |
| 2453 emit_byte(0xD1); | |
| 2454 emit_byte(0xF8 | encode); | |
| 2455 } else { | |
| 2456 emit_byte(0xC1); | |
| 2457 emit_byte(0xF8 | encode); | |
| 2458 emit_byte(imm8); | |
| 2459 } | |
| 2460 } | |
| 2461 | |
| 2462 void Assembler::sarl(Register dst) { | |
| 2463 int encode = prefix_and_encode(dst->encoding()); | |
| 2464 emit_byte(0xD3); | |
| 2465 emit_byte(0xF8 | encode); | |
| 2466 } | |
| 2467 | |
| 2468 void Assembler::sbbl(Address dst, int32_t imm32) { | |
| 2469 InstructionMark im(this); | |
| 2470 prefix(dst); | |
| 2471 emit_arith_operand(0x81, rbx, dst, imm32); | |
| 2472 } | |
| 2473 | |
| 2474 void Assembler::sbbl(Register dst, int32_t imm32) { | |
| 2475 prefix(dst); | |
| 2476 emit_arith(0x81, 0xD8, dst, imm32); | |
| 2477 } | |
| 2478 | |
| 2479 | |
| 2480 void Assembler::sbbl(Register dst, Address src) { | |
| 2481 InstructionMark im(this); | |
| 2482 prefix(src, dst); | |
| 2483 emit_byte(0x1B); | |
| 2484 emit_operand(dst, src); | |
| 2485 } | |
| 2486 | |
| 2487 void Assembler::sbbl(Register dst, Register src) { | |
| 2488 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2489 emit_arith(0x1B, 0xC0, dst, src); | |
| 2490 } | |
| 2491 | |
| 2492 void Assembler::setb(Condition cc, Register dst) { | |
| 2493 assert(0 <= cc && cc < 16, "illegal cc"); | |
| 2494 int encode = prefix_and_encode(dst->encoding(), true); | |
| 0 | 2495 emit_byte(0x0F); |
| 304 | 2496 emit_byte(0x90 | cc); |
| 2497 emit_byte(0xC0 | encode); | |
| 2498 } | |
| 2499 | |
| 2500 void Assembler::shll(Register dst, int imm8) { | |
| 2501 assert(isShiftCount(imm8), "illegal shift count"); | |
| 2502 int encode = prefix_and_encode(dst->encoding()); | |
| 2503 if (imm8 == 1 ) { | |
| 2504 emit_byte(0xD1); | |
| 2505 emit_byte(0xE0 | encode); | |
| 2506 } else { | |
| 2507 emit_byte(0xC1); | |
| 2508 emit_byte(0xE0 | encode); | |
| 2509 emit_byte(imm8); | |
| 2510 } | |
| 2511 } | |
| 2512 | |
| 2513 void Assembler::shll(Register dst) { | |
| 2514 int encode = prefix_and_encode(dst->encoding()); | |
| 2515 emit_byte(0xD3); | |
| 2516 emit_byte(0xE0 | encode); | |
| 2517 } | |
| 2518 | |
| 2519 void Assembler::shrl(Register dst, int imm8) { | |
| 2520 assert(isShiftCount(imm8), "illegal shift count"); | |
| 2521 int encode = prefix_and_encode(dst->encoding()); | |
| 2522 emit_byte(0xC1); | |
| 2523 emit_byte(0xE8 | encode); | |
| 2524 emit_byte(imm8); | |
| 2525 } | |
| 2526 | |
| 2527 void Assembler::shrl(Register dst) { | |
| 2528 int encode = prefix_and_encode(dst->encoding()); | |
| 2529 emit_byte(0xD3); | |
| 2530 emit_byte(0xE8 | encode); | |
| 2531 } | |
| 0 | 2532 |
| 2533 // copies a single word from [esi] to [edi] | |
| 2534 void Assembler::smovl() { | |
| 2535 emit_byte(0xA5); | |
| 2536 } | |
| 2537 | |
| 304 | 2538 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) { |
| 2539 // HMM Table D-1 says sse2 | |
| 2540 // NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 2541 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2542 emit_byte(0xF2); | |
| 2543 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2544 emit_byte(0x0F); | |
| 2545 emit_byte(0x51); | |
| 2546 emit_byte(0xC0 | encode); | |
| 2547 } | |
| 2548 | |
| 2549 void Assembler::stmxcsr( Address dst) { | |
| 2550 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 2551 InstructionMark im(this); | |
| 2552 prefix(dst); | |
| 2553 emit_byte(0x0F); | |
| 2554 emit_byte(0xAE); | |
| 2555 emit_operand(as_Register(3), dst); | |
| 2556 } | |
| 2557 | |
| 2558 void Assembler::subl(Address dst, int32_t imm32) { | |
| 2559 InstructionMark im(this); | |
| 2560 prefix(dst); | |
| 2561 if (is8bit(imm32)) { | |
| 2562 emit_byte(0x83); | |
| 2563 emit_operand(rbp, dst, 1); | |
| 2564 emit_byte(imm32 & 0xFF); | |
| 2565 } else { | |
| 2566 emit_byte(0x81); | |
| 2567 emit_operand(rbp, dst, 4); | |
| 2568 emit_long(imm32); | |
| 2569 } | |
| 2570 } | |
| 2571 | |
| 2572 void Assembler::subl(Register dst, int32_t imm32) { | |
| 2573 prefix(dst); | |
| 2574 emit_arith(0x81, 0xE8, dst, imm32); | |
| 2575 } | |
| 2576 | |
| 2577 void Assembler::subl(Address dst, Register src) { | |
| 2578 InstructionMark im(this); | |
| 2579 prefix(dst, src); | |
| 2580 emit_byte(0x29); | |
| 2581 emit_operand(src, dst); | |
| 2582 } | |
| 2583 | |
| 2584 void Assembler::subl(Register dst, Address src) { | |
| 2585 InstructionMark im(this); | |
| 2586 prefix(src, dst); | |
| 2587 emit_byte(0x2B); | |
| 2588 emit_operand(dst, src); | |
| 2589 } | |
| 2590 | |
| 2591 void Assembler::subl(Register dst, Register src) { | |
| 2592 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2593 emit_arith(0x2B, 0xC0, dst, src); | |
| 2594 } | |
| 2595 | |
| 2596 void Assembler::subsd(XMMRegister dst, XMMRegister src) { | |
| 2597 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2598 emit_byte(0xF2); | |
| 2599 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2600 emit_byte(0x0F); | |
| 2601 emit_byte(0x5C); | |
| 2602 emit_byte(0xC0 | encode); | |
| 2603 } | |
| 2604 | |
| 2605 void Assembler::subsd(XMMRegister dst, Address src) { | |
| 2606 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2607 InstructionMark im(this); | |
| 2608 emit_byte(0xF2); | |
| 2609 prefix(src, dst); | |
| 2610 emit_byte(0x0F); | |
| 2611 emit_byte(0x5C); | |
| 2612 emit_operand(dst, src); | |
| 2613 } | |
| 2614 | |
| 2615 void Assembler::subss(XMMRegister dst, XMMRegister src) { | |
| 2616 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 0 | 2617 emit_byte(0xF3); |
| 304 | 2618 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
| 2619 emit_byte(0x0F); | |
| 2620 emit_byte(0x5C); | |
| 2621 emit_byte(0xC0 | encode); | |
| 2622 } | |
| 2623 | |
| 2624 void Assembler::subss(XMMRegister dst, Address src) { | |
| 2625 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 2626 InstructionMark im(this); | |
| 2627 emit_byte(0xF3); | |
| 2628 prefix(src, dst); | |
| 2629 emit_byte(0x0F); | |
| 2630 emit_byte(0x5C); | |
| 2631 emit_operand(dst, src); | |
| 2632 } | |
| 2633 | |
| 2634 void Assembler::testb(Register dst, int imm8) { | |
| 2635 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); | |
| 2636 (void) prefix_and_encode(dst->encoding(), true); | |
| 2637 emit_arith_b(0xF6, 0xC0, dst, imm8); | |
| 2638 } | |
| 2639 | |
| 2640 void Assembler::testl(Register dst, int32_t imm32) { | |
| 2641 // not using emit_arith because test | |
| 2642 // doesn't support sign-extension of | |
| 2643 // 8bit operands | |
| 2644 int encode = dst->encoding(); | |
| 2645 if (encode == 0) { | |
| 2646 emit_byte(0xA9); | |
| 2647 } else { | |
| 2648 encode = prefix_and_encode(encode); | |
| 2649 emit_byte(0xF7); | |
| 2650 emit_byte(0xC0 | encode); | |
| 2651 } | |
| 2652 emit_long(imm32); | |
| 2653 } | |
| 2654 | |
| 2655 void Assembler::testl(Register dst, Register src) { | |
| 2656 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2657 emit_arith(0x85, 0xC0, dst, src); | |
| 2658 } | |
| 2659 | |
| 2660 void Assembler::testl(Register dst, Address src) { | |
| 2661 InstructionMark im(this); | |
| 2662 prefix(src, dst); | |
| 2663 emit_byte(0x85); | |
| 2664 emit_operand(dst, src); | |
| 2665 } | |
| 2666 | |
| 2667 void Assembler::ucomisd(XMMRegister dst, Address src) { | |
| 2668 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2669 emit_byte(0x66); | |
| 2670 ucomiss(dst, src); | |
| 2671 } | |
| 2672 | |
| 2673 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) { | |
| 2674 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2675 emit_byte(0x66); | |
| 2676 ucomiss(dst, src); | |
| 2677 } | |
| 2678 | |
| 2679 void Assembler::ucomiss(XMMRegister dst, Address src) { | |
| 2680 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 2681 | |
| 2682 InstructionMark im(this); | |
| 2683 prefix(src, dst); | |
| 2684 emit_byte(0x0F); | |
| 2685 emit_byte(0x2E); | |
| 2686 emit_operand(dst, src); | |
| 2687 } | |
| 2688 | |
| 2689 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) { | |
| 2690 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 2691 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2692 emit_byte(0x0F); | |
| 2693 emit_byte(0x2E); | |
| 2694 emit_byte(0xC0 | encode); | |
| 2695 } | |
| 2696 | |
| 2697 | |
| 2698 void Assembler::xaddl(Address dst, Register src) { | |
| 2699 InstructionMark im(this); | |
| 2700 prefix(dst, src); | |
| 0 | 2701 emit_byte(0x0F); |
| 304 | 2702 emit_byte(0xC1); |
| 2703 emit_operand(src, dst); | |
| 2704 } | |
| 2705 | |
| 2706 void Assembler::xchgl(Register dst, Address src) { // xchg | |
| 2707 InstructionMark im(this); | |
| 2708 prefix(src, dst); | |
| 2709 emit_byte(0x87); | |
| 2710 emit_operand(dst, src); | |
| 2711 } | |
| 2712 | |
| 2713 void Assembler::xchgl(Register dst, Register src) { | |
| 2714 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2715 emit_byte(0x87); | |
| 2716 emit_byte(0xc0 | encode); | |
| 2717 } | |
| 2718 | |
| 2719 void Assembler::xorl(Register dst, int32_t imm32) { | |
| 2720 prefix(dst); | |
| 2721 emit_arith(0x81, 0xF0, dst, imm32); | |
| 2722 } | |
| 2723 | |
| 2724 void Assembler::xorl(Register dst, Address src) { | |
| 2725 InstructionMark im(this); | |
| 2726 prefix(src, dst); | |
| 2727 emit_byte(0x33); | |
| 2728 emit_operand(dst, src); | |
| 2729 } | |
| 2730 | |
| 2731 void Assembler::xorl(Register dst, Register src) { | |
| 2732 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2733 emit_arith(0x33, 0xC0, dst, src); | |
| 2734 } | |
| 2735 | |
| 2736 void Assembler::xorpd(XMMRegister dst, XMMRegister src) { | |
| 2737 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2738 emit_byte(0x66); | |
| 2739 xorps(dst, src); | |
| 2740 } | |
| 2741 | |
| 2742 void Assembler::xorpd(XMMRegister dst, Address src) { | |
| 2743 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2744 InstructionMark im(this); | |
| 2745 emit_byte(0x66); | |
| 2746 prefix(src, dst); | |
| 2747 emit_byte(0x0F); | |
| 2748 emit_byte(0x57); | |
| 2749 emit_operand(dst, src); | |
| 2750 } | |
| 2751 | |
| 2752 | |
| 2753 void Assembler::xorps(XMMRegister dst, XMMRegister src) { | |
| 2754 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 2755 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2756 emit_byte(0x0F); | |
| 2757 emit_byte(0x57); | |
| 2758 emit_byte(0xC0 | encode); | |
| 2759 } | |
| 2760 | |
| 2761 void Assembler::xorps(XMMRegister dst, Address src) { | |
| 2762 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 2763 InstructionMark im(this); | |
| 2764 prefix(src, dst); | |
| 2765 emit_byte(0x0F); | |
| 2766 emit_byte(0x57); | |
| 2767 emit_operand(dst, src); | |
| 2768 } | |
| 2769 | |
| 2770 #ifndef _LP64 | |
| 2771 // 32bit only pieces of the assembler | |
| 2772 | |
| 2773 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) { | |
| 2774 // NO PREFIX AS NEVER 64BIT | |
| 2775 InstructionMark im(this); | |
| 2776 emit_byte(0x81); | |
| 2777 emit_byte(0xF8 | src1->encoding()); | |
| 2778 emit_data(imm32, rspec, 0); | |
| 2779 } | |
| 2780 | |
| 2781 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) { | |
| 2782 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs | |
| 2783 InstructionMark im(this); | |
| 2784 emit_byte(0x81); | |
| 2785 emit_operand(rdi, src1); | |
| 2786 emit_data(imm32, rspec, 0); | |
| 2787 } | |
| 2788 | |
| 2789 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax, | |
| 2790 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded | |
| 2791 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise. | |
| 2792 void Assembler::cmpxchg8(Address adr) { | |
| 2793 InstructionMark im(this); | |
| 2794 emit_byte(0x0F); | |
| 2795 emit_byte(0xc7); | |
| 2796 emit_operand(rcx, adr); | |
| 2797 } | |
| 2798 | |
| 2799 void Assembler::decl(Register dst) { | |
| 2800 // Don't use it directly. Use MacroAssembler::decrementl() instead. | |
| 2801 emit_byte(0x48 | dst->encoding()); | |
| 2802 } | |
| 2803 | |
| 2804 #endif // _LP64 | |
| 2805 | |
| 2806 // 64bit typically doesn't use the x87 but needs to for the trig funcs | |
| 2807 | |
| 2808 void Assembler::fabs() { | |
| 2809 emit_byte(0xD9); | |
| 2810 emit_byte(0xE1); | |
| 2811 } | |
| 2812 | |
| 2813 void Assembler::fadd(int i) { | |
| 2814 emit_farith(0xD8, 0xC0, i); | |
| 2815 } | |
| 2816 | |
| 2817 void Assembler::fadd_d(Address src) { | |
| 2818 InstructionMark im(this); | |
| 2819 emit_byte(0xDC); | |
| 2820 emit_operand32(rax, src); | |
| 2821 } | |
| 2822 | |
| 2823 void Assembler::fadd_s(Address src) { | |
| 2824 InstructionMark im(this); | |
| 2825 emit_byte(0xD8); | |
| 2826 emit_operand32(rax, src); | |
| 2827 } | |
| 2828 | |
| 2829 void Assembler::fadda(int i) { | |
| 2830 emit_farith(0xDC, 0xC0, i); | |
| 2831 } | |
| 2832 | |
| 2833 void Assembler::faddp(int i) { | |
| 2834 emit_farith(0xDE, 0xC0, i); | |
| 2835 } | |
| 2836 | |
| 2837 void Assembler::fchs() { | |
| 2838 emit_byte(0xD9); | |
| 2839 emit_byte(0xE0); | |
| 2840 } | |
| 2841 | |
| 2842 void Assembler::fcom(int i) { | |
| 2843 emit_farith(0xD8, 0xD0, i); | |
| 2844 } | |
| 2845 | |
| 2846 void Assembler::fcomp(int i) { | |
| 2847 emit_farith(0xD8, 0xD8, i); | |
| 2848 } | |
| 2849 | |
| 2850 void Assembler::fcomp_d(Address src) { | |
| 2851 InstructionMark im(this); | |
| 2852 emit_byte(0xDC); | |
| 2853 emit_operand32(rbx, src); | |
| 2854 } | |
| 2855 | |
| 2856 void Assembler::fcomp_s(Address src) { | |
| 2857 InstructionMark im(this); | |
| 2858 emit_byte(0xD8); | |
| 2859 emit_operand32(rbx, src); | |
| 2860 } | |
| 2861 | |
| 2862 void Assembler::fcompp() { | |
| 2863 emit_byte(0xDE); | |
| 2864 emit_byte(0xD9); | |
| 2865 } | |
| 2866 | |
| 2867 void Assembler::fcos() { | |
| 2868 emit_byte(0xD9); | |
| 0 | 2869 emit_byte(0xFF); |
| 304 | 2870 } |
| 2871 | |
| 2872 void Assembler::fdecstp() { | |
| 2873 emit_byte(0xD9); | |
| 2874 emit_byte(0xF6); | |
| 2875 } | |
| 2876 | |
| 2877 void Assembler::fdiv(int i) { | |
| 2878 emit_farith(0xD8, 0xF0, i); | |
| 2879 } | |
| 2880 | |
| 2881 void Assembler::fdiv_d(Address src) { | |
| 2882 InstructionMark im(this); | |
| 2883 emit_byte(0xDC); | |
| 2884 emit_operand32(rsi, src); | |
| 2885 } | |
| 2886 | |
| 2887 void Assembler::fdiv_s(Address src) { | |
| 2888 InstructionMark im(this); | |
| 2889 emit_byte(0xD8); | |
| 2890 emit_operand32(rsi, src); | |
| 2891 } | |
| 2892 | |
| 2893 void Assembler::fdiva(int i) { | |
| 2894 emit_farith(0xDC, 0xF8, i); | |
| 2895 } | |
| 2896 | |
| 2897 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994) | |
| 2898 // is erroneous for some of the floating-point instructions below. | |
| 2899 | |
| 2900 void Assembler::fdivp(int i) { | |
| 2901 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong) | |
| 2902 } | |
| 2903 | |
| 2904 void Assembler::fdivr(int i) { | |
| 2905 emit_farith(0xD8, 0xF8, i); | |
| 2906 } | |
| 2907 | |
| 2908 void Assembler::fdivr_d(Address src) { | |
| 2909 InstructionMark im(this); | |
| 2910 emit_byte(0xDC); | |
| 2911 emit_operand32(rdi, src); | |
| 2912 } | |
| 2913 | |
| 2914 void Assembler::fdivr_s(Address src) { | |
| 2915 InstructionMark im(this); | |
| 2916 emit_byte(0xD8); | |
| 2917 emit_operand32(rdi, src); | |
| 2918 } | |
| 2919 | |
| 2920 void Assembler::fdivra(int i) { | |
| 2921 emit_farith(0xDC, 0xF0, i); | |
| 2922 } | |
| 2923 | |
| 2924 void Assembler::fdivrp(int i) { | |
| 2925 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong) | |
| 2926 } | |
| 2927 | |
| 2928 void Assembler::ffree(int i) { | |
| 2929 emit_farith(0xDD, 0xC0, i); | |
| 2930 } | |
| 2931 | |
| 2932 void Assembler::fild_d(Address adr) { | |
| 2933 InstructionMark im(this); | |
| 2934 emit_byte(0xDF); | |
| 2935 emit_operand32(rbp, adr); | |
| 2936 } | |
| 2937 | |
| 2938 void Assembler::fild_s(Address adr) { | |
| 2939 InstructionMark im(this); | |
| 2940 emit_byte(0xDB); | |
| 2941 emit_operand32(rax, adr); | |
| 2942 } | |
| 2943 | |
| 2944 void Assembler::fincstp() { | |
| 2945 emit_byte(0xD9); | |
| 2946 emit_byte(0xF7); | |
| 2947 } | |
| 2948 | |
| 2949 void Assembler::finit() { | |
| 2950 emit_byte(0x9B); | |
| 2951 emit_byte(0xDB); | |
| 2952 emit_byte(0xE3); | |
| 2953 } | |
| 2954 | |
| 2955 void Assembler::fist_s(Address adr) { | |
| 2956 InstructionMark im(this); | |
| 2957 emit_byte(0xDB); | |
| 2958 emit_operand32(rdx, adr); | |
| 2959 } | |
| 2960 | |
| 2961 void Assembler::fistp_d(Address adr) { | |
| 2962 InstructionMark im(this); | |
| 2963 emit_byte(0xDF); | |
| 2964 emit_operand32(rdi, adr); | |
| 2965 } | |
| 2966 | |
| 2967 void Assembler::fistp_s(Address adr) { | |
| 2968 InstructionMark im(this); | |
| 2969 emit_byte(0xDB); | |
| 2970 emit_operand32(rbx, adr); | |
| 2971 } | |
| 0 | 2972 |
| 2973 void Assembler::fld1() { | |
| 2974 emit_byte(0xD9); | |
| 2975 emit_byte(0xE8); | |
| 2976 } | |
| 2977 | |
| 304 | 2978 void Assembler::fld_d(Address adr) { |
| 2979 InstructionMark im(this); | |
| 2980 emit_byte(0xDD); | |
| 2981 emit_operand32(rax, adr); | |
| 2982 } | |
| 0 | 2983 |
| 2984 void Assembler::fld_s(Address adr) { | |
| 2985 InstructionMark im(this); | |
| 2986 emit_byte(0xD9); | |
| 304 | 2987 emit_operand32(rax, adr); |
| 2988 } | |
| 2989 | |
| 2990 | |
| 2991 void Assembler::fld_s(int index) { | |
| 0 | 2992 emit_farith(0xD9, 0xC0, index); |
| 2993 } | |
| 2994 | |
| 2995 void Assembler::fld_x(Address adr) { | |
| 2996 InstructionMark im(this); | |
| 2997 emit_byte(0xDB); | |
| 304 | 2998 emit_operand32(rbp, adr); |
| 2999 } | |
| 3000 | |
| 3001 void Assembler::fldcw(Address src) { | |
| 3002 InstructionMark im(this); | |
| 3003 emit_byte(0xd9); | |
| 3004 emit_operand32(rbp, src); | |
| 3005 } | |
| 3006 | |
| 3007 void Assembler::fldenv(Address src) { | |
| 0 | 3008 InstructionMark im(this); |
| 3009 emit_byte(0xD9); | |
| 304 | 3010 emit_operand32(rsp, src); |
| 3011 } | |
| 3012 | |
| 3013 void Assembler::fldlg2() { | |
| 0 | 3014 emit_byte(0xD9); |
| 304 | 3015 emit_byte(0xEC); |
| 3016 } | |
| 0 | 3017 |
| 3018 void Assembler::fldln2() { | |
| 3019 emit_byte(0xD9); | |
| 3020 emit_byte(0xED); | |
| 3021 } | |
| 3022 | |
| 304 | 3023 void Assembler::fldz() { |
| 0 | 3024 emit_byte(0xD9); |
| 304 | 3025 emit_byte(0xEE); |
| 3026 } | |
| 0 | 3027 |
| 3028 void Assembler::flog() { | |
| 3029 fldln2(); | |
| 3030 fxch(); | |
| 3031 fyl2x(); | |
| 3032 } | |
| 3033 | |
| 3034 void Assembler::flog10() { | |
| 3035 fldlg2(); | |
| 3036 fxch(); | |
| 3037 fyl2x(); | |
| 3038 } | |
| 3039 | |
| 304 | 3040 void Assembler::fmul(int i) { |
| 3041 emit_farith(0xD8, 0xC8, i); | |
| 3042 } | |
| 3043 | |
| 3044 void Assembler::fmul_d(Address src) { | |
| 3045 InstructionMark im(this); | |
| 3046 emit_byte(0xDC); | |
| 3047 emit_operand32(rcx, src); | |
| 3048 } | |
| 3049 | |
| 3050 void Assembler::fmul_s(Address src) { | |
| 3051 InstructionMark im(this); | |
| 3052 emit_byte(0xD8); | |
| 3053 emit_operand32(rcx, src); | |
| 3054 } | |
| 3055 | |
| 3056 void Assembler::fmula(int i) { | |
| 3057 emit_farith(0xDC, 0xC8, i); | |
| 3058 } | |
| 3059 | |
| 3060 void Assembler::fmulp(int i) { | |
| 3061 emit_farith(0xDE, 0xC8, i); | |
| 3062 } | |
| 3063 | |
| 3064 void Assembler::fnsave(Address dst) { | |
| 3065 InstructionMark im(this); | |
| 3066 emit_byte(0xDD); | |
| 3067 emit_operand32(rsi, dst); | |
| 3068 } | |
| 3069 | |
| 3070 void Assembler::fnstcw(Address src) { | |
| 3071 InstructionMark im(this); | |
| 3072 emit_byte(0x9B); | |
| 3073 emit_byte(0xD9); | |
| 3074 emit_operand32(rdi, src); | |
| 3075 } | |
| 3076 | |
| 3077 void Assembler::fnstsw_ax() { | |
| 3078 emit_byte(0xdF); | |
| 3079 emit_byte(0xE0); | |
| 3080 } | |
| 3081 | |
| 3082 void Assembler::fprem() { | |
| 3083 emit_byte(0xD9); | |
| 3084 emit_byte(0xF8); | |
| 3085 } | |
| 3086 | |
| 3087 void Assembler::fprem1() { | |
| 3088 emit_byte(0xD9); | |
| 3089 emit_byte(0xF5); | |
| 3090 } | |
| 3091 | |
| 3092 void Assembler::frstor(Address src) { | |
| 3093 InstructionMark im(this); | |
| 3094 emit_byte(0xDD); | |
| 3095 emit_operand32(rsp, src); | |
| 3096 } | |
| 0 | 3097 |
| 3098 void Assembler::fsin() { | |
| 3099 emit_byte(0xD9); | |
| 3100 emit_byte(0xFE); | |
| 3101 } | |
| 3102 | |
| 304 | 3103 void Assembler::fsqrt() { |
| 3104 emit_byte(0xD9); | |
| 3105 emit_byte(0xFA); | |
| 3106 } | |
| 3107 | |
| 3108 void Assembler::fst_d(Address adr) { | |
| 3109 InstructionMark im(this); | |
| 3110 emit_byte(0xDD); | |
| 3111 emit_operand32(rdx, adr); | |
| 3112 } | |
| 3113 | |
| 3114 void Assembler::fst_s(Address adr) { | |
| 3115 InstructionMark im(this); | |
| 3116 emit_byte(0xD9); | |
| 3117 emit_operand32(rdx, adr); | |
| 3118 } | |
| 3119 | |
| 3120 void Assembler::fstp_d(Address adr) { | |
| 3121 InstructionMark im(this); | |
| 3122 emit_byte(0xDD); | |
| 3123 emit_operand32(rbx, adr); | |
| 3124 } | |
| 3125 | |
| 3126 void Assembler::fstp_d(int index) { | |
| 3127 emit_farith(0xDD, 0xD8, index); | |
| 3128 } | |
| 3129 | |
| 3130 void Assembler::fstp_s(Address adr) { | |
| 3131 InstructionMark im(this); | |
| 0 | 3132 emit_byte(0xD9); |
| 304 | 3133 emit_operand32(rbx, adr); |
| 3134 } | |
| 3135 | |
| 3136 void Assembler::fstp_x(Address adr) { | |
| 3137 InstructionMark im(this); | |
| 3138 emit_byte(0xDB); | |
| 3139 emit_operand32(rdi, adr); | |
| 3140 } | |
| 3141 | |
| 3142 void Assembler::fsub(int i) { | |
| 3143 emit_farith(0xD8, 0xE0, i); | |
| 3144 } | |
| 3145 | |
| 3146 void Assembler::fsub_d(Address src) { | |
| 3147 InstructionMark im(this); | |
| 3148 emit_byte(0xDC); | |
| 3149 emit_operand32(rsp, src); | |
| 3150 } | |
| 3151 | |
| 3152 void Assembler::fsub_s(Address src) { | |
| 3153 InstructionMark im(this); | |
| 3154 emit_byte(0xD8); | |
| 3155 emit_operand32(rsp, src); | |
| 3156 } | |
| 3157 | |
| 3158 void Assembler::fsuba(int i) { | |
| 3159 emit_farith(0xDC, 0xE8, i); | |
| 3160 } | |
| 3161 | |
| 3162 void Assembler::fsubp(int i) { | |
| 3163 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong) | |
| 3164 } | |
| 3165 | |
| 3166 void Assembler::fsubr(int i) { | |
| 3167 emit_farith(0xD8, 0xE8, i); | |
| 3168 } | |
| 3169 | |
| 3170 void Assembler::fsubr_d(Address src) { | |
| 3171 InstructionMark im(this); | |
| 3172 emit_byte(0xDC); | |
| 3173 emit_operand32(rbp, src); | |
| 3174 } | |
| 3175 | |
| 3176 void Assembler::fsubr_s(Address src) { | |
| 3177 InstructionMark im(this); | |
| 3178 emit_byte(0xD8); | |
| 3179 emit_operand32(rbp, src); | |
| 3180 } | |
| 3181 | |
| 3182 void Assembler::fsubra(int i) { | |
| 3183 emit_farith(0xDC, 0xE0, i); | |
| 3184 } | |
| 3185 | |
| 3186 void Assembler::fsubrp(int i) { | |
| 3187 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong) | |
| 0 | 3188 } |
| 3189 | |
| 3190 void Assembler::ftan() { | |
| 3191 emit_byte(0xD9); | |
| 3192 emit_byte(0xF2); | |
| 3193 emit_byte(0xDD); | |
| 3194 emit_byte(0xD8); | |
| 3195 } | |
| 3196 | |
| 304 | 3197 void Assembler::ftst() { |
| 0 | 3198 emit_byte(0xD9); |
| 304 | 3199 emit_byte(0xE4); |
| 3200 } | |
| 0 | 3201 |
| 3202 void Assembler::fucomi(int i) { | |
| 3203 // make sure the instruction is supported (introduced for P6, together with cmov) | |
| 3204 guarantee(VM_Version::supports_cmov(), "illegal instruction"); | |
| 3205 emit_farith(0xDB, 0xE8, i); | |
| 3206 } | |
| 3207 | |
| 3208 void Assembler::fucomip(int i) { | |
| 3209 // make sure the instruction is supported (introduced for P6, together with cmov) | |
| 3210 guarantee(VM_Version::supports_cmov(), "illegal instruction"); | |
| 3211 emit_farith(0xDF, 0xE8, i); | |
| 3212 } | |
| 3213 | |
| 3214 void Assembler::fwait() { | |
| 3215 emit_byte(0x9B); | |
| 3216 } | |
| 3217 | |
| 304 | 3218 void Assembler::fxch(int i) { |
| 3219 emit_farith(0xD9, 0xC8, i); | |
| 3220 } | |
| 3221 | |
| 3222 void Assembler::fyl2x() { | |
| 0 | 3223 emit_byte(0xD9); |
| 304 | 3224 emit_byte(0xF1); |
| 3225 } | |
| 3226 | |
| 3227 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec, int format) { | |
| 3228 InstructionMark im(this); | |
| 3229 int encode = prefix_and_encode(dst->encoding()); | |
| 3230 emit_byte(0xB8 | encode); | |
| 3231 emit_data((int)imm32, rspec, format); | |
| 3232 } | |
| 3233 | |
| 3234 #ifndef _LP64 | |
| 3235 | |
| 3236 void Assembler::incl(Register dst) { | |
| 3237 // Don't use it directly. Use MacroAssembler::incrementl() instead. | |
| 3238 emit_byte(0x40 | dst->encoding()); | |
| 3239 } | |
| 3240 | |
| 3241 void Assembler::lea(Register dst, Address src) { | |
| 3242 leal(dst, src); | |
| 3243 } | |
| 3244 | |
| 3245 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) { | |
| 3246 InstructionMark im(this); | |
| 3247 emit_byte(0xC7); | |
| 3248 emit_operand(rax, dst); | |
| 3249 emit_data((int)imm32, rspec, 0); | |
| 3250 } | |
| 3251 | |
| 3252 | |
| 3253 void Assembler::popa() { // 32bit | |
| 3254 emit_byte(0x61); | |
| 3255 } | |
| 3256 | |
| 3257 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) { | |
| 3258 InstructionMark im(this); | |
| 3259 emit_byte(0x68); | |
| 3260 emit_data(imm32, rspec, 0); | |
| 3261 } | |
| 3262 | |
| 3263 void Assembler::pusha() { // 32bit | |
| 3264 emit_byte(0x60); | |
| 3265 } | |
| 3266 | |
| 3267 void Assembler::set_byte_if_not_zero(Register dst) { | |
| 0 | 3268 emit_byte(0x0F); |
| 304 | 3269 emit_byte(0x95); |
| 3270 emit_byte(0xE0 | dst->encoding()); | |
| 3271 } | |
| 3272 | |
| 3273 void Assembler::shldl(Register dst, Register src) { | |
| 0 | 3274 emit_byte(0x0F); |
| 304 | 3275 emit_byte(0xA5); |
| 3276 emit_byte(0xC0 | src->encoding() << 3 | dst->encoding()); | |
| 3277 } | |
| 3278 | |
| 3279 void Assembler::shrdl(Register dst, Register src) { | |
| 0 | 3280 emit_byte(0x0F); |
| 304 | 3281 emit_byte(0xAD); |
| 3282 emit_byte(0xC0 | src->encoding() << 3 | dst->encoding()); | |
| 3283 } | |
| 3284 | |
| 3285 #else // LP64 | |
| 3286 | |
| 3287 // 64bit only pieces of the assembler | |
| 3288 // This should only be used by 64bit instructions that can use rip-relative | |
| 3289 // it cannot be used by instructions that want an immediate value. | |
| 3290 | |
| 3291 bool Assembler::reachable(AddressLiteral adr) { | |
| 3292 int64_t disp; | |
| 3293 // None will force a 64bit literal to the code stream. Likely a placeholder | |
| 3294 // for something that will be patched later and we need to certain it will | |
| 3295 // always be reachable. | |
| 3296 if (adr.reloc() == relocInfo::none) { | |
| 3297 return false; | |
| 3298 } | |
| 3299 if (adr.reloc() == relocInfo::internal_word_type) { | |
| 3300 // This should be rip relative and easily reachable. | |
| 3301 return true; | |
| 3302 } | |
| 3303 if (adr.reloc() == relocInfo::virtual_call_type || | |
| 3304 adr.reloc() == relocInfo::opt_virtual_call_type || | |
| 3305 adr.reloc() == relocInfo::static_call_type || | |
| 3306 adr.reloc() == relocInfo::static_stub_type ) { | |
| 3307 // This should be rip relative within the code cache and easily | |
| 3308 // reachable until we get huge code caches. (At which point | |
| 3309 // ic code is going to have issues). | |
| 3310 return true; | |
| 3311 } | |
| 3312 if (adr.reloc() != relocInfo::external_word_type && | |
| 3313 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special | |
| 3314 adr.reloc() != relocInfo::poll_type && // relocs to identify them | |
| 3315 adr.reloc() != relocInfo::runtime_call_type ) { | |
| 3316 return false; | |
| 3317 } | |
| 3318 | |
| 3319 // Stress the correction code | |
| 3320 if (ForceUnreachable) { | |
| 3321 // Must be runtimecall reloc, see if it is in the codecache | |
| 3322 // Flipping stuff in the codecache to be unreachable causes issues | |
| 3323 // with things like inline caches where the additional instructions | |
| 3324 // are not handled. | |
| 3325 if (CodeCache::find_blob(adr._target) == NULL) { | |
| 3326 return false; | |
| 3327 } | |
| 3328 } | |
| 3329 // For external_word_type/runtime_call_type if it is reachable from where we | |
| 3330 // are now (possibly a temp buffer) and where we might end up | |
| 3331 // anywhere in the codeCache then we are always reachable. | |
| 3332 // This would have to change if we ever save/restore shared code | |
| 3333 // to be more pessimistic. | |
| 3334 | |
| 3335 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int)); | |
| 3336 if (!is_simm32(disp)) return false; | |
| 3337 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int)); | |
| 3338 if (!is_simm32(disp)) return false; | |
| 3339 | |
| 3340 disp = (int64_t)adr._target - ((int64_t)_code_pos + sizeof(int)); | |
| 3341 | |
| 3342 // Because rip relative is a disp + address_of_next_instruction and we | |
| 3343 // don't know the value of address_of_next_instruction we apply a fudge factor | |
| 3344 // to make sure we will be ok no matter the size of the instruction we get placed into. | |
| 3345 // We don't have to fudge the checks above here because they are already worst case. | |
| 3346 | |
| 3347 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal | |
| 3348 // + 4 because better safe than sorry. | |
| 3349 const int fudge = 12 + 4; | |
| 3350 if (disp < 0) { | |
| 3351 disp -= fudge; | |
| 3352 } else { | |
| 3353 disp += fudge; | |
| 3354 } | |
| 3355 return is_simm32(disp); | |
| 3356 } | |
| 3357 | |
| 3358 void Assembler::emit_data64(jlong data, | |
| 3359 relocInfo::relocType rtype, | |
| 3360 int format) { | |
| 3361 if (rtype == relocInfo::none) { | |
| 3362 emit_long64(data); | |
| 3363 } else { | |
| 3364 emit_data64(data, Relocation::spec_simple(rtype), format); | |
| 3365 } | |
| 3366 } | |
| 3367 | |
| 3368 void Assembler::emit_data64(jlong data, | |
| 3369 RelocationHolder const& rspec, | |
| 3370 int format) { | |
| 3371 assert(imm_operand == 0, "default format must be immediate in this file"); | |
| 3372 assert(imm_operand == format, "must be immediate"); | |
| 3373 assert(inst_mark() != NULL, "must be inside InstructionMark"); | |
| 3374 // Do not use AbstractAssembler::relocate, which is not intended for | |
| 3375 // embedded words. Instead, relocate to the enclosing instruction. | |
| 3376 code_section()->relocate(inst_mark(), rspec, format); | |
| 3377 #ifdef ASSERT | |
| 3378 check_relocation(rspec, format); | |
| 3379 #endif | |
| 3380 emit_long64(data); | |
| 3381 } | |
| 3382 | |
| 3383 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) { | |
| 3384 if (reg_enc >= 8) { | |
| 3385 prefix(REX_B); | |
| 3386 reg_enc -= 8; | |
| 3387 } else if (byteinst && reg_enc >= 4) { | |
| 3388 prefix(REX); | |
| 3389 } | |
| 3390 return reg_enc; | |
| 3391 } | |
| 3392 | |
| 3393 int Assembler::prefixq_and_encode(int reg_enc) { | |
| 3394 if (reg_enc < 8) { | |
| 3395 prefix(REX_W); | |
| 3396 } else { | |
| 3397 prefix(REX_WB); | |
| 3398 reg_enc -= 8; | |
| 3399 } | |
| 3400 return reg_enc; | |
| 3401 } | |
| 3402 | |
| 3403 int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) { | |
| 3404 if (dst_enc < 8) { | |
| 3405 if (src_enc >= 8) { | |
| 3406 prefix(REX_B); | |
| 3407 src_enc -= 8; | |
| 3408 } else if (byteinst && src_enc >= 4) { | |
| 3409 prefix(REX); | |
| 3410 } | |
| 3411 } else { | |
| 3412 if (src_enc < 8) { | |
| 3413 prefix(REX_R); | |
| 3414 } else { | |
| 3415 prefix(REX_RB); | |
| 3416 src_enc -= 8; | |
| 3417 } | |
| 3418 dst_enc -= 8; | |
| 3419 } | |
| 3420 return dst_enc << 3 | src_enc; | |
| 3421 } | |
| 3422 | |
| 3423 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) { | |
| 3424 if (dst_enc < 8) { | |
| 3425 if (src_enc < 8) { | |
| 3426 prefix(REX_W); | |
| 3427 } else { | |
| 3428 prefix(REX_WB); | |
| 3429 src_enc -= 8; | |
| 3430 } | |
| 3431 } else { | |
| 3432 if (src_enc < 8) { | |
| 3433 prefix(REX_WR); | |
| 3434 } else { | |
| 3435 prefix(REX_WRB); | |
| 3436 src_enc -= 8; | |
| 3437 } | |
| 3438 dst_enc -= 8; | |
| 3439 } | |
| 3440 return dst_enc << 3 | src_enc; | |
| 3441 } | |
| 3442 | |
| 3443 void Assembler::prefix(Register reg) { | |
| 3444 if (reg->encoding() >= 8) { | |
| 3445 prefix(REX_B); | |
| 3446 } | |
| 3447 } | |
| 3448 | |
| 3449 void Assembler::prefix(Address adr) { | |
| 3450 if (adr.base_needs_rex()) { | |
| 3451 if (adr.index_needs_rex()) { | |
| 3452 prefix(REX_XB); | |
| 3453 } else { | |
| 3454 prefix(REX_B); | |
| 3455 } | |
| 3456 } else { | |
| 3457 if (adr.index_needs_rex()) { | |
| 3458 prefix(REX_X); | |
| 3459 } | |
| 3460 } | |
| 3461 } | |
| 3462 | |
| 3463 void Assembler::prefixq(Address adr) { | |
| 3464 if (adr.base_needs_rex()) { | |
| 3465 if (adr.index_needs_rex()) { | |
| 3466 prefix(REX_WXB); | |
| 3467 } else { | |
| 3468 prefix(REX_WB); | |
| 3469 } | |
| 3470 } else { | |
| 3471 if (adr.index_needs_rex()) { | |
| 3472 prefix(REX_WX); | |
| 3473 } else { | |
| 3474 prefix(REX_W); | |
| 3475 } | |
| 3476 } | |
| 3477 } | |
| 3478 | |
| 3479 | |
| 3480 void Assembler::prefix(Address adr, Register reg, bool byteinst) { | |
| 3481 if (reg->encoding() < 8) { | |
| 3482 if (adr.base_needs_rex()) { | |
| 3483 if (adr.index_needs_rex()) { | |
| 3484 prefix(REX_XB); | |
| 3485 } else { | |
| 3486 prefix(REX_B); | |
| 3487 } | |
| 3488 } else { | |
| 3489 if (adr.index_needs_rex()) { | |
| 3490 prefix(REX_X); | |
| 3491 } else if (reg->encoding() >= 4 ) { | |
| 3492 prefix(REX); | |
| 3493 } | |
| 3494 } | |
| 3495 } else { | |
| 3496 if (adr.base_needs_rex()) { | |
| 3497 if (adr.index_needs_rex()) { | |
| 3498 prefix(REX_RXB); | |
| 3499 } else { | |
| 3500 prefix(REX_RB); | |
| 3501 } | |
| 3502 } else { | |
| 3503 if (adr.index_needs_rex()) { | |
| 3504 prefix(REX_RX); | |
| 3505 } else { | |
| 3506 prefix(REX_R); | |
| 3507 } | |
| 3508 } | |
| 3509 } | |
| 3510 } | |
| 3511 | |
| 3512 void Assembler::prefixq(Address adr, Register src) { | |
| 3513 if (src->encoding() < 8) { | |
| 3514 if (adr.base_needs_rex()) { | |
| 3515 if (adr.index_needs_rex()) { | |
| 3516 prefix(REX_WXB); | |
| 3517 } else { | |
| 3518 prefix(REX_WB); | |
| 3519 } | |
| 3520 } else { | |
| 3521 if (adr.index_needs_rex()) { | |
| 3522 prefix(REX_WX); | |
| 3523 } else { | |
| 3524 prefix(REX_W); | |
| 3525 } | |
| 3526 } | |
| 3527 } else { | |
| 3528 if (adr.base_needs_rex()) { | |
| 3529 if (adr.index_needs_rex()) { | |
| 3530 prefix(REX_WRXB); | |
| 3531 } else { | |
| 3532 prefix(REX_WRB); | |
| 3533 } | |
| 3534 } else { | |
| 3535 if (adr.index_needs_rex()) { | |
| 3536 prefix(REX_WRX); | |
| 3537 } else { | |
| 3538 prefix(REX_WR); | |
| 3539 } | |
| 3540 } | |
| 3541 } | |
| 3542 } | |
| 3543 | |
| 3544 void Assembler::prefix(Address adr, XMMRegister reg) { | |
| 3545 if (reg->encoding() < 8) { | |
| 3546 if (adr.base_needs_rex()) { | |
| 3547 if (adr.index_needs_rex()) { | |
| 3548 prefix(REX_XB); | |
| 3549 } else { | |
| 3550 prefix(REX_B); | |
| 3551 } | |
| 3552 } else { | |
| 3553 if (adr.index_needs_rex()) { | |
| 3554 prefix(REX_X); | |
| 3555 } | |
| 3556 } | |
| 3557 } else { | |
| 3558 if (adr.base_needs_rex()) { | |
| 3559 if (adr.index_needs_rex()) { | |
| 3560 prefix(REX_RXB); | |
| 3561 } else { | |
| 3562 prefix(REX_RB); | |
| 3563 } | |
| 3564 } else { | |
| 3565 if (adr.index_needs_rex()) { | |
| 3566 prefix(REX_RX); | |
| 3567 } else { | |
| 3568 prefix(REX_R); | |
| 3569 } | |
| 3570 } | |
| 3571 } | |
| 3572 } | |
| 3573 | |
| 3574 void Assembler::adcq(Register dst, int32_t imm32) { | |
| 3575 (void) prefixq_and_encode(dst->encoding()); | |
| 3576 emit_arith(0x81, 0xD0, dst, imm32); | |
| 3577 } | |
| 3578 | |
| 3579 void Assembler::adcq(Register dst, Address src) { | |
| 3580 InstructionMark im(this); | |
| 3581 prefixq(src, dst); | |
| 3582 emit_byte(0x13); | |
| 3583 emit_operand(dst, src); | |
| 3584 } | |
| 3585 | |
| 3586 void Assembler::adcq(Register dst, Register src) { | |
| 3587 (int) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3588 emit_arith(0x13, 0xC0, dst, src); | |
| 3589 } | |
| 3590 | |
| 3591 void Assembler::addq(Address dst, int32_t imm32) { | |
| 3592 InstructionMark im(this); | |
| 3593 prefixq(dst); | |
| 3594 emit_arith_operand(0x81, rax, dst,imm32); | |
| 3595 } | |
| 3596 | |
| 3597 void Assembler::addq(Address dst, Register src) { | |
| 3598 InstructionMark im(this); | |
| 3599 prefixq(dst, src); | |
| 3600 emit_byte(0x01); | |
| 3601 emit_operand(src, dst); | |
| 3602 } | |
| 3603 | |
| 3604 void Assembler::addq(Register dst, int32_t imm32) { | |
| 3605 (void) prefixq_and_encode(dst->encoding()); | |
| 3606 emit_arith(0x81, 0xC0, dst, imm32); | |
| 3607 } | |
| 3608 | |
| 3609 void Assembler::addq(Register dst, Address src) { | |
| 3610 InstructionMark im(this); | |
| 3611 prefixq(src, dst); | |
| 3612 emit_byte(0x03); | |
| 3613 emit_operand(dst, src); | |
| 3614 } | |
| 3615 | |
| 3616 void Assembler::addq(Register dst, Register src) { | |
| 3617 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3618 emit_arith(0x03, 0xC0, dst, src); | |
| 3619 } | |
| 3620 | |
| 3621 void Assembler::andq(Register dst, int32_t imm32) { | |
| 3622 (void) prefixq_and_encode(dst->encoding()); | |
| 3623 emit_arith(0x81, 0xE0, dst, imm32); | |
| 3624 } | |
| 3625 | |
| 3626 void Assembler::andq(Register dst, Address src) { | |
| 3627 InstructionMark im(this); | |
| 3628 prefixq(src, dst); | |
| 3629 emit_byte(0x23); | |
| 3630 emit_operand(dst, src); | |
| 3631 } | |
| 3632 | |
| 3633 void Assembler::andq(Register dst, Register src) { | |
| 3634 (int) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3635 emit_arith(0x23, 0xC0, dst, src); | |
| 3636 } | |
| 3637 | |
| 3638 void Assembler::bswapq(Register reg) { | |
| 3639 int encode = prefixq_and_encode(reg->encoding()); | |
| 3640 emit_byte(0x0F); | |
| 3641 emit_byte(0xC8 | encode); | |
| 3642 } | |
| 3643 | |
| 3644 void Assembler::cdqq() { | |
| 3645 prefix(REX_W); | |
| 3646 emit_byte(0x99); | |
| 3647 } | |
| 3648 | |
| 3649 void Assembler::clflush(Address adr) { | |
| 3650 prefix(adr); | |
| 3651 emit_byte(0x0F); | |
| 3652 emit_byte(0xAE); | |
| 3653 emit_operand(rdi, adr); | |
| 3654 } | |
| 3655 | |
| 3656 void Assembler::cmovq(Condition cc, Register dst, Register src) { | |
| 3657 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3658 emit_byte(0x0F); | |
| 3659 emit_byte(0x40 | cc); | |
| 3660 emit_byte(0xC0 | encode); | |
| 3661 } | |
| 3662 | |
| 3663 void Assembler::cmovq(Condition cc, Register dst, Address src) { | |
| 3664 InstructionMark im(this); | |
| 3665 prefixq(src, dst); | |
| 3666 emit_byte(0x0F); | |
| 3667 emit_byte(0x40 | cc); | |
| 3668 emit_operand(dst, src); | |
| 3669 } | |
| 3670 | |
| 3671 void Assembler::cmpq(Address dst, int32_t imm32) { | |
| 3672 InstructionMark im(this); | |
| 3673 prefixq(dst); | |
| 3674 emit_byte(0x81); | |
| 3675 emit_operand(rdi, dst, 4); | |
| 3676 emit_long(imm32); | |
| 3677 } | |
| 3678 | |
| 3679 void Assembler::cmpq(Register dst, int32_t imm32) { | |
| 3680 (void) prefixq_and_encode(dst->encoding()); | |
| 3681 emit_arith(0x81, 0xF8, dst, imm32); | |
| 3682 } | |
| 3683 | |
| 3684 void Assembler::cmpq(Address dst, Register src) { | |
| 3685 InstructionMark im(this); | |
| 3686 prefixq(dst, src); | |
| 3687 emit_byte(0x3B); | |
| 3688 emit_operand(src, dst); | |
| 3689 } | |
| 3690 | |
| 3691 void Assembler::cmpq(Register dst, Register src) { | |
| 3692 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3693 emit_arith(0x3B, 0xC0, dst, src); | |
| 3694 } | |
| 3695 | |
| 3696 void Assembler::cmpq(Register dst, Address src) { | |
| 3697 InstructionMark im(this); | |
| 3698 prefixq(src, dst); | |
| 3699 emit_byte(0x3B); | |
| 3700 emit_operand(dst, src); | |
| 3701 } | |
| 3702 | |
| 3703 void Assembler::cmpxchgq(Register reg, Address adr) { | |
| 3704 InstructionMark im(this); | |
| 3705 prefixq(adr, reg); | |
| 3706 emit_byte(0x0F); | |
| 3707 emit_byte(0xB1); | |
| 3708 emit_operand(reg, adr); | |
| 3709 } | |
| 3710 | |
| 3711 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) { | |
| 3712 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 3713 emit_byte(0xF2); | |
| 3714 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3715 emit_byte(0x0F); | |
| 3716 emit_byte(0x2A); | |
| 3717 emit_byte(0xC0 | encode); | |
| 3718 } | |
| 3719 | |
| 3720 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) { | |
| 3721 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 3722 emit_byte(0xF3); | |
| 3723 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3724 emit_byte(0x0F); | |
| 3725 emit_byte(0x2A); | |
| 3726 emit_byte(0xC0 | encode); | |
| 3727 } | |
| 3728 | |
| 3729 void Assembler::cvttsd2siq(Register dst, XMMRegister src) { | |
| 3730 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 3731 emit_byte(0xF2); | |
| 3732 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3733 emit_byte(0x0F); | |
| 3734 emit_byte(0x2C); | |
| 3735 emit_byte(0xC0 | encode); | |
| 3736 } | |
| 3737 | |
| 3738 void Assembler::cvttss2siq(Register dst, XMMRegister src) { | |
| 3739 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 3740 emit_byte(0xF3); | |
| 3741 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3742 emit_byte(0x0F); | |
| 3743 emit_byte(0x2C); | |
| 3744 emit_byte(0xC0 | encode); | |
| 3745 } | |
| 3746 | |
| 3747 void Assembler::decl(Register dst) { | |
| 3748 // Don't use it directly. Use MacroAssembler::decrementl() instead. | |
| 3749 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode) | |
| 3750 int encode = prefix_and_encode(dst->encoding()); | |
| 3751 emit_byte(0xFF); | |
| 3752 emit_byte(0xC8 | encode); | |
| 3753 } | |
| 3754 | |
| 3755 void Assembler::decq(Register dst) { | |
| 3756 // Don't use it directly. Use MacroAssembler::decrementq() instead. | |
| 3757 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |
| 3758 int encode = prefixq_and_encode(dst->encoding()); | |
| 3759 emit_byte(0xFF); | |
| 3760 emit_byte(0xC8 | encode); | |
| 3761 } | |
| 3762 | |
| 3763 void Assembler::decq(Address dst) { | |
| 3764 // Don't use it directly. Use MacroAssembler::decrementq() instead. | |
| 3765 InstructionMark im(this); | |
| 3766 prefixq(dst); | |
| 3767 emit_byte(0xFF); | |
| 3768 emit_operand(rcx, dst); | |
| 3769 } | |
| 3770 | |
| 3771 void Assembler::fxrstor(Address src) { | |
| 3772 prefixq(src); | |
| 3773 emit_byte(0x0F); | |
| 3774 emit_byte(0xAE); | |
| 3775 emit_operand(as_Register(1), src); | |
| 3776 } | |
| 3777 | |
| 3778 void Assembler::fxsave(Address dst) { | |
| 3779 prefixq(dst); | |
| 3780 emit_byte(0x0F); | |
| 3781 emit_byte(0xAE); | |
| 3782 emit_operand(as_Register(0), dst); | |
| 3783 } | |
| 3784 | |
| 3785 void Assembler::idivq(Register src) { | |
| 3786 int encode = prefixq_and_encode(src->encoding()); | |
| 3787 emit_byte(0xF7); | |
| 3788 emit_byte(0xF8 | encode); | |
| 3789 } | |
| 3790 | |
| 3791 void Assembler::imulq(Register dst, Register src) { | |
| 3792 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3793 emit_byte(0x0F); | |
| 3794 emit_byte(0xAF); | |
| 3795 emit_byte(0xC0 | encode); | |
| 3796 } | |
| 3797 | |
| 3798 void Assembler::imulq(Register dst, Register src, int value) { | |
| 3799 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3800 if (is8bit(value)) { | |
| 3801 emit_byte(0x6B); | |
| 3802 emit_byte(0xC0 | encode); | |
| 3803 emit_byte(value); | |
| 3804 } else { | |
| 3805 emit_byte(0x69); | |
| 3806 emit_byte(0xC0 | encode); | |
| 3807 emit_long(value); | |
| 3808 } | |
| 3809 } | |
| 3810 | |
| 3811 void Assembler::incl(Register dst) { | |
| 3812 // Don't use it directly. Use MacroAssembler::incrementl() instead. | |
| 3813 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |
| 3814 int encode = prefix_and_encode(dst->encoding()); | |
| 3815 emit_byte(0xFF); | |
| 3816 emit_byte(0xC0 | encode); | |
| 3817 } | |
| 3818 | |
| 3819 void Assembler::incq(Register dst) { | |
| 3820 // Don't use it directly. Use MacroAssembler::incrementq() instead. | |
| 3821 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |
| 3822 int encode = prefixq_and_encode(dst->encoding()); | |
| 3823 emit_byte(0xFF); | |
| 3824 emit_byte(0xC0 | encode); | |
| 3825 } | |
| 3826 | |
| 3827 void Assembler::incq(Address dst) { | |
| 3828 // Don't use it directly. Use MacroAssembler::incrementq() instead. | |
| 3829 InstructionMark im(this); | |
| 3830 prefixq(dst); | |
| 3831 emit_byte(0xFF); | |
| 3832 emit_operand(rax, dst); | |
| 3833 } | |
| 3834 | |
| 3835 void Assembler::lea(Register dst, Address src) { | |
| 3836 leaq(dst, src); | |
| 3837 } | |
| 3838 | |
| 3839 void Assembler::leaq(Register dst, Address src) { | |
| 3840 InstructionMark im(this); | |
| 3841 prefixq(src, dst); | |
| 3842 emit_byte(0x8D); | |
| 3843 emit_operand(dst, src); | |
| 3844 } | |
| 3845 | |
| 3846 void Assembler::mov64(Register dst, int64_t imm64) { | |
| 3847 InstructionMark im(this); | |
| 3848 int encode = prefixq_and_encode(dst->encoding()); | |
| 3849 emit_byte(0xB8 | encode); | |
| 3850 emit_long64(imm64); | |
| 3851 } | |
| 3852 | |
| 3853 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) { | |
| 3854 InstructionMark im(this); | |
| 3855 int encode = prefixq_and_encode(dst->encoding()); | |
| 3856 emit_byte(0xB8 | encode); | |
| 3857 emit_data64(imm64, rspec); | |
| 3858 } | |
| 3859 | |
| 3860 void Assembler::movdq(XMMRegister dst, Register src) { | |
| 3861 // table D-1 says MMX/SSE2 | |
| 3862 NOT_LP64(assert(VM_Version::supports_sse2() || VM_Version::supports_mmx(), "")); | |
| 0 | 3863 emit_byte(0x66); |
| 304 | 3864 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
| 0 | 3865 emit_byte(0x0F); |
| 304 | 3866 emit_byte(0x6E); |
| 3867 emit_byte(0xC0 | encode); | |
| 3868 } | |
| 3869 | |
| 3870 void Assembler::movdq(Register dst, XMMRegister src) { | |
| 3871 // table D-1 says MMX/SSE2 | |
| 3872 NOT_LP64(assert(VM_Version::supports_sse2() || VM_Version::supports_mmx(), "")); | |
| 0 | 3873 emit_byte(0x66); |
| 304 | 3874 // swap src/dst to get correct prefix |
| 3875 int encode = prefixq_and_encode(src->encoding(), dst->encoding()); | |
| 0 | 3876 emit_byte(0x0F); |
| 3877 emit_byte(0x7E); | |
| 304 | 3878 emit_byte(0xC0 | encode); |
| 3879 } | |
| 3880 | |
| 3881 void Assembler::movq(Register dst, Register src) { | |
| 3882 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3883 emit_byte(0x8B); | |
| 3884 emit_byte(0xC0 | encode); | |
| 3885 } | |
| 3886 | |
| 3887 void Assembler::movq(Register dst, Address src) { | |
| 3888 InstructionMark im(this); | |
| 3889 prefixq(src, dst); | |
| 3890 emit_byte(0x8B); | |
| 3891 emit_operand(dst, src); | |
| 3892 } | |
| 3893 | |
| 3894 void Assembler::movq(Address dst, Register src) { | |
| 3895 InstructionMark im(this); | |
| 3896 prefixq(dst, src); | |
| 3897 emit_byte(0x89); | |
| 3898 emit_operand(src, dst); | |
| 3899 } | |
| 3900 | |
| 624 | 3901 void Assembler::movsbq(Register dst, Address src) { |
| 3902 InstructionMark im(this); | |
| 3903 prefixq(src, dst); | |
| 3904 emit_byte(0x0F); | |
| 3905 emit_byte(0xBE); | |
| 3906 emit_operand(dst, src); | |
| 3907 } | |
| 3908 | |
| 3909 void Assembler::movsbq(Register dst, Register src) { | |
| 3910 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3911 emit_byte(0x0F); | |
| 3912 emit_byte(0xBE); | |
| 3913 emit_byte(0xC0 | encode); | |
| 3914 } | |
| 3915 | |
| 304 | 3916 void Assembler::movslq(Register dst, int32_t imm32) { |
| 3917 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx) | |
| 3918 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx) | |
| 3919 // as a result we shouldn't use until tested at runtime... | |
| 3920 ShouldNotReachHere(); | |
| 3921 InstructionMark im(this); | |
| 3922 int encode = prefixq_and_encode(dst->encoding()); | |
| 3923 emit_byte(0xC7 | encode); | |
| 3924 emit_long(imm32); | |
| 3925 } | |
| 3926 | |
| 3927 void Assembler::movslq(Address dst, int32_t imm32) { | |
| 3928 assert(is_simm32(imm32), "lost bits"); | |
| 3929 InstructionMark im(this); | |
| 3930 prefixq(dst); | |
| 3931 emit_byte(0xC7); | |
| 3932 emit_operand(rax, dst, 4); | |
| 3933 emit_long(imm32); | |
| 3934 } | |
| 3935 | |
| 3936 void Assembler::movslq(Register dst, Address src) { | |
| 3937 InstructionMark im(this); | |
| 3938 prefixq(src, dst); | |
| 3939 emit_byte(0x63); | |
| 3940 emit_operand(dst, src); | |
| 3941 } | |
| 3942 | |
| 3943 void Assembler::movslq(Register dst, Register src) { | |
| 3944 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3945 emit_byte(0x63); | |
| 3946 emit_byte(0xC0 | encode); | |
| 3947 } | |
| 3948 | |
| 624 | 3949 void Assembler::movswq(Register dst, Address src) { |
| 3950 InstructionMark im(this); | |
| 3951 prefixq(src, dst); | |
| 3952 emit_byte(0x0F); | |
| 3953 emit_byte(0xBF); | |
| 3954 emit_operand(dst, src); | |
| 3955 } | |
| 3956 | |
| 3957 void Assembler::movswq(Register dst, Register src) { | |
| 3958 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3959 emit_byte(0x0F); | |
| 3960 emit_byte(0xBF); | |
| 3961 emit_byte(0xC0 | encode); | |
| 3962 } | |
| 3963 | |
| 3964 void Assembler::movzbq(Register dst, Address src) { | |
| 3965 InstructionMark im(this); | |
| 3966 prefixq(src, dst); | |
| 3967 emit_byte(0x0F); | |
| 3968 emit_byte(0xB6); | |
| 3969 emit_operand(dst, src); | |
| 3970 } | |
| 3971 | |
| 3972 void Assembler::movzbq(Register dst, Register src) { | |
| 3973 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3974 emit_byte(0x0F); | |
| 3975 emit_byte(0xB6); | |
| 3976 emit_byte(0xC0 | encode); | |
| 3977 } | |
| 3978 | |
| 3979 void Assembler::movzwq(Register dst, Address src) { | |
| 3980 InstructionMark im(this); | |
| 3981 prefixq(src, dst); | |
| 3982 emit_byte(0x0F); | |
| 3983 emit_byte(0xB7); | |
| 3984 emit_operand(dst, src); | |
| 3985 } | |
| 3986 | |
| 3987 void Assembler::movzwq(Register dst, Register src) { | |
| 3988 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3989 emit_byte(0x0F); | |
| 3990 emit_byte(0xB7); | |
| 3991 emit_byte(0xC0 | encode); | |
| 3992 } | |
| 3993 | |
| 304 | 3994 void Assembler::negq(Register dst) { |
| 3995 int encode = prefixq_and_encode(dst->encoding()); | |
| 3996 emit_byte(0xF7); | |
| 3997 emit_byte(0xD8 | encode); | |
| 3998 } | |
| 3999 | |
| 4000 void Assembler::notq(Register dst) { | |
| 4001 int encode = prefixq_and_encode(dst->encoding()); | |
| 4002 emit_byte(0xF7); | |
| 4003 emit_byte(0xD0 | encode); | |
| 4004 } | |
| 4005 | |
| 4006 void Assembler::orq(Address dst, int32_t imm32) { | |
| 4007 InstructionMark im(this); | |
| 4008 prefixq(dst); | |
| 4009 emit_byte(0x81); | |
| 4010 emit_operand(rcx, dst, 4); | |
| 4011 emit_long(imm32); | |
| 4012 } | |
| 4013 | |
| 4014 void Assembler::orq(Register dst, int32_t imm32) { | |
| 4015 (void) prefixq_and_encode(dst->encoding()); | |
| 4016 emit_arith(0x81, 0xC8, dst, imm32); | |
| 4017 } | |
| 4018 | |
| 4019 void Assembler::orq(Register dst, Address src) { | |
| 4020 InstructionMark im(this); | |
| 4021 prefixq(src, dst); | |
| 4022 emit_byte(0x0B); | |
| 4023 emit_operand(dst, src); | |
| 4024 } | |
| 4025 | |
| 4026 void Assembler::orq(Register dst, Register src) { | |
| 4027 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4028 emit_arith(0x0B, 0xC0, dst, src); | |
| 4029 } | |
| 4030 | |
| 4031 void Assembler::popa() { // 64bit | |
| 4032 movq(r15, Address(rsp, 0)); | |
| 4033 movq(r14, Address(rsp, wordSize)); | |
| 4034 movq(r13, Address(rsp, 2 * wordSize)); | |
| 4035 movq(r12, Address(rsp, 3 * wordSize)); | |
| 4036 movq(r11, Address(rsp, 4 * wordSize)); | |
| 4037 movq(r10, Address(rsp, 5 * wordSize)); | |
| 4038 movq(r9, Address(rsp, 6 * wordSize)); | |
| 4039 movq(r8, Address(rsp, 7 * wordSize)); | |
| 4040 movq(rdi, Address(rsp, 8 * wordSize)); | |
| 4041 movq(rsi, Address(rsp, 9 * wordSize)); | |
| 4042 movq(rbp, Address(rsp, 10 * wordSize)); | |
| 4043 // skip rsp | |
| 4044 movq(rbx, Address(rsp, 12 * wordSize)); | |
| 4045 movq(rdx, Address(rsp, 13 * wordSize)); | |
| 4046 movq(rcx, Address(rsp, 14 * wordSize)); | |
| 4047 movq(rax, Address(rsp, 15 * wordSize)); | |
| 4048 | |
| 4049 addq(rsp, 16 * wordSize); | |
| 4050 } | |
| 4051 | |
| 4052 void Assembler::popq(Address dst) { | |
| 4053 InstructionMark im(this); | |
| 4054 prefixq(dst); | |
| 4055 emit_byte(0x8F); | |
| 4056 emit_operand(rax, dst); | |
| 4057 } | |
| 4058 | |
| 4059 void Assembler::pusha() { // 64bit | |
| 4060 // we have to store original rsp. ABI says that 128 bytes | |
| 4061 // below rsp are local scratch. | |
| 4062 movq(Address(rsp, -5 * wordSize), rsp); | |
| 4063 | |
| 4064 subq(rsp, 16 * wordSize); | |
| 4065 | |
| 4066 movq(Address(rsp, 15 * wordSize), rax); | |
| 4067 movq(Address(rsp, 14 * wordSize), rcx); | |
| 4068 movq(Address(rsp, 13 * wordSize), rdx); | |
| 4069 movq(Address(rsp, 12 * wordSize), rbx); | |
| 4070 // skip rsp | |
| 4071 movq(Address(rsp, 10 * wordSize), rbp); | |
| 4072 movq(Address(rsp, 9 * wordSize), rsi); | |
| 4073 movq(Address(rsp, 8 * wordSize), rdi); | |
| 4074 movq(Address(rsp, 7 * wordSize), r8); | |
| 4075 movq(Address(rsp, 6 * wordSize), r9); | |
| 4076 movq(Address(rsp, 5 * wordSize), r10); | |
| 4077 movq(Address(rsp, 4 * wordSize), r11); | |
| 4078 movq(Address(rsp, 3 * wordSize), r12); | |
| 4079 movq(Address(rsp, 2 * wordSize), r13); | |
| 4080 movq(Address(rsp, wordSize), r14); | |
| 4081 movq(Address(rsp, 0), r15); | |
| 4082 } | |
| 4083 | |
| 4084 void Assembler::pushq(Address src) { | |
| 4085 InstructionMark im(this); | |
| 4086 prefixq(src); | |
| 4087 emit_byte(0xFF); | |
| 4088 emit_operand(rsi, src); | |
| 4089 } | |
| 4090 | |
| 4091 void Assembler::rclq(Register dst, int imm8) { | |
| 4092 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
| 4093 int encode = prefixq_and_encode(dst->encoding()); | |
| 4094 if (imm8 == 1) { | |
| 4095 emit_byte(0xD1); | |
| 4096 emit_byte(0xD0 | encode); | |
| 4097 } else { | |
| 4098 emit_byte(0xC1); | |
| 4099 emit_byte(0xD0 | encode); | |
| 4100 emit_byte(imm8); | |
| 4101 } | |
| 4102 } | |
| 4103 void Assembler::sarq(Register dst, int imm8) { | |
| 4104 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
| 4105 int encode = prefixq_and_encode(dst->encoding()); | |
| 4106 if (imm8 == 1) { | |
| 4107 emit_byte(0xD1); | |
| 4108 emit_byte(0xF8 | encode); | |
| 4109 } else { | |
| 4110 emit_byte(0xC1); | |
| 4111 emit_byte(0xF8 | encode); | |
| 4112 emit_byte(imm8); | |
| 4113 } | |
| 4114 } | |
| 4115 | |
| 4116 void Assembler::sarq(Register dst) { | |
| 4117 int encode = prefixq_and_encode(dst->encoding()); | |
| 4118 emit_byte(0xD3); | |
| 4119 emit_byte(0xF8 | encode); | |
| 4120 } | |
| 4121 void Assembler::sbbq(Address dst, int32_t imm32) { | |
| 4122 InstructionMark im(this); | |
| 4123 prefixq(dst); | |
| 4124 emit_arith_operand(0x81, rbx, dst, imm32); | |
| 4125 } | |
| 4126 | |
| 4127 void Assembler::sbbq(Register dst, int32_t imm32) { | |
| 4128 (void) prefixq_and_encode(dst->encoding()); | |
| 4129 emit_arith(0x81, 0xD8, dst, imm32); | |
| 4130 } | |
| 4131 | |
| 4132 void Assembler::sbbq(Register dst, Address src) { | |
| 4133 InstructionMark im(this); | |
| 4134 prefixq(src, dst); | |
| 4135 emit_byte(0x1B); | |
| 4136 emit_operand(dst, src); | |
| 4137 } | |
| 4138 | |
| 4139 void Assembler::sbbq(Register dst, Register src) { | |
| 4140 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4141 emit_arith(0x1B, 0xC0, dst, src); | |
| 4142 } | |
| 4143 | |
| 4144 void Assembler::shlq(Register dst, int imm8) { | |
| 4145 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
| 4146 int encode = prefixq_and_encode(dst->encoding()); | |
| 4147 if (imm8 == 1) { | |
| 4148 emit_byte(0xD1); | |
| 4149 emit_byte(0xE0 | encode); | |
| 4150 } else { | |
| 4151 emit_byte(0xC1); | |
| 4152 emit_byte(0xE0 | encode); | |
| 4153 emit_byte(imm8); | |
| 4154 } | |
| 4155 } | |
| 4156 | |
| 4157 void Assembler::shlq(Register dst) { | |
| 4158 int encode = prefixq_and_encode(dst->encoding()); | |
| 4159 emit_byte(0xD3); | |
| 4160 emit_byte(0xE0 | encode); | |
| 4161 } | |
| 4162 | |
| 4163 void Assembler::shrq(Register dst, int imm8) { | |
| 4164 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
| 4165 int encode = prefixq_and_encode(dst->encoding()); | |
| 4166 emit_byte(0xC1); | |
| 4167 emit_byte(0xE8 | encode); | |
| 4168 emit_byte(imm8); | |
| 4169 } | |
| 4170 | |
| 4171 void Assembler::shrq(Register dst) { | |
| 4172 int encode = prefixq_and_encode(dst->encoding()); | |
| 4173 emit_byte(0xD3); | |
| 4174 emit_byte(0xE8 | encode); | |
| 4175 } | |
| 4176 | |
| 4177 void Assembler::sqrtsd(XMMRegister dst, Address src) { | |
| 4178 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 0 | 4179 InstructionMark im(this); |
| 4180 emit_byte(0xF2); | |
| 304 | 4181 prefix(src, dst); |
| 0 | 4182 emit_byte(0x0F); |
| 304 | 4183 emit_byte(0x51); |
| 4184 emit_operand(dst, src); | |
| 4185 } | |
| 4186 | |
| 4187 void Assembler::subq(Address dst, int32_t imm32) { | |
| 4188 InstructionMark im(this); | |
| 4189 prefixq(dst); | |
| 4190 if (is8bit(imm32)) { | |
| 4191 emit_byte(0x83); | |
| 4192 emit_operand(rbp, dst, 1); | |
| 4193 emit_byte(imm32 & 0xFF); | |
| 4194 } else { | |
| 4195 emit_byte(0x81); | |
| 4196 emit_operand(rbp, dst, 4); | |
| 4197 emit_long(imm32); | |
| 4198 } | |
| 4199 } | |
| 4200 | |
| 4201 void Assembler::subq(Register dst, int32_t imm32) { | |
| 4202 (void) prefixq_and_encode(dst->encoding()); | |
| 4203 emit_arith(0x81, 0xE8, dst, imm32); | |
| 4204 } | |
| 4205 | |
| 4206 void Assembler::subq(Address dst, Register src) { | |
| 4207 InstructionMark im(this); | |
| 4208 prefixq(dst, src); | |
| 4209 emit_byte(0x29); | |
| 4210 emit_operand(src, dst); | |
| 4211 } | |
| 4212 | |
| 4213 void Assembler::subq(Register dst, Address src) { | |
| 4214 InstructionMark im(this); | |
| 4215 prefixq(src, dst); | |
| 4216 emit_byte(0x2B); | |
| 4217 emit_operand(dst, src); | |
| 4218 } | |
| 4219 | |
| 4220 void Assembler::subq(Register dst, Register src) { | |
| 4221 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4222 emit_arith(0x2B, 0xC0, dst, src); | |
| 4223 } | |
| 4224 | |
| 4225 void Assembler::testq(Register dst, int32_t imm32) { | |
| 4226 // not using emit_arith because test | |
| 4227 // doesn't support sign-extension of | |
| 4228 // 8bit operands | |
| 4229 int encode = dst->encoding(); | |
| 4230 if (encode == 0) { | |
| 4231 prefix(REX_W); | |
| 4232 emit_byte(0xA9); | |
| 4233 } else { | |
| 4234 encode = prefixq_and_encode(encode); | |
| 4235 emit_byte(0xF7); | |
| 4236 emit_byte(0xC0 | encode); | |
| 4237 } | |
| 4238 emit_long(imm32); | |
| 4239 } | |
| 4240 | |
| 4241 void Assembler::testq(Register dst, Register src) { | |
| 4242 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4243 emit_arith(0x85, 0xC0, dst, src); | |
| 4244 } | |
| 4245 | |
| 4246 void Assembler::xaddq(Address dst, Register src) { | |
| 4247 InstructionMark im(this); | |
| 4248 prefixq(dst, src); | |
| 71 | 4249 emit_byte(0x0F); |
| 304 | 4250 emit_byte(0xC1); |
| 4251 emit_operand(src, dst); | |
| 4252 } | |
| 4253 | |
| 4254 void Assembler::xchgq(Register dst, Address src) { | |
| 4255 InstructionMark im(this); | |
| 4256 prefixq(src, dst); | |
| 4257 emit_byte(0x87); | |
| 4258 emit_operand(dst, src); | |
| 4259 } | |
| 4260 | |
| 4261 void Assembler::xchgq(Register dst, Register src) { | |
| 4262 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4263 emit_byte(0x87); | |
| 4264 emit_byte(0xc0 | encode); | |
| 4265 } | |
| 4266 | |
| 4267 void Assembler::xorq(Register dst, Register src) { | |
| 4268 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4269 emit_arith(0x33, 0xC0, dst, src); | |
| 4270 } | |
| 4271 | |
| 4272 void Assembler::xorq(Register dst, Address src) { | |
| 4273 InstructionMark im(this); | |
| 4274 prefixq(src, dst); | |
| 4275 emit_byte(0x33); | |
| 4276 emit_operand(dst, src); | |
| 4277 } | |
| 4278 | |
| 4279 #endif // !LP64 | |
| 4280 | |
| 4281 static Assembler::Condition reverse[] = { | |
| 4282 Assembler::noOverflow /* overflow = 0x0 */ , | |
| 4283 Assembler::overflow /* noOverflow = 0x1 */ , | |
| 4284 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ , | |
| 4285 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ , | |
| 4286 Assembler::notZero /* zero = 0x4, equal = 0x4 */ , | |
| 4287 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ , | |
| 4288 Assembler::above /* belowEqual = 0x6 */ , | |
| 4289 Assembler::belowEqual /* above = 0x7 */ , | |
| 4290 Assembler::positive /* negative = 0x8 */ , | |
| 4291 Assembler::negative /* positive = 0x9 */ , | |
| 4292 Assembler::noParity /* parity = 0xa */ , | |
| 4293 Assembler::parity /* noParity = 0xb */ , | |
| 4294 Assembler::greaterEqual /* less = 0xc */ , | |
| 4295 Assembler::less /* greaterEqual = 0xd */ , | |
| 4296 Assembler::greater /* lessEqual = 0xe */ , | |
| 4297 Assembler::lessEqual /* greater = 0xf, */ | |
| 4298 | |
| 4299 }; | |
| 4300 | |
| 0 | 4301 |
| 4302 // Implementation of MacroAssembler | |
| 4303 | |
| 304 | 4304 // First all the versions that have distinct versions depending on 32/64 bit |
| 4305 // Unless the difference is trivial (1 line or so). | |
| 4306 | |
| 4307 #ifndef _LP64 | |
| 4308 | |
| 4309 // 32bit versions | |
| 4310 | |
| 0 | 4311 Address MacroAssembler::as_Address(AddressLiteral adr) { |
| 4312 return Address(adr.target(), adr.rspec()); | |
| 4313 } | |
| 4314 | |
| 4315 Address MacroAssembler::as_Address(ArrayAddress adr) { | |
| 4316 return Address::make_array(adr); | |
| 4317 } | |
| 4318 | |
| 304 | 4319 int MacroAssembler::biased_locking_enter(Register lock_reg, |
| 4320 Register obj_reg, | |
| 4321 Register swap_reg, | |
| 4322 Register tmp_reg, | |
| 4323 bool swap_reg_contains_mark, | |
| 4324 Label& done, | |
| 4325 Label* slow_case, | |
| 4326 BiasedLockingCounters* counters) { | |
| 4327 assert(UseBiasedLocking, "why call this otherwise?"); | |
| 4328 assert(swap_reg == rax, "swap_reg must be rax, for cmpxchg"); | |
| 4329 assert_different_registers(lock_reg, obj_reg, swap_reg); | |
| 4330 | |
| 4331 if (PrintBiasedLockingStatistics && counters == NULL) | |
| 4332 counters = BiasedLocking::counters(); | |
| 4333 | |
| 4334 bool need_tmp_reg = false; | |
| 4335 if (tmp_reg == noreg) { | |
| 4336 need_tmp_reg = true; | |
| 4337 tmp_reg = lock_reg; | |
| 4338 } else { | |
| 4339 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg); | |
| 4340 } | |
| 4341 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); | |
| 4342 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes()); | |
| 4343 Address klass_addr (obj_reg, oopDesc::klass_offset_in_bytes()); | |
| 4344 Address saved_mark_addr(lock_reg, 0); | |
| 4345 | |
| 4346 // Biased locking | |
| 4347 // See whether the lock is currently biased toward our thread and | |
| 4348 // whether the epoch is still valid | |
| 4349 // Note that the runtime guarantees sufficient alignment of JavaThread | |
| 4350 // pointers to allow age to be placed into low bits | |
| 4351 // First check to see whether biasing is even enabled for this object | |
| 4352 Label cas_label; | |
| 4353 int null_check_offset = -1; | |
| 4354 if (!swap_reg_contains_mark) { | |
| 4355 null_check_offset = offset(); | |
| 4356 movl(swap_reg, mark_addr); | |
| 4357 } | |
| 4358 if (need_tmp_reg) { | |
| 4359 push(tmp_reg); | |
| 4360 } | |
| 4361 movl(tmp_reg, swap_reg); | |
| 4362 andl(tmp_reg, markOopDesc::biased_lock_mask_in_place); | |
| 4363 cmpl(tmp_reg, markOopDesc::biased_lock_pattern); | |
| 4364 if (need_tmp_reg) { | |
| 4365 pop(tmp_reg); | |
| 4366 } | |
| 4367 jcc(Assembler::notEqual, cas_label); | |
| 4368 // The bias pattern is present in the object's header. Need to check | |
| 4369 // whether the bias owner and the epoch are both still current. | |
| 4370 // Note that because there is no current thread register on x86 we | |
| 4371 // need to store off the mark word we read out of the object to | |
| 4372 // avoid reloading it and needing to recheck invariants below. This | |
| 4373 // store is unfortunate but it makes the overall code shorter and | |
| 4374 // simpler. | |
| 4375 movl(saved_mark_addr, swap_reg); | |
| 4376 if (need_tmp_reg) { | |
| 4377 push(tmp_reg); | |
| 4378 } | |
| 4379 get_thread(tmp_reg); | |
| 4380 xorl(swap_reg, tmp_reg); | |
| 4381 if (swap_reg_contains_mark) { | |
| 4382 null_check_offset = offset(); | |
| 4383 } | |
| 4384 movl(tmp_reg, klass_addr); | |
| 4385 xorl(swap_reg, Address(tmp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); | |
| 4386 andl(swap_reg, ~((int) markOopDesc::age_mask_in_place)); | |
| 4387 if (need_tmp_reg) { | |
| 4388 pop(tmp_reg); | |
| 4389 } | |
| 4390 if (counters != NULL) { | |
| 4391 cond_inc32(Assembler::zero, | |
| 4392 ExternalAddress((address)counters->biased_lock_entry_count_addr())); | |
| 4393 } | |
| 4394 jcc(Assembler::equal, done); | |
| 4395 | |
| 4396 Label try_revoke_bias; | |
| 4397 Label try_rebias; | |
| 4398 | |
| 4399 // At this point we know that the header has the bias pattern and | |
| 4400 // that we are not the bias owner in the current epoch. We need to | |
| 4401 // figure out more details about the state of the header in order to | |
| 4402 // know what operations can be legally performed on the object's | |
| 4403 // header. | |
| 4404 | |
| 4405 // If the low three bits in the xor result aren't clear, that means | |
| 4406 // the prototype header is no longer biased and we have to revoke | |
| 4407 // the bias on this object. | |
| 4408 testl(swap_reg, markOopDesc::biased_lock_mask_in_place); | |
| 4409 jcc(Assembler::notZero, try_revoke_bias); | |
| 4410 | |
| 4411 // Biasing is still enabled for this data type. See whether the | |
| 4412 // epoch of the current bias is still valid, meaning that the epoch | |
| 4413 // bits of the mark word are equal to the epoch bits of the | |
| 4414 // prototype header. (Note that the prototype header's epoch bits | |
| 4415 // only change at a safepoint.) If not, attempt to rebias the object | |
| 4416 // toward the current thread. Note that we must be absolutely sure | |
| 4417 // that the current epoch is invalid in order to do this because | |
| 4418 // otherwise the manipulations it performs on the mark word are | |
| 4419 // illegal. | |
| 4420 testl(swap_reg, markOopDesc::epoch_mask_in_place); | |
| 4421 jcc(Assembler::notZero, try_rebias); | |
| 4422 | |
| 4423 // The epoch of the current bias is still valid but we know nothing | |
| 4424 // about the owner; it might be set or it might be clear. Try to | |
| 4425 // acquire the bias of the object using an atomic operation. If this | |
| 4426 // fails we will go in to the runtime to revoke the object's bias. | |
| 4427 // Note that we first construct the presumed unbiased header so we | |
| 4428 // don't accidentally blow away another thread's valid bias. | |
| 4429 movl(swap_reg, saved_mark_addr); | |
| 4430 andl(swap_reg, | |
| 4431 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place); | |
| 4432 if (need_tmp_reg) { | |
| 4433 push(tmp_reg); | |
| 4434 } | |
| 4435 get_thread(tmp_reg); | |
| 4436 orl(tmp_reg, swap_reg); | |
| 4437 if (os::is_MP()) { | |
| 4438 lock(); | |
| 4439 } | |
| 4440 cmpxchgptr(tmp_reg, Address(obj_reg, 0)); | |
| 4441 if (need_tmp_reg) { | |
| 4442 pop(tmp_reg); | |
| 4443 } | |
| 4444 // If the biasing toward our thread failed, this means that | |
| 4445 // another thread succeeded in biasing it toward itself and we | |
| 4446 // need to revoke that bias. The revocation will occur in the | |
| 4447 // interpreter runtime in the slow case. | |
| 4448 if (counters != NULL) { | |
| 4449 cond_inc32(Assembler::zero, | |
| 4450 ExternalAddress((address)counters->anonymously_biased_lock_entry_count_addr())); | |
| 4451 } | |
| 4452 if (slow_case != NULL) { | |
| 4453 jcc(Assembler::notZero, *slow_case); | |
| 4454 } | |
| 4455 jmp(done); | |
| 4456 | |
| 4457 bind(try_rebias); | |
| 4458 // At this point we know the epoch has expired, meaning that the | |
| 4459 // current "bias owner", if any, is actually invalid. Under these | |
| 4460 // circumstances _only_, we are allowed to use the current header's | |
| 4461 // value as the comparison value when doing the cas to acquire the | |
| 4462 // bias in the current epoch. In other words, we allow transfer of | |
| 4463 // the bias from one thread to another directly in this situation. | |
| 4464 // | |
| 4465 // FIXME: due to a lack of registers we currently blow away the age | |
| 4466 // bits in this situation. Should attempt to preserve them. | |
| 4467 if (need_tmp_reg) { | |
| 4468 push(tmp_reg); | |
| 4469 } | |
| 4470 get_thread(tmp_reg); | |
| 4471 movl(swap_reg, klass_addr); | |
| 4472 orl(tmp_reg, Address(swap_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); | |
| 4473 movl(swap_reg, saved_mark_addr); | |
| 4474 if (os::is_MP()) { | |
| 4475 lock(); | |
| 4476 } | |
| 4477 cmpxchgptr(tmp_reg, Address(obj_reg, 0)); | |
| 4478 if (need_tmp_reg) { | |
| 4479 pop(tmp_reg); | |
| 4480 } | |
| 4481 // If the biasing toward our thread failed, then another thread | |
| 4482 // succeeded in biasing it toward itself and we need to revoke that | |
| 4483 // bias. The revocation will occur in the runtime in the slow case. | |
| 4484 if (counters != NULL) { | |
| 4485 cond_inc32(Assembler::zero, | |
| 4486 ExternalAddress((address)counters->rebiased_lock_entry_count_addr())); | |
| 4487 } | |
| 4488 if (slow_case != NULL) { | |
| 4489 jcc(Assembler::notZero, *slow_case); | |
| 4490 } | |
| 4491 jmp(done); | |
| 4492 | |
| 4493 bind(try_revoke_bias); | |
| 4494 // The prototype mark in the klass doesn't have the bias bit set any | |
| 4495 // more, indicating that objects of this data type are not supposed | |
| 4496 // to be biased any more. We are going to try to reset the mark of | |
| 4497 // this object to the prototype value and fall through to the | |
| 4498 // CAS-based locking scheme. Note that if our CAS fails, it means | |
| 4499 // that another thread raced us for the privilege of revoking the | |
| 4500 // bias of this particular object, so it's okay to continue in the | |
| 4501 // normal locking code. | |
| 4502 // | |
| 4503 // FIXME: due to a lack of registers we currently blow away the age | |
| 4504 // bits in this situation. Should attempt to preserve them. | |
| 4505 movl(swap_reg, saved_mark_addr); | |
| 4506 if (need_tmp_reg) { | |
| 4507 push(tmp_reg); | |
| 4508 } | |
| 4509 movl(tmp_reg, klass_addr); | |
| 4510 movl(tmp_reg, Address(tmp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); | |
| 4511 if (os::is_MP()) { | |
| 4512 lock(); | |
| 4513 } | |
| 4514 cmpxchgptr(tmp_reg, Address(obj_reg, 0)); | |
| 4515 if (need_tmp_reg) { | |
| 4516 pop(tmp_reg); | |
| 4517 } | |
| 4518 // Fall through to the normal CAS-based lock, because no matter what | |
| 4519 // the result of the above CAS, some thread must have succeeded in | |
| 4520 // removing the bias bit from the object's header. | |
| 4521 if (counters != NULL) { | |
| 4522 cond_inc32(Assembler::zero, | |
| 4523 ExternalAddress((address)counters->revoked_lock_entry_count_addr())); | |
| 4524 } | |
| 4525 | |
| 4526 bind(cas_label); | |
| 4527 | |
| 4528 return null_check_offset; | |
| 4529 } | |
| 4530 void MacroAssembler::call_VM_leaf_base(address entry_point, | |
| 4531 int number_of_arguments) { | |
| 4532 call(RuntimeAddress(entry_point)); | |
| 4533 increment(rsp, number_of_arguments * wordSize); | |
| 4534 } | |
| 4535 | |
| 4536 void MacroAssembler::cmpoop(Address src1, jobject obj) { | |
| 4537 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); | |
| 4538 } | |
| 4539 | |
| 4540 void MacroAssembler::cmpoop(Register src1, jobject obj) { | |
| 4541 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); | |
| 4542 } | |
| 4543 | |
| 4544 void MacroAssembler::extend_sign(Register hi, Register lo) { | |
| 4545 // According to Intel Doc. AP-526, "Integer Divide", p.18. | |
| 4546 if (VM_Version::is_P6() && hi == rdx && lo == rax) { | |
| 4547 cdql(); | |
| 4548 } else { | |
| 4549 movl(hi, lo); | |
| 4550 sarl(hi, 31); | |
| 4551 } | |
| 4552 } | |
| 4553 | |
| 0 | 4554 void MacroAssembler::fat_nop() { |
| 4555 // A 5 byte nop that is safe for patching (see patch_verified_entry) | |
| 4556 emit_byte(0x26); // es: | |
| 4557 emit_byte(0x2e); // cs: | |
| 4558 emit_byte(0x64); // fs: | |
| 4559 emit_byte(0x65); // gs: | |
| 4560 emit_byte(0x90); | |
| 4561 } | |
| 4562 | |
| 304 | 4563 void MacroAssembler::jC2(Register tmp, Label& L) { |
| 4564 // set parity bit if FPU flag C2 is set (via rax) | |
| 4565 save_rax(tmp); | |
| 4566 fwait(); fnstsw_ax(); | |
| 4567 sahf(); | |
| 4568 restore_rax(tmp); | |
| 4569 // branch | |
| 4570 jcc(Assembler::parity, L); | |
| 4571 } | |
| 4572 | |
| 4573 void MacroAssembler::jnC2(Register tmp, Label& L) { | |
| 4574 // set parity bit if FPU flag C2 is set (via rax) | |
| 4575 save_rax(tmp); | |
| 4576 fwait(); fnstsw_ax(); | |
| 4577 sahf(); | |
| 4578 restore_rax(tmp); | |
| 4579 // branch | |
| 4580 jcc(Assembler::noParity, L); | |
| 4581 } | |
| 4582 | |
| 0 | 4583 // 32bit can do a case table jump in one instruction but we no longer allow the base |
| 4584 // to be installed in the Address class | |
| 4585 void MacroAssembler::jump(ArrayAddress entry) { | |
| 4586 jmp(as_Address(entry)); | |
| 4587 } | |
| 4588 | |
| 304 | 4589 // Note: y_lo will be destroyed |
| 4590 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { | |
| 4591 // Long compare for Java (semantics as described in JVM spec.) | |
| 4592 Label high, low, done; | |
| 4593 | |
| 4594 cmpl(x_hi, y_hi); | |
| 4595 jcc(Assembler::less, low); | |
| 4596 jcc(Assembler::greater, high); | |
| 4597 // x_hi is the return register | |
| 4598 xorl(x_hi, x_hi); | |
| 4599 cmpl(x_lo, y_lo); | |
| 4600 jcc(Assembler::below, low); | |
| 4601 jcc(Assembler::equal, done); | |
| 4602 | |
| 4603 bind(high); | |
| 4604 xorl(x_hi, x_hi); | |
| 4605 increment(x_hi); | |
| 4606 jmp(done); | |
| 4607 | |
| 4608 bind(low); | |
| 4609 xorl(x_hi, x_hi); | |
| 4610 decrementl(x_hi); | |
| 4611 | |
| 4612 bind(done); | |
| 4613 } | |
| 4614 | |
| 4615 void MacroAssembler::lea(Register dst, AddressLiteral src) { | |
| 4616 mov_literal32(dst, (int32_t)src.target(), src.rspec()); | |
| 0 | 4617 } |
| 4618 | |
| 4619 void MacroAssembler::lea(Address dst, AddressLiteral adr) { | |
| 4620 // leal(dst, as_Address(adr)); | |
| 304 | 4621 // see note in movl as to why we must use a move |
| 0 | 4622 mov_literal32(dst, (int32_t) adr.target(), adr.rspec()); |
| 4623 } | |
| 4624 | |
| 4625 void MacroAssembler::leave() { | |
| 304 | 4626 mov(rsp, rbp); |
| 4627 pop(rbp); | |
| 4628 } | |
| 0 | 4629 |
| 4630 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) { | |
| 4631 // Multiplication of two Java long values stored on the stack | |
| 4632 // as illustrated below. Result is in rdx:rax. | |
| 4633 // | |
| 4634 // rsp ---> [ ?? ] \ \ | |
| 4635 // .... | y_rsp_offset | | |
| 4636 // [ y_lo ] / (in bytes) | x_rsp_offset | |
| 4637 // [ y_hi ] | (in bytes) | |
| 4638 // .... | | |
| 4639 // [ x_lo ] / | |
| 4640 // [ x_hi ] | |
| 4641 // .... | |
| 4642 // | |
| 4643 // Basic idea: lo(result) = lo(x_lo * y_lo) | |
| 4644 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) | |
| 4645 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset); | |
| 4646 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset); | |
| 4647 Label quick; | |
| 4648 // load x_hi, y_hi and check if quick | |
| 4649 // multiplication is possible | |
| 4650 movl(rbx, x_hi); | |
| 4651 movl(rcx, y_hi); | |
| 4652 movl(rax, rbx); | |
| 4653 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0 | |
| 4654 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply | |
| 4655 // do full multiplication | |
| 4656 // 1st step | |
| 4657 mull(y_lo); // x_hi * y_lo | |
| 4658 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx, | |
| 4659 // 2nd step | |
| 4660 movl(rax, x_lo); | |
| 4661 mull(rcx); // x_lo * y_hi | |
| 4662 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx, | |
| 4663 // 3rd step | |
| 4664 bind(quick); // note: rbx, = 0 if quick multiply! | |
| 4665 movl(rax, x_lo); | |
| 4666 mull(y_lo); // x_lo * y_lo | |
| 4667 addl(rdx, rbx); // correct hi(x_lo * y_lo) | |
| 4668 } | |
| 4669 | |
| 304 | 4670 void MacroAssembler::lneg(Register hi, Register lo) { |
| 4671 negl(lo); | |
| 4672 adcl(hi, 0); | |
| 4673 negl(hi); | |
| 4674 } | |
| 0 | 4675 |
| 4676 void MacroAssembler::lshl(Register hi, Register lo) { | |
| 4677 // Java shift left long support (semantics as described in JVM spec., p.305) | |
| 4678 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n)) | |
| 4679 // shift value is in rcx ! | |
| 4680 assert(hi != rcx, "must not use rcx"); | |
| 4681 assert(lo != rcx, "must not use rcx"); | |
| 4682 const Register s = rcx; // shift count | |
| 4683 const int n = BitsPerWord; | |
| 4684 Label L; | |
| 4685 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) | |
| 4686 cmpl(s, n); // if (s < n) | |
| 4687 jcc(Assembler::less, L); // else (s >= n) | |
| 4688 movl(hi, lo); // x := x << n | |
| 4689 xorl(lo, lo); | |
| 4690 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! | |
| 4691 bind(L); // s (mod n) < n | |
| 4692 shldl(hi, lo); // x := x << s | |
| 4693 shll(lo); | |
| 4694 } | |
| 4695 | |
| 4696 | |
| 4697 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) { | |
| 4698 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310) | |
| 4699 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n)) | |
| 4700 assert(hi != rcx, "must not use rcx"); | |
| 4701 assert(lo != rcx, "must not use rcx"); | |
| 4702 const Register s = rcx; // shift count | |
| 4703 const int n = BitsPerWord; | |
| 4704 Label L; | |
| 4705 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) | |
| 4706 cmpl(s, n); // if (s < n) | |
| 4707 jcc(Assembler::less, L); // else (s >= n) | |
| 4708 movl(lo, hi); // x := x >> n | |
| 4709 if (sign_extension) sarl(hi, 31); | |
| 4710 else xorl(hi, hi); | |
| 4711 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! | |
| 4712 bind(L); // s (mod n) < n | |
| 4713 shrdl(lo, hi); // x := x >> s | |
| 4714 if (sign_extension) sarl(hi); | |
| 4715 else shrl(hi); | |
| 4716 } | |
| 4717 | |
| 304 | 4718 void MacroAssembler::movoop(Register dst, jobject obj) { |
| 4719 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); | |
| 4720 } | |
| 4721 | |
| 4722 void MacroAssembler::movoop(Address dst, jobject obj) { | |
| 4723 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); | |
| 4724 } | |
| 4725 | |
| 4726 void MacroAssembler::movptr(Register dst, AddressLiteral src) { | |
| 4727 if (src.is_lval()) { | |
| 4728 mov_literal32(dst, (intptr_t)src.target(), src.rspec()); | |
| 4729 } else { | |
| 4730 movl(dst, as_Address(src)); | |
| 4731 } | |
| 4732 } | |
| 4733 | |
| 4734 void MacroAssembler::movptr(ArrayAddress dst, Register src) { | |
| 4735 movl(as_Address(dst), src); | |
| 4736 } | |
| 4737 | |
| 4738 void MacroAssembler::movptr(Register dst, ArrayAddress src) { | |
| 4739 movl(dst, as_Address(src)); | |
| 4740 } | |
| 4741 | |
| 4742 // src should NEVER be a real pointer. Use AddressLiteral for true pointers | |
| 4743 void MacroAssembler::movptr(Address dst, intptr_t src) { | |
| 4744 movl(dst, src); | |
| 4745 } | |
| 4746 | |
| 4747 | |
| 4748 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) { | |
| 4749 movsd(dst, as_Address(src)); | |
| 4750 } | |
| 4751 | |
| 4752 void MacroAssembler::pop_callee_saved_registers() { | |
| 4753 pop(rcx); | |
| 4754 pop(rdx); | |
| 4755 pop(rdi); | |
| 4756 pop(rsi); | |
| 4757 } | |
| 4758 | |
| 4759 void MacroAssembler::pop_fTOS() { | |
| 4760 fld_d(Address(rsp, 0)); | |
| 4761 addl(rsp, 2 * wordSize); | |
| 4762 } | |
| 4763 | |
| 4764 void MacroAssembler::push_callee_saved_registers() { | |
| 4765 push(rsi); | |
| 4766 push(rdi); | |
| 4767 push(rdx); | |
| 4768 push(rcx); | |
| 4769 } | |
| 4770 | |
| 4771 void MacroAssembler::push_fTOS() { | |
| 4772 subl(rsp, 2 * wordSize); | |
| 4773 fstp_d(Address(rsp, 0)); | |
| 4774 } | |
| 4775 | |
| 4776 | |
| 4777 void MacroAssembler::pushoop(jobject obj) { | |
| 4778 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate()); | |
| 4779 } | |
| 4780 | |
| 4781 | |
| 4782 void MacroAssembler::pushptr(AddressLiteral src) { | |
| 4783 if (src.is_lval()) { | |
| 4784 push_literal32((int32_t)src.target(), src.rspec()); | |
| 4785 } else { | |
| 4786 pushl(as_Address(src)); | |
| 4787 } | |
| 4788 } | |
| 4789 | |
| 4790 void MacroAssembler::set_word_if_not_zero(Register dst) { | |
| 4791 xorl(dst, dst); | |
| 4792 set_byte_if_not_zero(dst); | |
| 4793 } | |
| 4794 | |
| 4795 static void pass_arg0(MacroAssembler* masm, Register arg) { | |
| 4796 masm->push(arg); | |
| 4797 } | |
| 4798 | |
| 4799 static void pass_arg1(MacroAssembler* masm, Register arg) { | |
| 4800 masm->push(arg); | |
| 4801 } | |
| 4802 | |
| 4803 static void pass_arg2(MacroAssembler* masm, Register arg) { | |
| 4804 masm->push(arg); | |
| 4805 } | |
| 4806 | |
| 4807 static void pass_arg3(MacroAssembler* masm, Register arg) { | |
| 4808 masm->push(arg); | |
| 4809 } | |
| 4810 | |
| 4811 #ifndef PRODUCT | |
| 4812 extern "C" void findpc(intptr_t x); | |
| 4813 #endif | |
| 4814 | |
| 4815 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) { | |
| 4816 // In order to get locks to work, we need to fake a in_VM state | |
| 4817 JavaThread* thread = JavaThread::current(); | |
| 4818 JavaThreadState saved_state = thread->thread_state(); | |
| 4819 thread->set_thread_state(_thread_in_vm); | |
| 4820 if (ShowMessageBoxOnError) { | |
| 4821 JavaThread* thread = JavaThread::current(); | |
| 4822 JavaThreadState saved_state = thread->thread_state(); | |
| 4823 thread->set_thread_state(_thread_in_vm); | |
| 4824 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { | |
| 4825 ttyLocker ttyl; | |
| 4826 BytecodeCounter::print(); | |
| 4827 } | |
| 4828 // To see where a verify_oop failed, get $ebx+40/X for this frame. | |
| 4829 // This is the value of eip which points to where verify_oop will return. | |
| 4830 if (os::message_box(msg, "Execution stopped, print registers?")) { | |
| 4831 ttyLocker ttyl; | |
| 4832 tty->print_cr("eip = 0x%08x", eip); | |
| 4833 #ifndef PRODUCT | |
| 4834 tty->cr(); | |
| 4835 findpc(eip); | |
| 4836 tty->cr(); | |
| 4837 #endif | |
| 4838 tty->print_cr("rax, = 0x%08x", rax); | |
| 4839 tty->print_cr("rbx, = 0x%08x", rbx); | |
| 4840 tty->print_cr("rcx = 0x%08x", rcx); | |
| 4841 tty->print_cr("rdx = 0x%08x", rdx); | |
| 4842 tty->print_cr("rdi = 0x%08x", rdi); | |
| 4843 tty->print_cr("rsi = 0x%08x", rsi); | |
| 4844 tty->print_cr("rbp, = 0x%08x", rbp); | |
| 4845 tty->print_cr("rsp = 0x%08x", rsp); | |
| 4846 BREAKPOINT; | |
| 4847 } | |
| 4848 } else { | |
| 4849 ttyLocker ttyl; | |
| 4850 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg); | |
| 4851 assert(false, "DEBUG MESSAGE"); | |
| 4852 } | |
| 4853 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); | |
| 4854 } | |
| 4855 | |
| 4856 void MacroAssembler::stop(const char* msg) { | |
| 4857 ExternalAddress message((address)msg); | |
| 4858 // push address of message | |
| 4859 pushptr(message.addr()); | |
| 4860 { Label L; call(L, relocInfo::none); bind(L); } // push eip | |
| 4861 pusha(); // push registers | |
| 4862 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32))); | |
| 4863 hlt(); | |
| 4864 } | |
| 4865 | |
| 4866 void MacroAssembler::warn(const char* msg) { | |
| 4867 push_CPU_state(); | |
| 4868 | |
| 4869 ExternalAddress message((address) msg); | |
| 4870 // push address of message | |
| 4871 pushptr(message.addr()); | |
| 4872 | |
| 4873 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning))); | |
| 4874 addl(rsp, wordSize); // discard argument | |
| 4875 pop_CPU_state(); | |
| 4876 } | |
| 4877 | |
| 4878 #else // _LP64 | |
| 4879 | |
| 4880 // 64 bit versions | |
| 4881 | |
| 4882 Address MacroAssembler::as_Address(AddressLiteral adr) { | |
| 4883 // amd64 always does this as a pc-rel | |
| 4884 // we can be absolute or disp based on the instruction type | |
| 4885 // jmp/call are displacements others are absolute | |
| 4886 assert(!adr.is_lval(), "must be rval"); | |
| 4887 assert(reachable(adr), "must be"); | |
| 4888 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc()); | |
| 4889 | |
| 4890 } | |
| 4891 | |
| 4892 Address MacroAssembler::as_Address(ArrayAddress adr) { | |
| 4893 AddressLiteral base = adr.base(); | |
| 4894 lea(rscratch1, base); | |
| 4895 Address index = adr.index(); | |
| 4896 assert(index._disp == 0, "must not have disp"); // maybe it can? | |
| 4897 Address array(rscratch1, index._index, index._scale, index._disp); | |
| 4898 return array; | |
| 4899 } | |
| 4900 | |
| 4901 int MacroAssembler::biased_locking_enter(Register lock_reg, | |
| 4902 Register obj_reg, | |
| 4903 Register swap_reg, | |
| 4904 Register tmp_reg, | |
| 4905 bool swap_reg_contains_mark, | |
| 4906 Label& done, | |
| 4907 Label* slow_case, | |
| 4908 BiasedLockingCounters* counters) { | |
| 4909 assert(UseBiasedLocking, "why call this otherwise?"); | |
| 4910 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq"); | |
| 4911 assert(tmp_reg != noreg, "tmp_reg must be supplied"); | |
| 4912 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg); | |
| 4913 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); | |
| 4914 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes()); | |
| 4915 Address saved_mark_addr(lock_reg, 0); | |
| 4916 | |
| 4917 if (PrintBiasedLockingStatistics && counters == NULL) | |
| 4918 counters = BiasedLocking::counters(); | |
| 4919 | |
| 4920 // Biased locking | |
| 4921 // See whether the lock is currently biased toward our thread and | |
| 4922 // whether the epoch is still valid | |
| 4923 // Note that the runtime guarantees sufficient alignment of JavaThread | |
| 4924 // pointers to allow age to be placed into low bits | |
| 4925 // First check to see whether biasing is even enabled for this object | |
| 4926 Label cas_label; | |
| 4927 int null_check_offset = -1; | |
| 4928 if (!swap_reg_contains_mark) { | |
| 4929 null_check_offset = offset(); | |
| 4930 movq(swap_reg, mark_addr); | |
| 4931 } | |
| 4932 movq(tmp_reg, swap_reg); | |
| 4933 andq(tmp_reg, markOopDesc::biased_lock_mask_in_place); | |
| 4934 cmpq(tmp_reg, markOopDesc::biased_lock_pattern); | |
| 4935 jcc(Assembler::notEqual, cas_label); | |
| 4936 // The bias pattern is present in the object's header. Need to check | |
| 4937 // whether the bias owner and the epoch are both still current. | |
| 4938 load_prototype_header(tmp_reg, obj_reg); | |
| 4939 orq(tmp_reg, r15_thread); | |
| 4940 xorq(tmp_reg, swap_reg); | |
| 4941 andq(tmp_reg, ~((int) markOopDesc::age_mask_in_place)); | |
| 4942 if (counters != NULL) { | |
| 4943 cond_inc32(Assembler::zero, | |
| 4944 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr())); | |
| 4945 } | |
| 0 | 4946 jcc(Assembler::equal, done); |
| 4947 | |
| 304 | 4948 Label try_revoke_bias; |
| 4949 Label try_rebias; | |
| 4950 | |
| 4951 // At this point we know that the header has the bias pattern and | |
| 4952 // that we are not the bias owner in the current epoch. We need to | |
| 4953 // figure out more details about the state of the header in order to | |
| 4954 // know what operations can be legally performed on the object's | |
| 4955 // header. | |
| 4956 | |
| 4957 // If the low three bits in the xor result aren't clear, that means | |
| 4958 // the prototype header is no longer biased and we have to revoke | |
| 4959 // the bias on this object. | |
| 4960 testq(tmp_reg, markOopDesc::biased_lock_mask_in_place); | |
| 4961 jcc(Assembler::notZero, try_revoke_bias); | |
| 4962 | |
| 4963 // Biasing is still enabled for this data type. See whether the | |
| 4964 // epoch of the current bias is still valid, meaning that the epoch | |
| 4965 // bits of the mark word are equal to the epoch bits of the | |
| 4966 // prototype header. (Note that the prototype header's epoch bits | |
| 4967 // only change at a safepoint.) If not, attempt to rebias the object | |
| 4968 // toward the current thread. Note that we must be absolutely sure | |
| 4969 // that the current epoch is invalid in order to do this because | |
| 4970 // otherwise the manipulations it performs on the mark word are | |
| 4971 // illegal. | |
| 4972 testq(tmp_reg, markOopDesc::epoch_mask_in_place); | |
| 4973 jcc(Assembler::notZero, try_rebias); | |
| 4974 | |
| 4975 // The epoch of the current bias is still valid but we know nothing | |
| 4976 // about the owner; it might be set or it might be clear. Try to | |
| 4977 // acquire the bias of the object using an atomic operation. If this | |
| 4978 // fails we will go in to the runtime to revoke the object's bias. | |
| 4979 // Note that we first construct the presumed unbiased header so we | |
| 4980 // don't accidentally blow away another thread's valid bias. | |
| 4981 andq(swap_reg, | |
| 4982 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place); | |
| 4983 movq(tmp_reg, swap_reg); | |
| 4984 orq(tmp_reg, r15_thread); | |
| 4985 if (os::is_MP()) { | |
| 4986 lock(); | |
| 4987 } | |
| 4988 cmpxchgq(tmp_reg, Address(obj_reg, 0)); | |
| 4989 // If the biasing toward our thread failed, this means that | |
| 4990 // another thread succeeded in biasing it toward itself and we | |
| 4991 // need to revoke that bias. The revocation will occur in the | |
| 4992 // interpreter runtime in the slow case. | |
| 4993 if (counters != NULL) { | |
| 4994 cond_inc32(Assembler::zero, | |
| 4995 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr())); | |
| 4996 } | |
| 4997 if (slow_case != NULL) { | |
| 4998 jcc(Assembler::notZero, *slow_case); | |
| 4999 } | |
| 0 | 5000 jmp(done); |
| 5001 | |
| 304 | 5002 bind(try_rebias); |
| 5003 // At this point we know the epoch has expired, meaning that the | |
| 5004 // current "bias owner", if any, is actually invalid. Under these | |
| 5005 // circumstances _only_, we are allowed to use the current header's | |
| 5006 // value as the comparison value when doing the cas to acquire the | |
| 5007 // bias in the current epoch. In other words, we allow transfer of | |
| 5008 // the bias from one thread to another directly in this situation. | |
| 5009 // | |
| 5010 // FIXME: due to a lack of registers we currently blow away the age | |
| 5011 // bits in this situation. Should attempt to preserve them. | |
| 5012 load_prototype_header(tmp_reg, obj_reg); | |
| 5013 orq(tmp_reg, r15_thread); | |
| 5014 if (os::is_MP()) { | |
| 5015 lock(); | |
| 5016 } | |
| 5017 cmpxchgq(tmp_reg, Address(obj_reg, 0)); | |
| 5018 // If the biasing toward our thread failed, then another thread | |
| 5019 // succeeded in biasing it toward itself and we need to revoke that | |
| 5020 // bias. The revocation will occur in the runtime in the slow case. | |
| 5021 if (counters != NULL) { | |
| 5022 cond_inc32(Assembler::zero, | |
| 5023 ExternalAddress((address) counters->rebiased_lock_entry_count_addr())); | |
| 5024 } | |
| 5025 if (slow_case != NULL) { | |
| 5026 jcc(Assembler::notZero, *slow_case); | |
| 0 | 5027 } |
| 5028 jmp(done); | |
| 5029 | |
| 304 | 5030 bind(try_revoke_bias); |
| 5031 // The prototype mark in the klass doesn't have the bias bit set any | |
| 5032 // more, indicating that objects of this data type are not supposed | |
| 5033 // to be biased any more. We are going to try to reset the mark of | |
| 5034 // this object to the prototype value and fall through to the | |
| 5035 // CAS-based locking scheme. Note that if our CAS fails, it means | |
| 5036 // that another thread raced us for the privilege of revoking the | |
| 5037 // bias of this particular object, so it's okay to continue in the | |
| 5038 // normal locking code. | |
| 5039 // | |
| 5040 // FIXME: due to a lack of registers we currently blow away the age | |
| 5041 // bits in this situation. Should attempt to preserve them. | |
| 5042 load_prototype_header(tmp_reg, obj_reg); | |
| 5043 if (os::is_MP()) { | |
| 5044 lock(); | |
| 5045 } | |
| 5046 cmpxchgq(tmp_reg, Address(obj_reg, 0)); | |
| 5047 // Fall through to the normal CAS-based lock, because no matter what | |
| 5048 // the result of the above CAS, some thread must have succeeded in | |
| 5049 // removing the bias bit from the object's header. | |
| 5050 if (counters != NULL) { | |
| 5051 cond_inc32(Assembler::zero, | |
| 5052 ExternalAddress((address) counters->revoked_lock_entry_count_addr())); | |
| 5053 } | |
| 5054 | |
| 5055 bind(cas_label); | |
| 5056 | |
| 5057 return null_check_offset; | |
| 5058 } | |
| 5059 | |
| 5060 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) { | |
| 5061 Label L, E; | |
| 5062 | |
| 5063 #ifdef _WIN64 | |
| 5064 // Windows always allocates space for it's register args | |
| 5065 assert(num_args <= 4, "only register arguments supported"); | |
| 5066 subq(rsp, frame::arg_reg_save_area_bytes); | |
| 5067 #endif | |
| 5068 | |
| 5069 // Align stack if necessary | |
| 5070 testl(rsp, 15); | |
| 5071 jcc(Assembler::zero, L); | |
| 5072 | |
| 5073 subq(rsp, 8); | |
| 5074 { | |
| 5075 call(RuntimeAddress(entry_point)); | |
| 5076 } | |
| 5077 addq(rsp, 8); | |
| 5078 jmp(E); | |
| 5079 | |
| 5080 bind(L); | |
| 5081 { | |
| 5082 call(RuntimeAddress(entry_point)); | |
| 5083 } | |
| 5084 | |
| 5085 bind(E); | |
| 5086 | |
| 5087 #ifdef _WIN64 | |
| 5088 // restore stack pointer | |
| 5089 addq(rsp, frame::arg_reg_save_area_bytes); | |
| 5090 #endif | |
| 5091 | |
| 5092 } | |
| 5093 | |
| 5094 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) { | |
| 5095 assert(!src2.is_lval(), "should use cmpptr"); | |
| 5096 | |
| 5097 if (reachable(src2)) { | |
| 5098 cmpq(src1, as_Address(src2)); | |
| 5099 } else { | |
| 5100 lea(rscratch1, src2); | |
| 5101 Assembler::cmpq(src1, Address(rscratch1, 0)); | |
| 5102 } | |
| 5103 } | |
| 5104 | |
| 5105 int MacroAssembler::corrected_idivq(Register reg) { | |
| 5106 // Full implementation of Java ldiv and lrem; checks for special | |
| 5107 // case as described in JVM spec., p.243 & p.271. The function | |
| 5108 // returns the (pc) offset of the idivl instruction - may be needed | |
| 5109 // for implicit exceptions. | |
| 5110 // | |
| 5111 // normal case special case | |
| 5112 // | |
| 5113 // input : rax: dividend min_long | |
| 5114 // reg: divisor (may not be eax/edx) -1 | |
| 5115 // | |
| 5116 // output: rax: quotient (= rax idiv reg) min_long | |
| 5117 // rdx: remainder (= rax irem reg) 0 | |
| 5118 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register"); | |
| 5119 static const int64_t min_long = 0x8000000000000000; | |
| 5120 Label normal_case, special_case; | |
| 5121 | |
| 5122 // check for special case | |
| 5123 cmp64(rax, ExternalAddress((address) &min_long)); | |
| 5124 jcc(Assembler::notEqual, normal_case); | |
| 5125 xorl(rdx, rdx); // prepare rdx for possible special case (where | |
| 5126 // remainder = 0) | |
| 5127 cmpq(reg, -1); | |
| 5128 jcc(Assembler::equal, special_case); | |
| 5129 | |
| 5130 // handle normal case | |
| 5131 bind(normal_case); | |
| 5132 cdqq(); | |
| 5133 int idivq_offset = offset(); | |
| 5134 idivq(reg); | |
| 5135 | |
| 5136 // normal and special case exit | |
| 5137 bind(special_case); | |
| 5138 | |
| 5139 return idivq_offset; | |
| 5140 } | |
| 5141 | |
| 5142 void MacroAssembler::decrementq(Register reg, int value) { | |
| 5143 if (value == min_jint) { subq(reg, value); return; } | |
| 5144 if (value < 0) { incrementq(reg, -value); return; } | |
| 5145 if (value == 0) { ; return; } | |
| 5146 if (value == 1 && UseIncDec) { decq(reg) ; return; } | |
| 5147 /* else */ { subq(reg, value) ; return; } | |
| 5148 } | |
| 5149 | |
| 5150 void MacroAssembler::decrementq(Address dst, int value) { | |
| 5151 if (value == min_jint) { subq(dst, value); return; } | |
| 5152 if (value < 0) { incrementq(dst, -value); return; } | |
| 5153 if (value == 0) { ; return; } | |
| 5154 if (value == 1 && UseIncDec) { decq(dst) ; return; } | |
| 5155 /* else */ { subq(dst, value) ; return; } | |
| 5156 } | |
| 5157 | |
| 5158 void MacroAssembler::fat_nop() { | |
| 5159 // A 5 byte nop that is safe for patching (see patch_verified_entry) | |
| 5160 // Recommened sequence from 'Software Optimization Guide for the AMD | |
| 5161 // Hammer Processor' | |
| 5162 emit_byte(0x66); | |
| 5163 emit_byte(0x66); | |
| 5164 emit_byte(0x90); | |
| 5165 emit_byte(0x66); | |
| 5166 emit_byte(0x90); | |
| 5167 } | |
| 5168 | |
| 5169 void MacroAssembler::incrementq(Register reg, int value) { | |
| 5170 if (value == min_jint) { addq(reg, value); return; } | |
| 5171 if (value < 0) { decrementq(reg, -value); return; } | |
| 5172 if (value == 0) { ; return; } | |
| 5173 if (value == 1 && UseIncDec) { incq(reg) ; return; } | |
| 5174 /* else */ { addq(reg, value) ; return; } | |
| 5175 } | |
| 5176 | |
| 5177 void MacroAssembler::incrementq(Address dst, int value) { | |
| 5178 if (value == min_jint) { addq(dst, value); return; } | |
| 5179 if (value < 0) { decrementq(dst, -value); return; } | |
| 5180 if (value == 0) { ; return; } | |
| 5181 if (value == 1 && UseIncDec) { incq(dst) ; return; } | |
| 5182 /* else */ { addq(dst, value) ; return; } | |
| 5183 } | |
| 5184 | |
| 5185 // 32bit can do a case table jump in one instruction but we no longer allow the base | |
| 5186 // to be installed in the Address class | |
| 5187 void MacroAssembler::jump(ArrayAddress entry) { | |
| 5188 lea(rscratch1, entry.base()); | |
| 5189 Address dispatch = entry.index(); | |
| 5190 assert(dispatch._base == noreg, "must be"); | |
| 5191 dispatch._base = rscratch1; | |
| 5192 jmp(dispatch); | |
| 5193 } | |
| 5194 | |
| 5195 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { | |
| 5196 ShouldNotReachHere(); // 64bit doesn't use two regs | |
| 5197 cmpq(x_lo, y_lo); | |
| 5198 } | |
| 5199 | |
| 5200 void MacroAssembler::lea(Register dst, AddressLiteral src) { | |
| 5201 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); | |
| 5202 } | |
| 5203 | |
| 5204 void MacroAssembler::lea(Address dst, AddressLiteral adr) { | |
| 5205 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec()); | |
| 5206 movptr(dst, rscratch1); | |
| 5207 } | |
| 5208 | |
| 5209 void MacroAssembler::leave() { | |
| 5210 // %%% is this really better? Why not on 32bit too? | |
| 5211 emit_byte(0xC9); // LEAVE | |
| 5212 } | |
| 5213 | |
| 5214 void MacroAssembler::lneg(Register hi, Register lo) { | |
| 5215 ShouldNotReachHere(); // 64bit doesn't use two regs | |
| 5216 negq(lo); | |
| 5217 } | |
| 5218 | |
| 5219 void MacroAssembler::movoop(Register dst, jobject obj) { | |
| 5220 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate()); | |
| 5221 } | |
| 5222 | |
| 5223 void MacroAssembler::movoop(Address dst, jobject obj) { | |
| 5224 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate()); | |
| 5225 movq(dst, rscratch1); | |
| 5226 } | |
| 5227 | |
| 5228 void MacroAssembler::movptr(Register dst, AddressLiteral src) { | |
| 5229 if (src.is_lval()) { | |
| 5230 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); | |
| 5231 } else { | |
| 5232 if (reachable(src)) { | |
| 5233 movq(dst, as_Address(src)); | |
| 5234 } else { | |
| 5235 lea(rscratch1, src); | |
| 5236 movq(dst, Address(rscratch1,0)); | |
| 0 | 5237 } |
| 304 | 5238 } |
| 5239 } | |
| 5240 | |
| 5241 void MacroAssembler::movptr(ArrayAddress dst, Register src) { | |
| 5242 movq(as_Address(dst), src); | |
| 5243 } | |
| 5244 | |
| 5245 void MacroAssembler::movptr(Register dst, ArrayAddress src) { | |
| 5246 movq(dst, as_Address(src)); | |
| 5247 } | |
| 5248 | |
| 5249 // src should NEVER be a real pointer. Use AddressLiteral for true pointers | |
| 5250 void MacroAssembler::movptr(Address dst, intptr_t src) { | |
| 5251 mov64(rscratch1, src); | |
| 5252 movq(dst, rscratch1); | |
| 5253 } | |
| 5254 | |
| 5255 // These are mostly for initializing NULL | |
| 5256 void MacroAssembler::movptr(Address dst, int32_t src) { | |
| 5257 movslq(dst, src); | |
| 5258 } | |
| 5259 | |
| 5260 void MacroAssembler::movptr(Register dst, int32_t src) { | |
| 5261 mov64(dst, (intptr_t)src); | |
| 5262 } | |
| 5263 | |
| 5264 void MacroAssembler::pushoop(jobject obj) { | |
| 5265 movoop(rscratch1, obj); | |
| 5266 push(rscratch1); | |
| 5267 } | |
| 5268 | |
| 5269 void MacroAssembler::pushptr(AddressLiteral src) { | |
| 5270 lea(rscratch1, src); | |
| 5271 if (src.is_lval()) { | |
| 5272 push(rscratch1); | |
| 5273 } else { | |
| 5274 pushq(Address(rscratch1, 0)); | |
| 5275 } | |
| 5276 } | |
| 5277 | |
| 5278 void MacroAssembler::reset_last_Java_frame(bool clear_fp, | |
| 5279 bool clear_pc) { | |
| 5280 // we must set sp to zero to clear frame | |
|
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|
5281 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); |
| 304 | 5282 // must clear fp, so that compiled frames are not confused; it is |
| 5283 // possible that we need it only for debugging | |
| 5284 if (clear_fp) { | |
|
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|
5285 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); |
| 304 | 5286 } |
| 5287 | |
| 5288 if (clear_pc) { | |
|
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|
5289 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); |
| 304 | 5290 } |
| 5291 } | |
| 5292 | |
| 5293 void MacroAssembler::set_last_Java_frame(Register last_java_sp, | |
| 5294 Register last_java_fp, | |
| 5295 address last_java_pc) { | |
| 5296 // determine last_java_sp register | |
| 5297 if (!last_java_sp->is_valid()) { | |
| 5298 last_java_sp = rsp; | |
| 5299 } | |
| 5300 | |
| 5301 // last_java_fp is optional | |
| 5302 if (last_java_fp->is_valid()) { | |
| 5303 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), | |
| 5304 last_java_fp); | |
| 5305 } | |
| 5306 | |
| 5307 // last_java_pc is optional | |
| 5308 if (last_java_pc != NULL) { | |
| 5309 Address java_pc(r15_thread, | |
| 5310 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()); | |
| 5311 lea(rscratch1, InternalAddress(last_java_pc)); | |
| 5312 movptr(java_pc, rscratch1); | |
| 5313 } | |
| 5314 | |
| 5315 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp); | |
| 5316 } | |
| 5317 | |
| 5318 static void pass_arg0(MacroAssembler* masm, Register arg) { | |
| 5319 if (c_rarg0 != arg ) { | |
| 5320 masm->mov(c_rarg0, arg); | |
| 5321 } | |
| 5322 } | |
| 5323 | |
| 5324 static void pass_arg1(MacroAssembler* masm, Register arg) { | |
| 5325 if (c_rarg1 != arg ) { | |
| 5326 masm->mov(c_rarg1, arg); | |
| 5327 } | |
| 5328 } | |
| 5329 | |
| 5330 static void pass_arg2(MacroAssembler* masm, Register arg) { | |
| 5331 if (c_rarg2 != arg ) { | |
| 5332 masm->mov(c_rarg2, arg); | |
| 5333 } | |
| 5334 } | |
| 5335 | |
| 5336 static void pass_arg3(MacroAssembler* masm, Register arg) { | |
| 5337 if (c_rarg3 != arg ) { | |
| 5338 masm->mov(c_rarg3, arg); | |
| 5339 } | |
| 5340 } | |
| 5341 | |
| 5342 void MacroAssembler::stop(const char* msg) { | |
| 5343 address rip = pc(); | |
| 5344 pusha(); // get regs on stack | |
| 5345 lea(c_rarg0, ExternalAddress((address) msg)); | |
| 5346 lea(c_rarg1, InternalAddress(rip)); | |
| 5347 movq(c_rarg2, rsp); // pass pointer to regs array | |
| 5348 andq(rsp, -16); // align stack as required by ABI | |
| 5349 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64))); | |
| 5350 hlt(); | |
| 5351 } | |
| 5352 | |
| 5353 void MacroAssembler::warn(const char* msg) { | |
| 5354 push(r12); | |
| 5355 movq(r12, rsp); | |
| 5356 andq(rsp, -16); // align stack as required by push_CPU_state and call | |
| 5357 | |
| 5358 push_CPU_state(); // keeps alignment at 16 bytes | |
| 5359 lea(c_rarg0, ExternalAddress((address) msg)); | |
| 5360 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0); | |
| 5361 pop_CPU_state(); | |
| 5362 | |
| 5363 movq(rsp, r12); | |
| 5364 pop(r12); | |
| 5365 } | |
| 5366 | |
| 5367 #ifndef PRODUCT | |
| 5368 extern "C" void findpc(intptr_t x); | |
| 5369 #endif | |
| 5370 | |
| 5371 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) { | |
| 5372 // In order to get locks to work, we need to fake a in_VM state | |
| 5373 if (ShowMessageBoxOnError ) { | |
| 5374 JavaThread* thread = JavaThread::current(); | |
| 5375 JavaThreadState saved_state = thread->thread_state(); | |
| 5376 thread->set_thread_state(_thread_in_vm); | |
| 5377 #ifndef PRODUCT | |
| 5378 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { | |
| 5379 ttyLocker ttyl; | |
| 5380 BytecodeCounter::print(); | |
| 0 | 5381 } |
| 304 | 5382 #endif |
| 5383 // To see where a verify_oop failed, get $ebx+40/X for this frame. | |
| 5384 // XXX correct this offset for amd64 | |
| 5385 // This is the value of eip which points to where verify_oop will return. | |
| 5386 if (os::message_box(msg, "Execution stopped, print registers?")) { | |
| 5387 ttyLocker ttyl; | |
| 5388 tty->print_cr("rip = 0x%016lx", pc); | |
| 5389 #ifndef PRODUCT | |
| 5390 tty->cr(); | |
| 5391 findpc(pc); | |
| 5392 tty->cr(); | |
| 5393 #endif | |
| 5394 tty->print_cr("rax = 0x%016lx", regs[15]); | |
| 5395 tty->print_cr("rbx = 0x%016lx", regs[12]); | |
| 5396 tty->print_cr("rcx = 0x%016lx", regs[14]); | |
| 5397 tty->print_cr("rdx = 0x%016lx", regs[13]); | |
| 5398 tty->print_cr("rdi = 0x%016lx", regs[8]); | |
| 5399 tty->print_cr("rsi = 0x%016lx", regs[9]); | |
| 5400 tty->print_cr("rbp = 0x%016lx", regs[10]); | |
| 5401 tty->print_cr("rsp = 0x%016lx", regs[11]); | |
| 5402 tty->print_cr("r8 = 0x%016lx", regs[7]); | |
| 5403 tty->print_cr("r9 = 0x%016lx", regs[6]); | |
| 5404 tty->print_cr("r10 = 0x%016lx", regs[5]); | |
| 5405 tty->print_cr("r11 = 0x%016lx", regs[4]); | |
| 5406 tty->print_cr("r12 = 0x%016lx", regs[3]); | |
| 5407 tty->print_cr("r13 = 0x%016lx", regs[2]); | |
| 5408 tty->print_cr("r14 = 0x%016lx", regs[1]); | |
| 5409 tty->print_cr("r15 = 0x%016lx", regs[0]); | |
| 5410 BREAKPOINT; | |
| 0 | 5411 } |
| 304 | 5412 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); |
| 5413 } else { | |
| 5414 ttyLocker ttyl; | |
| 5415 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", | |
| 5416 msg); | |
| 5417 } | |
| 5418 } | |
| 5419 | |
| 5420 #endif // _LP64 | |
| 5421 | |
| 5422 // Now versions that are common to 32/64 bit | |
| 5423 | |
| 5424 void MacroAssembler::addptr(Register dst, int32_t imm32) { | |
| 5425 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32)); | |
| 5426 } | |
| 5427 | |
| 5428 void MacroAssembler::addptr(Register dst, Register src) { | |
| 5429 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); | |
| 5430 } | |
| 5431 | |
| 5432 void MacroAssembler::addptr(Address dst, Register src) { | |
| 5433 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); | |
| 5434 } | |
| 5435 | |
| 5436 void MacroAssembler::align(int modulus) { | |
| 5437 if (offset() % modulus != 0) { | |
| 5438 nop(modulus - (offset() % modulus)); | |
| 5439 } | |
| 5440 } | |
| 5441 | |
| 5442 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) { | |
| 5443 andpd(dst, as_Address(src)); | |
| 5444 } | |
| 5445 | |
| 5446 void MacroAssembler::andptr(Register dst, int32_t imm32) { | |
| 5447 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32)); | |
| 5448 } | |
| 5449 | |
| 5450 void MacroAssembler::atomic_incl(AddressLiteral counter_addr) { | |
| 5451 pushf(); | |
| 5452 if (os::is_MP()) | |
| 5453 lock(); | |
| 5454 incrementl(counter_addr); | |
| 5455 popf(); | |
| 5456 } | |
| 5457 | |
| 5458 // Writes to stack successive pages until offset reached to check for | |
| 5459 // stack overflow + shadow pages. This clobbers tmp. | |
| 5460 void MacroAssembler::bang_stack_size(Register size, Register tmp) { | |
| 5461 movptr(tmp, rsp); | |
| 5462 // Bang stack for total size given plus shadow page size. | |
| 5463 // Bang one page at a time because large size can bang beyond yellow and | |
| 5464 // red zones. | |
| 5465 Label loop; | |
| 5466 bind(loop); | |
| 5467 movl(Address(tmp, (-os::vm_page_size())), size ); | |
| 5468 subptr(tmp, os::vm_page_size()); | |
| 5469 subl(size, os::vm_page_size()); | |
| 5470 jcc(Assembler::greater, loop); | |
| 5471 | |
| 5472 // Bang down shadow pages too. | |
| 5473 // The -1 because we already subtracted 1 page. | |
| 5474 for (int i = 0; i< StackShadowPages-1; i++) { | |
| 5475 // this could be any sized move but this is can be a debugging crumb | |
| 5476 // so the bigger the better. | |
| 5477 movptr(Address(tmp, (-i*os::vm_page_size())), size ); | |
| 5478 } | |
| 5479 } | |
| 5480 | |
| 5481 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) { | |
| 5482 assert(UseBiasedLocking, "why call this otherwise?"); | |
| 5483 | |
| 5484 // Check for biased locking unlock case, which is a no-op | |
| 5485 // Note: we do not have to check the thread ID for two reasons. | |
| 5486 // First, the interpreter checks for IllegalMonitorStateException at | |
| 5487 // a higher level. Second, if the bias was revoked while we held the | |
| 5488 // lock, the object could not be rebiased toward another thread, so | |
| 5489 // the bias bit would be clear. | |
| 5490 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes())); | |
| 5491 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place); | |
| 5492 cmpptr(temp_reg, markOopDesc::biased_lock_pattern); | |
| 5493 jcc(Assembler::equal, done); | |
| 5494 } | |
| 5495 | |
| 5496 void MacroAssembler::c2bool(Register x) { | |
| 5497 // implements x == 0 ? 0 : 1 | |
| 5498 // note: must only look at least-significant byte of x | |
| 5499 // since C-style booleans are stored in one byte | |
| 5500 // only! (was bug) | |
| 5501 andl(x, 0xFF); | |
| 5502 setb(Assembler::notZero, x); | |
| 5503 } | |
| 5504 | |
| 5505 // Wouldn't need if AddressLiteral version had new name | |
| 5506 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) { | |
| 5507 Assembler::call(L, rtype); | |
| 5508 } | |
| 5509 | |
| 5510 void MacroAssembler::call(Register entry) { | |
| 5511 Assembler::call(entry); | |
| 5512 } | |
| 5513 | |
| 5514 void MacroAssembler::call(AddressLiteral entry) { | |
| 5515 if (reachable(entry)) { | |
| 5516 Assembler::call_literal(entry.target(), entry.rspec()); | |
| 5517 } else { | |
| 5518 lea(rscratch1, entry); | |
| 5519 Assembler::call(rscratch1); | |
| 5520 } | |
| 5521 } | |
| 5522 | |
| 5523 // Implementation of call_VM versions | |
| 5524 | |
| 5525 void MacroAssembler::call_VM(Register oop_result, | |
| 5526 address entry_point, | |
| 5527 bool check_exceptions) { | |
| 5528 Label C, E; | |
| 5529 call(C, relocInfo::none); | |
| 5530 jmp(E); | |
| 5531 | |
| 5532 bind(C); | |
| 5533 call_VM_helper(oop_result, entry_point, 0, check_exceptions); | |
| 5534 ret(0); | |
| 5535 | |
| 5536 bind(E); | |
| 5537 } | |
| 5538 | |
| 5539 void MacroAssembler::call_VM(Register oop_result, | |
| 5540 address entry_point, | |
| 5541 Register arg_1, | |
| 5542 bool check_exceptions) { | |
| 5543 Label C, E; | |
| 5544 call(C, relocInfo::none); | |
| 5545 jmp(E); | |
| 5546 | |
| 5547 bind(C); | |
| 5548 pass_arg1(this, arg_1); | |
| 5549 call_VM_helper(oop_result, entry_point, 1, check_exceptions); | |
| 5550 ret(0); | |
| 5551 | |
| 5552 bind(E); | |
| 5553 } | |
| 5554 | |
| 5555 void MacroAssembler::call_VM(Register oop_result, | |
| 5556 address entry_point, | |
| 5557 Register arg_1, | |
| 5558 Register arg_2, | |
| 5559 bool check_exceptions) { | |
| 5560 Label C, E; | |
| 5561 call(C, relocInfo::none); | |
| 5562 jmp(E); | |
| 5563 | |
| 5564 bind(C); | |
| 5565 | |
| 5566 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
| 5567 | |
| 5568 pass_arg2(this, arg_2); | |
| 5569 pass_arg1(this, arg_1); | |
| 5570 call_VM_helper(oop_result, entry_point, 2, check_exceptions); | |
| 5571 ret(0); | |
| 5572 | |
| 5573 bind(E); | |
| 5574 } | |
| 5575 | |
| 5576 void MacroAssembler::call_VM(Register oop_result, | |
| 5577 address entry_point, | |
| 5578 Register arg_1, | |
| 5579 Register arg_2, | |
| 5580 Register arg_3, | |
| 5581 bool check_exceptions) { | |
| 5582 Label C, E; | |
| 5583 call(C, relocInfo::none); | |
| 5584 jmp(E); | |
| 5585 | |
| 5586 bind(C); | |
| 5587 | |
| 5588 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); | |
| 5589 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); | |
| 5590 pass_arg3(this, arg_3); | |
| 5591 | |
| 5592 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
| 5593 pass_arg2(this, arg_2); | |
| 5594 | |
| 5595 pass_arg1(this, arg_1); | |
| 5596 call_VM_helper(oop_result, entry_point, 3, check_exceptions); | |
| 5597 ret(0); | |
| 5598 | |
| 5599 bind(E); | |
| 5600 } | |
| 5601 | |
| 5602 void MacroAssembler::call_VM(Register oop_result, | |
| 5603 Register last_java_sp, | |
| 5604 address entry_point, | |
| 5605 int number_of_arguments, | |
| 5606 bool check_exceptions) { | |
| 5607 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); | |
| 5608 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); | |
| 5609 } | |
| 5610 | |
| 5611 void MacroAssembler::call_VM(Register oop_result, | |
| 5612 Register last_java_sp, | |
| 5613 address entry_point, | |
| 5614 Register arg_1, | |
| 5615 bool check_exceptions) { | |
| 5616 pass_arg1(this, arg_1); | |
| 5617 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); | |
| 5618 } | |
| 5619 | |
| 5620 void MacroAssembler::call_VM(Register oop_result, | |
| 5621 Register last_java_sp, | |
| 5622 address entry_point, | |
| 5623 Register arg_1, | |
| 5624 Register arg_2, | |
| 5625 bool check_exceptions) { | |
| 5626 | |
| 5627 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
| 5628 pass_arg2(this, arg_2); | |
| 5629 pass_arg1(this, arg_1); | |
| 5630 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); | |
| 5631 } | |
| 5632 | |
| 5633 void MacroAssembler::call_VM(Register oop_result, | |
| 5634 Register last_java_sp, | |
| 5635 address entry_point, | |
| 5636 Register arg_1, | |
| 5637 Register arg_2, | |
| 5638 Register arg_3, | |
| 5639 bool check_exceptions) { | |
| 5640 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); | |
| 5641 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); | |
| 5642 pass_arg3(this, arg_3); | |
| 5643 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
| 5644 pass_arg2(this, arg_2); | |
| 5645 pass_arg1(this, arg_1); | |
| 5646 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); | |
| 5647 } | |
| 5648 | |
| 5649 void MacroAssembler::call_VM_base(Register oop_result, | |
| 5650 Register java_thread, | |
| 5651 Register last_java_sp, | |
| 5652 address entry_point, | |
| 5653 int number_of_arguments, | |
| 5654 bool check_exceptions) { | |
| 5655 // determine java_thread register | |
| 5656 if (!java_thread->is_valid()) { | |
| 5657 #ifdef _LP64 | |
| 5658 java_thread = r15_thread; | |
| 5659 #else | |
| 5660 java_thread = rdi; | |
| 5661 get_thread(java_thread); | |
| 5662 #endif // LP64 | |
| 5663 } | |
| 5664 // determine last_java_sp register | |
| 5665 if (!last_java_sp->is_valid()) { | |
| 5666 last_java_sp = rsp; | |
| 5667 } | |
| 5668 // debugging support | |
| 5669 assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); | |
| 5670 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register")); | |
| 5671 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result"); | |
| 5672 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp"); | |
| 5673 | |
| 5674 // push java thread (becomes first argument of C function) | |
| 5675 | |
| 5676 NOT_LP64(push(java_thread); number_of_arguments++); | |
| 5677 LP64_ONLY(mov(c_rarg0, r15_thread)); | |
| 5678 | |
| 5679 // set last Java frame before call | |
| 5680 assert(last_java_sp != rbp, "can't use ebp/rbp"); | |
| 5681 | |
| 5682 // Only interpreter should have to set fp | |
| 5683 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL); | |
| 5684 | |
| 5685 // do the call, remove parameters | |
| 5686 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments); | |
| 5687 | |
| 5688 // restore the thread (cannot use the pushed argument since arguments | |
| 5689 // may be overwritten by C code generated by an optimizing compiler); | |
| 5690 // however can use the register value directly if it is callee saved. | |
| 5691 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) { | |
| 5692 // rdi & rsi (also r15) are callee saved -> nothing to do | |
| 5693 #ifdef ASSERT | |
| 5694 guarantee(java_thread != rax, "change this code"); | |
| 5695 push(rax); | |
| 5696 { Label L; | |
| 5697 get_thread(rax); | |
| 5698 cmpptr(java_thread, rax); | |
| 5699 jcc(Assembler::equal, L); | |
| 5700 stop("MacroAssembler::call_VM_base: rdi not callee saved?"); | |
| 5701 bind(L); | |
| 0 | 5702 } |
| 304 | 5703 pop(rax); |
| 5704 #endif | |
| 5705 } else { | |
| 5706 get_thread(java_thread); | |
| 5707 } | |
| 5708 // reset last Java frame | |
| 5709 // Only interpreter should have to clear fp | |
| 5710 reset_last_Java_frame(java_thread, true, false); | |
| 5711 | |
| 5712 #ifndef CC_INTERP | |
| 5713 // C++ interp handles this in the interpreter | |
| 5714 check_and_handle_popframe(java_thread); | |
| 5715 check_and_handle_earlyret(java_thread); | |
| 5716 #endif /* CC_INTERP */ | |
| 5717 | |
| 5718 if (check_exceptions) { | |
| 5719 // check for pending exceptions (java_thread is set upon return) | |
| 5720 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD); | |
| 5721 #ifndef _LP64 | |
| 5722 jump_cc(Assembler::notEqual, | |
| 5723 RuntimeAddress(StubRoutines::forward_exception_entry())); | |
| 5724 #else | |
| 5725 // This used to conditionally jump to forward_exception however it is | |
| 5726 // possible if we relocate that the branch will not reach. So we must jump | |
| 5727 // around so we can always reach | |
| 5728 | |
| 5729 Label ok; | |
| 5730 jcc(Assembler::equal, ok); | |
| 5731 jump(RuntimeAddress(StubRoutines::forward_exception_entry())); | |
| 5732 bind(ok); | |
| 5733 #endif // LP64 | |
| 5734 } | |
| 5735 | |
| 5736 // get oop result if there is one and reset the value in the thread | |
| 5737 if (oop_result->is_valid()) { | |
| 5738 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset())); | |
|
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changeset
|
5739 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD); |
| 304 | 5740 verify_oop(oop_result, "broken oop in call_VM_base"); |
| 5741 } | |
| 5742 } | |
| 5743 | |
| 5744 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) { | |
| 5745 | |
| 5746 // Calculate the value for last_Java_sp | |
| 5747 // somewhat subtle. call_VM does an intermediate call | |
| 5748 // which places a return address on the stack just under the | |
| 5749 // stack pointer as the user finsihed with it. This allows | |
| 5750 // use to retrieve last_Java_pc from last_Java_sp[-1]. | |
| 5751 // On 32bit we then have to push additional args on the stack to accomplish | |
| 5752 // the actual requested call. On 64bit call_VM only can use register args | |
| 5753 // so the only extra space is the return address that call_VM created. | |
| 5754 // This hopefully explains the calculations here. | |
| 5755 | |
| 5756 #ifdef _LP64 | |
| 5757 // We've pushed one address, correct last_Java_sp | |
| 5758 lea(rax, Address(rsp, wordSize)); | |
| 5759 #else | |
| 5760 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize)); | |
| 5761 #endif // LP64 | |
| 5762 | |
| 5763 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions); | |
| 5764 | |
| 5765 } | |
| 5766 | |
| 5767 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) { | |
| 5768 call_VM_leaf_base(entry_point, number_of_arguments); | |
| 5769 } | |
| 5770 | |
| 5771 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) { | |
| 5772 pass_arg0(this, arg_0); | |
| 5773 call_VM_leaf(entry_point, 1); | |
| 5774 } | |
| 5775 | |
| 5776 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { | |
| 5777 | |
| 5778 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); | |
| 5779 pass_arg1(this, arg_1); | |
| 5780 pass_arg0(this, arg_0); | |
| 5781 call_VM_leaf(entry_point, 2); | |
| 5782 } | |
| 5783 | |
| 5784 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { | |
| 5785 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); | |
| 5786 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
| 5787 pass_arg2(this, arg_2); | |
| 5788 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); | |
| 5789 pass_arg1(this, arg_1); | |
| 5790 pass_arg0(this, arg_0); | |
| 5791 call_VM_leaf(entry_point, 3); | |
| 5792 } | |
| 5793 | |
| 5794 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { | |
| 5795 } | |
| 5796 | |
| 5797 void MacroAssembler::check_and_handle_popframe(Register java_thread) { | |
| 5798 } | |
| 5799 | |
| 5800 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) { | |
| 5801 if (reachable(src1)) { | |
| 5802 cmpl(as_Address(src1), imm); | |
| 5803 } else { | |
| 5804 lea(rscratch1, src1); | |
| 5805 cmpl(Address(rscratch1, 0), imm); | |
| 5806 } | |
| 5807 } | |
| 5808 | |
| 5809 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) { | |
| 5810 assert(!src2.is_lval(), "use cmpptr"); | |
| 5811 if (reachable(src2)) { | |
| 5812 cmpl(src1, as_Address(src2)); | |
| 5813 } else { | |
| 5814 lea(rscratch1, src2); | |
| 5815 cmpl(src1, Address(rscratch1, 0)); | |
| 5816 } | |
| 5817 } | |
| 5818 | |
| 5819 void MacroAssembler::cmp32(Register src1, int32_t imm) { | |
| 5820 Assembler::cmpl(src1, imm); | |
| 5821 } | |
| 5822 | |
| 5823 void MacroAssembler::cmp32(Register src1, Address src2) { | |
| 5824 Assembler::cmpl(src1, src2); | |
| 5825 } | |
| 5826 | |
| 5827 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { | |
| 5828 ucomisd(opr1, opr2); | |
| 5829 | |
| 5830 Label L; | |
| 5831 if (unordered_is_less) { | |
| 5832 movl(dst, -1); | |
| 5833 jcc(Assembler::parity, L); | |
| 5834 jcc(Assembler::below , L); | |
| 5835 movl(dst, 0); | |
| 5836 jcc(Assembler::equal , L); | |
| 5837 increment(dst); | |
| 5838 } else { // unordered is greater | |
| 5839 movl(dst, 1); | |
| 5840 jcc(Assembler::parity, L); | |
| 5841 jcc(Assembler::above , L); | |
| 5842 movl(dst, 0); | |
| 5843 jcc(Assembler::equal , L); | |
| 5844 decrementl(dst); | |
| 5845 } | |
| 5846 bind(L); | |
| 5847 } | |
| 5848 | |
| 5849 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { | |
| 5850 ucomiss(opr1, opr2); | |
| 5851 | |
| 5852 Label L; | |
| 5853 if (unordered_is_less) { | |
| 5854 movl(dst, -1); | |
| 5855 jcc(Assembler::parity, L); | |
| 5856 jcc(Assembler::below , L); | |
| 5857 movl(dst, 0); | |
| 5858 jcc(Assembler::equal , L); | |
| 5859 increment(dst); | |
| 5860 } else { // unordered is greater | |
| 5861 movl(dst, 1); | |
| 5862 jcc(Assembler::parity, L); | |
| 5863 jcc(Assembler::above , L); | |
| 5864 movl(dst, 0); | |
| 5865 jcc(Assembler::equal , L); | |
| 5866 decrementl(dst); | |
| 5867 } | |
| 5868 bind(L); | |
| 5869 } | |
| 5870 | |
| 5871 | |
| 5872 void MacroAssembler::cmp8(AddressLiteral src1, int imm) { | |
| 5873 if (reachable(src1)) { | |
| 5874 cmpb(as_Address(src1), imm); | |
| 5875 } else { | |
| 5876 lea(rscratch1, src1); | |
| 5877 cmpb(Address(rscratch1, 0), imm); | |
| 5878 } | |
| 5879 } | |
| 5880 | |
| 5881 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) { | |
| 5882 #ifdef _LP64 | |
| 5883 if (src2.is_lval()) { | |
| 5884 movptr(rscratch1, src2); | |
| 5885 Assembler::cmpq(src1, rscratch1); | |
| 5886 } else if (reachable(src2)) { | |
| 5887 cmpq(src1, as_Address(src2)); | |
| 5888 } else { | |
| 5889 lea(rscratch1, src2); | |
| 5890 Assembler::cmpq(src1, Address(rscratch1, 0)); | |
| 5891 } | |
| 5892 #else | |
| 5893 if (src2.is_lval()) { | |
| 5894 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); | |
| 5895 } else { | |
| 5896 cmpl(src1, as_Address(src2)); | |
| 5897 } | |
| 5898 #endif // _LP64 | |
| 5899 } | |
| 5900 | |
| 5901 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) { | |
| 5902 assert(src2.is_lval(), "not a mem-mem compare"); | |
| 5903 #ifdef _LP64 | |
| 5904 // moves src2's literal address | |
| 5905 movptr(rscratch1, src2); | |
| 5906 Assembler::cmpq(src1, rscratch1); | |
| 5907 #else | |
| 5908 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); | |
| 5909 #endif // _LP64 | |
| 5910 } | |
| 5911 | |
| 5912 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) { | |
| 5913 if (reachable(adr)) { | |
| 5914 if (os::is_MP()) | |
| 5915 lock(); | |
| 5916 cmpxchgptr(reg, as_Address(adr)); | |
| 5917 } else { | |
| 5918 lea(rscratch1, adr); | |
| 5919 if (os::is_MP()) | |
| 5920 lock(); | |
| 5921 cmpxchgptr(reg, Address(rscratch1, 0)); | |
| 5922 } | |
| 5923 } | |
| 5924 | |
| 5925 void MacroAssembler::cmpxchgptr(Register reg, Address adr) { | |
| 5926 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr)); | |
| 5927 } | |
| 5928 | |
| 5929 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) { | |
| 5930 comisd(dst, as_Address(src)); | |
| 5931 } | |
| 5932 | |
| 5933 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) { | |
| 5934 comiss(dst, as_Address(src)); | |
| 5935 } | |
| 5936 | |
| 5937 | |
| 5938 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) { | |
| 5939 Condition negated_cond = negate_condition(cond); | |
| 5940 Label L; | |
| 5941 jcc(negated_cond, L); | |
| 5942 atomic_incl(counter_addr); | |
| 5943 bind(L); | |
| 5944 } | |
| 5945 | |
| 5946 int MacroAssembler::corrected_idivl(Register reg) { | |
| 5947 // Full implementation of Java idiv and irem; checks for | |
| 5948 // special case as described in JVM spec., p.243 & p.271. | |
| 5949 // The function returns the (pc) offset of the idivl | |
| 5950 // instruction - may be needed for implicit exceptions. | |
| 5951 // | |
| 5952 // normal case special case | |
| 5953 // | |
| 5954 // input : rax,: dividend min_int | |
| 5955 // reg: divisor (may not be rax,/rdx) -1 | |
| 5956 // | |
| 5957 // output: rax,: quotient (= rax, idiv reg) min_int | |
| 5958 // rdx: remainder (= rax, irem reg) 0 | |
| 5959 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register"); | |
| 5960 const int min_int = 0x80000000; | |
| 5961 Label normal_case, special_case; | |
| 5962 | |
| 5963 // check for special case | |
| 5964 cmpl(rax, min_int); | |
| 5965 jcc(Assembler::notEqual, normal_case); | |
| 5966 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0) | |
| 5967 cmpl(reg, -1); | |
| 5968 jcc(Assembler::equal, special_case); | |
| 5969 | |
| 5970 // handle normal case | |
| 5971 bind(normal_case); | |
| 5972 cdql(); | |
| 5973 int idivl_offset = offset(); | |
| 5974 idivl(reg); | |
| 5975 | |
| 5976 // normal and special case exit | |
| 5977 bind(special_case); | |
| 5978 | |
| 5979 return idivl_offset; | |
| 5980 } | |
| 5981 | |
| 5982 | |
| 5983 | |
| 5984 void MacroAssembler::decrementl(Register reg, int value) { | |
| 5985 if (value == min_jint) {subl(reg, value) ; return; } | |
| 5986 if (value < 0) { incrementl(reg, -value); return; } | |
| 5987 if (value == 0) { ; return; } | |
| 5988 if (value == 1 && UseIncDec) { decl(reg) ; return; } | |
| 5989 /* else */ { subl(reg, value) ; return; } | |
| 5990 } | |
| 5991 | |
| 5992 void MacroAssembler::decrementl(Address dst, int value) { | |
| 5993 if (value == min_jint) {subl(dst, value) ; return; } | |
| 5994 if (value < 0) { incrementl(dst, -value); return; } | |
| 5995 if (value == 0) { ; return; } | |
| 5996 if (value == 1 && UseIncDec) { decl(dst) ; return; } | |
| 5997 /* else */ { subl(dst, value) ; return; } | |
| 5998 } | |
| 5999 | |
| 6000 void MacroAssembler::division_with_shift (Register reg, int shift_value) { | |
| 6001 assert (shift_value > 0, "illegal shift value"); | |
| 6002 Label _is_positive; | |
| 6003 testl (reg, reg); | |
| 6004 jcc (Assembler::positive, _is_positive); | |
| 6005 int offset = (1 << shift_value) - 1 ; | |
| 6006 | |
| 6007 if (offset == 1) { | |
| 6008 incrementl(reg); | |
| 6009 } else { | |
| 6010 addl(reg, offset); | |
| 6011 } | |
| 6012 | |
| 6013 bind (_is_positive); | |
| 6014 sarl(reg, shift_value); | |
| 6015 } | |
| 6016 | |
| 6017 // !defined(COMPILER2) is because of stupid core builds | |
| 6018 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) | |
| 6019 void MacroAssembler::empty_FPU_stack() { | |
| 6020 if (VM_Version::supports_mmx()) { | |
| 6021 emms(); | |
| 6022 } else { | |
| 6023 for (int i = 8; i-- > 0; ) ffree(i); | |
| 6024 } | |
| 6025 } | |
| 6026 #endif // !LP64 || C1 || !C2 | |
| 6027 | |
| 6028 | |
| 6029 // Defines obj, preserves var_size_in_bytes | |
| 6030 void MacroAssembler::eden_allocate(Register obj, | |
| 6031 Register var_size_in_bytes, | |
| 6032 int con_size_in_bytes, | |
| 6033 Register t1, | |
| 6034 Label& slow_case) { | |
| 6035 assert(obj == rax, "obj must be in rax, for cmpxchg"); | |
| 6036 assert_different_registers(obj, var_size_in_bytes, t1); | |
| 362 | 6037 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { |
| 6038 jmp(slow_case); | |
| 304 | 6039 } else { |
| 362 | 6040 Register end = t1; |
| 6041 Label retry; | |
| 6042 bind(retry); | |
| 6043 ExternalAddress heap_top((address) Universe::heap()->top_addr()); | |
| 6044 movptr(obj, heap_top); | |
| 6045 if (var_size_in_bytes == noreg) { | |
| 6046 lea(end, Address(obj, con_size_in_bytes)); | |
| 6047 } else { | |
| 6048 lea(end, Address(obj, var_size_in_bytes, Address::times_1)); | |
| 6049 } | |
| 6050 // if end < obj then we wrapped around => object too long => slow case | |
| 6051 cmpptr(end, obj); | |
| 6052 jcc(Assembler::below, slow_case); | |
| 6053 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr())); | |
| 6054 jcc(Assembler::above, slow_case); | |
| 6055 // Compare obj with the top addr, and if still equal, store the new top addr in | |
| 6056 // end at the address of the top addr pointer. Sets ZF if was equal, and clears | |
| 6057 // it otherwise. Use lock prefix for atomicity on MPs. | |
| 6058 locked_cmpxchgptr(end, heap_top); | |
| 6059 jcc(Assembler::notEqual, retry); | |
| 6060 } | |
| 304 | 6061 } |
| 6062 | |
| 6063 void MacroAssembler::enter() { | |
| 6064 push(rbp); | |
| 6065 mov(rbp, rsp); | |
| 6066 } | |
| 0 | 6067 |
| 6068 void MacroAssembler::fcmp(Register tmp) { | |
| 6069 fcmp(tmp, 1, true, true); | |
| 6070 } | |
| 6071 | |
| 6072 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) { | |
| 6073 assert(!pop_right || pop_left, "usage error"); | |
| 6074 if (VM_Version::supports_cmov()) { | |
| 6075 assert(tmp == noreg, "unneeded temp"); | |
| 6076 if (pop_left) { | |
| 6077 fucomip(index); | |
| 6078 } else { | |
| 6079 fucomi(index); | |
| 6080 } | |
| 6081 if (pop_right) { | |
| 6082 fpop(); | |
| 6083 } | |
| 6084 } else { | |
| 6085 assert(tmp != noreg, "need temp"); | |
| 6086 if (pop_left) { | |
| 6087 if (pop_right) { | |
| 6088 fcompp(); | |
| 6089 } else { | |
| 6090 fcomp(index); | |
| 6091 } | |
| 6092 } else { | |
| 6093 fcom(index); | |
| 6094 } | |
| 6095 // convert FPU condition into eflags condition via rax, | |
| 6096 save_rax(tmp); | |
| 6097 fwait(); fnstsw_ax(); | |
| 6098 sahf(); | |
| 6099 restore_rax(tmp); | |
| 6100 } | |
| 6101 // condition codes set as follows: | |
| 6102 // | |
| 6103 // CF (corresponds to C0) if x < y | |
| 6104 // PF (corresponds to C2) if unordered | |
| 6105 // ZF (corresponds to C3) if x = y | |
| 6106 } | |
| 6107 | |
| 6108 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) { | |
| 6109 fcmp2int(dst, unordered_is_less, 1, true, true); | |
| 6110 } | |
| 6111 | |
| 6112 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) { | |
| 6113 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right); | |
| 6114 Label L; | |
| 6115 if (unordered_is_less) { | |
| 6116 movl(dst, -1); | |
| 6117 jcc(Assembler::parity, L); | |
| 6118 jcc(Assembler::below , L); | |
| 6119 movl(dst, 0); | |
| 6120 jcc(Assembler::equal , L); | |
| 6121 increment(dst); | |
| 6122 } else { // unordered is greater | |
| 6123 movl(dst, 1); | |
| 6124 jcc(Assembler::parity, L); | |
| 6125 jcc(Assembler::above , L); | |
| 6126 movl(dst, 0); | |
| 6127 jcc(Assembler::equal , L); | |
| 304 | 6128 decrementl(dst); |
| 0 | 6129 } |
| 6130 bind(L); | |
| 6131 } | |
| 6132 | |
| 304 | 6133 void MacroAssembler::fld_d(AddressLiteral src) { |
| 6134 fld_d(as_Address(src)); | |
| 6135 } | |
| 6136 | |
| 6137 void MacroAssembler::fld_s(AddressLiteral src) { | |
| 6138 fld_s(as_Address(src)); | |
| 6139 } | |
| 6140 | |
| 6141 void MacroAssembler::fld_x(AddressLiteral src) { | |
| 6142 Assembler::fld_x(as_Address(src)); | |
| 6143 } | |
| 6144 | |
| 6145 void MacroAssembler::fldcw(AddressLiteral src) { | |
| 6146 Assembler::fldcw(as_Address(src)); | |
| 6147 } | |
| 0 | 6148 |
| 6149 void MacroAssembler::fpop() { | |
| 6150 ffree(); | |
| 6151 fincstp(); | |
| 6152 } | |
| 6153 | |
| 304 | 6154 void MacroAssembler::fremr(Register tmp) { |
| 6155 save_rax(tmp); | |
| 6156 { Label L; | |
| 6157 bind(L); | |
| 6158 fprem(); | |
| 6159 fwait(); fnstsw_ax(); | |
| 6160 #ifdef _LP64 | |
| 6161 testl(rax, 0x400); | |
| 6162 jcc(Assembler::notEqual, L); | |
| 6163 #else | |
| 6164 sahf(); | |
| 6165 jcc(Assembler::parity, L); | |
| 6166 #endif // _LP64 | |
| 6167 } | |
| 6168 restore_rax(tmp); | |
| 6169 // Result is in ST0. | |
| 6170 // Note: fxch & fpop to get rid of ST1 | |
| 6171 // (otherwise FPU stack could overflow eventually) | |
| 6172 fxch(1); | |
| 6173 fpop(); | |
| 6174 } | |
| 6175 | |
| 6176 | |
| 6177 void MacroAssembler::incrementl(AddressLiteral dst) { | |
| 6178 if (reachable(dst)) { | |
| 6179 incrementl(as_Address(dst)); | |
| 0 | 6180 } else { |
| 304 | 6181 lea(rscratch1, dst); |
| 6182 incrementl(Address(rscratch1, 0)); | |
| 6183 } | |
| 6184 } | |
| 6185 | |
| 6186 void MacroAssembler::incrementl(ArrayAddress dst) { | |
| 6187 incrementl(as_Address(dst)); | |
| 6188 } | |
| 6189 | |
| 6190 void MacroAssembler::incrementl(Register reg, int value) { | |
| 6191 if (value == min_jint) {addl(reg, value) ; return; } | |
| 6192 if (value < 0) { decrementl(reg, -value); return; } | |
| 6193 if (value == 0) { ; return; } | |
| 6194 if (value == 1 && UseIncDec) { incl(reg) ; return; } | |
| 6195 /* else */ { addl(reg, value) ; return; } | |
| 6196 } | |
| 6197 | |
| 6198 void MacroAssembler::incrementl(Address dst, int value) { | |
| 6199 if (value == min_jint) {addl(dst, value) ; return; } | |
| 6200 if (value < 0) { decrementl(dst, -value); return; } | |
| 6201 if (value == 0) { ; return; } | |
| 6202 if (value == 1 && UseIncDec) { incl(dst) ; return; } | |
| 6203 /* else */ { addl(dst, value) ; return; } | |
| 6204 } | |
| 6205 | |
| 6206 void MacroAssembler::jump(AddressLiteral dst) { | |
| 6207 if (reachable(dst)) { | |
| 6208 jmp_literal(dst.target(), dst.rspec()); | |
| 6209 } else { | |
| 6210 lea(rscratch1, dst); | |
| 6211 jmp(rscratch1); | |
| 6212 } | |
| 6213 } | |
| 6214 | |
| 6215 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) { | |
| 6216 if (reachable(dst)) { | |
| 6217 InstructionMark im(this); | |
| 6218 relocate(dst.reloc()); | |
| 6219 const int short_size = 2; | |
| 6220 const int long_size = 6; | |
| 6221 int offs = (intptr_t)dst.target() - ((intptr_t)_code_pos); | |
| 6222 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) { | |
| 6223 // 0111 tttn #8-bit disp | |
| 6224 emit_byte(0x70 | cc); | |
| 6225 emit_byte((offs - short_size) & 0xFF); | |
| 6226 } else { | |
| 6227 // 0000 1111 1000 tttn #32-bit disp | |
| 6228 emit_byte(0x0F); | |
| 6229 emit_byte(0x80 | cc); | |
| 6230 emit_long(offs - long_size); | |
| 6231 } | |
| 0 | 6232 } else { |
| 304 | 6233 #ifdef ASSERT |
| 6234 warning("reversing conditional branch"); | |
| 6235 #endif /* ASSERT */ | |
| 6236 Label skip; | |
| 6237 jccb(reverse[cc], skip); | |
| 6238 lea(rscratch1, dst); | |
| 6239 Assembler::jmp(rscratch1); | |
| 6240 bind(skip); | |
| 6241 } | |
| 6242 } | |
| 6243 | |
| 6244 void MacroAssembler::ldmxcsr(AddressLiteral src) { | |
| 6245 if (reachable(src)) { | |
| 6246 Assembler::ldmxcsr(as_Address(src)); | |
| 6247 } else { | |
| 6248 lea(rscratch1, src); | |
| 6249 Assembler::ldmxcsr(Address(rscratch1, 0)); | |
| 6250 } | |
| 6251 } | |
| 6252 | |
| 6253 int MacroAssembler::load_signed_byte(Register dst, Address src) { | |
| 6254 int off; | |
| 6255 if (LP64_ONLY(true ||) VM_Version::is_P6()) { | |
| 6256 off = offset(); | |
| 6257 movsbl(dst, src); // movsxb | |
| 6258 } else { | |
| 6259 off = load_unsigned_byte(dst, src); | |
| 6260 shll(dst, 24); | |
| 6261 sarl(dst, 24); | |
| 6262 } | |
| 6263 return off; | |
| 6264 } | |
| 6265 | |
|
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6266 // Note: load_signed_short used to be called load_signed_word. |
|
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6267 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler |
|
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6268 // manual, which means 16 bits, that usage is found nowhere in HotSpot code. |
|
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6269 // The term "word" in HotSpot means a 32- or 64-bit machine word. |
|
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|
6270 int MacroAssembler::load_signed_short(Register dst, Address src) { |
| 304 | 6271 int off; |
| 6272 if (LP64_ONLY(true ||) VM_Version::is_P6()) { | |
| 6273 // This is dubious to me since it seems safe to do a signed 16 => 64 bit | |
| 6274 // version but this is what 64bit has always done. This seems to imply | |
| 6275 // that users are only using 32bits worth. | |
| 6276 off = offset(); | |
| 6277 movswl(dst, src); // movsxw | |
| 6278 } else { | |
|
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|
6279 off = load_unsigned_short(dst, src); |
| 304 | 6280 shll(dst, 16); |
| 6281 sarl(dst, 16); | |
| 6282 } | |
| 6283 return off; | |
| 6284 } | |
| 6285 | |
| 6286 int MacroAssembler::load_unsigned_byte(Register dst, Address src) { | |
| 6287 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, | |
| 6288 // and "3.9 Partial Register Penalties", p. 22). | |
| 6289 int off; | |
| 6290 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) { | |
| 6291 off = offset(); | |
| 6292 movzbl(dst, src); // movzxb | |
| 6293 } else { | |
| 6294 xorl(dst, dst); | |
| 6295 off = offset(); | |
| 6296 movb(dst, src); | |
| 6297 } | |
| 6298 return off; | |
| 6299 } | |
| 6300 | |
|
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6301 // Note: load_unsigned_short used to be called load_unsigned_word. |
|
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6302 int MacroAssembler::load_unsigned_short(Register dst, Address src) { |
| 304 | 6303 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, |
| 6304 // and "3.9 Partial Register Penalties", p. 22). | |
| 6305 int off; | |
| 6306 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) { | |
| 6307 off = offset(); | |
| 6308 movzwl(dst, src); // movzxw | |
| 6309 } else { | |
| 6310 xorl(dst, dst); | |
| 6311 off = offset(); | |
| 6312 movw(dst, src); | |
| 6313 } | |
| 6314 return off; | |
| 6315 } | |
| 6316 | |
|
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6317 void MacroAssembler::load_sized_value(Register dst, Address src, |
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6318 int size_in_bytes, bool is_signed) { |
|
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6319 switch (size_in_bytes ^ (is_signed ? -1 : 0)) { |
|
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6320 #ifndef _LP64 |
|
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6321 // For case 8, caller is responsible for manually loading |
|
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6322 // the second word into another register. |
|
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6323 case ~8: // fall through: |
|
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6324 case 8: movl( dst, src ); break; |
|
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6325 #else |
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6326 case ~8: // fall through: |
|
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6327 case 8: movq( dst, src ); break; |
|
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6328 #endif |
|
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6329 case ~4: // fall through: |
|
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6330 case 4: movl( dst, src ); break; |
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6331 case ~2: load_signed_short( dst, src ); break; |
|
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6332 case 2: load_unsigned_short( dst, src ); break; |
|
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6333 case ~1: load_signed_byte( dst, src ); break; |
|
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6334 case 1: load_unsigned_byte( dst, src ); break; |
|
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6335 default: ShouldNotReachHere(); |
|
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6336 } |
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|
6337 } |
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|
6338 |
| 304 | 6339 void MacroAssembler::mov32(AddressLiteral dst, Register src) { |
| 6340 if (reachable(dst)) { | |
| 6341 movl(as_Address(dst), src); | |
| 6342 } else { | |
| 6343 lea(rscratch1, dst); | |
| 6344 movl(Address(rscratch1, 0), src); | |
| 6345 } | |
| 6346 } | |
| 6347 | |
| 6348 void MacroAssembler::mov32(Register dst, AddressLiteral src) { | |
| 6349 if (reachable(src)) { | |
| 6350 movl(dst, as_Address(src)); | |
| 6351 } else { | |
| 6352 lea(rscratch1, src); | |
| 6353 movl(dst, Address(rscratch1, 0)); | |
| 6354 } | |
| 0 | 6355 } |
| 6356 | |
| 6357 // C++ bool manipulation | |
| 6358 | |
| 6359 void MacroAssembler::movbool(Register dst, Address src) { | |
| 6360 if(sizeof(bool) == 1) | |
| 6361 movb(dst, src); | |
| 6362 else if(sizeof(bool) == 2) | |
| 6363 movw(dst, src); | |
| 6364 else if(sizeof(bool) == 4) | |
| 6365 movl(dst, src); | |
| 6366 else | |
| 6367 // unsupported | |
| 6368 ShouldNotReachHere(); | |
| 6369 } | |
| 6370 | |
| 6371 void MacroAssembler::movbool(Address dst, bool boolconst) { | |
| 6372 if(sizeof(bool) == 1) | |
| 6373 movb(dst, (int) boolconst); | |
| 6374 else if(sizeof(bool) == 2) | |
| 6375 movw(dst, (int) boolconst); | |
| 6376 else if(sizeof(bool) == 4) | |
| 6377 movl(dst, (int) boolconst); | |
| 6378 else | |
| 6379 // unsupported | |
| 6380 ShouldNotReachHere(); | |
| 6381 } | |
| 6382 | |
| 6383 void MacroAssembler::movbool(Address dst, Register src) { | |
| 6384 if(sizeof(bool) == 1) | |
| 6385 movb(dst, src); | |
| 6386 else if(sizeof(bool) == 2) | |
| 6387 movw(dst, src); | |
| 6388 else if(sizeof(bool) == 4) | |
| 6389 movl(dst, src); | |
| 6390 else | |
| 6391 // unsupported | |
| 6392 ShouldNotReachHere(); | |
| 6393 } | |
| 6394 | |
| 304 | 6395 void MacroAssembler::movbyte(ArrayAddress dst, int src) { |
| 6396 movb(as_Address(dst), src); | |
| 6397 } | |
| 6398 | |
| 6399 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) { | |
| 6400 if (reachable(src)) { | |
| 6401 if (UseXmmLoadAndClearUpper) { | |
| 6402 movsd (dst, as_Address(src)); | |
| 6403 } else { | |
| 6404 movlpd(dst, as_Address(src)); | |
| 6405 } | |
| 6406 } else { | |
| 6407 lea(rscratch1, src); | |
| 6408 if (UseXmmLoadAndClearUpper) { | |
| 6409 movsd (dst, Address(rscratch1, 0)); | |
| 6410 } else { | |
| 6411 movlpd(dst, Address(rscratch1, 0)); | |
| 6412 } | |
| 6413 } | |
| 6414 } | |
| 6415 | |
| 6416 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) { | |
| 6417 if (reachable(src)) { | |
| 6418 movss(dst, as_Address(src)); | |
| 6419 } else { | |
| 6420 lea(rscratch1, src); | |
| 6421 movss(dst, Address(rscratch1, 0)); | |
| 6422 } | |
| 6423 } | |
| 6424 | |
| 6425 void MacroAssembler::movptr(Register dst, Register src) { | |
| 6426 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
| 6427 } | |
| 6428 | |
| 6429 void MacroAssembler::movptr(Register dst, Address src) { | |
| 6430 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
| 6431 } | |
| 6432 | |
| 6433 // src should NEVER be a real pointer. Use AddressLiteral for true pointers | |
| 6434 void MacroAssembler::movptr(Register dst, intptr_t src) { | |
| 6435 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src)); | |
| 6436 } | |
| 6437 | |
| 6438 void MacroAssembler::movptr(Address dst, Register src) { | |
| 6439 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
| 6440 } | |
| 6441 | |
| 6442 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) { | |
| 6443 if (reachable(src)) { | |
| 6444 movss(dst, as_Address(src)); | |
| 6445 } else { | |
| 6446 lea(rscratch1, src); | |
| 6447 movss(dst, Address(rscratch1, 0)); | |
| 6448 } | |
| 6449 } | |
| 6450 | |
| 6451 void MacroAssembler::null_check(Register reg, int offset) { | |
| 6452 if (needs_explicit_null_check(offset)) { | |
| 6453 // provoke OS NULL exception if reg = NULL by | |
| 6454 // accessing M[reg] w/o changing any (non-CC) registers | |
| 6455 // NOTE: cmpl is plenty here to provoke a segv | |
| 6456 cmpptr(rax, Address(reg, 0)); | |
| 6457 // Note: should probably use testl(rax, Address(reg, 0)); | |
| 6458 // may be shorter code (however, this version of | |
| 6459 // testl needs to be implemented first) | |
| 6460 } else { | |
| 6461 // nothing to do, (later) access of M[reg + offset] | |
| 6462 // will provoke OS NULL exception if reg = NULL | |
| 6463 } | |
| 6464 } | |
| 6465 | |
| 6466 void MacroAssembler::os_breakpoint() { | |
| 6467 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability | |
| 6468 // (e.g., MSVC can't call ps() otherwise) | |
| 6469 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint))); | |
| 6470 } | |
| 6471 | |
| 6472 void MacroAssembler::pop_CPU_state() { | |
| 6473 pop_FPU_state(); | |
| 6474 pop_IU_state(); | |
| 6475 } | |
| 6476 | |
| 6477 void MacroAssembler::pop_FPU_state() { | |
| 6478 NOT_LP64(frstor(Address(rsp, 0));) | |
| 6479 LP64_ONLY(fxrstor(Address(rsp, 0));) | |
| 6480 addptr(rsp, FPUStateSizeInWords * wordSize); | |
| 6481 } | |
| 6482 | |
| 6483 void MacroAssembler::pop_IU_state() { | |
| 6484 popa(); | |
| 6485 LP64_ONLY(addq(rsp, 8)); | |
| 6486 popf(); | |
| 6487 } | |
| 6488 | |
| 6489 // Save Integer and Float state | |
| 6490 // Warning: Stack must be 16 byte aligned (64bit) | |
| 6491 void MacroAssembler::push_CPU_state() { | |
| 6492 push_IU_state(); | |
| 6493 push_FPU_state(); | |
| 6494 } | |
| 6495 | |
| 6496 void MacroAssembler::push_FPU_state() { | |
| 6497 subptr(rsp, FPUStateSizeInWords * wordSize); | |
| 6498 #ifndef _LP64 | |
| 6499 fnsave(Address(rsp, 0)); | |
| 6500 fwait(); | |
| 6501 #else | |
| 6502 fxsave(Address(rsp, 0)); | |
| 6503 #endif // LP64 | |
| 6504 } | |
| 6505 | |
| 6506 void MacroAssembler::push_IU_state() { | |
| 6507 // Push flags first because pusha kills them | |
| 6508 pushf(); | |
| 6509 // Make sure rsp stays 16-byte aligned | |
| 6510 LP64_ONLY(subq(rsp, 8)); | |
| 6511 pusha(); | |
| 6512 } | |
| 6513 | |
| 6514 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) { | |
| 6515 // determine java_thread register | |
| 6516 if (!java_thread->is_valid()) { | |
| 6517 java_thread = rdi; | |
| 6518 get_thread(java_thread); | |
| 6519 } | |
| 6520 // we must set sp to zero to clear frame | |
|
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6521 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); |
| 304 | 6522 if (clear_fp) { |
|
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|
6523 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); |
| 304 | 6524 } |
| 6525 | |
| 6526 if (clear_pc) | |
|
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|
6527 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); |
| 304 | 6528 |
| 6529 } | |
| 6530 | |
| 6531 void MacroAssembler::restore_rax(Register tmp) { | |
| 6532 if (tmp == noreg) pop(rax); | |
| 6533 else if (tmp != rax) mov(rax, tmp); | |
| 6534 } | |
| 6535 | |
| 6536 void MacroAssembler::round_to(Register reg, int modulus) { | |
| 6537 addptr(reg, modulus - 1); | |
| 6538 andptr(reg, -modulus); | |
| 6539 } | |
| 6540 | |
| 6541 void MacroAssembler::save_rax(Register tmp) { | |
| 6542 if (tmp == noreg) push(rax); | |
| 6543 else if (tmp != rax) mov(tmp, rax); | |
| 6544 } | |
| 6545 | |
| 6546 // Write serialization page so VM thread can do a pseudo remote membar. | |
| 6547 // We use the current thread pointer to calculate a thread specific | |
| 6548 // offset to write to within the page. This minimizes bus traffic | |
| 6549 // due to cache line collision. | |
| 6550 void MacroAssembler::serialize_memory(Register thread, Register tmp) { | |
| 6551 movl(tmp, thread); | |
| 6552 shrl(tmp, os::get_serialize_page_shift_count()); | |
| 6553 andl(tmp, (os::vm_page_size() - sizeof(int))); | |
| 6554 | |
| 6555 Address index(noreg, tmp, Address::times_1); | |
| 6556 ExternalAddress page(os::get_memory_serialize_page()); | |
| 6557 | |
|
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|
6558 // Size of store must match masking code above |
|
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|
6559 movl(as_Address(ArrayAddress(page, index)), tmp); |
| 304 | 6560 } |
| 6561 | |
| 6562 // Calls to C land | |
| 6563 // | |
| 6564 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded | |
| 6565 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp | |
| 6566 // has to be reset to 0. This is required to allow proper stack traversal. | |
| 6567 void MacroAssembler::set_last_Java_frame(Register java_thread, | |
| 6568 Register last_java_sp, | |
| 6569 Register last_java_fp, | |
| 6570 address last_java_pc) { | |
| 6571 // determine java_thread register | |
| 6572 if (!java_thread->is_valid()) { | |
| 6573 java_thread = rdi; | |
| 6574 get_thread(java_thread); | |
| 6575 } | |
| 6576 // determine last_java_sp register | |
| 6577 if (!last_java_sp->is_valid()) { | |
| 6578 last_java_sp = rsp; | |
| 6579 } | |
| 6580 | |
| 6581 // last_java_fp is optional | |
| 6582 | |
| 6583 if (last_java_fp->is_valid()) { | |
| 6584 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp); | |
| 6585 } | |
| 6586 | |
| 6587 // last_java_pc is optional | |
| 6588 | |
| 6589 if (last_java_pc != NULL) { | |
| 6590 lea(Address(java_thread, | |
| 6591 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()), | |
| 6592 InternalAddress(last_java_pc)); | |
| 6593 | |
| 6594 } | |
| 6595 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp); | |
| 6596 } | |
| 6597 | |
| 6598 void MacroAssembler::shlptr(Register dst, int imm8) { | |
| 6599 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8)); | |
| 6600 } | |
| 6601 | |
| 6602 void MacroAssembler::shrptr(Register dst, int imm8) { | |
| 6603 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8)); | |
| 6604 } | |
| 6605 | |
| 6606 void MacroAssembler::sign_extend_byte(Register reg) { | |
| 6607 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) { | |
| 6608 movsbl(reg, reg); // movsxb | |
| 6609 } else { | |
| 6610 shll(reg, 24); | |
| 6611 sarl(reg, 24); | |
| 6612 } | |
| 6613 } | |
| 6614 | |
| 6615 void MacroAssembler::sign_extend_short(Register reg) { | |
| 6616 if (LP64_ONLY(true ||) VM_Version::is_P6()) { | |
| 6617 movswl(reg, reg); // movsxw | |
| 6618 } else { | |
| 6619 shll(reg, 16); | |
| 6620 sarl(reg, 16); | |
| 6621 } | |
| 6622 } | |
| 6623 | |
| 362 | 6624 ////////////////////////////////////////////////////////////////////////////////// |
| 6625 #ifndef SERIALGC | |
| 6626 | |
| 6627 void MacroAssembler::g1_write_barrier_pre(Register obj, | |
| 6628 #ifndef _LP64 | |
| 6629 Register thread, | |
| 6630 #endif | |
| 6631 Register tmp, | |
| 6632 Register tmp2, | |
| 6633 bool tosca_live) { | |
| 6634 LP64_ONLY(Register thread = r15_thread;) | |
| 6635 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() + | |
| 6636 PtrQueue::byte_offset_of_active())); | |
| 6637 | |
| 6638 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() + | |
| 6639 PtrQueue::byte_offset_of_index())); | |
| 6640 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() + | |
| 6641 PtrQueue::byte_offset_of_buf())); | |
| 6642 | |
| 6643 | |
| 6644 Label done; | |
| 6645 Label runtime; | |
| 6646 | |
| 6647 // if (!marking_in_progress) goto done; | |
| 6648 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) { | |
| 6649 cmpl(in_progress, 0); | |
| 6650 } else { | |
| 6651 assert(in_bytes(PtrQueue::byte_width_of_active()) == 1, "Assumption"); | |
| 6652 cmpb(in_progress, 0); | |
| 6653 } | |
| 6654 jcc(Assembler::equal, done); | |
| 6655 | |
| 6656 // if (x.f == NULL) goto done; | |
| 6657 cmpptr(Address(obj, 0), NULL_WORD); | |
| 6658 jcc(Assembler::equal, done); | |
| 6659 | |
| 6660 // Can we store original value in the thread's buffer? | |
| 6661 | |
| 6662 LP64_ONLY(movslq(tmp, index);) | |
| 6663 movptr(tmp2, Address(obj, 0)); | |
| 6664 #ifdef _LP64 | |
| 6665 cmpq(tmp, 0); | |
| 6666 #else | |
| 6667 cmpl(index, 0); | |
| 6668 #endif | |
| 6669 jcc(Assembler::equal, runtime); | |
| 6670 #ifdef _LP64 | |
| 6671 subq(tmp, wordSize); | |
| 6672 movl(index, tmp); | |
| 6673 addq(tmp, buffer); | |
| 6674 #else | |
| 6675 subl(index, wordSize); | |
| 6676 movl(tmp, buffer); | |
| 6677 addl(tmp, index); | |
| 6678 #endif | |
| 6679 movptr(Address(tmp, 0), tmp2); | |
| 6680 jmp(done); | |
| 6681 bind(runtime); | |
| 6682 // save the live input values | |
| 6683 if(tosca_live) push(rax); | |
| 6684 push(obj); | |
| 6685 #ifdef _LP64 | |
| 6686 movq(c_rarg0, Address(obj, 0)); | |
| 6687 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), c_rarg0, r15_thread); | |
| 6688 #else | |
| 6689 push(thread); | |
| 6690 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), tmp2, thread); | |
| 6691 pop(thread); | |
| 6692 #endif | |
| 6693 pop(obj); | |
| 6694 if(tosca_live) pop(rax); | |
| 6695 bind(done); | |
| 6696 | |
| 6697 } | |
| 6698 | |
| 6699 void MacroAssembler::g1_write_barrier_post(Register store_addr, | |
| 6700 Register new_val, | |
| 6701 #ifndef _LP64 | |
| 6702 Register thread, | |
| 6703 #endif | |
| 6704 Register tmp, | |
| 6705 Register tmp2) { | |
| 6706 | |
| 6707 LP64_ONLY(Register thread = r15_thread;) | |
| 6708 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() + | |
| 6709 PtrQueue::byte_offset_of_index())); | |
| 6710 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() + | |
| 6711 PtrQueue::byte_offset_of_buf())); | |
| 6712 BarrierSet* bs = Universe::heap()->barrier_set(); | |
| 6713 CardTableModRefBS* ct = (CardTableModRefBS*)bs; | |
| 6714 Label done; | |
| 6715 Label runtime; | |
| 6716 | |
| 6717 // Does store cross heap regions? | |
| 6718 | |
| 6719 movptr(tmp, store_addr); | |
| 6720 xorptr(tmp, new_val); | |
| 6721 shrptr(tmp, HeapRegion::LogOfHRGrainBytes); | |
| 6722 jcc(Assembler::equal, done); | |
| 6723 | |
| 6724 // crosses regions, storing NULL? | |
| 6725 | |
| 6726 cmpptr(new_val, (int32_t) NULL_WORD); | |
| 6727 jcc(Assembler::equal, done); | |
| 6728 | |
| 6729 // storing region crossing non-NULL, is card already dirty? | |
| 6730 | |
| 6731 ExternalAddress cardtable((address) ct->byte_map_base); | |
| 6732 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); | |
| 6733 #ifdef _LP64 | |
| 6734 const Register card_addr = tmp; | |
| 6735 | |
| 6736 movq(card_addr, store_addr); | |
| 6737 shrq(card_addr, CardTableModRefBS::card_shift); | |
| 6738 | |
| 6739 lea(tmp2, cardtable); | |
| 6740 | |
| 6741 // get the address of the card | |
| 6742 addq(card_addr, tmp2); | |
| 6743 #else | |
| 6744 const Register card_index = tmp; | |
| 6745 | |
| 6746 movl(card_index, store_addr); | |
| 6747 shrl(card_index, CardTableModRefBS::card_shift); | |
| 6748 | |
| 6749 Address index(noreg, card_index, Address::times_1); | |
| 6750 const Register card_addr = tmp; | |
| 6751 lea(card_addr, as_Address(ArrayAddress(cardtable, index))); | |
| 6752 #endif | |
| 6753 cmpb(Address(card_addr, 0), 0); | |
| 6754 jcc(Assembler::equal, done); | |
| 6755 | |
| 6756 // storing a region crossing, non-NULL oop, card is clean. | |
| 6757 // dirty card and log. | |
| 6758 | |
| 6759 movb(Address(card_addr, 0), 0); | |
| 6760 | |
| 6761 cmpl(queue_index, 0); | |
| 6762 jcc(Assembler::equal, runtime); | |
| 6763 subl(queue_index, wordSize); | |
| 6764 movptr(tmp2, buffer); | |
| 6765 #ifdef _LP64 | |
| 6766 movslq(rscratch1, queue_index); | |
| 6767 addq(tmp2, rscratch1); | |
| 6768 movq(Address(tmp2, 0), card_addr); | |
| 6769 #else | |
| 6770 addl(tmp2, queue_index); | |
| 6771 movl(Address(tmp2, 0), card_index); | |
| 6772 #endif | |
| 6773 jmp(done); | |
| 6774 | |
| 6775 bind(runtime); | |
| 6776 // save the live input values | |
| 6777 push(store_addr); | |
| 6778 push(new_val); | |
| 6779 #ifdef _LP64 | |
| 6780 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread); | |
| 6781 #else | |
| 6782 push(thread); | |
| 6783 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread); | |
| 6784 pop(thread); | |
| 6785 #endif | |
| 6786 pop(new_val); | |
| 6787 pop(store_addr); | |
| 6788 | |
| 6789 bind(done); | |
| 6790 | |
| 6791 } | |
| 6792 | |
| 6793 #endif // SERIALGC | |
| 6794 ////////////////////////////////////////////////////////////////////////////////// | |
| 6795 | |
| 6796 | |
| 304 | 6797 void MacroAssembler::store_check(Register obj) { |
| 6798 // Does a store check for the oop in register obj. The content of | |
| 6799 // register obj is destroyed afterwards. | |
| 6800 store_check_part_1(obj); | |
| 6801 store_check_part_2(obj); | |
| 6802 } | |
| 6803 | |
| 6804 void MacroAssembler::store_check(Register obj, Address dst) { | |
| 6805 store_check(obj); | |
| 6806 } | |
| 6807 | |
| 6808 | |
| 6809 // split the store check operation so that other instructions can be scheduled inbetween | |
| 6810 void MacroAssembler::store_check_part_1(Register obj) { | |
| 6811 BarrierSet* bs = Universe::heap()->barrier_set(); | |
| 6812 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind"); | |
| 6813 shrptr(obj, CardTableModRefBS::card_shift); | |
| 6814 } | |
| 6815 | |
| 6816 void MacroAssembler::store_check_part_2(Register obj) { | |
| 6817 BarrierSet* bs = Universe::heap()->barrier_set(); | |
| 6818 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind"); | |
| 6819 CardTableModRefBS* ct = (CardTableModRefBS*)bs; | |
| 6820 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); | |
| 6821 | |
| 6822 // The calculation for byte_map_base is as follows: | |
| 6823 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift); | |
| 6824 // So this essentially converts an address to a displacement and | |
| 6825 // it will never need to be relocated. On 64bit however the value may be too | |
| 6826 // large for a 32bit displacement | |
| 6827 | |
| 6828 intptr_t disp = (intptr_t) ct->byte_map_base; | |
| 6829 if (is_simm32(disp)) { | |
| 6830 Address cardtable(noreg, obj, Address::times_1, disp); | |
| 6831 movb(cardtable, 0); | |
| 6832 } else { | |
| 6833 // By doing it as an ExternalAddress disp could be converted to a rip-relative | |
| 6834 // displacement and done in a single instruction given favorable mapping and | |
| 6835 // a smarter version of as_Address. Worst case it is two instructions which | |
| 6836 // is no worse off then loading disp into a register and doing as a simple | |
| 6837 // Address() as above. | |
| 6838 // We can't do as ExternalAddress as the only style since if disp == 0 we'll | |
| 6839 // assert since NULL isn't acceptable in a reloci (see 6644928). In any case | |
| 6840 // in some cases we'll get a single instruction version. | |
| 6841 | |
| 6842 ExternalAddress cardtable((address)disp); | |
| 6843 Address index(noreg, obj, Address::times_1); | |
| 6844 movb(as_Address(ArrayAddress(cardtable, index)), 0); | |
| 6845 } | |
| 6846 } | |
| 6847 | |
| 6848 void MacroAssembler::subptr(Register dst, int32_t imm32) { | |
| 6849 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32)); | |
| 6850 } | |
| 6851 | |
| 6852 void MacroAssembler::subptr(Register dst, Register src) { | |
| 6853 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); | |
| 6854 } | |
| 6855 | |
| 6856 void MacroAssembler::test32(Register src1, AddressLiteral src2) { | |
| 6857 // src2 must be rval | |
| 6858 | |
| 6859 if (reachable(src2)) { | |
| 6860 testl(src1, as_Address(src2)); | |
| 6861 } else { | |
| 6862 lea(rscratch1, src2); | |
| 6863 testl(src1, Address(rscratch1, 0)); | |
| 6864 } | |
| 6865 } | |
| 6866 | |
| 6867 // C++ bool manipulation | |
| 0 | 6868 void MacroAssembler::testbool(Register dst) { |
| 6869 if(sizeof(bool) == 1) | |
| 304 | 6870 testb(dst, 0xff); |
| 0 | 6871 else if(sizeof(bool) == 2) { |
| 6872 // testw implementation needed for two byte bools | |
| 6873 ShouldNotReachHere(); | |
| 6874 } else if(sizeof(bool) == 4) | |
| 6875 testl(dst, dst); | |
| 6876 else | |
| 6877 // unsupported | |
| 6878 ShouldNotReachHere(); | |
| 6879 } | |
| 6880 | |
| 304 | 6881 void MacroAssembler::testptr(Register dst, Register src) { |
| 6882 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src)); | |
| 6883 } | |
| 6884 | |
| 6885 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes. | |
| 6886 void MacroAssembler::tlab_allocate(Register obj, | |
| 6887 Register var_size_in_bytes, | |
| 6888 int con_size_in_bytes, | |
| 6889 Register t1, | |
| 6890 Register t2, | |
| 6891 Label& slow_case) { | |
| 6892 assert_different_registers(obj, t1, t2); | |
| 6893 assert_different_registers(obj, var_size_in_bytes, t1); | |
| 6894 Register end = t2; | |
| 6895 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread); | |
| 6896 | |
| 6897 verify_tlab(); | |
| 6898 | |
| 6899 NOT_LP64(get_thread(thread)); | |
| 6900 | |
| 6901 movptr(obj, Address(thread, JavaThread::tlab_top_offset())); | |
| 6902 if (var_size_in_bytes == noreg) { | |
| 6903 lea(end, Address(obj, con_size_in_bytes)); | |
| 6904 } else { | |
| 6905 lea(end, Address(obj, var_size_in_bytes, Address::times_1)); | |
| 6906 } | |
| 6907 cmpptr(end, Address(thread, JavaThread::tlab_end_offset())); | |
| 6908 jcc(Assembler::above, slow_case); | |
| 6909 | |
| 6910 // update the tlab top pointer | |
| 6911 movptr(Address(thread, JavaThread::tlab_top_offset()), end); | |
| 6912 | |
| 6913 // recover var_size_in_bytes if necessary | |
| 6914 if (var_size_in_bytes == end) { | |
| 6915 subptr(var_size_in_bytes, obj); | |
| 6916 } | |
| 6917 verify_tlab(); | |
| 6918 } | |
| 6919 | |
| 6920 // Preserves rbx, and rdx. | |
| 6921 void MacroAssembler::tlab_refill(Label& retry, | |
| 6922 Label& try_eden, | |
| 6923 Label& slow_case) { | |
| 6924 Register top = rax; | |
| 6925 Register t1 = rcx; | |
| 6926 Register t2 = rsi; | |
| 6927 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread); | |
| 6928 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx); | |
| 6929 Label do_refill, discard_tlab; | |
| 6930 | |
| 6931 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { | |
| 6932 // No allocation in the shared eden. | |
| 6933 jmp(slow_case); | |
| 6934 } | |
| 6935 | |
| 6936 NOT_LP64(get_thread(thread_reg)); | |
| 6937 | |
| 6938 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); | |
| 6939 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); | |
| 6940 | |
| 6941 // calculate amount of free space | |
| 6942 subptr(t1, top); | |
| 6943 shrptr(t1, LogHeapWordSize); | |
| 6944 | |
| 6945 // Retain tlab and allocate object in shared space if | |
| 6946 // the amount free in the tlab is too large to discard. | |
| 6947 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset()))); | |
| 6948 jcc(Assembler::lessEqual, discard_tlab); | |
| 6949 | |
| 6950 // Retain | |
| 6951 // %%% yuck as movptr... | |
| 6952 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment()); | |
| 6953 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2); | |
| 6954 if (TLABStats) { | |
| 6955 // increment number of slow_allocations | |
| 6956 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1); | |
| 6957 } | |
| 6958 jmp(try_eden); | |
| 6959 | |
| 6960 bind(discard_tlab); | |
| 6961 if (TLABStats) { | |
| 6962 // increment number of refills | |
| 6963 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1); | |
| 6964 // accumulate wastage -- t1 is amount free in tlab | |
| 6965 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1); | |
| 6966 } | |
| 6967 | |
| 6968 // if tlab is currently allocated (top or end != null) then | |
| 6969 // fill [top, end + alignment_reserve) with array object | |
| 6970 testptr (top, top); | |
| 6971 jcc(Assembler::zero, do_refill); | |
| 6972 | |
| 6973 // set up the mark word | |
| 6974 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2)); | |
| 6975 // set the length to the remaining space | |
| 6976 subptr(t1, typeArrayOopDesc::header_size(T_INT)); | |
| 6977 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve()); | |
| 6978 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint))); | |
| 6979 movptr(Address(top, arrayOopDesc::length_offset_in_bytes()), t1); | |
| 6980 // set klass to intArrayKlass | |
| 6981 // dubious reloc why not an oop reloc? | |
| 6982 movptr(t1, ExternalAddress((address) Universe::intArrayKlassObj_addr())); | |
| 6983 // store klass last. concurrent gcs assumes klass length is valid if | |
| 6984 // klass field is not null. | |
| 6985 store_klass(top, t1); | |
| 6986 | |
| 6987 // refill the tlab with an eden allocation | |
| 6988 bind(do_refill); | |
| 6989 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); | |
| 6990 shlptr(t1, LogHeapWordSize); | |
| 6991 // add object_size ?? | |
| 6992 eden_allocate(top, t1, 0, t2, slow_case); | |
| 6993 | |
| 6994 // Check that t1 was preserved in eden_allocate. | |
| 6995 #ifdef ASSERT | |
| 6996 if (UseTLAB) { | |
| 6997 Label ok; | |
| 6998 Register tsize = rsi; | |
| 6999 assert_different_registers(tsize, thread_reg, t1); | |
| 7000 push(tsize); | |
| 7001 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); | |
| 7002 shlptr(tsize, LogHeapWordSize); | |
| 7003 cmpptr(t1, tsize); | |
| 7004 jcc(Assembler::equal, ok); | |
| 7005 stop("assert(t1 != tlab size)"); | |
| 7006 should_not_reach_here(); | |
| 7007 | |
| 7008 bind(ok); | |
| 7009 pop(tsize); | |
| 7010 } | |
| 7011 #endif | |
| 7012 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top); | |
| 7013 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top); | |
| 7014 addptr(top, t1); | |
| 7015 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes()); | |
| 7016 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top); | |
| 7017 verify_tlab(); | |
| 7018 jmp(retry); | |
| 7019 } | |
| 7020 | |
| 7021 static const double pi_4 = 0.7853981633974483; | |
| 7022 | |
| 7023 void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) { | |
| 7024 // A hand-coded argument reduction for values in fabs(pi/4, pi/2) | |
| 7025 // was attempted in this code; unfortunately it appears that the | |
| 7026 // switch to 80-bit precision and back causes this to be | |
| 7027 // unprofitable compared with simply performing a runtime call if | |
| 7028 // the argument is out of the (-pi/4, pi/4) range. | |
| 7029 | |
| 7030 Register tmp = noreg; | |
| 7031 if (!VM_Version::supports_cmov()) { | |
| 7032 // fcmp needs a temporary so preserve rbx, | |
| 7033 tmp = rbx; | |
| 7034 push(tmp); | |
| 7035 } | |
| 7036 | |
| 7037 Label slow_case, done; | |
| 7038 | |
|
520
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7039 ExternalAddress pi4_adr = (address)&pi_4; |
|
52a431267315
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diff
changeset
|
7040 if (reachable(pi4_adr)) { |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
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diff
changeset
|
7041 // x ?<= pi/4 |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
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diff
changeset
|
7042 fld_d(pi4_adr); |
|
52a431267315
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diff
changeset
|
7043 fld_s(1); // Stack: X PI/4 X |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
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diff
changeset
|
7044 fabs(); // Stack: |X| PI/4 X |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
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diff
changeset
|
7045 fcmp(tmp); |
|
52a431267315
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diff
changeset
|
7046 jcc(Assembler::above, slow_case); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7047 |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7048 // fastest case: -pi/4 <= x <= pi/4 |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7049 switch(trig) { |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7050 case 's': |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7051 fsin(); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7052 break; |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7053 case 'c': |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7054 fcos(); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7055 break; |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7056 case 't': |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7057 ftan(); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7058 break; |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7059 default: |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7060 assert(false, "bad intrinsic"); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7061 break; |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7062 } |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7063 jmp(done); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7064 } |
| 304 | 7065 |
| 7066 // slow case: runtime call | |
| 7067 bind(slow_case); | |
| 7068 // Preserve registers across runtime call | |
| 7069 pusha(); | |
| 7070 int incoming_argument_and_return_value_offset = -1; | |
| 7071 if (num_fpu_regs_in_use > 1) { | |
| 7072 // Must preserve all other FPU regs (could alternatively convert | |
| 7073 // SharedRuntime::dsin and dcos into assembly routines known not to trash | |
| 7074 // FPU state, but can not trust C compiler) | |
| 7075 NEEDS_CLEANUP; | |
| 7076 // NOTE that in this case we also push the incoming argument to | |
| 7077 // the stack and restore it later; we also use this stack slot to | |
| 7078 // hold the return value from dsin or dcos. | |
| 7079 for (int i = 0; i < num_fpu_regs_in_use; i++) { | |
| 7080 subptr(rsp, sizeof(jdouble)); | |
| 7081 fstp_d(Address(rsp, 0)); | |
| 7082 } | |
| 7083 incoming_argument_and_return_value_offset = sizeof(jdouble)*(num_fpu_regs_in_use-1); | |
| 7084 fld_d(Address(rsp, incoming_argument_and_return_value_offset)); | |
| 7085 } | |
| 7086 subptr(rsp, sizeof(jdouble)); | |
| 7087 fstp_d(Address(rsp, 0)); | |
| 7088 #ifdef _LP64 | |
| 7089 movdbl(xmm0, Address(rsp, 0)); | |
| 7090 #endif // _LP64 | |
| 7091 | |
| 7092 // NOTE: we must not use call_VM_leaf here because that requires a | |
| 7093 // complete interpreter frame in debug mode -- same bug as 4387334 | |
| 7094 // MacroAssembler::call_VM_leaf_base is perfectly safe and will | |
| 7095 // do proper 64bit abi | |
| 7096 | |
| 7097 NEEDS_CLEANUP; | |
| 7098 // Need to add stack banging before this runtime call if it needs to | |
| 7099 // be taken; however, there is no generic stack banging routine at | |
| 7100 // the MacroAssembler level | |
| 7101 switch(trig) { | |
| 7102 case 's': | |
| 7103 { | |
| 7104 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), 0); | |
| 7105 } | |
| 7106 break; | |
| 7107 case 'c': | |
| 7108 { | |
| 7109 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), 0); | |
| 7110 } | |
| 7111 break; | |
| 7112 case 't': | |
| 7113 { | |
| 7114 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dtan), 0); | |
| 7115 } | |
| 7116 break; | |
| 7117 default: | |
| 7118 assert(false, "bad intrinsic"); | |
| 7119 break; | |
| 7120 } | |
| 7121 #ifdef _LP64 | |
| 7122 movsd(Address(rsp, 0), xmm0); | |
| 7123 fld_d(Address(rsp, 0)); | |
| 7124 #endif // _LP64 | |
| 7125 addptr(rsp, sizeof(jdouble)); | |
| 7126 if (num_fpu_regs_in_use > 1) { | |
| 7127 // Must save return value to stack and then restore entire FPU stack | |
| 7128 fstp_d(Address(rsp, incoming_argument_and_return_value_offset)); | |
| 7129 for (int i = 0; i < num_fpu_regs_in_use; i++) { | |
| 7130 fld_d(Address(rsp, 0)); | |
| 7131 addptr(rsp, sizeof(jdouble)); | |
| 7132 } | |
| 7133 } | |
| 7134 popa(); | |
| 7135 | |
| 7136 // Come here with result in F-TOS | |
| 7137 bind(done); | |
| 7138 | |
| 7139 if (tmp != noreg) { | |
| 7140 pop(tmp); | |
| 7141 } | |
| 7142 } | |
| 7143 | |
| 7144 | |
|
623
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7145 // Look up the method for a megamorphic invokeinterface call. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7146 // The target method is determined by <intf_klass, itable_index>. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7147 // The receiver klass is in recv_klass. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7148 // On success, the result will be in method_result, and execution falls through. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7149 // On failure, execution transfers to the given label. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7150 void MacroAssembler::lookup_interface_method(Register recv_klass, |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7151 Register intf_klass, |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7152 RegisterConstant itable_index, |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7153 Register method_result, |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7154 Register scan_temp, |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7155 Label& L_no_such_interface) { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7156 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7157 assert(itable_index.is_constant() || itable_index.as_register() == method_result, |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7158 "caller must use same register for non-constant itable index as for method"); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7159 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7160 // Compute start of first itableOffsetEntry (which is at the end of the vtable) |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7161 int vtable_base = instanceKlass::vtable_start_offset() * wordSize; |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7162 int itentry_off = itableMethodEntry::method_offset_in_bytes(); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7163 int scan_step = itableOffsetEntry::size() * wordSize; |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7164 int vte_size = vtableEntry::size() * wordSize; |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7165 Address::ScaleFactor times_vte_scale = Address::times_ptr; |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7166 assert(vte_size == wordSize, "else adjust times_vte_scale"); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7167 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7168 movl(scan_temp, Address(recv_klass, instanceKlass::vtable_length_offset() * wordSize)); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7169 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7170 // %%% Could store the aligned, prescaled offset in the klassoop. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7171 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base)); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7172 if (HeapWordsPerLong > 1) { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7173 // Round up to align_object_offset boundary |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7174 // see code for instanceKlass::start_of_itable! |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7175 round_to(scan_temp, BytesPerLong); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7176 } |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7177 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7178 // Adjust recv_klass by scaled itable_index, so we can free itable_index. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7179 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below"); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7180 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off)); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7181 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7182 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7183 // if (scan->interface() == intf) { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7184 // result = (klass + scan->offset() + itable_index); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7185 // } |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7186 // } |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7187 Label search, found_method; |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7188 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7189 for (int peel = 1; peel >= 0; peel--) { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7190 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes())); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7191 cmpptr(intf_klass, method_result); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7192 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7193 if (peel) { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7194 jccb(Assembler::equal, found_method); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7195 } else { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7196 jccb(Assembler::notEqual, search); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7197 // (invert the test to fall through to found_method...) |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7198 } |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7199 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7200 if (!peel) break; |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7201 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7202 bind(search); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7203 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7204 // Check that the previous entry is non-null. A null entry means that |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7205 // the receiver class doesn't implement the interface, and wasn't the |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7206 // same as when the caller was compiled. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7207 testptr(method_result, method_result); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7208 jcc(Assembler::zero, L_no_such_interface); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7209 addptr(scan_temp, scan_step); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7210 } |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7211 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7212 bind(found_method); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7213 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7214 // Got a hit. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7215 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes())); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7216 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1)); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7217 } |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7218 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7219 |
| 304 | 7220 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) { |
| 7221 ucomisd(dst, as_Address(src)); | |
| 7222 } | |
| 7223 | |
| 7224 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) { | |
| 7225 ucomiss(dst, as_Address(src)); | |
| 7226 } | |
| 7227 | |
| 7228 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) { | |
| 7229 if (reachable(src)) { | |
| 7230 xorpd(dst, as_Address(src)); | |
| 7231 } else { | |
| 7232 lea(rscratch1, src); | |
| 7233 xorpd(dst, Address(rscratch1, 0)); | |
| 7234 } | |
| 7235 } | |
| 7236 | |
| 7237 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) { | |
| 7238 if (reachable(src)) { | |
| 7239 xorps(dst, as_Address(src)); | |
| 7240 } else { | |
| 7241 lea(rscratch1, src); | |
| 7242 xorps(dst, Address(rscratch1, 0)); | |
| 7243 } | |
| 7244 } | |
| 7245 | |
| 0 | 7246 void MacroAssembler::verify_oop(Register reg, const char* s) { |
| 7247 if (!VerifyOops) return; | |
| 304 | 7248 |
| 0 | 7249 // Pass register number to verify_oop_subroutine |
| 7250 char* b = new char[strlen(s) + 50]; | |
| 7251 sprintf(b, "verify_oop: %s: %s", reg->name(), s); | |
| 304 | 7252 push(rax); // save rax, |
| 7253 push(reg); // pass register argument | |
| 0 | 7254 ExternalAddress buffer((address) b); |
| 304 | 7255 // avoid using pushptr, as it modifies scratch registers |
| 7256 // and our contract is not to modify anything | |
| 7257 movptr(rax, buffer.addr()); | |
| 7258 push(rax); | |
| 0 | 7259 // call indirectly to solve generation ordering problem |
| 7260 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); | |
| 7261 call(rax); | |
| 7262 } | |
| 7263 | |
| 7264 | |
|
622
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7265 RegisterConstant MacroAssembler::delayed_value(intptr_t* delayed_value_addr, |
|
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7266 Register tmp, |
|
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7267 int offset) { |
|
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7268 intptr_t value = *delayed_value_addr; |
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7269 if (value != 0) |
|
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7270 return RegisterConstant(value + offset); |
|
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7271 |
|
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7272 // load indirectly to solve generation ordering problem |
|
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7273 movptr(tmp, ExternalAddress((address) delayed_value_addr)); |
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7274 |
|
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7275 #ifdef ASSERT |
|
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7276 Label L; |
|
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7277 testl(tmp, tmp); |
|
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7278 jccb(Assembler::notZero, L); |
|
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7279 hlt(); |
|
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7280 bind(L); |
|
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7281 #endif |
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7282 |
|
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7283 if (offset != 0) |
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7284 addptr(tmp, offset); |
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7285 |
|
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7286 return RegisterConstant(tmp); |
|
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7287 } |
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7288 |
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|
7289 |
| 0 | 7290 void MacroAssembler::verify_oop_addr(Address addr, const char* s) { |
| 7291 if (!VerifyOops) return; | |
| 304 | 7292 |
| 0 | 7293 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord); |
| 7294 // Pass register number to verify_oop_subroutine | |
| 7295 char* b = new char[strlen(s) + 50]; | |
| 7296 sprintf(b, "verify_oop_addr: %s", s); | |
| 304 | 7297 |
| 7298 push(rax); // save rax, | |
| 0 | 7299 // addr may contain rsp so we will have to adjust it based on the push |
| 7300 // we just did | |
| 304 | 7301 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which |
| 7302 // stores rax into addr which is backwards of what was intended. | |
| 0 | 7303 if (addr.uses(rsp)) { |
| 304 | 7304 lea(rax, addr); |
| 7305 pushptr(Address(rax, BytesPerWord)); | |
| 0 | 7306 } else { |
| 304 | 7307 pushptr(addr); |
| 7308 } | |
| 7309 | |
| 0 | 7310 ExternalAddress buffer((address) b); |
| 7311 // pass msg argument | |
| 304 | 7312 // avoid using pushptr, as it modifies scratch registers |
| 7313 // and our contract is not to modify anything | |
| 7314 movptr(rax, buffer.addr()); | |
| 7315 push(rax); | |
| 7316 | |
| 0 | 7317 // call indirectly to solve generation ordering problem |
| 7318 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); | |
| 7319 call(rax); | |
| 7320 // Caller pops the arguments and restores rax, from the stack | |
| 7321 } | |
| 7322 | |
| 304 | 7323 void MacroAssembler::verify_tlab() { |
| 7324 #ifdef ASSERT | |
| 7325 if (UseTLAB && VerifyOops) { | |
| 7326 Label next, ok; | |
| 7327 Register t1 = rsi; | |
| 7328 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread); | |
| 7329 | |
| 7330 push(t1); | |
| 7331 NOT_LP64(push(thread_reg)); | |
| 7332 NOT_LP64(get_thread(thread_reg)); | |
| 7333 | |
| 7334 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); | |
| 7335 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); | |
| 7336 jcc(Assembler::aboveEqual, next); | |
| 7337 stop("assert(top >= start)"); | |
| 7338 should_not_reach_here(); | |
| 7339 | |
| 7340 bind(next); | |
| 7341 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); | |
| 7342 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); | |
| 7343 jcc(Assembler::aboveEqual, ok); | |
| 7344 stop("assert(top <= end)"); | |
| 7345 should_not_reach_here(); | |
| 7346 | |
| 7347 bind(ok); | |
| 7348 NOT_LP64(pop(thread_reg)); | |
| 7349 pop(t1); | |
| 7350 } | |
| 7351 #endif | |
| 7352 } | |
| 0 | 7353 |
| 7354 class ControlWord { | |
| 7355 public: | |
| 7356 int32_t _value; | |
| 7357 | |
| 7358 int rounding_control() const { return (_value >> 10) & 3 ; } | |
| 7359 int precision_control() const { return (_value >> 8) & 3 ; } | |
| 7360 bool precision() const { return ((_value >> 5) & 1) != 0; } | |
| 7361 bool underflow() const { return ((_value >> 4) & 1) != 0; } | |
| 7362 bool overflow() const { return ((_value >> 3) & 1) != 0; } | |
| 7363 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } | |
| 7364 bool denormalized() const { return ((_value >> 1) & 1) != 0; } | |
| 7365 bool invalid() const { return ((_value >> 0) & 1) != 0; } | |
| 7366 | |
| 7367 void print() const { | |
| 7368 // rounding control | |
| 7369 const char* rc; | |
| 7370 switch (rounding_control()) { | |
| 7371 case 0: rc = "round near"; break; | |
| 7372 case 1: rc = "round down"; break; | |
| 7373 case 2: rc = "round up "; break; | |
| 7374 case 3: rc = "chop "; break; | |
| 7375 }; | |
| 7376 // precision control | |
| 7377 const char* pc; | |
| 7378 switch (precision_control()) { | |
| 7379 case 0: pc = "24 bits "; break; | |
| 7380 case 1: pc = "reserved"; break; | |
| 7381 case 2: pc = "53 bits "; break; | |
| 7382 case 3: pc = "64 bits "; break; | |
| 7383 }; | |
| 7384 // flags | |
| 7385 char f[9]; | |
| 7386 f[0] = ' '; | |
| 7387 f[1] = ' '; | |
| 7388 f[2] = (precision ()) ? 'P' : 'p'; | |
| 7389 f[3] = (underflow ()) ? 'U' : 'u'; | |
| 7390 f[4] = (overflow ()) ? 'O' : 'o'; | |
| 7391 f[5] = (zero_divide ()) ? 'Z' : 'z'; | |
| 7392 f[6] = (denormalized()) ? 'D' : 'd'; | |
| 7393 f[7] = (invalid ()) ? 'I' : 'i'; | |
| 7394 f[8] = '\x0'; | |
| 7395 // output | |
| 7396 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc); | |
| 7397 } | |
| 7398 | |
| 7399 }; | |
| 7400 | |
| 7401 class StatusWord { | |
| 7402 public: | |
| 7403 int32_t _value; | |
| 7404 | |
| 7405 bool busy() const { return ((_value >> 15) & 1) != 0; } | |
| 7406 bool C3() const { return ((_value >> 14) & 1) != 0; } | |
| 7407 bool C2() const { return ((_value >> 10) & 1) != 0; } | |
| 7408 bool C1() const { return ((_value >> 9) & 1) != 0; } | |
| 7409 bool C0() const { return ((_value >> 8) & 1) != 0; } | |
| 7410 int top() const { return (_value >> 11) & 7 ; } | |
| 7411 bool error_status() const { return ((_value >> 7) & 1) != 0; } | |
| 7412 bool stack_fault() const { return ((_value >> 6) & 1) != 0; } | |
| 7413 bool precision() const { return ((_value >> 5) & 1) != 0; } | |
| 7414 bool underflow() const { return ((_value >> 4) & 1) != 0; } | |
| 7415 bool overflow() const { return ((_value >> 3) & 1) != 0; } | |
| 7416 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } | |
| 7417 bool denormalized() const { return ((_value >> 1) & 1) != 0; } | |
| 7418 bool invalid() const { return ((_value >> 0) & 1) != 0; } | |
| 7419 | |
| 7420 void print() const { | |
| 7421 // condition codes | |
| 7422 char c[5]; | |
| 7423 c[0] = (C3()) ? '3' : '-'; | |
| 7424 c[1] = (C2()) ? '2' : '-'; | |
| 7425 c[2] = (C1()) ? '1' : '-'; | |
| 7426 c[3] = (C0()) ? '0' : '-'; | |
| 7427 c[4] = '\x0'; | |
| 7428 // flags | |
| 7429 char f[9]; | |
| 7430 f[0] = (error_status()) ? 'E' : '-'; | |
| 7431 f[1] = (stack_fault ()) ? 'S' : '-'; | |
| 7432 f[2] = (precision ()) ? 'P' : '-'; | |
| 7433 f[3] = (underflow ()) ? 'U' : '-'; | |
| 7434 f[4] = (overflow ()) ? 'O' : '-'; | |
| 7435 f[5] = (zero_divide ()) ? 'Z' : '-'; | |
| 7436 f[6] = (denormalized()) ? 'D' : '-'; | |
| 7437 f[7] = (invalid ()) ? 'I' : '-'; | |
| 7438 f[8] = '\x0'; | |
| 7439 // output | |
| 7440 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top()); | |
| 7441 } | |
| 7442 | |
| 7443 }; | |
| 7444 | |
| 7445 class TagWord { | |
| 7446 public: | |
| 7447 int32_t _value; | |
| 7448 | |
| 7449 int tag_at(int i) const { return (_value >> (i*2)) & 3; } | |
| 7450 | |
| 7451 void print() const { | |
| 7452 printf("%04x", _value & 0xFFFF); | |
| 7453 } | |
| 7454 | |
| 7455 }; | |
| 7456 | |
| 7457 class FPU_Register { | |
| 7458 public: | |
| 7459 int32_t _m0; | |
| 7460 int32_t _m1; | |
| 7461 int16_t _ex; | |
| 7462 | |
| 7463 bool is_indefinite() const { | |
| 7464 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0; | |
| 7465 } | |
| 7466 | |
| 7467 void print() const { | |
| 7468 char sign = (_ex < 0) ? '-' : '+'; | |
| 7469 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " "; | |
| 7470 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind); | |
| 7471 }; | |
| 7472 | |
| 7473 }; | |
| 7474 | |
| 7475 class FPU_State { | |
| 7476 public: | |
| 7477 enum { | |
| 7478 register_size = 10, | |
| 7479 number_of_registers = 8, | |
| 7480 register_mask = 7 | |
| 7481 }; | |
| 7482 | |
| 7483 ControlWord _control_word; | |
| 7484 StatusWord _status_word; | |
| 7485 TagWord _tag_word; | |
| 7486 int32_t _error_offset; | |
| 7487 int32_t _error_selector; | |
| 7488 int32_t _data_offset; | |
| 7489 int32_t _data_selector; | |
| 7490 int8_t _register[register_size * number_of_registers]; | |
| 7491 | |
| 7492 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); } | |
| 7493 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; } | |
| 7494 | |
| 7495 const char* tag_as_string(int tag) const { | |
| 7496 switch (tag) { | |
| 7497 case 0: return "valid"; | |
| 7498 case 1: return "zero"; | |
| 7499 case 2: return "special"; | |
| 7500 case 3: return "empty"; | |
| 7501 } | |
| 7502 ShouldNotReachHere() | |
| 7503 return NULL; | |
| 7504 } | |
| 7505 | |
| 7506 void print() const { | |
| 7507 // print computation registers | |
| 7508 { int t = _status_word.top(); | |
| 7509 for (int i = 0; i < number_of_registers; i++) { | |
| 7510 int j = (i - t) & register_mask; | |
| 7511 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j); | |
| 7512 st(j)->print(); | |
| 7513 printf(" %s\n", tag_as_string(_tag_word.tag_at(i))); | |
| 7514 } | |
| 7515 } | |
| 7516 printf("\n"); | |
| 7517 // print control registers | |
| 7518 printf("ctrl = "); _control_word.print(); printf("\n"); | |
| 7519 printf("stat = "); _status_word .print(); printf("\n"); | |
| 7520 printf("tags = "); _tag_word .print(); printf("\n"); | |
| 7521 } | |
| 7522 | |
| 7523 }; | |
| 7524 | |
| 7525 class Flag_Register { | |
| 7526 public: | |
| 7527 int32_t _value; | |
| 7528 | |
| 7529 bool overflow() const { return ((_value >> 11) & 1) != 0; } | |
| 7530 bool direction() const { return ((_value >> 10) & 1) != 0; } | |
| 7531 bool sign() const { return ((_value >> 7) & 1) != 0; } | |
| 7532 bool zero() const { return ((_value >> 6) & 1) != 0; } | |
| 7533 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; } | |
| 7534 bool parity() const { return ((_value >> 2) & 1) != 0; } | |
| 7535 bool carry() const { return ((_value >> 0) & 1) != 0; } | |
| 7536 | |
| 7537 void print() const { | |
| 7538 // flags | |
| 7539 char f[8]; | |
| 7540 f[0] = (overflow ()) ? 'O' : '-'; | |
| 7541 f[1] = (direction ()) ? 'D' : '-'; | |
| 7542 f[2] = (sign ()) ? 'S' : '-'; | |
| 7543 f[3] = (zero ()) ? 'Z' : '-'; | |
| 7544 f[4] = (auxiliary_carry()) ? 'A' : '-'; | |
| 7545 f[5] = (parity ()) ? 'P' : '-'; | |
| 7546 f[6] = (carry ()) ? 'C' : '-'; | |
| 7547 f[7] = '\x0'; | |
| 7548 // output | |
| 7549 printf("%08x flags = %s", _value, f); | |
| 7550 } | |
| 7551 | |
| 7552 }; | |
| 7553 | |
| 7554 class IU_Register { | |
| 7555 public: | |
| 7556 int32_t _value; | |
| 7557 | |
| 7558 void print() const { | |
| 7559 printf("%08x %11d", _value, _value); | |
| 7560 } | |
| 7561 | |
| 7562 }; | |
| 7563 | |
| 7564 class IU_State { | |
| 7565 public: | |
| 7566 Flag_Register _eflags; | |
| 7567 IU_Register _rdi; | |
| 7568 IU_Register _rsi; | |
| 7569 IU_Register _rbp; | |
| 7570 IU_Register _rsp; | |
| 7571 IU_Register _rbx; | |
| 7572 IU_Register _rdx; | |
| 7573 IU_Register _rcx; | |
| 7574 IU_Register _rax; | |
| 7575 | |
| 7576 void print() const { | |
| 7577 // computation registers | |
| 7578 printf("rax, = "); _rax.print(); printf("\n"); | |
| 7579 printf("rbx, = "); _rbx.print(); printf("\n"); | |
| 7580 printf("rcx = "); _rcx.print(); printf("\n"); | |
| 7581 printf("rdx = "); _rdx.print(); printf("\n"); | |
| 7582 printf("rdi = "); _rdi.print(); printf("\n"); | |
| 7583 printf("rsi = "); _rsi.print(); printf("\n"); | |
| 7584 printf("rbp, = "); _rbp.print(); printf("\n"); | |
| 7585 printf("rsp = "); _rsp.print(); printf("\n"); | |
| 7586 printf("\n"); | |
| 7587 // control registers | |
| 7588 printf("flgs = "); _eflags.print(); printf("\n"); | |
| 7589 } | |
| 7590 }; | |
| 7591 | |
| 7592 | |
| 7593 class CPU_State { | |
| 7594 public: | |
| 7595 FPU_State _fpu_state; | |
| 7596 IU_State _iu_state; | |
| 7597 | |
| 7598 void print() const { | |
| 7599 printf("--------------------------------------------------\n"); | |
| 7600 _iu_state .print(); | |
| 7601 printf("\n"); | |
| 7602 _fpu_state.print(); | |
| 7603 printf("--------------------------------------------------\n"); | |
| 7604 } | |
| 7605 | |
| 7606 }; | |
| 7607 | |
| 7608 | |
| 7609 static void _print_CPU_state(CPU_State* state) { | |
| 7610 state->print(); | |
| 7611 }; | |
| 7612 | |
| 7613 | |
| 7614 void MacroAssembler::print_CPU_state() { | |
| 7615 push_CPU_state(); | |
| 304 | 7616 push(rsp); // pass CPU state |
| 0 | 7617 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state))); |
| 304 | 7618 addptr(rsp, wordSize); // discard argument |
| 0 | 7619 pop_CPU_state(); |
| 7620 } | |
| 7621 | |
| 7622 | |
| 7623 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) { | |
| 7624 static int counter = 0; | |
| 7625 FPU_State* fs = &state->_fpu_state; | |
| 7626 counter++; | |
| 7627 // For leaf calls, only verify that the top few elements remain empty. | |
| 7628 // We only need 1 empty at the top for C2 code. | |
| 7629 if( stack_depth < 0 ) { | |
| 7630 if( fs->tag_for_st(7) != 3 ) { | |
| 7631 printf("FPR7 not empty\n"); | |
| 7632 state->print(); | |
| 7633 assert(false, "error"); | |
| 7634 return false; | |
| 7635 } | |
| 7636 return true; // All other stack states do not matter | |
| 7637 } | |
| 7638 | |
| 7639 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std, | |
| 7640 "bad FPU control word"); | |
| 7641 | |
| 7642 // compute stack depth | |
| 7643 int i = 0; | |
| 7644 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++; | |
| 7645 int d = i; | |
| 7646 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++; | |
| 7647 // verify findings | |
| 7648 if (i != FPU_State::number_of_registers) { | |
| 7649 // stack not contiguous | |
| 7650 printf("%s: stack not contiguous at ST%d\n", s, i); | |
| 7651 state->print(); | |
| 7652 assert(false, "error"); | |
| 7653 return false; | |
| 7654 } | |
| 7655 // check if computed stack depth corresponds to expected stack depth | |
| 7656 if (stack_depth < 0) { | |
| 7657 // expected stack depth is -stack_depth or less | |
| 7658 if (d > -stack_depth) { | |
| 7659 // too many elements on the stack | |
| 7660 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d); | |
| 7661 state->print(); | |
| 7662 assert(false, "error"); | |
| 7663 return false; | |
| 7664 } | |
| 7665 } else { | |
| 7666 // expected stack depth is stack_depth | |
| 7667 if (d != stack_depth) { | |
| 7668 // wrong stack depth | |
| 7669 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d); | |
| 7670 state->print(); | |
| 7671 assert(false, "error"); | |
| 7672 return false; | |
| 7673 } | |
| 7674 } | |
| 7675 // everything is cool | |
| 7676 return true; | |
| 7677 } | |
| 7678 | |
| 7679 | |
| 7680 void MacroAssembler::verify_FPU(int stack_depth, const char* s) { | |
| 7681 if (!VerifyFPU) return; | |
| 7682 push_CPU_state(); | |
| 304 | 7683 push(rsp); // pass CPU state |
| 0 | 7684 ExternalAddress msg((address) s); |
| 7685 // pass message string s | |
| 7686 pushptr(msg.addr()); | |
| 304 | 7687 push(stack_depth); // pass stack depth |
| 0 | 7688 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU))); |
| 304 | 7689 addptr(rsp, 3 * wordSize); // discard arguments |
| 0 | 7690 // check for error |
| 7691 { Label L; | |
| 7692 testl(rax, rax); | |
| 7693 jcc(Assembler::notZero, L); | |
| 7694 int3(); // break if error condition | |
| 7695 bind(L); | |
| 7696 } | |
| 7697 pop_CPU_state(); | |
| 7698 } | |
| 7699 | |
| 304 | 7700 void MacroAssembler::load_klass(Register dst, Register src) { |
| 7701 #ifdef _LP64 | |
| 7702 if (UseCompressedOops) { | |
| 7703 movl(dst, Address(src, oopDesc::klass_offset_in_bytes())); | |
| 7704 decode_heap_oop_not_null(dst); | |
| 7705 } else | |
| 7706 #endif | |
| 7707 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes())); | |
| 7708 } | |
| 7709 | |
| 7710 void MacroAssembler::load_prototype_header(Register dst, Register src) { | |
| 7711 #ifdef _LP64 | |
| 7712 if (UseCompressedOops) { | |
| 7713 movl(dst, Address(src, oopDesc::klass_offset_in_bytes())); | |
| 7714 movq(dst, Address(r12_heapbase, dst, Address::times_8, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); | |
| 7715 } else | |
| 7716 #endif | |
| 7717 { | |
| 7718 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes())); | |
| 7719 movptr(dst, Address(dst, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); | |
| 7720 } | |
| 7721 } | |
| 7722 | |
| 7723 void MacroAssembler::store_klass(Register dst, Register src) { | |
| 7724 #ifdef _LP64 | |
| 7725 if (UseCompressedOops) { | |
| 7726 encode_heap_oop_not_null(src); | |
| 7727 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src); | |
| 7728 } else | |
| 7729 #endif | |
| 7730 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src); | |
| 7731 } | |
| 7732 | |
| 7733 #ifdef _LP64 | |
| 7734 void MacroAssembler::store_klass_gap(Register dst, Register src) { | |
| 7735 if (UseCompressedOops) { | |
| 7736 // Store to klass gap in destination | |
| 7737 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src); | |
| 7738 } | |
| 7739 } | |
| 7740 | |
| 7741 void MacroAssembler::load_heap_oop(Register dst, Address src) { | |
| 7742 if (UseCompressedOops) { | |
| 7743 movl(dst, src); | |
| 7744 decode_heap_oop(dst); | |
| 7745 } else { | |
| 7746 movq(dst, src); | |
| 7747 } | |
| 7748 } | |
| 7749 | |
| 7750 void MacroAssembler::store_heap_oop(Address dst, Register src) { | |
| 7751 if (UseCompressedOops) { | |
| 7752 assert(!dst.uses(src), "not enough registers"); | |
| 7753 encode_heap_oop(src); | |
| 7754 movl(dst, src); | |
| 7755 } else { | |
| 7756 movq(dst, src); | |
| 7757 } | |
| 7758 } | |
| 7759 | |
| 7760 // Algorithm must match oop.inline.hpp encode_heap_oop. | |
| 7761 void MacroAssembler::encode_heap_oop(Register r) { | |
| 7762 assert (UseCompressedOops, "should be compressed"); | |
| 0 | 7763 #ifdef ASSERT |
| 304 | 7764 if (CheckCompressedOops) { |
| 7765 Label ok; | |
| 7766 push(rscratch1); // cmpptr trashes rscratch1 | |
| 7767 cmpptr(r12_heapbase, ExternalAddress((address)Universe::heap_base_addr())); | |
| 7768 jcc(Assembler::equal, ok); | |
| 7769 stop("MacroAssembler::encode_heap_oop: heap base corrupted?"); | |
| 0 | 7770 bind(ok); |
| 304 | 7771 pop(rscratch1); |
| 0 | 7772 } |
| 7773 #endif | |
| 304 | 7774 verify_oop(r, "broken oop in encode_heap_oop"); |
| 7775 testq(r, r); | |
| 7776 cmovq(Assembler::equal, r, r12_heapbase); | |
| 7777 subq(r, r12_heapbase); | |
| 7778 shrq(r, LogMinObjAlignmentInBytes); | |
| 7779 } | |
| 7780 | |
| 7781 void MacroAssembler::encode_heap_oop_not_null(Register r) { | |
| 7782 assert (UseCompressedOops, "should be compressed"); | |
| 0 | 7783 #ifdef ASSERT |
| 304 | 7784 if (CheckCompressedOops) { |
| 0 | 7785 Label ok; |
| 304 | 7786 testq(r, r); |
| 7787 jcc(Assembler::notEqual, ok); | |
| 7788 stop("null oop passed to encode_heap_oop_not_null"); | |
| 0 | 7789 bind(ok); |
| 304 | 7790 } |
| 7791 #endif | |
| 7792 verify_oop(r, "broken oop in encode_heap_oop_not_null"); | |
| 7793 subq(r, r12_heapbase); | |
| 7794 shrq(r, LogMinObjAlignmentInBytes); | |
| 7795 } | |
| 7796 | |
| 7797 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) { | |
| 7798 assert (UseCompressedOops, "should be compressed"); | |
| 7799 #ifdef ASSERT | |
| 7800 if (CheckCompressedOops) { | |
| 7801 Label ok; | |
| 7802 testq(src, src); | |
| 7803 jcc(Assembler::notEqual, ok); | |
| 7804 stop("null oop passed to encode_heap_oop_not_null2"); | |
| 7805 bind(ok); | |
| 0 | 7806 } |
| 7807 #endif | |
| 304 | 7808 verify_oop(src, "broken oop in encode_heap_oop_not_null2"); |
| 7809 if (dst != src) { | |
| 7810 movq(dst, src); | |
| 7811 } | |
| 7812 subq(dst, r12_heapbase); | |
| 7813 shrq(dst, LogMinObjAlignmentInBytes); | |
| 7814 } | |
| 7815 | |
| 7816 void MacroAssembler::decode_heap_oop(Register r) { | |
| 7817 assert (UseCompressedOops, "should be compressed"); | |
| 7818 #ifdef ASSERT | |
| 7819 if (CheckCompressedOops) { | |
| 7820 Label ok; | |
| 7821 push(rscratch1); | |
| 7822 cmpptr(r12_heapbase, | |
| 7823 ExternalAddress((address)Universe::heap_base_addr())); | |
| 7824 jcc(Assembler::equal, ok); | |
| 7825 stop("MacroAssembler::decode_heap_oop: heap base corrupted?"); | |
| 7826 bind(ok); | |
| 7827 pop(rscratch1); | |
| 7828 } | |
| 7829 #endif | |
| 7830 | |
| 7831 Label done; | |
| 7832 shlq(r, LogMinObjAlignmentInBytes); | |
| 7833 jccb(Assembler::equal, done); | |
| 7834 addq(r, r12_heapbase); | |
| 7835 #if 0 | |
| 7836 // alternate decoding probably a wash. | |
| 7837 testq(r, r); | |
| 7838 jccb(Assembler::equal, done); | |
| 7839 leaq(r, Address(r12_heapbase, r, Address::times_8, 0)); | |
| 7840 #endif | |
| 7841 bind(done); | |
| 7842 verify_oop(r, "broken oop in decode_heap_oop"); | |
| 7843 } | |
| 7844 | |
| 7845 void MacroAssembler::decode_heap_oop_not_null(Register r) { | |
| 7846 assert (UseCompressedOops, "should only be used for compressed headers"); | |
| 7847 // Cannot assert, unverified entry point counts instructions (see .ad file) | |
| 7848 // vtableStubs also counts instructions in pd_code_size_limit. | |
| 7849 // Also do not verify_oop as this is called by verify_oop. | |
| 7850 assert(Address::times_8 == LogMinObjAlignmentInBytes, "decode alg wrong"); | |
| 7851 leaq(r, Address(r12_heapbase, r, Address::times_8, 0)); | |
| 7852 } | |
| 7853 | |
| 7854 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) { | |
| 7855 assert (UseCompressedOops, "should only be used for compressed headers"); | |
| 7856 // Cannot assert, unverified entry point counts instructions (see .ad file) | |
| 7857 // vtableStubs also counts instructions in pd_code_size_limit. | |
| 7858 // Also do not verify_oop as this is called by verify_oop. | |
| 7859 assert(Address::times_8 == LogMinObjAlignmentInBytes, "decode alg wrong"); | |
| 7860 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0)); | |
| 7861 } | |
| 7862 | |
| 7863 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) { | |
| 7864 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder"); | |
| 7865 int oop_index = oop_recorder()->find_index(obj); | |
| 7866 RelocationHolder rspec = oop_Relocation::spec(oop_index); | |
| 7867 mov_literal32(dst, oop_index, rspec, narrow_oop_operand); | |
| 7868 } | |
| 7869 | |
| 7870 void MacroAssembler::reinit_heapbase() { | |
| 7871 if (UseCompressedOops) { | |
| 7872 movptr(r12_heapbase, ExternalAddress((address)Universe::heap_base_addr())); | |
| 7873 } | |
| 7874 } | |
| 7875 #endif // _LP64 | |
| 0 | 7876 |
| 7877 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) { | |
| 7878 switch (cond) { | |
| 7879 // Note some conditions are synonyms for others | |
| 7880 case Assembler::zero: return Assembler::notZero; | |
| 7881 case Assembler::notZero: return Assembler::zero; | |
| 7882 case Assembler::less: return Assembler::greaterEqual; | |
| 7883 case Assembler::lessEqual: return Assembler::greater; | |
| 7884 case Assembler::greater: return Assembler::lessEqual; | |
| 7885 case Assembler::greaterEqual: return Assembler::less; | |
| 7886 case Assembler::below: return Assembler::aboveEqual; | |
| 7887 case Assembler::belowEqual: return Assembler::above; | |
| 7888 case Assembler::above: return Assembler::belowEqual; | |
| 7889 case Assembler::aboveEqual: return Assembler::below; | |
| 7890 case Assembler::overflow: return Assembler::noOverflow; | |
| 7891 case Assembler::noOverflow: return Assembler::overflow; | |
| 7892 case Assembler::negative: return Assembler::positive; | |
| 7893 case Assembler::positive: return Assembler::negative; | |
| 7894 case Assembler::parity: return Assembler::noParity; | |
| 7895 case Assembler::noParity: return Assembler::parity; | |
| 7896 } | |
| 7897 ShouldNotReachHere(); return Assembler::overflow; | |
| 7898 } | |
| 7899 | |
| 7900 SkipIfEqual::SkipIfEqual( | |
| 7901 MacroAssembler* masm, const bool* flag_addr, bool value) { | |
| 7902 _masm = masm; | |
| 7903 _masm->cmp8(ExternalAddress((address)flag_addr), value); | |
| 7904 _masm->jcc(Assembler::equal, _label); | |
| 7905 } | |
| 7906 | |
| 7907 SkipIfEqual::~SkipIfEqual() { | |
| 7908 _masm->bind(_label); | |
| 7909 } |