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comparison graal/com.oracle.jvmci.asm.amd64.test/src/com/oracle/jvmci/asm/amd64/test/BitOpsTest.java @ 21709:3c17c0c41a6b

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moved com.oracle.asm.**.test to JVMCI namespace (JBS:GRAAL-53)
author Doug Simon <doug.simon@oracle.com>
date Wed, 03 Jun 2015 18:33:23 +0200
parents graal/com.oracle.graal.asm.amd64.test/src/com/oracle/graal/asm/amd64/test/BitOpsTest.java@6df25b1418be
children
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21708:6df25b1418be 21709:3c17c0c41a6b
1 /*
2 * Copyright (c) 2013, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 */
23
24 package com.oracle.jvmci.asm.amd64.test;
25
26 import com.oracle.jvmci.amd64.*;
27 import com.oracle.jvmci.amd64.AMD64.*;
28 import com.oracle.jvmci.asm.amd64.*;
29 import com.oracle.jvmci.asm.test.*;
30 import com.oracle.jvmci.code.RegisterConfig;
31 import com.oracle.jvmci.code.TargetDescription;
32 import com.oracle.jvmci.code.Register;
33 import com.oracle.jvmci.code.CallingConvention;
34 import com.oracle.jvmci.code.CompilationResult;
35 import com.oracle.jvmci.meta.Kind;
36
37 import static com.oracle.jvmci.asm.amd64.AMD64Assembler.AMD64RMOp.*;
38 import static com.oracle.jvmci.asm.amd64.AMD64Assembler.OperandSize.*;
39 import static com.oracle.jvmci.code.ValueUtil.*;
40 import static com.oracle.jvmci.common.UnsafeAccess.*;
41 import static org.junit.Assume.*;
42
43 import java.lang.reflect.*;
44 import java.util.*;
45
46 import org.junit.*;
47
48 public class BitOpsTest extends AssemblerTest {
49 private static boolean lzcntSupported;
50 private static boolean tzcntSupported;
51
52 @Before
53 public void checkAMD64() {
54 assumeTrue("skipping AMD64 specific test", codeCache.getTarget().arch instanceof AMD64);
55 EnumSet<CPUFeature> features = ((AMD64) codeCache.getTarget().arch).getFeatures();
56 lzcntSupported = features.contains(CPUFeature.LZCNT);
57 tzcntSupported = features.contains(CPUFeature.BMI1);
58 }
59
60 @Test
61 public void lzcntlTest() {
62 if (lzcntSupported) {
63 CodeGenTest test = new CodeGenTest() {
64
65 @Override
66 public byte[] generateCode(CompilationResult compResult, TargetDescription target, RegisterConfig registerConfig, CallingConvention cc) {
67 AMD64Assembler asm = new AMD64Assembler(target, registerConfig);
68 Register ret = registerConfig.getReturnRegister(Kind.Int);
69 Register arg = asRegister(cc.getArgument(0));
70 LZCNT.emit(asm, DWORD, ret, arg);
71 asm.ret(0);
72 return asm.close(true);
73 }
74 };
75 assertReturn("intStub", test, 31, 1);
76 }
77 }
78
79 @Test
80 public void lzcntlMemTest() {
81 if (lzcntSupported) {
82 CodeGenTest test = new CodeGenTest() {
83
84 @Override
85 public byte[] generateCode(CompilationResult compResult, TargetDescription target, RegisterConfig registerConfig, CallingConvention cc) {
86 AMD64Assembler asm = new AMD64Assembler(target, registerConfig);
87 Register ret = registerConfig.getReturnRegister(Kind.Int);
88 try {
89 Field f = IntField.class.getDeclaredField("x");
90 AMD64Address arg = new AMD64Address(asRegister(cc.getArgument(0)), (int) unsafe.objectFieldOffset(f));
91 LZCNT.emit(asm, DWORD, ret, arg);
92 asm.ret(0);
93 return asm.close(true);
94 } catch (Exception e) {
95 throw new RuntimeException("exception while trying to generate field access:", e);
96 }
97 }
98 };
99 assertReturn("intFieldStub", test, 31, new IntField(1));
100 }
101 }
102
103 @Test
104 public void lzcntqTest() {
105 if (lzcntSupported) {
106 CodeGenTest test = new CodeGenTest() {
107
108 @Override
109 public byte[] generateCode(CompilationResult compResult, TargetDescription target, RegisterConfig registerConfig, CallingConvention cc) {
110 AMD64Assembler asm = new AMD64Assembler(target, registerConfig);
111 Register ret = registerConfig.getReturnRegister(Kind.Int);
112 Register arg = asRegister(cc.getArgument(0));
113 LZCNT.emit(asm, QWORD, ret, arg);
114 asm.ret(0);
115 return asm.close(true);
116 }
117 };
118 assertReturn("longStub", test, 63, 1L);
119 }
120 }
121
122 @Test
123 public void lzcntqMemTest() {
124 if (lzcntSupported) {
125 CodeGenTest test = new CodeGenTest() {
126
127 @Override
128 public byte[] generateCode(CompilationResult compResult, TargetDescription target, RegisterConfig registerConfig, CallingConvention cc) {
129 AMD64Assembler asm = new AMD64Assembler(target, registerConfig);
130 Register ret = registerConfig.getReturnRegister(Kind.Int);
131 try {
132 Field f = LongField.class.getDeclaredField("x");
133 AMD64Address arg = new AMD64Address(asRegister(cc.getArgument(0)), (int) unsafe.objectFieldOffset(f));
134 LZCNT.emit(asm, QWORD, ret, arg);
135 asm.ret(0);
136 return asm.close(true);
137 } catch (Exception e) {
138 throw new RuntimeException("exception while trying to generate field access:", e);
139 }
140 }
141 };
142 assertReturn("longFieldStub", test, 63, new LongField(1));
143 }
144 }
145
146 @Test
147 public void tzcntlTest() {
148 if (tzcntSupported) {
149 CodeGenTest test = new CodeGenTest() {
150
151 @Override
152 public byte[] generateCode(CompilationResult compResult, TargetDescription target, RegisterConfig registerConfig, CallingConvention cc) {
153 AMD64Assembler asm = new AMD64Assembler(target, registerConfig);
154 Register ret = registerConfig.getReturnRegister(Kind.Int);
155 Register arg = asRegister(cc.getArgument(0));
156 TZCNT.emit(asm, DWORD, ret, arg);
157 asm.ret(0);
158 return asm.close(true);
159 }
160 };
161 assertReturn("intStub", test, 31, 0x8000_0000);
162 }
163 }
164
165 @Test
166 public void tzcntlMemTest() {
167 if (tzcntSupported) {
168 CodeGenTest test = new CodeGenTest() {
169
170 @Override
171 public byte[] generateCode(CompilationResult compResult, TargetDescription target, RegisterConfig registerConfig, CallingConvention cc) {
172 AMD64Assembler asm = new AMD64Assembler(target, registerConfig);
173 Register ret = registerConfig.getReturnRegister(Kind.Int);
174 try {
175 Field f = IntField.class.getDeclaredField("x");
176 AMD64Address arg = new AMD64Address(asRegister(cc.getArgument(0)), (int) unsafe.objectFieldOffset(f));
177 TZCNT.emit(asm, DWORD, ret, arg);
178 asm.ret(0);
179 return asm.close(true);
180 } catch (Exception e) {
181 throw new RuntimeException("exception while trying to generate field access:", e);
182 }
183 }
184 };
185 assertReturn("intFieldStub", test, 31, new IntField(0x8000_0000));
186 }
187 }
188
189 @Test
190 public void tzcntqTest() {
191 if (tzcntSupported) {
192 CodeGenTest test = new CodeGenTest() {
193
194 @Override
195 public byte[] generateCode(CompilationResult compResult, TargetDescription target, RegisterConfig registerConfig, CallingConvention cc) {
196 AMD64Assembler asm = new AMD64Assembler(target, registerConfig);
197 Register ret = registerConfig.getReturnRegister(Kind.Int);
198 Register arg = asRegister(cc.getArgument(0));
199 TZCNT.emit(asm, QWORD, ret, arg);
200 asm.ret(0);
201 return asm.close(true);
202 }
203 };
204 assertReturn("longStub", test, 63, 0x8000_0000_0000_0000L);
205 }
206 }
207
208 @Test
209 public void tzcntqMemTest() {
210 if (tzcntSupported) {
211 CodeGenTest test = new CodeGenTest() {
212
213 @Override
214 public byte[] generateCode(CompilationResult compResult, TargetDescription target, RegisterConfig registerConfig, CallingConvention cc) {
215 AMD64Assembler asm = new AMD64Assembler(target, registerConfig);
216 Register ret = registerConfig.getReturnRegister(Kind.Int);
217 try {
218 Field f = LongField.class.getDeclaredField("x");
219 AMD64Address arg = new AMD64Address(asRegister(cc.getArgument(0)), (int) unsafe.objectFieldOffset(f));
220 TZCNT.emit(asm, QWORD, ret, arg);
221 asm.ret(0);
222 return asm.close(true);
223 } catch (Exception e) {
224 throw new RuntimeException("exception while trying to generate field access:", e);
225 }
226 }
227 };
228 assertReturn("longFieldStub", test, 63, new LongField(0x8000_0000_0000_0000L));
229 }
230 }
231
232 @SuppressWarnings("unused")
233 public static int intStub(int arg) {
234 return 0;
235 }
236
237 @SuppressWarnings("unused")
238 public static int longStub(long arg) {
239 return 0;
240 }
241
242 public static class IntField {
243 public int x;
244
245 IntField(int x) {
246 this.x = x;
247 }
248 }
249
250 public static class LongField {
251 public long x;
252
253 LongField(long x) {
254 this.x = x;
255 }
256 }
257
258 @SuppressWarnings("unused")
259 public static int intFieldStub(IntField arg) {
260 return 0;
261 }
262
263 @SuppressWarnings("unused")
264 public static int longFieldStub(LongField arg) {
265 return 0;
266 }
267 }