Mercurial > hg > truffle
annotate graal/com.oracle.jvmci.asm.amd64.test/src/com/oracle/jvmci/asm/amd64/test/BitOpsTest.java @ 21709:3c17c0c41a6b
moved com.oracle.asm.**.test to JVMCI namespace (JBS:GRAAL-53)
author | Doug Simon <doug.simon@oracle.com> |
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date | Wed, 03 Jun 2015 18:33:23 +0200 |
parents | graal/com.oracle.graal.asm.amd64.test/src/com/oracle/graal/asm/amd64/test/BitOpsTest.java@6df25b1418be |
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1 /* |
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2 * Copyright (c) 2013, 2015, Oracle and/or its affiliates. All rights reserved. |
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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4 * |
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5 * This code is free software; you can redistribute it and/or modify it |
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6 * under the terms of the GNU General Public License version 2 only, as |
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7 * published by the Free Software Foundation. |
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8 * |
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9 * This code is distributed in the hope that it will be useful, but WITHOUT |
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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12 * version 2 for more details (a copy is included in the LICENSE file that |
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13 * accompanied this code). |
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14 * |
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15 * You should have received a copy of the GNU General Public License version |
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16 * 2 along with this work; if not, write to the Free Software Foundation, |
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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18 * |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
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22 */ |
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23 |
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24 package com.oracle.jvmci.asm.amd64.test; |
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25 |
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26 import com.oracle.jvmci.amd64.*; |
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27 import com.oracle.jvmci.amd64.AMD64.*; |
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28 import com.oracle.jvmci.asm.amd64.*; |
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29 import com.oracle.jvmci.asm.test.*; |
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30 import com.oracle.jvmci.code.RegisterConfig; |
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31 import com.oracle.jvmci.code.TargetDescription; |
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32 import com.oracle.jvmci.code.Register; |
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33 import com.oracle.jvmci.code.CallingConvention; |
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34 import com.oracle.jvmci.code.CompilationResult; |
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35 import com.oracle.jvmci.meta.Kind; |
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36 |
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37 import static com.oracle.jvmci.asm.amd64.AMD64Assembler.AMD64RMOp.*; |
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38 import static com.oracle.jvmci.asm.amd64.AMD64Assembler.OperandSize.*; |
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39 import static com.oracle.jvmci.code.ValueUtil.*; |
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40 import static com.oracle.jvmci.common.UnsafeAccess.*; |
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41 import static org.junit.Assume.*; |
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42 |
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43 import java.lang.reflect.*; |
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44 import java.util.*; |
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45 |
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46 import org.junit.*; |
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47 |
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48 public class BitOpsTest extends AssemblerTest { |
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49 private static boolean lzcntSupported; |
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50 private static boolean tzcntSupported; |
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51 |
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52 @Before |
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53 public void checkAMD64() { |
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54 assumeTrue("skipping AMD64 specific test", codeCache.getTarget().arch instanceof AMD64); |
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55 EnumSet<CPUFeature> features = ((AMD64) codeCache.getTarget().arch).getFeatures(); |
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56 lzcntSupported = features.contains(CPUFeature.LZCNT); |
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57 tzcntSupported = features.contains(CPUFeature.BMI1); |
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58 } |
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59 |
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60 @Test |
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61 public void lzcntlTest() { |
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62 if (lzcntSupported) { |
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63 CodeGenTest test = new CodeGenTest() { |
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64 |
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65 @Override |
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66 public byte[] generateCode(CompilationResult compResult, TargetDescription target, RegisterConfig registerConfig, CallingConvention cc) { |
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67 AMD64Assembler asm = new AMD64Assembler(target, registerConfig); |
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68 Register ret = registerConfig.getReturnRegister(Kind.Int); |
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69 Register arg = asRegister(cc.getArgument(0)); |
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70 LZCNT.emit(asm, DWORD, ret, arg); |
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71 asm.ret(0); |
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72 return asm.close(true); |
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73 } |
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74 }; |
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75 assertReturn("intStub", test, 31, 1); |
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76 } |
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77 } |
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78 |
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79 @Test |
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80 public void lzcntlMemTest() { |
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81 if (lzcntSupported) { |
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82 CodeGenTest test = new CodeGenTest() { |
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83 |
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84 @Override |
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85 public byte[] generateCode(CompilationResult compResult, TargetDescription target, RegisterConfig registerConfig, CallingConvention cc) { |
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86 AMD64Assembler asm = new AMD64Assembler(target, registerConfig); |
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87 Register ret = registerConfig.getReturnRegister(Kind.Int); |
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88 try { |
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89 Field f = IntField.class.getDeclaredField("x"); |
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90 AMD64Address arg = new AMD64Address(asRegister(cc.getArgument(0)), (int) unsafe.objectFieldOffset(f)); |
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91 LZCNT.emit(asm, DWORD, ret, arg); |
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92 asm.ret(0); |
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93 return asm.close(true); |
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94 } catch (Exception e) { |
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95 throw new RuntimeException("exception while trying to generate field access:", e); |
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96 } |
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97 } |
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98 }; |
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99 assertReturn("intFieldStub", test, 31, new IntField(1)); |
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100 } |
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101 } |
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102 |
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103 @Test |
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104 public void lzcntqTest() { |
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105 if (lzcntSupported) { |
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106 CodeGenTest test = new CodeGenTest() { |
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107 |
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108 @Override |
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109 public byte[] generateCode(CompilationResult compResult, TargetDescription target, RegisterConfig registerConfig, CallingConvention cc) { |
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110 AMD64Assembler asm = new AMD64Assembler(target, registerConfig); |
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111 Register ret = registerConfig.getReturnRegister(Kind.Int); |
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112 Register arg = asRegister(cc.getArgument(0)); |
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113 LZCNT.emit(asm, QWORD, ret, arg); |
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114 asm.ret(0); |
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115 return asm.close(true); |
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116 } |
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117 }; |
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118 assertReturn("longStub", test, 63, 1L); |
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119 } |
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120 } |
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121 |
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122 @Test |
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123 public void lzcntqMemTest() { |
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124 if (lzcntSupported) { |
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125 CodeGenTest test = new CodeGenTest() { |
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126 |
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127 @Override |
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128 public byte[] generateCode(CompilationResult compResult, TargetDescription target, RegisterConfig registerConfig, CallingConvention cc) { |
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129 AMD64Assembler asm = new AMD64Assembler(target, registerConfig); |
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130 Register ret = registerConfig.getReturnRegister(Kind.Int); |
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131 try { |
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132 Field f = LongField.class.getDeclaredField("x"); |
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133 AMD64Address arg = new AMD64Address(asRegister(cc.getArgument(0)), (int) unsafe.objectFieldOffset(f)); |
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134 LZCNT.emit(asm, QWORD, ret, arg); |
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135 asm.ret(0); |
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136 return asm.close(true); |
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137 } catch (Exception e) { |
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138 throw new RuntimeException("exception while trying to generate field access:", e); |
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139 } |
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140 } |
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141 }; |
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142 assertReturn("longFieldStub", test, 63, new LongField(1)); |
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143 } |
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144 } |
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145 |
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146 @Test |
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147 public void tzcntlTest() { |
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148 if (tzcntSupported) { |
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149 CodeGenTest test = new CodeGenTest() { |
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150 |
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151 @Override |
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152 public byte[] generateCode(CompilationResult compResult, TargetDescription target, RegisterConfig registerConfig, CallingConvention cc) { |
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153 AMD64Assembler asm = new AMD64Assembler(target, registerConfig); |
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154 Register ret = registerConfig.getReturnRegister(Kind.Int); |
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155 Register arg = asRegister(cc.getArgument(0)); |
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156 TZCNT.emit(asm, DWORD, ret, arg); |
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157 asm.ret(0); |
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158 return asm.close(true); |
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159 } |
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160 }; |
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161 assertReturn("intStub", test, 31, 0x8000_0000); |
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162 } |
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163 } |
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164 |
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165 @Test |
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166 public void tzcntlMemTest() { |
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167 if (tzcntSupported) { |
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168 CodeGenTest test = new CodeGenTest() { |
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169 |
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170 @Override |
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171 public byte[] generateCode(CompilationResult compResult, TargetDescription target, RegisterConfig registerConfig, CallingConvention cc) { |
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172 AMD64Assembler asm = new AMD64Assembler(target, registerConfig); |
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173 Register ret = registerConfig.getReturnRegister(Kind.Int); |
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174 try { |
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175 Field f = IntField.class.getDeclaredField("x"); |
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176 AMD64Address arg = new AMD64Address(asRegister(cc.getArgument(0)), (int) unsafe.objectFieldOffset(f)); |
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177 TZCNT.emit(asm, DWORD, ret, arg); |
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178 asm.ret(0); |
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179 return asm.close(true); |
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180 } catch (Exception e) { |
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181 throw new RuntimeException("exception while trying to generate field access:", e); |
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182 } |
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183 } |
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184 }; |
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185 assertReturn("intFieldStub", test, 31, new IntField(0x8000_0000)); |
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186 } |
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187 } |
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188 |
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189 @Test |
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190 public void tzcntqTest() { |
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191 if (tzcntSupported) { |
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192 CodeGenTest test = new CodeGenTest() { |
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193 |
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194 @Override |
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195 public byte[] generateCode(CompilationResult compResult, TargetDescription target, RegisterConfig registerConfig, CallingConvention cc) { |
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196 AMD64Assembler asm = new AMD64Assembler(target, registerConfig); |
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197 Register ret = registerConfig.getReturnRegister(Kind.Int); |
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198 Register arg = asRegister(cc.getArgument(0)); |
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199 TZCNT.emit(asm, QWORD, ret, arg); |
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200 asm.ret(0); |
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201 return asm.close(true); |
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202 } |
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203 }; |
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|
204 assertReturn("longStub", test, 63, 0x8000_0000_0000_0000L); |
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205 } |
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206 } |
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207 |
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208 @Test |
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209 public void tzcntqMemTest() { |
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210 if (tzcntSupported) { |
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211 CodeGenTest test = new CodeGenTest() { |
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212 |
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213 @Override |
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214 public byte[] generateCode(CompilationResult compResult, TargetDescription target, RegisterConfig registerConfig, CallingConvention cc) { |
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215 AMD64Assembler asm = new AMD64Assembler(target, registerConfig); |
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216 Register ret = registerConfig.getReturnRegister(Kind.Int); |
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217 try { |
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218 Field f = LongField.class.getDeclaredField("x"); |
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219 AMD64Address arg = new AMD64Address(asRegister(cc.getArgument(0)), (int) unsafe.objectFieldOffset(f)); |
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220 TZCNT.emit(asm, QWORD, ret, arg); |
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221 asm.ret(0); |
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222 return asm.close(true); |
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223 } catch (Exception e) { |
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224 throw new RuntimeException("exception while trying to generate field access:", e); |
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225 } |
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226 } |
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227 }; |
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228 assertReturn("longFieldStub", test, 63, new LongField(0x8000_0000_0000_0000L)); |
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229 } |
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230 } |
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231 |
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232 @SuppressWarnings("unused") |
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233 public static int intStub(int arg) { |
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234 return 0; |
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235 } |
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236 |
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237 @SuppressWarnings("unused") |
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238 public static int longStub(long arg) { |
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239 return 0; |
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240 } |
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241 |
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242 public static class IntField { |
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243 public int x; |
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244 |
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245 IntField(int x) { |
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246 this.x = x; |
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247 } |
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248 } |
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249 |
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250 public static class LongField { |
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251 public long x; |
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252 |
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253 LongField(long x) { |
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254 this.x = x; |
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255 } |
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256 } |
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257 |
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258 @SuppressWarnings("unused") |
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259 public static int intFieldStub(IntField arg) { |
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260 return 0; |
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261 } |
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262 |
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263 @SuppressWarnings("unused") |
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264 public static int longFieldStub(LongField arg) { |
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265 return 0; |
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266 } |
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267 } |