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comparison src/cpu/sparc/vm/assembler_sparc.hpp @ 2029:6ce496c8fc07

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Merge
author coleenp
date Thu, 16 Dec 2010 09:31:55 -0500
parents 2f644f85485d
children 7737fa7ec2b5 b1a2afa37ec4
comparison
equal deleted inserted replaced
2028:450ece4d8a10 2029:6ce496c8fc07
1619 1619
1620 // pp 230 1620 // pp 230
1621 1621
1622 void sub( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | rs2(s2) ); } 1622 void sub( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | rs2(s2) ); }
1623 void sub( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1623 void sub( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1624
1625 // Note: offset is added to s2.
1626 inline void sub(Register s1, RegisterOrConstant s2, Register d, int offset = 0);
1627
1624 void subcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | rs2(s2) ); } 1628 void subcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | rs2(s2) ); }
1625 void subcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1629 void subcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1626 void subc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | rs2(s2) ); } 1630 void subc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | rs2(s2) ); }
1627 void subc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1631 void subc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1628 void subccc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } 1632 void subccc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1796 MacroAssembler* delayed() { Assembler::delayed(); return this; } 1800 MacroAssembler* delayed() { Assembler::delayed(); return this; }
1797 1801
1798 // branches that use right instruction for v8 vs. v9 1802 // branches that use right instruction for v8 vs. v9
1799 inline void br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); 1803 inline void br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1800 inline void br( Condition c, bool a, Predict p, Label& L ); 1804 inline void br( Condition c, bool a, Predict p, Label& L );
1805
1801 inline void fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); 1806 inline void fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1802 inline void fb( Condition c, bool a, Predict p, Label& L ); 1807 inline void fb( Condition c, bool a, Predict p, Label& L );
1803 1808
1804 // compares register with zero and branches (V9 and V8 instructions) 1809 // compares register with zero and branches (V9 and V8 instructions)
1805 void br_zero( Condition c, bool a, Predict p, Register s1, Label& L); 1810 void br_zero( Condition c, bool a, Predict p, Register s1, Label& L);
1891 void set(intptr_t value, Register d); 1896 void set(intptr_t value, Register d);
1892 void set(address addr, Register d, RelocationHolder const& rspec); 1897 void set(address addr, Register d, RelocationHolder const& rspec);
1893 void patchable_set(const AddressLiteral& addrlit, Register d); 1898 void patchable_set(const AddressLiteral& addrlit, Register d);
1894 void patchable_set(intptr_t value, Register d); 1899 void patchable_set(intptr_t value, Register d);
1895 void set64(jlong value, Register d, Register tmp); 1900 void set64(jlong value, Register d, Register tmp);
1901
1902 // Compute size of set64.
1903 static int size_of_set64(jlong value);
1896 1904
1897 // sign-extend 32 to 64 1905 // sign-extend 32 to 64
1898 inline void signx( Register s, Register d ) { sra( s, G0, d); } 1906 inline void signx( Register s, Register d ) { sra( s, G0, d); }
1899 inline void signx( Register d ) { sra( d, G0, d); } 1907 inline void signx( Register d ) { sra( d, G0, d); }
1900 1908