--- a/src/cpu/sparc/vm/assembler_sparc.hpp	Wed Dec 15 08:03:54 2010 -0800
+++ b/src/cpu/sparc/vm/assembler_sparc.hpp	Thu Dec 16 09:31:55 2010 -0500
@@ -1621,6 +1621,10 @@
 
   void sub(    Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3              ) | rs1(s1) | rs2(s2) ); }
   void sub(    Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3              ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
+
+  // Note: offset is added to s2.
+  inline void sub(Register s1, RegisterOrConstant s2, Register d, int offset = 0);
+
   void subcc(  Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | rs2(s2) ); }
   void subcc(  Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
   void subc(   Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3             ) | rs1(s1) | rs2(s2) ); }
@@ -1798,6 +1802,7 @@
   // branches that use right instruction for v8 vs. v9
   inline void br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
   inline void br( Condition c, bool a, Predict p, Label& L );
+
   inline void fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
   inline void fb( Condition c, bool a, Predict p, Label& L );
 
@@ -1894,6 +1899,9 @@
   void patchable_set(intptr_t value, Register d);
   void set64(jlong value, Register d, Register tmp);
 
+  // Compute size of set64.
+  static int size_of_set64(jlong value);
+
   // sign-extend 32 to 64
   inline void signx( Register s, Register d ) { sra( s, G0, d); }
   inline void signx( Register d )             { sra( d, G0, d); }