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comparison src/cpu/sparc/vm/vm_version_sparc.hpp @ 20804:7848fc12602b

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Merge with jdk8u40-b25
author Gilles Duboscq <gilles.m.duboscq@oracle.com>
date Tue, 07 Apr 2015 14:58:49 +0200
parents 52b4284cb496 d635fd1ac81c
children
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equal deleted inserted replaced
20184:84105dcdb05b 20804:7848fc12602b
1 /* 1 /*
2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. 2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 * 4 *
5 * This code is free software; you can redistribute it and/or modify it 5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as 6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation. 7 * published by the Free Software Foundation.
49 sparc64_family = 14, 49 sparc64_family = 14,
50 M_family = 15, 50 M_family = 15,
51 T_family = 16, 51 T_family = 16,
52 T1_model = 17, 52 T1_model = 17,
53 sparc5_instructions = 18, 53 sparc5_instructions = 18,
54 aes_instructions = 19 54 aes_instructions = 19,
55 sha1_instruction = 20,
56 sha256_instruction = 21,
57 sha512_instruction = 22
55 }; 58 };
56 59
57 enum Feature_Flag_Set { 60 enum Feature_Flag_Set {
58 unknown_m = 0, 61 unknown_m = 0,
59 all_features_m = -1, 62 all_features_m = -1,
76 M_family_m = 1 << M_family, 79 M_family_m = 1 << M_family,
77 T_family_m = 1 << T_family, 80 T_family_m = 1 << T_family,
78 T1_model_m = 1 << T1_model, 81 T1_model_m = 1 << T1_model,
79 sparc5_instructions_m = 1 << sparc5_instructions, 82 sparc5_instructions_m = 1 << sparc5_instructions,
80 aes_instructions_m = 1 << aes_instructions, 83 aes_instructions_m = 1 << aes_instructions,
84 sha1_instruction_m = 1 << sha1_instruction,
85 sha256_instruction_m = 1 << sha256_instruction,
86 sha512_instruction_m = 1 << sha512_instruction,
81 87
82 generic_v8_m = v8_instructions_m | hardware_mul32_m | hardware_div32_m | hardware_fsmuld_m, 88 generic_v8_m = v8_instructions_m | hardware_mul32_m | hardware_div32_m | hardware_fsmuld_m,
83 generic_v9_m = generic_v8_m | v9_instructions_m, 89 generic_v9_m = generic_v8_m | v9_instructions_m,
84 ultra3_m = generic_v9_m | vis1_instructions_m | vis2_instructions_m, 90 ultra3_m = generic_v9_m | vis1_instructions_m | vis2_instructions_m,
85 91
88 niagara1_m = generic_v9_m | niagara1_unique_m 94 niagara1_m = generic_v9_m | niagara1_unique_m
89 }; 95 };
90 96
91 static int _features; 97 static int _features;
92 static const char* _features_str; 98 static const char* _features_str;
99
100 static unsigned int _L2_cache_line_size;
101 static unsigned int L2_cache_line_size() { return _L2_cache_line_size; }
93 102
94 static void print_features(); 103 static void print_features();
95 static int determine_features(); 104 static int determine_features();
96 static int platform_features(int features); 105 static int platform_features(int features);
97 106
128 static bool has_vis3() { return (_features & vis3_instructions_m) != 0; } 137 static bool has_vis3() { return (_features & vis3_instructions_m) != 0; }
129 static bool has_blk_init() { return (_features & blk_init_instructions_m) != 0; } 138 static bool has_blk_init() { return (_features & blk_init_instructions_m) != 0; }
130 static bool has_cbcond() { return (_features & cbcond_instructions_m) != 0; } 139 static bool has_cbcond() { return (_features & cbcond_instructions_m) != 0; }
131 static bool has_sparc5_instr() { return (_features & sparc5_instructions_m) != 0; } 140 static bool has_sparc5_instr() { return (_features & sparc5_instructions_m) != 0; }
132 static bool has_aes() { return (_features & aes_instructions_m) != 0; } 141 static bool has_aes() { return (_features & aes_instructions_m) != 0; }
142 static bool has_sha1() { return (_features & sha1_instruction_m) != 0; }
143 static bool has_sha256() { return (_features & sha256_instruction_m) != 0; }
144 static bool has_sha512() { return (_features & sha512_instruction_m) != 0; }
133 145
134 static bool supports_compare_and_exchange() 146 static bool supports_compare_and_exchange()
135 { return has_v9(); } 147 { return has_v9(); }
136 148
137 // Returns true if the platform is in the niagara line (T series) 149 // Returns true if the platform is in the niagara line (T series)
157 // On T4 and newer Sparc BIS to the beginning of cache line always zeros it. 169 // On T4 and newer Sparc BIS to the beginning of cache line always zeros it.
158 static bool has_block_zeroing() { return has_blk_init() && is_T4(); } 170 static bool has_block_zeroing() { return has_blk_init() && is_T4(); }
159 171
160 static const char* cpu_features() { return _features_str; } 172 static const char* cpu_features() { return _features_str; }
161 173
162 static intx prefetch_data_size() { 174 // default prefetch block size on sparc
163 return is_T4() && !is_T7() ? 32 : 64; // default prefetch block size on sparc 175 static intx prefetch_data_size() { return L2_cache_line_size(); }
164 }
165 176
166 // Prefetch 177 // Prefetch
167 static intx prefetch_copy_interval_in_bytes() { 178 static intx prefetch_copy_interval_in_bytes() {
168 intx interval = PrefetchCopyIntervalInBytes; 179 intx interval = PrefetchCopyIntervalInBytes;
169 return interval >= 0 ? interval : (has_v9() ? 512 : 0); 180 return interval >= 0 ? interval : (has_v9() ? 512 : 0);