Mercurial > hg > truffle
annotate src/cpu/sparc/vm/vm_version_sparc.hpp @ 20804:7848fc12602b
Merge with jdk8u40-b25
| author | Gilles Duboscq <gilles.m.duboscq@oracle.com> |
|---|---|
| date | Tue, 07 Apr 2015 14:58:49 +0200 |
| parents | 52b4284cb496 d635fd1ac81c |
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| rev | line source |
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| 0 | 1 /* |
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2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
|
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
| 0 | 22 * |
| 23 */ | |
| 24 | |
| 1972 | 25 #ifndef CPU_SPARC_VM_VM_VERSION_SPARC_HPP |
| 26 #define CPU_SPARC_VM_VM_VERSION_SPARC_HPP | |
| 27 | |
| 28 #include "runtime/globals_extension.hpp" | |
| 29 #include "runtime/vm_version.hpp" | |
| 30 | |
| 0 | 31 class VM_Version: public Abstract_VM_Version { |
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32 friend class VMStructs; |
| 0 | 33 protected: |
| 34 enum Feature_Flag { | |
| 3839 | 35 v8_instructions = 0, |
| 36 hardware_mul32 = 1, | |
| 37 hardware_div32 = 2, | |
| 38 hardware_fsmuld = 3, | |
| 39 hardware_popc = 4, | |
| 40 v9_instructions = 5, | |
| 41 vis1_instructions = 6, | |
| 42 vis2_instructions = 7, | |
| 43 sun4v_instructions = 8, | |
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44 blk_init_instructions = 9, |
| 3839 | 45 fmaf_instructions = 10, |
| 46 fmau_instructions = 11, | |
| 47 vis3_instructions = 12, | |
| 6269 | 48 cbcond_instructions = 13, |
| 49 sparc64_family = 14, | |
| 50 M_family = 15, | |
| 51 T_family = 16, | |
| 14261 | 52 T1_model = 17, |
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53 sparc5_instructions = 18, |
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54 aes_instructions = 19, |
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55 sha1_instruction = 20, |
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56 sha256_instruction = 21, |
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57 sha512_instruction = 22 |
| 0 | 58 }; |
| 59 | |
| 60 enum Feature_Flag_Set { | |
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61 unknown_m = 0, |
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62 all_features_m = -1, |
| 0 | 63 |
| 3839 | 64 v8_instructions_m = 1 << v8_instructions, |
| 65 hardware_mul32_m = 1 << hardware_mul32, | |
| 66 hardware_div32_m = 1 << hardware_div32, | |
| 67 hardware_fsmuld_m = 1 << hardware_fsmuld, | |
| 68 hardware_popc_m = 1 << hardware_popc, | |
| 69 v9_instructions_m = 1 << v9_instructions, | |
| 70 vis1_instructions_m = 1 << vis1_instructions, | |
| 71 vis2_instructions_m = 1 << vis2_instructions, | |
| 72 sun4v_m = 1 << sun4v_instructions, | |
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73 blk_init_instructions_m = 1 << blk_init_instructions, |
| 3839 | 74 fmaf_instructions_m = 1 << fmaf_instructions, |
| 75 fmau_instructions_m = 1 << fmau_instructions, | |
| 76 vis3_instructions_m = 1 << vis3_instructions, | |
| 6269 | 77 cbcond_instructions_m = 1 << cbcond_instructions, |
| 3839 | 78 sparc64_family_m = 1 << sparc64_family, |
| 6269 | 79 M_family_m = 1 << M_family, |
| 3839 | 80 T_family_m = 1 << T_family, |
| 81 T1_model_m = 1 << T1_model, | |
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82 sparc5_instructions_m = 1 << sparc5_instructions, |
| 14261 | 83 aes_instructions_m = 1 << aes_instructions, |
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84 sha1_instruction_m = 1 << sha1_instruction, |
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85 sha256_instruction_m = 1 << sha256_instruction, |
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86 sha512_instruction_m = 1 << sha512_instruction, |
| 0 | 87 |
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88 generic_v8_m = v8_instructions_m | hardware_mul32_m | hardware_div32_m | hardware_fsmuld_m, |
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89 generic_v9_m = generic_v8_m | v9_instructions_m, |
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90 ultra3_m = generic_v9_m | vis1_instructions_m | vis2_instructions_m, |
| 0 | 91 |
| 92 // Temporary until we have something more accurate | |
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93 niagara1_unique_m = sun4v_m, |
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94 niagara1_m = generic_v9_m | niagara1_unique_m |
| 0 | 95 }; |
| 96 | |
| 97 static int _features; | |
| 98 static const char* _features_str; | |
| 99 | |
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100 static unsigned int _L2_cache_line_size; |
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101 static unsigned int L2_cache_line_size() { return _L2_cache_line_size; } |
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102 |
| 0 | 103 static void print_features(); |
| 104 static int determine_features(); | |
| 105 static int platform_features(int features); | |
| 106 | |
| 2080 | 107 // Returns true if the platform is in the niagara line (T series) |
| 6269 | 108 static bool is_M_family(int features) { return (features & M_family_m) != 0; } |
| 2080 | 109 static bool is_T_family(int features) { return (features & T_family_m) != 0; } |
| 110 static bool is_niagara() { return is_T_family(_features); } | |
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111 #ifdef ASSERT |
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112 static bool is_niagara(int features) { |
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113 // 'sun4v_m' may be defined on both Sun/Oracle Sparc CPUs as well as |
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114 // on Fujitsu Sparc64 CPUs, but only Sun/Oracle Sparcs can be 'niagaras'. |
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115 return (features & sun4v_m) != 0 && (features & sparc64_family_m) == 0; |
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116 } |
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117 #endif |
| 2080 | 118 |
| 119 // Returns true if it is niagara1 (T1). | |
| 120 static bool is_T1_model(int features) { return is_T_family(features) && ((features & T1_model_m) != 0); } | |
| 0 | 121 |
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122 static int maximum_niagara1_processor_count() { return 32; } |
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123 |
| 0 | 124 public: |
| 125 // Initialization | |
| 126 static void initialize(); | |
| 127 | |
| 128 // Instruction support | |
| 129 static bool has_v8() { return (_features & v8_instructions_m) != 0; } | |
| 130 static bool has_v9() { return (_features & v9_instructions_m) != 0; } | |
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131 static bool has_hardware_mul32() { return (_features & hardware_mul32_m) != 0; } |
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132 static bool has_hardware_div32() { return (_features & hardware_div32_m) != 0; } |
| 0 | 133 static bool has_hardware_fsmuld() { return (_features & hardware_fsmuld_m) != 0; } |
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134 static bool has_hardware_popc() { return (_features & hardware_popc_m) != 0; } |
| 0 | 135 static bool has_vis1() { return (_features & vis1_instructions_m) != 0; } |
| 136 static bool has_vis2() { return (_features & vis2_instructions_m) != 0; } | |
| 2080 | 137 static bool has_vis3() { return (_features & vis3_instructions_m) != 0; } |
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138 static bool has_blk_init() { return (_features & blk_init_instructions_m) != 0; } |
| 3839 | 139 static bool has_cbcond() { return (_features & cbcond_instructions_m) != 0; } |
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140 static bool has_sparc5_instr() { return (_features & sparc5_instructions_m) != 0; } |
| 14261 | 141 static bool has_aes() { return (_features & aes_instructions_m) != 0; } |
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142 static bool has_sha1() { return (_features & sha1_instruction_m) != 0; } |
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143 static bool has_sha256() { return (_features & sha256_instruction_m) != 0; } |
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144 static bool has_sha512() { return (_features & sha512_instruction_m) != 0; } |
| 0 | 145 |
| 146 static bool supports_compare_and_exchange() | |
| 147 { return has_v9(); } | |
| 148 | |
| 2080 | 149 // Returns true if the platform is in the niagara line (T series) |
| 150 // and newer than the niagara1. | |
| 151 static bool is_niagara_plus() { return is_T_family(_features) && !is_T1_model(_features); } | |
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152 |
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153 static bool is_M_series() { return is_M_family(_features); } |
| 3854 | 154 static bool is_T4() { return is_T_family(_features) && has_cbcond(); } |
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155 static bool is_T7() { return is_T_family(_features) && has_sparc5_instr(); } |
| 3839 | 156 |
| 2080 | 157 // Fujitsu SPARC64 |
| 158 static bool is_sparc64() { return (_features & sparc64_family_m) != 0; } | |
| 0 | 159 |
| 3839 | 160 static bool is_sun4v() { return (_features & sun4v_m) != 0; } |
| 161 static bool is_ultra3() { return (_features & ultra3_m) == ultra3_m && !is_sun4v() && !is_sparc64(); } | |
| 162 | |
| 2080 | 163 static bool has_fast_fxtof() { return is_niagara() || is_sparc64() || has_v9() && !is_ultra3(); } |
| 164 static bool has_fast_idiv() { return is_niagara_plus() || is_sparc64(); } | |
| 3854 | 165 |
| 3839 | 166 // T4 and newer Sparc have fast RDPC instruction. |
| 3854 | 167 static bool has_fast_rdpc() { return is_T4(); } |
| 168 | |
| 3892 | 169 // On T4 and newer Sparc BIS to the beginning of cache line always zeros it. |
| 170 static bool has_block_zeroing() { return has_blk_init() && is_T4(); } | |
| 0 | 171 |
| 172 static const char* cpu_features() { return _features_str; } | |
| 173 | |
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174 // default prefetch block size on sparc |
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175 static intx prefetch_data_size() { return L2_cache_line_size(); } |
| 0 | 176 |
| 177 // Prefetch | |
| 178 static intx prefetch_copy_interval_in_bytes() { | |
| 179 intx interval = PrefetchCopyIntervalInBytes; | |
| 180 return interval >= 0 ? interval : (has_v9() ? 512 : 0); | |
| 181 } | |
| 182 static intx prefetch_scan_interval_in_bytes() { | |
| 183 intx interval = PrefetchScanIntervalInBytes; | |
| 184 return interval >= 0 ? interval : (has_v9() ? 512 : 0); | |
| 185 } | |
| 186 static intx prefetch_fields_ahead() { | |
| 187 intx count = PrefetchFieldsAhead; | |
| 188 return count >= 0 ? count : (is_ultra3() ? 1 : 0); | |
| 189 } | |
| 190 | |
| 191 static intx allocate_prefetch_distance() { | |
| 192 // This method should be called before allocate_prefetch_style(). | |
| 193 intx count = AllocatePrefetchDistance; | |
| 194 if (count < 0) { // default is not defined ? | |
| 195 count = 512; | |
| 196 } | |
| 197 return count; | |
| 198 } | |
| 199 static intx allocate_prefetch_style() { | |
| 200 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive"); | |
| 201 // Return 0 if AllocatePrefetchDistance was not defined. | |
| 202 return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0; | |
| 203 } | |
| 204 | |
| 205 // Assembler testing | |
| 206 static void allow_all(); | |
| 207 static void revert(); | |
| 208 | |
| 209 // Override the Abstract_VM_Version implementation. | |
| 210 static uint page_size_count() { return is_sun4v() ? 4 : 2; } | |
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211 |
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212 // Calculates the number of parallel threads |
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213 static unsigned int calc_parallel_worker_threads(); |
| 0 | 214 }; |
| 1972 | 215 |
| 216 #endif // CPU_SPARC_VM_VM_VERSION_SPARC_HPP |