Mercurial > hg > truffle

comparison src/cpu/sparc/vm/sparc.ad @ 2401:7e88bdae86ec

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
7029017: Additional architecture support for c2 compiler Summary: Enables cross building of a c2 VM. Support masking of shift counts when the processor architecture mandates it. Reviewed-by: kvn, never
author roland
date Fri, 25 Mar 2011 09:35:39 +0100
parents ab42c7e1cf83
children faa472957b38
comparison
equal deleted inserted replaced
2399:b2949bf39900 2401:7e88bdae86ec
1840 1840
1841 // Should the Matcher clone shifts on addressing modes, expecting them to 1841 // Should the Matcher clone shifts on addressing modes, expecting them to
1842 // be subsumed into complex addressing expressions or compute them into 1842 // be subsumed into complex addressing expressions or compute them into
1843 // registers? True for Intel but false for most RISCs 1843 // registers? True for Intel but false for most RISCs
1844 const bool Matcher::clone_shift_expressions = false; 1844 const bool Matcher::clone_shift_expressions = false;
1845
1846 // Do we need to mask the count passed to shift instructions or does
1847 // the cpu only look at the lower 5/6 bits anyway?
1848 const bool Matcher::need_masked_shift_count = false;
1845 1849
1846 bool Matcher::narrow_oop_use_complex_address() { 1850 bool Matcher::narrow_oop_use_complex_address() {
1847 NOT_LP64(ShouldNotCallThis()); 1851 NOT_LP64(ShouldNotCallThis());
1848 assert(UseCompressedOops, "only for compressed oops code"); 1852 assert(UseCompressedOops, "only for compressed oops code");
1849 return false; 1853 return false;