Mercurial > hg > truffle
comparison src/cpu/x86/vm/assembler_x86.cpp @ 6179:8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
Summary: Increase vector size up to 256-bits for YMM AVX registers on x86.
Reviewed-by: never, twisti, roland
author | kvn |
---|---|
date | Fri, 15 Jun 2012 01:25:19 -0700 |
parents | e7715c222897 |
children | 2c368ea3e844 |
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6146:eba1d5bce9e8 | 6179:8c92982cbbc4 |
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1635 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE); | 1635 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE); |
1636 emit_byte(0x28); | 1636 emit_byte(0x28); |
1637 emit_byte(0xC0 | encode); | 1637 emit_byte(0xC0 | encode); |
1638 } | 1638 } |
1639 | 1639 |
1640 void Assembler::movlhps(XMMRegister dst, XMMRegister src) { | |
1641 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1642 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE); | |
1643 emit_byte(0x16); | |
1644 emit_byte(0xC0 | encode); | |
1645 } | |
1646 | |
1640 void Assembler::movb(Register dst, Address src) { | 1647 void Assembler::movb(Register dst, Address src) { |
1641 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); | 1648 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); |
1642 InstructionMark im(this); | 1649 InstructionMark im(this); |
1643 prefix(src, dst, true); | 1650 prefix(src, dst, true); |
1644 emit_byte(0x8A); | 1651 emit_byte(0x8A); |
1684 simd_prefix(dst, src, VEX_SIMD_66); | 1691 simd_prefix(dst, src, VEX_SIMD_66); |
1685 emit_byte(0x6E); | 1692 emit_byte(0x6E); |
1686 emit_operand(dst, src); | 1693 emit_operand(dst, src); |
1687 } | 1694 } |
1688 | 1695 |
1696 void Assembler::movdl(Address dst, XMMRegister src) { | |
1697 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1698 InstructionMark im(this); | |
1699 simd_prefix(dst, src, VEX_SIMD_66); | |
1700 emit_byte(0x7E); | |
1701 emit_operand(src, dst); | |
1702 } | |
1703 | |
1689 void Assembler::movdqa(XMMRegister dst, XMMRegister src) { | 1704 void Assembler::movdqa(XMMRegister dst, XMMRegister src) { |
1690 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1705 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1691 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); | 1706 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); |
1692 emit_byte(0x6F); | 1707 emit_byte(0x6F); |
1693 emit_byte(0xC0 | encode); | 1708 emit_byte(0xC0 | encode); |
1710 | 1725 |
1711 void Assembler::movdqu(Address dst, XMMRegister src) { | 1726 void Assembler::movdqu(Address dst, XMMRegister src) { |
1712 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1727 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1713 InstructionMark im(this); | 1728 InstructionMark im(this); |
1714 simd_prefix(dst, src, VEX_SIMD_F3); | 1729 simd_prefix(dst, src, VEX_SIMD_F3); |
1730 emit_byte(0x7F); | |
1731 emit_operand(src, dst); | |
1732 } | |
1733 | |
1734 // Move Unaligned 256bit Vector | |
1735 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) { | |
1736 assert(UseAVX, ""); | |
1737 bool vector256 = true; | |
1738 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, vector256); | |
1739 emit_byte(0x6F); | |
1740 emit_byte(0xC0 | encode); | |
1741 } | |
1742 | |
1743 void Assembler::vmovdqu(XMMRegister dst, Address src) { | |
1744 assert(UseAVX, ""); | |
1745 InstructionMark im(this); | |
1746 bool vector256 = true; | |
1747 vex_prefix(dst, xnoreg, src, VEX_SIMD_F3, vector256); | |
1748 emit_byte(0x6F); | |
1749 emit_operand(dst, src); | |
1750 } | |
1751 | |
1752 void Assembler::vmovdqu(Address dst, XMMRegister src) { | |
1753 assert(UseAVX, ""); | |
1754 InstructionMark im(this); | |
1755 bool vector256 = true; | |
1756 // swap src<->dst for encoding | |
1757 assert(src != xnoreg, "sanity"); | |
1758 vex_prefix(src, xnoreg, dst, VEX_SIMD_F3, vector256); | |
1715 emit_byte(0x7F); | 1759 emit_byte(0x7F); |
1716 emit_operand(src, dst); | 1760 emit_operand(src, dst); |
1717 } | 1761 } |
1718 | 1762 |
1719 // Uses zero extension on 64bit | 1763 // Uses zero extension on 64bit |
3110 vex_prefix(dst, nds, src, VEX_SIMD_66); // 128-bit vector | 3154 vex_prefix(dst, nds, src, VEX_SIMD_66); // 128-bit vector |
3111 emit_byte(0x57); | 3155 emit_byte(0x57); |
3112 emit_operand(dst, src); | 3156 emit_operand(dst, src); |
3113 } | 3157 } |
3114 | 3158 |
3159 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { | |
3160 assert(VM_Version::supports_avx(), ""); | |
3161 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256); | |
3162 emit_byte(0x57); | |
3163 emit_byte(0xC0 | encode); | |
3164 } | |
3165 | |
3115 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src) { | 3166 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src) { |
3116 assert(VM_Version::supports_avx(), ""); | 3167 assert(VM_Version::supports_avx(), ""); |
3117 InstructionMark im(this); | 3168 InstructionMark im(this); |
3118 vex_prefix(dst, nds, src, VEX_SIMD_NONE); // 128-bit vector | 3169 vex_prefix(dst, nds, src, VEX_SIMD_NONE); // 128-bit vector |
3119 emit_byte(0x57); | 3170 emit_byte(0x57); |
3120 emit_operand(dst, src); | 3171 emit_operand(dst, src); |
3172 } | |
3173 | |
3174 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { | |
3175 assert(VM_Version::supports_avx(), ""); | |
3176 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_NONE, vector256); | |
3177 emit_byte(0x57); | |
3178 emit_byte(0xC0 | encode); | |
3179 } | |
3180 | |
3181 void Assembler::vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src) { | |
3182 assert(VM_Version::supports_avx(), ""); | |
3183 bool vector256 = true; | |
3184 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A); | |
3185 emit_byte(0x18); | |
3186 emit_byte(0xC0 | encode); | |
3187 // 0x00 - insert into lower 128 bits | |
3188 // 0x01 - insert into upper 128 bits | |
3189 emit_byte(0x01); | |
3190 } | |
3191 | |
3192 void Assembler::vzeroupper() { | |
3193 assert(VM_Version::supports_avx(), ""); | |
3194 (void)vex_prefix_and_encode(xmm0, xmm0, xmm0, VEX_SIMD_NONE); | |
3195 emit_byte(0x77); | |
3121 } | 3196 } |
3122 | 3197 |
3123 | 3198 |
3124 #ifndef _LP64 | 3199 #ifndef _LP64 |
3125 // 32bit only pieces of the assembler | 3200 // 32bit only pieces of the assembler |