Mercurial > hg > truffle
annotate src/cpu/x86/vm/assembler_x86.cpp @ 6179:8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
Summary: Increase vector size up to 256-bits for YMM AVX registers on x86.
Reviewed-by: never, twisti, roland
| author | kvn |
|---|---|
| date | Fri, 15 Jun 2012 01:25:19 -0700 |
| parents | e7715c222897 |
| children | 2c368ea3e844 |
| rev | line source |
|---|---|
| 0 | 1 /* |
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2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
|
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
|
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
| 0 | 22 * |
| 23 */ | |
| 24 | |
| 1972 | 25 #include "precompiled.hpp" |
| 26 #include "assembler_x86.inline.hpp" | |
| 27 #include "gc_interface/collectedHeap.inline.hpp" | |
| 28 #include "interpreter/interpreter.hpp" | |
| 29 #include "memory/cardTableModRefBS.hpp" | |
| 30 #include "memory/resourceArea.hpp" | |
| 31 #include "prims/methodHandles.hpp" | |
| 32 #include "runtime/biasedLocking.hpp" | |
| 33 #include "runtime/interfaceSupport.hpp" | |
| 34 #include "runtime/objectMonitor.hpp" | |
| 35 #include "runtime/os.hpp" | |
| 36 #include "runtime/sharedRuntime.hpp" | |
| 37 #include "runtime/stubRoutines.hpp" | |
| 38 #ifndef SERIALGC | |
| 39 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp" | |
| 40 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp" | |
| 41 #include "gc_implementation/g1/heapRegion.hpp" | |
| 42 #endif | |
| 0 | 43 |
| 44 // Implementation of AddressLiteral | |
| 45 | |
| 46 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) { | |
| 47 _is_lval = false; | |
| 48 _target = target; | |
| 49 switch (rtype) { | |
| 50 case relocInfo::oop_type: | |
| 51 // Oops are a special case. Normally they would be their own section | |
| 52 // but in cases like icBuffer they are literals in the code stream that | |
| 53 // we don't have a section for. We use none so that we get a literal address | |
| 54 // which is always patchable. | |
| 55 break; | |
| 56 case relocInfo::external_word_type: | |
| 57 _rspec = external_word_Relocation::spec(target); | |
| 58 break; | |
| 59 case relocInfo::internal_word_type: | |
| 60 _rspec = internal_word_Relocation::spec(target); | |
| 61 break; | |
| 62 case relocInfo::opt_virtual_call_type: | |
| 63 _rspec = opt_virtual_call_Relocation::spec(); | |
| 64 break; | |
| 65 case relocInfo::static_call_type: | |
| 66 _rspec = static_call_Relocation::spec(); | |
| 67 break; | |
| 68 case relocInfo::runtime_call_type: | |
| 69 _rspec = runtime_call_Relocation::spec(); | |
| 70 break; | |
| 71 case relocInfo::poll_type: | |
| 72 case relocInfo::poll_return_type: | |
| 73 _rspec = Relocation::spec_simple(rtype); | |
| 74 break; | |
| 75 case relocInfo::none: | |
| 76 break; | |
| 77 default: | |
| 78 ShouldNotReachHere(); | |
| 79 break; | |
| 80 } | |
| 81 } | |
| 82 | |
| 83 // Implementation of Address | |
| 84 | |
| 304 | 85 #ifdef _LP64 |
| 86 | |
| 0 | 87 Address Address::make_array(ArrayAddress adr) { |
| 88 // Not implementable on 64bit machines | |
| 89 // Should have been handled higher up the call chain. | |
| 90 ShouldNotReachHere(); | |
| 304 | 91 return Address(); |
| 92 } | |
| 93 | |
| 94 // exceedingly dangerous constructor | |
| 95 Address::Address(int disp, address loc, relocInfo::relocType rtype) { | |
| 96 _base = noreg; | |
| 97 _index = noreg; | |
| 98 _scale = no_scale; | |
| 99 _disp = disp; | |
| 100 switch (rtype) { | |
| 101 case relocInfo::external_word_type: | |
| 102 _rspec = external_word_Relocation::spec(loc); | |
| 103 break; | |
| 104 case relocInfo::internal_word_type: | |
| 105 _rspec = internal_word_Relocation::spec(loc); | |
| 106 break; | |
| 107 case relocInfo::runtime_call_type: | |
| 108 // HMM | |
| 109 _rspec = runtime_call_Relocation::spec(); | |
| 110 break; | |
| 111 case relocInfo::poll_type: | |
| 112 case relocInfo::poll_return_type: | |
| 113 _rspec = Relocation::spec_simple(rtype); | |
| 114 break; | |
| 115 case relocInfo::none: | |
| 116 break; | |
| 117 default: | |
| 118 ShouldNotReachHere(); | |
| 119 } | |
| 120 } | |
| 121 #else // LP64 | |
| 122 | |
| 123 Address Address::make_array(ArrayAddress adr) { | |
| 0 | 124 AddressLiteral base = adr.base(); |
| 125 Address index = adr.index(); | |
| 126 assert(index._disp == 0, "must not have disp"); // maybe it can? | |
| 127 Address array(index._base, index._index, index._scale, (intptr_t) base.target()); | |
| 128 array._rspec = base._rspec; | |
| 129 return array; | |
| 304 | 130 } |
| 0 | 131 |
| 132 // exceedingly dangerous constructor | |
| 133 Address::Address(address loc, RelocationHolder spec) { | |
| 134 _base = noreg; | |
| 135 _index = noreg; | |
| 136 _scale = no_scale; | |
| 137 _disp = (intptr_t) loc; | |
| 138 _rspec = spec; | |
| 139 } | |
| 304 | 140 |
| 0 | 141 #endif // _LP64 |
| 142 | |
| 304 | 143 |
| 144 | |
| 0 | 145 // Convert the raw encoding form into the form expected by the constructor for |
| 146 // Address. An index of 4 (rsp) corresponds to having no index, so convert | |
| 147 // that to noreg for the Address constructor. | |
| 624 | 148 Address Address::make_raw(int base, int index, int scale, int disp, bool disp_is_oop) { |
| 149 RelocationHolder rspec; | |
| 150 if (disp_is_oop) { | |
| 151 rspec = Relocation::spec_simple(relocInfo::oop_type); | |
| 152 } | |
| 0 | 153 bool valid_index = index != rsp->encoding(); |
| 154 if (valid_index) { | |
| 155 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp)); | |
| 624 | 156 madr._rspec = rspec; |
| 0 | 157 return madr; |
| 158 } else { | |
| 159 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp)); | |
| 624 | 160 madr._rspec = rspec; |
| 0 | 161 return madr; |
| 162 } | |
| 163 } | |
| 164 | |
| 165 // Implementation of Assembler | |
| 166 | |
| 167 int AbstractAssembler::code_fill_byte() { | |
| 168 return (u_char)'\xF4'; // hlt | |
| 169 } | |
| 170 | |
| 171 // make this go away someday | |
| 172 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) { | |
| 173 if (rtype == relocInfo::none) | |
| 174 emit_long(data); | |
| 175 else emit_data(data, Relocation::spec_simple(rtype), format); | |
| 176 } | |
| 177 | |
| 178 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) { | |
| 304 | 179 assert(imm_operand == 0, "default format must be immediate in this file"); |
| 0 | 180 assert(inst_mark() != NULL, "must be inside InstructionMark"); |
| 181 if (rspec.type() != relocInfo::none) { | |
| 182 #ifdef ASSERT | |
| 183 check_relocation(rspec, format); | |
| 184 #endif | |
| 185 // Do not use AbstractAssembler::relocate, which is not intended for | |
| 186 // embedded words. Instead, relocate to the enclosing instruction. | |
| 187 | |
| 188 // hack. call32 is too wide for mask so use disp32 | |
| 189 if (format == call32_operand) | |
| 190 code_section()->relocate(inst_mark(), rspec, disp32_operand); | |
| 191 else | |
| 192 code_section()->relocate(inst_mark(), rspec, format); | |
| 193 } | |
| 194 emit_long(data); | |
| 195 } | |
| 196 | |
| 304 | 197 static int encode(Register r) { |
| 198 int enc = r->encoding(); | |
| 199 if (enc >= 8) { | |
| 200 enc -= 8; | |
| 201 } | |
| 202 return enc; | |
| 203 } | |
| 204 | |
| 205 static int encode(XMMRegister r) { | |
| 206 int enc = r->encoding(); | |
| 207 if (enc >= 8) { | |
| 208 enc -= 8; | |
| 209 } | |
| 210 return enc; | |
| 211 } | |
| 0 | 212 |
| 213 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) { | |
| 214 assert(dst->has_byte_register(), "must have byte register"); | |
| 215 assert(isByte(op1) && isByte(op2), "wrong opcode"); | |
| 216 assert(isByte(imm8), "not a byte"); | |
| 217 assert((op1 & 0x01) == 0, "should be 8bit operation"); | |
| 218 emit_byte(op1); | |
| 304 | 219 emit_byte(op2 | encode(dst)); |
| 0 | 220 emit_byte(imm8); |
| 221 } | |
| 222 | |
| 223 | |
| 304 | 224 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) { |
| 0 | 225 assert(isByte(op1) && isByte(op2), "wrong opcode"); |
| 226 assert((op1 & 0x01) == 1, "should be 32bit operation"); | |
| 227 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); | |
| 228 if (is8bit(imm32)) { | |
| 229 emit_byte(op1 | 0x02); // set sign bit | |
| 304 | 230 emit_byte(op2 | encode(dst)); |
| 0 | 231 emit_byte(imm32 & 0xFF); |
| 232 } else { | |
| 233 emit_byte(op1); | |
| 304 | 234 emit_byte(op2 | encode(dst)); |
| 0 | 235 emit_long(imm32); |
| 236 } | |
| 237 } | |
| 238 | |
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239 // Force generation of a 4 byte immediate value even if it fits into 8bit |
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240 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) { |
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241 assert(isByte(op1) && isByte(op2), "wrong opcode"); |
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242 assert((op1 & 0x01) == 1, "should be 32bit operation"); |
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243 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); |
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244 emit_byte(op1); |
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245 emit_byte(op2 | encode(dst)); |
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246 emit_long(imm32); |
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247 } |
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248 |
| 0 | 249 // immediate-to-memory forms |
| 304 | 250 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) { |
| 0 | 251 assert((op1 & 0x01) == 1, "should be 32bit operation"); |
| 252 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); | |
| 253 if (is8bit(imm32)) { | |
| 254 emit_byte(op1 | 0x02); // set sign bit | |
| 304 | 255 emit_operand(rm, adr, 1); |
| 0 | 256 emit_byte(imm32 & 0xFF); |
| 257 } else { | |
| 258 emit_byte(op1); | |
| 304 | 259 emit_operand(rm, adr, 4); |
| 0 | 260 emit_long(imm32); |
| 261 } | |
| 262 } | |
| 263 | |
| 264 void Assembler::emit_arith(int op1, int op2, Register dst, jobject obj) { | |
| 304 | 265 LP64_ONLY(ShouldNotReachHere()); |
| 0 | 266 assert(isByte(op1) && isByte(op2), "wrong opcode"); |
| 267 assert((op1 & 0x01) == 1, "should be 32bit operation"); | |
| 268 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); | |
| 269 InstructionMark im(this); | |
| 270 emit_byte(op1); | |
| 304 | 271 emit_byte(op2 | encode(dst)); |
| 272 emit_data((intptr_t)obj, relocInfo::oop_type, 0); | |
| 0 | 273 } |
| 274 | |
| 275 | |
| 276 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) { | |
| 277 assert(isByte(op1) && isByte(op2), "wrong opcode"); | |
| 278 emit_byte(op1); | |
| 304 | 279 emit_byte(op2 | encode(dst) << 3 | encode(src)); |
| 280 } | |
| 281 | |
| 282 | |
| 283 void Assembler::emit_operand(Register reg, Register base, Register index, | |
| 284 Address::ScaleFactor scale, int disp, | |
| 285 RelocationHolder const& rspec, | |
| 286 int rip_relative_correction) { | |
| 0 | 287 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type(); |
| 304 | 288 |
| 289 // Encode the registers as needed in the fields they are used in | |
| 290 | |
| 291 int regenc = encode(reg) << 3; | |
| 292 int indexenc = index->is_valid() ? encode(index) << 3 : 0; | |
| 293 int baseenc = base->is_valid() ? encode(base) : 0; | |
| 294 | |
| 0 | 295 if (base->is_valid()) { |
| 296 if (index->is_valid()) { | |
| 297 assert(scale != Address::no_scale, "inconsistent address"); | |
| 298 // [base + index*scale + disp] | |
| 304 | 299 if (disp == 0 && rtype == relocInfo::none && |
| 300 base != rbp LP64_ONLY(&& base != r13)) { | |
| 0 | 301 // [base + index*scale] |
| 302 // [00 reg 100][ss index base] | |
| 303 assert(index != rsp, "illegal addressing mode"); | |
| 304 | 304 emit_byte(0x04 | regenc); |
| 305 emit_byte(scale << 6 | indexenc | baseenc); | |
| 0 | 306 } else if (is8bit(disp) && rtype == relocInfo::none) { |
| 307 // [base + index*scale + imm8] | |
| 308 // [01 reg 100][ss index base] imm8 | |
| 309 assert(index != rsp, "illegal addressing mode"); | |
| 304 | 310 emit_byte(0x44 | regenc); |
| 311 emit_byte(scale << 6 | indexenc | baseenc); | |
| 0 | 312 emit_byte(disp & 0xFF); |
| 313 } else { | |
| 304 | 314 // [base + index*scale + disp32] |
| 315 // [10 reg 100][ss index base] disp32 | |
| 0 | 316 assert(index != rsp, "illegal addressing mode"); |
| 304 | 317 emit_byte(0x84 | regenc); |
| 318 emit_byte(scale << 6 | indexenc | baseenc); | |
| 0 | 319 emit_data(disp, rspec, disp32_operand); |
| 320 } | |
| 304 | 321 } else if (base == rsp LP64_ONLY(|| base == r12)) { |
| 322 // [rsp + disp] | |
| 0 | 323 if (disp == 0 && rtype == relocInfo::none) { |
| 304 | 324 // [rsp] |
| 0 | 325 // [00 reg 100][00 100 100] |
| 304 | 326 emit_byte(0x04 | regenc); |
| 0 | 327 emit_byte(0x24); |
| 328 } else if (is8bit(disp) && rtype == relocInfo::none) { | |
| 304 | 329 // [rsp + imm8] |
| 330 // [01 reg 100][00 100 100] disp8 | |
| 331 emit_byte(0x44 | regenc); | |
| 0 | 332 emit_byte(0x24); |
| 333 emit_byte(disp & 0xFF); | |
| 334 } else { | |
| 304 | 335 // [rsp + imm32] |
| 336 // [10 reg 100][00 100 100] disp32 | |
| 337 emit_byte(0x84 | regenc); | |
| 0 | 338 emit_byte(0x24); |
| 339 emit_data(disp, rspec, disp32_operand); | |
| 340 } | |
| 341 } else { | |
| 342 // [base + disp] | |
| 304 | 343 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode"); |
| 344 if (disp == 0 && rtype == relocInfo::none && | |
| 345 base != rbp LP64_ONLY(&& base != r13)) { | |
| 0 | 346 // [base] |
| 347 // [00 reg base] | |
| 304 | 348 emit_byte(0x00 | regenc | baseenc); |
| 0 | 349 } else if (is8bit(disp) && rtype == relocInfo::none) { |
| 304 | 350 // [base + disp8] |
| 351 // [01 reg base] disp8 | |
| 352 emit_byte(0x40 | regenc | baseenc); | |
| 0 | 353 emit_byte(disp & 0xFF); |
| 354 } else { | |
| 304 | 355 // [base + disp32] |
| 356 // [10 reg base] disp32 | |
| 357 emit_byte(0x80 | regenc | baseenc); | |
| 0 | 358 emit_data(disp, rspec, disp32_operand); |
| 359 } | |
| 360 } | |
| 361 } else { | |
| 362 if (index->is_valid()) { | |
| 363 assert(scale != Address::no_scale, "inconsistent address"); | |
| 364 // [index*scale + disp] | |
| 304 | 365 // [00 reg 100][ss index 101] disp32 |
| 0 | 366 assert(index != rsp, "illegal addressing mode"); |
| 304 | 367 emit_byte(0x04 | regenc); |
| 368 emit_byte(scale << 6 | indexenc | 0x05); | |
| 0 | 369 emit_data(disp, rspec, disp32_operand); |
| 304 | 370 } else if (rtype != relocInfo::none ) { |
| 371 // [disp] (64bit) RIP-RELATIVE (32bit) abs | |
| 372 // [00 000 101] disp32 | |
| 373 | |
| 374 emit_byte(0x05 | regenc); | |
| 375 // Note that the RIP-rel. correction applies to the generated | |
| 376 // disp field, but _not_ to the target address in the rspec. | |
| 377 | |
| 378 // disp was created by converting the target address minus the pc | |
| 379 // at the start of the instruction. That needs more correction here. | |
| 380 // intptr_t disp = target - next_ip; | |
| 381 assert(inst_mark() != NULL, "must be inside InstructionMark"); | |
| 382 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction; | |
| 383 int64_t adjusted = disp; | |
| 384 // Do rip-rel adjustment for 64bit | |
| 385 LP64_ONLY(adjusted -= (next_ip - inst_mark())); | |
| 386 assert(is_simm32(adjusted), | |
| 387 "must be 32bit offset (RIP relative address)"); | |
| 388 emit_data((int32_t) adjusted, rspec, disp32_operand); | |
| 389 | |
| 0 | 390 } else { |
| 304 | 391 // 32bit never did this, did everything as the rip-rel/disp code above |
| 392 // [disp] ABSOLUTE | |
| 393 // [00 reg 100][00 100 101] disp32 | |
| 394 emit_byte(0x04 | regenc); | |
| 395 emit_byte(0x25); | |
| 0 | 396 emit_data(disp, rspec, disp32_operand); |
| 397 } | |
| 398 } | |
| 399 } | |
| 400 | |
| 304 | 401 void Assembler::emit_operand(XMMRegister reg, Register base, Register index, |
| 402 Address::ScaleFactor scale, int disp, | |
| 403 RelocationHolder const& rspec) { | |
| 404 emit_operand((Register)reg, base, index, scale, disp, rspec); | |
| 405 } | |
| 406 | |
| 0 | 407 // Secret local extension to Assembler::WhichOperand: |
| 408 #define end_pc_operand (_WhichOperand_limit) | |
| 409 | |
| 410 address Assembler::locate_operand(address inst, WhichOperand which) { | |
| 411 // Decode the given instruction, and return the address of | |
| 412 // an embedded 32-bit operand word. | |
| 413 | |
| 414 // If "which" is disp32_operand, selects the displacement portion | |
| 415 // of an effective address specifier. | |
| 304 | 416 // If "which" is imm64_operand, selects the trailing immediate constant. |
| 0 | 417 // If "which" is call32_operand, selects the displacement of a call or jump. |
| 418 // Caller is responsible for ensuring that there is such an operand, | |
| 304 | 419 // and that it is 32/64 bits wide. |
| 0 | 420 |
| 421 // If "which" is end_pc_operand, find the end of the instruction. | |
| 422 | |
| 423 address ip = inst; | |
| 304 | 424 bool is_64bit = false; |
| 425 | |
| 426 debug_only(bool has_disp32 = false); | |
| 427 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn | |
| 428 | |
| 429 again_after_prefix: | |
| 0 | 430 switch (0xFF & *ip++) { |
| 431 | |
| 432 // These convenience macros generate groups of "case" labels for the switch. | |
| 304 | 433 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3 |
| 434 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \ | |
| 0 | 435 case (x)+4: case (x)+5: case (x)+6: case (x)+7 |
| 304 | 436 #define REP16(x) REP8((x)+0): \ |
| 0 | 437 case REP8((x)+8) |
| 438 | |
| 439 case CS_segment: | |
| 440 case SS_segment: | |
| 441 case DS_segment: | |
| 442 case ES_segment: | |
| 443 case FS_segment: | |
| 444 case GS_segment: | |
| 304 | 445 // Seems dubious |
| 446 LP64_ONLY(assert(false, "shouldn't have that prefix")); | |
| 0 | 447 assert(ip == inst+1, "only one prefix allowed"); |
| 448 goto again_after_prefix; | |
| 449 | |
| 304 | 450 case 0x67: |
| 451 case REX: | |
| 452 case REX_B: | |
| 453 case REX_X: | |
| 454 case REX_XB: | |
| 455 case REX_R: | |
| 456 case REX_RB: | |
| 457 case REX_RX: | |
| 458 case REX_RXB: | |
| 459 NOT_LP64(assert(false, "64bit prefixes")); | |
| 460 goto again_after_prefix; | |
| 461 | |
| 462 case REX_W: | |
| 463 case REX_WB: | |
| 464 case REX_WX: | |
| 465 case REX_WXB: | |
| 466 case REX_WR: | |
| 467 case REX_WRB: | |
| 468 case REX_WRX: | |
| 469 case REX_WRXB: | |
| 470 NOT_LP64(assert(false, "64bit prefixes")); | |
| 471 is_64bit = true; | |
| 472 goto again_after_prefix; | |
| 473 | |
| 474 case 0xFF: // pushq a; decl a; incl a; call a; jmp a | |
| 0 | 475 case 0x88: // movb a, r |
| 476 case 0x89: // movl a, r | |
| 477 case 0x8A: // movb r, a | |
| 478 case 0x8B: // movl r, a | |
| 479 case 0x8F: // popl a | |
| 304 | 480 debug_only(has_disp32 = true); |
| 0 | 481 break; |
| 482 | |
| 304 | 483 case 0x68: // pushq #32 |
| 484 if (which == end_pc_operand) { | |
| 485 return ip + 4; | |
| 486 } | |
| 487 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate"); | |
| 0 | 488 return ip; // not produced by emit_operand |
| 489 | |
| 490 case 0x66: // movw ... (size prefix) | |
| 304 | 491 again_after_size_prefix2: |
| 0 | 492 switch (0xFF & *ip++) { |
| 304 | 493 case REX: |
| 494 case REX_B: | |
| 495 case REX_X: | |
| 496 case REX_XB: | |
| 497 case REX_R: | |
| 498 case REX_RB: | |
| 499 case REX_RX: | |
| 500 case REX_RXB: | |
| 501 case REX_W: | |
| 502 case REX_WB: | |
| 503 case REX_WX: | |
| 504 case REX_WXB: | |
| 505 case REX_WR: | |
| 506 case REX_WRB: | |
| 507 case REX_WRX: | |
| 508 case REX_WRXB: | |
| 509 NOT_LP64(assert(false, "64bit prefix found")); | |
| 510 goto again_after_size_prefix2; | |
| 0 | 511 case 0x8B: // movw r, a |
| 512 case 0x89: // movw a, r | |
| 304 | 513 debug_only(has_disp32 = true); |
| 0 | 514 break; |
| 515 case 0xC7: // movw a, #16 | |
| 304 | 516 debug_only(has_disp32 = true); |
| 0 | 517 tail_size = 2; // the imm16 |
| 518 break; | |
| 519 case 0x0F: // several SSE/SSE2 variants | |
| 520 ip--; // reparse the 0x0F | |
| 521 goto again_after_prefix; | |
| 522 default: | |
| 523 ShouldNotReachHere(); | |
| 524 } | |
| 525 break; | |
| 526 | |
| 304 | 527 case REP8(0xB8): // movl/q r, #32/#64(oop?) |
| 528 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4); | |
| 529 // these asserts are somewhat nonsensical | |
| 530 #ifndef _LP64 | |
| 5984 | 531 assert(which == imm_operand || which == disp32_operand, |
| 532 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, ip)); | |
| 304 | 533 #else |
| 534 assert((which == call32_operand || which == imm_operand) && is_64bit || | |
| 5984 | 535 which == narrow_oop_operand && !is_64bit, |
| 536 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, ip)); | |
| 304 | 537 #endif // _LP64 |
| 0 | 538 return ip; |
| 539 | |
| 540 case 0x69: // imul r, a, #32 | |
| 541 case 0xC7: // movl a, #32(oop?) | |
| 542 tail_size = 4; | |
| 304 | 543 debug_only(has_disp32 = true); // has both kinds of operands! |
| 0 | 544 break; |
| 545 | |
| 546 case 0x0F: // movx..., etc. | |
| 547 switch (0xFF & *ip++) { | |
| 4759 | 548 case 0x3A: // pcmpestri |
| 549 tail_size = 1; | |
| 550 case 0x38: // ptest, pmovzxbw | |
| 551 ip++; // skip opcode | |
| 552 debug_only(has_disp32 = true); // has both kinds of operands! | |
| 553 break; | |
| 554 | |
| 555 case 0x70: // pshufd r, r/a, #8 | |
| 556 debug_only(has_disp32 = true); // has both kinds of operands! | |
| 557 case 0x73: // psrldq r, #8 | |
| 558 tail_size = 1; | |
| 559 break; | |
| 560 | |
| 0 | 561 case 0x12: // movlps |
| 562 case 0x28: // movaps | |
| 563 case 0x2E: // ucomiss | |
| 564 case 0x2F: // comiss | |
| 565 case 0x54: // andps | |
| 566 case 0x55: // andnps | |
| 567 case 0x56: // orps | |
| 568 case 0x57: // xorps | |
| 569 case 0x6E: // movd | |
| 570 case 0x7E: // movd | |
| 4759 | 571 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush |
| 304 | 572 debug_only(has_disp32 = true); |
| 0 | 573 break; |
| 574 | |
| 575 case 0xAD: // shrd r, a, %cl | |
| 576 case 0xAF: // imul r, a | |
| 304 | 577 case 0xBE: // movsbl r, a (movsxb) |
| 578 case 0xBF: // movswl r, a (movsxw) | |
| 579 case 0xB6: // movzbl r, a (movzxb) | |
| 580 case 0xB7: // movzwl r, a (movzxw) | |
| 0 | 581 case REP16(0x40): // cmovl cc, r, a |
| 582 case 0xB0: // cmpxchgb | |
| 583 case 0xB1: // cmpxchg | |
| 584 case 0xC1: // xaddl | |
| 585 case 0xC7: // cmpxchg8 | |
| 586 case REP16(0x90): // setcc a | |
| 304 | 587 debug_only(has_disp32 = true); |
| 0 | 588 // fall out of the switch to decode the address |
| 589 break; | |
| 304 | 590 |
| 4759 | 591 case 0xC4: // pinsrw r, a, #8 |
| 592 debug_only(has_disp32 = true); | |
| 593 case 0xC5: // pextrw r, r, #8 | |
| 594 tail_size = 1; // the imm8 | |
| 595 break; | |
| 596 | |
| 0 | 597 case 0xAC: // shrd r, a, #8 |
| 304 | 598 debug_only(has_disp32 = true); |
| 0 | 599 tail_size = 1; // the imm8 |
| 600 break; | |
| 304 | 601 |
| 0 | 602 case REP16(0x80): // jcc rdisp32 |
| 603 if (which == end_pc_operand) return ip + 4; | |
| 304 | 604 assert(which == call32_operand, "jcc has no disp32 or imm"); |
| 0 | 605 return ip; |
| 606 default: | |
| 607 ShouldNotReachHere(); | |
| 608 } | |
| 609 break; | |
| 610 | |
| 611 case 0x81: // addl a, #32; addl r, #32 | |
| 612 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl | |
| 304 | 613 // on 32bit in the case of cmpl, the imm might be an oop |
| 0 | 614 tail_size = 4; |
| 304 | 615 debug_only(has_disp32 = true); // has both kinds of operands! |
| 0 | 616 break; |
| 617 | |
| 618 case 0x83: // addl a, #8; addl r, #8 | |
| 619 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl | |
| 304 | 620 debug_only(has_disp32 = true); // has both kinds of operands! |
| 0 | 621 tail_size = 1; |
| 622 break; | |
| 623 | |
| 624 case 0x9B: | |
| 625 switch (0xFF & *ip++) { | |
| 626 case 0xD9: // fnstcw a | |
| 304 | 627 debug_only(has_disp32 = true); |
| 0 | 628 break; |
| 629 default: | |
| 630 ShouldNotReachHere(); | |
| 631 } | |
| 632 break; | |
| 633 | |
| 634 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a | |
| 635 case REP4(0x10): // adc... | |
| 636 case REP4(0x20): // and... | |
| 637 case REP4(0x30): // xor... | |
| 638 case REP4(0x08): // or... | |
| 639 case REP4(0x18): // sbb... | |
| 640 case REP4(0x28): // sub... | |
| 304 | 641 case 0xF7: // mull a |
| 642 case 0x8D: // lea r, a | |
| 643 case 0x87: // xchg r, a | |
| 0 | 644 case REP4(0x38): // cmp... |
| 304 | 645 case 0x85: // test r, a |
| 646 debug_only(has_disp32 = true); // has both kinds of operands! | |
| 0 | 647 break; |
| 648 | |
| 649 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8 | |
| 650 case 0xC6: // movb a, #8 | |
| 651 case 0x80: // cmpb a, #8 | |
| 652 case 0x6B: // imul r, a, #8 | |
| 304 | 653 debug_only(has_disp32 = true); // has both kinds of operands! |
| 0 | 654 tail_size = 1; // the imm8 |
| 655 break; | |
| 656 | |
| 4759 | 657 case 0xC4: // VEX_3bytes |
| 658 case 0xC5: // VEX_2bytes | |
| 659 assert((UseAVX > 0), "shouldn't have VEX prefix"); | |
| 660 assert(ip == inst+1, "no prefixes allowed"); | |
| 661 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions | |
| 662 // but they have prefix 0x0F and processed when 0x0F processed above. | |
| 663 // | |
| 664 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES | |
| 665 // instructions (these instructions are not supported in 64-bit mode). | |
| 666 // To distinguish them bits [7:6] are set in the VEX second byte since | |
| 667 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set | |
| 668 // those VEX bits REX and vvvv bits are inverted. | |
| 669 // | |
| 670 // Fortunately C2 doesn't generate these instructions so we don't need | |
| 671 // to check for them in product version. | |
| 672 | |
| 673 // Check second byte | |
| 674 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions")); | |
| 675 | |
| 676 // First byte | |
| 677 if ((0xFF & *inst) == VEX_3bytes) { | |
| 678 ip++; // third byte | |
| 679 is_64bit = ((VEX_W & *ip) == VEX_W); | |
| 680 } | |
| 681 ip++; // opcode | |
| 682 // To find the end of instruction (which == end_pc_operand). | |
| 683 switch (0xFF & *ip) { | |
| 684 case 0x61: // pcmpestri r, r/a, #8 | |
| 685 case 0x70: // pshufd r, r/a, #8 | |
| 686 case 0x73: // psrldq r, #8 | |
| 687 tail_size = 1; // the imm8 | |
| 688 break; | |
| 689 default: | |
| 690 break; | |
| 691 } | |
| 692 ip++; // skip opcode | |
| 693 debug_only(has_disp32 = true); // has both kinds of operands! | |
| 694 break; | |
| 0 | 695 |
| 696 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1 | |
| 697 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl | |
| 698 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a | |
| 699 case 0xDD: // fld_d a; fst_d a; fstp_d a | |
| 700 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a | |
| 701 case 0xDF: // fild_d a; fistp_d a | |
| 702 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a | |
| 703 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a | |
| 704 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a | |
| 304 | 705 debug_only(has_disp32 = true); |
| 0 | 706 break; |
| 707 | |
| 4759 | 708 case 0xE8: // call rdisp32 |
| 709 case 0xE9: // jmp rdisp32 | |
| 710 if (which == end_pc_operand) return ip + 4; | |
| 711 assert(which == call32_operand, "call has no disp32 or imm"); | |
| 712 return ip; | |
| 713 | |
|
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714 case 0xF0: // Lock |
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715 assert(os::is_MP(), "only on MP"); |
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716 goto again_after_prefix; |
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717 |
| 0 | 718 case 0xF3: // For SSE |
| 719 case 0xF2: // For SSE2 | |
| 304 | 720 switch (0xFF & *ip++) { |
| 721 case REX: | |
| 722 case REX_B: | |
| 723 case REX_X: | |
| 724 case REX_XB: | |
| 725 case REX_R: | |
| 726 case REX_RB: | |
| 727 case REX_RX: | |
| 728 case REX_RXB: | |
| 729 case REX_W: | |
| 730 case REX_WB: | |
| 731 case REX_WX: | |
| 732 case REX_WXB: | |
| 733 case REX_WR: | |
| 734 case REX_WRB: | |
| 735 case REX_WRX: | |
| 736 case REX_WRXB: | |
| 737 NOT_LP64(assert(false, "found 64bit prefix")); | |
| 738 ip++; | |
| 739 default: | |
| 740 ip++; | |
| 741 } | |
| 742 debug_only(has_disp32 = true); // has both kinds of operands! | |
| 0 | 743 break; |
| 744 | |
| 745 default: | |
| 746 ShouldNotReachHere(); | |
| 747 | |
| 304 | 748 #undef REP8 |
| 749 #undef REP16 | |
| 0 | 750 } |
| 751 | |
| 752 assert(which != call32_operand, "instruction is not a call, jmp, or jcc"); | |
| 304 | 753 #ifdef _LP64 |
| 754 assert(which != imm_operand, "instruction is not a movq reg, imm64"); | |
| 755 #else | |
| 756 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field"); | |
| 757 assert(which != imm_operand || has_disp32, "instruction has no imm32 field"); | |
| 758 #endif // LP64 | |
| 759 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field"); | |
| 0 | 760 |
| 761 // parse the output of emit_operand | |
| 762 int op2 = 0xFF & *ip++; | |
| 763 int base = op2 & 0x07; | |
| 764 int op3 = -1; | |
| 765 const int b100 = 4; | |
| 766 const int b101 = 5; | |
| 767 if (base == b100 && (op2 >> 6) != 3) { | |
| 768 op3 = 0xFF & *ip++; | |
| 769 base = op3 & 0x07; // refetch the base | |
| 770 } | |
| 771 // now ip points at the disp (if any) | |
| 772 | |
| 773 switch (op2 >> 6) { | |
| 774 case 0: | |
| 775 // [00 reg 100][ss index base] | |
| 304 | 776 // [00 reg 100][00 100 esp] |
| 0 | 777 // [00 reg base] |
| 778 // [00 reg 100][ss index 101][disp32] | |
| 779 // [00 reg 101] [disp32] | |
| 780 | |
| 781 if (base == b101) { | |
| 782 if (which == disp32_operand) | |
| 783 return ip; // caller wants the disp32 | |
| 784 ip += 4; // skip the disp32 | |
| 785 } | |
| 786 break; | |
| 787 | |
| 788 case 1: | |
| 789 // [01 reg 100][ss index base][disp8] | |
| 304 | 790 // [01 reg 100][00 100 esp][disp8] |
| 0 | 791 // [01 reg base] [disp8] |
| 792 ip += 1; // skip the disp8 | |
| 793 break; | |
| 794 | |
| 795 case 2: | |
| 796 // [10 reg 100][ss index base][disp32] | |
| 304 | 797 // [10 reg 100][00 100 esp][disp32] |
| 0 | 798 // [10 reg base] [disp32] |
| 799 if (which == disp32_operand) | |
| 800 return ip; // caller wants the disp32 | |
| 801 ip += 4; // skip the disp32 | |
| 802 break; | |
| 803 | |
| 804 case 3: | |
| 805 // [11 reg base] (not a memory addressing mode) | |
| 806 break; | |
| 807 } | |
| 808 | |
| 809 if (which == end_pc_operand) { | |
| 810 return ip + tail_size; | |
| 811 } | |
| 812 | |
| 304 | 813 #ifdef _LP64 |
|
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814 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32"); |
| 304 | 815 #else |
| 816 assert(which == imm_operand, "instruction has only an imm field"); | |
| 817 #endif // LP64 | |
| 0 | 818 return ip; |
| 819 } | |
| 820 | |
| 821 address Assembler::locate_next_instruction(address inst) { | |
| 822 // Secretly share code with locate_operand: | |
| 823 return locate_operand(inst, end_pc_operand); | |
| 824 } | |
| 825 | |
| 826 | |
| 827 #ifdef ASSERT | |
| 828 void Assembler::check_relocation(RelocationHolder const& rspec, int format) { | |
| 829 address inst = inst_mark(); | |
| 830 assert(inst != NULL && inst < pc(), "must point to beginning of instruction"); | |
| 831 address opnd; | |
| 832 | |
| 833 Relocation* r = rspec.reloc(); | |
| 834 if (r->type() == relocInfo::none) { | |
| 835 return; | |
| 836 } else if (r->is_call() || format == call32_operand) { | |
| 837 // assert(format == imm32_operand, "cannot specify a nonzero format"); | |
| 838 opnd = locate_operand(inst, call32_operand); | |
| 839 } else if (r->is_data()) { | |
| 304 | 840 assert(format == imm_operand || format == disp32_operand |
| 841 LP64_ONLY(|| format == narrow_oop_operand), "format ok"); | |
| 0 | 842 opnd = locate_operand(inst, (WhichOperand)format); |
| 843 } else { | |
| 304 | 844 assert(format == imm_operand, "cannot specify a format"); |
| 0 | 845 return; |
| 846 } | |
| 847 assert(opnd == pc(), "must put operand where relocs can find it"); | |
| 848 } | |
| 304 | 849 #endif // ASSERT |
| 850 | |
| 851 void Assembler::emit_operand32(Register reg, Address adr) { | |
| 852 assert(reg->encoding() < 8, "no extended registers"); | |
| 853 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); | |
| 854 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |
| 855 adr._rspec); | |
| 856 } | |
| 857 | |
| 858 void Assembler::emit_operand(Register reg, Address adr, | |
| 859 int rip_relative_correction) { | |
| 860 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |
| 861 adr._rspec, | |
| 862 rip_relative_correction); | |
| 863 } | |
| 864 | |
| 865 void Assembler::emit_operand(XMMRegister reg, Address adr) { | |
| 866 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |
| 867 adr._rspec); | |
| 868 } | |
| 869 | |
| 870 // MMX operations | |
| 871 void Assembler::emit_operand(MMXRegister reg, Address adr) { | |
| 872 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); | |
| 873 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); | |
| 874 } | |
| 875 | |
| 876 // work around gcc (3.2.1-7a) bug | |
| 877 void Assembler::emit_operand(Address adr, MMXRegister reg) { | |
| 878 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); | |
| 879 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); | |
| 0 | 880 } |
| 881 | |
| 882 | |
| 883 void Assembler::emit_farith(int b1, int b2, int i) { | |
| 884 assert(isByte(b1) && isByte(b2), "wrong opcode"); | |
| 885 assert(0 <= i && i < 8, "illegal stack offset"); | |
| 886 emit_byte(b1); | |
| 887 emit_byte(b2 + i); | |
| 888 } | |
| 889 | |
| 890 | |
|
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891 // Now the Assembler instructions (identical for 32/64 bits) |
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892 |
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893 void Assembler::adcl(Address dst, int32_t imm32) { |
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894 InstructionMark im(this); |
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895 prefix(dst); |
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896 emit_arith_operand(0x81, rdx, dst, imm32); |
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897 } |
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898 |
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899 void Assembler::adcl(Address dst, Register src) { |
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900 InstructionMark im(this); |
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901 prefix(dst, src); |
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902 emit_byte(0x11); |
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903 emit_operand(src, dst); |
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7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
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2014
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changeset
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904 } |
| 304 | 905 |
| 906 void Assembler::adcl(Register dst, int32_t imm32) { | |
| 907 prefix(dst); | |
| 0 | 908 emit_arith(0x81, 0xD0, dst, imm32); |
| 909 } | |
| 910 | |
| 911 void Assembler::adcl(Register dst, Address src) { | |
| 912 InstructionMark im(this); | |
| 304 | 913 prefix(src, dst); |
| 0 | 914 emit_byte(0x13); |
| 915 emit_operand(dst, src); | |
| 916 } | |
| 917 | |
| 918 void Assembler::adcl(Register dst, Register src) { | |
| 304 | 919 (void) prefix_and_encode(dst->encoding(), src->encoding()); |
| 0 | 920 emit_arith(0x13, 0xC0, dst, src); |
| 921 } | |
| 922 | |
| 304 | 923 void Assembler::addl(Address dst, int32_t imm32) { |
| 924 InstructionMark im(this); | |
| 925 prefix(dst); | |
| 926 emit_arith_operand(0x81, rax, dst, imm32); | |
| 927 } | |
| 0 | 928 |
| 929 void Assembler::addl(Address dst, Register src) { | |
| 930 InstructionMark im(this); | |
| 304 | 931 prefix(dst, src); |
| 0 | 932 emit_byte(0x01); |
| 933 emit_operand(src, dst); | |
| 934 } | |
| 935 | |
| 304 | 936 void Assembler::addl(Register dst, int32_t imm32) { |
| 937 prefix(dst); | |
| 0 | 938 emit_arith(0x81, 0xC0, dst, imm32); |
| 939 } | |
| 940 | |
| 941 void Assembler::addl(Register dst, Address src) { | |
| 942 InstructionMark im(this); | |
| 304 | 943 prefix(src, dst); |
| 0 | 944 emit_byte(0x03); |
| 945 emit_operand(dst, src); | |
| 946 } | |
| 947 | |
| 948 void Assembler::addl(Register dst, Register src) { | |
| 304 | 949 (void) prefix_and_encode(dst->encoding(), src->encoding()); |
| 0 | 950 emit_arith(0x03, 0xC0, dst, src); |
| 951 } | |
| 952 | |
| 953 void Assembler::addr_nop_4() { | |
|
4947
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7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
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954 assert(UseAddressNop, "no CPU support"); |
| 0 | 955 // 4 bytes: NOP DWORD PTR [EAX+0] |
| 956 emit_byte(0x0F); | |
| 957 emit_byte(0x1F); | |
| 958 emit_byte(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc); | |
| 959 emit_byte(0); // 8-bits offset (1 byte) | |
| 960 } | |
| 961 | |
| 962 void Assembler::addr_nop_5() { | |
|
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963 assert(UseAddressNop, "no CPU support"); |
| 0 | 964 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset |
| 965 emit_byte(0x0F); | |
| 966 emit_byte(0x1F); | |
| 967 emit_byte(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4); | |
| 968 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); | |
| 969 emit_byte(0); // 8-bits offset (1 byte) | |
| 970 } | |
| 971 | |
| 972 void Assembler::addr_nop_7() { | |
|
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973 assert(UseAddressNop, "no CPU support"); |
| 0 | 974 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset |
| 975 emit_byte(0x0F); | |
| 976 emit_byte(0x1F); | |
| 977 emit_byte(0x80); // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc); | |
| 978 emit_long(0); // 32-bits offset (4 bytes) | |
| 979 } | |
| 980 | |
| 981 void Assembler::addr_nop_8() { | |
|
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982 assert(UseAddressNop, "no CPU support"); |
| 0 | 983 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset |
| 984 emit_byte(0x0F); | |
| 985 emit_byte(0x1F); | |
| 986 emit_byte(0x84); // emit_rm(cbuf, 0x2, EAX_enc, 0x4); | |
| 987 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); | |
| 988 emit_long(0); // 32-bits offset (4 bytes) | |
| 989 } | |
| 990 | |
| 304 | 991 void Assembler::addsd(XMMRegister dst, XMMRegister src) { |
| 992 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 993 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
| 304 | 994 emit_byte(0x58); |
| 995 emit_byte(0xC0 | encode); | |
| 996 } | |
| 997 | |
| 998 void Assembler::addsd(XMMRegister dst, Address src) { | |
| 999 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1000 InstructionMark im(this); | |
| 4759 | 1001 simd_prefix(dst, dst, src, VEX_SIMD_F2); |
| 304 | 1002 emit_byte(0x58); |
| 1003 emit_operand(dst, src); | |
| 1004 } | |
| 1005 | |
| 1006 void Assembler::addss(XMMRegister dst, XMMRegister src) { | |
| 1007 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 4759 | 1008 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); |
| 304 | 1009 emit_byte(0x58); |
| 1010 emit_byte(0xC0 | encode); | |
| 1011 } | |
| 1012 | |
| 1013 void Assembler::addss(XMMRegister dst, Address src) { | |
| 1014 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1015 InstructionMark im(this); | |
| 4759 | 1016 simd_prefix(dst, dst, src, VEX_SIMD_F3); |
| 304 | 1017 emit_byte(0x58); |
| 1018 emit_operand(dst, src); | |
| 1019 } | |
| 1020 | |
| 4759 | 1021 void Assembler::andl(Address dst, int32_t imm32) { |
| 1022 InstructionMark im(this); | |
| 1023 prefix(dst); | |
| 1024 emit_byte(0x81); | |
| 1025 emit_operand(rsp, dst, 4); | |
| 1026 emit_long(imm32); | |
| 1027 } | |
| 1028 | |
| 304 | 1029 void Assembler::andl(Register dst, int32_t imm32) { |
| 1030 prefix(dst); | |
| 1031 emit_arith(0x81, 0xE0, dst, imm32); | |
| 1032 } | |
| 1033 | |
| 1034 void Assembler::andl(Register dst, Address src) { | |
| 1035 InstructionMark im(this); | |
| 1036 prefix(src, dst); | |
| 1037 emit_byte(0x23); | |
| 1038 emit_operand(dst, src); | |
| 1039 } | |
| 1040 | |
| 1041 void Assembler::andl(Register dst, Register src) { | |
| 1042 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1043 emit_arith(0x23, 0xC0, dst, src); | |
| 1044 } | |
| 1045 | |
| 1046 void Assembler::andpd(XMMRegister dst, Address src) { | |
| 1047 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1048 InstructionMark im(this); | |
| 4759 | 1049 simd_prefix(dst, dst, src, VEX_SIMD_66); |
| 304 | 1050 emit_byte(0x54); |
| 1051 emit_operand(dst, src); | |
| 1052 } | |
| 1053 | |
| 4759 | 1054 void Assembler::andpd(XMMRegister dst, XMMRegister src) { |
| 1055 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1056 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); | |
| 1057 emit_byte(0x54); | |
| 1058 emit_byte(0xC0 | encode); | |
| 1059 } | |
| 1060 | |
| 1061 void Assembler::andps(XMMRegister dst, Address src) { | |
| 1062 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1063 InstructionMark im(this); | |
| 1064 simd_prefix(dst, dst, src, VEX_SIMD_NONE); | |
| 1065 emit_byte(0x54); | |
| 1066 emit_operand(dst, src); | |
| 1067 } | |
| 1068 | |
| 1069 void Assembler::andps(XMMRegister dst, XMMRegister src) { | |
| 1070 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1071 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE); | |
| 1072 emit_byte(0x54); | |
| 1073 emit_byte(0xC0 | encode); | |
| 1074 } | |
| 1075 | |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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diff
changeset
|
1076 void Assembler::bsfl(Register dst, Register src) { |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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710
diff
changeset
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1077 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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diff
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1078 emit_byte(0x0F); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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1079 emit_byte(0xBC); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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1080 emit_byte(0xC0 | encode); |
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93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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1081 } |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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1082 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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1083 void Assembler::bsrl(Register dst, Register src) { |
|
93c14e5562c4
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1084 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT"); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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diff
changeset
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1085 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
1086 emit_byte(0x0F); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
1087 emit_byte(0xBD); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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710
diff
changeset
|
1088 emit_byte(0xC0 | encode); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
1089 } |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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|
1090 |
| 304 | 1091 void Assembler::bswapl(Register reg) { // bswap |
| 1092 int encode = prefix_and_encode(reg->encoding()); | |
| 1093 emit_byte(0x0F); | |
| 1094 emit_byte(0xC8 | encode); | |
| 1095 } | |
| 1096 | |
| 1097 void Assembler::call(Label& L, relocInfo::relocType rtype) { | |
| 1098 // suspect disp32 is always good | |
| 1099 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand); | |
| 1100 | |
| 1101 if (L.is_bound()) { | |
| 1102 const int long_size = 5; | |
| 1103 int offs = (int)( target(L) - pc() ); | |
| 1104 assert(offs <= 0, "assembler error"); | |
| 1105 InstructionMark im(this); | |
| 1106 // 1110 1000 #32-bit disp | |
| 1107 emit_byte(0xE8); | |
| 1108 emit_data(offs - long_size, rtype, operand); | |
| 1109 } else { | |
| 1110 InstructionMark im(this); | |
| 1111 // 1110 1000 #32-bit disp | |
| 1112 L.add_patch_at(code(), locator()); | |
| 1113 | |
| 1114 emit_byte(0xE8); | |
| 1115 emit_data(int(0), rtype, operand); | |
| 1116 } | |
| 1117 } | |
| 1118 | |
| 1119 void Assembler::call(Register dst) { | |
| 4759 | 1120 int encode = prefix_and_encode(dst->encoding()); |
| 304 | 1121 emit_byte(0xFF); |
| 1122 emit_byte(0xD0 | encode); | |
| 1123 } | |
| 1124 | |
| 1125 | |
| 1126 void Assembler::call(Address adr) { | |
| 1127 InstructionMark im(this); | |
| 1128 prefix(adr); | |
| 1129 emit_byte(0xFF); | |
| 1130 emit_operand(rdx, adr); | |
| 1131 } | |
| 1132 | |
| 1133 void Assembler::call_literal(address entry, RelocationHolder const& rspec) { | |
| 1134 assert(entry != NULL, "call most probably wrong"); | |
| 1135 InstructionMark im(this); | |
| 1136 emit_byte(0xE8); | |
| 1137 intptr_t disp = entry - (_code_pos + sizeof(int32_t)); | |
| 1138 assert(is_simm32(disp), "must be 32bit offset (call2)"); | |
| 1139 // Technically, should use call32_operand, but this format is | |
| 1140 // implied by the fact that we're emitting a call instruction. | |
| 1141 | |
| 1142 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand); | |
| 1143 emit_data((int) disp, rspec, operand); | |
| 1144 } | |
| 1145 | |
| 1146 void Assembler::cdql() { | |
| 1147 emit_byte(0x99); | |
| 1148 } | |
| 1149 | |
| 1150 void Assembler::cmovl(Condition cc, Register dst, Register src) { | |
| 1151 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); | |
| 1152 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1153 emit_byte(0x0F); | |
| 1154 emit_byte(0x40 | cc); | |
| 1155 emit_byte(0xC0 | encode); | |
| 1156 } | |
| 1157 | |
| 1158 | |
| 1159 void Assembler::cmovl(Condition cc, Register dst, Address src) { | |
| 1160 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); | |
| 1161 prefix(src, dst); | |
| 1162 emit_byte(0x0F); | |
| 1163 emit_byte(0x40 | cc); | |
| 1164 emit_operand(dst, src); | |
| 1165 } | |
| 1166 | |
| 1167 void Assembler::cmpb(Address dst, int imm8) { | |
| 1168 InstructionMark im(this); | |
| 1169 prefix(dst); | |
| 1170 emit_byte(0x80); | |
| 1171 emit_operand(rdi, dst, 1); | |
| 1172 emit_byte(imm8); | |
| 1173 } | |
| 1174 | |
| 1175 void Assembler::cmpl(Address dst, int32_t imm32) { | |
| 1176 InstructionMark im(this); | |
| 1177 prefix(dst); | |
| 1178 emit_byte(0x81); | |
| 1179 emit_operand(rdi, dst, 4); | |
| 1180 emit_long(imm32); | |
| 1181 } | |
| 1182 | |
| 1183 void Assembler::cmpl(Register dst, int32_t imm32) { | |
| 1184 prefix(dst); | |
| 1185 emit_arith(0x81, 0xF8, dst, imm32); | |
| 1186 } | |
| 1187 | |
| 1188 void Assembler::cmpl(Register dst, Register src) { | |
| 1189 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1190 emit_arith(0x3B, 0xC0, dst, src); | |
| 1191 } | |
| 1192 | |
| 1193 | |
| 1194 void Assembler::cmpl(Register dst, Address src) { | |
| 1195 InstructionMark im(this); | |
| 1196 prefix(src, dst); | |
| 1197 emit_byte(0x3B); | |
| 1198 emit_operand(dst, src); | |
| 1199 } | |
| 1200 | |
| 1201 void Assembler::cmpw(Address dst, int imm16) { | |
| 1202 InstructionMark im(this); | |
| 1203 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers"); | |
| 1204 emit_byte(0x66); | |
| 1205 emit_byte(0x81); | |
| 1206 emit_operand(rdi, dst, 2); | |
| 1207 emit_word(imm16); | |
| 1208 } | |
| 1209 | |
| 1210 // The 32-bit cmpxchg compares the value at adr with the contents of rax, | |
| 1211 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,. | |
| 1212 // The ZF is set if the compared values were equal, and cleared otherwise. | |
| 1213 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg | |
| 1214 if (Atomics & 2) { | |
| 1215 // caveat: no instructionmark, so this isn't relocatable. | |
| 1216 // Emit a synthetic, non-atomic, CAS equivalent. | |
| 1217 // Beware. The synthetic form sets all ICCs, not just ZF. | |
| 1218 // cmpxchg r,[m] is equivalent to rax, = CAS (m, rax, r) | |
| 1219 cmpl(rax, adr); | |
| 1220 movl(rax, adr); | |
| 1221 if (reg != rax) { | |
| 1222 Label L ; | |
| 1223 jcc(Assembler::notEqual, L); | |
| 1224 movl(adr, reg); | |
| 1225 bind(L); | |
| 1226 } | |
| 1227 } else { | |
| 1228 InstructionMark im(this); | |
| 1229 prefix(adr, reg); | |
| 1230 emit_byte(0x0F); | |
| 1231 emit_byte(0xB1); | |
| 1232 emit_operand(reg, adr); | |
| 1233 } | |
| 1234 } | |
| 1235 | |
| 1236 void Assembler::comisd(XMMRegister dst, Address src) { | |
| 1237 // NOTE: dbx seems to decode this as comiss even though the | |
| 1238 // 0x66 is there. Strangly ucomisd comes out correct | |
| 1239 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 1240 InstructionMark im(this); |
| 1241 simd_prefix(dst, src, VEX_SIMD_66); | |
| 1242 emit_byte(0x2F); | |
| 1243 emit_operand(dst, src); | |
| 1244 } | |
| 1245 | |
| 1246 void Assembler::comisd(XMMRegister dst, XMMRegister src) { | |
| 1247 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1248 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); | |
| 1249 emit_byte(0x2F); | |
| 1250 emit_byte(0xC0 | encode); | |
| 304 | 1251 } |
| 1252 | |
| 1253 void Assembler::comiss(XMMRegister dst, Address src) { | |
| 1254 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 4759 | 1255 InstructionMark im(this); |
| 1256 simd_prefix(dst, src, VEX_SIMD_NONE); | |
| 304 | 1257 emit_byte(0x2F); |
| 1258 emit_operand(dst, src); | |
| 1259 } | |
| 1260 | |
| 4759 | 1261 void Assembler::comiss(XMMRegister dst, XMMRegister src) { |
| 1262 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1263 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE); | |
| 1264 emit_byte(0x2F); | |
| 1265 emit_byte(0xC0 | encode); | |
| 1266 } | |
| 1267 | |
| 304 | 1268 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) { |
| 1269 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 1270 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3); |
| 304 | 1271 emit_byte(0xE6); |
| 1272 emit_byte(0xC0 | encode); | |
| 1273 } | |
| 1274 | |
| 1275 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) { | |
| 1276 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 1277 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE); |
| 304 | 1278 emit_byte(0x5B); |
| 1279 emit_byte(0xC0 | encode); | |
| 1280 } | |
| 1281 | |
| 1282 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) { | |
| 1283 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 1284 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
| 304 | 1285 emit_byte(0x5A); |
| 1286 emit_byte(0xC0 | encode); | |
| 1287 } | |
| 1288 | |
| 4759 | 1289 void Assembler::cvtsd2ss(XMMRegister dst, Address src) { |
| 1290 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1291 InstructionMark im(this); | |
| 1292 simd_prefix(dst, dst, src, VEX_SIMD_F2); | |
| 1293 emit_byte(0x5A); | |
| 1294 emit_operand(dst, src); | |
| 1295 } | |
| 1296 | |
| 304 | 1297 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) { |
| 1298 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 1299 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
| 304 | 1300 emit_byte(0x2A); |
| 1301 emit_byte(0xC0 | encode); | |
| 1302 } | |
| 1303 | |
| 4759 | 1304 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) { |
| 1305 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1306 InstructionMark im(this); | |
| 1307 simd_prefix(dst, dst, src, VEX_SIMD_F2); | |
| 1308 emit_byte(0x2A); | |
| 1309 emit_operand(dst, src); | |
| 1310 } | |
| 1311 | |
| 304 | 1312 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) { |
| 1313 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 4759 | 1314 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); |
| 304 | 1315 emit_byte(0x2A); |
| 1316 emit_byte(0xC0 | encode); | |
| 1317 } | |
| 1318 | |
| 4759 | 1319 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) { |
| 1320 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1321 InstructionMark im(this); | |
| 1322 simd_prefix(dst, dst, src, VEX_SIMD_F3); | |
| 1323 emit_byte(0x2A); | |
| 1324 emit_operand(dst, src); | |
| 1325 } | |
| 1326 | |
| 304 | 1327 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) { |
| 1328 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 1329 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); |
| 304 | 1330 emit_byte(0x5A); |
| 1331 emit_byte(0xC0 | encode); | |
| 1332 } | |
| 1333 | |
| 4759 | 1334 void Assembler::cvtss2sd(XMMRegister dst, Address src) { |
| 1335 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1336 InstructionMark im(this); | |
| 1337 simd_prefix(dst, dst, src, VEX_SIMD_F3); | |
| 1338 emit_byte(0x5A); | |
| 1339 emit_operand(dst, src); | |
| 1340 } | |
| 1341 | |
| 1342 | |
| 304 | 1343 void Assembler::cvttsd2sil(Register dst, XMMRegister src) { |
| 1344 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 1345 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2); |
| 304 | 1346 emit_byte(0x2C); |
| 1347 emit_byte(0xC0 | encode); | |
| 1348 } | |
| 1349 | |
| 1350 void Assembler::cvttss2sil(Register dst, XMMRegister src) { | |
| 1351 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 4759 | 1352 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3); |
| 304 | 1353 emit_byte(0x2C); |
| 1354 emit_byte(0xC0 | encode); | |
| 1355 } | |
| 1356 | |
| 1357 void Assembler::decl(Address dst) { | |
| 1358 // Don't use it directly. Use MacroAssembler::decrement() instead. | |
| 1359 InstructionMark im(this); | |
| 1360 prefix(dst); | |
| 1361 emit_byte(0xFF); | |
| 1362 emit_operand(rcx, dst); | |
| 1363 } | |
| 1364 | |
| 1365 void Assembler::divsd(XMMRegister dst, Address src) { | |
| 1366 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1367 InstructionMark im(this); | |
| 4759 | 1368 simd_prefix(dst, dst, src, VEX_SIMD_F2); |
| 304 | 1369 emit_byte(0x5E); |
| 1370 emit_operand(dst, src); | |
| 1371 } | |
| 1372 | |
| 1373 void Assembler::divsd(XMMRegister dst, XMMRegister src) { | |
| 1374 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 1375 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
| 304 | 1376 emit_byte(0x5E); |
| 1377 emit_byte(0xC0 | encode); | |
| 1378 } | |
| 1379 | |
| 1380 void Assembler::divss(XMMRegister dst, Address src) { | |
| 1381 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1382 InstructionMark im(this); | |
| 4759 | 1383 simd_prefix(dst, dst, src, VEX_SIMD_F3); |
| 304 | 1384 emit_byte(0x5E); |
| 1385 emit_operand(dst, src); | |
| 1386 } | |
| 1387 | |
| 1388 void Assembler::divss(XMMRegister dst, XMMRegister src) { | |
| 1389 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 4759 | 1390 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); |
| 304 | 1391 emit_byte(0x5E); |
| 1392 emit_byte(0xC0 | encode); | |
| 1393 } | |
| 1394 | |
| 1395 void Assembler::emms() { | |
| 1396 NOT_LP64(assert(VM_Version::supports_mmx(), "")); | |
| 1397 emit_byte(0x0F); | |
| 1398 emit_byte(0x77); | |
| 1399 } | |
| 1400 | |
| 1401 void Assembler::hlt() { | |
| 1402 emit_byte(0xF4); | |
| 1403 } | |
| 1404 | |
| 1405 void Assembler::idivl(Register src) { | |
| 1406 int encode = prefix_and_encode(src->encoding()); | |
| 1407 emit_byte(0xF7); | |
| 1408 emit_byte(0xF8 | encode); | |
| 1409 } | |
| 1410 | |
| 1920 | 1411 void Assembler::divl(Register src) { // Unsigned |
| 1412 int encode = prefix_and_encode(src->encoding()); | |
| 1413 emit_byte(0xF7); | |
| 1414 emit_byte(0xF0 | encode); | |
| 1415 } | |
| 1416 | |
| 304 | 1417 void Assembler::imull(Register dst, Register src) { |
| 1418 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1419 emit_byte(0x0F); | |
| 1420 emit_byte(0xAF); | |
| 1421 emit_byte(0xC0 | encode); | |
| 1422 } | |
| 1423 | |
| 1424 | |
| 1425 void Assembler::imull(Register dst, Register src, int value) { | |
| 1426 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1427 if (is8bit(value)) { | |
| 1428 emit_byte(0x6B); | |
| 1429 emit_byte(0xC0 | encode); | |
|
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1430 emit_byte(value & 0xFF); |
| 304 | 1431 } else { |
| 1432 emit_byte(0x69); | |
| 1433 emit_byte(0xC0 | encode); | |
| 1434 emit_long(value); | |
| 1435 } | |
| 1436 } | |
| 1437 | |
| 1438 void Assembler::incl(Address dst) { | |
| 1439 // Don't use it directly. Use MacroAssembler::increment() instead. | |
| 1440 InstructionMark im(this); | |
| 1441 prefix(dst); | |
| 1442 emit_byte(0xFF); | |
| 1443 emit_operand(rax, dst); | |
| 1444 } | |
| 1445 | |
| 3851 | 1446 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) { |
| 1447 InstructionMark im(this); | |
| 304 | 1448 assert((0 <= cc) && (cc < 16), "illegal cc"); |
| 1449 if (L.is_bound()) { | |
| 1450 address dst = target(L); | |
| 1451 assert(dst != NULL, "jcc most probably wrong"); | |
| 1452 | |
| 1453 const int short_size = 2; | |
| 1454 const int long_size = 6; | |
| 1455 intptr_t offs = (intptr_t)dst - (intptr_t)_code_pos; | |
| 3851 | 1456 if (maybe_short && is8bit(offs - short_size)) { |
| 304 | 1457 // 0111 tttn #8-bit disp |
| 1458 emit_byte(0x70 | cc); | |
| 1459 emit_byte((offs - short_size) & 0xFF); | |
| 1460 } else { | |
| 1461 // 0000 1111 1000 tttn #32-bit disp | |
| 1462 assert(is_simm32(offs - long_size), | |
| 1463 "must be 32bit offset (call4)"); | |
| 1464 emit_byte(0x0F); | |
| 1465 emit_byte(0x80 | cc); | |
| 1466 emit_long(offs - long_size); | |
| 1467 } | |
| 1468 } else { | |
| 1469 // Note: could eliminate cond. jumps to this jump if condition | |
| 1470 // is the same however, seems to be rather unlikely case. | |
| 1471 // Note: use jccb() if label to be bound is very close to get | |
| 1472 // an 8-bit displacement | |
| 1473 L.add_patch_at(code(), locator()); | |
| 1474 emit_byte(0x0F); | |
| 1475 emit_byte(0x80 | cc); | |
| 1476 emit_long(0); | |
| 1477 } | |
| 1478 } | |
| 1479 | |
| 1480 void Assembler::jccb(Condition cc, Label& L) { | |
| 1481 if (L.is_bound()) { | |
| 1482 const int short_size = 2; | |
| 1483 address entry = target(L); | |
|
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1484 #ifdef ASSERT |
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1485 intptr_t dist = (intptr_t)entry - ((intptr_t)_code_pos + short_size); |
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1486 intptr_t delta = short_branch_delta(); |
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1487 if (delta != 0) { |
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1488 dist += (dist < 0 ? (-delta) :delta); |
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1489 } |
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1490 assert(is8bit(dist), "Dispacement too large for a short jmp"); |
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1491 #endif |
| 304 | 1492 intptr_t offs = (intptr_t)entry - (intptr_t)_code_pos; |
| 1493 // 0111 tttn #8-bit disp | |
| 1494 emit_byte(0x70 | cc); | |
| 1495 emit_byte((offs - short_size) & 0xFF); | |
| 1496 } else { | |
| 1497 InstructionMark im(this); | |
| 1498 L.add_patch_at(code(), locator()); | |
| 1499 emit_byte(0x70 | cc); | |
| 1500 emit_byte(0); | |
| 1501 } | |
| 1502 } | |
| 1503 | |
| 1504 void Assembler::jmp(Address adr) { | |
| 1505 InstructionMark im(this); | |
| 1506 prefix(adr); | |
| 1507 emit_byte(0xFF); | |
| 1508 emit_operand(rsp, adr); | |
| 1509 } | |
| 1510 | |
| 3851 | 1511 void Assembler::jmp(Label& L, bool maybe_short) { |
| 304 | 1512 if (L.is_bound()) { |
| 1513 address entry = target(L); | |
| 1514 assert(entry != NULL, "jmp most probably wrong"); | |
| 1515 InstructionMark im(this); | |
| 1516 const int short_size = 2; | |
| 1517 const int long_size = 5; | |
| 1518 intptr_t offs = entry - _code_pos; | |
| 3851 | 1519 if (maybe_short && is8bit(offs - short_size)) { |
| 304 | 1520 emit_byte(0xEB); |
| 1521 emit_byte((offs - short_size) & 0xFF); | |
| 1522 } else { | |
| 1523 emit_byte(0xE9); | |
| 1524 emit_long(offs - long_size); | |
| 1525 } | |
| 1526 } else { | |
| 1527 // By default, forward jumps are always 32-bit displacements, since | |
| 1528 // we can't yet know where the label will be bound. If you're sure that | |
| 1529 // the forward jump will not run beyond 256 bytes, use jmpb to | |
| 1530 // force an 8-bit displacement. | |
| 1531 InstructionMark im(this); | |
| 1532 L.add_patch_at(code(), locator()); | |
| 1533 emit_byte(0xE9); | |
| 1534 emit_long(0); | |
| 1535 } | |
| 1536 } | |
| 1537 | |
| 1538 void Assembler::jmp(Register entry) { | |
| 1539 int encode = prefix_and_encode(entry->encoding()); | |
| 1540 emit_byte(0xFF); | |
| 1541 emit_byte(0xE0 | encode); | |
| 1542 } | |
| 1543 | |
| 1544 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) { | |
| 1545 InstructionMark im(this); | |
| 1546 emit_byte(0xE9); | |
| 1547 assert(dest != NULL, "must have a target"); | |
| 1548 intptr_t disp = dest - (_code_pos + sizeof(int32_t)); | |
| 1549 assert(is_simm32(disp), "must be 32bit offset (jmp)"); | |
| 1550 emit_data(disp, rspec.reloc(), call32_operand); | |
| 1551 } | |
| 1552 | |
| 1553 void Assembler::jmpb(Label& L) { | |
| 1554 if (L.is_bound()) { | |
| 1555 const int short_size = 2; | |
| 1556 address entry = target(L); | |
| 1557 assert(entry != NULL, "jmp most probably wrong"); | |
|
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1558 #ifdef ASSERT |
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1559 intptr_t dist = (intptr_t)entry - ((intptr_t)_code_pos + short_size); |
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1560 intptr_t delta = short_branch_delta(); |
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1561 if (delta != 0) { |
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1562 dist += (dist < 0 ? (-delta) :delta); |
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1563 } |
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1564 assert(is8bit(dist), "Dispacement too large for a short jmp"); |
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1565 #endif |
| 304 | 1566 intptr_t offs = entry - _code_pos; |
| 1567 emit_byte(0xEB); | |
| 1568 emit_byte((offs - short_size) & 0xFF); | |
| 1569 } else { | |
| 1570 InstructionMark im(this); | |
| 1571 L.add_patch_at(code(), locator()); | |
| 1572 emit_byte(0xEB); | |
| 1573 emit_byte(0); | |
| 1574 } | |
| 1575 } | |
| 1576 | |
| 1577 void Assembler::ldmxcsr( Address src) { | |
| 1578 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1579 InstructionMark im(this); | |
| 1580 prefix(src); | |
| 1581 emit_byte(0x0F); | |
| 1582 emit_byte(0xAE); | |
| 1583 emit_operand(as_Register(2), src); | |
| 1584 } | |
| 1585 | |
| 1586 void Assembler::leal(Register dst, Address src) { | |
| 1587 InstructionMark im(this); | |
| 1588 #ifdef _LP64 | |
| 1589 emit_byte(0x67); // addr32 | |
| 1590 prefix(src, dst); | |
| 1591 #endif // LP64 | |
| 1592 emit_byte(0x8D); | |
| 1593 emit_operand(dst, src); | |
| 1594 } | |
| 1595 | |
| 1596 void Assembler::lock() { | |
| 1597 if (Atomics & 1) { | |
| 1598 // Emit either nothing, a NOP, or a NOP: prefix | |
| 1599 emit_byte(0x90) ; | |
| 1600 } else { | |
| 1601 emit_byte(0xF0); | |
| 1602 } | |
| 1603 } | |
| 1604 | |
|
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1605 void Assembler::lzcntl(Register dst, Register src) { |
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1606 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); |
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1607 emit_byte(0xF3); |
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1608 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
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1609 emit_byte(0x0F); |
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1610 emit_byte(0xBD); |
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1611 emit_byte(0xC0 | encode); |
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1612 } |
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1613 |
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1614 // Emit mfence instruction |
| 304 | 1615 void Assembler::mfence() { |
|
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1616 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");) |
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1617 emit_byte( 0x0F ); |
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1618 emit_byte( 0xAE ); |
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1619 emit_byte( 0xF0 ); |
| 304 | 1620 } |
| 1621 | |
| 1622 void Assembler::mov(Register dst, Register src) { | |
| 1623 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
| 1624 } | |
| 1625 | |
| 1626 void Assembler::movapd(XMMRegister dst, XMMRegister src) { | |
| 1627 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 1628 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); |
| 304 | 1629 emit_byte(0x28); |
| 4759 | 1630 emit_byte(0xC0 | encode); |
| 304 | 1631 } |
| 1632 | |
| 1633 void Assembler::movaps(XMMRegister dst, XMMRegister src) { | |
| 1634 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 4759 | 1635 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE); |
| 304 | 1636 emit_byte(0x28); |
| 4759 | 1637 emit_byte(0xC0 | encode); |
| 304 | 1638 } |
| 1639 | |
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1640 void Assembler::movlhps(XMMRegister dst, XMMRegister src) { |
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1641 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
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1642 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE); |
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1643 emit_byte(0x16); |
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1644 emit_byte(0xC0 | encode); |
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1645 } |
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1646 |
| 304 | 1647 void Assembler::movb(Register dst, Address src) { |
| 1648 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); | |
| 1649 InstructionMark im(this); | |
| 1650 prefix(src, dst, true); | |
| 1651 emit_byte(0x8A); | |
| 1652 emit_operand(dst, src); | |
| 1653 } | |
| 1654 | |
| 1655 | |
| 1656 void Assembler::movb(Address dst, int imm8) { | |
| 1657 InstructionMark im(this); | |
| 1658 prefix(dst); | |
| 1659 emit_byte(0xC6); | |
| 1660 emit_operand(rax, dst, 1); | |
| 1661 emit_byte(imm8); | |
| 1662 } | |
| 1663 | |
| 1664 | |
| 1665 void Assembler::movb(Address dst, Register src) { | |
| 1666 assert(src->has_byte_register(), "must have byte register"); | |
| 1667 InstructionMark im(this); | |
| 1668 prefix(dst, src, true); | |
| 1669 emit_byte(0x88); | |
| 1670 emit_operand(src, dst); | |
| 1671 } | |
| 1672 | |
| 1673 void Assembler::movdl(XMMRegister dst, Register src) { | |
| 1674 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 1675 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); |
| 304 | 1676 emit_byte(0x6E); |
| 1677 emit_byte(0xC0 | encode); | |
| 1678 } | |
| 1679 | |
| 1680 void Assembler::movdl(Register dst, XMMRegister src) { | |
| 1681 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1682 // swap src/dst to get correct prefix | |
| 4759 | 1683 int encode = simd_prefix_and_encode(src, dst, VEX_SIMD_66); |
| 304 | 1684 emit_byte(0x7E); |
| 1685 emit_byte(0xC0 | encode); | |
| 1686 } | |
| 1687 | |
|
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1688 void Assembler::movdl(XMMRegister dst, Address src) { |
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1689 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
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1690 InstructionMark im(this); |
| 4759 | 1691 simd_prefix(dst, src, VEX_SIMD_66); |
|
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1692 emit_byte(0x6E); |
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1693 emit_operand(dst, src); |
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1694 } |
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1695 |
|
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1696 void Assembler::movdl(Address dst, XMMRegister src) { |
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1697 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
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1698 InstructionMark im(this); |
|
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1699 simd_prefix(dst, src, VEX_SIMD_66); |
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1700 emit_byte(0x7E); |
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1701 emit_operand(src, dst); |
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1702 } |
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1703 |
| 304 | 1704 void Assembler::movdqa(XMMRegister dst, XMMRegister src) { |
| 1705 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 1706 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); |
| 304 | 1707 emit_byte(0x6F); |
| 1708 emit_byte(0xC0 | encode); | |
| 1709 } | |
| 1710 | |
| 405 | 1711 void Assembler::movdqu(XMMRegister dst, Address src) { |
| 1712 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1713 InstructionMark im(this); | |
| 4759 | 1714 simd_prefix(dst, src, VEX_SIMD_F3); |
| 405 | 1715 emit_byte(0x6F); |
| 1716 emit_operand(dst, src); | |
| 1717 } | |
| 1718 | |
| 1719 void Assembler::movdqu(XMMRegister dst, XMMRegister src) { | |
| 1720 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 1721 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3); |
| 405 | 1722 emit_byte(0x6F); |
| 1723 emit_byte(0xC0 | encode); | |
| 1724 } | |
| 1725 | |
| 1726 void Assembler::movdqu(Address dst, XMMRegister src) { | |
| 1727 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1728 InstructionMark im(this); | |
| 4759 | 1729 simd_prefix(dst, src, VEX_SIMD_F3); |
| 405 | 1730 emit_byte(0x7F); |
| 1731 emit_operand(src, dst); | |
| 1732 } | |
| 1733 | |
|
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1734 // Move Unaligned 256bit Vector |
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1735 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) { |
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1736 assert(UseAVX, ""); |
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1737 bool vector256 = true; |
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1738 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, vector256); |
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1739 emit_byte(0x6F); |
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1740 emit_byte(0xC0 | encode); |
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1741 } |
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1742 |
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1743 void Assembler::vmovdqu(XMMRegister dst, Address src) { |
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1744 assert(UseAVX, ""); |
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1745 InstructionMark im(this); |
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1746 bool vector256 = true; |
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1747 vex_prefix(dst, xnoreg, src, VEX_SIMD_F3, vector256); |
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1748 emit_byte(0x6F); |
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1749 emit_operand(dst, src); |
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1750 } |
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1751 |
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1752 void Assembler::vmovdqu(Address dst, XMMRegister src) { |
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1753 assert(UseAVX, ""); |
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1754 InstructionMark im(this); |
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1755 bool vector256 = true; |
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1756 // swap src<->dst for encoding |
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1757 assert(src != xnoreg, "sanity"); |
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1758 vex_prefix(src, xnoreg, dst, VEX_SIMD_F3, vector256); |
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1759 emit_byte(0x7F); |
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1760 emit_operand(src, dst); |
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1761 } |
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1762 |
| 304 | 1763 // Uses zero extension on 64bit |
| 1764 | |
| 1765 void Assembler::movl(Register dst, int32_t imm32) { | |
| 1766 int encode = prefix_and_encode(dst->encoding()); | |
| 1767 emit_byte(0xB8 | encode); | |
| 1768 emit_long(imm32); | |
| 1769 } | |
| 1770 | |
| 1771 void Assembler::movl(Register dst, Register src) { | |
| 1772 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1773 emit_byte(0x8B); | |
| 1774 emit_byte(0xC0 | encode); | |
| 1775 } | |
| 1776 | |
| 1777 void Assembler::movl(Register dst, Address src) { | |
| 1778 InstructionMark im(this); | |
| 1779 prefix(src, dst); | |
| 1780 emit_byte(0x8B); | |
| 1781 emit_operand(dst, src); | |
| 1782 } | |
| 1783 | |
| 1784 void Assembler::movl(Address dst, int32_t imm32) { | |
| 1785 InstructionMark im(this); | |
| 1786 prefix(dst); | |
| 1787 emit_byte(0xC7); | |
| 1788 emit_operand(rax, dst, 4); | |
| 1789 emit_long(imm32); | |
| 1790 } | |
| 1791 | |
| 1792 void Assembler::movl(Address dst, Register src) { | |
| 1793 InstructionMark im(this); | |
| 1794 prefix(dst, src); | |
| 1795 emit_byte(0x89); | |
| 1796 emit_operand(src, dst); | |
| 1797 } | |
| 1798 | |
| 1799 // New cpus require to use movsd and movss to avoid partial register stall | |
| 1800 // when loading from memory. But for old Opteron use movlpd instead of movsd. | |
| 1801 // The selection is done in MacroAssembler::movdbl() and movflt(). | |
| 1802 void Assembler::movlpd(XMMRegister dst, Address src) { | |
| 1803 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1804 InstructionMark im(this); | |
| 4759 | 1805 simd_prefix(dst, dst, src, VEX_SIMD_66); |
| 304 | 1806 emit_byte(0x12); |
| 1807 emit_operand(dst, src); | |
| 1808 } | |
| 1809 | |
| 1810 void Assembler::movq( MMXRegister dst, Address src ) { | |
| 1811 assert( VM_Version::supports_mmx(), "" ); | |
| 1812 emit_byte(0x0F); | |
| 1813 emit_byte(0x6F); | |
| 1814 emit_operand(dst, src); | |
| 1815 } | |
| 1816 | |
| 1817 void Assembler::movq( Address dst, MMXRegister src ) { | |
| 1818 assert( VM_Version::supports_mmx(), "" ); | |
| 1819 emit_byte(0x0F); | |
| 1820 emit_byte(0x7F); | |
| 1821 // workaround gcc (3.2.1-7a) bug | |
| 1822 // In that version of gcc with only an emit_operand(MMX, Address) | |
| 1823 // gcc will tail jump and try and reverse the parameters completely | |
| 1824 // obliterating dst in the process. By having a version available | |
| 1825 // that doesn't need to swap the args at the tail jump the bug is | |
| 1826 // avoided. | |
| 1827 emit_operand(dst, src); | |
| 1828 } | |
| 1829 | |
| 1830 void Assembler::movq(XMMRegister dst, Address src) { | |
| 1831 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1832 InstructionMark im(this); | |
| 4759 | 1833 simd_prefix(dst, src, VEX_SIMD_F3); |
| 304 | 1834 emit_byte(0x7E); |
| 1835 emit_operand(dst, src); | |
| 1836 } | |
| 1837 | |
| 1838 void Assembler::movq(Address dst, XMMRegister src) { | |
| 1839 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1840 InstructionMark im(this); | |
| 4759 | 1841 simd_prefix(dst, src, VEX_SIMD_66); |
| 304 | 1842 emit_byte(0xD6); |
| 1843 emit_operand(src, dst); | |
| 1844 } | |
| 1845 | |
| 1846 void Assembler::movsbl(Register dst, Address src) { // movsxb | |
| 1847 InstructionMark im(this); | |
| 1848 prefix(src, dst); | |
| 1849 emit_byte(0x0F); | |
| 1850 emit_byte(0xBE); | |
| 1851 emit_operand(dst, src); | |
| 1852 } | |
| 1853 | |
| 1854 void Assembler::movsbl(Register dst, Register src) { // movsxb | |
| 1855 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); | |
| 1856 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true); | |
| 1857 emit_byte(0x0F); | |
| 1858 emit_byte(0xBE); | |
| 1859 emit_byte(0xC0 | encode); | |
| 1860 } | |
| 1861 | |
| 1862 void Assembler::movsd(XMMRegister dst, XMMRegister src) { | |
| 1863 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 1864 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
| 304 | 1865 emit_byte(0x10); |
| 1866 emit_byte(0xC0 | encode); | |
| 1867 } | |
| 1868 | |
| 1869 void Assembler::movsd(XMMRegister dst, Address src) { | |
| 1870 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1871 InstructionMark im(this); | |
| 4759 | 1872 simd_prefix(dst, src, VEX_SIMD_F2); |
| 304 | 1873 emit_byte(0x10); |
| 1874 emit_operand(dst, src); | |
| 1875 } | |
| 1876 | |
| 1877 void Assembler::movsd(Address dst, XMMRegister src) { | |
| 1878 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1879 InstructionMark im(this); | |
| 4759 | 1880 simd_prefix(dst, src, VEX_SIMD_F2); |
| 304 | 1881 emit_byte(0x11); |
| 1882 emit_operand(src, dst); | |
| 1883 } | |
| 1884 | |
| 1885 void Assembler::movss(XMMRegister dst, XMMRegister src) { | |
| 1886 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 4759 | 1887 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); |
| 304 | 1888 emit_byte(0x10); |
| 1889 emit_byte(0xC0 | encode); | |
| 1890 } | |
| 1891 | |
| 1892 void Assembler::movss(XMMRegister dst, Address src) { | |
| 1893 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1894 InstructionMark im(this); | |
| 4759 | 1895 simd_prefix(dst, src, VEX_SIMD_F3); |
| 304 | 1896 emit_byte(0x10); |
| 1897 emit_operand(dst, src); | |
| 1898 } | |
| 1899 | |
| 1900 void Assembler::movss(Address dst, XMMRegister src) { | |
| 1901 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1902 InstructionMark im(this); | |
| 4759 | 1903 simd_prefix(dst, src, VEX_SIMD_F3); |
| 304 | 1904 emit_byte(0x11); |
| 1905 emit_operand(src, dst); | |
| 1906 } | |
| 1907 | |
| 1908 void Assembler::movswl(Register dst, Address src) { // movsxw | |
| 1909 InstructionMark im(this); | |
| 1910 prefix(src, dst); | |
| 1911 emit_byte(0x0F); | |
| 1912 emit_byte(0xBF); | |
| 1913 emit_operand(dst, src); | |
| 1914 } | |
| 1915 | |
| 1916 void Assembler::movswl(Register dst, Register src) { // movsxw | |
| 1917 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1918 emit_byte(0x0F); | |
| 1919 emit_byte(0xBF); | |
| 1920 emit_byte(0xC0 | encode); | |
| 1921 } | |
| 1922 | |
| 1923 void Assembler::movw(Address dst, int imm16) { | |
| 1924 InstructionMark im(this); | |
| 1925 | |
| 1926 emit_byte(0x66); // switch to 16-bit mode | |
| 1927 prefix(dst); | |
| 1928 emit_byte(0xC7); | |
| 1929 emit_operand(rax, dst, 2); | |
| 1930 emit_word(imm16); | |
| 1931 } | |
| 1932 | |
| 1933 void Assembler::movw(Register dst, Address src) { | |
| 1934 InstructionMark im(this); | |
| 1935 emit_byte(0x66); | |
| 1936 prefix(src, dst); | |
| 1937 emit_byte(0x8B); | |
| 1938 emit_operand(dst, src); | |
| 1939 } | |
| 1940 | |
| 1941 void Assembler::movw(Address dst, Register src) { | |
| 1942 InstructionMark im(this); | |
| 1943 emit_byte(0x66); | |
| 1944 prefix(dst, src); | |
| 1945 emit_byte(0x89); | |
| 1946 emit_operand(src, dst); | |
| 1947 } | |
| 1948 | |
| 1949 void Assembler::movzbl(Register dst, Address src) { // movzxb | |
| 1950 InstructionMark im(this); | |
| 1951 prefix(src, dst); | |
| 1952 emit_byte(0x0F); | |
| 1953 emit_byte(0xB6); | |
| 1954 emit_operand(dst, src); | |
| 1955 } | |
| 1956 | |
| 1957 void Assembler::movzbl(Register dst, Register src) { // movzxb | |
| 1958 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); | |
| 1959 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true); | |
| 1960 emit_byte(0x0F); | |
| 1961 emit_byte(0xB6); | |
| 1962 emit_byte(0xC0 | encode); | |
| 1963 } | |
| 1964 | |
| 1965 void Assembler::movzwl(Register dst, Address src) { // movzxw | |
| 1966 InstructionMark im(this); | |
| 1967 prefix(src, dst); | |
| 1968 emit_byte(0x0F); | |
| 1969 emit_byte(0xB7); | |
| 1970 emit_operand(dst, src); | |
| 1971 } | |
| 1972 | |
| 1973 void Assembler::movzwl(Register dst, Register src) { // movzxw | |
| 1974 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1975 emit_byte(0x0F); | |
| 1976 emit_byte(0xB7); | |
| 1977 emit_byte(0xC0 | encode); | |
| 1978 } | |
| 1979 | |
| 1980 void Assembler::mull(Address src) { | |
| 1981 InstructionMark im(this); | |
| 1982 prefix(src); | |
| 1983 emit_byte(0xF7); | |
| 1984 emit_operand(rsp, src); | |
| 1985 } | |
| 1986 | |
| 1987 void Assembler::mull(Register src) { | |
| 1988 int encode = prefix_and_encode(src->encoding()); | |
| 1989 emit_byte(0xF7); | |
| 1990 emit_byte(0xE0 | encode); | |
| 1991 } | |
| 1992 | |
| 1993 void Assembler::mulsd(XMMRegister dst, Address src) { | |
| 1994 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1995 InstructionMark im(this); | |
| 4759 | 1996 simd_prefix(dst, dst, src, VEX_SIMD_F2); |
| 304 | 1997 emit_byte(0x59); |
| 1998 emit_operand(dst, src); | |
| 1999 } | |
| 2000 | |
| 2001 void Assembler::mulsd(XMMRegister dst, XMMRegister src) { | |
| 2002 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 2003 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
| 304 | 2004 emit_byte(0x59); |
| 2005 emit_byte(0xC0 | encode); | |
| 2006 } | |
| 2007 | |
| 2008 void Assembler::mulss(XMMRegister dst, Address src) { | |
| 2009 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 2010 InstructionMark im(this); | |
| 4759 | 2011 simd_prefix(dst, dst, src, VEX_SIMD_F3); |
| 304 | 2012 emit_byte(0x59); |
| 2013 emit_operand(dst, src); | |
| 2014 } | |
| 2015 | |
| 2016 void Assembler::mulss(XMMRegister dst, XMMRegister src) { | |
| 2017 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 4759 | 2018 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); |
| 304 | 2019 emit_byte(0x59); |
| 2020 emit_byte(0xC0 | encode); | |
| 2021 } | |
| 2022 | |
| 2023 void Assembler::negl(Register dst) { | |
| 2024 int encode = prefix_and_encode(dst->encoding()); | |
| 2025 emit_byte(0xF7); | |
| 2026 emit_byte(0xD8 | encode); | |
| 2027 } | |
| 2028 | |
| 0 | 2029 void Assembler::nop(int i) { |
| 304 | 2030 #ifdef ASSERT |
| 0 | 2031 assert(i > 0, " "); |
| 304 | 2032 // The fancy nops aren't currently recognized by debuggers making it a |
| 2033 // pain to disassemble code while debugging. If asserts are on clearly | |
| 2034 // speed is not an issue so simply use the single byte traditional nop | |
| 2035 // to do alignment. | |
| 2036 | |
| 2037 for (; i > 0 ; i--) emit_byte(0x90); | |
| 2038 return; | |
| 2039 | |
| 2040 #endif // ASSERT | |
| 2041 | |
| 0 | 2042 if (UseAddressNop && VM_Version::is_intel()) { |
| 2043 // | |
| 2044 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel | |
| 2045 // 1: 0x90 | |
| 2046 // 2: 0x66 0x90 | |
| 2047 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) | |
| 2048 // 4: 0x0F 0x1F 0x40 0x00 | |
| 2049 // 5: 0x0F 0x1F 0x44 0x00 0x00 | |
| 2050 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
| 2051 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
| 2052 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 2053 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 2054 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 2055 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 2056 | |
| 2057 // The rest coding is Intel specific - don't use consecutive address nops | |
| 2058 | |
| 2059 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
| 2060 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
| 2061 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
| 2062 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
| 2063 | |
| 2064 while(i >= 15) { | |
| 2065 // For Intel don't generate consecutive addess nops (mix with regular nops) | |
| 2066 i -= 15; | |
| 2067 emit_byte(0x66); // size prefix | |
| 2068 emit_byte(0x66); // size prefix | |
| 2069 emit_byte(0x66); // size prefix | |
| 2070 addr_nop_8(); | |
| 2071 emit_byte(0x66); // size prefix | |
| 2072 emit_byte(0x66); // size prefix | |
| 2073 emit_byte(0x66); // size prefix | |
| 2074 emit_byte(0x90); // nop | |
| 2075 } | |
| 2076 switch (i) { | |
| 2077 case 14: | |
| 2078 emit_byte(0x66); // size prefix | |
| 2079 case 13: | |
| 2080 emit_byte(0x66); // size prefix | |
| 2081 case 12: | |
| 2082 addr_nop_8(); | |
| 2083 emit_byte(0x66); // size prefix | |
| 2084 emit_byte(0x66); // size prefix | |
| 2085 emit_byte(0x66); // size prefix | |
| 2086 emit_byte(0x90); // nop | |
| 2087 break; | |
| 2088 case 11: | |
| 2089 emit_byte(0x66); // size prefix | |
| 2090 case 10: | |
| 2091 emit_byte(0x66); // size prefix | |
| 2092 case 9: | |
| 2093 emit_byte(0x66); // size prefix | |
| 2094 case 8: | |
| 2095 addr_nop_8(); | |
| 2096 break; | |
| 2097 case 7: | |
| 2098 addr_nop_7(); | |
| 2099 break; | |
| 2100 case 6: | |
| 2101 emit_byte(0x66); // size prefix | |
| 2102 case 5: | |
| 2103 addr_nop_5(); | |
| 2104 break; | |
| 2105 case 4: | |
| 2106 addr_nop_4(); | |
| 2107 break; | |
| 2108 case 3: | |
| 2109 // Don't use "0x0F 0x1F 0x00" - need patching safe padding | |
| 2110 emit_byte(0x66); // size prefix | |
| 2111 case 2: | |
| 2112 emit_byte(0x66); // size prefix | |
| 2113 case 1: | |
| 2114 emit_byte(0x90); // nop | |
| 2115 break; | |
| 2116 default: | |
| 2117 assert(i == 0, " "); | |
| 2118 } | |
| 2119 return; | |
| 2120 } | |
| 2121 if (UseAddressNop && VM_Version::is_amd()) { | |
| 2122 // | |
| 2123 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD. | |
| 2124 // 1: 0x90 | |
| 2125 // 2: 0x66 0x90 | |
| 2126 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) | |
| 2127 // 4: 0x0F 0x1F 0x40 0x00 | |
| 2128 // 5: 0x0F 0x1F 0x44 0x00 0x00 | |
| 2129 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
| 2130 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
| 2131 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 2132 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 2133 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 2134 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 2135 | |
| 2136 // The rest coding is AMD specific - use consecutive address nops | |
| 2137 | |
| 2138 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
| 2139 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
| 2140 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
| 2141 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
| 2142 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 2143 // Size prefixes (0x66) are added for larger sizes | |
| 2144 | |
| 2145 while(i >= 22) { | |
| 2146 i -= 11; | |
| 2147 emit_byte(0x66); // size prefix | |
| 2148 emit_byte(0x66); // size prefix | |
| 2149 emit_byte(0x66); // size prefix | |
| 2150 addr_nop_8(); | |
| 2151 } | |
| 2152 // Generate first nop for size between 21-12 | |
| 2153 switch (i) { | |
| 2154 case 21: | |
| 2155 i -= 1; | |
| 2156 emit_byte(0x66); // size prefix | |
| 2157 case 20: | |
| 2158 case 19: | |
| 2159 i -= 1; | |
| 2160 emit_byte(0x66); // size prefix | |
| 2161 case 18: | |
| 2162 case 17: | |
| 2163 i -= 1; | |
| 2164 emit_byte(0x66); // size prefix | |
| 2165 case 16: | |
| 2166 case 15: | |
| 2167 i -= 8; | |
| 2168 addr_nop_8(); | |
| 2169 break; | |
| 2170 case 14: | |
| 2171 case 13: | |
| 2172 i -= 7; | |
| 2173 addr_nop_7(); | |
| 2174 break; | |
| 2175 case 12: | |
| 2176 i -= 6; | |
| 2177 emit_byte(0x66); // size prefix | |
| 2178 addr_nop_5(); | |
| 2179 break; | |
| 2180 default: | |
| 2181 assert(i < 12, " "); | |
| 2182 } | |
| 2183 | |
| 2184 // Generate second nop for size between 11-1 | |
| 2185 switch (i) { | |
| 2186 case 11: | |
| 2187 emit_byte(0x66); // size prefix | |
| 2188 case 10: | |
| 2189 emit_byte(0x66); // size prefix | |
| 2190 case 9: | |
| 2191 emit_byte(0x66); // size prefix | |
| 2192 case 8: | |
| 2193 addr_nop_8(); | |
| 2194 break; | |
| 2195 case 7: | |
| 2196 addr_nop_7(); | |
| 2197 break; | |
| 2198 case 6: | |
| 2199 emit_byte(0x66); // size prefix | |
| 2200 case 5: | |
| 2201 addr_nop_5(); | |
| 2202 break; | |
| 2203 case 4: | |
| 2204 addr_nop_4(); | |
| 2205 break; | |
| 2206 case 3: | |
| 2207 // Don't use "0x0F 0x1F 0x00" - need patching safe padding | |
| 2208 emit_byte(0x66); // size prefix | |
| 2209 case 2: | |
| 2210 emit_byte(0x66); // size prefix | |
| 2211 case 1: | |
| 2212 emit_byte(0x90); // nop | |
| 2213 break; | |
| 2214 default: | |
| 2215 assert(i == 0, " "); | |
| 2216 } | |
| 2217 return; | |
| 2218 } | |
| 2219 | |
| 2220 // Using nops with size prefixes "0x66 0x90". | |
| 2221 // From AMD Optimization Guide: | |
| 2222 // 1: 0x90 | |
| 2223 // 2: 0x66 0x90 | |
| 2224 // 3: 0x66 0x66 0x90 | |
| 2225 // 4: 0x66 0x66 0x66 0x90 | |
| 2226 // 5: 0x66 0x66 0x90 0x66 0x90 | |
| 2227 // 6: 0x66 0x66 0x90 0x66 0x66 0x90 | |
| 2228 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 | |
| 2229 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90 | |
| 2230 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 | |
| 2231 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 | |
| 2232 // | |
| 2233 while(i > 12) { | |
| 2234 i -= 4; | |
| 2235 emit_byte(0x66); // size prefix | |
| 2236 emit_byte(0x66); | |
| 2237 emit_byte(0x66); | |
| 2238 emit_byte(0x90); // nop | |
| 2239 } | |
| 2240 // 1 - 12 nops | |
| 2241 if(i > 8) { | |
| 2242 if(i > 9) { | |
| 2243 i -= 1; | |
| 2244 emit_byte(0x66); | |
| 2245 } | |
| 2246 i -= 3; | |
| 2247 emit_byte(0x66); | |
| 2248 emit_byte(0x66); | |
| 2249 emit_byte(0x90); | |
| 2250 } | |
| 2251 // 1 - 8 nops | |
| 2252 if(i > 4) { | |
| 2253 if(i > 6) { | |
| 2254 i -= 1; | |
| 2255 emit_byte(0x66); | |
| 2256 } | |
| 2257 i -= 3; | |
| 2258 emit_byte(0x66); | |
| 2259 emit_byte(0x66); | |
| 2260 emit_byte(0x90); | |
| 2261 } | |
| 2262 switch (i) { | |
| 2263 case 4: | |
| 2264 emit_byte(0x66); | |
| 2265 case 3: | |
| 2266 emit_byte(0x66); | |
| 2267 case 2: | |
| 2268 emit_byte(0x66); | |
| 2269 case 1: | |
| 2270 emit_byte(0x90); | |
| 2271 break; | |
| 2272 default: | |
| 2273 assert(i == 0, " "); | |
| 2274 } | |
| 2275 } | |
| 2276 | |
| 304 | 2277 void Assembler::notl(Register dst) { |
| 2278 int encode = prefix_and_encode(dst->encoding()); | |
| 2279 emit_byte(0xF7); | |
| 2280 emit_byte(0xD0 | encode ); | |
| 2281 } | |
| 2282 | |
| 2283 void Assembler::orl(Address dst, int32_t imm32) { | |
| 2284 InstructionMark im(this); | |
| 2285 prefix(dst); | |
|
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diff
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2286 emit_arith_operand(0x81, rcx, dst, imm32); |
| 304 | 2287 } |
| 2288 | |
| 2289 void Assembler::orl(Register dst, int32_t imm32) { | |
| 2290 prefix(dst); | |
| 2291 emit_arith(0x81, 0xC8, dst, imm32); | |
| 2292 } | |
| 2293 | |
| 2294 void Assembler::orl(Register dst, Address src) { | |
| 2295 InstructionMark im(this); | |
| 2296 prefix(src, dst); | |
| 2297 emit_byte(0x0B); | |
| 2298 emit_operand(dst, src); | |
| 2299 } | |
| 2300 | |
| 2301 void Assembler::orl(Register dst, Register src) { | |
| 2302 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2303 emit_arith(0x0B, 0xC0, dst, src); | |
| 2304 } | |
| 2305 | |
| 4759 | 2306 void Assembler::packuswb(XMMRegister dst, Address src) { |
| 2307 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2308 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); | |
| 2309 InstructionMark im(this); | |
| 2310 simd_prefix(dst, dst, src, VEX_SIMD_66); | |
| 2311 emit_byte(0x67); | |
| 2312 emit_operand(dst, src); | |
| 2313 } | |
| 2314 | |
| 2315 void Assembler::packuswb(XMMRegister dst, XMMRegister src) { | |
| 2316 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2317 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); | |
| 2318 emit_byte(0x67); | |
| 2319 emit_byte(0xC0 | encode); | |
| 2320 } | |
| 2321 | |
| 681 | 2322 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) { |
| 2323 assert(VM_Version::supports_sse4_2(), ""); | |
| 4759 | 2324 InstructionMark im(this); |
| 2325 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A); | |
| 681 | 2326 emit_byte(0x61); |
| 2327 emit_operand(dst, src); | |
| 2328 emit_byte(imm8); | |
| 2329 } | |
| 2330 | |
| 2331 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) { | |
| 2332 assert(VM_Version::supports_sse4_2(), ""); | |
| 4759 | 2333 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A); |
| 681 | 2334 emit_byte(0x61); |
| 2335 emit_byte(0xC0 | encode); | |
| 2336 emit_byte(imm8); | |
| 2337 } | |
| 2338 | |
| 4759 | 2339 void Assembler::pmovzxbw(XMMRegister dst, Address src) { |
| 2340 assert(VM_Version::supports_sse4_1(), ""); | |
| 2341 InstructionMark im(this); | |
| 2342 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
| 2343 emit_byte(0x30); | |
| 2344 emit_operand(dst, src); | |
| 2345 } | |
| 2346 | |
| 2347 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) { | |
| 2348 assert(VM_Version::supports_sse4_1(), ""); | |
| 2349 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
| 2350 emit_byte(0x30); | |
| 2351 emit_byte(0xC0 | encode); | |
| 2352 } | |
| 2353 | |
| 304 | 2354 // generic |
| 2355 void Assembler::pop(Register dst) { | |
| 2356 int encode = prefix_and_encode(dst->encoding()); | |
| 2357 emit_byte(0x58 | encode); | |
| 2358 } | |
| 2359 | |
|
643
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diff
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2360 void Assembler::popcntl(Register dst, Address src) { |
|
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diff
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2361 assert(VM_Version::supports_popcnt(), "must support"); |
|
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2362 InstructionMark im(this); |
|
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|
2363 emit_byte(0xF3); |
|
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diff
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|
2364 prefix(src, dst); |
|
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2365 emit_byte(0x0F); |
|
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|
2366 emit_byte(0xB8); |
|
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2367 emit_operand(dst, src); |
|
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2368 } |
|
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2369 |
|
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2370 void Assembler::popcntl(Register dst, Register src) { |
|
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|
2371 assert(VM_Version::supports_popcnt(), "must support"); |
|
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|
2372 emit_byte(0xF3); |
|
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diff
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|
2373 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
|
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2374 emit_byte(0x0F); |
|
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diff
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|
2375 emit_byte(0xB8); |
|
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diff
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|
2376 emit_byte(0xC0 | encode); |
|
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|
2377 } |
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|
2378 |
| 304 | 2379 void Assembler::popf() { |
| 2380 emit_byte(0x9D); | |
| 2381 } | |
| 2382 | |
| 1060 | 2383 #ifndef _LP64 // no 32bit push/pop on amd64 |
| 304 | 2384 void Assembler::popl(Address dst) { |
| 2385 // NOTE: this will adjust stack by 8byte on 64bits | |
| 2386 InstructionMark im(this); | |
| 2387 prefix(dst); | |
| 2388 emit_byte(0x8F); | |
| 2389 emit_operand(rax, dst); | |
| 2390 } | |
| 1060 | 2391 #endif |
| 304 | 2392 |
| 2393 void Assembler::prefetch_prefix(Address src) { | |
| 2394 prefix(src); | |
| 2395 emit_byte(0x0F); | |
| 2396 } | |
| 2397 | |
| 2398 void Assembler::prefetchnta(Address src) { | |
|
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2399 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); |
| 304 | 2400 InstructionMark im(this); |
| 2401 prefetch_prefix(src); | |
| 2402 emit_byte(0x18); | |
| 2403 emit_operand(rax, src); // 0, src | |
| 2404 } | |
| 2405 | |
| 2406 void Assembler::prefetchr(Address src) { | |
| 3854 | 2407 assert(VM_Version::supports_3dnow_prefetch(), "must support"); |
| 304 | 2408 InstructionMark im(this); |
| 2409 prefetch_prefix(src); | |
| 2410 emit_byte(0x0D); | |
| 2411 emit_operand(rax, src); // 0, src | |
| 2412 } | |
| 2413 | |
| 2414 void Assembler::prefetcht0(Address src) { | |
| 2415 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |
| 2416 InstructionMark im(this); | |
| 2417 prefetch_prefix(src); | |
| 2418 emit_byte(0x18); | |
| 2419 emit_operand(rcx, src); // 1, src | |
| 2420 } | |
| 2421 | |
| 2422 void Assembler::prefetcht1(Address src) { | |
| 2423 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |
| 2424 InstructionMark im(this); | |
| 2425 prefetch_prefix(src); | |
| 2426 emit_byte(0x18); | |
| 2427 emit_operand(rdx, src); // 2, src | |
| 2428 } | |
| 2429 | |
| 2430 void Assembler::prefetcht2(Address src) { | |
| 2431 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |
| 2432 InstructionMark im(this); | |
| 2433 prefetch_prefix(src); | |
| 2434 emit_byte(0x18); | |
| 2435 emit_operand(rbx, src); // 3, src | |
| 2436 } | |
| 2437 | |
| 2438 void Assembler::prefetchw(Address src) { | |
| 3854 | 2439 assert(VM_Version::supports_3dnow_prefetch(), "must support"); |
| 304 | 2440 InstructionMark im(this); |
| 2441 prefetch_prefix(src); | |
| 2442 emit_byte(0x0D); | |
| 2443 emit_operand(rcx, src); // 1, src | |
| 2444 } | |
| 2445 | |
| 2446 void Assembler::prefix(Prefix p) { | |
| 2447 a_byte(p); | |
| 2448 } | |
| 2449 | |
| 2262 | 2450 void Assembler::por(XMMRegister dst, XMMRegister src) { |
| 2451 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 2452 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); |
| 2262 | 2453 emit_byte(0xEB); |
| 2454 emit_byte(0xC0 | encode); | |
| 2455 } | |
| 2456 | |
| 4759 | 2457 void Assembler::por(XMMRegister dst, Address src) { |
| 2458 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2459 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); | |
| 2460 InstructionMark im(this); | |
| 2461 simd_prefix(dst, dst, src, VEX_SIMD_66); | |
| 2462 emit_byte(0xEB); | |
| 2463 emit_operand(dst, src); | |
| 2464 } | |
| 2465 | |
| 304 | 2466 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) { |
| 2467 assert(isByte(mode), "invalid value"); | |
| 2468 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 2469 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); |
| 304 | 2470 emit_byte(0x70); |
| 2471 emit_byte(0xC0 | encode); | |
| 2472 emit_byte(mode & 0xFF); | |
| 2473 | |
| 2474 } | |
| 2475 | |
| 2476 void Assembler::pshufd(XMMRegister dst, Address src, int mode) { | |
| 2477 assert(isByte(mode), "invalid value"); | |
| 2478 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 2479 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
| 2480 InstructionMark im(this); | |
| 2481 simd_prefix(dst, src, VEX_SIMD_66); | |
| 304 | 2482 emit_byte(0x70); |
| 2483 emit_operand(dst, src); | |
| 2484 emit_byte(mode & 0xFF); | |
| 2485 } | |
| 2486 | |
| 2487 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) { | |
| 2488 assert(isByte(mode), "invalid value"); | |
| 2489 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 2490 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2); |
| 304 | 2491 emit_byte(0x70); |
| 2492 emit_byte(0xC0 | encode); | |
| 2493 emit_byte(mode & 0xFF); | |
| 2494 } | |
| 2495 | |
| 2496 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) { | |
| 2497 assert(isByte(mode), "invalid value"); | |
| 2498 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 2499 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
| 2500 InstructionMark im(this); | |
| 2501 simd_prefix(dst, src, VEX_SIMD_F2); | |
| 304 | 2502 emit_byte(0x70); |
| 2503 emit_operand(dst, src); | |
| 2504 emit_byte(mode & 0xFF); | |
| 2505 } | |
| 2506 | |
| 2507 void Assembler::psrlq(XMMRegister dst, int shift) { | |
|
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2508 // Shift 64 bit value logically right by specified number of bits. |
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2509 // HMM Table D-1 says sse2 or mmx. |
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2510 // Do not confuse it with psrldq SSE2 instruction which |
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2511 // shifts 128 bit value in xmm register by number of bytes. |
| 4759 | 2512 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
| 2513 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66); | |
| 304 | 2514 emit_byte(0x73); |
| 2515 emit_byte(0xC0 | encode); | |
| 2516 emit_byte(shift); | |
| 2517 } | |
| 2518 | |
|
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2519 void Assembler::psrldq(XMMRegister dst, int shift) { |
|
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2520 // Shift 128 bit value in xmm register by number of bytes. |
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2521 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
| 4759 | 2522 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66); |
|
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2523 emit_byte(0x73); |
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2524 emit_byte(0xC0 | encode); |
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2525 emit_byte(shift); |
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2526 } |
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2527 |
| 681 | 2528 void Assembler::ptest(XMMRegister dst, Address src) { |
| 2529 assert(VM_Version::supports_sse4_1(), ""); | |
| 4759 | 2530 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
| 2531 InstructionMark im(this); | |
| 2532 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
| 681 | 2533 emit_byte(0x17); |
| 2534 emit_operand(dst, src); | |
| 2535 } | |
| 2536 | |
| 2537 void Assembler::ptest(XMMRegister dst, XMMRegister src) { | |
| 2538 assert(VM_Version::supports_sse4_1(), ""); | |
| 4759 | 2539 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
| 681 | 2540 emit_byte(0x17); |
| 2541 emit_byte(0xC0 | encode); | |
| 2542 } | |
| 2543 | |
| 4759 | 2544 void Assembler::punpcklbw(XMMRegister dst, Address src) { |
| 2545 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2546 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); | |
| 2547 InstructionMark im(this); | |
| 2548 simd_prefix(dst, dst, src, VEX_SIMD_66); | |
| 2549 emit_byte(0x60); | |
| 2550 emit_operand(dst, src); | |
| 2551 } | |
| 2552 | |
| 304 | 2553 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) { |
| 2554 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 2555 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); |
| 304 | 2556 emit_byte(0x60); |
| 2557 emit_byte(0xC0 | encode); | |
| 2558 } | |
| 2559 | |
| 4759 | 2560 void Assembler::punpckldq(XMMRegister dst, Address src) { |
| 2561 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2562 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); | |
| 2563 InstructionMark im(this); | |
| 2564 simd_prefix(dst, dst, src, VEX_SIMD_66); | |
| 2565 emit_byte(0x62); | |
| 2566 emit_operand(dst, src); | |
| 2567 } | |
| 2568 | |
| 2569 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) { | |
| 2570 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2571 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); | |
| 2572 emit_byte(0x62); | |
| 2573 emit_byte(0xC0 | encode); | |
| 2574 } | |
| 2575 | |
| 304 | 2576 void Assembler::push(int32_t imm32) { |
| 2577 // in 64bits we push 64bits onto the stack but only | |
| 2578 // take a 32bit immediate | |
| 2579 emit_byte(0x68); | |
| 2580 emit_long(imm32); | |
| 2581 } | |
| 2582 | |
| 2583 void Assembler::push(Register src) { | |
| 2584 int encode = prefix_and_encode(src->encoding()); | |
| 2585 | |
| 2586 emit_byte(0x50 | encode); | |
| 2587 } | |
| 2588 | |
| 2589 void Assembler::pushf() { | |
| 2590 emit_byte(0x9C); | |
| 2591 } | |
| 2592 | |
| 1060 | 2593 #ifndef _LP64 // no 32bit push/pop on amd64 |
| 304 | 2594 void Assembler::pushl(Address src) { |
| 2595 // Note this will push 64bit on 64bit | |
| 2596 InstructionMark im(this); | |
| 2597 prefix(src); | |
| 2598 emit_byte(0xFF); | |
| 2599 emit_operand(rsi, src); | |
| 2600 } | |
| 1060 | 2601 #endif |
| 304 | 2602 |
| 2603 void Assembler::pxor(XMMRegister dst, Address src) { | |
| 2604 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 2605 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
| 2606 InstructionMark im(this); | |
| 2607 simd_prefix(dst, dst, src, VEX_SIMD_66); | |
| 304 | 2608 emit_byte(0xEF); |
| 2609 emit_operand(dst, src); | |
| 2610 } | |
| 2611 | |
| 2612 void Assembler::pxor(XMMRegister dst, XMMRegister src) { | |
| 2613 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 2614 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); |
| 304 | 2615 emit_byte(0xEF); |
| 2616 emit_byte(0xC0 | encode); | |
| 2617 } | |
| 2618 | |
| 2619 void Assembler::rcll(Register dst, int imm8) { | |
| 2620 assert(isShiftCount(imm8), "illegal shift count"); | |
| 2621 int encode = prefix_and_encode(dst->encoding()); | |
| 2622 if (imm8 == 1) { | |
| 2623 emit_byte(0xD1); | |
| 2624 emit_byte(0xD0 | encode); | |
| 2625 } else { | |
| 2626 emit_byte(0xC1); | |
| 2627 emit_byte(0xD0 | encode); | |
| 2628 emit_byte(imm8); | |
| 2629 } | |
| 2630 } | |
| 2631 | |
| 2632 // copies data from [esi] to [edi] using rcx pointer sized words | |
| 2633 // generic | |
| 2634 void Assembler::rep_mov() { | |
| 2635 emit_byte(0xF3); | |
| 2636 // MOVSQ | |
| 2637 LP64_ONLY(prefix(REX_W)); | |
| 2638 emit_byte(0xA5); | |
| 2639 } | |
| 2640 | |
| 2641 // sets rcx pointer sized words with rax, value at [edi] | |
| 2642 // generic | |
| 2643 void Assembler::rep_set() { // rep_set | |
| 2644 emit_byte(0xF3); | |
| 2645 // STOSQ | |
| 2646 LP64_ONLY(prefix(REX_W)); | |
| 2647 emit_byte(0xAB); | |
| 2648 } | |
| 2649 | |
| 2650 // scans rcx pointer sized words at [edi] for occurance of rax, | |
| 2651 // generic | |
| 2652 void Assembler::repne_scan() { // repne_scan | |
| 2653 emit_byte(0xF2); | |
| 2654 // SCASQ | |
| 2655 LP64_ONLY(prefix(REX_W)); | |
| 2656 emit_byte(0xAF); | |
| 2657 } | |
| 2658 | |
| 2659 #ifdef _LP64 | |
| 2660 // scans rcx 4 byte words at [edi] for occurance of rax, | |
| 2661 // generic | |
| 2662 void Assembler::repne_scanl() { // repne_scan | |
| 2663 emit_byte(0xF2); | |
| 2664 // SCASL | |
| 2665 emit_byte(0xAF); | |
| 2666 } | |
| 2667 #endif | |
| 2668 | |
| 0 | 2669 void Assembler::ret(int imm16) { |
| 2670 if (imm16 == 0) { | |
| 2671 emit_byte(0xC3); | |
| 2672 } else { | |
| 2673 emit_byte(0xC2); | |
| 2674 emit_word(imm16); | |
| 2675 } | |
| 2676 } | |
| 2677 | |
| 304 | 2678 void Assembler::sahf() { |
| 2679 #ifdef _LP64 | |
| 2680 // Not supported in 64bit mode | |
| 2681 ShouldNotReachHere(); | |
| 2682 #endif | |
| 2683 emit_byte(0x9E); | |
| 2684 } | |
| 2685 | |
| 2686 void Assembler::sarl(Register dst, int imm8) { | |
| 2687 int encode = prefix_and_encode(dst->encoding()); | |
| 2688 assert(isShiftCount(imm8), "illegal shift count"); | |
| 2689 if (imm8 == 1) { | |
| 2690 emit_byte(0xD1); | |
| 2691 emit_byte(0xF8 | encode); | |
| 2692 } else { | |
| 2693 emit_byte(0xC1); | |
| 2694 emit_byte(0xF8 | encode); | |
| 2695 emit_byte(imm8); | |
| 2696 } | |
| 2697 } | |
| 2698 | |
| 2699 void Assembler::sarl(Register dst) { | |
| 2700 int encode = prefix_and_encode(dst->encoding()); | |
| 2701 emit_byte(0xD3); | |
| 2702 emit_byte(0xF8 | encode); | |
| 2703 } | |
| 2704 | |
| 2705 void Assembler::sbbl(Address dst, int32_t imm32) { | |
| 2706 InstructionMark im(this); | |
| 2707 prefix(dst); | |
| 2708 emit_arith_operand(0x81, rbx, dst, imm32); | |
| 2709 } | |
| 2710 | |
| 2711 void Assembler::sbbl(Register dst, int32_t imm32) { | |
| 2712 prefix(dst); | |
| 2713 emit_arith(0x81, 0xD8, dst, imm32); | |
| 2714 } | |
| 2715 | |
| 2716 | |
| 2717 void Assembler::sbbl(Register dst, Address src) { | |
| 2718 InstructionMark im(this); | |
| 2719 prefix(src, dst); | |
| 2720 emit_byte(0x1B); | |
| 2721 emit_operand(dst, src); | |
| 2722 } | |
| 2723 | |
| 2724 void Assembler::sbbl(Register dst, Register src) { | |
| 2725 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2726 emit_arith(0x1B, 0xC0, dst, src); | |
| 2727 } | |
| 2728 | |
| 2729 void Assembler::setb(Condition cc, Register dst) { | |
| 2730 assert(0 <= cc && cc < 16, "illegal cc"); | |
| 2731 int encode = prefix_and_encode(dst->encoding(), true); | |
| 0 | 2732 emit_byte(0x0F); |
| 304 | 2733 emit_byte(0x90 | cc); |
| 2734 emit_byte(0xC0 | encode); | |
| 2735 } | |
| 2736 | |
| 2737 void Assembler::shll(Register dst, int imm8) { | |
| 2738 assert(isShiftCount(imm8), "illegal shift count"); | |
| 2739 int encode = prefix_and_encode(dst->encoding()); | |
| 2740 if (imm8 == 1 ) { | |
| 2741 emit_byte(0xD1); | |
| 2742 emit_byte(0xE0 | encode); | |
| 2743 } else { | |
| 2744 emit_byte(0xC1); | |
| 2745 emit_byte(0xE0 | encode); | |
| 2746 emit_byte(imm8); | |
| 2747 } | |
| 2748 } | |
| 2749 | |
| 2750 void Assembler::shll(Register dst) { | |
| 2751 int encode = prefix_and_encode(dst->encoding()); | |
| 2752 emit_byte(0xD3); | |
| 2753 emit_byte(0xE0 | encode); | |
| 2754 } | |
| 2755 | |
| 2756 void Assembler::shrl(Register dst, int imm8) { | |
| 2757 assert(isShiftCount(imm8), "illegal shift count"); | |
| 2758 int encode = prefix_and_encode(dst->encoding()); | |
| 2759 emit_byte(0xC1); | |
| 2760 emit_byte(0xE8 | encode); | |
| 2761 emit_byte(imm8); | |
| 2762 } | |
| 2763 | |
| 2764 void Assembler::shrl(Register dst) { | |
| 2765 int encode = prefix_and_encode(dst->encoding()); | |
| 2766 emit_byte(0xD3); | |
| 2767 emit_byte(0xE8 | encode); | |
| 2768 } | |
| 0 | 2769 |
| 2770 // copies a single word from [esi] to [edi] | |
| 2771 void Assembler::smovl() { | |
| 2772 emit_byte(0xA5); | |
| 2773 } | |
| 2774 | |
| 304 | 2775 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) { |
| 2776 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 2777 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
| 304 | 2778 emit_byte(0x51); |
| 2779 emit_byte(0xC0 | encode); | |
| 2780 } | |
| 2781 | |
| 2008 | 2782 void Assembler::sqrtsd(XMMRegister dst, Address src) { |
| 2783 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2784 InstructionMark im(this); | |
| 4759 | 2785 simd_prefix(dst, dst, src, VEX_SIMD_F2); |
| 2008 | 2786 emit_byte(0x51); |
| 2787 emit_operand(dst, src); | |
| 2788 } | |
| 2789 | |
| 2790 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) { | |
| 4759 | 2791 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
| 2792 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); | |
| 2008 | 2793 emit_byte(0x51); |
| 2794 emit_byte(0xC0 | encode); | |
| 2795 } | |
| 2796 | |
| 2797 void Assembler::sqrtss(XMMRegister dst, Address src) { | |
| 4759 | 2798 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
| 2799 InstructionMark im(this); | |
| 2800 simd_prefix(dst, dst, src, VEX_SIMD_F3); | |
| 2008 | 2801 emit_byte(0x51); |
| 2802 emit_operand(dst, src); | |
| 2803 } | |
| 2804 | |
| 304 | 2805 void Assembler::stmxcsr( Address dst) { |
| 2806 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 2807 InstructionMark im(this); | |
| 2808 prefix(dst); | |
| 2809 emit_byte(0x0F); | |
| 2810 emit_byte(0xAE); | |
| 2811 emit_operand(as_Register(3), dst); | |
| 2812 } | |
| 2813 | |
| 2814 void Assembler::subl(Address dst, int32_t imm32) { | |
| 2815 InstructionMark im(this); | |
| 2816 prefix(dst); | |
|
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2817 emit_arith_operand(0x81, rbp, dst, imm32); |
| 304 | 2818 } |
| 2819 | |
| 2820 void Assembler::subl(Address dst, Register src) { | |
| 2821 InstructionMark im(this); | |
| 2822 prefix(dst, src); | |
| 2823 emit_byte(0x29); | |
| 2824 emit_operand(src, dst); | |
| 2825 } | |
| 2826 | |
|
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2827 void Assembler::subl(Register dst, int32_t imm32) { |
|
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2828 prefix(dst); |
|
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2829 emit_arith(0x81, 0xE8, dst, imm32); |
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2830 } |
|
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2831 |
|
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2832 // Force generation of a 4 byte immediate value even if it fits into 8bit |
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2833 void Assembler::subl_imm32(Register dst, int32_t imm32) { |
|
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2834 prefix(dst); |
|
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2835 emit_arith_imm32(0x81, 0xE8, dst, imm32); |
|
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2836 } |
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2837 |
| 304 | 2838 void Assembler::subl(Register dst, Address src) { |
| 2839 InstructionMark im(this); | |
| 2840 prefix(src, dst); | |
| 2841 emit_byte(0x2B); | |
| 2842 emit_operand(dst, src); | |
| 2843 } | |
| 2844 | |
| 2845 void Assembler::subl(Register dst, Register src) { | |
| 2846 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2847 emit_arith(0x2B, 0xC0, dst, src); | |
| 2848 } | |
| 2849 | |
| 2850 void Assembler::subsd(XMMRegister dst, XMMRegister src) { | |
| 2851 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 2852 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
| 304 | 2853 emit_byte(0x5C); |
| 2854 emit_byte(0xC0 | encode); | |
| 2855 } | |
| 2856 | |
| 2857 void Assembler::subsd(XMMRegister dst, Address src) { | |
| 2858 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2859 InstructionMark im(this); | |
| 4759 | 2860 simd_prefix(dst, dst, src, VEX_SIMD_F2); |
| 304 | 2861 emit_byte(0x5C); |
| 2862 emit_operand(dst, src); | |
| 2863 } | |
| 2864 | |
| 2865 void Assembler::subss(XMMRegister dst, XMMRegister src) { | |
| 2866 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 4759 | 2867 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); |
| 304 | 2868 emit_byte(0x5C); |
| 2869 emit_byte(0xC0 | encode); | |
| 2870 } | |
| 2871 | |
| 2872 void Assembler::subss(XMMRegister dst, Address src) { | |
| 2873 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 2874 InstructionMark im(this); | |
| 4759 | 2875 simd_prefix(dst, dst, src, VEX_SIMD_F3); |
| 304 | 2876 emit_byte(0x5C); |
| 2877 emit_operand(dst, src); | |
| 2878 } | |
| 2879 | |
| 2880 void Assembler::testb(Register dst, int imm8) { | |
| 2881 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); | |
| 2882 (void) prefix_and_encode(dst->encoding(), true); | |
| 2883 emit_arith_b(0xF6, 0xC0, dst, imm8); | |
| 2884 } | |
| 2885 | |
| 2886 void Assembler::testl(Register dst, int32_t imm32) { | |
| 2887 // not using emit_arith because test | |
| 2888 // doesn't support sign-extension of | |
| 2889 // 8bit operands | |
| 2890 int encode = dst->encoding(); | |
| 2891 if (encode == 0) { | |
| 2892 emit_byte(0xA9); | |
| 2893 } else { | |
| 2894 encode = prefix_and_encode(encode); | |
| 2895 emit_byte(0xF7); | |
| 2896 emit_byte(0xC0 | encode); | |
| 2897 } | |
| 2898 emit_long(imm32); | |
| 2899 } | |
| 2900 | |
| 2901 void Assembler::testl(Register dst, Register src) { | |
| 2902 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2903 emit_arith(0x85, 0xC0, dst, src); | |
| 2904 } | |
| 2905 | |
| 2906 void Assembler::testl(Register dst, Address src) { | |
| 2907 InstructionMark im(this); | |
| 2908 prefix(src, dst); | |
| 2909 emit_byte(0x85); | |
| 2910 emit_operand(dst, src); | |
| 2911 } | |
| 2912 | |
| 2913 void Assembler::ucomisd(XMMRegister dst, Address src) { | |
| 2914 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 2915 InstructionMark im(this); |
| 2916 simd_prefix(dst, src, VEX_SIMD_66); | |
| 2917 emit_byte(0x2E); | |
| 2918 emit_operand(dst, src); | |
| 304 | 2919 } |
| 2920 | |
| 2921 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) { | |
| 2922 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 2923 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); |
| 2924 emit_byte(0x2E); | |
| 2925 emit_byte(0xC0 | encode); | |
| 304 | 2926 } |
| 2927 | |
| 2928 void Assembler::ucomiss(XMMRegister dst, Address src) { | |
| 2929 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 4759 | 2930 InstructionMark im(this); |
| 2931 simd_prefix(dst, src, VEX_SIMD_NONE); | |
| 304 | 2932 emit_byte(0x2E); |
| 2933 emit_operand(dst, src); | |
| 2934 } | |
| 2935 | |
| 2936 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) { | |
| 2937 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 4759 | 2938 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE); |
| 304 | 2939 emit_byte(0x2E); |
| 2940 emit_byte(0xC0 | encode); | |
| 2941 } | |
| 2942 | |
| 2943 | |
| 2944 void Assembler::xaddl(Address dst, Register src) { | |
| 2945 InstructionMark im(this); | |
| 2946 prefix(dst, src); | |
| 0 | 2947 emit_byte(0x0F); |
| 304 | 2948 emit_byte(0xC1); |
| 2949 emit_operand(src, dst); | |
| 2950 } | |
| 2951 | |
| 2952 void Assembler::xchgl(Register dst, Address src) { // xchg | |
| 2953 InstructionMark im(this); | |
| 2954 prefix(src, dst); | |
| 2955 emit_byte(0x87); | |
| 2956 emit_operand(dst, src); | |
| 2957 } | |
| 2958 | |
| 2959 void Assembler::xchgl(Register dst, Register src) { | |
| 2960 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2961 emit_byte(0x87); | |
| 2962 emit_byte(0xc0 | encode); | |
| 2963 } | |
| 2964 | |
| 2965 void Assembler::xorl(Register dst, int32_t imm32) { | |
| 2966 prefix(dst); | |
| 2967 emit_arith(0x81, 0xF0, dst, imm32); | |
| 2968 } | |
| 2969 | |
| 2970 void Assembler::xorl(Register dst, Address src) { | |
| 2971 InstructionMark im(this); | |
| 2972 prefix(src, dst); | |
| 2973 emit_byte(0x33); | |
| 2974 emit_operand(dst, src); | |
| 2975 } | |
| 2976 | |
| 2977 void Assembler::xorl(Register dst, Register src) { | |
| 2978 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2979 emit_arith(0x33, 0xC0, dst, src); | |
| 2980 } | |
| 2981 | |
| 2982 void Assembler::xorpd(XMMRegister dst, XMMRegister src) { | |
| 2983 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 2984 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); |
| 2985 emit_byte(0x57); | |
| 2986 emit_byte(0xC0 | encode); | |
| 304 | 2987 } |
| 2988 | |
| 2989 void Assembler::xorpd(XMMRegister dst, Address src) { | |
| 2990 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2991 InstructionMark im(this); | |
| 4759 | 2992 simd_prefix(dst, dst, src, VEX_SIMD_66); |
| 304 | 2993 emit_byte(0x57); |
| 2994 emit_operand(dst, src); | |
| 2995 } | |
| 2996 | |
| 2997 | |
| 2998 void Assembler::xorps(XMMRegister dst, XMMRegister src) { | |
| 2999 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 4759 | 3000 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE); |
| 304 | 3001 emit_byte(0x57); |
| 3002 emit_byte(0xC0 | encode); | |
| 3003 } | |
| 3004 | |
| 3005 void Assembler::xorps(XMMRegister dst, Address src) { | |
| 3006 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 3007 InstructionMark im(this); | |
| 4759 | 3008 simd_prefix(dst, dst, src, VEX_SIMD_NONE); |
| 304 | 3009 emit_byte(0x57); |
| 3010 emit_operand(dst, src); | |
| 3011 } | |
| 3012 | |
|
4761
65149e74c706
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|
3013 // AVX 3-operands non destructive source instructions (encoded with VEX prefix) |
|
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|
3014 |
|
65149e74c706
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|
3015 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) { |
|
65149e74c706
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|
3016 assert(VM_Version::supports_avx(), ""); |
|
65149e74c706
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|
3017 InstructionMark im(this); |
|
65149e74c706
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|
3018 vex_prefix(dst, nds, src, VEX_SIMD_F2); |
|
65149e74c706
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|
3019 emit_byte(0x58); |
|
65149e74c706
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|
3020 emit_operand(dst, src); |
|
65149e74c706
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|
3021 } |
|
65149e74c706
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|
3022 |
|
65149e74c706
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|
3023 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
|
65149e74c706
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|
3024 assert(VM_Version::supports_avx(), ""); |
|
65149e74c706
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|
3025 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F2); |
|
65149e74c706
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|
3026 emit_byte(0x58); |
|
65149e74c706
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|
3027 emit_byte(0xC0 | encode); |
|
65149e74c706
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|
3028 } |
|
65149e74c706
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|
3029 |
|
65149e74c706
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|
3030 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) { |
|
65149e74c706
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|
3031 assert(VM_Version::supports_avx(), ""); |
|
65149e74c706
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|
3032 InstructionMark im(this); |
|
65149e74c706
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|
3033 vex_prefix(dst, nds, src, VEX_SIMD_F3); |
|
65149e74c706
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|
3034 emit_byte(0x58); |
|
65149e74c706
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|
3035 emit_operand(dst, src); |
|
65149e74c706
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|
3036 } |
|
65149e74c706
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|
3037 |
|
65149e74c706
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|
3038 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
|
65149e74c706
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|
3039 assert(VM_Version::supports_avx(), ""); |
|
65149e74c706
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|
3040 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F3); |
|
65149e74c706
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|
3041 emit_byte(0x58); |
|
65149e74c706
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|
3042 emit_byte(0xC0 | encode); |
|
65149e74c706
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|
3043 } |
|
65149e74c706
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|
3044 |
|
65149e74c706
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|
3045 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src) { |
|
65149e74c706
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|
3046 assert(VM_Version::supports_avx(), ""); |
|
65149e74c706
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changeset
|
3047 InstructionMark im(this); |
|
65149e74c706
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changeset
|
3048 vex_prefix(dst, nds, src, VEX_SIMD_66); // 128-bit vector |
|
65149e74c706
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|
3049 emit_byte(0x54); |
|
65149e74c706
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|
3050 emit_operand(dst, src); |
|
65149e74c706
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|
3051 } |
|
65149e74c706
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|
3052 |
|
65149e74c706
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|
3053 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src) { |
|
65149e74c706
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|
3054 assert(VM_Version::supports_avx(), ""); |
|
65149e74c706
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|
3055 InstructionMark im(this); |
|
65149e74c706
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changeset
|
3056 vex_prefix(dst, nds, src, VEX_SIMD_NONE); // 128-bit vector |
|
65149e74c706
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|
3057 emit_byte(0x54); |
|
65149e74c706
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|
3058 emit_operand(dst, src); |
|
65149e74c706
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|
3059 } |
|
65149e74c706
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|
3060 |
|
65149e74c706
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|
3061 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) { |
|
65149e74c706
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|
3062 assert(VM_Version::supports_avx(), ""); |
|
65149e74c706
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|
3063 InstructionMark im(this); |
|
65149e74c706
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changeset
|
3064 vex_prefix(dst, nds, src, VEX_SIMD_F2); |
|
65149e74c706
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|
3065 emit_byte(0x5E); |
|
65149e74c706
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|
3066 emit_operand(dst, src); |
|
65149e74c706
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|
3067 } |
|
65149e74c706
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|
3068 |
|
65149e74c706
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|
3069 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
|
65149e74c706
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|
3070 assert(VM_Version::supports_avx(), ""); |
|
65149e74c706
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|
3071 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F2); |
|
65149e74c706
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|
3072 emit_byte(0x5E); |
|
65149e74c706
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|
3073 emit_byte(0xC0 | encode); |
|
65149e74c706
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|
3074 } |
|
65149e74c706
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|
3075 |
|
65149e74c706
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|
3076 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) { |
|
65149e74c706
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|
3077 assert(VM_Version::supports_avx(), ""); |
|
65149e74c706
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|
3078 InstructionMark im(this); |
|
65149e74c706
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|
3079 vex_prefix(dst, nds, src, VEX_SIMD_F3); |
|
65149e74c706
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|
3080 emit_byte(0x5E); |
|
65149e74c706
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|
3081 emit_operand(dst, src); |
|
65149e74c706
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|
3082 } |
|
65149e74c706
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|
3083 |
|
65149e74c706
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|
3084 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
|
65149e74c706
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|
3085 assert(VM_Version::supports_avx(), ""); |
|
65149e74c706
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|
3086 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F3); |
|
65149e74c706
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|
3087 emit_byte(0x5E); |
|
65149e74c706
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|
3088 emit_byte(0xC0 | encode); |
|
65149e74c706
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|
3089 } |
|
65149e74c706
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|
3090 |
|
65149e74c706
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|
3091 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) { |
|
65149e74c706
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|
3092 assert(VM_Version::supports_avx(), ""); |
|
65149e74c706
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|
3093 InstructionMark im(this); |
|
65149e74c706
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|
3094 vex_prefix(dst, nds, src, VEX_SIMD_F2); |
|
65149e74c706
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|
3095 emit_byte(0x59); |
|
65149e74c706
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|
3096 emit_operand(dst, src); |
|
65149e74c706
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|
3097 } |
|
65149e74c706
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|
3098 |
|
65149e74c706
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changeset
|
3099 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
|
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|
3100 assert(VM_Version::supports_avx(), ""); |
|
65149e74c706
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|
3101 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F2); |
|
65149e74c706
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|
3102 emit_byte(0x59); |
|
65149e74c706
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|
3103 emit_byte(0xC0 | encode); |
|
65149e74c706
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|
3104 } |
|
65149e74c706
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|
3105 |
|
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|
3106 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) { |
|
65149e74c706
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|
3107 InstructionMark im(this); |
|
65149e74c706
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|
3108 vex_prefix(dst, nds, src, VEX_SIMD_F3); |
|
65149e74c706
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|
3109 emit_byte(0x59); |
|
65149e74c706
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|
3110 emit_operand(dst, src); |
|
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|
3111 } |
|
65149e74c706
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|
3112 |
|
65149e74c706
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|
3113 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
|
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|
3114 assert(VM_Version::supports_avx(), ""); |
|
65149e74c706
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|
3115 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F3); |
|
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|
3116 emit_byte(0x59); |
|
65149e74c706
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|
3117 emit_byte(0xC0 | encode); |
|
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|
3118 } |
|
65149e74c706
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|
3119 |
|
65149e74c706
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|
3120 |
|
65149e74c706
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|
3121 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) { |
|
65149e74c706
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|
3122 assert(VM_Version::supports_avx(), ""); |
|
65149e74c706
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|
3123 InstructionMark im(this); |
|
65149e74c706
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|
3124 vex_prefix(dst, nds, src, VEX_SIMD_F2); |
|
65149e74c706
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|
3125 emit_byte(0x5C); |
|
65149e74c706
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|
3126 emit_operand(dst, src); |
|
65149e74c706
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|
3127 } |
|
65149e74c706
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|
3128 |
|
65149e74c706
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|
3129 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
|
65149e74c706
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|
3130 assert(VM_Version::supports_avx(), ""); |
|
65149e74c706
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|
3131 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F2); |
|
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|
3132 emit_byte(0x5C); |
|
65149e74c706
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|
3133 emit_byte(0xC0 | encode); |
|
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|
3134 } |
|
65149e74c706
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|
3135 |
|
65149e74c706
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|
3136 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) { |
|
65149e74c706
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|
3137 assert(VM_Version::supports_avx(), ""); |
|
65149e74c706
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|
3138 InstructionMark im(this); |
|
65149e74c706
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|
3139 vex_prefix(dst, nds, src, VEX_SIMD_F3); |
|
65149e74c706
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|
3140 emit_byte(0x5C); |
|
65149e74c706
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|
3141 emit_operand(dst, src); |
|
65149e74c706
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|
3142 } |
|
65149e74c706
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|
3143 |
|
65149e74c706
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|
3144 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
|
65149e74c706
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|
3145 assert(VM_Version::supports_avx(), ""); |
|
65149e74c706
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|
3146 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F3); |
|
65149e74c706
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|
3147 emit_byte(0x5C); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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|
3148 emit_byte(0xC0 | encode); |
|
65149e74c706
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|
3149 } |
|
65149e74c706
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kvn
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changeset
|
3150 |
|
65149e74c706
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|
3151 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src) { |
|
65149e74c706
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|
3152 assert(VM_Version::supports_avx(), ""); |
|
65149e74c706
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kvn
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|
3153 InstructionMark im(this); |
|
65149e74c706
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|
3154 vex_prefix(dst, nds, src, VEX_SIMD_66); // 128-bit vector |
|
65149e74c706
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|
3155 emit_byte(0x57); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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|
3156 emit_operand(dst, src); |
|
65149e74c706
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|
3157 } |
|
65149e74c706
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|
3158 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
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diff
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|
3159 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
8c92982cbbc4
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kvn
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|
3160 assert(VM_Version::supports_avx(), ""); |
|
8c92982cbbc4
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kvn
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6141
diff
changeset
|
3161 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
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changeset
|
3162 emit_byte(0x57); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3163 emit_byte(0xC0 | encode); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
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6141
diff
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|
3164 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
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6141
diff
changeset
|
3165 |
|
4761
65149e74c706
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|
3166 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src) { |
|
65149e74c706
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|
3167 assert(VM_Version::supports_avx(), ""); |
|
65149e74c706
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kvn
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|
3168 InstructionMark im(this); |
|
65149e74c706
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changeset
|
3169 vex_prefix(dst, nds, src, VEX_SIMD_NONE); // 128-bit vector |
|
65149e74c706
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|
3170 emit_byte(0x57); |
|
65149e74c706
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|
3171 emit_operand(dst, src); |
|
65149e74c706
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|
3172 } |
|
65149e74c706
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|
3173 |
|
6179
8c92982cbbc4
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kvn
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diff
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|
3174 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
|
8c92982cbbc4
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kvn
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|
3175 assert(VM_Version::supports_avx(), ""); |
|
8c92982cbbc4
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kvn
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changeset
|
3176 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_NONE, vector256); |
|
8c92982cbbc4
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kvn
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|
3177 emit_byte(0x57); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
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changeset
|
3178 emit_byte(0xC0 | encode); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
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6141
diff
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|
3179 } |
|
8c92982cbbc4
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kvn
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6141
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changeset
|
3180 |
|
8c92982cbbc4
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kvn
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changeset
|
3181 void Assembler::vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
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changeset
|
3182 assert(VM_Version::supports_avx(), ""); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
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|
3183 bool vector256 = true; |
|
8c92982cbbc4
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kvn
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|
3184 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
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changeset
|
3185 emit_byte(0x18); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
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6141
diff
changeset
|
3186 emit_byte(0xC0 | encode); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
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changeset
|
3187 // 0x00 - insert into lower 128 bits |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
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changeset
|
3188 // 0x01 - insert into upper 128 bits |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
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changeset
|
3189 emit_byte(0x01); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
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changeset
|
3190 } |
|
8c92982cbbc4
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kvn
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changeset
|
3191 |
|
8c92982cbbc4
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kvn
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|
3192 void Assembler::vzeroupper() { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
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changeset
|
3193 assert(VM_Version::supports_avx(), ""); |
|
8c92982cbbc4
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kvn
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6141
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changeset
|
3194 (void)vex_prefix_and_encode(xmm0, xmm0, xmm0, VEX_SIMD_NONE); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
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|
3195 emit_byte(0x77); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
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6141
diff
changeset
|
3196 } |
|
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changeset
|
3197 |
|
4761
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|
3198 |
| 304 | 3199 #ifndef _LP64 |
| 3200 // 32bit only pieces of the assembler | |
| 3201 | |
| 3202 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) { | |
| 3203 // NO PREFIX AS NEVER 64BIT | |
| 3204 InstructionMark im(this); | |
| 3205 emit_byte(0x81); | |
| 3206 emit_byte(0xF8 | src1->encoding()); | |
| 3207 emit_data(imm32, rspec, 0); | |
| 3208 } | |
| 3209 | |
| 3210 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) { | |
| 3211 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs | |
| 3212 InstructionMark im(this); | |
| 3213 emit_byte(0x81); | |
| 3214 emit_operand(rdi, src1); | |
| 3215 emit_data(imm32, rspec, 0); | |
| 3216 } | |
| 3217 | |
| 3218 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax, | |
| 3219 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded | |
| 3220 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise. | |
| 3221 void Assembler::cmpxchg8(Address adr) { | |
| 3222 InstructionMark im(this); | |
| 3223 emit_byte(0x0F); | |
| 3224 emit_byte(0xc7); | |
| 3225 emit_operand(rcx, adr); | |
| 3226 } | |
| 3227 | |
| 3228 void Assembler::decl(Register dst) { | |
| 3229 // Don't use it directly. Use MacroAssembler::decrementl() instead. | |
| 3230 emit_byte(0x48 | dst->encoding()); | |
| 3231 } | |
| 3232 | |
| 3233 #endif // _LP64 | |
| 3234 | |
| 3235 // 64bit typically doesn't use the x87 but needs to for the trig funcs | |
| 3236 | |
| 3237 void Assembler::fabs() { | |
| 3238 emit_byte(0xD9); | |
| 3239 emit_byte(0xE1); | |
| 3240 } | |
| 3241 | |
| 3242 void Assembler::fadd(int i) { | |
| 3243 emit_farith(0xD8, 0xC0, i); | |
| 3244 } | |
| 3245 | |
| 3246 void Assembler::fadd_d(Address src) { | |
| 3247 InstructionMark im(this); | |
| 3248 emit_byte(0xDC); | |
| 3249 emit_operand32(rax, src); | |
| 3250 } | |
| 3251 | |
| 3252 void Assembler::fadd_s(Address src) { | |
| 3253 InstructionMark im(this); | |
| 3254 emit_byte(0xD8); | |
| 3255 emit_operand32(rax, src); | |
| 3256 } | |
| 3257 | |
| 3258 void Assembler::fadda(int i) { | |
| 3259 emit_farith(0xDC, 0xC0, i); | |
| 3260 } | |
| 3261 | |
| 3262 void Assembler::faddp(int i) { | |
| 3263 emit_farith(0xDE, 0xC0, i); | |
| 3264 } | |
| 3265 | |
| 3266 void Assembler::fchs() { | |
| 3267 emit_byte(0xD9); | |
| 3268 emit_byte(0xE0); | |
| 3269 } | |
| 3270 | |
| 3271 void Assembler::fcom(int i) { | |
| 3272 emit_farith(0xD8, 0xD0, i); | |
| 3273 } | |
| 3274 | |
| 3275 void Assembler::fcomp(int i) { | |
| 3276 emit_farith(0xD8, 0xD8, i); | |
| 3277 } | |
| 3278 | |
| 3279 void Assembler::fcomp_d(Address src) { | |
| 3280 InstructionMark im(this); | |
| 3281 emit_byte(0xDC); | |
| 3282 emit_operand32(rbx, src); | |
| 3283 } | |
| 3284 | |
| 3285 void Assembler::fcomp_s(Address src) { | |
| 3286 InstructionMark im(this); | |
| 3287 emit_byte(0xD8); | |
| 3288 emit_operand32(rbx, src); | |
| 3289 } | |
| 3290 | |
| 3291 void Assembler::fcompp() { | |
| 3292 emit_byte(0xDE); | |
| 3293 emit_byte(0xD9); | |
| 3294 } | |
| 3295 | |
| 3296 void Assembler::fcos() { | |
| 3297 emit_byte(0xD9); | |
| 0 | 3298 emit_byte(0xFF); |
| 304 | 3299 } |
| 3300 | |
| 3301 void Assembler::fdecstp() { | |
| 3302 emit_byte(0xD9); | |
| 3303 emit_byte(0xF6); | |
| 3304 } | |
| 3305 | |
| 3306 void Assembler::fdiv(int i) { | |
| 3307 emit_farith(0xD8, 0xF0, i); | |
| 3308 } | |
| 3309 | |
| 3310 void Assembler::fdiv_d(Address src) { | |
| 3311 InstructionMark im(this); | |
| 3312 emit_byte(0xDC); | |
| 3313 emit_operand32(rsi, src); | |
| 3314 } | |
| 3315 | |
| 3316 void Assembler::fdiv_s(Address src) { | |
| 3317 InstructionMark im(this); | |
| 3318 emit_byte(0xD8); | |
| 3319 emit_operand32(rsi, src); | |
| 3320 } | |
| 3321 | |
| 3322 void Assembler::fdiva(int i) { | |
| 3323 emit_farith(0xDC, 0xF8, i); | |
| 3324 } | |
| 3325 | |
| 3326 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994) | |
| 3327 // is erroneous for some of the floating-point instructions below. | |
| 3328 | |
| 3329 void Assembler::fdivp(int i) { | |
| 3330 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong) | |
| 3331 } | |
| 3332 | |
| 3333 void Assembler::fdivr(int i) { | |
| 3334 emit_farith(0xD8, 0xF8, i); | |
| 3335 } | |
| 3336 | |
| 3337 void Assembler::fdivr_d(Address src) { | |
| 3338 InstructionMark im(this); | |
| 3339 emit_byte(0xDC); | |
| 3340 emit_operand32(rdi, src); | |
| 3341 } | |
| 3342 | |
| 3343 void Assembler::fdivr_s(Address src) { | |
| 3344 InstructionMark im(this); | |
| 3345 emit_byte(0xD8); | |
| 3346 emit_operand32(rdi, src); | |
| 3347 } | |
| 3348 | |
| 3349 void Assembler::fdivra(int i) { | |
| 3350 emit_farith(0xDC, 0xF0, i); | |
| 3351 } | |
| 3352 | |
| 3353 void Assembler::fdivrp(int i) { | |
| 3354 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong) | |
| 3355 } | |
| 3356 | |
| 3357 void Assembler::ffree(int i) { | |
| 3358 emit_farith(0xDD, 0xC0, i); | |
| 3359 } | |
| 3360 | |
| 3361 void Assembler::fild_d(Address adr) { | |
| 3362 InstructionMark im(this); | |
| 3363 emit_byte(0xDF); | |
| 3364 emit_operand32(rbp, adr); | |
| 3365 } | |
| 3366 | |
| 3367 void Assembler::fild_s(Address adr) { | |
| 3368 InstructionMark im(this); | |
| 3369 emit_byte(0xDB); | |
| 3370 emit_operand32(rax, adr); | |
| 3371 } | |
| 3372 | |
| 3373 void Assembler::fincstp() { | |
| 3374 emit_byte(0xD9); | |
| 3375 emit_byte(0xF7); | |
| 3376 } | |
| 3377 | |
| 3378 void Assembler::finit() { | |
| 3379 emit_byte(0x9B); | |
| 3380 emit_byte(0xDB); | |
| 3381 emit_byte(0xE3); | |
| 3382 } | |
| 3383 | |
| 3384 void Assembler::fist_s(Address adr) { | |
| 3385 InstructionMark im(this); | |
| 3386 emit_byte(0xDB); | |
| 3387 emit_operand32(rdx, adr); | |
| 3388 } | |
| 3389 | |
| 3390 void Assembler::fistp_d(Address adr) { | |
| 3391 InstructionMark im(this); | |
| 3392 emit_byte(0xDF); | |
| 3393 emit_operand32(rdi, adr); | |
| 3394 } | |
| 3395 | |
| 3396 void Assembler::fistp_s(Address adr) { | |
| 3397 InstructionMark im(this); | |
| 3398 emit_byte(0xDB); | |
| 3399 emit_operand32(rbx, adr); | |
| 3400 } | |
| 0 | 3401 |
| 3402 void Assembler::fld1() { | |
| 3403 emit_byte(0xD9); | |
| 3404 emit_byte(0xE8); | |
| 3405 } | |
| 3406 | |
| 304 | 3407 void Assembler::fld_d(Address adr) { |
| 3408 InstructionMark im(this); | |
| 3409 emit_byte(0xDD); | |
| 3410 emit_operand32(rax, adr); | |
| 3411 } | |
| 0 | 3412 |
| 3413 void Assembler::fld_s(Address adr) { | |
| 3414 InstructionMark im(this); | |
| 3415 emit_byte(0xD9); | |
| 304 | 3416 emit_operand32(rax, adr); |
| 3417 } | |
| 3418 | |
| 3419 | |
| 3420 void Assembler::fld_s(int index) { | |
| 0 | 3421 emit_farith(0xD9, 0xC0, index); |
| 3422 } | |
| 3423 | |
| 3424 void Assembler::fld_x(Address adr) { | |
| 3425 InstructionMark im(this); | |
| 3426 emit_byte(0xDB); | |
| 304 | 3427 emit_operand32(rbp, adr); |
| 3428 } | |
| 3429 | |
| 3430 void Assembler::fldcw(Address src) { | |
| 3431 InstructionMark im(this); | |
| 3432 emit_byte(0xd9); | |
| 3433 emit_operand32(rbp, src); | |
| 3434 } | |
| 3435 | |
| 3436 void Assembler::fldenv(Address src) { | |
| 0 | 3437 InstructionMark im(this); |
| 3438 emit_byte(0xD9); | |
| 304 | 3439 emit_operand32(rsp, src); |
| 3440 } | |
| 3441 | |
| 3442 void Assembler::fldlg2() { | |
| 0 | 3443 emit_byte(0xD9); |
| 304 | 3444 emit_byte(0xEC); |
| 3445 } | |
| 0 | 3446 |
| 3447 void Assembler::fldln2() { | |
| 3448 emit_byte(0xD9); | |
| 3449 emit_byte(0xED); | |
| 3450 } | |
| 3451 | |
| 304 | 3452 void Assembler::fldz() { |
| 0 | 3453 emit_byte(0xD9); |
| 304 | 3454 emit_byte(0xEE); |
| 3455 } | |
| 0 | 3456 |
| 3457 void Assembler::flog() { | |
| 3458 fldln2(); | |
| 3459 fxch(); | |
| 3460 fyl2x(); | |
| 3461 } | |
| 3462 | |
| 3463 void Assembler::flog10() { | |
| 3464 fldlg2(); | |
| 3465 fxch(); | |
| 3466 fyl2x(); | |
| 3467 } | |
| 3468 | |
| 304 | 3469 void Assembler::fmul(int i) { |
| 3470 emit_farith(0xD8, 0xC8, i); | |
| 3471 } | |
| 3472 | |
| 3473 void Assembler::fmul_d(Address src) { | |
| 3474 InstructionMark im(this); | |
| 3475 emit_byte(0xDC); | |
| 3476 emit_operand32(rcx, src); | |
| 3477 } | |
| 3478 | |
| 3479 void Assembler::fmul_s(Address src) { | |
| 3480 InstructionMark im(this); | |
| 3481 emit_byte(0xD8); | |
| 3482 emit_operand32(rcx, src); | |
| 3483 } | |
| 3484 | |
| 3485 void Assembler::fmula(int i) { | |
| 3486 emit_farith(0xDC, 0xC8, i); | |
| 3487 } | |
| 3488 | |
| 3489 void Assembler::fmulp(int i) { | |
| 3490 emit_farith(0xDE, 0xC8, i); | |
| 3491 } | |
| 3492 | |
| 3493 void Assembler::fnsave(Address dst) { | |
| 3494 InstructionMark im(this); | |
| 3495 emit_byte(0xDD); | |
| 3496 emit_operand32(rsi, dst); | |
| 3497 } | |
| 3498 | |
| 3499 void Assembler::fnstcw(Address src) { | |
| 3500 InstructionMark im(this); | |
| 3501 emit_byte(0x9B); | |
| 3502 emit_byte(0xD9); | |
| 3503 emit_operand32(rdi, src); | |
| 3504 } | |
| 3505 | |
| 3506 void Assembler::fnstsw_ax() { | |
| 3507 emit_byte(0xdF); | |
| 3508 emit_byte(0xE0); | |
| 3509 } | |
| 3510 | |
| 3511 void Assembler::fprem() { | |
| 3512 emit_byte(0xD9); | |
| 3513 emit_byte(0xF8); | |
| 3514 } | |
| 3515 | |
| 3516 void Assembler::fprem1() { | |
| 3517 emit_byte(0xD9); | |
| 3518 emit_byte(0xF5); | |
| 3519 } | |
| 3520 | |
| 3521 void Assembler::frstor(Address src) { | |
| 3522 InstructionMark im(this); | |
| 3523 emit_byte(0xDD); | |
| 3524 emit_operand32(rsp, src); | |
| 3525 } | |
| 0 | 3526 |
| 3527 void Assembler::fsin() { | |
| 3528 emit_byte(0xD9); | |
| 3529 emit_byte(0xFE); | |
| 3530 } | |
| 3531 | |
| 304 | 3532 void Assembler::fsqrt() { |
| 3533 emit_byte(0xD9); | |
| 3534 emit_byte(0xFA); | |
| 3535 } | |
| 3536 | |
| 3537 void Assembler::fst_d(Address adr) { | |
| 3538 InstructionMark im(this); | |
| 3539 emit_byte(0xDD); | |
| 3540 emit_operand32(rdx, adr); | |
| 3541 } | |
| 3542 | |
| 3543 void Assembler::fst_s(Address adr) { | |
| 3544 InstructionMark im(this); | |
| 3545 emit_byte(0xD9); | |
| 3546 emit_operand32(rdx, adr); | |
| 3547 } | |
| 3548 | |
| 3549 void Assembler::fstp_d(Address adr) { | |
| 3550 InstructionMark im(this); | |
| 3551 emit_byte(0xDD); | |
| 3552 emit_operand32(rbx, adr); | |
| 3553 } | |
| 3554 | |
| 3555 void Assembler::fstp_d(int index) { | |
| 3556 emit_farith(0xDD, 0xD8, index); | |
| 3557 } | |
| 3558 | |
| 3559 void Assembler::fstp_s(Address adr) { | |
| 3560 InstructionMark im(this); | |
| 0 | 3561 emit_byte(0xD9); |
| 304 | 3562 emit_operand32(rbx, adr); |
| 3563 } | |
| 3564 | |
| 3565 void Assembler::fstp_x(Address adr) { | |
| 3566 InstructionMark im(this); | |
| 3567 emit_byte(0xDB); | |
| 3568 emit_operand32(rdi, adr); | |
| 3569 } | |
| 3570 | |
| 3571 void Assembler::fsub(int i) { | |
| 3572 emit_farith(0xD8, 0xE0, i); | |
| 3573 } | |
| 3574 | |
| 3575 void Assembler::fsub_d(Address src) { | |
| 3576 InstructionMark im(this); | |
| 3577 emit_byte(0xDC); | |
| 3578 emit_operand32(rsp, src); | |
| 3579 } | |
| 3580 | |
| 3581 void Assembler::fsub_s(Address src) { | |
| 3582 InstructionMark im(this); | |
| 3583 emit_byte(0xD8); | |
| 3584 emit_operand32(rsp, src); | |
| 3585 } | |
| 3586 | |
| 3587 void Assembler::fsuba(int i) { | |
| 3588 emit_farith(0xDC, 0xE8, i); | |
| 3589 } | |
| 3590 | |
| 3591 void Assembler::fsubp(int i) { | |
| 3592 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong) | |
| 3593 } | |
| 3594 | |
| 3595 void Assembler::fsubr(int i) { | |
| 3596 emit_farith(0xD8, 0xE8, i); | |
| 3597 } | |
| 3598 | |
| 3599 void Assembler::fsubr_d(Address src) { | |
| 3600 InstructionMark im(this); | |
| 3601 emit_byte(0xDC); | |
| 3602 emit_operand32(rbp, src); | |
| 3603 } | |
| 3604 | |
| 3605 void Assembler::fsubr_s(Address src) { | |
| 3606 InstructionMark im(this); | |
| 3607 emit_byte(0xD8); | |
| 3608 emit_operand32(rbp, src); | |
| 3609 } | |
| 3610 | |
| 3611 void Assembler::fsubra(int i) { | |
| 3612 emit_farith(0xDC, 0xE0, i); | |
| 3613 } | |
| 3614 | |
| 3615 void Assembler::fsubrp(int i) { | |
| 3616 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong) | |
| 0 | 3617 } |
| 3618 | |
| 3619 void Assembler::ftan() { | |
| 3620 emit_byte(0xD9); | |
| 3621 emit_byte(0xF2); | |
| 3622 emit_byte(0xDD); | |
| 3623 emit_byte(0xD8); | |
| 3624 } | |
| 3625 | |
| 304 | 3626 void Assembler::ftst() { |
| 0 | 3627 emit_byte(0xD9); |
| 304 | 3628 emit_byte(0xE4); |
| 3629 } | |
| 0 | 3630 |
| 3631 void Assembler::fucomi(int i) { | |
| 3632 // make sure the instruction is supported (introduced for P6, together with cmov) | |
| 3633 guarantee(VM_Version::supports_cmov(), "illegal instruction"); | |
| 3634 emit_farith(0xDB, 0xE8, i); | |
| 3635 } | |
| 3636 | |
| 3637 void Assembler::fucomip(int i) { | |
| 3638 // make sure the instruction is supported (introduced for P6, together with cmov) | |
| 3639 guarantee(VM_Version::supports_cmov(), "illegal instruction"); | |
| 3640 emit_farith(0xDF, 0xE8, i); | |
| 3641 } | |
| 3642 | |
| 3643 void Assembler::fwait() { | |
| 3644 emit_byte(0x9B); | |
| 3645 } | |
| 3646 | |
| 304 | 3647 void Assembler::fxch(int i) { |
| 3648 emit_farith(0xD9, 0xC8, i); | |
| 3649 } | |
| 3650 | |
| 3651 void Assembler::fyl2x() { | |
| 0 | 3652 emit_byte(0xD9); |
| 304 | 3653 emit_byte(0xF1); |
| 3654 } | |
| 3655 | |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
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|
3656 void Assembler::frndint() { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
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diff
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|
3657 emit_byte(0xD9); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
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5984
diff
changeset
|
3658 emit_byte(0xFC); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
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|
3659 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
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|
3660 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
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diff
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|
3661 void Assembler::f2xm1() { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
3662 emit_byte(0xD9); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
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5984
diff
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|
3663 emit_byte(0xF0); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
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|
3664 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
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|
3665 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
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|
3666 void Assembler::fldl2e() { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
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parents:
5984
diff
changeset
|
3667 emit_byte(0xD9); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
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parents:
5984
diff
changeset
|
3668 emit_byte(0xEA); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
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diff
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|
3669 } |
|
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|
3670 |
| 4759 | 3671 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding. |
| 3672 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 }; | |
| 3673 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding. | |
| 3674 static int simd_opc[4] = { 0, 0, 0x38, 0x3A }; | |
| 3675 | |
| 3676 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding. | |
| 3677 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) { | |
| 3678 if (pre > 0) { | |
| 3679 emit_byte(simd_pre[pre]); | |
| 3680 } | |
| 3681 if (rex_w) { | |
| 3682 prefixq(adr, xreg); | |
| 3683 } else { | |
| 3684 prefix(adr, xreg); | |
| 3685 } | |
| 3686 if (opc > 0) { | |
| 3687 emit_byte(0x0F); | |
| 3688 int opc2 = simd_opc[opc]; | |
| 3689 if (opc2 > 0) { | |
| 3690 emit_byte(opc2); | |
| 3691 } | |
| 3692 } | |
| 3693 } | |
| 3694 | |
| 3695 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) { | |
| 3696 if (pre > 0) { | |
| 3697 emit_byte(simd_pre[pre]); | |
| 3698 } | |
| 3699 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : | |
| 3700 prefix_and_encode(dst_enc, src_enc); | |
| 3701 if (opc > 0) { | |
| 3702 emit_byte(0x0F); | |
| 3703 int opc2 = simd_opc[opc]; | |
| 3704 if (opc2 > 0) { | |
| 3705 emit_byte(opc2); | |
| 3706 } | |
| 3707 } | |
| 3708 return encode; | |
| 3709 } | |
| 3710 | |
| 3711 | |
| 3712 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, int nds_enc, VexSimdPrefix pre, VexOpcode opc, bool vector256) { | |
| 3713 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) { | |
| 3714 prefix(VEX_3bytes); | |
| 3715 | |
| 3716 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0); | |
| 3717 byte1 = (~byte1) & 0xE0; | |
| 3718 byte1 |= opc; | |
| 3719 a_byte(byte1); | |
| 3720 | |
| 3721 int byte2 = ((~nds_enc) & 0xf) << 3; | |
| 3722 byte2 |= (vex_w ? VEX_W : 0) | (vector256 ? 4 : 0) | pre; | |
| 3723 emit_byte(byte2); | |
| 3724 } else { | |
| 3725 prefix(VEX_2bytes); | |
| 3726 | |
| 3727 int byte1 = vex_r ? VEX_R : 0; | |
| 3728 byte1 = (~byte1) & 0x80; | |
| 3729 byte1 |= ((~nds_enc) & 0xf) << 3; | |
| 3730 byte1 |= (vector256 ? 4 : 0) | pre; | |
| 3731 emit_byte(byte1); | |
| 3732 } | |
| 3733 } | |
| 3734 | |
| 3735 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256){ | |
| 3736 bool vex_r = (xreg_enc >= 8); | |
| 3737 bool vex_b = adr.base_needs_rex(); | |
| 3738 bool vex_x = adr.index_needs_rex(); | |
| 3739 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256); | |
| 3740 } | |
| 3741 | |
| 3742 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256) { | |
| 3743 bool vex_r = (dst_enc >= 8); | |
| 3744 bool vex_b = (src_enc >= 8); | |
| 3745 bool vex_x = false; | |
| 3746 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256); | |
| 3747 return (((dst_enc & 7) << 3) | (src_enc & 7)); | |
| 3748 } | |
| 3749 | |
| 3750 | |
| 3751 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) { | |
| 3752 if (UseAVX > 0) { | |
| 3753 int xreg_enc = xreg->encoding(); | |
| 3754 int nds_enc = nds->is_valid() ? nds->encoding() : 0; | |
| 3755 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, rex_w, vector256); | |
| 3756 } else { | |
| 3757 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding"); | |
| 3758 rex_prefix(adr, xreg, pre, opc, rex_w); | |
| 3759 } | |
| 3760 } | |
| 3761 | |
| 3762 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) { | |
| 3763 int dst_enc = dst->encoding(); | |
| 3764 int src_enc = src->encoding(); | |
| 3765 if (UseAVX > 0) { | |
| 3766 int nds_enc = nds->is_valid() ? nds->encoding() : 0; | |
| 3767 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector256); | |
| 3768 } else { | |
| 3769 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding"); | |
| 3770 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, rex_w); | |
| 3771 } | |
| 3772 } | |
| 304 | 3773 |
| 3774 #ifndef _LP64 | |
| 3775 | |
| 3776 void Assembler::incl(Register dst) { | |
| 3777 // Don't use it directly. Use MacroAssembler::incrementl() instead. | |
| 4759 | 3778 emit_byte(0x40 | dst->encoding()); |
| 304 | 3779 } |
| 3780 | |
| 3781 void Assembler::lea(Register dst, Address src) { | |
| 3782 leal(dst, src); | |
| 3783 } | |
| 3784 | |
| 3785 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) { | |
| 3786 InstructionMark im(this); | |
| 3787 emit_byte(0xC7); | |
| 3788 emit_operand(rax, dst); | |
| 3789 emit_data((int)imm32, rspec, 0); | |
| 3790 } | |
| 3791 | |
|
642
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|
3792 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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|
3793 InstructionMark im(this); |
|
660978a2a31a
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diff
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|
3794 int encode = prefix_and_encode(dst->encoding()); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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|
3795 emit_byte(0xB8 | encode); |
|
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|
3796 emit_data((int)imm32, rspec, 0); |
|
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|
3797 } |
| 304 | 3798 |
| 3799 void Assembler::popa() { // 32bit | |
| 3800 emit_byte(0x61); | |
| 3801 } | |
| 3802 | |
| 3803 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) { | |
| 3804 InstructionMark im(this); | |
| 3805 emit_byte(0x68); | |
| 3806 emit_data(imm32, rspec, 0); | |
| 3807 } | |
| 3808 | |
| 3809 void Assembler::pusha() { // 32bit | |
| 3810 emit_byte(0x60); | |
| 3811 } | |
| 3812 | |
| 3813 void Assembler::set_byte_if_not_zero(Register dst) { | |
| 0 | 3814 emit_byte(0x0F); |
| 304 | 3815 emit_byte(0x95); |
| 3816 emit_byte(0xE0 | dst->encoding()); | |
| 3817 } | |
| 3818 | |
| 3819 void Assembler::shldl(Register dst, Register src) { | |
| 0 | 3820 emit_byte(0x0F); |
| 304 | 3821 emit_byte(0xA5); |
| 3822 emit_byte(0xC0 | src->encoding() << 3 | dst->encoding()); | |
| 3823 } | |
| 3824 | |
| 3825 void Assembler::shrdl(Register dst, Register src) { | |
| 0 | 3826 emit_byte(0x0F); |
| 304 | 3827 emit_byte(0xAD); |
| 3828 emit_byte(0xC0 | src->encoding() << 3 | dst->encoding()); | |
| 3829 } | |
| 3830 | |
| 3831 #else // LP64 | |
| 3832 | |
| 1369 | 3833 void Assembler::set_byte_if_not_zero(Register dst) { |
| 3834 int enc = prefix_and_encode(dst->encoding(), true); | |
| 3835 emit_byte(0x0F); | |
| 3836 emit_byte(0x95); | |
| 3837 emit_byte(0xE0 | enc); | |
| 3838 } | |
| 3839 | |
| 304 | 3840 // 64bit only pieces of the assembler |
| 3841 // This should only be used by 64bit instructions that can use rip-relative | |
| 3842 // it cannot be used by instructions that want an immediate value. | |
| 3843 | |
| 3844 bool Assembler::reachable(AddressLiteral adr) { | |
| 3845 int64_t disp; | |
| 3846 // None will force a 64bit literal to the code stream. Likely a placeholder | |
| 3847 // for something that will be patched later and we need to certain it will | |
| 3848 // always be reachable. | |
| 3849 if (adr.reloc() == relocInfo::none) { | |
| 3850 return false; | |
| 3851 } | |
| 3852 if (adr.reloc() == relocInfo::internal_word_type) { | |
| 3853 // This should be rip relative and easily reachable. | |
| 3854 return true; | |
| 3855 } | |
| 3856 if (adr.reloc() == relocInfo::virtual_call_type || | |
| 3857 adr.reloc() == relocInfo::opt_virtual_call_type || | |
| 3858 adr.reloc() == relocInfo::static_call_type || | |
| 3859 adr.reloc() == relocInfo::static_stub_type ) { | |
| 3860 // This should be rip relative within the code cache and easily | |
| 3861 // reachable until we get huge code caches. (At which point | |
| 3862 // ic code is going to have issues). | |
| 3863 return true; | |
| 3864 } | |
| 3865 if (adr.reloc() != relocInfo::external_word_type && | |
| 3866 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special | |
| 3867 adr.reloc() != relocInfo::poll_type && // relocs to identify them | |
| 3868 adr.reloc() != relocInfo::runtime_call_type ) { | |
| 3869 return false; | |
| 3870 } | |
| 3871 | |
| 3872 // Stress the correction code | |
| 3873 if (ForceUnreachable) { | |
| 3874 // Must be runtimecall reloc, see if it is in the codecache | |
| 3875 // Flipping stuff in the codecache to be unreachable causes issues | |
| 3876 // with things like inline caches where the additional instructions | |
| 3877 // are not handled. | |
| 3878 if (CodeCache::find_blob(adr._target) == NULL) { | |
| 3879 return false; | |
| 3880 } | |
| 3881 } | |
| 3882 // For external_word_type/runtime_call_type if it is reachable from where we | |
| 3883 // are now (possibly a temp buffer) and where we might end up | |
| 3884 // anywhere in the codeCache then we are always reachable. | |
| 3885 // This would have to change if we ever save/restore shared code | |
| 3886 // to be more pessimistic. | |
| 3887 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int)); | |
| 3888 if (!is_simm32(disp)) return false; | |
| 3889 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int)); | |
| 3890 if (!is_simm32(disp)) return false; | |
| 3891 | |
| 3892 disp = (int64_t)adr._target - ((int64_t)_code_pos + sizeof(int)); | |
| 3893 | |
| 3894 // Because rip relative is a disp + address_of_next_instruction and we | |
| 3895 // don't know the value of address_of_next_instruction we apply a fudge factor | |
| 3896 // to make sure we will be ok no matter the size of the instruction we get placed into. | |
| 3897 // We don't have to fudge the checks above here because they are already worst case. | |
| 3898 | |
| 3899 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal | |
| 3900 // + 4 because better safe than sorry. | |
| 3901 const int fudge = 12 + 4; | |
| 3902 if (disp < 0) { | |
| 3903 disp -= fudge; | |
| 3904 } else { | |
| 3905 disp += fudge; | |
| 3906 } | |
| 3907 return is_simm32(disp); | |
| 3908 } | |
| 3909 | |
|
2404
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diff
changeset
|
3910 // Check if the polling page is not reachable from the code cache using rip-relative |
|
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diff
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|
3911 // addressing. |
|
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diff
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|
3912 bool Assembler::is_polling_page_far() { |
|
b40d4fa697bf
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diff
changeset
|
3913 intptr_t addr = (intptr_t)os::get_polling_page(); |
|
4118
59bc0d4d9ea3
7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
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parents:
3938
diff
changeset
|
3914 return ForceUnreachable || |
|
59bc0d4d9ea3
7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
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3938
diff
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|
3915 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) || |
|
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|
3916 !is_simm32(addr - (intptr_t)CodeCache::high_bound()); |
|
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|
3917 } |
|
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|
3918 |
| 304 | 3919 void Assembler::emit_data64(jlong data, |
| 3920 relocInfo::relocType rtype, | |
| 3921 int format) { | |
| 3922 if (rtype == relocInfo::none) { | |
| 3923 emit_long64(data); | |
| 3924 } else { | |
| 3925 emit_data64(data, Relocation::spec_simple(rtype), format); | |
| 3926 } | |
| 3927 } | |
| 3928 | |
| 3929 void Assembler::emit_data64(jlong data, | |
| 3930 RelocationHolder const& rspec, | |
| 3931 int format) { | |
| 3932 assert(imm_operand == 0, "default format must be immediate in this file"); | |
| 3933 assert(imm_operand == format, "must be immediate"); | |
| 3934 assert(inst_mark() != NULL, "must be inside InstructionMark"); | |
| 3935 // Do not use AbstractAssembler::relocate, which is not intended for | |
| 3936 // embedded words. Instead, relocate to the enclosing instruction. | |
| 3937 code_section()->relocate(inst_mark(), rspec, format); | |
| 3938 #ifdef ASSERT | |
| 3939 check_relocation(rspec, format); | |
| 3940 #endif | |
| 3941 emit_long64(data); | |
| 3942 } | |
| 3943 | |
| 3944 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) { | |
| 3945 if (reg_enc >= 8) { | |
| 3946 prefix(REX_B); | |
| 3947 reg_enc -= 8; | |
| 3948 } else if (byteinst && reg_enc >= 4) { | |
| 3949 prefix(REX); | |
| 3950 } | |
| 3951 return reg_enc; | |
| 3952 } | |
| 3953 | |
| 3954 int Assembler::prefixq_and_encode(int reg_enc) { | |
| 3955 if (reg_enc < 8) { | |
| 3956 prefix(REX_W); | |
| 3957 } else { | |
| 3958 prefix(REX_WB); | |
| 3959 reg_enc -= 8; | |
| 3960 } | |
| 3961 return reg_enc; | |
| 3962 } | |
| 3963 | |
| 3964 int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) { | |
| 3965 if (dst_enc < 8) { | |
| 3966 if (src_enc >= 8) { | |
| 3967 prefix(REX_B); | |
| 3968 src_enc -= 8; | |
| 3969 } else if (byteinst && src_enc >= 4) { | |
| 3970 prefix(REX); | |
| 3971 } | |
| 3972 } else { | |
| 3973 if (src_enc < 8) { | |
| 3974 prefix(REX_R); | |
| 3975 } else { | |
| 3976 prefix(REX_RB); | |
| 3977 src_enc -= 8; | |
| 3978 } | |
| 3979 dst_enc -= 8; | |
| 3980 } | |
| 3981 return dst_enc << 3 | src_enc; | |
| 3982 } | |
| 3983 | |
| 3984 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) { | |
| 3985 if (dst_enc < 8) { | |
| 3986 if (src_enc < 8) { | |
| 3987 prefix(REX_W); | |
| 3988 } else { | |
| 3989 prefix(REX_WB); | |
| 3990 src_enc -= 8; | |
| 3991 } | |
| 3992 } else { | |
| 3993 if (src_enc < 8) { | |
| 3994 prefix(REX_WR); | |
| 3995 } else { | |
| 3996 prefix(REX_WRB); | |
| 3997 src_enc -= 8; | |
| 3998 } | |
| 3999 dst_enc -= 8; | |
| 4000 } | |
| 4001 return dst_enc << 3 | src_enc; | |
| 4002 } | |
| 4003 | |
| 4004 void Assembler::prefix(Register reg) { | |
| 4005 if (reg->encoding() >= 8) { | |
| 4006 prefix(REX_B); | |
| 4007 } | |
| 4008 } | |
| 4009 | |
| 4010 void Assembler::prefix(Address adr) { | |
| 4011 if (adr.base_needs_rex()) { | |
| 4012 if (adr.index_needs_rex()) { | |
| 4013 prefix(REX_XB); | |
| 4014 } else { | |
| 4015 prefix(REX_B); | |
| 4016 } | |
| 4017 } else { | |
| 4018 if (adr.index_needs_rex()) { | |
| 4019 prefix(REX_X); | |
| 4020 } | |
| 4021 } | |
| 4022 } | |
| 4023 | |
| 4024 void Assembler::prefixq(Address adr) { | |
| 4025 if (adr.base_needs_rex()) { | |
| 4026 if (adr.index_needs_rex()) { | |
| 4027 prefix(REX_WXB); | |
| 4028 } else { | |
| 4029 prefix(REX_WB); | |
| 4030 } | |
| 4031 } else { | |
| 4032 if (adr.index_needs_rex()) { | |
| 4033 prefix(REX_WX); | |
| 4034 } else { | |
| 4035 prefix(REX_W); | |
| 4036 } | |
| 4037 } | |
| 4038 } | |
| 4039 | |
| 4040 | |
| 4041 void Assembler::prefix(Address adr, Register reg, bool byteinst) { | |
| 4042 if (reg->encoding() < 8) { | |
| 4043 if (adr.base_needs_rex()) { | |
| 4044 if (adr.index_needs_rex()) { | |
| 4045 prefix(REX_XB); | |
| 4046 } else { | |
| 4047 prefix(REX_B); | |
| 4048 } | |
| 4049 } else { | |
| 4050 if (adr.index_needs_rex()) { | |
| 4051 prefix(REX_X); | |
| 3855 | 4052 } else if (byteinst && reg->encoding() >= 4 ) { |
| 304 | 4053 prefix(REX); |
| 4054 } | |
| 4055 } | |
| 4056 } else { | |
| 4057 if (adr.base_needs_rex()) { | |
| 4058 if (adr.index_needs_rex()) { | |
| 4059 prefix(REX_RXB); | |
| 4060 } else { | |
| 4061 prefix(REX_RB); | |
| 4062 } | |
| 4063 } else { | |
| 4064 if (adr.index_needs_rex()) { | |
| 4065 prefix(REX_RX); | |
| 4066 } else { | |
| 4067 prefix(REX_R); | |
| 4068 } | |
| 4069 } | |
| 4070 } | |
| 4071 } | |
| 4072 | |
| 4073 void Assembler::prefixq(Address adr, Register src) { | |
| 4074 if (src->encoding() < 8) { | |
| 4075 if (adr.base_needs_rex()) { | |
| 4076 if (adr.index_needs_rex()) { | |
| 4077 prefix(REX_WXB); | |
| 4078 } else { | |
| 4079 prefix(REX_WB); | |
| 4080 } | |
| 4081 } else { | |
| 4082 if (adr.index_needs_rex()) { | |
| 4083 prefix(REX_WX); | |
| 4084 } else { | |
| 4085 prefix(REX_W); | |
| 4086 } | |
| 4087 } | |
| 4088 } else { | |
| 4089 if (adr.base_needs_rex()) { | |
| 4090 if (adr.index_needs_rex()) { | |
| 4091 prefix(REX_WRXB); | |
| 4092 } else { | |
| 4093 prefix(REX_WRB); | |
| 4094 } | |
| 4095 } else { | |
| 4096 if (adr.index_needs_rex()) { | |
| 4097 prefix(REX_WRX); | |
| 4098 } else { | |
| 4099 prefix(REX_WR); | |
| 4100 } | |
| 4101 } | |
| 4102 } | |
| 4103 } | |
| 4104 | |
| 4105 void Assembler::prefix(Address adr, XMMRegister reg) { | |
| 4106 if (reg->encoding() < 8) { | |
| 4107 if (adr.base_needs_rex()) { | |
| 4108 if (adr.index_needs_rex()) { | |
| 4109 prefix(REX_XB); | |
| 4110 } else { | |
| 4111 prefix(REX_B); | |
| 4112 } | |
| 4113 } else { | |
| 4114 if (adr.index_needs_rex()) { | |
| 4115 prefix(REX_X); | |
| 4116 } | |
| 4117 } | |
| 4118 } else { | |
| 4119 if (adr.base_needs_rex()) { | |
| 4120 if (adr.index_needs_rex()) { | |
| 4121 prefix(REX_RXB); | |
| 4122 } else { | |
| 4123 prefix(REX_RB); | |
| 4124 } | |
| 4125 } else { | |
| 4126 if (adr.index_needs_rex()) { | |
| 4127 prefix(REX_RX); | |
| 4128 } else { | |
| 4129 prefix(REX_R); | |
| 4130 } | |
| 4131 } | |
| 4132 } | |
| 4133 } | |
| 4134 | |
| 4759 | 4135 void Assembler::prefixq(Address adr, XMMRegister src) { |
| 4136 if (src->encoding() < 8) { | |
| 4137 if (adr.base_needs_rex()) { | |
| 4138 if (adr.index_needs_rex()) { | |
| 4139 prefix(REX_WXB); | |
| 4140 } else { | |
| 4141 prefix(REX_WB); | |
| 4142 } | |
| 4143 } else { | |
| 4144 if (adr.index_needs_rex()) { | |
| 4145 prefix(REX_WX); | |
| 4146 } else { | |
| 4147 prefix(REX_W); | |
| 4148 } | |
| 4149 } | |
| 4150 } else { | |
| 4151 if (adr.base_needs_rex()) { | |
| 4152 if (adr.index_needs_rex()) { | |
| 4153 prefix(REX_WRXB); | |
| 4154 } else { | |
| 4155 prefix(REX_WRB); | |
| 4156 } | |
| 4157 } else { | |
| 4158 if (adr.index_needs_rex()) { | |
| 4159 prefix(REX_WRX); | |
| 4160 } else { | |
| 4161 prefix(REX_WR); | |
| 4162 } | |
| 4163 } | |
| 4164 } | |
| 4165 } | |
| 4166 | |
| 304 | 4167 void Assembler::adcq(Register dst, int32_t imm32) { |
| 4168 (void) prefixq_and_encode(dst->encoding()); | |
| 4169 emit_arith(0x81, 0xD0, dst, imm32); | |
| 4170 } | |
| 4171 | |
| 4172 void Assembler::adcq(Register dst, Address src) { | |
| 4173 InstructionMark im(this); | |
| 4174 prefixq(src, dst); | |
| 4175 emit_byte(0x13); | |
| 4176 emit_operand(dst, src); | |
| 4177 } | |
| 4178 | |
| 4179 void Assembler::adcq(Register dst, Register src) { | |
| 4180 (int) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4181 emit_arith(0x13, 0xC0, dst, src); | |
| 4182 } | |
| 4183 | |
| 4184 void Assembler::addq(Address dst, int32_t imm32) { | |
| 4185 InstructionMark im(this); | |
| 4186 prefixq(dst); | |
| 4187 emit_arith_operand(0x81, rax, dst,imm32); | |
| 4188 } | |
| 4189 | |
| 4190 void Assembler::addq(Address dst, Register src) { | |
| 4191 InstructionMark im(this); | |
| 4192 prefixq(dst, src); | |
| 4193 emit_byte(0x01); | |
| 4194 emit_operand(src, dst); | |
| 4195 } | |
| 4196 | |
| 4197 void Assembler::addq(Register dst, int32_t imm32) { | |
| 4198 (void) prefixq_and_encode(dst->encoding()); | |
| 4199 emit_arith(0x81, 0xC0, dst, imm32); | |
| 4200 } | |
| 4201 | |
| 4202 void Assembler::addq(Register dst, Address src) { | |
| 4203 InstructionMark im(this); | |
| 4204 prefixq(src, dst); | |
| 4205 emit_byte(0x03); | |
| 4206 emit_operand(dst, src); | |
| 4207 } | |
| 4208 | |
| 4209 void Assembler::addq(Register dst, Register src) { | |
| 4210 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4211 emit_arith(0x03, 0xC0, dst, src); | |
| 4212 } | |
| 4213 | |
| 3783 | 4214 void Assembler::andq(Address dst, int32_t imm32) { |
| 4215 InstructionMark im(this); | |
| 4216 prefixq(dst); | |
| 4217 emit_byte(0x81); | |
| 4218 emit_operand(rsp, dst, 4); | |
| 4219 emit_long(imm32); | |
| 4220 } | |
| 4221 | |
| 304 | 4222 void Assembler::andq(Register dst, int32_t imm32) { |
| 4223 (void) prefixq_and_encode(dst->encoding()); | |
| 4224 emit_arith(0x81, 0xE0, dst, imm32); | |
| 4225 } | |
| 4226 | |
| 4227 void Assembler::andq(Register dst, Address src) { | |
| 4228 InstructionMark im(this); | |
| 4229 prefixq(src, dst); | |
| 4230 emit_byte(0x23); | |
| 4231 emit_operand(dst, src); | |
| 4232 } | |
| 4233 | |
| 4234 void Assembler::andq(Register dst, Register src) { | |
| 4235 (int) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4236 emit_arith(0x23, 0xC0, dst, src); | |
| 4237 } | |
| 4238 | |
|
775
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diff
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|
4239 void Assembler::bsfq(Register dst, Register src) { |
|
93c14e5562c4
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diff
changeset
|
4240 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
|
93c14e5562c4
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diff
changeset
|
4241 emit_byte(0x0F); |
|
93c14e5562c4
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twisti
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diff
changeset
|
4242 emit_byte(0xBC); |
|
93c14e5562c4
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diff
changeset
|
4243 emit_byte(0xC0 | encode); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
4244 } |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
4245 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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parents:
710
diff
changeset
|
4246 void Assembler::bsrq(Register dst, Register src) { |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
4247 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT"); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
4248 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
4249 emit_byte(0x0F); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
4250 emit_byte(0xBD); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
4251 emit_byte(0xC0 | encode); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
4252 } |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
4253 |
| 304 | 4254 void Assembler::bswapq(Register reg) { |
| 4255 int encode = prefixq_and_encode(reg->encoding()); | |
| 4256 emit_byte(0x0F); | |
| 4257 emit_byte(0xC8 | encode); | |
| 4258 } | |
| 4259 | |
| 4260 void Assembler::cdqq() { | |
| 4261 prefix(REX_W); | |
| 4262 emit_byte(0x99); | |
| 4263 } | |
| 4264 | |
| 4265 void Assembler::clflush(Address adr) { | |
| 4266 prefix(adr); | |
| 4267 emit_byte(0x0F); | |
| 4268 emit_byte(0xAE); | |
| 4269 emit_operand(rdi, adr); | |
| 4270 } | |
| 4271 | |
| 4272 void Assembler::cmovq(Condition cc, Register dst, Register src) { | |
| 4273 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4274 emit_byte(0x0F); | |
| 4275 emit_byte(0x40 | cc); | |
| 4276 emit_byte(0xC0 | encode); | |
| 4277 } | |
| 4278 | |
| 4279 void Assembler::cmovq(Condition cc, Register dst, Address src) { | |
| 4280 InstructionMark im(this); | |
| 4281 prefixq(src, dst); | |
| 4282 emit_byte(0x0F); | |
| 4283 emit_byte(0x40 | cc); | |
| 4284 emit_operand(dst, src); | |
| 4285 } | |
| 4286 | |
| 4287 void Assembler::cmpq(Address dst, int32_t imm32) { | |
| 4288 InstructionMark im(this); | |
| 4289 prefixq(dst); | |
| 4290 emit_byte(0x81); | |
| 4291 emit_operand(rdi, dst, 4); | |
| 4292 emit_long(imm32); | |
| 4293 } | |
| 4294 | |
| 4295 void Assembler::cmpq(Register dst, int32_t imm32) { | |
| 4296 (void) prefixq_and_encode(dst->encoding()); | |
| 4297 emit_arith(0x81, 0xF8, dst, imm32); | |
| 4298 } | |
| 4299 | |
| 4300 void Assembler::cmpq(Address dst, Register src) { | |
| 4301 InstructionMark im(this); | |
| 4302 prefixq(dst, src); | |
| 4303 emit_byte(0x3B); | |
| 4304 emit_operand(src, dst); | |
| 4305 } | |
| 4306 | |
| 4307 void Assembler::cmpq(Register dst, Register src) { | |
| 4308 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4309 emit_arith(0x3B, 0xC0, dst, src); | |
| 4310 } | |
| 4311 | |
| 4312 void Assembler::cmpq(Register dst, Address src) { | |
| 4313 InstructionMark im(this); | |
| 4314 prefixq(src, dst); | |
| 4315 emit_byte(0x3B); | |
| 4316 emit_operand(dst, src); | |
| 4317 } | |
| 4318 | |
| 4319 void Assembler::cmpxchgq(Register reg, Address adr) { | |
| 4320 InstructionMark im(this); | |
| 4321 prefixq(adr, reg); | |
| 4322 emit_byte(0x0F); | |
| 4323 emit_byte(0xB1); | |
| 4324 emit_operand(reg, adr); | |
| 4325 } | |
| 4326 | |
| 4327 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) { | |
| 4328 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 4329 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F2); |
| 304 | 4330 emit_byte(0x2A); |
| 4331 emit_byte(0xC0 | encode); | |
| 4332 } | |
| 4333 | |
| 4759 | 4334 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) { |
| 4335 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4336 InstructionMark im(this); | |
| 4337 simd_prefix_q(dst, dst, src, VEX_SIMD_F2); | |
| 4338 emit_byte(0x2A); | |
| 4339 emit_operand(dst, src); | |
| 4340 } | |
| 4341 | |
| 304 | 4342 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) { |
| 4343 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 4759 | 4344 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F3); |
| 304 | 4345 emit_byte(0x2A); |
| 4346 emit_byte(0xC0 | encode); | |
| 4347 } | |
| 4348 | |
| 4759 | 4349 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) { |
| 4350 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 4351 InstructionMark im(this); | |
| 4352 simd_prefix_q(dst, dst, src, VEX_SIMD_F3); | |
| 4353 emit_byte(0x2A); | |
| 4354 emit_operand(dst, src); | |
| 4355 } | |
| 4356 | |
| 304 | 4357 void Assembler::cvttsd2siq(Register dst, XMMRegister src) { |
| 4358 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 4359 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F2); |
| 304 | 4360 emit_byte(0x2C); |
| 4361 emit_byte(0xC0 | encode); | |
| 4362 } | |
| 4363 | |
| 4364 void Assembler::cvttss2siq(Register dst, XMMRegister src) { | |
| 4365 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 4759 | 4366 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F3); |
| 304 | 4367 emit_byte(0x2C); |
| 4368 emit_byte(0xC0 | encode); | |
| 4369 } | |
| 4370 | |
| 4371 void Assembler::decl(Register dst) { | |
| 4372 // Don't use it directly. Use MacroAssembler::decrementl() instead. | |
| 4373 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode) | |
| 4374 int encode = prefix_and_encode(dst->encoding()); | |
| 4375 emit_byte(0xFF); | |
| 4376 emit_byte(0xC8 | encode); | |
| 4377 } | |
| 4378 | |
| 4379 void Assembler::decq(Register dst) { | |
| 4380 // Don't use it directly. Use MacroAssembler::decrementq() instead. | |
| 4381 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |
| 4382 int encode = prefixq_and_encode(dst->encoding()); | |
| 4383 emit_byte(0xFF); | |
| 4384 emit_byte(0xC8 | encode); | |
| 4385 } | |
| 4386 | |
| 4387 void Assembler::decq(Address dst) { | |
| 4388 // Don't use it directly. Use MacroAssembler::decrementq() instead. | |
| 4389 InstructionMark im(this); | |
| 4390 prefixq(dst); | |
| 4391 emit_byte(0xFF); | |
| 4392 emit_operand(rcx, dst); | |
| 4393 } | |
| 4394 | |
| 4395 void Assembler::fxrstor(Address src) { | |
| 4396 prefixq(src); | |
| 4397 emit_byte(0x0F); | |
| 4398 emit_byte(0xAE); | |
| 4399 emit_operand(as_Register(1), src); | |
| 4400 } | |
| 4401 | |
| 4402 void Assembler::fxsave(Address dst) { | |
| 4403 prefixq(dst); | |
| 4404 emit_byte(0x0F); | |
| 4405 emit_byte(0xAE); | |
| 4406 emit_operand(as_Register(0), dst); | |
| 4407 } | |
| 4408 | |
| 4409 void Assembler::idivq(Register src) { | |
| 4410 int encode = prefixq_and_encode(src->encoding()); | |
| 4411 emit_byte(0xF7); | |
| 4412 emit_byte(0xF8 | encode); | |
| 4413 } | |
| 4414 | |
| 4415 void Assembler::imulq(Register dst, Register src) { | |
| 4416 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4417 emit_byte(0x0F); | |
| 4418 emit_byte(0xAF); | |
| 4419 emit_byte(0xC0 | encode); | |
| 4420 } | |
| 4421 | |
| 4422 void Assembler::imulq(Register dst, Register src, int value) { | |
| 4423 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4424 if (is8bit(value)) { | |
| 4425 emit_byte(0x6B); | |
| 4426 emit_byte(0xC0 | encode); | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1846
diff
changeset
|
4427 emit_byte(value & 0xFF); |
| 304 | 4428 } else { |
| 4429 emit_byte(0x69); | |
| 4430 emit_byte(0xC0 | encode); | |
| 4431 emit_long(value); | |
| 4432 } | |
| 4433 } | |
| 4434 | |
| 4435 void Assembler::incl(Register dst) { | |
| 4436 // Don't use it directly. Use MacroAssembler::incrementl() instead. | |
| 4437 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |
| 4438 int encode = prefix_and_encode(dst->encoding()); | |
| 4439 emit_byte(0xFF); | |
| 4440 emit_byte(0xC0 | encode); | |
| 4441 } | |
| 4442 | |
| 4443 void Assembler::incq(Register dst) { | |
| 4444 // Don't use it directly. Use MacroAssembler::incrementq() instead. | |
| 4445 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |
| 4446 int encode = prefixq_and_encode(dst->encoding()); | |
| 4447 emit_byte(0xFF); | |
| 4448 emit_byte(0xC0 | encode); | |
| 4449 } | |
| 4450 | |
| 4451 void Assembler::incq(Address dst) { | |
| 4452 // Don't use it directly. Use MacroAssembler::incrementq() instead. | |
| 4453 InstructionMark im(this); | |
| 4454 prefixq(dst); | |
| 4455 emit_byte(0xFF); | |
| 4456 emit_operand(rax, dst); | |
| 4457 } | |
| 4458 | |
| 4459 void Assembler::lea(Register dst, Address src) { | |
| 4460 leaq(dst, src); | |
| 4461 } | |
| 4462 | |
| 4463 void Assembler::leaq(Register dst, Address src) { | |
| 4464 InstructionMark im(this); | |
| 4465 prefixq(src, dst); | |
| 4466 emit_byte(0x8D); | |
| 4467 emit_operand(dst, src); | |
| 4468 } | |
| 4469 | |
| 4470 void Assembler::mov64(Register dst, int64_t imm64) { | |
| 4471 InstructionMark im(this); | |
| 4472 int encode = prefixq_and_encode(dst->encoding()); | |
| 4473 emit_byte(0xB8 | encode); | |
| 4474 emit_long64(imm64); | |
| 4475 } | |
| 4476 | |
| 4477 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) { | |
| 4478 InstructionMark im(this); | |
| 4479 int encode = prefixq_and_encode(dst->encoding()); | |
| 4480 emit_byte(0xB8 | encode); | |
| 4481 emit_data64(imm64, rspec); | |
| 4482 } | |
| 4483 | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
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|
4484 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
4485 InstructionMark im(this); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4486 int encode = prefix_and_encode(dst->encoding()); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4487 emit_byte(0xB8 | encode); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4488 emit_data((int)imm32, rspec, narrow_oop_operand); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4489 } |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4490 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4491 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4492 InstructionMark im(this); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4493 prefix(dst); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4494 emit_byte(0xC7); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4495 emit_operand(rax, dst, 4); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4496 emit_data((int)imm32, rspec, narrow_oop_operand); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4497 } |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4498 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4499 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4500 InstructionMark im(this); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4501 int encode = prefix_and_encode(src1->encoding()); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4502 emit_byte(0x81); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4503 emit_byte(0xF8 | encode); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4504 emit_data((int)imm32, rspec, narrow_oop_operand); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4505 } |
|
660978a2a31a
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kvn
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624
diff
changeset
|
4506 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
4507 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
4508 InstructionMark im(this); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4509 prefix(src1); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4510 emit_byte(0x81); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
4511 emit_operand(rax, src1, 4); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
4512 emit_data((int)imm32, rspec, narrow_oop_operand); |
|
660978a2a31a
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kvn
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624
diff
changeset
|
4513 } |
|
660978a2a31a
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624
diff
changeset
|
4514 |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
4515 void Assembler::lzcntq(Register dst, Register src) { |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
4516 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
4517 emit_byte(0xF3); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
4518 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
4519 emit_byte(0x0F); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
4520 emit_byte(0xBD); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
4521 emit_byte(0xC0 | encode); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
4522 } |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
4523 |
| 304 | 4524 void Assembler::movdq(XMMRegister dst, Register src) { |
| 4525 // table D-1 says MMX/SSE2 | |
| 4759 | 4526 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
| 4527 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_66); | |
| 304 | 4528 emit_byte(0x6E); |
| 4529 emit_byte(0xC0 | encode); | |
| 4530 } | |
| 4531 | |
| 4532 void Assembler::movdq(Register dst, XMMRegister src) { | |
| 4533 // table D-1 says MMX/SSE2 | |
| 4759 | 4534 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
| 304 | 4535 // swap src/dst to get correct prefix |
| 4759 | 4536 int encode = simd_prefix_and_encode_q(src, dst, VEX_SIMD_66); |
| 0 | 4537 emit_byte(0x7E); |
| 304 | 4538 emit_byte(0xC0 | encode); |
| 4539 } | |
| 4540 | |
| 4541 void Assembler::movq(Register dst, Register src) { | |
| 4542 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4543 emit_byte(0x8B); | |
| 4544 emit_byte(0xC0 | encode); | |
| 4545 } | |
| 4546 | |
| 4547 void Assembler::movq(Register dst, Address src) { | |
| 4548 InstructionMark im(this); | |
| 4549 prefixq(src, dst); | |
| 4550 emit_byte(0x8B); | |
| 4551 emit_operand(dst, src); | |
| 4552 } | |
| 4553 | |
| 4554 void Assembler::movq(Address dst, Register src) { | |
| 4555 InstructionMark im(this); | |
| 4556 prefixq(dst, src); | |
| 4557 emit_byte(0x89); | |
| 4558 emit_operand(src, dst); | |
| 4559 } | |
| 4560 | |
| 624 | 4561 void Assembler::movsbq(Register dst, Address src) { |
| 4562 InstructionMark im(this); | |
| 4563 prefixq(src, dst); | |
| 4564 emit_byte(0x0F); | |
| 4565 emit_byte(0xBE); | |
| 4566 emit_operand(dst, src); | |
| 4567 } | |
| 4568 | |
| 4569 void Assembler::movsbq(Register dst, Register src) { | |
| 4570 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4571 emit_byte(0x0F); | |
| 4572 emit_byte(0xBE); | |
| 4573 emit_byte(0xC0 | encode); | |
| 4574 } | |
| 4575 | |
| 304 | 4576 void Assembler::movslq(Register dst, int32_t imm32) { |
| 4577 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx) | |
| 4578 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx) | |
| 4579 // as a result we shouldn't use until tested at runtime... | |
| 4580 ShouldNotReachHere(); | |
| 4581 InstructionMark im(this); | |
| 4582 int encode = prefixq_and_encode(dst->encoding()); | |
| 4583 emit_byte(0xC7 | encode); | |
| 4584 emit_long(imm32); | |
| 4585 } | |
| 4586 | |
| 4587 void Assembler::movslq(Address dst, int32_t imm32) { | |
| 4588 assert(is_simm32(imm32), "lost bits"); | |
| 4589 InstructionMark im(this); | |
| 4590 prefixq(dst); | |
| 4591 emit_byte(0xC7); | |
| 4592 emit_operand(rax, dst, 4); | |
| 4593 emit_long(imm32); | |
| 4594 } | |
| 4595 | |
| 4596 void Assembler::movslq(Register dst, Address src) { | |
| 4597 InstructionMark im(this); | |
| 4598 prefixq(src, dst); | |
| 4599 emit_byte(0x63); | |
| 4600 emit_operand(dst, src); | |
| 4601 } | |
| 4602 | |
| 4603 void Assembler::movslq(Register dst, Register src) { | |
| 4604 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4605 emit_byte(0x63); | |
| 4606 emit_byte(0xC0 | encode); | |
| 4607 } | |
| 4608 | |
| 624 | 4609 void Assembler::movswq(Register dst, Address src) { |
| 4610 InstructionMark im(this); | |
| 4611 prefixq(src, dst); | |
| 4612 emit_byte(0x0F); | |
| 4613 emit_byte(0xBF); | |
| 4614 emit_operand(dst, src); | |
| 4615 } | |
| 4616 | |
| 4617 void Assembler::movswq(Register dst, Register src) { | |
| 4618 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4619 emit_byte(0x0F); | |
| 4620 emit_byte(0xBF); | |
| 4621 emit_byte(0xC0 | encode); | |
| 4622 } | |
| 4623 | |
| 4624 void Assembler::movzbq(Register dst, Address src) { | |
| 4625 InstructionMark im(this); | |
| 4626 prefixq(src, dst); | |
| 4627 emit_byte(0x0F); | |
| 4628 emit_byte(0xB6); | |
| 4629 emit_operand(dst, src); | |
| 4630 } | |
| 4631 | |
| 4632 void Assembler::movzbq(Register dst, Register src) { | |
| 4633 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4634 emit_byte(0x0F); | |
| 4635 emit_byte(0xB6); | |
| 4636 emit_byte(0xC0 | encode); | |
| 4637 } | |
| 4638 | |
| 4639 void Assembler::movzwq(Register dst, Address src) { | |
| 4640 InstructionMark im(this); | |
| 4641 prefixq(src, dst); | |
| 4642 emit_byte(0x0F); | |
| 4643 emit_byte(0xB7); | |
| 4644 emit_operand(dst, src); | |
| 4645 } | |
| 4646 | |
| 4647 void Assembler::movzwq(Register dst, Register src) { | |
| 4648 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4649 emit_byte(0x0F); | |
| 4650 emit_byte(0xB7); | |
| 4651 emit_byte(0xC0 | encode); | |
| 4652 } | |
| 4653 | |
| 304 | 4654 void Assembler::negq(Register dst) { |
| 4655 int encode = prefixq_and_encode(dst->encoding()); | |
| 4656 emit_byte(0xF7); | |
| 4657 emit_byte(0xD8 | encode); | |
| 4658 } | |
| 4659 | |
| 4660 void Assembler::notq(Register dst) { | |
| 4661 int encode = prefixq_and_encode(dst->encoding()); | |
| 4662 emit_byte(0xF7); | |
| 4663 emit_byte(0xD0 | encode); | |
| 4664 } | |
| 4665 | |
| 4666 void Assembler::orq(Address dst, int32_t imm32) { | |
| 4667 InstructionMark im(this); | |
| 4668 prefixq(dst); | |
| 4669 emit_byte(0x81); | |
| 4670 emit_operand(rcx, dst, 4); | |
| 4671 emit_long(imm32); | |
| 4672 } | |
| 4673 | |
| 4674 void Assembler::orq(Register dst, int32_t imm32) { | |
| 4675 (void) prefixq_and_encode(dst->encoding()); | |
| 4676 emit_arith(0x81, 0xC8, dst, imm32); | |
| 4677 } | |
| 4678 | |
| 4679 void Assembler::orq(Register dst, Address src) { | |
| 4680 InstructionMark im(this); | |
| 4681 prefixq(src, dst); | |
| 4682 emit_byte(0x0B); | |
| 4683 emit_operand(dst, src); | |
| 4684 } | |
| 4685 | |
| 4686 void Assembler::orq(Register dst, Register src) { | |
| 4687 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4688 emit_arith(0x0B, 0xC0, dst, src); | |
| 4689 } | |
| 4690 | |
| 4691 void Assembler::popa() { // 64bit | |
| 4692 movq(r15, Address(rsp, 0)); | |
| 4693 movq(r14, Address(rsp, wordSize)); | |
| 4694 movq(r13, Address(rsp, 2 * wordSize)); | |
| 4695 movq(r12, Address(rsp, 3 * wordSize)); | |
| 4696 movq(r11, Address(rsp, 4 * wordSize)); | |
| 4697 movq(r10, Address(rsp, 5 * wordSize)); | |
| 4698 movq(r9, Address(rsp, 6 * wordSize)); | |
| 4699 movq(r8, Address(rsp, 7 * wordSize)); | |
| 4700 movq(rdi, Address(rsp, 8 * wordSize)); | |
| 4701 movq(rsi, Address(rsp, 9 * wordSize)); | |
| 4702 movq(rbp, Address(rsp, 10 * wordSize)); | |
| 4703 // skip rsp | |
| 4704 movq(rbx, Address(rsp, 12 * wordSize)); | |
| 4705 movq(rdx, Address(rsp, 13 * wordSize)); | |
| 4706 movq(rcx, Address(rsp, 14 * wordSize)); | |
| 4707 movq(rax, Address(rsp, 15 * wordSize)); | |
| 4708 | |
| 4709 addq(rsp, 16 * wordSize); | |
| 4710 } | |
| 4711 | |
|
643
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diff
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|
4712 void Assembler::popcntq(Register dst, Address src) { |
|
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|
4713 assert(VM_Version::supports_popcnt(), "must support"); |
|
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|
4714 InstructionMark im(this); |
|
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diff
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|
4715 emit_byte(0xF3); |
|
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|
4716 prefixq(src, dst); |
|
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|
4717 emit_byte(0x0F); |
|
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|
4718 emit_byte(0xB8); |
|
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|
4719 emit_operand(dst, src); |
|
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|
4720 } |
|
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|
4721 |
|
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diff
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|
4722 void Assembler::popcntq(Register dst, Register src) { |
|
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|
4723 assert(VM_Version::supports_popcnt(), "must support"); |
|
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|
4724 emit_byte(0xF3); |
|
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|
4725 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
|
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|
4726 emit_byte(0x0F); |
|
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diff
changeset
|
4727 emit_byte(0xB8); |
|
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diff
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|
4728 emit_byte(0xC0 | encode); |
|
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diff
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|
4729 } |
|
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|
4730 |
| 304 | 4731 void Assembler::popq(Address dst) { |
| 4732 InstructionMark im(this); | |
| 4733 prefixq(dst); | |
| 4734 emit_byte(0x8F); | |
| 4735 emit_operand(rax, dst); | |
| 4736 } | |
| 4737 | |
| 4738 void Assembler::pusha() { // 64bit | |
| 4739 // we have to store original rsp. ABI says that 128 bytes | |
| 4740 // below rsp are local scratch. | |
| 4741 movq(Address(rsp, -5 * wordSize), rsp); | |
| 4742 | |
| 4743 subq(rsp, 16 * wordSize); | |
| 4744 | |
| 4745 movq(Address(rsp, 15 * wordSize), rax); | |
| 4746 movq(Address(rsp, 14 * wordSize), rcx); | |
| 4747 movq(Address(rsp, 13 * wordSize), rdx); | |
| 4748 movq(Address(rsp, 12 * wordSize), rbx); | |
| 4749 // skip rsp | |
| 4750 movq(Address(rsp, 10 * wordSize), rbp); | |
| 4751 movq(Address(rsp, 9 * wordSize), rsi); | |
| 4752 movq(Address(rsp, 8 * wordSize), rdi); | |
| 4753 movq(Address(rsp, 7 * wordSize), r8); | |
| 4754 movq(Address(rsp, 6 * wordSize), r9); | |
| 4755 movq(Address(rsp, 5 * wordSize), r10); | |
| 4756 movq(Address(rsp, 4 * wordSize), r11); | |
| 4757 movq(Address(rsp, 3 * wordSize), r12); | |
| 4758 movq(Address(rsp, 2 * wordSize), r13); | |
| 4759 movq(Address(rsp, wordSize), r14); | |
| 4760 movq(Address(rsp, 0), r15); | |
| 4761 } | |
| 4762 | |
| 4763 void Assembler::pushq(Address src) { | |
| 4764 InstructionMark im(this); | |
| 4765 prefixq(src); | |
| 4766 emit_byte(0xFF); | |
| 4767 emit_operand(rsi, src); | |
| 4768 } | |
| 4769 | |
| 4770 void Assembler::rclq(Register dst, int imm8) { | |
| 4771 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
| 4772 int encode = prefixq_and_encode(dst->encoding()); | |
| 4773 if (imm8 == 1) { | |
| 4774 emit_byte(0xD1); | |
| 4775 emit_byte(0xD0 | encode); | |
| 4776 } else { | |
| 4777 emit_byte(0xC1); | |
| 4778 emit_byte(0xD0 | encode); | |
| 4779 emit_byte(imm8); | |
| 4780 } | |
| 4781 } | |
| 4782 void Assembler::sarq(Register dst, int imm8) { | |
| 4783 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
| 4784 int encode = prefixq_and_encode(dst->encoding()); | |
| 4785 if (imm8 == 1) { | |
| 4786 emit_byte(0xD1); | |
| 4787 emit_byte(0xF8 | encode); | |
| 4788 } else { | |
| 4789 emit_byte(0xC1); | |
| 4790 emit_byte(0xF8 | encode); | |
| 4791 emit_byte(imm8); | |
| 4792 } | |
| 4793 } | |
| 4794 | |
| 4795 void Assembler::sarq(Register dst) { | |
| 4796 int encode = prefixq_and_encode(dst->encoding()); | |
| 4797 emit_byte(0xD3); | |
| 4798 emit_byte(0xF8 | encode); | |
| 4799 } | |
|
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diff
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|
4800 |
| 304 | 4801 void Assembler::sbbq(Address dst, int32_t imm32) { |
| 4802 InstructionMark im(this); | |
| 4803 prefixq(dst); | |
| 4804 emit_arith_operand(0x81, rbx, dst, imm32); | |
| 4805 } | |
| 4806 | |
| 4807 void Assembler::sbbq(Register dst, int32_t imm32) { | |
| 4808 (void) prefixq_and_encode(dst->encoding()); | |
| 4809 emit_arith(0x81, 0xD8, dst, imm32); | |
| 4810 } | |
| 4811 | |
| 4812 void Assembler::sbbq(Register dst, Address src) { | |
| 4813 InstructionMark im(this); | |
| 4814 prefixq(src, dst); | |
| 4815 emit_byte(0x1B); | |
| 4816 emit_operand(dst, src); | |
| 4817 } | |
| 4818 | |
| 4819 void Assembler::sbbq(Register dst, Register src) { | |
| 4820 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4821 emit_arith(0x1B, 0xC0, dst, src); | |
| 4822 } | |
| 4823 | |
| 4824 void Assembler::shlq(Register dst, int imm8) { | |
| 4825 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
| 4826 int encode = prefixq_and_encode(dst->encoding()); | |
| 4827 if (imm8 == 1) { | |
| 4828 emit_byte(0xD1); | |
| 4829 emit_byte(0xE0 | encode); | |
| 4830 } else { | |
| 4831 emit_byte(0xC1); | |
| 4832 emit_byte(0xE0 | encode); | |
| 4833 emit_byte(imm8); | |
| 4834 } | |
| 4835 } | |
| 4836 | |
| 4837 void Assembler::shlq(Register dst) { | |
| 4838 int encode = prefixq_and_encode(dst->encoding()); | |
| 4839 emit_byte(0xD3); | |
| 4840 emit_byte(0xE0 | encode); | |
| 4841 } | |
| 4842 | |
| 4843 void Assembler::shrq(Register dst, int imm8) { | |
| 4844 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
| 4845 int encode = prefixq_and_encode(dst->encoding()); | |
| 4846 emit_byte(0xC1); | |
| 4847 emit_byte(0xE8 | encode); | |
| 4848 emit_byte(imm8); | |
| 4849 } | |
| 4850 | |
| 4851 void Assembler::shrq(Register dst) { | |
| 4852 int encode = prefixq_and_encode(dst->encoding()); | |
| 4853 emit_byte(0xD3); | |
| 4854 emit_byte(0xE8 | encode); | |
| 4855 } | |
| 4856 | |
| 4857 void Assembler::subq(Address dst, int32_t imm32) { | |
| 4858 InstructionMark im(this); | |
| 4859 prefixq(dst); | |
|
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diff
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|
4860 emit_arith_operand(0x81, rbp, dst, imm32); |
| 304 | 4861 } |
| 4862 | |
| 4863 void Assembler::subq(Address dst, Register src) { | |
| 4864 InstructionMark im(this); | |
| 4865 prefixq(dst, src); | |
| 4866 emit_byte(0x29); | |
| 4867 emit_operand(src, dst); | |
| 4868 } | |
| 4869 | |
|
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|
4870 void Assembler::subq(Register dst, int32_t imm32) { |
|
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diff
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|
4871 (void) prefixq_and_encode(dst->encoding()); |
|
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diff
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|
4872 emit_arith(0x81, 0xE8, dst, imm32); |
|
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|
4873 } |
|
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|
4874 |
|
4947
fd8114661503
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parents:
4770
diff
changeset
|
4875 // Force generation of a 4 byte immediate value even if it fits into 8bit |
|
fd8114661503
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4770
diff
changeset
|
4876 void Assembler::subq_imm32(Register dst, int32_t imm32) { |
|
fd8114661503
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4770
diff
changeset
|
4877 (void) prefixq_and_encode(dst->encoding()); |
|
fd8114661503
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4770
diff
changeset
|
4878 emit_arith_imm32(0x81, 0xE8, dst, imm32); |
|
fd8114661503
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4770
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|
4879 } |
|
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4770
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changeset
|
4880 |
| 304 | 4881 void Assembler::subq(Register dst, Address src) { |
| 4882 InstructionMark im(this); | |
| 4883 prefixq(src, dst); | |
| 4884 emit_byte(0x2B); | |
| 4885 emit_operand(dst, src); | |
| 4886 } | |
| 4887 | |
| 4888 void Assembler::subq(Register dst, Register src) { | |
| 4889 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4890 emit_arith(0x2B, 0xC0, dst, src); | |
| 4891 } | |
| 4892 | |
| 4893 void Assembler::testq(Register dst, int32_t imm32) { | |
| 4894 // not using emit_arith because test | |
| 4895 // doesn't support sign-extension of | |
| 4896 // 8bit operands | |
| 4897 int encode = dst->encoding(); | |
| 4898 if (encode == 0) { | |
| 4899 prefix(REX_W); | |
| 4900 emit_byte(0xA9); | |
| 4901 } else { | |
| 4902 encode = prefixq_and_encode(encode); | |
| 4903 emit_byte(0xF7); | |
| 4904 emit_byte(0xC0 | encode); | |
| 4905 } | |
| 4906 emit_long(imm32); | |
| 4907 } | |
| 4908 | |
| 4909 void Assembler::testq(Register dst, Register src) { | |
| 4910 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4911 emit_arith(0x85, 0xC0, dst, src); | |
| 4912 } | |
| 4913 | |
| 4914 void Assembler::xaddq(Address dst, Register src) { | |
| 4915 InstructionMark im(this); | |
| 4916 prefixq(dst, src); | |
| 71 | 4917 emit_byte(0x0F); |
| 304 | 4918 emit_byte(0xC1); |
| 4919 emit_operand(src, dst); | |
| 4920 } | |
| 4921 | |
| 4922 void Assembler::xchgq(Register dst, Address src) { | |
| 4923 InstructionMark im(this); | |
| 4924 prefixq(src, dst); | |
| 4925 emit_byte(0x87); | |
| 4926 emit_operand(dst, src); | |
| 4927 } | |
| 4928 | |
| 4929 void Assembler::xchgq(Register dst, Register src) { | |
| 4930 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4931 emit_byte(0x87); | |
| 4932 emit_byte(0xc0 | encode); | |
| 4933 } | |
| 4934 | |
| 4935 void Assembler::xorq(Register dst, Register src) { | |
| 4936 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4937 emit_arith(0x33, 0xC0, dst, src); | |
| 4938 } | |
| 4939 | |
| 4940 void Assembler::xorq(Register dst, Address src) { | |
| 4941 InstructionMark im(this); | |
| 4942 prefixq(src, dst); | |
| 4943 emit_byte(0x33); | |
| 4944 emit_operand(dst, src); | |
| 4945 } | |
| 4946 | |
| 4947 #endif // !LP64 | |
| 4948 | |
| 4949 static Assembler::Condition reverse[] = { | |
| 4950 Assembler::noOverflow /* overflow = 0x0 */ , | |
| 4951 Assembler::overflow /* noOverflow = 0x1 */ , | |
| 4952 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ , | |
| 4953 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ , | |
| 4954 Assembler::notZero /* zero = 0x4, equal = 0x4 */ , | |
| 4955 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ , | |
| 4956 Assembler::above /* belowEqual = 0x6 */ , | |
| 4957 Assembler::belowEqual /* above = 0x7 */ , | |
| 4958 Assembler::positive /* negative = 0x8 */ , | |
| 4959 Assembler::negative /* positive = 0x9 */ , | |
| 4960 Assembler::noParity /* parity = 0xa */ , | |
| 4961 Assembler::parity /* noParity = 0xb */ , | |
| 4962 Assembler::greaterEqual /* less = 0xc */ , | |
| 4963 Assembler::less /* greaterEqual = 0xd */ , | |
| 4964 Assembler::greater /* lessEqual = 0xe */ , | |
| 4965 Assembler::lessEqual /* greater = 0xf, */ | |
| 4966 | |
| 4967 }; | |
| 4968 | |
| 0 | 4969 |
| 4970 // Implementation of MacroAssembler | |
| 4971 | |
| 304 | 4972 // First all the versions that have distinct versions depending on 32/64 bit |
| 4973 // Unless the difference is trivial (1 line or so). | |
| 4974 | |
| 4975 #ifndef _LP64 | |
| 4976 | |
| 4977 // 32bit versions | |
| 4978 | |
| 0 | 4979 Address MacroAssembler::as_Address(AddressLiteral adr) { |
| 4980 return Address(adr.target(), adr.rspec()); | |
| 4981 } | |
| 4982 | |
| 4983 Address MacroAssembler::as_Address(ArrayAddress adr) { | |
| 4984 return Address::make_array(adr); | |
| 4985 } | |
| 4986 | |
| 304 | 4987 int MacroAssembler::biased_locking_enter(Register lock_reg, |
| 4988 Register obj_reg, | |
| 4989 Register swap_reg, | |
| 4990 Register tmp_reg, | |
| 4991 bool swap_reg_contains_mark, | |
| 4992 Label& done, | |
| 4993 Label* slow_case, | |
| 4994 BiasedLockingCounters* counters) { | |
| 4995 assert(UseBiasedLocking, "why call this otherwise?"); | |
| 4996 assert(swap_reg == rax, "swap_reg must be rax, for cmpxchg"); | |
| 4997 assert_different_registers(lock_reg, obj_reg, swap_reg); | |
| 4998 | |
| 4999 if (PrintBiasedLockingStatistics && counters == NULL) | |
| 5000 counters = BiasedLocking::counters(); | |
| 5001 | |
| 5002 bool need_tmp_reg = false; | |
| 5003 if (tmp_reg == noreg) { | |
| 5004 need_tmp_reg = true; | |
| 5005 tmp_reg = lock_reg; | |
| 5006 } else { | |
| 5007 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg); | |
| 5008 } | |
| 5009 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); | |
| 5010 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes()); | |
| 5011 Address klass_addr (obj_reg, oopDesc::klass_offset_in_bytes()); | |
| 5012 Address saved_mark_addr(lock_reg, 0); | |
| 5013 | |
| 5014 // Biased locking | |
| 5015 // See whether the lock is currently biased toward our thread and | |
| 5016 // whether the epoch is still valid | |
| 5017 // Note that the runtime guarantees sufficient alignment of JavaThread | |
| 5018 // pointers to allow age to be placed into low bits | |
| 5019 // First check to see whether biasing is even enabled for this object | |
| 5020 Label cas_label; | |
| 5021 int null_check_offset = -1; | |
| 5022 if (!swap_reg_contains_mark) { | |
| 5023 null_check_offset = offset(); | |
| 5024 movl(swap_reg, mark_addr); | |
| 5025 } | |
| 5026 if (need_tmp_reg) { | |
| 5027 push(tmp_reg); | |
| 5028 } | |
| 5029 movl(tmp_reg, swap_reg); | |
| 5030 andl(tmp_reg, markOopDesc::biased_lock_mask_in_place); | |
| 5031 cmpl(tmp_reg, markOopDesc::biased_lock_pattern); | |
| 5032 if (need_tmp_reg) { | |
| 5033 pop(tmp_reg); | |
| 5034 } | |
| 5035 jcc(Assembler::notEqual, cas_label); | |
| 5036 // The bias pattern is present in the object's header. Need to check | |
| 5037 // whether the bias owner and the epoch are both still current. | |
| 5038 // Note that because there is no current thread register on x86 we | |
| 5039 // need to store off the mark word we read out of the object to | |
| 5040 // avoid reloading it and needing to recheck invariants below. This | |
| 5041 // store is unfortunate but it makes the overall code shorter and | |
| 5042 // simpler. | |
| 5043 movl(saved_mark_addr, swap_reg); | |
| 5044 if (need_tmp_reg) { | |
| 5045 push(tmp_reg); | |
| 5046 } | |
| 5047 get_thread(tmp_reg); | |
| 5048 xorl(swap_reg, tmp_reg); | |
| 5049 if (swap_reg_contains_mark) { | |
| 5050 null_check_offset = offset(); | |
| 5051 } | |
| 5052 movl(tmp_reg, klass_addr); | |
|
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|
5053 xorl(swap_reg, Address(tmp_reg, Klass::prototype_header_offset())); |
| 304 | 5054 andl(swap_reg, ~((int) markOopDesc::age_mask_in_place)); |
| 5055 if (need_tmp_reg) { | |
| 5056 pop(tmp_reg); | |
| 5057 } | |
| 5058 if (counters != NULL) { | |
| 5059 cond_inc32(Assembler::zero, | |
| 5060 ExternalAddress((address)counters->biased_lock_entry_count_addr())); | |
| 5061 } | |
| 5062 jcc(Assembler::equal, done); | |
| 5063 | |
| 5064 Label try_revoke_bias; | |
| 5065 Label try_rebias; | |
| 5066 | |
| 5067 // At this point we know that the header has the bias pattern and | |
| 5068 // that we are not the bias owner in the current epoch. We need to | |
| 5069 // figure out more details about the state of the header in order to | |
| 5070 // know what operations can be legally performed on the object's | |
| 5071 // header. | |
| 5072 | |
| 5073 // If the low three bits in the xor result aren't clear, that means | |
| 5074 // the prototype header is no longer biased and we have to revoke | |
| 5075 // the bias on this object. | |
| 5076 testl(swap_reg, markOopDesc::biased_lock_mask_in_place); | |
| 5077 jcc(Assembler::notZero, try_revoke_bias); | |
| 5078 | |
| 5079 // Biasing is still enabled for this data type. See whether the | |
| 5080 // epoch of the current bias is still valid, meaning that the epoch | |
| 5081 // bits of the mark word are equal to the epoch bits of the | |
| 5082 // prototype header. (Note that the prototype header's epoch bits | |
| 5083 // only change at a safepoint.) If not, attempt to rebias the object | |
| 5084 // toward the current thread. Note that we must be absolutely sure | |
| 5085 // that the current epoch is invalid in order to do this because | |
| 5086 // otherwise the manipulations it performs on the mark word are | |
| 5087 // illegal. | |
| 5088 testl(swap_reg, markOopDesc::epoch_mask_in_place); | |
| 5089 jcc(Assembler::notZero, try_rebias); | |
| 5090 | |
| 5091 // The epoch of the current bias is still valid but we know nothing | |
| 5092 // about the owner; it might be set or it might be clear. Try to | |
| 5093 // acquire the bias of the object using an atomic operation. If this | |
| 5094 // fails we will go in to the runtime to revoke the object's bias. | |
| 5095 // Note that we first construct the presumed unbiased header so we | |
| 5096 // don't accidentally blow away another thread's valid bias. | |
| 5097 movl(swap_reg, saved_mark_addr); | |
| 5098 andl(swap_reg, | |
| 5099 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place); | |
| 5100 if (need_tmp_reg) { | |
| 5101 push(tmp_reg); | |
| 5102 } | |
| 5103 get_thread(tmp_reg); | |
| 5104 orl(tmp_reg, swap_reg); | |
| 5105 if (os::is_MP()) { | |
| 5106 lock(); | |
| 5107 } | |
| 5108 cmpxchgptr(tmp_reg, Address(obj_reg, 0)); | |
| 5109 if (need_tmp_reg) { | |
| 5110 pop(tmp_reg); | |
| 5111 } | |
| 5112 // If the biasing toward our thread failed, this means that | |
| 5113 // another thread succeeded in biasing it toward itself and we | |
| 5114 // need to revoke that bias. The revocation will occur in the | |
| 5115 // interpreter runtime in the slow case. | |
| 5116 if (counters != NULL) { | |
| 5117 cond_inc32(Assembler::zero, | |
| 5118 ExternalAddress((address)counters->anonymously_biased_lock_entry_count_addr())); | |
| 5119 } | |
| 5120 if (slow_case != NULL) { | |
| 5121 jcc(Assembler::notZero, *slow_case); | |
| 5122 } | |
| 5123 jmp(done); | |
| 5124 | |
| 5125 bind(try_rebias); | |
| 5126 // At this point we know the epoch has expired, meaning that the | |
| 5127 // current "bias owner", if any, is actually invalid. Under these | |
| 5128 // circumstances _only_, we are allowed to use the current header's | |
| 5129 // value as the comparison value when doing the cas to acquire the | |
| 5130 // bias in the current epoch. In other words, we allow transfer of | |
| 5131 // the bias from one thread to another directly in this situation. | |
| 5132 // | |
| 5133 // FIXME: due to a lack of registers we currently blow away the age | |
| 5134 // bits in this situation. Should attempt to preserve them. | |
| 5135 if (need_tmp_reg) { | |
| 5136 push(tmp_reg); | |
| 5137 } | |
| 5138 get_thread(tmp_reg); | |
| 5139 movl(swap_reg, klass_addr); | |
|
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|
5140 orl(tmp_reg, Address(swap_reg, Klass::prototype_header_offset())); |
| 304 | 5141 movl(swap_reg, saved_mark_addr); |
| 5142 if (os::is_MP()) { | |
| 5143 lock(); | |
| 5144 } | |
| 5145 cmpxchgptr(tmp_reg, Address(obj_reg, 0)); | |
| 5146 if (need_tmp_reg) { | |
| 5147 pop(tmp_reg); | |
| 5148 } | |
| 5149 // If the biasing toward our thread failed, then another thread | |
| 5150 // succeeded in biasing it toward itself and we need to revoke that | |
| 5151 // bias. The revocation will occur in the runtime in the slow case. | |
| 5152 if (counters != NULL) { | |
| 5153 cond_inc32(Assembler::zero, | |
| 5154 ExternalAddress((address)counters->rebiased_lock_entry_count_addr())); | |
| 5155 } | |
| 5156 if (slow_case != NULL) { | |
| 5157 jcc(Assembler::notZero, *slow_case); | |
| 5158 } | |
| 5159 jmp(done); | |
| 5160 | |
| 5161 bind(try_revoke_bias); | |
| 5162 // The prototype mark in the klass doesn't have the bias bit set any | |
| 5163 // more, indicating that objects of this data type are not supposed | |
| 5164 // to be biased any more. We are going to try to reset the mark of | |
| 5165 // this object to the prototype value and fall through to the | |
| 5166 // CAS-based locking scheme. Note that if our CAS fails, it means | |
| 5167 // that another thread raced us for the privilege of revoking the | |
| 5168 // bias of this particular object, so it's okay to continue in the | |
| 5169 // normal locking code. | |
| 5170 // | |
| 5171 // FIXME: due to a lack of registers we currently blow away the age | |
| 5172 // bits in this situation. Should attempt to preserve them. | |
| 5173 movl(swap_reg, saved_mark_addr); | |
| 5174 if (need_tmp_reg) { | |
| 5175 push(tmp_reg); | |
| 5176 } | |
| 5177 movl(tmp_reg, klass_addr); | |
|
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|
5178 movl(tmp_reg, Address(tmp_reg, Klass::prototype_header_offset())); |
| 304 | 5179 if (os::is_MP()) { |
| 5180 lock(); | |
| 5181 } | |
| 5182 cmpxchgptr(tmp_reg, Address(obj_reg, 0)); | |
| 5183 if (need_tmp_reg) { | |
| 5184 pop(tmp_reg); | |
| 5185 } | |
| 5186 // Fall through to the normal CAS-based lock, because no matter what | |
| 5187 // the result of the above CAS, some thread must have succeeded in | |
| 5188 // removing the bias bit from the object's header. | |
| 5189 if (counters != NULL) { | |
| 5190 cond_inc32(Assembler::zero, | |
| 5191 ExternalAddress((address)counters->revoked_lock_entry_count_addr())); | |
| 5192 } | |
| 5193 | |
| 5194 bind(cas_label); | |
| 5195 | |
| 5196 return null_check_offset; | |
| 5197 } | |
| 5198 void MacroAssembler::call_VM_leaf_base(address entry_point, | |
| 5199 int number_of_arguments) { | |
| 5200 call(RuntimeAddress(entry_point)); | |
| 5201 increment(rsp, number_of_arguments * wordSize); | |
| 5202 } | |
| 5203 | |
| 5204 void MacroAssembler::cmpoop(Address src1, jobject obj) { | |
| 5205 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); | |
| 5206 } | |
| 5207 | |
| 5208 void MacroAssembler::cmpoop(Register src1, jobject obj) { | |
| 5209 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); | |
| 5210 } | |
| 5211 | |
| 5212 void MacroAssembler::extend_sign(Register hi, Register lo) { | |
| 5213 // According to Intel Doc. AP-526, "Integer Divide", p.18. | |
| 5214 if (VM_Version::is_P6() && hi == rdx && lo == rax) { | |
| 5215 cdql(); | |
| 5216 } else { | |
| 5217 movl(hi, lo); | |
| 5218 sarl(hi, 31); | |
| 5219 } | |
| 5220 } | |
| 5221 | |
| 5222 void MacroAssembler::jC2(Register tmp, Label& L) { | |
| 5223 // set parity bit if FPU flag C2 is set (via rax) | |
| 5224 save_rax(tmp); | |
| 5225 fwait(); fnstsw_ax(); | |
| 5226 sahf(); | |
| 5227 restore_rax(tmp); | |
| 5228 // branch | |
| 5229 jcc(Assembler::parity, L); | |
| 5230 } | |
| 5231 | |
| 5232 void MacroAssembler::jnC2(Register tmp, Label& L) { | |
| 5233 // set parity bit if FPU flag C2 is set (via rax) | |
| 5234 save_rax(tmp); | |
| 5235 fwait(); fnstsw_ax(); | |
| 5236 sahf(); | |
| 5237 restore_rax(tmp); | |
| 5238 // branch | |
| 5239 jcc(Assembler::noParity, L); | |
| 5240 } | |
| 5241 | |
| 0 | 5242 // 32bit can do a case table jump in one instruction but we no longer allow the base |
| 5243 // to be installed in the Address class | |
| 5244 void MacroAssembler::jump(ArrayAddress entry) { | |
| 5245 jmp(as_Address(entry)); | |
| 5246 } | |
| 5247 | |
| 304 | 5248 // Note: y_lo will be destroyed |
| 5249 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { | |
| 5250 // Long compare for Java (semantics as described in JVM spec.) | |
| 5251 Label high, low, done; | |
| 5252 | |
| 5253 cmpl(x_hi, y_hi); | |
| 5254 jcc(Assembler::less, low); | |
| 5255 jcc(Assembler::greater, high); | |
| 5256 // x_hi is the return register | |
| 5257 xorl(x_hi, x_hi); | |
| 5258 cmpl(x_lo, y_lo); | |
| 5259 jcc(Assembler::below, low); | |
| 5260 jcc(Assembler::equal, done); | |
| 5261 | |
| 5262 bind(high); | |
| 5263 xorl(x_hi, x_hi); | |
| 5264 increment(x_hi); | |
| 5265 jmp(done); | |
| 5266 | |
| 5267 bind(low); | |
| 5268 xorl(x_hi, x_hi); | |
| 5269 decrementl(x_hi); | |
| 5270 | |
| 5271 bind(done); | |
| 5272 } | |
| 5273 | |
| 5274 void MacroAssembler::lea(Register dst, AddressLiteral src) { | |
| 5275 mov_literal32(dst, (int32_t)src.target(), src.rspec()); | |
| 0 | 5276 } |
| 5277 | |
| 5278 void MacroAssembler::lea(Address dst, AddressLiteral adr) { | |
| 5279 // leal(dst, as_Address(adr)); | |
| 304 | 5280 // see note in movl as to why we must use a move |
| 0 | 5281 mov_literal32(dst, (int32_t) adr.target(), adr.rspec()); |
| 5282 } | |
| 5283 | |
| 5284 void MacroAssembler::leave() { | |
| 304 | 5285 mov(rsp, rbp); |
| 5286 pop(rbp); | |
| 5287 } | |
| 0 | 5288 |
| 5289 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) { | |
| 5290 // Multiplication of two Java long values stored on the stack | |
| 5291 // as illustrated below. Result is in rdx:rax. | |
| 5292 // | |
| 5293 // rsp ---> [ ?? ] \ \ | |
| 5294 // .... | y_rsp_offset | | |
| 5295 // [ y_lo ] / (in bytes) | x_rsp_offset | |
| 5296 // [ y_hi ] | (in bytes) | |
| 5297 // .... | | |
| 5298 // [ x_lo ] / | |
| 5299 // [ x_hi ] | |
| 5300 // .... | |
| 5301 // | |
| 5302 // Basic idea: lo(result) = lo(x_lo * y_lo) | |
| 5303 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) | |
| 5304 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset); | |
| 5305 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset); | |
| 5306 Label quick; | |
| 5307 // load x_hi, y_hi and check if quick | |
| 5308 // multiplication is possible | |
| 5309 movl(rbx, x_hi); | |
| 5310 movl(rcx, y_hi); | |
| 5311 movl(rax, rbx); | |
| 5312 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0 | |
| 5313 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply | |
| 5314 // do full multiplication | |
| 5315 // 1st step | |
| 5316 mull(y_lo); // x_hi * y_lo | |
| 5317 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx, | |
| 5318 // 2nd step | |
| 5319 movl(rax, x_lo); | |
| 5320 mull(rcx); // x_lo * y_hi | |
| 5321 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx, | |
| 5322 // 3rd step | |
| 5323 bind(quick); // note: rbx, = 0 if quick multiply! | |
| 5324 movl(rax, x_lo); | |
| 5325 mull(y_lo); // x_lo * y_lo | |
| 5326 addl(rdx, rbx); // correct hi(x_lo * y_lo) | |
| 5327 } | |
| 5328 | |
| 304 | 5329 void MacroAssembler::lneg(Register hi, Register lo) { |
| 5330 negl(lo); | |
| 5331 adcl(hi, 0); | |
| 5332 negl(hi); | |
| 5333 } | |
| 0 | 5334 |
| 5335 void MacroAssembler::lshl(Register hi, Register lo) { | |
| 5336 // Java shift left long support (semantics as described in JVM spec., p.305) | |
| 5337 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n)) | |
| 5338 // shift value is in rcx ! | |
| 5339 assert(hi != rcx, "must not use rcx"); | |
| 5340 assert(lo != rcx, "must not use rcx"); | |
| 5341 const Register s = rcx; // shift count | |
| 5342 const int n = BitsPerWord; | |
| 5343 Label L; | |
| 5344 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) | |
| 5345 cmpl(s, n); // if (s < n) | |
| 5346 jcc(Assembler::less, L); // else (s >= n) | |
| 5347 movl(hi, lo); // x := x << n | |
| 5348 xorl(lo, lo); | |
| 5349 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! | |
| 5350 bind(L); // s (mod n) < n | |
| 5351 shldl(hi, lo); // x := x << s | |
| 5352 shll(lo); | |
| 5353 } | |
| 5354 | |
| 5355 | |
| 5356 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) { | |
| 5357 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310) | |
| 5358 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n)) | |
| 5359 assert(hi != rcx, "must not use rcx"); | |
| 5360 assert(lo != rcx, "must not use rcx"); | |
| 5361 const Register s = rcx; // shift count | |
| 5362 const int n = BitsPerWord; | |
| 5363 Label L; | |
| 5364 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) | |
| 5365 cmpl(s, n); // if (s < n) | |
| 5366 jcc(Assembler::less, L); // else (s >= n) | |
| 5367 movl(lo, hi); // x := x >> n | |
| 5368 if (sign_extension) sarl(hi, 31); | |
| 5369 else xorl(hi, hi); | |
| 5370 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! | |
| 5371 bind(L); // s (mod n) < n | |
| 5372 shrdl(lo, hi); // x := x >> s | |
| 5373 if (sign_extension) sarl(hi); | |
| 5374 else shrl(hi); | |
| 5375 } | |
| 5376 | |
| 304 | 5377 void MacroAssembler::movoop(Register dst, jobject obj) { |
| 5378 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); | |
| 5379 } | |
| 5380 | |
| 5381 void MacroAssembler::movoop(Address dst, jobject obj) { | |
| 5382 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); | |
| 5383 } | |
| 5384 | |
| 5385 void MacroAssembler::movptr(Register dst, AddressLiteral src) { | |
| 5386 if (src.is_lval()) { | |
| 5387 mov_literal32(dst, (intptr_t)src.target(), src.rspec()); | |
| 5388 } else { | |
| 5389 movl(dst, as_Address(src)); | |
| 5390 } | |
| 5391 } | |
| 5392 | |
| 5393 void MacroAssembler::movptr(ArrayAddress dst, Register src) { | |
| 5394 movl(as_Address(dst), src); | |
| 5395 } | |
| 5396 | |
| 5397 void MacroAssembler::movptr(Register dst, ArrayAddress src) { | |
| 5398 movl(dst, as_Address(src)); | |
| 5399 } | |
| 5400 | |
| 5401 // src should NEVER be a real pointer. Use AddressLiteral for true pointers | |
| 5402 void MacroAssembler::movptr(Address dst, intptr_t src) { | |
| 5403 movl(dst, src); | |
| 5404 } | |
| 5405 | |
| 5406 | |
| 5407 void MacroAssembler::pop_callee_saved_registers() { | |
| 5408 pop(rcx); | |
| 5409 pop(rdx); | |
| 5410 pop(rdi); | |
| 5411 pop(rsi); | |
| 5412 } | |
| 5413 | |
| 5414 void MacroAssembler::pop_fTOS() { | |
| 5415 fld_d(Address(rsp, 0)); | |
| 5416 addl(rsp, 2 * wordSize); | |
| 5417 } | |
| 5418 | |
| 5419 void MacroAssembler::push_callee_saved_registers() { | |
| 5420 push(rsi); | |
| 5421 push(rdi); | |
| 5422 push(rdx); | |
| 5423 push(rcx); | |
| 5424 } | |
| 5425 | |
| 5426 void MacroAssembler::push_fTOS() { | |
| 5427 subl(rsp, 2 * wordSize); | |
| 5428 fstp_d(Address(rsp, 0)); | |
| 5429 } | |
| 5430 | |
| 5431 | |
| 5432 void MacroAssembler::pushoop(jobject obj) { | |
| 5433 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate()); | |
| 5434 } | |
| 5435 | |
| 5436 | |
| 5437 void MacroAssembler::pushptr(AddressLiteral src) { | |
| 5438 if (src.is_lval()) { | |
| 5439 push_literal32((int32_t)src.target(), src.rspec()); | |
| 5440 } else { | |
| 5441 pushl(as_Address(src)); | |
| 5442 } | |
| 5443 } | |
| 5444 | |
| 5445 void MacroAssembler::set_word_if_not_zero(Register dst) { | |
| 5446 xorl(dst, dst); | |
| 5447 set_byte_if_not_zero(dst); | |
| 5448 } | |
| 5449 | |
| 5450 static void pass_arg0(MacroAssembler* masm, Register arg) { | |
| 5451 masm->push(arg); | |
| 5452 } | |
| 5453 | |
| 5454 static void pass_arg1(MacroAssembler* masm, Register arg) { | |
| 5455 masm->push(arg); | |
| 5456 } | |
| 5457 | |
| 5458 static void pass_arg2(MacroAssembler* masm, Register arg) { | |
| 5459 masm->push(arg); | |
| 5460 } | |
| 5461 | |
| 5462 static void pass_arg3(MacroAssembler* masm, Register arg) { | |
| 5463 masm->push(arg); | |
| 5464 } | |
| 5465 | |
| 5466 #ifndef PRODUCT | |
| 5467 extern "C" void findpc(intptr_t x); | |
| 5468 #endif | |
| 5469 | |
| 5470 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) { | |
| 5471 // In order to get locks to work, we need to fake a in_VM state | |
| 5472 JavaThread* thread = JavaThread::current(); | |
| 5473 JavaThreadState saved_state = thread->thread_state(); | |
| 5474 thread->set_thread_state(_thread_in_vm); | |
| 5475 if (ShowMessageBoxOnError) { | |
| 5476 JavaThread* thread = JavaThread::current(); | |
| 5477 JavaThreadState saved_state = thread->thread_state(); | |
| 5478 thread->set_thread_state(_thread_in_vm); | |
| 5479 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { | |
| 5480 ttyLocker ttyl; | |
| 5481 BytecodeCounter::print(); | |
| 5482 } | |
| 5483 // To see where a verify_oop failed, get $ebx+40/X for this frame. | |
| 5484 // This is the value of eip which points to where verify_oop will return. | |
| 5485 if (os::message_box(msg, "Execution stopped, print registers?")) { | |
| 5486 ttyLocker ttyl; | |
| 5487 tty->print_cr("eip = 0x%08x", eip); | |
| 5488 #ifndef PRODUCT | |
|
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|
5489 if ((WizardMode || Verbose) && PrintMiscellaneous) { |
|
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|
5490 tty->cr(); |
|
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|
5491 findpc(eip); |
|
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|
5492 tty->cr(); |
|
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|
5493 } |
| 304 | 5494 #endif |
|
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|
5495 tty->print_cr("rax = 0x%08x", rax); |
|
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|
5496 tty->print_cr("rbx = 0x%08x", rbx); |
| 304 | 5497 tty->print_cr("rcx = 0x%08x", rcx); |
| 5498 tty->print_cr("rdx = 0x%08x", rdx); | |
| 5499 tty->print_cr("rdi = 0x%08x", rdi); | |
| 5500 tty->print_cr("rsi = 0x%08x", rsi); | |
|
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|
5501 tty->print_cr("rbp = 0x%08x", rbp); |
| 304 | 5502 tty->print_cr("rsp = 0x%08x", rsp); |
| 5503 BREAKPOINT; | |
|
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|
5504 assert(false, "start up GDB"); |
| 304 | 5505 } |
| 5506 } else { | |
| 5507 ttyLocker ttyl; | |
| 5508 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg); | |
|
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|
5509 assert(false, err_msg("DEBUG MESSAGE: %s", msg)); |
| 304 | 5510 } |
| 5511 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); | |
| 5512 } | |
| 5513 | |
| 5514 void MacroAssembler::stop(const char* msg) { | |
| 5515 ExternalAddress message((address)msg); | |
| 5516 // push address of message | |
| 5517 pushptr(message.addr()); | |
| 5518 { Label L; call(L, relocInfo::none); bind(L); } // push eip | |
| 5519 pusha(); // push registers | |
| 5520 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32))); | |
| 5521 hlt(); | |
| 5522 } | |
| 5523 | |
| 5524 void MacroAssembler::warn(const char* msg) { | |
| 5525 push_CPU_state(); | |
| 5526 | |
| 5527 ExternalAddress message((address) msg); | |
| 5528 // push address of message | |
| 5529 pushptr(message.addr()); | |
| 5530 | |
| 5531 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning))); | |
| 5532 addl(rsp, wordSize); // discard argument | |
| 5533 pop_CPU_state(); | |
| 5534 } | |
| 5535 | |
| 5536 #else // _LP64 | |
| 5537 | |
| 5538 // 64 bit versions | |
| 5539 | |
| 5540 Address MacroAssembler::as_Address(AddressLiteral adr) { | |
| 5541 // amd64 always does this as a pc-rel | |
| 5542 // we can be absolute or disp based on the instruction type | |
| 5543 // jmp/call are displacements others are absolute | |
| 5544 assert(!adr.is_lval(), "must be rval"); | |
| 5545 assert(reachable(adr), "must be"); | |
| 5546 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc()); | |
| 5547 | |
| 5548 } | |
| 5549 | |
| 5550 Address MacroAssembler::as_Address(ArrayAddress adr) { | |
| 5551 AddressLiteral base = adr.base(); | |
| 5552 lea(rscratch1, base); | |
| 5553 Address index = adr.index(); | |
| 5554 assert(index._disp == 0, "must not have disp"); // maybe it can? | |
| 5555 Address array(rscratch1, index._index, index._scale, index._disp); | |
| 5556 return array; | |
| 5557 } | |
| 5558 | |
| 5559 int MacroAssembler::biased_locking_enter(Register lock_reg, | |
| 5560 Register obj_reg, | |
| 5561 Register swap_reg, | |
| 5562 Register tmp_reg, | |
| 5563 bool swap_reg_contains_mark, | |
| 5564 Label& done, | |
| 5565 Label* slow_case, | |
| 5566 BiasedLockingCounters* counters) { | |
| 5567 assert(UseBiasedLocking, "why call this otherwise?"); | |
| 5568 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq"); | |
| 5569 assert(tmp_reg != noreg, "tmp_reg must be supplied"); | |
| 5570 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg); | |
| 5571 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); | |
| 5572 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes()); | |
| 5573 Address saved_mark_addr(lock_reg, 0); | |
| 5574 | |
| 5575 if (PrintBiasedLockingStatistics && counters == NULL) | |
| 5576 counters = BiasedLocking::counters(); | |
| 5577 | |
| 5578 // Biased locking | |
| 5579 // See whether the lock is currently biased toward our thread and | |
| 5580 // whether the epoch is still valid | |
| 5581 // Note that the runtime guarantees sufficient alignment of JavaThread | |
| 5582 // pointers to allow age to be placed into low bits | |
| 5583 // First check to see whether biasing is even enabled for this object | |
| 5584 Label cas_label; | |
| 5585 int null_check_offset = -1; | |
| 5586 if (!swap_reg_contains_mark) { | |
| 5587 null_check_offset = offset(); | |
| 5588 movq(swap_reg, mark_addr); | |
| 5589 } | |
| 5590 movq(tmp_reg, swap_reg); | |
| 5591 andq(tmp_reg, markOopDesc::biased_lock_mask_in_place); | |
| 5592 cmpq(tmp_reg, markOopDesc::biased_lock_pattern); | |
| 5593 jcc(Assembler::notEqual, cas_label); | |
| 5594 // The bias pattern is present in the object's header. Need to check | |
| 5595 // whether the bias owner and the epoch are both still current. | |
| 5596 load_prototype_header(tmp_reg, obj_reg); | |
| 5597 orq(tmp_reg, r15_thread); | |
| 5598 xorq(tmp_reg, swap_reg); | |
| 5599 andq(tmp_reg, ~((int) markOopDesc::age_mask_in_place)); | |
| 5600 if (counters != NULL) { | |
| 5601 cond_inc32(Assembler::zero, | |
| 5602 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr())); | |
| 5603 } | |
| 0 | 5604 jcc(Assembler::equal, done); |
| 5605 | |
| 304 | 5606 Label try_revoke_bias; |
| 5607 Label try_rebias; | |
| 5608 | |
| 5609 // At this point we know that the header has the bias pattern and | |
| 5610 // that we are not the bias owner in the current epoch. We need to | |
| 5611 // figure out more details about the state of the header in order to | |
| 5612 // know what operations can be legally performed on the object's | |
| 5613 // header. | |
| 5614 | |
| 5615 // If the low three bits in the xor result aren't clear, that means | |
| 5616 // the prototype header is no longer biased and we have to revoke | |
| 5617 // the bias on this object. | |
| 5618 testq(tmp_reg, markOopDesc::biased_lock_mask_in_place); | |
| 5619 jcc(Assembler::notZero, try_revoke_bias); | |
| 5620 | |
| 5621 // Biasing is still enabled for this data type. See whether the | |
| 5622 // epoch of the current bias is still valid, meaning that the epoch | |
| 5623 // bits of the mark word are equal to the epoch bits of the | |
| 5624 // prototype header. (Note that the prototype header's epoch bits | |
| 5625 // only change at a safepoint.) If not, attempt to rebias the object | |
| 5626 // toward the current thread. Note that we must be absolutely sure | |
| 5627 // that the current epoch is invalid in order to do this because | |
| 5628 // otherwise the manipulations it performs on the mark word are | |
| 5629 // illegal. | |
| 5630 testq(tmp_reg, markOopDesc::epoch_mask_in_place); | |
| 5631 jcc(Assembler::notZero, try_rebias); | |
| 5632 | |
| 5633 // The epoch of the current bias is still valid but we know nothing | |
| 5634 // about the owner; it might be set or it might be clear. Try to | |
| 5635 // acquire the bias of the object using an atomic operation. If this | |
| 5636 // fails we will go in to the runtime to revoke the object's bias. | |
| 5637 // Note that we first construct the presumed unbiased header so we | |
| 5638 // don't accidentally blow away another thread's valid bias. | |
| 5639 andq(swap_reg, | |
| 5640 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place); | |
| 5641 movq(tmp_reg, swap_reg); | |
| 5642 orq(tmp_reg, r15_thread); | |
| 5643 if (os::is_MP()) { | |
| 5644 lock(); | |
| 5645 } | |
| 5646 cmpxchgq(tmp_reg, Address(obj_reg, 0)); | |
| 5647 // If the biasing toward our thread failed, this means that | |
| 5648 // another thread succeeded in biasing it toward itself and we | |
| 5649 // need to revoke that bias. The revocation will occur in the | |
| 5650 // interpreter runtime in the slow case. | |
| 5651 if (counters != NULL) { | |
| 5652 cond_inc32(Assembler::zero, | |
| 5653 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr())); | |
| 5654 } | |
| 5655 if (slow_case != NULL) { | |
| 5656 jcc(Assembler::notZero, *slow_case); | |
| 5657 } | |
| 0 | 5658 jmp(done); |
| 5659 | |
| 304 | 5660 bind(try_rebias); |
| 5661 // At this point we know the epoch has expired, meaning that the | |
| 5662 // current "bias owner", if any, is actually invalid. Under these | |
| 5663 // circumstances _only_, we are allowed to use the current header's | |
| 5664 // value as the comparison value when doing the cas to acquire the | |
| 5665 // bias in the current epoch. In other words, we allow transfer of | |
| 5666 // the bias from one thread to another directly in this situation. | |
| 5667 // | |
| 5668 // FIXME: due to a lack of registers we currently blow away the age | |
| 5669 // bits in this situation. Should attempt to preserve them. | |
| 5670 load_prototype_header(tmp_reg, obj_reg); | |
| 5671 orq(tmp_reg, r15_thread); | |
| 5672 if (os::is_MP()) { | |
| 5673 lock(); | |
| 5674 } | |
| 5675 cmpxchgq(tmp_reg, Address(obj_reg, 0)); | |
| 5676 // If the biasing toward our thread failed, then another thread | |
| 5677 // succeeded in biasing it toward itself and we need to revoke that | |
| 5678 // bias. The revocation will occur in the runtime in the slow case. | |
| 5679 if (counters != NULL) { | |
| 5680 cond_inc32(Assembler::zero, | |
| 5681 ExternalAddress((address) counters->rebiased_lock_entry_count_addr())); | |
| 5682 } | |
| 5683 if (slow_case != NULL) { | |
| 5684 jcc(Assembler::notZero, *slow_case); | |
| 0 | 5685 } |
| 5686 jmp(done); | |
| 5687 | |
| 304 | 5688 bind(try_revoke_bias); |
| 5689 // The prototype mark in the klass doesn't have the bias bit set any | |
| 5690 // more, indicating that objects of this data type are not supposed | |
| 5691 // to be biased any more. We are going to try to reset the mark of | |
| 5692 // this object to the prototype value and fall through to the | |
| 5693 // CAS-based locking scheme. Note that if our CAS fails, it means | |
| 5694 // that another thread raced us for the privilege of revoking the | |
| 5695 // bias of this particular object, so it's okay to continue in the | |
| 5696 // normal locking code. | |
| 5697 // | |
| 5698 // FIXME: due to a lack of registers we currently blow away the age | |
| 5699 // bits in this situation. Should attempt to preserve them. | |
| 5700 load_prototype_header(tmp_reg, obj_reg); | |
| 5701 if (os::is_MP()) { | |
| 5702 lock(); | |
| 5703 } | |
| 5704 cmpxchgq(tmp_reg, Address(obj_reg, 0)); | |
| 5705 // Fall through to the normal CAS-based lock, because no matter what | |
| 5706 // the result of the above CAS, some thread must have succeeded in | |
| 5707 // removing the bias bit from the object's header. | |
| 5708 if (counters != NULL) { | |
| 5709 cond_inc32(Assembler::zero, | |
| 5710 ExternalAddress((address) counters->revoked_lock_entry_count_addr())); | |
| 5711 } | |
| 5712 | |
| 5713 bind(cas_label); | |
| 5714 | |
| 5715 return null_check_offset; | |
| 5716 } | |
| 5717 | |
| 5718 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) { | |
| 5719 Label L, E; | |
| 5720 | |
| 5721 #ifdef _WIN64 | |
| 5722 // Windows always allocates space for it's register args | |
| 5723 assert(num_args <= 4, "only register arguments supported"); | |
| 5724 subq(rsp, frame::arg_reg_save_area_bytes); | |
| 5725 #endif | |
| 5726 | |
| 5727 // Align stack if necessary | |
| 5728 testl(rsp, 15); | |
| 5729 jcc(Assembler::zero, L); | |
| 5730 | |
| 5731 subq(rsp, 8); | |
| 5732 { | |
| 5733 call(RuntimeAddress(entry_point)); | |
| 5734 } | |
| 5735 addq(rsp, 8); | |
| 5736 jmp(E); | |
| 5737 | |
| 5738 bind(L); | |
| 5739 { | |
| 5740 call(RuntimeAddress(entry_point)); | |
| 5741 } | |
| 5742 | |
| 5743 bind(E); | |
| 5744 | |
| 5745 #ifdef _WIN64 | |
| 5746 // restore stack pointer | |
| 5747 addq(rsp, frame::arg_reg_save_area_bytes); | |
| 5748 #endif | |
| 5749 | |
| 5750 } | |
| 5751 | |
| 5752 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) { | |
| 5753 assert(!src2.is_lval(), "should use cmpptr"); | |
| 5754 | |
| 5755 if (reachable(src2)) { | |
| 5756 cmpq(src1, as_Address(src2)); | |
| 5757 } else { | |
| 5758 lea(rscratch1, src2); | |
| 5759 Assembler::cmpq(src1, Address(rscratch1, 0)); | |
| 5760 } | |
| 5761 } | |
| 5762 | |
| 5763 int MacroAssembler::corrected_idivq(Register reg) { | |
| 5764 // Full implementation of Java ldiv and lrem; checks for special | |
| 5765 // case as described in JVM spec., p.243 & p.271. The function | |
| 5766 // returns the (pc) offset of the idivl instruction - may be needed | |
| 5767 // for implicit exceptions. | |
| 5768 // | |
| 5769 // normal case special case | |
| 5770 // | |
| 5771 // input : rax: dividend min_long | |
| 5772 // reg: divisor (may not be eax/edx) -1 | |
| 5773 // | |
| 5774 // output: rax: quotient (= rax idiv reg) min_long | |
| 5775 // rdx: remainder (= rax irem reg) 0 | |
| 5776 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register"); | |
| 5777 static const int64_t min_long = 0x8000000000000000; | |
| 5778 Label normal_case, special_case; | |
| 5779 | |
| 5780 // check for special case | |
| 5781 cmp64(rax, ExternalAddress((address) &min_long)); | |
| 5782 jcc(Assembler::notEqual, normal_case); | |
| 5783 xorl(rdx, rdx); // prepare rdx for possible special case (where | |
| 5784 // remainder = 0) | |
| 5785 cmpq(reg, -1); | |
| 5786 jcc(Assembler::equal, special_case); | |
| 5787 | |
| 5788 // handle normal case | |
| 5789 bind(normal_case); | |
| 5790 cdqq(); | |
| 5791 int idivq_offset = offset(); | |
| 5792 idivq(reg); | |
| 5793 | |
| 5794 // normal and special case exit | |
| 5795 bind(special_case); | |
| 5796 | |
| 5797 return idivq_offset; | |
| 5798 } | |
| 5799 | |
| 5800 void MacroAssembler::decrementq(Register reg, int value) { | |
| 5801 if (value == min_jint) { subq(reg, value); return; } | |
| 5802 if (value < 0) { incrementq(reg, -value); return; } | |
| 5803 if (value == 0) { ; return; } | |
| 5804 if (value == 1 && UseIncDec) { decq(reg) ; return; } | |
| 5805 /* else */ { subq(reg, value) ; return; } | |
| 5806 } | |
| 5807 | |
| 5808 void MacroAssembler::decrementq(Address dst, int value) { | |
| 5809 if (value == min_jint) { subq(dst, value); return; } | |
| 5810 if (value < 0) { incrementq(dst, -value); return; } | |
| 5811 if (value == 0) { ; return; } | |
| 5812 if (value == 1 && UseIncDec) { decq(dst) ; return; } | |
| 5813 /* else */ { subq(dst, value) ; return; } | |
| 5814 } | |
| 5815 | |
| 5816 void MacroAssembler::incrementq(Register reg, int value) { | |
| 5817 if (value == min_jint) { addq(reg, value); return; } | |
| 5818 if (value < 0) { decrementq(reg, -value); return; } | |
| 5819 if (value == 0) { ; return; } | |
| 5820 if (value == 1 && UseIncDec) { incq(reg) ; return; } | |
| 5821 /* else */ { addq(reg, value) ; return; } | |
| 5822 } | |
| 5823 | |
| 5824 void MacroAssembler::incrementq(Address dst, int value) { | |
| 5825 if (value == min_jint) { addq(dst, value); return; } | |
| 5826 if (value < 0) { decrementq(dst, -value); return; } | |
| 5827 if (value == 0) { ; return; } | |
| 5828 if (value == 1 && UseIncDec) { incq(dst) ; return; } | |
| 5829 /* else */ { addq(dst, value) ; return; } | |
| 5830 } | |
| 5831 | |
| 5832 // 32bit can do a case table jump in one instruction but we no longer allow the base | |
| 5833 // to be installed in the Address class | |
| 5834 void MacroAssembler::jump(ArrayAddress entry) { | |
| 5835 lea(rscratch1, entry.base()); | |
| 5836 Address dispatch = entry.index(); | |
| 5837 assert(dispatch._base == noreg, "must be"); | |
| 5838 dispatch._base = rscratch1; | |
| 5839 jmp(dispatch); | |
| 5840 } | |
| 5841 | |
| 5842 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { | |
| 5843 ShouldNotReachHere(); // 64bit doesn't use two regs | |
| 5844 cmpq(x_lo, y_lo); | |
| 5845 } | |
| 5846 | |
| 5847 void MacroAssembler::lea(Register dst, AddressLiteral src) { | |
| 5848 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); | |
| 5849 } | |
| 5850 | |
| 5851 void MacroAssembler::lea(Address dst, AddressLiteral adr) { | |
| 5852 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec()); | |
| 5853 movptr(dst, rscratch1); | |
| 5854 } | |
| 5855 | |
| 5856 void MacroAssembler::leave() { | |
| 5857 // %%% is this really better? Why not on 32bit too? | |
| 5858 emit_byte(0xC9); // LEAVE | |
| 5859 } | |
| 5860 | |
| 5861 void MacroAssembler::lneg(Register hi, Register lo) { | |
| 5862 ShouldNotReachHere(); // 64bit doesn't use two regs | |
| 5863 negq(lo); | |
| 5864 } | |
| 5865 | |
| 5866 void MacroAssembler::movoop(Register dst, jobject obj) { | |
| 5867 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate()); | |
| 5868 } | |
| 5869 | |
| 5870 void MacroAssembler::movoop(Address dst, jobject obj) { | |
| 5871 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate()); | |
| 5872 movq(dst, rscratch1); | |
| 5873 } | |
| 5874 | |
| 5875 void MacroAssembler::movptr(Register dst, AddressLiteral src) { | |
| 5876 if (src.is_lval()) { | |
| 5877 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); | |
| 5878 } else { | |
| 5879 if (reachable(src)) { | |
| 5880 movq(dst, as_Address(src)); | |
| 5881 } else { | |
| 5882 lea(rscratch1, src); | |
| 5883 movq(dst, Address(rscratch1,0)); | |
| 0 | 5884 } |
| 304 | 5885 } |
| 5886 } | |
| 5887 | |
| 5888 void MacroAssembler::movptr(ArrayAddress dst, Register src) { | |
| 5889 movq(as_Address(dst), src); | |
| 5890 } | |
| 5891 | |
| 5892 void MacroAssembler::movptr(Register dst, ArrayAddress src) { | |
| 5893 movq(dst, as_Address(src)); | |
| 5894 } | |
| 5895 | |
| 5896 // src should NEVER be a real pointer. Use AddressLiteral for true pointers | |
| 5897 void MacroAssembler::movptr(Address dst, intptr_t src) { | |
| 5898 mov64(rscratch1, src); | |
| 5899 movq(dst, rscratch1); | |
| 5900 } | |
| 5901 | |
| 5902 // These are mostly for initializing NULL | |
| 5903 void MacroAssembler::movptr(Address dst, int32_t src) { | |
| 5904 movslq(dst, src); | |
| 5905 } | |
| 5906 | |
| 5907 void MacroAssembler::movptr(Register dst, int32_t src) { | |
| 5908 mov64(dst, (intptr_t)src); | |
| 5909 } | |
| 5910 | |
| 5911 void MacroAssembler::pushoop(jobject obj) { | |
| 5912 movoop(rscratch1, obj); | |
| 5913 push(rscratch1); | |
| 5914 } | |
| 5915 | |
| 5916 void MacroAssembler::pushptr(AddressLiteral src) { | |
| 5917 lea(rscratch1, src); | |
| 5918 if (src.is_lval()) { | |
| 5919 push(rscratch1); | |
| 5920 } else { | |
| 5921 pushq(Address(rscratch1, 0)); | |
| 5922 } | |
| 5923 } | |
| 5924 | |
| 5925 void MacroAssembler::reset_last_Java_frame(bool clear_fp, | |
| 5926 bool clear_pc) { | |
| 5927 // we must set sp to zero to clear frame | |
|
512
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6787106: Hotspot 32 bit build fails on platforms having different definitions for intptr_t & int32_t
xlu
parents:
420
diff
changeset
|
5928 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); |
| 304 | 5929 // must clear fp, so that compiled frames are not confused; it is |
| 5930 // possible that we need it only for debugging | |
| 5931 if (clear_fp) { | |
|
512
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parents:
420
diff
changeset
|
5932 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); |
| 304 | 5933 } |
| 5934 | |
| 5935 if (clear_pc) { | |
|
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parents:
420
diff
changeset
|
5936 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); |
| 304 | 5937 } |
| 5938 } | |
| 5939 | |
| 5940 void MacroAssembler::set_last_Java_frame(Register last_java_sp, | |
| 5941 Register last_java_fp, | |
| 5942 address last_java_pc) { | |
| 5943 // determine last_java_sp register | |
| 5944 if (!last_java_sp->is_valid()) { | |
| 5945 last_java_sp = rsp; | |
| 5946 } | |
| 5947 | |
| 5948 // last_java_fp is optional | |
| 5949 if (last_java_fp->is_valid()) { | |
| 5950 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), | |
| 5951 last_java_fp); | |
| 5952 } | |
| 5953 | |
| 5954 // last_java_pc is optional | |
| 5955 if (last_java_pc != NULL) { | |
| 5956 Address java_pc(r15_thread, | |
| 5957 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()); | |
| 5958 lea(rscratch1, InternalAddress(last_java_pc)); | |
| 5959 movptr(java_pc, rscratch1); | |
| 5960 } | |
| 5961 | |
| 5962 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp); | |
| 5963 } | |
| 5964 | |
| 5965 static void pass_arg0(MacroAssembler* masm, Register arg) { | |
| 5966 if (c_rarg0 != arg ) { | |
| 5967 masm->mov(c_rarg0, arg); | |
| 5968 } | |
| 5969 } | |
| 5970 | |
| 5971 static void pass_arg1(MacroAssembler* masm, Register arg) { | |
| 5972 if (c_rarg1 != arg ) { | |
| 5973 masm->mov(c_rarg1, arg); | |
| 5974 } | |
| 5975 } | |
| 5976 | |
| 5977 static void pass_arg2(MacroAssembler* masm, Register arg) { | |
| 5978 if (c_rarg2 != arg ) { | |
| 5979 masm->mov(c_rarg2, arg); | |
| 5980 } | |
| 5981 } | |
| 5982 | |
| 5983 static void pass_arg3(MacroAssembler* masm, Register arg) { | |
| 5984 if (c_rarg3 != arg ) { | |
| 5985 masm->mov(c_rarg3, arg); | |
| 5986 } | |
| 5987 } | |
| 5988 | |
| 5989 void MacroAssembler::stop(const char* msg) { | |
| 5990 address rip = pc(); | |
| 5991 pusha(); // get regs on stack | |
| 5992 lea(c_rarg0, ExternalAddress((address) msg)); | |
| 5993 lea(c_rarg1, InternalAddress(rip)); | |
| 5994 movq(c_rarg2, rsp); // pass pointer to regs array | |
| 5995 andq(rsp, -16); // align stack as required by ABI | |
| 5996 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64))); | |
| 5997 hlt(); | |
| 5998 } | |
| 5999 | |
| 6000 void MacroAssembler::warn(const char* msg) { | |
|
1976
0fc262af204f
6780143: hs203t003 hits SIGSEGV/EXCEPTION_ACCESS_VIOLATION with -XX:+UseCompressedOops
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parents:
1972
diff
changeset
|
6001 push(rsp); |
| 304 | 6002 andq(rsp, -16); // align stack as required by push_CPU_state and call |
| 6003 | |
| 6004 push_CPU_state(); // keeps alignment at 16 bytes | |
| 6005 lea(c_rarg0, ExternalAddress((address) msg)); | |
| 6006 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0); | |
| 6007 pop_CPU_state(); | |
|
1976
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diff
changeset
|
6008 pop(rsp); |
| 304 | 6009 } |
| 6010 | |
| 6011 #ifndef PRODUCT | |
| 6012 extern "C" void findpc(intptr_t x); | |
| 6013 #endif | |
| 6014 | |
| 6015 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) { | |
| 6016 // In order to get locks to work, we need to fake a in_VM state | |
| 6017 if (ShowMessageBoxOnError ) { | |
| 6018 JavaThread* thread = JavaThread::current(); | |
| 6019 JavaThreadState saved_state = thread->thread_state(); | |
| 6020 thread->set_thread_state(_thread_in_vm); | |
| 6021 #ifndef PRODUCT | |
| 6022 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { | |
| 6023 ttyLocker ttyl; | |
| 6024 BytecodeCounter::print(); | |
| 0 | 6025 } |
| 304 | 6026 #endif |
| 6027 // To see where a verify_oop failed, get $ebx+40/X for this frame. | |
| 6028 // XXX correct this offset for amd64 | |
| 6029 // This is the value of eip which points to where verify_oop will return. | |
| 6030 if (os::message_box(msg, "Execution stopped, print registers?")) { | |
| 6031 ttyLocker ttyl; | |
| 6032 tty->print_cr("rip = 0x%016lx", pc); | |
| 6033 #ifndef PRODUCT | |
| 6034 tty->cr(); | |
| 6035 findpc(pc); | |
| 6036 tty->cr(); | |
| 6037 #endif | |
| 6038 tty->print_cr("rax = 0x%016lx", regs[15]); | |
| 6039 tty->print_cr("rbx = 0x%016lx", regs[12]); | |
| 6040 tty->print_cr("rcx = 0x%016lx", regs[14]); | |
| 6041 tty->print_cr("rdx = 0x%016lx", regs[13]); | |
| 6042 tty->print_cr("rdi = 0x%016lx", regs[8]); | |
| 6043 tty->print_cr("rsi = 0x%016lx", regs[9]); | |
| 6044 tty->print_cr("rbp = 0x%016lx", regs[10]); | |
| 6045 tty->print_cr("rsp = 0x%016lx", regs[11]); | |
| 6046 tty->print_cr("r8 = 0x%016lx", regs[7]); | |
| 6047 tty->print_cr("r9 = 0x%016lx", regs[6]); | |
| 6048 tty->print_cr("r10 = 0x%016lx", regs[5]); | |
| 6049 tty->print_cr("r11 = 0x%016lx", regs[4]); | |
| 6050 tty->print_cr("r12 = 0x%016lx", regs[3]); | |
| 6051 tty->print_cr("r13 = 0x%016lx", regs[2]); | |
| 6052 tty->print_cr("r14 = 0x%016lx", regs[1]); | |
| 6053 tty->print_cr("r15 = 0x%016lx", regs[0]); | |
| 6054 BREAKPOINT; | |
| 0 | 6055 } |
| 304 | 6056 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); |
| 6057 } else { | |
| 6058 ttyLocker ttyl; | |
| 6059 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", | |
| 6060 msg); | |
|
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7045514: SPARC assembly code for JSR 292 ricochet frames
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3336
diff
changeset
|
6061 assert(false, err_msg("DEBUG MESSAGE: %s", msg)); |
| 304 | 6062 } |
| 6063 } | |
| 6064 | |
| 6065 #endif // _LP64 | |
| 6066 | |
| 6067 // Now versions that are common to 32/64 bit | |
| 6068 | |
| 6069 void MacroAssembler::addptr(Register dst, int32_t imm32) { | |
| 6070 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32)); | |
| 6071 } | |
| 6072 | |
| 6073 void MacroAssembler::addptr(Register dst, Register src) { | |
| 6074 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); | |
| 6075 } | |
| 6076 | |
| 6077 void MacroAssembler::addptr(Address dst, Register src) { | |
| 6078 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); | |
| 6079 } | |
| 6080 | |
| 4759 | 6081 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) { |
| 6082 if (reachable(src)) { | |
| 6083 Assembler::addsd(dst, as_Address(src)); | |
| 6084 } else { | |
| 6085 lea(rscratch1, src); | |
| 6086 Assembler::addsd(dst, Address(rscratch1, 0)); | |
| 6087 } | |
| 6088 } | |
| 6089 | |
| 6090 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) { | |
| 6091 if (reachable(src)) { | |
| 6092 addss(dst, as_Address(src)); | |
| 6093 } else { | |
| 6094 lea(rscratch1, src); | |
| 6095 addss(dst, Address(rscratch1, 0)); | |
| 6096 } | |
| 6097 } | |
| 6098 | |
| 304 | 6099 void MacroAssembler::align(int modulus) { |
| 6100 if (offset() % modulus != 0) { | |
| 6101 nop(modulus - (offset() % modulus)); | |
| 6102 } | |
| 6103 } | |
| 6104 | |
| 6105 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) { | |
| 4759 | 6106 // Used in sign-masking with aligned address. |
| 6107 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); | |
| 1060 | 6108 if (reachable(src)) { |
| 4759 | 6109 Assembler::andpd(dst, as_Address(src)); |
| 1060 | 6110 } else { |
| 6111 lea(rscratch1, src); | |
| 4759 | 6112 Assembler::andpd(dst, Address(rscratch1, 0)); |
| 6113 } | |
| 6114 } | |
| 6115 | |
| 6116 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) { | |
| 6117 // Used in sign-masking with aligned address. | |
| 6118 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); | |
| 6119 if (reachable(src)) { | |
| 6120 Assembler::andps(dst, as_Address(src)); | |
| 6121 } else { | |
| 6122 lea(rscratch1, src); | |
| 6123 Assembler::andps(dst, Address(rscratch1, 0)); | |
| 1060 | 6124 } |
| 304 | 6125 } |
| 6126 | |
| 6127 void MacroAssembler::andptr(Register dst, int32_t imm32) { | |
| 6128 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32)); | |
| 6129 } | |
| 6130 | |
| 6131 void MacroAssembler::atomic_incl(AddressLiteral counter_addr) { | |
| 6132 pushf(); | |
| 6133 if (os::is_MP()) | |
| 6134 lock(); | |
| 6135 incrementl(counter_addr); | |
| 6136 popf(); | |
| 6137 } | |
| 6138 | |
| 6139 // Writes to stack successive pages until offset reached to check for | |
| 6140 // stack overflow + shadow pages. This clobbers tmp. | |
| 6141 void MacroAssembler::bang_stack_size(Register size, Register tmp) { | |
| 6142 movptr(tmp, rsp); | |
| 6143 // Bang stack for total size given plus shadow page size. | |
| 6144 // Bang one page at a time because large size can bang beyond yellow and | |
| 6145 // red zones. | |
| 6146 Label loop; | |
| 6147 bind(loop); | |
| 6148 movl(Address(tmp, (-os::vm_page_size())), size ); | |
| 6149 subptr(tmp, os::vm_page_size()); | |
| 6150 subl(size, os::vm_page_size()); | |
| 6151 jcc(Assembler::greater, loop); | |
| 6152 | |
| 6153 // Bang down shadow pages too. | |
| 6154 // The -1 because we already subtracted 1 page. | |
| 6155 for (int i = 0; i< StackShadowPages-1; i++) { | |
| 6156 // this could be any sized move but this is can be a debugging crumb | |
| 6157 // so the bigger the better. | |
| 6158 movptr(Address(tmp, (-i*os::vm_page_size())), size ); | |
| 6159 } | |
| 6160 } | |
| 6161 | |
| 6162 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) { | |
| 6163 assert(UseBiasedLocking, "why call this otherwise?"); | |
| 6164 | |
| 6165 // Check for biased locking unlock case, which is a no-op | |
| 6166 // Note: we do not have to check the thread ID for two reasons. | |
| 6167 // First, the interpreter checks for IllegalMonitorStateException at | |
| 6168 // a higher level. Second, if the bias was revoked while we held the | |
| 6169 // lock, the object could not be rebiased toward another thread, so | |
| 6170 // the bias bit would be clear. | |
| 6171 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes())); | |
| 6172 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place); | |
| 6173 cmpptr(temp_reg, markOopDesc::biased_lock_pattern); | |
| 6174 jcc(Assembler::equal, done); | |
| 6175 } | |
| 6176 | |
| 6177 void MacroAssembler::c2bool(Register x) { | |
| 6178 // implements x == 0 ? 0 : 1 | |
| 6179 // note: must only look at least-significant byte of x | |
| 6180 // since C-style booleans are stored in one byte | |
| 6181 // only! (was bug) | |
| 6182 andl(x, 0xFF); | |
| 6183 setb(Assembler::notZero, x); | |
| 6184 } | |
| 6185 | |
| 6186 // Wouldn't need if AddressLiteral version had new name | |
| 6187 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) { | |
| 6188 Assembler::call(L, rtype); | |
| 6189 } | |
| 6190 | |
| 6191 void MacroAssembler::call(Register entry) { | |
| 6192 Assembler::call(entry); | |
| 6193 } | |
| 6194 | |
| 6195 void MacroAssembler::call(AddressLiteral entry) { | |
| 6196 if (reachable(entry)) { | |
| 6197 Assembler::call_literal(entry.target(), entry.rspec()); | |
| 6198 } else { | |
| 6199 lea(rscratch1, entry); | |
| 6200 Assembler::call(rscratch1); | |
| 6201 } | |
| 6202 } | |
| 6203 | |
| 6204 // Implementation of call_VM versions | |
| 6205 | |
| 6206 void MacroAssembler::call_VM(Register oop_result, | |
| 6207 address entry_point, | |
| 6208 bool check_exceptions) { | |
| 6209 Label C, E; | |
| 6210 call(C, relocInfo::none); | |
| 6211 jmp(E); | |
| 6212 | |
| 6213 bind(C); | |
| 6214 call_VM_helper(oop_result, entry_point, 0, check_exceptions); | |
| 6215 ret(0); | |
| 6216 | |
| 6217 bind(E); | |
| 6218 } | |
| 6219 | |
| 6220 void MacroAssembler::call_VM(Register oop_result, | |
| 6221 address entry_point, | |
| 6222 Register arg_1, | |
| 6223 bool check_exceptions) { | |
| 6224 Label C, E; | |
| 6225 call(C, relocInfo::none); | |
| 6226 jmp(E); | |
| 6227 | |
| 6228 bind(C); | |
| 6229 pass_arg1(this, arg_1); | |
| 6230 call_VM_helper(oop_result, entry_point, 1, check_exceptions); | |
| 6231 ret(0); | |
| 6232 | |
| 6233 bind(E); | |
| 6234 } | |
| 6235 | |
| 6236 void MacroAssembler::call_VM(Register oop_result, | |
| 6237 address entry_point, | |
| 6238 Register arg_1, | |
| 6239 Register arg_2, | |
| 6240 bool check_exceptions) { | |
| 6241 Label C, E; | |
| 6242 call(C, relocInfo::none); | |
| 6243 jmp(E); | |
| 6244 | |
| 6245 bind(C); | |
| 6246 | |
| 6247 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
| 6248 | |
| 6249 pass_arg2(this, arg_2); | |
| 6250 pass_arg1(this, arg_1); | |
| 6251 call_VM_helper(oop_result, entry_point, 2, check_exceptions); | |
| 6252 ret(0); | |
| 6253 | |
| 6254 bind(E); | |
| 6255 } | |
| 6256 | |
| 6257 void MacroAssembler::call_VM(Register oop_result, | |
| 6258 address entry_point, | |
| 6259 Register arg_1, | |
| 6260 Register arg_2, | |
| 6261 Register arg_3, | |
| 6262 bool check_exceptions) { | |
| 6263 Label C, E; | |
| 6264 call(C, relocInfo::none); | |
| 6265 jmp(E); | |
| 6266 | |
| 6267 bind(C); | |
| 6268 | |
| 6269 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); | |
| 6270 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); | |
| 6271 pass_arg3(this, arg_3); | |
| 6272 | |
| 6273 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
| 6274 pass_arg2(this, arg_2); | |
| 6275 | |
| 6276 pass_arg1(this, arg_1); | |
| 6277 call_VM_helper(oop_result, entry_point, 3, check_exceptions); | |
| 6278 ret(0); | |
| 6279 | |
| 6280 bind(E); | |
| 6281 } | |
| 6282 | |
| 6283 void MacroAssembler::call_VM(Register oop_result, | |
| 6284 Register last_java_sp, | |
| 6285 address entry_point, | |
| 6286 int number_of_arguments, | |
| 6287 bool check_exceptions) { | |
| 6288 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); | |
| 6289 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); | |
| 6290 } | |
| 6291 | |
| 6292 void MacroAssembler::call_VM(Register oop_result, | |
| 6293 Register last_java_sp, | |
| 6294 address entry_point, | |
| 6295 Register arg_1, | |
| 6296 bool check_exceptions) { | |
| 6297 pass_arg1(this, arg_1); | |
| 6298 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); | |
| 6299 } | |
| 6300 | |
| 6301 void MacroAssembler::call_VM(Register oop_result, | |
| 6302 Register last_java_sp, | |
| 6303 address entry_point, | |
| 6304 Register arg_1, | |
| 6305 Register arg_2, | |
| 6306 bool check_exceptions) { | |
| 6307 | |
| 6308 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
| 6309 pass_arg2(this, arg_2); | |
| 6310 pass_arg1(this, arg_1); | |
| 6311 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); | |
| 6312 } | |
| 6313 | |
| 6314 void MacroAssembler::call_VM(Register oop_result, | |
| 6315 Register last_java_sp, | |
| 6316 address entry_point, | |
| 6317 Register arg_1, | |
| 6318 Register arg_2, | |
| 6319 Register arg_3, | |
| 6320 bool check_exceptions) { | |
| 6321 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); | |
| 6322 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); | |
| 6323 pass_arg3(this, arg_3); | |
| 6324 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
| 6325 pass_arg2(this, arg_2); | |
| 6326 pass_arg1(this, arg_1); | |
| 6327 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); | |
| 6328 } | |
| 6329 | |
|
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3753
diff
changeset
|
6330 void MacroAssembler::super_call_VM(Register oop_result, |
|
5cf771a79037
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
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3753
diff
changeset
|
6331 Register last_java_sp, |
|
5cf771a79037
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
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3753
diff
changeset
|
6332 address entry_point, |
|
5cf771a79037
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
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3753
diff
changeset
|
6333 int number_of_arguments, |
|
5cf771a79037
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
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3753
diff
changeset
|
6334 bool check_exceptions) { |
|
5cf771a79037
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
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3753
diff
changeset
|
6335 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); |
|
5cf771a79037
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
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3753
diff
changeset
|
6336 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); |
|
5cf771a79037
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
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3753
diff
changeset
|
6337 } |
|
5cf771a79037
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
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3753
diff
changeset
|
6338 |
|
5cf771a79037
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
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3753
diff
changeset
|
6339 void MacroAssembler::super_call_VM(Register oop_result, |
|
5cf771a79037
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
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3753
diff
changeset
|
6340 Register last_java_sp, |
|
5cf771a79037
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
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3753
diff
changeset
|
6341 address entry_point, |
|
5cf771a79037
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3753
diff
changeset
|
6342 Register arg_1, |
|
5cf771a79037
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3753
diff
changeset
|
6343 bool check_exceptions) { |
|
5cf771a79037
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3753
diff
changeset
|
6344 pass_arg1(this, arg_1); |
|
5cf771a79037
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3753
diff
changeset
|
6345 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); |
|
5cf771a79037
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3753
diff
changeset
|
6346 } |
|
5cf771a79037
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3753
diff
changeset
|
6347 |
|
5cf771a79037
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3753
diff
changeset
|
6348 void MacroAssembler::super_call_VM(Register oop_result, |
|
5cf771a79037
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3753
diff
changeset
|
6349 Register last_java_sp, |
|
5cf771a79037
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3753
diff
changeset
|
6350 address entry_point, |
|
5cf771a79037
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3753
diff
changeset
|
6351 Register arg_1, |
|
5cf771a79037
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3753
diff
changeset
|
6352 Register arg_2, |
|
5cf771a79037
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3753
diff
changeset
|
6353 bool check_exceptions) { |
|
5cf771a79037
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3753
diff
changeset
|
6354 |
|
5cf771a79037
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3753
diff
changeset
|
6355 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); |
|
5cf771a79037
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3753
diff
changeset
|
6356 pass_arg2(this, arg_2); |
|
5cf771a79037
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3753
diff
changeset
|
6357 pass_arg1(this, arg_1); |
|
5cf771a79037
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3753
diff
changeset
|
6358 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); |
|
5cf771a79037
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3753
diff
changeset
|
6359 } |
|
5cf771a79037
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3753
diff
changeset
|
6360 |
|
5cf771a79037
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3753
diff
changeset
|
6361 void MacroAssembler::super_call_VM(Register oop_result, |
|
5cf771a79037
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3753
diff
changeset
|
6362 Register last_java_sp, |
|
5cf771a79037
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3753
diff
changeset
|
6363 address entry_point, |
|
5cf771a79037
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3753
diff
changeset
|
6364 Register arg_1, |
|
5cf771a79037
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3753
diff
changeset
|
6365 Register arg_2, |
|
5cf771a79037
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3753
diff
changeset
|
6366 Register arg_3, |
|
5cf771a79037
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3753
diff
changeset
|
6367 bool check_exceptions) { |
|
5cf771a79037
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3753
diff
changeset
|
6368 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); |
|
5cf771a79037
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3753
diff
changeset
|
6369 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); |
|
5cf771a79037
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3753
diff
changeset
|
6370 pass_arg3(this, arg_3); |
|
5cf771a79037
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3753
diff
changeset
|
6371 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); |
|
5cf771a79037
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3753
diff
changeset
|
6372 pass_arg2(this, arg_2); |
|
5cf771a79037
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3753
diff
changeset
|
6373 pass_arg1(this, arg_1); |
|
5cf771a79037
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3753
diff
changeset
|
6374 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); |
|
5cf771a79037
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3753
diff
changeset
|
6375 } |
|
5cf771a79037
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
3753
diff
changeset
|
6376 |
| 304 | 6377 void MacroAssembler::call_VM_base(Register oop_result, |
| 6378 Register java_thread, | |
| 6379 Register last_java_sp, | |
| 6380 address entry_point, | |
| 6381 int number_of_arguments, | |
| 6382 bool check_exceptions) { | |
| 6383 // determine java_thread register | |
| 6384 if (!java_thread->is_valid()) { | |
| 6385 #ifdef _LP64 | |
| 6386 java_thread = r15_thread; | |
| 6387 #else | |
| 6388 java_thread = rdi; | |
| 6389 get_thread(java_thread); | |
| 6390 #endif // LP64 | |
| 6391 } | |
| 6392 // determine last_java_sp register | |
| 6393 if (!last_java_sp->is_valid()) { | |
| 6394 last_java_sp = rsp; | |
| 6395 } | |
| 6396 // debugging support | |
| 6397 assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); | |
| 6398 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register")); | |
|
1976
0fc262af204f
6780143: hs203t003 hits SIGSEGV/EXCEPTION_ACCESS_VIOLATION with -XX:+UseCompressedOops
coleenp
parents:
1972
diff
changeset
|
6399 #ifdef ASSERT |
|
4714
96ce4c27112f
7122939: TraceBytecodes broken with UseCompressedOops
coleenp
parents:
4118
diff
changeset
|
6400 // TraceBytecodes does not use r12 but saves it over the call, so don't verify |
|
96ce4c27112f
7122939: TraceBytecodes broken with UseCompressedOops
coleenp
parents:
4118
diff
changeset
|
6401 // r12 is the heapbase. |
|
96ce4c27112f
7122939: TraceBytecodes broken with UseCompressedOops
coleenp
parents:
4118
diff
changeset
|
6402 LP64_ONLY(if (UseCompressedOops && !TraceBytecodes) verify_heapbase("call_VM_base");) |
|
1976
0fc262af204f
6780143: hs203t003 hits SIGSEGV/EXCEPTION_ACCESS_VIOLATION with -XX:+UseCompressedOops
coleenp
parents:
1972
diff
changeset
|
6403 #endif // ASSERT |
|
0fc262af204f
6780143: hs203t003 hits SIGSEGV/EXCEPTION_ACCESS_VIOLATION with -XX:+UseCompressedOops
coleenp
parents:
1972
diff
changeset
|
6404 |
| 304 | 6405 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result"); |
| 6406 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp"); | |
| 6407 | |
| 6408 // push java thread (becomes first argument of C function) | |
| 6409 | |
| 6410 NOT_LP64(push(java_thread); number_of_arguments++); | |
| 6411 LP64_ONLY(mov(c_rarg0, r15_thread)); | |
| 6412 | |
| 6413 // set last Java frame before call | |
| 6414 assert(last_java_sp != rbp, "can't use ebp/rbp"); | |
| 6415 | |
| 6416 // Only interpreter should have to set fp | |
| 6417 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL); | |
| 6418 | |
| 6419 // do the call, remove parameters | |
| 6420 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments); | |
| 6421 | |
| 6422 // restore the thread (cannot use the pushed argument since arguments | |
| 6423 // may be overwritten by C code generated by an optimizing compiler); | |
| 6424 // however can use the register value directly if it is callee saved. | |
| 6425 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) { | |
| 6426 // rdi & rsi (also r15) are callee saved -> nothing to do | |
| 6427 #ifdef ASSERT | |
| 6428 guarantee(java_thread != rax, "change this code"); | |
| 6429 push(rax); | |
| 6430 { Label L; | |
| 6431 get_thread(rax); | |
| 6432 cmpptr(java_thread, rax); | |
| 6433 jcc(Assembler::equal, L); | |
| 6434 stop("MacroAssembler::call_VM_base: rdi not callee saved?"); | |
| 6435 bind(L); | |
| 0 | 6436 } |
| 304 | 6437 pop(rax); |
| 6438 #endif | |
| 6439 } else { | |
| 6440 get_thread(java_thread); | |
| 6441 } | |
| 6442 // reset last Java frame | |
| 6443 // Only interpreter should have to clear fp | |
| 6444 reset_last_Java_frame(java_thread, true, false); | |
| 6445 | |
| 6446 #ifndef CC_INTERP | |
| 6447 // C++ interp handles this in the interpreter | |
| 6448 check_and_handle_popframe(java_thread); | |
| 6449 check_and_handle_earlyret(java_thread); | |
| 6450 #endif /* CC_INTERP */ | |
| 6451 | |
| 6452 if (check_exceptions) { | |
| 6453 // check for pending exceptions (java_thread is set upon return) | |
| 6454 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD); | |
| 6455 #ifndef _LP64 | |
| 6456 jump_cc(Assembler::notEqual, | |
| 6457 RuntimeAddress(StubRoutines::forward_exception_entry())); | |
| 6458 #else | |
| 6459 // This used to conditionally jump to forward_exception however it is | |
| 6460 // possible if we relocate that the branch will not reach. So we must jump | |
| 6461 // around so we can always reach | |
| 6462 | |
| 6463 Label ok; | |
| 6464 jcc(Assembler::equal, ok); | |
| 6465 jump(RuntimeAddress(StubRoutines::forward_exception_entry())); | |
| 6466 bind(ok); | |
| 6467 #endif // LP64 | |
| 6468 } | |
| 6469 | |
| 6470 // get oop result if there is one and reset the value in the thread | |
| 6471 if (oop_result->is_valid()) { | |
| 6472 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset())); | |
|
512
db4caa99ef11
6787106: Hotspot 32 bit build fails on platforms having different definitions for intptr_t & int32_t
xlu
parents:
420
diff
changeset
|
6473 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD); |
| 304 | 6474 verify_oop(oop_result, "broken oop in call_VM_base"); |
| 6475 } | |
| 6476 } | |
| 6477 | |
| 6478 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) { | |
| 6479 | |
| 6480 // Calculate the value for last_Java_sp | |
| 6481 // somewhat subtle. call_VM does an intermediate call | |
| 6482 // which places a return address on the stack just under the | |
| 6483 // stack pointer as the user finsihed with it. This allows | |
| 6484 // use to retrieve last_Java_pc from last_Java_sp[-1]. | |
| 6485 // On 32bit we then have to push additional args on the stack to accomplish | |
| 6486 // the actual requested call. On 64bit call_VM only can use register args | |
| 6487 // so the only extra space is the return address that call_VM created. | |
| 6488 // This hopefully explains the calculations here. | |
| 6489 | |
| 6490 #ifdef _LP64 | |
| 6491 // We've pushed one address, correct last_Java_sp | |
| 6492 lea(rax, Address(rsp, wordSize)); | |
| 6493 #else | |
| 6494 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize)); | |
| 6495 #endif // LP64 | |
| 6496 | |
| 6497 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions); | |
| 6498 | |
| 6499 } | |
| 6500 | |
| 6501 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) { | |
| 6502 call_VM_leaf_base(entry_point, number_of_arguments); | |
| 6503 } | |
| 6504 | |
| 6505 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) { | |
| 6506 pass_arg0(this, arg_0); | |
| 6507 call_VM_leaf(entry_point, 1); | |
| 6508 } | |
| 6509 | |
| 6510 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { | |
| 6511 | |
| 6512 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); | |
| 6513 pass_arg1(this, arg_1); | |
| 6514 pass_arg0(this, arg_0); | |
| 6515 call_VM_leaf(entry_point, 2); | |
| 6516 } | |
| 6517 | |
| 6518 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { | |
| 6519 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); | |
| 6520 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
| 6521 pass_arg2(this, arg_2); | |
| 6522 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); | |
| 6523 pass_arg1(this, arg_1); | |
| 6524 pass_arg0(this, arg_0); | |
| 6525 call_VM_leaf(entry_point, 3); | |
| 6526 } | |
| 6527 | |
|
3336
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6528 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) { |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6529 pass_arg0(this, arg_0); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6530 MacroAssembler::call_VM_leaf_base(entry_point, 1); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6531 } |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6532 |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6533 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6534 |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6535 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6536 pass_arg1(this, arg_1); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6537 pass_arg0(this, arg_0); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6538 MacroAssembler::call_VM_leaf_base(entry_point, 2); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6539 } |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6540 |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6541 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6542 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6543 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6544 pass_arg2(this, arg_2); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6545 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6546 pass_arg1(this, arg_1); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6547 pass_arg0(this, arg_0); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6548 MacroAssembler::call_VM_leaf_base(entry_point, 3); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6549 } |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6550 |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6551 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) { |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6552 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg")); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6553 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6554 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6555 pass_arg3(this, arg_3); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6556 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6557 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6558 pass_arg2(this, arg_2); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6559 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6560 pass_arg1(this, arg_1); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6561 pass_arg0(this, arg_0); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6562 MacroAssembler::call_VM_leaf_base(entry_point, 4); |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
3261
diff
changeset
|
6563 } |
|
2e038ad0c1d0
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
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3261
diff
changeset
|
6564 |
| 304 | 6565 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { |
| 6566 } | |
| 6567 | |
| 6568 void MacroAssembler::check_and_handle_popframe(Register java_thread) { | |
| 6569 } | |
| 6570 | |
| 6571 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) { | |
| 6572 if (reachable(src1)) { | |
| 6573 cmpl(as_Address(src1), imm); | |
| 6574 } else { | |
| 6575 lea(rscratch1, src1); | |
| 6576 cmpl(Address(rscratch1, 0), imm); | |
| 6577 } | |
| 6578 } | |
| 6579 | |
| 6580 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) { | |
| 6581 assert(!src2.is_lval(), "use cmpptr"); | |
| 6582 if (reachable(src2)) { | |
| 6583 cmpl(src1, as_Address(src2)); | |
| 6584 } else { | |
| 6585 lea(rscratch1, src2); | |
| 6586 cmpl(src1, Address(rscratch1, 0)); | |
| 6587 } | |
| 6588 } | |
| 6589 | |
| 6590 void MacroAssembler::cmp32(Register src1, int32_t imm) { | |
| 6591 Assembler::cmpl(src1, imm); | |
| 6592 } | |
| 6593 | |
| 6594 void MacroAssembler::cmp32(Register src1, Address src2) { | |
| 6595 Assembler::cmpl(src1, src2); | |
| 6596 } | |
| 6597 | |
| 6598 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { | |
| 6599 ucomisd(opr1, opr2); | |
| 6600 | |
| 6601 Label L; | |
| 6602 if (unordered_is_less) { | |
| 6603 movl(dst, -1); | |
| 6604 jcc(Assembler::parity, L); | |
| 6605 jcc(Assembler::below , L); | |
| 6606 movl(dst, 0); | |
| 6607 jcc(Assembler::equal , L); | |
| 6608 increment(dst); | |
| 6609 } else { // unordered is greater | |
| 6610 movl(dst, 1); | |
| 6611 jcc(Assembler::parity, L); | |
| 6612 jcc(Assembler::above , L); | |
| 6613 movl(dst, 0); | |
| 6614 jcc(Assembler::equal , L); | |
| 6615 decrementl(dst); | |
| 6616 } | |
| 6617 bind(L); | |
| 6618 } | |
| 6619 | |
| 6620 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { | |
| 6621 ucomiss(opr1, opr2); | |
| 6622 | |
| 6623 Label L; | |
| 6624 if (unordered_is_less) { | |
| 6625 movl(dst, -1); | |
| 6626 jcc(Assembler::parity, L); | |
| 6627 jcc(Assembler::below , L); | |
| 6628 movl(dst, 0); | |
| 6629 jcc(Assembler::equal , L); | |
| 6630 increment(dst); | |
| 6631 } else { // unordered is greater | |
| 6632 movl(dst, 1); | |
| 6633 jcc(Assembler::parity, L); | |
| 6634 jcc(Assembler::above , L); | |
| 6635 movl(dst, 0); | |
| 6636 jcc(Assembler::equal , L); | |
| 6637 decrementl(dst); | |
| 6638 } | |
| 6639 bind(L); | |
| 6640 } | |
| 6641 | |
| 6642 | |
| 6643 void MacroAssembler::cmp8(AddressLiteral src1, int imm) { | |
| 6644 if (reachable(src1)) { | |
| 6645 cmpb(as_Address(src1), imm); | |
| 6646 } else { | |
| 6647 lea(rscratch1, src1); | |
| 6648 cmpb(Address(rscratch1, 0), imm); | |
| 6649 } | |
| 6650 } | |
| 6651 | |
| 6652 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) { | |
| 6653 #ifdef _LP64 | |
| 6654 if (src2.is_lval()) { | |
| 6655 movptr(rscratch1, src2); | |
| 6656 Assembler::cmpq(src1, rscratch1); | |
| 6657 } else if (reachable(src2)) { | |
| 6658 cmpq(src1, as_Address(src2)); | |
| 6659 } else { | |
| 6660 lea(rscratch1, src2); | |
| 6661 Assembler::cmpq(src1, Address(rscratch1, 0)); | |
| 6662 } | |
| 6663 #else | |
| 6664 if (src2.is_lval()) { | |
| 6665 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); | |
| 6666 } else { | |
| 6667 cmpl(src1, as_Address(src2)); | |
| 6668 } | |
| 6669 #endif // _LP64 | |
| 6670 } | |
| 6671 | |
| 6672 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) { | |
| 6673 assert(src2.is_lval(), "not a mem-mem compare"); | |
| 6674 #ifdef _LP64 | |
| 6675 // moves src2's literal address | |
| 6676 movptr(rscratch1, src2); | |
| 6677 Assembler::cmpq(src1, rscratch1); | |
| 6678 #else | |
| 6679 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); | |
| 6680 #endif // _LP64 | |
| 6681 } | |
| 6682 | |
| 6683 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) { | |
| 6684 if (reachable(adr)) { | |
| 6685 if (os::is_MP()) | |
| 6686 lock(); | |
| 6687 cmpxchgptr(reg, as_Address(adr)); | |
| 6688 } else { | |
| 6689 lea(rscratch1, adr); | |
| 6690 if (os::is_MP()) | |
| 6691 lock(); | |
| 6692 cmpxchgptr(reg, Address(rscratch1, 0)); | |
| 6693 } | |
| 6694 } | |
| 6695 | |
| 6696 void MacroAssembler::cmpxchgptr(Register reg, Address adr) { | |
| 6697 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr)); | |
| 6698 } | |
| 6699 | |
| 6700 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) { | |
| 1060 | 6701 if (reachable(src)) { |
| 4759 | 6702 Assembler::comisd(dst, as_Address(src)); |
| 1060 | 6703 } else { |
| 6704 lea(rscratch1, src); | |
| 4759 | 6705 Assembler::comisd(dst, Address(rscratch1, 0)); |
| 1060 | 6706 } |
| 304 | 6707 } |
| 6708 | |
| 6709 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) { | |
| 1060 | 6710 if (reachable(src)) { |
| 4759 | 6711 Assembler::comiss(dst, as_Address(src)); |
| 1060 | 6712 } else { |
| 6713 lea(rscratch1, src); | |
| 4759 | 6714 Assembler::comiss(dst, Address(rscratch1, 0)); |
| 1060 | 6715 } |
| 304 | 6716 } |
| 6717 | |
| 6718 | |
| 6719 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) { | |
| 6720 Condition negated_cond = negate_condition(cond); | |
| 6721 Label L; | |
| 6722 jcc(negated_cond, L); | |
| 6723 atomic_incl(counter_addr); | |
| 6724 bind(L); | |
| 6725 } | |
| 6726 | |
| 6727 int MacroAssembler::corrected_idivl(Register reg) { | |
| 6728 // Full implementation of Java idiv and irem; checks for | |
| 6729 // special case as described in JVM spec., p.243 & p.271. | |
| 6730 // The function returns the (pc) offset of the idivl | |
| 6731 // instruction - may be needed for implicit exceptions. | |
| 6732 // | |
| 6733 // normal case special case | |
| 6734 // | |
| 6735 // input : rax,: dividend min_int | |
| 6736 // reg: divisor (may not be rax,/rdx) -1 | |
| 6737 // | |
| 6738 // output: rax,: quotient (= rax, idiv reg) min_int | |
| 6739 // rdx: remainder (= rax, irem reg) 0 | |
| 6740 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register"); | |
| 6741 const int min_int = 0x80000000; | |
| 6742 Label normal_case, special_case; | |
| 6743 | |
| 6744 // check for special case | |
| 6745 cmpl(rax, min_int); | |
| 6746 jcc(Assembler::notEqual, normal_case); | |
| 6747 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0) | |
| 6748 cmpl(reg, -1); | |
| 6749 jcc(Assembler::equal, special_case); | |
| 6750 | |
| 6751 // handle normal case | |
| 6752 bind(normal_case); | |
| 6753 cdql(); | |
| 6754 int idivl_offset = offset(); | |
| 6755 idivl(reg); | |
| 6756 | |
| 6757 // normal and special case exit | |
| 6758 bind(special_case); | |
| 6759 | |
| 6760 return idivl_offset; | |
| 6761 } | |
| 6762 | |
| 6763 | |
| 6764 | |
| 6765 void MacroAssembler::decrementl(Register reg, int value) { | |
| 6766 if (value == min_jint) {subl(reg, value) ; return; } | |
| 6767 if (value < 0) { incrementl(reg, -value); return; } | |
| 6768 if (value == 0) { ; return; } | |
| 6769 if (value == 1 && UseIncDec) { decl(reg) ; return; } | |
| 6770 /* else */ { subl(reg, value) ; return; } | |
| 6771 } | |
| 6772 | |
| 6773 void MacroAssembler::decrementl(Address dst, int value) { | |
| 6774 if (value == min_jint) {subl(dst, value) ; return; } | |
| 6775 if (value < 0) { incrementl(dst, -value); return; } | |
| 6776 if (value == 0) { ; return; } | |
| 6777 if (value == 1 && UseIncDec) { decl(dst) ; return; } | |
| 6778 /* else */ { subl(dst, value) ; return; } | |
| 6779 } | |
| 6780 | |
| 6781 void MacroAssembler::division_with_shift (Register reg, int shift_value) { | |
| 6782 assert (shift_value > 0, "illegal shift value"); | |
| 6783 Label _is_positive; | |
| 6784 testl (reg, reg); | |
| 6785 jcc (Assembler::positive, _is_positive); | |
| 6786 int offset = (1 << shift_value) - 1 ; | |
| 6787 | |
| 6788 if (offset == 1) { | |
| 6789 incrementl(reg); | |
| 6790 } else { | |
| 6791 addl(reg, offset); | |
| 6792 } | |
| 6793 | |
| 6794 bind (_is_positive); | |
| 6795 sarl(reg, shift_value); | |
| 6796 } | |
| 6797 | |
| 4759 | 6798 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) { |
| 6799 if (reachable(src)) { | |
| 6800 Assembler::divsd(dst, as_Address(src)); | |
| 6801 } else { | |
| 6802 lea(rscratch1, src); | |
| 6803 Assembler::divsd(dst, Address(rscratch1, 0)); | |
| 6804 } | |
| 6805 } | |
| 6806 | |
| 6807 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) { | |
| 6808 if (reachable(src)) { | |
| 6809 Assembler::divss(dst, as_Address(src)); | |
| 6810 } else { | |
| 6811 lea(rscratch1, src); | |
| 6812 Assembler::divss(dst, Address(rscratch1, 0)); | |
| 6813 } | |
| 6814 } | |
| 6815 | |
| 304 | 6816 // !defined(COMPILER2) is because of stupid core builds |
| 6817 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) | |
| 6818 void MacroAssembler::empty_FPU_stack() { | |
| 6819 if (VM_Version::supports_mmx()) { | |
| 6820 emms(); | |
| 6821 } else { | |
| 6822 for (int i = 8; i-- > 0; ) ffree(i); | |
| 6823 } | |
| 6824 } | |
| 6825 #endif // !LP64 || C1 || !C2 | |
| 6826 | |
| 6827 | |
| 6828 // Defines obj, preserves var_size_in_bytes | |
| 6829 void MacroAssembler::eden_allocate(Register obj, | |
| 6830 Register var_size_in_bytes, | |
| 6831 int con_size_in_bytes, | |
| 6832 Register t1, | |
| 6833 Label& slow_case) { | |
| 6834 assert(obj == rax, "obj must be in rax, for cmpxchg"); | |
| 6835 assert_different_registers(obj, var_size_in_bytes, t1); | |
| 362 | 6836 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { |
| 6837 jmp(slow_case); | |
| 304 | 6838 } else { |
| 362 | 6839 Register end = t1; |
| 6840 Label retry; | |
| 6841 bind(retry); | |
| 6842 ExternalAddress heap_top((address) Universe::heap()->top_addr()); | |
| 6843 movptr(obj, heap_top); | |
| 6844 if (var_size_in_bytes == noreg) { | |
| 6845 lea(end, Address(obj, con_size_in_bytes)); | |
| 6846 } else { | |
| 6847 lea(end, Address(obj, var_size_in_bytes, Address::times_1)); | |
| 6848 } | |
| 6849 // if end < obj then we wrapped around => object too long => slow case | |
| 6850 cmpptr(end, obj); | |
| 6851 jcc(Assembler::below, slow_case); | |
| 6852 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr())); | |
| 6853 jcc(Assembler::above, slow_case); | |
| 6854 // Compare obj with the top addr, and if still equal, store the new top addr in | |
| 6855 // end at the address of the top addr pointer. Sets ZF if was equal, and clears | |
| 6856 // it otherwise. Use lock prefix for atomicity on MPs. | |
| 6857 locked_cmpxchgptr(end, heap_top); | |
| 6858 jcc(Assembler::notEqual, retry); | |
| 6859 } | |
| 304 | 6860 } |
| 6861 | |
| 6862 void MacroAssembler::enter() { | |
| 6863 push(rbp); | |
| 6864 mov(rbp, rsp); | |
| 6865 } | |
| 0 | 6866 |
|
4947
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
6867 // A 5 byte nop that is safe for patching (see patch_verified_entry) |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
6868 void MacroAssembler::fat_nop() { |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
6869 if (UseAddressNop) { |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
6870 addr_nop_5(); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
6871 } else { |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
6872 emit_byte(0x26); // es: |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
6873 emit_byte(0x2e); // cs: |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
6874 emit_byte(0x64); // fs: |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
6875 emit_byte(0x65); // gs: |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
6876 emit_byte(0x90); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
6877 } |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
6878 } |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
6879 |
| 0 | 6880 void MacroAssembler::fcmp(Register tmp) { |
| 6881 fcmp(tmp, 1, true, true); | |
| 6882 } | |
| 6883 | |
| 6884 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) { | |
| 6885 assert(!pop_right || pop_left, "usage error"); | |
| 6886 if (VM_Version::supports_cmov()) { | |
| 6887 assert(tmp == noreg, "unneeded temp"); | |
| 6888 if (pop_left) { | |
| 6889 fucomip(index); | |
| 6890 } else { | |
| 6891 fucomi(index); | |
| 6892 } | |
| 6893 if (pop_right) { | |
| 6894 fpop(); | |
| 6895 } | |
| 6896 } else { | |
| 6897 assert(tmp != noreg, "need temp"); | |
| 6898 if (pop_left) { | |
| 6899 if (pop_right) { | |
| 6900 fcompp(); | |
| 6901 } else { | |
| 6902 fcomp(index); | |
| 6903 } | |
| 6904 } else { | |
| 6905 fcom(index); | |
| 6906 } | |
| 6907 // convert FPU condition into eflags condition via rax, | |
| 6908 save_rax(tmp); | |
| 6909 fwait(); fnstsw_ax(); | |
| 6910 sahf(); | |
| 6911 restore_rax(tmp); | |
| 6912 } | |
| 6913 // condition codes set as follows: | |
| 6914 // | |
| 6915 // CF (corresponds to C0) if x < y | |
| 6916 // PF (corresponds to C2) if unordered | |
| 6917 // ZF (corresponds to C3) if x = y | |
| 6918 } | |
| 6919 | |
| 6920 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) { | |
| 6921 fcmp2int(dst, unordered_is_less, 1, true, true); | |
| 6922 } | |
| 6923 | |
| 6924 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) { | |
| 6925 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right); | |
| 6926 Label L; | |
| 6927 if (unordered_is_less) { | |
| 6928 movl(dst, -1); | |
| 6929 jcc(Assembler::parity, L); | |
| 6930 jcc(Assembler::below , L); | |
| 6931 movl(dst, 0); | |
| 6932 jcc(Assembler::equal , L); | |
| 6933 increment(dst); | |
| 6934 } else { // unordered is greater | |
| 6935 movl(dst, 1); | |
| 6936 jcc(Assembler::parity, L); | |
| 6937 jcc(Assembler::above , L); | |
| 6938 movl(dst, 0); | |
| 6939 jcc(Assembler::equal , L); | |
| 304 | 6940 decrementl(dst); |
| 0 | 6941 } |
| 6942 bind(L); | |
| 6943 } | |
| 6944 | |
| 304 | 6945 void MacroAssembler::fld_d(AddressLiteral src) { |
| 6946 fld_d(as_Address(src)); | |
| 6947 } | |
| 6948 | |
| 6949 void MacroAssembler::fld_s(AddressLiteral src) { | |
| 6950 fld_s(as_Address(src)); | |
| 6951 } | |
| 6952 | |
| 6953 void MacroAssembler::fld_x(AddressLiteral src) { | |
| 6954 Assembler::fld_x(as_Address(src)); | |
| 6955 } | |
| 6956 | |
| 6957 void MacroAssembler::fldcw(AddressLiteral src) { | |
| 6958 Assembler::fldcw(as_Address(src)); | |
| 6959 } | |
| 0 | 6960 |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
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5984
diff
changeset
|
6961 void MacroAssembler::pow_exp_core_encoding() { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
6962 // kills rax, rcx, rdx |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
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5984
diff
changeset
|
6963 subptr(rsp,sizeof(jdouble)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
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parents:
5984
diff
changeset
|
6964 // computes 2^X. Stack: X ... |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
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parents:
5984
diff
changeset
|
6965 // f2xm1 computes 2^X-1 but only operates on -1<=X<=1. Get int(X) and |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
6966 // keep it on the thread's stack to compute 2^int(X) later |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
6967 // then compute 2^(X-int(X)) as (2^(X-int(X)-1+1) |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
6968 // final result is obtained with: 2^X = 2^int(X) * 2^(X-int(X)) |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
6969 fld_s(0); // Stack: X X ... |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
6970 frndint(); // Stack: int(X) X ... |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
6971 fsuba(1); // Stack: int(X) X-int(X) ... |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
6972 fistp_s(Address(rsp,0)); // move int(X) as integer to thread's stack. Stack: X-int(X) ... |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
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5984
diff
changeset
|
6973 f2xm1(); // Stack: 2^(X-int(X))-1 ... |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
6974 fld1(); // Stack: 1 2^(X-int(X))-1 ... |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
6975 faddp(1); // Stack: 2^(X-int(X)) |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
6976 // computes 2^(int(X)): add exponent bias (1023) to int(X), then |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
6977 // shift int(X)+1023 to exponent position. |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
6978 // Exponent is limited to 11 bits if int(X)+1023 does not fit in 11 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
6979 // bits, set result to NaN. 0x000 and 0x7FF are reserved exponent |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
6980 // values so detect them and set result to NaN. |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
6981 movl(rax,Address(rsp,0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
6982 movl(rcx, -2048); // 11 bit mask and valid NaN binary encoding |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
6983 addl(rax, 1023); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
6984 movl(rdx,rax); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
6985 shll(rax,20); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
6986 // Check that 0 < int(X)+1023 < 2047. Otherwise set rax to NaN. |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
6987 addl(rdx,1); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
6988 // Check that 1 < int(X)+1023+1 < 2048 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
6989 // in 3 steps: |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
6990 // 1- (int(X)+1023+1)&-2048 == 0 => 0 <= int(X)+1023+1 < 2048 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
6991 // 2- (int(X)+1023+1)&-2048 != 0 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
6992 // 3- (int(X)+1023+1)&-2048 != 1 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
6993 // Do 2- first because addl just updated the flags. |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
6994 cmov32(Assembler::equal,rax,rcx); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
6995 cmpl(rdx,1); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
6996 cmov32(Assembler::equal,rax,rcx); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
6997 testl(rdx,rcx); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
6998 cmov32(Assembler::notEqual,rax,rcx); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
6999 movl(Address(rsp,4),rax); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7000 movl(Address(rsp,0),0); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7001 fmul_d(Address(rsp,0)); // Stack: 2^X ... |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7002 addptr(rsp,sizeof(jdouble)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7003 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7004 |
|
6141
e7715c222897
7174532: jdk/test/java/lang/Math/WorstCaseTests.java failing on x86
roland
parents:
6087
diff
changeset
|
7005 void MacroAssembler::increase_precision() { |
|
e7715c222897
7174532: jdk/test/java/lang/Math/WorstCaseTests.java failing on x86
roland
parents:
6087
diff
changeset
|
7006 subptr(rsp, BytesPerWord); |
|
e7715c222897
7174532: jdk/test/java/lang/Math/WorstCaseTests.java failing on x86
roland
parents:
6087
diff
changeset
|
7007 fnstcw(Address(rsp, 0)); |
|
e7715c222897
7174532: jdk/test/java/lang/Math/WorstCaseTests.java failing on x86
roland
parents:
6087
diff
changeset
|
7008 movl(rax, Address(rsp, 0)); |
|
e7715c222897
7174532: jdk/test/java/lang/Math/WorstCaseTests.java failing on x86
roland
parents:
6087
diff
changeset
|
7009 orl(rax, 0x300); |
|
e7715c222897
7174532: jdk/test/java/lang/Math/WorstCaseTests.java failing on x86
roland
parents:
6087
diff
changeset
|
7010 push(rax); |
|
e7715c222897
7174532: jdk/test/java/lang/Math/WorstCaseTests.java failing on x86
roland
parents:
6087
diff
changeset
|
7011 fldcw(Address(rsp, 0)); |
|
e7715c222897
7174532: jdk/test/java/lang/Math/WorstCaseTests.java failing on x86
roland
parents:
6087
diff
changeset
|
7012 pop(rax); |
|
e7715c222897
7174532: jdk/test/java/lang/Math/WorstCaseTests.java failing on x86
roland
parents:
6087
diff
changeset
|
7013 } |
|
e7715c222897
7174532: jdk/test/java/lang/Math/WorstCaseTests.java failing on x86
roland
parents:
6087
diff
changeset
|
7014 |
|
e7715c222897
7174532: jdk/test/java/lang/Math/WorstCaseTests.java failing on x86
roland
parents:
6087
diff
changeset
|
7015 void MacroAssembler::restore_precision() { |
|
e7715c222897
7174532: jdk/test/java/lang/Math/WorstCaseTests.java failing on x86
roland
parents:
6087
diff
changeset
|
7016 fldcw(Address(rsp, 0)); |
|
e7715c222897
7174532: jdk/test/java/lang/Math/WorstCaseTests.java failing on x86
roland
parents:
6087
diff
changeset
|
7017 addptr(rsp, BytesPerWord); |
|
e7715c222897
7174532: jdk/test/java/lang/Math/WorstCaseTests.java failing on x86
roland
parents:
6087
diff
changeset
|
7018 } |
|
e7715c222897
7174532: jdk/test/java/lang/Math/WorstCaseTests.java failing on x86
roland
parents:
6087
diff
changeset
|
7019 |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7020 void MacroAssembler::fast_pow() { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7021 // computes X^Y = 2^(Y * log2(X)) |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7022 // if fast computation is not possible, result is NaN. Requires |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7023 // fallback from user of this macro. |
|
6141
e7715c222897
7174532: jdk/test/java/lang/Math/WorstCaseTests.java failing on x86
roland
parents:
6087
diff
changeset
|
7024 // increase precision for intermediate steps of the computation |
|
e7715c222897
7174532: jdk/test/java/lang/Math/WorstCaseTests.java failing on x86
roland
parents:
6087
diff
changeset
|
7025 increase_precision(); |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7026 fyl2x(); // Stack: (Y*log2(X)) ... |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7027 pow_exp_core_encoding(); // Stack: exp(X) ... |
|
6141
e7715c222897
7174532: jdk/test/java/lang/Math/WorstCaseTests.java failing on x86
roland
parents:
6087
diff
changeset
|
7028 restore_precision(); |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7029 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7030 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7031 void MacroAssembler::fast_exp() { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7032 // computes exp(X) = 2^(X * log2(e)) |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7033 // if fast computation is not possible, result is NaN. Requires |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7034 // fallback from user of this macro. |
|
6141
e7715c222897
7174532: jdk/test/java/lang/Math/WorstCaseTests.java failing on x86
roland
parents:
6087
diff
changeset
|
7035 // increase precision for intermediate steps of the computation |
|
e7715c222897
7174532: jdk/test/java/lang/Math/WorstCaseTests.java failing on x86
roland
parents:
6087
diff
changeset
|
7036 increase_precision(); |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7037 fldl2e(); // Stack: log2(e) X ... |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7038 fmulp(1); // Stack: (X*log2(e)) ... |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7039 pow_exp_core_encoding(); // Stack: exp(X) ... |
|
6141
e7715c222897
7174532: jdk/test/java/lang/Math/WorstCaseTests.java failing on x86
roland
parents:
6087
diff
changeset
|
7040 restore_precision(); |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7041 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7042 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7043 void MacroAssembler::pow_or_exp(bool is_exp, int num_fpu_regs_in_use) { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7044 // kills rax, rcx, rdx |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7045 // pow and exp needs 2 extra registers on the fpu stack. |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7046 Label slow_case, done; |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7047 Register tmp = noreg; |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7048 if (!VM_Version::supports_cmov()) { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7049 // fcmp needs a temporary so preserve rdx, |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7050 tmp = rdx; |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7051 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7052 Register tmp2 = rax; |
|
6087
e2961d14584b
7169934: pow(x,y) or x64 computes incorrect result when x<0 and y is an odd integer
roland
parents:
6084
diff
changeset
|
7053 Register tmp3 = rcx; |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7054 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7055 if (is_exp) { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7056 // Stack: X |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7057 fld_s(0); // duplicate argument for runtime call. Stack: X X |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7058 fast_exp(); // Stack: exp(X) X |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7059 fcmp(tmp, 0, false, false); // Stack: exp(X) X |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7060 // exp(X) not equal to itself: exp(X) is NaN go to slow case. |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7061 jcc(Assembler::parity, slow_case); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7062 // get rid of duplicate argument. Stack: exp(X) |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7063 if (num_fpu_regs_in_use > 0) { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7064 fxch(); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7065 fpop(); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7066 } else { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7067 ffree(1); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7068 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7069 jmp(done); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7070 } else { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7071 // Stack: X Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7072 Label x_negative, y_odd; |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7073 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7074 fldz(); // Stack: 0 X Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7075 fcmp(tmp, 1, true, false); // Stack: X Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7076 jcc(Assembler::above, x_negative); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7077 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7078 // X >= 0 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7079 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7080 fld_s(1); // duplicate arguments for runtime call. Stack: Y X Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7081 fld_s(1); // Stack: X Y X Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7082 fast_pow(); // Stack: X^Y X Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7083 fcmp(tmp, 0, false, false); // Stack: X^Y X Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7084 // X^Y not equal to itself: X^Y is NaN go to slow case. |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7085 jcc(Assembler::parity, slow_case); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7086 // get rid of duplicate arguments. Stack: X^Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
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|
7087 if (num_fpu_regs_in_use > 0) { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7088 fxch(); fpop(); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7089 fxch(); fpop(); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7090 } else { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7091 ffree(2); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7092 ffree(1); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7093 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7094 jmp(done); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7095 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7096 // X <= 0 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7097 bind(x_negative); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7098 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7099 fld_s(1); // Stack: Y X Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7100 frndint(); // Stack: int(Y) X Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7101 fcmp(tmp, 2, false, false); // Stack: int(Y) X Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7102 jcc(Assembler::notEqual, slow_case); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7103 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7104 subptr(rsp, 8); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7105 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7106 // For X^Y, when X < 0, Y has to be an integer and the final |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7107 // result depends on whether it's odd or even. We just checked |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7108 // that int(Y) == Y. We move int(Y) to gp registers as a 64 bit |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7109 // integer to test its parity. If int(Y) is huge and doesn't fit |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7110 // in the 64 bit integer range, the integer indefinite value will |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7111 // end up in the gp registers. Huge numbers are all even, the |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7112 // integer indefinite number is even so it's fine. |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7113 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7114 #ifdef ASSERT |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7115 // Let's check we don't end up with an integer indefinite number |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7116 // when not expected. First test for huge numbers: check whether |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7117 // int(Y)+1 == int(Y) which is true for very large numbers and |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7118 // those are all even. A 64 bit integer is guaranteed to not |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7119 // overflow for numbers where y+1 != y (when precision is set to |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7120 // double precision). |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7121 Label y_not_huge; |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7122 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7123 fld1(); // Stack: 1 int(Y) X Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7124 fadd(1); // Stack: 1+int(Y) int(Y) X Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7125 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7126 #ifdef _LP64 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7127 // trip to memory to force the precision down from double extended |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7128 // precision |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7129 fstp_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7130 fld_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7131 #endif |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7132 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7133 fcmp(tmp, 1, true, false); // Stack: int(Y) X Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7134 #endif |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7135 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7136 // move int(Y) as 64 bit integer to thread's stack |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7137 fistp_d(Address(rsp,0)); // Stack: X Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7138 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7139 #ifdef ASSERT |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7140 jcc(Assembler::notEqual, y_not_huge); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7141 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7142 // Y is huge so we know it's even. It may not fit in a 64 bit |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7143 // integer and we don't want the debug code below to see the |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7144 // integer indefinite value so overwrite int(Y) on the thread's |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7145 // stack with 0. |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7146 movl(Address(rsp, 0), 0); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7147 movl(Address(rsp, 4), 0); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7148 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7149 bind(y_not_huge); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7150 #endif |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7151 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7152 fld_s(1); // duplicate arguments for runtime call. Stack: Y X Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7153 fld_s(1); // Stack: X Y X Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7154 fabs(); // Stack: abs(X) Y X Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7155 fast_pow(); // Stack: abs(X)^Y X Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7156 fcmp(tmp, 0, false, false); // Stack: abs(X)^Y X Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7157 // abs(X)^Y not equal to itself: abs(X)^Y is NaN go to slow case. |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7158 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7159 pop(tmp2); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7160 NOT_LP64(pop(tmp3)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7161 jcc(Assembler::parity, slow_case); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7162 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7163 #ifdef ASSERT |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7164 // Check that int(Y) is not integer indefinite value (int |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7165 // overflow). Shouldn't happen because for values that would |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7166 // overflow, 1+int(Y)==Y which was tested earlier. |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7167 #ifndef _LP64 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7168 { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7169 Label integer; |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7170 testl(tmp2, tmp2); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7171 jcc(Assembler::notZero, integer); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7172 cmpl(tmp3, 0x80000000); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7173 jcc(Assembler::notZero, integer); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7174 stop("integer indefinite value shouldn't be seen here"); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7175 bind(integer); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7176 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7177 #else |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7178 { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7179 Label integer; |
|
6087
e2961d14584b
7169934: pow(x,y) or x64 computes incorrect result when x<0 and y is an odd integer
roland
parents:
6084
diff
changeset
|
7180 mov(tmp3, tmp2); // preserve tmp2 for parity check below |
|
e2961d14584b
7169934: pow(x,y) or x64 computes incorrect result when x<0 and y is an odd integer
roland
parents:
6084
diff
changeset
|
7181 shlq(tmp3, 1); |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7182 jcc(Assembler::carryClear, integer); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7183 jcc(Assembler::notZero, integer); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7184 stop("integer indefinite value shouldn't be seen here"); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7185 bind(integer); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7186 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7187 #endif |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7188 #endif |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7189 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7190 // get rid of duplicate arguments. Stack: X^Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7191 if (num_fpu_regs_in_use > 0) { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7192 fxch(); fpop(); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7193 fxch(); fpop(); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7194 } else { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7195 ffree(2); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7196 ffree(1); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7197 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7198 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7199 testl(tmp2, 1); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7200 jcc(Assembler::zero, done); // X <= 0, Y even: X^Y = abs(X)^Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7201 // X <= 0, Y even: X^Y = -abs(X)^Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7202 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7203 fchs(); // Stack: -abs(X)^Y Y |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7204 jmp(done); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7205 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7206 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
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5984
diff
changeset
|
7207 // slow case: runtime call |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
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diff
changeset
|
7208 bind(slow_case); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
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5984
diff
changeset
|
7209 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
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5984
diff
changeset
|
7210 fpop(); // pop incorrect result or int(Y) |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7211 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
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5984
diff
changeset
|
7212 fp_runtime_fallback(is_exp ? CAST_FROM_FN_PTR(address, SharedRuntime::dexp) : CAST_FROM_FN_PTR(address, SharedRuntime::dpow), |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
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5984
diff
changeset
|
7213 is_exp ? 1 : 2, num_fpu_regs_in_use); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7214 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
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5984
diff
changeset
|
7215 // Come here with result in F-TOS |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
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parents:
5984
diff
changeset
|
7216 bind(done); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
7217 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
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5984
diff
changeset
|
7218 |
| 0 | 7219 void MacroAssembler::fpop() { |
| 7220 ffree(); | |
| 7221 fincstp(); | |
| 7222 } | |
| 7223 | |
| 304 | 7224 void MacroAssembler::fremr(Register tmp) { |
| 7225 save_rax(tmp); | |
| 7226 { Label L; | |
| 7227 bind(L); | |
| 7228 fprem(); | |
| 7229 fwait(); fnstsw_ax(); | |
| 7230 #ifdef _LP64 | |
| 7231 testl(rax, 0x400); | |
| 7232 jcc(Assembler::notEqual, L); | |
| 7233 #else | |
| 7234 sahf(); | |
| 7235 jcc(Assembler::parity, L); | |
| 7236 #endif // _LP64 | |
| 7237 } | |
| 7238 restore_rax(tmp); | |
| 7239 // Result is in ST0. | |
| 7240 // Note: fxch & fpop to get rid of ST1 | |
| 7241 // (otherwise FPU stack could overflow eventually) | |
| 7242 fxch(1); | |
| 7243 fpop(); | |
| 7244 } | |
| 7245 | |
| 7246 | |
| 7247 void MacroAssembler::incrementl(AddressLiteral dst) { | |
| 7248 if (reachable(dst)) { | |
| 7249 incrementl(as_Address(dst)); | |
| 0 | 7250 } else { |
| 304 | 7251 lea(rscratch1, dst); |
| 7252 incrementl(Address(rscratch1, 0)); | |
| 7253 } | |
| 7254 } | |
| 7255 | |
| 7256 void MacroAssembler::incrementl(ArrayAddress dst) { | |
| 7257 incrementl(as_Address(dst)); | |
| 7258 } | |
| 7259 | |
| 7260 void MacroAssembler::incrementl(Register reg, int value) { | |
| 7261 if (value == min_jint) {addl(reg, value) ; return; } | |
| 7262 if (value < 0) { decrementl(reg, -value); return; } | |
| 7263 if (value == 0) { ; return; } | |
| 7264 if (value == 1 && UseIncDec) { incl(reg) ; return; } | |
| 7265 /* else */ { addl(reg, value) ; return; } | |
| 7266 } | |
| 7267 | |
| 7268 void MacroAssembler::incrementl(Address dst, int value) { | |
| 7269 if (value == min_jint) {addl(dst, value) ; return; } | |
| 7270 if (value < 0) { decrementl(dst, -value); return; } | |
| 7271 if (value == 0) { ; return; } | |
| 7272 if (value == 1 && UseIncDec) { incl(dst) ; return; } | |
| 7273 /* else */ { addl(dst, value) ; return; } | |
| 7274 } | |
| 7275 | |
| 7276 void MacroAssembler::jump(AddressLiteral dst) { | |
| 7277 if (reachable(dst)) { | |
| 7278 jmp_literal(dst.target(), dst.rspec()); | |
| 7279 } else { | |
| 7280 lea(rscratch1, dst); | |
| 7281 jmp(rscratch1); | |
| 7282 } | |
| 7283 } | |
| 7284 | |
| 7285 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) { | |
| 7286 if (reachable(dst)) { | |
| 7287 InstructionMark im(this); | |
| 7288 relocate(dst.reloc()); | |
| 7289 const int short_size = 2; | |
| 7290 const int long_size = 6; | |
| 7291 int offs = (intptr_t)dst.target() - ((intptr_t)_code_pos); | |
| 7292 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) { | |
| 7293 // 0111 tttn #8-bit disp | |
| 7294 emit_byte(0x70 | cc); | |
| 7295 emit_byte((offs - short_size) & 0xFF); | |
| 7296 } else { | |
| 7297 // 0000 1111 1000 tttn #32-bit disp | |
| 7298 emit_byte(0x0F); | |
| 7299 emit_byte(0x80 | cc); | |
| 7300 emit_long(offs - long_size); | |
| 7301 } | |
| 0 | 7302 } else { |
| 304 | 7303 #ifdef ASSERT |
| 7304 warning("reversing conditional branch"); | |
| 7305 #endif /* ASSERT */ | |
| 7306 Label skip; | |
| 7307 jccb(reverse[cc], skip); | |
| 7308 lea(rscratch1, dst); | |
| 7309 Assembler::jmp(rscratch1); | |
| 7310 bind(skip); | |
| 7311 } | |
| 7312 } | |
| 7313 | |
| 7314 void MacroAssembler::ldmxcsr(AddressLiteral src) { | |
| 7315 if (reachable(src)) { | |
| 7316 Assembler::ldmxcsr(as_Address(src)); | |
| 7317 } else { | |
| 7318 lea(rscratch1, src); | |
| 7319 Assembler::ldmxcsr(Address(rscratch1, 0)); | |
| 7320 } | |
| 7321 } | |
| 7322 | |
| 7323 int MacroAssembler::load_signed_byte(Register dst, Address src) { | |
| 7324 int off; | |
| 7325 if (LP64_ONLY(true ||) VM_Version::is_P6()) { | |
| 7326 off = offset(); | |
| 7327 movsbl(dst, src); // movsxb | |
| 7328 } else { | |
| 7329 off = load_unsigned_byte(dst, src); | |
| 7330 shll(dst, 24); | |
| 7331 sarl(dst, 24); | |
| 7332 } | |
| 7333 return off; | |
| 7334 } | |
| 7335 | |
|
622
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6812678: macro assembler needs delayed binding of a few constants (for 6655638)
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606
diff
changeset
|
7336 // Note: load_signed_short used to be called load_signed_word. |
|
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606
diff
changeset
|
7337 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler |
|
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6812678: macro assembler needs delayed binding of a few constants (for 6655638)
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606
diff
changeset
|
7338 // manual, which means 16 bits, that usage is found nowhere in HotSpot code. |
|
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6812678: macro assembler needs delayed binding of a few constants (for 6655638)
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606
diff
changeset
|
7339 // The term "word" in HotSpot means a 32- or 64-bit machine word. |
|
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
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606
diff
changeset
|
7340 int MacroAssembler::load_signed_short(Register dst, Address src) { |
| 304 | 7341 int off; |
| 7342 if (LP64_ONLY(true ||) VM_Version::is_P6()) { | |
| 7343 // This is dubious to me since it seems safe to do a signed 16 => 64 bit | |
| 7344 // version but this is what 64bit has always done. This seems to imply | |
| 7345 // that users are only using 32bits worth. | |
| 7346 off = offset(); | |
| 7347 movswl(dst, src); // movsxw | |
| 7348 } else { | |
|
622
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6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
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606
diff
changeset
|
7349 off = load_unsigned_short(dst, src); |
| 304 | 7350 shll(dst, 16); |
| 7351 sarl(dst, 16); | |
| 7352 } | |
| 7353 return off; | |
| 7354 } | |
| 7355 | |
| 7356 int MacroAssembler::load_unsigned_byte(Register dst, Address src) { | |
| 7357 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, | |
| 7358 // and "3.9 Partial Register Penalties", p. 22). | |
| 7359 int off; | |
| 7360 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) { | |
| 7361 off = offset(); | |
| 7362 movzbl(dst, src); // movzxb | |
| 7363 } else { | |
| 7364 xorl(dst, dst); | |
| 7365 off = offset(); | |
| 7366 movb(dst, src); | |
| 7367 } | |
| 7368 return off; | |
| 7369 } | |
| 7370 | |
|
622
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
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606
diff
changeset
|
7371 // Note: load_unsigned_short used to be called load_unsigned_word. |
|
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jrose
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606
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changeset
|
7372 int MacroAssembler::load_unsigned_short(Register dst, Address src) { |
| 304 | 7373 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, |
| 7374 // and "3.9 Partial Register Penalties", p. 22). | |
| 7375 int off; | |
| 7376 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) { | |
| 7377 off = offset(); | |
| 7378 movzwl(dst, src); // movzxw | |
| 7379 } else { | |
| 7380 xorl(dst, dst); | |
| 7381 off = offset(); | |
| 7382 movw(dst, src); | |
| 7383 } | |
| 7384 return off; | |
| 7385 } | |
| 7386 | |
|
2258
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
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2100
diff
changeset
|
7387 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) { |
| 1503 | 7388 switch (size_in_bytes) { |
|
622
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6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
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606
diff
changeset
|
7389 #ifndef _LP64 |
|
2258
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
7390 case 8: |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
7391 assert(dst2 != noreg, "second dest register required"); |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
7392 movl(dst, src); |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
7393 movl(dst2, src.plus_disp(BytesPerInt)); |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
7394 break; |
|
622
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
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606
diff
changeset
|
7395 #else |
|
2258
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
7396 case 8: movq(dst, src); break; |
|
622
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6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
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606
diff
changeset
|
7397 #endif |
|
2258
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
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2100
diff
changeset
|
7398 case 4: movl(dst, src); break; |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
7399 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break; |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
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2100
diff
changeset
|
7400 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break; |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
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2100
diff
changeset
|
7401 default: ShouldNotReachHere(); |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
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2100
diff
changeset
|
7402 } |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
7403 } |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
7404 |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
7405 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) { |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
7406 switch (size_in_bytes) { |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
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2100
diff
changeset
|
7407 #ifndef _LP64 |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
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2100
diff
changeset
|
7408 case 8: |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
7409 assert(src2 != noreg, "second source register required"); |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
7410 movl(dst, src); |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
7411 movl(dst.plus_disp(BytesPerInt), src2); |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
7412 break; |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
7413 #else |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
7414 case 8: movq(dst, src); break; |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
7415 #endif |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
7416 case 4: movl(dst, src); break; |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
7417 case 2: movw(dst, src); break; |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
7418 case 1: movb(dst, src); break; |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
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2100
diff
changeset
|
7419 default: ShouldNotReachHere(); |
|
622
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
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606
diff
changeset
|
7420 } |
|
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
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606
diff
changeset
|
7421 } |
|
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
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606
diff
changeset
|
7422 |
| 304 | 7423 void MacroAssembler::mov32(AddressLiteral dst, Register src) { |
| 7424 if (reachable(dst)) { | |
| 7425 movl(as_Address(dst), src); | |
| 7426 } else { | |
| 7427 lea(rscratch1, dst); | |
| 7428 movl(Address(rscratch1, 0), src); | |
| 7429 } | |
| 7430 } | |
| 7431 | |
| 7432 void MacroAssembler::mov32(Register dst, AddressLiteral src) { | |
| 7433 if (reachable(src)) { | |
| 7434 movl(dst, as_Address(src)); | |
| 7435 } else { | |
| 7436 lea(rscratch1, src); | |
| 7437 movl(dst, Address(rscratch1, 0)); | |
| 7438 } | |
| 0 | 7439 } |
| 7440 | |
| 7441 // C++ bool manipulation | |
| 7442 | |
| 7443 void MacroAssembler::movbool(Register dst, Address src) { | |
| 7444 if(sizeof(bool) == 1) | |
| 7445 movb(dst, src); | |
| 7446 else if(sizeof(bool) == 2) | |
| 7447 movw(dst, src); | |
| 7448 else if(sizeof(bool) == 4) | |
| 7449 movl(dst, src); | |
| 7450 else | |
| 7451 // unsupported | |
| 7452 ShouldNotReachHere(); | |
| 7453 } | |
| 7454 | |
| 7455 void MacroAssembler::movbool(Address dst, bool boolconst) { | |
| 7456 if(sizeof(bool) == 1) | |
| 7457 movb(dst, (int) boolconst); | |
| 7458 else if(sizeof(bool) == 2) | |
| 7459 movw(dst, (int) boolconst); | |
| 7460 else if(sizeof(bool) == 4) | |
| 7461 movl(dst, (int) boolconst); | |
| 7462 else | |
| 7463 // unsupported | |
| 7464 ShouldNotReachHere(); | |
| 7465 } | |
| 7466 | |
| 7467 void MacroAssembler::movbool(Address dst, Register src) { | |
| 7468 if(sizeof(bool) == 1) | |
| 7469 movb(dst, src); | |
| 7470 else if(sizeof(bool) == 2) | |
| 7471 movw(dst, src); | |
| 7472 else if(sizeof(bool) == 4) | |
| 7473 movl(dst, src); | |
| 7474 else | |
| 7475 // unsupported | |
| 7476 ShouldNotReachHere(); | |
| 7477 } | |
| 7478 | |
| 304 | 7479 void MacroAssembler::movbyte(ArrayAddress dst, int src) { |
| 7480 movb(as_Address(dst), src); | |
| 7481 } | |
| 7482 | |
| 7483 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) { | |
| 7484 if (reachable(src)) { | |
| 7485 if (UseXmmLoadAndClearUpper) { | |
| 7486 movsd (dst, as_Address(src)); | |
| 7487 } else { | |
| 7488 movlpd(dst, as_Address(src)); | |
| 7489 } | |
| 7490 } else { | |
| 7491 lea(rscratch1, src); | |
| 7492 if (UseXmmLoadAndClearUpper) { | |
| 7493 movsd (dst, Address(rscratch1, 0)); | |
| 7494 } else { | |
| 7495 movlpd(dst, Address(rscratch1, 0)); | |
| 7496 } | |
| 7497 } | |
| 7498 } | |
| 7499 | |
| 7500 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) { | |
| 7501 if (reachable(src)) { | |
| 7502 movss(dst, as_Address(src)); | |
| 7503 } else { | |
| 7504 lea(rscratch1, src); | |
| 7505 movss(dst, Address(rscratch1, 0)); | |
| 7506 } | |
| 7507 } | |
| 7508 | |
| 7509 void MacroAssembler::movptr(Register dst, Register src) { | |
| 7510 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
| 7511 } | |
| 7512 | |
| 7513 void MacroAssembler::movptr(Register dst, Address src) { | |
| 7514 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
| 7515 } | |
| 7516 | |
| 7517 // src should NEVER be a real pointer. Use AddressLiteral for true pointers | |
| 7518 void MacroAssembler::movptr(Register dst, intptr_t src) { | |
| 7519 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src)); | |
| 7520 } | |
| 7521 | |
| 7522 void MacroAssembler::movptr(Address dst, Register src) { | |
| 7523 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
| 7524 } | |
| 7525 | |
| 4759 | 7526 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) { |
| 7527 if (reachable(src)) { | |
| 7528 Assembler::movsd(dst, as_Address(src)); | |
| 7529 } else { | |
| 7530 lea(rscratch1, src); | |
| 7531 Assembler::movsd(dst, Address(rscratch1, 0)); | |
| 7532 } | |
| 7533 } | |
| 7534 | |
| 304 | 7535 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) { |
| 7536 if (reachable(src)) { | |
| 4759 | 7537 Assembler::movss(dst, as_Address(src)); |
| 304 | 7538 } else { |
| 7539 lea(rscratch1, src); | |
| 4759 | 7540 Assembler::movss(dst, Address(rscratch1, 0)); |
| 7541 } | |
| 7542 } | |
| 7543 | |
| 7544 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) { | |
| 7545 if (reachable(src)) { | |
| 7546 Assembler::mulsd(dst, as_Address(src)); | |
| 7547 } else { | |
| 7548 lea(rscratch1, src); | |
| 7549 Assembler::mulsd(dst, Address(rscratch1, 0)); | |
| 7550 } | |
| 7551 } | |
| 7552 | |
| 7553 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) { | |
| 7554 if (reachable(src)) { | |
| 7555 Assembler::mulss(dst, as_Address(src)); | |
| 7556 } else { | |
| 7557 lea(rscratch1, src); | |
| 7558 Assembler::mulss(dst, Address(rscratch1, 0)); | |
| 304 | 7559 } |
| 7560 } | |
| 7561 | |
| 7562 void MacroAssembler::null_check(Register reg, int offset) { | |
| 7563 if (needs_explicit_null_check(offset)) { | |
| 7564 // provoke OS NULL exception if reg = NULL by | |
| 7565 // accessing M[reg] w/o changing any (non-CC) registers | |
| 7566 // NOTE: cmpl is plenty here to provoke a segv | |
| 7567 cmpptr(rax, Address(reg, 0)); | |
| 7568 // Note: should probably use testl(rax, Address(reg, 0)); | |
| 7569 // may be shorter code (however, this version of | |
| 7570 // testl needs to be implemented first) | |
| 7571 } else { | |
| 7572 // nothing to do, (later) access of M[reg + offset] | |
| 7573 // will provoke OS NULL exception if reg = NULL | |
| 7574 } | |
| 7575 } | |
| 7576 | |
| 7577 void MacroAssembler::os_breakpoint() { | |
| 7578 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability | |
| 7579 // (e.g., MSVC can't call ps() otherwise) | |
| 7580 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint))); | |
| 7581 } | |
| 7582 | |
| 7583 void MacroAssembler::pop_CPU_state() { | |
| 7584 pop_FPU_state(); | |
| 7585 pop_IU_state(); | |
| 7586 } | |
| 7587 | |
| 7588 void MacroAssembler::pop_FPU_state() { | |
| 7589 NOT_LP64(frstor(Address(rsp, 0));) | |
| 7590 LP64_ONLY(fxrstor(Address(rsp, 0));) | |
| 7591 addptr(rsp, FPUStateSizeInWords * wordSize); | |
| 7592 } | |
| 7593 | |
| 7594 void MacroAssembler::pop_IU_state() { | |
| 7595 popa(); | |
| 7596 LP64_ONLY(addq(rsp, 8)); | |
| 7597 popf(); | |
| 7598 } | |
| 7599 | |
| 7600 // Save Integer and Float state | |
| 7601 // Warning: Stack must be 16 byte aligned (64bit) | |
| 7602 void MacroAssembler::push_CPU_state() { | |
| 7603 push_IU_state(); | |
| 7604 push_FPU_state(); | |
| 7605 } | |
| 7606 | |
| 7607 void MacroAssembler::push_FPU_state() { | |
| 7608 subptr(rsp, FPUStateSizeInWords * wordSize); | |
| 7609 #ifndef _LP64 | |
| 7610 fnsave(Address(rsp, 0)); | |
| 7611 fwait(); | |
| 7612 #else | |
| 7613 fxsave(Address(rsp, 0)); | |
| 7614 #endif // LP64 | |
| 7615 } | |
| 7616 | |
| 7617 void MacroAssembler::push_IU_state() { | |
| 7618 // Push flags first because pusha kills them | |
| 7619 pushf(); | |
| 7620 // Make sure rsp stays 16-byte aligned | |
| 7621 LP64_ONLY(subq(rsp, 8)); | |
| 7622 pusha(); | |
| 7623 } | |
| 7624 | |
| 7625 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) { | |
| 7626 // determine java_thread register | |
| 7627 if (!java_thread->is_valid()) { | |
| 7628 java_thread = rdi; | |
| 7629 get_thread(java_thread); | |
| 7630 } | |
| 7631 // we must set sp to zero to clear frame | |
|
512
db4caa99ef11
6787106: Hotspot 32 bit build fails on platforms having different definitions for intptr_t & int32_t
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420
diff
changeset
|
7632 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); |
| 304 | 7633 if (clear_fp) { |
|
512
db4caa99ef11
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diff
changeset
|
7634 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); |
| 304 | 7635 } |
| 7636 | |
| 7637 if (clear_pc) | |
|
512
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diff
changeset
|
7638 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); |
| 304 | 7639 |
| 7640 } | |
| 7641 | |
| 7642 void MacroAssembler::restore_rax(Register tmp) { | |
| 7643 if (tmp == noreg) pop(rax); | |
| 7644 else if (tmp != rax) mov(rax, tmp); | |
| 7645 } | |
| 7646 | |
| 7647 void MacroAssembler::round_to(Register reg, int modulus) { | |
| 7648 addptr(reg, modulus - 1); | |
| 7649 andptr(reg, -modulus); | |
| 7650 } | |
| 7651 | |
| 7652 void MacroAssembler::save_rax(Register tmp) { | |
| 7653 if (tmp == noreg) push(rax); | |
| 7654 else if (tmp != rax) mov(tmp, rax); | |
| 7655 } | |
| 7656 | |
| 7657 // Write serialization page so VM thread can do a pseudo remote membar. | |
| 7658 // We use the current thread pointer to calculate a thread specific | |
| 7659 // offset to write to within the page. This minimizes bus traffic | |
| 7660 // due to cache line collision. | |
| 7661 void MacroAssembler::serialize_memory(Register thread, Register tmp) { | |
| 7662 movl(tmp, thread); | |
| 7663 shrl(tmp, os::get_serialize_page_shift_count()); | |
| 7664 andl(tmp, (os::vm_page_size() - sizeof(int))); | |
| 7665 | |
| 7666 Address index(noreg, tmp, Address::times_1); | |
| 7667 ExternalAddress page(os::get_memory_serialize_page()); | |
| 7668 | |
|
606
19962e74284f
6811384: MacroAssembler::serialize_memory may touch next page on amd64
never
parents:
520
diff
changeset
|
7669 // Size of store must match masking code above |
|
19962e74284f
6811384: MacroAssembler::serialize_memory may touch next page on amd64
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diff
changeset
|
7670 movl(as_Address(ArrayAddress(page, index)), tmp); |
| 304 | 7671 } |
| 7672 | |
| 7673 // Calls to C land | |
| 7674 // | |
| 7675 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded | |
| 7676 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp | |
| 7677 // has to be reset to 0. This is required to allow proper stack traversal. | |
| 7678 void MacroAssembler::set_last_Java_frame(Register java_thread, | |
| 7679 Register last_java_sp, | |
| 7680 Register last_java_fp, | |
| 7681 address last_java_pc) { | |
| 7682 // determine java_thread register | |
| 7683 if (!java_thread->is_valid()) { | |
| 7684 java_thread = rdi; | |
| 7685 get_thread(java_thread); | |
| 7686 } | |
| 7687 // determine last_java_sp register | |
| 7688 if (!last_java_sp->is_valid()) { | |
| 7689 last_java_sp = rsp; | |
| 7690 } | |
| 7691 | |
| 7692 // last_java_fp is optional | |
| 7693 | |
| 7694 if (last_java_fp->is_valid()) { | |
| 7695 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp); | |
| 7696 } | |
| 7697 | |
| 7698 // last_java_pc is optional | |
| 7699 | |
| 7700 if (last_java_pc != NULL) { | |
| 7701 lea(Address(java_thread, | |
| 7702 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()), | |
| 7703 InternalAddress(last_java_pc)); | |
| 7704 | |
| 7705 } | |
| 7706 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp); | |
| 7707 } | |
| 7708 | |
| 7709 void MacroAssembler::shlptr(Register dst, int imm8) { | |
| 7710 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8)); | |
| 7711 } | |
| 7712 | |
| 7713 void MacroAssembler::shrptr(Register dst, int imm8) { | |
| 7714 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8)); | |
| 7715 } | |
| 7716 | |
| 7717 void MacroAssembler::sign_extend_byte(Register reg) { | |
| 7718 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) { | |
| 7719 movsbl(reg, reg); // movsxb | |
| 7720 } else { | |
| 7721 shll(reg, 24); | |
| 7722 sarl(reg, 24); | |
| 7723 } | |
| 7724 } | |
| 7725 | |
| 7726 void MacroAssembler::sign_extend_short(Register reg) { | |
| 7727 if (LP64_ONLY(true ||) VM_Version::is_P6()) { | |
| 7728 movswl(reg, reg); // movsxw | |
| 7729 } else { | |
| 7730 shll(reg, 16); | |
| 7731 sarl(reg, 16); | |
| 7732 } | |
| 7733 } | |
| 7734 | |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2357
diff
changeset
|
7735 void MacroAssembler::testl(Register dst, AddressLiteral src) { |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2357
diff
changeset
|
7736 assert(reachable(src), "Address should be reachable"); |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2357
diff
changeset
|
7737 testl(dst, as_Address(src)); |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2357
diff
changeset
|
7738 } |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2357
diff
changeset
|
7739 |
| 4759 | 7740 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) { |
| 7741 if (reachable(src)) { | |
| 7742 Assembler::sqrtsd(dst, as_Address(src)); | |
| 7743 } else { | |
| 7744 lea(rscratch1, src); | |
| 7745 Assembler::sqrtsd(dst, Address(rscratch1, 0)); | |
| 7746 } | |
| 7747 } | |
| 7748 | |
| 7749 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) { | |
| 7750 if (reachable(src)) { | |
| 7751 Assembler::sqrtss(dst, as_Address(src)); | |
| 7752 } else { | |
| 7753 lea(rscratch1, src); | |
| 7754 Assembler::sqrtss(dst, Address(rscratch1, 0)); | |
| 7755 } | |
| 7756 } | |
| 7757 | |
| 7758 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) { | |
| 7759 if (reachable(src)) { | |
| 7760 Assembler::subsd(dst, as_Address(src)); | |
| 7761 } else { | |
| 7762 lea(rscratch1, src); | |
| 7763 Assembler::subsd(dst, Address(rscratch1, 0)); | |
| 7764 } | |
| 7765 } | |
| 7766 | |
| 7767 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) { | |
| 7768 if (reachable(src)) { | |
| 7769 Assembler::subss(dst, as_Address(src)); | |
| 7770 } else { | |
| 7771 lea(rscratch1, src); | |
| 7772 Assembler::subss(dst, Address(rscratch1, 0)); | |
| 7773 } | |
| 7774 } | |
| 7775 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7776 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7777 if (reachable(src)) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7778 Assembler::ucomisd(dst, as_Address(src)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7779 } else { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
7780 lea(rscratch1, src); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7781 Assembler::ucomisd(dst, Address(rscratch1, 0)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7782 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
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diff
changeset
|
7783 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
7784 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
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4759
diff
changeset
|
7785 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7786 if (reachable(src)) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7787 Assembler::ucomiss(dst, as_Address(src)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7788 } else { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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parents:
4759
diff
changeset
|
7789 lea(rscratch1, src); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7790 Assembler::ucomiss(dst, Address(rscratch1, 0)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7791 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7792 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7793 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7794 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7795 // Used in sign-bit flipping with aligned address. |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7796 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
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4759
diff
changeset
|
7797 if (reachable(src)) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
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4759
diff
changeset
|
7798 Assembler::xorpd(dst, as_Address(src)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
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4759
diff
changeset
|
7799 } else { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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4759
diff
changeset
|
7800 lea(rscratch1, src); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
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4759
diff
changeset
|
7801 Assembler::xorpd(dst, Address(rscratch1, 0)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
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diff
changeset
|
7802 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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4759
diff
changeset
|
7803 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
7804 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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4759
diff
changeset
|
7805 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
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4759
diff
changeset
|
7806 // Used in sign-bit flipping with aligned address. |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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4759
diff
changeset
|
7807 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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4759
diff
changeset
|
7808 if (reachable(src)) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
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4759
diff
changeset
|
7809 Assembler::xorps(dst, as_Address(src)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
7810 } else { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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4759
diff
changeset
|
7811 lea(rscratch1, src); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
7812 Assembler::xorps(dst, Address(rscratch1, 0)); |
|
65149e74c706
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diff
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|
7813 } |
|
65149e74c706
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diff
changeset
|
7814 } |
|
65149e74c706
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changeset
|
7815 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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|
7816 // AVX 3-operands instructions |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
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diff
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|
7817 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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|
7818 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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changeset
|
7819 if (reachable(src)) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
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4759
diff
changeset
|
7820 vaddsd(dst, nds, as_Address(src)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
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|
7821 } else { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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changeset
|
7822 lea(rscratch1, src); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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4759
diff
changeset
|
7823 vaddsd(dst, nds, Address(rscratch1, 0)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
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4759
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|
7824 } |
|
65149e74c706
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|
7825 } |
|
65149e74c706
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changeset
|
7826 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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4759
diff
changeset
|
7827 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
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4759
diff
changeset
|
7828 if (reachable(src)) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
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4759
diff
changeset
|
7829 vaddss(dst, nds, as_Address(src)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
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diff
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|
7830 } else { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
7831 lea(rscratch1, src); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
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4759
diff
changeset
|
7832 vaddss(dst, nds, Address(rscratch1, 0)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7833 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7834 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7835 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7836 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7837 if (reachable(src)) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7838 vandpd(dst, nds, as_Address(src)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7839 } else { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7840 lea(rscratch1, src); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7841 vandpd(dst, nds, Address(rscratch1, 0)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7842 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7843 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7844 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7845 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7846 if (reachable(src)) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7847 vandps(dst, nds, as_Address(src)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7848 } else { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7849 lea(rscratch1, src); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7850 vandps(dst, nds, Address(rscratch1, 0)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7851 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7852 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7853 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7854 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7855 if (reachable(src)) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7856 vdivsd(dst, nds, as_Address(src)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7857 } else { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7858 lea(rscratch1, src); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7859 vdivsd(dst, nds, Address(rscratch1, 0)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7860 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7861 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7862 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7863 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7864 if (reachable(src)) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7865 vdivss(dst, nds, as_Address(src)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7866 } else { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7867 lea(rscratch1, src); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7868 vdivss(dst, nds, Address(rscratch1, 0)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7869 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7870 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7871 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7872 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7873 if (reachable(src)) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7874 vmulsd(dst, nds, as_Address(src)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7875 } else { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7876 lea(rscratch1, src); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7877 vmulsd(dst, nds, Address(rscratch1, 0)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7878 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7879 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7880 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7881 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7882 if (reachable(src)) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7883 vmulss(dst, nds, as_Address(src)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7884 } else { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7885 lea(rscratch1, src); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7886 vmulss(dst, nds, Address(rscratch1, 0)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7887 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7888 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7889 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7890 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7891 if (reachable(src)) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7892 vsubsd(dst, nds, as_Address(src)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7893 } else { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7894 lea(rscratch1, src); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7895 vsubsd(dst, nds, Address(rscratch1, 0)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7896 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7897 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7898 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7899 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7900 if (reachable(src)) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7901 vsubss(dst, nds, as_Address(src)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7902 } else { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7903 lea(rscratch1, src); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7904 vsubss(dst, nds, Address(rscratch1, 0)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7905 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7906 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7907 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7908 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7909 if (reachable(src)) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7910 vxorpd(dst, nds, as_Address(src)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7911 } else { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7912 lea(rscratch1, src); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7913 vxorpd(dst, nds, Address(rscratch1, 0)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7914 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7915 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7916 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7917 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7918 if (reachable(src)) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7919 vxorps(dst, nds, as_Address(src)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7920 } else { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7921 lea(rscratch1, src); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7922 vxorps(dst, nds, Address(rscratch1, 0)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7923 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7924 } |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7925 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7926 |
| 362 | 7927 ////////////////////////////////////////////////////////////////////////////////// |
| 7928 #ifndef SERIALGC | |
| 7929 | |
| 7930 void MacroAssembler::g1_write_barrier_pre(Register obj, | |
|
3249
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7931 Register pre_val, |
| 362 | 7932 Register thread, |
| 7933 Register tmp, | |
|
3249
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7934 bool tosca_live, |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7935 bool expand_call) { |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7936 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7937 // If expand_call is true then we expand the call_VM_leaf macro |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7938 // directly to skip generating the check by |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7939 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp. |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7940 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7941 #ifdef _LP64 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7942 assert(thread == r15_thread, "must be"); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7943 #endif // _LP64 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7944 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7945 Label done; |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7946 Label runtime; |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7947 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7948 assert(pre_val != noreg, "check this code"); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7949 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7950 if (obj != noreg) { |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7951 assert_different_registers(obj, pre_val, tmp); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7952 assert(pre_val != rax, "check this code"); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7953 } |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7954 |
| 362 | 7955 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() + |
| 7956 PtrQueue::byte_offset_of_active())); | |
| 7957 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() + | |
| 7958 PtrQueue::byte_offset_of_index())); | |
| 7959 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() + | |
| 7960 PtrQueue::byte_offset_of_buf())); | |
| 7961 | |
| 7962 | |
|
3249
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
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changeset
|
7963 // Is marking active? |
| 362 | 7964 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) { |
| 7965 cmpl(in_progress, 0); | |
| 7966 } else { | |
| 7967 assert(in_bytes(PtrQueue::byte_width_of_active()) == 1, "Assumption"); | |
| 7968 cmpb(in_progress, 0); | |
| 7969 } | |
| 7970 jcc(Assembler::equal, done); | |
| 7971 | |
|
3249
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
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changeset
|
7972 // Do we need to load the previous value? |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
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parents:
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|
7973 if (obj != noreg) { |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
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parents:
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|
7974 load_heap_oop(pre_val, Address(obj, 0)); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
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parents:
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|
7975 } |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
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diff
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|
7976 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
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changeset
|
7977 // Is the previous value null? |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
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changeset
|
7978 cmpptr(pre_val, (int32_t) NULL_WORD); |
| 362 | 7979 jcc(Assembler::equal, done); |
| 7980 | |
| 7981 // Can we store original value in the thread's buffer? | |
|
3249
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
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diff
changeset
|
7982 // Is index == 0? |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
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|
7983 // (The index field is typed as size_t.) |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
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|
7984 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
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changeset
|
7985 movptr(tmp, index); // tmp := *index_adr |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
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changeset
|
7986 cmpptr(tmp, 0); // tmp == 0? |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
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|
7987 jcc(Assembler::equal, runtime); // If yes, goto runtime |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
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diff
changeset
|
7988 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
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changeset
|
7989 subptr(tmp, wordSize); // tmp := tmp - wordSize |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
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changeset
|
7990 movptr(index, tmp); // *index_adr := tmp |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
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changeset
|
7991 addptr(tmp, buffer); // tmp := tmp + *buffer_adr |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
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changeset
|
7992 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
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diff
changeset
|
7993 // Record the previous value |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
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|
7994 movptr(Address(tmp, 0), pre_val); |
| 362 | 7995 jmp(done); |
|
3249
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
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|
7996 |
| 362 | 7997 bind(runtime); |
| 7998 // save the live input values | |
| 7999 if(tosca_live) push(rax); | |
|
3249
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
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|
8000 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
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|
8001 if (obj != noreg && obj != rax) |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
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changeset
|
8002 push(obj); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
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|
8003 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
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diff
changeset
|
8004 if (pre_val != rax) |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
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diff
changeset
|
8005 push(pre_val); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
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diff
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|
8006 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
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|
8007 // Calling the runtime using the regular call_VM_leaf mechanism generates |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
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|
8008 // code (generated by InterpreterMacroAssember::call_VM_leaf_base) |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
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diff
changeset
|
8009 // that checks that the *(ebp+frame::interpreter_frame_last_sp) == NULL. |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
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diff
changeset
|
8010 // |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
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diff
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|
8011 // If we care generating the pre-barrier without a frame (e.g. in the |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
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|
8012 // intrinsified Reference.get() routine) then ebp might be pointing to |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
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|
8013 // the caller frame and so this check will most likely fail at runtime. |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
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|
8014 // |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8015 // Expanding the call directly bypasses the generation of the check. |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
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changeset
|
8016 // So when we do not have have a full interpreter frame on the stack |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
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changeset
|
8017 // expand_call should be passed true. |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
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diff
changeset
|
8018 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
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changeset
|
8019 NOT_LP64( push(thread); ) |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
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changeset
|
8020 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
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changeset
|
8021 if (expand_call) { |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
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|
8022 LP64_ONLY( assert(pre_val != c_rarg1, "smashed arg"); ) |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
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|
8023 pass_arg1(this, thread); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
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changeset
|
8024 pass_arg0(this, pre_val); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
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changeset
|
8025 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
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parents:
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changeset
|
8026 } else { |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
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changeset
|
8027 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
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|
8028 } |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
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changeset
|
8029 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
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changeset
|
8030 NOT_LP64( pop(thread); ) |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
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changeset
|
8031 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
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changeset
|
8032 // save the live input values |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
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changeset
|
8033 if (pre_val != rax) |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
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diff
changeset
|
8034 pop(pre_val); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8035 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
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diff
changeset
|
8036 if (obj != noreg && obj != rax) |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
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diff
changeset
|
8037 pop(obj); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
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|
8038 |
| 362 | 8039 if(tosca_live) pop(rax); |
|
3249
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
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changeset
|
8040 |
| 362 | 8041 bind(done); |
| 8042 } | |
| 8043 | |
| 8044 void MacroAssembler::g1_write_barrier_post(Register store_addr, | |
| 8045 Register new_val, | |
| 8046 Register thread, | |
| 8047 Register tmp, | |
| 8048 Register tmp2) { | |
|
3249
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8049 #ifdef _LP64 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8050 assert(thread == r15_thread, "must be"); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
8051 #endif // _LP64 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
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changeset
|
8052 |
| 362 | 8053 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() + |
| 8054 PtrQueue::byte_offset_of_index())); | |
| 8055 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() + | |
| 8056 PtrQueue::byte_offset_of_buf())); | |
|
3249
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
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diff
changeset
|
8057 |
| 362 | 8058 BarrierSet* bs = Universe::heap()->barrier_set(); |
| 8059 CardTableModRefBS* ct = (CardTableModRefBS*)bs; | |
| 8060 Label done; | |
| 8061 Label runtime; | |
| 8062 | |
| 8063 // Does store cross heap regions? | |
| 8064 | |
| 8065 movptr(tmp, store_addr); | |
| 8066 xorptr(tmp, new_val); | |
| 8067 shrptr(tmp, HeapRegion::LogOfHRGrainBytes); | |
| 8068 jcc(Assembler::equal, done); | |
| 8069 | |
| 8070 // crosses regions, storing NULL? | |
| 8071 | |
| 8072 cmpptr(new_val, (int32_t) NULL_WORD); | |
| 8073 jcc(Assembler::equal, done); | |
| 8074 | |
| 8075 // storing region crossing non-NULL, is card already dirty? | |
| 8076 | |
| 8077 ExternalAddress cardtable((address) ct->byte_map_base); | |
| 8078 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); | |
| 8079 #ifdef _LP64 | |
| 8080 const Register card_addr = tmp; | |
| 8081 | |
| 8082 movq(card_addr, store_addr); | |
| 8083 shrq(card_addr, CardTableModRefBS::card_shift); | |
| 8084 | |
| 8085 lea(tmp2, cardtable); | |
| 8086 | |
| 8087 // get the address of the card | |
| 8088 addq(card_addr, tmp2); | |
| 8089 #else | |
| 8090 const Register card_index = tmp; | |
| 8091 | |
| 8092 movl(card_index, store_addr); | |
| 8093 shrl(card_index, CardTableModRefBS::card_shift); | |
| 8094 | |
| 8095 Address index(noreg, card_index, Address::times_1); | |
| 8096 const Register card_addr = tmp; | |
| 8097 lea(card_addr, as_Address(ArrayAddress(cardtable, index))); | |
| 8098 #endif | |
| 8099 cmpb(Address(card_addr, 0), 0); | |
| 8100 jcc(Assembler::equal, done); | |
| 8101 | |
| 8102 // storing a region crossing, non-NULL oop, card is clean. | |
| 8103 // dirty card and log. | |
| 8104 | |
| 8105 movb(Address(card_addr, 0), 0); | |
| 8106 | |
| 8107 cmpl(queue_index, 0); | |
| 8108 jcc(Assembler::equal, runtime); | |
| 8109 subl(queue_index, wordSize); | |
| 8110 movptr(tmp2, buffer); | |
| 8111 #ifdef _LP64 | |
| 8112 movslq(rscratch1, queue_index); | |
| 8113 addq(tmp2, rscratch1); | |
| 8114 movq(Address(tmp2, 0), card_addr); | |
| 8115 #else | |
| 8116 addl(tmp2, queue_index); | |
| 8117 movl(Address(tmp2, 0), card_index); | |
| 8118 #endif | |
| 8119 jmp(done); | |
| 8120 | |
| 8121 bind(runtime); | |
| 8122 // save the live input values | |
| 8123 push(store_addr); | |
| 8124 push(new_val); | |
| 8125 #ifdef _LP64 | |
| 8126 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread); | |
| 8127 #else | |
| 8128 push(thread); | |
| 8129 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread); | |
| 8130 pop(thread); | |
| 8131 #endif | |
| 8132 pop(new_val); | |
| 8133 pop(store_addr); | |
| 8134 | |
| 8135 bind(done); | |
| 8136 } | |
| 8137 | |
| 8138 #endif // SERIALGC | |
| 8139 ////////////////////////////////////////////////////////////////////////////////// | |
| 8140 | |
| 8141 | |
| 304 | 8142 void MacroAssembler::store_check(Register obj) { |
| 8143 // Does a store check for the oop in register obj. The content of | |
| 8144 // register obj is destroyed afterwards. | |
| 8145 store_check_part_1(obj); | |
| 8146 store_check_part_2(obj); | |
| 8147 } | |
| 8148 | |
| 8149 void MacroAssembler::store_check(Register obj, Address dst) { | |
| 8150 store_check(obj); | |
| 8151 } | |
| 8152 | |
| 8153 | |
| 8154 // split the store check operation so that other instructions can be scheduled inbetween | |
| 8155 void MacroAssembler::store_check_part_1(Register obj) { | |
| 8156 BarrierSet* bs = Universe::heap()->barrier_set(); | |
| 8157 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind"); | |
| 8158 shrptr(obj, CardTableModRefBS::card_shift); | |
| 8159 } | |
| 8160 | |
| 8161 void MacroAssembler::store_check_part_2(Register obj) { | |
| 8162 BarrierSet* bs = Universe::heap()->barrier_set(); | |
| 8163 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind"); | |
| 8164 CardTableModRefBS* ct = (CardTableModRefBS*)bs; | |
| 8165 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); | |
| 8166 | |
| 8167 // The calculation for byte_map_base is as follows: | |
| 8168 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift); | |
| 8169 // So this essentially converts an address to a displacement and | |
| 8170 // it will never need to be relocated. On 64bit however the value may be too | |
| 8171 // large for a 32bit displacement | |
| 8172 | |
| 8173 intptr_t disp = (intptr_t) ct->byte_map_base; | |
| 8174 if (is_simm32(disp)) { | |
| 8175 Address cardtable(noreg, obj, Address::times_1, disp); | |
| 8176 movb(cardtable, 0); | |
| 8177 } else { | |
| 8178 // By doing it as an ExternalAddress disp could be converted to a rip-relative | |
| 8179 // displacement and done in a single instruction given favorable mapping and | |
| 8180 // a smarter version of as_Address. Worst case it is two instructions which | |
| 8181 // is no worse off then loading disp into a register and doing as a simple | |
| 8182 // Address() as above. | |
| 8183 // We can't do as ExternalAddress as the only style since if disp == 0 we'll | |
| 8184 // assert since NULL isn't acceptable in a reloci (see 6644928). In any case | |
| 8185 // in some cases we'll get a single instruction version. | |
| 8186 | |
| 8187 ExternalAddress cardtable((address)disp); | |
| 8188 Address index(noreg, obj, Address::times_1); | |
| 8189 movb(as_Address(ArrayAddress(cardtable, index)), 0); | |
| 8190 } | |
| 8191 } | |
| 8192 | |
| 8193 void MacroAssembler::subptr(Register dst, int32_t imm32) { | |
| 8194 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32)); | |
| 8195 } | |
| 8196 | |
|
4947
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
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changeset
|
8197 // Force generation of a 4 byte immediate value even if it fits into 8bit |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
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changeset
|
8198 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) { |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
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changeset
|
8199 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32)); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
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changeset
|
8200 } |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
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changeset
|
8201 |
| 304 | 8202 void MacroAssembler::subptr(Register dst, Register src) { |
| 8203 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); | |
| 8204 } | |
| 8205 | |
| 8206 // C++ bool manipulation | |
| 0 | 8207 void MacroAssembler::testbool(Register dst) { |
| 8208 if(sizeof(bool) == 1) | |
| 304 | 8209 testb(dst, 0xff); |
| 0 | 8210 else if(sizeof(bool) == 2) { |
| 8211 // testw implementation needed for two byte bools | |
| 8212 ShouldNotReachHere(); | |
| 8213 } else if(sizeof(bool) == 4) | |
| 8214 testl(dst, dst); | |
| 8215 else | |
| 8216 // unsupported | |
| 8217 ShouldNotReachHere(); | |
| 8218 } | |
| 8219 | |
| 304 | 8220 void MacroAssembler::testptr(Register dst, Register src) { |
| 8221 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src)); | |
| 8222 } | |
| 8223 | |
| 8224 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes. | |
| 8225 void MacroAssembler::tlab_allocate(Register obj, | |
| 8226 Register var_size_in_bytes, | |
| 8227 int con_size_in_bytes, | |
| 8228 Register t1, | |
| 8229 Register t2, | |
| 8230 Label& slow_case) { | |
| 8231 assert_different_registers(obj, t1, t2); | |
| 8232 assert_different_registers(obj, var_size_in_bytes, t1); | |
| 8233 Register end = t2; | |
| 8234 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread); | |
| 8235 | |
| 8236 verify_tlab(); | |
| 8237 | |
| 8238 NOT_LP64(get_thread(thread)); | |
| 8239 | |
| 8240 movptr(obj, Address(thread, JavaThread::tlab_top_offset())); | |
| 8241 if (var_size_in_bytes == noreg) { | |
| 8242 lea(end, Address(obj, con_size_in_bytes)); | |
| 8243 } else { | |
| 8244 lea(end, Address(obj, var_size_in_bytes, Address::times_1)); | |
| 8245 } | |
| 8246 cmpptr(end, Address(thread, JavaThread::tlab_end_offset())); | |
| 8247 jcc(Assembler::above, slow_case); | |
| 8248 | |
| 8249 // update the tlab top pointer | |
| 8250 movptr(Address(thread, JavaThread::tlab_top_offset()), end); | |
| 8251 | |
| 8252 // recover var_size_in_bytes if necessary | |
| 8253 if (var_size_in_bytes == end) { | |
| 8254 subptr(var_size_in_bytes, obj); | |
| 8255 } | |
| 8256 verify_tlab(); | |
| 8257 } | |
| 8258 | |
| 8259 // Preserves rbx, and rdx. | |
|
2100
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|
8260 Register MacroAssembler::tlab_refill(Label& retry, |
|
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|
8261 Label& try_eden, |
|
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diff
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|
8262 Label& slow_case) { |
| 304 | 8263 Register top = rax; |
| 8264 Register t1 = rcx; | |
| 8265 Register t2 = rsi; | |
| 8266 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread); | |
| 8267 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx); | |
| 8268 Label do_refill, discard_tlab; | |
| 8269 | |
| 8270 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { | |
| 8271 // No allocation in the shared eden. | |
| 8272 jmp(slow_case); | |
| 8273 } | |
| 8274 | |
| 8275 NOT_LP64(get_thread(thread_reg)); | |
| 8276 | |
| 8277 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); | |
| 8278 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); | |
| 8279 | |
| 8280 // calculate amount of free space | |
| 8281 subptr(t1, top); | |
| 8282 shrptr(t1, LogHeapWordSize); | |
| 8283 | |
| 8284 // Retain tlab and allocate object in shared space if | |
| 8285 // the amount free in the tlab is too large to discard. | |
| 8286 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset()))); | |
| 8287 jcc(Assembler::lessEqual, discard_tlab); | |
| 8288 | |
| 8289 // Retain | |
| 8290 // %%% yuck as movptr... | |
| 8291 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment()); | |
| 8292 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2); | |
| 8293 if (TLABStats) { | |
| 8294 // increment number of slow_allocations | |
| 8295 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1); | |
| 8296 } | |
| 8297 jmp(try_eden); | |
| 8298 | |
| 8299 bind(discard_tlab); | |
| 8300 if (TLABStats) { | |
| 8301 // increment number of refills | |
| 8302 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1); | |
| 8303 // accumulate wastage -- t1 is amount free in tlab | |
| 8304 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1); | |
| 8305 } | |
| 8306 | |
| 8307 // if tlab is currently allocated (top or end != null) then | |
| 8308 // fill [top, end + alignment_reserve) with array object | |
|
2100
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|
8309 testptr(top, top); |
| 304 | 8310 jcc(Assembler::zero, do_refill); |
| 8311 | |
| 8312 // set up the mark word | |
| 8313 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2)); | |
| 8314 // set the length to the remaining space | |
| 8315 subptr(t1, typeArrayOopDesc::header_size(T_INT)); | |
| 8316 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve()); | |
| 8317 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint))); | |
| 1690 | 8318 movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1); |
| 304 | 8319 // set klass to intArrayKlass |
| 8320 // dubious reloc why not an oop reloc? | |
|
2100
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|
8321 movptr(t1, ExternalAddress((address)Universe::intArrayKlassObj_addr())); |
| 304 | 8322 // store klass last. concurrent gcs assumes klass length is valid if |
| 8323 // klass field is not null. | |
| 8324 store_klass(top, t1); | |
| 8325 | |
|
2100
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7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
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diff
changeset
|
8326 movptr(t1, top); |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
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parents:
2014
diff
changeset
|
8327 subptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); |
|
b1a2afa37ec4
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parents:
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diff
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|
8328 incr_allocated_bytes(thread_reg, t1, 0); |
|
b1a2afa37ec4
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phh
parents:
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diff
changeset
|
8329 |
| 304 | 8330 // refill the tlab with an eden allocation |
| 8331 bind(do_refill); | |
| 8332 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); | |
| 8333 shlptr(t1, LogHeapWordSize); | |
|
2100
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diff
changeset
|
8334 // allocate new tlab, address returned in top |
| 304 | 8335 eden_allocate(top, t1, 0, t2, slow_case); |
| 8336 | |
| 8337 // Check that t1 was preserved in eden_allocate. | |
| 8338 #ifdef ASSERT | |
| 8339 if (UseTLAB) { | |
| 8340 Label ok; | |
| 8341 Register tsize = rsi; | |
| 8342 assert_different_registers(tsize, thread_reg, t1); | |
| 8343 push(tsize); | |
| 8344 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); | |
| 8345 shlptr(tsize, LogHeapWordSize); | |
| 8346 cmpptr(t1, tsize); | |
| 8347 jcc(Assembler::equal, ok); | |
| 8348 stop("assert(t1 != tlab size)"); | |
| 8349 should_not_reach_here(); | |
| 8350 | |
| 8351 bind(ok); | |
| 8352 pop(tsize); | |
| 8353 } | |
| 8354 #endif | |
| 8355 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top); | |
| 8356 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top); | |
| 8357 addptr(top, t1); | |
| 8358 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes()); | |
| 8359 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top); | |
| 8360 verify_tlab(); | |
| 8361 jmp(retry); | |
|
2100
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7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
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diff
changeset
|
8362 |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
8363 return thread_reg; // for use by caller |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
8364 } |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
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diff
changeset
|
8365 |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
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2014
diff
changeset
|
8366 void MacroAssembler::incr_allocated_bytes(Register thread, |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
8367 Register var_size_in_bytes, |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
8368 int con_size_in_bytes, |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
8369 Register t1) { |
|
4770
1cb50d7a9d95
7119294: Two command line options cause JVM to crash
iveresov
parents:
4768
diff
changeset
|
8370 if (!thread->is_valid()) { |
|
1cb50d7a9d95
7119294: Two command line options cause JVM to crash
iveresov
parents:
4768
diff
changeset
|
8371 #ifdef _LP64 |
|
1cb50d7a9d95
7119294: Two command line options cause JVM to crash
iveresov
parents:
4768
diff
changeset
|
8372 thread = r15_thread; |
|
1cb50d7a9d95
7119294: Two command line options cause JVM to crash
iveresov
parents:
4768
diff
changeset
|
8373 #else |
|
1cb50d7a9d95
7119294: Two command line options cause JVM to crash
iveresov
parents:
4768
diff
changeset
|
8374 assert(t1->is_valid(), "need temp reg"); |
|
1cb50d7a9d95
7119294: Two command line options cause JVM to crash
iveresov
parents:
4768
diff
changeset
|
8375 thread = t1; |
|
1cb50d7a9d95
7119294: Two command line options cause JVM to crash
iveresov
parents:
4768
diff
changeset
|
8376 get_thread(thread); |
|
1cb50d7a9d95
7119294: Two command line options cause JVM to crash
iveresov
parents:
4768
diff
changeset
|
8377 #endif |
|
1cb50d7a9d95
7119294: Two command line options cause JVM to crash
iveresov
parents:
4768
diff
changeset
|
8378 } |
|
1cb50d7a9d95
7119294: Two command line options cause JVM to crash
iveresov
parents:
4768
diff
changeset
|
8379 |
|
2100
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
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diff
changeset
|
8380 #ifdef _LP64 |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
8381 if (var_size_in_bytes->is_valid()) { |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
8382 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes); |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
8383 } else { |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
8384 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes); |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
8385 } |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
8386 #else |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
8387 if (var_size_in_bytes->is_valid()) { |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
8388 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes); |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
8389 } else { |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
8390 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes); |
|
b1a2afa37ec4
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phh
parents:
2014
diff
changeset
|
8391 } |
|
b1a2afa37ec4
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phh
parents:
2014
diff
changeset
|
8392 adcl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())+4), 0); |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
8393 #endif |
| 304 | 8394 } |
| 8395 | |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8396 void MacroAssembler::fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use) { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8397 pusha(); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8398 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8399 // if we are coming from c1, xmm registers may be live |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8400 if (UseSSE >= 1) { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8401 subptr(rsp, sizeof(jdouble)* LP64_ONLY(16) NOT_LP64(8)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8402 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8403 int off = 0; |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8404 if (UseSSE == 1) { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8405 movflt(Address(rsp,off++*sizeof(jdouble)),xmm0); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8406 movflt(Address(rsp,off++*sizeof(jdouble)),xmm1); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8407 movflt(Address(rsp,off++*sizeof(jdouble)),xmm2); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8408 movflt(Address(rsp,off++*sizeof(jdouble)),xmm3); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8409 movflt(Address(rsp,off++*sizeof(jdouble)),xmm4); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8410 movflt(Address(rsp,off++*sizeof(jdouble)),xmm5); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8411 movflt(Address(rsp,off++*sizeof(jdouble)),xmm6); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8412 movflt(Address(rsp,off++*sizeof(jdouble)),xmm7); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8413 } else if (UseSSE >= 2) { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8414 movdbl(Address(rsp,off++*sizeof(jdouble)),xmm0); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8415 movdbl(Address(rsp,off++*sizeof(jdouble)),xmm1); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8416 movdbl(Address(rsp,off++*sizeof(jdouble)),xmm2); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8417 movdbl(Address(rsp,off++*sizeof(jdouble)),xmm3); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8418 movdbl(Address(rsp,off++*sizeof(jdouble)),xmm4); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8419 movdbl(Address(rsp,off++*sizeof(jdouble)),xmm5); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8420 movdbl(Address(rsp,off++*sizeof(jdouble)),xmm6); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8421 movdbl(Address(rsp,off++*sizeof(jdouble)),xmm7); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8422 #ifdef _LP64 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8423 movdbl(Address(rsp,off++*sizeof(jdouble)),xmm8); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8424 movdbl(Address(rsp,off++*sizeof(jdouble)),xmm9); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8425 movdbl(Address(rsp,off++*sizeof(jdouble)),xmm10); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8426 movdbl(Address(rsp,off++*sizeof(jdouble)),xmm11); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8427 movdbl(Address(rsp,off++*sizeof(jdouble)),xmm12); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8428 movdbl(Address(rsp,off++*sizeof(jdouble)),xmm13); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8429 movdbl(Address(rsp,off++*sizeof(jdouble)),xmm14); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8430 movdbl(Address(rsp,off++*sizeof(jdouble)),xmm15); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8431 #endif |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8432 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8433 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8434 // Preserve registers across runtime call |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8435 int incoming_argument_and_return_value_offset = -1; |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8436 if (num_fpu_regs_in_use > 1) { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8437 // Must preserve all other FPU regs (could alternatively convert |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8438 // SharedRuntime::dsin, dcos etc. into assembly routines known not to trash |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8439 // FPU state, but can not trust C compiler) |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8440 NEEDS_CLEANUP; |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8441 // NOTE that in this case we also push the incoming argument(s) to |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8442 // the stack and restore it later; we also use this stack slot to |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8443 // hold the return value from dsin, dcos etc. |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8444 for (int i = 0; i < num_fpu_regs_in_use; i++) { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8445 subptr(rsp, sizeof(jdouble)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8446 fstp_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8447 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8448 incoming_argument_and_return_value_offset = sizeof(jdouble)*(num_fpu_regs_in_use-1); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8449 for (int i = nb_args-1; i >= 0; i--) { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8450 fld_d(Address(rsp, incoming_argument_and_return_value_offset-i*sizeof(jdouble))); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8451 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8452 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8453 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8454 subptr(rsp, nb_args*sizeof(jdouble)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8455 for (int i = 0; i < nb_args; i++) { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8456 fstp_d(Address(rsp, i*sizeof(jdouble))); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8457 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8458 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8459 #ifdef _LP64 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8460 if (nb_args > 0) { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8461 movdbl(xmm0, Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8462 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8463 if (nb_args > 1) { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8464 movdbl(xmm1, Address(rsp, sizeof(jdouble))); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8465 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8466 assert(nb_args <= 2, "unsupported number of args"); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8467 #endif // _LP64 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8468 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8469 // NOTE: we must not use call_VM_leaf here because that requires a |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8470 // complete interpreter frame in debug mode -- same bug as 4387334 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8471 // MacroAssembler::call_VM_leaf_base is perfectly safe and will |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8472 // do proper 64bit abi |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8473 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8474 NEEDS_CLEANUP; |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8475 // Need to add stack banging before this runtime call if it needs to |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8476 // be taken; however, there is no generic stack banging routine at |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8477 // the MacroAssembler level |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8478 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8479 MacroAssembler::call_VM_leaf_base(runtime_entry, 0); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8480 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8481 #ifdef _LP64 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8482 movsd(Address(rsp, 0), xmm0); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8483 fld_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8484 #endif // _LP64 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8485 addptr(rsp, sizeof(jdouble) * nb_args); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8486 if (num_fpu_regs_in_use > 1) { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8487 // Must save return value to stack and then restore entire FPU |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8488 // stack except incoming arguments |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8489 fstp_d(Address(rsp, incoming_argument_and_return_value_offset)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8490 for (int i = 0; i < num_fpu_regs_in_use - nb_args; i++) { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8491 fld_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8492 addptr(rsp, sizeof(jdouble)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8493 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8494 fld_d(Address(rsp, (nb_args-1)*sizeof(jdouble))); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8495 addptr(rsp, sizeof(jdouble) * nb_args); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8496 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8497 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8498 off = 0; |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8499 if (UseSSE == 1) { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8500 movflt(xmm0, Address(rsp,off++*sizeof(jdouble))); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8501 movflt(xmm1, Address(rsp,off++*sizeof(jdouble))); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8502 movflt(xmm2, Address(rsp,off++*sizeof(jdouble))); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8503 movflt(xmm3, Address(rsp,off++*sizeof(jdouble))); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8504 movflt(xmm4, Address(rsp,off++*sizeof(jdouble))); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8505 movflt(xmm5, Address(rsp,off++*sizeof(jdouble))); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8506 movflt(xmm6, Address(rsp,off++*sizeof(jdouble))); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8507 movflt(xmm7, Address(rsp,off++*sizeof(jdouble))); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8508 } else if (UseSSE >= 2) { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8509 movdbl(xmm0, Address(rsp,off++*sizeof(jdouble))); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8510 movdbl(xmm1, Address(rsp,off++*sizeof(jdouble))); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8511 movdbl(xmm2, Address(rsp,off++*sizeof(jdouble))); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8512 movdbl(xmm3, Address(rsp,off++*sizeof(jdouble))); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8513 movdbl(xmm4, Address(rsp,off++*sizeof(jdouble))); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8514 movdbl(xmm5, Address(rsp,off++*sizeof(jdouble))); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8515 movdbl(xmm6, Address(rsp,off++*sizeof(jdouble))); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8516 movdbl(xmm7, Address(rsp,off++*sizeof(jdouble))); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8517 #ifdef _LP64 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8518 movdbl(xmm8, Address(rsp,off++*sizeof(jdouble))); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8519 movdbl(xmm9, Address(rsp,off++*sizeof(jdouble))); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8520 movdbl(xmm10, Address(rsp,off++*sizeof(jdouble))); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8521 movdbl(xmm11, Address(rsp,off++*sizeof(jdouble))); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8522 movdbl(xmm12, Address(rsp,off++*sizeof(jdouble))); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8523 movdbl(xmm13, Address(rsp,off++*sizeof(jdouble))); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8524 movdbl(xmm14, Address(rsp,off++*sizeof(jdouble))); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8525 movdbl(xmm15, Address(rsp,off++*sizeof(jdouble))); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8526 #endif |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8527 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8528 if (UseSSE >= 1) { |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8529 addptr(rsp, sizeof(jdouble)* LP64_ONLY(16) NOT_LP64(8)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8530 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8531 popa(); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8532 } |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8533 |
| 304 | 8534 static const double pi_4 = 0.7853981633974483; |
| 8535 | |
| 8536 void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) { | |
| 8537 // A hand-coded argument reduction for values in fabs(pi/4, pi/2) | |
| 8538 // was attempted in this code; unfortunately it appears that the | |
| 8539 // switch to 80-bit precision and back causes this to be | |
| 8540 // unprofitable compared with simply performing a runtime call if | |
| 8541 // the argument is out of the (-pi/4, pi/4) range. | |
| 8542 | |
| 8543 Register tmp = noreg; | |
| 8544 if (!VM_Version::supports_cmov()) { | |
| 8545 // fcmp needs a temporary so preserve rbx, | |
| 8546 tmp = rbx; | |
| 8547 push(tmp); | |
| 8548 } | |
| 8549 | |
| 8550 Label slow_case, done; | |
| 8551 | |
|
520
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
8552 ExternalAddress pi4_adr = (address)&pi_4; |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
8553 if (reachable(pi4_adr)) { |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
8554 // x ?<= pi/4 |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
8555 fld_d(pi4_adr); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
8556 fld_s(1); // Stack: X PI/4 X |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
8557 fabs(); // Stack: |X| PI/4 X |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
8558 fcmp(tmp); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
8559 jcc(Assembler::above, slow_case); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
8560 |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
8561 // fastest case: -pi/4 <= x <= pi/4 |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
8562 switch(trig) { |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
8563 case 's': |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
8564 fsin(); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
8565 break; |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
8566 case 'c': |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
8567 fcos(); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
8568 break; |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
8569 case 't': |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
8570 ftan(); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
8571 break; |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
8572 default: |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
8573 assert(false, "bad intrinsic"); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
8574 break; |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
8575 } |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
8576 jmp(done); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
8577 } |
| 304 | 8578 |
| 8579 // slow case: runtime call | |
| 8580 bind(slow_case); | |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8581 |
| 304 | 8582 switch(trig) { |
| 8583 case 's': | |
| 8584 { | |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8585 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), 1, num_fpu_regs_in_use); |
| 304 | 8586 } |
| 8587 break; | |
| 8588 case 'c': | |
| 8589 { | |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8590 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), 1, num_fpu_regs_in_use); |
| 304 | 8591 } |
| 8592 break; | |
| 8593 case 't': | |
| 8594 { | |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5984
diff
changeset
|
8595 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dtan), 1, num_fpu_regs_in_use); |
| 304 | 8596 } |
| 8597 break; | |
| 8598 default: | |
| 8599 assert(false, "bad intrinsic"); | |
| 8600 break; | |
| 8601 } | |
| 8602 | |
| 8603 // Come here with result in F-TOS | |
| 8604 bind(done); | |
| 8605 | |
| 8606 if (tmp != noreg) { | |
| 8607 pop(tmp); | |
| 8608 } | |
| 8609 } | |
| 8610 | |
| 8611 | |
|
623
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8612 // Look up the method for a megamorphic invokeinterface call. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8613 // The target method is determined by <intf_klass, itable_index>. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8614 // The receiver klass is in recv_klass. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8615 // On success, the result will be in method_result, and execution falls through. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8616 // On failure, execution transfers to the given label. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8617 void MacroAssembler::lookup_interface_method(Register recv_klass, |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8618 Register intf_klass, |
|
665
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
647
diff
changeset
|
8619 RegisterOrConstant itable_index, |
|
623
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8620 Register method_result, |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8621 Register scan_temp, |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8622 Label& L_no_such_interface) { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8623 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8624 assert(itable_index.is_constant() || itable_index.as_register() == method_result, |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8625 "caller must use same register for non-constant itable index as for method"); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8626 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8627 // Compute start of first itableOffsetEntry (which is at the end of the vtable) |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8628 int vtable_base = instanceKlass::vtable_start_offset() * wordSize; |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8629 int itentry_off = itableMethodEntry::method_offset_in_bytes(); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8630 int scan_step = itableOffsetEntry::size() * wordSize; |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8631 int vte_size = vtableEntry::size() * wordSize; |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8632 Address::ScaleFactor times_vte_scale = Address::times_ptr; |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8633 assert(vte_size == wordSize, "else adjust times_vte_scale"); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8634 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8635 movl(scan_temp, Address(recv_klass, instanceKlass::vtable_length_offset() * wordSize)); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8636 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8637 // %%% Could store the aligned, prescaled offset in the klassoop. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8638 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base)); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8639 if (HeapWordsPerLong > 1) { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8640 // Round up to align_object_offset boundary |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8641 // see code for instanceKlass::start_of_itable! |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8642 round_to(scan_temp, BytesPerLong); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8643 } |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8644 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8645 // Adjust recv_klass by scaled itable_index, so we can free itable_index. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8646 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below"); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8647 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off)); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8648 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8649 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8650 // if (scan->interface() == intf) { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8651 // result = (klass + scan->offset() + itable_index); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8652 // } |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8653 // } |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8654 Label search, found_method; |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8655 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8656 for (int peel = 1; peel >= 0; peel--) { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8657 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes())); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8658 cmpptr(intf_klass, method_result); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8659 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8660 if (peel) { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8661 jccb(Assembler::equal, found_method); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8662 } else { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8663 jccb(Assembler::notEqual, search); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8664 // (invert the test to fall through to found_method...) |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8665 } |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8666 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8667 if (!peel) break; |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8668 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8669 bind(search); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8670 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8671 // Check that the previous entry is non-null. A null entry means that |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8672 // the receiver class doesn't implement the interface, and wasn't the |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8673 // same as when the caller was compiled. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8674 testptr(method_result, method_result); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8675 jcc(Assembler::zero, L_no_such_interface); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8676 addptr(scan_temp, scan_step); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8677 } |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8678 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8679 bind(found_method); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8680 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8681 // Got a hit. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8682 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes())); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8683 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1)); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8684 } |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8685 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
8686 |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8687 void MacroAssembler::check_klass_subtype(Register sub_klass, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8688 Register super_klass, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8689 Register temp_reg, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8690 Label& L_success) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8691 Label L_failure; |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8692 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8693 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8694 bind(L_failure); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8695 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8696 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8697 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8698 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8699 Register super_klass, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8700 Register temp_reg, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8701 Label* L_success, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8702 Label* L_failure, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8703 Label* L_slow_path, |
|
665
c89f86385056
6814659: separable cleanups and subroutines for 6655638
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parents:
647
diff
changeset
|
8704 RegisterOrConstant super_check_offset) { |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8705 assert_different_registers(sub_klass, super_klass, temp_reg); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8706 bool must_load_sco = (super_check_offset.constant_or_zero() == -1); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8707 if (super_check_offset.is_register()) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8708 assert_different_registers(sub_klass, super_klass, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8709 super_check_offset.as_register()); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
8710 } else if (must_load_sco) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8711 assert(temp_reg != noreg, "supply either a temp or a register offset"); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8712 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8713 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8714 Label L_fallthrough; |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8715 int label_nulls = 0; |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8716 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
8717 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8718 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
8719 assert(label_nulls <= 1, "at most one NULL in the batch"); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8720 |
|
4762
069ab3f976d3
7118863: Move sizeof(klassOopDesc) into the *Klass::*_offset_in_bytes() functions
stefank
parents:
4761
diff
changeset
|
8721 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); |
|
069ab3f976d3
7118863: Move sizeof(klassOopDesc) into the *Klass::*_offset_in_bytes() functions
stefank
parents:
4761
diff
changeset
|
8722 int sco_offset = in_bytes(Klass::super_check_offset_offset()); |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
8723 Address super_check_offset_addr(super_klass, sco_offset); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8724 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8725 // Hacked jcc, which "knows" that L_fallthrough, at least, is in |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8726 // range of a jccb. If this routine grows larger, reconsider at |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8727 // least some of these. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8728 #define local_jcc(assembler_cond, label) \ |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8729 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \ |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8730 else jcc( assembler_cond, label) /*omit semi*/ |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
8731 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8732 // Hacked jmp, which may only be used just before L_fallthrough. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
8733 #define final_jmp(label) \ |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
8734 if (&(label) == &L_fallthrough) { /*do nothing*/ } \ |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8735 else jmp(label) /*omit semi*/ |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8736 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
8737 // If the pointers are equal, we are done (e.g., String[] elements). |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8738 // This self-check enables sharing of secondary supertype arrays among |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8739 // non-primary types such as array-of-interface. Otherwise, each such |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8740 // type would need its own customized SSA. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8741 // We move this check to the front of the fast path because many |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8742 // type checks are in fact trivially successful in this manner, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8743 // so we get a nicely predicted branch right at the start of the check. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8744 cmpptr(sub_klass, super_klass); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8745 local_jcc(Assembler::equal, *L_success); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8746 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8747 // Check the supertype display: |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8748 if (must_load_sco) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8749 // Positive movl does right thing on LP64. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8750 movl(temp_reg, super_check_offset_addr); |
|
665
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
647
diff
changeset
|
8751 super_check_offset = RegisterOrConstant(temp_reg); |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8752 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8753 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8754 cmpptr(super_klass, super_check_addr); // load displayed supertype |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8755 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8756 // This check has worked decisively for primary supers. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8757 // Secondary supers are sought in the super_cache ('super_cache_addr'). |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8758 // (Secondary supers are interfaces and very deeply nested subtypes.) |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8759 // This works in the same check above because of a tricky aliasing |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8760 // between the super_cache and the primary super display elements. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8761 // (The 'super_check_addr' can address either, as the case requires.) |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8762 // Note that the cache is updated below if it does not help us find |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8763 // what we need immediately. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8764 // So if it was a primary super, we can just fail immediately. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8765 // Otherwise, it's the slow path for us (no success at this point). |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8766 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8767 if (super_check_offset.is_register()) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8768 local_jcc(Assembler::equal, *L_success); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8769 cmpl(super_check_offset.as_register(), sc_offset); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8770 if (L_failure == &L_fallthrough) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8771 local_jcc(Assembler::equal, *L_slow_path); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8772 } else { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8773 local_jcc(Assembler::notEqual, *L_failure); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8774 final_jmp(*L_slow_path); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8775 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8776 } else if (super_check_offset.as_constant() == sc_offset) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8777 // Need a slow path; fast failure is impossible. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8778 if (L_slow_path == &L_fallthrough) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8779 local_jcc(Assembler::equal, *L_success); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8780 } else { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8781 local_jcc(Assembler::notEqual, *L_slow_path); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8782 final_jmp(*L_success); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8783 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8784 } else { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8785 // No slow path; it's a fast decision. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8786 if (L_failure == &L_fallthrough) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8787 local_jcc(Assembler::equal, *L_success); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8788 } else { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8789 local_jcc(Assembler::notEqual, *L_failure); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8790 final_jmp(*L_success); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8791 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8792 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8793 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8794 bind(L_fallthrough); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8795 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8796 #undef local_jcc |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8797 #undef final_jmp |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8798 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8799 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8800 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8801 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8802 Register super_klass, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8803 Register temp_reg, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8804 Register temp2_reg, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8805 Label* L_success, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8806 Label* L_failure, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8807 bool set_cond_codes) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8808 assert_different_registers(sub_klass, super_klass, temp_reg); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8809 if (temp2_reg != noreg) |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8810 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8811 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg) |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8812 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8813 Label L_fallthrough; |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8814 int label_nulls = 0; |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8815 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8816 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8817 assert(label_nulls <= 1, "at most one NULL in the batch"); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8818 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8819 // a couple of useful fields in sub_klass: |
|
4762
069ab3f976d3
7118863: Move sizeof(klassOopDesc) into the *Klass::*_offset_in_bytes() functions
stefank
parents:
4761
diff
changeset
|
8820 int ss_offset = in_bytes(Klass::secondary_supers_offset()); |
|
069ab3f976d3
7118863: Move sizeof(klassOopDesc) into the *Klass::*_offset_in_bytes() functions
stefank
parents:
4761
diff
changeset
|
8821 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8822 Address secondary_supers_addr(sub_klass, ss_offset); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8823 Address super_cache_addr( sub_klass, sc_offset); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8824 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8825 // Do a linear scan of the secondary super-klass chain. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8826 // This code is rarely used, so simplicity is a virtue here. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8827 // The repne_scan instruction uses fixed registers, which we must spill. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8828 // Don't worry too much about pre-existing connections with the input regs. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8829 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8830 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super) |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8831 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter) |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8832 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8833 // Get super_klass value into rax (even if it was in rdi or rcx). |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8834 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false; |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8835 if (super_klass != rax || UseCompressedOops) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8836 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8837 mov(rax, super_klass); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8838 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8839 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8840 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8841 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8842 #ifndef PRODUCT |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8843 int* pst_counter = &SharedRuntime::_partial_subtype_ctr; |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8844 ExternalAddress pst_counter_addr((address) pst_counter); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8845 NOT_LP64( incrementl(pst_counter_addr) ); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8846 LP64_ONLY( lea(rcx, pst_counter_addr) ); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8847 LP64_ONLY( incrementl(Address(rcx, 0)) ); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8848 #endif //PRODUCT |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8849 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8850 // We will consult the secondary-super array. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8851 movptr(rdi, secondary_supers_addr); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8852 // Load the array length. (Positive movl does right thing on LP64.) |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8853 movl(rcx, Address(rdi, arrayOopDesc::length_offset_in_bytes())); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8854 // Skip to start of data. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8855 addptr(rdi, arrayOopDesc::base_offset_in_bytes(T_OBJECT)); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8856 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8857 // Scan RCX words at [RDI] for an occurrence of RAX. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8858 // Set NZ/Z based on last compare. |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8859 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8860 // not change flags (only scas instruction which is repeated sets flags). |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8861 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found. |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8862 #ifdef _LP64 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8863 // This part is tricky, as values in supers array could be 32 or 64 bit wide |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8864 // and we store values in objArrays always encoded, thus we need to encode |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8865 // the value of rax before repne. Note that rax is dead after the repne. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8866 if (UseCompressedOops) { |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8867 encode_heap_oop_not_null(rax); // Changes flags. |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8868 // The superclass is never null; it would be a basic system error if a null |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8869 // pointer were to sneak in here. Note that we have already loaded the |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8870 // Klass::super_check_offset from the super_klass in the fast path, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8871 // so if there is a null in that register, we are already in the afterlife. |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8872 testl(rax,rax); // Set Z = 0 |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8873 repne_scanl(); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8874 } else |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8875 #endif // _LP64 |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8876 { |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8877 testptr(rax,rax); // Set Z = 0 |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8878 repne_scan(); |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8879 } |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8880 // Unspill the temp. registers: |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8881 if (pushed_rdi) pop(rdi); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8882 if (pushed_rcx) pop(rcx); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8883 if (pushed_rax) pop(rax); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8884 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8885 if (set_cond_codes) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8886 // Special hack for the AD files: rdi is guaranteed non-zero. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8887 assert(!pushed_rdi, "rdi must be left non-NULL"); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8888 // Also, the condition codes are properly set Z/NZ on succeed/failure. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8889 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8890 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8891 if (L_failure == &L_fallthrough) |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8892 jccb(Assembler::notEqual, *L_failure); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8893 else jcc(Assembler::notEqual, *L_failure); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8894 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8895 // Success. Cache the super we found and proceed in triumph. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8896 movptr(super_cache_addr, super_klass); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8897 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8898 if (L_success != &L_fallthrough) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8899 jmp(*L_success); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8900 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8901 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8902 #undef IS_A_TEMP |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8903 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8904 bind(L_fallthrough); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8905 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8906 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8907 |
|
2415
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
8908 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) { |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
8909 if (VM_Version::supports_cmov()) { |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
8910 cmovl(cc, dst, src); |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
8911 } else { |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
8912 Label L; |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
8913 jccb(negate_condition(cc), L); |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
8914 movl(dst, src); |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
8915 bind(L); |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
8916 } |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
8917 } |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
8918 |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
8919 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) { |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
8920 if (VM_Version::supports_cmov()) { |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
8921 cmovl(cc, dst, src); |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
8922 } else { |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
8923 Label L; |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
8924 jccb(negate_condition(cc), L); |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
8925 movl(dst, src); |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
8926 bind(L); |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
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changeset
|
8927 } |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
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2404
diff
changeset
|
8928 } |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
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2404
diff
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|
8929 |
| 0 | 8930 void MacroAssembler::verify_oop(Register reg, const char* s) { |
| 8931 if (!VerifyOops) return; | |
| 304 | 8932 |
| 0 | 8933 // Pass register number to verify_oop_subroutine |
| 8934 char* b = new char[strlen(s) + 50]; | |
| 8935 sprintf(b, "verify_oop: %s: %s", reg->name(), s); | |
| 1583 | 8936 #ifdef _LP64 |
| 8937 push(rscratch1); // save r10, trashed by movptr() | |
| 8938 #endif | |
| 304 | 8939 push(rax); // save rax, |
| 8940 push(reg); // pass register argument | |
| 0 | 8941 ExternalAddress buffer((address) b); |
| 304 | 8942 // avoid using pushptr, as it modifies scratch registers |
| 8943 // and our contract is not to modify anything | |
| 8944 movptr(rax, buffer.addr()); | |
| 8945 push(rax); | |
| 0 | 8946 // call indirectly to solve generation ordering problem |
| 8947 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); | |
| 8948 call(rax); | |
| 1583 | 8949 // Caller pops the arguments (oop, message) and restores rax, r10 |
| 0 | 8950 } |
| 8951 | |
| 8952 | |
|
665
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diff
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|
8953 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr, |
|
c89f86385056
6814659: separable cleanups and subroutines for 6655638
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|
8954 Register tmp, |
|
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|
8955 int offset) { |
|
622
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|
8956 intptr_t value = *delayed_value_addr; |
|
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|
8957 if (value != 0) |
|
665
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|
8958 return RegisterOrConstant(value + offset); |
|
622
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|
8959 |
|
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|
8960 // load indirectly to solve generation ordering problem |
|
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|
8961 movptr(tmp, ExternalAddress((address) delayed_value_addr)); |
|
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|
8962 |
|
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|
8963 #ifdef ASSERT |
|
1793
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6939224: MethodHandle.invokeGeneric needs to perform the correct set of conversions
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|
8964 { Label L; |
|
d257356e35f0
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diff
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|
8965 testptr(tmp, tmp); |
|
d257356e35f0
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|
8966 if (WizardMode) { |
|
d257356e35f0
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|
8967 jcc(Assembler::notZero, L); |
|
d257356e35f0
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|
8968 char* buf = new char[40]; |
|
d257356e35f0
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|
8969 sprintf(buf, "DelayedValue="INTPTR_FORMAT, delayed_value_addr[1]); |
|
d257356e35f0
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jrose
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|
8970 stop(buf); |
|
d257356e35f0
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jrose
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diff
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|
8971 } else { |
|
d257356e35f0
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|
8972 jccb(Assembler::notZero, L); |
|
d257356e35f0
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jrose
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|
8973 hlt(); |
|
d257356e35f0
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jrose
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1763
diff
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|
8974 } |
|
d257356e35f0
6939224: MethodHandle.invokeGeneric needs to perform the correct set of conversions
jrose
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1763
diff
changeset
|
8975 bind(L); |
|
d257356e35f0
6939224: MethodHandle.invokeGeneric needs to perform the correct set of conversions
jrose
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|
8976 } |
|
622
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|
8977 #endif |
|
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
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|
8978 |
|
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|
8979 if (offset != 0) |
|
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|
8980 addptr(tmp, offset); |
|
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|
8981 |
|
665
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|
8982 return RegisterOrConstant(tmp); |
|
622
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|
8983 } |
|
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|
8984 |
|
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|
8985 |
| 710 | 8986 // registers on entry: |
| 8987 // - rax ('check' register): required MethodType | |
| 8988 // - rcx: method handle | |
| 8989 // - rdx, rsi, or ?: killable temp | |
| 8990 void MacroAssembler::check_method_handle_type(Register mtype_reg, Register mh_reg, | |
| 8991 Register temp_reg, | |
| 8992 Label& wrong_method_type) { | |
|
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diff
changeset
|
8993 Address type_addr(mh_reg, delayed_value(java_lang_invoke_MethodHandle::type_offset_in_bytes, temp_reg)); |
| 710 | 8994 // compare method type against that of the receiver |
| 1846 | 8995 if (UseCompressedOops) { |
| 8996 load_heap_oop(temp_reg, type_addr); | |
| 8997 cmpptr(mtype_reg, temp_reg); | |
| 8998 } else { | |
| 8999 cmpptr(mtype_reg, type_addr); | |
| 9000 } | |
| 710 | 9001 jcc(Assembler::notEqual, wrong_method_type); |
| 9002 } | |
| 9003 | |
| 9004 | |
| 9005 // A method handle has a "vmslots" field which gives the size of its | |
| 9006 // argument list in JVM stack slots. This field is either located directly | |
| 9007 // in every method handle, or else is indirectly accessed through the | |
| 9008 // method handle's MethodType. This macro hides the distinction. | |
| 9009 void MacroAssembler::load_method_handle_vmslots(Register vmslots_reg, Register mh_reg, | |
| 9010 Register temp_reg) { | |
| 1503 | 9011 assert_different_registers(vmslots_reg, mh_reg, temp_reg); |
| 710 | 9012 // load mh.type.form.vmslots |
| 3938 | 9013 Register temp2_reg = vmslots_reg; |
| 9014 load_heap_oop(temp2_reg, Address(mh_reg, delayed_value(java_lang_invoke_MethodHandle::type_offset_in_bytes, temp_reg))); | |
| 9015 load_heap_oop(temp2_reg, Address(temp2_reg, delayed_value(java_lang_invoke_MethodType::form_offset_in_bytes, temp_reg))); | |
| 9016 movl(vmslots_reg, Address(temp2_reg, delayed_value(java_lang_invoke_MethodTypeForm::vmslots_offset_in_bytes, temp_reg))); | |
| 710 | 9017 } |
| 9018 | |
| 9019 | |
| 9020 // registers on entry: | |
| 9021 // - rcx: method handle | |
| 9022 // - rdx: killable temp (interpreted only) | |
| 9023 // - rax: killable temp (compiled only) | |
| 9024 void MacroAssembler::jump_to_method_handle_entry(Register mh_reg, Register temp_reg) { | |
| 9025 assert(mh_reg == rcx, "caller must put MH object in rcx"); | |
| 9026 assert_different_registers(mh_reg, temp_reg); | |
| 9027 | |
| 9028 // pick out the interpreted side of the handler | |
| 1846 | 9029 // NOTE: vmentry is not an oop! |
|
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2320
diff
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|
9030 movptr(temp_reg, Address(mh_reg, delayed_value(java_lang_invoke_MethodHandle::vmentry_offset_in_bytes, temp_reg))); |
| 710 | 9031 |
| 9032 // off we go... | |
| 9033 jmp(Address(temp_reg, MethodHandleEntry::from_interpreted_entry_offset_in_bytes())); | |
| 9034 | |
| 9035 // for the various stubs which take control at this point, | |
| 9036 // see MethodHandles::generate_method_handle_stub | |
| 9037 } | |
| 9038 | |
| 9039 | |
| 9040 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot, | |
| 9041 int extra_slot_offset) { | |
| 9042 // cf. TemplateTable::prepare_invoke(), if (load_receiver). | |
| 1506 | 9043 int stackElementSize = Interpreter::stackElementSize; |
| 710 | 9044 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0); |
| 9045 #ifdef ASSERT | |
| 9046 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1); | |
| 9047 assert(offset1 - offset == stackElementSize, "correct arithmetic"); | |
| 9048 #endif | |
| 9049 Register scale_reg = noreg; | |
| 9050 Address::ScaleFactor scale_factor = Address::no_scale; | |
| 9051 if (arg_slot.is_constant()) { | |
| 9052 offset += arg_slot.as_constant() * stackElementSize; | |
| 9053 } else { | |
| 9054 scale_reg = arg_slot.as_register(); | |
| 9055 scale_factor = Address::times(stackElementSize); | |
| 9056 } | |
| 9057 offset += wordSize; // return PC is on stack | |
| 9058 return Address(rsp, scale_reg, scale_factor, offset); | |
| 9059 } | |
| 9060 | |
| 9061 | |
| 0 | 9062 void MacroAssembler::verify_oop_addr(Address addr, const char* s) { |
| 9063 if (!VerifyOops) return; | |
| 304 | 9064 |
| 0 | 9065 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord); |
| 9066 // Pass register number to verify_oop_subroutine | |
| 9067 char* b = new char[strlen(s) + 50]; | |
| 9068 sprintf(b, "verify_oop_addr: %s", s); | |
| 304 | 9069 |
| 1583 | 9070 #ifdef _LP64 |
| 9071 push(rscratch1); // save r10, trashed by movptr() | |
| 9072 #endif | |
| 304 | 9073 push(rax); // save rax, |
| 0 | 9074 // addr may contain rsp so we will have to adjust it based on the push |
|
2464
d86923d96dca
7034967: C1: assert(false) failed: error (assembler_sparc.cpp:2043)
iveresov
parents:
2415
diff
changeset
|
9075 // we just did (and on 64 bit we do two pushes) |
| 304 | 9076 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which |
| 9077 // stores rax into addr which is backwards of what was intended. | |
| 0 | 9078 if (addr.uses(rsp)) { |
| 304 | 9079 lea(rax, addr); |
|
2464
d86923d96dca
7034967: C1: assert(false) failed: error (assembler_sparc.cpp:2043)
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parents:
2415
diff
changeset
|
9080 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord)); |
| 0 | 9081 } else { |
| 304 | 9082 pushptr(addr); |
| 9083 } | |
| 9084 | |
| 0 | 9085 ExternalAddress buffer((address) b); |
| 9086 // pass msg argument | |
| 304 | 9087 // avoid using pushptr, as it modifies scratch registers |
| 9088 // and our contract is not to modify anything | |
| 9089 movptr(rax, buffer.addr()); | |
| 9090 push(rax); | |
| 9091 | |
| 0 | 9092 // call indirectly to solve generation ordering problem |
| 9093 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); | |
| 9094 call(rax); | |
| 1583 | 9095 // Caller pops the arguments (addr, message) and restores rax, r10. |
| 0 | 9096 } |
| 9097 | |
| 304 | 9098 void MacroAssembler::verify_tlab() { |
| 9099 #ifdef ASSERT | |
| 9100 if (UseTLAB && VerifyOops) { | |
| 9101 Label next, ok; | |
| 9102 Register t1 = rsi; | |
| 9103 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread); | |
| 9104 | |
| 9105 push(t1); | |
| 9106 NOT_LP64(push(thread_reg)); | |
| 9107 NOT_LP64(get_thread(thread_reg)); | |
| 9108 | |
| 9109 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); | |
| 9110 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); | |
| 9111 jcc(Assembler::aboveEqual, next); | |
| 9112 stop("assert(top >= start)"); | |
| 9113 should_not_reach_here(); | |
| 9114 | |
| 9115 bind(next); | |
| 9116 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); | |
| 9117 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); | |
| 9118 jcc(Assembler::aboveEqual, ok); | |
| 9119 stop("assert(top <= end)"); | |
| 9120 should_not_reach_here(); | |
| 9121 | |
| 9122 bind(ok); | |
| 9123 NOT_LP64(pop(thread_reg)); | |
| 9124 pop(t1); | |
| 9125 } | |
| 9126 #endif | |
| 9127 } | |
| 0 | 9128 |
| 9129 class ControlWord { | |
| 9130 public: | |
| 9131 int32_t _value; | |
| 9132 | |
| 9133 int rounding_control() const { return (_value >> 10) & 3 ; } | |
| 9134 int precision_control() const { return (_value >> 8) & 3 ; } | |
| 9135 bool precision() const { return ((_value >> 5) & 1) != 0; } | |
| 9136 bool underflow() const { return ((_value >> 4) & 1) != 0; } | |
| 9137 bool overflow() const { return ((_value >> 3) & 1) != 0; } | |
| 9138 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } | |
| 9139 bool denormalized() const { return ((_value >> 1) & 1) != 0; } | |
| 9140 bool invalid() const { return ((_value >> 0) & 1) != 0; } | |
| 9141 | |
| 9142 void print() const { | |
| 9143 // rounding control | |
| 9144 const char* rc; | |
| 9145 switch (rounding_control()) { | |
| 9146 case 0: rc = "round near"; break; | |
| 9147 case 1: rc = "round down"; break; | |
| 9148 case 2: rc = "round up "; break; | |
| 9149 case 3: rc = "chop "; break; | |
| 9150 }; | |
| 9151 // precision control | |
| 9152 const char* pc; | |
| 9153 switch (precision_control()) { | |
| 9154 case 0: pc = "24 bits "; break; | |
| 9155 case 1: pc = "reserved"; break; | |
| 9156 case 2: pc = "53 bits "; break; | |
| 9157 case 3: pc = "64 bits "; break; | |
| 9158 }; | |
| 9159 // flags | |
| 9160 char f[9]; | |
| 9161 f[0] = ' '; | |
| 9162 f[1] = ' '; | |
| 9163 f[2] = (precision ()) ? 'P' : 'p'; | |
| 9164 f[3] = (underflow ()) ? 'U' : 'u'; | |
| 9165 f[4] = (overflow ()) ? 'O' : 'o'; | |
| 9166 f[5] = (zero_divide ()) ? 'Z' : 'z'; | |
| 9167 f[6] = (denormalized()) ? 'D' : 'd'; | |
| 9168 f[7] = (invalid ()) ? 'I' : 'i'; | |
| 9169 f[8] = '\x0'; | |
| 9170 // output | |
| 9171 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc); | |
| 9172 } | |
| 9173 | |
| 9174 }; | |
| 9175 | |
| 9176 class StatusWord { | |
| 9177 public: | |
| 9178 int32_t _value; | |
| 9179 | |
| 9180 bool busy() const { return ((_value >> 15) & 1) != 0; } | |
| 9181 bool C3() const { return ((_value >> 14) & 1) != 0; } | |
| 9182 bool C2() const { return ((_value >> 10) & 1) != 0; } | |
| 9183 bool C1() const { return ((_value >> 9) & 1) != 0; } | |
| 9184 bool C0() const { return ((_value >> 8) & 1) != 0; } | |
| 9185 int top() const { return (_value >> 11) & 7 ; } | |
| 9186 bool error_status() const { return ((_value >> 7) & 1) != 0; } | |
| 9187 bool stack_fault() const { return ((_value >> 6) & 1) != 0; } | |
| 9188 bool precision() const { return ((_value >> 5) & 1) != 0; } | |
| 9189 bool underflow() const { return ((_value >> 4) & 1) != 0; } | |
| 9190 bool overflow() const { return ((_value >> 3) & 1) != 0; } | |
| 9191 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } | |
| 9192 bool denormalized() const { return ((_value >> 1) & 1) != 0; } | |
| 9193 bool invalid() const { return ((_value >> 0) & 1) != 0; } | |
| 9194 | |
| 9195 void print() const { | |
| 9196 // condition codes | |
| 9197 char c[5]; | |
| 9198 c[0] = (C3()) ? '3' : '-'; | |
| 9199 c[1] = (C2()) ? '2' : '-'; | |
| 9200 c[2] = (C1()) ? '1' : '-'; | |
| 9201 c[3] = (C0()) ? '0' : '-'; | |
| 9202 c[4] = '\x0'; | |
| 9203 // flags | |
| 9204 char f[9]; | |
| 9205 f[0] = (error_status()) ? 'E' : '-'; | |
| 9206 f[1] = (stack_fault ()) ? 'S' : '-'; | |
| 9207 f[2] = (precision ()) ? 'P' : '-'; | |
| 9208 f[3] = (underflow ()) ? 'U' : '-'; | |
| 9209 f[4] = (overflow ()) ? 'O' : '-'; | |
| 9210 f[5] = (zero_divide ()) ? 'Z' : '-'; | |
| 9211 f[6] = (denormalized()) ? 'D' : '-'; | |
| 9212 f[7] = (invalid ()) ? 'I' : '-'; | |
| 9213 f[8] = '\x0'; | |
| 9214 // output | |
| 9215 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top()); | |
| 9216 } | |
| 9217 | |
| 9218 }; | |
| 9219 | |
| 9220 class TagWord { | |
| 9221 public: | |
| 9222 int32_t _value; | |
| 9223 | |
| 9224 int tag_at(int i) const { return (_value >> (i*2)) & 3; } | |
| 9225 | |
| 9226 void print() const { | |
| 9227 printf("%04x", _value & 0xFFFF); | |
| 9228 } | |
| 9229 | |
| 9230 }; | |
| 9231 | |
| 9232 class FPU_Register { | |
| 9233 public: | |
| 9234 int32_t _m0; | |
| 9235 int32_t _m1; | |
| 9236 int16_t _ex; | |
| 9237 | |
| 9238 bool is_indefinite() const { | |
| 9239 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0; | |
| 9240 } | |
| 9241 | |
| 9242 void print() const { | |
| 9243 char sign = (_ex < 0) ? '-' : '+'; | |
| 9244 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " "; | |
| 9245 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind); | |
| 9246 }; | |
| 9247 | |
| 9248 }; | |
| 9249 | |
| 9250 class FPU_State { | |
| 9251 public: | |
| 9252 enum { | |
| 9253 register_size = 10, | |
| 9254 number_of_registers = 8, | |
| 9255 register_mask = 7 | |
| 9256 }; | |
| 9257 | |
| 9258 ControlWord _control_word; | |
| 9259 StatusWord _status_word; | |
| 9260 TagWord _tag_word; | |
| 9261 int32_t _error_offset; | |
| 9262 int32_t _error_selector; | |
| 9263 int32_t _data_offset; | |
| 9264 int32_t _data_selector; | |
| 9265 int8_t _register[register_size * number_of_registers]; | |
| 9266 | |
| 9267 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); } | |
| 9268 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; } | |
| 9269 | |
| 9270 const char* tag_as_string(int tag) const { | |
| 9271 switch (tag) { | |
| 9272 case 0: return "valid"; | |
| 9273 case 1: return "zero"; | |
| 9274 case 2: return "special"; | |
| 9275 case 3: return "empty"; | |
| 9276 } | |
|
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1369
diff
changeset
|
9277 ShouldNotReachHere(); |
| 0 | 9278 return NULL; |
| 9279 } | |
| 9280 | |
| 9281 void print() const { | |
| 9282 // print computation registers | |
| 9283 { int t = _status_word.top(); | |
| 9284 for (int i = 0; i < number_of_registers; i++) { | |
| 9285 int j = (i - t) & register_mask; | |
| 9286 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j); | |
| 9287 st(j)->print(); | |
| 9288 printf(" %s\n", tag_as_string(_tag_word.tag_at(i))); | |
| 9289 } | |
| 9290 } | |
| 9291 printf("\n"); | |
| 9292 // print control registers | |
| 9293 printf("ctrl = "); _control_word.print(); printf("\n"); | |
| 9294 printf("stat = "); _status_word .print(); printf("\n"); | |
| 9295 printf("tags = "); _tag_word .print(); printf("\n"); | |
| 9296 } | |
| 9297 | |
| 9298 }; | |
| 9299 | |
| 9300 class Flag_Register { | |
| 9301 public: | |
| 9302 int32_t _value; | |
| 9303 | |
| 9304 bool overflow() const { return ((_value >> 11) & 1) != 0; } | |
| 9305 bool direction() const { return ((_value >> 10) & 1) != 0; } | |
| 9306 bool sign() const { return ((_value >> 7) & 1) != 0; } | |
| 9307 bool zero() const { return ((_value >> 6) & 1) != 0; } | |
| 9308 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; } | |
| 9309 bool parity() const { return ((_value >> 2) & 1) != 0; } | |
| 9310 bool carry() const { return ((_value >> 0) & 1) != 0; } | |
| 9311 | |
| 9312 void print() const { | |
| 9313 // flags | |
| 9314 char f[8]; | |
| 9315 f[0] = (overflow ()) ? 'O' : '-'; | |
| 9316 f[1] = (direction ()) ? 'D' : '-'; | |
| 9317 f[2] = (sign ()) ? 'S' : '-'; | |
| 9318 f[3] = (zero ()) ? 'Z' : '-'; | |
| 9319 f[4] = (auxiliary_carry()) ? 'A' : '-'; | |
| 9320 f[5] = (parity ()) ? 'P' : '-'; | |
| 9321 f[6] = (carry ()) ? 'C' : '-'; | |
| 9322 f[7] = '\x0'; | |
| 9323 // output | |
| 9324 printf("%08x flags = %s", _value, f); | |
| 9325 } | |
| 9326 | |
| 9327 }; | |
| 9328 | |
| 9329 class IU_Register { | |
| 9330 public: | |
| 9331 int32_t _value; | |
| 9332 | |
| 9333 void print() const { | |
| 9334 printf("%08x %11d", _value, _value); | |
| 9335 } | |
| 9336 | |
| 9337 }; | |
| 9338 | |
| 9339 class IU_State { | |
| 9340 public: | |
| 9341 Flag_Register _eflags; | |
| 9342 IU_Register _rdi; | |
| 9343 IU_Register _rsi; | |
| 9344 IU_Register _rbp; | |
| 9345 IU_Register _rsp; | |
| 9346 IU_Register _rbx; | |
| 9347 IU_Register _rdx; | |
| 9348 IU_Register _rcx; | |
| 9349 IU_Register _rax; | |
| 9350 | |
| 9351 void print() const { | |
| 9352 // computation registers | |
| 9353 printf("rax, = "); _rax.print(); printf("\n"); | |
| 9354 printf("rbx, = "); _rbx.print(); printf("\n"); | |
| 9355 printf("rcx = "); _rcx.print(); printf("\n"); | |
| 9356 printf("rdx = "); _rdx.print(); printf("\n"); | |
| 9357 printf("rdi = "); _rdi.print(); printf("\n"); | |
| 9358 printf("rsi = "); _rsi.print(); printf("\n"); | |
| 9359 printf("rbp, = "); _rbp.print(); printf("\n"); | |
| 9360 printf("rsp = "); _rsp.print(); printf("\n"); | |
| 9361 printf("\n"); | |
| 9362 // control registers | |
| 9363 printf("flgs = "); _eflags.print(); printf("\n"); | |
| 9364 } | |
| 9365 }; | |
| 9366 | |
| 9367 | |
| 9368 class CPU_State { | |
| 9369 public: | |
| 9370 FPU_State _fpu_state; | |
| 9371 IU_State _iu_state; | |
| 9372 | |
| 9373 void print() const { | |
| 9374 printf("--------------------------------------------------\n"); | |
| 9375 _iu_state .print(); | |
| 9376 printf("\n"); | |
| 9377 _fpu_state.print(); | |
| 9378 printf("--------------------------------------------------\n"); | |
| 9379 } | |
| 9380 | |
| 9381 }; | |
| 9382 | |
| 9383 | |
| 9384 static void _print_CPU_state(CPU_State* state) { | |
| 9385 state->print(); | |
| 9386 }; | |
| 9387 | |
| 9388 | |
| 9389 void MacroAssembler::print_CPU_state() { | |
| 9390 push_CPU_state(); | |
| 304 | 9391 push(rsp); // pass CPU state |
| 0 | 9392 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state))); |
| 304 | 9393 addptr(rsp, wordSize); // discard argument |
| 0 | 9394 pop_CPU_state(); |
| 9395 } | |
| 9396 | |
| 9397 | |
| 9398 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) { | |
| 9399 static int counter = 0; | |
| 9400 FPU_State* fs = &state->_fpu_state; | |
| 9401 counter++; | |
| 9402 // For leaf calls, only verify that the top few elements remain empty. | |
| 9403 // We only need 1 empty at the top for C2 code. | |
| 9404 if( stack_depth < 0 ) { | |
| 9405 if( fs->tag_for_st(7) != 3 ) { | |
| 9406 printf("FPR7 not empty\n"); | |
| 9407 state->print(); | |
| 9408 assert(false, "error"); | |
| 9409 return false; | |
| 9410 } | |
| 9411 return true; // All other stack states do not matter | |
| 9412 } | |
| 9413 | |
| 9414 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std, | |
| 9415 "bad FPU control word"); | |
| 9416 | |
| 9417 // compute stack depth | |
| 9418 int i = 0; | |
| 9419 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++; | |
| 9420 int d = i; | |
| 9421 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++; | |
| 9422 // verify findings | |
| 9423 if (i != FPU_State::number_of_registers) { | |
| 9424 // stack not contiguous | |
| 9425 printf("%s: stack not contiguous at ST%d\n", s, i); | |
| 9426 state->print(); | |
| 9427 assert(false, "error"); | |
| 9428 return false; | |
| 9429 } | |
| 9430 // check if computed stack depth corresponds to expected stack depth | |
| 9431 if (stack_depth < 0) { | |
| 9432 // expected stack depth is -stack_depth or less | |
| 9433 if (d > -stack_depth) { | |
| 9434 // too many elements on the stack | |
| 9435 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d); | |
| 9436 state->print(); | |
| 9437 assert(false, "error"); | |
| 9438 return false; | |
| 9439 } | |
| 9440 } else { | |
| 9441 // expected stack depth is stack_depth | |
| 9442 if (d != stack_depth) { | |
| 9443 // wrong stack depth | |
| 9444 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d); | |
| 9445 state->print(); | |
| 9446 assert(false, "error"); | |
| 9447 return false; | |
| 9448 } | |
| 9449 } | |
| 9450 // everything is cool | |
| 9451 return true; | |
| 9452 } | |
| 9453 | |
| 9454 | |
| 9455 void MacroAssembler::verify_FPU(int stack_depth, const char* s) { | |
| 9456 if (!VerifyFPU) return; | |
| 9457 push_CPU_state(); | |
| 304 | 9458 push(rsp); // pass CPU state |
| 0 | 9459 ExternalAddress msg((address) s); |
| 9460 // pass message string s | |
| 9461 pushptr(msg.addr()); | |
| 304 | 9462 push(stack_depth); // pass stack depth |
| 0 | 9463 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU))); |
| 304 | 9464 addptr(rsp, 3 * wordSize); // discard arguments |
| 0 | 9465 // check for error |
| 9466 { Label L; | |
| 9467 testl(rax, rax); | |
| 9468 jcc(Assembler::notZero, L); | |
| 9469 int3(); // break if error condition | |
| 9470 bind(L); | |
| 9471 } | |
| 9472 pop_CPU_state(); | |
| 9473 } | |
| 9474 | |
| 304 | 9475 void MacroAssembler::load_klass(Register dst, Register src) { |
| 9476 #ifdef _LP64 | |
| 9477 if (UseCompressedOops) { | |
| 9478 movl(dst, Address(src, oopDesc::klass_offset_in_bytes())); | |
| 9479 decode_heap_oop_not_null(dst); | |
| 9480 } else | |
| 9481 #endif | |
| 9482 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes())); | |
| 9483 } | |
| 9484 | |
| 9485 void MacroAssembler::load_prototype_header(Register dst, Register src) { | |
| 9486 #ifdef _LP64 | |
| 9487 if (UseCompressedOops) { | |
|
642
660978a2a31a
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624
diff
changeset
|
9488 assert (Universe::heap() != NULL, "java heap should be initialized"); |
| 304 | 9489 movl(dst, Address(src, oopDesc::klass_offset_in_bytes())); |
|
642
660978a2a31a
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diff
changeset
|
9490 if (Universe::narrow_oop_shift() != 0) { |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
9491 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
9492 if (LogMinObjAlignmentInBytes == Address::times_8) { |
|
4762
069ab3f976d3
7118863: Move sizeof(klassOopDesc) into the *Klass::*_offset_in_bytes() functions
stefank
parents:
4761
diff
changeset
|
9493 movq(dst, Address(r12_heapbase, dst, Address::times_8, Klass::prototype_header_offset())); |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
9494 } else { |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
9495 // OK to use shift since we don't need to preserve flags. |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
9496 shlq(dst, LogMinObjAlignmentInBytes); |
|
4762
069ab3f976d3
7118863: Move sizeof(klassOopDesc) into the *Klass::*_offset_in_bytes() functions
stefank
parents:
4761
diff
changeset
|
9497 movq(dst, Address(r12_heapbase, dst, Address::times_1, Klass::prototype_header_offset())); |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
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1513
diff
changeset
|
9498 } |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9499 } else { |
|
4762
069ab3f976d3
7118863: Move sizeof(klassOopDesc) into the *Klass::*_offset_in_bytes() functions
stefank
parents:
4761
diff
changeset
|
9500 movq(dst, Address(dst, Klass::prototype_header_offset())); |
|
642
660978a2a31a
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kvn
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624
diff
changeset
|
9501 } |
| 304 | 9502 } else |
| 9503 #endif | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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parents:
624
diff
changeset
|
9504 { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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624
diff
changeset
|
9505 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes())); |
|
4762
069ab3f976d3
7118863: Move sizeof(klassOopDesc) into the *Klass::*_offset_in_bytes() functions
stefank
parents:
4761
diff
changeset
|
9506 movptr(dst, Address(dst, Klass::prototype_header_offset())); |
|
642
660978a2a31a
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kvn
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624
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|
9507 } |
| 304 | 9508 } |
| 9509 | |
| 9510 void MacroAssembler::store_klass(Register dst, Register src) { | |
| 9511 #ifdef _LP64 | |
| 9512 if (UseCompressedOops) { | |
| 9513 encode_heap_oop_not_null(src); | |
| 9514 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src); | |
| 9515 } else | |
| 9516 #endif | |
| 9517 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src); | |
| 9518 } | |
| 9519 | |
| 1846 | 9520 void MacroAssembler::load_heap_oop(Register dst, Address src) { |
| 9521 #ifdef _LP64 | |
| 9522 if (UseCompressedOops) { | |
| 9523 movl(dst, src); | |
| 9524 decode_heap_oop(dst); | |
| 9525 } else | |
| 9526 #endif | |
| 9527 movptr(dst, src); | |
| 9528 } | |
| 9529 | |
|
2464
d86923d96dca
7034967: C1: assert(false) failed: error (assembler_sparc.cpp:2043)
iveresov
parents:
2415
diff
changeset
|
9530 // Doesn't do verfication, generates fixed size code |
|
d86923d96dca
7034967: C1: assert(false) failed: error (assembler_sparc.cpp:2043)
iveresov
parents:
2415
diff
changeset
|
9531 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) { |
|
d86923d96dca
7034967: C1: assert(false) failed: error (assembler_sparc.cpp:2043)
iveresov
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2415
diff
changeset
|
9532 #ifdef _LP64 |
|
d86923d96dca
7034967: C1: assert(false) failed: error (assembler_sparc.cpp:2043)
iveresov
parents:
2415
diff
changeset
|
9533 if (UseCompressedOops) { |
|
d86923d96dca
7034967: C1: assert(false) failed: error (assembler_sparc.cpp:2043)
iveresov
parents:
2415
diff
changeset
|
9534 movl(dst, src); |
|
d86923d96dca
7034967: C1: assert(false) failed: error (assembler_sparc.cpp:2043)
iveresov
parents:
2415
diff
changeset
|
9535 decode_heap_oop_not_null(dst); |
|
d86923d96dca
7034967: C1: assert(false) failed: error (assembler_sparc.cpp:2043)
iveresov
parents:
2415
diff
changeset
|
9536 } else |
|
d86923d96dca
7034967: C1: assert(false) failed: error (assembler_sparc.cpp:2043)
iveresov
parents:
2415
diff
changeset
|
9537 #endif |
|
d86923d96dca
7034967: C1: assert(false) failed: error (assembler_sparc.cpp:2043)
iveresov
parents:
2415
diff
changeset
|
9538 movptr(dst, src); |
|
d86923d96dca
7034967: C1: assert(false) failed: error (assembler_sparc.cpp:2043)
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parents:
2415
diff
changeset
|
9539 } |
|
d86923d96dca
7034967: C1: assert(false) failed: error (assembler_sparc.cpp:2043)
iveresov
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2415
diff
changeset
|
9540 |
| 1846 | 9541 void MacroAssembler::store_heap_oop(Address dst, Register src) { |
| 9542 #ifdef _LP64 | |
| 9543 if (UseCompressedOops) { | |
| 9544 assert(!dst.uses(src), "not enough registers"); | |
| 9545 encode_heap_oop(src); | |
| 9546 movl(dst, src); | |
| 9547 } else | |
| 9548 #endif | |
| 9549 movptr(dst, src); | |
| 9550 } | |
| 9551 | |
| 9552 // Used for storing NULLs. | |
| 9553 void MacroAssembler::store_heap_oop_null(Address dst) { | |
| 9554 #ifdef _LP64 | |
| 9555 if (UseCompressedOops) { | |
| 9556 movl(dst, (int32_t)NULL_WORD); | |
| 9557 } else { | |
| 9558 movslq(dst, (int32_t)NULL_WORD); | |
| 9559 } | |
| 9560 #else | |
| 9561 movl(dst, (int32_t)NULL_WORD); | |
| 9562 #endif | |
| 9563 } | |
| 9564 | |
| 304 | 9565 #ifdef _LP64 |
| 9566 void MacroAssembler::store_klass_gap(Register dst, Register src) { | |
| 9567 if (UseCompressedOops) { | |
| 9568 // Store to klass gap in destination | |
| 9569 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src); | |
| 9570 } | |
| 9571 } | |
| 9572 | |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
9573 #ifdef ASSERT |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
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parents:
1583
diff
changeset
|
9574 void MacroAssembler::verify_heapbase(const char* msg) { |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
9575 assert (UseCompressedOops, "should be compressed"); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
9576 assert (Universe::heap() != NULL, "java heap should be initialized"); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
9577 if (CheckCompressedOops) { |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
9578 Label ok; |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
9579 push(rscratch1); // cmpptr trashes rscratch1 |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
9580 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_oop_base_addr())); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
9581 jcc(Assembler::equal, ok); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
9582 stop(msg); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
9583 bind(ok); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
9584 pop(rscratch1); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
9585 } |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
9586 } |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
9587 #endif |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
9588 |
| 304 | 9589 // Algorithm must match oop.inline.hpp encode_heap_oop. |
| 9590 void MacroAssembler::encode_heap_oop(Register r) { | |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
9591 #ifdef ASSERT |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
9592 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?"); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
9593 #endif |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
9594 verify_oop(r, "broken oop in encode_heap_oop"); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9595 if (Universe::narrow_oop_base() == NULL) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9596 if (Universe::narrow_oop_shift() != 0) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9597 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9598 shrq(r, LogMinObjAlignmentInBytes); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9599 } |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9600 return; |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9601 } |
| 304 | 9602 testq(r, r); |
| 9603 cmovq(Assembler::equal, r, r12_heapbase); | |
| 9604 subq(r, r12_heapbase); | |
| 9605 shrq(r, LogMinObjAlignmentInBytes); | |
| 9606 } | |
| 9607 | |
| 9608 void MacroAssembler::encode_heap_oop_not_null(Register r) { | |
| 0 | 9609 #ifdef ASSERT |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
9610 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?"); |
| 304 | 9611 if (CheckCompressedOops) { |
| 0 | 9612 Label ok; |
| 304 | 9613 testq(r, r); |
| 9614 jcc(Assembler::notEqual, ok); | |
| 9615 stop("null oop passed to encode_heap_oop_not_null"); | |
| 0 | 9616 bind(ok); |
| 304 | 9617 } |
| 9618 #endif | |
| 9619 verify_oop(r, "broken oop in encode_heap_oop_not_null"); | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9620 if (Universe::narrow_oop_base() != NULL) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9621 subq(r, r12_heapbase); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9622 } |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9623 if (Universe::narrow_oop_shift() != 0) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9624 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9625 shrq(r, LogMinObjAlignmentInBytes); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9626 } |
| 304 | 9627 } |
| 9628 | |
| 9629 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) { | |
| 9630 #ifdef ASSERT | |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
9631 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?"); |
| 304 | 9632 if (CheckCompressedOops) { |
| 9633 Label ok; | |
| 9634 testq(src, src); | |
| 9635 jcc(Assembler::notEqual, ok); | |
| 9636 stop("null oop passed to encode_heap_oop_not_null2"); | |
| 9637 bind(ok); | |
| 0 | 9638 } |
| 9639 #endif | |
| 304 | 9640 verify_oop(src, "broken oop in encode_heap_oop_not_null2"); |
| 9641 if (dst != src) { | |
| 9642 movq(dst, src); | |
| 9643 } | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9644 if (Universe::narrow_oop_base() != NULL) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9645 subq(dst, r12_heapbase); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9646 } |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9647 if (Universe::narrow_oop_shift() != 0) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9648 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9649 shrq(dst, LogMinObjAlignmentInBytes); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9650 } |
| 304 | 9651 } |
| 9652 | |
| 9653 void MacroAssembler::decode_heap_oop(Register r) { | |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
9654 #ifdef ASSERT |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
9655 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?"); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
9656 #endif |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9657 if (Universe::narrow_oop_base() == NULL) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9658 if (Universe::narrow_oop_shift() != 0) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9659 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9660 shlq(r, LogMinObjAlignmentInBytes); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9661 } |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
9662 } else { |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
9663 Label done; |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
9664 shlq(r, LogMinObjAlignmentInBytes); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
9665 jccb(Assembler::equal, done); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
9666 addq(r, r12_heapbase); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
9667 bind(done); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
9668 } |
| 304 | 9669 verify_oop(r, "broken oop in decode_heap_oop"); |
| 9670 } | |
| 9671 | |
| 9672 void MacroAssembler::decode_heap_oop_not_null(Register r) { | |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
9673 // Note: it will change flags |
| 304 | 9674 assert (UseCompressedOops, "should only be used for compressed headers"); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9675 assert (Universe::heap() != NULL, "java heap should be initialized"); |
| 304 | 9676 // Cannot assert, unverified entry point counts instructions (see .ad file) |
| 9677 // vtableStubs also counts instructions in pd_code_size_limit. | |
| 9678 // Also do not verify_oop as this is called by verify_oop. | |
|
898
60fea60a6db5
6864914: SPECjvm2008 produces invalid result with zero based Compressed Oops
kvn
parents:
845
diff
changeset
|
9679 if (Universe::narrow_oop_shift() != 0) { |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
9680 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
9681 shlq(r, LogMinObjAlignmentInBytes); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
9682 if (Universe::narrow_oop_base() != NULL) { |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
9683 addq(r, r12_heapbase); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
9684 } |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9685 } else { |
|
898
60fea60a6db5
6864914: SPECjvm2008 produces invalid result with zero based Compressed Oops
kvn
parents:
845
diff
changeset
|
9686 assert (Universe::narrow_oop_base() == NULL, "sanity"); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9687 } |
| 304 | 9688 } |
| 9689 | |
| 9690 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) { | |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
9691 // Note: it will change flags |
| 304 | 9692 assert (UseCompressedOops, "should only be used for compressed headers"); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9693 assert (Universe::heap() != NULL, "java heap should be initialized"); |
| 304 | 9694 // Cannot assert, unverified entry point counts instructions (see .ad file) |
| 9695 // vtableStubs also counts instructions in pd_code_size_limit. | |
| 9696 // Also do not verify_oop as this is called by verify_oop. | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9697 if (Universe::narrow_oop_shift() != 0) { |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
9698 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
9699 if (LogMinObjAlignmentInBytes == Address::times_8) { |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
9700 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0)); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
9701 } else { |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
9702 if (dst != src) { |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
9703 movq(dst, src); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
9704 } |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
9705 shlq(dst, LogMinObjAlignmentInBytes); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
9706 if (Universe::narrow_oop_base() != NULL) { |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
9707 addq(dst, r12_heapbase); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
9708 } |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
9709 } |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
9710 } else { |
|
898
60fea60a6db5
6864914: SPECjvm2008 produces invalid result with zero based Compressed Oops
kvn
parents:
845
diff
changeset
|
9711 assert (Universe::narrow_oop_base() == NULL, "sanity"); |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
9712 if (dst != src) { |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
9713 movq(dst, src); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
9714 } |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9715 } |
| 304 | 9716 } |
| 9717 | |
| 9718 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) { | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9719 assert (UseCompressedOops, "should only be used for compressed headers"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9720 assert (Universe::heap() != NULL, "java heap should be initialized"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9721 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9722 int oop_index = oop_recorder()->find_index(obj); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9723 RelocationHolder rspec = oop_Relocation::spec(oop_index); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9724 mov_narrow_oop(dst, oop_index, rspec); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9725 } |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9726 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9727 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9728 assert (UseCompressedOops, "should only be used for compressed headers"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9729 assert (Universe::heap() != NULL, "java heap should be initialized"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9730 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
| 304 | 9731 int oop_index = oop_recorder()->find_index(obj); |
| 9732 RelocationHolder rspec = oop_Relocation::spec(oop_index); | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9733 mov_narrow_oop(dst, oop_index, rspec); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9734 } |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9735 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9736 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9737 assert (UseCompressedOops, "should only be used for compressed headers"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9738 assert (Universe::heap() != NULL, "java heap should be initialized"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9739 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9740 int oop_index = oop_recorder()->find_index(obj); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9741 RelocationHolder rspec = oop_Relocation::spec(oop_index); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9742 Assembler::cmp_narrow_oop(dst, oop_index, rspec); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9743 } |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9744 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9745 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9746 assert (UseCompressedOops, "should only be used for compressed headers"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9747 assert (Universe::heap() != NULL, "java heap should be initialized"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9748 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9749 int oop_index = oop_recorder()->find_index(obj); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9750 RelocationHolder rspec = oop_Relocation::spec(oop_index); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9751 Assembler::cmp_narrow_oop(dst, oop_index, rspec); |
| 304 | 9752 } |
| 9753 | |
| 9754 void MacroAssembler::reinit_heapbase() { | |
| 9755 if (UseCompressedOops) { | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9756 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_oop_base_addr())); |
| 304 | 9757 } |
| 9758 } | |
| 9759 #endif // _LP64 | |
| 0 | 9760 |
|
4947
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9761 |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9762 // C2 compiled method's prolog code. |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9763 void MacroAssembler::verified_entry(int framesize, bool stack_bang, bool fp_mode_24b) { |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9764 |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9765 // WARNING: Initial instruction MUST be 5 bytes or longer so that |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9766 // NativeJump::patch_verified_entry will be able to patch out the entry |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9767 // code safely. The push to verify stack depth is ok at 5 bytes, |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9768 // the frame allocation can be either 3 or 6 bytes. So if we don't do |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9769 // stack bang then we must use the 6 byte frame allocation even if |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9770 // we have no frame. :-( |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9771 |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9772 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9773 // Remove word for return addr |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9774 framesize -= wordSize; |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9775 |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9776 // Calls to C2R adapters often do not accept exceptional returns. |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9777 // We require that their callers must bang for them. But be careful, because |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9778 // some VM calls (such as call site linkage) can use several kilobytes of |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9779 // stack. But the stack safety zone should account for that. |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9780 // See bugs 4446381, 4468289, 4497237. |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9781 if (stack_bang) { |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9782 generate_stack_overflow_check(framesize); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9783 |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9784 // We always push rbp, so that on return to interpreter rbp, will be |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9785 // restored correctly and we can correct the stack. |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9786 push(rbp); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9787 // Remove word for ebp |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9788 framesize -= wordSize; |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9789 |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9790 // Create frame |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9791 if (framesize) { |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9792 subptr(rsp, framesize); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9793 } |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9794 } else { |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9795 // Create frame (force generation of a 4 byte immediate value) |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9796 subptr_imm32(rsp, framesize); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9797 |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9798 // Save RBP register now. |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9799 framesize -= wordSize; |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9800 movptr(Address(rsp, framesize), rbp); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9801 } |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9802 |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9803 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9804 framesize -= wordSize; |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9805 movptr(Address(rsp, framesize), (int32_t)0xbadb100d); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9806 } |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9807 |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9808 #ifndef _LP64 |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9809 // If method sets FPU control word do it now |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9810 if (fp_mode_24b) { |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9811 fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9812 } |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9813 if (UseSSE >= 2 && VerifyFPU) { |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9814 verify_FPU(0, "FPU stack must be clean on entry"); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9815 } |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9816 #endif |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9817 |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9818 #ifdef ASSERT |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9819 if (VerifyStackAtCalls) { |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9820 Label L; |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9821 push(rax); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9822 mov(rax, rsp); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9823 andptr(rax, StackAlignmentInBytes-1); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9824 cmpptr(rax, StackAlignmentInBytes-wordSize); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9825 pop(rax); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9826 jcc(Assembler::equal, L); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9827 stop("Stack is not properly aligned!"); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9828 bind(L); |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9829 } |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9830 #endif |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9831 |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9832 } |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9833 |
|
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
4770
diff
changeset
|
9834 |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9835 // IndexOf for constant substrings with size >= 8 chars |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9836 // which don't need to be loaded through stack. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9837 void MacroAssembler::string_indexofC8(Register str1, Register str2, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9838 Register cnt1, Register cnt2, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9839 int int_cnt2, Register result, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9840 XMMRegister vec, Register tmp) { |
|
4766
40c2484c09e1
7110832: ctw/.../org_apache_avalon_composition_util_StringHelper crashes the VM
kvn
parents:
4762
diff
changeset
|
9841 ShortBranchVerifier sbv(this); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9842 assert(UseSSE42Intrinsics, "SSE4.2 is required"); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9843 |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9844 // This method uses pcmpestri inxtruction with bound registers |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9845 // inputs: |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9846 // xmm - substring |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9847 // rax - substring length (elements count) |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9848 // mem - scanned string |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9849 // rdx - string length (elements count) |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9850 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts) |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9851 // outputs: |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9852 // rcx - matched index in string |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9853 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9854 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9855 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9856 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9857 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9858 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9859 // Note, inline_string_indexOf() generates checks: |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9860 // if (substr.count > string.count) return -1; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9861 // if (substr.count == 0) return 0; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9862 assert(int_cnt2 >= 8, "this code isused only for cnt2 >= 8 chars"); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9863 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9864 // Load substring. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9865 movdqu(vec, Address(str2, 0)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9866 movl(cnt2, int_cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9867 movptr(result, str1); // string addr |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9868 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9869 if (int_cnt2 > 8) { |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9870 jmpb(SCAN_TO_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9871 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9872 // Reload substr for rescan, this code |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9873 // is executed only for large substrings (> 8 chars) |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9874 bind(RELOAD_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9875 movdqu(vec, Address(str2, 0)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9876 negptr(cnt2); // Jumped here with negative cnt2, convert to positive |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
9877 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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diff
changeset
|
9878 bind(RELOAD_STR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
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diff
changeset
|
9879 // We came here after the beginning of the substring was |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
9880 // matched but the rest of it was not so we need to search |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
9881 // again. Start from the next element after the previous match. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
9882 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
9883 // cnt2 is number of substring reminding elements and |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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changeset
|
9884 // cnt1 is number of string reminding elements when cmp failed. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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|
9885 // Restored cnt1 = cnt1 - cnt2 + int_cnt2 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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changeset
|
9886 subl(cnt1, cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
9887 addl(cnt1, int_cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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changeset
|
9888 movl(cnt2, int_cnt2); // Now restore cnt2 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
9889 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
9890 decrementl(cnt1); // Shift to next element |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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changeset
|
9891 cmpl(cnt1, cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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|
9892 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring |
|
41d4973cf100
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parents:
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diff
changeset
|
9893 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
9894 addptr(result, 2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
9895 |
|
41d4973cf100
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parents:
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diff
changeset
|
9896 } // (int_cnt2 > 8) |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
9897 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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diff
changeset
|
9898 // Scan string for start of substr in 16-byte vectors |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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changeset
|
9899 bind(SCAN_TO_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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|
9900 pcmpestri(vec, Address(result, 0), 0x0d); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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|
9901 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
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diff
changeset
|
9902 subl(cnt1, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
9903 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
9904 cmpl(cnt1, cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
9905 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
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diff
changeset
|
9906 addptr(result, 16); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9907 jmpb(SCAN_TO_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9908 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9909 // Found a potential substr |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9910 bind(FOUND_CANDIDATE); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
9911 // Matched whole vector if first element matched (tmp(rcx) == 0). |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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changeset
|
9912 if (int_cnt2 == 8) { |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
9913 jccb(Assembler::overflow, RET_FOUND); // OF == 1 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
9914 } else { // int_cnt2 > 8 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
9915 jccb(Assembler::overflow, FOUND_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9916 } |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
9917 // After pcmpestri tmp(rcx) contains matched element index |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
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diff
changeset
|
9918 // Compute start addr of substr |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
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diff
changeset
|
9919 lea(result, Address(result, tmp, Address::times_2)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
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diff
changeset
|
9920 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
9921 // Make sure string is still long enough |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
9922 subl(cnt1, tmp); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
9923 cmpl(cnt1, cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
9924 if (int_cnt2 == 8) { |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
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diff
changeset
|
9925 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9926 } else { // int_cnt2 > 8 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
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diff
changeset
|
9927 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9928 } |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
9929 // Left less then substring. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9930 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9931 bind(RET_NOT_FOUND); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9932 movl(result, -1); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
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diff
changeset
|
9933 jmpb(EXIT); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9934 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9935 if (int_cnt2 > 8) { |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9936 // This code is optimized for the case when whole substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9937 // is matched if its head is matched. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9938 bind(MATCH_SUBSTR_HEAD); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9939 pcmpestri(vec, Address(result, 0), 0x0d); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
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diff
changeset
|
9940 // Reload only string if does not match |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9941 jccb(Assembler::noOverflow, RELOAD_STR); // OF == 0 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9942 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9943 Label CONT_SCAN_SUBSTR; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9944 // Compare the rest of substring (> 8 chars). |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
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diff
changeset
|
9945 bind(FOUND_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
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diff
changeset
|
9946 // First 8 chars are already matched. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9947 negptr(cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9948 addptr(cnt2, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9949 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9950 bind(SCAN_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9951 subl(cnt1, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9952 cmpl(cnt2, -8); // Do not read beyond substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9953 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9954 // Back-up strings to avoid reading beyond substring: |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9955 // cnt1 = cnt1 - cnt2 + 8 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9956 addl(cnt1, cnt2); // cnt2 is negative |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9957 addl(cnt1, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9958 movl(cnt2, 8); negptr(cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9959 bind(CONT_SCAN_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9960 if (int_cnt2 < (int)G) { |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9961 movdqu(vec, Address(str2, cnt2, Address::times_2, int_cnt2*2)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9962 pcmpestri(vec, Address(result, cnt2, Address::times_2, int_cnt2*2), 0x0d); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
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diff
changeset
|
9963 } else { |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9964 // calculate index in register to avoid integer overflow (int_cnt2*2) |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9965 movl(tmp, int_cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9966 addptr(tmp, cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9967 movdqu(vec, Address(str2, tmp, Address::times_2, 0)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9968 pcmpestri(vec, Address(result, tmp, Address::times_2, 0), 0x0d); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9969 } |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9970 // Need to reload strings pointers if not matched whole vector |
|
4766
40c2484c09e1
7110832: ctw/.../org_apache_avalon_composition_util_StringHelper crashes the VM
kvn
parents:
4762
diff
changeset
|
9971 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0 |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9972 addptr(cnt2, 8); |
|
4766
40c2484c09e1
7110832: ctw/.../org_apache_avalon_composition_util_StringHelper crashes the VM
kvn
parents:
4762
diff
changeset
|
9973 jcc(Assembler::negative, SCAN_SUBSTR); |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9974 // Fall through if found full substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9975 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9976 } // (int_cnt2 > 8) |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9977 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9978 bind(RET_FOUND); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9979 // Found result if we matched full small substring. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9980 // Compute substr offset |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9981 subptr(result, str1); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9982 shrl(result, 1); // index |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9983 bind(EXIT); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9984 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9985 } // string_indexofC8 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9986 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9987 // Small strings are loaded through stack if they cross page boundary. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9988 void MacroAssembler::string_indexof(Register str1, Register str2, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
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2262
diff
changeset
|
9989 Register cnt1, Register cnt2, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9990 int int_cnt2, Register result, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9991 XMMRegister vec, Register tmp) { |
|
4766
40c2484c09e1
7110832: ctw/.../org_apache_avalon_composition_util_StringHelper crashes the VM
kvn
parents:
4762
diff
changeset
|
9992 ShortBranchVerifier sbv(this); |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9993 assert(UseSSE42Intrinsics, "SSE4.2 is required"); |
|
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|
9994 // |
|
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|
9995 // int_cnt2 is length of small (< 8 chars) constant substring |
|
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|
9996 // or (-1) for non constant substring in which case its length |
|
41d4973cf100
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|
9997 // is in cnt2 register. |
|
41d4973cf100
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|
9998 // |
|
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|
9999 // Note, inline_string_indexOf() generates checks: |
|
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|
10000 // if (substr.count > string.count) return -1; |
|
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|
10001 // if (substr.count == 0) return 0; |
|
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|
10002 // |
|
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|
10003 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < 8), "should be != 0"); |
|
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|
10004 |
|
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|
10005 // This method uses pcmpestri inxtruction with bound registers |
|
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|
10006 // inputs: |
|
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|
10007 // xmm - substring |
|
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|
10008 // rax - substring length (elements count) |
|
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|
10009 // mem - scanned string |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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898
diff
changeset
|
10010 // rdx - string length (elements count) |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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diff
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|
10011 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts) |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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898
diff
changeset
|
10012 // outputs: |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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898
diff
changeset
|
10013 // rcx - matched index in string |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
10014 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); |
|
62001a362ce9
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898
diff
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|
10015 |
|
2320
41d4973cf100
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|
10016 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR, |
|
41d4973cf100
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|
10017 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR, |
|
41d4973cf100
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|
10018 FOUND_CANDIDATE; |
|
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|
10019 |
|
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|
10020 { //======================================================== |
|
41d4973cf100
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|
10021 // We don't know where these strings are located |
|
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|
10022 // and we can't read beyond them. Load them through stack. |
|
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|
10023 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR; |
|
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|
10024 |
|
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|
10025 movptr(tmp, rsp); // save old SP |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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|
10026 |
|
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|
10027 if (int_cnt2 > 0) { // small (< 8 chars) constant substring |
|
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|
10028 if (int_cnt2 == 1) { // One char |
|
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|
10029 load_unsigned_short(result, Address(str2, 0)); |
|
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|
10030 movdl(vec, result); // move 32 bits |
|
41d4973cf100
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|
10031 } else if (int_cnt2 == 2) { // Two chars |
|
41d4973cf100
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|
10032 movdl(vec, Address(str2, 0)); // move 32 bits |
|
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|
10033 } else if (int_cnt2 == 4) { // Four chars |
|
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|
10034 movq(vec, Address(str2, 0)); // move 64 bits |
|
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|
10035 } else { // cnt2 = { 3, 5, 6, 7 } |
|
41d4973cf100
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|
10036 // Array header size is 12 bytes in 32-bit VM |
|
41d4973cf100
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|
10037 // + 6 bytes for 3 chars == 18 bytes, |
|
41d4973cf100
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|
10038 // enough space to load vec and shift. |
|
41d4973cf100
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|
10039 assert(HeapWordSize*typeArrayKlass::header_size() >= 12,"sanity"); |
|
41d4973cf100
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|
10040 movdqu(vec, Address(str2, (int_cnt2*2)-16)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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|
10041 psrldq(vec, 16-(int_cnt2*2)); |
|
41d4973cf100
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|
10042 } |
|
41d4973cf100
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|
10043 } else { // not constant substring |
|
41d4973cf100
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|
10044 cmpl(cnt2, 8); |
|
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|
10045 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough |
|
41d4973cf100
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|
10046 |
|
41d4973cf100
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changeset
|
10047 // We can read beyond string if srt+16 does not cross page boundary |
|
41d4973cf100
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|
10048 // since heaps are aligned and mapped by pages. |
|
41d4973cf100
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|
10049 assert(os::vm_page_size() < (int)G, "default page should be small"); |
|
41d4973cf100
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|
10050 movl(result, str2); // We need only low 32 bits |
|
41d4973cf100
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|
10051 andl(result, (os::vm_page_size()-1)); |
|
41d4973cf100
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|
10052 cmpl(result, (os::vm_page_size()-16)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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|
10053 jccb(Assembler::belowEqual, CHECK_STR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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diff
changeset
|
10054 |
|
41d4973cf100
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changeset
|
10055 // Move small strings to stack to allow load 16 bytes into vec. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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|
10056 subptr(rsp, 16); |
|
41d4973cf100
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changeset
|
10057 int stk_offset = wordSize-2; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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diff
changeset
|
10058 push(cnt2); |
|
41d4973cf100
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diff
changeset
|
10059 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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changeset
|
10060 bind(COPY_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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|
10061 load_unsigned_short(result, Address(str2, cnt2, Address::times_2, -2)); |
|
41d4973cf100
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changeset
|
10062 movw(Address(rsp, cnt2, Address::times_2, stk_offset), result); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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|
10063 decrement(cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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changeset
|
10064 jccb(Assembler::notZero, COPY_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
10065 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
10066 pop(cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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changeset
|
10067 movptr(str2, rsp); // New substring address |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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changeset
|
10068 } // non constant |
|
41d4973cf100
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diff
changeset
|
10069 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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changeset
|
10070 bind(CHECK_STR); |
|
41d4973cf100
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changeset
|
10071 cmpl(cnt1, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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changeset
|
10072 jccb(Assembler::aboveEqual, BIG_STRINGS); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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changeset
|
10073 |
|
41d4973cf100
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changeset
|
10074 // Check cross page boundary. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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changeset
|
10075 movl(result, str1); // We need only low 32 bits |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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changeset
|
10076 andl(result, (os::vm_page_size()-1)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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|
10077 cmpl(result, (os::vm_page_size()-16)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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changeset
|
10078 jccb(Assembler::belowEqual, BIG_STRINGS); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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changeset
|
10079 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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changeset
|
10080 subptr(rsp, 16); |
|
41d4973cf100
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changeset
|
10081 int stk_offset = -2; |
|
41d4973cf100
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|
10082 if (int_cnt2 < 0) { // not constant |
|
41d4973cf100
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diff
changeset
|
10083 push(cnt2); |
|
41d4973cf100
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changeset
|
10084 stk_offset += wordSize; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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changeset
|
10085 } |
|
41d4973cf100
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changeset
|
10086 movl(cnt2, cnt1); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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changeset
|
10087 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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changeset
|
10088 bind(COPY_STR); |
|
41d4973cf100
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changeset
|
10089 load_unsigned_short(result, Address(str1, cnt2, Address::times_2, -2)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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|
10090 movw(Address(rsp, cnt2, Address::times_2, stk_offset), result); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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changeset
|
10091 decrement(cnt2); |
|
41d4973cf100
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changeset
|
10092 jccb(Assembler::notZero, COPY_STR); |
|
41d4973cf100
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diff
changeset
|
10093 |
|
41d4973cf100
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changeset
|
10094 if (int_cnt2 < 0) { // not constant |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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diff
changeset
|
10095 pop(cnt2); |
|
41d4973cf100
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diff
changeset
|
10096 } |
|
41d4973cf100
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changeset
|
10097 movptr(str1, rsp); // New string address |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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changeset
|
10098 |
|
41d4973cf100
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changeset
|
10099 bind(BIG_STRINGS); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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changeset
|
10100 // Load substring. |
|
41d4973cf100
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changeset
|
10101 if (int_cnt2 < 0) { // -1 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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|
10102 movdqu(vec, Address(str2, 0)); |
|
41d4973cf100
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|
10103 push(cnt2); // substr count |
|
41d4973cf100
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changeset
|
10104 push(str2); // substr addr |
|
41d4973cf100
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changeset
|
10105 push(str1); // string addr |
|
41d4973cf100
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changeset
|
10106 } else { |
|
41d4973cf100
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changeset
|
10107 // Small (< 8 chars) constant substrings are loaded already. |
|
41d4973cf100
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|
10108 movl(cnt2, int_cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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diff
changeset
|
10109 } |
|
41d4973cf100
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changeset
|
10110 push(tmp); // original SP |
|
41d4973cf100
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changeset
|
10111 |
|
41d4973cf100
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|
10112 } // Finished loading |
|
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|
10113 |
|
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|
10114 //======================================================== |
|
41d4973cf100
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|
10115 // Start search |
|
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|
10116 // |
|
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|
10117 |
|
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|
10118 movptr(result, str1); // string addr |
|
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|
10119 |
|
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changeset
|
10120 if (int_cnt2 < 0) { // Only for non constant substring |
|
41d4973cf100
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|
10121 jmpb(SCAN_TO_SUBSTR); |
|
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|
10122 |
|
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changeset
|
10123 // SP saved at sp+0 |
|
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|
10124 // String saved at sp+1*wordSize |
|
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|
10125 // Substr saved at sp+2*wordSize |
|
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|
10126 // Substr count saved at sp+3*wordSize |
|
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|
10127 |
|
41d4973cf100
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changeset
|
10128 // Reload substr for rescan, this code |
|
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|
10129 // is executed only for large substrings (> 8 chars) |
|
41d4973cf100
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|
10130 bind(RELOAD_SUBSTR); |
|
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6942326: x86 code in string_indexof() could read beyond reserved heap space
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|
10131 movptr(str2, Address(rsp, 2*wordSize)); |
|
41d4973cf100
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|
10132 movl(cnt2, Address(rsp, 3*wordSize)); |
|
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|
10133 movdqu(vec, Address(str2, 0)); |
|
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|
10134 // We came here after the beginning of the substring was |
|
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|
10135 // matched but the rest of it was not so we need to search |
|
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|
10136 // again. Start from the next element after the previous match. |
|
41d4973cf100
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|
10137 subptr(str1, result); // Restore counter |
|
41d4973cf100
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|
10138 shrl(str1, 1); |
|
41d4973cf100
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|
10139 addl(cnt1, str1); |
|
41d4973cf100
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|
10140 decrementl(cnt1); // Shift to next element |
|
41d4973cf100
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changeset
|
10141 cmpl(cnt1, cnt2); |
|
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|
10142 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring |
|
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changeset
|
10143 |
|
41d4973cf100
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changeset
|
10144 addptr(result, 2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
10145 } // non constant |
|
41d4973cf100
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diff
changeset
|
10146 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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diff
changeset
|
10147 // Scan string for start of substr in 16-byte vectors |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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changeset
|
10148 bind(SCAN_TO_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
10149 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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|
10150 pcmpestri(vec, Address(result, 0), 0x0d); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
10151 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
10152 subl(cnt1, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
10153 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
10154 cmpl(cnt1, cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
10155 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring |
|
41d4973cf100
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parents:
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diff
changeset
|
10156 addptr(result, 16); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
10157 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
10158 bind(ADJUST_STR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
10159 cmpl(cnt1, 8); // Do not read beyond string |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
10160 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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changeset
|
10161 // Back-up string to avoid reading beyond string. |
|
41d4973cf100
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changeset
|
10162 lea(result, Address(result, cnt1, Address::times_2, -16)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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changeset
|
10163 movl(cnt1, 8); |
|
41d4973cf100
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parents:
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changeset
|
10164 jmpb(SCAN_TO_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
10165 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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2262
diff
changeset
|
10166 // Found a potential substr |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
10167 bind(FOUND_CANDIDATE); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
10168 // After pcmpestri tmp(rcx) contains matched element index |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10169 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10170 // Make sure string is still long enough |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10171 subl(cnt1, tmp); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10172 cmpl(cnt1, cnt2); |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
10173 jccb(Assembler::greaterEqual, FOUND_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
10174 // Left less then substring. |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10175 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10176 bind(RET_NOT_FOUND); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10177 movl(result, -1); |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10178 jmpb(CLEANUP); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
10179 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10180 bind(FOUND_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
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diff
changeset
|
10181 // Compute start addr of substr |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
10182 lea(result, Address(result, tmp, Address::times_2)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10183 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10184 if (int_cnt2 > 0) { // Constant substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10185 // Repeat search for small substring (< 8 chars) |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10186 // from new point without reloading substring. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
10187 // Have to check that we don't read beyond string. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10188 cmpl(tmp, 8-int_cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10189 jccb(Assembler::greater, ADJUST_STR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10190 // Fall through if matched whole substring. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
10191 } else { // non constant |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10192 assert(int_cnt2 == -1, "should be != 0"); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10193 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10194 addl(tmp, cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10195 // Found result if we matched whole substring. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10196 cmpl(tmp, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10197 jccb(Assembler::lessEqual, RET_FOUND); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10198 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10199 // Repeat search for small substring (<= 8 chars) |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10200 // from new point 'str1' without reloading substring. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10201 cmpl(cnt2, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
10202 // Have to check that we don't read beyond string. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10203 jccb(Assembler::lessEqual, ADJUST_STR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10204 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10205 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
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diff
changeset
|
10206 // Compare the rest of substring (> 8 chars). |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10207 movptr(str1, result); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10208 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10209 cmpl(tmp, cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10210 // First 8 chars are already matched. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10211 jccb(Assembler::equal, CHECK_NEXT); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10212 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10213 bind(SCAN_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10214 pcmpestri(vec, Address(str1, 0), 0x0d); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10215 // Need to reload strings pointers if not matched whole vector |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10216 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10217 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10218 bind(CHECK_NEXT); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10219 subl(cnt2, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10220 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10221 addptr(str1, 16); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10222 addptr(str2, 16); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10223 subl(cnt1, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10224 cmpl(cnt2, 8); // Do not read beyond substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10225 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10226 // Back-up strings to avoid reading beyond substring. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10227 lea(str2, Address(str2, cnt2, Address::times_2, -16)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10228 lea(str1, Address(str1, cnt2, Address::times_2, -16)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10229 subl(cnt1, cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10230 movl(cnt2, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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|
10231 addl(cnt1, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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|
10232 bind(CONT_SCAN_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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diff
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|
10233 movdqu(vec, Address(str2, 0)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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|
10234 jmpb(SCAN_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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diff
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|
10235 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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diff
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|
10236 bind(RET_FOUND_LONG); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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|
10237 movptr(str1, Address(rsp, wordSize)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
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|
10238 } // non constant |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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diff
changeset
|
10239 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
10240 bind(RET_FOUND); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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2262
diff
changeset
|
10241 // Compute substr offset |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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diff
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|
10242 subptr(result, str1); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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diff
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|
10243 shrl(result, 1); // index |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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diff
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|
10244 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
changeset
|
10245 bind(CLEANUP); |
|
2320
41d4973cf100
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|
10246 pop(rsp); // restore SP |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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diff
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|
10247 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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diff
changeset
|
10248 } // string_indexof |
|
986
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diff
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|
10249 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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898
diff
changeset
|
10250 // Compare strings. |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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diff
changeset
|
10251 void MacroAssembler::string_compare(Register str1, Register str2, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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|
10252 Register cnt1, Register cnt2, Register result, |
| 2262 | 10253 XMMRegister vec1) { |
|
4766
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7110832: ctw/.../org_apache_avalon_composition_util_StringHelper crashes the VM
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|
10254 ShortBranchVerifier sbv(this); |
|
986
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6827605: new String intrinsics may prevent EA scalar replacement
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diff
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|
10255 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL; |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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diff
changeset
|
10256 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
changeset
|
10257 // Compute the minimum of the string lengths and the |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
10258 // difference of the string lengths (stack). |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
10259 // Do the conditional move stuff |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
10260 movl(result, cnt1); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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898
diff
changeset
|
10261 subl(cnt1, cnt2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
changeset
|
10262 push(cnt1); |
|
2415
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
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|
10263 cmov32(Assembler::lessEqual, cnt2, result); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
changeset
|
10264 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
10265 // Is the minimum length zero? |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
10266 testl(cnt2, cnt2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
10267 jcc(Assembler::zero, LENGTH_DIFF_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
10268 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
changeset
|
10269 // Load first characters |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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diff
changeset
|
10270 load_unsigned_short(result, Address(str1, 0)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
changeset
|
10271 load_unsigned_short(cnt1, Address(str2, 0)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
10272 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
10273 // Compare first characters |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
10274 subl(result, cnt1); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
10275 jcc(Assembler::notZero, POP_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
10276 decrementl(cnt2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10277 jcc(Assembler::zero, LENGTH_DIFF_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10278 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
10279 { |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10280 // Check after comparing first character to see if strings are equivalent |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10281 Label LSkip2; |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10282 // Check if the strings start at same location |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10283 cmpptr(str1, str2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10284 jccb(Assembler::notEqual, LSkip2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10285 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10286 // Check if the length difference is zero (from stack) |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10287 cmpl(Address(rsp, 0), 0x0); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10288 jcc(Assembler::equal, LENGTH_DIFF_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10289 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10290 // Strings might not be equivalent |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10291 bind(LSkip2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10292 } |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10293 |
| 2262 | 10294 Address::ScaleFactor scale = Address::times_2; |
| 10295 int stride = 8; | |
| 10296 | |
| 10297 // Advance to next element | |
| 10298 addptr(str1, 16/stride); | |
| 10299 addptr(str2, 16/stride); | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10300 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10301 if (UseSSE42Intrinsics) { |
| 2262 | 10302 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL; |
| 10303 int pcmpmask = 0x19; | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10304 // Setup to compare 16-byte vectors |
| 2262 | 10305 movl(result, cnt2); |
| 10306 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10307 jccb(Assembler::zero, COMPARE_TAIL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10308 |
| 2262 | 10309 lea(str1, Address(str1, result, scale)); |
| 10310 lea(str2, Address(str2, result, scale)); | |
| 10311 negptr(result); | |
| 10312 | |
| 10313 // pcmpestri | |
| 10314 // inputs: | |
| 10315 // vec1- substring | |
| 10316 // rax - negative string length (elements count) | |
| 10317 // mem - scaned string | |
| 10318 // rdx - string length (elements count) | |
| 10319 // pcmpmask - cmp mode: 11000 (string compare with negated result) | |
| 10320 // + 00 (unsigned bytes) or + 01 (unsigned shorts) | |
| 10321 // outputs: | |
| 10322 // rcx - first mismatched element index | |
| 10323 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri"); | |
| 10324 | |
| 10325 bind(COMPARE_WIDE_VECTORS); | |
| 10326 movdqu(vec1, Address(str1, result, scale)); | |
| 10327 pcmpestri(vec1, Address(str2, result, scale), pcmpmask); | |
| 10328 // After pcmpestri cnt1(rcx) contains mismatched element index | |
| 10329 | |
| 10330 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1 | |
| 10331 addptr(result, stride); | |
| 10332 subptr(cnt2, stride); | |
| 10333 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS); | |
| 10334 | |
| 10335 // compare wide vectors tail | |
| 10336 testl(result, result); | |
| 10337 jccb(Assembler::zero, LENGTH_DIFF_LABEL); | |
| 10338 | |
| 10339 movl(cnt2, stride); | |
| 10340 movl(result, stride); | |
| 10341 negptr(result); | |
| 10342 movdqu(vec1, Address(str1, result, scale)); | |
| 10343 pcmpestri(vec1, Address(str2, result, scale), pcmpmask); | |
| 10344 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL); | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10345 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10346 // Mismatched characters in the vectors |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10347 bind(VECTOR_NOT_EQUAL); |
| 2262 | 10348 addptr(result, cnt1); |
| 10349 movptr(cnt2, result); | |
| 10350 load_unsigned_short(result, Address(str1, cnt2, scale)); | |
| 10351 load_unsigned_short(cnt1, Address(str2, cnt2, scale)); | |
| 10352 subl(result, cnt1); | |
| 10353 jmpb(POP_LABEL); | |
| 10354 | |
| 10355 bind(COMPARE_TAIL); // limit is zero | |
| 10356 movl(cnt2, result); | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10357 // Fallthru to tail compare |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10358 } |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10359 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10360 // Shift str2 and str1 to the end of the arrays, negate min |
| 2262 | 10361 lea(str1, Address(str1, cnt2, scale, 0)); |
| 10362 lea(str2, Address(str2, cnt2, scale, 0)); | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10363 negptr(cnt2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10364 |
| 2262 | 10365 // Compare the rest of the elements |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10366 bind(WHILE_HEAD_LABEL); |
| 2262 | 10367 load_unsigned_short(result, Address(str1, cnt2, scale, 0)); |
| 10368 load_unsigned_short(cnt1, Address(str2, cnt2, scale, 0)); | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
10369 subl(result, cnt1); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10370 jccb(Assembler::notZero, POP_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10371 increment(cnt2); |
| 2262 | 10372 jccb(Assembler::notZero, WHILE_HEAD_LABEL); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
10373 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
10374 // Strings are equal up to min length. Return the length difference. |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10375 bind(LENGTH_DIFF_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10376 pop(result); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10377 jmpb(DONE_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10378 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
10379 // Discard the stored length difference |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10380 bind(POP_LABEL); |
| 2262 | 10381 pop(cnt1); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10382 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
10383 // That's it |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10384 bind(DONE_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10385 } |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10386 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
10387 // Compare char[] arrays aligned to 4 bytes or substrings. |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10388 void MacroAssembler::char_arrays_equals(bool is_array_equ, Register ary1, Register ary2, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
10389 Register limit, Register result, Register chr, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
10390 XMMRegister vec1, XMMRegister vec2) { |
|
4766
40c2484c09e1
7110832: ctw/.../org_apache_avalon_composition_util_StringHelper crashes the VM
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4762
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|
10391 ShortBranchVerifier sbv(this); |
|
986
62001a362ce9
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parents:
898
diff
changeset
|
10392 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR; |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10393 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
10394 int length_offset = arrayOopDesc::length_offset_in_bytes(); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
10395 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10396 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
10397 // Check the input args |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
10398 cmpptr(ary1, ary2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
changeset
|
10399 jcc(Assembler::equal, TRUE_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
10400 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
10401 if (is_array_equ) { |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
10402 // Need additional checks for arrays_equals. |
| 1016 | 10403 testptr(ary1, ary1); |
| 10404 jcc(Assembler::zero, FALSE_LABEL); | |
| 10405 testptr(ary2, ary2); | |
| 10406 jcc(Assembler::zero, FALSE_LABEL); | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
10407 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
10408 // Check the lengths |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
10409 movl(limit, Address(ary1, length_offset)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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|
10410 cmpl(limit, Address(ary2, length_offset)); |
|
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|
10411 jcc(Assembler::notEqual, FALSE_LABEL); |
|
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parents:
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diff
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|
10412 } |
|
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parents:
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diff
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|
10413 |
|
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6827605: new String intrinsics may prevent EA scalar replacement
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diff
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|
10414 // count == 0 |
|
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diff
changeset
|
10415 testl(limit, limit); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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diff
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|
10416 jcc(Assembler::zero, TRUE_LABEL); |
|
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diff
changeset
|
10417 |
|
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6827605: new String intrinsics may prevent EA scalar replacement
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898
diff
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|
10418 if (is_array_equ) { |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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diff
changeset
|
10419 // Load array address |
|
62001a362ce9
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diff
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|
10420 lea(ary1, Address(ary1, base_offset)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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diff
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|
10421 lea(ary2, Address(ary2, base_offset)); |
|
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6827605: new String intrinsics may prevent EA scalar replacement
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diff
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|
10422 } |
|
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6827605: new String intrinsics may prevent EA scalar replacement
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diff
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|
10423 |
|
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6827605: new String intrinsics may prevent EA scalar replacement
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898
diff
changeset
|
10424 shll(limit, 1); // byte count != 0 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
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|
10425 movl(result, limit); // copy |
|
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parents:
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diff
changeset
|
10426 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
changeset
|
10427 if (UseSSE42Intrinsics) { |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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diff
changeset
|
10428 // With SSE4.2, use double quad vector compare |
|
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6827605: new String intrinsics may prevent EA scalar replacement
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|
10429 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; |
| 2262 | 10430 |
|
986
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diff
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|
10431 // Compare 16-byte vectors |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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diff
changeset
|
10432 andl(result, 0x0000000e); // tail count (in bytes) |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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|
10433 andl(limit, 0xfffffff0); // vector count (in bytes) |
|
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6827605: new String intrinsics may prevent EA scalar replacement
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diff
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|
10434 jccb(Assembler::zero, COMPARE_TAIL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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diff
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|
10435 |
|
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6827605: new String intrinsics may prevent EA scalar replacement
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diff
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|
10436 lea(ary1, Address(ary1, limit, Address::times_1)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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diff
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|
10437 lea(ary2, Address(ary2, limit, Address::times_1)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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diff
changeset
|
10438 negptr(limit); |
|
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6827605: new String intrinsics may prevent EA scalar replacement
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diff
changeset
|
10439 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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diff
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|
10440 bind(COMPARE_WIDE_VECTORS); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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diff
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|
10441 movdqu(vec1, Address(ary1, limit, Address::times_1)); |
|
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6827605: new String intrinsics may prevent EA scalar replacement
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|
10442 movdqu(vec2, Address(ary2, limit, Address::times_1)); |
|
62001a362ce9
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|
10443 pxor(vec1, vec2); |
| 2262 | 10444 |
|
986
62001a362ce9
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parents:
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diff
changeset
|
10445 ptest(vec1, vec1); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
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|
10446 jccb(Assembler::notZero, FALSE_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
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diff
changeset
|
10447 addptr(limit, 16); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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diff
changeset
|
10448 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
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|
10449 |
| 2262 | 10450 testl(result, result); |
| 10451 jccb(Assembler::zero, TRUE_LABEL); | |
| 10452 | |
| 10453 movdqu(vec1, Address(ary1, result, Address::times_1, -16)); | |
| 10454 movdqu(vec2, Address(ary2, result, Address::times_1, -16)); | |
| 10455 pxor(vec1, vec2); | |
| 10456 | |
| 10457 ptest(vec1, vec1); | |
| 10458 jccb(Assembler::notZero, FALSE_LABEL); | |
| 10459 jmpb(TRUE_LABEL); | |
| 10460 | |
|
986
62001a362ce9
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diff
changeset
|
10461 bind(COMPARE_TAIL); // limit is zero |
|
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6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
changeset
|
10462 movl(limit, result); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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diff
changeset
|
10463 // Fallthru to tail compare |
|
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diff
changeset
|
10464 } |
|
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parents:
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diff
changeset
|
10465 |
|
62001a362ce9
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diff
changeset
|
10466 // Compare 4-byte vectors |
|
62001a362ce9
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diff
changeset
|
10467 andl(limit, 0xfffffffc); // vector count (in bytes) |
|
62001a362ce9
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changeset
|
10468 jccb(Assembler::zero, COMPARE_CHAR); |
|
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diff
changeset
|
10469 |
|
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changeset
|
10470 lea(ary1, Address(ary1, limit, Address::times_1)); |
|
62001a362ce9
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|
10471 lea(ary2, Address(ary2, limit, Address::times_1)); |
|
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diff
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|
10472 negptr(limit); |
|
62001a362ce9
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diff
changeset
|
10473 |
|
62001a362ce9
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changeset
|
10474 bind(COMPARE_VECTORS); |
|
62001a362ce9
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|
10475 movl(chr, Address(ary1, limit, Address::times_1)); |
|
62001a362ce9
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|
10476 cmpl(chr, Address(ary2, limit, Address::times_1)); |
|
62001a362ce9
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|
10477 jccb(Assembler::notEqual, FALSE_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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diff
changeset
|
10478 addptr(limit, 4); |
|
62001a362ce9
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diff
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|
10479 jcc(Assembler::notZero, COMPARE_VECTORS); |
|
62001a362ce9
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diff
changeset
|
10480 |
|
62001a362ce9
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parents:
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diff
changeset
|
10481 // Compare trailing char (final 2 bytes), if any |
|
62001a362ce9
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parents:
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diff
changeset
|
10482 bind(COMPARE_CHAR); |
|
62001a362ce9
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diff
changeset
|
10483 testl(result, 0x2); // tail char |
|
62001a362ce9
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diff
changeset
|
10484 jccb(Assembler::zero, TRUE_LABEL); |
|
62001a362ce9
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diff
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|
10485 load_unsigned_short(chr, Address(ary1, 0)); |
|
62001a362ce9
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diff
changeset
|
10486 load_unsigned_short(limit, Address(ary2, 0)); |
|
62001a362ce9
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parents:
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diff
changeset
|
10487 cmpl(chr, limit); |
|
62001a362ce9
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parents:
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diff
changeset
|
10488 jccb(Assembler::notEqual, FALSE_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
changeset
|
10489 |
|
62001a362ce9
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diff
changeset
|
10490 bind(TRUE_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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diff
changeset
|
10491 movl(result, 1); // return true |
|
62001a362ce9
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parents:
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diff
changeset
|
10492 jmpb(DONE); |
|
62001a362ce9
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parents:
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diff
changeset
|
10493 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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diff
changeset
|
10494 bind(FALSE_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
10495 xorl(result, result); // return false |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
10496 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
10497 // That's it |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
10498 bind(DONE); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
10499 } |
|
62001a362ce9
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diff
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|
10500 |
| 1763 | 10501 #ifdef PRODUCT |
| 10502 #define BLOCK_COMMENT(str) /* nothing */ | |
| 10503 #else | |
| 10504 #define BLOCK_COMMENT(str) block_comment(str) | |
| 10505 #endif | |
| 10506 | |
| 10507 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") | |
| 10508 void MacroAssembler::generate_fill(BasicType t, bool aligned, | |
| 10509 Register to, Register value, Register count, | |
| 10510 Register rtmp, XMMRegister xtmp) { | |
|
4766
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|
10511 ShortBranchVerifier sbv(this); |
| 1763 | 10512 assert_different_registers(to, value, count, rtmp); |
| 10513 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte; | |
| 10514 Label L_fill_2_bytes, L_fill_4_bytes; | |
| 10515 | |
| 10516 int shift = -1; | |
| 10517 switch (t) { | |
| 10518 case T_BYTE: | |
| 10519 shift = 2; | |
| 10520 break; | |
| 10521 case T_SHORT: | |
| 10522 shift = 1; | |
| 10523 break; | |
| 10524 case T_INT: | |
| 10525 shift = 0; | |
| 10526 break; | |
| 10527 default: ShouldNotReachHere(); | |
| 10528 } | |
| 10529 | |
| 10530 if (t == T_BYTE) { | |
| 10531 andl(value, 0xff); | |
| 10532 movl(rtmp, value); | |
| 10533 shll(rtmp, 8); | |
| 10534 orl(value, rtmp); | |
| 10535 } | |
| 10536 if (t == T_SHORT) { | |
| 10537 andl(value, 0xffff); | |
| 10538 } | |
| 10539 if (t == T_BYTE || t == T_SHORT) { | |
| 10540 movl(rtmp, value); | |
| 10541 shll(rtmp, 16); | |
| 10542 orl(value, rtmp); | |
| 10543 } | |
| 10544 | |
| 10545 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element | |
| 10546 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp | |
| 10547 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) { | |
| 10548 // align source address at 4 bytes address boundary | |
| 10549 if (t == T_BYTE) { | |
| 10550 // One byte misalignment happens only for byte arrays | |
| 10551 testptr(to, 1); | |
| 10552 jccb(Assembler::zero, L_skip_align1); | |
| 10553 movb(Address(to, 0), value); | |
| 10554 increment(to); | |
| 10555 decrement(count); | |
| 10556 BIND(L_skip_align1); | |
| 10557 } | |
| 10558 // Two bytes misalignment happens only for byte and short (char) arrays | |
| 10559 testptr(to, 2); | |
| 10560 jccb(Assembler::zero, L_skip_align2); | |
| 10561 movw(Address(to, 0), value); | |
| 10562 addptr(to, 2); | |
| 10563 subl(count, 1<<(shift-1)); | |
| 10564 BIND(L_skip_align2); | |
| 10565 } | |
| 10566 if (UseSSE < 2) { | |
| 10567 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; | |
| 10568 // Fill 32-byte chunks | |
| 10569 subl(count, 8 << shift); | |
| 10570 jcc(Assembler::less, L_check_fill_8_bytes); | |
| 10571 align(16); | |
| 10572 | |
| 10573 BIND(L_fill_32_bytes_loop); | |
| 10574 | |
| 10575 for (int i = 0; i < 32; i += 4) { | |
| 10576 movl(Address(to, i), value); | |
| 10577 } | |
| 10578 | |
| 10579 addptr(to, 32); | |
| 10580 subl(count, 8 << shift); | |
| 10581 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); | |
| 10582 BIND(L_check_fill_8_bytes); | |
| 10583 addl(count, 8 << shift); | |
| 10584 jccb(Assembler::zero, L_exit); | |
| 10585 jmpb(L_fill_8_bytes); | |
| 10586 | |
| 10587 // | |
| 10588 // length is too short, just fill qwords | |
| 10589 // | |
| 10590 BIND(L_fill_8_bytes_loop); | |
| 10591 movl(Address(to, 0), value); | |
| 10592 movl(Address(to, 4), value); | |
| 10593 addptr(to, 8); | |
| 10594 BIND(L_fill_8_bytes); | |
| 10595 subl(count, 1 << (shift + 1)); | |
| 10596 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); | |
| 10597 // fall through to fill 4 bytes | |
| 10598 } else { | |
| 10599 Label L_fill_32_bytes; | |
| 10600 if (!UseUnalignedLoadStores) { | |
| 10601 // align to 8 bytes, we know we are 4 byte aligned to start | |
| 10602 testptr(to, 4); | |
| 10603 jccb(Assembler::zero, L_fill_32_bytes); | |
| 10604 movl(Address(to, 0), value); | |
| 10605 addptr(to, 4); | |
| 10606 subl(count, 1<<shift); | |
| 10607 } | |
| 10608 BIND(L_fill_32_bytes); | |
| 10609 { | |
| 10610 assert( UseSSE >= 2, "supported cpu only" ); | |
| 10611 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; | |
| 10612 // Fill 32-byte chunks | |
| 10613 movdl(xtmp, value); | |
| 10614 pshufd(xtmp, xtmp, 0); | |
| 10615 | |
| 10616 subl(count, 8 << shift); | |
| 10617 jcc(Assembler::less, L_check_fill_8_bytes); | |
| 10618 align(16); | |
| 10619 | |
| 10620 BIND(L_fill_32_bytes_loop); | |
| 10621 | |
| 10622 if (UseUnalignedLoadStores) { | |
| 10623 movdqu(Address(to, 0), xtmp); | |
| 10624 movdqu(Address(to, 16), xtmp); | |
| 10625 } else { | |
| 10626 movq(Address(to, 0), xtmp); | |
| 10627 movq(Address(to, 8), xtmp); | |
| 10628 movq(Address(to, 16), xtmp); | |
| 10629 movq(Address(to, 24), xtmp); | |
| 10630 } | |
| 10631 | |
| 10632 addptr(to, 32); | |
| 10633 subl(count, 8 << shift); | |
| 10634 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); | |
| 10635 BIND(L_check_fill_8_bytes); | |
| 10636 addl(count, 8 << shift); | |
| 10637 jccb(Assembler::zero, L_exit); | |
| 10638 jmpb(L_fill_8_bytes); | |
| 10639 | |
| 10640 // | |
| 10641 // length is too short, just fill qwords | |
| 10642 // | |
| 10643 BIND(L_fill_8_bytes_loop); | |
| 10644 movq(Address(to, 0), xtmp); | |
| 10645 addptr(to, 8); | |
| 10646 BIND(L_fill_8_bytes); | |
| 10647 subl(count, 1 << (shift + 1)); | |
| 10648 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); | |
| 10649 } | |
| 10650 } | |
| 10651 // fill trailing 4 bytes | |
| 10652 BIND(L_fill_4_bytes); | |
| 10653 testl(count, 1<<shift); | |
| 10654 jccb(Assembler::zero, L_fill_2_bytes); | |
| 10655 movl(Address(to, 0), value); | |
| 10656 if (t == T_BYTE || t == T_SHORT) { | |
| 10657 addptr(to, 4); | |
| 10658 BIND(L_fill_2_bytes); | |
| 10659 // fill trailing 2 bytes | |
| 10660 testl(count, 1<<(shift-1)); | |
| 10661 jccb(Assembler::zero, L_fill_byte); | |
| 10662 movw(Address(to, 0), value); | |
| 10663 if (t == T_BYTE) { | |
| 10664 addptr(to, 2); | |
| 10665 BIND(L_fill_byte); | |
| 10666 // fill trailing byte | |
| 10667 testl(count, 1); | |
| 10668 jccb(Assembler::zero, L_exit); | |
| 10669 movb(Address(to, 0), value); | |
| 10670 } else { | |
| 10671 BIND(L_fill_byte); | |
| 10672 } | |
| 10673 } else { | |
| 10674 BIND(L_fill_2_bytes); | |
| 10675 } | |
| 10676 BIND(L_exit); | |
| 10677 } | |
| 10678 #undef BIND | |
| 10679 #undef BLOCK_COMMENT | |
| 10680 | |
| 10681 | |
| 0 | 10682 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) { |
| 10683 switch (cond) { | |
| 10684 // Note some conditions are synonyms for others | |
| 10685 case Assembler::zero: return Assembler::notZero; | |
| 10686 case Assembler::notZero: return Assembler::zero; | |
| 10687 case Assembler::less: return Assembler::greaterEqual; | |
| 10688 case Assembler::lessEqual: return Assembler::greater; | |
| 10689 case Assembler::greater: return Assembler::lessEqual; | |
| 10690 case Assembler::greaterEqual: return Assembler::less; | |
| 10691 case Assembler::below: return Assembler::aboveEqual; | |
| 10692 case Assembler::belowEqual: return Assembler::above; | |
| 10693 case Assembler::above: return Assembler::belowEqual; | |
| 10694 case Assembler::aboveEqual: return Assembler::below; | |
| 10695 case Assembler::overflow: return Assembler::noOverflow; | |
| 10696 case Assembler::noOverflow: return Assembler::overflow; | |
| 10697 case Assembler::negative: return Assembler::positive; | |
| 10698 case Assembler::positive: return Assembler::negative; | |
| 10699 case Assembler::parity: return Assembler::noParity; | |
| 10700 case Assembler::noParity: return Assembler::parity; | |
| 10701 } | |
| 10702 ShouldNotReachHere(); return Assembler::overflow; | |
| 10703 } | |
| 10704 | |
| 10705 SkipIfEqual::SkipIfEqual( | |
| 10706 MacroAssembler* masm, const bool* flag_addr, bool value) { | |
| 10707 _masm = masm; | |
| 10708 _masm->cmp8(ExternalAddress((address)flag_addr), value); | |
| 10709 _masm->jcc(Assembler::equal, _label); | |
| 10710 } | |
| 10711 | |
| 10712 SkipIfEqual::~SkipIfEqual() { | |
| 10713 _masm->bind(_label); | |
| 10714 } |