Mercurial > hg > truffle
annotate src/cpu/x86/vm/assembler_x86.cpp @ 2100:b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
Summary: Track allocated bytes in Thread's, update on TLAB retirement and direct allocation in Eden and tenured, add JNI methods for ThreadMXBean.
Reviewed-by: coleenp, kvn, dholmes, ysr
| author | phh |
|---|---|
| date | Fri, 07 Jan 2011 10:42:32 -0500 |
| parents | 4de5f4101cfd |
| children | 91fe28b03d6a 28bf941f445e |
| rev | line source |
|---|---|
| 0 | 1 /* |
|
2100
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
2 * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
|
1552
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1513
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changeset
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
|
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1513
diff
changeset
|
20 * or visit www.oracle.com if you need additional information or have any |
|
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
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parents:
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21 * questions. |
| 0 | 22 * |
| 23 */ | |
| 24 | |
| 1972 | 25 #include "precompiled.hpp" |
| 26 #include "assembler_x86.inline.hpp" | |
| 27 #include "gc_interface/collectedHeap.inline.hpp" | |
| 28 #include "interpreter/interpreter.hpp" | |
| 29 #include "memory/cardTableModRefBS.hpp" | |
| 30 #include "memory/resourceArea.hpp" | |
| 31 #include "prims/methodHandles.hpp" | |
| 32 #include "runtime/biasedLocking.hpp" | |
| 33 #include "runtime/interfaceSupport.hpp" | |
| 34 #include "runtime/objectMonitor.hpp" | |
| 35 #include "runtime/os.hpp" | |
| 36 #include "runtime/sharedRuntime.hpp" | |
| 37 #include "runtime/stubRoutines.hpp" | |
| 38 #ifndef SERIALGC | |
| 39 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp" | |
| 40 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp" | |
| 41 #include "gc_implementation/g1/heapRegion.hpp" | |
| 42 #endif | |
| 0 | 43 |
| 44 // Implementation of AddressLiteral | |
| 45 | |
| 46 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) { | |
| 47 _is_lval = false; | |
| 48 _target = target; | |
| 49 switch (rtype) { | |
| 50 case relocInfo::oop_type: | |
| 51 // Oops are a special case. Normally they would be their own section | |
| 52 // but in cases like icBuffer they are literals in the code stream that | |
| 53 // we don't have a section for. We use none so that we get a literal address | |
| 54 // which is always patchable. | |
| 55 break; | |
| 56 case relocInfo::external_word_type: | |
| 57 _rspec = external_word_Relocation::spec(target); | |
| 58 break; | |
| 59 case relocInfo::internal_word_type: | |
| 60 _rspec = internal_word_Relocation::spec(target); | |
| 61 break; | |
| 62 case relocInfo::opt_virtual_call_type: | |
| 63 _rspec = opt_virtual_call_Relocation::spec(); | |
| 64 break; | |
| 65 case relocInfo::static_call_type: | |
| 66 _rspec = static_call_Relocation::spec(); | |
| 67 break; | |
| 68 case relocInfo::runtime_call_type: | |
| 69 _rspec = runtime_call_Relocation::spec(); | |
| 70 break; | |
| 71 case relocInfo::poll_type: | |
| 72 case relocInfo::poll_return_type: | |
| 73 _rspec = Relocation::spec_simple(rtype); | |
| 74 break; | |
| 75 case relocInfo::none: | |
| 76 break; | |
| 77 default: | |
| 78 ShouldNotReachHere(); | |
| 79 break; | |
| 80 } | |
| 81 } | |
| 82 | |
| 83 // Implementation of Address | |
| 84 | |
| 304 | 85 #ifdef _LP64 |
| 86 | |
| 0 | 87 Address Address::make_array(ArrayAddress adr) { |
| 88 // Not implementable on 64bit machines | |
| 89 // Should have been handled higher up the call chain. | |
| 90 ShouldNotReachHere(); | |
| 304 | 91 return Address(); |
| 92 } | |
| 93 | |
| 94 // exceedingly dangerous constructor | |
| 95 Address::Address(int disp, address loc, relocInfo::relocType rtype) { | |
| 96 _base = noreg; | |
| 97 _index = noreg; | |
| 98 _scale = no_scale; | |
| 99 _disp = disp; | |
| 100 switch (rtype) { | |
| 101 case relocInfo::external_word_type: | |
| 102 _rspec = external_word_Relocation::spec(loc); | |
| 103 break; | |
| 104 case relocInfo::internal_word_type: | |
| 105 _rspec = internal_word_Relocation::spec(loc); | |
| 106 break; | |
| 107 case relocInfo::runtime_call_type: | |
| 108 // HMM | |
| 109 _rspec = runtime_call_Relocation::spec(); | |
| 110 break; | |
| 111 case relocInfo::poll_type: | |
| 112 case relocInfo::poll_return_type: | |
| 113 _rspec = Relocation::spec_simple(rtype); | |
| 114 break; | |
| 115 case relocInfo::none: | |
| 116 break; | |
| 117 default: | |
| 118 ShouldNotReachHere(); | |
| 119 } | |
| 120 } | |
| 121 #else // LP64 | |
| 122 | |
| 123 Address Address::make_array(ArrayAddress adr) { | |
| 0 | 124 AddressLiteral base = adr.base(); |
| 125 Address index = adr.index(); | |
| 126 assert(index._disp == 0, "must not have disp"); // maybe it can? | |
| 127 Address array(index._base, index._index, index._scale, (intptr_t) base.target()); | |
| 128 array._rspec = base._rspec; | |
| 129 return array; | |
| 304 | 130 } |
| 0 | 131 |
| 132 // exceedingly dangerous constructor | |
| 133 Address::Address(address loc, RelocationHolder spec) { | |
| 134 _base = noreg; | |
| 135 _index = noreg; | |
| 136 _scale = no_scale; | |
| 137 _disp = (intptr_t) loc; | |
| 138 _rspec = spec; | |
| 139 } | |
| 304 | 140 |
| 0 | 141 #endif // _LP64 |
| 142 | |
| 304 | 143 |
| 144 | |
| 0 | 145 // Convert the raw encoding form into the form expected by the constructor for |
| 146 // Address. An index of 4 (rsp) corresponds to having no index, so convert | |
| 147 // that to noreg for the Address constructor. | |
| 624 | 148 Address Address::make_raw(int base, int index, int scale, int disp, bool disp_is_oop) { |
| 149 RelocationHolder rspec; | |
| 150 if (disp_is_oop) { | |
| 151 rspec = Relocation::spec_simple(relocInfo::oop_type); | |
| 152 } | |
| 0 | 153 bool valid_index = index != rsp->encoding(); |
| 154 if (valid_index) { | |
| 155 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp)); | |
| 624 | 156 madr._rspec = rspec; |
| 0 | 157 return madr; |
| 158 } else { | |
| 159 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp)); | |
| 624 | 160 madr._rspec = rspec; |
| 0 | 161 return madr; |
| 162 } | |
| 163 } | |
| 164 | |
| 165 // Implementation of Assembler | |
| 166 | |
| 167 int AbstractAssembler::code_fill_byte() { | |
| 168 return (u_char)'\xF4'; // hlt | |
| 169 } | |
| 170 | |
| 171 // make this go away someday | |
| 172 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) { | |
| 173 if (rtype == relocInfo::none) | |
| 174 emit_long(data); | |
| 175 else emit_data(data, Relocation::spec_simple(rtype), format); | |
| 176 } | |
| 177 | |
| 178 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) { | |
| 304 | 179 assert(imm_operand == 0, "default format must be immediate in this file"); |
| 0 | 180 assert(inst_mark() != NULL, "must be inside InstructionMark"); |
| 181 if (rspec.type() != relocInfo::none) { | |
| 182 #ifdef ASSERT | |
| 183 check_relocation(rspec, format); | |
| 184 #endif | |
| 185 // Do not use AbstractAssembler::relocate, which is not intended for | |
| 186 // embedded words. Instead, relocate to the enclosing instruction. | |
| 187 | |
| 188 // hack. call32 is too wide for mask so use disp32 | |
| 189 if (format == call32_operand) | |
| 190 code_section()->relocate(inst_mark(), rspec, disp32_operand); | |
| 191 else | |
| 192 code_section()->relocate(inst_mark(), rspec, format); | |
| 193 } | |
| 194 emit_long(data); | |
| 195 } | |
| 196 | |
| 304 | 197 static int encode(Register r) { |
| 198 int enc = r->encoding(); | |
| 199 if (enc >= 8) { | |
| 200 enc -= 8; | |
| 201 } | |
| 202 return enc; | |
| 203 } | |
| 204 | |
| 205 static int encode(XMMRegister r) { | |
| 206 int enc = r->encoding(); | |
| 207 if (enc >= 8) { | |
| 208 enc -= 8; | |
| 209 } | |
| 210 return enc; | |
| 211 } | |
| 0 | 212 |
| 213 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) { | |
| 214 assert(dst->has_byte_register(), "must have byte register"); | |
| 215 assert(isByte(op1) && isByte(op2), "wrong opcode"); | |
| 216 assert(isByte(imm8), "not a byte"); | |
| 217 assert((op1 & 0x01) == 0, "should be 8bit operation"); | |
| 218 emit_byte(op1); | |
| 304 | 219 emit_byte(op2 | encode(dst)); |
| 0 | 220 emit_byte(imm8); |
| 221 } | |
| 222 | |
| 223 | |
| 304 | 224 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) { |
| 0 | 225 assert(isByte(op1) && isByte(op2), "wrong opcode"); |
| 226 assert((op1 & 0x01) == 1, "should be 32bit operation"); | |
| 227 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); | |
| 228 if (is8bit(imm32)) { | |
| 229 emit_byte(op1 | 0x02); // set sign bit | |
| 304 | 230 emit_byte(op2 | encode(dst)); |
| 0 | 231 emit_byte(imm32 & 0xFF); |
| 232 } else { | |
| 233 emit_byte(op1); | |
| 304 | 234 emit_byte(op2 | encode(dst)); |
| 0 | 235 emit_long(imm32); |
| 236 } | |
| 237 } | |
| 238 | |
| 239 // immediate-to-memory forms | |
| 304 | 240 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) { |
| 0 | 241 assert((op1 & 0x01) == 1, "should be 32bit operation"); |
| 242 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); | |
| 243 if (is8bit(imm32)) { | |
| 244 emit_byte(op1 | 0x02); // set sign bit | |
| 304 | 245 emit_operand(rm, adr, 1); |
| 0 | 246 emit_byte(imm32 & 0xFF); |
| 247 } else { | |
| 248 emit_byte(op1); | |
| 304 | 249 emit_operand(rm, adr, 4); |
| 0 | 250 emit_long(imm32); |
| 251 } | |
| 252 } | |
| 253 | |
| 254 void Assembler::emit_arith(int op1, int op2, Register dst, jobject obj) { | |
| 304 | 255 LP64_ONLY(ShouldNotReachHere()); |
| 0 | 256 assert(isByte(op1) && isByte(op2), "wrong opcode"); |
| 257 assert((op1 & 0x01) == 1, "should be 32bit operation"); | |
| 258 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); | |
| 259 InstructionMark im(this); | |
| 260 emit_byte(op1); | |
| 304 | 261 emit_byte(op2 | encode(dst)); |
| 262 emit_data((intptr_t)obj, relocInfo::oop_type, 0); | |
| 0 | 263 } |
| 264 | |
| 265 | |
| 266 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) { | |
| 267 assert(isByte(op1) && isByte(op2), "wrong opcode"); | |
| 268 emit_byte(op1); | |
| 304 | 269 emit_byte(op2 | encode(dst) << 3 | encode(src)); |
| 270 } | |
| 271 | |
| 272 | |
| 273 void Assembler::emit_operand(Register reg, Register base, Register index, | |
| 274 Address::ScaleFactor scale, int disp, | |
| 275 RelocationHolder const& rspec, | |
| 276 int rip_relative_correction) { | |
| 0 | 277 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type(); |
| 304 | 278 |
| 279 // Encode the registers as needed in the fields they are used in | |
| 280 | |
| 281 int regenc = encode(reg) << 3; | |
| 282 int indexenc = index->is_valid() ? encode(index) << 3 : 0; | |
| 283 int baseenc = base->is_valid() ? encode(base) : 0; | |
| 284 | |
| 0 | 285 if (base->is_valid()) { |
| 286 if (index->is_valid()) { | |
| 287 assert(scale != Address::no_scale, "inconsistent address"); | |
| 288 // [base + index*scale + disp] | |
| 304 | 289 if (disp == 0 && rtype == relocInfo::none && |
| 290 base != rbp LP64_ONLY(&& base != r13)) { | |
| 0 | 291 // [base + index*scale] |
| 292 // [00 reg 100][ss index base] | |
| 293 assert(index != rsp, "illegal addressing mode"); | |
| 304 | 294 emit_byte(0x04 | regenc); |
| 295 emit_byte(scale << 6 | indexenc | baseenc); | |
| 0 | 296 } else if (is8bit(disp) && rtype == relocInfo::none) { |
| 297 // [base + index*scale + imm8] | |
| 298 // [01 reg 100][ss index base] imm8 | |
| 299 assert(index != rsp, "illegal addressing mode"); | |
| 304 | 300 emit_byte(0x44 | regenc); |
| 301 emit_byte(scale << 6 | indexenc | baseenc); | |
| 0 | 302 emit_byte(disp & 0xFF); |
| 303 } else { | |
| 304 | 304 // [base + index*scale + disp32] |
| 305 // [10 reg 100][ss index base] disp32 | |
| 0 | 306 assert(index != rsp, "illegal addressing mode"); |
| 304 | 307 emit_byte(0x84 | regenc); |
| 308 emit_byte(scale << 6 | indexenc | baseenc); | |
| 0 | 309 emit_data(disp, rspec, disp32_operand); |
| 310 } | |
| 304 | 311 } else if (base == rsp LP64_ONLY(|| base == r12)) { |
| 312 // [rsp + disp] | |
| 0 | 313 if (disp == 0 && rtype == relocInfo::none) { |
| 304 | 314 // [rsp] |
| 0 | 315 // [00 reg 100][00 100 100] |
| 304 | 316 emit_byte(0x04 | regenc); |
| 0 | 317 emit_byte(0x24); |
| 318 } else if (is8bit(disp) && rtype == relocInfo::none) { | |
| 304 | 319 // [rsp + imm8] |
| 320 // [01 reg 100][00 100 100] disp8 | |
| 321 emit_byte(0x44 | regenc); | |
| 0 | 322 emit_byte(0x24); |
| 323 emit_byte(disp & 0xFF); | |
| 324 } else { | |
| 304 | 325 // [rsp + imm32] |
| 326 // [10 reg 100][00 100 100] disp32 | |
| 327 emit_byte(0x84 | regenc); | |
| 0 | 328 emit_byte(0x24); |
| 329 emit_data(disp, rspec, disp32_operand); | |
| 330 } | |
| 331 } else { | |
| 332 // [base + disp] | |
| 304 | 333 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode"); |
| 334 if (disp == 0 && rtype == relocInfo::none && | |
| 335 base != rbp LP64_ONLY(&& base != r13)) { | |
| 0 | 336 // [base] |
| 337 // [00 reg base] | |
| 304 | 338 emit_byte(0x00 | regenc | baseenc); |
| 0 | 339 } else if (is8bit(disp) && rtype == relocInfo::none) { |
| 304 | 340 // [base + disp8] |
| 341 // [01 reg base] disp8 | |
| 342 emit_byte(0x40 | regenc | baseenc); | |
| 0 | 343 emit_byte(disp & 0xFF); |
| 344 } else { | |
| 304 | 345 // [base + disp32] |
| 346 // [10 reg base] disp32 | |
| 347 emit_byte(0x80 | regenc | baseenc); | |
| 0 | 348 emit_data(disp, rspec, disp32_operand); |
| 349 } | |
| 350 } | |
| 351 } else { | |
| 352 if (index->is_valid()) { | |
| 353 assert(scale != Address::no_scale, "inconsistent address"); | |
| 354 // [index*scale + disp] | |
| 304 | 355 // [00 reg 100][ss index 101] disp32 |
| 0 | 356 assert(index != rsp, "illegal addressing mode"); |
| 304 | 357 emit_byte(0x04 | regenc); |
| 358 emit_byte(scale << 6 | indexenc | 0x05); | |
| 0 | 359 emit_data(disp, rspec, disp32_operand); |
| 304 | 360 } else if (rtype != relocInfo::none ) { |
| 361 // [disp] (64bit) RIP-RELATIVE (32bit) abs | |
| 362 // [00 000 101] disp32 | |
| 363 | |
| 364 emit_byte(0x05 | regenc); | |
| 365 // Note that the RIP-rel. correction applies to the generated | |
| 366 // disp field, but _not_ to the target address in the rspec. | |
| 367 | |
| 368 // disp was created by converting the target address minus the pc | |
| 369 // at the start of the instruction. That needs more correction here. | |
| 370 // intptr_t disp = target - next_ip; | |
| 371 assert(inst_mark() != NULL, "must be inside InstructionMark"); | |
| 372 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction; | |
| 373 int64_t adjusted = disp; | |
| 374 // Do rip-rel adjustment for 64bit | |
| 375 LP64_ONLY(adjusted -= (next_ip - inst_mark())); | |
| 376 assert(is_simm32(adjusted), | |
| 377 "must be 32bit offset (RIP relative address)"); | |
| 378 emit_data((int32_t) adjusted, rspec, disp32_operand); | |
| 379 | |
| 0 | 380 } else { |
| 304 | 381 // 32bit never did this, did everything as the rip-rel/disp code above |
| 382 // [disp] ABSOLUTE | |
| 383 // [00 reg 100][00 100 101] disp32 | |
| 384 emit_byte(0x04 | regenc); | |
| 385 emit_byte(0x25); | |
| 0 | 386 emit_data(disp, rspec, disp32_operand); |
| 387 } | |
| 388 } | |
| 389 } | |
| 390 | |
| 304 | 391 void Assembler::emit_operand(XMMRegister reg, Register base, Register index, |
| 392 Address::ScaleFactor scale, int disp, | |
| 393 RelocationHolder const& rspec) { | |
| 394 emit_operand((Register)reg, base, index, scale, disp, rspec); | |
| 395 } | |
| 396 | |
| 0 | 397 // Secret local extension to Assembler::WhichOperand: |
| 398 #define end_pc_operand (_WhichOperand_limit) | |
| 399 | |
| 400 address Assembler::locate_operand(address inst, WhichOperand which) { | |
| 401 // Decode the given instruction, and return the address of | |
| 402 // an embedded 32-bit operand word. | |
| 403 | |
| 404 // If "which" is disp32_operand, selects the displacement portion | |
| 405 // of an effective address specifier. | |
| 304 | 406 // If "which" is imm64_operand, selects the trailing immediate constant. |
| 0 | 407 // If "which" is call32_operand, selects the displacement of a call or jump. |
| 408 // Caller is responsible for ensuring that there is such an operand, | |
| 304 | 409 // and that it is 32/64 bits wide. |
| 0 | 410 |
| 411 // If "which" is end_pc_operand, find the end of the instruction. | |
| 412 | |
| 413 address ip = inst; | |
| 304 | 414 bool is_64bit = false; |
| 415 | |
| 416 debug_only(bool has_disp32 = false); | |
| 417 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn | |
| 418 | |
| 419 again_after_prefix: | |
| 0 | 420 switch (0xFF & *ip++) { |
| 421 | |
| 422 // These convenience macros generate groups of "case" labels for the switch. | |
| 304 | 423 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3 |
| 424 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \ | |
| 0 | 425 case (x)+4: case (x)+5: case (x)+6: case (x)+7 |
| 304 | 426 #define REP16(x) REP8((x)+0): \ |
| 0 | 427 case REP8((x)+8) |
| 428 | |
| 429 case CS_segment: | |
| 430 case SS_segment: | |
| 431 case DS_segment: | |
| 432 case ES_segment: | |
| 433 case FS_segment: | |
| 434 case GS_segment: | |
| 304 | 435 // Seems dubious |
| 436 LP64_ONLY(assert(false, "shouldn't have that prefix")); | |
| 0 | 437 assert(ip == inst+1, "only one prefix allowed"); |
| 438 goto again_after_prefix; | |
| 439 | |
| 304 | 440 case 0x67: |
| 441 case REX: | |
| 442 case REX_B: | |
| 443 case REX_X: | |
| 444 case REX_XB: | |
| 445 case REX_R: | |
| 446 case REX_RB: | |
| 447 case REX_RX: | |
| 448 case REX_RXB: | |
| 449 NOT_LP64(assert(false, "64bit prefixes")); | |
| 450 goto again_after_prefix; | |
| 451 | |
| 452 case REX_W: | |
| 453 case REX_WB: | |
| 454 case REX_WX: | |
| 455 case REX_WXB: | |
| 456 case REX_WR: | |
| 457 case REX_WRB: | |
| 458 case REX_WRX: | |
| 459 case REX_WRXB: | |
| 460 NOT_LP64(assert(false, "64bit prefixes")); | |
| 461 is_64bit = true; | |
| 462 goto again_after_prefix; | |
| 463 | |
| 464 case 0xFF: // pushq a; decl a; incl a; call a; jmp a | |
| 0 | 465 case 0x88: // movb a, r |
| 466 case 0x89: // movl a, r | |
| 467 case 0x8A: // movb r, a | |
| 468 case 0x8B: // movl r, a | |
| 469 case 0x8F: // popl a | |
| 304 | 470 debug_only(has_disp32 = true); |
| 0 | 471 break; |
| 472 | |
| 304 | 473 case 0x68: // pushq #32 |
| 474 if (which == end_pc_operand) { | |
| 475 return ip + 4; | |
| 476 } | |
| 477 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate"); | |
| 0 | 478 return ip; // not produced by emit_operand |
| 479 | |
| 480 case 0x66: // movw ... (size prefix) | |
| 304 | 481 again_after_size_prefix2: |
| 0 | 482 switch (0xFF & *ip++) { |
| 304 | 483 case REX: |
| 484 case REX_B: | |
| 485 case REX_X: | |
| 486 case REX_XB: | |
| 487 case REX_R: | |
| 488 case REX_RB: | |
| 489 case REX_RX: | |
| 490 case REX_RXB: | |
| 491 case REX_W: | |
| 492 case REX_WB: | |
| 493 case REX_WX: | |
| 494 case REX_WXB: | |
| 495 case REX_WR: | |
| 496 case REX_WRB: | |
| 497 case REX_WRX: | |
| 498 case REX_WRXB: | |
| 499 NOT_LP64(assert(false, "64bit prefix found")); | |
| 500 goto again_after_size_prefix2; | |
| 0 | 501 case 0x8B: // movw r, a |
| 502 case 0x89: // movw a, r | |
| 304 | 503 debug_only(has_disp32 = true); |
| 0 | 504 break; |
| 505 case 0xC7: // movw a, #16 | |
| 304 | 506 debug_only(has_disp32 = true); |
| 0 | 507 tail_size = 2; // the imm16 |
| 508 break; | |
| 509 case 0x0F: // several SSE/SSE2 variants | |
| 510 ip--; // reparse the 0x0F | |
| 511 goto again_after_prefix; | |
| 512 default: | |
| 513 ShouldNotReachHere(); | |
| 514 } | |
| 515 break; | |
| 516 | |
| 304 | 517 case REP8(0xB8): // movl/q r, #32/#64(oop?) |
| 518 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4); | |
| 519 // these asserts are somewhat nonsensical | |
| 520 #ifndef _LP64 | |
| 521 assert(which == imm_operand || which == disp32_operand, ""); | |
| 522 #else | |
| 523 assert((which == call32_operand || which == imm_operand) && is_64bit || | |
| 524 which == narrow_oop_operand && !is_64bit, ""); | |
| 525 #endif // _LP64 | |
| 0 | 526 return ip; |
| 527 | |
| 528 case 0x69: // imul r, a, #32 | |
| 529 case 0xC7: // movl a, #32(oop?) | |
| 530 tail_size = 4; | |
| 304 | 531 debug_only(has_disp32 = true); // has both kinds of operands! |
| 0 | 532 break; |
| 533 | |
| 534 case 0x0F: // movx..., etc. | |
| 535 switch (0xFF & *ip++) { | |
| 536 case 0x12: // movlps | |
| 537 case 0x28: // movaps | |
| 538 case 0x2E: // ucomiss | |
| 539 case 0x2F: // comiss | |
| 540 case 0x54: // andps | |
| 541 case 0x55: // andnps | |
| 542 case 0x56: // orps | |
| 543 case 0x57: // xorps | |
| 544 case 0x6E: // movd | |
| 545 case 0x7E: // movd | |
| 546 case 0xAE: // ldmxcsr a | |
| 304 | 547 // 64bit side says it these have both operands but that doesn't |
| 548 // appear to be true | |
| 549 debug_only(has_disp32 = true); | |
| 0 | 550 break; |
| 551 | |
| 552 case 0xAD: // shrd r, a, %cl | |
| 553 case 0xAF: // imul r, a | |
| 304 | 554 case 0xBE: // movsbl r, a (movsxb) |
| 555 case 0xBF: // movswl r, a (movsxw) | |
| 556 case 0xB6: // movzbl r, a (movzxb) | |
| 557 case 0xB7: // movzwl r, a (movzxw) | |
| 0 | 558 case REP16(0x40): // cmovl cc, r, a |
| 559 case 0xB0: // cmpxchgb | |
| 560 case 0xB1: // cmpxchg | |
| 561 case 0xC1: // xaddl | |
| 562 case 0xC7: // cmpxchg8 | |
| 563 case REP16(0x90): // setcc a | |
| 304 | 564 debug_only(has_disp32 = true); |
| 0 | 565 // fall out of the switch to decode the address |
| 566 break; | |
| 304 | 567 |
| 0 | 568 case 0xAC: // shrd r, a, #8 |
| 304 | 569 debug_only(has_disp32 = true); |
| 0 | 570 tail_size = 1; // the imm8 |
| 571 break; | |
| 304 | 572 |
| 0 | 573 case REP16(0x80): // jcc rdisp32 |
| 574 if (which == end_pc_operand) return ip + 4; | |
| 304 | 575 assert(which == call32_operand, "jcc has no disp32 or imm"); |
| 0 | 576 return ip; |
| 577 default: | |
| 578 ShouldNotReachHere(); | |
| 579 } | |
| 580 break; | |
| 581 | |
| 582 case 0x81: // addl a, #32; addl r, #32 | |
| 583 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl | |
| 304 | 584 // on 32bit in the case of cmpl, the imm might be an oop |
| 0 | 585 tail_size = 4; |
| 304 | 586 debug_only(has_disp32 = true); // has both kinds of operands! |
| 0 | 587 break; |
| 588 | |
| 589 case 0x83: // addl a, #8; addl r, #8 | |
| 590 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl | |
| 304 | 591 debug_only(has_disp32 = true); // has both kinds of operands! |
| 0 | 592 tail_size = 1; |
| 593 break; | |
| 594 | |
| 595 case 0x9B: | |
| 596 switch (0xFF & *ip++) { | |
| 597 case 0xD9: // fnstcw a | |
| 304 | 598 debug_only(has_disp32 = true); |
| 0 | 599 break; |
| 600 default: | |
| 601 ShouldNotReachHere(); | |
| 602 } | |
| 603 break; | |
| 604 | |
| 605 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a | |
| 606 case REP4(0x10): // adc... | |
| 607 case REP4(0x20): // and... | |
| 608 case REP4(0x30): // xor... | |
| 609 case REP4(0x08): // or... | |
| 610 case REP4(0x18): // sbb... | |
| 611 case REP4(0x28): // sub... | |
| 304 | 612 case 0xF7: // mull a |
| 613 case 0x8D: // lea r, a | |
| 614 case 0x87: // xchg r, a | |
| 0 | 615 case REP4(0x38): // cmp... |
| 304 | 616 case 0x85: // test r, a |
| 617 debug_only(has_disp32 = true); // has both kinds of operands! | |
| 0 | 618 break; |
| 619 | |
| 620 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8 | |
| 621 case 0xC6: // movb a, #8 | |
| 622 case 0x80: // cmpb a, #8 | |
| 623 case 0x6B: // imul r, a, #8 | |
| 304 | 624 debug_only(has_disp32 = true); // has both kinds of operands! |
| 0 | 625 tail_size = 1; // the imm8 |
| 626 break; | |
| 627 | |
| 628 case 0xE8: // call rdisp32 | |
| 629 case 0xE9: // jmp rdisp32 | |
| 630 if (which == end_pc_operand) return ip + 4; | |
| 304 | 631 assert(which == call32_operand, "call has no disp32 or imm"); |
| 0 | 632 return ip; |
| 633 | |
| 634 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1 | |
| 635 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl | |
| 636 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a | |
| 637 case 0xDD: // fld_d a; fst_d a; fstp_d a | |
| 638 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a | |
| 639 case 0xDF: // fild_d a; fistp_d a | |
| 640 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a | |
| 641 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a | |
| 642 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a | |
| 304 | 643 debug_only(has_disp32 = true); |
| 0 | 644 break; |
| 645 | |
|
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646 case 0xF0: // Lock |
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647 assert(os::is_MP(), "only on MP"); |
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648 goto again_after_prefix; |
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649 |
| 0 | 650 case 0xF3: // For SSE |
| 651 case 0xF2: // For SSE2 | |
| 304 | 652 switch (0xFF & *ip++) { |
| 653 case REX: | |
| 654 case REX_B: | |
| 655 case REX_X: | |
| 656 case REX_XB: | |
| 657 case REX_R: | |
| 658 case REX_RB: | |
| 659 case REX_RX: | |
| 660 case REX_RXB: | |
| 661 case REX_W: | |
| 662 case REX_WB: | |
| 663 case REX_WX: | |
| 664 case REX_WXB: | |
| 665 case REX_WR: | |
| 666 case REX_WRB: | |
| 667 case REX_WRX: | |
| 668 case REX_WRXB: | |
| 669 NOT_LP64(assert(false, "found 64bit prefix")); | |
| 670 ip++; | |
| 671 default: | |
| 672 ip++; | |
| 673 } | |
| 674 debug_only(has_disp32 = true); // has both kinds of operands! | |
| 0 | 675 break; |
| 676 | |
| 677 default: | |
| 678 ShouldNotReachHere(); | |
| 679 | |
| 304 | 680 #undef REP8 |
| 681 #undef REP16 | |
| 0 | 682 } |
| 683 | |
| 684 assert(which != call32_operand, "instruction is not a call, jmp, or jcc"); | |
| 304 | 685 #ifdef _LP64 |
| 686 assert(which != imm_operand, "instruction is not a movq reg, imm64"); | |
| 687 #else | |
| 688 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field"); | |
| 689 assert(which != imm_operand || has_disp32, "instruction has no imm32 field"); | |
| 690 #endif // LP64 | |
| 691 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field"); | |
| 0 | 692 |
| 693 // parse the output of emit_operand | |
| 694 int op2 = 0xFF & *ip++; | |
| 695 int base = op2 & 0x07; | |
| 696 int op3 = -1; | |
| 697 const int b100 = 4; | |
| 698 const int b101 = 5; | |
| 699 if (base == b100 && (op2 >> 6) != 3) { | |
| 700 op3 = 0xFF & *ip++; | |
| 701 base = op3 & 0x07; // refetch the base | |
| 702 } | |
| 703 // now ip points at the disp (if any) | |
| 704 | |
| 705 switch (op2 >> 6) { | |
| 706 case 0: | |
| 707 // [00 reg 100][ss index base] | |
| 304 | 708 // [00 reg 100][00 100 esp] |
| 0 | 709 // [00 reg base] |
| 710 // [00 reg 100][ss index 101][disp32] | |
| 711 // [00 reg 101] [disp32] | |
| 712 | |
| 713 if (base == b101) { | |
| 714 if (which == disp32_operand) | |
| 715 return ip; // caller wants the disp32 | |
| 716 ip += 4; // skip the disp32 | |
| 717 } | |
| 718 break; | |
| 719 | |
| 720 case 1: | |
| 721 // [01 reg 100][ss index base][disp8] | |
| 304 | 722 // [01 reg 100][00 100 esp][disp8] |
| 0 | 723 // [01 reg base] [disp8] |
| 724 ip += 1; // skip the disp8 | |
| 725 break; | |
| 726 | |
| 727 case 2: | |
| 728 // [10 reg 100][ss index base][disp32] | |
| 304 | 729 // [10 reg 100][00 100 esp][disp32] |
| 0 | 730 // [10 reg base] [disp32] |
| 731 if (which == disp32_operand) | |
| 732 return ip; // caller wants the disp32 | |
| 733 ip += 4; // skip the disp32 | |
| 734 break; | |
| 735 | |
| 736 case 3: | |
| 737 // [11 reg base] (not a memory addressing mode) | |
| 738 break; | |
| 739 } | |
| 740 | |
| 741 if (which == end_pc_operand) { | |
| 742 return ip + tail_size; | |
| 743 } | |
| 744 | |
| 304 | 745 #ifdef _LP64 |
|
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746 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32"); |
| 304 | 747 #else |
| 748 assert(which == imm_operand, "instruction has only an imm field"); | |
| 749 #endif // LP64 | |
| 0 | 750 return ip; |
| 751 } | |
| 752 | |
| 753 address Assembler::locate_next_instruction(address inst) { | |
| 754 // Secretly share code with locate_operand: | |
| 755 return locate_operand(inst, end_pc_operand); | |
| 756 } | |
| 757 | |
| 758 | |
| 759 #ifdef ASSERT | |
| 760 void Assembler::check_relocation(RelocationHolder const& rspec, int format) { | |
| 761 address inst = inst_mark(); | |
| 762 assert(inst != NULL && inst < pc(), "must point to beginning of instruction"); | |
| 763 address opnd; | |
| 764 | |
| 765 Relocation* r = rspec.reloc(); | |
| 766 if (r->type() == relocInfo::none) { | |
| 767 return; | |
| 768 } else if (r->is_call() || format == call32_operand) { | |
| 769 // assert(format == imm32_operand, "cannot specify a nonzero format"); | |
| 770 opnd = locate_operand(inst, call32_operand); | |
| 771 } else if (r->is_data()) { | |
| 304 | 772 assert(format == imm_operand || format == disp32_operand |
| 773 LP64_ONLY(|| format == narrow_oop_operand), "format ok"); | |
| 0 | 774 opnd = locate_operand(inst, (WhichOperand)format); |
| 775 } else { | |
| 304 | 776 assert(format == imm_operand, "cannot specify a format"); |
| 0 | 777 return; |
| 778 } | |
| 779 assert(opnd == pc(), "must put operand where relocs can find it"); | |
| 780 } | |
| 304 | 781 #endif // ASSERT |
| 782 | |
| 783 void Assembler::emit_operand32(Register reg, Address adr) { | |
| 784 assert(reg->encoding() < 8, "no extended registers"); | |
| 785 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); | |
| 786 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |
| 787 adr._rspec); | |
| 788 } | |
| 789 | |
| 790 void Assembler::emit_operand(Register reg, Address adr, | |
| 791 int rip_relative_correction) { | |
| 792 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |
| 793 adr._rspec, | |
| 794 rip_relative_correction); | |
| 795 } | |
| 796 | |
| 797 void Assembler::emit_operand(XMMRegister reg, Address adr) { | |
| 798 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |
| 799 adr._rspec); | |
| 800 } | |
| 801 | |
| 802 // MMX operations | |
| 803 void Assembler::emit_operand(MMXRegister reg, Address adr) { | |
| 804 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); | |
| 805 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); | |
| 806 } | |
| 807 | |
| 808 // work around gcc (3.2.1-7a) bug | |
| 809 void Assembler::emit_operand(Address adr, MMXRegister reg) { | |
| 810 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); | |
| 811 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); | |
| 0 | 812 } |
| 813 | |
| 814 | |
| 815 void Assembler::emit_farith(int b1, int b2, int i) { | |
| 816 assert(isByte(b1) && isByte(b2), "wrong opcode"); | |
| 817 assert(0 <= i && i < 8, "illegal stack offset"); | |
| 818 emit_byte(b1); | |
| 819 emit_byte(b2 + i); | |
| 820 } | |
| 821 | |
| 822 | |
|
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823 // Now the Assembler instructions (identical for 32/64 bits) |
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824 |
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825 void Assembler::adcl(Address dst, int32_t imm32) { |
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826 InstructionMark im(this); |
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827 prefix(dst); |
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828 emit_arith_operand(0x81, rdx, dst, imm32); |
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829 } |
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830 |
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831 void Assembler::adcl(Address dst, Register src) { |
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832 InstructionMark im(this); |
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833 prefix(dst, src); |
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834 emit_byte(0x11); |
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835 emit_operand(src, dst); |
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836 } |
| 304 | 837 |
| 838 void Assembler::adcl(Register dst, int32_t imm32) { | |
| 839 prefix(dst); | |
| 0 | 840 emit_arith(0x81, 0xD0, dst, imm32); |
| 841 } | |
| 842 | |
| 843 void Assembler::adcl(Register dst, Address src) { | |
| 844 InstructionMark im(this); | |
| 304 | 845 prefix(src, dst); |
| 0 | 846 emit_byte(0x13); |
| 847 emit_operand(dst, src); | |
| 848 } | |
| 849 | |
| 850 void Assembler::adcl(Register dst, Register src) { | |
| 304 | 851 (void) prefix_and_encode(dst->encoding(), src->encoding()); |
| 0 | 852 emit_arith(0x13, 0xC0, dst, src); |
| 853 } | |
| 854 | |
| 304 | 855 void Assembler::addl(Address dst, int32_t imm32) { |
| 856 InstructionMark im(this); | |
| 857 prefix(dst); | |
| 858 emit_arith_operand(0x81, rax, dst, imm32); | |
| 859 } | |
| 0 | 860 |
| 861 void Assembler::addl(Address dst, Register src) { | |
| 862 InstructionMark im(this); | |
| 304 | 863 prefix(dst, src); |
| 0 | 864 emit_byte(0x01); |
| 865 emit_operand(src, dst); | |
| 866 } | |
| 867 | |
| 304 | 868 void Assembler::addl(Register dst, int32_t imm32) { |
| 869 prefix(dst); | |
| 0 | 870 emit_arith(0x81, 0xC0, dst, imm32); |
| 871 } | |
| 872 | |
| 873 void Assembler::addl(Register dst, Address src) { | |
| 874 InstructionMark im(this); | |
| 304 | 875 prefix(src, dst); |
| 0 | 876 emit_byte(0x03); |
| 877 emit_operand(dst, src); | |
| 878 } | |
| 879 | |
| 880 void Assembler::addl(Register dst, Register src) { | |
| 304 | 881 (void) prefix_and_encode(dst->encoding(), src->encoding()); |
| 0 | 882 emit_arith(0x03, 0xC0, dst, src); |
| 883 } | |
| 884 | |
| 885 void Assembler::addr_nop_4() { | |
| 886 // 4 bytes: NOP DWORD PTR [EAX+0] | |
| 887 emit_byte(0x0F); | |
| 888 emit_byte(0x1F); | |
| 889 emit_byte(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc); | |
| 890 emit_byte(0); // 8-bits offset (1 byte) | |
| 891 } | |
| 892 | |
| 893 void Assembler::addr_nop_5() { | |
| 894 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset | |
| 895 emit_byte(0x0F); | |
| 896 emit_byte(0x1F); | |
| 897 emit_byte(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4); | |
| 898 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); | |
| 899 emit_byte(0); // 8-bits offset (1 byte) | |
| 900 } | |
| 901 | |
| 902 void Assembler::addr_nop_7() { | |
| 903 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset | |
| 904 emit_byte(0x0F); | |
| 905 emit_byte(0x1F); | |
| 906 emit_byte(0x80); // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc); | |
| 907 emit_long(0); // 32-bits offset (4 bytes) | |
| 908 } | |
| 909 | |
| 910 void Assembler::addr_nop_8() { | |
| 911 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset | |
| 912 emit_byte(0x0F); | |
| 913 emit_byte(0x1F); | |
| 914 emit_byte(0x84); // emit_rm(cbuf, 0x2, EAX_enc, 0x4); | |
| 915 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); | |
| 916 emit_long(0); // 32-bits offset (4 bytes) | |
| 917 } | |
| 918 | |
| 304 | 919 void Assembler::addsd(XMMRegister dst, XMMRegister src) { |
| 920 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 921 emit_byte(0xF2); | |
| 922 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 923 emit_byte(0x0F); | |
| 924 emit_byte(0x58); | |
| 925 emit_byte(0xC0 | encode); | |
| 926 } | |
| 927 | |
| 928 void Assembler::addsd(XMMRegister dst, Address src) { | |
| 929 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 930 InstructionMark im(this); | |
| 931 emit_byte(0xF2); | |
| 932 prefix(src, dst); | |
| 933 emit_byte(0x0F); | |
| 934 emit_byte(0x58); | |
| 935 emit_operand(dst, src); | |
| 936 } | |
| 937 | |
| 938 void Assembler::addss(XMMRegister dst, XMMRegister src) { | |
| 939 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 940 emit_byte(0xF3); | |
| 941 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 942 emit_byte(0x0F); | |
| 943 emit_byte(0x58); | |
| 944 emit_byte(0xC0 | encode); | |
| 945 } | |
| 946 | |
| 947 void Assembler::addss(XMMRegister dst, Address src) { | |
| 948 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 949 InstructionMark im(this); | |
| 950 emit_byte(0xF3); | |
| 951 prefix(src, dst); | |
| 952 emit_byte(0x0F); | |
| 953 emit_byte(0x58); | |
| 954 emit_operand(dst, src); | |
| 955 } | |
| 956 | |
| 957 void Assembler::andl(Register dst, int32_t imm32) { | |
| 958 prefix(dst); | |
| 959 emit_arith(0x81, 0xE0, dst, imm32); | |
| 960 } | |
| 961 | |
| 962 void Assembler::andl(Register dst, Address src) { | |
| 963 InstructionMark im(this); | |
| 964 prefix(src, dst); | |
| 965 emit_byte(0x23); | |
| 966 emit_operand(dst, src); | |
| 967 } | |
| 968 | |
| 969 void Assembler::andl(Register dst, Register src) { | |
| 970 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 971 emit_arith(0x23, 0xC0, dst, src); | |
| 972 } | |
| 973 | |
| 974 void Assembler::andpd(XMMRegister dst, Address src) { | |
| 975 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 976 InstructionMark im(this); | |
| 977 emit_byte(0x66); | |
| 978 prefix(src, dst); | |
| 979 emit_byte(0x0F); | |
| 980 emit_byte(0x54); | |
| 981 emit_operand(dst, src); | |
| 982 } | |
| 983 | |
|
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984 void Assembler::bsfl(Register dst, Register src) { |
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985 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
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986 emit_byte(0x0F); |
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987 emit_byte(0xBC); |
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988 emit_byte(0xC0 | encode); |
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989 } |
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990 |
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991 void Assembler::bsrl(Register dst, Register src) { |
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992 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT"); |
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993 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
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994 emit_byte(0x0F); |
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995 emit_byte(0xBD); |
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996 emit_byte(0xC0 | encode); |
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997 } |
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998 |
| 304 | 999 void Assembler::bswapl(Register reg) { // bswap |
| 1000 int encode = prefix_and_encode(reg->encoding()); | |
| 1001 emit_byte(0x0F); | |
| 1002 emit_byte(0xC8 | encode); | |
| 1003 } | |
| 1004 | |
| 1005 void Assembler::call(Label& L, relocInfo::relocType rtype) { | |
| 1006 // suspect disp32 is always good | |
| 1007 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand); | |
| 1008 | |
| 1009 if (L.is_bound()) { | |
| 1010 const int long_size = 5; | |
| 1011 int offs = (int)( target(L) - pc() ); | |
| 1012 assert(offs <= 0, "assembler error"); | |
| 1013 InstructionMark im(this); | |
| 1014 // 1110 1000 #32-bit disp | |
| 1015 emit_byte(0xE8); | |
| 1016 emit_data(offs - long_size, rtype, operand); | |
| 1017 } else { | |
| 1018 InstructionMark im(this); | |
| 1019 // 1110 1000 #32-bit disp | |
| 1020 L.add_patch_at(code(), locator()); | |
| 1021 | |
| 1022 emit_byte(0xE8); | |
| 1023 emit_data(int(0), rtype, operand); | |
| 1024 } | |
| 1025 } | |
| 1026 | |
| 1027 void Assembler::call(Register dst) { | |
| 1028 // This was originally using a 32bit register encoding | |
| 1029 // and surely we want 64bit! | |
| 1030 // this is a 32bit encoding but in 64bit mode the default | |
| 1031 // operand size is 64bit so there is no need for the | |
| 1032 // wide prefix. So prefix only happens if we use the | |
| 1033 // new registers. Much like push/pop. | |
| 1034 int x = offset(); | |
| 1035 // this may be true but dbx disassembles it as if it | |
| 1036 // were 32bits... | |
| 1037 // int encode = prefix_and_encode(dst->encoding()); | |
| 1038 // if (offset() != x) assert(dst->encoding() >= 8, "what?"); | |
| 1039 int encode = prefixq_and_encode(dst->encoding()); | |
| 1040 | |
| 1041 emit_byte(0xFF); | |
| 1042 emit_byte(0xD0 | encode); | |
| 1043 } | |
| 1044 | |
| 1045 | |
| 1046 void Assembler::call(Address adr) { | |
| 1047 InstructionMark im(this); | |
| 1048 prefix(adr); | |
| 1049 emit_byte(0xFF); | |
| 1050 emit_operand(rdx, adr); | |
| 1051 } | |
| 1052 | |
| 1053 void Assembler::call_literal(address entry, RelocationHolder const& rspec) { | |
| 1054 assert(entry != NULL, "call most probably wrong"); | |
| 1055 InstructionMark im(this); | |
| 1056 emit_byte(0xE8); | |
| 1057 intptr_t disp = entry - (_code_pos + sizeof(int32_t)); | |
| 1058 assert(is_simm32(disp), "must be 32bit offset (call2)"); | |
| 1059 // Technically, should use call32_operand, but this format is | |
| 1060 // implied by the fact that we're emitting a call instruction. | |
| 1061 | |
| 1062 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand); | |
| 1063 emit_data((int) disp, rspec, operand); | |
| 1064 } | |
| 1065 | |
| 1066 void Assembler::cdql() { | |
| 1067 emit_byte(0x99); | |
| 1068 } | |
| 1069 | |
| 1070 void Assembler::cmovl(Condition cc, Register dst, Register src) { | |
| 1071 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); | |
| 1072 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1073 emit_byte(0x0F); | |
| 1074 emit_byte(0x40 | cc); | |
| 1075 emit_byte(0xC0 | encode); | |
| 1076 } | |
| 1077 | |
| 1078 | |
| 1079 void Assembler::cmovl(Condition cc, Register dst, Address src) { | |
| 1080 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); | |
| 1081 prefix(src, dst); | |
| 1082 emit_byte(0x0F); | |
| 1083 emit_byte(0x40 | cc); | |
| 1084 emit_operand(dst, src); | |
| 1085 } | |
| 1086 | |
| 1087 void Assembler::cmpb(Address dst, int imm8) { | |
| 1088 InstructionMark im(this); | |
| 1089 prefix(dst); | |
| 1090 emit_byte(0x80); | |
| 1091 emit_operand(rdi, dst, 1); | |
| 1092 emit_byte(imm8); | |
| 1093 } | |
| 1094 | |
| 1095 void Assembler::cmpl(Address dst, int32_t imm32) { | |
| 1096 InstructionMark im(this); | |
| 1097 prefix(dst); | |
| 1098 emit_byte(0x81); | |
| 1099 emit_operand(rdi, dst, 4); | |
| 1100 emit_long(imm32); | |
| 1101 } | |
| 1102 | |
| 1103 void Assembler::cmpl(Register dst, int32_t imm32) { | |
| 1104 prefix(dst); | |
| 1105 emit_arith(0x81, 0xF8, dst, imm32); | |
| 1106 } | |
| 1107 | |
| 1108 void Assembler::cmpl(Register dst, Register src) { | |
| 1109 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1110 emit_arith(0x3B, 0xC0, dst, src); | |
| 1111 } | |
| 1112 | |
| 1113 | |
| 1114 void Assembler::cmpl(Register dst, Address src) { | |
| 1115 InstructionMark im(this); | |
| 1116 prefix(src, dst); | |
| 1117 emit_byte(0x3B); | |
| 1118 emit_operand(dst, src); | |
| 1119 } | |
| 1120 | |
| 1121 void Assembler::cmpw(Address dst, int imm16) { | |
| 1122 InstructionMark im(this); | |
| 1123 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers"); | |
| 1124 emit_byte(0x66); | |
| 1125 emit_byte(0x81); | |
| 1126 emit_operand(rdi, dst, 2); | |
| 1127 emit_word(imm16); | |
| 1128 } | |
| 1129 | |
| 1130 // The 32-bit cmpxchg compares the value at adr with the contents of rax, | |
| 1131 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,. | |
| 1132 // The ZF is set if the compared values were equal, and cleared otherwise. | |
| 1133 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg | |
| 1134 if (Atomics & 2) { | |
| 1135 // caveat: no instructionmark, so this isn't relocatable. | |
| 1136 // Emit a synthetic, non-atomic, CAS equivalent. | |
| 1137 // Beware. The synthetic form sets all ICCs, not just ZF. | |
| 1138 // cmpxchg r,[m] is equivalent to rax, = CAS (m, rax, r) | |
| 1139 cmpl(rax, adr); | |
| 1140 movl(rax, adr); | |
| 1141 if (reg != rax) { | |
| 1142 Label L ; | |
| 1143 jcc(Assembler::notEqual, L); | |
| 1144 movl(adr, reg); | |
| 1145 bind(L); | |
| 1146 } | |
| 1147 } else { | |
| 1148 InstructionMark im(this); | |
| 1149 prefix(adr, reg); | |
| 1150 emit_byte(0x0F); | |
| 1151 emit_byte(0xB1); | |
| 1152 emit_operand(reg, adr); | |
| 1153 } | |
| 1154 } | |
| 1155 | |
| 1156 void Assembler::comisd(XMMRegister dst, Address src) { | |
| 1157 // NOTE: dbx seems to decode this as comiss even though the | |
| 1158 // 0x66 is there. Strangly ucomisd comes out correct | |
| 1159 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1160 emit_byte(0x66); | |
| 1161 comiss(dst, src); | |
| 1162 } | |
| 1163 | |
| 1164 void Assembler::comiss(XMMRegister dst, Address src) { | |
| 1165 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1166 | |
| 1167 InstructionMark im(this); | |
| 1168 prefix(src, dst); | |
| 1169 emit_byte(0x0F); | |
| 1170 emit_byte(0x2F); | |
| 1171 emit_operand(dst, src); | |
| 1172 } | |
| 1173 | |
| 1174 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) { | |
| 1175 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1176 emit_byte(0xF3); | |
| 1177 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1178 emit_byte(0x0F); | |
| 1179 emit_byte(0xE6); | |
| 1180 emit_byte(0xC0 | encode); | |
| 1181 } | |
| 1182 | |
| 1183 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) { | |
| 1184 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1185 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1186 emit_byte(0x0F); | |
| 1187 emit_byte(0x5B); | |
| 1188 emit_byte(0xC0 | encode); | |
| 1189 } | |
| 1190 | |
| 1191 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) { | |
| 1192 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1193 emit_byte(0xF2); | |
| 1194 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1195 emit_byte(0x0F); | |
| 1196 emit_byte(0x5A); | |
| 1197 emit_byte(0xC0 | encode); | |
| 1198 } | |
| 1199 | |
| 1200 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) { | |
| 1201 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1202 emit_byte(0xF2); | |
| 1203 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1204 emit_byte(0x0F); | |
| 1205 emit_byte(0x2A); | |
| 1206 emit_byte(0xC0 | encode); | |
| 1207 } | |
| 1208 | |
| 1209 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) { | |
| 1210 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1211 emit_byte(0xF3); | |
| 1212 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1213 emit_byte(0x0F); | |
| 1214 emit_byte(0x2A); | |
| 1215 emit_byte(0xC0 | encode); | |
| 1216 } | |
| 1217 | |
| 1218 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) { | |
| 1219 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1220 emit_byte(0xF3); | |
| 1221 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1222 emit_byte(0x0F); | |
| 1223 emit_byte(0x5A); | |
| 1224 emit_byte(0xC0 | encode); | |
| 1225 } | |
| 1226 | |
| 1227 void Assembler::cvttsd2sil(Register dst, XMMRegister src) { | |
| 1228 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1229 emit_byte(0xF2); | |
| 1230 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1231 emit_byte(0x0F); | |
| 1232 emit_byte(0x2C); | |
| 1233 emit_byte(0xC0 | encode); | |
| 1234 } | |
| 1235 | |
| 1236 void Assembler::cvttss2sil(Register dst, XMMRegister src) { | |
| 1237 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1238 emit_byte(0xF3); | |
| 1239 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1240 emit_byte(0x0F); | |
| 1241 emit_byte(0x2C); | |
| 1242 emit_byte(0xC0 | encode); | |
| 1243 } | |
| 1244 | |
| 1245 void Assembler::decl(Address dst) { | |
| 1246 // Don't use it directly. Use MacroAssembler::decrement() instead. | |
| 1247 InstructionMark im(this); | |
| 1248 prefix(dst); | |
| 1249 emit_byte(0xFF); | |
| 1250 emit_operand(rcx, dst); | |
| 1251 } | |
| 1252 | |
| 1253 void Assembler::divsd(XMMRegister dst, Address src) { | |
| 1254 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1255 InstructionMark im(this); | |
| 1256 emit_byte(0xF2); | |
| 1257 prefix(src, dst); | |
| 1258 emit_byte(0x0F); | |
| 1259 emit_byte(0x5E); | |
| 1260 emit_operand(dst, src); | |
| 1261 } | |
| 1262 | |
| 1263 void Assembler::divsd(XMMRegister dst, XMMRegister src) { | |
| 1264 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1265 emit_byte(0xF2); | |
| 1266 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1267 emit_byte(0x0F); | |
| 1268 emit_byte(0x5E); | |
| 1269 emit_byte(0xC0 | encode); | |
| 1270 } | |
| 1271 | |
| 1272 void Assembler::divss(XMMRegister dst, Address src) { | |
| 1273 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1274 InstructionMark im(this); | |
| 1275 emit_byte(0xF3); | |
| 1276 prefix(src, dst); | |
| 1277 emit_byte(0x0F); | |
| 1278 emit_byte(0x5E); | |
| 1279 emit_operand(dst, src); | |
| 1280 } | |
| 1281 | |
| 1282 void Assembler::divss(XMMRegister dst, XMMRegister src) { | |
| 1283 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1284 emit_byte(0xF3); | |
| 1285 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1286 emit_byte(0x0F); | |
| 1287 emit_byte(0x5E); | |
| 1288 emit_byte(0xC0 | encode); | |
| 1289 } | |
| 1290 | |
| 1291 void Assembler::emms() { | |
| 1292 NOT_LP64(assert(VM_Version::supports_mmx(), "")); | |
| 1293 emit_byte(0x0F); | |
| 1294 emit_byte(0x77); | |
| 1295 } | |
| 1296 | |
| 1297 void Assembler::hlt() { | |
| 1298 emit_byte(0xF4); | |
| 1299 } | |
| 1300 | |
| 1301 void Assembler::idivl(Register src) { | |
| 1302 int encode = prefix_and_encode(src->encoding()); | |
| 1303 emit_byte(0xF7); | |
| 1304 emit_byte(0xF8 | encode); | |
| 1305 } | |
| 1306 | |
| 1920 | 1307 void Assembler::divl(Register src) { // Unsigned |
| 1308 int encode = prefix_and_encode(src->encoding()); | |
| 1309 emit_byte(0xF7); | |
| 1310 emit_byte(0xF0 | encode); | |
| 1311 } | |
| 1312 | |
| 304 | 1313 void Assembler::imull(Register dst, Register src) { |
| 1314 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1315 emit_byte(0x0F); | |
| 1316 emit_byte(0xAF); | |
| 1317 emit_byte(0xC0 | encode); | |
| 1318 } | |
| 1319 | |
| 1320 | |
| 1321 void Assembler::imull(Register dst, Register src, int value) { | |
| 1322 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1323 if (is8bit(value)) { | |
| 1324 emit_byte(0x6B); | |
| 1325 emit_byte(0xC0 | encode); | |
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1326 emit_byte(value & 0xFF); |
| 304 | 1327 } else { |
| 1328 emit_byte(0x69); | |
| 1329 emit_byte(0xC0 | encode); | |
| 1330 emit_long(value); | |
| 1331 } | |
| 1332 } | |
| 1333 | |
| 1334 void Assembler::incl(Address dst) { | |
| 1335 // Don't use it directly. Use MacroAssembler::increment() instead. | |
| 1336 InstructionMark im(this); | |
| 1337 prefix(dst); | |
| 1338 emit_byte(0xFF); | |
| 1339 emit_operand(rax, dst); | |
| 1340 } | |
| 1341 | |
| 1342 void Assembler::jcc(Condition cc, Label& L, relocInfo::relocType rtype) { | |
| 1343 InstructionMark im(this); | |
| 1344 relocate(rtype); | |
| 1345 assert((0 <= cc) && (cc < 16), "illegal cc"); | |
| 1346 if (L.is_bound()) { | |
| 1347 address dst = target(L); | |
| 1348 assert(dst != NULL, "jcc most probably wrong"); | |
| 1349 | |
| 1350 const int short_size = 2; | |
| 1351 const int long_size = 6; | |
| 1352 intptr_t offs = (intptr_t)dst - (intptr_t)_code_pos; | |
| 1353 if (rtype == relocInfo::none && is8bit(offs - short_size)) { | |
| 1354 // 0111 tttn #8-bit disp | |
| 1355 emit_byte(0x70 | cc); | |
| 1356 emit_byte((offs - short_size) & 0xFF); | |
| 1357 } else { | |
| 1358 // 0000 1111 1000 tttn #32-bit disp | |
| 1359 assert(is_simm32(offs - long_size), | |
| 1360 "must be 32bit offset (call4)"); | |
| 1361 emit_byte(0x0F); | |
| 1362 emit_byte(0x80 | cc); | |
| 1363 emit_long(offs - long_size); | |
| 1364 } | |
| 1365 } else { | |
| 1366 // Note: could eliminate cond. jumps to this jump if condition | |
| 1367 // is the same however, seems to be rather unlikely case. | |
| 1368 // Note: use jccb() if label to be bound is very close to get | |
| 1369 // an 8-bit displacement | |
| 1370 L.add_patch_at(code(), locator()); | |
| 1371 emit_byte(0x0F); | |
| 1372 emit_byte(0x80 | cc); | |
| 1373 emit_long(0); | |
| 1374 } | |
| 1375 } | |
| 1376 | |
| 1377 void Assembler::jccb(Condition cc, Label& L) { | |
| 1378 if (L.is_bound()) { | |
| 1379 const int short_size = 2; | |
| 1380 address entry = target(L); | |
| 1381 assert(is8bit((intptr_t)entry - ((intptr_t)_code_pos + short_size)), | |
| 1382 "Dispacement too large for a short jmp"); | |
| 1383 intptr_t offs = (intptr_t)entry - (intptr_t)_code_pos; | |
| 1384 // 0111 tttn #8-bit disp | |
| 1385 emit_byte(0x70 | cc); | |
| 1386 emit_byte((offs - short_size) & 0xFF); | |
| 1387 } else { | |
| 1388 InstructionMark im(this); | |
| 1389 L.add_patch_at(code(), locator()); | |
| 1390 emit_byte(0x70 | cc); | |
| 1391 emit_byte(0); | |
| 1392 } | |
| 1393 } | |
| 1394 | |
| 1395 void Assembler::jmp(Address adr) { | |
| 1396 InstructionMark im(this); | |
| 1397 prefix(adr); | |
| 1398 emit_byte(0xFF); | |
| 1399 emit_operand(rsp, adr); | |
| 1400 } | |
| 1401 | |
| 1402 void Assembler::jmp(Label& L, relocInfo::relocType rtype) { | |
| 1403 if (L.is_bound()) { | |
| 1404 address entry = target(L); | |
| 1405 assert(entry != NULL, "jmp most probably wrong"); | |
| 1406 InstructionMark im(this); | |
| 1407 const int short_size = 2; | |
| 1408 const int long_size = 5; | |
| 1409 intptr_t offs = entry - _code_pos; | |
| 1410 if (rtype == relocInfo::none && is8bit(offs - short_size)) { | |
| 1411 emit_byte(0xEB); | |
| 1412 emit_byte((offs - short_size) & 0xFF); | |
| 1413 } else { | |
| 1414 emit_byte(0xE9); | |
| 1415 emit_long(offs - long_size); | |
| 1416 } | |
| 1417 } else { | |
| 1418 // By default, forward jumps are always 32-bit displacements, since | |
| 1419 // we can't yet know where the label will be bound. If you're sure that | |
| 1420 // the forward jump will not run beyond 256 bytes, use jmpb to | |
| 1421 // force an 8-bit displacement. | |
| 1422 InstructionMark im(this); | |
| 1423 relocate(rtype); | |
| 1424 L.add_patch_at(code(), locator()); | |
| 1425 emit_byte(0xE9); | |
| 1426 emit_long(0); | |
| 1427 } | |
| 1428 } | |
| 1429 | |
| 1430 void Assembler::jmp(Register entry) { | |
| 1431 int encode = prefix_and_encode(entry->encoding()); | |
| 1432 emit_byte(0xFF); | |
| 1433 emit_byte(0xE0 | encode); | |
| 1434 } | |
| 1435 | |
| 1436 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) { | |
| 1437 InstructionMark im(this); | |
| 1438 emit_byte(0xE9); | |
| 1439 assert(dest != NULL, "must have a target"); | |
| 1440 intptr_t disp = dest - (_code_pos + sizeof(int32_t)); | |
| 1441 assert(is_simm32(disp), "must be 32bit offset (jmp)"); | |
| 1442 emit_data(disp, rspec.reloc(), call32_operand); | |
| 1443 } | |
| 1444 | |
| 1445 void Assembler::jmpb(Label& L) { | |
| 1446 if (L.is_bound()) { | |
| 1447 const int short_size = 2; | |
| 1448 address entry = target(L); | |
| 1449 assert(is8bit((entry - _code_pos) + short_size), | |
| 1450 "Dispacement too large for a short jmp"); | |
| 1451 assert(entry != NULL, "jmp most probably wrong"); | |
| 1452 intptr_t offs = entry - _code_pos; | |
| 1453 emit_byte(0xEB); | |
| 1454 emit_byte((offs - short_size) & 0xFF); | |
| 1455 } else { | |
| 1456 InstructionMark im(this); | |
| 1457 L.add_patch_at(code(), locator()); | |
| 1458 emit_byte(0xEB); | |
| 1459 emit_byte(0); | |
| 1460 } | |
| 1461 } | |
| 1462 | |
| 1463 void Assembler::ldmxcsr( Address src) { | |
| 1464 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1465 InstructionMark im(this); | |
| 1466 prefix(src); | |
| 1467 emit_byte(0x0F); | |
| 1468 emit_byte(0xAE); | |
| 1469 emit_operand(as_Register(2), src); | |
| 1470 } | |
| 1471 | |
| 1472 void Assembler::leal(Register dst, Address src) { | |
| 1473 InstructionMark im(this); | |
| 1474 #ifdef _LP64 | |
| 1475 emit_byte(0x67); // addr32 | |
| 1476 prefix(src, dst); | |
| 1477 #endif // LP64 | |
| 1478 emit_byte(0x8D); | |
| 1479 emit_operand(dst, src); | |
| 1480 } | |
| 1481 | |
| 1482 void Assembler::lock() { | |
| 1483 if (Atomics & 1) { | |
| 1484 // Emit either nothing, a NOP, or a NOP: prefix | |
| 1485 emit_byte(0x90) ; | |
| 1486 } else { | |
| 1487 emit_byte(0xF0); | |
| 1488 } | |
| 1489 } | |
| 1490 | |
|
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1491 void Assembler::lzcntl(Register dst, Register src) { |
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1492 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); |
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1493 emit_byte(0xF3); |
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1494 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
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1495 emit_byte(0x0F); |
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1496 emit_byte(0xBD); |
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1497 emit_byte(0xC0 | encode); |
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1498 } |
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1499 |
|
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1500 // Emit mfence instruction |
| 304 | 1501 void Assembler::mfence() { |
|
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1502 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");) |
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1503 emit_byte( 0x0F ); |
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1504 emit_byte( 0xAE ); |
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1505 emit_byte( 0xF0 ); |
| 304 | 1506 } |
| 1507 | |
| 1508 void Assembler::mov(Register dst, Register src) { | |
| 1509 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
| 1510 } | |
| 1511 | |
| 1512 void Assembler::movapd(XMMRegister dst, XMMRegister src) { | |
| 1513 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1514 int dstenc = dst->encoding(); | |
| 1515 int srcenc = src->encoding(); | |
| 1516 emit_byte(0x66); | |
| 1517 if (dstenc < 8) { | |
| 1518 if (srcenc >= 8) { | |
| 1519 prefix(REX_B); | |
| 1520 srcenc -= 8; | |
| 1521 } | |
| 1522 } else { | |
| 1523 if (srcenc < 8) { | |
| 1524 prefix(REX_R); | |
| 1525 } else { | |
| 1526 prefix(REX_RB); | |
| 1527 srcenc -= 8; | |
| 1528 } | |
| 1529 dstenc -= 8; | |
| 1530 } | |
| 1531 emit_byte(0x0F); | |
| 1532 emit_byte(0x28); | |
| 1533 emit_byte(0xC0 | dstenc << 3 | srcenc); | |
| 1534 } | |
| 1535 | |
| 1536 void Assembler::movaps(XMMRegister dst, XMMRegister src) { | |
| 1537 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1538 int dstenc = dst->encoding(); | |
| 1539 int srcenc = src->encoding(); | |
| 1540 if (dstenc < 8) { | |
| 1541 if (srcenc >= 8) { | |
| 1542 prefix(REX_B); | |
| 1543 srcenc -= 8; | |
| 1544 } | |
| 1545 } else { | |
| 1546 if (srcenc < 8) { | |
| 1547 prefix(REX_R); | |
| 1548 } else { | |
| 1549 prefix(REX_RB); | |
| 1550 srcenc -= 8; | |
| 1551 } | |
| 1552 dstenc -= 8; | |
| 1553 } | |
| 1554 emit_byte(0x0F); | |
| 1555 emit_byte(0x28); | |
| 1556 emit_byte(0xC0 | dstenc << 3 | srcenc); | |
| 1557 } | |
| 1558 | |
| 1559 void Assembler::movb(Register dst, Address src) { | |
| 1560 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); | |
| 1561 InstructionMark im(this); | |
| 1562 prefix(src, dst, true); | |
| 1563 emit_byte(0x8A); | |
| 1564 emit_operand(dst, src); | |
| 1565 } | |
| 1566 | |
| 1567 | |
| 1568 void Assembler::movb(Address dst, int imm8) { | |
| 1569 InstructionMark im(this); | |
| 1570 prefix(dst); | |
| 1571 emit_byte(0xC6); | |
| 1572 emit_operand(rax, dst, 1); | |
| 1573 emit_byte(imm8); | |
| 1574 } | |
| 1575 | |
| 1576 | |
| 1577 void Assembler::movb(Address dst, Register src) { | |
| 1578 assert(src->has_byte_register(), "must have byte register"); | |
| 1579 InstructionMark im(this); | |
| 1580 prefix(dst, src, true); | |
| 1581 emit_byte(0x88); | |
| 1582 emit_operand(src, dst); | |
| 1583 } | |
| 1584 | |
| 1585 void Assembler::movdl(XMMRegister dst, Register src) { | |
| 1586 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1587 emit_byte(0x66); | |
| 1588 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1589 emit_byte(0x0F); | |
| 1590 emit_byte(0x6E); | |
| 1591 emit_byte(0xC0 | encode); | |
| 1592 } | |
| 1593 | |
| 1594 void Assembler::movdl(Register dst, XMMRegister src) { | |
| 1595 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1596 emit_byte(0x66); | |
| 1597 // swap src/dst to get correct prefix | |
| 1598 int encode = prefix_and_encode(src->encoding(), dst->encoding()); | |
| 1599 emit_byte(0x0F); | |
| 1600 emit_byte(0x7E); | |
| 1601 emit_byte(0xC0 | encode); | |
| 1602 } | |
| 1603 | |
| 1604 void Assembler::movdqa(XMMRegister dst, Address src) { | |
| 1605 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1606 InstructionMark im(this); | |
| 1607 emit_byte(0x66); | |
| 1608 prefix(src, dst); | |
| 1609 emit_byte(0x0F); | |
| 1610 emit_byte(0x6F); | |
| 1611 emit_operand(dst, src); | |
| 1612 } | |
| 1613 | |
| 1614 void Assembler::movdqa(XMMRegister dst, XMMRegister src) { | |
| 1615 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1616 emit_byte(0x66); | |
| 1617 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 1618 emit_byte(0x0F); | |
| 1619 emit_byte(0x6F); | |
| 1620 emit_byte(0xC0 | encode); | |
| 1621 } | |
| 1622 | |
| 1623 void Assembler::movdqa(Address dst, XMMRegister src) { | |
| 1624 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1625 InstructionMark im(this); | |
| 1626 emit_byte(0x66); | |
| 1627 prefix(dst, src); | |
| 1628 emit_byte(0x0F); | |
| 1629 emit_byte(0x7F); | |
| 1630 emit_operand(src, dst); | |
| 1631 } | |
| 1632 | |
| 405 | 1633 void Assembler::movdqu(XMMRegister dst, Address src) { |
| 1634 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1635 InstructionMark im(this); | |
| 1636 emit_byte(0xF3); | |
| 1637 prefix(src, dst); | |
| 1638 emit_byte(0x0F); | |
| 1639 emit_byte(0x6F); | |
| 1640 emit_operand(dst, src); | |
| 1641 } | |
| 1642 | |
| 1643 void Assembler::movdqu(XMMRegister dst, XMMRegister src) { | |
| 1644 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1645 emit_byte(0xF3); | |
| 1646 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 1647 emit_byte(0x0F); | |
| 1648 emit_byte(0x6F); | |
| 1649 emit_byte(0xC0 | encode); | |
| 1650 } | |
| 1651 | |
| 1652 void Assembler::movdqu(Address dst, XMMRegister src) { | |
| 1653 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1654 InstructionMark im(this); | |
| 1655 emit_byte(0xF3); | |
| 1656 prefix(dst, src); | |
| 1657 emit_byte(0x0F); | |
| 1658 emit_byte(0x7F); | |
| 1659 emit_operand(src, dst); | |
| 1660 } | |
| 1661 | |
| 304 | 1662 // Uses zero extension on 64bit |
| 1663 | |
| 1664 void Assembler::movl(Register dst, int32_t imm32) { | |
| 1665 int encode = prefix_and_encode(dst->encoding()); | |
| 1666 emit_byte(0xB8 | encode); | |
| 1667 emit_long(imm32); | |
| 1668 } | |
| 1669 | |
| 1670 void Assembler::movl(Register dst, Register src) { | |
| 1671 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1672 emit_byte(0x8B); | |
| 1673 emit_byte(0xC0 | encode); | |
| 1674 } | |
| 1675 | |
| 1676 void Assembler::movl(Register dst, Address src) { | |
| 1677 InstructionMark im(this); | |
| 1678 prefix(src, dst); | |
| 1679 emit_byte(0x8B); | |
| 1680 emit_operand(dst, src); | |
| 1681 } | |
| 1682 | |
| 1683 void Assembler::movl(Address dst, int32_t imm32) { | |
| 1684 InstructionMark im(this); | |
| 1685 prefix(dst); | |
| 1686 emit_byte(0xC7); | |
| 1687 emit_operand(rax, dst, 4); | |
| 1688 emit_long(imm32); | |
| 1689 } | |
| 1690 | |
| 1691 void Assembler::movl(Address dst, Register src) { | |
| 1692 InstructionMark im(this); | |
| 1693 prefix(dst, src); | |
| 1694 emit_byte(0x89); | |
| 1695 emit_operand(src, dst); | |
| 1696 } | |
| 1697 | |
| 1698 // New cpus require to use movsd and movss to avoid partial register stall | |
| 1699 // when loading from memory. But for old Opteron use movlpd instead of movsd. | |
| 1700 // The selection is done in MacroAssembler::movdbl() and movflt(). | |
| 1701 void Assembler::movlpd(XMMRegister dst, Address src) { | |
| 1702 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1703 InstructionMark im(this); | |
| 1704 emit_byte(0x66); | |
| 1705 prefix(src, dst); | |
| 1706 emit_byte(0x0F); | |
| 1707 emit_byte(0x12); | |
| 1708 emit_operand(dst, src); | |
| 1709 } | |
| 1710 | |
| 1711 void Assembler::movq( MMXRegister dst, Address src ) { | |
| 1712 assert( VM_Version::supports_mmx(), "" ); | |
| 1713 emit_byte(0x0F); | |
| 1714 emit_byte(0x6F); | |
| 1715 emit_operand(dst, src); | |
| 1716 } | |
| 1717 | |
| 1718 void Assembler::movq( Address dst, MMXRegister src ) { | |
| 1719 assert( VM_Version::supports_mmx(), "" ); | |
| 1720 emit_byte(0x0F); | |
| 1721 emit_byte(0x7F); | |
| 1722 // workaround gcc (3.2.1-7a) bug | |
| 1723 // In that version of gcc with only an emit_operand(MMX, Address) | |
| 1724 // gcc will tail jump and try and reverse the parameters completely | |
| 1725 // obliterating dst in the process. By having a version available | |
| 1726 // that doesn't need to swap the args at the tail jump the bug is | |
| 1727 // avoided. | |
| 1728 emit_operand(dst, src); | |
| 1729 } | |
| 1730 | |
| 1731 void Assembler::movq(XMMRegister dst, Address src) { | |
| 1732 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1733 InstructionMark im(this); | |
| 1734 emit_byte(0xF3); | |
| 1735 prefix(src, dst); | |
| 1736 emit_byte(0x0F); | |
| 1737 emit_byte(0x7E); | |
| 1738 emit_operand(dst, src); | |
| 1739 } | |
| 1740 | |
| 1741 void Assembler::movq(Address dst, XMMRegister src) { | |
| 1742 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1743 InstructionMark im(this); | |
| 1744 emit_byte(0x66); | |
| 1745 prefix(dst, src); | |
| 1746 emit_byte(0x0F); | |
| 1747 emit_byte(0xD6); | |
| 1748 emit_operand(src, dst); | |
| 1749 } | |
| 1750 | |
| 1751 void Assembler::movsbl(Register dst, Address src) { // movsxb | |
| 1752 InstructionMark im(this); | |
| 1753 prefix(src, dst); | |
| 1754 emit_byte(0x0F); | |
| 1755 emit_byte(0xBE); | |
| 1756 emit_operand(dst, src); | |
| 1757 } | |
| 1758 | |
| 1759 void Assembler::movsbl(Register dst, Register src) { // movsxb | |
| 1760 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); | |
| 1761 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true); | |
| 1762 emit_byte(0x0F); | |
| 1763 emit_byte(0xBE); | |
| 1764 emit_byte(0xC0 | encode); | |
| 1765 } | |
| 1766 | |
| 1767 void Assembler::movsd(XMMRegister dst, XMMRegister src) { | |
| 1768 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1769 emit_byte(0xF2); | |
| 1770 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1771 emit_byte(0x0F); | |
| 1772 emit_byte(0x10); | |
| 1773 emit_byte(0xC0 | encode); | |
| 1774 } | |
| 1775 | |
| 1776 void Assembler::movsd(XMMRegister dst, Address src) { | |
| 1777 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1778 InstructionMark im(this); | |
| 1779 emit_byte(0xF2); | |
| 1780 prefix(src, dst); | |
| 1781 emit_byte(0x0F); | |
| 1782 emit_byte(0x10); | |
| 1783 emit_operand(dst, src); | |
| 1784 } | |
| 1785 | |
| 1786 void Assembler::movsd(Address dst, XMMRegister src) { | |
| 1787 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1788 InstructionMark im(this); | |
| 1789 emit_byte(0xF2); | |
| 1790 prefix(dst, src); | |
| 1791 emit_byte(0x0F); | |
| 1792 emit_byte(0x11); | |
| 1793 emit_operand(src, dst); | |
| 1794 } | |
| 1795 | |
| 1796 void Assembler::movss(XMMRegister dst, XMMRegister src) { | |
| 1797 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1798 emit_byte(0xF3); | |
| 1799 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1800 emit_byte(0x0F); | |
| 1801 emit_byte(0x10); | |
| 1802 emit_byte(0xC0 | encode); | |
| 1803 } | |
| 1804 | |
| 1805 void Assembler::movss(XMMRegister dst, Address src) { | |
| 1806 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1807 InstructionMark im(this); | |
| 1808 emit_byte(0xF3); | |
| 1809 prefix(src, dst); | |
| 1810 emit_byte(0x0F); | |
| 1811 emit_byte(0x10); | |
| 1812 emit_operand(dst, src); | |
| 1813 } | |
| 1814 | |
| 1815 void Assembler::movss(Address dst, XMMRegister src) { | |
| 1816 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1817 InstructionMark im(this); | |
| 1818 emit_byte(0xF3); | |
| 1819 prefix(dst, src); | |
| 1820 emit_byte(0x0F); | |
| 1821 emit_byte(0x11); | |
| 1822 emit_operand(src, dst); | |
| 1823 } | |
| 1824 | |
| 1825 void Assembler::movswl(Register dst, Address src) { // movsxw | |
| 1826 InstructionMark im(this); | |
| 1827 prefix(src, dst); | |
| 1828 emit_byte(0x0F); | |
| 1829 emit_byte(0xBF); | |
| 1830 emit_operand(dst, src); | |
| 1831 } | |
| 1832 | |
| 1833 void Assembler::movswl(Register dst, Register src) { // movsxw | |
| 1834 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1835 emit_byte(0x0F); | |
| 1836 emit_byte(0xBF); | |
| 1837 emit_byte(0xC0 | encode); | |
| 1838 } | |
| 1839 | |
| 1840 void Assembler::movw(Address dst, int imm16) { | |
| 1841 InstructionMark im(this); | |
| 1842 | |
| 1843 emit_byte(0x66); // switch to 16-bit mode | |
| 1844 prefix(dst); | |
| 1845 emit_byte(0xC7); | |
| 1846 emit_operand(rax, dst, 2); | |
| 1847 emit_word(imm16); | |
| 1848 } | |
| 1849 | |
| 1850 void Assembler::movw(Register dst, Address src) { | |
| 1851 InstructionMark im(this); | |
| 1852 emit_byte(0x66); | |
| 1853 prefix(src, dst); | |
| 1854 emit_byte(0x8B); | |
| 1855 emit_operand(dst, src); | |
| 1856 } | |
| 1857 | |
| 1858 void Assembler::movw(Address dst, Register src) { | |
| 1859 InstructionMark im(this); | |
| 1860 emit_byte(0x66); | |
| 1861 prefix(dst, src); | |
| 1862 emit_byte(0x89); | |
| 1863 emit_operand(src, dst); | |
| 1864 } | |
| 1865 | |
| 1866 void Assembler::movzbl(Register dst, Address src) { // movzxb | |
| 1867 InstructionMark im(this); | |
| 1868 prefix(src, dst); | |
| 1869 emit_byte(0x0F); | |
| 1870 emit_byte(0xB6); | |
| 1871 emit_operand(dst, src); | |
| 1872 } | |
| 1873 | |
| 1874 void Assembler::movzbl(Register dst, Register src) { // movzxb | |
| 1875 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); | |
| 1876 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true); | |
| 1877 emit_byte(0x0F); | |
| 1878 emit_byte(0xB6); | |
| 1879 emit_byte(0xC0 | encode); | |
| 1880 } | |
| 1881 | |
| 1882 void Assembler::movzwl(Register dst, Address src) { // movzxw | |
| 1883 InstructionMark im(this); | |
| 1884 prefix(src, dst); | |
| 1885 emit_byte(0x0F); | |
| 1886 emit_byte(0xB7); | |
| 1887 emit_operand(dst, src); | |
| 1888 } | |
| 1889 | |
| 1890 void Assembler::movzwl(Register dst, Register src) { // movzxw | |
| 1891 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1892 emit_byte(0x0F); | |
| 1893 emit_byte(0xB7); | |
| 1894 emit_byte(0xC0 | encode); | |
| 1895 } | |
| 1896 | |
| 1897 void Assembler::mull(Address src) { | |
| 1898 InstructionMark im(this); | |
| 1899 prefix(src); | |
| 1900 emit_byte(0xF7); | |
| 1901 emit_operand(rsp, src); | |
| 1902 } | |
| 1903 | |
| 1904 void Assembler::mull(Register src) { | |
| 1905 int encode = prefix_and_encode(src->encoding()); | |
| 1906 emit_byte(0xF7); | |
| 1907 emit_byte(0xE0 | encode); | |
| 1908 } | |
| 1909 | |
| 1910 void Assembler::mulsd(XMMRegister dst, Address src) { | |
| 1911 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1912 InstructionMark im(this); | |
| 1913 emit_byte(0xF2); | |
| 1914 prefix(src, dst); | |
| 1915 emit_byte(0x0F); | |
| 1916 emit_byte(0x59); | |
| 1917 emit_operand(dst, src); | |
| 1918 } | |
| 1919 | |
| 1920 void Assembler::mulsd(XMMRegister dst, XMMRegister src) { | |
| 1921 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1922 emit_byte(0xF2); | |
| 1923 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1924 emit_byte(0x0F); | |
| 1925 emit_byte(0x59); | |
| 1926 emit_byte(0xC0 | encode); | |
| 1927 } | |
| 1928 | |
| 1929 void Assembler::mulss(XMMRegister dst, Address src) { | |
| 1930 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1931 InstructionMark im(this); | |
| 1932 emit_byte(0xF3); | |
| 1933 prefix(src, dst); | |
| 1934 emit_byte(0x0F); | |
| 1935 emit_byte(0x59); | |
| 1936 emit_operand(dst, src); | |
| 1937 } | |
| 1938 | |
| 1939 void Assembler::mulss(XMMRegister dst, XMMRegister src) { | |
| 1940 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1941 emit_byte(0xF3); | |
| 1942 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1943 emit_byte(0x0F); | |
| 1944 emit_byte(0x59); | |
| 1945 emit_byte(0xC0 | encode); | |
| 1946 } | |
| 1947 | |
| 1948 void Assembler::negl(Register dst) { | |
| 1949 int encode = prefix_and_encode(dst->encoding()); | |
| 1950 emit_byte(0xF7); | |
| 1951 emit_byte(0xD8 | encode); | |
| 1952 } | |
| 1953 | |
| 0 | 1954 void Assembler::nop(int i) { |
| 304 | 1955 #ifdef ASSERT |
| 0 | 1956 assert(i > 0, " "); |
| 304 | 1957 // The fancy nops aren't currently recognized by debuggers making it a |
| 1958 // pain to disassemble code while debugging. If asserts are on clearly | |
| 1959 // speed is not an issue so simply use the single byte traditional nop | |
| 1960 // to do alignment. | |
| 1961 | |
| 1962 for (; i > 0 ; i--) emit_byte(0x90); | |
| 1963 return; | |
| 1964 | |
| 1965 #endif // ASSERT | |
| 1966 | |
| 0 | 1967 if (UseAddressNop && VM_Version::is_intel()) { |
| 1968 // | |
| 1969 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel | |
| 1970 // 1: 0x90 | |
| 1971 // 2: 0x66 0x90 | |
| 1972 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) | |
| 1973 // 4: 0x0F 0x1F 0x40 0x00 | |
| 1974 // 5: 0x0F 0x1F 0x44 0x00 0x00 | |
| 1975 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
| 1976 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
| 1977 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 1978 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 1979 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 1980 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 1981 | |
| 1982 // The rest coding is Intel specific - don't use consecutive address nops | |
| 1983 | |
| 1984 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
| 1985 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
| 1986 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
| 1987 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
| 1988 | |
| 1989 while(i >= 15) { | |
| 1990 // For Intel don't generate consecutive addess nops (mix with regular nops) | |
| 1991 i -= 15; | |
| 1992 emit_byte(0x66); // size prefix | |
| 1993 emit_byte(0x66); // size prefix | |
| 1994 emit_byte(0x66); // size prefix | |
| 1995 addr_nop_8(); | |
| 1996 emit_byte(0x66); // size prefix | |
| 1997 emit_byte(0x66); // size prefix | |
| 1998 emit_byte(0x66); // size prefix | |
| 1999 emit_byte(0x90); // nop | |
| 2000 } | |
| 2001 switch (i) { | |
| 2002 case 14: | |
| 2003 emit_byte(0x66); // size prefix | |
| 2004 case 13: | |
| 2005 emit_byte(0x66); // size prefix | |
| 2006 case 12: | |
| 2007 addr_nop_8(); | |
| 2008 emit_byte(0x66); // size prefix | |
| 2009 emit_byte(0x66); // size prefix | |
| 2010 emit_byte(0x66); // size prefix | |
| 2011 emit_byte(0x90); // nop | |
| 2012 break; | |
| 2013 case 11: | |
| 2014 emit_byte(0x66); // size prefix | |
| 2015 case 10: | |
| 2016 emit_byte(0x66); // size prefix | |
| 2017 case 9: | |
| 2018 emit_byte(0x66); // size prefix | |
| 2019 case 8: | |
| 2020 addr_nop_8(); | |
| 2021 break; | |
| 2022 case 7: | |
| 2023 addr_nop_7(); | |
| 2024 break; | |
| 2025 case 6: | |
| 2026 emit_byte(0x66); // size prefix | |
| 2027 case 5: | |
| 2028 addr_nop_5(); | |
| 2029 break; | |
| 2030 case 4: | |
| 2031 addr_nop_4(); | |
| 2032 break; | |
| 2033 case 3: | |
| 2034 // Don't use "0x0F 0x1F 0x00" - need patching safe padding | |
| 2035 emit_byte(0x66); // size prefix | |
| 2036 case 2: | |
| 2037 emit_byte(0x66); // size prefix | |
| 2038 case 1: | |
| 2039 emit_byte(0x90); // nop | |
| 2040 break; | |
| 2041 default: | |
| 2042 assert(i == 0, " "); | |
| 2043 } | |
| 2044 return; | |
| 2045 } | |
| 2046 if (UseAddressNop && VM_Version::is_amd()) { | |
| 2047 // | |
| 2048 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD. | |
| 2049 // 1: 0x90 | |
| 2050 // 2: 0x66 0x90 | |
| 2051 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) | |
| 2052 // 4: 0x0F 0x1F 0x40 0x00 | |
| 2053 // 5: 0x0F 0x1F 0x44 0x00 0x00 | |
| 2054 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
| 2055 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
| 2056 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 2057 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 2058 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 2059 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 2060 | |
| 2061 // The rest coding is AMD specific - use consecutive address nops | |
| 2062 | |
| 2063 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
| 2064 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
| 2065 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
| 2066 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
| 2067 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 2068 // Size prefixes (0x66) are added for larger sizes | |
| 2069 | |
| 2070 while(i >= 22) { | |
| 2071 i -= 11; | |
| 2072 emit_byte(0x66); // size prefix | |
| 2073 emit_byte(0x66); // size prefix | |
| 2074 emit_byte(0x66); // size prefix | |
| 2075 addr_nop_8(); | |
| 2076 } | |
| 2077 // Generate first nop for size between 21-12 | |
| 2078 switch (i) { | |
| 2079 case 21: | |
| 2080 i -= 1; | |
| 2081 emit_byte(0x66); // size prefix | |
| 2082 case 20: | |
| 2083 case 19: | |
| 2084 i -= 1; | |
| 2085 emit_byte(0x66); // size prefix | |
| 2086 case 18: | |
| 2087 case 17: | |
| 2088 i -= 1; | |
| 2089 emit_byte(0x66); // size prefix | |
| 2090 case 16: | |
| 2091 case 15: | |
| 2092 i -= 8; | |
| 2093 addr_nop_8(); | |
| 2094 break; | |
| 2095 case 14: | |
| 2096 case 13: | |
| 2097 i -= 7; | |
| 2098 addr_nop_7(); | |
| 2099 break; | |
| 2100 case 12: | |
| 2101 i -= 6; | |
| 2102 emit_byte(0x66); // size prefix | |
| 2103 addr_nop_5(); | |
| 2104 break; | |
| 2105 default: | |
| 2106 assert(i < 12, " "); | |
| 2107 } | |
| 2108 | |
| 2109 // Generate second nop for size between 11-1 | |
| 2110 switch (i) { | |
| 2111 case 11: | |
| 2112 emit_byte(0x66); // size prefix | |
| 2113 case 10: | |
| 2114 emit_byte(0x66); // size prefix | |
| 2115 case 9: | |
| 2116 emit_byte(0x66); // size prefix | |
| 2117 case 8: | |
| 2118 addr_nop_8(); | |
| 2119 break; | |
| 2120 case 7: | |
| 2121 addr_nop_7(); | |
| 2122 break; | |
| 2123 case 6: | |
| 2124 emit_byte(0x66); // size prefix | |
| 2125 case 5: | |
| 2126 addr_nop_5(); | |
| 2127 break; | |
| 2128 case 4: | |
| 2129 addr_nop_4(); | |
| 2130 break; | |
| 2131 case 3: | |
| 2132 // Don't use "0x0F 0x1F 0x00" - need patching safe padding | |
| 2133 emit_byte(0x66); // size prefix | |
| 2134 case 2: | |
| 2135 emit_byte(0x66); // size prefix | |
| 2136 case 1: | |
| 2137 emit_byte(0x90); // nop | |
| 2138 break; | |
| 2139 default: | |
| 2140 assert(i == 0, " "); | |
| 2141 } | |
| 2142 return; | |
| 2143 } | |
| 2144 | |
| 2145 // Using nops with size prefixes "0x66 0x90". | |
| 2146 // From AMD Optimization Guide: | |
| 2147 // 1: 0x90 | |
| 2148 // 2: 0x66 0x90 | |
| 2149 // 3: 0x66 0x66 0x90 | |
| 2150 // 4: 0x66 0x66 0x66 0x90 | |
| 2151 // 5: 0x66 0x66 0x90 0x66 0x90 | |
| 2152 // 6: 0x66 0x66 0x90 0x66 0x66 0x90 | |
| 2153 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 | |
| 2154 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90 | |
| 2155 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 | |
| 2156 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 | |
| 2157 // | |
| 2158 while(i > 12) { | |
| 2159 i -= 4; | |
| 2160 emit_byte(0x66); // size prefix | |
| 2161 emit_byte(0x66); | |
| 2162 emit_byte(0x66); | |
| 2163 emit_byte(0x90); // nop | |
| 2164 } | |
| 2165 // 1 - 12 nops | |
| 2166 if(i > 8) { | |
| 2167 if(i > 9) { | |
| 2168 i -= 1; | |
| 2169 emit_byte(0x66); | |
| 2170 } | |
| 2171 i -= 3; | |
| 2172 emit_byte(0x66); | |
| 2173 emit_byte(0x66); | |
| 2174 emit_byte(0x90); | |
| 2175 } | |
| 2176 // 1 - 8 nops | |
| 2177 if(i > 4) { | |
| 2178 if(i > 6) { | |
| 2179 i -= 1; | |
| 2180 emit_byte(0x66); | |
| 2181 } | |
| 2182 i -= 3; | |
| 2183 emit_byte(0x66); | |
| 2184 emit_byte(0x66); | |
| 2185 emit_byte(0x90); | |
| 2186 } | |
| 2187 switch (i) { | |
| 2188 case 4: | |
| 2189 emit_byte(0x66); | |
| 2190 case 3: | |
| 2191 emit_byte(0x66); | |
| 2192 case 2: | |
| 2193 emit_byte(0x66); | |
| 2194 case 1: | |
| 2195 emit_byte(0x90); | |
| 2196 break; | |
| 2197 default: | |
| 2198 assert(i == 0, " "); | |
| 2199 } | |
| 2200 } | |
| 2201 | |
| 304 | 2202 void Assembler::notl(Register dst) { |
| 2203 int encode = prefix_and_encode(dst->encoding()); | |
| 2204 emit_byte(0xF7); | |
| 2205 emit_byte(0xD0 | encode ); | |
| 2206 } | |
| 2207 | |
| 2208 void Assembler::orl(Address dst, int32_t imm32) { | |
| 2209 InstructionMark im(this); | |
| 2210 prefix(dst); | |
|
2100
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2211 emit_arith_operand(0x81, rcx, dst, imm32); |
| 304 | 2212 } |
| 2213 | |
| 2214 void Assembler::orl(Register dst, int32_t imm32) { | |
| 2215 prefix(dst); | |
| 2216 emit_arith(0x81, 0xC8, dst, imm32); | |
| 2217 } | |
| 2218 | |
| 2219 void Assembler::orl(Register dst, Address src) { | |
| 2220 InstructionMark im(this); | |
| 2221 prefix(src, dst); | |
| 2222 emit_byte(0x0B); | |
| 2223 emit_operand(dst, src); | |
| 2224 } | |
| 2225 | |
| 2226 void Assembler::orl(Register dst, Register src) { | |
| 2227 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2228 emit_arith(0x0B, 0xC0, dst, src); | |
| 2229 } | |
| 2230 | |
| 681 | 2231 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) { |
| 2232 assert(VM_Version::supports_sse4_2(), ""); | |
| 2233 | |
| 2234 InstructionMark im(this); | |
| 2235 emit_byte(0x66); | |
| 2236 prefix(src, dst); | |
| 2237 emit_byte(0x0F); | |
| 2238 emit_byte(0x3A); | |
| 2239 emit_byte(0x61); | |
| 2240 emit_operand(dst, src); | |
| 2241 emit_byte(imm8); | |
| 2242 } | |
| 2243 | |
| 2244 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) { | |
| 2245 assert(VM_Version::supports_sse4_2(), ""); | |
| 2246 | |
| 2247 emit_byte(0x66); | |
| 2248 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 2249 emit_byte(0x0F); | |
| 2250 emit_byte(0x3A); | |
| 2251 emit_byte(0x61); | |
| 2252 emit_byte(0xC0 | encode); | |
| 2253 emit_byte(imm8); | |
| 2254 } | |
| 2255 | |
| 304 | 2256 // generic |
| 2257 void Assembler::pop(Register dst) { | |
| 2258 int encode = prefix_and_encode(dst->encoding()); | |
| 2259 emit_byte(0x58 | encode); | |
| 2260 } | |
| 2261 | |
|
643
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2262 void Assembler::popcntl(Register dst, Address src) { |
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2263 assert(VM_Version::supports_popcnt(), "must support"); |
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2264 InstructionMark im(this); |
|
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2265 emit_byte(0xF3); |
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2266 prefix(src, dst); |
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2267 emit_byte(0x0F); |
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2268 emit_byte(0xB8); |
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2269 emit_operand(dst, src); |
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2270 } |
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2271 |
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2272 void Assembler::popcntl(Register dst, Register src) { |
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2273 assert(VM_Version::supports_popcnt(), "must support"); |
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2274 emit_byte(0xF3); |
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2275 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
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2276 emit_byte(0x0F); |
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2277 emit_byte(0xB8); |
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2278 emit_byte(0xC0 | encode); |
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2279 } |
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2280 |
| 304 | 2281 void Assembler::popf() { |
| 2282 emit_byte(0x9D); | |
| 2283 } | |
| 2284 | |
| 1060 | 2285 #ifndef _LP64 // no 32bit push/pop on amd64 |
| 304 | 2286 void Assembler::popl(Address dst) { |
| 2287 // NOTE: this will adjust stack by 8byte on 64bits | |
| 2288 InstructionMark im(this); | |
| 2289 prefix(dst); | |
| 2290 emit_byte(0x8F); | |
| 2291 emit_operand(rax, dst); | |
| 2292 } | |
| 1060 | 2293 #endif |
| 304 | 2294 |
| 2295 void Assembler::prefetch_prefix(Address src) { | |
| 2296 prefix(src); | |
| 2297 emit_byte(0x0F); | |
| 2298 } | |
| 2299 | |
| 2300 void Assembler::prefetchnta(Address src) { | |
| 2301 NOT_LP64(assert(VM_Version::supports_sse2(), "must support")); | |
| 2302 InstructionMark im(this); | |
| 2303 prefetch_prefix(src); | |
| 2304 emit_byte(0x18); | |
| 2305 emit_operand(rax, src); // 0, src | |
| 2306 } | |
| 2307 | |
| 2308 void Assembler::prefetchr(Address src) { | |
| 2309 NOT_LP64(assert(VM_Version::supports_3dnow(), "must support")); | |
| 2310 InstructionMark im(this); | |
| 2311 prefetch_prefix(src); | |
| 2312 emit_byte(0x0D); | |
| 2313 emit_operand(rax, src); // 0, src | |
| 2314 } | |
| 2315 | |
| 2316 void Assembler::prefetcht0(Address src) { | |
| 2317 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |
| 2318 InstructionMark im(this); | |
| 2319 prefetch_prefix(src); | |
| 2320 emit_byte(0x18); | |
| 2321 emit_operand(rcx, src); // 1, src | |
| 2322 } | |
| 2323 | |
| 2324 void Assembler::prefetcht1(Address src) { | |
| 2325 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |
| 2326 InstructionMark im(this); | |
| 2327 prefetch_prefix(src); | |
| 2328 emit_byte(0x18); | |
| 2329 emit_operand(rdx, src); // 2, src | |
| 2330 } | |
| 2331 | |
| 2332 void Assembler::prefetcht2(Address src) { | |
| 2333 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |
| 2334 InstructionMark im(this); | |
| 2335 prefetch_prefix(src); | |
| 2336 emit_byte(0x18); | |
| 2337 emit_operand(rbx, src); // 3, src | |
| 2338 } | |
| 2339 | |
| 2340 void Assembler::prefetchw(Address src) { | |
| 2341 NOT_LP64(assert(VM_Version::supports_3dnow(), "must support")); | |
| 2342 InstructionMark im(this); | |
| 2343 prefetch_prefix(src); | |
| 2344 emit_byte(0x0D); | |
| 2345 emit_operand(rcx, src); // 1, src | |
| 2346 } | |
| 2347 | |
| 2348 void Assembler::prefix(Prefix p) { | |
| 2349 a_byte(p); | |
| 2350 } | |
| 2351 | |
| 2352 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) { | |
| 2353 assert(isByte(mode), "invalid value"); | |
| 2354 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2355 | |
| 2356 emit_byte(0x66); | |
| 2357 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2358 emit_byte(0x0F); | |
| 2359 emit_byte(0x70); | |
| 2360 emit_byte(0xC0 | encode); | |
| 2361 emit_byte(mode & 0xFF); | |
| 2362 | |
| 2363 } | |
| 2364 | |
| 2365 void Assembler::pshufd(XMMRegister dst, Address src, int mode) { | |
| 2366 assert(isByte(mode), "invalid value"); | |
| 2367 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2368 | |
| 2369 InstructionMark im(this); | |
| 2370 emit_byte(0x66); | |
| 2371 prefix(src, dst); | |
| 2372 emit_byte(0x0F); | |
| 2373 emit_byte(0x70); | |
| 2374 emit_operand(dst, src); | |
| 2375 emit_byte(mode & 0xFF); | |
| 2376 } | |
| 2377 | |
| 2378 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) { | |
| 2379 assert(isByte(mode), "invalid value"); | |
| 2380 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2381 | |
| 2382 emit_byte(0xF2); | |
| 2383 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2384 emit_byte(0x0F); | |
| 2385 emit_byte(0x70); | |
| 2386 emit_byte(0xC0 | encode); | |
| 2387 emit_byte(mode & 0xFF); | |
| 2388 } | |
| 2389 | |
| 2390 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) { | |
| 2391 assert(isByte(mode), "invalid value"); | |
| 2392 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2393 | |
| 2394 InstructionMark im(this); | |
| 2395 emit_byte(0xF2); | |
| 2396 prefix(src, dst); // QQ new | |
| 2397 emit_byte(0x0F); | |
| 2398 emit_byte(0x70); | |
| 2399 emit_operand(dst, src); | |
| 2400 emit_byte(mode & 0xFF); | |
| 2401 } | |
| 2402 | |
| 2403 void Assembler::psrlq(XMMRegister dst, int shift) { | |
| 2404 // HMM Table D-1 says sse2 or mmx | |
| 2405 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 2406 | |
| 2407 int encode = prefixq_and_encode(xmm2->encoding(), dst->encoding()); | |
| 2408 emit_byte(0x66); | |
| 2409 emit_byte(0x0F); | |
| 2410 emit_byte(0x73); | |
| 2411 emit_byte(0xC0 | encode); | |
| 2412 emit_byte(shift); | |
| 2413 } | |
| 2414 | |
| 681 | 2415 void Assembler::ptest(XMMRegister dst, Address src) { |
| 2416 assert(VM_Version::supports_sse4_1(), ""); | |
| 2417 | |
| 2418 InstructionMark im(this); | |
| 2419 emit_byte(0x66); | |
| 2420 prefix(src, dst); | |
| 2421 emit_byte(0x0F); | |
| 2422 emit_byte(0x38); | |
| 2423 emit_byte(0x17); | |
| 2424 emit_operand(dst, src); | |
| 2425 } | |
| 2426 | |
| 2427 void Assembler::ptest(XMMRegister dst, XMMRegister src) { | |
| 2428 assert(VM_Version::supports_sse4_1(), ""); | |
| 2429 | |
| 2430 emit_byte(0x66); | |
| 2431 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 2432 emit_byte(0x0F); | |
| 2433 emit_byte(0x38); | |
| 2434 emit_byte(0x17); | |
| 2435 emit_byte(0xC0 | encode); | |
| 2436 } | |
| 2437 | |
| 304 | 2438 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) { |
| 2439 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2440 emit_byte(0x66); | |
| 2441 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2442 emit_byte(0x0F); | |
| 2443 emit_byte(0x60); | |
| 2444 emit_byte(0xC0 | encode); | |
| 2445 } | |
| 2446 | |
| 2447 void Assembler::push(int32_t imm32) { | |
| 2448 // in 64bits we push 64bits onto the stack but only | |
| 2449 // take a 32bit immediate | |
| 2450 emit_byte(0x68); | |
| 2451 emit_long(imm32); | |
| 2452 } | |
| 2453 | |
| 2454 void Assembler::push(Register src) { | |
| 2455 int encode = prefix_and_encode(src->encoding()); | |
| 2456 | |
| 2457 emit_byte(0x50 | encode); | |
| 2458 } | |
| 2459 | |
| 2460 void Assembler::pushf() { | |
| 2461 emit_byte(0x9C); | |
| 2462 } | |
| 2463 | |
| 1060 | 2464 #ifndef _LP64 // no 32bit push/pop on amd64 |
| 304 | 2465 void Assembler::pushl(Address src) { |
| 2466 // Note this will push 64bit on 64bit | |
| 2467 InstructionMark im(this); | |
| 2468 prefix(src); | |
| 2469 emit_byte(0xFF); | |
| 2470 emit_operand(rsi, src); | |
| 2471 } | |
| 1060 | 2472 #endif |
| 304 | 2473 |
| 2474 void Assembler::pxor(XMMRegister dst, Address src) { | |
| 2475 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2476 InstructionMark im(this); | |
| 2477 emit_byte(0x66); | |
| 2478 prefix(src, dst); | |
| 2479 emit_byte(0x0F); | |
| 2480 emit_byte(0xEF); | |
| 2481 emit_operand(dst, src); | |
| 2482 } | |
| 2483 | |
| 2484 void Assembler::pxor(XMMRegister dst, XMMRegister src) { | |
| 2485 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2486 InstructionMark im(this); | |
| 2487 emit_byte(0x66); | |
| 2488 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2489 emit_byte(0x0F); | |
| 2490 emit_byte(0xEF); | |
| 2491 emit_byte(0xC0 | encode); | |
| 2492 } | |
| 2493 | |
| 2494 void Assembler::rcll(Register dst, int imm8) { | |
| 2495 assert(isShiftCount(imm8), "illegal shift count"); | |
| 2496 int encode = prefix_and_encode(dst->encoding()); | |
| 2497 if (imm8 == 1) { | |
| 2498 emit_byte(0xD1); | |
| 2499 emit_byte(0xD0 | encode); | |
| 2500 } else { | |
| 2501 emit_byte(0xC1); | |
| 2502 emit_byte(0xD0 | encode); | |
| 2503 emit_byte(imm8); | |
| 2504 } | |
| 2505 } | |
| 2506 | |
| 2507 // copies data from [esi] to [edi] using rcx pointer sized words | |
| 2508 // generic | |
| 2509 void Assembler::rep_mov() { | |
| 2510 emit_byte(0xF3); | |
| 2511 // MOVSQ | |
| 2512 LP64_ONLY(prefix(REX_W)); | |
| 2513 emit_byte(0xA5); | |
| 2514 } | |
| 2515 | |
| 2516 // sets rcx pointer sized words with rax, value at [edi] | |
| 2517 // generic | |
| 2518 void Assembler::rep_set() { // rep_set | |
| 2519 emit_byte(0xF3); | |
| 2520 // STOSQ | |
| 2521 LP64_ONLY(prefix(REX_W)); | |
| 2522 emit_byte(0xAB); | |
| 2523 } | |
| 2524 | |
| 2525 // scans rcx pointer sized words at [edi] for occurance of rax, | |
| 2526 // generic | |
| 2527 void Assembler::repne_scan() { // repne_scan | |
| 2528 emit_byte(0xF2); | |
| 2529 // SCASQ | |
| 2530 LP64_ONLY(prefix(REX_W)); | |
| 2531 emit_byte(0xAF); | |
| 2532 } | |
| 2533 | |
| 2534 #ifdef _LP64 | |
| 2535 // scans rcx 4 byte words at [edi] for occurance of rax, | |
| 2536 // generic | |
| 2537 void Assembler::repne_scanl() { // repne_scan | |
| 2538 emit_byte(0xF2); | |
| 2539 // SCASL | |
| 2540 emit_byte(0xAF); | |
| 2541 } | |
| 2542 #endif | |
| 2543 | |
| 0 | 2544 void Assembler::ret(int imm16) { |
| 2545 if (imm16 == 0) { | |
| 2546 emit_byte(0xC3); | |
| 2547 } else { | |
| 2548 emit_byte(0xC2); | |
| 2549 emit_word(imm16); | |
| 2550 } | |
| 2551 } | |
| 2552 | |
| 304 | 2553 void Assembler::sahf() { |
| 2554 #ifdef _LP64 | |
| 2555 // Not supported in 64bit mode | |
| 2556 ShouldNotReachHere(); | |
| 2557 #endif | |
| 2558 emit_byte(0x9E); | |
| 2559 } | |
| 2560 | |
| 2561 void Assembler::sarl(Register dst, int imm8) { | |
| 2562 int encode = prefix_and_encode(dst->encoding()); | |
| 2563 assert(isShiftCount(imm8), "illegal shift count"); | |
| 2564 if (imm8 == 1) { | |
| 2565 emit_byte(0xD1); | |
| 2566 emit_byte(0xF8 | encode); | |
| 2567 } else { | |
| 2568 emit_byte(0xC1); | |
| 2569 emit_byte(0xF8 | encode); | |
| 2570 emit_byte(imm8); | |
| 2571 } | |
| 2572 } | |
| 2573 | |
| 2574 void Assembler::sarl(Register dst) { | |
| 2575 int encode = prefix_and_encode(dst->encoding()); | |
| 2576 emit_byte(0xD3); | |
| 2577 emit_byte(0xF8 | encode); | |
| 2578 } | |
| 2579 | |
| 2580 void Assembler::sbbl(Address dst, int32_t imm32) { | |
| 2581 InstructionMark im(this); | |
| 2582 prefix(dst); | |
| 2583 emit_arith_operand(0x81, rbx, dst, imm32); | |
| 2584 } | |
| 2585 | |
| 2586 void Assembler::sbbl(Register dst, int32_t imm32) { | |
| 2587 prefix(dst); | |
| 2588 emit_arith(0x81, 0xD8, dst, imm32); | |
| 2589 } | |
| 2590 | |
| 2591 | |
| 2592 void Assembler::sbbl(Register dst, Address src) { | |
| 2593 InstructionMark im(this); | |
| 2594 prefix(src, dst); | |
| 2595 emit_byte(0x1B); | |
| 2596 emit_operand(dst, src); | |
| 2597 } | |
| 2598 | |
| 2599 void Assembler::sbbl(Register dst, Register src) { | |
| 2600 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2601 emit_arith(0x1B, 0xC0, dst, src); | |
| 2602 } | |
| 2603 | |
| 2604 void Assembler::setb(Condition cc, Register dst) { | |
| 2605 assert(0 <= cc && cc < 16, "illegal cc"); | |
| 2606 int encode = prefix_and_encode(dst->encoding(), true); | |
| 0 | 2607 emit_byte(0x0F); |
| 304 | 2608 emit_byte(0x90 | cc); |
| 2609 emit_byte(0xC0 | encode); | |
| 2610 } | |
| 2611 | |
| 2612 void Assembler::shll(Register dst, int imm8) { | |
| 2613 assert(isShiftCount(imm8), "illegal shift count"); | |
| 2614 int encode = prefix_and_encode(dst->encoding()); | |
| 2615 if (imm8 == 1 ) { | |
| 2616 emit_byte(0xD1); | |
| 2617 emit_byte(0xE0 | encode); | |
| 2618 } else { | |
| 2619 emit_byte(0xC1); | |
| 2620 emit_byte(0xE0 | encode); | |
| 2621 emit_byte(imm8); | |
| 2622 } | |
| 2623 } | |
| 2624 | |
| 2625 void Assembler::shll(Register dst) { | |
| 2626 int encode = prefix_and_encode(dst->encoding()); | |
| 2627 emit_byte(0xD3); | |
| 2628 emit_byte(0xE0 | encode); | |
| 2629 } | |
| 2630 | |
| 2631 void Assembler::shrl(Register dst, int imm8) { | |
| 2632 assert(isShiftCount(imm8), "illegal shift count"); | |
| 2633 int encode = prefix_and_encode(dst->encoding()); | |
| 2634 emit_byte(0xC1); | |
| 2635 emit_byte(0xE8 | encode); | |
| 2636 emit_byte(imm8); | |
| 2637 } | |
| 2638 | |
| 2639 void Assembler::shrl(Register dst) { | |
| 2640 int encode = prefix_and_encode(dst->encoding()); | |
| 2641 emit_byte(0xD3); | |
| 2642 emit_byte(0xE8 | encode); | |
| 2643 } | |
| 0 | 2644 |
| 2645 // copies a single word from [esi] to [edi] | |
| 2646 void Assembler::smovl() { | |
| 2647 emit_byte(0xA5); | |
| 2648 } | |
| 2649 | |
| 304 | 2650 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) { |
| 2651 // HMM Table D-1 says sse2 | |
| 2652 // NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 2653 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2654 emit_byte(0xF2); | |
| 2655 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2656 emit_byte(0x0F); | |
| 2657 emit_byte(0x51); | |
| 2658 emit_byte(0xC0 | encode); | |
| 2659 } | |
| 2660 | |
| 2008 | 2661 void Assembler::sqrtsd(XMMRegister dst, Address src) { |
| 2662 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2663 InstructionMark im(this); | |
| 2664 emit_byte(0xF2); | |
| 2665 prefix(src, dst); | |
| 2666 emit_byte(0x0F); | |
| 2667 emit_byte(0x51); | |
| 2668 emit_operand(dst, src); | |
| 2669 } | |
| 2670 | |
| 2671 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) { | |
| 2672 // HMM Table D-1 says sse2 | |
| 2673 // NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 2674 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2675 emit_byte(0xF3); | |
| 2676 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2677 emit_byte(0x0F); | |
| 2678 emit_byte(0x51); | |
| 2679 emit_byte(0xC0 | encode); | |
| 2680 } | |
| 2681 | |
| 2682 void Assembler::sqrtss(XMMRegister dst, Address src) { | |
| 2683 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2684 InstructionMark im(this); | |
| 2685 emit_byte(0xF3); | |
| 2686 prefix(src, dst); | |
| 2687 emit_byte(0x0F); | |
| 2688 emit_byte(0x51); | |
| 2689 emit_operand(dst, src); | |
| 2690 } | |
| 2691 | |
| 304 | 2692 void Assembler::stmxcsr( Address dst) { |
| 2693 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 2694 InstructionMark im(this); | |
| 2695 prefix(dst); | |
| 2696 emit_byte(0x0F); | |
| 2697 emit_byte(0xAE); | |
| 2698 emit_operand(as_Register(3), dst); | |
| 2699 } | |
| 2700 | |
| 2701 void Assembler::subl(Address dst, int32_t imm32) { | |
| 2702 InstructionMark im(this); | |
| 2703 prefix(dst); | |
|
2100
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
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|
2704 emit_arith_operand(0x81, rbp, dst, imm32); |
| 304 | 2705 } |
| 2706 | |
| 2707 void Assembler::subl(Address dst, Register src) { | |
| 2708 InstructionMark im(this); | |
| 2709 prefix(dst, src); | |
| 2710 emit_byte(0x29); | |
| 2711 emit_operand(src, dst); | |
| 2712 } | |
| 2713 | |
|
2100
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diff
changeset
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2714 void Assembler::subl(Register dst, int32_t imm32) { |
|
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7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
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parents:
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diff
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|
2715 prefix(dst); |
|
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7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
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diff
changeset
|
2716 emit_arith(0x81, 0xE8, dst, imm32); |
|
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7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
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|
2717 } |
|
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7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
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|
2718 |
| 304 | 2719 void Assembler::subl(Register dst, Address src) { |
| 2720 InstructionMark im(this); | |
| 2721 prefix(src, dst); | |
| 2722 emit_byte(0x2B); | |
| 2723 emit_operand(dst, src); | |
| 2724 } | |
| 2725 | |
| 2726 void Assembler::subl(Register dst, Register src) { | |
| 2727 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2728 emit_arith(0x2B, 0xC0, dst, src); | |
| 2729 } | |
| 2730 | |
| 2731 void Assembler::subsd(XMMRegister dst, XMMRegister src) { | |
| 2732 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2733 emit_byte(0xF2); | |
| 2734 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2735 emit_byte(0x0F); | |
| 2736 emit_byte(0x5C); | |
| 2737 emit_byte(0xC0 | encode); | |
| 2738 } | |
| 2739 | |
| 2740 void Assembler::subsd(XMMRegister dst, Address src) { | |
| 2741 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2742 InstructionMark im(this); | |
| 2743 emit_byte(0xF2); | |
| 2744 prefix(src, dst); | |
| 2745 emit_byte(0x0F); | |
| 2746 emit_byte(0x5C); | |
| 2747 emit_operand(dst, src); | |
| 2748 } | |
| 2749 | |
| 2750 void Assembler::subss(XMMRegister dst, XMMRegister src) { | |
| 2751 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 0 | 2752 emit_byte(0xF3); |
| 304 | 2753 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
| 2754 emit_byte(0x0F); | |
| 2755 emit_byte(0x5C); | |
| 2756 emit_byte(0xC0 | encode); | |
| 2757 } | |
| 2758 | |
| 2759 void Assembler::subss(XMMRegister dst, Address src) { | |
| 2760 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 2761 InstructionMark im(this); | |
| 2762 emit_byte(0xF3); | |
| 2763 prefix(src, dst); | |
| 2764 emit_byte(0x0F); | |
| 2765 emit_byte(0x5C); | |
| 2766 emit_operand(dst, src); | |
| 2767 } | |
| 2768 | |
| 2769 void Assembler::testb(Register dst, int imm8) { | |
| 2770 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); | |
| 2771 (void) prefix_and_encode(dst->encoding(), true); | |
| 2772 emit_arith_b(0xF6, 0xC0, dst, imm8); | |
| 2773 } | |
| 2774 | |
| 2775 void Assembler::testl(Register dst, int32_t imm32) { | |
| 2776 // not using emit_arith because test | |
| 2777 // doesn't support sign-extension of | |
| 2778 // 8bit operands | |
| 2779 int encode = dst->encoding(); | |
| 2780 if (encode == 0) { | |
| 2781 emit_byte(0xA9); | |
| 2782 } else { | |
| 2783 encode = prefix_and_encode(encode); | |
| 2784 emit_byte(0xF7); | |
| 2785 emit_byte(0xC0 | encode); | |
| 2786 } | |
| 2787 emit_long(imm32); | |
| 2788 } | |
| 2789 | |
| 2790 void Assembler::testl(Register dst, Register src) { | |
| 2791 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2792 emit_arith(0x85, 0xC0, dst, src); | |
| 2793 } | |
| 2794 | |
| 2795 void Assembler::testl(Register dst, Address src) { | |
| 2796 InstructionMark im(this); | |
| 2797 prefix(src, dst); | |
| 2798 emit_byte(0x85); | |
| 2799 emit_operand(dst, src); | |
| 2800 } | |
| 2801 | |
| 2802 void Assembler::ucomisd(XMMRegister dst, Address src) { | |
| 2803 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2804 emit_byte(0x66); | |
| 2805 ucomiss(dst, src); | |
| 2806 } | |
| 2807 | |
| 2808 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) { | |
| 2809 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2810 emit_byte(0x66); | |
| 2811 ucomiss(dst, src); | |
| 2812 } | |
| 2813 | |
| 2814 void Assembler::ucomiss(XMMRegister dst, Address src) { | |
| 2815 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 2816 | |
| 2817 InstructionMark im(this); | |
| 2818 prefix(src, dst); | |
| 2819 emit_byte(0x0F); | |
| 2820 emit_byte(0x2E); | |
| 2821 emit_operand(dst, src); | |
| 2822 } | |
| 2823 | |
| 2824 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) { | |
| 2825 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 2826 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2827 emit_byte(0x0F); | |
| 2828 emit_byte(0x2E); | |
| 2829 emit_byte(0xC0 | encode); | |
| 2830 } | |
| 2831 | |
| 2832 | |
| 2833 void Assembler::xaddl(Address dst, Register src) { | |
| 2834 InstructionMark im(this); | |
| 2835 prefix(dst, src); | |
| 0 | 2836 emit_byte(0x0F); |
| 304 | 2837 emit_byte(0xC1); |
| 2838 emit_operand(src, dst); | |
| 2839 } | |
| 2840 | |
| 2841 void Assembler::xchgl(Register dst, Address src) { // xchg | |
| 2842 InstructionMark im(this); | |
| 2843 prefix(src, dst); | |
| 2844 emit_byte(0x87); | |
| 2845 emit_operand(dst, src); | |
| 2846 } | |
| 2847 | |
| 2848 void Assembler::xchgl(Register dst, Register src) { | |
| 2849 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2850 emit_byte(0x87); | |
| 2851 emit_byte(0xc0 | encode); | |
| 2852 } | |
| 2853 | |
| 2854 void Assembler::xorl(Register dst, int32_t imm32) { | |
| 2855 prefix(dst); | |
| 2856 emit_arith(0x81, 0xF0, dst, imm32); | |
| 2857 } | |
| 2858 | |
| 2859 void Assembler::xorl(Register dst, Address src) { | |
| 2860 InstructionMark im(this); | |
| 2861 prefix(src, dst); | |
| 2862 emit_byte(0x33); | |
| 2863 emit_operand(dst, src); | |
| 2864 } | |
| 2865 | |
| 2866 void Assembler::xorl(Register dst, Register src) { | |
| 2867 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2868 emit_arith(0x33, 0xC0, dst, src); | |
| 2869 } | |
| 2870 | |
| 2871 void Assembler::xorpd(XMMRegister dst, XMMRegister src) { | |
| 2872 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2873 emit_byte(0x66); | |
| 2874 xorps(dst, src); | |
| 2875 } | |
| 2876 | |
| 2877 void Assembler::xorpd(XMMRegister dst, Address src) { | |
| 2878 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2879 InstructionMark im(this); | |
| 2880 emit_byte(0x66); | |
| 2881 prefix(src, dst); | |
| 2882 emit_byte(0x0F); | |
| 2883 emit_byte(0x57); | |
| 2884 emit_operand(dst, src); | |
| 2885 } | |
| 2886 | |
| 2887 | |
| 2888 void Assembler::xorps(XMMRegister dst, XMMRegister src) { | |
| 2889 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 2890 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2891 emit_byte(0x0F); | |
| 2892 emit_byte(0x57); | |
| 2893 emit_byte(0xC0 | encode); | |
| 2894 } | |
| 2895 | |
| 2896 void Assembler::xorps(XMMRegister dst, Address src) { | |
| 2897 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 2898 InstructionMark im(this); | |
| 2899 prefix(src, dst); | |
| 2900 emit_byte(0x0F); | |
| 2901 emit_byte(0x57); | |
| 2902 emit_operand(dst, src); | |
| 2903 } | |
| 2904 | |
| 2905 #ifndef _LP64 | |
| 2906 // 32bit only pieces of the assembler | |
| 2907 | |
| 2908 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) { | |
| 2909 // NO PREFIX AS NEVER 64BIT | |
| 2910 InstructionMark im(this); | |
| 2911 emit_byte(0x81); | |
| 2912 emit_byte(0xF8 | src1->encoding()); | |
| 2913 emit_data(imm32, rspec, 0); | |
| 2914 } | |
| 2915 | |
| 2916 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) { | |
| 2917 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs | |
| 2918 InstructionMark im(this); | |
| 2919 emit_byte(0x81); | |
| 2920 emit_operand(rdi, src1); | |
| 2921 emit_data(imm32, rspec, 0); | |
| 2922 } | |
| 2923 | |
| 2924 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax, | |
| 2925 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded | |
| 2926 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise. | |
| 2927 void Assembler::cmpxchg8(Address adr) { | |
| 2928 InstructionMark im(this); | |
| 2929 emit_byte(0x0F); | |
| 2930 emit_byte(0xc7); | |
| 2931 emit_operand(rcx, adr); | |
| 2932 } | |
| 2933 | |
| 2934 void Assembler::decl(Register dst) { | |
| 2935 // Don't use it directly. Use MacroAssembler::decrementl() instead. | |
| 2936 emit_byte(0x48 | dst->encoding()); | |
| 2937 } | |
| 2938 | |
| 2939 #endif // _LP64 | |
| 2940 | |
| 2941 // 64bit typically doesn't use the x87 but needs to for the trig funcs | |
| 2942 | |
| 2943 void Assembler::fabs() { | |
| 2944 emit_byte(0xD9); | |
| 2945 emit_byte(0xE1); | |
| 2946 } | |
| 2947 | |
| 2948 void Assembler::fadd(int i) { | |
| 2949 emit_farith(0xD8, 0xC0, i); | |
| 2950 } | |
| 2951 | |
| 2952 void Assembler::fadd_d(Address src) { | |
| 2953 InstructionMark im(this); | |
| 2954 emit_byte(0xDC); | |
| 2955 emit_operand32(rax, src); | |
| 2956 } | |
| 2957 | |
| 2958 void Assembler::fadd_s(Address src) { | |
| 2959 InstructionMark im(this); | |
| 2960 emit_byte(0xD8); | |
| 2961 emit_operand32(rax, src); | |
| 2962 } | |
| 2963 | |
| 2964 void Assembler::fadda(int i) { | |
| 2965 emit_farith(0xDC, 0xC0, i); | |
| 2966 } | |
| 2967 | |
| 2968 void Assembler::faddp(int i) { | |
| 2969 emit_farith(0xDE, 0xC0, i); | |
| 2970 } | |
| 2971 | |
| 2972 void Assembler::fchs() { | |
| 2973 emit_byte(0xD9); | |
| 2974 emit_byte(0xE0); | |
| 2975 } | |
| 2976 | |
| 2977 void Assembler::fcom(int i) { | |
| 2978 emit_farith(0xD8, 0xD0, i); | |
| 2979 } | |
| 2980 | |
| 2981 void Assembler::fcomp(int i) { | |
| 2982 emit_farith(0xD8, 0xD8, i); | |
| 2983 } | |
| 2984 | |
| 2985 void Assembler::fcomp_d(Address src) { | |
| 2986 InstructionMark im(this); | |
| 2987 emit_byte(0xDC); | |
| 2988 emit_operand32(rbx, src); | |
| 2989 } | |
| 2990 | |
| 2991 void Assembler::fcomp_s(Address src) { | |
| 2992 InstructionMark im(this); | |
| 2993 emit_byte(0xD8); | |
| 2994 emit_operand32(rbx, src); | |
| 2995 } | |
| 2996 | |
| 2997 void Assembler::fcompp() { | |
| 2998 emit_byte(0xDE); | |
| 2999 emit_byte(0xD9); | |
| 3000 } | |
| 3001 | |
| 3002 void Assembler::fcos() { | |
| 3003 emit_byte(0xD9); | |
| 0 | 3004 emit_byte(0xFF); |
| 304 | 3005 } |
| 3006 | |
| 3007 void Assembler::fdecstp() { | |
| 3008 emit_byte(0xD9); | |
| 3009 emit_byte(0xF6); | |
| 3010 } | |
| 3011 | |
| 3012 void Assembler::fdiv(int i) { | |
| 3013 emit_farith(0xD8, 0xF0, i); | |
| 3014 } | |
| 3015 | |
| 3016 void Assembler::fdiv_d(Address src) { | |
| 3017 InstructionMark im(this); | |
| 3018 emit_byte(0xDC); | |
| 3019 emit_operand32(rsi, src); | |
| 3020 } | |
| 3021 | |
| 3022 void Assembler::fdiv_s(Address src) { | |
| 3023 InstructionMark im(this); | |
| 3024 emit_byte(0xD8); | |
| 3025 emit_operand32(rsi, src); | |
| 3026 } | |
| 3027 | |
| 3028 void Assembler::fdiva(int i) { | |
| 3029 emit_farith(0xDC, 0xF8, i); | |
| 3030 } | |
| 3031 | |
| 3032 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994) | |
| 3033 // is erroneous for some of the floating-point instructions below. | |
| 3034 | |
| 3035 void Assembler::fdivp(int i) { | |
| 3036 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong) | |
| 3037 } | |
| 3038 | |
| 3039 void Assembler::fdivr(int i) { | |
| 3040 emit_farith(0xD8, 0xF8, i); | |
| 3041 } | |
| 3042 | |
| 3043 void Assembler::fdivr_d(Address src) { | |
| 3044 InstructionMark im(this); | |
| 3045 emit_byte(0xDC); | |
| 3046 emit_operand32(rdi, src); | |
| 3047 } | |
| 3048 | |
| 3049 void Assembler::fdivr_s(Address src) { | |
| 3050 InstructionMark im(this); | |
| 3051 emit_byte(0xD8); | |
| 3052 emit_operand32(rdi, src); | |
| 3053 } | |
| 3054 | |
| 3055 void Assembler::fdivra(int i) { | |
| 3056 emit_farith(0xDC, 0xF0, i); | |
| 3057 } | |
| 3058 | |
| 3059 void Assembler::fdivrp(int i) { | |
| 3060 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong) | |
| 3061 } | |
| 3062 | |
| 3063 void Assembler::ffree(int i) { | |
| 3064 emit_farith(0xDD, 0xC0, i); | |
| 3065 } | |
| 3066 | |
| 3067 void Assembler::fild_d(Address adr) { | |
| 3068 InstructionMark im(this); | |
| 3069 emit_byte(0xDF); | |
| 3070 emit_operand32(rbp, adr); | |
| 3071 } | |
| 3072 | |
| 3073 void Assembler::fild_s(Address adr) { | |
| 3074 InstructionMark im(this); | |
| 3075 emit_byte(0xDB); | |
| 3076 emit_operand32(rax, adr); | |
| 3077 } | |
| 3078 | |
| 3079 void Assembler::fincstp() { | |
| 3080 emit_byte(0xD9); | |
| 3081 emit_byte(0xF7); | |
| 3082 } | |
| 3083 | |
| 3084 void Assembler::finit() { | |
| 3085 emit_byte(0x9B); | |
| 3086 emit_byte(0xDB); | |
| 3087 emit_byte(0xE3); | |
| 3088 } | |
| 3089 | |
| 3090 void Assembler::fist_s(Address adr) { | |
| 3091 InstructionMark im(this); | |
| 3092 emit_byte(0xDB); | |
| 3093 emit_operand32(rdx, adr); | |
| 3094 } | |
| 3095 | |
| 3096 void Assembler::fistp_d(Address adr) { | |
| 3097 InstructionMark im(this); | |
| 3098 emit_byte(0xDF); | |
| 3099 emit_operand32(rdi, adr); | |
| 3100 } | |
| 3101 | |
| 3102 void Assembler::fistp_s(Address adr) { | |
| 3103 InstructionMark im(this); | |
| 3104 emit_byte(0xDB); | |
| 3105 emit_operand32(rbx, adr); | |
| 3106 } | |
| 0 | 3107 |
| 3108 void Assembler::fld1() { | |
| 3109 emit_byte(0xD9); | |
| 3110 emit_byte(0xE8); | |
| 3111 } | |
| 3112 | |
| 304 | 3113 void Assembler::fld_d(Address adr) { |
| 3114 InstructionMark im(this); | |
| 3115 emit_byte(0xDD); | |
| 3116 emit_operand32(rax, adr); | |
| 3117 } | |
| 0 | 3118 |
| 3119 void Assembler::fld_s(Address adr) { | |
| 3120 InstructionMark im(this); | |
| 3121 emit_byte(0xD9); | |
| 304 | 3122 emit_operand32(rax, adr); |
| 3123 } | |
| 3124 | |
| 3125 | |
| 3126 void Assembler::fld_s(int index) { | |
| 0 | 3127 emit_farith(0xD9, 0xC0, index); |
| 3128 } | |
| 3129 | |
| 3130 void Assembler::fld_x(Address adr) { | |
| 3131 InstructionMark im(this); | |
| 3132 emit_byte(0xDB); | |
| 304 | 3133 emit_operand32(rbp, adr); |
| 3134 } | |
| 3135 | |
| 3136 void Assembler::fldcw(Address src) { | |
| 3137 InstructionMark im(this); | |
| 3138 emit_byte(0xd9); | |
| 3139 emit_operand32(rbp, src); | |
| 3140 } | |
| 3141 | |
| 3142 void Assembler::fldenv(Address src) { | |
| 0 | 3143 InstructionMark im(this); |
| 3144 emit_byte(0xD9); | |
| 304 | 3145 emit_operand32(rsp, src); |
| 3146 } | |
| 3147 | |
| 3148 void Assembler::fldlg2() { | |
| 0 | 3149 emit_byte(0xD9); |
| 304 | 3150 emit_byte(0xEC); |
| 3151 } | |
| 0 | 3152 |
| 3153 void Assembler::fldln2() { | |
| 3154 emit_byte(0xD9); | |
| 3155 emit_byte(0xED); | |
| 3156 } | |
| 3157 | |
| 304 | 3158 void Assembler::fldz() { |
| 0 | 3159 emit_byte(0xD9); |
| 304 | 3160 emit_byte(0xEE); |
| 3161 } | |
| 0 | 3162 |
| 3163 void Assembler::flog() { | |
| 3164 fldln2(); | |
| 3165 fxch(); | |
| 3166 fyl2x(); | |
| 3167 } | |
| 3168 | |
| 3169 void Assembler::flog10() { | |
| 3170 fldlg2(); | |
| 3171 fxch(); | |
| 3172 fyl2x(); | |
| 3173 } | |
| 3174 | |
| 304 | 3175 void Assembler::fmul(int i) { |
| 3176 emit_farith(0xD8, 0xC8, i); | |
| 3177 } | |
| 3178 | |
| 3179 void Assembler::fmul_d(Address src) { | |
| 3180 InstructionMark im(this); | |
| 3181 emit_byte(0xDC); | |
| 3182 emit_operand32(rcx, src); | |
| 3183 } | |
| 3184 | |
| 3185 void Assembler::fmul_s(Address src) { | |
| 3186 InstructionMark im(this); | |
| 3187 emit_byte(0xD8); | |
| 3188 emit_operand32(rcx, src); | |
| 3189 } | |
| 3190 | |
| 3191 void Assembler::fmula(int i) { | |
| 3192 emit_farith(0xDC, 0xC8, i); | |
| 3193 } | |
| 3194 | |
| 3195 void Assembler::fmulp(int i) { | |
| 3196 emit_farith(0xDE, 0xC8, i); | |
| 3197 } | |
| 3198 | |
| 3199 void Assembler::fnsave(Address dst) { | |
| 3200 InstructionMark im(this); | |
| 3201 emit_byte(0xDD); | |
| 3202 emit_operand32(rsi, dst); | |
| 3203 } | |
| 3204 | |
| 3205 void Assembler::fnstcw(Address src) { | |
| 3206 InstructionMark im(this); | |
| 3207 emit_byte(0x9B); | |
| 3208 emit_byte(0xD9); | |
| 3209 emit_operand32(rdi, src); | |
| 3210 } | |
| 3211 | |
| 3212 void Assembler::fnstsw_ax() { | |
| 3213 emit_byte(0xdF); | |
| 3214 emit_byte(0xE0); | |
| 3215 } | |
| 3216 | |
| 3217 void Assembler::fprem() { | |
| 3218 emit_byte(0xD9); | |
| 3219 emit_byte(0xF8); | |
| 3220 } | |
| 3221 | |
| 3222 void Assembler::fprem1() { | |
| 3223 emit_byte(0xD9); | |
| 3224 emit_byte(0xF5); | |
| 3225 } | |
| 3226 | |
| 3227 void Assembler::frstor(Address src) { | |
| 3228 InstructionMark im(this); | |
| 3229 emit_byte(0xDD); | |
| 3230 emit_operand32(rsp, src); | |
| 3231 } | |
| 0 | 3232 |
| 3233 void Assembler::fsin() { | |
| 3234 emit_byte(0xD9); | |
| 3235 emit_byte(0xFE); | |
| 3236 } | |
| 3237 | |
| 304 | 3238 void Assembler::fsqrt() { |
| 3239 emit_byte(0xD9); | |
| 3240 emit_byte(0xFA); | |
| 3241 } | |
| 3242 | |
| 3243 void Assembler::fst_d(Address adr) { | |
| 3244 InstructionMark im(this); | |
| 3245 emit_byte(0xDD); | |
| 3246 emit_operand32(rdx, adr); | |
| 3247 } | |
| 3248 | |
| 3249 void Assembler::fst_s(Address adr) { | |
| 3250 InstructionMark im(this); | |
| 3251 emit_byte(0xD9); | |
| 3252 emit_operand32(rdx, adr); | |
| 3253 } | |
| 3254 | |
| 3255 void Assembler::fstp_d(Address adr) { | |
| 3256 InstructionMark im(this); | |
| 3257 emit_byte(0xDD); | |
| 3258 emit_operand32(rbx, adr); | |
| 3259 } | |
| 3260 | |
| 3261 void Assembler::fstp_d(int index) { | |
| 3262 emit_farith(0xDD, 0xD8, index); | |
| 3263 } | |
| 3264 | |
| 3265 void Assembler::fstp_s(Address adr) { | |
| 3266 InstructionMark im(this); | |
| 0 | 3267 emit_byte(0xD9); |
| 304 | 3268 emit_operand32(rbx, adr); |
| 3269 } | |
| 3270 | |
| 3271 void Assembler::fstp_x(Address adr) { | |
| 3272 InstructionMark im(this); | |
| 3273 emit_byte(0xDB); | |
| 3274 emit_operand32(rdi, adr); | |
| 3275 } | |
| 3276 | |
| 3277 void Assembler::fsub(int i) { | |
| 3278 emit_farith(0xD8, 0xE0, i); | |
| 3279 } | |
| 3280 | |
| 3281 void Assembler::fsub_d(Address src) { | |
| 3282 InstructionMark im(this); | |
| 3283 emit_byte(0xDC); | |
| 3284 emit_operand32(rsp, src); | |
| 3285 } | |
| 3286 | |
| 3287 void Assembler::fsub_s(Address src) { | |
| 3288 InstructionMark im(this); | |
| 3289 emit_byte(0xD8); | |
| 3290 emit_operand32(rsp, src); | |
| 3291 } | |
| 3292 | |
| 3293 void Assembler::fsuba(int i) { | |
| 3294 emit_farith(0xDC, 0xE8, i); | |
| 3295 } | |
| 3296 | |
| 3297 void Assembler::fsubp(int i) { | |
| 3298 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong) | |
| 3299 } | |
| 3300 | |
| 3301 void Assembler::fsubr(int i) { | |
| 3302 emit_farith(0xD8, 0xE8, i); | |
| 3303 } | |
| 3304 | |
| 3305 void Assembler::fsubr_d(Address src) { | |
| 3306 InstructionMark im(this); | |
| 3307 emit_byte(0xDC); | |
| 3308 emit_operand32(rbp, src); | |
| 3309 } | |
| 3310 | |
| 3311 void Assembler::fsubr_s(Address src) { | |
| 3312 InstructionMark im(this); | |
| 3313 emit_byte(0xD8); | |
| 3314 emit_operand32(rbp, src); | |
| 3315 } | |
| 3316 | |
| 3317 void Assembler::fsubra(int i) { | |
| 3318 emit_farith(0xDC, 0xE0, i); | |
| 3319 } | |
| 3320 | |
| 3321 void Assembler::fsubrp(int i) { | |
| 3322 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong) | |
| 0 | 3323 } |
| 3324 | |
| 3325 void Assembler::ftan() { | |
| 3326 emit_byte(0xD9); | |
| 3327 emit_byte(0xF2); | |
| 3328 emit_byte(0xDD); | |
| 3329 emit_byte(0xD8); | |
| 3330 } | |
| 3331 | |
| 304 | 3332 void Assembler::ftst() { |
| 0 | 3333 emit_byte(0xD9); |
| 304 | 3334 emit_byte(0xE4); |
| 3335 } | |
| 0 | 3336 |
| 3337 void Assembler::fucomi(int i) { | |
| 3338 // make sure the instruction is supported (introduced for P6, together with cmov) | |
| 3339 guarantee(VM_Version::supports_cmov(), "illegal instruction"); | |
| 3340 emit_farith(0xDB, 0xE8, i); | |
| 3341 } | |
| 3342 | |
| 3343 void Assembler::fucomip(int i) { | |
| 3344 // make sure the instruction is supported (introduced for P6, together with cmov) | |
| 3345 guarantee(VM_Version::supports_cmov(), "illegal instruction"); | |
| 3346 emit_farith(0xDF, 0xE8, i); | |
| 3347 } | |
| 3348 | |
| 3349 void Assembler::fwait() { | |
| 3350 emit_byte(0x9B); | |
| 3351 } | |
| 3352 | |
| 304 | 3353 void Assembler::fxch(int i) { |
| 3354 emit_farith(0xD9, 0xC8, i); | |
| 3355 } | |
| 3356 | |
| 3357 void Assembler::fyl2x() { | |
| 0 | 3358 emit_byte(0xD9); |
| 304 | 3359 emit_byte(0xF1); |
| 3360 } | |
| 3361 | |
| 3362 | |
| 3363 #ifndef _LP64 | |
| 3364 | |
| 3365 void Assembler::incl(Register dst) { | |
| 3366 // Don't use it directly. Use MacroAssembler::incrementl() instead. | |
| 3367 emit_byte(0x40 | dst->encoding()); | |
| 3368 } | |
| 3369 | |
| 3370 void Assembler::lea(Register dst, Address src) { | |
| 3371 leal(dst, src); | |
| 3372 } | |
| 3373 | |
| 3374 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) { | |
| 3375 InstructionMark im(this); | |
| 3376 emit_byte(0xC7); | |
| 3377 emit_operand(rax, dst); | |
| 3378 emit_data((int)imm32, rspec, 0); | |
| 3379 } | |
| 3380 | |
|
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660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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changeset
|
3381 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) { |
|
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|
3382 InstructionMark im(this); |
|
660978a2a31a
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diff
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|
3383 int encode = prefix_and_encode(dst->encoding()); |
|
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diff
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|
3384 emit_byte(0xB8 | encode); |
|
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diff
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|
3385 emit_data((int)imm32, rspec, 0); |
|
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|
3386 } |
| 304 | 3387 |
| 3388 void Assembler::popa() { // 32bit | |
| 3389 emit_byte(0x61); | |
| 3390 } | |
| 3391 | |
| 3392 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) { | |
| 3393 InstructionMark im(this); | |
| 3394 emit_byte(0x68); | |
| 3395 emit_data(imm32, rspec, 0); | |
| 3396 } | |
| 3397 | |
| 3398 void Assembler::pusha() { // 32bit | |
| 3399 emit_byte(0x60); | |
| 3400 } | |
| 3401 | |
| 3402 void Assembler::set_byte_if_not_zero(Register dst) { | |
| 0 | 3403 emit_byte(0x0F); |
| 304 | 3404 emit_byte(0x95); |
| 3405 emit_byte(0xE0 | dst->encoding()); | |
| 3406 } | |
| 3407 | |
| 3408 void Assembler::shldl(Register dst, Register src) { | |
| 0 | 3409 emit_byte(0x0F); |
| 304 | 3410 emit_byte(0xA5); |
| 3411 emit_byte(0xC0 | src->encoding() << 3 | dst->encoding()); | |
| 3412 } | |
| 3413 | |
| 3414 void Assembler::shrdl(Register dst, Register src) { | |
| 0 | 3415 emit_byte(0x0F); |
| 304 | 3416 emit_byte(0xAD); |
| 3417 emit_byte(0xC0 | src->encoding() << 3 | dst->encoding()); | |
| 3418 } | |
| 3419 | |
| 3420 #else // LP64 | |
| 3421 | |
| 1369 | 3422 void Assembler::set_byte_if_not_zero(Register dst) { |
| 3423 int enc = prefix_and_encode(dst->encoding(), true); | |
| 3424 emit_byte(0x0F); | |
| 3425 emit_byte(0x95); | |
| 3426 emit_byte(0xE0 | enc); | |
| 3427 } | |
| 3428 | |
| 304 | 3429 // 64bit only pieces of the assembler |
| 3430 // This should only be used by 64bit instructions that can use rip-relative | |
| 3431 // it cannot be used by instructions that want an immediate value. | |
| 3432 | |
| 3433 bool Assembler::reachable(AddressLiteral adr) { | |
| 3434 int64_t disp; | |
| 3435 // None will force a 64bit literal to the code stream. Likely a placeholder | |
| 3436 // for something that will be patched later and we need to certain it will | |
| 3437 // always be reachable. | |
| 3438 if (adr.reloc() == relocInfo::none) { | |
| 3439 return false; | |
| 3440 } | |
| 3441 if (adr.reloc() == relocInfo::internal_word_type) { | |
| 3442 // This should be rip relative and easily reachable. | |
| 3443 return true; | |
| 3444 } | |
| 3445 if (adr.reloc() == relocInfo::virtual_call_type || | |
| 3446 adr.reloc() == relocInfo::opt_virtual_call_type || | |
| 3447 adr.reloc() == relocInfo::static_call_type || | |
| 3448 adr.reloc() == relocInfo::static_stub_type ) { | |
| 3449 // This should be rip relative within the code cache and easily | |
| 3450 // reachable until we get huge code caches. (At which point | |
| 3451 // ic code is going to have issues). | |
| 3452 return true; | |
| 3453 } | |
| 3454 if (adr.reloc() != relocInfo::external_word_type && | |
| 3455 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special | |
| 3456 adr.reloc() != relocInfo::poll_type && // relocs to identify them | |
| 3457 adr.reloc() != relocInfo::runtime_call_type ) { | |
| 3458 return false; | |
| 3459 } | |
| 3460 | |
| 3461 // Stress the correction code | |
| 3462 if (ForceUnreachable) { | |
| 3463 // Must be runtimecall reloc, see if it is in the codecache | |
| 3464 // Flipping stuff in the codecache to be unreachable causes issues | |
| 3465 // with things like inline caches where the additional instructions | |
| 3466 // are not handled. | |
| 3467 if (CodeCache::find_blob(adr._target) == NULL) { | |
| 3468 return false; | |
| 3469 } | |
| 3470 } | |
| 3471 // For external_word_type/runtime_call_type if it is reachable from where we | |
| 3472 // are now (possibly a temp buffer) and where we might end up | |
| 3473 // anywhere in the codeCache then we are always reachable. | |
| 3474 // This would have to change if we ever save/restore shared code | |
| 3475 // to be more pessimistic. | |
| 3476 | |
| 3477 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int)); | |
| 3478 if (!is_simm32(disp)) return false; | |
| 3479 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int)); | |
| 3480 if (!is_simm32(disp)) return false; | |
| 3481 | |
| 3482 disp = (int64_t)adr._target - ((int64_t)_code_pos + sizeof(int)); | |
| 3483 | |
| 3484 // Because rip relative is a disp + address_of_next_instruction and we | |
| 3485 // don't know the value of address_of_next_instruction we apply a fudge factor | |
| 3486 // to make sure we will be ok no matter the size of the instruction we get placed into. | |
| 3487 // We don't have to fudge the checks above here because they are already worst case. | |
| 3488 | |
| 3489 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal | |
| 3490 // + 4 because better safe than sorry. | |
| 3491 const int fudge = 12 + 4; | |
| 3492 if (disp < 0) { | |
| 3493 disp -= fudge; | |
| 3494 } else { | |
| 3495 disp += fudge; | |
| 3496 } | |
| 3497 return is_simm32(disp); | |
| 3498 } | |
| 3499 | |
| 3500 void Assembler::emit_data64(jlong data, | |
| 3501 relocInfo::relocType rtype, | |
| 3502 int format) { | |
| 3503 if (rtype == relocInfo::none) { | |
| 3504 emit_long64(data); | |
| 3505 } else { | |
| 3506 emit_data64(data, Relocation::spec_simple(rtype), format); | |
| 3507 } | |
| 3508 } | |
| 3509 | |
| 3510 void Assembler::emit_data64(jlong data, | |
| 3511 RelocationHolder const& rspec, | |
| 3512 int format) { | |
| 3513 assert(imm_operand == 0, "default format must be immediate in this file"); | |
| 3514 assert(imm_operand == format, "must be immediate"); | |
| 3515 assert(inst_mark() != NULL, "must be inside InstructionMark"); | |
| 3516 // Do not use AbstractAssembler::relocate, which is not intended for | |
| 3517 // embedded words. Instead, relocate to the enclosing instruction. | |
| 3518 code_section()->relocate(inst_mark(), rspec, format); | |
| 3519 #ifdef ASSERT | |
| 3520 check_relocation(rspec, format); | |
| 3521 #endif | |
| 3522 emit_long64(data); | |
| 3523 } | |
| 3524 | |
| 3525 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) { | |
| 3526 if (reg_enc >= 8) { | |
| 3527 prefix(REX_B); | |
| 3528 reg_enc -= 8; | |
| 3529 } else if (byteinst && reg_enc >= 4) { | |
| 3530 prefix(REX); | |
| 3531 } | |
| 3532 return reg_enc; | |
| 3533 } | |
| 3534 | |
| 3535 int Assembler::prefixq_and_encode(int reg_enc) { | |
| 3536 if (reg_enc < 8) { | |
| 3537 prefix(REX_W); | |
| 3538 } else { | |
| 3539 prefix(REX_WB); | |
| 3540 reg_enc -= 8; | |
| 3541 } | |
| 3542 return reg_enc; | |
| 3543 } | |
| 3544 | |
| 3545 int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) { | |
| 3546 if (dst_enc < 8) { | |
| 3547 if (src_enc >= 8) { | |
| 3548 prefix(REX_B); | |
| 3549 src_enc -= 8; | |
| 3550 } else if (byteinst && src_enc >= 4) { | |
| 3551 prefix(REX); | |
| 3552 } | |
| 3553 } else { | |
| 3554 if (src_enc < 8) { | |
| 3555 prefix(REX_R); | |
| 3556 } else { | |
| 3557 prefix(REX_RB); | |
| 3558 src_enc -= 8; | |
| 3559 } | |
| 3560 dst_enc -= 8; | |
| 3561 } | |
| 3562 return dst_enc << 3 | src_enc; | |
| 3563 } | |
| 3564 | |
| 3565 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) { | |
| 3566 if (dst_enc < 8) { | |
| 3567 if (src_enc < 8) { | |
| 3568 prefix(REX_W); | |
| 3569 } else { | |
| 3570 prefix(REX_WB); | |
| 3571 src_enc -= 8; | |
| 3572 } | |
| 3573 } else { | |
| 3574 if (src_enc < 8) { | |
| 3575 prefix(REX_WR); | |
| 3576 } else { | |
| 3577 prefix(REX_WRB); | |
| 3578 src_enc -= 8; | |
| 3579 } | |
| 3580 dst_enc -= 8; | |
| 3581 } | |
| 3582 return dst_enc << 3 | src_enc; | |
| 3583 } | |
| 3584 | |
| 3585 void Assembler::prefix(Register reg) { | |
| 3586 if (reg->encoding() >= 8) { | |
| 3587 prefix(REX_B); | |
| 3588 } | |
| 3589 } | |
| 3590 | |
| 3591 void Assembler::prefix(Address adr) { | |
| 3592 if (adr.base_needs_rex()) { | |
| 3593 if (adr.index_needs_rex()) { | |
| 3594 prefix(REX_XB); | |
| 3595 } else { | |
| 3596 prefix(REX_B); | |
| 3597 } | |
| 3598 } else { | |
| 3599 if (adr.index_needs_rex()) { | |
| 3600 prefix(REX_X); | |
| 3601 } | |
| 3602 } | |
| 3603 } | |
| 3604 | |
| 3605 void Assembler::prefixq(Address adr) { | |
| 3606 if (adr.base_needs_rex()) { | |
| 3607 if (adr.index_needs_rex()) { | |
| 3608 prefix(REX_WXB); | |
| 3609 } else { | |
| 3610 prefix(REX_WB); | |
| 3611 } | |
| 3612 } else { | |
| 3613 if (adr.index_needs_rex()) { | |
| 3614 prefix(REX_WX); | |
| 3615 } else { | |
| 3616 prefix(REX_W); | |
| 3617 } | |
| 3618 } | |
| 3619 } | |
| 3620 | |
| 3621 | |
| 3622 void Assembler::prefix(Address adr, Register reg, bool byteinst) { | |
| 3623 if (reg->encoding() < 8) { | |
| 3624 if (adr.base_needs_rex()) { | |
| 3625 if (adr.index_needs_rex()) { | |
| 3626 prefix(REX_XB); | |
| 3627 } else { | |
| 3628 prefix(REX_B); | |
| 3629 } | |
| 3630 } else { | |
| 3631 if (adr.index_needs_rex()) { | |
| 3632 prefix(REX_X); | |
| 3633 } else if (reg->encoding() >= 4 ) { | |
| 3634 prefix(REX); | |
| 3635 } | |
| 3636 } | |
| 3637 } else { | |
| 3638 if (adr.base_needs_rex()) { | |
| 3639 if (adr.index_needs_rex()) { | |
| 3640 prefix(REX_RXB); | |
| 3641 } else { | |
| 3642 prefix(REX_RB); | |
| 3643 } | |
| 3644 } else { | |
| 3645 if (adr.index_needs_rex()) { | |
| 3646 prefix(REX_RX); | |
| 3647 } else { | |
| 3648 prefix(REX_R); | |
| 3649 } | |
| 3650 } | |
| 3651 } | |
| 3652 } | |
| 3653 | |
| 3654 void Assembler::prefixq(Address adr, Register src) { | |
| 3655 if (src->encoding() < 8) { | |
| 3656 if (adr.base_needs_rex()) { | |
| 3657 if (adr.index_needs_rex()) { | |
| 3658 prefix(REX_WXB); | |
| 3659 } else { | |
| 3660 prefix(REX_WB); | |
| 3661 } | |
| 3662 } else { | |
| 3663 if (adr.index_needs_rex()) { | |
| 3664 prefix(REX_WX); | |
| 3665 } else { | |
| 3666 prefix(REX_W); | |
| 3667 } | |
| 3668 } | |
| 3669 } else { | |
| 3670 if (adr.base_needs_rex()) { | |
| 3671 if (adr.index_needs_rex()) { | |
| 3672 prefix(REX_WRXB); | |
| 3673 } else { | |
| 3674 prefix(REX_WRB); | |
| 3675 } | |
| 3676 } else { | |
| 3677 if (adr.index_needs_rex()) { | |
| 3678 prefix(REX_WRX); | |
| 3679 } else { | |
| 3680 prefix(REX_WR); | |
| 3681 } | |
| 3682 } | |
| 3683 } | |
| 3684 } | |
| 3685 | |
| 3686 void Assembler::prefix(Address adr, XMMRegister reg) { | |
| 3687 if (reg->encoding() < 8) { | |
| 3688 if (adr.base_needs_rex()) { | |
| 3689 if (adr.index_needs_rex()) { | |
| 3690 prefix(REX_XB); | |
| 3691 } else { | |
| 3692 prefix(REX_B); | |
| 3693 } | |
| 3694 } else { | |
| 3695 if (adr.index_needs_rex()) { | |
| 3696 prefix(REX_X); | |
| 3697 } | |
| 3698 } | |
| 3699 } else { | |
| 3700 if (adr.base_needs_rex()) { | |
| 3701 if (adr.index_needs_rex()) { | |
| 3702 prefix(REX_RXB); | |
| 3703 } else { | |
| 3704 prefix(REX_RB); | |
| 3705 } | |
| 3706 } else { | |
| 3707 if (adr.index_needs_rex()) { | |
| 3708 prefix(REX_RX); | |
| 3709 } else { | |
| 3710 prefix(REX_R); | |
| 3711 } | |
| 3712 } | |
| 3713 } | |
| 3714 } | |
| 3715 | |
| 3716 void Assembler::adcq(Register dst, int32_t imm32) { | |
| 3717 (void) prefixq_and_encode(dst->encoding()); | |
| 3718 emit_arith(0x81, 0xD0, dst, imm32); | |
| 3719 } | |
| 3720 | |
| 3721 void Assembler::adcq(Register dst, Address src) { | |
| 3722 InstructionMark im(this); | |
| 3723 prefixq(src, dst); | |
| 3724 emit_byte(0x13); | |
| 3725 emit_operand(dst, src); | |
| 3726 } | |
| 3727 | |
| 3728 void Assembler::adcq(Register dst, Register src) { | |
| 3729 (int) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3730 emit_arith(0x13, 0xC0, dst, src); | |
| 3731 } | |
| 3732 | |
| 3733 void Assembler::addq(Address dst, int32_t imm32) { | |
| 3734 InstructionMark im(this); | |
| 3735 prefixq(dst); | |
| 3736 emit_arith_operand(0x81, rax, dst,imm32); | |
| 3737 } | |
| 3738 | |
| 3739 void Assembler::addq(Address dst, Register src) { | |
| 3740 InstructionMark im(this); | |
| 3741 prefixq(dst, src); | |
| 3742 emit_byte(0x01); | |
| 3743 emit_operand(src, dst); | |
| 3744 } | |
| 3745 | |
| 3746 void Assembler::addq(Register dst, int32_t imm32) { | |
| 3747 (void) prefixq_and_encode(dst->encoding()); | |
| 3748 emit_arith(0x81, 0xC0, dst, imm32); | |
| 3749 } | |
| 3750 | |
| 3751 void Assembler::addq(Register dst, Address src) { | |
| 3752 InstructionMark im(this); | |
| 3753 prefixq(src, dst); | |
| 3754 emit_byte(0x03); | |
| 3755 emit_operand(dst, src); | |
| 3756 } | |
| 3757 | |
| 3758 void Assembler::addq(Register dst, Register src) { | |
| 3759 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3760 emit_arith(0x03, 0xC0, dst, src); | |
| 3761 } | |
| 3762 | |
| 3763 void Assembler::andq(Register dst, int32_t imm32) { | |
| 3764 (void) prefixq_and_encode(dst->encoding()); | |
| 3765 emit_arith(0x81, 0xE0, dst, imm32); | |
| 3766 } | |
| 3767 | |
| 3768 void Assembler::andq(Register dst, Address src) { | |
| 3769 InstructionMark im(this); | |
| 3770 prefixq(src, dst); | |
| 3771 emit_byte(0x23); | |
| 3772 emit_operand(dst, src); | |
| 3773 } | |
| 3774 | |
| 3775 void Assembler::andq(Register dst, Register src) { | |
| 3776 (int) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3777 emit_arith(0x23, 0xC0, dst, src); | |
| 3778 } | |
| 3779 | |
|
775
93c14e5562c4
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diff
changeset
|
3780 void Assembler::bsfq(Register dst, Register src) { |
|
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6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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diff
changeset
|
3781 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
|
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diff
changeset
|
3782 emit_byte(0x0F); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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diff
changeset
|
3783 emit_byte(0xBC); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
3784 emit_byte(0xC0 | encode); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
3785 } |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
3786 |
|
93c14e5562c4
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twisti
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710
diff
changeset
|
3787 void Assembler::bsrq(Register dst, Register src) { |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
3788 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT"); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
3789 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
3790 emit_byte(0x0F); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
3791 emit_byte(0xBD); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
3792 emit_byte(0xC0 | encode); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
3793 } |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
3794 |
| 304 | 3795 void Assembler::bswapq(Register reg) { |
| 3796 int encode = prefixq_and_encode(reg->encoding()); | |
| 3797 emit_byte(0x0F); | |
| 3798 emit_byte(0xC8 | encode); | |
| 3799 } | |
| 3800 | |
| 3801 void Assembler::cdqq() { | |
| 3802 prefix(REX_W); | |
| 3803 emit_byte(0x99); | |
| 3804 } | |
| 3805 | |
| 3806 void Assembler::clflush(Address adr) { | |
| 3807 prefix(adr); | |
| 3808 emit_byte(0x0F); | |
| 3809 emit_byte(0xAE); | |
| 3810 emit_operand(rdi, adr); | |
| 3811 } | |
| 3812 | |
| 3813 void Assembler::cmovq(Condition cc, Register dst, Register src) { | |
| 3814 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3815 emit_byte(0x0F); | |
| 3816 emit_byte(0x40 | cc); | |
| 3817 emit_byte(0xC0 | encode); | |
| 3818 } | |
| 3819 | |
| 3820 void Assembler::cmovq(Condition cc, Register dst, Address src) { | |
| 3821 InstructionMark im(this); | |
| 3822 prefixq(src, dst); | |
| 3823 emit_byte(0x0F); | |
| 3824 emit_byte(0x40 | cc); | |
| 3825 emit_operand(dst, src); | |
| 3826 } | |
| 3827 | |
| 3828 void Assembler::cmpq(Address dst, int32_t imm32) { | |
| 3829 InstructionMark im(this); | |
| 3830 prefixq(dst); | |
| 3831 emit_byte(0x81); | |
| 3832 emit_operand(rdi, dst, 4); | |
| 3833 emit_long(imm32); | |
| 3834 } | |
| 3835 | |
| 3836 void Assembler::cmpq(Register dst, int32_t imm32) { | |
| 3837 (void) prefixq_and_encode(dst->encoding()); | |
| 3838 emit_arith(0x81, 0xF8, dst, imm32); | |
| 3839 } | |
| 3840 | |
| 3841 void Assembler::cmpq(Address dst, Register src) { | |
| 3842 InstructionMark im(this); | |
| 3843 prefixq(dst, src); | |
| 3844 emit_byte(0x3B); | |
| 3845 emit_operand(src, dst); | |
| 3846 } | |
| 3847 | |
| 3848 void Assembler::cmpq(Register dst, Register src) { | |
| 3849 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3850 emit_arith(0x3B, 0xC0, dst, src); | |
| 3851 } | |
| 3852 | |
| 3853 void Assembler::cmpq(Register dst, Address src) { | |
| 3854 InstructionMark im(this); | |
| 3855 prefixq(src, dst); | |
| 3856 emit_byte(0x3B); | |
| 3857 emit_operand(dst, src); | |
| 3858 } | |
| 3859 | |
| 3860 void Assembler::cmpxchgq(Register reg, Address adr) { | |
| 3861 InstructionMark im(this); | |
| 3862 prefixq(adr, reg); | |
| 3863 emit_byte(0x0F); | |
| 3864 emit_byte(0xB1); | |
| 3865 emit_operand(reg, adr); | |
| 3866 } | |
| 3867 | |
| 3868 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) { | |
| 3869 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 3870 emit_byte(0xF2); | |
| 3871 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3872 emit_byte(0x0F); | |
| 3873 emit_byte(0x2A); | |
| 3874 emit_byte(0xC0 | encode); | |
| 3875 } | |
| 3876 | |
| 3877 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) { | |
| 3878 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 3879 emit_byte(0xF3); | |
| 3880 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3881 emit_byte(0x0F); | |
| 3882 emit_byte(0x2A); | |
| 3883 emit_byte(0xC0 | encode); | |
| 3884 } | |
| 3885 | |
| 3886 void Assembler::cvttsd2siq(Register dst, XMMRegister src) { | |
| 3887 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 3888 emit_byte(0xF2); | |
| 3889 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3890 emit_byte(0x0F); | |
| 3891 emit_byte(0x2C); | |
| 3892 emit_byte(0xC0 | encode); | |
| 3893 } | |
| 3894 | |
| 3895 void Assembler::cvttss2siq(Register dst, XMMRegister src) { | |
| 3896 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 3897 emit_byte(0xF3); | |
| 3898 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3899 emit_byte(0x0F); | |
| 3900 emit_byte(0x2C); | |
| 3901 emit_byte(0xC0 | encode); | |
| 3902 } | |
| 3903 | |
| 3904 void Assembler::decl(Register dst) { | |
| 3905 // Don't use it directly. Use MacroAssembler::decrementl() instead. | |
| 3906 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode) | |
| 3907 int encode = prefix_and_encode(dst->encoding()); | |
| 3908 emit_byte(0xFF); | |
| 3909 emit_byte(0xC8 | encode); | |
| 3910 } | |
| 3911 | |
| 3912 void Assembler::decq(Register dst) { | |
| 3913 // Don't use it directly. Use MacroAssembler::decrementq() instead. | |
| 3914 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |
| 3915 int encode = prefixq_and_encode(dst->encoding()); | |
| 3916 emit_byte(0xFF); | |
| 3917 emit_byte(0xC8 | encode); | |
| 3918 } | |
| 3919 | |
| 3920 void Assembler::decq(Address dst) { | |
| 3921 // Don't use it directly. Use MacroAssembler::decrementq() instead. | |
| 3922 InstructionMark im(this); | |
| 3923 prefixq(dst); | |
| 3924 emit_byte(0xFF); | |
| 3925 emit_operand(rcx, dst); | |
| 3926 } | |
| 3927 | |
| 3928 void Assembler::fxrstor(Address src) { | |
| 3929 prefixq(src); | |
| 3930 emit_byte(0x0F); | |
| 3931 emit_byte(0xAE); | |
| 3932 emit_operand(as_Register(1), src); | |
| 3933 } | |
| 3934 | |
| 3935 void Assembler::fxsave(Address dst) { | |
| 3936 prefixq(dst); | |
| 3937 emit_byte(0x0F); | |
| 3938 emit_byte(0xAE); | |
| 3939 emit_operand(as_Register(0), dst); | |
| 3940 } | |
| 3941 | |
| 3942 void Assembler::idivq(Register src) { | |
| 3943 int encode = prefixq_and_encode(src->encoding()); | |
| 3944 emit_byte(0xF7); | |
| 3945 emit_byte(0xF8 | encode); | |
| 3946 } | |
| 3947 | |
| 3948 void Assembler::imulq(Register dst, Register src) { | |
| 3949 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3950 emit_byte(0x0F); | |
| 3951 emit_byte(0xAF); | |
| 3952 emit_byte(0xC0 | encode); | |
| 3953 } | |
| 3954 | |
| 3955 void Assembler::imulq(Register dst, Register src, int value) { | |
| 3956 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3957 if (is8bit(value)) { | |
| 3958 emit_byte(0x6B); | |
| 3959 emit_byte(0xC0 | encode); | |
|
1914
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diff
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|
3960 emit_byte(value & 0xFF); |
| 304 | 3961 } else { |
| 3962 emit_byte(0x69); | |
| 3963 emit_byte(0xC0 | encode); | |
| 3964 emit_long(value); | |
| 3965 } | |
| 3966 } | |
| 3967 | |
| 3968 void Assembler::incl(Register dst) { | |
| 3969 // Don't use it directly. Use MacroAssembler::incrementl() instead. | |
| 3970 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |
| 3971 int encode = prefix_and_encode(dst->encoding()); | |
| 3972 emit_byte(0xFF); | |
| 3973 emit_byte(0xC0 | encode); | |
| 3974 } | |
| 3975 | |
| 3976 void Assembler::incq(Register dst) { | |
| 3977 // Don't use it directly. Use MacroAssembler::incrementq() instead. | |
| 3978 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |
| 3979 int encode = prefixq_and_encode(dst->encoding()); | |
| 3980 emit_byte(0xFF); | |
| 3981 emit_byte(0xC0 | encode); | |
| 3982 } | |
| 3983 | |
| 3984 void Assembler::incq(Address dst) { | |
| 3985 // Don't use it directly. Use MacroAssembler::incrementq() instead. | |
| 3986 InstructionMark im(this); | |
| 3987 prefixq(dst); | |
| 3988 emit_byte(0xFF); | |
| 3989 emit_operand(rax, dst); | |
| 3990 } | |
| 3991 | |
| 3992 void Assembler::lea(Register dst, Address src) { | |
| 3993 leaq(dst, src); | |
| 3994 } | |
| 3995 | |
| 3996 void Assembler::leaq(Register dst, Address src) { | |
| 3997 InstructionMark im(this); | |
| 3998 prefixq(src, dst); | |
| 3999 emit_byte(0x8D); | |
| 4000 emit_operand(dst, src); | |
| 4001 } | |
| 4002 | |
| 4003 void Assembler::mov64(Register dst, int64_t imm64) { | |
| 4004 InstructionMark im(this); | |
| 4005 int encode = prefixq_and_encode(dst->encoding()); | |
| 4006 emit_byte(0xB8 | encode); | |
| 4007 emit_long64(imm64); | |
| 4008 } | |
| 4009 | |
| 4010 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) { | |
| 4011 InstructionMark im(this); | |
| 4012 int encode = prefixq_and_encode(dst->encoding()); | |
| 4013 emit_byte(0xB8 | encode); | |
| 4014 emit_data64(imm64, rspec); | |
| 4015 } | |
| 4016 | |
|
642
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|
4017 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) { |
|
660978a2a31a
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4018 InstructionMark im(this); |
|
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|
4019 int encode = prefix_and_encode(dst->encoding()); |
|
660978a2a31a
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4020 emit_byte(0xB8 | encode); |
|
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|
4021 emit_data((int)imm32, rspec, narrow_oop_operand); |
|
660978a2a31a
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4022 } |
|
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|
4023 |
|
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|
4024 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) { |
|
660978a2a31a
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|
4025 InstructionMark im(this); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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diff
changeset
|
4026 prefix(dst); |
|
660978a2a31a
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|
4027 emit_byte(0xC7); |
|
660978a2a31a
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|
4028 emit_operand(rax, dst, 4); |
|
660978a2a31a
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|
4029 emit_data((int)imm32, rspec, narrow_oop_operand); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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|
4030 } |
|
660978a2a31a
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|
4031 |
|
660978a2a31a
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|
4032 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) { |
|
660978a2a31a
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4033 InstructionMark im(this); |
|
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|
4034 int encode = prefix_and_encode(src1->encoding()); |
|
660978a2a31a
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|
4035 emit_byte(0x81); |
|
660978a2a31a
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|
4036 emit_byte(0xF8 | encode); |
|
660978a2a31a
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diff
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|
4037 emit_data((int)imm32, rspec, narrow_oop_operand); |
|
660978a2a31a
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|
4038 } |
|
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|
4039 |
|
660978a2a31a
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|
4040 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) { |
|
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|
4041 InstructionMark im(this); |
|
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624
diff
changeset
|
4042 prefix(src1); |
|
660978a2a31a
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|
4043 emit_byte(0x81); |
|
660978a2a31a
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|
4044 emit_operand(rax, src1, 4); |
|
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|
4045 emit_data((int)imm32, rspec, narrow_oop_operand); |
|
660978a2a31a
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|
4046 } |
|
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|
4047 |
|
775
93c14e5562c4
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diff
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|
4048 void Assembler::lzcntq(Register dst, Register src) { |
|
93c14e5562c4
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diff
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|
4049 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); |
|
93c14e5562c4
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diff
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|
4050 emit_byte(0xF3); |
|
93c14e5562c4
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twisti
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diff
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|
4051 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
|
93c14e5562c4
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twisti
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diff
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|
4052 emit_byte(0x0F); |
|
93c14e5562c4
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twisti
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diff
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|
4053 emit_byte(0xBD); |
|
93c14e5562c4
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twisti
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diff
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|
4054 emit_byte(0xC0 | encode); |
|
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diff
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|
4055 } |
|
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|
4056 |
| 304 | 4057 void Assembler::movdq(XMMRegister dst, Register src) { |
| 4058 // table D-1 says MMX/SSE2 | |
| 4059 NOT_LP64(assert(VM_Version::supports_sse2() || VM_Version::supports_mmx(), "")); | |
| 0 | 4060 emit_byte(0x66); |
| 304 | 4061 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
| 0 | 4062 emit_byte(0x0F); |
| 304 | 4063 emit_byte(0x6E); |
| 4064 emit_byte(0xC0 | encode); | |
| 4065 } | |
| 4066 | |
| 4067 void Assembler::movdq(Register dst, XMMRegister src) { | |
| 4068 // table D-1 says MMX/SSE2 | |
| 4069 NOT_LP64(assert(VM_Version::supports_sse2() || VM_Version::supports_mmx(), "")); | |
| 0 | 4070 emit_byte(0x66); |
| 304 | 4071 // swap src/dst to get correct prefix |
| 4072 int encode = prefixq_and_encode(src->encoding(), dst->encoding()); | |
| 0 | 4073 emit_byte(0x0F); |
| 4074 emit_byte(0x7E); | |
| 304 | 4075 emit_byte(0xC0 | encode); |
| 4076 } | |
| 4077 | |
| 4078 void Assembler::movq(Register dst, Register src) { | |
| 4079 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4080 emit_byte(0x8B); | |
| 4081 emit_byte(0xC0 | encode); | |
| 4082 } | |
| 4083 | |
| 4084 void Assembler::movq(Register dst, Address src) { | |
| 4085 InstructionMark im(this); | |
| 4086 prefixq(src, dst); | |
| 4087 emit_byte(0x8B); | |
| 4088 emit_operand(dst, src); | |
| 4089 } | |
| 4090 | |
| 4091 void Assembler::movq(Address dst, Register src) { | |
| 4092 InstructionMark im(this); | |
| 4093 prefixq(dst, src); | |
| 4094 emit_byte(0x89); | |
| 4095 emit_operand(src, dst); | |
| 4096 } | |
| 4097 | |
| 624 | 4098 void Assembler::movsbq(Register dst, Address src) { |
| 4099 InstructionMark im(this); | |
| 4100 prefixq(src, dst); | |
| 4101 emit_byte(0x0F); | |
| 4102 emit_byte(0xBE); | |
| 4103 emit_operand(dst, src); | |
| 4104 } | |
| 4105 | |
| 4106 void Assembler::movsbq(Register dst, Register src) { | |
| 4107 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4108 emit_byte(0x0F); | |
| 4109 emit_byte(0xBE); | |
| 4110 emit_byte(0xC0 | encode); | |
| 4111 } | |
| 4112 | |
| 304 | 4113 void Assembler::movslq(Register dst, int32_t imm32) { |
| 4114 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx) | |
| 4115 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx) | |
| 4116 // as a result we shouldn't use until tested at runtime... | |
| 4117 ShouldNotReachHere(); | |
| 4118 InstructionMark im(this); | |
| 4119 int encode = prefixq_and_encode(dst->encoding()); | |
| 4120 emit_byte(0xC7 | encode); | |
| 4121 emit_long(imm32); | |
| 4122 } | |
| 4123 | |
| 4124 void Assembler::movslq(Address dst, int32_t imm32) { | |
| 4125 assert(is_simm32(imm32), "lost bits"); | |
| 4126 InstructionMark im(this); | |
| 4127 prefixq(dst); | |
| 4128 emit_byte(0xC7); | |
| 4129 emit_operand(rax, dst, 4); | |
| 4130 emit_long(imm32); | |
| 4131 } | |
| 4132 | |
| 4133 void Assembler::movslq(Register dst, Address src) { | |
| 4134 InstructionMark im(this); | |
| 4135 prefixq(src, dst); | |
| 4136 emit_byte(0x63); | |
| 4137 emit_operand(dst, src); | |
| 4138 } | |
| 4139 | |
| 4140 void Assembler::movslq(Register dst, Register src) { | |
| 4141 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4142 emit_byte(0x63); | |
| 4143 emit_byte(0xC0 | encode); | |
| 4144 } | |
| 4145 | |
| 624 | 4146 void Assembler::movswq(Register dst, Address src) { |
| 4147 InstructionMark im(this); | |
| 4148 prefixq(src, dst); | |
| 4149 emit_byte(0x0F); | |
| 4150 emit_byte(0xBF); | |
| 4151 emit_operand(dst, src); | |
| 4152 } | |
| 4153 | |
| 4154 void Assembler::movswq(Register dst, Register src) { | |
| 4155 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4156 emit_byte(0x0F); | |
| 4157 emit_byte(0xBF); | |
| 4158 emit_byte(0xC0 | encode); | |
| 4159 } | |
| 4160 | |
| 4161 void Assembler::movzbq(Register dst, Address src) { | |
| 4162 InstructionMark im(this); | |
| 4163 prefixq(src, dst); | |
| 4164 emit_byte(0x0F); | |
| 4165 emit_byte(0xB6); | |
| 4166 emit_operand(dst, src); | |
| 4167 } | |
| 4168 | |
| 4169 void Assembler::movzbq(Register dst, Register src) { | |
| 4170 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4171 emit_byte(0x0F); | |
| 4172 emit_byte(0xB6); | |
| 4173 emit_byte(0xC0 | encode); | |
| 4174 } | |
| 4175 | |
| 4176 void Assembler::movzwq(Register dst, Address src) { | |
| 4177 InstructionMark im(this); | |
| 4178 prefixq(src, dst); | |
| 4179 emit_byte(0x0F); | |
| 4180 emit_byte(0xB7); | |
| 4181 emit_operand(dst, src); | |
| 4182 } | |
| 4183 | |
| 4184 void Assembler::movzwq(Register dst, Register src) { | |
| 4185 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4186 emit_byte(0x0F); | |
| 4187 emit_byte(0xB7); | |
| 4188 emit_byte(0xC0 | encode); | |
| 4189 } | |
| 4190 | |
| 304 | 4191 void Assembler::negq(Register dst) { |
| 4192 int encode = prefixq_and_encode(dst->encoding()); | |
| 4193 emit_byte(0xF7); | |
| 4194 emit_byte(0xD8 | encode); | |
| 4195 } | |
| 4196 | |
| 4197 void Assembler::notq(Register dst) { | |
| 4198 int encode = prefixq_and_encode(dst->encoding()); | |
| 4199 emit_byte(0xF7); | |
| 4200 emit_byte(0xD0 | encode); | |
| 4201 } | |
| 4202 | |
| 4203 void Assembler::orq(Address dst, int32_t imm32) { | |
| 4204 InstructionMark im(this); | |
| 4205 prefixq(dst); | |
| 4206 emit_byte(0x81); | |
| 4207 emit_operand(rcx, dst, 4); | |
| 4208 emit_long(imm32); | |
| 4209 } | |
| 4210 | |
| 4211 void Assembler::orq(Register dst, int32_t imm32) { | |
| 4212 (void) prefixq_and_encode(dst->encoding()); | |
| 4213 emit_arith(0x81, 0xC8, dst, imm32); | |
| 4214 } | |
| 4215 | |
| 4216 void Assembler::orq(Register dst, Address src) { | |
| 4217 InstructionMark im(this); | |
| 4218 prefixq(src, dst); | |
| 4219 emit_byte(0x0B); | |
| 4220 emit_operand(dst, src); | |
| 4221 } | |
| 4222 | |
| 4223 void Assembler::orq(Register dst, Register src) { | |
| 4224 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4225 emit_arith(0x0B, 0xC0, dst, src); | |
| 4226 } | |
| 4227 | |
| 4228 void Assembler::popa() { // 64bit | |
| 4229 movq(r15, Address(rsp, 0)); | |
| 4230 movq(r14, Address(rsp, wordSize)); | |
| 4231 movq(r13, Address(rsp, 2 * wordSize)); | |
| 4232 movq(r12, Address(rsp, 3 * wordSize)); | |
| 4233 movq(r11, Address(rsp, 4 * wordSize)); | |
| 4234 movq(r10, Address(rsp, 5 * wordSize)); | |
| 4235 movq(r9, Address(rsp, 6 * wordSize)); | |
| 4236 movq(r8, Address(rsp, 7 * wordSize)); | |
| 4237 movq(rdi, Address(rsp, 8 * wordSize)); | |
| 4238 movq(rsi, Address(rsp, 9 * wordSize)); | |
| 4239 movq(rbp, Address(rsp, 10 * wordSize)); | |
| 4240 // skip rsp | |
| 4241 movq(rbx, Address(rsp, 12 * wordSize)); | |
| 4242 movq(rdx, Address(rsp, 13 * wordSize)); | |
| 4243 movq(rcx, Address(rsp, 14 * wordSize)); | |
| 4244 movq(rax, Address(rsp, 15 * wordSize)); | |
| 4245 | |
| 4246 addq(rsp, 16 * wordSize); | |
| 4247 } | |
| 4248 | |
|
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4249 void Assembler::popcntq(Register dst, Address src) { |
|
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4250 assert(VM_Version::supports_popcnt(), "must support"); |
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4251 InstructionMark im(this); |
|
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4252 emit_byte(0xF3); |
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4253 prefixq(src, dst); |
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4254 emit_byte(0x0F); |
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4255 emit_byte(0xB8); |
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4256 emit_operand(dst, src); |
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4257 } |
|
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4258 |
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4259 void Assembler::popcntq(Register dst, Register src) { |
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4260 assert(VM_Version::supports_popcnt(), "must support"); |
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4261 emit_byte(0xF3); |
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4262 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
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4263 emit_byte(0x0F); |
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4264 emit_byte(0xB8); |
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4265 emit_byte(0xC0 | encode); |
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4266 } |
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4267 |
| 304 | 4268 void Assembler::popq(Address dst) { |
| 4269 InstructionMark im(this); | |
| 4270 prefixq(dst); | |
| 4271 emit_byte(0x8F); | |
| 4272 emit_operand(rax, dst); | |
| 4273 } | |
| 4274 | |
| 4275 void Assembler::pusha() { // 64bit | |
| 4276 // we have to store original rsp. ABI says that 128 bytes | |
| 4277 // below rsp are local scratch. | |
| 4278 movq(Address(rsp, -5 * wordSize), rsp); | |
| 4279 | |
| 4280 subq(rsp, 16 * wordSize); | |
| 4281 | |
| 4282 movq(Address(rsp, 15 * wordSize), rax); | |
| 4283 movq(Address(rsp, 14 * wordSize), rcx); | |
| 4284 movq(Address(rsp, 13 * wordSize), rdx); | |
| 4285 movq(Address(rsp, 12 * wordSize), rbx); | |
| 4286 // skip rsp | |
| 4287 movq(Address(rsp, 10 * wordSize), rbp); | |
| 4288 movq(Address(rsp, 9 * wordSize), rsi); | |
| 4289 movq(Address(rsp, 8 * wordSize), rdi); | |
| 4290 movq(Address(rsp, 7 * wordSize), r8); | |
| 4291 movq(Address(rsp, 6 * wordSize), r9); | |
| 4292 movq(Address(rsp, 5 * wordSize), r10); | |
| 4293 movq(Address(rsp, 4 * wordSize), r11); | |
| 4294 movq(Address(rsp, 3 * wordSize), r12); | |
| 4295 movq(Address(rsp, 2 * wordSize), r13); | |
| 4296 movq(Address(rsp, wordSize), r14); | |
| 4297 movq(Address(rsp, 0), r15); | |
| 4298 } | |
| 4299 | |
| 4300 void Assembler::pushq(Address src) { | |
| 4301 InstructionMark im(this); | |
| 4302 prefixq(src); | |
| 4303 emit_byte(0xFF); | |
| 4304 emit_operand(rsi, src); | |
| 4305 } | |
| 4306 | |
| 4307 void Assembler::rclq(Register dst, int imm8) { | |
| 4308 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
| 4309 int encode = prefixq_and_encode(dst->encoding()); | |
| 4310 if (imm8 == 1) { | |
| 4311 emit_byte(0xD1); | |
| 4312 emit_byte(0xD0 | encode); | |
| 4313 } else { | |
| 4314 emit_byte(0xC1); | |
| 4315 emit_byte(0xD0 | encode); | |
| 4316 emit_byte(imm8); | |
| 4317 } | |
| 4318 } | |
| 4319 void Assembler::sarq(Register dst, int imm8) { | |
| 4320 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
| 4321 int encode = prefixq_and_encode(dst->encoding()); | |
| 4322 if (imm8 == 1) { | |
| 4323 emit_byte(0xD1); | |
| 4324 emit_byte(0xF8 | encode); | |
| 4325 } else { | |
| 4326 emit_byte(0xC1); | |
| 4327 emit_byte(0xF8 | encode); | |
| 4328 emit_byte(imm8); | |
| 4329 } | |
| 4330 } | |
| 4331 | |
| 4332 void Assembler::sarq(Register dst) { | |
| 4333 int encode = prefixq_and_encode(dst->encoding()); | |
| 4334 emit_byte(0xD3); | |
| 4335 emit_byte(0xF8 | encode); | |
| 4336 } | |
|
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4337 |
| 304 | 4338 void Assembler::sbbq(Address dst, int32_t imm32) { |
| 4339 InstructionMark im(this); | |
| 4340 prefixq(dst); | |
| 4341 emit_arith_operand(0x81, rbx, dst, imm32); | |
| 4342 } | |
| 4343 | |
| 4344 void Assembler::sbbq(Register dst, int32_t imm32) { | |
| 4345 (void) prefixq_and_encode(dst->encoding()); | |
| 4346 emit_arith(0x81, 0xD8, dst, imm32); | |
| 4347 } | |
| 4348 | |
| 4349 void Assembler::sbbq(Register dst, Address src) { | |
| 4350 InstructionMark im(this); | |
| 4351 prefixq(src, dst); | |
| 4352 emit_byte(0x1B); | |
| 4353 emit_operand(dst, src); | |
| 4354 } | |
| 4355 | |
| 4356 void Assembler::sbbq(Register dst, Register src) { | |
| 4357 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4358 emit_arith(0x1B, 0xC0, dst, src); | |
| 4359 } | |
| 4360 | |
| 4361 void Assembler::shlq(Register dst, int imm8) { | |
| 4362 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
| 4363 int encode = prefixq_and_encode(dst->encoding()); | |
| 4364 if (imm8 == 1) { | |
| 4365 emit_byte(0xD1); | |
| 4366 emit_byte(0xE0 | encode); | |
| 4367 } else { | |
| 4368 emit_byte(0xC1); | |
| 4369 emit_byte(0xE0 | encode); | |
| 4370 emit_byte(imm8); | |
| 4371 } | |
| 4372 } | |
| 4373 | |
| 4374 void Assembler::shlq(Register dst) { | |
| 4375 int encode = prefixq_and_encode(dst->encoding()); | |
| 4376 emit_byte(0xD3); | |
| 4377 emit_byte(0xE0 | encode); | |
| 4378 } | |
| 4379 | |
| 4380 void Assembler::shrq(Register dst, int imm8) { | |
| 4381 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
| 4382 int encode = prefixq_and_encode(dst->encoding()); | |
| 4383 emit_byte(0xC1); | |
| 4384 emit_byte(0xE8 | encode); | |
| 4385 emit_byte(imm8); | |
| 4386 } | |
| 4387 | |
| 4388 void Assembler::shrq(Register dst) { | |
| 4389 int encode = prefixq_and_encode(dst->encoding()); | |
| 4390 emit_byte(0xD3); | |
| 4391 emit_byte(0xE8 | encode); | |
| 4392 } | |
| 4393 | |
| 4394 void Assembler::subq(Address dst, int32_t imm32) { | |
| 4395 InstructionMark im(this); | |
| 4396 prefixq(dst); | |
|
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4397 emit_arith_operand(0x81, rbp, dst, imm32); |
| 304 | 4398 } |
| 4399 | |
| 4400 void Assembler::subq(Address dst, Register src) { | |
| 4401 InstructionMark im(this); | |
| 4402 prefixq(dst, src); | |
| 4403 emit_byte(0x29); | |
| 4404 emit_operand(src, dst); | |
| 4405 } | |
| 4406 | |
|
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4407 void Assembler::subq(Register dst, int32_t imm32) { |
|
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4408 (void) prefixq_and_encode(dst->encoding()); |
|
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4409 emit_arith(0x81, 0xE8, dst, imm32); |
|
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4410 } |
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|
4411 |
| 304 | 4412 void Assembler::subq(Register dst, Address src) { |
| 4413 InstructionMark im(this); | |
| 4414 prefixq(src, dst); | |
| 4415 emit_byte(0x2B); | |
| 4416 emit_operand(dst, src); | |
| 4417 } | |
| 4418 | |
| 4419 void Assembler::subq(Register dst, Register src) { | |
| 4420 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4421 emit_arith(0x2B, 0xC0, dst, src); | |
| 4422 } | |
| 4423 | |
| 4424 void Assembler::testq(Register dst, int32_t imm32) { | |
| 4425 // not using emit_arith because test | |
| 4426 // doesn't support sign-extension of | |
| 4427 // 8bit operands | |
| 4428 int encode = dst->encoding(); | |
| 4429 if (encode == 0) { | |
| 4430 prefix(REX_W); | |
| 4431 emit_byte(0xA9); | |
| 4432 } else { | |
| 4433 encode = prefixq_and_encode(encode); | |
| 4434 emit_byte(0xF7); | |
| 4435 emit_byte(0xC0 | encode); | |
| 4436 } | |
| 4437 emit_long(imm32); | |
| 4438 } | |
| 4439 | |
| 4440 void Assembler::testq(Register dst, Register src) { | |
| 4441 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4442 emit_arith(0x85, 0xC0, dst, src); | |
| 4443 } | |
| 4444 | |
| 4445 void Assembler::xaddq(Address dst, Register src) { | |
| 4446 InstructionMark im(this); | |
| 4447 prefixq(dst, src); | |
| 71 | 4448 emit_byte(0x0F); |
| 304 | 4449 emit_byte(0xC1); |
| 4450 emit_operand(src, dst); | |
| 4451 } | |
| 4452 | |
| 4453 void Assembler::xchgq(Register dst, Address src) { | |
| 4454 InstructionMark im(this); | |
| 4455 prefixq(src, dst); | |
| 4456 emit_byte(0x87); | |
| 4457 emit_operand(dst, src); | |
| 4458 } | |
| 4459 | |
| 4460 void Assembler::xchgq(Register dst, Register src) { | |
| 4461 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4462 emit_byte(0x87); | |
| 4463 emit_byte(0xc0 | encode); | |
| 4464 } | |
| 4465 | |
| 4466 void Assembler::xorq(Register dst, Register src) { | |
| 4467 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4468 emit_arith(0x33, 0xC0, dst, src); | |
| 4469 } | |
| 4470 | |
| 4471 void Assembler::xorq(Register dst, Address src) { | |
| 4472 InstructionMark im(this); | |
| 4473 prefixq(src, dst); | |
| 4474 emit_byte(0x33); | |
| 4475 emit_operand(dst, src); | |
| 4476 } | |
| 4477 | |
| 4478 #endif // !LP64 | |
| 4479 | |
| 4480 static Assembler::Condition reverse[] = { | |
| 4481 Assembler::noOverflow /* overflow = 0x0 */ , | |
| 4482 Assembler::overflow /* noOverflow = 0x1 */ , | |
| 4483 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ , | |
| 4484 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ , | |
| 4485 Assembler::notZero /* zero = 0x4, equal = 0x4 */ , | |
| 4486 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ , | |
| 4487 Assembler::above /* belowEqual = 0x6 */ , | |
| 4488 Assembler::belowEqual /* above = 0x7 */ , | |
| 4489 Assembler::positive /* negative = 0x8 */ , | |
| 4490 Assembler::negative /* positive = 0x9 */ , | |
| 4491 Assembler::noParity /* parity = 0xa */ , | |
| 4492 Assembler::parity /* noParity = 0xb */ , | |
| 4493 Assembler::greaterEqual /* less = 0xc */ , | |
| 4494 Assembler::less /* greaterEqual = 0xd */ , | |
| 4495 Assembler::greater /* lessEqual = 0xe */ , | |
| 4496 Assembler::lessEqual /* greater = 0xf, */ | |
| 4497 | |
| 4498 }; | |
| 4499 | |
| 0 | 4500 |
| 4501 // Implementation of MacroAssembler | |
| 4502 | |
| 304 | 4503 // First all the versions that have distinct versions depending on 32/64 bit |
| 4504 // Unless the difference is trivial (1 line or so). | |
| 4505 | |
| 4506 #ifndef _LP64 | |
| 4507 | |
| 4508 // 32bit versions | |
| 4509 | |
| 0 | 4510 Address MacroAssembler::as_Address(AddressLiteral adr) { |
| 4511 return Address(adr.target(), adr.rspec()); | |
| 4512 } | |
| 4513 | |
| 4514 Address MacroAssembler::as_Address(ArrayAddress adr) { | |
| 4515 return Address::make_array(adr); | |
| 4516 } | |
| 4517 | |
| 304 | 4518 int MacroAssembler::biased_locking_enter(Register lock_reg, |
| 4519 Register obj_reg, | |
| 4520 Register swap_reg, | |
| 4521 Register tmp_reg, | |
| 4522 bool swap_reg_contains_mark, | |
| 4523 Label& done, | |
| 4524 Label* slow_case, | |
| 4525 BiasedLockingCounters* counters) { | |
| 4526 assert(UseBiasedLocking, "why call this otherwise?"); | |
| 4527 assert(swap_reg == rax, "swap_reg must be rax, for cmpxchg"); | |
| 4528 assert_different_registers(lock_reg, obj_reg, swap_reg); | |
| 4529 | |
| 4530 if (PrintBiasedLockingStatistics && counters == NULL) | |
| 4531 counters = BiasedLocking::counters(); | |
| 4532 | |
| 4533 bool need_tmp_reg = false; | |
| 4534 if (tmp_reg == noreg) { | |
| 4535 need_tmp_reg = true; | |
| 4536 tmp_reg = lock_reg; | |
| 4537 } else { | |
| 4538 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg); | |
| 4539 } | |
| 4540 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); | |
| 4541 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes()); | |
| 4542 Address klass_addr (obj_reg, oopDesc::klass_offset_in_bytes()); | |
| 4543 Address saved_mark_addr(lock_reg, 0); | |
| 4544 | |
| 4545 // Biased locking | |
| 4546 // See whether the lock is currently biased toward our thread and | |
| 4547 // whether the epoch is still valid | |
| 4548 // Note that the runtime guarantees sufficient alignment of JavaThread | |
| 4549 // pointers to allow age to be placed into low bits | |
| 4550 // First check to see whether biasing is even enabled for this object | |
| 4551 Label cas_label; | |
| 4552 int null_check_offset = -1; | |
| 4553 if (!swap_reg_contains_mark) { | |
| 4554 null_check_offset = offset(); | |
| 4555 movl(swap_reg, mark_addr); | |
| 4556 } | |
| 4557 if (need_tmp_reg) { | |
| 4558 push(tmp_reg); | |
| 4559 } | |
| 4560 movl(tmp_reg, swap_reg); | |
| 4561 andl(tmp_reg, markOopDesc::biased_lock_mask_in_place); | |
| 4562 cmpl(tmp_reg, markOopDesc::biased_lock_pattern); | |
| 4563 if (need_tmp_reg) { | |
| 4564 pop(tmp_reg); | |
| 4565 } | |
| 4566 jcc(Assembler::notEqual, cas_label); | |
| 4567 // The bias pattern is present in the object's header. Need to check | |
| 4568 // whether the bias owner and the epoch are both still current. | |
| 4569 // Note that because there is no current thread register on x86 we | |
| 4570 // need to store off the mark word we read out of the object to | |
| 4571 // avoid reloading it and needing to recheck invariants below. This | |
| 4572 // store is unfortunate but it makes the overall code shorter and | |
| 4573 // simpler. | |
| 4574 movl(saved_mark_addr, swap_reg); | |
| 4575 if (need_tmp_reg) { | |
| 4576 push(tmp_reg); | |
| 4577 } | |
| 4578 get_thread(tmp_reg); | |
| 4579 xorl(swap_reg, tmp_reg); | |
| 4580 if (swap_reg_contains_mark) { | |
| 4581 null_check_offset = offset(); | |
| 4582 } | |
| 4583 movl(tmp_reg, klass_addr); | |
| 4584 xorl(swap_reg, Address(tmp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); | |
| 4585 andl(swap_reg, ~((int) markOopDesc::age_mask_in_place)); | |
| 4586 if (need_tmp_reg) { | |
| 4587 pop(tmp_reg); | |
| 4588 } | |
| 4589 if (counters != NULL) { | |
| 4590 cond_inc32(Assembler::zero, | |
| 4591 ExternalAddress((address)counters->biased_lock_entry_count_addr())); | |
| 4592 } | |
| 4593 jcc(Assembler::equal, done); | |
| 4594 | |
| 4595 Label try_revoke_bias; | |
| 4596 Label try_rebias; | |
| 4597 | |
| 4598 // At this point we know that the header has the bias pattern and | |
| 4599 // that we are not the bias owner in the current epoch. We need to | |
| 4600 // figure out more details about the state of the header in order to | |
| 4601 // know what operations can be legally performed on the object's | |
| 4602 // header. | |
| 4603 | |
| 4604 // If the low three bits in the xor result aren't clear, that means | |
| 4605 // the prototype header is no longer biased and we have to revoke | |
| 4606 // the bias on this object. | |
| 4607 testl(swap_reg, markOopDesc::biased_lock_mask_in_place); | |
| 4608 jcc(Assembler::notZero, try_revoke_bias); | |
| 4609 | |
| 4610 // Biasing is still enabled for this data type. See whether the | |
| 4611 // epoch of the current bias is still valid, meaning that the epoch | |
| 4612 // bits of the mark word are equal to the epoch bits of the | |
| 4613 // prototype header. (Note that the prototype header's epoch bits | |
| 4614 // only change at a safepoint.) If not, attempt to rebias the object | |
| 4615 // toward the current thread. Note that we must be absolutely sure | |
| 4616 // that the current epoch is invalid in order to do this because | |
| 4617 // otherwise the manipulations it performs on the mark word are | |
| 4618 // illegal. | |
| 4619 testl(swap_reg, markOopDesc::epoch_mask_in_place); | |
| 4620 jcc(Assembler::notZero, try_rebias); | |
| 4621 | |
| 4622 // The epoch of the current bias is still valid but we know nothing | |
| 4623 // about the owner; it might be set or it might be clear. Try to | |
| 4624 // acquire the bias of the object using an atomic operation. If this | |
| 4625 // fails we will go in to the runtime to revoke the object's bias. | |
| 4626 // Note that we first construct the presumed unbiased header so we | |
| 4627 // don't accidentally blow away another thread's valid bias. | |
| 4628 movl(swap_reg, saved_mark_addr); | |
| 4629 andl(swap_reg, | |
| 4630 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place); | |
| 4631 if (need_tmp_reg) { | |
| 4632 push(tmp_reg); | |
| 4633 } | |
| 4634 get_thread(tmp_reg); | |
| 4635 orl(tmp_reg, swap_reg); | |
| 4636 if (os::is_MP()) { | |
| 4637 lock(); | |
| 4638 } | |
| 4639 cmpxchgptr(tmp_reg, Address(obj_reg, 0)); | |
| 4640 if (need_tmp_reg) { | |
| 4641 pop(tmp_reg); | |
| 4642 } | |
| 4643 // If the biasing toward our thread failed, this means that | |
| 4644 // another thread succeeded in biasing it toward itself and we | |
| 4645 // need to revoke that bias. The revocation will occur in the | |
| 4646 // interpreter runtime in the slow case. | |
| 4647 if (counters != NULL) { | |
| 4648 cond_inc32(Assembler::zero, | |
| 4649 ExternalAddress((address)counters->anonymously_biased_lock_entry_count_addr())); | |
| 4650 } | |
| 4651 if (slow_case != NULL) { | |
| 4652 jcc(Assembler::notZero, *slow_case); | |
| 4653 } | |
| 4654 jmp(done); | |
| 4655 | |
| 4656 bind(try_rebias); | |
| 4657 // At this point we know the epoch has expired, meaning that the | |
| 4658 // current "bias owner", if any, is actually invalid. Under these | |
| 4659 // circumstances _only_, we are allowed to use the current header's | |
| 4660 // value as the comparison value when doing the cas to acquire the | |
| 4661 // bias in the current epoch. In other words, we allow transfer of | |
| 4662 // the bias from one thread to another directly in this situation. | |
| 4663 // | |
| 4664 // FIXME: due to a lack of registers we currently blow away the age | |
| 4665 // bits in this situation. Should attempt to preserve them. | |
| 4666 if (need_tmp_reg) { | |
| 4667 push(tmp_reg); | |
| 4668 } | |
| 4669 get_thread(tmp_reg); | |
| 4670 movl(swap_reg, klass_addr); | |
| 4671 orl(tmp_reg, Address(swap_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); | |
| 4672 movl(swap_reg, saved_mark_addr); | |
| 4673 if (os::is_MP()) { | |
| 4674 lock(); | |
| 4675 } | |
| 4676 cmpxchgptr(tmp_reg, Address(obj_reg, 0)); | |
| 4677 if (need_tmp_reg) { | |
| 4678 pop(tmp_reg); | |
| 4679 } | |
| 4680 // If the biasing toward our thread failed, then another thread | |
| 4681 // succeeded in biasing it toward itself and we need to revoke that | |
| 4682 // bias. The revocation will occur in the runtime in the slow case. | |
| 4683 if (counters != NULL) { | |
| 4684 cond_inc32(Assembler::zero, | |
| 4685 ExternalAddress((address)counters->rebiased_lock_entry_count_addr())); | |
| 4686 } | |
| 4687 if (slow_case != NULL) { | |
| 4688 jcc(Assembler::notZero, *slow_case); | |
| 4689 } | |
| 4690 jmp(done); | |
| 4691 | |
| 4692 bind(try_revoke_bias); | |
| 4693 // The prototype mark in the klass doesn't have the bias bit set any | |
| 4694 // more, indicating that objects of this data type are not supposed | |
| 4695 // to be biased any more. We are going to try to reset the mark of | |
| 4696 // this object to the prototype value and fall through to the | |
| 4697 // CAS-based locking scheme. Note that if our CAS fails, it means | |
| 4698 // that another thread raced us for the privilege of revoking the | |
| 4699 // bias of this particular object, so it's okay to continue in the | |
| 4700 // normal locking code. | |
| 4701 // | |
| 4702 // FIXME: due to a lack of registers we currently blow away the age | |
| 4703 // bits in this situation. Should attempt to preserve them. | |
| 4704 movl(swap_reg, saved_mark_addr); | |
| 4705 if (need_tmp_reg) { | |
| 4706 push(tmp_reg); | |
| 4707 } | |
| 4708 movl(tmp_reg, klass_addr); | |
| 4709 movl(tmp_reg, Address(tmp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); | |
| 4710 if (os::is_MP()) { | |
| 4711 lock(); | |
| 4712 } | |
| 4713 cmpxchgptr(tmp_reg, Address(obj_reg, 0)); | |
| 4714 if (need_tmp_reg) { | |
| 4715 pop(tmp_reg); | |
| 4716 } | |
| 4717 // Fall through to the normal CAS-based lock, because no matter what | |
| 4718 // the result of the above CAS, some thread must have succeeded in | |
| 4719 // removing the bias bit from the object's header. | |
| 4720 if (counters != NULL) { | |
| 4721 cond_inc32(Assembler::zero, | |
| 4722 ExternalAddress((address)counters->revoked_lock_entry_count_addr())); | |
| 4723 } | |
| 4724 | |
| 4725 bind(cas_label); | |
| 4726 | |
| 4727 return null_check_offset; | |
| 4728 } | |
| 4729 void MacroAssembler::call_VM_leaf_base(address entry_point, | |
| 4730 int number_of_arguments) { | |
| 4731 call(RuntimeAddress(entry_point)); | |
| 4732 increment(rsp, number_of_arguments * wordSize); | |
| 4733 } | |
| 4734 | |
| 4735 void MacroAssembler::cmpoop(Address src1, jobject obj) { | |
| 4736 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); | |
| 4737 } | |
| 4738 | |
| 4739 void MacroAssembler::cmpoop(Register src1, jobject obj) { | |
| 4740 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); | |
| 4741 } | |
| 4742 | |
| 4743 void MacroAssembler::extend_sign(Register hi, Register lo) { | |
| 4744 // According to Intel Doc. AP-526, "Integer Divide", p.18. | |
| 4745 if (VM_Version::is_P6() && hi == rdx && lo == rax) { | |
| 4746 cdql(); | |
| 4747 } else { | |
| 4748 movl(hi, lo); | |
| 4749 sarl(hi, 31); | |
| 4750 } | |
| 4751 } | |
| 4752 | |
| 0 | 4753 void MacroAssembler::fat_nop() { |
| 4754 // A 5 byte nop that is safe for patching (see patch_verified_entry) | |
| 4755 emit_byte(0x26); // es: | |
| 4756 emit_byte(0x2e); // cs: | |
| 4757 emit_byte(0x64); // fs: | |
| 4758 emit_byte(0x65); // gs: | |
| 4759 emit_byte(0x90); | |
| 4760 } | |
| 4761 | |
| 304 | 4762 void MacroAssembler::jC2(Register tmp, Label& L) { |
| 4763 // set parity bit if FPU flag C2 is set (via rax) | |
| 4764 save_rax(tmp); | |
| 4765 fwait(); fnstsw_ax(); | |
| 4766 sahf(); | |
| 4767 restore_rax(tmp); | |
| 4768 // branch | |
| 4769 jcc(Assembler::parity, L); | |
| 4770 } | |
| 4771 | |
| 4772 void MacroAssembler::jnC2(Register tmp, Label& L) { | |
| 4773 // set parity bit if FPU flag C2 is set (via rax) | |
| 4774 save_rax(tmp); | |
| 4775 fwait(); fnstsw_ax(); | |
| 4776 sahf(); | |
| 4777 restore_rax(tmp); | |
| 4778 // branch | |
| 4779 jcc(Assembler::noParity, L); | |
| 4780 } | |
| 4781 | |
| 0 | 4782 // 32bit can do a case table jump in one instruction but we no longer allow the base |
| 4783 // to be installed in the Address class | |
| 4784 void MacroAssembler::jump(ArrayAddress entry) { | |
| 4785 jmp(as_Address(entry)); | |
| 4786 } | |
| 4787 | |
| 304 | 4788 // Note: y_lo will be destroyed |
| 4789 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { | |
| 4790 // Long compare for Java (semantics as described in JVM spec.) | |
| 4791 Label high, low, done; | |
| 4792 | |
| 4793 cmpl(x_hi, y_hi); | |
| 4794 jcc(Assembler::less, low); | |
| 4795 jcc(Assembler::greater, high); | |
| 4796 // x_hi is the return register | |
| 4797 xorl(x_hi, x_hi); | |
| 4798 cmpl(x_lo, y_lo); | |
| 4799 jcc(Assembler::below, low); | |
| 4800 jcc(Assembler::equal, done); | |
| 4801 | |
| 4802 bind(high); | |
| 4803 xorl(x_hi, x_hi); | |
| 4804 increment(x_hi); | |
| 4805 jmp(done); | |
| 4806 | |
| 4807 bind(low); | |
| 4808 xorl(x_hi, x_hi); | |
| 4809 decrementl(x_hi); | |
| 4810 | |
| 4811 bind(done); | |
| 4812 } | |
| 4813 | |
| 4814 void MacroAssembler::lea(Register dst, AddressLiteral src) { | |
| 4815 mov_literal32(dst, (int32_t)src.target(), src.rspec()); | |
| 0 | 4816 } |
| 4817 | |
| 4818 void MacroAssembler::lea(Address dst, AddressLiteral adr) { | |
| 4819 // leal(dst, as_Address(adr)); | |
| 304 | 4820 // see note in movl as to why we must use a move |
| 0 | 4821 mov_literal32(dst, (int32_t) adr.target(), adr.rspec()); |
| 4822 } | |
| 4823 | |
| 4824 void MacroAssembler::leave() { | |
| 304 | 4825 mov(rsp, rbp); |
| 4826 pop(rbp); | |
| 4827 } | |
| 0 | 4828 |
| 4829 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) { | |
| 4830 // Multiplication of two Java long values stored on the stack | |
| 4831 // as illustrated below. Result is in rdx:rax. | |
| 4832 // | |
| 4833 // rsp ---> [ ?? ] \ \ | |
| 4834 // .... | y_rsp_offset | | |
| 4835 // [ y_lo ] / (in bytes) | x_rsp_offset | |
| 4836 // [ y_hi ] | (in bytes) | |
| 4837 // .... | | |
| 4838 // [ x_lo ] / | |
| 4839 // [ x_hi ] | |
| 4840 // .... | |
| 4841 // | |
| 4842 // Basic idea: lo(result) = lo(x_lo * y_lo) | |
| 4843 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) | |
| 4844 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset); | |
| 4845 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset); | |
| 4846 Label quick; | |
| 4847 // load x_hi, y_hi and check if quick | |
| 4848 // multiplication is possible | |
| 4849 movl(rbx, x_hi); | |
| 4850 movl(rcx, y_hi); | |
| 4851 movl(rax, rbx); | |
| 4852 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0 | |
| 4853 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply | |
| 4854 // do full multiplication | |
| 4855 // 1st step | |
| 4856 mull(y_lo); // x_hi * y_lo | |
| 4857 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx, | |
| 4858 // 2nd step | |
| 4859 movl(rax, x_lo); | |
| 4860 mull(rcx); // x_lo * y_hi | |
| 4861 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx, | |
| 4862 // 3rd step | |
| 4863 bind(quick); // note: rbx, = 0 if quick multiply! | |
| 4864 movl(rax, x_lo); | |
| 4865 mull(y_lo); // x_lo * y_lo | |
| 4866 addl(rdx, rbx); // correct hi(x_lo * y_lo) | |
| 4867 } | |
| 4868 | |
| 304 | 4869 void MacroAssembler::lneg(Register hi, Register lo) { |
| 4870 negl(lo); | |
| 4871 adcl(hi, 0); | |
| 4872 negl(hi); | |
| 4873 } | |
| 0 | 4874 |
| 4875 void MacroAssembler::lshl(Register hi, Register lo) { | |
| 4876 // Java shift left long support (semantics as described in JVM spec., p.305) | |
| 4877 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n)) | |
| 4878 // shift value is in rcx ! | |
| 4879 assert(hi != rcx, "must not use rcx"); | |
| 4880 assert(lo != rcx, "must not use rcx"); | |
| 4881 const Register s = rcx; // shift count | |
| 4882 const int n = BitsPerWord; | |
| 4883 Label L; | |
| 4884 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) | |
| 4885 cmpl(s, n); // if (s < n) | |
| 4886 jcc(Assembler::less, L); // else (s >= n) | |
| 4887 movl(hi, lo); // x := x << n | |
| 4888 xorl(lo, lo); | |
| 4889 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! | |
| 4890 bind(L); // s (mod n) < n | |
| 4891 shldl(hi, lo); // x := x << s | |
| 4892 shll(lo); | |
| 4893 } | |
| 4894 | |
| 4895 | |
| 4896 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) { | |
| 4897 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310) | |
| 4898 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n)) | |
| 4899 assert(hi != rcx, "must not use rcx"); | |
| 4900 assert(lo != rcx, "must not use rcx"); | |
| 4901 const Register s = rcx; // shift count | |
| 4902 const int n = BitsPerWord; | |
| 4903 Label L; | |
| 4904 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) | |
| 4905 cmpl(s, n); // if (s < n) | |
| 4906 jcc(Assembler::less, L); // else (s >= n) | |
| 4907 movl(lo, hi); // x := x >> n | |
| 4908 if (sign_extension) sarl(hi, 31); | |
| 4909 else xorl(hi, hi); | |
| 4910 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! | |
| 4911 bind(L); // s (mod n) < n | |
| 4912 shrdl(lo, hi); // x := x >> s | |
| 4913 if (sign_extension) sarl(hi); | |
| 4914 else shrl(hi); | |
| 4915 } | |
| 4916 | |
| 304 | 4917 void MacroAssembler::movoop(Register dst, jobject obj) { |
| 4918 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); | |
| 4919 } | |
| 4920 | |
| 4921 void MacroAssembler::movoop(Address dst, jobject obj) { | |
| 4922 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); | |
| 4923 } | |
| 4924 | |
| 4925 void MacroAssembler::movptr(Register dst, AddressLiteral src) { | |
| 4926 if (src.is_lval()) { | |
| 4927 mov_literal32(dst, (intptr_t)src.target(), src.rspec()); | |
| 4928 } else { | |
| 4929 movl(dst, as_Address(src)); | |
| 4930 } | |
| 4931 } | |
| 4932 | |
| 4933 void MacroAssembler::movptr(ArrayAddress dst, Register src) { | |
| 4934 movl(as_Address(dst), src); | |
| 4935 } | |
| 4936 | |
| 4937 void MacroAssembler::movptr(Register dst, ArrayAddress src) { | |
| 4938 movl(dst, as_Address(src)); | |
| 4939 } | |
| 4940 | |
| 4941 // src should NEVER be a real pointer. Use AddressLiteral for true pointers | |
| 4942 void MacroAssembler::movptr(Address dst, intptr_t src) { | |
| 4943 movl(dst, src); | |
| 4944 } | |
| 4945 | |
| 4946 | |
| 4947 void MacroAssembler::pop_callee_saved_registers() { | |
| 4948 pop(rcx); | |
| 4949 pop(rdx); | |
| 4950 pop(rdi); | |
| 4951 pop(rsi); | |
| 4952 } | |
| 4953 | |
| 4954 void MacroAssembler::pop_fTOS() { | |
| 4955 fld_d(Address(rsp, 0)); | |
| 4956 addl(rsp, 2 * wordSize); | |
| 4957 } | |
| 4958 | |
| 4959 void MacroAssembler::push_callee_saved_registers() { | |
| 4960 push(rsi); | |
| 4961 push(rdi); | |
| 4962 push(rdx); | |
| 4963 push(rcx); | |
| 4964 } | |
| 4965 | |
| 4966 void MacroAssembler::push_fTOS() { | |
| 4967 subl(rsp, 2 * wordSize); | |
| 4968 fstp_d(Address(rsp, 0)); | |
| 4969 } | |
| 4970 | |
| 4971 | |
| 4972 void MacroAssembler::pushoop(jobject obj) { | |
| 4973 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate()); | |
| 4974 } | |
| 4975 | |
| 4976 | |
| 4977 void MacroAssembler::pushptr(AddressLiteral src) { | |
| 4978 if (src.is_lval()) { | |
| 4979 push_literal32((int32_t)src.target(), src.rspec()); | |
| 4980 } else { | |
| 4981 pushl(as_Address(src)); | |
| 4982 } | |
| 4983 } | |
| 4984 | |
| 4985 void MacroAssembler::set_word_if_not_zero(Register dst) { | |
| 4986 xorl(dst, dst); | |
| 4987 set_byte_if_not_zero(dst); | |
| 4988 } | |
| 4989 | |
| 4990 static void pass_arg0(MacroAssembler* masm, Register arg) { | |
| 4991 masm->push(arg); | |
| 4992 } | |
| 4993 | |
| 4994 static void pass_arg1(MacroAssembler* masm, Register arg) { | |
| 4995 masm->push(arg); | |
| 4996 } | |
| 4997 | |
| 4998 static void pass_arg2(MacroAssembler* masm, Register arg) { | |
| 4999 masm->push(arg); | |
| 5000 } | |
| 5001 | |
| 5002 static void pass_arg3(MacroAssembler* masm, Register arg) { | |
| 5003 masm->push(arg); | |
| 5004 } | |
| 5005 | |
| 5006 #ifndef PRODUCT | |
| 5007 extern "C" void findpc(intptr_t x); | |
| 5008 #endif | |
| 5009 | |
| 5010 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) { | |
| 5011 // In order to get locks to work, we need to fake a in_VM state | |
| 5012 JavaThread* thread = JavaThread::current(); | |
| 5013 JavaThreadState saved_state = thread->thread_state(); | |
| 5014 thread->set_thread_state(_thread_in_vm); | |
| 5015 if (ShowMessageBoxOnError) { | |
| 5016 JavaThread* thread = JavaThread::current(); | |
| 5017 JavaThreadState saved_state = thread->thread_state(); | |
| 5018 thread->set_thread_state(_thread_in_vm); | |
| 5019 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { | |
| 5020 ttyLocker ttyl; | |
| 5021 BytecodeCounter::print(); | |
| 5022 } | |
| 5023 // To see where a verify_oop failed, get $ebx+40/X for this frame. | |
| 5024 // This is the value of eip which points to where verify_oop will return. | |
| 5025 if (os::message_box(msg, "Execution stopped, print registers?")) { | |
| 5026 ttyLocker ttyl; | |
| 5027 tty->print_cr("eip = 0x%08x", eip); | |
| 5028 #ifndef PRODUCT | |
|
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|
5029 if ((WizardMode || Verbose) && PrintMiscellaneous) { |
|
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|
5030 tty->cr(); |
|
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|
5031 findpc(eip); |
|
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changeset
|
5032 tty->cr(); |
|
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|
5033 } |
| 304 | 5034 #endif |
|
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|
5035 tty->print_cr("rax = 0x%08x", rax); |
|
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|
5036 tty->print_cr("rbx = 0x%08x", rbx); |
| 304 | 5037 tty->print_cr("rcx = 0x%08x", rcx); |
| 5038 tty->print_cr("rdx = 0x%08x", rdx); | |
| 5039 tty->print_cr("rdi = 0x%08x", rdi); | |
| 5040 tty->print_cr("rsi = 0x%08x", rsi); | |
|
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|
5041 tty->print_cr("rbp = 0x%08x", rbp); |
| 304 | 5042 tty->print_cr("rsp = 0x%08x", rsp); |
| 5043 BREAKPOINT; | |
|
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|
5044 assert(false, "start up GDB"); |
| 304 | 5045 } |
| 5046 } else { | |
| 5047 ttyLocker ttyl; | |
| 5048 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg); | |
| 5049 assert(false, "DEBUG MESSAGE"); | |
| 5050 } | |
| 5051 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); | |
| 5052 } | |
| 5053 | |
| 5054 void MacroAssembler::stop(const char* msg) { | |
| 5055 ExternalAddress message((address)msg); | |
| 5056 // push address of message | |
| 5057 pushptr(message.addr()); | |
| 5058 { Label L; call(L, relocInfo::none); bind(L); } // push eip | |
| 5059 pusha(); // push registers | |
| 5060 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32))); | |
| 5061 hlt(); | |
| 5062 } | |
| 5063 | |
| 5064 void MacroAssembler::warn(const char* msg) { | |
| 5065 push_CPU_state(); | |
| 5066 | |
| 5067 ExternalAddress message((address) msg); | |
| 5068 // push address of message | |
| 5069 pushptr(message.addr()); | |
| 5070 | |
| 5071 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning))); | |
| 5072 addl(rsp, wordSize); // discard argument | |
| 5073 pop_CPU_state(); | |
| 5074 } | |
| 5075 | |
| 5076 #else // _LP64 | |
| 5077 | |
| 5078 // 64 bit versions | |
| 5079 | |
| 5080 Address MacroAssembler::as_Address(AddressLiteral adr) { | |
| 5081 // amd64 always does this as a pc-rel | |
| 5082 // we can be absolute or disp based on the instruction type | |
| 5083 // jmp/call are displacements others are absolute | |
| 5084 assert(!adr.is_lval(), "must be rval"); | |
| 5085 assert(reachable(adr), "must be"); | |
| 5086 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc()); | |
| 5087 | |
| 5088 } | |
| 5089 | |
| 5090 Address MacroAssembler::as_Address(ArrayAddress adr) { | |
| 5091 AddressLiteral base = adr.base(); | |
| 5092 lea(rscratch1, base); | |
| 5093 Address index = adr.index(); | |
| 5094 assert(index._disp == 0, "must not have disp"); // maybe it can? | |
| 5095 Address array(rscratch1, index._index, index._scale, index._disp); | |
| 5096 return array; | |
| 5097 } | |
| 5098 | |
| 5099 int MacroAssembler::biased_locking_enter(Register lock_reg, | |
| 5100 Register obj_reg, | |
| 5101 Register swap_reg, | |
| 5102 Register tmp_reg, | |
| 5103 bool swap_reg_contains_mark, | |
| 5104 Label& done, | |
| 5105 Label* slow_case, | |
| 5106 BiasedLockingCounters* counters) { | |
| 5107 assert(UseBiasedLocking, "why call this otherwise?"); | |
| 5108 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq"); | |
| 5109 assert(tmp_reg != noreg, "tmp_reg must be supplied"); | |
| 5110 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg); | |
| 5111 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); | |
| 5112 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes()); | |
| 5113 Address saved_mark_addr(lock_reg, 0); | |
| 5114 | |
| 5115 if (PrintBiasedLockingStatistics && counters == NULL) | |
| 5116 counters = BiasedLocking::counters(); | |
| 5117 | |
| 5118 // Biased locking | |
| 5119 // See whether the lock is currently biased toward our thread and | |
| 5120 // whether the epoch is still valid | |
| 5121 // Note that the runtime guarantees sufficient alignment of JavaThread | |
| 5122 // pointers to allow age to be placed into low bits | |
| 5123 // First check to see whether biasing is even enabled for this object | |
| 5124 Label cas_label; | |
| 5125 int null_check_offset = -1; | |
| 5126 if (!swap_reg_contains_mark) { | |
| 5127 null_check_offset = offset(); | |
| 5128 movq(swap_reg, mark_addr); | |
| 5129 } | |
| 5130 movq(tmp_reg, swap_reg); | |
| 5131 andq(tmp_reg, markOopDesc::biased_lock_mask_in_place); | |
| 5132 cmpq(tmp_reg, markOopDesc::biased_lock_pattern); | |
| 5133 jcc(Assembler::notEqual, cas_label); | |
| 5134 // The bias pattern is present in the object's header. Need to check | |
| 5135 // whether the bias owner and the epoch are both still current. | |
| 5136 load_prototype_header(tmp_reg, obj_reg); | |
| 5137 orq(tmp_reg, r15_thread); | |
| 5138 xorq(tmp_reg, swap_reg); | |
| 5139 andq(tmp_reg, ~((int) markOopDesc::age_mask_in_place)); | |
| 5140 if (counters != NULL) { | |
| 5141 cond_inc32(Assembler::zero, | |
| 5142 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr())); | |
| 5143 } | |
| 0 | 5144 jcc(Assembler::equal, done); |
| 5145 | |
| 304 | 5146 Label try_revoke_bias; |
| 5147 Label try_rebias; | |
| 5148 | |
| 5149 // At this point we know that the header has the bias pattern and | |
| 5150 // that we are not the bias owner in the current epoch. We need to | |
| 5151 // figure out more details about the state of the header in order to | |
| 5152 // know what operations can be legally performed on the object's | |
| 5153 // header. | |
| 5154 | |
| 5155 // If the low three bits in the xor result aren't clear, that means | |
| 5156 // the prototype header is no longer biased and we have to revoke | |
| 5157 // the bias on this object. | |
| 5158 testq(tmp_reg, markOopDesc::biased_lock_mask_in_place); | |
| 5159 jcc(Assembler::notZero, try_revoke_bias); | |
| 5160 | |
| 5161 // Biasing is still enabled for this data type. See whether the | |
| 5162 // epoch of the current bias is still valid, meaning that the epoch | |
| 5163 // bits of the mark word are equal to the epoch bits of the | |
| 5164 // prototype header. (Note that the prototype header's epoch bits | |
| 5165 // only change at a safepoint.) If not, attempt to rebias the object | |
| 5166 // toward the current thread. Note that we must be absolutely sure | |
| 5167 // that the current epoch is invalid in order to do this because | |
| 5168 // otherwise the manipulations it performs on the mark word are | |
| 5169 // illegal. | |
| 5170 testq(tmp_reg, markOopDesc::epoch_mask_in_place); | |
| 5171 jcc(Assembler::notZero, try_rebias); | |
| 5172 | |
| 5173 // The epoch of the current bias is still valid but we know nothing | |
| 5174 // about the owner; it might be set or it might be clear. Try to | |
| 5175 // acquire the bias of the object using an atomic operation. If this | |
| 5176 // fails we will go in to the runtime to revoke the object's bias. | |
| 5177 // Note that we first construct the presumed unbiased header so we | |
| 5178 // don't accidentally blow away another thread's valid bias. | |
| 5179 andq(swap_reg, | |
| 5180 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place); | |
| 5181 movq(tmp_reg, swap_reg); | |
| 5182 orq(tmp_reg, r15_thread); | |
| 5183 if (os::is_MP()) { | |
| 5184 lock(); | |
| 5185 } | |
| 5186 cmpxchgq(tmp_reg, Address(obj_reg, 0)); | |
| 5187 // If the biasing toward our thread failed, this means that | |
| 5188 // another thread succeeded in biasing it toward itself and we | |
| 5189 // need to revoke that bias. The revocation will occur in the | |
| 5190 // interpreter runtime in the slow case. | |
| 5191 if (counters != NULL) { | |
| 5192 cond_inc32(Assembler::zero, | |
| 5193 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr())); | |
| 5194 } | |
| 5195 if (slow_case != NULL) { | |
| 5196 jcc(Assembler::notZero, *slow_case); | |
| 5197 } | |
| 0 | 5198 jmp(done); |
| 5199 | |
| 304 | 5200 bind(try_rebias); |
| 5201 // At this point we know the epoch has expired, meaning that the | |
| 5202 // current "bias owner", if any, is actually invalid. Under these | |
| 5203 // circumstances _only_, we are allowed to use the current header's | |
| 5204 // value as the comparison value when doing the cas to acquire the | |
| 5205 // bias in the current epoch. In other words, we allow transfer of | |
| 5206 // the bias from one thread to another directly in this situation. | |
| 5207 // | |
| 5208 // FIXME: due to a lack of registers we currently blow away the age | |
| 5209 // bits in this situation. Should attempt to preserve them. | |
| 5210 load_prototype_header(tmp_reg, obj_reg); | |
| 5211 orq(tmp_reg, r15_thread); | |
| 5212 if (os::is_MP()) { | |
| 5213 lock(); | |
| 5214 } | |
| 5215 cmpxchgq(tmp_reg, Address(obj_reg, 0)); | |
| 5216 // If the biasing toward our thread failed, then another thread | |
| 5217 // succeeded in biasing it toward itself and we need to revoke that | |
| 5218 // bias. The revocation will occur in the runtime in the slow case. | |
| 5219 if (counters != NULL) { | |
| 5220 cond_inc32(Assembler::zero, | |
| 5221 ExternalAddress((address) counters->rebiased_lock_entry_count_addr())); | |
| 5222 } | |
| 5223 if (slow_case != NULL) { | |
| 5224 jcc(Assembler::notZero, *slow_case); | |
| 0 | 5225 } |
| 5226 jmp(done); | |
| 5227 | |
| 304 | 5228 bind(try_revoke_bias); |
| 5229 // The prototype mark in the klass doesn't have the bias bit set any | |
| 5230 // more, indicating that objects of this data type are not supposed | |
| 5231 // to be biased any more. We are going to try to reset the mark of | |
| 5232 // this object to the prototype value and fall through to the | |
| 5233 // CAS-based locking scheme. Note that if our CAS fails, it means | |
| 5234 // that another thread raced us for the privilege of revoking the | |
| 5235 // bias of this particular object, so it's okay to continue in the | |
| 5236 // normal locking code. | |
| 5237 // | |
| 5238 // FIXME: due to a lack of registers we currently blow away the age | |
| 5239 // bits in this situation. Should attempt to preserve them. | |
| 5240 load_prototype_header(tmp_reg, obj_reg); | |
| 5241 if (os::is_MP()) { | |
| 5242 lock(); | |
| 5243 } | |
| 5244 cmpxchgq(tmp_reg, Address(obj_reg, 0)); | |
| 5245 // Fall through to the normal CAS-based lock, because no matter what | |
| 5246 // the result of the above CAS, some thread must have succeeded in | |
| 5247 // removing the bias bit from the object's header. | |
| 5248 if (counters != NULL) { | |
| 5249 cond_inc32(Assembler::zero, | |
| 5250 ExternalAddress((address) counters->revoked_lock_entry_count_addr())); | |
| 5251 } | |
| 5252 | |
| 5253 bind(cas_label); | |
| 5254 | |
| 5255 return null_check_offset; | |
| 5256 } | |
| 5257 | |
| 5258 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) { | |
| 5259 Label L, E; | |
| 5260 | |
| 5261 #ifdef _WIN64 | |
| 5262 // Windows always allocates space for it's register args | |
| 5263 assert(num_args <= 4, "only register arguments supported"); | |
| 5264 subq(rsp, frame::arg_reg_save_area_bytes); | |
| 5265 #endif | |
| 5266 | |
| 5267 // Align stack if necessary | |
| 5268 testl(rsp, 15); | |
| 5269 jcc(Assembler::zero, L); | |
| 5270 | |
| 5271 subq(rsp, 8); | |
| 5272 { | |
| 5273 call(RuntimeAddress(entry_point)); | |
| 5274 } | |
| 5275 addq(rsp, 8); | |
| 5276 jmp(E); | |
| 5277 | |
| 5278 bind(L); | |
| 5279 { | |
| 5280 call(RuntimeAddress(entry_point)); | |
| 5281 } | |
| 5282 | |
| 5283 bind(E); | |
| 5284 | |
| 5285 #ifdef _WIN64 | |
| 5286 // restore stack pointer | |
| 5287 addq(rsp, frame::arg_reg_save_area_bytes); | |
| 5288 #endif | |
| 5289 | |
| 5290 } | |
| 5291 | |
| 5292 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) { | |
| 5293 assert(!src2.is_lval(), "should use cmpptr"); | |
| 5294 | |
| 5295 if (reachable(src2)) { | |
| 5296 cmpq(src1, as_Address(src2)); | |
| 5297 } else { | |
| 5298 lea(rscratch1, src2); | |
| 5299 Assembler::cmpq(src1, Address(rscratch1, 0)); | |
| 5300 } | |
| 5301 } | |
| 5302 | |
| 5303 int MacroAssembler::corrected_idivq(Register reg) { | |
| 5304 // Full implementation of Java ldiv and lrem; checks for special | |
| 5305 // case as described in JVM spec., p.243 & p.271. The function | |
| 5306 // returns the (pc) offset of the idivl instruction - may be needed | |
| 5307 // for implicit exceptions. | |
| 5308 // | |
| 5309 // normal case special case | |
| 5310 // | |
| 5311 // input : rax: dividend min_long | |
| 5312 // reg: divisor (may not be eax/edx) -1 | |
| 5313 // | |
| 5314 // output: rax: quotient (= rax idiv reg) min_long | |
| 5315 // rdx: remainder (= rax irem reg) 0 | |
| 5316 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register"); | |
| 5317 static const int64_t min_long = 0x8000000000000000; | |
| 5318 Label normal_case, special_case; | |
| 5319 | |
| 5320 // check for special case | |
| 5321 cmp64(rax, ExternalAddress((address) &min_long)); | |
| 5322 jcc(Assembler::notEqual, normal_case); | |
| 5323 xorl(rdx, rdx); // prepare rdx for possible special case (where | |
| 5324 // remainder = 0) | |
| 5325 cmpq(reg, -1); | |
| 5326 jcc(Assembler::equal, special_case); | |
| 5327 | |
| 5328 // handle normal case | |
| 5329 bind(normal_case); | |
| 5330 cdqq(); | |
| 5331 int idivq_offset = offset(); | |
| 5332 idivq(reg); | |
| 5333 | |
| 5334 // normal and special case exit | |
| 5335 bind(special_case); | |
| 5336 | |
| 5337 return idivq_offset; | |
| 5338 } | |
| 5339 | |
| 5340 void MacroAssembler::decrementq(Register reg, int value) { | |
| 5341 if (value == min_jint) { subq(reg, value); return; } | |
| 5342 if (value < 0) { incrementq(reg, -value); return; } | |
| 5343 if (value == 0) { ; return; } | |
| 5344 if (value == 1 && UseIncDec) { decq(reg) ; return; } | |
| 5345 /* else */ { subq(reg, value) ; return; } | |
| 5346 } | |
| 5347 | |
| 5348 void MacroAssembler::decrementq(Address dst, int value) { | |
| 5349 if (value == min_jint) { subq(dst, value); return; } | |
| 5350 if (value < 0) { incrementq(dst, -value); return; } | |
| 5351 if (value == 0) { ; return; } | |
| 5352 if (value == 1 && UseIncDec) { decq(dst) ; return; } | |
| 5353 /* else */ { subq(dst, value) ; return; } | |
| 5354 } | |
| 5355 | |
| 5356 void MacroAssembler::fat_nop() { | |
| 5357 // A 5 byte nop that is safe for patching (see patch_verified_entry) | |
| 5358 // Recommened sequence from 'Software Optimization Guide for the AMD | |
| 5359 // Hammer Processor' | |
| 5360 emit_byte(0x66); | |
| 5361 emit_byte(0x66); | |
| 5362 emit_byte(0x90); | |
| 5363 emit_byte(0x66); | |
| 5364 emit_byte(0x90); | |
| 5365 } | |
| 5366 | |
| 5367 void MacroAssembler::incrementq(Register reg, int value) { | |
| 5368 if (value == min_jint) { addq(reg, value); return; } | |
| 5369 if (value < 0) { decrementq(reg, -value); return; } | |
| 5370 if (value == 0) { ; return; } | |
| 5371 if (value == 1 && UseIncDec) { incq(reg) ; return; } | |
| 5372 /* else */ { addq(reg, value) ; return; } | |
| 5373 } | |
| 5374 | |
| 5375 void MacroAssembler::incrementq(Address dst, int value) { | |
| 5376 if (value == min_jint) { addq(dst, value); return; } | |
| 5377 if (value < 0) { decrementq(dst, -value); return; } | |
| 5378 if (value == 0) { ; return; } | |
| 5379 if (value == 1 && UseIncDec) { incq(dst) ; return; } | |
| 5380 /* else */ { addq(dst, value) ; return; } | |
| 5381 } | |
| 5382 | |
| 5383 // 32bit can do a case table jump in one instruction but we no longer allow the base | |
| 5384 // to be installed in the Address class | |
| 5385 void MacroAssembler::jump(ArrayAddress entry) { | |
| 5386 lea(rscratch1, entry.base()); | |
| 5387 Address dispatch = entry.index(); | |
| 5388 assert(dispatch._base == noreg, "must be"); | |
| 5389 dispatch._base = rscratch1; | |
| 5390 jmp(dispatch); | |
| 5391 } | |
| 5392 | |
| 5393 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { | |
| 5394 ShouldNotReachHere(); // 64bit doesn't use two regs | |
| 5395 cmpq(x_lo, y_lo); | |
| 5396 } | |
| 5397 | |
| 5398 void MacroAssembler::lea(Register dst, AddressLiteral src) { | |
| 5399 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); | |
| 5400 } | |
| 5401 | |
| 5402 void MacroAssembler::lea(Address dst, AddressLiteral adr) { | |
| 5403 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec()); | |
| 5404 movptr(dst, rscratch1); | |
| 5405 } | |
| 5406 | |
| 5407 void MacroAssembler::leave() { | |
| 5408 // %%% is this really better? Why not on 32bit too? | |
| 5409 emit_byte(0xC9); // LEAVE | |
| 5410 } | |
| 5411 | |
| 5412 void MacroAssembler::lneg(Register hi, Register lo) { | |
| 5413 ShouldNotReachHere(); // 64bit doesn't use two regs | |
| 5414 negq(lo); | |
| 5415 } | |
| 5416 | |
| 5417 void MacroAssembler::movoop(Register dst, jobject obj) { | |
| 5418 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate()); | |
| 5419 } | |
| 5420 | |
| 5421 void MacroAssembler::movoop(Address dst, jobject obj) { | |
| 5422 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate()); | |
| 5423 movq(dst, rscratch1); | |
| 5424 } | |
| 5425 | |
| 5426 void MacroAssembler::movptr(Register dst, AddressLiteral src) { | |
| 5427 if (src.is_lval()) { | |
| 5428 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); | |
| 5429 } else { | |
| 5430 if (reachable(src)) { | |
| 5431 movq(dst, as_Address(src)); | |
| 5432 } else { | |
| 5433 lea(rscratch1, src); | |
| 5434 movq(dst, Address(rscratch1,0)); | |
| 0 | 5435 } |
| 304 | 5436 } |
| 5437 } | |
| 5438 | |
| 5439 void MacroAssembler::movptr(ArrayAddress dst, Register src) { | |
| 5440 movq(as_Address(dst), src); | |
| 5441 } | |
| 5442 | |
| 5443 void MacroAssembler::movptr(Register dst, ArrayAddress src) { | |
| 5444 movq(dst, as_Address(src)); | |
| 5445 } | |
| 5446 | |
| 5447 // src should NEVER be a real pointer. Use AddressLiteral for true pointers | |
| 5448 void MacroAssembler::movptr(Address dst, intptr_t src) { | |
| 5449 mov64(rscratch1, src); | |
| 5450 movq(dst, rscratch1); | |
| 5451 } | |
| 5452 | |
| 5453 // These are mostly for initializing NULL | |
| 5454 void MacroAssembler::movptr(Address dst, int32_t src) { | |
| 5455 movslq(dst, src); | |
| 5456 } | |
| 5457 | |
| 5458 void MacroAssembler::movptr(Register dst, int32_t src) { | |
| 5459 mov64(dst, (intptr_t)src); | |
| 5460 } | |
| 5461 | |
| 5462 void MacroAssembler::pushoop(jobject obj) { | |
| 5463 movoop(rscratch1, obj); | |
| 5464 push(rscratch1); | |
| 5465 } | |
| 5466 | |
| 5467 void MacroAssembler::pushptr(AddressLiteral src) { | |
| 5468 lea(rscratch1, src); | |
| 5469 if (src.is_lval()) { | |
| 5470 push(rscratch1); | |
| 5471 } else { | |
| 5472 pushq(Address(rscratch1, 0)); | |
| 5473 } | |
| 5474 } | |
| 5475 | |
| 5476 void MacroAssembler::reset_last_Java_frame(bool clear_fp, | |
| 5477 bool clear_pc) { | |
| 5478 // we must set sp to zero to clear frame | |
|
512
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|
5479 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); |
| 304 | 5480 // must clear fp, so that compiled frames are not confused; it is |
| 5481 // possible that we need it only for debugging | |
| 5482 if (clear_fp) { | |
|
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|
5483 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); |
| 304 | 5484 } |
| 5485 | |
| 5486 if (clear_pc) { | |
|
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|
5487 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); |
| 304 | 5488 } |
| 5489 } | |
| 5490 | |
| 5491 void MacroAssembler::set_last_Java_frame(Register last_java_sp, | |
| 5492 Register last_java_fp, | |
| 5493 address last_java_pc) { | |
| 5494 // determine last_java_sp register | |
| 5495 if (!last_java_sp->is_valid()) { | |
| 5496 last_java_sp = rsp; | |
| 5497 } | |
| 5498 | |
| 5499 // last_java_fp is optional | |
| 5500 if (last_java_fp->is_valid()) { | |
| 5501 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), | |
| 5502 last_java_fp); | |
| 5503 } | |
| 5504 | |
| 5505 // last_java_pc is optional | |
| 5506 if (last_java_pc != NULL) { | |
| 5507 Address java_pc(r15_thread, | |
| 5508 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()); | |
| 5509 lea(rscratch1, InternalAddress(last_java_pc)); | |
| 5510 movptr(java_pc, rscratch1); | |
| 5511 } | |
| 5512 | |
| 5513 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp); | |
| 5514 } | |
| 5515 | |
| 5516 static void pass_arg0(MacroAssembler* masm, Register arg) { | |
| 5517 if (c_rarg0 != arg ) { | |
| 5518 masm->mov(c_rarg0, arg); | |
| 5519 } | |
| 5520 } | |
| 5521 | |
| 5522 static void pass_arg1(MacroAssembler* masm, Register arg) { | |
| 5523 if (c_rarg1 != arg ) { | |
| 5524 masm->mov(c_rarg1, arg); | |
| 5525 } | |
| 5526 } | |
| 5527 | |
| 5528 static void pass_arg2(MacroAssembler* masm, Register arg) { | |
| 5529 if (c_rarg2 != arg ) { | |
| 5530 masm->mov(c_rarg2, arg); | |
| 5531 } | |
| 5532 } | |
| 5533 | |
| 5534 static void pass_arg3(MacroAssembler* masm, Register arg) { | |
| 5535 if (c_rarg3 != arg ) { | |
| 5536 masm->mov(c_rarg3, arg); | |
| 5537 } | |
| 5538 } | |
| 5539 | |
| 5540 void MacroAssembler::stop(const char* msg) { | |
| 5541 address rip = pc(); | |
| 5542 pusha(); // get regs on stack | |
| 5543 lea(c_rarg0, ExternalAddress((address) msg)); | |
| 5544 lea(c_rarg1, InternalAddress(rip)); | |
| 5545 movq(c_rarg2, rsp); // pass pointer to regs array | |
| 5546 andq(rsp, -16); // align stack as required by ABI | |
| 5547 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64))); | |
| 5548 hlt(); | |
| 5549 } | |
| 5550 | |
| 5551 void MacroAssembler::warn(const char* msg) { | |
|
1976
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6780143: hs203t003 hits SIGSEGV/EXCEPTION_ACCESS_VIOLATION with -XX:+UseCompressedOops
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1972
diff
changeset
|
5552 push(rsp); |
| 304 | 5553 andq(rsp, -16); // align stack as required by push_CPU_state and call |
| 5554 | |
| 5555 push_CPU_state(); // keeps alignment at 16 bytes | |
| 5556 lea(c_rarg0, ExternalAddress((address) msg)); | |
| 5557 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0); | |
| 5558 pop_CPU_state(); | |
|
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diff
changeset
|
5559 pop(rsp); |
| 304 | 5560 } |
| 5561 | |
| 5562 #ifndef PRODUCT | |
| 5563 extern "C" void findpc(intptr_t x); | |
| 5564 #endif | |
| 5565 | |
| 5566 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) { | |
| 5567 // In order to get locks to work, we need to fake a in_VM state | |
| 5568 if (ShowMessageBoxOnError ) { | |
| 5569 JavaThread* thread = JavaThread::current(); | |
| 5570 JavaThreadState saved_state = thread->thread_state(); | |
| 5571 thread->set_thread_state(_thread_in_vm); | |
| 5572 #ifndef PRODUCT | |
| 5573 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { | |
| 5574 ttyLocker ttyl; | |
| 5575 BytecodeCounter::print(); | |
| 0 | 5576 } |
| 304 | 5577 #endif |
| 5578 // To see where a verify_oop failed, get $ebx+40/X for this frame. | |
| 5579 // XXX correct this offset for amd64 | |
| 5580 // This is the value of eip which points to where verify_oop will return. | |
| 5581 if (os::message_box(msg, "Execution stopped, print registers?")) { | |
| 5582 ttyLocker ttyl; | |
| 5583 tty->print_cr("rip = 0x%016lx", pc); | |
| 5584 #ifndef PRODUCT | |
| 5585 tty->cr(); | |
| 5586 findpc(pc); | |
| 5587 tty->cr(); | |
| 5588 #endif | |
| 5589 tty->print_cr("rax = 0x%016lx", regs[15]); | |
| 5590 tty->print_cr("rbx = 0x%016lx", regs[12]); | |
| 5591 tty->print_cr("rcx = 0x%016lx", regs[14]); | |
| 5592 tty->print_cr("rdx = 0x%016lx", regs[13]); | |
| 5593 tty->print_cr("rdi = 0x%016lx", regs[8]); | |
| 5594 tty->print_cr("rsi = 0x%016lx", regs[9]); | |
| 5595 tty->print_cr("rbp = 0x%016lx", regs[10]); | |
| 5596 tty->print_cr("rsp = 0x%016lx", regs[11]); | |
| 5597 tty->print_cr("r8 = 0x%016lx", regs[7]); | |
| 5598 tty->print_cr("r9 = 0x%016lx", regs[6]); | |
| 5599 tty->print_cr("r10 = 0x%016lx", regs[5]); | |
| 5600 tty->print_cr("r11 = 0x%016lx", regs[4]); | |
| 5601 tty->print_cr("r12 = 0x%016lx", regs[3]); | |
| 5602 tty->print_cr("r13 = 0x%016lx", regs[2]); | |
| 5603 tty->print_cr("r14 = 0x%016lx", regs[1]); | |
| 5604 tty->print_cr("r15 = 0x%016lx", regs[0]); | |
| 5605 BREAKPOINT; | |
| 0 | 5606 } |
| 304 | 5607 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); |
| 5608 } else { | |
| 5609 ttyLocker ttyl; | |
| 5610 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", | |
| 5611 msg); | |
| 5612 } | |
| 5613 } | |
| 5614 | |
| 5615 #endif // _LP64 | |
| 5616 | |
| 5617 // Now versions that are common to 32/64 bit | |
| 5618 | |
| 5619 void MacroAssembler::addptr(Register dst, int32_t imm32) { | |
| 5620 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32)); | |
| 5621 } | |
| 5622 | |
| 5623 void MacroAssembler::addptr(Register dst, Register src) { | |
| 5624 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); | |
| 5625 } | |
| 5626 | |
| 5627 void MacroAssembler::addptr(Address dst, Register src) { | |
| 5628 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); | |
| 5629 } | |
| 5630 | |
| 5631 void MacroAssembler::align(int modulus) { | |
| 5632 if (offset() % modulus != 0) { | |
| 5633 nop(modulus - (offset() % modulus)); | |
| 5634 } | |
| 5635 } | |
| 5636 | |
| 5637 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) { | |
| 1060 | 5638 if (reachable(src)) { |
| 5639 andpd(dst, as_Address(src)); | |
| 5640 } else { | |
| 5641 lea(rscratch1, src); | |
| 5642 andpd(dst, Address(rscratch1, 0)); | |
| 5643 } | |
| 304 | 5644 } |
| 5645 | |
| 5646 void MacroAssembler::andptr(Register dst, int32_t imm32) { | |
| 5647 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32)); | |
| 5648 } | |
| 5649 | |
| 5650 void MacroAssembler::atomic_incl(AddressLiteral counter_addr) { | |
| 5651 pushf(); | |
| 5652 if (os::is_MP()) | |
| 5653 lock(); | |
| 5654 incrementl(counter_addr); | |
| 5655 popf(); | |
| 5656 } | |
| 5657 | |
| 5658 // Writes to stack successive pages until offset reached to check for | |
| 5659 // stack overflow + shadow pages. This clobbers tmp. | |
| 5660 void MacroAssembler::bang_stack_size(Register size, Register tmp) { | |
| 5661 movptr(tmp, rsp); | |
| 5662 // Bang stack for total size given plus shadow page size. | |
| 5663 // Bang one page at a time because large size can bang beyond yellow and | |
| 5664 // red zones. | |
| 5665 Label loop; | |
| 5666 bind(loop); | |
| 5667 movl(Address(tmp, (-os::vm_page_size())), size ); | |
| 5668 subptr(tmp, os::vm_page_size()); | |
| 5669 subl(size, os::vm_page_size()); | |
| 5670 jcc(Assembler::greater, loop); | |
| 5671 | |
| 5672 // Bang down shadow pages too. | |
| 5673 // The -1 because we already subtracted 1 page. | |
| 5674 for (int i = 0; i< StackShadowPages-1; i++) { | |
| 5675 // this could be any sized move but this is can be a debugging crumb | |
| 5676 // so the bigger the better. | |
| 5677 movptr(Address(tmp, (-i*os::vm_page_size())), size ); | |
| 5678 } | |
| 5679 } | |
| 5680 | |
| 5681 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) { | |
| 5682 assert(UseBiasedLocking, "why call this otherwise?"); | |
| 5683 | |
| 5684 // Check for biased locking unlock case, which is a no-op | |
| 5685 // Note: we do not have to check the thread ID for two reasons. | |
| 5686 // First, the interpreter checks for IllegalMonitorStateException at | |
| 5687 // a higher level. Second, if the bias was revoked while we held the | |
| 5688 // lock, the object could not be rebiased toward another thread, so | |
| 5689 // the bias bit would be clear. | |
| 5690 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes())); | |
| 5691 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place); | |
| 5692 cmpptr(temp_reg, markOopDesc::biased_lock_pattern); | |
| 5693 jcc(Assembler::equal, done); | |
| 5694 } | |
| 5695 | |
| 5696 void MacroAssembler::c2bool(Register x) { | |
| 5697 // implements x == 0 ? 0 : 1 | |
| 5698 // note: must only look at least-significant byte of x | |
| 5699 // since C-style booleans are stored in one byte | |
| 5700 // only! (was bug) | |
| 5701 andl(x, 0xFF); | |
| 5702 setb(Assembler::notZero, x); | |
| 5703 } | |
| 5704 | |
| 5705 // Wouldn't need if AddressLiteral version had new name | |
| 5706 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) { | |
| 5707 Assembler::call(L, rtype); | |
| 5708 } | |
| 5709 | |
| 5710 void MacroAssembler::call(Register entry) { | |
| 5711 Assembler::call(entry); | |
| 5712 } | |
| 5713 | |
| 5714 void MacroAssembler::call(AddressLiteral entry) { | |
| 5715 if (reachable(entry)) { | |
| 5716 Assembler::call_literal(entry.target(), entry.rspec()); | |
| 5717 } else { | |
| 5718 lea(rscratch1, entry); | |
| 5719 Assembler::call(rscratch1); | |
| 5720 } | |
| 5721 } | |
| 5722 | |
| 5723 // Implementation of call_VM versions | |
| 5724 | |
| 5725 void MacroAssembler::call_VM(Register oop_result, | |
| 5726 address entry_point, | |
| 5727 bool check_exceptions) { | |
| 5728 Label C, E; | |
| 5729 call(C, relocInfo::none); | |
| 5730 jmp(E); | |
| 5731 | |
| 5732 bind(C); | |
| 5733 call_VM_helper(oop_result, entry_point, 0, check_exceptions); | |
| 5734 ret(0); | |
| 5735 | |
| 5736 bind(E); | |
| 5737 } | |
| 5738 | |
| 5739 void MacroAssembler::call_VM(Register oop_result, | |
| 5740 address entry_point, | |
| 5741 Register arg_1, | |
| 5742 bool check_exceptions) { | |
| 5743 Label C, E; | |
| 5744 call(C, relocInfo::none); | |
| 5745 jmp(E); | |
| 5746 | |
| 5747 bind(C); | |
| 5748 pass_arg1(this, arg_1); | |
| 5749 call_VM_helper(oop_result, entry_point, 1, check_exceptions); | |
| 5750 ret(0); | |
| 5751 | |
| 5752 bind(E); | |
| 5753 } | |
| 5754 | |
| 5755 void MacroAssembler::call_VM(Register oop_result, | |
| 5756 address entry_point, | |
| 5757 Register arg_1, | |
| 5758 Register arg_2, | |
| 5759 bool check_exceptions) { | |
| 5760 Label C, E; | |
| 5761 call(C, relocInfo::none); | |
| 5762 jmp(E); | |
| 5763 | |
| 5764 bind(C); | |
| 5765 | |
| 5766 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
| 5767 | |
| 5768 pass_arg2(this, arg_2); | |
| 5769 pass_arg1(this, arg_1); | |
| 5770 call_VM_helper(oop_result, entry_point, 2, check_exceptions); | |
| 5771 ret(0); | |
| 5772 | |
| 5773 bind(E); | |
| 5774 } | |
| 5775 | |
| 5776 void MacroAssembler::call_VM(Register oop_result, | |
| 5777 address entry_point, | |
| 5778 Register arg_1, | |
| 5779 Register arg_2, | |
| 5780 Register arg_3, | |
| 5781 bool check_exceptions) { | |
| 5782 Label C, E; | |
| 5783 call(C, relocInfo::none); | |
| 5784 jmp(E); | |
| 5785 | |
| 5786 bind(C); | |
| 5787 | |
| 5788 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); | |
| 5789 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); | |
| 5790 pass_arg3(this, arg_3); | |
| 5791 | |
| 5792 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
| 5793 pass_arg2(this, arg_2); | |
| 5794 | |
| 5795 pass_arg1(this, arg_1); | |
| 5796 call_VM_helper(oop_result, entry_point, 3, check_exceptions); | |
| 5797 ret(0); | |
| 5798 | |
| 5799 bind(E); | |
| 5800 } | |
| 5801 | |
| 5802 void MacroAssembler::call_VM(Register oop_result, | |
| 5803 Register last_java_sp, | |
| 5804 address entry_point, | |
| 5805 int number_of_arguments, | |
| 5806 bool check_exceptions) { | |
| 5807 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); | |
| 5808 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); | |
| 5809 } | |
| 5810 | |
| 5811 void MacroAssembler::call_VM(Register oop_result, | |
| 5812 Register last_java_sp, | |
| 5813 address entry_point, | |
| 5814 Register arg_1, | |
| 5815 bool check_exceptions) { | |
| 5816 pass_arg1(this, arg_1); | |
| 5817 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); | |
| 5818 } | |
| 5819 | |
| 5820 void MacroAssembler::call_VM(Register oop_result, | |
| 5821 Register last_java_sp, | |
| 5822 address entry_point, | |
| 5823 Register arg_1, | |
| 5824 Register arg_2, | |
| 5825 bool check_exceptions) { | |
| 5826 | |
| 5827 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
| 5828 pass_arg2(this, arg_2); | |
| 5829 pass_arg1(this, arg_1); | |
| 5830 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); | |
| 5831 } | |
| 5832 | |
| 5833 void MacroAssembler::call_VM(Register oop_result, | |
| 5834 Register last_java_sp, | |
| 5835 address entry_point, | |
| 5836 Register arg_1, | |
| 5837 Register arg_2, | |
| 5838 Register arg_3, | |
| 5839 bool check_exceptions) { | |
| 5840 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); | |
| 5841 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); | |
| 5842 pass_arg3(this, arg_3); | |
| 5843 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
| 5844 pass_arg2(this, arg_2); | |
| 5845 pass_arg1(this, arg_1); | |
| 5846 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); | |
| 5847 } | |
| 5848 | |
| 5849 void MacroAssembler::call_VM_base(Register oop_result, | |
| 5850 Register java_thread, | |
| 5851 Register last_java_sp, | |
| 5852 address entry_point, | |
| 5853 int number_of_arguments, | |
| 5854 bool check_exceptions) { | |
| 5855 // determine java_thread register | |
| 5856 if (!java_thread->is_valid()) { | |
| 5857 #ifdef _LP64 | |
| 5858 java_thread = r15_thread; | |
| 5859 #else | |
| 5860 java_thread = rdi; | |
| 5861 get_thread(java_thread); | |
| 5862 #endif // LP64 | |
| 5863 } | |
| 5864 // determine last_java_sp register | |
| 5865 if (!last_java_sp->is_valid()) { | |
| 5866 last_java_sp = rsp; | |
| 5867 } | |
| 5868 // debugging support | |
| 5869 assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); | |
| 5870 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register")); | |
|
1976
0fc262af204f
6780143: hs203t003 hits SIGSEGV/EXCEPTION_ACCESS_VIOLATION with -XX:+UseCompressedOops
coleenp
parents:
1972
diff
changeset
|
5871 #ifdef ASSERT |
|
0fc262af204f
6780143: hs203t003 hits SIGSEGV/EXCEPTION_ACCESS_VIOLATION with -XX:+UseCompressedOops
coleenp
parents:
1972
diff
changeset
|
5872 LP64_ONLY(if (UseCompressedOops) verify_heapbase("call_VM_base");) |
|
0fc262af204f
6780143: hs203t003 hits SIGSEGV/EXCEPTION_ACCESS_VIOLATION with -XX:+UseCompressedOops
coleenp
parents:
1972
diff
changeset
|
5873 #endif // ASSERT |
|
0fc262af204f
6780143: hs203t003 hits SIGSEGV/EXCEPTION_ACCESS_VIOLATION with -XX:+UseCompressedOops
coleenp
parents:
1972
diff
changeset
|
5874 |
| 304 | 5875 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result"); |
| 5876 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp"); | |
| 5877 | |
| 5878 // push java thread (becomes first argument of C function) | |
| 5879 | |
| 5880 NOT_LP64(push(java_thread); number_of_arguments++); | |
| 5881 LP64_ONLY(mov(c_rarg0, r15_thread)); | |
| 5882 | |
| 5883 // set last Java frame before call | |
| 5884 assert(last_java_sp != rbp, "can't use ebp/rbp"); | |
| 5885 | |
| 5886 // Only interpreter should have to set fp | |
| 5887 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL); | |
| 5888 | |
| 5889 // do the call, remove parameters | |
| 5890 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments); | |
| 5891 | |
| 5892 // restore the thread (cannot use the pushed argument since arguments | |
| 5893 // may be overwritten by C code generated by an optimizing compiler); | |
| 5894 // however can use the register value directly if it is callee saved. | |
| 5895 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) { | |
| 5896 // rdi & rsi (also r15) are callee saved -> nothing to do | |
| 5897 #ifdef ASSERT | |
| 5898 guarantee(java_thread != rax, "change this code"); | |
| 5899 push(rax); | |
| 5900 { Label L; | |
| 5901 get_thread(rax); | |
| 5902 cmpptr(java_thread, rax); | |
| 5903 jcc(Assembler::equal, L); | |
| 5904 stop("MacroAssembler::call_VM_base: rdi not callee saved?"); | |
| 5905 bind(L); | |
| 0 | 5906 } |
| 304 | 5907 pop(rax); |
| 5908 #endif | |
| 5909 } else { | |
| 5910 get_thread(java_thread); | |
| 5911 } | |
| 5912 // reset last Java frame | |
| 5913 // Only interpreter should have to clear fp | |
| 5914 reset_last_Java_frame(java_thread, true, false); | |
| 5915 | |
| 5916 #ifndef CC_INTERP | |
| 5917 // C++ interp handles this in the interpreter | |
| 5918 check_and_handle_popframe(java_thread); | |
| 5919 check_and_handle_earlyret(java_thread); | |
| 5920 #endif /* CC_INTERP */ | |
| 5921 | |
| 5922 if (check_exceptions) { | |
| 5923 // check for pending exceptions (java_thread is set upon return) | |
| 5924 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD); | |
| 5925 #ifndef _LP64 | |
| 5926 jump_cc(Assembler::notEqual, | |
| 5927 RuntimeAddress(StubRoutines::forward_exception_entry())); | |
| 5928 #else | |
| 5929 // This used to conditionally jump to forward_exception however it is | |
| 5930 // possible if we relocate that the branch will not reach. So we must jump | |
| 5931 // around so we can always reach | |
| 5932 | |
| 5933 Label ok; | |
| 5934 jcc(Assembler::equal, ok); | |
| 5935 jump(RuntimeAddress(StubRoutines::forward_exception_entry())); | |
| 5936 bind(ok); | |
| 5937 #endif // LP64 | |
| 5938 } | |
| 5939 | |
| 5940 // get oop result if there is one and reset the value in the thread | |
| 5941 if (oop_result->is_valid()) { | |
| 5942 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset())); | |
|
512
db4caa99ef11
6787106: Hotspot 32 bit build fails on platforms having different definitions for intptr_t & int32_t
xlu
parents:
420
diff
changeset
|
5943 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD); |
| 304 | 5944 verify_oop(oop_result, "broken oop in call_VM_base"); |
| 5945 } | |
| 5946 } | |
| 5947 | |
| 5948 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) { | |
| 5949 | |
| 5950 // Calculate the value for last_Java_sp | |
| 5951 // somewhat subtle. call_VM does an intermediate call | |
| 5952 // which places a return address on the stack just under the | |
| 5953 // stack pointer as the user finsihed with it. This allows | |
| 5954 // use to retrieve last_Java_pc from last_Java_sp[-1]. | |
| 5955 // On 32bit we then have to push additional args on the stack to accomplish | |
| 5956 // the actual requested call. On 64bit call_VM only can use register args | |
| 5957 // so the only extra space is the return address that call_VM created. | |
| 5958 // This hopefully explains the calculations here. | |
| 5959 | |
| 5960 #ifdef _LP64 | |
| 5961 // We've pushed one address, correct last_Java_sp | |
| 5962 lea(rax, Address(rsp, wordSize)); | |
| 5963 #else | |
| 5964 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize)); | |
| 5965 #endif // LP64 | |
| 5966 | |
| 5967 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions); | |
| 5968 | |
| 5969 } | |
| 5970 | |
| 5971 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) { | |
| 5972 call_VM_leaf_base(entry_point, number_of_arguments); | |
| 5973 } | |
| 5974 | |
| 5975 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) { | |
| 5976 pass_arg0(this, arg_0); | |
| 5977 call_VM_leaf(entry_point, 1); | |
| 5978 } | |
| 5979 | |
| 5980 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { | |
| 5981 | |
| 5982 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); | |
| 5983 pass_arg1(this, arg_1); | |
| 5984 pass_arg0(this, arg_0); | |
| 5985 call_VM_leaf(entry_point, 2); | |
| 5986 } | |
| 5987 | |
| 5988 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { | |
| 5989 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); | |
| 5990 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
| 5991 pass_arg2(this, arg_2); | |
| 5992 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); | |
| 5993 pass_arg1(this, arg_1); | |
| 5994 pass_arg0(this, arg_0); | |
| 5995 call_VM_leaf(entry_point, 3); | |
| 5996 } | |
| 5997 | |
| 5998 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { | |
| 5999 } | |
| 6000 | |
| 6001 void MacroAssembler::check_and_handle_popframe(Register java_thread) { | |
| 6002 } | |
| 6003 | |
| 6004 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) { | |
| 6005 if (reachable(src1)) { | |
| 6006 cmpl(as_Address(src1), imm); | |
| 6007 } else { | |
| 6008 lea(rscratch1, src1); | |
| 6009 cmpl(Address(rscratch1, 0), imm); | |
| 6010 } | |
| 6011 } | |
| 6012 | |
| 6013 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) { | |
| 6014 assert(!src2.is_lval(), "use cmpptr"); | |
| 6015 if (reachable(src2)) { | |
| 6016 cmpl(src1, as_Address(src2)); | |
| 6017 } else { | |
| 6018 lea(rscratch1, src2); | |
| 6019 cmpl(src1, Address(rscratch1, 0)); | |
| 6020 } | |
| 6021 } | |
| 6022 | |
| 6023 void MacroAssembler::cmp32(Register src1, int32_t imm) { | |
| 6024 Assembler::cmpl(src1, imm); | |
| 6025 } | |
| 6026 | |
| 6027 void MacroAssembler::cmp32(Register src1, Address src2) { | |
| 6028 Assembler::cmpl(src1, src2); | |
| 6029 } | |
| 6030 | |
| 6031 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { | |
| 6032 ucomisd(opr1, opr2); | |
| 6033 | |
| 6034 Label L; | |
| 6035 if (unordered_is_less) { | |
| 6036 movl(dst, -1); | |
| 6037 jcc(Assembler::parity, L); | |
| 6038 jcc(Assembler::below , L); | |
| 6039 movl(dst, 0); | |
| 6040 jcc(Assembler::equal , L); | |
| 6041 increment(dst); | |
| 6042 } else { // unordered is greater | |
| 6043 movl(dst, 1); | |
| 6044 jcc(Assembler::parity, L); | |
| 6045 jcc(Assembler::above , L); | |
| 6046 movl(dst, 0); | |
| 6047 jcc(Assembler::equal , L); | |
| 6048 decrementl(dst); | |
| 6049 } | |
| 6050 bind(L); | |
| 6051 } | |
| 6052 | |
| 6053 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { | |
| 6054 ucomiss(opr1, opr2); | |
| 6055 | |
| 6056 Label L; | |
| 6057 if (unordered_is_less) { | |
| 6058 movl(dst, -1); | |
| 6059 jcc(Assembler::parity, L); | |
| 6060 jcc(Assembler::below , L); | |
| 6061 movl(dst, 0); | |
| 6062 jcc(Assembler::equal , L); | |
| 6063 increment(dst); | |
| 6064 } else { // unordered is greater | |
| 6065 movl(dst, 1); | |
| 6066 jcc(Assembler::parity, L); | |
| 6067 jcc(Assembler::above , L); | |
| 6068 movl(dst, 0); | |
| 6069 jcc(Assembler::equal , L); | |
| 6070 decrementl(dst); | |
| 6071 } | |
| 6072 bind(L); | |
| 6073 } | |
| 6074 | |
| 6075 | |
| 6076 void MacroAssembler::cmp8(AddressLiteral src1, int imm) { | |
| 6077 if (reachable(src1)) { | |
| 6078 cmpb(as_Address(src1), imm); | |
| 6079 } else { | |
| 6080 lea(rscratch1, src1); | |
| 6081 cmpb(Address(rscratch1, 0), imm); | |
| 6082 } | |
| 6083 } | |
| 6084 | |
| 6085 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) { | |
| 6086 #ifdef _LP64 | |
| 6087 if (src2.is_lval()) { | |
| 6088 movptr(rscratch1, src2); | |
| 6089 Assembler::cmpq(src1, rscratch1); | |
| 6090 } else if (reachable(src2)) { | |
| 6091 cmpq(src1, as_Address(src2)); | |
| 6092 } else { | |
| 6093 lea(rscratch1, src2); | |
| 6094 Assembler::cmpq(src1, Address(rscratch1, 0)); | |
| 6095 } | |
| 6096 #else | |
| 6097 if (src2.is_lval()) { | |
| 6098 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); | |
| 6099 } else { | |
| 6100 cmpl(src1, as_Address(src2)); | |
| 6101 } | |
| 6102 #endif // _LP64 | |
| 6103 } | |
| 6104 | |
| 6105 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) { | |
| 6106 assert(src2.is_lval(), "not a mem-mem compare"); | |
| 6107 #ifdef _LP64 | |
| 6108 // moves src2's literal address | |
| 6109 movptr(rscratch1, src2); | |
| 6110 Assembler::cmpq(src1, rscratch1); | |
| 6111 #else | |
| 6112 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); | |
| 6113 #endif // _LP64 | |
| 6114 } | |
| 6115 | |
| 6116 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) { | |
| 6117 if (reachable(adr)) { | |
| 6118 if (os::is_MP()) | |
| 6119 lock(); | |
| 6120 cmpxchgptr(reg, as_Address(adr)); | |
| 6121 } else { | |
| 6122 lea(rscratch1, adr); | |
| 6123 if (os::is_MP()) | |
| 6124 lock(); | |
| 6125 cmpxchgptr(reg, Address(rscratch1, 0)); | |
| 6126 } | |
| 6127 } | |
| 6128 | |
| 6129 void MacroAssembler::cmpxchgptr(Register reg, Address adr) { | |
| 6130 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr)); | |
| 6131 } | |
| 6132 | |
| 6133 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) { | |
| 1060 | 6134 if (reachable(src)) { |
| 6135 comisd(dst, as_Address(src)); | |
| 6136 } else { | |
| 6137 lea(rscratch1, src); | |
| 6138 comisd(dst, Address(rscratch1, 0)); | |
| 6139 } | |
| 304 | 6140 } |
| 6141 | |
| 6142 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) { | |
| 1060 | 6143 if (reachable(src)) { |
| 6144 comiss(dst, as_Address(src)); | |
| 6145 } else { | |
| 6146 lea(rscratch1, src); | |
| 6147 comiss(dst, Address(rscratch1, 0)); | |
| 6148 } | |
| 304 | 6149 } |
| 6150 | |
| 6151 | |
| 6152 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) { | |
| 6153 Condition negated_cond = negate_condition(cond); | |
| 6154 Label L; | |
| 6155 jcc(negated_cond, L); | |
| 6156 atomic_incl(counter_addr); | |
| 6157 bind(L); | |
| 6158 } | |
| 6159 | |
| 6160 int MacroAssembler::corrected_idivl(Register reg) { | |
| 6161 // Full implementation of Java idiv and irem; checks for | |
| 6162 // special case as described in JVM spec., p.243 & p.271. | |
| 6163 // The function returns the (pc) offset of the idivl | |
| 6164 // instruction - may be needed for implicit exceptions. | |
| 6165 // | |
| 6166 // normal case special case | |
| 6167 // | |
| 6168 // input : rax,: dividend min_int | |
| 6169 // reg: divisor (may not be rax,/rdx) -1 | |
| 6170 // | |
| 6171 // output: rax,: quotient (= rax, idiv reg) min_int | |
| 6172 // rdx: remainder (= rax, irem reg) 0 | |
| 6173 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register"); | |
| 6174 const int min_int = 0x80000000; | |
| 6175 Label normal_case, special_case; | |
| 6176 | |
| 6177 // check for special case | |
| 6178 cmpl(rax, min_int); | |
| 6179 jcc(Assembler::notEqual, normal_case); | |
| 6180 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0) | |
| 6181 cmpl(reg, -1); | |
| 6182 jcc(Assembler::equal, special_case); | |
| 6183 | |
| 6184 // handle normal case | |
| 6185 bind(normal_case); | |
| 6186 cdql(); | |
| 6187 int idivl_offset = offset(); | |
| 6188 idivl(reg); | |
| 6189 | |
| 6190 // normal and special case exit | |
| 6191 bind(special_case); | |
| 6192 | |
| 6193 return idivl_offset; | |
| 6194 } | |
| 6195 | |
| 6196 | |
| 6197 | |
| 6198 void MacroAssembler::decrementl(Register reg, int value) { | |
| 6199 if (value == min_jint) {subl(reg, value) ; return; } | |
| 6200 if (value < 0) { incrementl(reg, -value); return; } | |
| 6201 if (value == 0) { ; return; } | |
| 6202 if (value == 1 && UseIncDec) { decl(reg) ; return; } | |
| 6203 /* else */ { subl(reg, value) ; return; } | |
| 6204 } | |
| 6205 | |
| 6206 void MacroAssembler::decrementl(Address dst, int value) { | |
| 6207 if (value == min_jint) {subl(dst, value) ; return; } | |
| 6208 if (value < 0) { incrementl(dst, -value); return; } | |
| 6209 if (value == 0) { ; return; } | |
| 6210 if (value == 1 && UseIncDec) { decl(dst) ; return; } | |
| 6211 /* else */ { subl(dst, value) ; return; } | |
| 6212 } | |
| 6213 | |
| 6214 void MacroAssembler::division_with_shift (Register reg, int shift_value) { | |
| 6215 assert (shift_value > 0, "illegal shift value"); | |
| 6216 Label _is_positive; | |
| 6217 testl (reg, reg); | |
| 6218 jcc (Assembler::positive, _is_positive); | |
| 6219 int offset = (1 << shift_value) - 1 ; | |
| 6220 | |
| 6221 if (offset == 1) { | |
| 6222 incrementl(reg); | |
| 6223 } else { | |
| 6224 addl(reg, offset); | |
| 6225 } | |
| 6226 | |
| 6227 bind (_is_positive); | |
| 6228 sarl(reg, shift_value); | |
| 6229 } | |
| 6230 | |
| 6231 // !defined(COMPILER2) is because of stupid core builds | |
| 6232 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) | |
| 6233 void MacroAssembler::empty_FPU_stack() { | |
| 6234 if (VM_Version::supports_mmx()) { | |
| 6235 emms(); | |
| 6236 } else { | |
| 6237 for (int i = 8; i-- > 0; ) ffree(i); | |
| 6238 } | |
| 6239 } | |
| 6240 #endif // !LP64 || C1 || !C2 | |
| 6241 | |
| 6242 | |
| 6243 // Defines obj, preserves var_size_in_bytes | |
| 6244 void MacroAssembler::eden_allocate(Register obj, | |
| 6245 Register var_size_in_bytes, | |
| 6246 int con_size_in_bytes, | |
| 6247 Register t1, | |
| 6248 Label& slow_case) { | |
| 6249 assert(obj == rax, "obj must be in rax, for cmpxchg"); | |
| 6250 assert_different_registers(obj, var_size_in_bytes, t1); | |
| 362 | 6251 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { |
| 6252 jmp(slow_case); | |
| 304 | 6253 } else { |
| 362 | 6254 Register end = t1; |
| 6255 Label retry; | |
| 6256 bind(retry); | |
| 6257 ExternalAddress heap_top((address) Universe::heap()->top_addr()); | |
| 6258 movptr(obj, heap_top); | |
| 6259 if (var_size_in_bytes == noreg) { | |
| 6260 lea(end, Address(obj, con_size_in_bytes)); | |
| 6261 } else { | |
| 6262 lea(end, Address(obj, var_size_in_bytes, Address::times_1)); | |
| 6263 } | |
| 6264 // if end < obj then we wrapped around => object too long => slow case | |
| 6265 cmpptr(end, obj); | |
| 6266 jcc(Assembler::below, slow_case); | |
| 6267 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr())); | |
| 6268 jcc(Assembler::above, slow_case); | |
| 6269 // Compare obj with the top addr, and if still equal, store the new top addr in | |
| 6270 // end at the address of the top addr pointer. Sets ZF if was equal, and clears | |
| 6271 // it otherwise. Use lock prefix for atomicity on MPs. | |
| 6272 locked_cmpxchgptr(end, heap_top); | |
| 6273 jcc(Assembler::notEqual, retry); | |
| 6274 } | |
| 304 | 6275 } |
| 6276 | |
| 6277 void MacroAssembler::enter() { | |
| 6278 push(rbp); | |
| 6279 mov(rbp, rsp); | |
| 6280 } | |
| 0 | 6281 |
| 6282 void MacroAssembler::fcmp(Register tmp) { | |
| 6283 fcmp(tmp, 1, true, true); | |
| 6284 } | |
| 6285 | |
| 6286 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) { | |
| 6287 assert(!pop_right || pop_left, "usage error"); | |
| 6288 if (VM_Version::supports_cmov()) { | |
| 6289 assert(tmp == noreg, "unneeded temp"); | |
| 6290 if (pop_left) { | |
| 6291 fucomip(index); | |
| 6292 } else { | |
| 6293 fucomi(index); | |
| 6294 } | |
| 6295 if (pop_right) { | |
| 6296 fpop(); | |
| 6297 } | |
| 6298 } else { | |
| 6299 assert(tmp != noreg, "need temp"); | |
| 6300 if (pop_left) { | |
| 6301 if (pop_right) { | |
| 6302 fcompp(); | |
| 6303 } else { | |
| 6304 fcomp(index); | |
| 6305 } | |
| 6306 } else { | |
| 6307 fcom(index); | |
| 6308 } | |
| 6309 // convert FPU condition into eflags condition via rax, | |
| 6310 save_rax(tmp); | |
| 6311 fwait(); fnstsw_ax(); | |
| 6312 sahf(); | |
| 6313 restore_rax(tmp); | |
| 6314 } | |
| 6315 // condition codes set as follows: | |
| 6316 // | |
| 6317 // CF (corresponds to C0) if x < y | |
| 6318 // PF (corresponds to C2) if unordered | |
| 6319 // ZF (corresponds to C3) if x = y | |
| 6320 } | |
| 6321 | |
| 6322 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) { | |
| 6323 fcmp2int(dst, unordered_is_less, 1, true, true); | |
| 6324 } | |
| 6325 | |
| 6326 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) { | |
| 6327 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right); | |
| 6328 Label L; | |
| 6329 if (unordered_is_less) { | |
| 6330 movl(dst, -1); | |
| 6331 jcc(Assembler::parity, L); | |
| 6332 jcc(Assembler::below , L); | |
| 6333 movl(dst, 0); | |
| 6334 jcc(Assembler::equal , L); | |
| 6335 increment(dst); | |
| 6336 } else { // unordered is greater | |
| 6337 movl(dst, 1); | |
| 6338 jcc(Assembler::parity, L); | |
| 6339 jcc(Assembler::above , L); | |
| 6340 movl(dst, 0); | |
| 6341 jcc(Assembler::equal , L); | |
| 304 | 6342 decrementl(dst); |
| 0 | 6343 } |
| 6344 bind(L); | |
| 6345 } | |
| 6346 | |
| 304 | 6347 void MacroAssembler::fld_d(AddressLiteral src) { |
| 6348 fld_d(as_Address(src)); | |
| 6349 } | |
| 6350 | |
| 6351 void MacroAssembler::fld_s(AddressLiteral src) { | |
| 6352 fld_s(as_Address(src)); | |
| 6353 } | |
| 6354 | |
| 6355 void MacroAssembler::fld_x(AddressLiteral src) { | |
| 6356 Assembler::fld_x(as_Address(src)); | |
| 6357 } | |
| 6358 | |
| 6359 void MacroAssembler::fldcw(AddressLiteral src) { | |
| 6360 Assembler::fldcw(as_Address(src)); | |
| 6361 } | |
| 0 | 6362 |
| 6363 void MacroAssembler::fpop() { | |
| 6364 ffree(); | |
| 6365 fincstp(); | |
| 6366 } | |
| 6367 | |
| 304 | 6368 void MacroAssembler::fremr(Register tmp) { |
| 6369 save_rax(tmp); | |
| 6370 { Label L; | |
| 6371 bind(L); | |
| 6372 fprem(); | |
| 6373 fwait(); fnstsw_ax(); | |
| 6374 #ifdef _LP64 | |
| 6375 testl(rax, 0x400); | |
| 6376 jcc(Assembler::notEqual, L); | |
| 6377 #else | |
| 6378 sahf(); | |
| 6379 jcc(Assembler::parity, L); | |
| 6380 #endif // _LP64 | |
| 6381 } | |
| 6382 restore_rax(tmp); | |
| 6383 // Result is in ST0. | |
| 6384 // Note: fxch & fpop to get rid of ST1 | |
| 6385 // (otherwise FPU stack could overflow eventually) | |
| 6386 fxch(1); | |
| 6387 fpop(); | |
| 6388 } | |
| 6389 | |
| 6390 | |
| 6391 void MacroAssembler::incrementl(AddressLiteral dst) { | |
| 6392 if (reachable(dst)) { | |
| 6393 incrementl(as_Address(dst)); | |
| 0 | 6394 } else { |
| 304 | 6395 lea(rscratch1, dst); |
| 6396 incrementl(Address(rscratch1, 0)); | |
| 6397 } | |
| 6398 } | |
| 6399 | |
| 6400 void MacroAssembler::incrementl(ArrayAddress dst) { | |
| 6401 incrementl(as_Address(dst)); | |
| 6402 } | |
| 6403 | |
| 6404 void MacroAssembler::incrementl(Register reg, int value) { | |
| 6405 if (value == min_jint) {addl(reg, value) ; return; } | |
| 6406 if (value < 0) { decrementl(reg, -value); return; } | |
| 6407 if (value == 0) { ; return; } | |
| 6408 if (value == 1 && UseIncDec) { incl(reg) ; return; } | |
| 6409 /* else */ { addl(reg, value) ; return; } | |
| 6410 } | |
| 6411 | |
| 6412 void MacroAssembler::incrementl(Address dst, int value) { | |
| 6413 if (value == min_jint) {addl(dst, value) ; return; } | |
| 6414 if (value < 0) { decrementl(dst, -value); return; } | |
| 6415 if (value == 0) { ; return; } | |
| 6416 if (value == 1 && UseIncDec) { incl(dst) ; return; } | |
| 6417 /* else */ { addl(dst, value) ; return; } | |
| 6418 } | |
| 6419 | |
| 6420 void MacroAssembler::jump(AddressLiteral dst) { | |
| 6421 if (reachable(dst)) { | |
| 6422 jmp_literal(dst.target(), dst.rspec()); | |
| 6423 } else { | |
| 6424 lea(rscratch1, dst); | |
| 6425 jmp(rscratch1); | |
| 6426 } | |
| 6427 } | |
| 6428 | |
| 6429 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) { | |
| 6430 if (reachable(dst)) { | |
| 6431 InstructionMark im(this); | |
| 6432 relocate(dst.reloc()); | |
| 6433 const int short_size = 2; | |
| 6434 const int long_size = 6; | |
| 6435 int offs = (intptr_t)dst.target() - ((intptr_t)_code_pos); | |
| 6436 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) { | |
| 6437 // 0111 tttn #8-bit disp | |
| 6438 emit_byte(0x70 | cc); | |
| 6439 emit_byte((offs - short_size) & 0xFF); | |
| 6440 } else { | |
| 6441 // 0000 1111 1000 tttn #32-bit disp | |
| 6442 emit_byte(0x0F); | |
| 6443 emit_byte(0x80 | cc); | |
| 6444 emit_long(offs - long_size); | |
| 6445 } | |
| 0 | 6446 } else { |
| 304 | 6447 #ifdef ASSERT |
| 6448 warning("reversing conditional branch"); | |
| 6449 #endif /* ASSERT */ | |
| 6450 Label skip; | |
| 6451 jccb(reverse[cc], skip); | |
| 6452 lea(rscratch1, dst); | |
| 6453 Assembler::jmp(rscratch1); | |
| 6454 bind(skip); | |
| 6455 } | |
| 6456 } | |
| 6457 | |
| 6458 void MacroAssembler::ldmxcsr(AddressLiteral src) { | |
| 6459 if (reachable(src)) { | |
| 6460 Assembler::ldmxcsr(as_Address(src)); | |
| 6461 } else { | |
| 6462 lea(rscratch1, src); | |
| 6463 Assembler::ldmxcsr(Address(rscratch1, 0)); | |
| 6464 } | |
| 6465 } | |
| 6466 | |
| 6467 int MacroAssembler::load_signed_byte(Register dst, Address src) { | |
| 6468 int off; | |
| 6469 if (LP64_ONLY(true ||) VM_Version::is_P6()) { | |
| 6470 off = offset(); | |
| 6471 movsbl(dst, src); // movsxb | |
| 6472 } else { | |
| 6473 off = load_unsigned_byte(dst, src); | |
| 6474 shll(dst, 24); | |
| 6475 sarl(dst, 24); | |
| 6476 } | |
| 6477 return off; | |
| 6478 } | |
| 6479 | |
|
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6480 // Note: load_signed_short used to be called load_signed_word. |
|
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|
6481 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler |
|
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|
6482 // manual, which means 16 bits, that usage is found nowhere in HotSpot code. |
|
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|
6483 // The term "word" in HotSpot means a 32- or 64-bit machine word. |
|
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|
6484 int MacroAssembler::load_signed_short(Register dst, Address src) { |
| 304 | 6485 int off; |
| 6486 if (LP64_ONLY(true ||) VM_Version::is_P6()) { | |
| 6487 // This is dubious to me since it seems safe to do a signed 16 => 64 bit | |
| 6488 // version but this is what 64bit has always done. This seems to imply | |
| 6489 // that users are only using 32bits worth. | |
| 6490 off = offset(); | |
| 6491 movswl(dst, src); // movsxw | |
| 6492 } else { | |
|
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|
6493 off = load_unsigned_short(dst, src); |
| 304 | 6494 shll(dst, 16); |
| 6495 sarl(dst, 16); | |
| 6496 } | |
| 6497 return off; | |
| 6498 } | |
| 6499 | |
| 6500 int MacroAssembler::load_unsigned_byte(Register dst, Address src) { | |
| 6501 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, | |
| 6502 // and "3.9 Partial Register Penalties", p. 22). | |
| 6503 int off; | |
| 6504 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) { | |
| 6505 off = offset(); | |
| 6506 movzbl(dst, src); // movzxb | |
| 6507 } else { | |
| 6508 xorl(dst, dst); | |
| 6509 off = offset(); | |
| 6510 movb(dst, src); | |
| 6511 } | |
| 6512 return off; | |
| 6513 } | |
| 6514 | |
|
622
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|
6515 // Note: load_unsigned_short used to be called load_unsigned_word. |
|
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|
6516 int MacroAssembler::load_unsigned_short(Register dst, Address src) { |
| 304 | 6517 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, |
| 6518 // and "3.9 Partial Register Penalties", p. 22). | |
| 6519 int off; | |
| 6520 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) { | |
| 6521 off = offset(); | |
| 6522 movzwl(dst, src); // movzxw | |
| 6523 } else { | |
| 6524 xorl(dst, dst); | |
| 6525 off = offset(); | |
| 6526 movw(dst, src); | |
| 6527 } | |
| 6528 return off; | |
| 6529 } | |
| 6530 | |
|
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diff
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|
6531 void MacroAssembler::load_sized_value(Register dst, Address src, |
| 1503 | 6532 size_t size_in_bytes, bool is_signed) { |
| 6533 switch (size_in_bytes) { | |
|
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6534 #ifndef _LP64 |
|
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6535 // For case 8, caller is responsible for manually loading |
|
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6536 // the second word into another register. |
| 1503 | 6537 case 8: movl(dst, src); break; |
|
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6538 #else |
| 1503 | 6539 case 8: movq(dst, src); break; |
|
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6540 #endif |
| 1503 | 6541 case 4: movl(dst, src); break; |
| 6542 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break; | |
| 6543 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break; | |
| 6544 default: ShouldNotReachHere(); | |
|
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6545 } |
|
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6546 } |
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|
6547 |
| 304 | 6548 void MacroAssembler::mov32(AddressLiteral dst, Register src) { |
| 6549 if (reachable(dst)) { | |
| 6550 movl(as_Address(dst), src); | |
| 6551 } else { | |
| 6552 lea(rscratch1, dst); | |
| 6553 movl(Address(rscratch1, 0), src); | |
| 6554 } | |
| 6555 } | |
| 6556 | |
| 6557 void MacroAssembler::mov32(Register dst, AddressLiteral src) { | |
| 6558 if (reachable(src)) { | |
| 6559 movl(dst, as_Address(src)); | |
| 6560 } else { | |
| 6561 lea(rscratch1, src); | |
| 6562 movl(dst, Address(rscratch1, 0)); | |
| 6563 } | |
| 0 | 6564 } |
| 6565 | |
| 6566 // C++ bool manipulation | |
| 6567 | |
| 6568 void MacroAssembler::movbool(Register dst, Address src) { | |
| 6569 if(sizeof(bool) == 1) | |
| 6570 movb(dst, src); | |
| 6571 else if(sizeof(bool) == 2) | |
| 6572 movw(dst, src); | |
| 6573 else if(sizeof(bool) == 4) | |
| 6574 movl(dst, src); | |
| 6575 else | |
| 6576 // unsupported | |
| 6577 ShouldNotReachHere(); | |
| 6578 } | |
| 6579 | |
| 6580 void MacroAssembler::movbool(Address dst, bool boolconst) { | |
| 6581 if(sizeof(bool) == 1) | |
| 6582 movb(dst, (int) boolconst); | |
| 6583 else if(sizeof(bool) == 2) | |
| 6584 movw(dst, (int) boolconst); | |
| 6585 else if(sizeof(bool) == 4) | |
| 6586 movl(dst, (int) boolconst); | |
| 6587 else | |
| 6588 // unsupported | |
| 6589 ShouldNotReachHere(); | |
| 6590 } | |
| 6591 | |
| 6592 void MacroAssembler::movbool(Address dst, Register src) { | |
| 6593 if(sizeof(bool) == 1) | |
| 6594 movb(dst, src); | |
| 6595 else if(sizeof(bool) == 2) | |
| 6596 movw(dst, src); | |
| 6597 else if(sizeof(bool) == 4) | |
| 6598 movl(dst, src); | |
| 6599 else | |
| 6600 // unsupported | |
| 6601 ShouldNotReachHere(); | |
| 6602 } | |
| 6603 | |
| 304 | 6604 void MacroAssembler::movbyte(ArrayAddress dst, int src) { |
| 6605 movb(as_Address(dst), src); | |
| 6606 } | |
| 6607 | |
| 6608 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) { | |
| 6609 if (reachable(src)) { | |
| 6610 if (UseXmmLoadAndClearUpper) { | |
| 6611 movsd (dst, as_Address(src)); | |
| 6612 } else { | |
| 6613 movlpd(dst, as_Address(src)); | |
| 6614 } | |
| 6615 } else { | |
| 6616 lea(rscratch1, src); | |
| 6617 if (UseXmmLoadAndClearUpper) { | |
| 6618 movsd (dst, Address(rscratch1, 0)); | |
| 6619 } else { | |
| 6620 movlpd(dst, Address(rscratch1, 0)); | |
| 6621 } | |
| 6622 } | |
| 6623 } | |
| 6624 | |
| 6625 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) { | |
| 6626 if (reachable(src)) { | |
| 6627 movss(dst, as_Address(src)); | |
| 6628 } else { | |
| 6629 lea(rscratch1, src); | |
| 6630 movss(dst, Address(rscratch1, 0)); | |
| 6631 } | |
| 6632 } | |
| 6633 | |
| 6634 void MacroAssembler::movptr(Register dst, Register src) { | |
| 6635 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
| 6636 } | |
| 6637 | |
| 6638 void MacroAssembler::movptr(Register dst, Address src) { | |
| 6639 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
| 6640 } | |
| 6641 | |
| 6642 // src should NEVER be a real pointer. Use AddressLiteral for true pointers | |
| 6643 void MacroAssembler::movptr(Register dst, intptr_t src) { | |
| 6644 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src)); | |
| 6645 } | |
| 6646 | |
| 6647 void MacroAssembler::movptr(Address dst, Register src) { | |
| 6648 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
| 6649 } | |
| 6650 | |
| 6651 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) { | |
| 6652 if (reachable(src)) { | |
| 6653 movss(dst, as_Address(src)); | |
| 6654 } else { | |
| 6655 lea(rscratch1, src); | |
| 6656 movss(dst, Address(rscratch1, 0)); | |
| 6657 } | |
| 6658 } | |
| 6659 | |
| 6660 void MacroAssembler::null_check(Register reg, int offset) { | |
| 6661 if (needs_explicit_null_check(offset)) { | |
| 6662 // provoke OS NULL exception if reg = NULL by | |
| 6663 // accessing M[reg] w/o changing any (non-CC) registers | |
| 6664 // NOTE: cmpl is plenty here to provoke a segv | |
| 6665 cmpptr(rax, Address(reg, 0)); | |
| 6666 // Note: should probably use testl(rax, Address(reg, 0)); | |
| 6667 // may be shorter code (however, this version of | |
| 6668 // testl needs to be implemented first) | |
| 6669 } else { | |
| 6670 // nothing to do, (later) access of M[reg + offset] | |
| 6671 // will provoke OS NULL exception if reg = NULL | |
| 6672 } | |
| 6673 } | |
| 6674 | |
| 6675 void MacroAssembler::os_breakpoint() { | |
| 6676 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability | |
| 6677 // (e.g., MSVC can't call ps() otherwise) | |
| 6678 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint))); | |
| 6679 } | |
| 6680 | |
| 6681 void MacroAssembler::pop_CPU_state() { | |
| 6682 pop_FPU_state(); | |
| 6683 pop_IU_state(); | |
| 6684 } | |
| 6685 | |
| 6686 void MacroAssembler::pop_FPU_state() { | |
| 6687 NOT_LP64(frstor(Address(rsp, 0));) | |
| 6688 LP64_ONLY(fxrstor(Address(rsp, 0));) | |
| 6689 addptr(rsp, FPUStateSizeInWords * wordSize); | |
| 6690 } | |
| 6691 | |
| 6692 void MacroAssembler::pop_IU_state() { | |
| 6693 popa(); | |
| 6694 LP64_ONLY(addq(rsp, 8)); | |
| 6695 popf(); | |
| 6696 } | |
| 6697 | |
| 6698 // Save Integer and Float state | |
| 6699 // Warning: Stack must be 16 byte aligned (64bit) | |
| 6700 void MacroAssembler::push_CPU_state() { | |
| 6701 push_IU_state(); | |
| 6702 push_FPU_state(); | |
| 6703 } | |
| 6704 | |
| 6705 void MacroAssembler::push_FPU_state() { | |
| 6706 subptr(rsp, FPUStateSizeInWords * wordSize); | |
| 6707 #ifndef _LP64 | |
| 6708 fnsave(Address(rsp, 0)); | |
| 6709 fwait(); | |
| 6710 #else | |
| 6711 fxsave(Address(rsp, 0)); | |
| 6712 #endif // LP64 | |
| 6713 } | |
| 6714 | |
| 6715 void MacroAssembler::push_IU_state() { | |
| 6716 // Push flags first because pusha kills them | |
| 6717 pushf(); | |
| 6718 // Make sure rsp stays 16-byte aligned | |
| 6719 LP64_ONLY(subq(rsp, 8)); | |
| 6720 pusha(); | |
| 6721 } | |
| 6722 | |
| 6723 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) { | |
| 6724 // determine java_thread register | |
| 6725 if (!java_thread->is_valid()) { | |
| 6726 java_thread = rdi; | |
| 6727 get_thread(java_thread); | |
| 6728 } | |
| 6729 // we must set sp to zero to clear frame | |
|
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|
6730 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); |
| 304 | 6731 if (clear_fp) { |
|
512
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|
6732 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); |
| 304 | 6733 } |
| 6734 | |
| 6735 if (clear_pc) | |
|
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|
6736 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); |
| 304 | 6737 |
| 6738 } | |
| 6739 | |
| 6740 void MacroAssembler::restore_rax(Register tmp) { | |
| 6741 if (tmp == noreg) pop(rax); | |
| 6742 else if (tmp != rax) mov(rax, tmp); | |
| 6743 } | |
| 6744 | |
| 6745 void MacroAssembler::round_to(Register reg, int modulus) { | |
| 6746 addptr(reg, modulus - 1); | |
| 6747 andptr(reg, -modulus); | |
| 6748 } | |
| 6749 | |
| 6750 void MacroAssembler::save_rax(Register tmp) { | |
| 6751 if (tmp == noreg) push(rax); | |
| 6752 else if (tmp != rax) mov(tmp, rax); | |
| 6753 } | |
| 6754 | |
| 6755 // Write serialization page so VM thread can do a pseudo remote membar. | |
| 6756 // We use the current thread pointer to calculate a thread specific | |
| 6757 // offset to write to within the page. This minimizes bus traffic | |
| 6758 // due to cache line collision. | |
| 6759 void MacroAssembler::serialize_memory(Register thread, Register tmp) { | |
| 6760 movl(tmp, thread); | |
| 6761 shrl(tmp, os::get_serialize_page_shift_count()); | |
| 6762 andl(tmp, (os::vm_page_size() - sizeof(int))); | |
| 6763 | |
| 6764 Address index(noreg, tmp, Address::times_1); | |
| 6765 ExternalAddress page(os::get_memory_serialize_page()); | |
| 6766 | |
|
606
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520
diff
changeset
|
6767 // Size of store must match masking code above |
|
19962e74284f
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520
diff
changeset
|
6768 movl(as_Address(ArrayAddress(page, index)), tmp); |
| 304 | 6769 } |
| 6770 | |
| 6771 // Calls to C land | |
| 6772 // | |
| 6773 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded | |
| 6774 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp | |
| 6775 // has to be reset to 0. This is required to allow proper stack traversal. | |
| 6776 void MacroAssembler::set_last_Java_frame(Register java_thread, | |
| 6777 Register last_java_sp, | |
| 6778 Register last_java_fp, | |
| 6779 address last_java_pc) { | |
| 6780 // determine java_thread register | |
| 6781 if (!java_thread->is_valid()) { | |
| 6782 java_thread = rdi; | |
| 6783 get_thread(java_thread); | |
| 6784 } | |
| 6785 // determine last_java_sp register | |
| 6786 if (!last_java_sp->is_valid()) { | |
| 6787 last_java_sp = rsp; | |
| 6788 } | |
| 6789 | |
| 6790 // last_java_fp is optional | |
| 6791 | |
| 6792 if (last_java_fp->is_valid()) { | |
| 6793 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp); | |
| 6794 } | |
| 6795 | |
| 6796 // last_java_pc is optional | |
| 6797 | |
| 6798 if (last_java_pc != NULL) { | |
| 6799 lea(Address(java_thread, | |
| 6800 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()), | |
| 6801 InternalAddress(last_java_pc)); | |
| 6802 | |
| 6803 } | |
| 6804 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp); | |
| 6805 } | |
| 6806 | |
| 6807 void MacroAssembler::shlptr(Register dst, int imm8) { | |
| 6808 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8)); | |
| 6809 } | |
| 6810 | |
| 6811 void MacroAssembler::shrptr(Register dst, int imm8) { | |
| 6812 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8)); | |
| 6813 } | |
| 6814 | |
| 6815 void MacroAssembler::sign_extend_byte(Register reg) { | |
| 6816 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) { | |
| 6817 movsbl(reg, reg); // movsxb | |
| 6818 } else { | |
| 6819 shll(reg, 24); | |
| 6820 sarl(reg, 24); | |
| 6821 } | |
| 6822 } | |
| 6823 | |
| 6824 void MacroAssembler::sign_extend_short(Register reg) { | |
| 6825 if (LP64_ONLY(true ||) VM_Version::is_P6()) { | |
| 6826 movswl(reg, reg); // movsxw | |
| 6827 } else { | |
| 6828 shll(reg, 16); | |
| 6829 sarl(reg, 16); | |
| 6830 } | |
| 6831 } | |
| 6832 | |
| 362 | 6833 ////////////////////////////////////////////////////////////////////////////////// |
| 6834 #ifndef SERIALGC | |
| 6835 | |
| 6836 void MacroAssembler::g1_write_barrier_pre(Register obj, | |
| 6837 #ifndef _LP64 | |
| 6838 Register thread, | |
| 6839 #endif | |
| 6840 Register tmp, | |
| 6841 Register tmp2, | |
| 6842 bool tosca_live) { | |
| 6843 LP64_ONLY(Register thread = r15_thread;) | |
| 6844 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() + | |
| 6845 PtrQueue::byte_offset_of_active())); | |
| 6846 | |
| 6847 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() + | |
| 6848 PtrQueue::byte_offset_of_index())); | |
| 6849 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() + | |
| 6850 PtrQueue::byte_offset_of_buf())); | |
| 6851 | |
| 6852 | |
| 6853 Label done; | |
| 6854 Label runtime; | |
| 6855 | |
| 6856 // if (!marking_in_progress) goto done; | |
| 6857 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) { | |
| 6858 cmpl(in_progress, 0); | |
| 6859 } else { | |
| 6860 assert(in_bytes(PtrQueue::byte_width_of_active()) == 1, "Assumption"); | |
| 6861 cmpb(in_progress, 0); | |
| 6862 } | |
| 6863 jcc(Assembler::equal, done); | |
| 6864 | |
| 6865 // if (x.f == NULL) goto done; | |
|
845
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|
6866 #ifdef _LP64 |
|
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|
6867 load_heap_oop(tmp2, Address(obj, 0)); |
|
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|
6868 #else |
|
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|
6869 movptr(tmp2, Address(obj, 0)); |
|
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|
6870 #endif |
|
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|
6871 cmpptr(tmp2, (int32_t) NULL_WORD); |
| 362 | 6872 jcc(Assembler::equal, done); |
| 6873 | |
| 6874 // Can we store original value in the thread's buffer? | |
| 6875 | |
| 6876 #ifdef _LP64 | |
|
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|
6877 movslq(tmp, index); |
| 362 | 6878 cmpq(tmp, 0); |
| 6879 #else | |
| 6880 cmpl(index, 0); | |
| 6881 #endif | |
| 6882 jcc(Assembler::equal, runtime); | |
| 6883 #ifdef _LP64 | |
| 6884 subq(tmp, wordSize); | |
| 6885 movl(index, tmp); | |
| 6886 addq(tmp, buffer); | |
| 6887 #else | |
| 6888 subl(index, wordSize); | |
| 6889 movl(tmp, buffer); | |
| 6890 addl(tmp, index); | |
| 6891 #endif | |
| 6892 movptr(Address(tmp, 0), tmp2); | |
| 6893 jmp(done); | |
| 6894 bind(runtime); | |
| 6895 // save the live input values | |
| 6896 if(tosca_live) push(rax); | |
| 6897 push(obj); | |
| 6898 #ifdef _LP64 | |
|
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|
6899 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), tmp2, r15_thread); |
| 362 | 6900 #else |
| 6901 push(thread); | |
| 6902 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), tmp2, thread); | |
| 6903 pop(thread); | |
| 6904 #endif | |
| 6905 pop(obj); | |
| 6906 if(tosca_live) pop(rax); | |
| 6907 bind(done); | |
| 6908 | |
| 6909 } | |
| 6910 | |
| 6911 void MacroAssembler::g1_write_barrier_post(Register store_addr, | |
| 6912 Register new_val, | |
| 6913 #ifndef _LP64 | |
| 6914 Register thread, | |
| 6915 #endif | |
| 6916 Register tmp, | |
| 6917 Register tmp2) { | |
| 6918 | |
| 6919 LP64_ONLY(Register thread = r15_thread;) | |
| 6920 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() + | |
| 6921 PtrQueue::byte_offset_of_index())); | |
| 6922 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() + | |
| 6923 PtrQueue::byte_offset_of_buf())); | |
| 6924 BarrierSet* bs = Universe::heap()->barrier_set(); | |
| 6925 CardTableModRefBS* ct = (CardTableModRefBS*)bs; | |
| 6926 Label done; | |
| 6927 Label runtime; | |
| 6928 | |
| 6929 // Does store cross heap regions? | |
| 6930 | |
| 6931 movptr(tmp, store_addr); | |
| 6932 xorptr(tmp, new_val); | |
| 6933 shrptr(tmp, HeapRegion::LogOfHRGrainBytes); | |
| 6934 jcc(Assembler::equal, done); | |
| 6935 | |
| 6936 // crosses regions, storing NULL? | |
| 6937 | |
| 6938 cmpptr(new_val, (int32_t) NULL_WORD); | |
| 6939 jcc(Assembler::equal, done); | |
| 6940 | |
| 6941 // storing region crossing non-NULL, is card already dirty? | |
| 6942 | |
| 6943 ExternalAddress cardtable((address) ct->byte_map_base); | |
| 6944 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); | |
| 6945 #ifdef _LP64 | |
| 6946 const Register card_addr = tmp; | |
| 6947 | |
| 6948 movq(card_addr, store_addr); | |
| 6949 shrq(card_addr, CardTableModRefBS::card_shift); | |
| 6950 | |
| 6951 lea(tmp2, cardtable); | |
| 6952 | |
| 6953 // get the address of the card | |
| 6954 addq(card_addr, tmp2); | |
| 6955 #else | |
| 6956 const Register card_index = tmp; | |
| 6957 | |
| 6958 movl(card_index, store_addr); | |
| 6959 shrl(card_index, CardTableModRefBS::card_shift); | |
| 6960 | |
| 6961 Address index(noreg, card_index, Address::times_1); | |
| 6962 const Register card_addr = tmp; | |
| 6963 lea(card_addr, as_Address(ArrayAddress(cardtable, index))); | |
| 6964 #endif | |
| 6965 cmpb(Address(card_addr, 0), 0); | |
| 6966 jcc(Assembler::equal, done); | |
| 6967 | |
| 6968 // storing a region crossing, non-NULL oop, card is clean. | |
| 6969 // dirty card and log. | |
| 6970 | |
| 6971 movb(Address(card_addr, 0), 0); | |
| 6972 | |
| 6973 cmpl(queue_index, 0); | |
| 6974 jcc(Assembler::equal, runtime); | |
| 6975 subl(queue_index, wordSize); | |
| 6976 movptr(tmp2, buffer); | |
| 6977 #ifdef _LP64 | |
| 6978 movslq(rscratch1, queue_index); | |
| 6979 addq(tmp2, rscratch1); | |
| 6980 movq(Address(tmp2, 0), card_addr); | |
| 6981 #else | |
| 6982 addl(tmp2, queue_index); | |
| 6983 movl(Address(tmp2, 0), card_index); | |
| 6984 #endif | |
| 6985 jmp(done); | |
| 6986 | |
| 6987 bind(runtime); | |
| 6988 // save the live input values | |
| 6989 push(store_addr); | |
| 6990 push(new_val); | |
| 6991 #ifdef _LP64 | |
| 6992 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread); | |
| 6993 #else | |
| 6994 push(thread); | |
| 6995 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread); | |
| 6996 pop(thread); | |
| 6997 #endif | |
| 6998 pop(new_val); | |
| 6999 pop(store_addr); | |
| 7000 | |
| 7001 bind(done); | |
| 7002 | |
| 7003 } | |
| 7004 | |
| 7005 #endif // SERIALGC | |
| 7006 ////////////////////////////////////////////////////////////////////////////////// | |
| 7007 | |
| 7008 | |
| 304 | 7009 void MacroAssembler::store_check(Register obj) { |
| 7010 // Does a store check for the oop in register obj. The content of | |
| 7011 // register obj is destroyed afterwards. | |
| 7012 store_check_part_1(obj); | |
| 7013 store_check_part_2(obj); | |
| 7014 } | |
| 7015 | |
| 7016 void MacroAssembler::store_check(Register obj, Address dst) { | |
| 7017 store_check(obj); | |
| 7018 } | |
| 7019 | |
| 7020 | |
| 7021 // split the store check operation so that other instructions can be scheduled inbetween | |
| 7022 void MacroAssembler::store_check_part_1(Register obj) { | |
| 7023 BarrierSet* bs = Universe::heap()->barrier_set(); | |
| 7024 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind"); | |
| 7025 shrptr(obj, CardTableModRefBS::card_shift); | |
| 7026 } | |
| 7027 | |
| 7028 void MacroAssembler::store_check_part_2(Register obj) { | |
| 7029 BarrierSet* bs = Universe::heap()->barrier_set(); | |
| 7030 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind"); | |
| 7031 CardTableModRefBS* ct = (CardTableModRefBS*)bs; | |
| 7032 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); | |
| 7033 | |
| 7034 // The calculation for byte_map_base is as follows: | |
| 7035 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift); | |
| 7036 // So this essentially converts an address to a displacement and | |
| 7037 // it will never need to be relocated. On 64bit however the value may be too | |
| 7038 // large for a 32bit displacement | |
| 7039 | |
| 7040 intptr_t disp = (intptr_t) ct->byte_map_base; | |
| 7041 if (is_simm32(disp)) { | |
| 7042 Address cardtable(noreg, obj, Address::times_1, disp); | |
| 7043 movb(cardtable, 0); | |
| 7044 } else { | |
| 7045 // By doing it as an ExternalAddress disp could be converted to a rip-relative | |
| 7046 // displacement and done in a single instruction given favorable mapping and | |
| 7047 // a smarter version of as_Address. Worst case it is two instructions which | |
| 7048 // is no worse off then loading disp into a register and doing as a simple | |
| 7049 // Address() as above. | |
| 7050 // We can't do as ExternalAddress as the only style since if disp == 0 we'll | |
| 7051 // assert since NULL isn't acceptable in a reloci (see 6644928). In any case | |
| 7052 // in some cases we'll get a single instruction version. | |
| 7053 | |
| 7054 ExternalAddress cardtable((address)disp); | |
| 7055 Address index(noreg, obj, Address::times_1); | |
| 7056 movb(as_Address(ArrayAddress(cardtable, index)), 0); | |
| 7057 } | |
| 7058 } | |
| 7059 | |
| 7060 void MacroAssembler::subptr(Register dst, int32_t imm32) { | |
| 7061 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32)); | |
| 7062 } | |
| 7063 | |
| 7064 void MacroAssembler::subptr(Register dst, Register src) { | |
| 7065 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); | |
| 7066 } | |
| 7067 | |
| 7068 void MacroAssembler::test32(Register src1, AddressLiteral src2) { | |
| 7069 // src2 must be rval | |
| 7070 | |
| 7071 if (reachable(src2)) { | |
| 7072 testl(src1, as_Address(src2)); | |
| 7073 } else { | |
| 7074 lea(rscratch1, src2); | |
| 7075 testl(src1, Address(rscratch1, 0)); | |
| 7076 } | |
| 7077 } | |
| 7078 | |
| 7079 // C++ bool manipulation | |
| 0 | 7080 void MacroAssembler::testbool(Register dst) { |
| 7081 if(sizeof(bool) == 1) | |
| 304 | 7082 testb(dst, 0xff); |
| 0 | 7083 else if(sizeof(bool) == 2) { |
| 7084 // testw implementation needed for two byte bools | |
| 7085 ShouldNotReachHere(); | |
| 7086 } else if(sizeof(bool) == 4) | |
| 7087 testl(dst, dst); | |
| 7088 else | |
| 7089 // unsupported | |
| 7090 ShouldNotReachHere(); | |
| 7091 } | |
| 7092 | |
| 304 | 7093 void MacroAssembler::testptr(Register dst, Register src) { |
| 7094 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src)); | |
| 7095 } | |
| 7096 | |
| 7097 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes. | |
| 7098 void MacroAssembler::tlab_allocate(Register obj, | |
| 7099 Register var_size_in_bytes, | |
| 7100 int con_size_in_bytes, | |
| 7101 Register t1, | |
| 7102 Register t2, | |
| 7103 Label& slow_case) { | |
| 7104 assert_different_registers(obj, t1, t2); | |
| 7105 assert_different_registers(obj, var_size_in_bytes, t1); | |
| 7106 Register end = t2; | |
| 7107 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread); | |
| 7108 | |
| 7109 verify_tlab(); | |
| 7110 | |
| 7111 NOT_LP64(get_thread(thread)); | |
| 7112 | |
| 7113 movptr(obj, Address(thread, JavaThread::tlab_top_offset())); | |
| 7114 if (var_size_in_bytes == noreg) { | |
| 7115 lea(end, Address(obj, con_size_in_bytes)); | |
| 7116 } else { | |
| 7117 lea(end, Address(obj, var_size_in_bytes, Address::times_1)); | |
| 7118 } | |
| 7119 cmpptr(end, Address(thread, JavaThread::tlab_end_offset())); | |
| 7120 jcc(Assembler::above, slow_case); | |
| 7121 | |
| 7122 // update the tlab top pointer | |
| 7123 movptr(Address(thread, JavaThread::tlab_top_offset()), end); | |
| 7124 | |
| 7125 // recover var_size_in_bytes if necessary | |
| 7126 if (var_size_in_bytes == end) { | |
| 7127 subptr(var_size_in_bytes, obj); | |
| 7128 } | |
| 7129 verify_tlab(); | |
| 7130 } | |
| 7131 | |
| 7132 // Preserves rbx, and rdx. | |
|
2100
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7133 Register MacroAssembler::tlab_refill(Label& retry, |
|
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|
7134 Label& try_eden, |
|
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|
7135 Label& slow_case) { |
| 304 | 7136 Register top = rax; |
| 7137 Register t1 = rcx; | |
| 7138 Register t2 = rsi; | |
| 7139 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread); | |
| 7140 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx); | |
| 7141 Label do_refill, discard_tlab; | |
| 7142 | |
| 7143 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { | |
| 7144 // No allocation in the shared eden. | |
| 7145 jmp(slow_case); | |
| 7146 } | |
| 7147 | |
| 7148 NOT_LP64(get_thread(thread_reg)); | |
| 7149 | |
| 7150 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); | |
| 7151 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); | |
| 7152 | |
| 7153 // calculate amount of free space | |
| 7154 subptr(t1, top); | |
| 7155 shrptr(t1, LogHeapWordSize); | |
| 7156 | |
| 7157 // Retain tlab and allocate object in shared space if | |
| 7158 // the amount free in the tlab is too large to discard. | |
| 7159 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset()))); | |
| 7160 jcc(Assembler::lessEqual, discard_tlab); | |
| 7161 | |
| 7162 // Retain | |
| 7163 // %%% yuck as movptr... | |
| 7164 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment()); | |
| 7165 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2); | |
| 7166 if (TLABStats) { | |
| 7167 // increment number of slow_allocations | |
| 7168 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1); | |
| 7169 } | |
| 7170 jmp(try_eden); | |
| 7171 | |
| 7172 bind(discard_tlab); | |
| 7173 if (TLABStats) { | |
| 7174 // increment number of refills | |
| 7175 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1); | |
| 7176 // accumulate wastage -- t1 is amount free in tlab | |
| 7177 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1); | |
| 7178 } | |
| 7179 | |
| 7180 // if tlab is currently allocated (top or end != null) then | |
| 7181 // fill [top, end + alignment_reserve) with array object | |
|
2100
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|
7182 testptr(top, top); |
| 304 | 7183 jcc(Assembler::zero, do_refill); |
| 7184 | |
| 7185 // set up the mark word | |
| 7186 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2)); | |
| 7187 // set the length to the remaining space | |
| 7188 subptr(t1, typeArrayOopDesc::header_size(T_INT)); | |
| 7189 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve()); | |
| 7190 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint))); | |
| 1690 | 7191 movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1); |
| 304 | 7192 // set klass to intArrayKlass |
| 7193 // dubious reloc why not an oop reloc? | |
|
2100
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|
7194 movptr(t1, ExternalAddress((address)Universe::intArrayKlassObj_addr())); |
| 304 | 7195 // store klass last. concurrent gcs assumes klass length is valid if |
| 7196 // klass field is not null. | |
| 7197 store_klass(top, t1); | |
| 7198 | |
|
2100
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|
7199 movptr(t1, top); |
|
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diff
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|
7200 subptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); |
|
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2014
diff
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|
7201 incr_allocated_bytes(thread_reg, t1, 0); |
|
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phh
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2014
diff
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|
7202 |
| 304 | 7203 // refill the tlab with an eden allocation |
| 7204 bind(do_refill); | |
| 7205 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); | |
| 7206 shlptr(t1, LogHeapWordSize); | |
|
2100
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|
7207 // allocate new tlab, address returned in top |
| 304 | 7208 eden_allocate(top, t1, 0, t2, slow_case); |
| 7209 | |
| 7210 // Check that t1 was preserved in eden_allocate. | |
| 7211 #ifdef ASSERT | |
| 7212 if (UseTLAB) { | |
| 7213 Label ok; | |
| 7214 Register tsize = rsi; | |
| 7215 assert_different_registers(tsize, thread_reg, t1); | |
| 7216 push(tsize); | |
| 7217 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); | |
| 7218 shlptr(tsize, LogHeapWordSize); | |
| 7219 cmpptr(t1, tsize); | |
| 7220 jcc(Assembler::equal, ok); | |
| 7221 stop("assert(t1 != tlab size)"); | |
| 7222 should_not_reach_here(); | |
| 7223 | |
| 7224 bind(ok); | |
| 7225 pop(tsize); | |
| 7226 } | |
| 7227 #endif | |
| 7228 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top); | |
| 7229 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top); | |
| 7230 addptr(top, t1); | |
| 7231 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes()); | |
| 7232 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top); | |
| 7233 verify_tlab(); | |
| 7234 jmp(retry); | |
|
2100
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|
7235 |
|
b1a2afa37ec4
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diff
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|
7236 return thread_reg; // for use by caller |
|
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|
7237 } |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
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2014
diff
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|
7238 |
|
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7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
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diff
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|
7239 void MacroAssembler::incr_allocated_bytes(Register thread, |
|
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2014
diff
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|
7240 Register var_size_in_bytes, |
|
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2014
diff
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|
7241 int con_size_in_bytes, |
|
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2014
diff
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|
7242 Register t1) { |
|
b1a2afa37ec4
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diff
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|
7243 #ifdef _LP64 |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
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2014
diff
changeset
|
7244 if (var_size_in_bytes->is_valid()) { |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
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|
7245 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes); |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
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|
7246 } else { |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
7247 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes); |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
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|
7248 } |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
7249 #else |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
7250 if (!thread->is_valid()) { |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
7251 assert(t1->is_valid(), "need temp reg"); |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
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|
7252 thread = t1; |
|
b1a2afa37ec4
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phh
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diff
changeset
|
7253 get_thread(thread); |
|
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7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
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2014
diff
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|
7254 } |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
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2014
diff
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|
7255 |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
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2014
diff
changeset
|
7256 if (var_size_in_bytes->is_valid()) { |
|
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parents:
2014
diff
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|
7257 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes); |
|
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diff
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|
7258 } else { |
|
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2014
diff
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|
7259 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes); |
|
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7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
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diff
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|
7260 } |
|
b1a2afa37ec4
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2014
diff
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|
7261 adcl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())+4), 0); |
|
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|
7262 #endif |
| 304 | 7263 } |
| 7264 | |
| 7265 static const double pi_4 = 0.7853981633974483; | |
| 7266 | |
| 7267 void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) { | |
| 7268 // A hand-coded argument reduction for values in fabs(pi/4, pi/2) | |
| 7269 // was attempted in this code; unfortunately it appears that the | |
| 7270 // switch to 80-bit precision and back causes this to be | |
| 7271 // unprofitable compared with simply performing a runtime call if | |
| 7272 // the argument is out of the (-pi/4, pi/4) range. | |
| 7273 | |
| 7274 Register tmp = noreg; | |
| 7275 if (!VM_Version::supports_cmov()) { | |
| 7276 // fcmp needs a temporary so preserve rbx, | |
| 7277 tmp = rbx; | |
| 7278 push(tmp); | |
| 7279 } | |
| 7280 | |
| 7281 Label slow_case, done; | |
| 7282 | |
|
520
52a431267315
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coleenp
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512
diff
changeset
|
7283 ExternalAddress pi4_adr = (address)&pi_4; |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
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512
diff
changeset
|
7284 if (reachable(pi4_adr)) { |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
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512
diff
changeset
|
7285 // x ?<= pi/4 |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
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512
diff
changeset
|
7286 fld_d(pi4_adr); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
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512
diff
changeset
|
7287 fld_s(1); // Stack: X PI/4 X |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7288 fabs(); // Stack: |X| PI/4 X |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
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512
diff
changeset
|
7289 fcmp(tmp); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7290 jcc(Assembler::above, slow_case); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7291 |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
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512
diff
changeset
|
7292 // fastest case: -pi/4 <= x <= pi/4 |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7293 switch(trig) { |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7294 case 's': |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7295 fsin(); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7296 break; |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7297 case 'c': |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7298 fcos(); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7299 break; |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7300 case 't': |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7301 ftan(); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7302 break; |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7303 default: |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7304 assert(false, "bad intrinsic"); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7305 break; |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7306 } |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7307 jmp(done); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7308 } |
| 304 | 7309 |
| 7310 // slow case: runtime call | |
| 7311 bind(slow_case); | |
| 7312 // Preserve registers across runtime call | |
| 7313 pusha(); | |
| 7314 int incoming_argument_and_return_value_offset = -1; | |
| 7315 if (num_fpu_regs_in_use > 1) { | |
| 7316 // Must preserve all other FPU regs (could alternatively convert | |
| 7317 // SharedRuntime::dsin and dcos into assembly routines known not to trash | |
| 7318 // FPU state, but can not trust C compiler) | |
| 7319 NEEDS_CLEANUP; | |
| 7320 // NOTE that in this case we also push the incoming argument to | |
| 7321 // the stack and restore it later; we also use this stack slot to | |
| 7322 // hold the return value from dsin or dcos. | |
| 7323 for (int i = 0; i < num_fpu_regs_in_use; i++) { | |
| 7324 subptr(rsp, sizeof(jdouble)); | |
| 7325 fstp_d(Address(rsp, 0)); | |
| 7326 } | |
| 7327 incoming_argument_and_return_value_offset = sizeof(jdouble)*(num_fpu_regs_in_use-1); | |
| 7328 fld_d(Address(rsp, incoming_argument_and_return_value_offset)); | |
| 7329 } | |
| 7330 subptr(rsp, sizeof(jdouble)); | |
| 7331 fstp_d(Address(rsp, 0)); | |
| 7332 #ifdef _LP64 | |
| 7333 movdbl(xmm0, Address(rsp, 0)); | |
| 7334 #endif // _LP64 | |
| 7335 | |
| 7336 // NOTE: we must not use call_VM_leaf here because that requires a | |
| 7337 // complete interpreter frame in debug mode -- same bug as 4387334 | |
| 7338 // MacroAssembler::call_VM_leaf_base is perfectly safe and will | |
| 7339 // do proper 64bit abi | |
| 7340 | |
| 7341 NEEDS_CLEANUP; | |
| 7342 // Need to add stack banging before this runtime call if it needs to | |
| 7343 // be taken; however, there is no generic stack banging routine at | |
| 7344 // the MacroAssembler level | |
| 7345 switch(trig) { | |
| 7346 case 's': | |
| 7347 { | |
| 7348 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), 0); | |
| 7349 } | |
| 7350 break; | |
| 7351 case 'c': | |
| 7352 { | |
| 7353 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), 0); | |
| 7354 } | |
| 7355 break; | |
| 7356 case 't': | |
| 7357 { | |
| 7358 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dtan), 0); | |
| 7359 } | |
| 7360 break; | |
| 7361 default: | |
| 7362 assert(false, "bad intrinsic"); | |
| 7363 break; | |
| 7364 } | |
| 7365 #ifdef _LP64 | |
| 7366 movsd(Address(rsp, 0), xmm0); | |
| 7367 fld_d(Address(rsp, 0)); | |
| 7368 #endif // _LP64 | |
| 7369 addptr(rsp, sizeof(jdouble)); | |
| 7370 if (num_fpu_regs_in_use > 1) { | |
| 7371 // Must save return value to stack and then restore entire FPU stack | |
| 7372 fstp_d(Address(rsp, incoming_argument_and_return_value_offset)); | |
| 7373 for (int i = 0; i < num_fpu_regs_in_use; i++) { | |
| 7374 fld_d(Address(rsp, 0)); | |
| 7375 addptr(rsp, sizeof(jdouble)); | |
| 7376 } | |
| 7377 } | |
| 7378 popa(); | |
| 7379 | |
| 7380 // Come here with result in F-TOS | |
| 7381 bind(done); | |
| 7382 | |
| 7383 if (tmp != noreg) { | |
| 7384 pop(tmp); | |
| 7385 } | |
| 7386 } | |
| 7387 | |
| 7388 | |
|
623
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7389 // Look up the method for a megamorphic invokeinterface call. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7390 // The target method is determined by <intf_klass, itable_index>. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7391 // The receiver klass is in recv_klass. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7392 // On success, the result will be in method_result, and execution falls through. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7393 // On failure, execution transfers to the given label. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7394 void MacroAssembler::lookup_interface_method(Register recv_klass, |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7395 Register intf_klass, |
|
665
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
647
diff
changeset
|
7396 RegisterOrConstant itable_index, |
|
623
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7397 Register method_result, |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7398 Register scan_temp, |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7399 Label& L_no_such_interface) { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7400 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7401 assert(itable_index.is_constant() || itable_index.as_register() == method_result, |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7402 "caller must use same register for non-constant itable index as for method"); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7403 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7404 // Compute start of first itableOffsetEntry (which is at the end of the vtable) |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7405 int vtable_base = instanceKlass::vtable_start_offset() * wordSize; |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7406 int itentry_off = itableMethodEntry::method_offset_in_bytes(); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7407 int scan_step = itableOffsetEntry::size() * wordSize; |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7408 int vte_size = vtableEntry::size() * wordSize; |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7409 Address::ScaleFactor times_vte_scale = Address::times_ptr; |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7410 assert(vte_size == wordSize, "else adjust times_vte_scale"); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7411 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7412 movl(scan_temp, Address(recv_klass, instanceKlass::vtable_length_offset() * wordSize)); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7413 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7414 // %%% Could store the aligned, prescaled offset in the klassoop. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7415 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base)); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7416 if (HeapWordsPerLong > 1) { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7417 // Round up to align_object_offset boundary |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7418 // see code for instanceKlass::start_of_itable! |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7419 round_to(scan_temp, BytesPerLong); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7420 } |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7421 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7422 // Adjust recv_klass by scaled itable_index, so we can free itable_index. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7423 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below"); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7424 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off)); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7425 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7426 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7427 // if (scan->interface() == intf) { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7428 // result = (klass + scan->offset() + itable_index); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7429 // } |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7430 // } |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7431 Label search, found_method; |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7432 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7433 for (int peel = 1; peel >= 0; peel--) { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7434 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes())); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7435 cmpptr(intf_klass, method_result); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7436 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7437 if (peel) { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7438 jccb(Assembler::equal, found_method); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7439 } else { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7440 jccb(Assembler::notEqual, search); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7441 // (invert the test to fall through to found_method...) |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7442 } |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7443 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7444 if (!peel) break; |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7445 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7446 bind(search); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7447 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7448 // Check that the previous entry is non-null. A null entry means that |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7449 // the receiver class doesn't implement the interface, and wasn't the |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7450 // same as when the caller was compiled. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7451 testptr(method_result, method_result); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7452 jcc(Assembler::zero, L_no_such_interface); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7453 addptr(scan_temp, scan_step); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7454 } |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7455 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7456 bind(found_method); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7457 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7458 // Got a hit. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7459 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes())); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7460 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1)); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7461 } |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7462 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7463 |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7464 void MacroAssembler::check_klass_subtype(Register sub_klass, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7465 Register super_klass, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7466 Register temp_reg, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7467 Label& L_success) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7468 Label L_failure; |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7469 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7470 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7471 bind(L_failure); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7472 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7473 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7474 |
|
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7475 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass, |
|
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7476 Register super_klass, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
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643
diff
changeset
|
7477 Register temp_reg, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7478 Label* L_success, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7479 Label* L_failure, |
|
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643
diff
changeset
|
7480 Label* L_slow_path, |
|
665
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6814659: separable cleanups and subroutines for 6655638
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diff
changeset
|
7481 RegisterOrConstant super_check_offset) { |
|
644
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7482 assert_different_registers(sub_klass, super_klass, temp_reg); |
|
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
7483 bool must_load_sco = (super_check_offset.constant_or_zero() == -1); |
|
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
7484 if (super_check_offset.is_register()) { |
|
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643
diff
changeset
|
7485 assert_different_registers(sub_klass, super_klass, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7486 super_check_offset.as_register()); |
|
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
7487 } else if (must_load_sco) { |
|
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643
diff
changeset
|
7488 assert(temp_reg != noreg, "supply either a temp or a register offset"); |
|
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diff
changeset
|
7489 } |
|
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643
diff
changeset
|
7490 |
|
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643
diff
changeset
|
7491 Label L_fallthrough; |
|
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7492 int label_nulls = 0; |
|
c517646eef23
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643
diff
changeset
|
7493 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } |
|
c517646eef23
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643
diff
changeset
|
7494 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } |
|
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643
diff
changeset
|
7495 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; } |
|
c517646eef23
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643
diff
changeset
|
7496 assert(label_nulls <= 1, "at most one NULL in the batch"); |
|
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643
diff
changeset
|
7497 |
|
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7498 int sc_offset = (klassOopDesc::header_size() * HeapWordSize + |
|
c517646eef23
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643
diff
changeset
|
7499 Klass::secondary_super_cache_offset_in_bytes()); |
|
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
7500 int sco_offset = (klassOopDesc::header_size() * HeapWordSize + |
|
c517646eef23
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diff
changeset
|
7501 Klass::super_check_offset_offset_in_bytes()); |
|
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diff
changeset
|
7502 Address super_check_offset_addr(super_klass, sco_offset); |
|
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643
diff
changeset
|
7503 |
|
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
7504 // Hacked jcc, which "knows" that L_fallthrough, at least, is in |
|
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643
diff
changeset
|
7505 // range of a jccb. If this routine grows larger, reconsider at |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7506 // least some of these. |
|
c517646eef23
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643
diff
changeset
|
7507 #define local_jcc(assembler_cond, label) \ |
|
c517646eef23
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parents:
643
diff
changeset
|
7508 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \ |
|
c517646eef23
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643
diff
changeset
|
7509 else jcc( assembler_cond, label) /*omit semi*/ |
|
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643
diff
changeset
|
7510 |
|
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7511 // Hacked jmp, which may only be used just before L_fallthrough. |
|
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parents:
643
diff
changeset
|
7512 #define final_jmp(label) \ |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7513 if (&(label) == &L_fallthrough) { /*do nothing*/ } \ |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7514 else jmp(label) /*omit semi*/ |
|
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7515 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7516 // If the pointers are equal, we are done (e.g., String[] elements). |
|
c517646eef23
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643
diff
changeset
|
7517 // This self-check enables sharing of secondary supertype arrays among |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7518 // non-primary types such as array-of-interface. Otherwise, each such |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7519 // type would need its own customized SSA. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7520 // We move this check to the front of the fast path because many |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7521 // type checks are in fact trivially successful in this manner, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7522 // so we get a nicely predicted branch right at the start of the check. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7523 cmpptr(sub_klass, super_klass); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7524 local_jcc(Assembler::equal, *L_success); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7525 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7526 // Check the supertype display: |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7527 if (must_load_sco) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7528 // Positive movl does right thing on LP64. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7529 movl(temp_reg, super_check_offset_addr); |
|
665
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
647
diff
changeset
|
7530 super_check_offset = RegisterOrConstant(temp_reg); |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7531 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7532 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7533 cmpptr(super_klass, super_check_addr); // load displayed supertype |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7534 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7535 // This check has worked decisively for primary supers. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7536 // Secondary supers are sought in the super_cache ('super_cache_addr'). |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7537 // (Secondary supers are interfaces and very deeply nested subtypes.) |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7538 // This works in the same check above because of a tricky aliasing |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7539 // between the super_cache and the primary super display elements. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7540 // (The 'super_check_addr' can address either, as the case requires.) |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7541 // Note that the cache is updated below if it does not help us find |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7542 // what we need immediately. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7543 // So if it was a primary super, we can just fail immediately. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7544 // Otherwise, it's the slow path for us (no success at this point). |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7545 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7546 if (super_check_offset.is_register()) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7547 local_jcc(Assembler::equal, *L_success); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7548 cmpl(super_check_offset.as_register(), sc_offset); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7549 if (L_failure == &L_fallthrough) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7550 local_jcc(Assembler::equal, *L_slow_path); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7551 } else { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7552 local_jcc(Assembler::notEqual, *L_failure); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7553 final_jmp(*L_slow_path); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7554 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7555 } else if (super_check_offset.as_constant() == sc_offset) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7556 // Need a slow path; fast failure is impossible. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7557 if (L_slow_path == &L_fallthrough) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7558 local_jcc(Assembler::equal, *L_success); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7559 } else { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7560 local_jcc(Assembler::notEqual, *L_slow_path); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7561 final_jmp(*L_success); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7562 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7563 } else { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7564 // No slow path; it's a fast decision. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7565 if (L_failure == &L_fallthrough) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7566 local_jcc(Assembler::equal, *L_success); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7567 } else { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7568 local_jcc(Assembler::notEqual, *L_failure); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7569 final_jmp(*L_success); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7570 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7571 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7572 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7573 bind(L_fallthrough); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7574 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7575 #undef local_jcc |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7576 #undef final_jmp |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7577 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7578 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7579 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7580 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7581 Register super_klass, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7582 Register temp_reg, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7583 Register temp2_reg, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7584 Label* L_success, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7585 Label* L_failure, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7586 bool set_cond_codes) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7587 assert_different_registers(sub_klass, super_klass, temp_reg); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7588 if (temp2_reg != noreg) |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7589 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7590 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg) |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
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643
diff
changeset
|
7591 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7592 Label L_fallthrough; |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
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643
diff
changeset
|
7593 int label_nulls = 0; |
|
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7594 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7595 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7596 assert(label_nulls <= 1, "at most one NULL in the batch"); |
|
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jrose
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643
diff
changeset
|
7597 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7598 // a couple of useful fields in sub_klass: |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7599 int ss_offset = (klassOopDesc::header_size() * HeapWordSize + |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7600 Klass::secondary_supers_offset_in_bytes()); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7601 int sc_offset = (klassOopDesc::header_size() * HeapWordSize + |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7602 Klass::secondary_super_cache_offset_in_bytes()); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7603 Address secondary_supers_addr(sub_klass, ss_offset); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7604 Address super_cache_addr( sub_klass, sc_offset); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
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643
diff
changeset
|
7605 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7606 // Do a linear scan of the secondary super-klass chain. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7607 // This code is rarely used, so simplicity is a virtue here. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7608 // The repne_scan instruction uses fixed registers, which we must spill. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7609 // Don't worry too much about pre-existing connections with the input regs. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7610 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7611 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super) |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7612 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter) |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7613 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7614 // Get super_klass value into rax (even if it was in rdi or rcx). |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
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643
diff
changeset
|
7615 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false; |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
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643
diff
changeset
|
7616 if (super_klass != rax || UseCompressedOops) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7617 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7618 mov(rax, super_klass); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7619 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7620 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7621 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7622 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7623 #ifndef PRODUCT |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7624 int* pst_counter = &SharedRuntime::_partial_subtype_ctr; |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7625 ExternalAddress pst_counter_addr((address) pst_counter); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7626 NOT_LP64( incrementl(pst_counter_addr) ); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7627 LP64_ONLY( lea(rcx, pst_counter_addr) ); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7628 LP64_ONLY( incrementl(Address(rcx, 0)) ); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7629 #endif //PRODUCT |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7630 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7631 // We will consult the secondary-super array. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7632 movptr(rdi, secondary_supers_addr); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7633 // Load the array length. (Positive movl does right thing on LP64.) |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7634 movl(rcx, Address(rdi, arrayOopDesc::length_offset_in_bytes())); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7635 // Skip to start of data. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7636 addptr(rdi, arrayOopDesc::base_offset_in_bytes(T_OBJECT)); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7637 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7638 // Scan RCX words at [RDI] for an occurrence of RAX. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7639 // Set NZ/Z based on last compare. |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
7640 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
7641 // not change flags (only scas instruction which is repeated sets flags). |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
7642 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found. |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7643 #ifdef _LP64 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7644 // This part is tricky, as values in supers array could be 32 or 64 bit wide |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7645 // and we store values in objArrays always encoded, thus we need to encode |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7646 // the value of rax before repne. Note that rax is dead after the repne. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7647 if (UseCompressedOops) { |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
7648 encode_heap_oop_not_null(rax); // Changes flags. |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7649 // The superclass is never null; it would be a basic system error if a null |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7650 // pointer were to sneak in here. Note that we have already loaded the |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7651 // Klass::super_check_offset from the super_klass in the fast path, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7652 // so if there is a null in that register, we are already in the afterlife. |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
7653 testl(rax,rax); // Set Z = 0 |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7654 repne_scanl(); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7655 } else |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7656 #endif // _LP64 |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
7657 { |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
7658 testptr(rax,rax); // Set Z = 0 |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7659 repne_scan(); |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
7660 } |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7661 // Unspill the temp. registers: |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7662 if (pushed_rdi) pop(rdi); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7663 if (pushed_rcx) pop(rcx); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7664 if (pushed_rax) pop(rax); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7665 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7666 if (set_cond_codes) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7667 // Special hack for the AD files: rdi is guaranteed non-zero. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7668 assert(!pushed_rdi, "rdi must be left non-NULL"); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7669 // Also, the condition codes are properly set Z/NZ on succeed/failure. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7670 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7671 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7672 if (L_failure == &L_fallthrough) |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7673 jccb(Assembler::notEqual, *L_failure); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7674 else jcc(Assembler::notEqual, *L_failure); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7675 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7676 // Success. Cache the super we found and proceed in triumph. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7677 movptr(super_cache_addr, super_klass); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7678 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7679 if (L_success != &L_fallthrough) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7680 jmp(*L_success); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7681 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7682 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7683 #undef IS_A_TEMP |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7684 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7685 bind(L_fallthrough); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7686 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7687 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7688 |
| 304 | 7689 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) { |
| 7690 ucomisd(dst, as_Address(src)); | |
| 7691 } | |
| 7692 | |
| 7693 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) { | |
| 7694 ucomiss(dst, as_Address(src)); | |
| 7695 } | |
| 7696 | |
| 7697 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) { | |
| 7698 if (reachable(src)) { | |
| 7699 xorpd(dst, as_Address(src)); | |
| 7700 } else { | |
| 7701 lea(rscratch1, src); | |
| 7702 xorpd(dst, Address(rscratch1, 0)); | |
| 7703 } | |
| 7704 } | |
| 7705 | |
| 7706 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) { | |
| 7707 if (reachable(src)) { | |
| 7708 xorps(dst, as_Address(src)); | |
| 7709 } else { | |
| 7710 lea(rscratch1, src); | |
| 7711 xorps(dst, Address(rscratch1, 0)); | |
| 7712 } | |
| 7713 } | |
| 7714 | |
| 0 | 7715 void MacroAssembler::verify_oop(Register reg, const char* s) { |
| 7716 if (!VerifyOops) return; | |
| 304 | 7717 |
| 0 | 7718 // Pass register number to verify_oop_subroutine |
| 7719 char* b = new char[strlen(s) + 50]; | |
| 7720 sprintf(b, "verify_oop: %s: %s", reg->name(), s); | |
| 1583 | 7721 #ifdef _LP64 |
| 7722 push(rscratch1); // save r10, trashed by movptr() | |
| 7723 #endif | |
| 304 | 7724 push(rax); // save rax, |
| 7725 push(reg); // pass register argument | |
| 0 | 7726 ExternalAddress buffer((address) b); |
| 304 | 7727 // avoid using pushptr, as it modifies scratch registers |
| 7728 // and our contract is not to modify anything | |
| 7729 movptr(rax, buffer.addr()); | |
| 7730 push(rax); | |
| 0 | 7731 // call indirectly to solve generation ordering problem |
| 7732 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); | |
| 7733 call(rax); | |
| 1583 | 7734 // Caller pops the arguments (oop, message) and restores rax, r10 |
| 0 | 7735 } |
| 7736 | |
| 7737 | |
|
665
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
647
diff
changeset
|
7738 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr, |
|
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
647
diff
changeset
|
7739 Register tmp, |
|
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
647
diff
changeset
|
7740 int offset) { |
|
622
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
7741 intptr_t value = *delayed_value_addr; |
|
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
7742 if (value != 0) |
|
665
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
647
diff
changeset
|
7743 return RegisterOrConstant(value + offset); |
|
622
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
7744 |
|
56aae7be60d4
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7745 // load indirectly to solve generation ordering problem |
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7746 movptr(tmp, ExternalAddress((address) delayed_value_addr)); |
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7747 |
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7748 #ifdef ASSERT |
|
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7749 { Label L; |
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7750 testptr(tmp, tmp); |
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7751 if (WizardMode) { |
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7752 jcc(Assembler::notZero, L); |
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7753 char* buf = new char[40]; |
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7754 sprintf(buf, "DelayedValue="INTPTR_FORMAT, delayed_value_addr[1]); |
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7755 stop(buf); |
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7756 } else { |
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7757 jccb(Assembler::notZero, L); |
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7758 hlt(); |
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|
7759 } |
|
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7760 bind(L); |
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7761 } |
|
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7762 #endif |
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7763 |
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7764 if (offset != 0) |
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7765 addptr(tmp, offset); |
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7766 |
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7767 return RegisterOrConstant(tmp); |
|
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7768 } |
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7769 |
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7770 |
| 710 | 7771 // registers on entry: |
| 7772 // - rax ('check' register): required MethodType | |
| 7773 // - rcx: method handle | |
| 7774 // - rdx, rsi, or ?: killable temp | |
| 7775 void MacroAssembler::check_method_handle_type(Register mtype_reg, Register mh_reg, | |
| 7776 Register temp_reg, | |
| 7777 Label& wrong_method_type) { | |
| 1846 | 7778 Address type_addr(mh_reg, delayed_value(java_dyn_MethodHandle::type_offset_in_bytes, temp_reg)); |
| 710 | 7779 // compare method type against that of the receiver |
| 1846 | 7780 if (UseCompressedOops) { |
| 7781 load_heap_oop(temp_reg, type_addr); | |
| 7782 cmpptr(mtype_reg, temp_reg); | |
| 7783 } else { | |
| 7784 cmpptr(mtype_reg, type_addr); | |
| 7785 } | |
| 710 | 7786 jcc(Assembler::notEqual, wrong_method_type); |
| 7787 } | |
| 7788 | |
| 7789 | |
| 7790 // A method handle has a "vmslots" field which gives the size of its | |
| 7791 // argument list in JVM stack slots. This field is either located directly | |
| 7792 // in every method handle, or else is indirectly accessed through the | |
| 7793 // method handle's MethodType. This macro hides the distinction. | |
| 7794 void MacroAssembler::load_method_handle_vmslots(Register vmslots_reg, Register mh_reg, | |
| 7795 Register temp_reg) { | |
| 1503 | 7796 assert_different_registers(vmslots_reg, mh_reg, temp_reg); |
| 710 | 7797 // load mh.type.form.vmslots |
| 7798 if (java_dyn_MethodHandle::vmslots_offset_in_bytes() != 0) { | |
| 7799 // hoist vmslots into every mh to avoid dependent load chain | |
| 7800 movl(vmslots_reg, Address(mh_reg, delayed_value(java_dyn_MethodHandle::vmslots_offset_in_bytes, temp_reg))); | |
| 7801 } else { | |
| 7802 Register temp2_reg = vmslots_reg; | |
| 1846 | 7803 load_heap_oop(temp2_reg, Address(mh_reg, delayed_value(java_dyn_MethodHandle::type_offset_in_bytes, temp_reg))); |
| 7804 load_heap_oop(temp2_reg, Address(temp2_reg, delayed_value(java_dyn_MethodType::form_offset_in_bytes, temp_reg))); | |
| 710 | 7805 movl(vmslots_reg, Address(temp2_reg, delayed_value(java_dyn_MethodTypeForm::vmslots_offset_in_bytes, temp_reg))); |
| 7806 } | |
| 7807 } | |
| 7808 | |
| 7809 | |
| 7810 // registers on entry: | |
| 7811 // - rcx: method handle | |
| 7812 // - rdx: killable temp (interpreted only) | |
| 7813 // - rax: killable temp (compiled only) | |
| 7814 void MacroAssembler::jump_to_method_handle_entry(Register mh_reg, Register temp_reg) { | |
| 7815 assert(mh_reg == rcx, "caller must put MH object in rcx"); | |
| 7816 assert_different_registers(mh_reg, temp_reg); | |
| 7817 | |
| 7818 // pick out the interpreted side of the handler | |
| 1846 | 7819 // NOTE: vmentry is not an oop! |
| 710 | 7820 movptr(temp_reg, Address(mh_reg, delayed_value(java_dyn_MethodHandle::vmentry_offset_in_bytes, temp_reg))); |
| 7821 | |
| 7822 // off we go... | |
| 7823 jmp(Address(temp_reg, MethodHandleEntry::from_interpreted_entry_offset_in_bytes())); | |
| 7824 | |
| 7825 // for the various stubs which take control at this point, | |
| 7826 // see MethodHandles::generate_method_handle_stub | |
| 7827 } | |
| 7828 | |
| 7829 | |
| 7830 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot, | |
| 7831 int extra_slot_offset) { | |
| 7832 // cf. TemplateTable::prepare_invoke(), if (load_receiver). | |
| 1506 | 7833 int stackElementSize = Interpreter::stackElementSize; |
| 710 | 7834 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0); |
| 7835 #ifdef ASSERT | |
| 7836 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1); | |
| 7837 assert(offset1 - offset == stackElementSize, "correct arithmetic"); | |
| 7838 #endif | |
| 7839 Register scale_reg = noreg; | |
| 7840 Address::ScaleFactor scale_factor = Address::no_scale; | |
| 7841 if (arg_slot.is_constant()) { | |
| 7842 offset += arg_slot.as_constant() * stackElementSize; | |
| 7843 } else { | |
| 7844 scale_reg = arg_slot.as_register(); | |
| 7845 scale_factor = Address::times(stackElementSize); | |
| 7846 } | |
| 7847 offset += wordSize; // return PC is on stack | |
| 7848 return Address(rsp, scale_reg, scale_factor, offset); | |
| 7849 } | |
| 7850 | |
| 7851 | |
| 0 | 7852 void MacroAssembler::verify_oop_addr(Address addr, const char* s) { |
| 7853 if (!VerifyOops) return; | |
| 304 | 7854 |
| 0 | 7855 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord); |
| 7856 // Pass register number to verify_oop_subroutine | |
| 7857 char* b = new char[strlen(s) + 50]; | |
| 7858 sprintf(b, "verify_oop_addr: %s", s); | |
| 304 | 7859 |
| 1583 | 7860 #ifdef _LP64 |
| 7861 push(rscratch1); // save r10, trashed by movptr() | |
| 7862 #endif | |
| 304 | 7863 push(rax); // save rax, |
| 0 | 7864 // addr may contain rsp so we will have to adjust it based on the push |
| 7865 // we just did | |
| 304 | 7866 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which |
| 7867 // stores rax into addr which is backwards of what was intended. | |
| 0 | 7868 if (addr.uses(rsp)) { |
| 304 | 7869 lea(rax, addr); |
| 7870 pushptr(Address(rax, BytesPerWord)); | |
| 0 | 7871 } else { |
| 304 | 7872 pushptr(addr); |
| 7873 } | |
| 7874 | |
| 0 | 7875 ExternalAddress buffer((address) b); |
| 7876 // pass msg argument | |
| 304 | 7877 // avoid using pushptr, as it modifies scratch registers |
| 7878 // and our contract is not to modify anything | |
| 7879 movptr(rax, buffer.addr()); | |
| 7880 push(rax); | |
| 7881 | |
| 0 | 7882 // call indirectly to solve generation ordering problem |
| 7883 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); | |
| 7884 call(rax); | |
| 1583 | 7885 // Caller pops the arguments (addr, message) and restores rax, r10. |
| 0 | 7886 } |
| 7887 | |
| 304 | 7888 void MacroAssembler::verify_tlab() { |
| 7889 #ifdef ASSERT | |
| 7890 if (UseTLAB && VerifyOops) { | |
| 7891 Label next, ok; | |
| 7892 Register t1 = rsi; | |
| 7893 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread); | |
| 7894 | |
| 7895 push(t1); | |
| 7896 NOT_LP64(push(thread_reg)); | |
| 7897 NOT_LP64(get_thread(thread_reg)); | |
| 7898 | |
| 7899 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); | |
| 7900 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); | |
| 7901 jcc(Assembler::aboveEqual, next); | |
| 7902 stop("assert(top >= start)"); | |
| 7903 should_not_reach_here(); | |
| 7904 | |
| 7905 bind(next); | |
| 7906 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); | |
| 7907 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); | |
| 7908 jcc(Assembler::aboveEqual, ok); | |
| 7909 stop("assert(top <= end)"); | |
| 7910 should_not_reach_here(); | |
| 7911 | |
| 7912 bind(ok); | |
| 7913 NOT_LP64(pop(thread_reg)); | |
| 7914 pop(t1); | |
| 7915 } | |
| 7916 #endif | |
| 7917 } | |
| 0 | 7918 |
| 7919 class ControlWord { | |
| 7920 public: | |
| 7921 int32_t _value; | |
| 7922 | |
| 7923 int rounding_control() const { return (_value >> 10) & 3 ; } | |
| 7924 int precision_control() const { return (_value >> 8) & 3 ; } | |
| 7925 bool precision() const { return ((_value >> 5) & 1) != 0; } | |
| 7926 bool underflow() const { return ((_value >> 4) & 1) != 0; } | |
| 7927 bool overflow() const { return ((_value >> 3) & 1) != 0; } | |
| 7928 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } | |
| 7929 bool denormalized() const { return ((_value >> 1) & 1) != 0; } | |
| 7930 bool invalid() const { return ((_value >> 0) & 1) != 0; } | |
| 7931 | |
| 7932 void print() const { | |
| 7933 // rounding control | |
| 7934 const char* rc; | |
| 7935 switch (rounding_control()) { | |
| 7936 case 0: rc = "round near"; break; | |
| 7937 case 1: rc = "round down"; break; | |
| 7938 case 2: rc = "round up "; break; | |
| 7939 case 3: rc = "chop "; break; | |
| 7940 }; | |
| 7941 // precision control | |
| 7942 const char* pc; | |
| 7943 switch (precision_control()) { | |
| 7944 case 0: pc = "24 bits "; break; | |
| 7945 case 1: pc = "reserved"; break; | |
| 7946 case 2: pc = "53 bits "; break; | |
| 7947 case 3: pc = "64 bits "; break; | |
| 7948 }; | |
| 7949 // flags | |
| 7950 char f[9]; | |
| 7951 f[0] = ' '; | |
| 7952 f[1] = ' '; | |
| 7953 f[2] = (precision ()) ? 'P' : 'p'; | |
| 7954 f[3] = (underflow ()) ? 'U' : 'u'; | |
| 7955 f[4] = (overflow ()) ? 'O' : 'o'; | |
| 7956 f[5] = (zero_divide ()) ? 'Z' : 'z'; | |
| 7957 f[6] = (denormalized()) ? 'D' : 'd'; | |
| 7958 f[7] = (invalid ()) ? 'I' : 'i'; | |
| 7959 f[8] = '\x0'; | |
| 7960 // output | |
| 7961 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc); | |
| 7962 } | |
| 7963 | |
| 7964 }; | |
| 7965 | |
| 7966 class StatusWord { | |
| 7967 public: | |
| 7968 int32_t _value; | |
| 7969 | |
| 7970 bool busy() const { return ((_value >> 15) & 1) != 0; } | |
| 7971 bool C3() const { return ((_value >> 14) & 1) != 0; } | |
| 7972 bool C2() const { return ((_value >> 10) & 1) != 0; } | |
| 7973 bool C1() const { return ((_value >> 9) & 1) != 0; } | |
| 7974 bool C0() const { return ((_value >> 8) & 1) != 0; } | |
| 7975 int top() const { return (_value >> 11) & 7 ; } | |
| 7976 bool error_status() const { return ((_value >> 7) & 1) != 0; } | |
| 7977 bool stack_fault() const { return ((_value >> 6) & 1) != 0; } | |
| 7978 bool precision() const { return ((_value >> 5) & 1) != 0; } | |
| 7979 bool underflow() const { return ((_value >> 4) & 1) != 0; } | |
| 7980 bool overflow() const { return ((_value >> 3) & 1) != 0; } | |
| 7981 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } | |
| 7982 bool denormalized() const { return ((_value >> 1) & 1) != 0; } | |
| 7983 bool invalid() const { return ((_value >> 0) & 1) != 0; } | |
| 7984 | |
| 7985 void print() const { | |
| 7986 // condition codes | |
| 7987 char c[5]; | |
| 7988 c[0] = (C3()) ? '3' : '-'; | |
| 7989 c[1] = (C2()) ? '2' : '-'; | |
| 7990 c[2] = (C1()) ? '1' : '-'; | |
| 7991 c[3] = (C0()) ? '0' : '-'; | |
| 7992 c[4] = '\x0'; | |
| 7993 // flags | |
| 7994 char f[9]; | |
| 7995 f[0] = (error_status()) ? 'E' : '-'; | |
| 7996 f[1] = (stack_fault ()) ? 'S' : '-'; | |
| 7997 f[2] = (precision ()) ? 'P' : '-'; | |
| 7998 f[3] = (underflow ()) ? 'U' : '-'; | |
| 7999 f[4] = (overflow ()) ? 'O' : '-'; | |
| 8000 f[5] = (zero_divide ()) ? 'Z' : '-'; | |
| 8001 f[6] = (denormalized()) ? 'D' : '-'; | |
| 8002 f[7] = (invalid ()) ? 'I' : '-'; | |
| 8003 f[8] = '\x0'; | |
| 8004 // output | |
| 8005 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top()); | |
| 8006 } | |
| 8007 | |
| 8008 }; | |
| 8009 | |
| 8010 class TagWord { | |
| 8011 public: | |
| 8012 int32_t _value; | |
| 8013 | |
| 8014 int tag_at(int i) const { return (_value >> (i*2)) & 3; } | |
| 8015 | |
| 8016 void print() const { | |
| 8017 printf("%04x", _value & 0xFFFF); | |
| 8018 } | |
| 8019 | |
| 8020 }; | |
| 8021 | |
| 8022 class FPU_Register { | |
| 8023 public: | |
| 8024 int32_t _m0; | |
| 8025 int32_t _m1; | |
| 8026 int16_t _ex; | |
| 8027 | |
| 8028 bool is_indefinite() const { | |
| 8029 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0; | |
| 8030 } | |
| 8031 | |
| 8032 void print() const { | |
| 8033 char sign = (_ex < 0) ? '-' : '+'; | |
| 8034 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " "; | |
| 8035 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind); | |
| 8036 }; | |
| 8037 | |
| 8038 }; | |
| 8039 | |
| 8040 class FPU_State { | |
| 8041 public: | |
| 8042 enum { | |
| 8043 register_size = 10, | |
| 8044 number_of_registers = 8, | |
| 8045 register_mask = 7 | |
| 8046 }; | |
| 8047 | |
| 8048 ControlWord _control_word; | |
| 8049 StatusWord _status_word; | |
| 8050 TagWord _tag_word; | |
| 8051 int32_t _error_offset; | |
| 8052 int32_t _error_selector; | |
| 8053 int32_t _data_offset; | |
| 8054 int32_t _data_selector; | |
| 8055 int8_t _register[register_size * number_of_registers]; | |
| 8056 | |
| 8057 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); } | |
| 8058 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; } | |
| 8059 | |
| 8060 const char* tag_as_string(int tag) const { | |
| 8061 switch (tag) { | |
| 8062 case 0: return "valid"; | |
| 8063 case 1: return "zero"; | |
| 8064 case 2: return "special"; | |
| 8065 case 3: return "empty"; | |
| 8066 } | |
|
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|
8067 ShouldNotReachHere(); |
| 0 | 8068 return NULL; |
| 8069 } | |
| 8070 | |
| 8071 void print() const { | |
| 8072 // print computation registers | |
| 8073 { int t = _status_word.top(); | |
| 8074 for (int i = 0; i < number_of_registers; i++) { | |
| 8075 int j = (i - t) & register_mask; | |
| 8076 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j); | |
| 8077 st(j)->print(); | |
| 8078 printf(" %s\n", tag_as_string(_tag_word.tag_at(i))); | |
| 8079 } | |
| 8080 } | |
| 8081 printf("\n"); | |
| 8082 // print control registers | |
| 8083 printf("ctrl = "); _control_word.print(); printf("\n"); | |
| 8084 printf("stat = "); _status_word .print(); printf("\n"); | |
| 8085 printf("tags = "); _tag_word .print(); printf("\n"); | |
| 8086 } | |
| 8087 | |
| 8088 }; | |
| 8089 | |
| 8090 class Flag_Register { | |
| 8091 public: | |
| 8092 int32_t _value; | |
| 8093 | |
| 8094 bool overflow() const { return ((_value >> 11) & 1) != 0; } | |
| 8095 bool direction() const { return ((_value >> 10) & 1) != 0; } | |
| 8096 bool sign() const { return ((_value >> 7) & 1) != 0; } | |
| 8097 bool zero() const { return ((_value >> 6) & 1) != 0; } | |
| 8098 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; } | |
| 8099 bool parity() const { return ((_value >> 2) & 1) != 0; } | |
| 8100 bool carry() const { return ((_value >> 0) & 1) != 0; } | |
| 8101 | |
| 8102 void print() const { | |
| 8103 // flags | |
| 8104 char f[8]; | |
| 8105 f[0] = (overflow ()) ? 'O' : '-'; | |
| 8106 f[1] = (direction ()) ? 'D' : '-'; | |
| 8107 f[2] = (sign ()) ? 'S' : '-'; | |
| 8108 f[3] = (zero ()) ? 'Z' : '-'; | |
| 8109 f[4] = (auxiliary_carry()) ? 'A' : '-'; | |
| 8110 f[5] = (parity ()) ? 'P' : '-'; | |
| 8111 f[6] = (carry ()) ? 'C' : '-'; | |
| 8112 f[7] = '\x0'; | |
| 8113 // output | |
| 8114 printf("%08x flags = %s", _value, f); | |
| 8115 } | |
| 8116 | |
| 8117 }; | |
| 8118 | |
| 8119 class IU_Register { | |
| 8120 public: | |
| 8121 int32_t _value; | |
| 8122 | |
| 8123 void print() const { | |
| 8124 printf("%08x %11d", _value, _value); | |
| 8125 } | |
| 8126 | |
| 8127 }; | |
| 8128 | |
| 8129 class IU_State { | |
| 8130 public: | |
| 8131 Flag_Register _eflags; | |
| 8132 IU_Register _rdi; | |
| 8133 IU_Register _rsi; | |
| 8134 IU_Register _rbp; | |
| 8135 IU_Register _rsp; | |
| 8136 IU_Register _rbx; | |
| 8137 IU_Register _rdx; | |
| 8138 IU_Register _rcx; | |
| 8139 IU_Register _rax; | |
| 8140 | |
| 8141 void print() const { | |
| 8142 // computation registers | |
| 8143 printf("rax, = "); _rax.print(); printf("\n"); | |
| 8144 printf("rbx, = "); _rbx.print(); printf("\n"); | |
| 8145 printf("rcx = "); _rcx.print(); printf("\n"); | |
| 8146 printf("rdx = "); _rdx.print(); printf("\n"); | |
| 8147 printf("rdi = "); _rdi.print(); printf("\n"); | |
| 8148 printf("rsi = "); _rsi.print(); printf("\n"); | |
| 8149 printf("rbp, = "); _rbp.print(); printf("\n"); | |
| 8150 printf("rsp = "); _rsp.print(); printf("\n"); | |
| 8151 printf("\n"); | |
| 8152 // control registers | |
| 8153 printf("flgs = "); _eflags.print(); printf("\n"); | |
| 8154 } | |
| 8155 }; | |
| 8156 | |
| 8157 | |
| 8158 class CPU_State { | |
| 8159 public: | |
| 8160 FPU_State _fpu_state; | |
| 8161 IU_State _iu_state; | |
| 8162 | |
| 8163 void print() const { | |
| 8164 printf("--------------------------------------------------\n"); | |
| 8165 _iu_state .print(); | |
| 8166 printf("\n"); | |
| 8167 _fpu_state.print(); | |
| 8168 printf("--------------------------------------------------\n"); | |
| 8169 } | |
| 8170 | |
| 8171 }; | |
| 8172 | |
| 8173 | |
| 8174 static void _print_CPU_state(CPU_State* state) { | |
| 8175 state->print(); | |
| 8176 }; | |
| 8177 | |
| 8178 | |
| 8179 void MacroAssembler::print_CPU_state() { | |
| 8180 push_CPU_state(); | |
| 304 | 8181 push(rsp); // pass CPU state |
| 0 | 8182 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state))); |
| 304 | 8183 addptr(rsp, wordSize); // discard argument |
| 0 | 8184 pop_CPU_state(); |
| 8185 } | |
| 8186 | |
| 8187 | |
| 8188 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) { | |
| 8189 static int counter = 0; | |
| 8190 FPU_State* fs = &state->_fpu_state; | |
| 8191 counter++; | |
| 8192 // For leaf calls, only verify that the top few elements remain empty. | |
| 8193 // We only need 1 empty at the top for C2 code. | |
| 8194 if( stack_depth < 0 ) { | |
| 8195 if( fs->tag_for_st(7) != 3 ) { | |
| 8196 printf("FPR7 not empty\n"); | |
| 8197 state->print(); | |
| 8198 assert(false, "error"); | |
| 8199 return false; | |
| 8200 } | |
| 8201 return true; // All other stack states do not matter | |
| 8202 } | |
| 8203 | |
| 8204 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std, | |
| 8205 "bad FPU control word"); | |
| 8206 | |
| 8207 // compute stack depth | |
| 8208 int i = 0; | |
| 8209 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++; | |
| 8210 int d = i; | |
| 8211 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++; | |
| 8212 // verify findings | |
| 8213 if (i != FPU_State::number_of_registers) { | |
| 8214 // stack not contiguous | |
| 8215 printf("%s: stack not contiguous at ST%d\n", s, i); | |
| 8216 state->print(); | |
| 8217 assert(false, "error"); | |
| 8218 return false; | |
| 8219 } | |
| 8220 // check if computed stack depth corresponds to expected stack depth | |
| 8221 if (stack_depth < 0) { | |
| 8222 // expected stack depth is -stack_depth or less | |
| 8223 if (d > -stack_depth) { | |
| 8224 // too many elements on the stack | |
| 8225 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d); | |
| 8226 state->print(); | |
| 8227 assert(false, "error"); | |
| 8228 return false; | |
| 8229 } | |
| 8230 } else { | |
| 8231 // expected stack depth is stack_depth | |
| 8232 if (d != stack_depth) { | |
| 8233 // wrong stack depth | |
| 8234 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d); | |
| 8235 state->print(); | |
| 8236 assert(false, "error"); | |
| 8237 return false; | |
| 8238 } | |
| 8239 } | |
| 8240 // everything is cool | |
| 8241 return true; | |
| 8242 } | |
| 8243 | |
| 8244 | |
| 8245 void MacroAssembler::verify_FPU(int stack_depth, const char* s) { | |
| 8246 if (!VerifyFPU) return; | |
| 8247 push_CPU_state(); | |
| 304 | 8248 push(rsp); // pass CPU state |
| 0 | 8249 ExternalAddress msg((address) s); |
| 8250 // pass message string s | |
| 8251 pushptr(msg.addr()); | |
| 304 | 8252 push(stack_depth); // pass stack depth |
| 0 | 8253 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU))); |
| 304 | 8254 addptr(rsp, 3 * wordSize); // discard arguments |
| 0 | 8255 // check for error |
| 8256 { Label L; | |
| 8257 testl(rax, rax); | |
| 8258 jcc(Assembler::notZero, L); | |
| 8259 int3(); // break if error condition | |
| 8260 bind(L); | |
| 8261 } | |
| 8262 pop_CPU_state(); | |
| 8263 } | |
| 8264 | |
| 304 | 8265 void MacroAssembler::load_klass(Register dst, Register src) { |
| 8266 #ifdef _LP64 | |
| 8267 if (UseCompressedOops) { | |
| 8268 movl(dst, Address(src, oopDesc::klass_offset_in_bytes())); | |
| 8269 decode_heap_oop_not_null(dst); | |
| 8270 } else | |
| 8271 #endif | |
| 8272 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes())); | |
| 8273 } | |
| 8274 | |
| 8275 void MacroAssembler::load_prototype_header(Register dst, Register src) { | |
| 8276 #ifdef _LP64 | |
| 8277 if (UseCompressedOops) { | |
|
642
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|
8278 assert (Universe::heap() != NULL, "java heap should be initialized"); |
| 304 | 8279 movl(dst, Address(src, oopDesc::klass_offset_in_bytes())); |
|
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|
8280 if (Universe::narrow_oop_shift() != 0) { |
|
1571
2d127394260e
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1513
diff
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|
8281 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
|
2d127394260e
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|
8282 if (LogMinObjAlignmentInBytes == Address::times_8) { |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
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1513
diff
changeset
|
8283 movq(dst, Address(r12_heapbase, dst, Address::times_8, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); |
|
2d127394260e
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diff
changeset
|
8284 } else { |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
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1513
diff
changeset
|
8285 // OK to use shift since we don't need to preserve flags. |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
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1513
diff
changeset
|
8286 shlq(dst, LogMinObjAlignmentInBytes); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
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1513
diff
changeset
|
8287 movq(dst, Address(r12_heapbase, dst, Address::times_1, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); |
|
2d127394260e
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1513
diff
changeset
|
8288 } |
|
642
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diff
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|
8289 } else { |
|
660978a2a31a
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diff
changeset
|
8290 movq(dst, Address(dst, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); |
|
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|
8291 } |
| 304 | 8292 } else |
| 8293 #endif | |
|
642
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|
8294 { |
|
660978a2a31a
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diff
changeset
|
8295 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes())); |
|
660978a2a31a
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624
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changeset
|
8296 movptr(dst, Address(dst, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); |
|
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|
8297 } |
| 304 | 8298 } |
| 8299 | |
| 8300 void MacroAssembler::store_klass(Register dst, Register src) { | |
| 8301 #ifdef _LP64 | |
| 8302 if (UseCompressedOops) { | |
| 8303 encode_heap_oop_not_null(src); | |
| 8304 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src); | |
| 8305 } else | |
| 8306 #endif | |
| 8307 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src); | |
| 8308 } | |
| 8309 | |
| 1846 | 8310 void MacroAssembler::load_heap_oop(Register dst, Address src) { |
| 8311 #ifdef _LP64 | |
| 8312 if (UseCompressedOops) { | |
| 8313 movl(dst, src); | |
| 8314 decode_heap_oop(dst); | |
| 8315 } else | |
| 8316 #endif | |
| 8317 movptr(dst, src); | |
| 8318 } | |
| 8319 | |
| 8320 void MacroAssembler::store_heap_oop(Address dst, Register src) { | |
| 8321 #ifdef _LP64 | |
| 8322 if (UseCompressedOops) { | |
| 8323 assert(!dst.uses(src), "not enough registers"); | |
| 8324 encode_heap_oop(src); | |
| 8325 movl(dst, src); | |
| 8326 } else | |
| 8327 #endif | |
| 8328 movptr(dst, src); | |
| 8329 } | |
| 8330 | |
| 8331 // Used for storing NULLs. | |
| 8332 void MacroAssembler::store_heap_oop_null(Address dst) { | |
| 8333 #ifdef _LP64 | |
| 8334 if (UseCompressedOops) { | |
| 8335 movl(dst, (int32_t)NULL_WORD); | |
| 8336 } else { | |
| 8337 movslq(dst, (int32_t)NULL_WORD); | |
| 8338 } | |
| 8339 #else | |
| 8340 movl(dst, (int32_t)NULL_WORD); | |
| 8341 #endif | |
| 8342 } | |
| 8343 | |
| 304 | 8344 #ifdef _LP64 |
| 8345 void MacroAssembler::store_klass_gap(Register dst, Register src) { | |
| 8346 if (UseCompressedOops) { | |
| 8347 // Store to klass gap in destination | |
| 8348 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src); | |
| 8349 } | |
| 8350 } | |
| 8351 | |
|
1684
66c5dadb4d61
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diff
changeset
|
8352 #ifdef ASSERT |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
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diff
changeset
|
8353 void MacroAssembler::verify_heapbase(const char* msg) { |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
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1583
diff
changeset
|
8354 assert (UseCompressedOops, "should be compressed"); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
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diff
changeset
|
8355 assert (Universe::heap() != NULL, "java heap should be initialized"); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
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diff
changeset
|
8356 if (CheckCompressedOops) { |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8357 Label ok; |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
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1583
diff
changeset
|
8358 push(rscratch1); // cmpptr trashes rscratch1 |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
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1583
diff
changeset
|
8359 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_oop_base_addr())); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8360 jcc(Assembler::equal, ok); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
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1583
diff
changeset
|
8361 stop(msg); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8362 bind(ok); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8363 pop(rscratch1); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8364 } |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
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1583
diff
changeset
|
8365 } |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
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diff
changeset
|
8366 #endif |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
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1583
diff
changeset
|
8367 |
| 304 | 8368 // Algorithm must match oop.inline.hpp encode_heap_oop. |
| 8369 void MacroAssembler::encode_heap_oop(Register r) { | |
|
1684
66c5dadb4d61
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diff
changeset
|
8370 #ifdef ASSERT |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
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1583
diff
changeset
|
8371 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?"); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
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1583
diff
changeset
|
8372 #endif |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
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1583
diff
changeset
|
8373 verify_oop(r, "broken oop in encode_heap_oop"); |
|
642
660978a2a31a
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624
diff
changeset
|
8374 if (Universe::narrow_oop_base() == NULL) { |
|
660978a2a31a
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624
diff
changeset
|
8375 if (Universe::narrow_oop_shift() != 0) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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624
diff
changeset
|
8376 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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624
diff
changeset
|
8377 shrq(r, LogMinObjAlignmentInBytes); |
|
660978a2a31a
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diff
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|
8378 } |
|
660978a2a31a
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624
diff
changeset
|
8379 return; |
|
660978a2a31a
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diff
changeset
|
8380 } |
| 304 | 8381 testq(r, r); |
| 8382 cmovq(Assembler::equal, r, r12_heapbase); | |
| 8383 subq(r, r12_heapbase); | |
| 8384 shrq(r, LogMinObjAlignmentInBytes); | |
| 8385 } | |
| 8386 | |
| 8387 void MacroAssembler::encode_heap_oop_not_null(Register r) { | |
| 0 | 8388 #ifdef ASSERT |
|
1684
66c5dadb4d61
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diff
changeset
|
8389 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?"); |
| 304 | 8390 if (CheckCompressedOops) { |
| 0 | 8391 Label ok; |
| 304 | 8392 testq(r, r); |
| 8393 jcc(Assembler::notEqual, ok); | |
| 8394 stop("null oop passed to encode_heap_oop_not_null"); | |
| 0 | 8395 bind(ok); |
| 304 | 8396 } |
| 8397 #endif | |
| 8398 verify_oop(r, "broken oop in encode_heap_oop_not_null"); | |
|
642
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|
8399 if (Universe::narrow_oop_base() != NULL) { |
|
660978a2a31a
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changeset
|
8400 subq(r, r12_heapbase); |
|
660978a2a31a
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diff
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|
8401 } |
|
660978a2a31a
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changeset
|
8402 if (Universe::narrow_oop_shift() != 0) { |
|
660978a2a31a
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changeset
|
8403 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
|
660978a2a31a
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changeset
|
8404 shrq(r, LogMinObjAlignmentInBytes); |
|
660978a2a31a
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|
8405 } |
| 304 | 8406 } |
| 8407 | |
| 8408 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) { | |
| 8409 #ifdef ASSERT | |
|
1684
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changeset
|
8410 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?"); |
| 304 | 8411 if (CheckCompressedOops) { |
| 8412 Label ok; | |
| 8413 testq(src, src); | |
| 8414 jcc(Assembler::notEqual, ok); | |
| 8415 stop("null oop passed to encode_heap_oop_not_null2"); | |
| 8416 bind(ok); | |
| 0 | 8417 } |
| 8418 #endif | |
| 304 | 8419 verify_oop(src, "broken oop in encode_heap_oop_not_null2"); |
| 8420 if (dst != src) { | |
| 8421 movq(dst, src); | |
| 8422 } | |
|
642
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changeset
|
8423 if (Universe::narrow_oop_base() != NULL) { |
|
660978a2a31a
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changeset
|
8424 subq(dst, r12_heapbase); |
|
660978a2a31a
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diff
changeset
|
8425 } |
|
660978a2a31a
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changeset
|
8426 if (Universe::narrow_oop_shift() != 0) { |
|
660978a2a31a
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changeset
|
8427 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
|
660978a2a31a
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changeset
|
8428 shrq(dst, LogMinObjAlignmentInBytes); |
|
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changeset
|
8429 } |
| 304 | 8430 } |
| 8431 | |
| 8432 void MacroAssembler::decode_heap_oop(Register r) { | |
|
1684
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changeset
|
8433 #ifdef ASSERT |
|
66c5dadb4d61
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changeset
|
8434 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?"); |
|
66c5dadb4d61
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changeset
|
8435 #endif |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8436 if (Universe::narrow_oop_base() == NULL) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8437 if (Universe::narrow_oop_shift() != 0) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8438 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8439 shlq(r, LogMinObjAlignmentInBytes); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8440 } |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8441 } else { |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8442 Label done; |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8443 shlq(r, LogMinObjAlignmentInBytes); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8444 jccb(Assembler::equal, done); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8445 addq(r, r12_heapbase); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8446 bind(done); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8447 } |
| 304 | 8448 verify_oop(r, "broken oop in decode_heap_oop"); |
| 8449 } | |
| 8450 | |
| 8451 void MacroAssembler::decode_heap_oop_not_null(Register r) { | |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8452 // Note: it will change flags |
| 304 | 8453 assert (UseCompressedOops, "should only be used for compressed headers"); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8454 assert (Universe::heap() != NULL, "java heap should be initialized"); |
| 304 | 8455 // Cannot assert, unverified entry point counts instructions (see .ad file) |
| 8456 // vtableStubs also counts instructions in pd_code_size_limit. | |
| 8457 // Also do not verify_oop as this is called by verify_oop. | |
|
898
60fea60a6db5
6864914: SPECjvm2008 produces invalid result with zero based Compressed Oops
kvn
parents:
845
diff
changeset
|
8458 if (Universe::narrow_oop_shift() != 0) { |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8459 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8460 shlq(r, LogMinObjAlignmentInBytes); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8461 if (Universe::narrow_oop_base() != NULL) { |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8462 addq(r, r12_heapbase); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8463 } |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8464 } else { |
|
898
60fea60a6db5
6864914: SPECjvm2008 produces invalid result with zero based Compressed Oops
kvn
parents:
845
diff
changeset
|
8465 assert (Universe::narrow_oop_base() == NULL, "sanity"); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8466 } |
| 304 | 8467 } |
| 8468 | |
| 8469 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) { | |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8470 // Note: it will change flags |
| 304 | 8471 assert (UseCompressedOops, "should only be used for compressed headers"); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8472 assert (Universe::heap() != NULL, "java heap should be initialized"); |
| 304 | 8473 // Cannot assert, unverified entry point counts instructions (see .ad file) |
| 8474 // vtableStubs also counts instructions in pd_code_size_limit. | |
| 8475 // Also do not verify_oop as this is called by verify_oop. | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8476 if (Universe::narrow_oop_shift() != 0) { |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8477 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8478 if (LogMinObjAlignmentInBytes == Address::times_8) { |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8479 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0)); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8480 } else { |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8481 if (dst != src) { |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8482 movq(dst, src); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8483 } |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8484 shlq(dst, LogMinObjAlignmentInBytes); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8485 if (Universe::narrow_oop_base() != NULL) { |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8486 addq(dst, r12_heapbase); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8487 } |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8488 } |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8489 } else { |
|
898
60fea60a6db5
6864914: SPECjvm2008 produces invalid result with zero based Compressed Oops
kvn
parents:
845
diff
changeset
|
8490 assert (Universe::narrow_oop_base() == NULL, "sanity"); |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8491 if (dst != src) { |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8492 movq(dst, src); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8493 } |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8494 } |
| 304 | 8495 } |
| 8496 | |
| 8497 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) { | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8498 assert (UseCompressedOops, "should only be used for compressed headers"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8499 assert (Universe::heap() != NULL, "java heap should be initialized"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8500 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8501 int oop_index = oop_recorder()->find_index(obj); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8502 RelocationHolder rspec = oop_Relocation::spec(oop_index); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8503 mov_narrow_oop(dst, oop_index, rspec); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8504 } |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8505 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8506 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8507 assert (UseCompressedOops, "should only be used for compressed headers"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8508 assert (Universe::heap() != NULL, "java heap should be initialized"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8509 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
| 304 | 8510 int oop_index = oop_recorder()->find_index(obj); |
| 8511 RelocationHolder rspec = oop_Relocation::spec(oop_index); | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8512 mov_narrow_oop(dst, oop_index, rspec); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8513 } |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8514 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8515 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8516 assert (UseCompressedOops, "should only be used for compressed headers"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8517 assert (Universe::heap() != NULL, "java heap should be initialized"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8518 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8519 int oop_index = oop_recorder()->find_index(obj); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8520 RelocationHolder rspec = oop_Relocation::spec(oop_index); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8521 Assembler::cmp_narrow_oop(dst, oop_index, rspec); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8522 } |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8523 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8524 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8525 assert (UseCompressedOops, "should only be used for compressed headers"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8526 assert (Universe::heap() != NULL, "java heap should be initialized"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8527 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8528 int oop_index = oop_recorder()->find_index(obj); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8529 RelocationHolder rspec = oop_Relocation::spec(oop_index); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8530 Assembler::cmp_narrow_oop(dst, oop_index, rspec); |
| 304 | 8531 } |
| 8532 | |
| 8533 void MacroAssembler::reinit_heapbase() { | |
| 8534 if (UseCompressedOops) { | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8535 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_oop_base_addr())); |
| 304 | 8536 } |
| 8537 } | |
| 8538 #endif // _LP64 | |
| 0 | 8539 |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8540 // IndexOf substring. |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8541 void MacroAssembler::string_indexof(Register str1, Register str2, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8542 Register cnt1, Register cnt2, Register result, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8543 XMMRegister vec, Register tmp) { |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8544 assert(UseSSE42Intrinsics, "SSE4.2 is required"); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8545 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8546 Label RELOAD_SUBSTR, PREP_FOR_SCAN, SCAN_TO_SUBSTR, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8547 SCAN_SUBSTR, RET_NOT_FOUND, CLEANUP; |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8548 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8549 push(str1); // string addr |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8550 push(str2); // substr addr |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8551 push(cnt2); // substr count |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8552 jmpb(PREP_FOR_SCAN); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8553 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8554 // Substr count saved at sp |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8555 // Substr saved at sp+1*wordSize |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8556 // String saved at sp+2*wordSize |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8557 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8558 // Reload substr for rescan |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8559 bind(RELOAD_SUBSTR); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8560 movl(cnt2, Address(rsp, 0)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8561 movptr(str2, Address(rsp, wordSize)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8562 // We came here after the beginninig of the substring was |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8563 // matched but the rest of it was not so we need to search |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8564 // again. Start from the next element after the previous match. |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8565 subptr(str1, result); // Restore counter |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8566 shrl(str1, 1); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8567 addl(cnt1, str1); |
|
1302
2484f4d6a54e
6935535: String.indexOf() returns incorrect result on x86 with SSE4.2
kvn
parents:
1108
diff
changeset
|
8568 decrementl(cnt1); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8569 lea(str1, Address(result, 2)); // Reload string |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8570 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8571 // Load substr |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8572 bind(PREP_FOR_SCAN); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8573 movdqu(vec, Address(str2, 0)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8574 addl(cnt1, 8); // prime the loop |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8575 subptr(str1, 16); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8576 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8577 // Scan string for substr in 16-byte vectors |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8578 bind(SCAN_TO_SUBSTR); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8579 subl(cnt1, 8); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8580 addptr(str1, 16); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8581 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8582 // pcmpestri |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8583 // inputs: |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8584 // xmm - substring |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8585 // rax - substring length (elements count) |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8586 // mem - scaned string |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8587 // rdx - string length (elements count) |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8588 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts) |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8589 // outputs: |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8590 // rcx - matched index in string |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8591 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8592 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8593 pcmpestri(vec, Address(str1, 0), 0x0d); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8594 jcc(Assembler::above, SCAN_TO_SUBSTR); // CF == 0 && ZF == 0 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8595 jccb(Assembler::aboveEqual, RET_NOT_FOUND); // CF == 0 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8596 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8597 // Fallthrough: found a potential substr |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8598 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8599 // Make sure string is still long enough |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8600 subl(cnt1, tmp); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8601 cmpl(cnt1, cnt2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8602 jccb(Assembler::negative, RET_NOT_FOUND); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8603 // Compute start addr of substr |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8604 lea(str1, Address(str1, tmp, Address::times_2)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8605 movptr(result, str1); // save |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8606 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8607 // Compare potential substr |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8608 addl(cnt1, 8); // prime the loop |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8609 addl(cnt2, 8); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8610 subptr(str1, 16); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8611 subptr(str2, 16); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8612 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8613 // Scan 16-byte vectors of string and substr |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8614 bind(SCAN_SUBSTR); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8615 subl(cnt1, 8); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8616 subl(cnt2, 8); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8617 addptr(str1, 16); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8618 addptr(str2, 16); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8619 movdqu(vec, Address(str2, 0)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8620 pcmpestri(vec, Address(str1, 0), 0x0d); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8621 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8622 jcc(Assembler::positive, SCAN_SUBSTR); // SF == 0 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8623 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8624 // Compute substr offset |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8625 subptr(result, Address(rsp, 2*wordSize)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8626 shrl(result, 1); // index |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8627 jmpb(CLEANUP); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8628 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8629 bind(RET_NOT_FOUND); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8630 movl(result, -1); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8631 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8632 bind(CLEANUP); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8633 addptr(rsp, 3*wordSize); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8634 } |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8635 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8636 // Compare strings. |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8637 void MacroAssembler::string_compare(Register str1, Register str2, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8638 Register cnt1, Register cnt2, Register result, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8639 XMMRegister vec1, XMMRegister vec2) { |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8640 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL; |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8641 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8642 // Compute the minimum of the string lengths and the |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8643 // difference of the string lengths (stack). |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8644 // Do the conditional move stuff |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8645 movl(result, cnt1); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8646 subl(cnt1, cnt2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8647 push(cnt1); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8648 if (VM_Version::supports_cmov()) { |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8649 cmovl(Assembler::lessEqual, cnt2, result); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8650 } else { |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8651 Label GT_LABEL; |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8652 jccb(Assembler::greater, GT_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8653 movl(cnt2, result); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8654 bind(GT_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8655 } |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8656 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8657 // Is the minimum length zero? |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8658 testl(cnt2, cnt2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8659 jcc(Assembler::zero, LENGTH_DIFF_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8660 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8661 // Load first characters |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8662 load_unsigned_short(result, Address(str1, 0)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8663 load_unsigned_short(cnt1, Address(str2, 0)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8664 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8665 // Compare first characters |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8666 subl(result, cnt1); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8667 jcc(Assembler::notZero, POP_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8668 decrementl(cnt2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8669 jcc(Assembler::zero, LENGTH_DIFF_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8670 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8671 { |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8672 // Check after comparing first character to see if strings are equivalent |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8673 Label LSkip2; |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8674 // Check if the strings start at same location |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8675 cmpptr(str1, str2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8676 jccb(Assembler::notEqual, LSkip2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8677 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8678 // Check if the length difference is zero (from stack) |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8679 cmpl(Address(rsp, 0), 0x0); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8680 jcc(Assembler::equal, LENGTH_DIFF_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8681 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8682 // Strings might not be equivalent |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8683 bind(LSkip2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8684 } |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8685 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8686 // Advance to next character |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8687 addptr(str1, 2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8688 addptr(str2, 2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8689 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8690 if (UseSSE42Intrinsics) { |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8691 // With SSE4.2, use double quad vector compare |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8692 Label COMPARE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL; |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8693 // Setup to compare 16-byte vectors |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8694 movl(cnt1, cnt2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8695 andl(cnt2, 0xfffffff8); // cnt2 holds the vector count |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8696 andl(cnt1, 0x00000007); // cnt1 holds the tail count |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8697 testl(cnt2, cnt2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8698 jccb(Assembler::zero, COMPARE_TAIL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8699 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8700 lea(str2, Address(str2, cnt2, Address::times_2)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8701 lea(str1, Address(str1, cnt2, Address::times_2)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8702 negptr(cnt2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8703 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8704 bind(COMPARE_VECTORS); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8705 movdqu(vec1, Address(str1, cnt2, Address::times_2)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8706 movdqu(vec2, Address(str2, cnt2, Address::times_2)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8707 pxor(vec1, vec2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8708 ptest(vec1, vec1); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8709 jccb(Assembler::notZero, VECTOR_NOT_EQUAL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8710 addptr(cnt2, 8); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8711 jcc(Assembler::notZero, COMPARE_VECTORS); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8712 jmpb(COMPARE_TAIL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8713 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8714 // Mismatched characters in the vectors |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8715 bind(VECTOR_NOT_EQUAL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8716 lea(str1, Address(str1, cnt2, Address::times_2)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8717 lea(str2, Address(str2, cnt2, Address::times_2)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8718 movl(cnt1, 8); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8719 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8720 // Compare tail (< 8 chars), or rescan last vectors to |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8721 // find 1st mismatched characters |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8722 bind(COMPARE_TAIL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8723 testl(cnt1, cnt1); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8724 jccb(Assembler::zero, LENGTH_DIFF_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8725 movl(cnt2, cnt1); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8726 // Fallthru to tail compare |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8727 } |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8728 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8729 // Shift str2 and str1 to the end of the arrays, negate min |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8730 lea(str1, Address(str1, cnt2, Address::times_2, 0)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8731 lea(str2, Address(str2, cnt2, Address::times_2, 0)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8732 negptr(cnt2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8733 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8734 // Compare the rest of the characters |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8735 bind(WHILE_HEAD_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8736 load_unsigned_short(result, Address(str1, cnt2, Address::times_2, 0)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8737 load_unsigned_short(cnt1, Address(str2, cnt2, Address::times_2, 0)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8738 subl(result, cnt1); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8739 jccb(Assembler::notZero, POP_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8740 increment(cnt2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8741 jcc(Assembler::notZero, WHILE_HEAD_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8742 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8743 // Strings are equal up to min length. Return the length difference. |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8744 bind(LENGTH_DIFF_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8745 pop(result); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8746 jmpb(DONE_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8747 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8748 // Discard the stored length difference |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8749 bind(POP_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8750 addptr(rsp, wordSize); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8751 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8752 // That's it |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8753 bind(DONE_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8754 } |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8755 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8756 // Compare char[] arrays aligned to 4 bytes or substrings. |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8757 void MacroAssembler::char_arrays_equals(bool is_array_equ, Register ary1, Register ary2, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8758 Register limit, Register result, Register chr, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8759 XMMRegister vec1, XMMRegister vec2) { |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8760 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR; |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8761 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8762 int length_offset = arrayOopDesc::length_offset_in_bytes(); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8763 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8764 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8765 // Check the input args |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8766 cmpptr(ary1, ary2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8767 jcc(Assembler::equal, TRUE_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8768 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8769 if (is_array_equ) { |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8770 // Need additional checks for arrays_equals. |
| 1016 | 8771 testptr(ary1, ary1); |
| 8772 jcc(Assembler::zero, FALSE_LABEL); | |
| 8773 testptr(ary2, ary2); | |
| 8774 jcc(Assembler::zero, FALSE_LABEL); | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8775 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8776 // Check the lengths |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8777 movl(limit, Address(ary1, length_offset)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8778 cmpl(limit, Address(ary2, length_offset)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8779 jcc(Assembler::notEqual, FALSE_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8780 } |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8781 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8782 // count == 0 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8783 testl(limit, limit); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8784 jcc(Assembler::zero, TRUE_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8785 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8786 if (is_array_equ) { |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8787 // Load array address |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8788 lea(ary1, Address(ary1, base_offset)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8789 lea(ary2, Address(ary2, base_offset)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8790 } |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8791 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8792 shll(limit, 1); // byte count != 0 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8793 movl(result, limit); // copy |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8794 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8795 if (UseSSE42Intrinsics) { |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8796 // With SSE4.2, use double quad vector compare |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8797 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8798 // Compare 16-byte vectors |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8799 andl(result, 0x0000000e); // tail count (in bytes) |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8800 andl(limit, 0xfffffff0); // vector count (in bytes) |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8801 jccb(Assembler::zero, COMPARE_TAIL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8802 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8803 lea(ary1, Address(ary1, limit, Address::times_1)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8804 lea(ary2, Address(ary2, limit, Address::times_1)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8805 negptr(limit); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8806 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8807 bind(COMPARE_WIDE_VECTORS); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8808 movdqu(vec1, Address(ary1, limit, Address::times_1)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8809 movdqu(vec2, Address(ary2, limit, Address::times_1)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8810 pxor(vec1, vec2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8811 ptest(vec1, vec1); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8812 jccb(Assembler::notZero, FALSE_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8813 addptr(limit, 16); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8814 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8815 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8816 bind(COMPARE_TAIL); // limit is zero |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8817 movl(limit, result); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8818 // Fallthru to tail compare |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8819 } |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8820 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8821 // Compare 4-byte vectors |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8822 andl(limit, 0xfffffffc); // vector count (in bytes) |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8823 jccb(Assembler::zero, COMPARE_CHAR); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8824 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8825 lea(ary1, Address(ary1, limit, Address::times_1)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8826 lea(ary2, Address(ary2, limit, Address::times_1)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8827 negptr(limit); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8828 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8829 bind(COMPARE_VECTORS); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8830 movl(chr, Address(ary1, limit, Address::times_1)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8831 cmpl(chr, Address(ary2, limit, Address::times_1)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8832 jccb(Assembler::notEqual, FALSE_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8833 addptr(limit, 4); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8834 jcc(Assembler::notZero, COMPARE_VECTORS); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8835 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8836 // Compare trailing char (final 2 bytes), if any |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8837 bind(COMPARE_CHAR); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8838 testl(result, 0x2); // tail char |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8839 jccb(Assembler::zero, TRUE_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8840 load_unsigned_short(chr, Address(ary1, 0)); |
|
62001a362ce9
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8841 load_unsigned_short(limit, Address(ary2, 0)); |
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8842 cmpl(chr, limit); |
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8843 jccb(Assembler::notEqual, FALSE_LABEL); |
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8844 |
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8845 bind(TRUE_LABEL); |
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8846 movl(result, 1); // return true |
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8847 jmpb(DONE); |
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8848 |
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8849 bind(FALSE_LABEL); |
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8850 xorl(result, result); // return false |
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8851 |
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8852 // That's it |
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8853 bind(DONE); |
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8854 } |
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8855 |
| 1763 | 8856 #ifdef PRODUCT |
| 8857 #define BLOCK_COMMENT(str) /* nothing */ | |
| 8858 #else | |
| 8859 #define BLOCK_COMMENT(str) block_comment(str) | |
| 8860 #endif | |
| 8861 | |
| 8862 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") | |
| 8863 void MacroAssembler::generate_fill(BasicType t, bool aligned, | |
| 8864 Register to, Register value, Register count, | |
| 8865 Register rtmp, XMMRegister xtmp) { | |
| 8866 assert_different_registers(to, value, count, rtmp); | |
| 8867 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte; | |
| 8868 Label L_fill_2_bytes, L_fill_4_bytes; | |
| 8869 | |
| 8870 int shift = -1; | |
| 8871 switch (t) { | |
| 8872 case T_BYTE: | |
| 8873 shift = 2; | |
| 8874 break; | |
| 8875 case T_SHORT: | |
| 8876 shift = 1; | |
| 8877 break; | |
| 8878 case T_INT: | |
| 8879 shift = 0; | |
| 8880 break; | |
| 8881 default: ShouldNotReachHere(); | |
| 8882 } | |
| 8883 | |
| 8884 if (t == T_BYTE) { | |
| 8885 andl(value, 0xff); | |
| 8886 movl(rtmp, value); | |
| 8887 shll(rtmp, 8); | |
| 8888 orl(value, rtmp); | |
| 8889 } | |
| 8890 if (t == T_SHORT) { | |
| 8891 andl(value, 0xffff); | |
| 8892 } | |
| 8893 if (t == T_BYTE || t == T_SHORT) { | |
| 8894 movl(rtmp, value); | |
| 8895 shll(rtmp, 16); | |
| 8896 orl(value, rtmp); | |
| 8897 } | |
| 8898 | |
| 8899 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element | |
| 8900 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp | |
| 8901 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) { | |
| 8902 // align source address at 4 bytes address boundary | |
| 8903 if (t == T_BYTE) { | |
| 8904 // One byte misalignment happens only for byte arrays | |
| 8905 testptr(to, 1); | |
| 8906 jccb(Assembler::zero, L_skip_align1); | |
| 8907 movb(Address(to, 0), value); | |
| 8908 increment(to); | |
| 8909 decrement(count); | |
| 8910 BIND(L_skip_align1); | |
| 8911 } | |
| 8912 // Two bytes misalignment happens only for byte and short (char) arrays | |
| 8913 testptr(to, 2); | |
| 8914 jccb(Assembler::zero, L_skip_align2); | |
| 8915 movw(Address(to, 0), value); | |
| 8916 addptr(to, 2); | |
| 8917 subl(count, 1<<(shift-1)); | |
| 8918 BIND(L_skip_align2); | |
| 8919 } | |
| 8920 if (UseSSE < 2) { | |
| 8921 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; | |
| 8922 // Fill 32-byte chunks | |
| 8923 subl(count, 8 << shift); | |
| 8924 jcc(Assembler::less, L_check_fill_8_bytes); | |
| 8925 align(16); | |
| 8926 | |
| 8927 BIND(L_fill_32_bytes_loop); | |
| 8928 | |
| 8929 for (int i = 0; i < 32; i += 4) { | |
| 8930 movl(Address(to, i), value); | |
| 8931 } | |
| 8932 | |
| 8933 addptr(to, 32); | |
| 8934 subl(count, 8 << shift); | |
| 8935 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); | |
| 8936 BIND(L_check_fill_8_bytes); | |
| 8937 addl(count, 8 << shift); | |
| 8938 jccb(Assembler::zero, L_exit); | |
| 8939 jmpb(L_fill_8_bytes); | |
| 8940 | |
| 8941 // | |
| 8942 // length is too short, just fill qwords | |
| 8943 // | |
| 8944 BIND(L_fill_8_bytes_loop); | |
| 8945 movl(Address(to, 0), value); | |
| 8946 movl(Address(to, 4), value); | |
| 8947 addptr(to, 8); | |
| 8948 BIND(L_fill_8_bytes); | |
| 8949 subl(count, 1 << (shift + 1)); | |
| 8950 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); | |
| 8951 // fall through to fill 4 bytes | |
| 8952 } else { | |
| 8953 Label L_fill_32_bytes; | |
| 8954 if (!UseUnalignedLoadStores) { | |
| 8955 // align to 8 bytes, we know we are 4 byte aligned to start | |
| 8956 testptr(to, 4); | |
| 8957 jccb(Assembler::zero, L_fill_32_bytes); | |
| 8958 movl(Address(to, 0), value); | |
| 8959 addptr(to, 4); | |
| 8960 subl(count, 1<<shift); | |
| 8961 } | |
| 8962 BIND(L_fill_32_bytes); | |
| 8963 { | |
| 8964 assert( UseSSE >= 2, "supported cpu only" ); | |
| 8965 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; | |
| 8966 // Fill 32-byte chunks | |
| 8967 movdl(xtmp, value); | |
| 8968 pshufd(xtmp, xtmp, 0); | |
| 8969 | |
| 8970 subl(count, 8 << shift); | |
| 8971 jcc(Assembler::less, L_check_fill_8_bytes); | |
| 8972 align(16); | |
| 8973 | |
| 8974 BIND(L_fill_32_bytes_loop); | |
| 8975 | |
| 8976 if (UseUnalignedLoadStores) { | |
| 8977 movdqu(Address(to, 0), xtmp); | |
| 8978 movdqu(Address(to, 16), xtmp); | |
| 8979 } else { | |
| 8980 movq(Address(to, 0), xtmp); | |
| 8981 movq(Address(to, 8), xtmp); | |
| 8982 movq(Address(to, 16), xtmp); | |
| 8983 movq(Address(to, 24), xtmp); | |
| 8984 } | |
| 8985 | |
| 8986 addptr(to, 32); | |
| 8987 subl(count, 8 << shift); | |
| 8988 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); | |
| 8989 BIND(L_check_fill_8_bytes); | |
| 8990 addl(count, 8 << shift); | |
| 8991 jccb(Assembler::zero, L_exit); | |
| 8992 jmpb(L_fill_8_bytes); | |
| 8993 | |
| 8994 // | |
| 8995 // length is too short, just fill qwords | |
| 8996 // | |
| 8997 BIND(L_fill_8_bytes_loop); | |
| 8998 movq(Address(to, 0), xtmp); | |
| 8999 addptr(to, 8); | |
| 9000 BIND(L_fill_8_bytes); | |
| 9001 subl(count, 1 << (shift + 1)); | |
| 9002 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); | |
| 9003 } | |
| 9004 } | |
| 9005 // fill trailing 4 bytes | |
| 9006 BIND(L_fill_4_bytes); | |
| 9007 testl(count, 1<<shift); | |
| 9008 jccb(Assembler::zero, L_fill_2_bytes); | |
| 9009 movl(Address(to, 0), value); | |
| 9010 if (t == T_BYTE || t == T_SHORT) { | |
| 9011 addptr(to, 4); | |
| 9012 BIND(L_fill_2_bytes); | |
| 9013 // fill trailing 2 bytes | |
| 9014 testl(count, 1<<(shift-1)); | |
| 9015 jccb(Assembler::zero, L_fill_byte); | |
| 9016 movw(Address(to, 0), value); | |
| 9017 if (t == T_BYTE) { | |
| 9018 addptr(to, 2); | |
| 9019 BIND(L_fill_byte); | |
| 9020 // fill trailing byte | |
| 9021 testl(count, 1); | |
| 9022 jccb(Assembler::zero, L_exit); | |
| 9023 movb(Address(to, 0), value); | |
| 9024 } else { | |
| 9025 BIND(L_fill_byte); | |
| 9026 } | |
| 9027 } else { | |
| 9028 BIND(L_fill_2_bytes); | |
| 9029 } | |
| 9030 BIND(L_exit); | |
| 9031 } | |
| 9032 #undef BIND | |
| 9033 #undef BLOCK_COMMENT | |
| 9034 | |
| 9035 | |
| 0 | 9036 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) { |
| 9037 switch (cond) { | |
| 9038 // Note some conditions are synonyms for others | |
| 9039 case Assembler::zero: return Assembler::notZero; | |
| 9040 case Assembler::notZero: return Assembler::zero; | |
| 9041 case Assembler::less: return Assembler::greaterEqual; | |
| 9042 case Assembler::lessEqual: return Assembler::greater; | |
| 9043 case Assembler::greater: return Assembler::lessEqual; | |
| 9044 case Assembler::greaterEqual: return Assembler::less; | |
| 9045 case Assembler::below: return Assembler::aboveEqual; | |
| 9046 case Assembler::belowEqual: return Assembler::above; | |
| 9047 case Assembler::above: return Assembler::belowEqual; | |
| 9048 case Assembler::aboveEqual: return Assembler::below; | |
| 9049 case Assembler::overflow: return Assembler::noOverflow; | |
| 9050 case Assembler::noOverflow: return Assembler::overflow; | |
| 9051 case Assembler::negative: return Assembler::positive; | |
| 9052 case Assembler::positive: return Assembler::negative; | |
| 9053 case Assembler::parity: return Assembler::noParity; | |
| 9054 case Assembler::noParity: return Assembler::parity; | |
| 9055 } | |
| 9056 ShouldNotReachHere(); return Assembler::overflow; | |
| 9057 } | |
| 9058 | |
| 9059 SkipIfEqual::SkipIfEqual( | |
| 9060 MacroAssembler* masm, const bool* flag_addr, bool value) { | |
| 9061 _masm = masm; | |
| 9062 _masm->cmp8(ExternalAddress((address)flag_addr), value); | |
| 9063 _masm->jcc(Assembler::equal, _label); | |
| 9064 } | |
| 9065 | |
| 9066 SkipIfEqual::~SkipIfEqual() { | |
| 9067 _masm->bind(_label); | |
| 9068 } |