Mercurial > hg > truffle
diff src/cpu/x86/vm/assembler_x86.cpp @ 775:93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
Summary: These methods can be instrinsified by using bit scan, bit test, and population count instructions.
Reviewed-by: kvn, never
| author | twisti |
|---|---|
| date | Wed, 06 May 2009 00:27:52 -0700 |
| parents | e5b0439ef4ae |
| children | df6caf649ff7 |
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--- a/src/cpu/x86/vm/assembler_x86.cpp Tue May 05 11:02:10 2009 -0700 +++ b/src/cpu/x86/vm/assembler_x86.cpp Wed May 06 00:27:52 2009 -0700 @@ -952,6 +952,21 @@ emit_operand(dst, src); } +void Assembler::bsfl(Register dst, Register src) { + int encode = prefix_and_encode(dst->encoding(), src->encoding()); + emit_byte(0x0F); + emit_byte(0xBC); + emit_byte(0xC0 | encode); +} + +void Assembler::bsrl(Register dst, Register src) { + assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT"); + int encode = prefix_and_encode(dst->encoding(), src->encoding()); + emit_byte(0x0F); + emit_byte(0xBD); + emit_byte(0xC0 | encode); +} + void Assembler::bswapl(Register reg) { // bswap int encode = prefix_and_encode(reg->encoding()); emit_byte(0x0F); @@ -1438,6 +1453,15 @@ } } +void Assembler::lzcntl(Register dst, Register src) { + assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); + emit_byte(0xF3); + int encode = prefix_and_encode(dst->encoding(), src->encoding()); + emit_byte(0x0F); + emit_byte(0xBD); + emit_byte(0xC0 | encode); +} + // Emit mfence instruction void Assembler::mfence() { NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");) @@ -3688,6 +3712,21 @@ emit_arith(0x23, 0xC0, dst, src); } +void Assembler::bsfq(Register dst, Register src) { + int encode = prefixq_and_encode(dst->encoding(), src->encoding()); + emit_byte(0x0F); + emit_byte(0xBC); + emit_byte(0xC0 | encode); +} + +void Assembler::bsrq(Register dst, Register src) { + assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT"); + int encode = prefixq_and_encode(dst->encoding(), src->encoding()); + emit_byte(0x0F); + emit_byte(0xBD); + emit_byte(0xC0 | encode); +} + void Assembler::bswapq(Register reg) { int encode = prefixq_and_encode(reg->encoding()); emit_byte(0x0F); @@ -3941,6 +3980,15 @@ emit_data((int)imm32, rspec, narrow_oop_operand); } +void Assembler::lzcntq(Register dst, Register src) { + assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); + emit_byte(0xF3); + int encode = prefixq_and_encode(dst->encoding(), src->encoding()); + emit_byte(0x0F); + emit_byte(0xBD); + emit_byte(0xC0 | encode); +} + void Assembler::movdq(XMMRegister dst, Register src) { // table D-1 says MMX/SSE2 NOT_LP64(assert(VM_Version::supports_sse2() || VM_Version::supports_mmx(), ""));