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comparison src/cpu/x86/vm/assembler_x86.cpp @ 775:93c14e5562c4

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6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() Summary: These methods can be instrinsified by using bit scan, bit test, and population count instructions. Reviewed-by: kvn, never
author twisti
date Wed, 06 May 2009 00:27:52 -0700
parents e5b0439ef4ae
children df6caf649ff7
comparison
equal deleted inserted replaced
755:36ee9b69616e 775:93c14e5562c4
950 emit_byte(0x0F); 950 emit_byte(0x0F);
951 emit_byte(0x54); 951 emit_byte(0x54);
952 emit_operand(dst, src); 952 emit_operand(dst, src);
953 } 953 }
954 954
955 void Assembler::bsfl(Register dst, Register src) {
956 int encode = prefix_and_encode(dst->encoding(), src->encoding());
957 emit_byte(0x0F);
958 emit_byte(0xBC);
959 emit_byte(0xC0 | encode);
960 }
961
962 void Assembler::bsrl(Register dst, Register src) {
963 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT");
964 int encode = prefix_and_encode(dst->encoding(), src->encoding());
965 emit_byte(0x0F);
966 emit_byte(0xBD);
967 emit_byte(0xC0 | encode);
968 }
969
955 void Assembler::bswapl(Register reg) { // bswap 970 void Assembler::bswapl(Register reg) { // bswap
956 int encode = prefix_and_encode(reg->encoding()); 971 int encode = prefix_and_encode(reg->encoding());
957 emit_byte(0x0F); 972 emit_byte(0x0F);
958 emit_byte(0xC8 | encode); 973 emit_byte(0xC8 | encode);
959 } 974 }
1434 // Emit either nothing, a NOP, or a NOP: prefix 1449 // Emit either nothing, a NOP, or a NOP: prefix
1435 emit_byte(0x90) ; 1450 emit_byte(0x90) ;
1436 } else { 1451 } else {
1437 emit_byte(0xF0); 1452 emit_byte(0xF0);
1438 } 1453 }
1454 }
1455
1456 void Assembler::lzcntl(Register dst, Register src) {
1457 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
1458 emit_byte(0xF3);
1459 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1460 emit_byte(0x0F);
1461 emit_byte(0xBD);
1462 emit_byte(0xC0 | encode);
1439 } 1463 }
1440 1464
1441 // Emit mfence instruction 1465 // Emit mfence instruction
1442 void Assembler::mfence() { 1466 void Assembler::mfence() {
1443 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");) 1467 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
3686 void Assembler::andq(Register dst, Register src) { 3710 void Assembler::andq(Register dst, Register src) {
3687 (int) prefixq_and_encode(dst->encoding(), src->encoding()); 3711 (int) prefixq_and_encode(dst->encoding(), src->encoding());
3688 emit_arith(0x23, 0xC0, dst, src); 3712 emit_arith(0x23, 0xC0, dst, src);
3689 } 3713 }
3690 3714
3715 void Assembler::bsfq(Register dst, Register src) {
3716 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3717 emit_byte(0x0F);
3718 emit_byte(0xBC);
3719 emit_byte(0xC0 | encode);
3720 }
3721
3722 void Assembler::bsrq(Register dst, Register src) {
3723 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT");
3724 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3725 emit_byte(0x0F);
3726 emit_byte(0xBD);
3727 emit_byte(0xC0 | encode);
3728 }
3729
3691 void Assembler::bswapq(Register reg) { 3730 void Assembler::bswapq(Register reg) {
3692 int encode = prefixq_and_encode(reg->encoding()); 3731 int encode = prefixq_and_encode(reg->encoding());
3693 emit_byte(0x0F); 3732 emit_byte(0x0F);
3694 emit_byte(0xC8 | encode); 3733 emit_byte(0xC8 | encode);
3695 } 3734 }
3937 InstructionMark im(this); 3976 InstructionMark im(this);
3938 prefix(src1); 3977 prefix(src1);
3939 emit_byte(0x81); 3978 emit_byte(0x81);
3940 emit_operand(rax, src1, 4); 3979 emit_operand(rax, src1, 4);
3941 emit_data((int)imm32, rspec, narrow_oop_operand); 3980 emit_data((int)imm32, rspec, narrow_oop_operand);
3981 }
3982
3983 void Assembler::lzcntq(Register dst, Register src) {
3984 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
3985 emit_byte(0xF3);
3986 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3987 emit_byte(0x0F);
3988 emit_byte(0xBD);
3989 emit_byte(0xC0 | encode);
3942 } 3990 }
3943 3991
3944 void Assembler::movdq(XMMRegister dst, Register src) { 3992 void Assembler::movdq(XMMRegister dst, Register src) {
3945 // table D-1 says MMX/SSE2 3993 // table D-1 says MMX/SSE2
3946 NOT_LP64(assert(VM_Version::supports_sse2() || VM_Version::supports_mmx(), "")); 3994 NOT_LP64(assert(VM_Version::supports_sse2() || VM_Version::supports_mmx(), ""));