Mercurial > hg > truffle
annotate src/cpu/x86/vm/assembler_x86.cpp @ 4759:127b3692c168
7116452: Add support for AVX instructions
Summary: Added support for AVX extension to the x86 instruction set.
Reviewed-by: never
| author | kvn |
|---|---|
| date | Wed, 14 Dec 2011 14:54:38 -0800 |
| parents | 59bc0d4d9ea3 |
| children | 65149e74c706 |
| rev | line source |
|---|---|
| 0 | 1 /* |
|
2100
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
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changeset
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2 * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
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1552
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
|
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
| 0 | 22 * |
| 23 */ | |
| 24 | |
| 1972 | 25 #include "precompiled.hpp" |
| 26 #include "assembler_x86.inline.hpp" | |
| 27 #include "gc_interface/collectedHeap.inline.hpp" | |
| 28 #include "interpreter/interpreter.hpp" | |
| 29 #include "memory/cardTableModRefBS.hpp" | |
| 30 #include "memory/resourceArea.hpp" | |
| 31 #include "prims/methodHandles.hpp" | |
| 32 #include "runtime/biasedLocking.hpp" | |
| 33 #include "runtime/interfaceSupport.hpp" | |
| 34 #include "runtime/objectMonitor.hpp" | |
| 35 #include "runtime/os.hpp" | |
| 36 #include "runtime/sharedRuntime.hpp" | |
| 37 #include "runtime/stubRoutines.hpp" | |
| 38 #ifndef SERIALGC | |
| 39 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp" | |
| 40 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp" | |
| 41 #include "gc_implementation/g1/heapRegion.hpp" | |
| 42 #endif | |
| 0 | 43 |
| 44 // Implementation of AddressLiteral | |
| 45 | |
| 46 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) { | |
| 47 _is_lval = false; | |
| 48 _target = target; | |
| 49 switch (rtype) { | |
| 50 case relocInfo::oop_type: | |
| 51 // Oops are a special case. Normally they would be their own section | |
| 52 // but in cases like icBuffer they are literals in the code stream that | |
| 53 // we don't have a section for. We use none so that we get a literal address | |
| 54 // which is always patchable. | |
| 55 break; | |
| 56 case relocInfo::external_word_type: | |
| 57 _rspec = external_word_Relocation::spec(target); | |
| 58 break; | |
| 59 case relocInfo::internal_word_type: | |
| 60 _rspec = internal_word_Relocation::spec(target); | |
| 61 break; | |
| 62 case relocInfo::opt_virtual_call_type: | |
| 63 _rspec = opt_virtual_call_Relocation::spec(); | |
| 64 break; | |
| 65 case relocInfo::static_call_type: | |
| 66 _rspec = static_call_Relocation::spec(); | |
| 67 break; | |
| 68 case relocInfo::runtime_call_type: | |
| 69 _rspec = runtime_call_Relocation::spec(); | |
| 70 break; | |
| 71 case relocInfo::poll_type: | |
| 72 case relocInfo::poll_return_type: | |
| 73 _rspec = Relocation::spec_simple(rtype); | |
| 74 break; | |
| 75 case relocInfo::none: | |
| 76 break; | |
| 77 default: | |
| 78 ShouldNotReachHere(); | |
| 79 break; | |
| 80 } | |
| 81 } | |
| 82 | |
| 83 // Implementation of Address | |
| 84 | |
| 304 | 85 #ifdef _LP64 |
| 86 | |
| 0 | 87 Address Address::make_array(ArrayAddress adr) { |
| 88 // Not implementable on 64bit machines | |
| 89 // Should have been handled higher up the call chain. | |
| 90 ShouldNotReachHere(); | |
| 304 | 91 return Address(); |
| 92 } | |
| 93 | |
| 94 // exceedingly dangerous constructor | |
| 95 Address::Address(int disp, address loc, relocInfo::relocType rtype) { | |
| 96 _base = noreg; | |
| 97 _index = noreg; | |
| 98 _scale = no_scale; | |
| 99 _disp = disp; | |
| 100 switch (rtype) { | |
| 101 case relocInfo::external_word_type: | |
| 102 _rspec = external_word_Relocation::spec(loc); | |
| 103 break; | |
| 104 case relocInfo::internal_word_type: | |
| 105 _rspec = internal_word_Relocation::spec(loc); | |
| 106 break; | |
| 107 case relocInfo::runtime_call_type: | |
| 108 // HMM | |
| 109 _rspec = runtime_call_Relocation::spec(); | |
| 110 break; | |
| 111 case relocInfo::poll_type: | |
| 112 case relocInfo::poll_return_type: | |
| 113 _rspec = Relocation::spec_simple(rtype); | |
| 114 break; | |
| 115 case relocInfo::none: | |
| 116 break; | |
| 117 default: | |
| 118 ShouldNotReachHere(); | |
| 119 } | |
| 120 } | |
| 121 #else // LP64 | |
| 122 | |
| 123 Address Address::make_array(ArrayAddress adr) { | |
| 0 | 124 AddressLiteral base = adr.base(); |
| 125 Address index = adr.index(); | |
| 126 assert(index._disp == 0, "must not have disp"); // maybe it can? | |
| 127 Address array(index._base, index._index, index._scale, (intptr_t) base.target()); | |
| 128 array._rspec = base._rspec; | |
| 129 return array; | |
| 304 | 130 } |
| 0 | 131 |
| 132 // exceedingly dangerous constructor | |
| 133 Address::Address(address loc, RelocationHolder spec) { | |
| 134 _base = noreg; | |
| 135 _index = noreg; | |
| 136 _scale = no_scale; | |
| 137 _disp = (intptr_t) loc; | |
| 138 _rspec = spec; | |
| 139 } | |
| 304 | 140 |
| 0 | 141 #endif // _LP64 |
| 142 | |
| 304 | 143 |
| 144 | |
| 0 | 145 // Convert the raw encoding form into the form expected by the constructor for |
| 146 // Address. An index of 4 (rsp) corresponds to having no index, so convert | |
| 147 // that to noreg for the Address constructor. | |
| 624 | 148 Address Address::make_raw(int base, int index, int scale, int disp, bool disp_is_oop) { |
| 149 RelocationHolder rspec; | |
| 150 if (disp_is_oop) { | |
| 151 rspec = Relocation::spec_simple(relocInfo::oop_type); | |
| 152 } | |
| 0 | 153 bool valid_index = index != rsp->encoding(); |
| 154 if (valid_index) { | |
| 155 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp)); | |
| 624 | 156 madr._rspec = rspec; |
| 0 | 157 return madr; |
| 158 } else { | |
| 159 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp)); | |
| 624 | 160 madr._rspec = rspec; |
| 0 | 161 return madr; |
| 162 } | |
| 163 } | |
| 164 | |
| 165 // Implementation of Assembler | |
| 166 | |
| 167 int AbstractAssembler::code_fill_byte() { | |
| 168 return (u_char)'\xF4'; // hlt | |
| 169 } | |
| 170 | |
| 171 // make this go away someday | |
| 172 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) { | |
| 173 if (rtype == relocInfo::none) | |
| 174 emit_long(data); | |
| 175 else emit_data(data, Relocation::spec_simple(rtype), format); | |
| 176 } | |
| 177 | |
| 178 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) { | |
| 304 | 179 assert(imm_operand == 0, "default format must be immediate in this file"); |
| 0 | 180 assert(inst_mark() != NULL, "must be inside InstructionMark"); |
| 181 if (rspec.type() != relocInfo::none) { | |
| 182 #ifdef ASSERT | |
| 183 check_relocation(rspec, format); | |
| 184 #endif | |
| 185 // Do not use AbstractAssembler::relocate, which is not intended for | |
| 186 // embedded words. Instead, relocate to the enclosing instruction. | |
| 187 | |
| 188 // hack. call32 is too wide for mask so use disp32 | |
| 189 if (format == call32_operand) | |
| 190 code_section()->relocate(inst_mark(), rspec, disp32_operand); | |
| 191 else | |
| 192 code_section()->relocate(inst_mark(), rspec, format); | |
| 193 } | |
| 194 emit_long(data); | |
| 195 } | |
| 196 | |
| 304 | 197 static int encode(Register r) { |
| 198 int enc = r->encoding(); | |
| 199 if (enc >= 8) { | |
| 200 enc -= 8; | |
| 201 } | |
| 202 return enc; | |
| 203 } | |
| 204 | |
| 205 static int encode(XMMRegister r) { | |
| 206 int enc = r->encoding(); | |
| 207 if (enc >= 8) { | |
| 208 enc -= 8; | |
| 209 } | |
| 210 return enc; | |
| 211 } | |
| 0 | 212 |
| 213 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) { | |
| 214 assert(dst->has_byte_register(), "must have byte register"); | |
| 215 assert(isByte(op1) && isByte(op2), "wrong opcode"); | |
| 216 assert(isByte(imm8), "not a byte"); | |
| 217 assert((op1 & 0x01) == 0, "should be 8bit operation"); | |
| 218 emit_byte(op1); | |
| 304 | 219 emit_byte(op2 | encode(dst)); |
| 0 | 220 emit_byte(imm8); |
| 221 } | |
| 222 | |
| 223 | |
| 304 | 224 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) { |
| 0 | 225 assert(isByte(op1) && isByte(op2), "wrong opcode"); |
| 226 assert((op1 & 0x01) == 1, "should be 32bit operation"); | |
| 227 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); | |
| 228 if (is8bit(imm32)) { | |
| 229 emit_byte(op1 | 0x02); // set sign bit | |
| 304 | 230 emit_byte(op2 | encode(dst)); |
| 0 | 231 emit_byte(imm32 & 0xFF); |
| 232 } else { | |
| 233 emit_byte(op1); | |
| 304 | 234 emit_byte(op2 | encode(dst)); |
| 0 | 235 emit_long(imm32); |
| 236 } | |
| 237 } | |
| 238 | |
| 239 // immediate-to-memory forms | |
| 304 | 240 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) { |
| 0 | 241 assert((op1 & 0x01) == 1, "should be 32bit operation"); |
| 242 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); | |
| 243 if (is8bit(imm32)) { | |
| 244 emit_byte(op1 | 0x02); // set sign bit | |
| 304 | 245 emit_operand(rm, adr, 1); |
| 0 | 246 emit_byte(imm32 & 0xFF); |
| 247 } else { | |
| 248 emit_byte(op1); | |
| 304 | 249 emit_operand(rm, adr, 4); |
| 0 | 250 emit_long(imm32); |
| 251 } | |
| 252 } | |
| 253 | |
| 254 void Assembler::emit_arith(int op1, int op2, Register dst, jobject obj) { | |
| 304 | 255 LP64_ONLY(ShouldNotReachHere()); |
| 0 | 256 assert(isByte(op1) && isByte(op2), "wrong opcode"); |
| 257 assert((op1 & 0x01) == 1, "should be 32bit operation"); | |
| 258 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); | |
| 259 InstructionMark im(this); | |
| 260 emit_byte(op1); | |
| 304 | 261 emit_byte(op2 | encode(dst)); |
| 262 emit_data((intptr_t)obj, relocInfo::oop_type, 0); | |
| 0 | 263 } |
| 264 | |
| 265 | |
| 266 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) { | |
| 267 assert(isByte(op1) && isByte(op2), "wrong opcode"); | |
| 268 emit_byte(op1); | |
| 304 | 269 emit_byte(op2 | encode(dst) << 3 | encode(src)); |
| 270 } | |
| 271 | |
| 272 | |
| 273 void Assembler::emit_operand(Register reg, Register base, Register index, | |
| 274 Address::ScaleFactor scale, int disp, | |
| 275 RelocationHolder const& rspec, | |
| 276 int rip_relative_correction) { | |
| 0 | 277 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type(); |
| 304 | 278 |
| 279 // Encode the registers as needed in the fields they are used in | |
| 280 | |
| 281 int regenc = encode(reg) << 3; | |
| 282 int indexenc = index->is_valid() ? encode(index) << 3 : 0; | |
| 283 int baseenc = base->is_valid() ? encode(base) : 0; | |
| 284 | |
| 0 | 285 if (base->is_valid()) { |
| 286 if (index->is_valid()) { | |
| 287 assert(scale != Address::no_scale, "inconsistent address"); | |
| 288 // [base + index*scale + disp] | |
| 304 | 289 if (disp == 0 && rtype == relocInfo::none && |
| 290 base != rbp LP64_ONLY(&& base != r13)) { | |
| 0 | 291 // [base + index*scale] |
| 292 // [00 reg 100][ss index base] | |
| 293 assert(index != rsp, "illegal addressing mode"); | |
| 304 | 294 emit_byte(0x04 | regenc); |
| 295 emit_byte(scale << 6 | indexenc | baseenc); | |
| 0 | 296 } else if (is8bit(disp) && rtype == relocInfo::none) { |
| 297 // [base + index*scale + imm8] | |
| 298 // [01 reg 100][ss index base] imm8 | |
| 299 assert(index != rsp, "illegal addressing mode"); | |
| 304 | 300 emit_byte(0x44 | regenc); |
| 301 emit_byte(scale << 6 | indexenc | baseenc); | |
| 0 | 302 emit_byte(disp & 0xFF); |
| 303 } else { | |
| 304 | 304 // [base + index*scale + disp32] |
| 305 // [10 reg 100][ss index base] disp32 | |
| 0 | 306 assert(index != rsp, "illegal addressing mode"); |
| 304 | 307 emit_byte(0x84 | regenc); |
| 308 emit_byte(scale << 6 | indexenc | baseenc); | |
| 0 | 309 emit_data(disp, rspec, disp32_operand); |
| 310 } | |
| 304 | 311 } else if (base == rsp LP64_ONLY(|| base == r12)) { |
| 312 // [rsp + disp] | |
| 0 | 313 if (disp == 0 && rtype == relocInfo::none) { |
| 304 | 314 // [rsp] |
| 0 | 315 // [00 reg 100][00 100 100] |
| 304 | 316 emit_byte(0x04 | regenc); |
| 0 | 317 emit_byte(0x24); |
| 318 } else if (is8bit(disp) && rtype == relocInfo::none) { | |
| 304 | 319 // [rsp + imm8] |
| 320 // [01 reg 100][00 100 100] disp8 | |
| 321 emit_byte(0x44 | regenc); | |
| 0 | 322 emit_byte(0x24); |
| 323 emit_byte(disp & 0xFF); | |
| 324 } else { | |
| 304 | 325 // [rsp + imm32] |
| 326 // [10 reg 100][00 100 100] disp32 | |
| 327 emit_byte(0x84 | regenc); | |
| 0 | 328 emit_byte(0x24); |
| 329 emit_data(disp, rspec, disp32_operand); | |
| 330 } | |
| 331 } else { | |
| 332 // [base + disp] | |
| 304 | 333 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode"); |
| 334 if (disp == 0 && rtype == relocInfo::none && | |
| 335 base != rbp LP64_ONLY(&& base != r13)) { | |
| 0 | 336 // [base] |
| 337 // [00 reg base] | |
| 304 | 338 emit_byte(0x00 | regenc | baseenc); |
| 0 | 339 } else if (is8bit(disp) && rtype == relocInfo::none) { |
| 304 | 340 // [base + disp8] |
| 341 // [01 reg base] disp8 | |
| 342 emit_byte(0x40 | regenc | baseenc); | |
| 0 | 343 emit_byte(disp & 0xFF); |
| 344 } else { | |
| 304 | 345 // [base + disp32] |
| 346 // [10 reg base] disp32 | |
| 347 emit_byte(0x80 | regenc | baseenc); | |
| 0 | 348 emit_data(disp, rspec, disp32_operand); |
| 349 } | |
| 350 } | |
| 351 } else { | |
| 352 if (index->is_valid()) { | |
| 353 assert(scale != Address::no_scale, "inconsistent address"); | |
| 354 // [index*scale + disp] | |
| 304 | 355 // [00 reg 100][ss index 101] disp32 |
| 0 | 356 assert(index != rsp, "illegal addressing mode"); |
| 304 | 357 emit_byte(0x04 | regenc); |
| 358 emit_byte(scale << 6 | indexenc | 0x05); | |
| 0 | 359 emit_data(disp, rspec, disp32_operand); |
| 304 | 360 } else if (rtype != relocInfo::none ) { |
| 361 // [disp] (64bit) RIP-RELATIVE (32bit) abs | |
| 362 // [00 000 101] disp32 | |
| 363 | |
| 364 emit_byte(0x05 | regenc); | |
| 365 // Note that the RIP-rel. correction applies to the generated | |
| 366 // disp field, but _not_ to the target address in the rspec. | |
| 367 | |
| 368 // disp was created by converting the target address minus the pc | |
| 369 // at the start of the instruction. That needs more correction here. | |
| 370 // intptr_t disp = target - next_ip; | |
| 371 assert(inst_mark() != NULL, "must be inside InstructionMark"); | |
| 372 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction; | |
| 373 int64_t adjusted = disp; | |
| 374 // Do rip-rel adjustment for 64bit | |
| 375 LP64_ONLY(adjusted -= (next_ip - inst_mark())); | |
| 376 assert(is_simm32(adjusted), | |
| 377 "must be 32bit offset (RIP relative address)"); | |
| 378 emit_data((int32_t) adjusted, rspec, disp32_operand); | |
| 379 | |
| 0 | 380 } else { |
| 304 | 381 // 32bit never did this, did everything as the rip-rel/disp code above |
| 382 // [disp] ABSOLUTE | |
| 383 // [00 reg 100][00 100 101] disp32 | |
| 384 emit_byte(0x04 | regenc); | |
| 385 emit_byte(0x25); | |
| 0 | 386 emit_data(disp, rspec, disp32_operand); |
| 387 } | |
| 388 } | |
| 389 } | |
| 390 | |
| 304 | 391 void Assembler::emit_operand(XMMRegister reg, Register base, Register index, |
| 392 Address::ScaleFactor scale, int disp, | |
| 393 RelocationHolder const& rspec) { | |
| 394 emit_operand((Register)reg, base, index, scale, disp, rspec); | |
| 395 } | |
| 396 | |
| 0 | 397 // Secret local extension to Assembler::WhichOperand: |
| 398 #define end_pc_operand (_WhichOperand_limit) | |
| 399 | |
| 400 address Assembler::locate_operand(address inst, WhichOperand which) { | |
| 401 // Decode the given instruction, and return the address of | |
| 402 // an embedded 32-bit operand word. | |
| 403 | |
| 404 // If "which" is disp32_operand, selects the displacement portion | |
| 405 // of an effective address specifier. | |
| 304 | 406 // If "which" is imm64_operand, selects the trailing immediate constant. |
| 0 | 407 // If "which" is call32_operand, selects the displacement of a call or jump. |
| 408 // Caller is responsible for ensuring that there is such an operand, | |
| 304 | 409 // and that it is 32/64 bits wide. |
| 0 | 410 |
| 411 // If "which" is end_pc_operand, find the end of the instruction. | |
| 412 | |
| 413 address ip = inst; | |
| 304 | 414 bool is_64bit = false; |
| 415 | |
| 416 debug_only(bool has_disp32 = false); | |
| 417 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn | |
| 418 | |
| 419 again_after_prefix: | |
| 0 | 420 switch (0xFF & *ip++) { |
| 421 | |
| 422 // These convenience macros generate groups of "case" labels for the switch. | |
| 304 | 423 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3 |
| 424 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \ | |
| 0 | 425 case (x)+4: case (x)+5: case (x)+6: case (x)+7 |
| 304 | 426 #define REP16(x) REP8((x)+0): \ |
| 0 | 427 case REP8((x)+8) |
| 428 | |
| 429 case CS_segment: | |
| 430 case SS_segment: | |
| 431 case DS_segment: | |
| 432 case ES_segment: | |
| 433 case FS_segment: | |
| 434 case GS_segment: | |
| 304 | 435 // Seems dubious |
| 436 LP64_ONLY(assert(false, "shouldn't have that prefix")); | |
| 0 | 437 assert(ip == inst+1, "only one prefix allowed"); |
| 438 goto again_after_prefix; | |
| 439 | |
| 304 | 440 case 0x67: |
| 441 case REX: | |
| 442 case REX_B: | |
| 443 case REX_X: | |
| 444 case REX_XB: | |
| 445 case REX_R: | |
| 446 case REX_RB: | |
| 447 case REX_RX: | |
| 448 case REX_RXB: | |
| 449 NOT_LP64(assert(false, "64bit prefixes")); | |
| 450 goto again_after_prefix; | |
| 451 | |
| 452 case REX_W: | |
| 453 case REX_WB: | |
| 454 case REX_WX: | |
| 455 case REX_WXB: | |
| 456 case REX_WR: | |
| 457 case REX_WRB: | |
| 458 case REX_WRX: | |
| 459 case REX_WRXB: | |
| 460 NOT_LP64(assert(false, "64bit prefixes")); | |
| 461 is_64bit = true; | |
| 462 goto again_after_prefix; | |
| 463 | |
| 464 case 0xFF: // pushq a; decl a; incl a; call a; jmp a | |
| 0 | 465 case 0x88: // movb a, r |
| 466 case 0x89: // movl a, r | |
| 467 case 0x8A: // movb r, a | |
| 468 case 0x8B: // movl r, a | |
| 469 case 0x8F: // popl a | |
| 304 | 470 debug_only(has_disp32 = true); |
| 0 | 471 break; |
| 472 | |
| 304 | 473 case 0x68: // pushq #32 |
| 474 if (which == end_pc_operand) { | |
| 475 return ip + 4; | |
| 476 } | |
| 477 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate"); | |
| 0 | 478 return ip; // not produced by emit_operand |
| 479 | |
| 480 case 0x66: // movw ... (size prefix) | |
| 304 | 481 again_after_size_prefix2: |
| 0 | 482 switch (0xFF & *ip++) { |
| 304 | 483 case REX: |
| 484 case REX_B: | |
| 485 case REX_X: | |
| 486 case REX_XB: | |
| 487 case REX_R: | |
| 488 case REX_RB: | |
| 489 case REX_RX: | |
| 490 case REX_RXB: | |
| 491 case REX_W: | |
| 492 case REX_WB: | |
| 493 case REX_WX: | |
| 494 case REX_WXB: | |
| 495 case REX_WR: | |
| 496 case REX_WRB: | |
| 497 case REX_WRX: | |
| 498 case REX_WRXB: | |
| 499 NOT_LP64(assert(false, "64bit prefix found")); | |
| 500 goto again_after_size_prefix2; | |
| 0 | 501 case 0x8B: // movw r, a |
| 502 case 0x89: // movw a, r | |
| 304 | 503 debug_only(has_disp32 = true); |
| 0 | 504 break; |
| 505 case 0xC7: // movw a, #16 | |
| 304 | 506 debug_only(has_disp32 = true); |
| 0 | 507 tail_size = 2; // the imm16 |
| 508 break; | |
| 509 case 0x0F: // several SSE/SSE2 variants | |
| 510 ip--; // reparse the 0x0F | |
| 511 goto again_after_prefix; | |
| 512 default: | |
| 513 ShouldNotReachHere(); | |
| 514 } | |
| 515 break; | |
| 516 | |
| 304 | 517 case REP8(0xB8): // movl/q r, #32/#64(oop?) |
| 518 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4); | |
| 519 // these asserts are somewhat nonsensical | |
| 520 #ifndef _LP64 | |
| 521 assert(which == imm_operand || which == disp32_operand, ""); | |
| 522 #else | |
| 523 assert((which == call32_operand || which == imm_operand) && is_64bit || | |
| 524 which == narrow_oop_operand && !is_64bit, ""); | |
| 525 #endif // _LP64 | |
| 0 | 526 return ip; |
| 527 | |
| 528 case 0x69: // imul r, a, #32 | |
| 529 case 0xC7: // movl a, #32(oop?) | |
| 530 tail_size = 4; | |
| 304 | 531 debug_only(has_disp32 = true); // has both kinds of operands! |
| 0 | 532 break; |
| 533 | |
| 534 case 0x0F: // movx..., etc. | |
| 535 switch (0xFF & *ip++) { | |
| 4759 | 536 case 0x3A: // pcmpestri |
| 537 tail_size = 1; | |
| 538 case 0x38: // ptest, pmovzxbw | |
| 539 ip++; // skip opcode | |
| 540 debug_only(has_disp32 = true); // has both kinds of operands! | |
| 541 break; | |
| 542 | |
| 543 case 0x70: // pshufd r, r/a, #8 | |
| 544 debug_only(has_disp32 = true); // has both kinds of operands! | |
| 545 case 0x73: // psrldq r, #8 | |
| 546 tail_size = 1; | |
| 547 break; | |
| 548 | |
| 0 | 549 case 0x12: // movlps |
| 550 case 0x28: // movaps | |
| 551 case 0x2E: // ucomiss | |
| 552 case 0x2F: // comiss | |
| 553 case 0x54: // andps | |
| 554 case 0x55: // andnps | |
| 555 case 0x56: // orps | |
| 556 case 0x57: // xorps | |
| 557 case 0x6E: // movd | |
| 558 case 0x7E: // movd | |
| 4759 | 559 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush |
| 304 | 560 debug_only(has_disp32 = true); |
| 0 | 561 break; |
| 562 | |
| 563 case 0xAD: // shrd r, a, %cl | |
| 564 case 0xAF: // imul r, a | |
| 304 | 565 case 0xBE: // movsbl r, a (movsxb) |
| 566 case 0xBF: // movswl r, a (movsxw) | |
| 567 case 0xB6: // movzbl r, a (movzxb) | |
| 568 case 0xB7: // movzwl r, a (movzxw) | |
| 0 | 569 case REP16(0x40): // cmovl cc, r, a |
| 570 case 0xB0: // cmpxchgb | |
| 571 case 0xB1: // cmpxchg | |
| 572 case 0xC1: // xaddl | |
| 573 case 0xC7: // cmpxchg8 | |
| 574 case REP16(0x90): // setcc a | |
| 304 | 575 debug_only(has_disp32 = true); |
| 0 | 576 // fall out of the switch to decode the address |
| 577 break; | |
| 304 | 578 |
| 4759 | 579 case 0xC4: // pinsrw r, a, #8 |
| 580 debug_only(has_disp32 = true); | |
| 581 case 0xC5: // pextrw r, r, #8 | |
| 582 tail_size = 1; // the imm8 | |
| 583 break; | |
| 584 | |
| 0 | 585 case 0xAC: // shrd r, a, #8 |
| 304 | 586 debug_only(has_disp32 = true); |
| 0 | 587 tail_size = 1; // the imm8 |
| 588 break; | |
| 304 | 589 |
| 0 | 590 case REP16(0x80): // jcc rdisp32 |
| 591 if (which == end_pc_operand) return ip + 4; | |
| 304 | 592 assert(which == call32_operand, "jcc has no disp32 or imm"); |
| 0 | 593 return ip; |
| 594 default: | |
| 595 ShouldNotReachHere(); | |
| 596 } | |
| 597 break; | |
| 598 | |
| 599 case 0x81: // addl a, #32; addl r, #32 | |
| 600 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl | |
| 304 | 601 // on 32bit in the case of cmpl, the imm might be an oop |
| 0 | 602 tail_size = 4; |
| 304 | 603 debug_only(has_disp32 = true); // has both kinds of operands! |
| 0 | 604 break; |
| 605 | |
| 606 case 0x83: // addl a, #8; addl r, #8 | |
| 607 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl | |
| 304 | 608 debug_only(has_disp32 = true); // has both kinds of operands! |
| 0 | 609 tail_size = 1; |
| 610 break; | |
| 611 | |
| 612 case 0x9B: | |
| 613 switch (0xFF & *ip++) { | |
| 614 case 0xD9: // fnstcw a | |
| 304 | 615 debug_only(has_disp32 = true); |
| 0 | 616 break; |
| 617 default: | |
| 618 ShouldNotReachHere(); | |
| 619 } | |
| 620 break; | |
| 621 | |
| 622 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a | |
| 623 case REP4(0x10): // adc... | |
| 624 case REP4(0x20): // and... | |
| 625 case REP4(0x30): // xor... | |
| 626 case REP4(0x08): // or... | |
| 627 case REP4(0x18): // sbb... | |
| 628 case REP4(0x28): // sub... | |
| 304 | 629 case 0xF7: // mull a |
| 630 case 0x8D: // lea r, a | |
| 631 case 0x87: // xchg r, a | |
| 0 | 632 case REP4(0x38): // cmp... |
| 304 | 633 case 0x85: // test r, a |
| 634 debug_only(has_disp32 = true); // has both kinds of operands! | |
| 0 | 635 break; |
| 636 | |
| 637 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8 | |
| 638 case 0xC6: // movb a, #8 | |
| 639 case 0x80: // cmpb a, #8 | |
| 640 case 0x6B: // imul r, a, #8 | |
| 304 | 641 debug_only(has_disp32 = true); // has both kinds of operands! |
| 0 | 642 tail_size = 1; // the imm8 |
| 643 break; | |
| 644 | |
| 4759 | 645 case 0xC4: // VEX_3bytes |
| 646 case 0xC5: // VEX_2bytes | |
| 647 assert((UseAVX > 0), "shouldn't have VEX prefix"); | |
| 648 assert(ip == inst+1, "no prefixes allowed"); | |
| 649 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions | |
| 650 // but they have prefix 0x0F and processed when 0x0F processed above. | |
| 651 // | |
| 652 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES | |
| 653 // instructions (these instructions are not supported in 64-bit mode). | |
| 654 // To distinguish them bits [7:6] are set in the VEX second byte since | |
| 655 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set | |
| 656 // those VEX bits REX and vvvv bits are inverted. | |
| 657 // | |
| 658 // Fortunately C2 doesn't generate these instructions so we don't need | |
| 659 // to check for them in product version. | |
| 660 | |
| 661 // Check second byte | |
| 662 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions")); | |
| 663 | |
| 664 // First byte | |
| 665 if ((0xFF & *inst) == VEX_3bytes) { | |
| 666 ip++; // third byte | |
| 667 is_64bit = ((VEX_W & *ip) == VEX_W); | |
| 668 } | |
| 669 ip++; // opcode | |
| 670 // To find the end of instruction (which == end_pc_operand). | |
| 671 switch (0xFF & *ip) { | |
| 672 case 0x61: // pcmpestri r, r/a, #8 | |
| 673 case 0x70: // pshufd r, r/a, #8 | |
| 674 case 0x73: // psrldq r, #8 | |
| 675 tail_size = 1; // the imm8 | |
| 676 break; | |
| 677 default: | |
| 678 break; | |
| 679 } | |
| 680 ip++; // skip opcode | |
| 681 debug_only(has_disp32 = true); // has both kinds of operands! | |
| 682 break; | |
| 0 | 683 |
| 684 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1 | |
| 685 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl | |
| 686 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a | |
| 687 case 0xDD: // fld_d a; fst_d a; fstp_d a | |
| 688 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a | |
| 689 case 0xDF: // fild_d a; fistp_d a | |
| 690 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a | |
| 691 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a | |
| 692 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a | |
| 304 | 693 debug_only(has_disp32 = true); |
| 0 | 694 break; |
| 695 | |
| 4759 | 696 case 0xE8: // call rdisp32 |
| 697 case 0xE9: // jmp rdisp32 | |
| 698 if (which == end_pc_operand) return ip + 4; | |
| 699 assert(which == call32_operand, "call has no disp32 or imm"); | |
| 700 return ip; | |
| 701 | |
|
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702 case 0xF0: // Lock |
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703 assert(os::is_MP(), "only on MP"); |
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704 goto again_after_prefix; |
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705 |
| 0 | 706 case 0xF3: // For SSE |
| 707 case 0xF2: // For SSE2 | |
| 304 | 708 switch (0xFF & *ip++) { |
| 709 case REX: | |
| 710 case REX_B: | |
| 711 case REX_X: | |
| 712 case REX_XB: | |
| 713 case REX_R: | |
| 714 case REX_RB: | |
| 715 case REX_RX: | |
| 716 case REX_RXB: | |
| 717 case REX_W: | |
| 718 case REX_WB: | |
| 719 case REX_WX: | |
| 720 case REX_WXB: | |
| 721 case REX_WR: | |
| 722 case REX_WRB: | |
| 723 case REX_WRX: | |
| 724 case REX_WRXB: | |
| 725 NOT_LP64(assert(false, "found 64bit prefix")); | |
| 726 ip++; | |
| 727 default: | |
| 728 ip++; | |
| 729 } | |
| 730 debug_only(has_disp32 = true); // has both kinds of operands! | |
| 0 | 731 break; |
| 732 | |
| 733 default: | |
| 734 ShouldNotReachHere(); | |
| 735 | |
| 304 | 736 #undef REP8 |
| 737 #undef REP16 | |
| 0 | 738 } |
| 739 | |
| 740 assert(which != call32_operand, "instruction is not a call, jmp, or jcc"); | |
| 304 | 741 #ifdef _LP64 |
| 742 assert(which != imm_operand, "instruction is not a movq reg, imm64"); | |
| 743 #else | |
| 744 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field"); | |
| 745 assert(which != imm_operand || has_disp32, "instruction has no imm32 field"); | |
| 746 #endif // LP64 | |
| 747 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field"); | |
| 0 | 748 |
| 749 // parse the output of emit_operand | |
| 750 int op2 = 0xFF & *ip++; | |
| 751 int base = op2 & 0x07; | |
| 752 int op3 = -1; | |
| 753 const int b100 = 4; | |
| 754 const int b101 = 5; | |
| 755 if (base == b100 && (op2 >> 6) != 3) { | |
| 756 op3 = 0xFF & *ip++; | |
| 757 base = op3 & 0x07; // refetch the base | |
| 758 } | |
| 759 // now ip points at the disp (if any) | |
| 760 | |
| 761 switch (op2 >> 6) { | |
| 762 case 0: | |
| 763 // [00 reg 100][ss index base] | |
| 304 | 764 // [00 reg 100][00 100 esp] |
| 0 | 765 // [00 reg base] |
| 766 // [00 reg 100][ss index 101][disp32] | |
| 767 // [00 reg 101] [disp32] | |
| 768 | |
| 769 if (base == b101) { | |
| 770 if (which == disp32_operand) | |
| 771 return ip; // caller wants the disp32 | |
| 772 ip += 4; // skip the disp32 | |
| 773 } | |
| 774 break; | |
| 775 | |
| 776 case 1: | |
| 777 // [01 reg 100][ss index base][disp8] | |
| 304 | 778 // [01 reg 100][00 100 esp][disp8] |
| 0 | 779 // [01 reg base] [disp8] |
| 780 ip += 1; // skip the disp8 | |
| 781 break; | |
| 782 | |
| 783 case 2: | |
| 784 // [10 reg 100][ss index base][disp32] | |
| 304 | 785 // [10 reg 100][00 100 esp][disp32] |
| 0 | 786 // [10 reg base] [disp32] |
| 787 if (which == disp32_operand) | |
| 788 return ip; // caller wants the disp32 | |
| 789 ip += 4; // skip the disp32 | |
| 790 break; | |
| 791 | |
| 792 case 3: | |
| 793 // [11 reg base] (not a memory addressing mode) | |
| 794 break; | |
| 795 } | |
| 796 | |
| 797 if (which == end_pc_operand) { | |
| 798 return ip + tail_size; | |
| 799 } | |
| 800 | |
| 304 | 801 #ifdef _LP64 |
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802 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32"); |
| 304 | 803 #else |
| 804 assert(which == imm_operand, "instruction has only an imm field"); | |
| 805 #endif // LP64 | |
| 0 | 806 return ip; |
| 807 } | |
| 808 | |
| 809 address Assembler::locate_next_instruction(address inst) { | |
| 810 // Secretly share code with locate_operand: | |
| 811 return locate_operand(inst, end_pc_operand); | |
| 812 } | |
| 813 | |
| 814 | |
| 815 #ifdef ASSERT | |
| 816 void Assembler::check_relocation(RelocationHolder const& rspec, int format) { | |
| 817 address inst = inst_mark(); | |
| 818 assert(inst != NULL && inst < pc(), "must point to beginning of instruction"); | |
| 819 address opnd; | |
| 820 | |
| 821 Relocation* r = rspec.reloc(); | |
| 822 if (r->type() == relocInfo::none) { | |
| 823 return; | |
| 824 } else if (r->is_call() || format == call32_operand) { | |
| 825 // assert(format == imm32_operand, "cannot specify a nonzero format"); | |
| 826 opnd = locate_operand(inst, call32_operand); | |
| 827 } else if (r->is_data()) { | |
| 304 | 828 assert(format == imm_operand || format == disp32_operand |
| 829 LP64_ONLY(|| format == narrow_oop_operand), "format ok"); | |
| 0 | 830 opnd = locate_operand(inst, (WhichOperand)format); |
| 831 } else { | |
| 304 | 832 assert(format == imm_operand, "cannot specify a format"); |
| 0 | 833 return; |
| 834 } | |
| 835 assert(opnd == pc(), "must put operand where relocs can find it"); | |
| 836 } | |
| 304 | 837 #endif // ASSERT |
| 838 | |
| 839 void Assembler::emit_operand32(Register reg, Address adr) { | |
| 840 assert(reg->encoding() < 8, "no extended registers"); | |
| 841 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); | |
| 842 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |
| 843 adr._rspec); | |
| 844 } | |
| 845 | |
| 846 void Assembler::emit_operand(Register reg, Address adr, | |
| 847 int rip_relative_correction) { | |
| 848 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |
| 849 adr._rspec, | |
| 850 rip_relative_correction); | |
| 851 } | |
| 852 | |
| 853 void Assembler::emit_operand(XMMRegister reg, Address adr) { | |
| 854 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |
| 855 adr._rspec); | |
| 856 } | |
| 857 | |
| 858 // MMX operations | |
| 859 void Assembler::emit_operand(MMXRegister reg, Address adr) { | |
| 860 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); | |
| 861 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); | |
| 862 } | |
| 863 | |
| 864 // work around gcc (3.2.1-7a) bug | |
| 865 void Assembler::emit_operand(Address adr, MMXRegister reg) { | |
| 866 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); | |
| 867 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); | |
| 0 | 868 } |
| 869 | |
| 870 | |
| 871 void Assembler::emit_farith(int b1, int b2, int i) { | |
| 872 assert(isByte(b1) && isByte(b2), "wrong opcode"); | |
| 873 assert(0 <= i && i < 8, "illegal stack offset"); | |
| 874 emit_byte(b1); | |
| 875 emit_byte(b2 + i); | |
| 876 } | |
| 877 | |
| 878 | |
|
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879 // Now the Assembler instructions (identical for 32/64 bits) |
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880 |
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881 void Assembler::adcl(Address dst, int32_t imm32) { |
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882 InstructionMark im(this); |
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883 prefix(dst); |
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884 emit_arith_operand(0x81, rdx, dst, imm32); |
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885 } |
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886 |
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887 void Assembler::adcl(Address dst, Register src) { |
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888 InstructionMark im(this); |
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889 prefix(dst, src); |
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890 emit_byte(0x11); |
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891 emit_operand(src, dst); |
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892 } |
| 304 | 893 |
| 894 void Assembler::adcl(Register dst, int32_t imm32) { | |
| 895 prefix(dst); | |
| 0 | 896 emit_arith(0x81, 0xD0, dst, imm32); |
| 897 } | |
| 898 | |
| 899 void Assembler::adcl(Register dst, Address src) { | |
| 900 InstructionMark im(this); | |
| 304 | 901 prefix(src, dst); |
| 0 | 902 emit_byte(0x13); |
| 903 emit_operand(dst, src); | |
| 904 } | |
| 905 | |
| 906 void Assembler::adcl(Register dst, Register src) { | |
| 304 | 907 (void) prefix_and_encode(dst->encoding(), src->encoding()); |
| 0 | 908 emit_arith(0x13, 0xC0, dst, src); |
| 909 } | |
| 910 | |
| 304 | 911 void Assembler::addl(Address dst, int32_t imm32) { |
| 912 InstructionMark im(this); | |
| 913 prefix(dst); | |
| 914 emit_arith_operand(0x81, rax, dst, imm32); | |
| 915 } | |
| 0 | 916 |
| 917 void Assembler::addl(Address dst, Register src) { | |
| 918 InstructionMark im(this); | |
| 304 | 919 prefix(dst, src); |
| 0 | 920 emit_byte(0x01); |
| 921 emit_operand(src, dst); | |
| 922 } | |
| 923 | |
| 304 | 924 void Assembler::addl(Register dst, int32_t imm32) { |
| 925 prefix(dst); | |
| 0 | 926 emit_arith(0x81, 0xC0, dst, imm32); |
| 927 } | |
| 928 | |
| 929 void Assembler::addl(Register dst, Address src) { | |
| 930 InstructionMark im(this); | |
| 304 | 931 prefix(src, dst); |
| 0 | 932 emit_byte(0x03); |
| 933 emit_operand(dst, src); | |
| 934 } | |
| 935 | |
| 936 void Assembler::addl(Register dst, Register src) { | |
| 304 | 937 (void) prefix_and_encode(dst->encoding(), src->encoding()); |
| 0 | 938 emit_arith(0x03, 0xC0, dst, src); |
| 939 } | |
| 940 | |
| 941 void Assembler::addr_nop_4() { | |
| 942 // 4 bytes: NOP DWORD PTR [EAX+0] | |
| 943 emit_byte(0x0F); | |
| 944 emit_byte(0x1F); | |
| 945 emit_byte(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc); | |
| 946 emit_byte(0); // 8-bits offset (1 byte) | |
| 947 } | |
| 948 | |
| 949 void Assembler::addr_nop_5() { | |
| 950 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset | |
| 951 emit_byte(0x0F); | |
| 952 emit_byte(0x1F); | |
| 953 emit_byte(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4); | |
| 954 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); | |
| 955 emit_byte(0); // 8-bits offset (1 byte) | |
| 956 } | |
| 957 | |
| 958 void Assembler::addr_nop_7() { | |
| 959 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset | |
| 960 emit_byte(0x0F); | |
| 961 emit_byte(0x1F); | |
| 962 emit_byte(0x80); // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc); | |
| 963 emit_long(0); // 32-bits offset (4 bytes) | |
| 964 } | |
| 965 | |
| 966 void Assembler::addr_nop_8() { | |
| 967 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset | |
| 968 emit_byte(0x0F); | |
| 969 emit_byte(0x1F); | |
| 970 emit_byte(0x84); // emit_rm(cbuf, 0x2, EAX_enc, 0x4); | |
| 971 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); | |
| 972 emit_long(0); // 32-bits offset (4 bytes) | |
| 973 } | |
| 974 | |
| 304 | 975 void Assembler::addsd(XMMRegister dst, XMMRegister src) { |
| 976 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 977 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
| 304 | 978 emit_byte(0x58); |
| 979 emit_byte(0xC0 | encode); | |
| 980 } | |
| 981 | |
| 982 void Assembler::addsd(XMMRegister dst, Address src) { | |
| 983 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 984 InstructionMark im(this); | |
| 4759 | 985 simd_prefix(dst, dst, src, VEX_SIMD_F2); |
| 304 | 986 emit_byte(0x58); |
| 987 emit_operand(dst, src); | |
| 988 } | |
| 989 | |
| 990 void Assembler::addss(XMMRegister dst, XMMRegister src) { | |
| 991 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 4759 | 992 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); |
| 304 | 993 emit_byte(0x58); |
| 994 emit_byte(0xC0 | encode); | |
| 995 } | |
| 996 | |
| 997 void Assembler::addss(XMMRegister dst, Address src) { | |
| 998 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 999 InstructionMark im(this); | |
| 4759 | 1000 simd_prefix(dst, dst, src, VEX_SIMD_F3); |
| 304 | 1001 emit_byte(0x58); |
| 1002 emit_operand(dst, src); | |
| 1003 } | |
| 1004 | |
| 4759 | 1005 void Assembler::andl(Address dst, int32_t imm32) { |
| 1006 InstructionMark im(this); | |
| 1007 prefix(dst); | |
| 1008 emit_byte(0x81); | |
| 1009 emit_operand(rsp, dst, 4); | |
| 1010 emit_long(imm32); | |
| 1011 } | |
| 1012 | |
| 304 | 1013 void Assembler::andl(Register dst, int32_t imm32) { |
| 1014 prefix(dst); | |
| 1015 emit_arith(0x81, 0xE0, dst, imm32); | |
| 1016 } | |
| 1017 | |
| 1018 void Assembler::andl(Register dst, Address src) { | |
| 1019 InstructionMark im(this); | |
| 1020 prefix(src, dst); | |
| 1021 emit_byte(0x23); | |
| 1022 emit_operand(dst, src); | |
| 1023 } | |
| 1024 | |
| 1025 void Assembler::andl(Register dst, Register src) { | |
| 1026 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1027 emit_arith(0x23, 0xC0, dst, src); | |
| 1028 } | |
| 1029 | |
| 1030 void Assembler::andpd(XMMRegister dst, Address src) { | |
| 1031 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1032 InstructionMark im(this); | |
| 4759 | 1033 simd_prefix(dst, dst, src, VEX_SIMD_66); |
| 304 | 1034 emit_byte(0x54); |
| 1035 emit_operand(dst, src); | |
| 1036 } | |
| 1037 | |
| 4759 | 1038 void Assembler::andpd(XMMRegister dst, XMMRegister src) { |
| 1039 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1040 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); | |
| 1041 emit_byte(0x54); | |
| 1042 emit_byte(0xC0 | encode); | |
| 1043 } | |
| 1044 | |
| 1045 void Assembler::andps(XMMRegister dst, Address src) { | |
| 1046 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1047 InstructionMark im(this); | |
| 1048 simd_prefix(dst, dst, src, VEX_SIMD_NONE); | |
| 1049 emit_byte(0x54); | |
| 1050 emit_operand(dst, src); | |
| 1051 } | |
| 1052 | |
| 1053 void Assembler::andps(XMMRegister dst, XMMRegister src) { | |
| 1054 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1055 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE); | |
| 1056 emit_byte(0x54); | |
| 1057 emit_byte(0xC0 | encode); | |
| 1058 } | |
| 1059 | |
|
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1060 void Assembler::bsfl(Register dst, Register src) { |
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1061 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
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1062 emit_byte(0x0F); |
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1063 emit_byte(0xBC); |
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1064 emit_byte(0xC0 | encode); |
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1065 } |
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1066 |
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1067 void Assembler::bsrl(Register dst, Register src) { |
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1068 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT"); |
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1069 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
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1070 emit_byte(0x0F); |
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1071 emit_byte(0xBD); |
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1072 emit_byte(0xC0 | encode); |
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1073 } |
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1074 |
| 304 | 1075 void Assembler::bswapl(Register reg) { // bswap |
| 1076 int encode = prefix_and_encode(reg->encoding()); | |
| 1077 emit_byte(0x0F); | |
| 1078 emit_byte(0xC8 | encode); | |
| 1079 } | |
| 1080 | |
| 1081 void Assembler::call(Label& L, relocInfo::relocType rtype) { | |
| 1082 // suspect disp32 is always good | |
| 1083 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand); | |
| 1084 | |
| 1085 if (L.is_bound()) { | |
| 1086 const int long_size = 5; | |
| 1087 int offs = (int)( target(L) - pc() ); | |
| 1088 assert(offs <= 0, "assembler error"); | |
| 1089 InstructionMark im(this); | |
| 1090 // 1110 1000 #32-bit disp | |
| 1091 emit_byte(0xE8); | |
| 1092 emit_data(offs - long_size, rtype, operand); | |
| 1093 } else { | |
| 1094 InstructionMark im(this); | |
| 1095 // 1110 1000 #32-bit disp | |
| 1096 L.add_patch_at(code(), locator()); | |
| 1097 | |
| 1098 emit_byte(0xE8); | |
| 1099 emit_data(int(0), rtype, operand); | |
| 1100 } | |
| 1101 } | |
| 1102 | |
| 1103 void Assembler::call(Register dst) { | |
| 4759 | 1104 int encode = prefix_and_encode(dst->encoding()); |
| 304 | 1105 emit_byte(0xFF); |
| 1106 emit_byte(0xD0 | encode); | |
| 1107 } | |
| 1108 | |
| 1109 | |
| 1110 void Assembler::call(Address adr) { | |
| 1111 InstructionMark im(this); | |
| 1112 prefix(adr); | |
| 1113 emit_byte(0xFF); | |
| 1114 emit_operand(rdx, adr); | |
| 1115 } | |
| 1116 | |
| 1117 void Assembler::call_literal(address entry, RelocationHolder const& rspec) { | |
| 1118 assert(entry != NULL, "call most probably wrong"); | |
| 1119 InstructionMark im(this); | |
| 1120 emit_byte(0xE8); | |
| 1121 intptr_t disp = entry - (_code_pos + sizeof(int32_t)); | |
| 1122 assert(is_simm32(disp), "must be 32bit offset (call2)"); | |
| 1123 // Technically, should use call32_operand, but this format is | |
| 1124 // implied by the fact that we're emitting a call instruction. | |
| 1125 | |
| 1126 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand); | |
| 1127 emit_data((int) disp, rspec, operand); | |
| 1128 } | |
| 1129 | |
| 1130 void Assembler::cdql() { | |
| 1131 emit_byte(0x99); | |
| 1132 } | |
| 1133 | |
| 1134 void Assembler::cmovl(Condition cc, Register dst, Register src) { | |
| 1135 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); | |
| 1136 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1137 emit_byte(0x0F); | |
| 1138 emit_byte(0x40 | cc); | |
| 1139 emit_byte(0xC0 | encode); | |
| 1140 } | |
| 1141 | |
| 1142 | |
| 1143 void Assembler::cmovl(Condition cc, Register dst, Address src) { | |
| 1144 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); | |
| 1145 prefix(src, dst); | |
| 1146 emit_byte(0x0F); | |
| 1147 emit_byte(0x40 | cc); | |
| 1148 emit_operand(dst, src); | |
| 1149 } | |
| 1150 | |
| 1151 void Assembler::cmpb(Address dst, int imm8) { | |
| 1152 InstructionMark im(this); | |
| 1153 prefix(dst); | |
| 1154 emit_byte(0x80); | |
| 1155 emit_operand(rdi, dst, 1); | |
| 1156 emit_byte(imm8); | |
| 1157 } | |
| 1158 | |
| 1159 void Assembler::cmpl(Address dst, int32_t imm32) { | |
| 1160 InstructionMark im(this); | |
| 1161 prefix(dst); | |
| 1162 emit_byte(0x81); | |
| 1163 emit_operand(rdi, dst, 4); | |
| 1164 emit_long(imm32); | |
| 1165 } | |
| 1166 | |
| 1167 void Assembler::cmpl(Register dst, int32_t imm32) { | |
| 1168 prefix(dst); | |
| 1169 emit_arith(0x81, 0xF8, dst, imm32); | |
| 1170 } | |
| 1171 | |
| 1172 void Assembler::cmpl(Register dst, Register src) { | |
| 1173 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1174 emit_arith(0x3B, 0xC0, dst, src); | |
| 1175 } | |
| 1176 | |
| 1177 | |
| 1178 void Assembler::cmpl(Register dst, Address src) { | |
| 1179 InstructionMark im(this); | |
| 1180 prefix(src, dst); | |
| 1181 emit_byte(0x3B); | |
| 1182 emit_operand(dst, src); | |
| 1183 } | |
| 1184 | |
| 1185 void Assembler::cmpw(Address dst, int imm16) { | |
| 1186 InstructionMark im(this); | |
| 1187 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers"); | |
| 1188 emit_byte(0x66); | |
| 1189 emit_byte(0x81); | |
| 1190 emit_operand(rdi, dst, 2); | |
| 1191 emit_word(imm16); | |
| 1192 } | |
| 1193 | |
| 1194 // The 32-bit cmpxchg compares the value at adr with the contents of rax, | |
| 1195 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,. | |
| 1196 // The ZF is set if the compared values were equal, and cleared otherwise. | |
| 1197 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg | |
| 1198 if (Atomics & 2) { | |
| 1199 // caveat: no instructionmark, so this isn't relocatable. | |
| 1200 // Emit a synthetic, non-atomic, CAS equivalent. | |
| 1201 // Beware. The synthetic form sets all ICCs, not just ZF. | |
| 1202 // cmpxchg r,[m] is equivalent to rax, = CAS (m, rax, r) | |
| 1203 cmpl(rax, adr); | |
| 1204 movl(rax, adr); | |
| 1205 if (reg != rax) { | |
| 1206 Label L ; | |
| 1207 jcc(Assembler::notEqual, L); | |
| 1208 movl(adr, reg); | |
| 1209 bind(L); | |
| 1210 } | |
| 1211 } else { | |
| 1212 InstructionMark im(this); | |
| 1213 prefix(adr, reg); | |
| 1214 emit_byte(0x0F); | |
| 1215 emit_byte(0xB1); | |
| 1216 emit_operand(reg, adr); | |
| 1217 } | |
| 1218 } | |
| 1219 | |
| 1220 void Assembler::comisd(XMMRegister dst, Address src) { | |
| 1221 // NOTE: dbx seems to decode this as comiss even though the | |
| 1222 // 0x66 is there. Strangly ucomisd comes out correct | |
| 1223 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 1224 InstructionMark im(this); |
| 1225 simd_prefix(dst, src, VEX_SIMD_66); | |
| 1226 emit_byte(0x2F); | |
| 1227 emit_operand(dst, src); | |
| 1228 } | |
| 1229 | |
| 1230 void Assembler::comisd(XMMRegister dst, XMMRegister src) { | |
| 1231 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1232 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); | |
| 1233 emit_byte(0x2F); | |
| 1234 emit_byte(0xC0 | encode); | |
| 304 | 1235 } |
| 1236 | |
| 1237 void Assembler::comiss(XMMRegister dst, Address src) { | |
| 1238 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 4759 | 1239 InstructionMark im(this); |
| 1240 simd_prefix(dst, src, VEX_SIMD_NONE); | |
| 304 | 1241 emit_byte(0x2F); |
| 1242 emit_operand(dst, src); | |
| 1243 } | |
| 1244 | |
| 4759 | 1245 void Assembler::comiss(XMMRegister dst, XMMRegister src) { |
| 1246 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1247 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE); | |
| 1248 emit_byte(0x2F); | |
| 1249 emit_byte(0xC0 | encode); | |
| 1250 } | |
| 1251 | |
| 304 | 1252 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) { |
| 1253 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 1254 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3); |
| 304 | 1255 emit_byte(0xE6); |
| 1256 emit_byte(0xC0 | encode); | |
| 1257 } | |
| 1258 | |
| 1259 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) { | |
| 1260 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 1261 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE); |
| 304 | 1262 emit_byte(0x5B); |
| 1263 emit_byte(0xC0 | encode); | |
| 1264 } | |
| 1265 | |
| 1266 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) { | |
| 1267 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 1268 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
| 304 | 1269 emit_byte(0x5A); |
| 1270 emit_byte(0xC0 | encode); | |
| 1271 } | |
| 1272 | |
| 4759 | 1273 void Assembler::cvtsd2ss(XMMRegister dst, Address src) { |
| 1274 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1275 InstructionMark im(this); | |
| 1276 simd_prefix(dst, dst, src, VEX_SIMD_F2); | |
| 1277 emit_byte(0x5A); | |
| 1278 emit_operand(dst, src); | |
| 1279 } | |
| 1280 | |
| 304 | 1281 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) { |
| 1282 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 1283 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
| 304 | 1284 emit_byte(0x2A); |
| 1285 emit_byte(0xC0 | encode); | |
| 1286 } | |
| 1287 | |
| 4759 | 1288 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) { |
| 1289 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1290 InstructionMark im(this); | |
| 1291 simd_prefix(dst, dst, src, VEX_SIMD_F2); | |
| 1292 emit_byte(0x2A); | |
| 1293 emit_operand(dst, src); | |
| 1294 } | |
| 1295 | |
| 304 | 1296 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) { |
| 1297 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 4759 | 1298 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); |
| 304 | 1299 emit_byte(0x2A); |
| 1300 emit_byte(0xC0 | encode); | |
| 1301 } | |
| 1302 | |
| 4759 | 1303 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) { |
| 1304 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1305 InstructionMark im(this); | |
| 1306 simd_prefix(dst, dst, src, VEX_SIMD_F3); | |
| 1307 emit_byte(0x2A); | |
| 1308 emit_operand(dst, src); | |
| 1309 } | |
| 1310 | |
| 304 | 1311 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) { |
| 1312 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 1313 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); |
| 304 | 1314 emit_byte(0x5A); |
| 1315 emit_byte(0xC0 | encode); | |
| 1316 } | |
| 1317 | |
| 4759 | 1318 void Assembler::cvtss2sd(XMMRegister dst, Address src) { |
| 1319 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1320 InstructionMark im(this); | |
| 1321 simd_prefix(dst, dst, src, VEX_SIMD_F3); | |
| 1322 emit_byte(0x5A); | |
| 1323 emit_operand(dst, src); | |
| 1324 } | |
| 1325 | |
| 1326 | |
| 304 | 1327 void Assembler::cvttsd2sil(Register dst, XMMRegister src) { |
| 1328 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 1329 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2); |
| 304 | 1330 emit_byte(0x2C); |
| 1331 emit_byte(0xC0 | encode); | |
| 1332 } | |
| 1333 | |
| 1334 void Assembler::cvttss2sil(Register dst, XMMRegister src) { | |
| 1335 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 4759 | 1336 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3); |
| 304 | 1337 emit_byte(0x2C); |
| 1338 emit_byte(0xC0 | encode); | |
| 1339 } | |
| 1340 | |
| 1341 void Assembler::decl(Address dst) { | |
| 1342 // Don't use it directly. Use MacroAssembler::decrement() instead. | |
| 1343 InstructionMark im(this); | |
| 1344 prefix(dst); | |
| 1345 emit_byte(0xFF); | |
| 1346 emit_operand(rcx, dst); | |
| 1347 } | |
| 1348 | |
| 1349 void Assembler::divsd(XMMRegister dst, Address src) { | |
| 1350 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1351 InstructionMark im(this); | |
| 4759 | 1352 simd_prefix(dst, dst, src, VEX_SIMD_F2); |
| 304 | 1353 emit_byte(0x5E); |
| 1354 emit_operand(dst, src); | |
| 1355 } | |
| 1356 | |
| 1357 void Assembler::divsd(XMMRegister dst, XMMRegister src) { | |
| 1358 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 1359 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
| 304 | 1360 emit_byte(0x5E); |
| 1361 emit_byte(0xC0 | encode); | |
| 1362 } | |
| 1363 | |
| 1364 void Assembler::divss(XMMRegister dst, Address src) { | |
| 1365 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1366 InstructionMark im(this); | |
| 4759 | 1367 simd_prefix(dst, dst, src, VEX_SIMD_F3); |
| 304 | 1368 emit_byte(0x5E); |
| 1369 emit_operand(dst, src); | |
| 1370 } | |
| 1371 | |
| 1372 void Assembler::divss(XMMRegister dst, XMMRegister src) { | |
| 1373 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 4759 | 1374 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); |
| 304 | 1375 emit_byte(0x5E); |
| 1376 emit_byte(0xC0 | encode); | |
| 1377 } | |
| 1378 | |
| 1379 void Assembler::emms() { | |
| 1380 NOT_LP64(assert(VM_Version::supports_mmx(), "")); | |
| 1381 emit_byte(0x0F); | |
| 1382 emit_byte(0x77); | |
| 1383 } | |
| 1384 | |
| 1385 void Assembler::hlt() { | |
| 1386 emit_byte(0xF4); | |
| 1387 } | |
| 1388 | |
| 1389 void Assembler::idivl(Register src) { | |
| 1390 int encode = prefix_and_encode(src->encoding()); | |
| 1391 emit_byte(0xF7); | |
| 1392 emit_byte(0xF8 | encode); | |
| 1393 } | |
| 1394 | |
| 1920 | 1395 void Assembler::divl(Register src) { // Unsigned |
| 1396 int encode = prefix_and_encode(src->encoding()); | |
| 1397 emit_byte(0xF7); | |
| 1398 emit_byte(0xF0 | encode); | |
| 1399 } | |
| 1400 | |
| 304 | 1401 void Assembler::imull(Register dst, Register src) { |
| 1402 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1403 emit_byte(0x0F); | |
| 1404 emit_byte(0xAF); | |
| 1405 emit_byte(0xC0 | encode); | |
| 1406 } | |
| 1407 | |
| 1408 | |
| 1409 void Assembler::imull(Register dst, Register src, int value) { | |
| 1410 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1411 if (is8bit(value)) { | |
| 1412 emit_byte(0x6B); | |
| 1413 emit_byte(0xC0 | encode); | |
|
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1414 emit_byte(value & 0xFF); |
| 304 | 1415 } else { |
| 1416 emit_byte(0x69); | |
| 1417 emit_byte(0xC0 | encode); | |
| 1418 emit_long(value); | |
| 1419 } | |
| 1420 } | |
| 1421 | |
| 1422 void Assembler::incl(Address dst) { | |
| 1423 // Don't use it directly. Use MacroAssembler::increment() instead. | |
| 1424 InstructionMark im(this); | |
| 1425 prefix(dst); | |
| 1426 emit_byte(0xFF); | |
| 1427 emit_operand(rax, dst); | |
| 1428 } | |
| 1429 | |
| 3851 | 1430 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) { |
| 1431 InstructionMark im(this); | |
| 304 | 1432 assert((0 <= cc) && (cc < 16), "illegal cc"); |
| 1433 if (L.is_bound()) { | |
| 1434 address dst = target(L); | |
| 1435 assert(dst != NULL, "jcc most probably wrong"); | |
| 1436 | |
| 1437 const int short_size = 2; | |
| 1438 const int long_size = 6; | |
| 1439 intptr_t offs = (intptr_t)dst - (intptr_t)_code_pos; | |
| 3851 | 1440 if (maybe_short && is8bit(offs - short_size)) { |
| 304 | 1441 // 0111 tttn #8-bit disp |
| 1442 emit_byte(0x70 | cc); | |
| 1443 emit_byte((offs - short_size) & 0xFF); | |
| 1444 } else { | |
| 1445 // 0000 1111 1000 tttn #32-bit disp | |
| 1446 assert(is_simm32(offs - long_size), | |
| 1447 "must be 32bit offset (call4)"); | |
| 1448 emit_byte(0x0F); | |
| 1449 emit_byte(0x80 | cc); | |
| 1450 emit_long(offs - long_size); | |
| 1451 } | |
| 1452 } else { | |
| 1453 // Note: could eliminate cond. jumps to this jump if condition | |
| 1454 // is the same however, seems to be rather unlikely case. | |
| 1455 // Note: use jccb() if label to be bound is very close to get | |
| 1456 // an 8-bit displacement | |
| 1457 L.add_patch_at(code(), locator()); | |
| 1458 emit_byte(0x0F); | |
| 1459 emit_byte(0x80 | cc); | |
| 1460 emit_long(0); | |
| 1461 } | |
| 1462 } | |
| 1463 | |
| 1464 void Assembler::jccb(Condition cc, Label& L) { | |
| 1465 if (L.is_bound()) { | |
| 1466 const int short_size = 2; | |
| 1467 address entry = target(L); | |
| 1468 assert(is8bit((intptr_t)entry - ((intptr_t)_code_pos + short_size)), | |
| 1469 "Dispacement too large for a short jmp"); | |
| 1470 intptr_t offs = (intptr_t)entry - (intptr_t)_code_pos; | |
| 1471 // 0111 tttn #8-bit disp | |
| 1472 emit_byte(0x70 | cc); | |
| 1473 emit_byte((offs - short_size) & 0xFF); | |
| 1474 } else { | |
| 1475 InstructionMark im(this); | |
| 1476 L.add_patch_at(code(), locator()); | |
| 1477 emit_byte(0x70 | cc); | |
| 1478 emit_byte(0); | |
| 1479 } | |
| 1480 } | |
| 1481 | |
| 1482 void Assembler::jmp(Address adr) { | |
| 1483 InstructionMark im(this); | |
| 1484 prefix(adr); | |
| 1485 emit_byte(0xFF); | |
| 1486 emit_operand(rsp, adr); | |
| 1487 } | |
| 1488 | |
| 3851 | 1489 void Assembler::jmp(Label& L, bool maybe_short) { |
| 304 | 1490 if (L.is_bound()) { |
| 1491 address entry = target(L); | |
| 1492 assert(entry != NULL, "jmp most probably wrong"); | |
| 1493 InstructionMark im(this); | |
| 1494 const int short_size = 2; | |
| 1495 const int long_size = 5; | |
| 1496 intptr_t offs = entry - _code_pos; | |
| 3851 | 1497 if (maybe_short && is8bit(offs - short_size)) { |
| 304 | 1498 emit_byte(0xEB); |
| 1499 emit_byte((offs - short_size) & 0xFF); | |
| 1500 } else { | |
| 1501 emit_byte(0xE9); | |
| 1502 emit_long(offs - long_size); | |
| 1503 } | |
| 1504 } else { | |
| 1505 // By default, forward jumps are always 32-bit displacements, since | |
| 1506 // we can't yet know where the label will be bound. If you're sure that | |
| 1507 // the forward jump will not run beyond 256 bytes, use jmpb to | |
| 1508 // force an 8-bit displacement. | |
| 1509 InstructionMark im(this); | |
| 1510 L.add_patch_at(code(), locator()); | |
| 1511 emit_byte(0xE9); | |
| 1512 emit_long(0); | |
| 1513 } | |
| 1514 } | |
| 1515 | |
| 1516 void Assembler::jmp(Register entry) { | |
| 1517 int encode = prefix_and_encode(entry->encoding()); | |
| 1518 emit_byte(0xFF); | |
| 1519 emit_byte(0xE0 | encode); | |
| 1520 } | |
| 1521 | |
| 1522 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) { | |
| 1523 InstructionMark im(this); | |
| 1524 emit_byte(0xE9); | |
| 1525 assert(dest != NULL, "must have a target"); | |
| 1526 intptr_t disp = dest - (_code_pos + sizeof(int32_t)); | |
| 1527 assert(is_simm32(disp), "must be 32bit offset (jmp)"); | |
| 1528 emit_data(disp, rspec.reloc(), call32_operand); | |
| 1529 } | |
| 1530 | |
| 1531 void Assembler::jmpb(Label& L) { | |
| 1532 if (L.is_bound()) { | |
| 1533 const int short_size = 2; | |
| 1534 address entry = target(L); | |
| 1535 assert(is8bit((entry - _code_pos) + short_size), | |
| 1536 "Dispacement too large for a short jmp"); | |
| 1537 assert(entry != NULL, "jmp most probably wrong"); | |
| 1538 intptr_t offs = entry - _code_pos; | |
| 1539 emit_byte(0xEB); | |
| 1540 emit_byte((offs - short_size) & 0xFF); | |
| 1541 } else { | |
| 1542 InstructionMark im(this); | |
| 1543 L.add_patch_at(code(), locator()); | |
| 1544 emit_byte(0xEB); | |
| 1545 emit_byte(0); | |
| 1546 } | |
| 1547 } | |
| 1548 | |
| 1549 void Assembler::ldmxcsr( Address src) { | |
| 1550 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1551 InstructionMark im(this); | |
| 1552 prefix(src); | |
| 1553 emit_byte(0x0F); | |
| 1554 emit_byte(0xAE); | |
| 1555 emit_operand(as_Register(2), src); | |
| 1556 } | |
| 1557 | |
| 1558 void Assembler::leal(Register dst, Address src) { | |
| 1559 InstructionMark im(this); | |
| 1560 #ifdef _LP64 | |
| 1561 emit_byte(0x67); // addr32 | |
| 1562 prefix(src, dst); | |
| 1563 #endif // LP64 | |
| 1564 emit_byte(0x8D); | |
| 1565 emit_operand(dst, src); | |
| 1566 } | |
| 1567 | |
| 1568 void Assembler::lock() { | |
| 1569 if (Atomics & 1) { | |
| 1570 // Emit either nothing, a NOP, or a NOP: prefix | |
| 1571 emit_byte(0x90) ; | |
| 1572 } else { | |
| 1573 emit_byte(0xF0); | |
| 1574 } | |
| 1575 } | |
| 1576 | |
|
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1577 void Assembler::lzcntl(Register dst, Register src) { |
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1578 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); |
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1579 emit_byte(0xF3); |
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1580 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
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1581 emit_byte(0x0F); |
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1582 emit_byte(0xBD); |
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1583 emit_byte(0xC0 | encode); |
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1584 } |
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1585 |
|
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1586 // Emit mfence instruction |
| 304 | 1587 void Assembler::mfence() { |
|
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1588 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");) |
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1589 emit_byte( 0x0F ); |
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1590 emit_byte( 0xAE ); |
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1591 emit_byte( 0xF0 ); |
| 304 | 1592 } |
| 1593 | |
| 1594 void Assembler::mov(Register dst, Register src) { | |
| 1595 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
| 1596 } | |
| 1597 | |
| 1598 void Assembler::movapd(XMMRegister dst, XMMRegister src) { | |
| 1599 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 1600 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); |
| 304 | 1601 emit_byte(0x28); |
| 4759 | 1602 emit_byte(0xC0 | encode); |
| 304 | 1603 } |
| 1604 | |
| 1605 void Assembler::movaps(XMMRegister dst, XMMRegister src) { | |
| 1606 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 4759 | 1607 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE); |
| 304 | 1608 emit_byte(0x28); |
| 4759 | 1609 emit_byte(0xC0 | encode); |
| 304 | 1610 } |
| 1611 | |
| 1612 void Assembler::movb(Register dst, Address src) { | |
| 1613 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); | |
| 1614 InstructionMark im(this); | |
| 1615 prefix(src, dst, true); | |
| 1616 emit_byte(0x8A); | |
| 1617 emit_operand(dst, src); | |
| 1618 } | |
| 1619 | |
| 1620 | |
| 1621 void Assembler::movb(Address dst, int imm8) { | |
| 1622 InstructionMark im(this); | |
| 1623 prefix(dst); | |
| 1624 emit_byte(0xC6); | |
| 1625 emit_operand(rax, dst, 1); | |
| 1626 emit_byte(imm8); | |
| 1627 } | |
| 1628 | |
| 1629 | |
| 1630 void Assembler::movb(Address dst, Register src) { | |
| 1631 assert(src->has_byte_register(), "must have byte register"); | |
| 1632 InstructionMark im(this); | |
| 1633 prefix(dst, src, true); | |
| 1634 emit_byte(0x88); | |
| 1635 emit_operand(src, dst); | |
| 1636 } | |
| 1637 | |
| 1638 void Assembler::movdl(XMMRegister dst, Register src) { | |
| 1639 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 1640 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); |
| 304 | 1641 emit_byte(0x6E); |
| 1642 emit_byte(0xC0 | encode); | |
| 1643 } | |
| 1644 | |
| 1645 void Assembler::movdl(Register dst, XMMRegister src) { | |
| 1646 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1647 // swap src/dst to get correct prefix | |
| 4759 | 1648 int encode = simd_prefix_and_encode(src, dst, VEX_SIMD_66); |
| 304 | 1649 emit_byte(0x7E); |
| 1650 emit_byte(0xC0 | encode); | |
| 1651 } | |
| 1652 | |
|
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1653 void Assembler::movdl(XMMRegister dst, Address src) { |
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1654 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
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1655 InstructionMark im(this); |
| 4759 | 1656 simd_prefix(dst, src, VEX_SIMD_66); |
|
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1657 emit_byte(0x6E); |
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1658 emit_operand(dst, src); |
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1659 } |
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1660 |
| 304 | 1661 void Assembler::movdqa(XMMRegister dst, XMMRegister src) { |
| 1662 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 1663 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); |
| 304 | 1664 emit_byte(0x6F); |
| 1665 emit_byte(0xC0 | encode); | |
| 1666 } | |
| 1667 | |
| 405 | 1668 void Assembler::movdqu(XMMRegister dst, Address src) { |
| 1669 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1670 InstructionMark im(this); | |
| 4759 | 1671 simd_prefix(dst, src, VEX_SIMD_F3); |
| 405 | 1672 emit_byte(0x6F); |
| 1673 emit_operand(dst, src); | |
| 1674 } | |
| 1675 | |
| 1676 void Assembler::movdqu(XMMRegister dst, XMMRegister src) { | |
| 1677 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 1678 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3); |
| 405 | 1679 emit_byte(0x6F); |
| 1680 emit_byte(0xC0 | encode); | |
| 1681 } | |
| 1682 | |
| 1683 void Assembler::movdqu(Address dst, XMMRegister src) { | |
| 1684 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1685 InstructionMark im(this); | |
| 4759 | 1686 simd_prefix(dst, src, VEX_SIMD_F3); |
| 405 | 1687 emit_byte(0x7F); |
| 1688 emit_operand(src, dst); | |
| 1689 } | |
| 1690 | |
| 304 | 1691 // Uses zero extension on 64bit |
| 1692 | |
| 1693 void Assembler::movl(Register dst, int32_t imm32) { | |
| 1694 int encode = prefix_and_encode(dst->encoding()); | |
| 1695 emit_byte(0xB8 | encode); | |
| 1696 emit_long(imm32); | |
| 1697 } | |
| 1698 | |
| 1699 void Assembler::movl(Register dst, Register src) { | |
| 1700 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1701 emit_byte(0x8B); | |
| 1702 emit_byte(0xC0 | encode); | |
| 1703 } | |
| 1704 | |
| 1705 void Assembler::movl(Register dst, Address src) { | |
| 1706 InstructionMark im(this); | |
| 1707 prefix(src, dst); | |
| 1708 emit_byte(0x8B); | |
| 1709 emit_operand(dst, src); | |
| 1710 } | |
| 1711 | |
| 1712 void Assembler::movl(Address dst, int32_t imm32) { | |
| 1713 InstructionMark im(this); | |
| 1714 prefix(dst); | |
| 1715 emit_byte(0xC7); | |
| 1716 emit_operand(rax, dst, 4); | |
| 1717 emit_long(imm32); | |
| 1718 } | |
| 1719 | |
| 1720 void Assembler::movl(Address dst, Register src) { | |
| 1721 InstructionMark im(this); | |
| 1722 prefix(dst, src); | |
| 1723 emit_byte(0x89); | |
| 1724 emit_operand(src, dst); | |
| 1725 } | |
| 1726 | |
| 1727 // New cpus require to use movsd and movss to avoid partial register stall | |
| 1728 // when loading from memory. But for old Opteron use movlpd instead of movsd. | |
| 1729 // The selection is done in MacroAssembler::movdbl() and movflt(). | |
| 1730 void Assembler::movlpd(XMMRegister dst, Address src) { | |
| 1731 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1732 InstructionMark im(this); | |
| 4759 | 1733 simd_prefix(dst, dst, src, VEX_SIMD_66); |
| 304 | 1734 emit_byte(0x12); |
| 1735 emit_operand(dst, src); | |
| 1736 } | |
| 1737 | |
| 1738 void Assembler::movq( MMXRegister dst, Address src ) { | |
| 1739 assert( VM_Version::supports_mmx(), "" ); | |
| 1740 emit_byte(0x0F); | |
| 1741 emit_byte(0x6F); | |
| 1742 emit_operand(dst, src); | |
| 1743 } | |
| 1744 | |
| 1745 void Assembler::movq( Address dst, MMXRegister src ) { | |
| 1746 assert( VM_Version::supports_mmx(), "" ); | |
| 1747 emit_byte(0x0F); | |
| 1748 emit_byte(0x7F); | |
| 1749 // workaround gcc (3.2.1-7a) bug | |
| 1750 // In that version of gcc with only an emit_operand(MMX, Address) | |
| 1751 // gcc will tail jump and try and reverse the parameters completely | |
| 1752 // obliterating dst in the process. By having a version available | |
| 1753 // that doesn't need to swap the args at the tail jump the bug is | |
| 1754 // avoided. | |
| 1755 emit_operand(dst, src); | |
| 1756 } | |
| 1757 | |
| 1758 void Assembler::movq(XMMRegister dst, Address src) { | |
| 1759 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1760 InstructionMark im(this); | |
| 4759 | 1761 simd_prefix(dst, src, VEX_SIMD_F3); |
| 304 | 1762 emit_byte(0x7E); |
| 1763 emit_operand(dst, src); | |
| 1764 } | |
| 1765 | |
| 1766 void Assembler::movq(Address dst, XMMRegister src) { | |
| 1767 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1768 InstructionMark im(this); | |
| 4759 | 1769 simd_prefix(dst, src, VEX_SIMD_66); |
| 304 | 1770 emit_byte(0xD6); |
| 1771 emit_operand(src, dst); | |
| 1772 } | |
| 1773 | |
| 1774 void Assembler::movsbl(Register dst, Address src) { // movsxb | |
| 1775 InstructionMark im(this); | |
| 1776 prefix(src, dst); | |
| 1777 emit_byte(0x0F); | |
| 1778 emit_byte(0xBE); | |
| 1779 emit_operand(dst, src); | |
| 1780 } | |
| 1781 | |
| 1782 void Assembler::movsbl(Register dst, Register src) { // movsxb | |
| 1783 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); | |
| 1784 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true); | |
| 1785 emit_byte(0x0F); | |
| 1786 emit_byte(0xBE); | |
| 1787 emit_byte(0xC0 | encode); | |
| 1788 } | |
| 1789 | |
| 1790 void Assembler::movsd(XMMRegister dst, XMMRegister src) { | |
| 1791 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 1792 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
| 304 | 1793 emit_byte(0x10); |
| 1794 emit_byte(0xC0 | encode); | |
| 1795 } | |
| 1796 | |
| 1797 void Assembler::movsd(XMMRegister dst, Address src) { | |
| 1798 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1799 InstructionMark im(this); | |
| 4759 | 1800 simd_prefix(dst, src, VEX_SIMD_F2); |
| 304 | 1801 emit_byte(0x10); |
| 1802 emit_operand(dst, src); | |
| 1803 } | |
| 1804 | |
| 1805 void Assembler::movsd(Address dst, XMMRegister src) { | |
| 1806 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1807 InstructionMark im(this); | |
| 4759 | 1808 simd_prefix(dst, src, VEX_SIMD_F2); |
| 304 | 1809 emit_byte(0x11); |
| 1810 emit_operand(src, dst); | |
| 1811 } | |
| 1812 | |
| 1813 void Assembler::movss(XMMRegister dst, XMMRegister src) { | |
| 1814 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 4759 | 1815 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); |
| 304 | 1816 emit_byte(0x10); |
| 1817 emit_byte(0xC0 | encode); | |
| 1818 } | |
| 1819 | |
| 1820 void Assembler::movss(XMMRegister dst, Address src) { | |
| 1821 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1822 InstructionMark im(this); | |
| 4759 | 1823 simd_prefix(dst, src, VEX_SIMD_F3); |
| 304 | 1824 emit_byte(0x10); |
| 1825 emit_operand(dst, src); | |
| 1826 } | |
| 1827 | |
| 1828 void Assembler::movss(Address dst, XMMRegister src) { | |
| 1829 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1830 InstructionMark im(this); | |
| 4759 | 1831 simd_prefix(dst, src, VEX_SIMD_F3); |
| 304 | 1832 emit_byte(0x11); |
| 1833 emit_operand(src, dst); | |
| 1834 } | |
| 1835 | |
| 1836 void Assembler::movswl(Register dst, Address src) { // movsxw | |
| 1837 InstructionMark im(this); | |
| 1838 prefix(src, dst); | |
| 1839 emit_byte(0x0F); | |
| 1840 emit_byte(0xBF); | |
| 1841 emit_operand(dst, src); | |
| 1842 } | |
| 1843 | |
| 1844 void Assembler::movswl(Register dst, Register src) { // movsxw | |
| 1845 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1846 emit_byte(0x0F); | |
| 1847 emit_byte(0xBF); | |
| 1848 emit_byte(0xC0 | encode); | |
| 1849 } | |
| 1850 | |
| 1851 void Assembler::movw(Address dst, int imm16) { | |
| 1852 InstructionMark im(this); | |
| 1853 | |
| 1854 emit_byte(0x66); // switch to 16-bit mode | |
| 1855 prefix(dst); | |
| 1856 emit_byte(0xC7); | |
| 1857 emit_operand(rax, dst, 2); | |
| 1858 emit_word(imm16); | |
| 1859 } | |
| 1860 | |
| 1861 void Assembler::movw(Register dst, Address src) { | |
| 1862 InstructionMark im(this); | |
| 1863 emit_byte(0x66); | |
| 1864 prefix(src, dst); | |
| 1865 emit_byte(0x8B); | |
| 1866 emit_operand(dst, src); | |
| 1867 } | |
| 1868 | |
| 1869 void Assembler::movw(Address dst, Register src) { | |
| 1870 InstructionMark im(this); | |
| 1871 emit_byte(0x66); | |
| 1872 prefix(dst, src); | |
| 1873 emit_byte(0x89); | |
| 1874 emit_operand(src, dst); | |
| 1875 } | |
| 1876 | |
| 1877 void Assembler::movzbl(Register dst, Address src) { // movzxb | |
| 1878 InstructionMark im(this); | |
| 1879 prefix(src, dst); | |
| 1880 emit_byte(0x0F); | |
| 1881 emit_byte(0xB6); | |
| 1882 emit_operand(dst, src); | |
| 1883 } | |
| 1884 | |
| 1885 void Assembler::movzbl(Register dst, Register src) { // movzxb | |
| 1886 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); | |
| 1887 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true); | |
| 1888 emit_byte(0x0F); | |
| 1889 emit_byte(0xB6); | |
| 1890 emit_byte(0xC0 | encode); | |
| 1891 } | |
| 1892 | |
| 1893 void Assembler::movzwl(Register dst, Address src) { // movzxw | |
| 1894 InstructionMark im(this); | |
| 1895 prefix(src, dst); | |
| 1896 emit_byte(0x0F); | |
| 1897 emit_byte(0xB7); | |
| 1898 emit_operand(dst, src); | |
| 1899 } | |
| 1900 | |
| 1901 void Assembler::movzwl(Register dst, Register src) { // movzxw | |
| 1902 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1903 emit_byte(0x0F); | |
| 1904 emit_byte(0xB7); | |
| 1905 emit_byte(0xC0 | encode); | |
| 1906 } | |
| 1907 | |
| 1908 void Assembler::mull(Address src) { | |
| 1909 InstructionMark im(this); | |
| 1910 prefix(src); | |
| 1911 emit_byte(0xF7); | |
| 1912 emit_operand(rsp, src); | |
| 1913 } | |
| 1914 | |
| 1915 void Assembler::mull(Register src) { | |
| 1916 int encode = prefix_and_encode(src->encoding()); | |
| 1917 emit_byte(0xF7); | |
| 1918 emit_byte(0xE0 | encode); | |
| 1919 } | |
| 1920 | |
| 1921 void Assembler::mulsd(XMMRegister dst, Address src) { | |
| 1922 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1923 InstructionMark im(this); | |
| 4759 | 1924 simd_prefix(dst, dst, src, VEX_SIMD_F2); |
| 304 | 1925 emit_byte(0x59); |
| 1926 emit_operand(dst, src); | |
| 1927 } | |
| 1928 | |
| 1929 void Assembler::mulsd(XMMRegister dst, XMMRegister src) { | |
| 1930 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 1931 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
| 304 | 1932 emit_byte(0x59); |
| 1933 emit_byte(0xC0 | encode); | |
| 1934 } | |
| 1935 | |
| 1936 void Assembler::mulss(XMMRegister dst, Address src) { | |
| 1937 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1938 InstructionMark im(this); | |
| 4759 | 1939 simd_prefix(dst, dst, src, VEX_SIMD_F3); |
| 304 | 1940 emit_byte(0x59); |
| 1941 emit_operand(dst, src); | |
| 1942 } | |
| 1943 | |
| 1944 void Assembler::mulss(XMMRegister dst, XMMRegister src) { | |
| 1945 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 4759 | 1946 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); |
| 304 | 1947 emit_byte(0x59); |
| 1948 emit_byte(0xC0 | encode); | |
| 1949 } | |
| 1950 | |
| 1951 void Assembler::negl(Register dst) { | |
| 1952 int encode = prefix_and_encode(dst->encoding()); | |
| 1953 emit_byte(0xF7); | |
| 1954 emit_byte(0xD8 | encode); | |
| 1955 } | |
| 1956 | |
| 0 | 1957 void Assembler::nop(int i) { |
| 304 | 1958 #ifdef ASSERT |
| 0 | 1959 assert(i > 0, " "); |
| 304 | 1960 // The fancy nops aren't currently recognized by debuggers making it a |
| 1961 // pain to disassemble code while debugging. If asserts are on clearly | |
| 1962 // speed is not an issue so simply use the single byte traditional nop | |
| 1963 // to do alignment. | |
| 1964 | |
| 1965 for (; i > 0 ; i--) emit_byte(0x90); | |
| 1966 return; | |
| 1967 | |
| 1968 #endif // ASSERT | |
| 1969 | |
| 0 | 1970 if (UseAddressNop && VM_Version::is_intel()) { |
| 1971 // | |
| 1972 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel | |
| 1973 // 1: 0x90 | |
| 1974 // 2: 0x66 0x90 | |
| 1975 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) | |
| 1976 // 4: 0x0F 0x1F 0x40 0x00 | |
| 1977 // 5: 0x0F 0x1F 0x44 0x00 0x00 | |
| 1978 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
| 1979 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
| 1980 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 1981 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 1982 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 1983 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 1984 | |
| 1985 // The rest coding is Intel specific - don't use consecutive address nops | |
| 1986 | |
| 1987 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
| 1988 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
| 1989 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
| 1990 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
| 1991 | |
| 1992 while(i >= 15) { | |
| 1993 // For Intel don't generate consecutive addess nops (mix with regular nops) | |
| 1994 i -= 15; | |
| 1995 emit_byte(0x66); // size prefix | |
| 1996 emit_byte(0x66); // size prefix | |
| 1997 emit_byte(0x66); // size prefix | |
| 1998 addr_nop_8(); | |
| 1999 emit_byte(0x66); // size prefix | |
| 2000 emit_byte(0x66); // size prefix | |
| 2001 emit_byte(0x66); // size prefix | |
| 2002 emit_byte(0x90); // nop | |
| 2003 } | |
| 2004 switch (i) { | |
| 2005 case 14: | |
| 2006 emit_byte(0x66); // size prefix | |
| 2007 case 13: | |
| 2008 emit_byte(0x66); // size prefix | |
| 2009 case 12: | |
| 2010 addr_nop_8(); | |
| 2011 emit_byte(0x66); // size prefix | |
| 2012 emit_byte(0x66); // size prefix | |
| 2013 emit_byte(0x66); // size prefix | |
| 2014 emit_byte(0x90); // nop | |
| 2015 break; | |
| 2016 case 11: | |
| 2017 emit_byte(0x66); // size prefix | |
| 2018 case 10: | |
| 2019 emit_byte(0x66); // size prefix | |
| 2020 case 9: | |
| 2021 emit_byte(0x66); // size prefix | |
| 2022 case 8: | |
| 2023 addr_nop_8(); | |
| 2024 break; | |
| 2025 case 7: | |
| 2026 addr_nop_7(); | |
| 2027 break; | |
| 2028 case 6: | |
| 2029 emit_byte(0x66); // size prefix | |
| 2030 case 5: | |
| 2031 addr_nop_5(); | |
| 2032 break; | |
| 2033 case 4: | |
| 2034 addr_nop_4(); | |
| 2035 break; | |
| 2036 case 3: | |
| 2037 // Don't use "0x0F 0x1F 0x00" - need patching safe padding | |
| 2038 emit_byte(0x66); // size prefix | |
| 2039 case 2: | |
| 2040 emit_byte(0x66); // size prefix | |
| 2041 case 1: | |
| 2042 emit_byte(0x90); // nop | |
| 2043 break; | |
| 2044 default: | |
| 2045 assert(i == 0, " "); | |
| 2046 } | |
| 2047 return; | |
| 2048 } | |
| 2049 if (UseAddressNop && VM_Version::is_amd()) { | |
| 2050 // | |
| 2051 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD. | |
| 2052 // 1: 0x90 | |
| 2053 // 2: 0x66 0x90 | |
| 2054 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) | |
| 2055 // 4: 0x0F 0x1F 0x40 0x00 | |
| 2056 // 5: 0x0F 0x1F 0x44 0x00 0x00 | |
| 2057 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
| 2058 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
| 2059 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 2060 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 2061 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 2062 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 2063 | |
| 2064 // The rest coding is AMD specific - use consecutive address nops | |
| 2065 | |
| 2066 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
| 2067 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
| 2068 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
| 2069 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
| 2070 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 2071 // Size prefixes (0x66) are added for larger sizes | |
| 2072 | |
| 2073 while(i >= 22) { | |
| 2074 i -= 11; | |
| 2075 emit_byte(0x66); // size prefix | |
| 2076 emit_byte(0x66); // size prefix | |
| 2077 emit_byte(0x66); // size prefix | |
| 2078 addr_nop_8(); | |
| 2079 } | |
| 2080 // Generate first nop for size between 21-12 | |
| 2081 switch (i) { | |
| 2082 case 21: | |
| 2083 i -= 1; | |
| 2084 emit_byte(0x66); // size prefix | |
| 2085 case 20: | |
| 2086 case 19: | |
| 2087 i -= 1; | |
| 2088 emit_byte(0x66); // size prefix | |
| 2089 case 18: | |
| 2090 case 17: | |
| 2091 i -= 1; | |
| 2092 emit_byte(0x66); // size prefix | |
| 2093 case 16: | |
| 2094 case 15: | |
| 2095 i -= 8; | |
| 2096 addr_nop_8(); | |
| 2097 break; | |
| 2098 case 14: | |
| 2099 case 13: | |
| 2100 i -= 7; | |
| 2101 addr_nop_7(); | |
| 2102 break; | |
| 2103 case 12: | |
| 2104 i -= 6; | |
| 2105 emit_byte(0x66); // size prefix | |
| 2106 addr_nop_5(); | |
| 2107 break; | |
| 2108 default: | |
| 2109 assert(i < 12, " "); | |
| 2110 } | |
| 2111 | |
| 2112 // Generate second nop for size between 11-1 | |
| 2113 switch (i) { | |
| 2114 case 11: | |
| 2115 emit_byte(0x66); // size prefix | |
| 2116 case 10: | |
| 2117 emit_byte(0x66); // size prefix | |
| 2118 case 9: | |
| 2119 emit_byte(0x66); // size prefix | |
| 2120 case 8: | |
| 2121 addr_nop_8(); | |
| 2122 break; | |
| 2123 case 7: | |
| 2124 addr_nop_7(); | |
| 2125 break; | |
| 2126 case 6: | |
| 2127 emit_byte(0x66); // size prefix | |
| 2128 case 5: | |
| 2129 addr_nop_5(); | |
| 2130 break; | |
| 2131 case 4: | |
| 2132 addr_nop_4(); | |
| 2133 break; | |
| 2134 case 3: | |
| 2135 // Don't use "0x0F 0x1F 0x00" - need patching safe padding | |
| 2136 emit_byte(0x66); // size prefix | |
| 2137 case 2: | |
| 2138 emit_byte(0x66); // size prefix | |
| 2139 case 1: | |
| 2140 emit_byte(0x90); // nop | |
| 2141 break; | |
| 2142 default: | |
| 2143 assert(i == 0, " "); | |
| 2144 } | |
| 2145 return; | |
| 2146 } | |
| 2147 | |
| 2148 // Using nops with size prefixes "0x66 0x90". | |
| 2149 // From AMD Optimization Guide: | |
| 2150 // 1: 0x90 | |
| 2151 // 2: 0x66 0x90 | |
| 2152 // 3: 0x66 0x66 0x90 | |
| 2153 // 4: 0x66 0x66 0x66 0x90 | |
| 2154 // 5: 0x66 0x66 0x90 0x66 0x90 | |
| 2155 // 6: 0x66 0x66 0x90 0x66 0x66 0x90 | |
| 2156 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 | |
| 2157 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90 | |
| 2158 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 | |
| 2159 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 | |
| 2160 // | |
| 2161 while(i > 12) { | |
| 2162 i -= 4; | |
| 2163 emit_byte(0x66); // size prefix | |
| 2164 emit_byte(0x66); | |
| 2165 emit_byte(0x66); | |
| 2166 emit_byte(0x90); // nop | |
| 2167 } | |
| 2168 // 1 - 12 nops | |
| 2169 if(i > 8) { | |
| 2170 if(i > 9) { | |
| 2171 i -= 1; | |
| 2172 emit_byte(0x66); | |
| 2173 } | |
| 2174 i -= 3; | |
| 2175 emit_byte(0x66); | |
| 2176 emit_byte(0x66); | |
| 2177 emit_byte(0x90); | |
| 2178 } | |
| 2179 // 1 - 8 nops | |
| 2180 if(i > 4) { | |
| 2181 if(i > 6) { | |
| 2182 i -= 1; | |
| 2183 emit_byte(0x66); | |
| 2184 } | |
| 2185 i -= 3; | |
| 2186 emit_byte(0x66); | |
| 2187 emit_byte(0x66); | |
| 2188 emit_byte(0x90); | |
| 2189 } | |
| 2190 switch (i) { | |
| 2191 case 4: | |
| 2192 emit_byte(0x66); | |
| 2193 case 3: | |
| 2194 emit_byte(0x66); | |
| 2195 case 2: | |
| 2196 emit_byte(0x66); | |
| 2197 case 1: | |
| 2198 emit_byte(0x90); | |
| 2199 break; | |
| 2200 default: | |
| 2201 assert(i == 0, " "); | |
| 2202 } | |
| 2203 } | |
| 2204 | |
| 304 | 2205 void Assembler::notl(Register dst) { |
| 2206 int encode = prefix_and_encode(dst->encoding()); | |
| 2207 emit_byte(0xF7); | |
| 2208 emit_byte(0xD0 | encode ); | |
| 2209 } | |
| 2210 | |
| 2211 void Assembler::orl(Address dst, int32_t imm32) { | |
| 2212 InstructionMark im(this); | |
| 2213 prefix(dst); | |
|
2100
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
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changeset
|
2214 emit_arith_operand(0x81, rcx, dst, imm32); |
| 304 | 2215 } |
| 2216 | |
| 2217 void Assembler::orl(Register dst, int32_t imm32) { | |
| 2218 prefix(dst); | |
| 2219 emit_arith(0x81, 0xC8, dst, imm32); | |
| 2220 } | |
| 2221 | |
| 2222 void Assembler::orl(Register dst, Address src) { | |
| 2223 InstructionMark im(this); | |
| 2224 prefix(src, dst); | |
| 2225 emit_byte(0x0B); | |
| 2226 emit_operand(dst, src); | |
| 2227 } | |
| 2228 | |
| 2229 void Assembler::orl(Register dst, Register src) { | |
| 2230 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2231 emit_arith(0x0B, 0xC0, dst, src); | |
| 2232 } | |
| 2233 | |
| 4759 | 2234 void Assembler::packuswb(XMMRegister dst, Address src) { |
| 2235 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2236 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); | |
| 2237 InstructionMark im(this); | |
| 2238 simd_prefix(dst, dst, src, VEX_SIMD_66); | |
| 2239 emit_byte(0x67); | |
| 2240 emit_operand(dst, src); | |
| 2241 } | |
| 2242 | |
| 2243 void Assembler::packuswb(XMMRegister dst, XMMRegister src) { | |
| 2244 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2245 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); | |
| 2246 emit_byte(0x67); | |
| 2247 emit_byte(0xC0 | encode); | |
| 2248 } | |
| 2249 | |
| 681 | 2250 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) { |
| 2251 assert(VM_Version::supports_sse4_2(), ""); | |
| 4759 | 2252 InstructionMark im(this); |
| 2253 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A); | |
| 681 | 2254 emit_byte(0x61); |
| 2255 emit_operand(dst, src); | |
| 2256 emit_byte(imm8); | |
| 2257 } | |
| 2258 | |
| 2259 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) { | |
| 2260 assert(VM_Version::supports_sse4_2(), ""); | |
| 4759 | 2261 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A); |
| 681 | 2262 emit_byte(0x61); |
| 2263 emit_byte(0xC0 | encode); | |
| 2264 emit_byte(imm8); | |
| 2265 } | |
| 2266 | |
| 4759 | 2267 void Assembler::pmovzxbw(XMMRegister dst, Address src) { |
| 2268 assert(VM_Version::supports_sse4_1(), ""); | |
| 2269 InstructionMark im(this); | |
| 2270 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
| 2271 emit_byte(0x30); | |
| 2272 emit_operand(dst, src); | |
| 2273 } | |
| 2274 | |
| 2275 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) { | |
| 2276 assert(VM_Version::supports_sse4_1(), ""); | |
| 2277 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
| 2278 emit_byte(0x30); | |
| 2279 emit_byte(0xC0 | encode); | |
| 2280 } | |
| 2281 | |
| 304 | 2282 // generic |
| 2283 void Assembler::pop(Register dst) { | |
| 2284 int encode = prefix_and_encode(dst->encoding()); | |
| 2285 emit_byte(0x58 | encode); | |
| 2286 } | |
| 2287 | |
|
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2288 void Assembler::popcntl(Register dst, Address src) { |
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2289 assert(VM_Version::supports_popcnt(), "must support"); |
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2290 InstructionMark im(this); |
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2291 emit_byte(0xF3); |
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2292 prefix(src, dst); |
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2293 emit_byte(0x0F); |
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2294 emit_byte(0xB8); |
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2295 emit_operand(dst, src); |
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2296 } |
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2297 |
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2298 void Assembler::popcntl(Register dst, Register src) { |
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2299 assert(VM_Version::supports_popcnt(), "must support"); |
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2300 emit_byte(0xF3); |
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2301 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
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2302 emit_byte(0x0F); |
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2303 emit_byte(0xB8); |
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2304 emit_byte(0xC0 | encode); |
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2305 } |
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2306 |
| 304 | 2307 void Assembler::popf() { |
| 2308 emit_byte(0x9D); | |
| 2309 } | |
| 2310 | |
| 1060 | 2311 #ifndef _LP64 // no 32bit push/pop on amd64 |
| 304 | 2312 void Assembler::popl(Address dst) { |
| 2313 // NOTE: this will adjust stack by 8byte on 64bits | |
| 2314 InstructionMark im(this); | |
| 2315 prefix(dst); | |
| 2316 emit_byte(0x8F); | |
| 2317 emit_operand(rax, dst); | |
| 2318 } | |
| 1060 | 2319 #endif |
| 304 | 2320 |
| 2321 void Assembler::prefetch_prefix(Address src) { | |
| 2322 prefix(src); | |
| 2323 emit_byte(0x0F); | |
| 2324 } | |
| 2325 | |
| 2326 void Assembler::prefetchnta(Address src) { | |
|
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2327 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); |
| 304 | 2328 InstructionMark im(this); |
| 2329 prefetch_prefix(src); | |
| 2330 emit_byte(0x18); | |
| 2331 emit_operand(rax, src); // 0, src | |
| 2332 } | |
| 2333 | |
| 2334 void Assembler::prefetchr(Address src) { | |
| 3854 | 2335 assert(VM_Version::supports_3dnow_prefetch(), "must support"); |
| 304 | 2336 InstructionMark im(this); |
| 2337 prefetch_prefix(src); | |
| 2338 emit_byte(0x0D); | |
| 2339 emit_operand(rax, src); // 0, src | |
| 2340 } | |
| 2341 | |
| 2342 void Assembler::prefetcht0(Address src) { | |
| 2343 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |
| 2344 InstructionMark im(this); | |
| 2345 prefetch_prefix(src); | |
| 2346 emit_byte(0x18); | |
| 2347 emit_operand(rcx, src); // 1, src | |
| 2348 } | |
| 2349 | |
| 2350 void Assembler::prefetcht1(Address src) { | |
| 2351 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |
| 2352 InstructionMark im(this); | |
| 2353 prefetch_prefix(src); | |
| 2354 emit_byte(0x18); | |
| 2355 emit_operand(rdx, src); // 2, src | |
| 2356 } | |
| 2357 | |
| 2358 void Assembler::prefetcht2(Address src) { | |
| 2359 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |
| 2360 InstructionMark im(this); | |
| 2361 prefetch_prefix(src); | |
| 2362 emit_byte(0x18); | |
| 2363 emit_operand(rbx, src); // 3, src | |
| 2364 } | |
| 2365 | |
| 2366 void Assembler::prefetchw(Address src) { | |
| 3854 | 2367 assert(VM_Version::supports_3dnow_prefetch(), "must support"); |
| 304 | 2368 InstructionMark im(this); |
| 2369 prefetch_prefix(src); | |
| 2370 emit_byte(0x0D); | |
| 2371 emit_operand(rcx, src); // 1, src | |
| 2372 } | |
| 2373 | |
| 2374 void Assembler::prefix(Prefix p) { | |
| 2375 a_byte(p); | |
| 2376 } | |
| 2377 | |
| 2262 | 2378 void Assembler::por(XMMRegister dst, XMMRegister src) { |
| 2379 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 2380 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); |
| 2262 | 2381 emit_byte(0xEB); |
| 2382 emit_byte(0xC0 | encode); | |
| 2383 } | |
| 2384 | |
| 4759 | 2385 void Assembler::por(XMMRegister dst, Address src) { |
| 2386 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2387 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); | |
| 2388 InstructionMark im(this); | |
| 2389 simd_prefix(dst, dst, src, VEX_SIMD_66); | |
| 2390 emit_byte(0xEB); | |
| 2391 emit_operand(dst, src); | |
| 2392 } | |
| 2393 | |
| 304 | 2394 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) { |
| 2395 assert(isByte(mode), "invalid value"); | |
| 2396 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 2397 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); |
| 304 | 2398 emit_byte(0x70); |
| 2399 emit_byte(0xC0 | encode); | |
| 2400 emit_byte(mode & 0xFF); | |
| 2401 | |
| 2402 } | |
| 2403 | |
| 2404 void Assembler::pshufd(XMMRegister dst, Address src, int mode) { | |
| 2405 assert(isByte(mode), "invalid value"); | |
| 2406 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 2407 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
| 2408 InstructionMark im(this); | |
| 2409 simd_prefix(dst, src, VEX_SIMD_66); | |
| 304 | 2410 emit_byte(0x70); |
| 2411 emit_operand(dst, src); | |
| 2412 emit_byte(mode & 0xFF); | |
| 2413 } | |
| 2414 | |
| 2415 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) { | |
| 2416 assert(isByte(mode), "invalid value"); | |
| 2417 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 2418 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2); |
| 304 | 2419 emit_byte(0x70); |
| 2420 emit_byte(0xC0 | encode); | |
| 2421 emit_byte(mode & 0xFF); | |
| 2422 } | |
| 2423 | |
| 2424 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) { | |
| 2425 assert(isByte(mode), "invalid value"); | |
| 2426 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 2427 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
| 2428 InstructionMark im(this); | |
| 2429 simd_prefix(dst, src, VEX_SIMD_F2); | |
| 304 | 2430 emit_byte(0x70); |
| 2431 emit_operand(dst, src); | |
| 2432 emit_byte(mode & 0xFF); | |
| 2433 } | |
| 2434 | |
| 2435 void Assembler::psrlq(XMMRegister dst, int shift) { | |
|
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2436 // Shift 64 bit value logically right by specified number of bits. |
|
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2437 // HMM Table D-1 says sse2 or mmx. |
|
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2438 // Do not confuse it with psrldq SSE2 instruction which |
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2439 // shifts 128 bit value in xmm register by number of bytes. |
| 4759 | 2440 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
| 2441 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66); | |
| 304 | 2442 emit_byte(0x73); |
| 2443 emit_byte(0xC0 | encode); | |
| 2444 emit_byte(shift); | |
| 2445 } | |
| 2446 | |
|
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2447 void Assembler::psrldq(XMMRegister dst, int shift) { |
|
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2448 // Shift 128 bit value in xmm register by number of bytes. |
|
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2449 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
| 4759 | 2450 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66); |
|
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2451 emit_byte(0x73); |
|
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2452 emit_byte(0xC0 | encode); |
|
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2453 emit_byte(shift); |
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2454 } |
|
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2455 |
| 681 | 2456 void Assembler::ptest(XMMRegister dst, Address src) { |
| 2457 assert(VM_Version::supports_sse4_1(), ""); | |
| 4759 | 2458 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
| 2459 InstructionMark im(this); | |
| 2460 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
| 681 | 2461 emit_byte(0x17); |
| 2462 emit_operand(dst, src); | |
| 2463 } | |
| 2464 | |
| 2465 void Assembler::ptest(XMMRegister dst, XMMRegister src) { | |
| 2466 assert(VM_Version::supports_sse4_1(), ""); | |
| 4759 | 2467 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
| 681 | 2468 emit_byte(0x17); |
| 2469 emit_byte(0xC0 | encode); | |
| 2470 } | |
| 2471 | |
| 4759 | 2472 void Assembler::punpcklbw(XMMRegister dst, Address src) { |
| 2473 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2474 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); | |
| 2475 InstructionMark im(this); | |
| 2476 simd_prefix(dst, dst, src, VEX_SIMD_66); | |
| 2477 emit_byte(0x60); | |
| 2478 emit_operand(dst, src); | |
| 2479 } | |
| 2480 | |
| 304 | 2481 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) { |
| 2482 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 2483 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); |
| 304 | 2484 emit_byte(0x60); |
| 2485 emit_byte(0xC0 | encode); | |
| 2486 } | |
| 2487 | |
| 4759 | 2488 void Assembler::punpckldq(XMMRegister dst, Address src) { |
| 2489 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2490 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); | |
| 2491 InstructionMark im(this); | |
| 2492 simd_prefix(dst, dst, src, VEX_SIMD_66); | |
| 2493 emit_byte(0x62); | |
| 2494 emit_operand(dst, src); | |
| 2495 } | |
| 2496 | |
| 2497 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) { | |
| 2498 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2499 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); | |
| 2500 emit_byte(0x62); | |
| 2501 emit_byte(0xC0 | encode); | |
| 2502 } | |
| 2503 | |
| 304 | 2504 void Assembler::push(int32_t imm32) { |
| 2505 // in 64bits we push 64bits onto the stack but only | |
| 2506 // take a 32bit immediate | |
| 2507 emit_byte(0x68); | |
| 2508 emit_long(imm32); | |
| 2509 } | |
| 2510 | |
| 2511 void Assembler::push(Register src) { | |
| 2512 int encode = prefix_and_encode(src->encoding()); | |
| 2513 | |
| 2514 emit_byte(0x50 | encode); | |
| 2515 } | |
| 2516 | |
| 2517 void Assembler::pushf() { | |
| 2518 emit_byte(0x9C); | |
| 2519 } | |
| 2520 | |
| 1060 | 2521 #ifndef _LP64 // no 32bit push/pop on amd64 |
| 304 | 2522 void Assembler::pushl(Address src) { |
| 2523 // Note this will push 64bit on 64bit | |
| 2524 InstructionMark im(this); | |
| 2525 prefix(src); | |
| 2526 emit_byte(0xFF); | |
| 2527 emit_operand(rsi, src); | |
| 2528 } | |
| 1060 | 2529 #endif |
| 304 | 2530 |
| 2531 void Assembler::pxor(XMMRegister dst, Address src) { | |
| 2532 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 2533 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
| 2534 InstructionMark im(this); | |
| 2535 simd_prefix(dst, dst, src, VEX_SIMD_66); | |
| 304 | 2536 emit_byte(0xEF); |
| 2537 emit_operand(dst, src); | |
| 2538 } | |
| 2539 | |
| 2540 void Assembler::pxor(XMMRegister dst, XMMRegister src) { | |
| 2541 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 2542 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); |
| 304 | 2543 emit_byte(0xEF); |
| 2544 emit_byte(0xC0 | encode); | |
| 2545 } | |
| 2546 | |
| 2547 void Assembler::rcll(Register dst, int imm8) { | |
| 2548 assert(isShiftCount(imm8), "illegal shift count"); | |
| 2549 int encode = prefix_and_encode(dst->encoding()); | |
| 2550 if (imm8 == 1) { | |
| 2551 emit_byte(0xD1); | |
| 2552 emit_byte(0xD0 | encode); | |
| 2553 } else { | |
| 2554 emit_byte(0xC1); | |
| 2555 emit_byte(0xD0 | encode); | |
| 2556 emit_byte(imm8); | |
| 2557 } | |
| 2558 } | |
| 2559 | |
| 2560 // copies data from [esi] to [edi] using rcx pointer sized words | |
| 2561 // generic | |
| 2562 void Assembler::rep_mov() { | |
| 2563 emit_byte(0xF3); | |
| 2564 // MOVSQ | |
| 2565 LP64_ONLY(prefix(REX_W)); | |
| 2566 emit_byte(0xA5); | |
| 2567 } | |
| 2568 | |
| 2569 // sets rcx pointer sized words with rax, value at [edi] | |
| 2570 // generic | |
| 2571 void Assembler::rep_set() { // rep_set | |
| 2572 emit_byte(0xF3); | |
| 2573 // STOSQ | |
| 2574 LP64_ONLY(prefix(REX_W)); | |
| 2575 emit_byte(0xAB); | |
| 2576 } | |
| 2577 | |
| 2578 // scans rcx pointer sized words at [edi] for occurance of rax, | |
| 2579 // generic | |
| 2580 void Assembler::repne_scan() { // repne_scan | |
| 2581 emit_byte(0xF2); | |
| 2582 // SCASQ | |
| 2583 LP64_ONLY(prefix(REX_W)); | |
| 2584 emit_byte(0xAF); | |
| 2585 } | |
| 2586 | |
| 2587 #ifdef _LP64 | |
| 2588 // scans rcx 4 byte words at [edi] for occurance of rax, | |
| 2589 // generic | |
| 2590 void Assembler::repne_scanl() { // repne_scan | |
| 2591 emit_byte(0xF2); | |
| 2592 // SCASL | |
| 2593 emit_byte(0xAF); | |
| 2594 } | |
| 2595 #endif | |
| 2596 | |
| 0 | 2597 void Assembler::ret(int imm16) { |
| 2598 if (imm16 == 0) { | |
| 2599 emit_byte(0xC3); | |
| 2600 } else { | |
| 2601 emit_byte(0xC2); | |
| 2602 emit_word(imm16); | |
| 2603 } | |
| 2604 } | |
| 2605 | |
| 304 | 2606 void Assembler::sahf() { |
| 2607 #ifdef _LP64 | |
| 2608 // Not supported in 64bit mode | |
| 2609 ShouldNotReachHere(); | |
| 2610 #endif | |
| 2611 emit_byte(0x9E); | |
| 2612 } | |
| 2613 | |
| 2614 void Assembler::sarl(Register dst, int imm8) { | |
| 2615 int encode = prefix_and_encode(dst->encoding()); | |
| 2616 assert(isShiftCount(imm8), "illegal shift count"); | |
| 2617 if (imm8 == 1) { | |
| 2618 emit_byte(0xD1); | |
| 2619 emit_byte(0xF8 | encode); | |
| 2620 } else { | |
| 2621 emit_byte(0xC1); | |
| 2622 emit_byte(0xF8 | encode); | |
| 2623 emit_byte(imm8); | |
| 2624 } | |
| 2625 } | |
| 2626 | |
| 2627 void Assembler::sarl(Register dst) { | |
| 2628 int encode = prefix_and_encode(dst->encoding()); | |
| 2629 emit_byte(0xD3); | |
| 2630 emit_byte(0xF8 | encode); | |
| 2631 } | |
| 2632 | |
| 2633 void Assembler::sbbl(Address dst, int32_t imm32) { | |
| 2634 InstructionMark im(this); | |
| 2635 prefix(dst); | |
| 2636 emit_arith_operand(0x81, rbx, dst, imm32); | |
| 2637 } | |
| 2638 | |
| 2639 void Assembler::sbbl(Register dst, int32_t imm32) { | |
| 2640 prefix(dst); | |
| 2641 emit_arith(0x81, 0xD8, dst, imm32); | |
| 2642 } | |
| 2643 | |
| 2644 | |
| 2645 void Assembler::sbbl(Register dst, Address src) { | |
| 2646 InstructionMark im(this); | |
| 2647 prefix(src, dst); | |
| 2648 emit_byte(0x1B); | |
| 2649 emit_operand(dst, src); | |
| 2650 } | |
| 2651 | |
| 2652 void Assembler::sbbl(Register dst, Register src) { | |
| 2653 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2654 emit_arith(0x1B, 0xC0, dst, src); | |
| 2655 } | |
| 2656 | |
| 2657 void Assembler::setb(Condition cc, Register dst) { | |
| 2658 assert(0 <= cc && cc < 16, "illegal cc"); | |
| 2659 int encode = prefix_and_encode(dst->encoding(), true); | |
| 0 | 2660 emit_byte(0x0F); |
| 304 | 2661 emit_byte(0x90 | cc); |
| 2662 emit_byte(0xC0 | encode); | |
| 2663 } | |
| 2664 | |
| 2665 void Assembler::shll(Register dst, int imm8) { | |
| 2666 assert(isShiftCount(imm8), "illegal shift count"); | |
| 2667 int encode = prefix_and_encode(dst->encoding()); | |
| 2668 if (imm8 == 1 ) { | |
| 2669 emit_byte(0xD1); | |
| 2670 emit_byte(0xE0 | encode); | |
| 2671 } else { | |
| 2672 emit_byte(0xC1); | |
| 2673 emit_byte(0xE0 | encode); | |
| 2674 emit_byte(imm8); | |
| 2675 } | |
| 2676 } | |
| 2677 | |
| 2678 void Assembler::shll(Register dst) { | |
| 2679 int encode = prefix_and_encode(dst->encoding()); | |
| 2680 emit_byte(0xD3); | |
| 2681 emit_byte(0xE0 | encode); | |
| 2682 } | |
| 2683 | |
| 2684 void Assembler::shrl(Register dst, int imm8) { | |
| 2685 assert(isShiftCount(imm8), "illegal shift count"); | |
| 2686 int encode = prefix_and_encode(dst->encoding()); | |
| 2687 emit_byte(0xC1); | |
| 2688 emit_byte(0xE8 | encode); | |
| 2689 emit_byte(imm8); | |
| 2690 } | |
| 2691 | |
| 2692 void Assembler::shrl(Register dst) { | |
| 2693 int encode = prefix_and_encode(dst->encoding()); | |
| 2694 emit_byte(0xD3); | |
| 2695 emit_byte(0xE8 | encode); | |
| 2696 } | |
| 0 | 2697 |
| 2698 // copies a single word from [esi] to [edi] | |
| 2699 void Assembler::smovl() { | |
| 2700 emit_byte(0xA5); | |
| 2701 } | |
| 2702 | |
| 304 | 2703 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) { |
| 2704 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 2705 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
| 304 | 2706 emit_byte(0x51); |
| 2707 emit_byte(0xC0 | encode); | |
| 2708 } | |
| 2709 | |
| 2008 | 2710 void Assembler::sqrtsd(XMMRegister dst, Address src) { |
| 2711 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2712 InstructionMark im(this); | |
| 4759 | 2713 simd_prefix(dst, dst, src, VEX_SIMD_F2); |
| 2008 | 2714 emit_byte(0x51); |
| 2715 emit_operand(dst, src); | |
| 2716 } | |
| 2717 | |
| 2718 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) { | |
| 4759 | 2719 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
| 2720 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); | |
| 2008 | 2721 emit_byte(0x51); |
| 2722 emit_byte(0xC0 | encode); | |
| 2723 } | |
| 2724 | |
| 2725 void Assembler::sqrtss(XMMRegister dst, Address src) { | |
| 4759 | 2726 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
| 2727 InstructionMark im(this); | |
| 2728 simd_prefix(dst, dst, src, VEX_SIMD_F3); | |
| 2008 | 2729 emit_byte(0x51); |
| 2730 emit_operand(dst, src); | |
| 2731 } | |
| 2732 | |
| 304 | 2733 void Assembler::stmxcsr( Address dst) { |
| 2734 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 2735 InstructionMark im(this); | |
| 2736 prefix(dst); | |
| 2737 emit_byte(0x0F); | |
| 2738 emit_byte(0xAE); | |
| 2739 emit_operand(as_Register(3), dst); | |
| 2740 } | |
| 2741 | |
| 2742 void Assembler::subl(Address dst, int32_t imm32) { | |
| 2743 InstructionMark im(this); | |
| 2744 prefix(dst); | |
|
2100
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7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
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changeset
|
2745 emit_arith_operand(0x81, rbp, dst, imm32); |
| 304 | 2746 } |
| 2747 | |
| 2748 void Assembler::subl(Address dst, Register src) { | |
| 2749 InstructionMark im(this); | |
| 2750 prefix(dst, src); | |
| 2751 emit_byte(0x29); | |
| 2752 emit_operand(src, dst); | |
| 2753 } | |
| 2754 | |
|
2100
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changeset
|
2755 void Assembler::subl(Register dst, int32_t imm32) { |
|
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7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
2756 prefix(dst); |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
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diff
changeset
|
2757 emit_arith(0x81, 0xE8, dst, imm32); |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
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parents:
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|
2758 } |
|
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7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
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|
2759 |
| 304 | 2760 void Assembler::subl(Register dst, Address src) { |
| 2761 InstructionMark im(this); | |
| 2762 prefix(src, dst); | |
| 2763 emit_byte(0x2B); | |
| 2764 emit_operand(dst, src); | |
| 2765 } | |
| 2766 | |
| 2767 void Assembler::subl(Register dst, Register src) { | |
| 2768 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2769 emit_arith(0x2B, 0xC0, dst, src); | |
| 2770 } | |
| 2771 | |
| 2772 void Assembler::subsd(XMMRegister dst, XMMRegister src) { | |
| 2773 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 2774 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
| 304 | 2775 emit_byte(0x5C); |
| 2776 emit_byte(0xC0 | encode); | |
| 2777 } | |
| 2778 | |
| 2779 void Assembler::subsd(XMMRegister dst, Address src) { | |
| 2780 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2781 InstructionMark im(this); | |
| 4759 | 2782 simd_prefix(dst, dst, src, VEX_SIMD_F2); |
| 304 | 2783 emit_byte(0x5C); |
| 2784 emit_operand(dst, src); | |
| 2785 } | |
| 2786 | |
| 2787 void Assembler::subss(XMMRegister dst, XMMRegister src) { | |
| 2788 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 4759 | 2789 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); |
| 304 | 2790 emit_byte(0x5C); |
| 2791 emit_byte(0xC0 | encode); | |
| 2792 } | |
| 2793 | |
| 2794 void Assembler::subss(XMMRegister dst, Address src) { | |
| 2795 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 2796 InstructionMark im(this); | |
| 4759 | 2797 simd_prefix(dst, dst, src, VEX_SIMD_F3); |
| 304 | 2798 emit_byte(0x5C); |
| 2799 emit_operand(dst, src); | |
| 2800 } | |
| 2801 | |
| 2802 void Assembler::testb(Register dst, int imm8) { | |
| 2803 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); | |
| 2804 (void) prefix_and_encode(dst->encoding(), true); | |
| 2805 emit_arith_b(0xF6, 0xC0, dst, imm8); | |
| 2806 } | |
| 2807 | |
| 2808 void Assembler::testl(Register dst, int32_t imm32) { | |
| 2809 // not using emit_arith because test | |
| 2810 // doesn't support sign-extension of | |
| 2811 // 8bit operands | |
| 2812 int encode = dst->encoding(); | |
| 2813 if (encode == 0) { | |
| 2814 emit_byte(0xA9); | |
| 2815 } else { | |
| 2816 encode = prefix_and_encode(encode); | |
| 2817 emit_byte(0xF7); | |
| 2818 emit_byte(0xC0 | encode); | |
| 2819 } | |
| 2820 emit_long(imm32); | |
| 2821 } | |
| 2822 | |
| 2823 void Assembler::testl(Register dst, Register src) { | |
| 2824 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2825 emit_arith(0x85, 0xC0, dst, src); | |
| 2826 } | |
| 2827 | |
| 2828 void Assembler::testl(Register dst, Address src) { | |
| 2829 InstructionMark im(this); | |
| 2830 prefix(src, dst); | |
| 2831 emit_byte(0x85); | |
| 2832 emit_operand(dst, src); | |
| 2833 } | |
| 2834 | |
| 2835 void Assembler::ucomisd(XMMRegister dst, Address src) { | |
| 2836 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 2837 InstructionMark im(this); |
| 2838 simd_prefix(dst, src, VEX_SIMD_66); | |
| 2839 emit_byte(0x2E); | |
| 2840 emit_operand(dst, src); | |
| 304 | 2841 } |
| 2842 | |
| 2843 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) { | |
| 2844 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 2845 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); |
| 2846 emit_byte(0x2E); | |
| 2847 emit_byte(0xC0 | encode); | |
| 304 | 2848 } |
| 2849 | |
| 2850 void Assembler::ucomiss(XMMRegister dst, Address src) { | |
| 2851 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 4759 | 2852 InstructionMark im(this); |
| 2853 simd_prefix(dst, src, VEX_SIMD_NONE); | |
| 304 | 2854 emit_byte(0x2E); |
| 2855 emit_operand(dst, src); | |
| 2856 } | |
| 2857 | |
| 2858 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) { | |
| 2859 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 4759 | 2860 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE); |
| 304 | 2861 emit_byte(0x2E); |
| 2862 emit_byte(0xC0 | encode); | |
| 2863 } | |
| 2864 | |
| 2865 | |
| 2866 void Assembler::xaddl(Address dst, Register src) { | |
| 2867 InstructionMark im(this); | |
| 2868 prefix(dst, src); | |
| 0 | 2869 emit_byte(0x0F); |
| 304 | 2870 emit_byte(0xC1); |
| 2871 emit_operand(src, dst); | |
| 2872 } | |
| 2873 | |
| 2874 void Assembler::xchgl(Register dst, Address src) { // xchg | |
| 2875 InstructionMark im(this); | |
| 2876 prefix(src, dst); | |
| 2877 emit_byte(0x87); | |
| 2878 emit_operand(dst, src); | |
| 2879 } | |
| 2880 | |
| 2881 void Assembler::xchgl(Register dst, Register src) { | |
| 2882 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2883 emit_byte(0x87); | |
| 2884 emit_byte(0xc0 | encode); | |
| 2885 } | |
| 2886 | |
| 2887 void Assembler::xorl(Register dst, int32_t imm32) { | |
| 2888 prefix(dst); | |
| 2889 emit_arith(0x81, 0xF0, dst, imm32); | |
| 2890 } | |
| 2891 | |
| 2892 void Assembler::xorl(Register dst, Address src) { | |
| 2893 InstructionMark im(this); | |
| 2894 prefix(src, dst); | |
| 2895 emit_byte(0x33); | |
| 2896 emit_operand(dst, src); | |
| 2897 } | |
| 2898 | |
| 2899 void Assembler::xorl(Register dst, Register src) { | |
| 2900 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2901 emit_arith(0x33, 0xC0, dst, src); | |
| 2902 } | |
| 2903 | |
| 2904 void Assembler::xorpd(XMMRegister dst, XMMRegister src) { | |
| 2905 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 2906 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); |
| 2907 emit_byte(0x57); | |
| 2908 emit_byte(0xC0 | encode); | |
| 304 | 2909 } |
| 2910 | |
| 2911 void Assembler::xorpd(XMMRegister dst, Address src) { | |
| 2912 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2913 InstructionMark im(this); | |
| 4759 | 2914 simd_prefix(dst, dst, src, VEX_SIMD_66); |
| 304 | 2915 emit_byte(0x57); |
| 2916 emit_operand(dst, src); | |
| 2917 } | |
| 2918 | |
| 2919 | |
| 2920 void Assembler::xorps(XMMRegister dst, XMMRegister src) { | |
| 2921 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 4759 | 2922 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE); |
| 304 | 2923 emit_byte(0x57); |
| 2924 emit_byte(0xC0 | encode); | |
| 2925 } | |
| 2926 | |
| 2927 void Assembler::xorps(XMMRegister dst, Address src) { | |
| 2928 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 2929 InstructionMark im(this); | |
| 4759 | 2930 simd_prefix(dst, dst, src, VEX_SIMD_NONE); |
| 304 | 2931 emit_byte(0x57); |
| 2932 emit_operand(dst, src); | |
| 2933 } | |
| 2934 | |
| 2935 #ifndef _LP64 | |
| 2936 // 32bit only pieces of the assembler | |
| 2937 | |
| 2938 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) { | |
| 2939 // NO PREFIX AS NEVER 64BIT | |
| 2940 InstructionMark im(this); | |
| 2941 emit_byte(0x81); | |
| 2942 emit_byte(0xF8 | src1->encoding()); | |
| 2943 emit_data(imm32, rspec, 0); | |
| 2944 } | |
| 2945 | |
| 2946 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) { | |
| 2947 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs | |
| 2948 InstructionMark im(this); | |
| 2949 emit_byte(0x81); | |
| 2950 emit_operand(rdi, src1); | |
| 2951 emit_data(imm32, rspec, 0); | |
| 2952 } | |
| 2953 | |
| 2954 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax, | |
| 2955 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded | |
| 2956 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise. | |
| 2957 void Assembler::cmpxchg8(Address adr) { | |
| 2958 InstructionMark im(this); | |
| 2959 emit_byte(0x0F); | |
| 2960 emit_byte(0xc7); | |
| 2961 emit_operand(rcx, adr); | |
| 2962 } | |
| 2963 | |
| 2964 void Assembler::decl(Register dst) { | |
| 2965 // Don't use it directly. Use MacroAssembler::decrementl() instead. | |
| 2966 emit_byte(0x48 | dst->encoding()); | |
| 2967 } | |
| 2968 | |
| 2969 #endif // _LP64 | |
| 2970 | |
| 2971 // 64bit typically doesn't use the x87 but needs to for the trig funcs | |
| 2972 | |
| 2973 void Assembler::fabs() { | |
| 2974 emit_byte(0xD9); | |
| 2975 emit_byte(0xE1); | |
| 2976 } | |
| 2977 | |
| 2978 void Assembler::fadd(int i) { | |
| 2979 emit_farith(0xD8, 0xC0, i); | |
| 2980 } | |
| 2981 | |
| 2982 void Assembler::fadd_d(Address src) { | |
| 2983 InstructionMark im(this); | |
| 2984 emit_byte(0xDC); | |
| 2985 emit_operand32(rax, src); | |
| 2986 } | |
| 2987 | |
| 2988 void Assembler::fadd_s(Address src) { | |
| 2989 InstructionMark im(this); | |
| 2990 emit_byte(0xD8); | |
| 2991 emit_operand32(rax, src); | |
| 2992 } | |
| 2993 | |
| 2994 void Assembler::fadda(int i) { | |
| 2995 emit_farith(0xDC, 0xC0, i); | |
| 2996 } | |
| 2997 | |
| 2998 void Assembler::faddp(int i) { | |
| 2999 emit_farith(0xDE, 0xC0, i); | |
| 3000 } | |
| 3001 | |
| 3002 void Assembler::fchs() { | |
| 3003 emit_byte(0xD9); | |
| 3004 emit_byte(0xE0); | |
| 3005 } | |
| 3006 | |
| 3007 void Assembler::fcom(int i) { | |
| 3008 emit_farith(0xD8, 0xD0, i); | |
| 3009 } | |
| 3010 | |
| 3011 void Assembler::fcomp(int i) { | |
| 3012 emit_farith(0xD8, 0xD8, i); | |
| 3013 } | |
| 3014 | |
| 3015 void Assembler::fcomp_d(Address src) { | |
| 3016 InstructionMark im(this); | |
| 3017 emit_byte(0xDC); | |
| 3018 emit_operand32(rbx, src); | |
| 3019 } | |
| 3020 | |
| 3021 void Assembler::fcomp_s(Address src) { | |
| 3022 InstructionMark im(this); | |
| 3023 emit_byte(0xD8); | |
| 3024 emit_operand32(rbx, src); | |
| 3025 } | |
| 3026 | |
| 3027 void Assembler::fcompp() { | |
| 3028 emit_byte(0xDE); | |
| 3029 emit_byte(0xD9); | |
| 3030 } | |
| 3031 | |
| 3032 void Assembler::fcos() { | |
| 3033 emit_byte(0xD9); | |
| 0 | 3034 emit_byte(0xFF); |
| 304 | 3035 } |
| 3036 | |
| 3037 void Assembler::fdecstp() { | |
| 3038 emit_byte(0xD9); | |
| 3039 emit_byte(0xF6); | |
| 3040 } | |
| 3041 | |
| 3042 void Assembler::fdiv(int i) { | |
| 3043 emit_farith(0xD8, 0xF0, i); | |
| 3044 } | |
| 3045 | |
| 3046 void Assembler::fdiv_d(Address src) { | |
| 3047 InstructionMark im(this); | |
| 3048 emit_byte(0xDC); | |
| 3049 emit_operand32(rsi, src); | |
| 3050 } | |
| 3051 | |
| 3052 void Assembler::fdiv_s(Address src) { | |
| 3053 InstructionMark im(this); | |
| 3054 emit_byte(0xD8); | |
| 3055 emit_operand32(rsi, src); | |
| 3056 } | |
| 3057 | |
| 3058 void Assembler::fdiva(int i) { | |
| 3059 emit_farith(0xDC, 0xF8, i); | |
| 3060 } | |
| 3061 | |
| 3062 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994) | |
| 3063 // is erroneous for some of the floating-point instructions below. | |
| 3064 | |
| 3065 void Assembler::fdivp(int i) { | |
| 3066 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong) | |
| 3067 } | |
| 3068 | |
| 3069 void Assembler::fdivr(int i) { | |
| 3070 emit_farith(0xD8, 0xF8, i); | |
| 3071 } | |
| 3072 | |
| 3073 void Assembler::fdivr_d(Address src) { | |
| 3074 InstructionMark im(this); | |
| 3075 emit_byte(0xDC); | |
| 3076 emit_operand32(rdi, src); | |
| 3077 } | |
| 3078 | |
| 3079 void Assembler::fdivr_s(Address src) { | |
| 3080 InstructionMark im(this); | |
| 3081 emit_byte(0xD8); | |
| 3082 emit_operand32(rdi, src); | |
| 3083 } | |
| 3084 | |
| 3085 void Assembler::fdivra(int i) { | |
| 3086 emit_farith(0xDC, 0xF0, i); | |
| 3087 } | |
| 3088 | |
| 3089 void Assembler::fdivrp(int i) { | |
| 3090 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong) | |
| 3091 } | |
| 3092 | |
| 3093 void Assembler::ffree(int i) { | |
| 3094 emit_farith(0xDD, 0xC0, i); | |
| 3095 } | |
| 3096 | |
| 3097 void Assembler::fild_d(Address adr) { | |
| 3098 InstructionMark im(this); | |
| 3099 emit_byte(0xDF); | |
| 3100 emit_operand32(rbp, adr); | |
| 3101 } | |
| 3102 | |
| 3103 void Assembler::fild_s(Address adr) { | |
| 3104 InstructionMark im(this); | |
| 3105 emit_byte(0xDB); | |
| 3106 emit_operand32(rax, adr); | |
| 3107 } | |
| 3108 | |
| 3109 void Assembler::fincstp() { | |
| 3110 emit_byte(0xD9); | |
| 3111 emit_byte(0xF7); | |
| 3112 } | |
| 3113 | |
| 3114 void Assembler::finit() { | |
| 3115 emit_byte(0x9B); | |
| 3116 emit_byte(0xDB); | |
| 3117 emit_byte(0xE3); | |
| 3118 } | |
| 3119 | |
| 3120 void Assembler::fist_s(Address adr) { | |
| 3121 InstructionMark im(this); | |
| 3122 emit_byte(0xDB); | |
| 3123 emit_operand32(rdx, adr); | |
| 3124 } | |
| 3125 | |
| 3126 void Assembler::fistp_d(Address adr) { | |
| 3127 InstructionMark im(this); | |
| 3128 emit_byte(0xDF); | |
| 3129 emit_operand32(rdi, adr); | |
| 3130 } | |
| 3131 | |
| 3132 void Assembler::fistp_s(Address adr) { | |
| 3133 InstructionMark im(this); | |
| 3134 emit_byte(0xDB); | |
| 3135 emit_operand32(rbx, adr); | |
| 3136 } | |
| 0 | 3137 |
| 3138 void Assembler::fld1() { | |
| 3139 emit_byte(0xD9); | |
| 3140 emit_byte(0xE8); | |
| 3141 } | |
| 3142 | |
| 304 | 3143 void Assembler::fld_d(Address adr) { |
| 3144 InstructionMark im(this); | |
| 3145 emit_byte(0xDD); | |
| 3146 emit_operand32(rax, adr); | |
| 3147 } | |
| 0 | 3148 |
| 3149 void Assembler::fld_s(Address adr) { | |
| 3150 InstructionMark im(this); | |
| 3151 emit_byte(0xD9); | |
| 304 | 3152 emit_operand32(rax, adr); |
| 3153 } | |
| 3154 | |
| 3155 | |
| 3156 void Assembler::fld_s(int index) { | |
| 0 | 3157 emit_farith(0xD9, 0xC0, index); |
| 3158 } | |
| 3159 | |
| 3160 void Assembler::fld_x(Address adr) { | |
| 3161 InstructionMark im(this); | |
| 3162 emit_byte(0xDB); | |
| 304 | 3163 emit_operand32(rbp, adr); |
| 3164 } | |
| 3165 | |
| 3166 void Assembler::fldcw(Address src) { | |
| 3167 InstructionMark im(this); | |
| 3168 emit_byte(0xd9); | |
| 3169 emit_operand32(rbp, src); | |
| 3170 } | |
| 3171 | |
| 3172 void Assembler::fldenv(Address src) { | |
| 0 | 3173 InstructionMark im(this); |
| 3174 emit_byte(0xD9); | |
| 304 | 3175 emit_operand32(rsp, src); |
| 3176 } | |
| 3177 | |
| 3178 void Assembler::fldlg2() { | |
| 0 | 3179 emit_byte(0xD9); |
| 304 | 3180 emit_byte(0xEC); |
| 3181 } | |
| 0 | 3182 |
| 3183 void Assembler::fldln2() { | |
| 3184 emit_byte(0xD9); | |
| 3185 emit_byte(0xED); | |
| 3186 } | |
| 3187 | |
| 304 | 3188 void Assembler::fldz() { |
| 0 | 3189 emit_byte(0xD9); |
| 304 | 3190 emit_byte(0xEE); |
| 3191 } | |
| 0 | 3192 |
| 3193 void Assembler::flog() { | |
| 3194 fldln2(); | |
| 3195 fxch(); | |
| 3196 fyl2x(); | |
| 3197 } | |
| 3198 | |
| 3199 void Assembler::flog10() { | |
| 3200 fldlg2(); | |
| 3201 fxch(); | |
| 3202 fyl2x(); | |
| 3203 } | |
| 3204 | |
| 304 | 3205 void Assembler::fmul(int i) { |
| 3206 emit_farith(0xD8, 0xC8, i); | |
| 3207 } | |
| 3208 | |
| 3209 void Assembler::fmul_d(Address src) { | |
| 3210 InstructionMark im(this); | |
| 3211 emit_byte(0xDC); | |
| 3212 emit_operand32(rcx, src); | |
| 3213 } | |
| 3214 | |
| 3215 void Assembler::fmul_s(Address src) { | |
| 3216 InstructionMark im(this); | |
| 3217 emit_byte(0xD8); | |
| 3218 emit_operand32(rcx, src); | |
| 3219 } | |
| 3220 | |
| 3221 void Assembler::fmula(int i) { | |
| 3222 emit_farith(0xDC, 0xC8, i); | |
| 3223 } | |
| 3224 | |
| 3225 void Assembler::fmulp(int i) { | |
| 3226 emit_farith(0xDE, 0xC8, i); | |
| 3227 } | |
| 3228 | |
| 3229 void Assembler::fnsave(Address dst) { | |
| 3230 InstructionMark im(this); | |
| 3231 emit_byte(0xDD); | |
| 3232 emit_operand32(rsi, dst); | |
| 3233 } | |
| 3234 | |
| 3235 void Assembler::fnstcw(Address src) { | |
| 3236 InstructionMark im(this); | |
| 3237 emit_byte(0x9B); | |
| 3238 emit_byte(0xD9); | |
| 3239 emit_operand32(rdi, src); | |
| 3240 } | |
| 3241 | |
| 3242 void Assembler::fnstsw_ax() { | |
| 3243 emit_byte(0xdF); | |
| 3244 emit_byte(0xE0); | |
| 3245 } | |
| 3246 | |
| 3247 void Assembler::fprem() { | |
| 3248 emit_byte(0xD9); | |
| 3249 emit_byte(0xF8); | |
| 3250 } | |
| 3251 | |
| 3252 void Assembler::fprem1() { | |
| 3253 emit_byte(0xD9); | |
| 3254 emit_byte(0xF5); | |
| 3255 } | |
| 3256 | |
| 3257 void Assembler::frstor(Address src) { | |
| 3258 InstructionMark im(this); | |
| 3259 emit_byte(0xDD); | |
| 3260 emit_operand32(rsp, src); | |
| 3261 } | |
| 0 | 3262 |
| 3263 void Assembler::fsin() { | |
| 3264 emit_byte(0xD9); | |
| 3265 emit_byte(0xFE); | |
| 3266 } | |
| 3267 | |
| 304 | 3268 void Assembler::fsqrt() { |
| 3269 emit_byte(0xD9); | |
| 3270 emit_byte(0xFA); | |
| 3271 } | |
| 3272 | |
| 3273 void Assembler::fst_d(Address adr) { | |
| 3274 InstructionMark im(this); | |
| 3275 emit_byte(0xDD); | |
| 3276 emit_operand32(rdx, adr); | |
| 3277 } | |
| 3278 | |
| 3279 void Assembler::fst_s(Address adr) { | |
| 3280 InstructionMark im(this); | |
| 3281 emit_byte(0xD9); | |
| 3282 emit_operand32(rdx, adr); | |
| 3283 } | |
| 3284 | |
| 3285 void Assembler::fstp_d(Address adr) { | |
| 3286 InstructionMark im(this); | |
| 3287 emit_byte(0xDD); | |
| 3288 emit_operand32(rbx, adr); | |
| 3289 } | |
| 3290 | |
| 3291 void Assembler::fstp_d(int index) { | |
| 3292 emit_farith(0xDD, 0xD8, index); | |
| 3293 } | |
| 3294 | |
| 3295 void Assembler::fstp_s(Address adr) { | |
| 3296 InstructionMark im(this); | |
| 0 | 3297 emit_byte(0xD9); |
| 304 | 3298 emit_operand32(rbx, adr); |
| 3299 } | |
| 3300 | |
| 3301 void Assembler::fstp_x(Address adr) { | |
| 3302 InstructionMark im(this); | |
| 3303 emit_byte(0xDB); | |
| 3304 emit_operand32(rdi, adr); | |
| 3305 } | |
| 3306 | |
| 3307 void Assembler::fsub(int i) { | |
| 3308 emit_farith(0xD8, 0xE0, i); | |
| 3309 } | |
| 3310 | |
| 3311 void Assembler::fsub_d(Address src) { | |
| 3312 InstructionMark im(this); | |
| 3313 emit_byte(0xDC); | |
| 3314 emit_operand32(rsp, src); | |
| 3315 } | |
| 3316 | |
| 3317 void Assembler::fsub_s(Address src) { | |
| 3318 InstructionMark im(this); | |
| 3319 emit_byte(0xD8); | |
| 3320 emit_operand32(rsp, src); | |
| 3321 } | |
| 3322 | |
| 3323 void Assembler::fsuba(int i) { | |
| 3324 emit_farith(0xDC, 0xE8, i); | |
| 3325 } | |
| 3326 | |
| 3327 void Assembler::fsubp(int i) { | |
| 3328 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong) | |
| 3329 } | |
| 3330 | |
| 3331 void Assembler::fsubr(int i) { | |
| 3332 emit_farith(0xD8, 0xE8, i); | |
| 3333 } | |
| 3334 | |
| 3335 void Assembler::fsubr_d(Address src) { | |
| 3336 InstructionMark im(this); | |
| 3337 emit_byte(0xDC); | |
| 3338 emit_operand32(rbp, src); | |
| 3339 } | |
| 3340 | |
| 3341 void Assembler::fsubr_s(Address src) { | |
| 3342 InstructionMark im(this); | |
| 3343 emit_byte(0xD8); | |
| 3344 emit_operand32(rbp, src); | |
| 3345 } | |
| 3346 | |
| 3347 void Assembler::fsubra(int i) { | |
| 3348 emit_farith(0xDC, 0xE0, i); | |
| 3349 } | |
| 3350 | |
| 3351 void Assembler::fsubrp(int i) { | |
| 3352 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong) | |
| 0 | 3353 } |
| 3354 | |
| 3355 void Assembler::ftan() { | |
| 3356 emit_byte(0xD9); | |
| 3357 emit_byte(0xF2); | |
| 3358 emit_byte(0xDD); | |
| 3359 emit_byte(0xD8); | |
| 3360 } | |
| 3361 | |
| 304 | 3362 void Assembler::ftst() { |
| 0 | 3363 emit_byte(0xD9); |
| 304 | 3364 emit_byte(0xE4); |
| 3365 } | |
| 0 | 3366 |
| 3367 void Assembler::fucomi(int i) { | |
| 3368 // make sure the instruction is supported (introduced for P6, together with cmov) | |
| 3369 guarantee(VM_Version::supports_cmov(), "illegal instruction"); | |
| 3370 emit_farith(0xDB, 0xE8, i); | |
| 3371 } | |
| 3372 | |
| 3373 void Assembler::fucomip(int i) { | |
| 3374 // make sure the instruction is supported (introduced for P6, together with cmov) | |
| 3375 guarantee(VM_Version::supports_cmov(), "illegal instruction"); | |
| 3376 emit_farith(0xDF, 0xE8, i); | |
| 3377 } | |
| 3378 | |
| 3379 void Assembler::fwait() { | |
| 3380 emit_byte(0x9B); | |
| 3381 } | |
| 3382 | |
| 304 | 3383 void Assembler::fxch(int i) { |
| 3384 emit_farith(0xD9, 0xC8, i); | |
| 3385 } | |
| 3386 | |
| 3387 void Assembler::fyl2x() { | |
| 0 | 3388 emit_byte(0xD9); |
| 304 | 3389 emit_byte(0xF1); |
| 3390 } | |
| 3391 | |
| 4759 | 3392 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding. |
| 3393 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 }; | |
| 3394 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding. | |
| 3395 static int simd_opc[4] = { 0, 0, 0x38, 0x3A }; | |
| 3396 | |
| 3397 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding. | |
| 3398 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) { | |
| 3399 if (pre > 0) { | |
| 3400 emit_byte(simd_pre[pre]); | |
| 3401 } | |
| 3402 if (rex_w) { | |
| 3403 prefixq(adr, xreg); | |
| 3404 } else { | |
| 3405 prefix(adr, xreg); | |
| 3406 } | |
| 3407 if (opc > 0) { | |
| 3408 emit_byte(0x0F); | |
| 3409 int opc2 = simd_opc[opc]; | |
| 3410 if (opc2 > 0) { | |
| 3411 emit_byte(opc2); | |
| 3412 } | |
| 3413 } | |
| 3414 } | |
| 3415 | |
| 3416 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) { | |
| 3417 if (pre > 0) { | |
| 3418 emit_byte(simd_pre[pre]); | |
| 3419 } | |
| 3420 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : | |
| 3421 prefix_and_encode(dst_enc, src_enc); | |
| 3422 if (opc > 0) { | |
| 3423 emit_byte(0x0F); | |
| 3424 int opc2 = simd_opc[opc]; | |
| 3425 if (opc2 > 0) { | |
| 3426 emit_byte(opc2); | |
| 3427 } | |
| 3428 } | |
| 3429 return encode; | |
| 3430 } | |
| 3431 | |
| 3432 | |
| 3433 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, int nds_enc, VexSimdPrefix pre, VexOpcode opc, bool vector256) { | |
| 3434 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) { | |
| 3435 prefix(VEX_3bytes); | |
| 3436 | |
| 3437 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0); | |
| 3438 byte1 = (~byte1) & 0xE0; | |
| 3439 byte1 |= opc; | |
| 3440 a_byte(byte1); | |
| 3441 | |
| 3442 int byte2 = ((~nds_enc) & 0xf) << 3; | |
| 3443 byte2 |= (vex_w ? VEX_W : 0) | (vector256 ? 4 : 0) | pre; | |
| 3444 emit_byte(byte2); | |
| 3445 } else { | |
| 3446 prefix(VEX_2bytes); | |
| 3447 | |
| 3448 int byte1 = vex_r ? VEX_R : 0; | |
| 3449 byte1 = (~byte1) & 0x80; | |
| 3450 byte1 |= ((~nds_enc) & 0xf) << 3; | |
| 3451 byte1 |= (vector256 ? 4 : 0) | pre; | |
| 3452 emit_byte(byte1); | |
| 3453 } | |
| 3454 } | |
| 3455 | |
| 3456 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256){ | |
| 3457 bool vex_r = (xreg_enc >= 8); | |
| 3458 bool vex_b = adr.base_needs_rex(); | |
| 3459 bool vex_x = adr.index_needs_rex(); | |
| 3460 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256); | |
| 3461 } | |
| 3462 | |
| 3463 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256) { | |
| 3464 bool vex_r = (dst_enc >= 8); | |
| 3465 bool vex_b = (src_enc >= 8); | |
| 3466 bool vex_x = false; | |
| 3467 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256); | |
| 3468 return (((dst_enc & 7) << 3) | (src_enc & 7)); | |
| 3469 } | |
| 3470 | |
| 3471 | |
| 3472 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) { | |
| 3473 if (UseAVX > 0) { | |
| 3474 int xreg_enc = xreg->encoding(); | |
| 3475 int nds_enc = nds->is_valid() ? nds->encoding() : 0; | |
| 3476 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, rex_w, vector256); | |
| 3477 } else { | |
| 3478 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding"); | |
| 3479 rex_prefix(adr, xreg, pre, opc, rex_w); | |
| 3480 } | |
| 3481 } | |
| 3482 | |
| 3483 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) { | |
| 3484 int dst_enc = dst->encoding(); | |
| 3485 int src_enc = src->encoding(); | |
| 3486 if (UseAVX > 0) { | |
| 3487 int nds_enc = nds->is_valid() ? nds->encoding() : 0; | |
| 3488 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector256); | |
| 3489 } else { | |
| 3490 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding"); | |
| 3491 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, rex_w); | |
| 3492 } | |
| 3493 } | |
| 304 | 3494 |
| 3495 #ifndef _LP64 | |
| 3496 | |
| 3497 void Assembler::incl(Register dst) { | |
| 3498 // Don't use it directly. Use MacroAssembler::incrementl() instead. | |
| 4759 | 3499 emit_byte(0x40 | dst->encoding()); |
| 304 | 3500 } |
| 3501 | |
| 3502 void Assembler::lea(Register dst, Address src) { | |
| 3503 leal(dst, src); | |
| 3504 } | |
| 3505 | |
| 3506 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) { | |
| 3507 InstructionMark im(this); | |
| 3508 emit_byte(0xC7); | |
| 3509 emit_operand(rax, dst); | |
| 3510 emit_data((int)imm32, rspec, 0); | |
| 3511 } | |
| 3512 | |
|
642
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624
diff
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|
3513 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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|
3514 InstructionMark im(this); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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diff
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|
3515 int encode = prefix_and_encode(dst->encoding()); |
|
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|
3516 emit_byte(0xB8 | encode); |
|
660978a2a31a
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|
3517 emit_data((int)imm32, rspec, 0); |
|
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|
3518 } |
| 304 | 3519 |
| 3520 void Assembler::popa() { // 32bit | |
| 3521 emit_byte(0x61); | |
| 3522 } | |
| 3523 | |
| 3524 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) { | |
| 3525 InstructionMark im(this); | |
| 3526 emit_byte(0x68); | |
| 3527 emit_data(imm32, rspec, 0); | |
| 3528 } | |
| 3529 | |
| 3530 void Assembler::pusha() { // 32bit | |
| 3531 emit_byte(0x60); | |
| 3532 } | |
| 3533 | |
| 3534 void Assembler::set_byte_if_not_zero(Register dst) { | |
| 0 | 3535 emit_byte(0x0F); |
| 304 | 3536 emit_byte(0x95); |
| 3537 emit_byte(0xE0 | dst->encoding()); | |
| 3538 } | |
| 3539 | |
| 3540 void Assembler::shldl(Register dst, Register src) { | |
| 0 | 3541 emit_byte(0x0F); |
| 304 | 3542 emit_byte(0xA5); |
| 3543 emit_byte(0xC0 | src->encoding() << 3 | dst->encoding()); | |
| 3544 } | |
| 3545 | |
| 3546 void Assembler::shrdl(Register dst, Register src) { | |
| 0 | 3547 emit_byte(0x0F); |
| 304 | 3548 emit_byte(0xAD); |
| 3549 emit_byte(0xC0 | src->encoding() << 3 | dst->encoding()); | |
| 3550 } | |
| 3551 | |
| 3552 #else // LP64 | |
| 3553 | |
| 1369 | 3554 void Assembler::set_byte_if_not_zero(Register dst) { |
| 3555 int enc = prefix_and_encode(dst->encoding(), true); | |
| 3556 emit_byte(0x0F); | |
| 3557 emit_byte(0x95); | |
| 3558 emit_byte(0xE0 | enc); | |
| 3559 } | |
| 3560 | |
| 304 | 3561 // 64bit only pieces of the assembler |
| 3562 // This should only be used by 64bit instructions that can use rip-relative | |
| 3563 // it cannot be used by instructions that want an immediate value. | |
| 3564 | |
| 3565 bool Assembler::reachable(AddressLiteral adr) { | |
| 3566 int64_t disp; | |
| 3567 // None will force a 64bit literal to the code stream. Likely a placeholder | |
| 3568 // for something that will be patched later and we need to certain it will | |
| 3569 // always be reachable. | |
| 3570 if (adr.reloc() == relocInfo::none) { | |
| 3571 return false; | |
| 3572 } | |
| 3573 if (adr.reloc() == relocInfo::internal_word_type) { | |
| 3574 // This should be rip relative and easily reachable. | |
| 3575 return true; | |
| 3576 } | |
| 3577 if (adr.reloc() == relocInfo::virtual_call_type || | |
| 3578 adr.reloc() == relocInfo::opt_virtual_call_type || | |
| 3579 adr.reloc() == relocInfo::static_call_type || | |
| 3580 adr.reloc() == relocInfo::static_stub_type ) { | |
| 3581 // This should be rip relative within the code cache and easily | |
| 3582 // reachable until we get huge code caches. (At which point | |
| 3583 // ic code is going to have issues). | |
| 3584 return true; | |
| 3585 } | |
| 3586 if (adr.reloc() != relocInfo::external_word_type && | |
| 3587 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special | |
| 3588 adr.reloc() != relocInfo::poll_type && // relocs to identify them | |
| 3589 adr.reloc() != relocInfo::runtime_call_type ) { | |
| 3590 return false; | |
| 3591 } | |
| 3592 | |
| 3593 // Stress the correction code | |
| 3594 if (ForceUnreachable) { | |
| 3595 // Must be runtimecall reloc, see if it is in the codecache | |
| 3596 // Flipping stuff in the codecache to be unreachable causes issues | |
| 3597 // with things like inline caches where the additional instructions | |
| 3598 // are not handled. | |
| 3599 if (CodeCache::find_blob(adr._target) == NULL) { | |
| 3600 return false; | |
| 3601 } | |
| 3602 } | |
| 3603 // For external_word_type/runtime_call_type if it is reachable from where we | |
| 3604 // are now (possibly a temp buffer) and where we might end up | |
| 3605 // anywhere in the codeCache then we are always reachable. | |
| 3606 // This would have to change if we ever save/restore shared code | |
| 3607 // to be more pessimistic. | |
| 3608 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int)); | |
| 3609 if (!is_simm32(disp)) return false; | |
| 3610 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int)); | |
| 3611 if (!is_simm32(disp)) return false; | |
| 3612 | |
| 3613 disp = (int64_t)adr._target - ((int64_t)_code_pos + sizeof(int)); | |
| 3614 | |
| 3615 // Because rip relative is a disp + address_of_next_instruction and we | |
| 3616 // don't know the value of address_of_next_instruction we apply a fudge factor | |
| 3617 // to make sure we will be ok no matter the size of the instruction we get placed into. | |
| 3618 // We don't have to fudge the checks above here because they are already worst case. | |
| 3619 | |
| 3620 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal | |
| 3621 // + 4 because better safe than sorry. | |
| 3622 const int fudge = 12 + 4; | |
| 3623 if (disp < 0) { | |
| 3624 disp -= fudge; | |
| 3625 } else { | |
| 3626 disp += fudge; | |
| 3627 } | |
| 3628 return is_simm32(disp); | |
| 3629 } | |
| 3630 | |
|
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diff
changeset
|
3631 // Check if the polling page is not reachable from the code cache using rip-relative |
|
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diff
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|
3632 // addressing. |
|
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diff
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|
3633 bool Assembler::is_polling_page_far() { |
|
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2357
diff
changeset
|
3634 intptr_t addr = (intptr_t)os::get_polling_page(); |
|
4118
59bc0d4d9ea3
7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
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3938
diff
changeset
|
3635 return ForceUnreachable || |
|
59bc0d4d9ea3
7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
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3938
diff
changeset
|
3636 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) || |
|
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|
3637 !is_simm32(addr - (intptr_t)CodeCache::high_bound()); |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2357
diff
changeset
|
3638 } |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2357
diff
changeset
|
3639 |
| 304 | 3640 void Assembler::emit_data64(jlong data, |
| 3641 relocInfo::relocType rtype, | |
| 3642 int format) { | |
| 3643 if (rtype == relocInfo::none) { | |
| 3644 emit_long64(data); | |
| 3645 } else { | |
| 3646 emit_data64(data, Relocation::spec_simple(rtype), format); | |
| 3647 } | |
| 3648 } | |
| 3649 | |
| 3650 void Assembler::emit_data64(jlong data, | |
| 3651 RelocationHolder const& rspec, | |
| 3652 int format) { | |
| 3653 assert(imm_operand == 0, "default format must be immediate in this file"); | |
| 3654 assert(imm_operand == format, "must be immediate"); | |
| 3655 assert(inst_mark() != NULL, "must be inside InstructionMark"); | |
| 3656 // Do not use AbstractAssembler::relocate, which is not intended for | |
| 3657 // embedded words. Instead, relocate to the enclosing instruction. | |
| 3658 code_section()->relocate(inst_mark(), rspec, format); | |
| 3659 #ifdef ASSERT | |
| 3660 check_relocation(rspec, format); | |
| 3661 #endif | |
| 3662 emit_long64(data); | |
| 3663 } | |
| 3664 | |
| 3665 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) { | |
| 3666 if (reg_enc >= 8) { | |
| 3667 prefix(REX_B); | |
| 3668 reg_enc -= 8; | |
| 3669 } else if (byteinst && reg_enc >= 4) { | |
| 3670 prefix(REX); | |
| 3671 } | |
| 3672 return reg_enc; | |
| 3673 } | |
| 3674 | |
| 3675 int Assembler::prefixq_and_encode(int reg_enc) { | |
| 3676 if (reg_enc < 8) { | |
| 3677 prefix(REX_W); | |
| 3678 } else { | |
| 3679 prefix(REX_WB); | |
| 3680 reg_enc -= 8; | |
| 3681 } | |
| 3682 return reg_enc; | |
| 3683 } | |
| 3684 | |
| 3685 int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) { | |
| 3686 if (dst_enc < 8) { | |
| 3687 if (src_enc >= 8) { | |
| 3688 prefix(REX_B); | |
| 3689 src_enc -= 8; | |
| 3690 } else if (byteinst && src_enc >= 4) { | |
| 3691 prefix(REX); | |
| 3692 } | |
| 3693 } else { | |
| 3694 if (src_enc < 8) { | |
| 3695 prefix(REX_R); | |
| 3696 } else { | |
| 3697 prefix(REX_RB); | |
| 3698 src_enc -= 8; | |
| 3699 } | |
| 3700 dst_enc -= 8; | |
| 3701 } | |
| 3702 return dst_enc << 3 | src_enc; | |
| 3703 } | |
| 3704 | |
| 3705 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) { | |
| 3706 if (dst_enc < 8) { | |
| 3707 if (src_enc < 8) { | |
| 3708 prefix(REX_W); | |
| 3709 } else { | |
| 3710 prefix(REX_WB); | |
| 3711 src_enc -= 8; | |
| 3712 } | |
| 3713 } else { | |
| 3714 if (src_enc < 8) { | |
| 3715 prefix(REX_WR); | |
| 3716 } else { | |
| 3717 prefix(REX_WRB); | |
| 3718 src_enc -= 8; | |
| 3719 } | |
| 3720 dst_enc -= 8; | |
| 3721 } | |
| 3722 return dst_enc << 3 | src_enc; | |
| 3723 } | |
| 3724 | |
| 3725 void Assembler::prefix(Register reg) { | |
| 3726 if (reg->encoding() >= 8) { | |
| 3727 prefix(REX_B); | |
| 3728 } | |
| 3729 } | |
| 3730 | |
| 3731 void Assembler::prefix(Address adr) { | |
| 3732 if (adr.base_needs_rex()) { | |
| 3733 if (adr.index_needs_rex()) { | |
| 3734 prefix(REX_XB); | |
| 3735 } else { | |
| 3736 prefix(REX_B); | |
| 3737 } | |
| 3738 } else { | |
| 3739 if (adr.index_needs_rex()) { | |
| 3740 prefix(REX_X); | |
| 3741 } | |
| 3742 } | |
| 3743 } | |
| 3744 | |
| 3745 void Assembler::prefixq(Address adr) { | |
| 3746 if (adr.base_needs_rex()) { | |
| 3747 if (adr.index_needs_rex()) { | |
| 3748 prefix(REX_WXB); | |
| 3749 } else { | |
| 3750 prefix(REX_WB); | |
| 3751 } | |
| 3752 } else { | |
| 3753 if (adr.index_needs_rex()) { | |
| 3754 prefix(REX_WX); | |
| 3755 } else { | |
| 3756 prefix(REX_W); | |
| 3757 } | |
| 3758 } | |
| 3759 } | |
| 3760 | |
| 3761 | |
| 3762 void Assembler::prefix(Address adr, Register reg, bool byteinst) { | |
| 3763 if (reg->encoding() < 8) { | |
| 3764 if (adr.base_needs_rex()) { | |
| 3765 if (adr.index_needs_rex()) { | |
| 3766 prefix(REX_XB); | |
| 3767 } else { | |
| 3768 prefix(REX_B); | |
| 3769 } | |
| 3770 } else { | |
| 3771 if (adr.index_needs_rex()) { | |
| 3772 prefix(REX_X); | |
| 3855 | 3773 } else if (byteinst && reg->encoding() >= 4 ) { |
| 304 | 3774 prefix(REX); |
| 3775 } | |
| 3776 } | |
| 3777 } else { | |
| 3778 if (adr.base_needs_rex()) { | |
| 3779 if (adr.index_needs_rex()) { | |
| 3780 prefix(REX_RXB); | |
| 3781 } else { | |
| 3782 prefix(REX_RB); | |
| 3783 } | |
| 3784 } else { | |
| 3785 if (adr.index_needs_rex()) { | |
| 3786 prefix(REX_RX); | |
| 3787 } else { | |
| 3788 prefix(REX_R); | |
| 3789 } | |
| 3790 } | |
| 3791 } | |
| 3792 } | |
| 3793 | |
| 3794 void Assembler::prefixq(Address adr, Register src) { | |
| 3795 if (src->encoding() < 8) { | |
| 3796 if (adr.base_needs_rex()) { | |
| 3797 if (adr.index_needs_rex()) { | |
| 3798 prefix(REX_WXB); | |
| 3799 } else { | |
| 3800 prefix(REX_WB); | |
| 3801 } | |
| 3802 } else { | |
| 3803 if (adr.index_needs_rex()) { | |
| 3804 prefix(REX_WX); | |
| 3805 } else { | |
| 3806 prefix(REX_W); | |
| 3807 } | |
| 3808 } | |
| 3809 } else { | |
| 3810 if (adr.base_needs_rex()) { | |
| 3811 if (adr.index_needs_rex()) { | |
| 3812 prefix(REX_WRXB); | |
| 3813 } else { | |
| 3814 prefix(REX_WRB); | |
| 3815 } | |
| 3816 } else { | |
| 3817 if (adr.index_needs_rex()) { | |
| 3818 prefix(REX_WRX); | |
| 3819 } else { | |
| 3820 prefix(REX_WR); | |
| 3821 } | |
| 3822 } | |
| 3823 } | |
| 3824 } | |
| 3825 | |
| 3826 void Assembler::prefix(Address adr, XMMRegister reg) { | |
| 3827 if (reg->encoding() < 8) { | |
| 3828 if (adr.base_needs_rex()) { | |
| 3829 if (adr.index_needs_rex()) { | |
| 3830 prefix(REX_XB); | |
| 3831 } else { | |
| 3832 prefix(REX_B); | |
| 3833 } | |
| 3834 } else { | |
| 3835 if (adr.index_needs_rex()) { | |
| 3836 prefix(REX_X); | |
| 3837 } | |
| 3838 } | |
| 3839 } else { | |
| 3840 if (adr.base_needs_rex()) { | |
| 3841 if (adr.index_needs_rex()) { | |
| 3842 prefix(REX_RXB); | |
| 3843 } else { | |
| 3844 prefix(REX_RB); | |
| 3845 } | |
| 3846 } else { | |
| 3847 if (adr.index_needs_rex()) { | |
| 3848 prefix(REX_RX); | |
| 3849 } else { | |
| 3850 prefix(REX_R); | |
| 3851 } | |
| 3852 } | |
| 3853 } | |
| 3854 } | |
| 3855 | |
| 4759 | 3856 void Assembler::prefixq(Address adr, XMMRegister src) { |
| 3857 if (src->encoding() < 8) { | |
| 3858 if (adr.base_needs_rex()) { | |
| 3859 if (adr.index_needs_rex()) { | |
| 3860 prefix(REX_WXB); | |
| 3861 } else { | |
| 3862 prefix(REX_WB); | |
| 3863 } | |
| 3864 } else { | |
| 3865 if (adr.index_needs_rex()) { | |
| 3866 prefix(REX_WX); | |
| 3867 } else { | |
| 3868 prefix(REX_W); | |
| 3869 } | |
| 3870 } | |
| 3871 } else { | |
| 3872 if (adr.base_needs_rex()) { | |
| 3873 if (adr.index_needs_rex()) { | |
| 3874 prefix(REX_WRXB); | |
| 3875 } else { | |
| 3876 prefix(REX_WRB); | |
| 3877 } | |
| 3878 } else { | |
| 3879 if (adr.index_needs_rex()) { | |
| 3880 prefix(REX_WRX); | |
| 3881 } else { | |
| 3882 prefix(REX_WR); | |
| 3883 } | |
| 3884 } | |
| 3885 } | |
| 3886 } | |
| 3887 | |
| 304 | 3888 void Assembler::adcq(Register dst, int32_t imm32) { |
| 3889 (void) prefixq_and_encode(dst->encoding()); | |
| 3890 emit_arith(0x81, 0xD0, dst, imm32); | |
| 3891 } | |
| 3892 | |
| 3893 void Assembler::adcq(Register dst, Address src) { | |
| 3894 InstructionMark im(this); | |
| 3895 prefixq(src, dst); | |
| 3896 emit_byte(0x13); | |
| 3897 emit_operand(dst, src); | |
| 3898 } | |
| 3899 | |
| 3900 void Assembler::adcq(Register dst, Register src) { | |
| 3901 (int) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3902 emit_arith(0x13, 0xC0, dst, src); | |
| 3903 } | |
| 3904 | |
| 3905 void Assembler::addq(Address dst, int32_t imm32) { | |
| 3906 InstructionMark im(this); | |
| 3907 prefixq(dst); | |
| 3908 emit_arith_operand(0x81, rax, dst,imm32); | |
| 3909 } | |
| 3910 | |
| 3911 void Assembler::addq(Address dst, Register src) { | |
| 3912 InstructionMark im(this); | |
| 3913 prefixq(dst, src); | |
| 3914 emit_byte(0x01); | |
| 3915 emit_operand(src, dst); | |
| 3916 } | |
| 3917 | |
| 3918 void Assembler::addq(Register dst, int32_t imm32) { | |
| 3919 (void) prefixq_and_encode(dst->encoding()); | |
| 3920 emit_arith(0x81, 0xC0, dst, imm32); | |
| 3921 } | |
| 3922 | |
| 3923 void Assembler::addq(Register dst, Address src) { | |
| 3924 InstructionMark im(this); | |
| 3925 prefixq(src, dst); | |
| 3926 emit_byte(0x03); | |
| 3927 emit_operand(dst, src); | |
| 3928 } | |
| 3929 | |
| 3930 void Assembler::addq(Register dst, Register src) { | |
| 3931 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3932 emit_arith(0x03, 0xC0, dst, src); | |
| 3933 } | |
| 3934 | |
| 3783 | 3935 void Assembler::andq(Address dst, int32_t imm32) { |
| 3936 InstructionMark im(this); | |
| 3937 prefixq(dst); | |
| 3938 emit_byte(0x81); | |
| 3939 emit_operand(rsp, dst, 4); | |
| 3940 emit_long(imm32); | |
| 3941 } | |
| 3942 | |
| 304 | 3943 void Assembler::andq(Register dst, int32_t imm32) { |
| 3944 (void) prefixq_and_encode(dst->encoding()); | |
| 3945 emit_arith(0x81, 0xE0, dst, imm32); | |
| 3946 } | |
| 3947 | |
| 3948 void Assembler::andq(Register dst, Address src) { | |
| 3949 InstructionMark im(this); | |
| 3950 prefixq(src, dst); | |
| 3951 emit_byte(0x23); | |
| 3952 emit_operand(dst, src); | |
| 3953 } | |
| 3954 | |
| 3955 void Assembler::andq(Register dst, Register src) { | |
| 3956 (int) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3957 emit_arith(0x23, 0xC0, dst, src); | |
| 3958 } | |
| 3959 | |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
3960 void Assembler::bsfq(Register dst, Register src) { |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
3961 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
3962 emit_byte(0x0F); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
3963 emit_byte(0xBC); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
3964 emit_byte(0xC0 | encode); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
3965 } |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
3966 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
3967 void Assembler::bsrq(Register dst, Register src) { |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
3968 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT"); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
3969 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
3970 emit_byte(0x0F); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
3971 emit_byte(0xBD); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
3972 emit_byte(0xC0 | encode); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
3973 } |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
3974 |
| 304 | 3975 void Assembler::bswapq(Register reg) { |
| 3976 int encode = prefixq_and_encode(reg->encoding()); | |
| 3977 emit_byte(0x0F); | |
| 3978 emit_byte(0xC8 | encode); | |
| 3979 } | |
| 3980 | |
| 3981 void Assembler::cdqq() { | |
| 3982 prefix(REX_W); | |
| 3983 emit_byte(0x99); | |
| 3984 } | |
| 3985 | |
| 3986 void Assembler::clflush(Address adr) { | |
| 3987 prefix(adr); | |
| 3988 emit_byte(0x0F); | |
| 3989 emit_byte(0xAE); | |
| 3990 emit_operand(rdi, adr); | |
| 3991 } | |
| 3992 | |
| 3993 void Assembler::cmovq(Condition cc, Register dst, Register src) { | |
| 3994 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3995 emit_byte(0x0F); | |
| 3996 emit_byte(0x40 | cc); | |
| 3997 emit_byte(0xC0 | encode); | |
| 3998 } | |
| 3999 | |
| 4000 void Assembler::cmovq(Condition cc, Register dst, Address src) { | |
| 4001 InstructionMark im(this); | |
| 4002 prefixq(src, dst); | |
| 4003 emit_byte(0x0F); | |
| 4004 emit_byte(0x40 | cc); | |
| 4005 emit_operand(dst, src); | |
| 4006 } | |
| 4007 | |
| 4008 void Assembler::cmpq(Address dst, int32_t imm32) { | |
| 4009 InstructionMark im(this); | |
| 4010 prefixq(dst); | |
| 4011 emit_byte(0x81); | |
| 4012 emit_operand(rdi, dst, 4); | |
| 4013 emit_long(imm32); | |
| 4014 } | |
| 4015 | |
| 4016 void Assembler::cmpq(Register dst, int32_t imm32) { | |
| 4017 (void) prefixq_and_encode(dst->encoding()); | |
| 4018 emit_arith(0x81, 0xF8, dst, imm32); | |
| 4019 } | |
| 4020 | |
| 4021 void Assembler::cmpq(Address dst, Register src) { | |
| 4022 InstructionMark im(this); | |
| 4023 prefixq(dst, src); | |
| 4024 emit_byte(0x3B); | |
| 4025 emit_operand(src, dst); | |
| 4026 } | |
| 4027 | |
| 4028 void Assembler::cmpq(Register dst, Register src) { | |
| 4029 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4030 emit_arith(0x3B, 0xC0, dst, src); | |
| 4031 } | |
| 4032 | |
| 4033 void Assembler::cmpq(Register dst, Address src) { | |
| 4034 InstructionMark im(this); | |
| 4035 prefixq(src, dst); | |
| 4036 emit_byte(0x3B); | |
| 4037 emit_operand(dst, src); | |
| 4038 } | |
| 4039 | |
| 4040 void Assembler::cmpxchgq(Register reg, Address adr) { | |
| 4041 InstructionMark im(this); | |
| 4042 prefixq(adr, reg); | |
| 4043 emit_byte(0x0F); | |
| 4044 emit_byte(0xB1); | |
| 4045 emit_operand(reg, adr); | |
| 4046 } | |
| 4047 | |
| 4048 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) { | |
| 4049 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 4050 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F2); |
| 304 | 4051 emit_byte(0x2A); |
| 4052 emit_byte(0xC0 | encode); | |
| 4053 } | |
| 4054 | |
| 4759 | 4055 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) { |
| 4056 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4057 InstructionMark im(this); | |
| 4058 simd_prefix_q(dst, dst, src, VEX_SIMD_F2); | |
| 4059 emit_byte(0x2A); | |
| 4060 emit_operand(dst, src); | |
| 4061 } | |
| 4062 | |
| 304 | 4063 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) { |
| 4064 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 4759 | 4065 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F3); |
| 304 | 4066 emit_byte(0x2A); |
| 4067 emit_byte(0xC0 | encode); | |
| 4068 } | |
| 4069 | |
| 4759 | 4070 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) { |
| 4071 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 4072 InstructionMark im(this); | |
| 4073 simd_prefix_q(dst, dst, src, VEX_SIMD_F3); | |
| 4074 emit_byte(0x2A); | |
| 4075 emit_operand(dst, src); | |
| 4076 } | |
| 4077 | |
| 304 | 4078 void Assembler::cvttsd2siq(Register dst, XMMRegister src) { |
| 4079 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 4759 | 4080 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F2); |
| 304 | 4081 emit_byte(0x2C); |
| 4082 emit_byte(0xC0 | encode); | |
| 4083 } | |
| 4084 | |
| 4085 void Assembler::cvttss2siq(Register dst, XMMRegister src) { | |
| 4086 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 4759 | 4087 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F3); |
| 304 | 4088 emit_byte(0x2C); |
| 4089 emit_byte(0xC0 | encode); | |
| 4090 } | |
| 4091 | |
| 4092 void Assembler::decl(Register dst) { | |
| 4093 // Don't use it directly. Use MacroAssembler::decrementl() instead. | |
| 4094 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode) | |
| 4095 int encode = prefix_and_encode(dst->encoding()); | |
| 4096 emit_byte(0xFF); | |
| 4097 emit_byte(0xC8 | encode); | |
| 4098 } | |
| 4099 | |
| 4100 void Assembler::decq(Register dst) { | |
| 4101 // Don't use it directly. Use MacroAssembler::decrementq() instead. | |
| 4102 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |
| 4103 int encode = prefixq_and_encode(dst->encoding()); | |
| 4104 emit_byte(0xFF); | |
| 4105 emit_byte(0xC8 | encode); | |
| 4106 } | |
| 4107 | |
| 4108 void Assembler::decq(Address dst) { | |
| 4109 // Don't use it directly. Use MacroAssembler::decrementq() instead. | |
| 4110 InstructionMark im(this); | |
| 4111 prefixq(dst); | |
| 4112 emit_byte(0xFF); | |
| 4113 emit_operand(rcx, dst); | |
| 4114 } | |
| 4115 | |
| 4116 void Assembler::fxrstor(Address src) { | |
| 4117 prefixq(src); | |
| 4118 emit_byte(0x0F); | |
| 4119 emit_byte(0xAE); | |
| 4120 emit_operand(as_Register(1), src); | |
| 4121 } | |
| 4122 | |
| 4123 void Assembler::fxsave(Address dst) { | |
| 4124 prefixq(dst); | |
| 4125 emit_byte(0x0F); | |
| 4126 emit_byte(0xAE); | |
| 4127 emit_operand(as_Register(0), dst); | |
| 4128 } | |
| 4129 | |
| 4130 void Assembler::idivq(Register src) { | |
| 4131 int encode = prefixq_and_encode(src->encoding()); | |
| 4132 emit_byte(0xF7); | |
| 4133 emit_byte(0xF8 | encode); | |
| 4134 } | |
| 4135 | |
| 4136 void Assembler::imulq(Register dst, Register src) { | |
| 4137 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4138 emit_byte(0x0F); | |
| 4139 emit_byte(0xAF); | |
| 4140 emit_byte(0xC0 | encode); | |
| 4141 } | |
| 4142 | |
| 4143 void Assembler::imulq(Register dst, Register src, int value) { | |
| 4144 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4145 if (is8bit(value)) { | |
| 4146 emit_byte(0x6B); | |
| 4147 emit_byte(0xC0 | encode); | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1846
diff
changeset
|
4148 emit_byte(value & 0xFF); |
| 304 | 4149 } else { |
| 4150 emit_byte(0x69); | |
| 4151 emit_byte(0xC0 | encode); | |
| 4152 emit_long(value); | |
| 4153 } | |
| 4154 } | |
| 4155 | |
| 4156 void Assembler::incl(Register dst) { | |
| 4157 // Don't use it directly. Use MacroAssembler::incrementl() instead. | |
| 4158 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |
| 4159 int encode = prefix_and_encode(dst->encoding()); | |
| 4160 emit_byte(0xFF); | |
| 4161 emit_byte(0xC0 | encode); | |
| 4162 } | |
| 4163 | |
| 4164 void Assembler::incq(Register dst) { | |
| 4165 // Don't use it directly. Use MacroAssembler::incrementq() instead. | |
| 4166 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |
| 4167 int encode = prefixq_and_encode(dst->encoding()); | |
| 4168 emit_byte(0xFF); | |
| 4169 emit_byte(0xC0 | encode); | |
| 4170 } | |
| 4171 | |
| 4172 void Assembler::incq(Address dst) { | |
| 4173 // Don't use it directly. Use MacroAssembler::incrementq() instead. | |
| 4174 InstructionMark im(this); | |
| 4175 prefixq(dst); | |
| 4176 emit_byte(0xFF); | |
| 4177 emit_operand(rax, dst); | |
| 4178 } | |
| 4179 | |
| 4180 void Assembler::lea(Register dst, Address src) { | |
| 4181 leaq(dst, src); | |
| 4182 } | |
| 4183 | |
| 4184 void Assembler::leaq(Register dst, Address src) { | |
| 4185 InstructionMark im(this); | |
| 4186 prefixq(src, dst); | |
| 4187 emit_byte(0x8D); | |
| 4188 emit_operand(dst, src); | |
| 4189 } | |
| 4190 | |
| 4191 void Assembler::mov64(Register dst, int64_t imm64) { | |
| 4192 InstructionMark im(this); | |
| 4193 int encode = prefixq_and_encode(dst->encoding()); | |
| 4194 emit_byte(0xB8 | encode); | |
| 4195 emit_long64(imm64); | |
| 4196 } | |
| 4197 | |
| 4198 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) { | |
| 4199 InstructionMark im(this); | |
| 4200 int encode = prefixq_and_encode(dst->encoding()); | |
| 4201 emit_byte(0xB8 | encode); | |
| 4202 emit_data64(imm64, rspec); | |
| 4203 } | |
| 4204 | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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624
diff
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|
4205 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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624
diff
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|
4206 InstructionMark im(this); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
4207 int encode = prefix_and_encode(dst->encoding()); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
4208 emit_byte(0xB8 | encode); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
4209 emit_data((int)imm32, rspec, narrow_oop_operand); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
4210 } |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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624
diff
changeset
|
4211 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
4212 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4213 InstructionMark im(this); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4214 prefix(dst); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4215 emit_byte(0xC7); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4216 emit_operand(rax, dst, 4); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
4217 emit_data((int)imm32, rspec, narrow_oop_operand); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4218 } |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
4219 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
4220 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
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|
4221 InstructionMark im(this); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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624
diff
changeset
|
4222 int encode = prefix_and_encode(src1->encoding()); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
4223 emit_byte(0x81); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4224 emit_byte(0xF8 | encode); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4225 emit_data((int)imm32, rspec, narrow_oop_operand); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
4226 } |
|
660978a2a31a
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kvn
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624
diff
changeset
|
4227 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
4228 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
4229 InstructionMark im(this); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4230 prefix(src1); |
|
660978a2a31a
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kvn
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624
diff
changeset
|
4231 emit_byte(0x81); |
|
660978a2a31a
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kvn
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624
diff
changeset
|
4232 emit_operand(rax, src1, 4); |
|
660978a2a31a
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624
diff
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|
4233 emit_data((int)imm32, rspec, narrow_oop_operand); |
|
660978a2a31a
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kvn
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624
diff
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|
4234 } |
|
660978a2a31a
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624
diff
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|
4235 |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
4236 void Assembler::lzcntq(Register dst, Register src) { |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
4237 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
4238 emit_byte(0xF3); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
4239 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
|
93c14e5562c4
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twisti
parents:
710
diff
changeset
|
4240 emit_byte(0x0F); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
4241 emit_byte(0xBD); |
|
93c14e5562c4
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twisti
parents:
710
diff
changeset
|
4242 emit_byte(0xC0 | encode); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
4243 } |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
4244 |
| 304 | 4245 void Assembler::movdq(XMMRegister dst, Register src) { |
| 4246 // table D-1 says MMX/SSE2 | |
| 4759 | 4247 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
| 4248 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_66); | |
| 304 | 4249 emit_byte(0x6E); |
| 4250 emit_byte(0xC0 | encode); | |
| 4251 } | |
| 4252 | |
| 4253 void Assembler::movdq(Register dst, XMMRegister src) { | |
| 4254 // table D-1 says MMX/SSE2 | |
| 4759 | 4255 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
| 304 | 4256 // swap src/dst to get correct prefix |
| 4759 | 4257 int encode = simd_prefix_and_encode_q(src, dst, VEX_SIMD_66); |
| 0 | 4258 emit_byte(0x7E); |
| 304 | 4259 emit_byte(0xC0 | encode); |
| 4260 } | |
| 4261 | |
| 4262 void Assembler::movq(Register dst, Register src) { | |
| 4263 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4264 emit_byte(0x8B); | |
| 4265 emit_byte(0xC0 | encode); | |
| 4266 } | |
| 4267 | |
| 4268 void Assembler::movq(Register dst, Address src) { | |
| 4269 InstructionMark im(this); | |
| 4270 prefixq(src, dst); | |
| 4271 emit_byte(0x8B); | |
| 4272 emit_operand(dst, src); | |
| 4273 } | |
| 4274 | |
| 4275 void Assembler::movq(Address dst, Register src) { | |
| 4276 InstructionMark im(this); | |
| 4277 prefixq(dst, src); | |
| 4278 emit_byte(0x89); | |
| 4279 emit_operand(src, dst); | |
| 4280 } | |
| 4281 | |
| 624 | 4282 void Assembler::movsbq(Register dst, Address src) { |
| 4283 InstructionMark im(this); | |
| 4284 prefixq(src, dst); | |
| 4285 emit_byte(0x0F); | |
| 4286 emit_byte(0xBE); | |
| 4287 emit_operand(dst, src); | |
| 4288 } | |
| 4289 | |
| 4290 void Assembler::movsbq(Register dst, Register src) { | |
| 4291 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4292 emit_byte(0x0F); | |
| 4293 emit_byte(0xBE); | |
| 4294 emit_byte(0xC0 | encode); | |
| 4295 } | |
| 4296 | |
| 304 | 4297 void Assembler::movslq(Register dst, int32_t imm32) { |
| 4298 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx) | |
| 4299 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx) | |
| 4300 // as a result we shouldn't use until tested at runtime... | |
| 4301 ShouldNotReachHere(); | |
| 4302 InstructionMark im(this); | |
| 4303 int encode = prefixq_and_encode(dst->encoding()); | |
| 4304 emit_byte(0xC7 | encode); | |
| 4305 emit_long(imm32); | |
| 4306 } | |
| 4307 | |
| 4308 void Assembler::movslq(Address dst, int32_t imm32) { | |
| 4309 assert(is_simm32(imm32), "lost bits"); | |
| 4310 InstructionMark im(this); | |
| 4311 prefixq(dst); | |
| 4312 emit_byte(0xC7); | |
| 4313 emit_operand(rax, dst, 4); | |
| 4314 emit_long(imm32); | |
| 4315 } | |
| 4316 | |
| 4317 void Assembler::movslq(Register dst, Address src) { | |
| 4318 InstructionMark im(this); | |
| 4319 prefixq(src, dst); | |
| 4320 emit_byte(0x63); | |
| 4321 emit_operand(dst, src); | |
| 4322 } | |
| 4323 | |
| 4324 void Assembler::movslq(Register dst, Register src) { | |
| 4325 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4326 emit_byte(0x63); | |
| 4327 emit_byte(0xC0 | encode); | |
| 4328 } | |
| 4329 | |
| 624 | 4330 void Assembler::movswq(Register dst, Address src) { |
| 4331 InstructionMark im(this); | |
| 4332 prefixq(src, dst); | |
| 4333 emit_byte(0x0F); | |
| 4334 emit_byte(0xBF); | |
| 4335 emit_operand(dst, src); | |
| 4336 } | |
| 4337 | |
| 4338 void Assembler::movswq(Register dst, Register src) { | |
| 4339 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4340 emit_byte(0x0F); | |
| 4341 emit_byte(0xBF); | |
| 4342 emit_byte(0xC0 | encode); | |
| 4343 } | |
| 4344 | |
| 4345 void Assembler::movzbq(Register dst, Address src) { | |
| 4346 InstructionMark im(this); | |
| 4347 prefixq(src, dst); | |
| 4348 emit_byte(0x0F); | |
| 4349 emit_byte(0xB6); | |
| 4350 emit_operand(dst, src); | |
| 4351 } | |
| 4352 | |
| 4353 void Assembler::movzbq(Register dst, Register src) { | |
| 4354 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4355 emit_byte(0x0F); | |
| 4356 emit_byte(0xB6); | |
| 4357 emit_byte(0xC0 | encode); | |
| 4358 } | |
| 4359 | |
| 4360 void Assembler::movzwq(Register dst, Address src) { | |
| 4361 InstructionMark im(this); | |
| 4362 prefixq(src, dst); | |
| 4363 emit_byte(0x0F); | |
| 4364 emit_byte(0xB7); | |
| 4365 emit_operand(dst, src); | |
| 4366 } | |
| 4367 | |
| 4368 void Assembler::movzwq(Register dst, Register src) { | |
| 4369 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4370 emit_byte(0x0F); | |
| 4371 emit_byte(0xB7); | |
| 4372 emit_byte(0xC0 | encode); | |
| 4373 } | |
| 4374 | |
| 304 | 4375 void Assembler::negq(Register dst) { |
| 4376 int encode = prefixq_and_encode(dst->encoding()); | |
| 4377 emit_byte(0xF7); | |
| 4378 emit_byte(0xD8 | encode); | |
| 4379 } | |
| 4380 | |
| 4381 void Assembler::notq(Register dst) { | |
| 4382 int encode = prefixq_and_encode(dst->encoding()); | |
| 4383 emit_byte(0xF7); | |
| 4384 emit_byte(0xD0 | encode); | |
| 4385 } | |
| 4386 | |
| 4387 void Assembler::orq(Address dst, int32_t imm32) { | |
| 4388 InstructionMark im(this); | |
| 4389 prefixq(dst); | |
| 4390 emit_byte(0x81); | |
| 4391 emit_operand(rcx, dst, 4); | |
| 4392 emit_long(imm32); | |
| 4393 } | |
| 4394 | |
| 4395 void Assembler::orq(Register dst, int32_t imm32) { | |
| 4396 (void) prefixq_and_encode(dst->encoding()); | |
| 4397 emit_arith(0x81, 0xC8, dst, imm32); | |
| 4398 } | |
| 4399 | |
| 4400 void Assembler::orq(Register dst, Address src) { | |
| 4401 InstructionMark im(this); | |
| 4402 prefixq(src, dst); | |
| 4403 emit_byte(0x0B); | |
| 4404 emit_operand(dst, src); | |
| 4405 } | |
| 4406 | |
| 4407 void Assembler::orq(Register dst, Register src) { | |
| 4408 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4409 emit_arith(0x0B, 0xC0, dst, src); | |
| 4410 } | |
| 4411 | |
| 4412 void Assembler::popa() { // 64bit | |
| 4413 movq(r15, Address(rsp, 0)); | |
| 4414 movq(r14, Address(rsp, wordSize)); | |
| 4415 movq(r13, Address(rsp, 2 * wordSize)); | |
| 4416 movq(r12, Address(rsp, 3 * wordSize)); | |
| 4417 movq(r11, Address(rsp, 4 * wordSize)); | |
| 4418 movq(r10, Address(rsp, 5 * wordSize)); | |
| 4419 movq(r9, Address(rsp, 6 * wordSize)); | |
| 4420 movq(r8, Address(rsp, 7 * wordSize)); | |
| 4421 movq(rdi, Address(rsp, 8 * wordSize)); | |
| 4422 movq(rsi, Address(rsp, 9 * wordSize)); | |
| 4423 movq(rbp, Address(rsp, 10 * wordSize)); | |
| 4424 // skip rsp | |
| 4425 movq(rbx, Address(rsp, 12 * wordSize)); | |
| 4426 movq(rdx, Address(rsp, 13 * wordSize)); | |
| 4427 movq(rcx, Address(rsp, 14 * wordSize)); | |
| 4428 movq(rax, Address(rsp, 15 * wordSize)); | |
| 4429 | |
| 4430 addq(rsp, 16 * wordSize); | |
| 4431 } | |
| 4432 | |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4433 void Assembler::popcntq(Register dst, Address src) { |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4434 assert(VM_Version::supports_popcnt(), "must support"); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4435 InstructionMark im(this); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4436 emit_byte(0xF3); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4437 prefixq(src, dst); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4438 emit_byte(0x0F); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4439 emit_byte(0xB8); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4440 emit_operand(dst, src); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4441 } |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4442 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4443 void Assembler::popcntq(Register dst, Register src) { |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4444 assert(VM_Version::supports_popcnt(), "must support"); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4445 emit_byte(0xF3); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4446 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
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642
diff
changeset
|
4447 emit_byte(0x0F); |
|
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|
4448 emit_byte(0xB8); |
|
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|
4449 emit_byte(0xC0 | encode); |
|
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|
4450 } |
|
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|
4451 |
| 304 | 4452 void Assembler::popq(Address dst) { |
| 4453 InstructionMark im(this); | |
| 4454 prefixq(dst); | |
| 4455 emit_byte(0x8F); | |
| 4456 emit_operand(rax, dst); | |
| 4457 } | |
| 4458 | |
| 4459 void Assembler::pusha() { // 64bit | |
| 4460 // we have to store original rsp. ABI says that 128 bytes | |
| 4461 // below rsp are local scratch. | |
| 4462 movq(Address(rsp, -5 * wordSize), rsp); | |
| 4463 | |
| 4464 subq(rsp, 16 * wordSize); | |
| 4465 | |
| 4466 movq(Address(rsp, 15 * wordSize), rax); | |
| 4467 movq(Address(rsp, 14 * wordSize), rcx); | |
| 4468 movq(Address(rsp, 13 * wordSize), rdx); | |
| 4469 movq(Address(rsp, 12 * wordSize), rbx); | |
| 4470 // skip rsp | |
| 4471 movq(Address(rsp, 10 * wordSize), rbp); | |
| 4472 movq(Address(rsp, 9 * wordSize), rsi); | |
| 4473 movq(Address(rsp, 8 * wordSize), rdi); | |
| 4474 movq(Address(rsp, 7 * wordSize), r8); | |
| 4475 movq(Address(rsp, 6 * wordSize), r9); | |
| 4476 movq(Address(rsp, 5 * wordSize), r10); | |
| 4477 movq(Address(rsp, 4 * wordSize), r11); | |
| 4478 movq(Address(rsp, 3 * wordSize), r12); | |
| 4479 movq(Address(rsp, 2 * wordSize), r13); | |
| 4480 movq(Address(rsp, wordSize), r14); | |
| 4481 movq(Address(rsp, 0), r15); | |
| 4482 } | |
| 4483 | |
| 4484 void Assembler::pushq(Address src) { | |
| 4485 InstructionMark im(this); | |
| 4486 prefixq(src); | |
| 4487 emit_byte(0xFF); | |
| 4488 emit_operand(rsi, src); | |
| 4489 } | |
| 4490 | |
| 4491 void Assembler::rclq(Register dst, int imm8) { | |
| 4492 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
| 4493 int encode = prefixq_and_encode(dst->encoding()); | |
| 4494 if (imm8 == 1) { | |
| 4495 emit_byte(0xD1); | |
| 4496 emit_byte(0xD0 | encode); | |
| 4497 } else { | |
| 4498 emit_byte(0xC1); | |
| 4499 emit_byte(0xD0 | encode); | |
| 4500 emit_byte(imm8); | |
| 4501 } | |
| 4502 } | |
| 4503 void Assembler::sarq(Register dst, int imm8) { | |
| 4504 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
| 4505 int encode = prefixq_and_encode(dst->encoding()); | |
| 4506 if (imm8 == 1) { | |
| 4507 emit_byte(0xD1); | |
| 4508 emit_byte(0xF8 | encode); | |
| 4509 } else { | |
| 4510 emit_byte(0xC1); | |
| 4511 emit_byte(0xF8 | encode); | |
| 4512 emit_byte(imm8); | |
| 4513 } | |
| 4514 } | |
| 4515 | |
| 4516 void Assembler::sarq(Register dst) { | |
| 4517 int encode = prefixq_and_encode(dst->encoding()); | |
| 4518 emit_byte(0xD3); | |
| 4519 emit_byte(0xF8 | encode); | |
| 4520 } | |
|
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4521 |
| 304 | 4522 void Assembler::sbbq(Address dst, int32_t imm32) { |
| 4523 InstructionMark im(this); | |
| 4524 prefixq(dst); | |
| 4525 emit_arith_operand(0x81, rbx, dst, imm32); | |
| 4526 } | |
| 4527 | |
| 4528 void Assembler::sbbq(Register dst, int32_t imm32) { | |
| 4529 (void) prefixq_and_encode(dst->encoding()); | |
| 4530 emit_arith(0x81, 0xD8, dst, imm32); | |
| 4531 } | |
| 4532 | |
| 4533 void Assembler::sbbq(Register dst, Address src) { | |
| 4534 InstructionMark im(this); | |
| 4535 prefixq(src, dst); | |
| 4536 emit_byte(0x1B); | |
| 4537 emit_operand(dst, src); | |
| 4538 } | |
| 4539 | |
| 4540 void Assembler::sbbq(Register dst, Register src) { | |
| 4541 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4542 emit_arith(0x1B, 0xC0, dst, src); | |
| 4543 } | |
| 4544 | |
| 4545 void Assembler::shlq(Register dst, int imm8) { | |
| 4546 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
| 4547 int encode = prefixq_and_encode(dst->encoding()); | |
| 4548 if (imm8 == 1) { | |
| 4549 emit_byte(0xD1); | |
| 4550 emit_byte(0xE0 | encode); | |
| 4551 } else { | |
| 4552 emit_byte(0xC1); | |
| 4553 emit_byte(0xE0 | encode); | |
| 4554 emit_byte(imm8); | |
| 4555 } | |
| 4556 } | |
| 4557 | |
| 4558 void Assembler::shlq(Register dst) { | |
| 4559 int encode = prefixq_and_encode(dst->encoding()); | |
| 4560 emit_byte(0xD3); | |
| 4561 emit_byte(0xE0 | encode); | |
| 4562 } | |
| 4563 | |
| 4564 void Assembler::shrq(Register dst, int imm8) { | |
| 4565 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
| 4566 int encode = prefixq_and_encode(dst->encoding()); | |
| 4567 emit_byte(0xC1); | |
| 4568 emit_byte(0xE8 | encode); | |
| 4569 emit_byte(imm8); | |
| 4570 } | |
| 4571 | |
| 4572 void Assembler::shrq(Register dst) { | |
| 4573 int encode = prefixq_and_encode(dst->encoding()); | |
| 4574 emit_byte(0xD3); | |
| 4575 emit_byte(0xE8 | encode); | |
| 4576 } | |
| 4577 | |
| 4578 void Assembler::subq(Address dst, int32_t imm32) { | |
| 4579 InstructionMark im(this); | |
| 4580 prefixq(dst); | |
|
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|
4581 emit_arith_operand(0x81, rbp, dst, imm32); |
| 304 | 4582 } |
| 4583 | |
| 4584 void Assembler::subq(Address dst, Register src) { | |
| 4585 InstructionMark im(this); | |
| 4586 prefixq(dst, src); | |
| 4587 emit_byte(0x29); | |
| 4588 emit_operand(src, dst); | |
| 4589 } | |
| 4590 | |
|
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|
4591 void Assembler::subq(Register dst, int32_t imm32) { |
|
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|
4592 (void) prefixq_and_encode(dst->encoding()); |
|
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|
4593 emit_arith(0x81, 0xE8, dst, imm32); |
|
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|
4594 } |
|
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|
4595 |
| 304 | 4596 void Assembler::subq(Register dst, Address src) { |
| 4597 InstructionMark im(this); | |
| 4598 prefixq(src, dst); | |
| 4599 emit_byte(0x2B); | |
| 4600 emit_operand(dst, src); | |
| 4601 } | |
| 4602 | |
| 4603 void Assembler::subq(Register dst, Register src) { | |
| 4604 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4605 emit_arith(0x2B, 0xC0, dst, src); | |
| 4606 } | |
| 4607 | |
| 4608 void Assembler::testq(Register dst, int32_t imm32) { | |
| 4609 // not using emit_arith because test | |
| 4610 // doesn't support sign-extension of | |
| 4611 // 8bit operands | |
| 4612 int encode = dst->encoding(); | |
| 4613 if (encode == 0) { | |
| 4614 prefix(REX_W); | |
| 4615 emit_byte(0xA9); | |
| 4616 } else { | |
| 4617 encode = prefixq_and_encode(encode); | |
| 4618 emit_byte(0xF7); | |
| 4619 emit_byte(0xC0 | encode); | |
| 4620 } | |
| 4621 emit_long(imm32); | |
| 4622 } | |
| 4623 | |
| 4624 void Assembler::testq(Register dst, Register src) { | |
| 4625 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4626 emit_arith(0x85, 0xC0, dst, src); | |
| 4627 } | |
| 4628 | |
| 4629 void Assembler::xaddq(Address dst, Register src) { | |
| 4630 InstructionMark im(this); | |
| 4631 prefixq(dst, src); | |
| 71 | 4632 emit_byte(0x0F); |
| 304 | 4633 emit_byte(0xC1); |
| 4634 emit_operand(src, dst); | |
| 4635 } | |
| 4636 | |
| 4637 void Assembler::xchgq(Register dst, Address src) { | |
| 4638 InstructionMark im(this); | |
| 4639 prefixq(src, dst); | |
| 4640 emit_byte(0x87); | |
| 4641 emit_operand(dst, src); | |
| 4642 } | |
| 4643 | |
| 4644 void Assembler::xchgq(Register dst, Register src) { | |
| 4645 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4646 emit_byte(0x87); | |
| 4647 emit_byte(0xc0 | encode); | |
| 4648 } | |
| 4649 | |
| 4650 void Assembler::xorq(Register dst, Register src) { | |
| 4651 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4652 emit_arith(0x33, 0xC0, dst, src); | |
| 4653 } | |
| 4654 | |
| 4655 void Assembler::xorq(Register dst, Address src) { | |
| 4656 InstructionMark im(this); | |
| 4657 prefixq(src, dst); | |
| 4658 emit_byte(0x33); | |
| 4659 emit_operand(dst, src); | |
| 4660 } | |
| 4661 | |
| 4662 #endif // !LP64 | |
| 4663 | |
| 4664 static Assembler::Condition reverse[] = { | |
| 4665 Assembler::noOverflow /* overflow = 0x0 */ , | |
| 4666 Assembler::overflow /* noOverflow = 0x1 */ , | |
| 4667 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ , | |
| 4668 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ , | |
| 4669 Assembler::notZero /* zero = 0x4, equal = 0x4 */ , | |
| 4670 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ , | |
| 4671 Assembler::above /* belowEqual = 0x6 */ , | |
| 4672 Assembler::belowEqual /* above = 0x7 */ , | |
| 4673 Assembler::positive /* negative = 0x8 */ , | |
| 4674 Assembler::negative /* positive = 0x9 */ , | |
| 4675 Assembler::noParity /* parity = 0xa */ , | |
| 4676 Assembler::parity /* noParity = 0xb */ , | |
| 4677 Assembler::greaterEqual /* less = 0xc */ , | |
| 4678 Assembler::less /* greaterEqual = 0xd */ , | |
| 4679 Assembler::greater /* lessEqual = 0xe */ , | |
| 4680 Assembler::lessEqual /* greater = 0xf, */ | |
| 4681 | |
| 4682 }; | |
| 4683 | |
| 0 | 4684 |
| 4685 // Implementation of MacroAssembler | |
| 4686 | |
| 304 | 4687 // First all the versions that have distinct versions depending on 32/64 bit |
| 4688 // Unless the difference is trivial (1 line or so). | |
| 4689 | |
| 4690 #ifndef _LP64 | |
| 4691 | |
| 4692 // 32bit versions | |
| 4693 | |
| 0 | 4694 Address MacroAssembler::as_Address(AddressLiteral adr) { |
| 4695 return Address(adr.target(), adr.rspec()); | |
| 4696 } | |
| 4697 | |
| 4698 Address MacroAssembler::as_Address(ArrayAddress adr) { | |
| 4699 return Address::make_array(adr); | |
| 4700 } | |
| 4701 | |
| 304 | 4702 int MacroAssembler::biased_locking_enter(Register lock_reg, |
| 4703 Register obj_reg, | |
| 4704 Register swap_reg, | |
| 4705 Register tmp_reg, | |
| 4706 bool swap_reg_contains_mark, | |
| 4707 Label& done, | |
| 4708 Label* slow_case, | |
| 4709 BiasedLockingCounters* counters) { | |
| 4710 assert(UseBiasedLocking, "why call this otherwise?"); | |
| 4711 assert(swap_reg == rax, "swap_reg must be rax, for cmpxchg"); | |
| 4712 assert_different_registers(lock_reg, obj_reg, swap_reg); | |
| 4713 | |
| 4714 if (PrintBiasedLockingStatistics && counters == NULL) | |
| 4715 counters = BiasedLocking::counters(); | |
| 4716 | |
| 4717 bool need_tmp_reg = false; | |
| 4718 if (tmp_reg == noreg) { | |
| 4719 need_tmp_reg = true; | |
| 4720 tmp_reg = lock_reg; | |
| 4721 } else { | |
| 4722 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg); | |
| 4723 } | |
| 4724 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); | |
| 4725 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes()); | |
| 4726 Address klass_addr (obj_reg, oopDesc::klass_offset_in_bytes()); | |
| 4727 Address saved_mark_addr(lock_reg, 0); | |
| 4728 | |
| 4729 // Biased locking | |
| 4730 // See whether the lock is currently biased toward our thread and | |
| 4731 // whether the epoch is still valid | |
| 4732 // Note that the runtime guarantees sufficient alignment of JavaThread | |
| 4733 // pointers to allow age to be placed into low bits | |
| 4734 // First check to see whether biasing is even enabled for this object | |
| 4735 Label cas_label; | |
| 4736 int null_check_offset = -1; | |
| 4737 if (!swap_reg_contains_mark) { | |
| 4738 null_check_offset = offset(); | |
| 4739 movl(swap_reg, mark_addr); | |
| 4740 } | |
| 4741 if (need_tmp_reg) { | |
| 4742 push(tmp_reg); | |
| 4743 } | |
| 4744 movl(tmp_reg, swap_reg); | |
| 4745 andl(tmp_reg, markOopDesc::biased_lock_mask_in_place); | |
| 4746 cmpl(tmp_reg, markOopDesc::biased_lock_pattern); | |
| 4747 if (need_tmp_reg) { | |
| 4748 pop(tmp_reg); | |
| 4749 } | |
| 4750 jcc(Assembler::notEqual, cas_label); | |
| 4751 // The bias pattern is present in the object's header. Need to check | |
| 4752 // whether the bias owner and the epoch are both still current. | |
| 4753 // Note that because there is no current thread register on x86 we | |
| 4754 // need to store off the mark word we read out of the object to | |
| 4755 // avoid reloading it and needing to recheck invariants below. This | |
| 4756 // store is unfortunate but it makes the overall code shorter and | |
| 4757 // simpler. | |
| 4758 movl(saved_mark_addr, swap_reg); | |
| 4759 if (need_tmp_reg) { | |
| 4760 push(tmp_reg); | |
| 4761 } | |
| 4762 get_thread(tmp_reg); | |
| 4763 xorl(swap_reg, tmp_reg); | |
| 4764 if (swap_reg_contains_mark) { | |
| 4765 null_check_offset = offset(); | |
| 4766 } | |
| 4767 movl(tmp_reg, klass_addr); | |
| 4768 xorl(swap_reg, Address(tmp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); | |
| 4769 andl(swap_reg, ~((int) markOopDesc::age_mask_in_place)); | |
| 4770 if (need_tmp_reg) { | |
| 4771 pop(tmp_reg); | |
| 4772 } | |
| 4773 if (counters != NULL) { | |
| 4774 cond_inc32(Assembler::zero, | |
| 4775 ExternalAddress((address)counters->biased_lock_entry_count_addr())); | |
| 4776 } | |
| 4777 jcc(Assembler::equal, done); | |
| 4778 | |
| 4779 Label try_revoke_bias; | |
| 4780 Label try_rebias; | |
| 4781 | |
| 4782 // At this point we know that the header has the bias pattern and | |
| 4783 // that we are not the bias owner in the current epoch. We need to | |
| 4784 // figure out more details about the state of the header in order to | |
| 4785 // know what operations can be legally performed on the object's | |
| 4786 // header. | |
| 4787 | |
| 4788 // If the low three bits in the xor result aren't clear, that means | |
| 4789 // the prototype header is no longer biased and we have to revoke | |
| 4790 // the bias on this object. | |
| 4791 testl(swap_reg, markOopDesc::biased_lock_mask_in_place); | |
| 4792 jcc(Assembler::notZero, try_revoke_bias); | |
| 4793 | |
| 4794 // Biasing is still enabled for this data type. See whether the | |
| 4795 // epoch of the current bias is still valid, meaning that the epoch | |
| 4796 // bits of the mark word are equal to the epoch bits of the | |
| 4797 // prototype header. (Note that the prototype header's epoch bits | |
| 4798 // only change at a safepoint.) If not, attempt to rebias the object | |
| 4799 // toward the current thread. Note that we must be absolutely sure | |
| 4800 // that the current epoch is invalid in order to do this because | |
| 4801 // otherwise the manipulations it performs on the mark word are | |
| 4802 // illegal. | |
| 4803 testl(swap_reg, markOopDesc::epoch_mask_in_place); | |
| 4804 jcc(Assembler::notZero, try_rebias); | |
| 4805 | |
| 4806 // The epoch of the current bias is still valid but we know nothing | |
| 4807 // about the owner; it might be set or it might be clear. Try to | |
| 4808 // acquire the bias of the object using an atomic operation. If this | |
| 4809 // fails we will go in to the runtime to revoke the object's bias. | |
| 4810 // Note that we first construct the presumed unbiased header so we | |
| 4811 // don't accidentally blow away another thread's valid bias. | |
| 4812 movl(swap_reg, saved_mark_addr); | |
| 4813 andl(swap_reg, | |
| 4814 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place); | |
| 4815 if (need_tmp_reg) { | |
| 4816 push(tmp_reg); | |
| 4817 } | |
| 4818 get_thread(tmp_reg); | |
| 4819 orl(tmp_reg, swap_reg); | |
| 4820 if (os::is_MP()) { | |
| 4821 lock(); | |
| 4822 } | |
| 4823 cmpxchgptr(tmp_reg, Address(obj_reg, 0)); | |
| 4824 if (need_tmp_reg) { | |
| 4825 pop(tmp_reg); | |
| 4826 } | |
| 4827 // If the biasing toward our thread failed, this means that | |
| 4828 // another thread succeeded in biasing it toward itself and we | |
| 4829 // need to revoke that bias. The revocation will occur in the | |
| 4830 // interpreter runtime in the slow case. | |
| 4831 if (counters != NULL) { | |
| 4832 cond_inc32(Assembler::zero, | |
| 4833 ExternalAddress((address)counters->anonymously_biased_lock_entry_count_addr())); | |
| 4834 } | |
| 4835 if (slow_case != NULL) { | |
| 4836 jcc(Assembler::notZero, *slow_case); | |
| 4837 } | |
| 4838 jmp(done); | |
| 4839 | |
| 4840 bind(try_rebias); | |
| 4841 // At this point we know the epoch has expired, meaning that the | |
| 4842 // current "bias owner", if any, is actually invalid. Under these | |
| 4843 // circumstances _only_, we are allowed to use the current header's | |
| 4844 // value as the comparison value when doing the cas to acquire the | |
| 4845 // bias in the current epoch. In other words, we allow transfer of | |
| 4846 // the bias from one thread to another directly in this situation. | |
| 4847 // | |
| 4848 // FIXME: due to a lack of registers we currently blow away the age | |
| 4849 // bits in this situation. Should attempt to preserve them. | |
| 4850 if (need_tmp_reg) { | |
| 4851 push(tmp_reg); | |
| 4852 } | |
| 4853 get_thread(tmp_reg); | |
| 4854 movl(swap_reg, klass_addr); | |
| 4855 orl(tmp_reg, Address(swap_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); | |
| 4856 movl(swap_reg, saved_mark_addr); | |
| 4857 if (os::is_MP()) { | |
| 4858 lock(); | |
| 4859 } | |
| 4860 cmpxchgptr(tmp_reg, Address(obj_reg, 0)); | |
| 4861 if (need_tmp_reg) { | |
| 4862 pop(tmp_reg); | |
| 4863 } | |
| 4864 // If the biasing toward our thread failed, then another thread | |
| 4865 // succeeded in biasing it toward itself and we need to revoke that | |
| 4866 // bias. The revocation will occur in the runtime in the slow case. | |
| 4867 if (counters != NULL) { | |
| 4868 cond_inc32(Assembler::zero, | |
| 4869 ExternalAddress((address)counters->rebiased_lock_entry_count_addr())); | |
| 4870 } | |
| 4871 if (slow_case != NULL) { | |
| 4872 jcc(Assembler::notZero, *slow_case); | |
| 4873 } | |
| 4874 jmp(done); | |
| 4875 | |
| 4876 bind(try_revoke_bias); | |
| 4877 // The prototype mark in the klass doesn't have the bias bit set any | |
| 4878 // more, indicating that objects of this data type are not supposed | |
| 4879 // to be biased any more. We are going to try to reset the mark of | |
| 4880 // this object to the prototype value and fall through to the | |
| 4881 // CAS-based locking scheme. Note that if our CAS fails, it means | |
| 4882 // that another thread raced us for the privilege of revoking the | |
| 4883 // bias of this particular object, so it's okay to continue in the | |
| 4884 // normal locking code. | |
| 4885 // | |
| 4886 // FIXME: due to a lack of registers we currently blow away the age | |
| 4887 // bits in this situation. Should attempt to preserve them. | |
| 4888 movl(swap_reg, saved_mark_addr); | |
| 4889 if (need_tmp_reg) { | |
| 4890 push(tmp_reg); | |
| 4891 } | |
| 4892 movl(tmp_reg, klass_addr); | |
| 4893 movl(tmp_reg, Address(tmp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); | |
| 4894 if (os::is_MP()) { | |
| 4895 lock(); | |
| 4896 } | |
| 4897 cmpxchgptr(tmp_reg, Address(obj_reg, 0)); | |
| 4898 if (need_tmp_reg) { | |
| 4899 pop(tmp_reg); | |
| 4900 } | |
| 4901 // Fall through to the normal CAS-based lock, because no matter what | |
| 4902 // the result of the above CAS, some thread must have succeeded in | |
| 4903 // removing the bias bit from the object's header. | |
| 4904 if (counters != NULL) { | |
| 4905 cond_inc32(Assembler::zero, | |
| 4906 ExternalAddress((address)counters->revoked_lock_entry_count_addr())); | |
| 4907 } | |
| 4908 | |
| 4909 bind(cas_label); | |
| 4910 | |
| 4911 return null_check_offset; | |
| 4912 } | |
| 4913 void MacroAssembler::call_VM_leaf_base(address entry_point, | |
| 4914 int number_of_arguments) { | |
| 4915 call(RuntimeAddress(entry_point)); | |
| 4916 increment(rsp, number_of_arguments * wordSize); | |
| 4917 } | |
| 4918 | |
| 4919 void MacroAssembler::cmpoop(Address src1, jobject obj) { | |
| 4920 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); | |
| 4921 } | |
| 4922 | |
| 4923 void MacroAssembler::cmpoop(Register src1, jobject obj) { | |
| 4924 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); | |
| 4925 } | |
| 4926 | |
| 4927 void MacroAssembler::extend_sign(Register hi, Register lo) { | |
| 4928 // According to Intel Doc. AP-526, "Integer Divide", p.18. | |
| 4929 if (VM_Version::is_P6() && hi == rdx && lo == rax) { | |
| 4930 cdql(); | |
| 4931 } else { | |
| 4932 movl(hi, lo); | |
| 4933 sarl(hi, 31); | |
| 4934 } | |
| 4935 } | |
| 4936 | |
| 0 | 4937 void MacroAssembler::fat_nop() { |
| 4938 // A 5 byte nop that is safe for patching (see patch_verified_entry) | |
| 4939 emit_byte(0x26); // es: | |
| 4940 emit_byte(0x2e); // cs: | |
| 4941 emit_byte(0x64); // fs: | |
| 4942 emit_byte(0x65); // gs: | |
| 4943 emit_byte(0x90); | |
| 4944 } | |
| 4945 | |
| 304 | 4946 void MacroAssembler::jC2(Register tmp, Label& L) { |
| 4947 // set parity bit if FPU flag C2 is set (via rax) | |
| 4948 save_rax(tmp); | |
| 4949 fwait(); fnstsw_ax(); | |
| 4950 sahf(); | |
| 4951 restore_rax(tmp); | |
| 4952 // branch | |
| 4953 jcc(Assembler::parity, L); | |
| 4954 } | |
| 4955 | |
| 4956 void MacroAssembler::jnC2(Register tmp, Label& L) { | |
| 4957 // set parity bit if FPU flag C2 is set (via rax) | |
| 4958 save_rax(tmp); | |
| 4959 fwait(); fnstsw_ax(); | |
| 4960 sahf(); | |
| 4961 restore_rax(tmp); | |
| 4962 // branch | |
| 4963 jcc(Assembler::noParity, L); | |
| 4964 } | |
| 4965 | |
| 0 | 4966 // 32bit can do a case table jump in one instruction but we no longer allow the base |
| 4967 // to be installed in the Address class | |
| 4968 void MacroAssembler::jump(ArrayAddress entry) { | |
| 4969 jmp(as_Address(entry)); | |
| 4970 } | |
| 4971 | |
| 304 | 4972 // Note: y_lo will be destroyed |
| 4973 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { | |
| 4974 // Long compare for Java (semantics as described in JVM spec.) | |
| 4975 Label high, low, done; | |
| 4976 | |
| 4977 cmpl(x_hi, y_hi); | |
| 4978 jcc(Assembler::less, low); | |
| 4979 jcc(Assembler::greater, high); | |
| 4980 // x_hi is the return register | |
| 4981 xorl(x_hi, x_hi); | |
| 4982 cmpl(x_lo, y_lo); | |
| 4983 jcc(Assembler::below, low); | |
| 4984 jcc(Assembler::equal, done); | |
| 4985 | |
| 4986 bind(high); | |
| 4987 xorl(x_hi, x_hi); | |
| 4988 increment(x_hi); | |
| 4989 jmp(done); | |
| 4990 | |
| 4991 bind(low); | |
| 4992 xorl(x_hi, x_hi); | |
| 4993 decrementl(x_hi); | |
| 4994 | |
| 4995 bind(done); | |
| 4996 } | |
| 4997 | |
| 4998 void MacroAssembler::lea(Register dst, AddressLiteral src) { | |
| 4999 mov_literal32(dst, (int32_t)src.target(), src.rspec()); | |
| 0 | 5000 } |
| 5001 | |
| 5002 void MacroAssembler::lea(Address dst, AddressLiteral adr) { | |
| 5003 // leal(dst, as_Address(adr)); | |
| 304 | 5004 // see note in movl as to why we must use a move |
| 0 | 5005 mov_literal32(dst, (int32_t) adr.target(), adr.rspec()); |
| 5006 } | |
| 5007 | |
| 5008 void MacroAssembler::leave() { | |
| 304 | 5009 mov(rsp, rbp); |
| 5010 pop(rbp); | |
| 5011 } | |
| 0 | 5012 |
| 5013 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) { | |
| 5014 // Multiplication of two Java long values stored on the stack | |
| 5015 // as illustrated below. Result is in rdx:rax. | |
| 5016 // | |
| 5017 // rsp ---> [ ?? ] \ \ | |
| 5018 // .... | y_rsp_offset | | |
| 5019 // [ y_lo ] / (in bytes) | x_rsp_offset | |
| 5020 // [ y_hi ] | (in bytes) | |
| 5021 // .... | | |
| 5022 // [ x_lo ] / | |
| 5023 // [ x_hi ] | |
| 5024 // .... | |
| 5025 // | |
| 5026 // Basic idea: lo(result) = lo(x_lo * y_lo) | |
| 5027 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) | |
| 5028 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset); | |
| 5029 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset); | |
| 5030 Label quick; | |
| 5031 // load x_hi, y_hi and check if quick | |
| 5032 // multiplication is possible | |
| 5033 movl(rbx, x_hi); | |
| 5034 movl(rcx, y_hi); | |
| 5035 movl(rax, rbx); | |
| 5036 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0 | |
| 5037 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply | |
| 5038 // do full multiplication | |
| 5039 // 1st step | |
| 5040 mull(y_lo); // x_hi * y_lo | |
| 5041 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx, | |
| 5042 // 2nd step | |
| 5043 movl(rax, x_lo); | |
| 5044 mull(rcx); // x_lo * y_hi | |
| 5045 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx, | |
| 5046 // 3rd step | |
| 5047 bind(quick); // note: rbx, = 0 if quick multiply! | |
| 5048 movl(rax, x_lo); | |
| 5049 mull(y_lo); // x_lo * y_lo | |
| 5050 addl(rdx, rbx); // correct hi(x_lo * y_lo) | |
| 5051 } | |
| 5052 | |
| 304 | 5053 void MacroAssembler::lneg(Register hi, Register lo) { |
| 5054 negl(lo); | |
| 5055 adcl(hi, 0); | |
| 5056 negl(hi); | |
| 5057 } | |
| 0 | 5058 |
| 5059 void MacroAssembler::lshl(Register hi, Register lo) { | |
| 5060 // Java shift left long support (semantics as described in JVM spec., p.305) | |
| 5061 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n)) | |
| 5062 // shift value is in rcx ! | |
| 5063 assert(hi != rcx, "must not use rcx"); | |
| 5064 assert(lo != rcx, "must not use rcx"); | |
| 5065 const Register s = rcx; // shift count | |
| 5066 const int n = BitsPerWord; | |
| 5067 Label L; | |
| 5068 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) | |
| 5069 cmpl(s, n); // if (s < n) | |
| 5070 jcc(Assembler::less, L); // else (s >= n) | |
| 5071 movl(hi, lo); // x := x << n | |
| 5072 xorl(lo, lo); | |
| 5073 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! | |
| 5074 bind(L); // s (mod n) < n | |
| 5075 shldl(hi, lo); // x := x << s | |
| 5076 shll(lo); | |
| 5077 } | |
| 5078 | |
| 5079 | |
| 5080 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) { | |
| 5081 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310) | |
| 5082 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n)) | |
| 5083 assert(hi != rcx, "must not use rcx"); | |
| 5084 assert(lo != rcx, "must not use rcx"); | |
| 5085 const Register s = rcx; // shift count | |
| 5086 const int n = BitsPerWord; | |
| 5087 Label L; | |
| 5088 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) | |
| 5089 cmpl(s, n); // if (s < n) | |
| 5090 jcc(Assembler::less, L); // else (s >= n) | |
| 5091 movl(lo, hi); // x := x >> n | |
| 5092 if (sign_extension) sarl(hi, 31); | |
| 5093 else xorl(hi, hi); | |
| 5094 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! | |
| 5095 bind(L); // s (mod n) < n | |
| 5096 shrdl(lo, hi); // x := x >> s | |
| 5097 if (sign_extension) sarl(hi); | |
| 5098 else shrl(hi); | |
| 5099 } | |
| 5100 | |
| 304 | 5101 void MacroAssembler::movoop(Register dst, jobject obj) { |
| 5102 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); | |
| 5103 } | |
| 5104 | |
| 5105 void MacroAssembler::movoop(Address dst, jobject obj) { | |
| 5106 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); | |
| 5107 } | |
| 5108 | |
| 5109 void MacroAssembler::movptr(Register dst, AddressLiteral src) { | |
| 5110 if (src.is_lval()) { | |
| 5111 mov_literal32(dst, (intptr_t)src.target(), src.rspec()); | |
| 5112 } else { | |
| 5113 movl(dst, as_Address(src)); | |
| 5114 } | |
| 5115 } | |
| 5116 | |
| 5117 void MacroAssembler::movptr(ArrayAddress dst, Register src) { | |
| 5118 movl(as_Address(dst), src); | |
| 5119 } | |
| 5120 | |
| 5121 void MacroAssembler::movptr(Register dst, ArrayAddress src) { | |
| 5122 movl(dst, as_Address(src)); | |
| 5123 } | |
| 5124 | |
| 5125 // src should NEVER be a real pointer. Use AddressLiteral for true pointers | |
| 5126 void MacroAssembler::movptr(Address dst, intptr_t src) { | |
| 5127 movl(dst, src); | |
| 5128 } | |
| 5129 | |
| 5130 | |
| 5131 void MacroAssembler::pop_callee_saved_registers() { | |
| 5132 pop(rcx); | |
| 5133 pop(rdx); | |
| 5134 pop(rdi); | |
| 5135 pop(rsi); | |
| 5136 } | |
| 5137 | |
| 5138 void MacroAssembler::pop_fTOS() { | |
| 5139 fld_d(Address(rsp, 0)); | |
| 5140 addl(rsp, 2 * wordSize); | |
| 5141 } | |
| 5142 | |
| 5143 void MacroAssembler::push_callee_saved_registers() { | |
| 5144 push(rsi); | |
| 5145 push(rdi); | |
| 5146 push(rdx); | |
| 5147 push(rcx); | |
| 5148 } | |
| 5149 | |
| 5150 void MacroAssembler::push_fTOS() { | |
| 5151 subl(rsp, 2 * wordSize); | |
| 5152 fstp_d(Address(rsp, 0)); | |
| 5153 } | |
| 5154 | |
| 5155 | |
| 5156 void MacroAssembler::pushoop(jobject obj) { | |
| 5157 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate()); | |
| 5158 } | |
| 5159 | |
| 5160 | |
| 5161 void MacroAssembler::pushptr(AddressLiteral src) { | |
| 5162 if (src.is_lval()) { | |
| 5163 push_literal32((int32_t)src.target(), src.rspec()); | |
| 5164 } else { | |
| 5165 pushl(as_Address(src)); | |
| 5166 } | |
| 5167 } | |
| 5168 | |
| 5169 void MacroAssembler::set_word_if_not_zero(Register dst) { | |
| 5170 xorl(dst, dst); | |
| 5171 set_byte_if_not_zero(dst); | |
| 5172 } | |
| 5173 | |
| 5174 static void pass_arg0(MacroAssembler* masm, Register arg) { | |
| 5175 masm->push(arg); | |
| 5176 } | |
| 5177 | |
| 5178 static void pass_arg1(MacroAssembler* masm, Register arg) { | |
| 5179 masm->push(arg); | |
| 5180 } | |
| 5181 | |
| 5182 static void pass_arg2(MacroAssembler* masm, Register arg) { | |
| 5183 masm->push(arg); | |
| 5184 } | |
| 5185 | |
| 5186 static void pass_arg3(MacroAssembler* masm, Register arg) { | |
| 5187 masm->push(arg); | |
| 5188 } | |
| 5189 | |
| 5190 #ifndef PRODUCT | |
| 5191 extern "C" void findpc(intptr_t x); | |
| 5192 #endif | |
| 5193 | |
| 5194 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) { | |
| 5195 // In order to get locks to work, we need to fake a in_VM state | |
| 5196 JavaThread* thread = JavaThread::current(); | |
| 5197 JavaThreadState saved_state = thread->thread_state(); | |
| 5198 thread->set_thread_state(_thread_in_vm); | |
| 5199 if (ShowMessageBoxOnError) { | |
| 5200 JavaThread* thread = JavaThread::current(); | |
| 5201 JavaThreadState saved_state = thread->thread_state(); | |
| 5202 thread->set_thread_state(_thread_in_vm); | |
| 5203 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { | |
| 5204 ttyLocker ttyl; | |
| 5205 BytecodeCounter::print(); | |
| 5206 } | |
| 5207 // To see where a verify_oop failed, get $ebx+40/X for this frame. | |
| 5208 // This is the value of eip which points to where verify_oop will return. | |
| 5209 if (os::message_box(msg, "Execution stopped, print registers?")) { | |
| 5210 ttyLocker ttyl; | |
| 5211 tty->print_cr("eip = 0x%08x", eip); | |
| 5212 #ifndef PRODUCT | |
|
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|
5213 if ((WizardMode || Verbose) && PrintMiscellaneous) { |
|
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|
5214 tty->cr(); |
|
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|
5215 findpc(eip); |
|
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|
5216 tty->cr(); |
|
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|
5217 } |
| 304 | 5218 #endif |
|
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|
5219 tty->print_cr("rax = 0x%08x", rax); |
|
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|
5220 tty->print_cr("rbx = 0x%08x", rbx); |
| 304 | 5221 tty->print_cr("rcx = 0x%08x", rcx); |
| 5222 tty->print_cr("rdx = 0x%08x", rdx); | |
| 5223 tty->print_cr("rdi = 0x%08x", rdi); | |
| 5224 tty->print_cr("rsi = 0x%08x", rsi); | |
|
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|
5225 tty->print_cr("rbp = 0x%08x", rbp); |
| 304 | 5226 tty->print_cr("rsp = 0x%08x", rsp); |
| 5227 BREAKPOINT; | |
|
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|
5228 assert(false, "start up GDB"); |
| 304 | 5229 } |
| 5230 } else { | |
| 5231 ttyLocker ttyl; | |
| 5232 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg); | |
|
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|
5233 assert(false, err_msg("DEBUG MESSAGE: %s", msg)); |
| 304 | 5234 } |
| 5235 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); | |
| 5236 } | |
| 5237 | |
| 5238 void MacroAssembler::stop(const char* msg) { | |
| 5239 ExternalAddress message((address)msg); | |
| 5240 // push address of message | |
| 5241 pushptr(message.addr()); | |
| 5242 { Label L; call(L, relocInfo::none); bind(L); } // push eip | |
| 5243 pusha(); // push registers | |
| 5244 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32))); | |
| 5245 hlt(); | |
| 5246 } | |
| 5247 | |
| 5248 void MacroAssembler::warn(const char* msg) { | |
| 5249 push_CPU_state(); | |
| 5250 | |
| 5251 ExternalAddress message((address) msg); | |
| 5252 // push address of message | |
| 5253 pushptr(message.addr()); | |
| 5254 | |
| 5255 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning))); | |
| 5256 addl(rsp, wordSize); // discard argument | |
| 5257 pop_CPU_state(); | |
| 5258 } | |
| 5259 | |
| 5260 #else // _LP64 | |
| 5261 | |
| 5262 // 64 bit versions | |
| 5263 | |
| 5264 Address MacroAssembler::as_Address(AddressLiteral adr) { | |
| 5265 // amd64 always does this as a pc-rel | |
| 5266 // we can be absolute or disp based on the instruction type | |
| 5267 // jmp/call are displacements others are absolute | |
| 5268 assert(!adr.is_lval(), "must be rval"); | |
| 5269 assert(reachable(adr), "must be"); | |
| 5270 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc()); | |
| 5271 | |
| 5272 } | |
| 5273 | |
| 5274 Address MacroAssembler::as_Address(ArrayAddress adr) { | |
| 5275 AddressLiteral base = adr.base(); | |
| 5276 lea(rscratch1, base); | |
| 5277 Address index = adr.index(); | |
| 5278 assert(index._disp == 0, "must not have disp"); // maybe it can? | |
| 5279 Address array(rscratch1, index._index, index._scale, index._disp); | |
| 5280 return array; | |
| 5281 } | |
| 5282 | |
| 5283 int MacroAssembler::biased_locking_enter(Register lock_reg, | |
| 5284 Register obj_reg, | |
| 5285 Register swap_reg, | |
| 5286 Register tmp_reg, | |
| 5287 bool swap_reg_contains_mark, | |
| 5288 Label& done, | |
| 5289 Label* slow_case, | |
| 5290 BiasedLockingCounters* counters) { | |
| 5291 assert(UseBiasedLocking, "why call this otherwise?"); | |
| 5292 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq"); | |
| 5293 assert(tmp_reg != noreg, "tmp_reg must be supplied"); | |
| 5294 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg); | |
| 5295 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); | |
| 5296 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes()); | |
| 5297 Address saved_mark_addr(lock_reg, 0); | |
| 5298 | |
| 5299 if (PrintBiasedLockingStatistics && counters == NULL) | |
| 5300 counters = BiasedLocking::counters(); | |
| 5301 | |
| 5302 // Biased locking | |
| 5303 // See whether the lock is currently biased toward our thread and | |
| 5304 // whether the epoch is still valid | |
| 5305 // Note that the runtime guarantees sufficient alignment of JavaThread | |
| 5306 // pointers to allow age to be placed into low bits | |
| 5307 // First check to see whether biasing is even enabled for this object | |
| 5308 Label cas_label; | |
| 5309 int null_check_offset = -1; | |
| 5310 if (!swap_reg_contains_mark) { | |
| 5311 null_check_offset = offset(); | |
| 5312 movq(swap_reg, mark_addr); | |
| 5313 } | |
| 5314 movq(tmp_reg, swap_reg); | |
| 5315 andq(tmp_reg, markOopDesc::biased_lock_mask_in_place); | |
| 5316 cmpq(tmp_reg, markOopDesc::biased_lock_pattern); | |
| 5317 jcc(Assembler::notEqual, cas_label); | |
| 5318 // The bias pattern is present in the object's header. Need to check | |
| 5319 // whether the bias owner and the epoch are both still current. | |
| 5320 load_prototype_header(tmp_reg, obj_reg); | |
| 5321 orq(tmp_reg, r15_thread); | |
| 5322 xorq(tmp_reg, swap_reg); | |
| 5323 andq(tmp_reg, ~((int) markOopDesc::age_mask_in_place)); | |
| 5324 if (counters != NULL) { | |
| 5325 cond_inc32(Assembler::zero, | |
| 5326 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr())); | |
| 5327 } | |
| 0 | 5328 jcc(Assembler::equal, done); |
| 5329 | |
| 304 | 5330 Label try_revoke_bias; |
| 5331 Label try_rebias; | |
| 5332 | |
| 5333 // At this point we know that the header has the bias pattern and | |
| 5334 // that we are not the bias owner in the current epoch. We need to | |
| 5335 // figure out more details about the state of the header in order to | |
| 5336 // know what operations can be legally performed on the object's | |
| 5337 // header. | |
| 5338 | |
| 5339 // If the low three bits in the xor result aren't clear, that means | |
| 5340 // the prototype header is no longer biased and we have to revoke | |
| 5341 // the bias on this object. | |
| 5342 testq(tmp_reg, markOopDesc::biased_lock_mask_in_place); | |
| 5343 jcc(Assembler::notZero, try_revoke_bias); | |
| 5344 | |
| 5345 // Biasing is still enabled for this data type. See whether the | |
| 5346 // epoch of the current bias is still valid, meaning that the epoch | |
| 5347 // bits of the mark word are equal to the epoch bits of the | |
| 5348 // prototype header. (Note that the prototype header's epoch bits | |
| 5349 // only change at a safepoint.) If not, attempt to rebias the object | |
| 5350 // toward the current thread. Note that we must be absolutely sure | |
| 5351 // that the current epoch is invalid in order to do this because | |
| 5352 // otherwise the manipulations it performs on the mark word are | |
| 5353 // illegal. | |
| 5354 testq(tmp_reg, markOopDesc::epoch_mask_in_place); | |
| 5355 jcc(Assembler::notZero, try_rebias); | |
| 5356 | |
| 5357 // The epoch of the current bias is still valid but we know nothing | |
| 5358 // about the owner; it might be set or it might be clear. Try to | |
| 5359 // acquire the bias of the object using an atomic operation. If this | |
| 5360 // fails we will go in to the runtime to revoke the object's bias. | |
| 5361 // Note that we first construct the presumed unbiased header so we | |
| 5362 // don't accidentally blow away another thread's valid bias. | |
| 5363 andq(swap_reg, | |
| 5364 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place); | |
| 5365 movq(tmp_reg, swap_reg); | |
| 5366 orq(tmp_reg, r15_thread); | |
| 5367 if (os::is_MP()) { | |
| 5368 lock(); | |
| 5369 } | |
| 5370 cmpxchgq(tmp_reg, Address(obj_reg, 0)); | |
| 5371 // If the biasing toward our thread failed, this means that | |
| 5372 // another thread succeeded in biasing it toward itself and we | |
| 5373 // need to revoke that bias. The revocation will occur in the | |
| 5374 // interpreter runtime in the slow case. | |
| 5375 if (counters != NULL) { | |
| 5376 cond_inc32(Assembler::zero, | |
| 5377 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr())); | |
| 5378 } | |
| 5379 if (slow_case != NULL) { | |
| 5380 jcc(Assembler::notZero, *slow_case); | |
| 5381 } | |
| 0 | 5382 jmp(done); |
| 5383 | |
| 304 | 5384 bind(try_rebias); |
| 5385 // At this point we know the epoch has expired, meaning that the | |
| 5386 // current "bias owner", if any, is actually invalid. Under these | |
| 5387 // circumstances _only_, we are allowed to use the current header's | |
| 5388 // value as the comparison value when doing the cas to acquire the | |
| 5389 // bias in the current epoch. In other words, we allow transfer of | |
| 5390 // the bias from one thread to another directly in this situation. | |
| 5391 // | |
| 5392 // FIXME: due to a lack of registers we currently blow away the age | |
| 5393 // bits in this situation. Should attempt to preserve them. | |
| 5394 load_prototype_header(tmp_reg, obj_reg); | |
| 5395 orq(tmp_reg, r15_thread); | |
| 5396 if (os::is_MP()) { | |
| 5397 lock(); | |
| 5398 } | |
| 5399 cmpxchgq(tmp_reg, Address(obj_reg, 0)); | |
| 5400 // If the biasing toward our thread failed, then another thread | |
| 5401 // succeeded in biasing it toward itself and we need to revoke that | |
| 5402 // bias. The revocation will occur in the runtime in the slow case. | |
| 5403 if (counters != NULL) { | |
| 5404 cond_inc32(Assembler::zero, | |
| 5405 ExternalAddress((address) counters->rebiased_lock_entry_count_addr())); | |
| 5406 } | |
| 5407 if (slow_case != NULL) { | |
| 5408 jcc(Assembler::notZero, *slow_case); | |
| 0 | 5409 } |
| 5410 jmp(done); | |
| 5411 | |
| 304 | 5412 bind(try_revoke_bias); |
| 5413 // The prototype mark in the klass doesn't have the bias bit set any | |
| 5414 // more, indicating that objects of this data type are not supposed | |
| 5415 // to be biased any more. We are going to try to reset the mark of | |
| 5416 // this object to the prototype value and fall through to the | |
| 5417 // CAS-based locking scheme. Note that if our CAS fails, it means | |
| 5418 // that another thread raced us for the privilege of revoking the | |
| 5419 // bias of this particular object, so it's okay to continue in the | |
| 5420 // normal locking code. | |
| 5421 // | |
| 5422 // FIXME: due to a lack of registers we currently blow away the age | |
| 5423 // bits in this situation. Should attempt to preserve them. | |
| 5424 load_prototype_header(tmp_reg, obj_reg); | |
| 5425 if (os::is_MP()) { | |
| 5426 lock(); | |
| 5427 } | |
| 5428 cmpxchgq(tmp_reg, Address(obj_reg, 0)); | |
| 5429 // Fall through to the normal CAS-based lock, because no matter what | |
| 5430 // the result of the above CAS, some thread must have succeeded in | |
| 5431 // removing the bias bit from the object's header. | |
| 5432 if (counters != NULL) { | |
| 5433 cond_inc32(Assembler::zero, | |
| 5434 ExternalAddress((address) counters->revoked_lock_entry_count_addr())); | |
| 5435 } | |
| 5436 | |
| 5437 bind(cas_label); | |
| 5438 | |
| 5439 return null_check_offset; | |
| 5440 } | |
| 5441 | |
| 5442 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) { | |
| 5443 Label L, E; | |
| 5444 | |
| 5445 #ifdef _WIN64 | |
| 5446 // Windows always allocates space for it's register args | |
| 5447 assert(num_args <= 4, "only register arguments supported"); | |
| 5448 subq(rsp, frame::arg_reg_save_area_bytes); | |
| 5449 #endif | |
| 5450 | |
| 5451 // Align stack if necessary | |
| 5452 testl(rsp, 15); | |
| 5453 jcc(Assembler::zero, L); | |
| 5454 | |
| 5455 subq(rsp, 8); | |
| 5456 { | |
| 5457 call(RuntimeAddress(entry_point)); | |
| 5458 } | |
| 5459 addq(rsp, 8); | |
| 5460 jmp(E); | |
| 5461 | |
| 5462 bind(L); | |
| 5463 { | |
| 5464 call(RuntimeAddress(entry_point)); | |
| 5465 } | |
| 5466 | |
| 5467 bind(E); | |
| 5468 | |
| 5469 #ifdef _WIN64 | |
| 5470 // restore stack pointer | |
| 5471 addq(rsp, frame::arg_reg_save_area_bytes); | |
| 5472 #endif | |
| 5473 | |
| 5474 } | |
| 5475 | |
| 5476 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) { | |
| 5477 assert(!src2.is_lval(), "should use cmpptr"); | |
| 5478 | |
| 5479 if (reachable(src2)) { | |
| 5480 cmpq(src1, as_Address(src2)); | |
| 5481 } else { | |
| 5482 lea(rscratch1, src2); | |
| 5483 Assembler::cmpq(src1, Address(rscratch1, 0)); | |
| 5484 } | |
| 5485 } | |
| 5486 | |
| 5487 int MacroAssembler::corrected_idivq(Register reg) { | |
| 5488 // Full implementation of Java ldiv and lrem; checks for special | |
| 5489 // case as described in JVM spec., p.243 & p.271. The function | |
| 5490 // returns the (pc) offset of the idivl instruction - may be needed | |
| 5491 // for implicit exceptions. | |
| 5492 // | |
| 5493 // normal case special case | |
| 5494 // | |
| 5495 // input : rax: dividend min_long | |
| 5496 // reg: divisor (may not be eax/edx) -1 | |
| 5497 // | |
| 5498 // output: rax: quotient (= rax idiv reg) min_long | |
| 5499 // rdx: remainder (= rax irem reg) 0 | |
| 5500 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register"); | |
| 5501 static const int64_t min_long = 0x8000000000000000; | |
| 5502 Label normal_case, special_case; | |
| 5503 | |
| 5504 // check for special case | |
| 5505 cmp64(rax, ExternalAddress((address) &min_long)); | |
| 5506 jcc(Assembler::notEqual, normal_case); | |
| 5507 xorl(rdx, rdx); // prepare rdx for possible special case (where | |
| 5508 // remainder = 0) | |
| 5509 cmpq(reg, -1); | |
| 5510 jcc(Assembler::equal, special_case); | |
| 5511 | |
| 5512 // handle normal case | |
| 5513 bind(normal_case); | |
| 5514 cdqq(); | |
| 5515 int idivq_offset = offset(); | |
| 5516 idivq(reg); | |
| 5517 | |
| 5518 // normal and special case exit | |
| 5519 bind(special_case); | |
| 5520 | |
| 5521 return idivq_offset; | |
| 5522 } | |
| 5523 | |
| 5524 void MacroAssembler::decrementq(Register reg, int value) { | |
| 5525 if (value == min_jint) { subq(reg, value); return; } | |
| 5526 if (value < 0) { incrementq(reg, -value); return; } | |
| 5527 if (value == 0) { ; return; } | |
| 5528 if (value == 1 && UseIncDec) { decq(reg) ; return; } | |
| 5529 /* else */ { subq(reg, value) ; return; } | |
| 5530 } | |
| 5531 | |
| 5532 void MacroAssembler::decrementq(Address dst, int value) { | |
| 5533 if (value == min_jint) { subq(dst, value); return; } | |
| 5534 if (value < 0) { incrementq(dst, -value); return; } | |
| 5535 if (value == 0) { ; return; } | |
| 5536 if (value == 1 && UseIncDec) { decq(dst) ; return; } | |
| 5537 /* else */ { subq(dst, value) ; return; } | |
| 5538 } | |
| 5539 | |
| 5540 void MacroAssembler::fat_nop() { | |
| 5541 // A 5 byte nop that is safe for patching (see patch_verified_entry) | |
| 5542 // Recommened sequence from 'Software Optimization Guide for the AMD | |
| 5543 // Hammer Processor' | |
| 5544 emit_byte(0x66); | |
| 5545 emit_byte(0x66); | |
| 5546 emit_byte(0x90); | |
| 5547 emit_byte(0x66); | |
| 5548 emit_byte(0x90); | |
| 5549 } | |
| 5550 | |
| 5551 void MacroAssembler::incrementq(Register reg, int value) { | |
| 5552 if (value == min_jint) { addq(reg, value); return; } | |
| 5553 if (value < 0) { decrementq(reg, -value); return; } | |
| 5554 if (value == 0) { ; return; } | |
| 5555 if (value == 1 && UseIncDec) { incq(reg) ; return; } | |
| 5556 /* else */ { addq(reg, value) ; return; } | |
| 5557 } | |
| 5558 | |
| 5559 void MacroAssembler::incrementq(Address dst, int value) { | |
| 5560 if (value == min_jint) { addq(dst, value); return; } | |
| 5561 if (value < 0) { decrementq(dst, -value); return; } | |
| 5562 if (value == 0) { ; return; } | |
| 5563 if (value == 1 && UseIncDec) { incq(dst) ; return; } | |
| 5564 /* else */ { addq(dst, value) ; return; } | |
| 5565 } | |
| 5566 | |
| 5567 // 32bit can do a case table jump in one instruction but we no longer allow the base | |
| 5568 // to be installed in the Address class | |
| 5569 void MacroAssembler::jump(ArrayAddress entry) { | |
| 5570 lea(rscratch1, entry.base()); | |
| 5571 Address dispatch = entry.index(); | |
| 5572 assert(dispatch._base == noreg, "must be"); | |
| 5573 dispatch._base = rscratch1; | |
| 5574 jmp(dispatch); | |
| 5575 } | |
| 5576 | |
| 5577 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { | |
| 5578 ShouldNotReachHere(); // 64bit doesn't use two regs | |
| 5579 cmpq(x_lo, y_lo); | |
| 5580 } | |
| 5581 | |
| 5582 void MacroAssembler::lea(Register dst, AddressLiteral src) { | |
| 5583 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); | |
| 5584 } | |
| 5585 | |
| 5586 void MacroAssembler::lea(Address dst, AddressLiteral adr) { | |
| 5587 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec()); | |
| 5588 movptr(dst, rscratch1); | |
| 5589 } | |
| 5590 | |
| 5591 void MacroAssembler::leave() { | |
| 5592 // %%% is this really better? Why not on 32bit too? | |
| 5593 emit_byte(0xC9); // LEAVE | |
| 5594 } | |
| 5595 | |
| 5596 void MacroAssembler::lneg(Register hi, Register lo) { | |
| 5597 ShouldNotReachHere(); // 64bit doesn't use two regs | |
| 5598 negq(lo); | |
| 5599 } | |
| 5600 | |
| 5601 void MacroAssembler::movoop(Register dst, jobject obj) { | |
| 5602 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate()); | |
| 5603 } | |
| 5604 | |
| 5605 void MacroAssembler::movoop(Address dst, jobject obj) { | |
| 5606 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate()); | |
| 5607 movq(dst, rscratch1); | |
| 5608 } | |
| 5609 | |
| 5610 void MacroAssembler::movptr(Register dst, AddressLiteral src) { | |
| 5611 if (src.is_lval()) { | |
| 5612 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); | |
| 5613 } else { | |
| 5614 if (reachable(src)) { | |
| 5615 movq(dst, as_Address(src)); | |
| 5616 } else { | |
| 5617 lea(rscratch1, src); | |
| 5618 movq(dst, Address(rscratch1,0)); | |
| 0 | 5619 } |
| 304 | 5620 } |
| 5621 } | |
| 5622 | |
| 5623 void MacroAssembler::movptr(ArrayAddress dst, Register src) { | |
| 5624 movq(as_Address(dst), src); | |
| 5625 } | |
| 5626 | |
| 5627 void MacroAssembler::movptr(Register dst, ArrayAddress src) { | |
| 5628 movq(dst, as_Address(src)); | |
| 5629 } | |
| 5630 | |
| 5631 // src should NEVER be a real pointer. Use AddressLiteral for true pointers | |
| 5632 void MacroAssembler::movptr(Address dst, intptr_t src) { | |
| 5633 mov64(rscratch1, src); | |
| 5634 movq(dst, rscratch1); | |
| 5635 } | |
| 5636 | |
| 5637 // These are mostly for initializing NULL | |
| 5638 void MacroAssembler::movptr(Address dst, int32_t src) { | |
| 5639 movslq(dst, src); | |
| 5640 } | |
| 5641 | |
| 5642 void MacroAssembler::movptr(Register dst, int32_t src) { | |
| 5643 mov64(dst, (intptr_t)src); | |
| 5644 } | |
| 5645 | |
| 5646 void MacroAssembler::pushoop(jobject obj) { | |
| 5647 movoop(rscratch1, obj); | |
| 5648 push(rscratch1); | |
| 5649 } | |
| 5650 | |
| 5651 void MacroAssembler::pushptr(AddressLiteral src) { | |
| 5652 lea(rscratch1, src); | |
| 5653 if (src.is_lval()) { | |
| 5654 push(rscratch1); | |
| 5655 } else { | |
| 5656 pushq(Address(rscratch1, 0)); | |
| 5657 } | |
| 5658 } | |
| 5659 | |
| 5660 void MacroAssembler::reset_last_Java_frame(bool clear_fp, | |
| 5661 bool clear_pc) { | |
| 5662 // we must set sp to zero to clear frame | |
|
512
db4caa99ef11
6787106: Hotspot 32 bit build fails on platforms having different definitions for intptr_t & int32_t
xlu
parents:
420
diff
changeset
|
5663 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); |
| 304 | 5664 // must clear fp, so that compiled frames are not confused; it is |
| 5665 // possible that we need it only for debugging | |
| 5666 if (clear_fp) { | |
|
512
db4caa99ef11
6787106: Hotspot 32 bit build fails on platforms having different definitions for intptr_t & int32_t
xlu
parents:
420
diff
changeset
|
5667 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); |
| 304 | 5668 } |
| 5669 | |
| 5670 if (clear_pc) { | |
|
512
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6787106: Hotspot 32 bit build fails on platforms having different definitions for intptr_t & int32_t
xlu
parents:
420
diff
changeset
|
5671 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); |
| 304 | 5672 } |
| 5673 } | |
| 5674 | |
| 5675 void MacroAssembler::set_last_Java_frame(Register last_java_sp, | |
| 5676 Register last_java_fp, | |
| 5677 address last_java_pc) { | |
| 5678 // determine last_java_sp register | |
| 5679 if (!last_java_sp->is_valid()) { | |
| 5680 last_java_sp = rsp; | |
| 5681 } | |
| 5682 | |
| 5683 // last_java_fp is optional | |
| 5684 if (last_java_fp->is_valid()) { | |
| 5685 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), | |
| 5686 last_java_fp); | |
| 5687 } | |
| 5688 | |
| 5689 // last_java_pc is optional | |
| 5690 if (last_java_pc != NULL) { | |
| 5691 Address java_pc(r15_thread, | |
| 5692 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()); | |
| 5693 lea(rscratch1, InternalAddress(last_java_pc)); | |
| 5694 movptr(java_pc, rscratch1); | |
| 5695 } | |
| 5696 | |
| 5697 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp); | |
| 5698 } | |
| 5699 | |
| 5700 static void pass_arg0(MacroAssembler* masm, Register arg) { | |
| 5701 if (c_rarg0 != arg ) { | |
| 5702 masm->mov(c_rarg0, arg); | |
| 5703 } | |
| 5704 } | |
| 5705 | |
| 5706 static void pass_arg1(MacroAssembler* masm, Register arg) { | |
| 5707 if (c_rarg1 != arg ) { | |
| 5708 masm->mov(c_rarg1, arg); | |
| 5709 } | |
| 5710 } | |
| 5711 | |
| 5712 static void pass_arg2(MacroAssembler* masm, Register arg) { | |
| 5713 if (c_rarg2 != arg ) { | |
| 5714 masm->mov(c_rarg2, arg); | |
| 5715 } | |
| 5716 } | |
| 5717 | |
| 5718 static void pass_arg3(MacroAssembler* masm, Register arg) { | |
| 5719 if (c_rarg3 != arg ) { | |
| 5720 masm->mov(c_rarg3, arg); | |
| 5721 } | |
| 5722 } | |
| 5723 | |
| 5724 void MacroAssembler::stop(const char* msg) { | |
| 5725 address rip = pc(); | |
| 5726 pusha(); // get regs on stack | |
| 5727 lea(c_rarg0, ExternalAddress((address) msg)); | |
| 5728 lea(c_rarg1, InternalAddress(rip)); | |
| 5729 movq(c_rarg2, rsp); // pass pointer to regs array | |
| 5730 andq(rsp, -16); // align stack as required by ABI | |
| 5731 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64))); | |
| 5732 hlt(); | |
| 5733 } | |
| 5734 | |
| 5735 void MacroAssembler::warn(const char* msg) { | |
|
1976
0fc262af204f
6780143: hs203t003 hits SIGSEGV/EXCEPTION_ACCESS_VIOLATION with -XX:+UseCompressedOops
coleenp
parents:
1972
diff
changeset
|
5736 push(rsp); |
| 304 | 5737 andq(rsp, -16); // align stack as required by push_CPU_state and call |
| 5738 | |
| 5739 push_CPU_state(); // keeps alignment at 16 bytes | |
| 5740 lea(c_rarg0, ExternalAddress((address) msg)); | |
| 5741 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0); | |
| 5742 pop_CPU_state(); | |
|
1976
0fc262af204f
6780143: hs203t003 hits SIGSEGV/EXCEPTION_ACCESS_VIOLATION with -XX:+UseCompressedOops
coleenp
parents:
1972
diff
changeset
|
5743 pop(rsp); |
| 304 | 5744 } |
| 5745 | |
| 5746 #ifndef PRODUCT | |
| 5747 extern "C" void findpc(intptr_t x); | |
| 5748 #endif | |
| 5749 | |
| 5750 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) { | |
| 5751 // In order to get locks to work, we need to fake a in_VM state | |
| 5752 if (ShowMessageBoxOnError ) { | |
| 5753 JavaThread* thread = JavaThread::current(); | |
| 5754 JavaThreadState saved_state = thread->thread_state(); | |
| 5755 thread->set_thread_state(_thread_in_vm); | |
| 5756 #ifndef PRODUCT | |
| 5757 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { | |
| 5758 ttyLocker ttyl; | |
| 5759 BytecodeCounter::print(); | |
| 0 | 5760 } |
| 304 | 5761 #endif |
| 5762 // To see where a verify_oop failed, get $ebx+40/X for this frame. | |
| 5763 // XXX correct this offset for amd64 | |
| 5764 // This is the value of eip which points to where verify_oop will return. | |
| 5765 if (os::message_box(msg, "Execution stopped, print registers?")) { | |
| 5766 ttyLocker ttyl; | |
| 5767 tty->print_cr("rip = 0x%016lx", pc); | |
| 5768 #ifndef PRODUCT | |
| 5769 tty->cr(); | |
| 5770 findpc(pc); | |
| 5771 tty->cr(); | |
| 5772 #endif | |
| 5773 tty->print_cr("rax = 0x%016lx", regs[15]); | |
| 5774 tty->print_cr("rbx = 0x%016lx", regs[12]); | |
| 5775 tty->print_cr("rcx = 0x%016lx", regs[14]); | |
| 5776 tty->print_cr("rdx = 0x%016lx", regs[13]); | |
| 5777 tty->print_cr("rdi = 0x%016lx", regs[8]); | |
| 5778 tty->print_cr("rsi = 0x%016lx", regs[9]); | |
| 5779 tty->print_cr("rbp = 0x%016lx", regs[10]); | |
| 5780 tty->print_cr("rsp = 0x%016lx", regs[11]); | |
| 5781 tty->print_cr("r8 = 0x%016lx", regs[7]); | |
| 5782 tty->print_cr("r9 = 0x%016lx", regs[6]); | |
| 5783 tty->print_cr("r10 = 0x%016lx", regs[5]); | |
| 5784 tty->print_cr("r11 = 0x%016lx", regs[4]); | |
| 5785 tty->print_cr("r12 = 0x%016lx", regs[3]); | |
| 5786 tty->print_cr("r13 = 0x%016lx", regs[2]); | |
| 5787 tty->print_cr("r14 = 0x%016lx", regs[1]); | |
| 5788 tty->print_cr("r15 = 0x%016lx", regs[0]); | |
| 5789 BREAKPOINT; | |
| 0 | 5790 } |
| 304 | 5791 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); |
| 5792 } else { | |
| 5793 ttyLocker ttyl; | |
| 5794 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", | |
| 5795 msg); | |
|
3753
cba7b5c2d53f
7045514: SPARC assembly code for JSR 292 ricochet frames
never
parents:
3336
diff
changeset
|
5796 assert(false, err_msg("DEBUG MESSAGE: %s", msg)); |
| 304 | 5797 } |
| 5798 } | |
| 5799 | |
| 5800 #endif // _LP64 | |
| 5801 | |
| 5802 // Now versions that are common to 32/64 bit | |
| 5803 | |
| 5804 void MacroAssembler::addptr(Register dst, int32_t imm32) { | |
| 5805 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32)); | |
| 5806 } | |
| 5807 | |
| 5808 void MacroAssembler::addptr(Register dst, Register src) { | |
| 5809 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); | |
| 5810 } | |
| 5811 | |
| 5812 void MacroAssembler::addptr(Address dst, Register src) { | |
| 5813 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); | |
| 5814 } | |
| 5815 | |
| 4759 | 5816 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) { |
| 5817 if (reachable(src)) { | |
| 5818 Assembler::addsd(dst, as_Address(src)); | |
| 5819 } else { | |
| 5820 lea(rscratch1, src); | |
| 5821 Assembler::addsd(dst, Address(rscratch1, 0)); | |
| 5822 } | |
| 5823 } | |
| 5824 | |
| 5825 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) { | |
| 5826 if (reachable(src)) { | |
| 5827 addss(dst, as_Address(src)); | |
| 5828 } else { | |
| 5829 lea(rscratch1, src); | |
| 5830 addss(dst, Address(rscratch1, 0)); | |
| 5831 } | |
| 5832 } | |
| 5833 | |
| 304 | 5834 void MacroAssembler::align(int modulus) { |
| 5835 if (offset() % modulus != 0) { | |
| 5836 nop(modulus - (offset() % modulus)); | |
| 5837 } | |
| 5838 } | |
| 5839 | |
| 5840 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) { | |
| 4759 | 5841 // Used in sign-masking with aligned address. |
| 5842 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); | |
| 1060 | 5843 if (reachable(src)) { |
| 4759 | 5844 Assembler::andpd(dst, as_Address(src)); |
| 1060 | 5845 } else { |
| 5846 lea(rscratch1, src); | |
| 4759 | 5847 Assembler::andpd(dst, Address(rscratch1, 0)); |
| 5848 } | |
| 5849 } | |
| 5850 | |
| 5851 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) { | |
| 5852 // Used in sign-masking with aligned address. | |
| 5853 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); | |
| 5854 if (reachable(src)) { | |
| 5855 Assembler::andps(dst, as_Address(src)); | |
| 5856 } else { | |
| 5857 lea(rscratch1, src); | |
| 5858 Assembler::andps(dst, Address(rscratch1, 0)); | |
| 1060 | 5859 } |
| 304 | 5860 } |
| 5861 | |
| 5862 void MacroAssembler::andptr(Register dst, int32_t imm32) { | |
| 5863 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32)); | |
| 5864 } | |
| 5865 | |
| 5866 void MacroAssembler::atomic_incl(AddressLiteral counter_addr) { | |
| 5867 pushf(); | |
| 5868 if (os::is_MP()) | |
| 5869 lock(); | |
| 5870 incrementl(counter_addr); | |
| 5871 popf(); | |
| 5872 } | |
| 5873 | |
| 5874 // Writes to stack successive pages until offset reached to check for | |
| 5875 // stack overflow + shadow pages. This clobbers tmp. | |
| 5876 void MacroAssembler::bang_stack_size(Register size, Register tmp) { | |
| 5877 movptr(tmp, rsp); | |
| 5878 // Bang stack for total size given plus shadow page size. | |
| 5879 // Bang one page at a time because large size can bang beyond yellow and | |
| 5880 // red zones. | |
| 5881 Label loop; | |
| 5882 bind(loop); | |
| 5883 movl(Address(tmp, (-os::vm_page_size())), size ); | |
| 5884 subptr(tmp, os::vm_page_size()); | |
| 5885 subl(size, os::vm_page_size()); | |
| 5886 jcc(Assembler::greater, loop); | |
| 5887 | |
| 5888 // Bang down shadow pages too. | |
| 5889 // The -1 because we already subtracted 1 page. | |
| 5890 for (int i = 0; i< StackShadowPages-1; i++) { | |
| 5891 // this could be any sized move but this is can be a debugging crumb | |
| 5892 // so the bigger the better. | |
| 5893 movptr(Address(tmp, (-i*os::vm_page_size())), size ); | |
| 5894 } | |
| 5895 } | |
| 5896 | |
| 5897 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) { | |
| 5898 assert(UseBiasedLocking, "why call this otherwise?"); | |
| 5899 | |
| 5900 // Check for biased locking unlock case, which is a no-op | |
| 5901 // Note: we do not have to check the thread ID for two reasons. | |
| 5902 // First, the interpreter checks for IllegalMonitorStateException at | |
| 5903 // a higher level. Second, if the bias was revoked while we held the | |
| 5904 // lock, the object could not be rebiased toward another thread, so | |
| 5905 // the bias bit would be clear. | |
| 5906 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes())); | |
| 5907 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place); | |
| 5908 cmpptr(temp_reg, markOopDesc::biased_lock_pattern); | |
| 5909 jcc(Assembler::equal, done); | |
| 5910 } | |
| 5911 | |
| 5912 void MacroAssembler::c2bool(Register x) { | |
| 5913 // implements x == 0 ? 0 : 1 | |
| 5914 // note: must only look at least-significant byte of x | |
| 5915 // since C-style booleans are stored in one byte | |
| 5916 // only! (was bug) | |
| 5917 andl(x, 0xFF); | |
| 5918 setb(Assembler::notZero, x); | |
| 5919 } | |
| 5920 | |
| 5921 // Wouldn't need if AddressLiteral version had new name | |
| 5922 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) { | |
| 5923 Assembler::call(L, rtype); | |
| 5924 } | |
| 5925 | |
| 5926 void MacroAssembler::call(Register entry) { | |
| 5927 Assembler::call(entry); | |
| 5928 } | |
| 5929 | |
| 5930 void MacroAssembler::call(AddressLiteral entry) { | |
| 5931 if (reachable(entry)) { | |
| 5932 Assembler::call_literal(entry.target(), entry.rspec()); | |
| 5933 } else { | |
| 5934 lea(rscratch1, entry); | |
| 5935 Assembler::call(rscratch1); | |
| 5936 } | |
| 5937 } | |
| 5938 | |
| 5939 // Implementation of call_VM versions | |
| 5940 | |
| 5941 void MacroAssembler::call_VM(Register oop_result, | |
| 5942 address entry_point, | |
| 5943 bool check_exceptions) { | |
| 5944 Label C, E; | |
| 5945 call(C, relocInfo::none); | |
| 5946 jmp(E); | |
| 5947 | |
| 5948 bind(C); | |
| 5949 call_VM_helper(oop_result, entry_point, 0, check_exceptions); | |
| 5950 ret(0); | |
| 5951 | |
| 5952 bind(E); | |
| 5953 } | |
| 5954 | |
| 5955 void MacroAssembler::call_VM(Register oop_result, | |
| 5956 address entry_point, | |
| 5957 Register arg_1, | |
| 5958 bool check_exceptions) { | |
| 5959 Label C, E; | |
| 5960 call(C, relocInfo::none); | |
| 5961 jmp(E); | |
| 5962 | |
| 5963 bind(C); | |
| 5964 pass_arg1(this, arg_1); | |
| 5965 call_VM_helper(oop_result, entry_point, 1, check_exceptions); | |
| 5966 ret(0); | |
| 5967 | |
| 5968 bind(E); | |
| 5969 } | |
| 5970 | |
| 5971 void MacroAssembler::call_VM(Register oop_result, | |
| 5972 address entry_point, | |
| 5973 Register arg_1, | |
| 5974 Register arg_2, | |
| 5975 bool check_exceptions) { | |
| 5976 Label C, E; | |
| 5977 call(C, relocInfo::none); | |
| 5978 jmp(E); | |
| 5979 | |
| 5980 bind(C); | |
| 5981 | |
| 5982 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
| 5983 | |
| 5984 pass_arg2(this, arg_2); | |
| 5985 pass_arg1(this, arg_1); | |
| 5986 call_VM_helper(oop_result, entry_point, 2, check_exceptions); | |
| 5987 ret(0); | |
| 5988 | |
| 5989 bind(E); | |
| 5990 } | |
| 5991 | |
| 5992 void MacroAssembler::call_VM(Register oop_result, | |
| 5993 address entry_point, | |
| 5994 Register arg_1, | |
| 5995 Register arg_2, | |
| 5996 Register arg_3, | |
| 5997 bool check_exceptions) { | |
| 5998 Label C, E; | |
| 5999 call(C, relocInfo::none); | |
| 6000 jmp(E); | |
| 6001 | |
| 6002 bind(C); | |
| 6003 | |
| 6004 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); | |
| 6005 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); | |
| 6006 pass_arg3(this, arg_3); | |
| 6007 | |
| 6008 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
| 6009 pass_arg2(this, arg_2); | |
| 6010 | |
| 6011 pass_arg1(this, arg_1); | |
| 6012 call_VM_helper(oop_result, entry_point, 3, check_exceptions); | |
| 6013 ret(0); | |
| 6014 | |
| 6015 bind(E); | |
| 6016 } | |
| 6017 | |
| 6018 void MacroAssembler::call_VM(Register oop_result, | |
| 6019 Register last_java_sp, | |
| 6020 address entry_point, | |
| 6021 int number_of_arguments, | |
| 6022 bool check_exceptions) { | |
| 6023 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); | |
| 6024 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); | |
| 6025 } | |
| 6026 | |
| 6027 void MacroAssembler::call_VM(Register oop_result, | |
| 6028 Register last_java_sp, | |
| 6029 address entry_point, | |
| 6030 Register arg_1, | |
| 6031 bool check_exceptions) { | |
| 6032 pass_arg1(this, arg_1); | |
| 6033 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); | |
| 6034 } | |
| 6035 | |
| 6036 void MacroAssembler::call_VM(Register oop_result, | |
| 6037 Register last_java_sp, | |
| 6038 address entry_point, | |
| 6039 Register arg_1, | |
| 6040 Register arg_2, | |
| 6041 bool check_exceptions) { | |
| 6042 | |
| 6043 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
| 6044 pass_arg2(this, arg_2); | |
| 6045 pass_arg1(this, arg_1); | |
| 6046 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); | |
| 6047 } | |
| 6048 | |
| 6049 void MacroAssembler::call_VM(Register oop_result, | |
| 6050 Register last_java_sp, | |
| 6051 address entry_point, | |
| 6052 Register arg_1, | |
| 6053 Register arg_2, | |
| 6054 Register arg_3, | |
| 6055 bool check_exceptions) { | |
| 6056 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); | |
| 6057 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); | |
| 6058 pass_arg3(this, arg_3); | |
| 6059 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
| 6060 pass_arg2(this, arg_2); | |
| 6061 pass_arg1(this, arg_1); | |
| 6062 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); | |
| 6063 } | |
| 6064 | |
|
3755
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6065 void MacroAssembler::super_call_VM(Register oop_result, |
|
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6066 Register last_java_sp, |
|
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6067 address entry_point, |
|
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|
6068 int number_of_arguments, |
|
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|
6069 bool check_exceptions) { |
|
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6070 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); |
|
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6071 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); |
|
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|
6072 } |
|
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|
6073 |
|
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6074 void MacroAssembler::super_call_VM(Register oop_result, |
|
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6075 Register last_java_sp, |
|
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|
6076 address entry_point, |
|
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|
6077 Register arg_1, |
|
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|
6078 bool check_exceptions) { |
|
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|
6079 pass_arg1(this, arg_1); |
|
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|
6080 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); |
|
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|
6081 } |
|
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|
6082 |
|
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|
6083 void MacroAssembler::super_call_VM(Register oop_result, |
|
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|
6084 Register last_java_sp, |
|
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|
6085 address entry_point, |
|
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|
6086 Register arg_1, |
|
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|
6087 Register arg_2, |
|
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|
6088 bool check_exceptions) { |
|
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|
6089 |
|
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|
6090 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); |
|
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|
6091 pass_arg2(this, arg_2); |
|
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|
6092 pass_arg1(this, arg_1); |
|
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|
6093 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); |
|
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|
6094 } |
|
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|
6095 |
|
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|
6096 void MacroAssembler::super_call_VM(Register oop_result, |
|
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|
6097 Register last_java_sp, |
|
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|
6098 address entry_point, |
|
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|
6099 Register arg_1, |
|
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|
6100 Register arg_2, |
|
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|
6101 Register arg_3, |
|
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|
6102 bool check_exceptions) { |
|
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|
6103 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); |
|
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|
6104 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); |
|
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|
6105 pass_arg3(this, arg_3); |
|
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|
6106 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); |
|
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|
6107 pass_arg2(this, arg_2); |
|
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|
6108 pass_arg1(this, arg_1); |
|
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|
6109 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); |
|
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|
6110 } |
|
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|
6111 |
| 304 | 6112 void MacroAssembler::call_VM_base(Register oop_result, |
| 6113 Register java_thread, | |
| 6114 Register last_java_sp, | |
| 6115 address entry_point, | |
| 6116 int number_of_arguments, | |
| 6117 bool check_exceptions) { | |
| 6118 // determine java_thread register | |
| 6119 if (!java_thread->is_valid()) { | |
| 6120 #ifdef _LP64 | |
| 6121 java_thread = r15_thread; | |
| 6122 #else | |
| 6123 java_thread = rdi; | |
| 6124 get_thread(java_thread); | |
| 6125 #endif // LP64 | |
| 6126 } | |
| 6127 // determine last_java_sp register | |
| 6128 if (!last_java_sp->is_valid()) { | |
| 6129 last_java_sp = rsp; | |
| 6130 } | |
| 6131 // debugging support | |
| 6132 assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); | |
| 6133 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register")); | |
|
1976
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|
6134 #ifdef ASSERT |
|
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|
6135 LP64_ONLY(if (UseCompressedOops) verify_heapbase("call_VM_base");) |
|
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|
6136 #endif // ASSERT |
|
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|
6137 |
| 304 | 6138 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result"); |
| 6139 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp"); | |
| 6140 | |
| 6141 // push java thread (becomes first argument of C function) | |
| 6142 | |
| 6143 NOT_LP64(push(java_thread); number_of_arguments++); | |
| 6144 LP64_ONLY(mov(c_rarg0, r15_thread)); | |
| 6145 | |
| 6146 // set last Java frame before call | |
| 6147 assert(last_java_sp != rbp, "can't use ebp/rbp"); | |
| 6148 | |
| 6149 // Only interpreter should have to set fp | |
| 6150 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL); | |
| 6151 | |
| 6152 // do the call, remove parameters | |
| 6153 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments); | |
| 6154 | |
| 6155 // restore the thread (cannot use the pushed argument since arguments | |
| 6156 // may be overwritten by C code generated by an optimizing compiler); | |
| 6157 // however can use the register value directly if it is callee saved. | |
| 6158 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) { | |
| 6159 // rdi & rsi (also r15) are callee saved -> nothing to do | |
| 6160 #ifdef ASSERT | |
| 6161 guarantee(java_thread != rax, "change this code"); | |
| 6162 push(rax); | |
| 6163 { Label L; | |
| 6164 get_thread(rax); | |
| 6165 cmpptr(java_thread, rax); | |
| 6166 jcc(Assembler::equal, L); | |
| 6167 stop("MacroAssembler::call_VM_base: rdi not callee saved?"); | |
| 6168 bind(L); | |
| 0 | 6169 } |
| 304 | 6170 pop(rax); |
| 6171 #endif | |
| 6172 } else { | |
| 6173 get_thread(java_thread); | |
| 6174 } | |
| 6175 // reset last Java frame | |
| 6176 // Only interpreter should have to clear fp | |
| 6177 reset_last_Java_frame(java_thread, true, false); | |
| 6178 | |
| 6179 #ifndef CC_INTERP | |
| 6180 // C++ interp handles this in the interpreter | |
| 6181 check_and_handle_popframe(java_thread); | |
| 6182 check_and_handle_earlyret(java_thread); | |
| 6183 #endif /* CC_INTERP */ | |
| 6184 | |
| 6185 if (check_exceptions) { | |
| 6186 // check for pending exceptions (java_thread is set upon return) | |
| 6187 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD); | |
| 6188 #ifndef _LP64 | |
| 6189 jump_cc(Assembler::notEqual, | |
| 6190 RuntimeAddress(StubRoutines::forward_exception_entry())); | |
| 6191 #else | |
| 6192 // This used to conditionally jump to forward_exception however it is | |
| 6193 // possible if we relocate that the branch will not reach. So we must jump | |
| 6194 // around so we can always reach | |
| 6195 | |
| 6196 Label ok; | |
| 6197 jcc(Assembler::equal, ok); | |
| 6198 jump(RuntimeAddress(StubRoutines::forward_exception_entry())); | |
| 6199 bind(ok); | |
| 6200 #endif // LP64 | |
| 6201 } | |
| 6202 | |
| 6203 // get oop result if there is one and reset the value in the thread | |
| 6204 if (oop_result->is_valid()) { | |
| 6205 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset())); | |
|
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|
6206 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD); |
| 304 | 6207 verify_oop(oop_result, "broken oop in call_VM_base"); |
| 6208 } | |
| 6209 } | |
| 6210 | |
| 6211 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) { | |
| 6212 | |
| 6213 // Calculate the value for last_Java_sp | |
| 6214 // somewhat subtle. call_VM does an intermediate call | |
| 6215 // which places a return address on the stack just under the | |
| 6216 // stack pointer as the user finsihed with it. This allows | |
| 6217 // use to retrieve last_Java_pc from last_Java_sp[-1]. | |
| 6218 // On 32bit we then have to push additional args on the stack to accomplish | |
| 6219 // the actual requested call. On 64bit call_VM only can use register args | |
| 6220 // so the only extra space is the return address that call_VM created. | |
| 6221 // This hopefully explains the calculations here. | |
| 6222 | |
| 6223 #ifdef _LP64 | |
| 6224 // We've pushed one address, correct last_Java_sp | |
| 6225 lea(rax, Address(rsp, wordSize)); | |
| 6226 #else | |
| 6227 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize)); | |
| 6228 #endif // LP64 | |
| 6229 | |
| 6230 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions); | |
| 6231 | |
| 6232 } | |
| 6233 | |
| 6234 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) { | |
| 6235 call_VM_leaf_base(entry_point, number_of_arguments); | |
| 6236 } | |
| 6237 | |
| 6238 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) { | |
| 6239 pass_arg0(this, arg_0); | |
| 6240 call_VM_leaf(entry_point, 1); | |
| 6241 } | |
| 6242 | |
| 6243 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { | |
| 6244 | |
| 6245 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); | |
| 6246 pass_arg1(this, arg_1); | |
| 6247 pass_arg0(this, arg_0); | |
| 6248 call_VM_leaf(entry_point, 2); | |
| 6249 } | |
| 6250 | |
| 6251 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { | |
| 6252 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); | |
| 6253 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
| 6254 pass_arg2(this, arg_2); | |
| 6255 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); | |
| 6256 pass_arg1(this, arg_1); | |
| 6257 pass_arg0(this, arg_0); | |
| 6258 call_VM_leaf(entry_point, 3); | |
| 6259 } | |
| 6260 | |
|
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6261 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) { |
|
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|
6262 pass_arg0(this, arg_0); |
|
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|
6263 MacroAssembler::call_VM_leaf_base(entry_point, 1); |
|
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6264 } |
|
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|
6265 |
|
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|
6266 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { |
|
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6267 |
|
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|
6268 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); |
|
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|
6269 pass_arg1(this, arg_1); |
|
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|
6270 pass_arg0(this, arg_0); |
|
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|
6271 MacroAssembler::call_VM_leaf_base(entry_point, 2); |
|
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6272 } |
|
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6273 |
|
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6274 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { |
|
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|
6275 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); |
|
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|
6276 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); |
|
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6277 pass_arg2(this, arg_2); |
|
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|
6278 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); |
|
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6279 pass_arg1(this, arg_1); |
|
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6280 pass_arg0(this, arg_0); |
|
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|
6281 MacroAssembler::call_VM_leaf_base(entry_point, 3); |
|
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6282 } |
|
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6283 |
|
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6284 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) { |
|
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6285 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg")); |
|
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6286 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); |
|
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|
6287 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); |
|
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|
6288 pass_arg3(this, arg_3); |
|
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|
6289 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); |
|
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|
6290 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); |
|
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|
6291 pass_arg2(this, arg_2); |
|
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|
6292 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); |
|
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|
6293 pass_arg1(this, arg_1); |
|
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|
6294 pass_arg0(this, arg_0); |
|
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|
6295 MacroAssembler::call_VM_leaf_base(entry_point, 4); |
|
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|
6296 } |
|
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|
6297 |
| 304 | 6298 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { |
| 6299 } | |
| 6300 | |
| 6301 void MacroAssembler::check_and_handle_popframe(Register java_thread) { | |
| 6302 } | |
| 6303 | |
| 6304 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) { | |
| 6305 if (reachable(src1)) { | |
| 6306 cmpl(as_Address(src1), imm); | |
| 6307 } else { | |
| 6308 lea(rscratch1, src1); | |
| 6309 cmpl(Address(rscratch1, 0), imm); | |
| 6310 } | |
| 6311 } | |
| 6312 | |
| 6313 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) { | |
| 6314 assert(!src2.is_lval(), "use cmpptr"); | |
| 6315 if (reachable(src2)) { | |
| 6316 cmpl(src1, as_Address(src2)); | |
| 6317 } else { | |
| 6318 lea(rscratch1, src2); | |
| 6319 cmpl(src1, Address(rscratch1, 0)); | |
| 6320 } | |
| 6321 } | |
| 6322 | |
| 6323 void MacroAssembler::cmp32(Register src1, int32_t imm) { | |
| 6324 Assembler::cmpl(src1, imm); | |
| 6325 } | |
| 6326 | |
| 6327 void MacroAssembler::cmp32(Register src1, Address src2) { | |
| 6328 Assembler::cmpl(src1, src2); | |
| 6329 } | |
| 6330 | |
| 6331 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { | |
| 6332 ucomisd(opr1, opr2); | |
| 6333 | |
| 6334 Label L; | |
| 6335 if (unordered_is_less) { | |
| 6336 movl(dst, -1); | |
| 6337 jcc(Assembler::parity, L); | |
| 6338 jcc(Assembler::below , L); | |
| 6339 movl(dst, 0); | |
| 6340 jcc(Assembler::equal , L); | |
| 6341 increment(dst); | |
| 6342 } else { // unordered is greater | |
| 6343 movl(dst, 1); | |
| 6344 jcc(Assembler::parity, L); | |
| 6345 jcc(Assembler::above , L); | |
| 6346 movl(dst, 0); | |
| 6347 jcc(Assembler::equal , L); | |
| 6348 decrementl(dst); | |
| 6349 } | |
| 6350 bind(L); | |
| 6351 } | |
| 6352 | |
| 6353 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { | |
| 6354 ucomiss(opr1, opr2); | |
| 6355 | |
| 6356 Label L; | |
| 6357 if (unordered_is_less) { | |
| 6358 movl(dst, -1); | |
| 6359 jcc(Assembler::parity, L); | |
| 6360 jcc(Assembler::below , L); | |
| 6361 movl(dst, 0); | |
| 6362 jcc(Assembler::equal , L); | |
| 6363 increment(dst); | |
| 6364 } else { // unordered is greater | |
| 6365 movl(dst, 1); | |
| 6366 jcc(Assembler::parity, L); | |
| 6367 jcc(Assembler::above , L); | |
| 6368 movl(dst, 0); | |
| 6369 jcc(Assembler::equal , L); | |
| 6370 decrementl(dst); | |
| 6371 } | |
| 6372 bind(L); | |
| 6373 } | |
| 6374 | |
| 6375 | |
| 6376 void MacroAssembler::cmp8(AddressLiteral src1, int imm) { | |
| 6377 if (reachable(src1)) { | |
| 6378 cmpb(as_Address(src1), imm); | |
| 6379 } else { | |
| 6380 lea(rscratch1, src1); | |
| 6381 cmpb(Address(rscratch1, 0), imm); | |
| 6382 } | |
| 6383 } | |
| 6384 | |
| 6385 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) { | |
| 6386 #ifdef _LP64 | |
| 6387 if (src2.is_lval()) { | |
| 6388 movptr(rscratch1, src2); | |
| 6389 Assembler::cmpq(src1, rscratch1); | |
| 6390 } else if (reachable(src2)) { | |
| 6391 cmpq(src1, as_Address(src2)); | |
| 6392 } else { | |
| 6393 lea(rscratch1, src2); | |
| 6394 Assembler::cmpq(src1, Address(rscratch1, 0)); | |
| 6395 } | |
| 6396 #else | |
| 6397 if (src2.is_lval()) { | |
| 6398 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); | |
| 6399 } else { | |
| 6400 cmpl(src1, as_Address(src2)); | |
| 6401 } | |
| 6402 #endif // _LP64 | |
| 6403 } | |
| 6404 | |
| 6405 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) { | |
| 6406 assert(src2.is_lval(), "not a mem-mem compare"); | |
| 6407 #ifdef _LP64 | |
| 6408 // moves src2's literal address | |
| 6409 movptr(rscratch1, src2); | |
| 6410 Assembler::cmpq(src1, rscratch1); | |
| 6411 #else | |
| 6412 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); | |
| 6413 #endif // _LP64 | |
| 6414 } | |
| 6415 | |
| 6416 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) { | |
| 6417 if (reachable(adr)) { | |
| 6418 if (os::is_MP()) | |
| 6419 lock(); | |
| 6420 cmpxchgptr(reg, as_Address(adr)); | |
| 6421 } else { | |
| 6422 lea(rscratch1, adr); | |
| 6423 if (os::is_MP()) | |
| 6424 lock(); | |
| 6425 cmpxchgptr(reg, Address(rscratch1, 0)); | |
| 6426 } | |
| 6427 } | |
| 6428 | |
| 6429 void MacroAssembler::cmpxchgptr(Register reg, Address adr) { | |
| 6430 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr)); | |
| 6431 } | |
| 6432 | |
| 6433 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) { | |
| 1060 | 6434 if (reachable(src)) { |
| 4759 | 6435 Assembler::comisd(dst, as_Address(src)); |
| 1060 | 6436 } else { |
| 6437 lea(rscratch1, src); | |
| 4759 | 6438 Assembler::comisd(dst, Address(rscratch1, 0)); |
| 1060 | 6439 } |
| 304 | 6440 } |
| 6441 | |
| 6442 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) { | |
| 1060 | 6443 if (reachable(src)) { |
| 4759 | 6444 Assembler::comiss(dst, as_Address(src)); |
| 1060 | 6445 } else { |
| 6446 lea(rscratch1, src); | |
| 4759 | 6447 Assembler::comiss(dst, Address(rscratch1, 0)); |
| 1060 | 6448 } |
| 304 | 6449 } |
| 6450 | |
| 6451 | |
| 6452 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) { | |
| 6453 Condition negated_cond = negate_condition(cond); | |
| 6454 Label L; | |
| 6455 jcc(negated_cond, L); | |
| 6456 atomic_incl(counter_addr); | |
| 6457 bind(L); | |
| 6458 } | |
| 6459 | |
| 6460 int MacroAssembler::corrected_idivl(Register reg) { | |
| 6461 // Full implementation of Java idiv and irem; checks for | |
| 6462 // special case as described in JVM spec., p.243 & p.271. | |
| 6463 // The function returns the (pc) offset of the idivl | |
| 6464 // instruction - may be needed for implicit exceptions. | |
| 6465 // | |
| 6466 // normal case special case | |
| 6467 // | |
| 6468 // input : rax,: dividend min_int | |
| 6469 // reg: divisor (may not be rax,/rdx) -1 | |
| 6470 // | |
| 6471 // output: rax,: quotient (= rax, idiv reg) min_int | |
| 6472 // rdx: remainder (= rax, irem reg) 0 | |
| 6473 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register"); | |
| 6474 const int min_int = 0x80000000; | |
| 6475 Label normal_case, special_case; | |
| 6476 | |
| 6477 // check for special case | |
| 6478 cmpl(rax, min_int); | |
| 6479 jcc(Assembler::notEqual, normal_case); | |
| 6480 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0) | |
| 6481 cmpl(reg, -1); | |
| 6482 jcc(Assembler::equal, special_case); | |
| 6483 | |
| 6484 // handle normal case | |
| 6485 bind(normal_case); | |
| 6486 cdql(); | |
| 6487 int idivl_offset = offset(); | |
| 6488 idivl(reg); | |
| 6489 | |
| 6490 // normal and special case exit | |
| 6491 bind(special_case); | |
| 6492 | |
| 6493 return idivl_offset; | |
| 6494 } | |
| 6495 | |
| 6496 | |
| 6497 | |
| 6498 void MacroAssembler::decrementl(Register reg, int value) { | |
| 6499 if (value == min_jint) {subl(reg, value) ; return; } | |
| 6500 if (value < 0) { incrementl(reg, -value); return; } | |
| 6501 if (value == 0) { ; return; } | |
| 6502 if (value == 1 && UseIncDec) { decl(reg) ; return; } | |
| 6503 /* else */ { subl(reg, value) ; return; } | |
| 6504 } | |
| 6505 | |
| 6506 void MacroAssembler::decrementl(Address dst, int value) { | |
| 6507 if (value == min_jint) {subl(dst, value) ; return; } | |
| 6508 if (value < 0) { incrementl(dst, -value); return; } | |
| 6509 if (value == 0) { ; return; } | |
| 6510 if (value == 1 && UseIncDec) { decl(dst) ; return; } | |
| 6511 /* else */ { subl(dst, value) ; return; } | |
| 6512 } | |
| 6513 | |
| 6514 void MacroAssembler::division_with_shift (Register reg, int shift_value) { | |
| 6515 assert (shift_value > 0, "illegal shift value"); | |
| 6516 Label _is_positive; | |
| 6517 testl (reg, reg); | |
| 6518 jcc (Assembler::positive, _is_positive); | |
| 6519 int offset = (1 << shift_value) - 1 ; | |
| 6520 | |
| 6521 if (offset == 1) { | |
| 6522 incrementl(reg); | |
| 6523 } else { | |
| 6524 addl(reg, offset); | |
| 6525 } | |
| 6526 | |
| 6527 bind (_is_positive); | |
| 6528 sarl(reg, shift_value); | |
| 6529 } | |
| 6530 | |
| 4759 | 6531 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) { |
| 6532 if (reachable(src)) { | |
| 6533 Assembler::divsd(dst, as_Address(src)); | |
| 6534 } else { | |
| 6535 lea(rscratch1, src); | |
| 6536 Assembler::divsd(dst, Address(rscratch1, 0)); | |
| 6537 } | |
| 6538 } | |
| 6539 | |
| 6540 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) { | |
| 6541 if (reachable(src)) { | |
| 6542 Assembler::divss(dst, as_Address(src)); | |
| 6543 } else { | |
| 6544 lea(rscratch1, src); | |
| 6545 Assembler::divss(dst, Address(rscratch1, 0)); | |
| 6546 } | |
| 6547 } | |
| 6548 | |
| 304 | 6549 // !defined(COMPILER2) is because of stupid core builds |
| 6550 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) | |
| 6551 void MacroAssembler::empty_FPU_stack() { | |
| 6552 if (VM_Version::supports_mmx()) { | |
| 6553 emms(); | |
| 6554 } else { | |
| 6555 for (int i = 8; i-- > 0; ) ffree(i); | |
| 6556 } | |
| 6557 } | |
| 6558 #endif // !LP64 || C1 || !C2 | |
| 6559 | |
| 6560 | |
| 6561 // Defines obj, preserves var_size_in_bytes | |
| 6562 void MacroAssembler::eden_allocate(Register obj, | |
| 6563 Register var_size_in_bytes, | |
| 6564 int con_size_in_bytes, | |
| 6565 Register t1, | |
| 6566 Label& slow_case) { | |
| 6567 assert(obj == rax, "obj must be in rax, for cmpxchg"); | |
| 6568 assert_different_registers(obj, var_size_in_bytes, t1); | |
| 362 | 6569 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { |
| 6570 jmp(slow_case); | |
| 304 | 6571 } else { |
| 362 | 6572 Register end = t1; |
| 6573 Label retry; | |
| 6574 bind(retry); | |
| 6575 ExternalAddress heap_top((address) Universe::heap()->top_addr()); | |
| 6576 movptr(obj, heap_top); | |
| 6577 if (var_size_in_bytes == noreg) { | |
| 6578 lea(end, Address(obj, con_size_in_bytes)); | |
| 6579 } else { | |
| 6580 lea(end, Address(obj, var_size_in_bytes, Address::times_1)); | |
| 6581 } | |
| 6582 // if end < obj then we wrapped around => object too long => slow case | |
| 6583 cmpptr(end, obj); | |
| 6584 jcc(Assembler::below, slow_case); | |
| 6585 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr())); | |
| 6586 jcc(Assembler::above, slow_case); | |
| 6587 // Compare obj with the top addr, and if still equal, store the new top addr in | |
| 6588 // end at the address of the top addr pointer. Sets ZF if was equal, and clears | |
| 6589 // it otherwise. Use lock prefix for atomicity on MPs. | |
| 6590 locked_cmpxchgptr(end, heap_top); | |
| 6591 jcc(Assembler::notEqual, retry); | |
| 6592 } | |
| 304 | 6593 } |
| 6594 | |
| 6595 void MacroAssembler::enter() { | |
| 6596 push(rbp); | |
| 6597 mov(rbp, rsp); | |
| 6598 } | |
| 0 | 6599 |
| 6600 void MacroAssembler::fcmp(Register tmp) { | |
| 6601 fcmp(tmp, 1, true, true); | |
| 6602 } | |
| 6603 | |
| 6604 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) { | |
| 6605 assert(!pop_right || pop_left, "usage error"); | |
| 6606 if (VM_Version::supports_cmov()) { | |
| 6607 assert(tmp == noreg, "unneeded temp"); | |
| 6608 if (pop_left) { | |
| 6609 fucomip(index); | |
| 6610 } else { | |
| 6611 fucomi(index); | |
| 6612 } | |
| 6613 if (pop_right) { | |
| 6614 fpop(); | |
| 6615 } | |
| 6616 } else { | |
| 6617 assert(tmp != noreg, "need temp"); | |
| 6618 if (pop_left) { | |
| 6619 if (pop_right) { | |
| 6620 fcompp(); | |
| 6621 } else { | |
| 6622 fcomp(index); | |
| 6623 } | |
| 6624 } else { | |
| 6625 fcom(index); | |
| 6626 } | |
| 6627 // convert FPU condition into eflags condition via rax, | |
| 6628 save_rax(tmp); | |
| 6629 fwait(); fnstsw_ax(); | |
| 6630 sahf(); | |
| 6631 restore_rax(tmp); | |
| 6632 } | |
| 6633 // condition codes set as follows: | |
| 6634 // | |
| 6635 // CF (corresponds to C0) if x < y | |
| 6636 // PF (corresponds to C2) if unordered | |
| 6637 // ZF (corresponds to C3) if x = y | |
| 6638 } | |
| 6639 | |
| 6640 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) { | |
| 6641 fcmp2int(dst, unordered_is_less, 1, true, true); | |
| 6642 } | |
| 6643 | |
| 6644 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) { | |
| 6645 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right); | |
| 6646 Label L; | |
| 6647 if (unordered_is_less) { | |
| 6648 movl(dst, -1); | |
| 6649 jcc(Assembler::parity, L); | |
| 6650 jcc(Assembler::below , L); | |
| 6651 movl(dst, 0); | |
| 6652 jcc(Assembler::equal , L); | |
| 6653 increment(dst); | |
| 6654 } else { // unordered is greater | |
| 6655 movl(dst, 1); | |
| 6656 jcc(Assembler::parity, L); | |
| 6657 jcc(Assembler::above , L); | |
| 6658 movl(dst, 0); | |
| 6659 jcc(Assembler::equal , L); | |
| 304 | 6660 decrementl(dst); |
| 0 | 6661 } |
| 6662 bind(L); | |
| 6663 } | |
| 6664 | |
| 304 | 6665 void MacroAssembler::fld_d(AddressLiteral src) { |
| 6666 fld_d(as_Address(src)); | |
| 6667 } | |
| 6668 | |
| 6669 void MacroAssembler::fld_s(AddressLiteral src) { | |
| 6670 fld_s(as_Address(src)); | |
| 6671 } | |
| 6672 | |
| 6673 void MacroAssembler::fld_x(AddressLiteral src) { | |
| 6674 Assembler::fld_x(as_Address(src)); | |
| 6675 } | |
| 6676 | |
| 6677 void MacroAssembler::fldcw(AddressLiteral src) { | |
| 6678 Assembler::fldcw(as_Address(src)); | |
| 6679 } | |
| 0 | 6680 |
| 6681 void MacroAssembler::fpop() { | |
| 6682 ffree(); | |
| 6683 fincstp(); | |
| 6684 } | |
| 6685 | |
| 304 | 6686 void MacroAssembler::fremr(Register tmp) { |
| 6687 save_rax(tmp); | |
| 6688 { Label L; | |
| 6689 bind(L); | |
| 6690 fprem(); | |
| 6691 fwait(); fnstsw_ax(); | |
| 6692 #ifdef _LP64 | |
| 6693 testl(rax, 0x400); | |
| 6694 jcc(Assembler::notEqual, L); | |
| 6695 #else | |
| 6696 sahf(); | |
| 6697 jcc(Assembler::parity, L); | |
| 6698 #endif // _LP64 | |
| 6699 } | |
| 6700 restore_rax(tmp); | |
| 6701 // Result is in ST0. | |
| 6702 // Note: fxch & fpop to get rid of ST1 | |
| 6703 // (otherwise FPU stack could overflow eventually) | |
| 6704 fxch(1); | |
| 6705 fpop(); | |
| 6706 } | |
| 6707 | |
| 6708 | |
| 6709 void MacroAssembler::incrementl(AddressLiteral dst) { | |
| 6710 if (reachable(dst)) { | |
| 6711 incrementl(as_Address(dst)); | |
| 0 | 6712 } else { |
| 304 | 6713 lea(rscratch1, dst); |
| 6714 incrementl(Address(rscratch1, 0)); | |
| 6715 } | |
| 6716 } | |
| 6717 | |
| 6718 void MacroAssembler::incrementl(ArrayAddress dst) { | |
| 6719 incrementl(as_Address(dst)); | |
| 6720 } | |
| 6721 | |
| 6722 void MacroAssembler::incrementl(Register reg, int value) { | |
| 6723 if (value == min_jint) {addl(reg, value) ; return; } | |
| 6724 if (value < 0) { decrementl(reg, -value); return; } | |
| 6725 if (value == 0) { ; return; } | |
| 6726 if (value == 1 && UseIncDec) { incl(reg) ; return; } | |
| 6727 /* else */ { addl(reg, value) ; return; } | |
| 6728 } | |
| 6729 | |
| 6730 void MacroAssembler::incrementl(Address dst, int value) { | |
| 6731 if (value == min_jint) {addl(dst, value) ; return; } | |
| 6732 if (value < 0) { decrementl(dst, -value); return; } | |
| 6733 if (value == 0) { ; return; } | |
| 6734 if (value == 1 && UseIncDec) { incl(dst) ; return; } | |
| 6735 /* else */ { addl(dst, value) ; return; } | |
| 6736 } | |
| 6737 | |
| 6738 void MacroAssembler::jump(AddressLiteral dst) { | |
| 6739 if (reachable(dst)) { | |
| 6740 jmp_literal(dst.target(), dst.rspec()); | |
| 6741 } else { | |
| 6742 lea(rscratch1, dst); | |
| 6743 jmp(rscratch1); | |
| 6744 } | |
| 6745 } | |
| 6746 | |
| 6747 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) { | |
| 6748 if (reachable(dst)) { | |
| 6749 InstructionMark im(this); | |
| 6750 relocate(dst.reloc()); | |
| 6751 const int short_size = 2; | |
| 6752 const int long_size = 6; | |
| 6753 int offs = (intptr_t)dst.target() - ((intptr_t)_code_pos); | |
| 6754 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) { | |
| 6755 // 0111 tttn #8-bit disp | |
| 6756 emit_byte(0x70 | cc); | |
| 6757 emit_byte((offs - short_size) & 0xFF); | |
| 6758 } else { | |
| 6759 // 0000 1111 1000 tttn #32-bit disp | |
| 6760 emit_byte(0x0F); | |
| 6761 emit_byte(0x80 | cc); | |
| 6762 emit_long(offs - long_size); | |
| 6763 } | |
| 0 | 6764 } else { |
| 304 | 6765 #ifdef ASSERT |
| 6766 warning("reversing conditional branch"); | |
| 6767 #endif /* ASSERT */ | |
| 6768 Label skip; | |
| 6769 jccb(reverse[cc], skip); | |
| 6770 lea(rscratch1, dst); | |
| 6771 Assembler::jmp(rscratch1); | |
| 6772 bind(skip); | |
| 6773 } | |
| 6774 } | |
| 6775 | |
| 6776 void MacroAssembler::ldmxcsr(AddressLiteral src) { | |
| 6777 if (reachable(src)) { | |
| 6778 Assembler::ldmxcsr(as_Address(src)); | |
| 6779 } else { | |
| 6780 lea(rscratch1, src); | |
| 6781 Assembler::ldmxcsr(Address(rscratch1, 0)); | |
| 6782 } | |
| 6783 } | |
| 6784 | |
| 6785 int MacroAssembler::load_signed_byte(Register dst, Address src) { | |
| 6786 int off; | |
| 6787 if (LP64_ONLY(true ||) VM_Version::is_P6()) { | |
| 6788 off = offset(); | |
| 6789 movsbl(dst, src); // movsxb | |
| 6790 } else { | |
| 6791 off = load_unsigned_byte(dst, src); | |
| 6792 shll(dst, 24); | |
| 6793 sarl(dst, 24); | |
| 6794 } | |
| 6795 return off; | |
| 6796 } | |
| 6797 | |
|
622
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6812678: macro assembler needs delayed binding of a few constants (for 6655638)
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606
diff
changeset
|
6798 // Note: load_signed_short used to be called load_signed_word. |
|
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
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606
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changeset
|
6799 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler |
|
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
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diff
changeset
|
6800 // manual, which means 16 bits, that usage is found nowhere in HotSpot code. |
|
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
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606
diff
changeset
|
6801 // The term "word" in HotSpot means a 32- or 64-bit machine word. |
|
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
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606
diff
changeset
|
6802 int MacroAssembler::load_signed_short(Register dst, Address src) { |
| 304 | 6803 int off; |
| 6804 if (LP64_ONLY(true ||) VM_Version::is_P6()) { | |
| 6805 // This is dubious to me since it seems safe to do a signed 16 => 64 bit | |
| 6806 // version but this is what 64bit has always done. This seems to imply | |
| 6807 // that users are only using 32bits worth. | |
| 6808 off = offset(); | |
| 6809 movswl(dst, src); // movsxw | |
| 6810 } else { | |
|
622
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6812678: macro assembler needs delayed binding of a few constants (for 6655638)
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606
diff
changeset
|
6811 off = load_unsigned_short(dst, src); |
| 304 | 6812 shll(dst, 16); |
| 6813 sarl(dst, 16); | |
| 6814 } | |
| 6815 return off; | |
| 6816 } | |
| 6817 | |
| 6818 int MacroAssembler::load_unsigned_byte(Register dst, Address src) { | |
| 6819 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, | |
| 6820 // and "3.9 Partial Register Penalties", p. 22). | |
| 6821 int off; | |
| 6822 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) { | |
| 6823 off = offset(); | |
| 6824 movzbl(dst, src); // movzxb | |
| 6825 } else { | |
| 6826 xorl(dst, dst); | |
| 6827 off = offset(); | |
| 6828 movb(dst, src); | |
| 6829 } | |
| 6830 return off; | |
| 6831 } | |
| 6832 | |
|
622
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6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
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606
diff
changeset
|
6833 // Note: load_unsigned_short used to be called load_unsigned_word. |
|
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6812678: macro assembler needs delayed binding of a few constants (for 6655638)
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606
diff
changeset
|
6834 int MacroAssembler::load_unsigned_short(Register dst, Address src) { |
| 304 | 6835 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, |
| 6836 // and "3.9 Partial Register Penalties", p. 22). | |
| 6837 int off; | |
| 6838 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) { | |
| 6839 off = offset(); | |
| 6840 movzwl(dst, src); // movzxw | |
| 6841 } else { | |
| 6842 xorl(dst, dst); | |
| 6843 off = offset(); | |
| 6844 movw(dst, src); | |
| 6845 } | |
| 6846 return off; | |
| 6847 } | |
| 6848 | |
|
2258
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7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
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2100
diff
changeset
|
6849 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) { |
| 1503 | 6850 switch (size_in_bytes) { |
|
622
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606
diff
changeset
|
6851 #ifndef _LP64 |
|
2258
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
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diff
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|
6852 case 8: |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
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2100
diff
changeset
|
6853 assert(dst2 != noreg, "second dest register required"); |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
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diff
changeset
|
6854 movl(dst, src); |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
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2100
diff
changeset
|
6855 movl(dst2, src.plus_disp(BytesPerInt)); |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
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2100
diff
changeset
|
6856 break; |
|
622
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
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606
diff
changeset
|
6857 #else |
|
2258
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7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
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2100
diff
changeset
|
6858 case 8: movq(dst, src); break; |
|
622
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6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
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606
diff
changeset
|
6859 #endif |
|
2258
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7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
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2100
diff
changeset
|
6860 case 4: movl(dst, src); break; |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
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2100
diff
changeset
|
6861 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break; |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
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2100
diff
changeset
|
6862 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break; |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
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diff
changeset
|
6863 default: ShouldNotReachHere(); |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
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2100
diff
changeset
|
6864 } |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
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2100
diff
changeset
|
6865 } |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
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diff
changeset
|
6866 |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
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2100
diff
changeset
|
6867 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) { |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
6868 switch (size_in_bytes) { |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
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2100
diff
changeset
|
6869 #ifndef _LP64 |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
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2100
diff
changeset
|
6870 case 8: |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
6871 assert(src2 != noreg, "second source register required"); |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
6872 movl(dst, src); |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
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2100
diff
changeset
|
6873 movl(dst.plus_disp(BytesPerInt), src2); |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
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2100
diff
changeset
|
6874 break; |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
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2100
diff
changeset
|
6875 #else |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
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2100
diff
changeset
|
6876 case 8: movq(dst, src); break; |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
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2100
diff
changeset
|
6877 #endif |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
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2100
diff
changeset
|
6878 case 4: movl(dst, src); break; |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
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2100
diff
changeset
|
6879 case 2: movw(dst, src); break; |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
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2100
diff
changeset
|
6880 case 1: movb(dst, src); break; |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
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2100
diff
changeset
|
6881 default: ShouldNotReachHere(); |
|
622
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
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606
diff
changeset
|
6882 } |
|
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
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606
diff
changeset
|
6883 } |
|
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6812678: macro assembler needs delayed binding of a few constants (for 6655638)
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diff
changeset
|
6884 |
| 304 | 6885 void MacroAssembler::mov32(AddressLiteral dst, Register src) { |
| 6886 if (reachable(dst)) { | |
| 6887 movl(as_Address(dst), src); | |
| 6888 } else { | |
| 6889 lea(rscratch1, dst); | |
| 6890 movl(Address(rscratch1, 0), src); | |
| 6891 } | |
| 6892 } | |
| 6893 | |
| 6894 void MacroAssembler::mov32(Register dst, AddressLiteral src) { | |
| 6895 if (reachable(src)) { | |
| 6896 movl(dst, as_Address(src)); | |
| 6897 } else { | |
| 6898 lea(rscratch1, src); | |
| 6899 movl(dst, Address(rscratch1, 0)); | |
| 6900 } | |
| 0 | 6901 } |
| 6902 | |
| 6903 // C++ bool manipulation | |
| 6904 | |
| 6905 void MacroAssembler::movbool(Register dst, Address src) { | |
| 6906 if(sizeof(bool) == 1) | |
| 6907 movb(dst, src); | |
| 6908 else if(sizeof(bool) == 2) | |
| 6909 movw(dst, src); | |
| 6910 else if(sizeof(bool) == 4) | |
| 6911 movl(dst, src); | |
| 6912 else | |
| 6913 // unsupported | |
| 6914 ShouldNotReachHere(); | |
| 6915 } | |
| 6916 | |
| 6917 void MacroAssembler::movbool(Address dst, bool boolconst) { | |
| 6918 if(sizeof(bool) == 1) | |
| 6919 movb(dst, (int) boolconst); | |
| 6920 else if(sizeof(bool) == 2) | |
| 6921 movw(dst, (int) boolconst); | |
| 6922 else if(sizeof(bool) == 4) | |
| 6923 movl(dst, (int) boolconst); | |
| 6924 else | |
| 6925 // unsupported | |
| 6926 ShouldNotReachHere(); | |
| 6927 } | |
| 6928 | |
| 6929 void MacroAssembler::movbool(Address dst, Register src) { | |
| 6930 if(sizeof(bool) == 1) | |
| 6931 movb(dst, src); | |
| 6932 else if(sizeof(bool) == 2) | |
| 6933 movw(dst, src); | |
| 6934 else if(sizeof(bool) == 4) | |
| 6935 movl(dst, src); | |
| 6936 else | |
| 6937 // unsupported | |
| 6938 ShouldNotReachHere(); | |
| 6939 } | |
| 6940 | |
| 304 | 6941 void MacroAssembler::movbyte(ArrayAddress dst, int src) { |
| 6942 movb(as_Address(dst), src); | |
| 6943 } | |
| 6944 | |
| 6945 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) { | |
| 6946 if (reachable(src)) { | |
| 6947 if (UseXmmLoadAndClearUpper) { | |
| 6948 movsd (dst, as_Address(src)); | |
| 6949 } else { | |
| 6950 movlpd(dst, as_Address(src)); | |
| 6951 } | |
| 6952 } else { | |
| 6953 lea(rscratch1, src); | |
| 6954 if (UseXmmLoadAndClearUpper) { | |
| 6955 movsd (dst, Address(rscratch1, 0)); | |
| 6956 } else { | |
| 6957 movlpd(dst, Address(rscratch1, 0)); | |
| 6958 } | |
| 6959 } | |
| 6960 } | |
| 6961 | |
| 6962 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) { | |
| 6963 if (reachable(src)) { | |
| 6964 movss(dst, as_Address(src)); | |
| 6965 } else { | |
| 6966 lea(rscratch1, src); | |
| 6967 movss(dst, Address(rscratch1, 0)); | |
| 6968 } | |
| 6969 } | |
| 6970 | |
| 6971 void MacroAssembler::movptr(Register dst, Register src) { | |
| 6972 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
| 6973 } | |
| 6974 | |
| 6975 void MacroAssembler::movptr(Register dst, Address src) { | |
| 6976 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
| 6977 } | |
| 6978 | |
| 6979 // src should NEVER be a real pointer. Use AddressLiteral for true pointers | |
| 6980 void MacroAssembler::movptr(Register dst, intptr_t src) { | |
| 6981 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src)); | |
| 6982 } | |
| 6983 | |
| 6984 void MacroAssembler::movptr(Address dst, Register src) { | |
| 6985 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
| 6986 } | |
| 6987 | |
| 4759 | 6988 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) { |
| 6989 if (reachable(src)) { | |
| 6990 Assembler::movsd(dst, as_Address(src)); | |
| 6991 } else { | |
| 6992 lea(rscratch1, src); | |
| 6993 Assembler::movsd(dst, Address(rscratch1, 0)); | |
| 6994 } | |
| 6995 } | |
| 6996 | |
| 304 | 6997 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) { |
| 6998 if (reachable(src)) { | |
| 4759 | 6999 Assembler::movss(dst, as_Address(src)); |
| 304 | 7000 } else { |
| 7001 lea(rscratch1, src); | |
| 4759 | 7002 Assembler::movss(dst, Address(rscratch1, 0)); |
| 7003 } | |
| 7004 } | |
| 7005 | |
| 7006 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) { | |
| 7007 if (reachable(src)) { | |
| 7008 Assembler::mulsd(dst, as_Address(src)); | |
| 7009 } else { | |
| 7010 lea(rscratch1, src); | |
| 7011 Assembler::mulsd(dst, Address(rscratch1, 0)); | |
| 7012 } | |
| 7013 } | |
| 7014 | |
| 7015 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) { | |
| 7016 if (reachable(src)) { | |
| 7017 Assembler::mulss(dst, as_Address(src)); | |
| 7018 } else { | |
| 7019 lea(rscratch1, src); | |
| 7020 Assembler::mulss(dst, Address(rscratch1, 0)); | |
| 304 | 7021 } |
| 7022 } | |
| 7023 | |
| 7024 void MacroAssembler::null_check(Register reg, int offset) { | |
| 7025 if (needs_explicit_null_check(offset)) { | |
| 7026 // provoke OS NULL exception if reg = NULL by | |
| 7027 // accessing M[reg] w/o changing any (non-CC) registers | |
| 7028 // NOTE: cmpl is plenty here to provoke a segv | |
| 7029 cmpptr(rax, Address(reg, 0)); | |
| 7030 // Note: should probably use testl(rax, Address(reg, 0)); | |
| 7031 // may be shorter code (however, this version of | |
| 7032 // testl needs to be implemented first) | |
| 7033 } else { | |
| 7034 // nothing to do, (later) access of M[reg + offset] | |
| 7035 // will provoke OS NULL exception if reg = NULL | |
| 7036 } | |
| 7037 } | |
| 7038 | |
| 7039 void MacroAssembler::os_breakpoint() { | |
| 7040 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability | |
| 7041 // (e.g., MSVC can't call ps() otherwise) | |
| 7042 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint))); | |
| 7043 } | |
| 7044 | |
| 7045 void MacroAssembler::pop_CPU_state() { | |
| 7046 pop_FPU_state(); | |
| 7047 pop_IU_state(); | |
| 7048 } | |
| 7049 | |
| 7050 void MacroAssembler::pop_FPU_state() { | |
| 7051 NOT_LP64(frstor(Address(rsp, 0));) | |
| 7052 LP64_ONLY(fxrstor(Address(rsp, 0));) | |
| 7053 addptr(rsp, FPUStateSizeInWords * wordSize); | |
| 7054 } | |
| 7055 | |
| 7056 void MacroAssembler::pop_IU_state() { | |
| 7057 popa(); | |
| 7058 LP64_ONLY(addq(rsp, 8)); | |
| 7059 popf(); | |
| 7060 } | |
| 7061 | |
| 7062 // Save Integer and Float state | |
| 7063 // Warning: Stack must be 16 byte aligned (64bit) | |
| 7064 void MacroAssembler::push_CPU_state() { | |
| 7065 push_IU_state(); | |
| 7066 push_FPU_state(); | |
| 7067 } | |
| 7068 | |
| 7069 void MacroAssembler::push_FPU_state() { | |
| 7070 subptr(rsp, FPUStateSizeInWords * wordSize); | |
| 7071 #ifndef _LP64 | |
| 7072 fnsave(Address(rsp, 0)); | |
| 7073 fwait(); | |
| 7074 #else | |
| 7075 fxsave(Address(rsp, 0)); | |
| 7076 #endif // LP64 | |
| 7077 } | |
| 7078 | |
| 7079 void MacroAssembler::push_IU_state() { | |
| 7080 // Push flags first because pusha kills them | |
| 7081 pushf(); | |
| 7082 // Make sure rsp stays 16-byte aligned | |
| 7083 LP64_ONLY(subq(rsp, 8)); | |
| 7084 pusha(); | |
| 7085 } | |
| 7086 | |
| 7087 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) { | |
| 7088 // determine java_thread register | |
| 7089 if (!java_thread->is_valid()) { | |
| 7090 java_thread = rdi; | |
| 7091 get_thread(java_thread); | |
| 7092 } | |
| 7093 // we must set sp to zero to clear frame | |
|
512
db4caa99ef11
6787106: Hotspot 32 bit build fails on platforms having different definitions for intptr_t & int32_t
xlu
parents:
420
diff
changeset
|
7094 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); |
| 304 | 7095 if (clear_fp) { |
|
512
db4caa99ef11
6787106: Hotspot 32 bit build fails on platforms having different definitions for intptr_t & int32_t
xlu
parents:
420
diff
changeset
|
7096 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); |
| 304 | 7097 } |
| 7098 | |
| 7099 if (clear_pc) | |
|
512
db4caa99ef11
6787106: Hotspot 32 bit build fails on platforms having different definitions for intptr_t & int32_t
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diff
changeset
|
7100 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); |
| 304 | 7101 |
| 7102 } | |
| 7103 | |
| 7104 void MacroAssembler::restore_rax(Register tmp) { | |
| 7105 if (tmp == noreg) pop(rax); | |
| 7106 else if (tmp != rax) mov(rax, tmp); | |
| 7107 } | |
| 7108 | |
| 7109 void MacroAssembler::round_to(Register reg, int modulus) { | |
| 7110 addptr(reg, modulus - 1); | |
| 7111 andptr(reg, -modulus); | |
| 7112 } | |
| 7113 | |
| 7114 void MacroAssembler::save_rax(Register tmp) { | |
| 7115 if (tmp == noreg) push(rax); | |
| 7116 else if (tmp != rax) mov(tmp, rax); | |
| 7117 } | |
| 7118 | |
| 7119 // Write serialization page so VM thread can do a pseudo remote membar. | |
| 7120 // We use the current thread pointer to calculate a thread specific | |
| 7121 // offset to write to within the page. This minimizes bus traffic | |
| 7122 // due to cache line collision. | |
| 7123 void MacroAssembler::serialize_memory(Register thread, Register tmp) { | |
| 7124 movl(tmp, thread); | |
| 7125 shrl(tmp, os::get_serialize_page_shift_count()); | |
| 7126 andl(tmp, (os::vm_page_size() - sizeof(int))); | |
| 7127 | |
| 7128 Address index(noreg, tmp, Address::times_1); | |
| 7129 ExternalAddress page(os::get_memory_serialize_page()); | |
| 7130 | |
|
606
19962e74284f
6811384: MacroAssembler::serialize_memory may touch next page on amd64
never
parents:
520
diff
changeset
|
7131 // Size of store must match masking code above |
|
19962e74284f
6811384: MacroAssembler::serialize_memory may touch next page on amd64
never
parents:
520
diff
changeset
|
7132 movl(as_Address(ArrayAddress(page, index)), tmp); |
| 304 | 7133 } |
| 7134 | |
| 7135 // Calls to C land | |
| 7136 // | |
| 7137 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded | |
| 7138 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp | |
| 7139 // has to be reset to 0. This is required to allow proper stack traversal. | |
| 7140 void MacroAssembler::set_last_Java_frame(Register java_thread, | |
| 7141 Register last_java_sp, | |
| 7142 Register last_java_fp, | |
| 7143 address last_java_pc) { | |
| 7144 // determine java_thread register | |
| 7145 if (!java_thread->is_valid()) { | |
| 7146 java_thread = rdi; | |
| 7147 get_thread(java_thread); | |
| 7148 } | |
| 7149 // determine last_java_sp register | |
| 7150 if (!last_java_sp->is_valid()) { | |
| 7151 last_java_sp = rsp; | |
| 7152 } | |
| 7153 | |
| 7154 // last_java_fp is optional | |
| 7155 | |
| 7156 if (last_java_fp->is_valid()) { | |
| 7157 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp); | |
| 7158 } | |
| 7159 | |
| 7160 // last_java_pc is optional | |
| 7161 | |
| 7162 if (last_java_pc != NULL) { | |
| 7163 lea(Address(java_thread, | |
| 7164 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()), | |
| 7165 InternalAddress(last_java_pc)); | |
| 7166 | |
| 7167 } | |
| 7168 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp); | |
| 7169 } | |
| 7170 | |
| 7171 void MacroAssembler::shlptr(Register dst, int imm8) { | |
| 7172 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8)); | |
| 7173 } | |
| 7174 | |
| 7175 void MacroAssembler::shrptr(Register dst, int imm8) { | |
| 7176 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8)); | |
| 7177 } | |
| 7178 | |
| 7179 void MacroAssembler::sign_extend_byte(Register reg) { | |
| 7180 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) { | |
| 7181 movsbl(reg, reg); // movsxb | |
| 7182 } else { | |
| 7183 shll(reg, 24); | |
| 7184 sarl(reg, 24); | |
| 7185 } | |
| 7186 } | |
| 7187 | |
| 7188 void MacroAssembler::sign_extend_short(Register reg) { | |
| 7189 if (LP64_ONLY(true ||) VM_Version::is_P6()) { | |
| 7190 movswl(reg, reg); // movsxw | |
| 7191 } else { | |
| 7192 shll(reg, 16); | |
| 7193 sarl(reg, 16); | |
| 7194 } | |
| 7195 } | |
| 7196 | |
|
2404
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6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
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2357
diff
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|
7197 void MacroAssembler::testl(Register dst, AddressLiteral src) { |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2357
diff
changeset
|
7198 assert(reachable(src), "Address should be reachable"); |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
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diff
changeset
|
7199 testl(dst, as_Address(src)); |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
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diff
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|
7200 } |
|
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
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diff
changeset
|
7201 |
| 4759 | 7202 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) { |
| 7203 if (reachable(src)) { | |
| 7204 Assembler::sqrtsd(dst, as_Address(src)); | |
| 7205 } else { | |
| 7206 lea(rscratch1, src); | |
| 7207 Assembler::sqrtsd(dst, Address(rscratch1, 0)); | |
| 7208 } | |
| 7209 } | |
| 7210 | |
| 7211 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) { | |
| 7212 if (reachable(src)) { | |
| 7213 Assembler::sqrtss(dst, as_Address(src)); | |
| 7214 } else { | |
| 7215 lea(rscratch1, src); | |
| 7216 Assembler::sqrtss(dst, Address(rscratch1, 0)); | |
| 7217 } | |
| 7218 } | |
| 7219 | |
| 7220 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) { | |
| 7221 if (reachable(src)) { | |
| 7222 Assembler::subsd(dst, as_Address(src)); | |
| 7223 } else { | |
| 7224 lea(rscratch1, src); | |
| 7225 Assembler::subsd(dst, Address(rscratch1, 0)); | |
| 7226 } | |
| 7227 } | |
| 7228 | |
| 7229 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) { | |
| 7230 if (reachable(src)) { | |
| 7231 Assembler::subss(dst, as_Address(src)); | |
| 7232 } else { | |
| 7233 lea(rscratch1, src); | |
| 7234 Assembler::subss(dst, Address(rscratch1, 0)); | |
| 7235 } | |
| 7236 } | |
| 7237 | |
| 362 | 7238 ////////////////////////////////////////////////////////////////////////////////// |
| 7239 #ifndef SERIALGC | |
| 7240 | |
| 7241 void MacroAssembler::g1_write_barrier_pre(Register obj, | |
|
3249
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7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
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diff
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|
7242 Register pre_val, |
| 362 | 7243 Register thread, |
| 7244 Register tmp, | |
|
3249
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
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2357
diff
changeset
|
7245 bool tosca_live, |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7246 bool expand_call) { |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7247 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7248 // If expand_call is true then we expand the call_VM_leaf macro |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7249 // directly to skip generating the check by |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7250 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp. |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7251 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
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2357
diff
changeset
|
7252 #ifdef _LP64 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7253 assert(thread == r15_thread, "must be"); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7254 #endif // _LP64 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7255 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7256 Label done; |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7257 Label runtime; |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7258 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7259 assert(pre_val != noreg, "check this code"); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7260 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7261 if (obj != noreg) { |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7262 assert_different_registers(obj, pre_val, tmp); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
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2357
diff
changeset
|
7263 assert(pre_val != rax, "check this code"); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7264 } |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
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diff
changeset
|
7265 |
| 362 | 7266 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() + |
| 7267 PtrQueue::byte_offset_of_active())); | |
| 7268 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() + | |
| 7269 PtrQueue::byte_offset_of_index())); | |
| 7270 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() + | |
| 7271 PtrQueue::byte_offset_of_buf())); | |
| 7272 | |
| 7273 | |
|
3249
e1162778c1c8
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parents:
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diff
changeset
|
7274 // Is marking active? |
| 362 | 7275 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) { |
| 7276 cmpl(in_progress, 0); | |
| 7277 } else { | |
| 7278 assert(in_bytes(PtrQueue::byte_width_of_active()) == 1, "Assumption"); | |
| 7279 cmpb(in_progress, 0); | |
| 7280 } | |
| 7281 jcc(Assembler::equal, done); | |
| 7282 | |
|
3249
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7283 // Do we need to load the previous value? |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7284 if (obj != noreg) { |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7285 load_heap_oop(pre_val, Address(obj, 0)); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7286 } |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7287 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7288 // Is the previous value null? |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7289 cmpptr(pre_val, (int32_t) NULL_WORD); |
| 362 | 7290 jcc(Assembler::equal, done); |
| 7291 | |
| 7292 // Can we store original value in the thread's buffer? | |
|
3249
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7293 // Is index == 0? |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7294 // (The index field is typed as size_t.) |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7295 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7296 movptr(tmp, index); // tmp := *index_adr |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7297 cmpptr(tmp, 0); // tmp == 0? |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7298 jcc(Assembler::equal, runtime); // If yes, goto runtime |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7299 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7300 subptr(tmp, wordSize); // tmp := tmp - wordSize |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7301 movptr(index, tmp); // *index_adr := tmp |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7302 addptr(tmp, buffer); // tmp := tmp + *buffer_adr |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7303 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7304 // Record the previous value |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7305 movptr(Address(tmp, 0), pre_val); |
| 362 | 7306 jmp(done); |
|
3249
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7307 |
| 362 | 7308 bind(runtime); |
| 7309 // save the live input values | |
| 7310 if(tosca_live) push(rax); | |
|
3249
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7311 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7312 if (obj != noreg && obj != rax) |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7313 push(obj); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7314 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7315 if (pre_val != rax) |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7316 push(pre_val); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7317 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7318 // Calling the runtime using the regular call_VM_leaf mechanism generates |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7319 // code (generated by InterpreterMacroAssember::call_VM_leaf_base) |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7320 // that checks that the *(ebp+frame::interpreter_frame_last_sp) == NULL. |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7321 // |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7322 // If we care generating the pre-barrier without a frame (e.g. in the |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7323 // intrinsified Reference.get() routine) then ebp might be pointing to |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7324 // the caller frame and so this check will most likely fail at runtime. |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7325 // |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7326 // Expanding the call directly bypasses the generation of the check. |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7327 // So when we do not have have a full interpreter frame on the stack |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7328 // expand_call should be passed true. |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7329 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7330 NOT_LP64( push(thread); ) |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7331 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7332 if (expand_call) { |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7333 LP64_ONLY( assert(pre_val != c_rarg1, "smashed arg"); ) |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7334 pass_arg1(this, thread); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7335 pass_arg0(this, pre_val); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7336 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7337 } else { |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7338 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7339 } |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7340 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7341 NOT_LP64( pop(thread); ) |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7342 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7343 // save the live input values |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7344 if (pre_val != rax) |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7345 pop(pre_val); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7346 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7347 if (obj != noreg && obj != rax) |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7348 pop(obj); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7349 |
| 362 | 7350 if(tosca_live) pop(rax); |
|
3249
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7351 |
| 362 | 7352 bind(done); |
| 7353 } | |
| 7354 | |
| 7355 void MacroAssembler::g1_write_barrier_post(Register store_addr, | |
| 7356 Register new_val, | |
| 7357 Register thread, | |
| 7358 Register tmp, | |
| 7359 Register tmp2) { | |
|
3249
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7360 #ifdef _LP64 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7361 assert(thread == r15_thread, "must be"); |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7362 #endif // _LP64 |
|
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7363 |
| 362 | 7364 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() + |
| 7365 PtrQueue::byte_offset_of_index())); | |
| 7366 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() + | |
| 7367 PtrQueue::byte_offset_of_buf())); | |
|
3249
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
changeset
|
7368 |
| 362 | 7369 BarrierSet* bs = Universe::heap()->barrier_set(); |
| 7370 CardTableModRefBS* ct = (CardTableModRefBS*)bs; | |
| 7371 Label done; | |
| 7372 Label runtime; | |
| 7373 | |
| 7374 // Does store cross heap regions? | |
| 7375 | |
| 7376 movptr(tmp, store_addr); | |
| 7377 xorptr(tmp, new_val); | |
| 7378 shrptr(tmp, HeapRegion::LogOfHRGrainBytes); | |
| 7379 jcc(Assembler::equal, done); | |
| 7380 | |
| 7381 // crosses regions, storing NULL? | |
| 7382 | |
| 7383 cmpptr(new_val, (int32_t) NULL_WORD); | |
| 7384 jcc(Assembler::equal, done); | |
| 7385 | |
| 7386 // storing region crossing non-NULL, is card already dirty? | |
| 7387 | |
| 7388 ExternalAddress cardtable((address) ct->byte_map_base); | |
| 7389 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); | |
| 7390 #ifdef _LP64 | |
| 7391 const Register card_addr = tmp; | |
| 7392 | |
| 7393 movq(card_addr, store_addr); | |
| 7394 shrq(card_addr, CardTableModRefBS::card_shift); | |
| 7395 | |
| 7396 lea(tmp2, cardtable); | |
| 7397 | |
| 7398 // get the address of the card | |
| 7399 addq(card_addr, tmp2); | |
| 7400 #else | |
| 7401 const Register card_index = tmp; | |
| 7402 | |
| 7403 movl(card_index, store_addr); | |
| 7404 shrl(card_index, CardTableModRefBS::card_shift); | |
| 7405 | |
| 7406 Address index(noreg, card_index, Address::times_1); | |
| 7407 const Register card_addr = tmp; | |
| 7408 lea(card_addr, as_Address(ArrayAddress(cardtable, index))); | |
| 7409 #endif | |
| 7410 cmpb(Address(card_addr, 0), 0); | |
| 7411 jcc(Assembler::equal, done); | |
| 7412 | |
| 7413 // storing a region crossing, non-NULL oop, card is clean. | |
| 7414 // dirty card and log. | |
| 7415 | |
| 7416 movb(Address(card_addr, 0), 0); | |
| 7417 | |
| 7418 cmpl(queue_index, 0); | |
| 7419 jcc(Assembler::equal, runtime); | |
| 7420 subl(queue_index, wordSize); | |
| 7421 movptr(tmp2, buffer); | |
| 7422 #ifdef _LP64 | |
| 7423 movslq(rscratch1, queue_index); | |
| 7424 addq(tmp2, rscratch1); | |
| 7425 movq(Address(tmp2, 0), card_addr); | |
| 7426 #else | |
| 7427 addl(tmp2, queue_index); | |
| 7428 movl(Address(tmp2, 0), card_index); | |
| 7429 #endif | |
| 7430 jmp(done); | |
| 7431 | |
| 7432 bind(runtime); | |
| 7433 // save the live input values | |
| 7434 push(store_addr); | |
| 7435 push(new_val); | |
| 7436 #ifdef _LP64 | |
| 7437 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread); | |
| 7438 #else | |
| 7439 push(thread); | |
| 7440 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread); | |
| 7441 pop(thread); | |
| 7442 #endif | |
| 7443 pop(new_val); | |
| 7444 pop(store_addr); | |
| 7445 | |
| 7446 bind(done); | |
| 7447 } | |
| 7448 | |
| 7449 #endif // SERIALGC | |
| 7450 ////////////////////////////////////////////////////////////////////////////////// | |
| 7451 | |
| 7452 | |
| 304 | 7453 void MacroAssembler::store_check(Register obj) { |
| 7454 // Does a store check for the oop in register obj. The content of | |
| 7455 // register obj is destroyed afterwards. | |
| 7456 store_check_part_1(obj); | |
| 7457 store_check_part_2(obj); | |
| 7458 } | |
| 7459 | |
| 7460 void MacroAssembler::store_check(Register obj, Address dst) { | |
| 7461 store_check(obj); | |
| 7462 } | |
| 7463 | |
| 7464 | |
| 7465 // split the store check operation so that other instructions can be scheduled inbetween | |
| 7466 void MacroAssembler::store_check_part_1(Register obj) { | |
| 7467 BarrierSet* bs = Universe::heap()->barrier_set(); | |
| 7468 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind"); | |
| 7469 shrptr(obj, CardTableModRefBS::card_shift); | |
| 7470 } | |
| 7471 | |
| 7472 void MacroAssembler::store_check_part_2(Register obj) { | |
| 7473 BarrierSet* bs = Universe::heap()->barrier_set(); | |
| 7474 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind"); | |
| 7475 CardTableModRefBS* ct = (CardTableModRefBS*)bs; | |
| 7476 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); | |
| 7477 | |
| 7478 // The calculation for byte_map_base is as follows: | |
| 7479 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift); | |
| 7480 // So this essentially converts an address to a displacement and | |
| 7481 // it will never need to be relocated. On 64bit however the value may be too | |
| 7482 // large for a 32bit displacement | |
| 7483 | |
| 7484 intptr_t disp = (intptr_t) ct->byte_map_base; | |
| 7485 if (is_simm32(disp)) { | |
| 7486 Address cardtable(noreg, obj, Address::times_1, disp); | |
| 7487 movb(cardtable, 0); | |
| 7488 } else { | |
| 7489 // By doing it as an ExternalAddress disp could be converted to a rip-relative | |
| 7490 // displacement and done in a single instruction given favorable mapping and | |
| 7491 // a smarter version of as_Address. Worst case it is two instructions which | |
| 7492 // is no worse off then loading disp into a register and doing as a simple | |
| 7493 // Address() as above. | |
| 7494 // We can't do as ExternalAddress as the only style since if disp == 0 we'll | |
| 7495 // assert since NULL isn't acceptable in a reloci (see 6644928). In any case | |
| 7496 // in some cases we'll get a single instruction version. | |
| 7497 | |
| 7498 ExternalAddress cardtable((address)disp); | |
| 7499 Address index(noreg, obj, Address::times_1); | |
| 7500 movb(as_Address(ArrayAddress(cardtable, index)), 0); | |
| 7501 } | |
| 7502 } | |
| 7503 | |
| 7504 void MacroAssembler::subptr(Register dst, int32_t imm32) { | |
| 7505 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32)); | |
| 7506 } | |
| 7507 | |
| 7508 void MacroAssembler::subptr(Register dst, Register src) { | |
| 7509 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); | |
| 7510 } | |
| 7511 | |
| 7512 // C++ bool manipulation | |
| 0 | 7513 void MacroAssembler::testbool(Register dst) { |
| 7514 if(sizeof(bool) == 1) | |
| 304 | 7515 testb(dst, 0xff); |
| 0 | 7516 else if(sizeof(bool) == 2) { |
| 7517 // testw implementation needed for two byte bools | |
| 7518 ShouldNotReachHere(); | |
| 7519 } else if(sizeof(bool) == 4) | |
| 7520 testl(dst, dst); | |
| 7521 else | |
| 7522 // unsupported | |
| 7523 ShouldNotReachHere(); | |
| 7524 } | |
| 7525 | |
| 304 | 7526 void MacroAssembler::testptr(Register dst, Register src) { |
| 7527 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src)); | |
| 7528 } | |
| 7529 | |
| 7530 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes. | |
| 7531 void MacroAssembler::tlab_allocate(Register obj, | |
| 7532 Register var_size_in_bytes, | |
| 7533 int con_size_in_bytes, | |
| 7534 Register t1, | |
| 7535 Register t2, | |
| 7536 Label& slow_case) { | |
| 7537 assert_different_registers(obj, t1, t2); | |
| 7538 assert_different_registers(obj, var_size_in_bytes, t1); | |
| 7539 Register end = t2; | |
| 7540 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread); | |
| 7541 | |
| 7542 verify_tlab(); | |
| 7543 | |
| 7544 NOT_LP64(get_thread(thread)); | |
| 7545 | |
| 7546 movptr(obj, Address(thread, JavaThread::tlab_top_offset())); | |
| 7547 if (var_size_in_bytes == noreg) { | |
| 7548 lea(end, Address(obj, con_size_in_bytes)); | |
| 7549 } else { | |
| 7550 lea(end, Address(obj, var_size_in_bytes, Address::times_1)); | |
| 7551 } | |
| 7552 cmpptr(end, Address(thread, JavaThread::tlab_end_offset())); | |
| 7553 jcc(Assembler::above, slow_case); | |
| 7554 | |
| 7555 // update the tlab top pointer | |
| 7556 movptr(Address(thread, JavaThread::tlab_top_offset()), end); | |
| 7557 | |
| 7558 // recover var_size_in_bytes if necessary | |
| 7559 if (var_size_in_bytes == end) { | |
| 7560 subptr(var_size_in_bytes, obj); | |
| 7561 } | |
| 7562 verify_tlab(); | |
| 7563 } | |
| 7564 | |
| 7565 // Preserves rbx, and rdx. | |
|
2100
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
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parents:
2014
diff
changeset
|
7566 Register MacroAssembler::tlab_refill(Label& retry, |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
7567 Label& try_eden, |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
7568 Label& slow_case) { |
| 304 | 7569 Register top = rax; |
| 7570 Register t1 = rcx; | |
| 7571 Register t2 = rsi; | |
| 7572 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread); | |
| 7573 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx); | |
| 7574 Label do_refill, discard_tlab; | |
| 7575 | |
| 7576 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { | |
| 7577 // No allocation in the shared eden. | |
| 7578 jmp(slow_case); | |
| 7579 } | |
| 7580 | |
| 7581 NOT_LP64(get_thread(thread_reg)); | |
| 7582 | |
| 7583 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); | |
| 7584 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); | |
| 7585 | |
| 7586 // calculate amount of free space | |
| 7587 subptr(t1, top); | |
| 7588 shrptr(t1, LogHeapWordSize); | |
| 7589 | |
| 7590 // Retain tlab and allocate object in shared space if | |
| 7591 // the amount free in the tlab is too large to discard. | |
| 7592 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset()))); | |
| 7593 jcc(Assembler::lessEqual, discard_tlab); | |
| 7594 | |
| 7595 // Retain | |
| 7596 // %%% yuck as movptr... | |
| 7597 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment()); | |
| 7598 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2); | |
| 7599 if (TLABStats) { | |
| 7600 // increment number of slow_allocations | |
| 7601 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1); | |
| 7602 } | |
| 7603 jmp(try_eden); | |
| 7604 | |
| 7605 bind(discard_tlab); | |
| 7606 if (TLABStats) { | |
| 7607 // increment number of refills | |
| 7608 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1); | |
| 7609 // accumulate wastage -- t1 is amount free in tlab | |
| 7610 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1); | |
| 7611 } | |
| 7612 | |
| 7613 // if tlab is currently allocated (top or end != null) then | |
| 7614 // fill [top, end + alignment_reserve) with array object | |
|
2100
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7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
7615 testptr(top, top); |
| 304 | 7616 jcc(Assembler::zero, do_refill); |
| 7617 | |
| 7618 // set up the mark word | |
| 7619 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2)); | |
| 7620 // set the length to the remaining space | |
| 7621 subptr(t1, typeArrayOopDesc::header_size(T_INT)); | |
| 7622 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve()); | |
| 7623 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint))); | |
| 1690 | 7624 movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1); |
| 304 | 7625 // set klass to intArrayKlass |
| 7626 // dubious reloc why not an oop reloc? | |
|
2100
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7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
7627 movptr(t1, ExternalAddress((address)Universe::intArrayKlassObj_addr())); |
| 304 | 7628 // store klass last. concurrent gcs assumes klass length is valid if |
| 7629 // klass field is not null. | |
| 7630 store_klass(top, t1); | |
| 7631 | |
|
2100
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
7632 movptr(t1, top); |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
7633 subptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
7634 incr_allocated_bytes(thread_reg, t1, 0); |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
7635 |
| 304 | 7636 // refill the tlab with an eden allocation |
| 7637 bind(do_refill); | |
| 7638 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); | |
| 7639 shlptr(t1, LogHeapWordSize); | |
|
2100
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
7640 // allocate new tlab, address returned in top |
| 304 | 7641 eden_allocate(top, t1, 0, t2, slow_case); |
| 7642 | |
| 7643 // Check that t1 was preserved in eden_allocate. | |
| 7644 #ifdef ASSERT | |
| 7645 if (UseTLAB) { | |
| 7646 Label ok; | |
| 7647 Register tsize = rsi; | |
| 7648 assert_different_registers(tsize, thread_reg, t1); | |
| 7649 push(tsize); | |
| 7650 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); | |
| 7651 shlptr(tsize, LogHeapWordSize); | |
| 7652 cmpptr(t1, tsize); | |
| 7653 jcc(Assembler::equal, ok); | |
| 7654 stop("assert(t1 != tlab size)"); | |
| 7655 should_not_reach_here(); | |
| 7656 | |
| 7657 bind(ok); | |
| 7658 pop(tsize); | |
| 7659 } | |
| 7660 #endif | |
| 7661 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top); | |
| 7662 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top); | |
| 7663 addptr(top, t1); | |
| 7664 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes()); | |
| 7665 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top); | |
| 7666 verify_tlab(); | |
| 7667 jmp(retry); | |
|
2100
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
7668 |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
7669 return thread_reg; // for use by caller |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
7670 } |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
7671 |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
7672 void MacroAssembler::incr_allocated_bytes(Register thread, |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
7673 Register var_size_in_bytes, |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
7674 int con_size_in_bytes, |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
7675 Register t1) { |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
7676 #ifdef _LP64 |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
7677 if (var_size_in_bytes->is_valid()) { |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
7678 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes); |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
7679 } else { |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
7680 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes); |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
7681 } |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
7682 #else |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
7683 if (!thread->is_valid()) { |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
7684 assert(t1->is_valid(), "need temp reg"); |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
7685 thread = t1; |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
7686 get_thread(thread); |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
7687 } |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
7688 |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
7689 if (var_size_in_bytes->is_valid()) { |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
7690 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes); |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
7691 } else { |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
7692 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes); |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
7693 } |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
7694 adcl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())+4), 0); |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
7695 #endif |
| 304 | 7696 } |
| 7697 | |
| 7698 static const double pi_4 = 0.7853981633974483; | |
| 7699 | |
| 7700 void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) { | |
| 7701 // A hand-coded argument reduction for values in fabs(pi/4, pi/2) | |
| 7702 // was attempted in this code; unfortunately it appears that the | |
| 7703 // switch to 80-bit precision and back causes this to be | |
| 7704 // unprofitable compared with simply performing a runtime call if | |
| 7705 // the argument is out of the (-pi/4, pi/4) range. | |
| 7706 | |
| 7707 Register tmp = noreg; | |
| 7708 if (!VM_Version::supports_cmov()) { | |
| 7709 // fcmp needs a temporary so preserve rbx, | |
| 7710 tmp = rbx; | |
| 7711 push(tmp); | |
| 7712 } | |
| 7713 | |
| 7714 Label slow_case, done; | |
| 7715 | |
|
520
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7716 ExternalAddress pi4_adr = (address)&pi_4; |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7717 if (reachable(pi4_adr)) { |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7718 // x ?<= pi/4 |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7719 fld_d(pi4_adr); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7720 fld_s(1); // Stack: X PI/4 X |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7721 fabs(); // Stack: |X| PI/4 X |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7722 fcmp(tmp); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7723 jcc(Assembler::above, slow_case); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7724 |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7725 // fastest case: -pi/4 <= x <= pi/4 |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7726 switch(trig) { |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7727 case 's': |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7728 fsin(); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7729 break; |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7730 case 'c': |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7731 fcos(); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7732 break; |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7733 case 't': |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7734 ftan(); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7735 break; |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7736 default: |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7737 assert(false, "bad intrinsic"); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7738 break; |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7739 } |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7740 jmp(done); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7741 } |
| 304 | 7742 |
| 7743 // slow case: runtime call | |
| 7744 bind(slow_case); | |
| 7745 // Preserve registers across runtime call | |
| 7746 pusha(); | |
| 7747 int incoming_argument_and_return_value_offset = -1; | |
| 7748 if (num_fpu_regs_in_use > 1) { | |
| 7749 // Must preserve all other FPU regs (could alternatively convert | |
| 7750 // SharedRuntime::dsin and dcos into assembly routines known not to trash | |
| 7751 // FPU state, but can not trust C compiler) | |
| 7752 NEEDS_CLEANUP; | |
| 7753 // NOTE that in this case we also push the incoming argument to | |
| 7754 // the stack and restore it later; we also use this stack slot to | |
| 7755 // hold the return value from dsin or dcos. | |
| 7756 for (int i = 0; i < num_fpu_regs_in_use; i++) { | |
| 7757 subptr(rsp, sizeof(jdouble)); | |
| 7758 fstp_d(Address(rsp, 0)); | |
| 7759 } | |
| 7760 incoming_argument_and_return_value_offset = sizeof(jdouble)*(num_fpu_regs_in_use-1); | |
| 7761 fld_d(Address(rsp, incoming_argument_and_return_value_offset)); | |
| 7762 } | |
| 7763 subptr(rsp, sizeof(jdouble)); | |
| 7764 fstp_d(Address(rsp, 0)); | |
| 7765 #ifdef _LP64 | |
| 7766 movdbl(xmm0, Address(rsp, 0)); | |
| 7767 #endif // _LP64 | |
| 7768 | |
| 7769 // NOTE: we must not use call_VM_leaf here because that requires a | |
| 7770 // complete interpreter frame in debug mode -- same bug as 4387334 | |
| 7771 // MacroAssembler::call_VM_leaf_base is perfectly safe and will | |
| 7772 // do proper 64bit abi | |
| 7773 | |
| 7774 NEEDS_CLEANUP; | |
| 7775 // Need to add stack banging before this runtime call if it needs to | |
| 7776 // be taken; however, there is no generic stack banging routine at | |
| 7777 // the MacroAssembler level | |
| 7778 switch(trig) { | |
| 7779 case 's': | |
| 7780 { | |
| 7781 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), 0); | |
| 7782 } | |
| 7783 break; | |
| 7784 case 'c': | |
| 7785 { | |
| 7786 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), 0); | |
| 7787 } | |
| 7788 break; | |
| 7789 case 't': | |
| 7790 { | |
| 7791 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dtan), 0); | |
| 7792 } | |
| 7793 break; | |
| 7794 default: | |
| 7795 assert(false, "bad intrinsic"); | |
| 7796 break; | |
| 7797 } | |
| 7798 #ifdef _LP64 | |
| 7799 movsd(Address(rsp, 0), xmm0); | |
| 7800 fld_d(Address(rsp, 0)); | |
| 7801 #endif // _LP64 | |
| 7802 addptr(rsp, sizeof(jdouble)); | |
| 7803 if (num_fpu_regs_in_use > 1) { | |
| 7804 // Must save return value to stack and then restore entire FPU stack | |
| 7805 fstp_d(Address(rsp, incoming_argument_and_return_value_offset)); | |
| 7806 for (int i = 0; i < num_fpu_regs_in_use; i++) { | |
| 7807 fld_d(Address(rsp, 0)); | |
| 7808 addptr(rsp, sizeof(jdouble)); | |
| 7809 } | |
| 7810 } | |
| 7811 popa(); | |
| 7812 | |
| 7813 // Come here with result in F-TOS | |
| 7814 bind(done); | |
| 7815 | |
| 7816 if (tmp != noreg) { | |
| 7817 pop(tmp); | |
| 7818 } | |
| 7819 } | |
| 7820 | |
| 7821 | |
|
623
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7822 // Look up the method for a megamorphic invokeinterface call. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7823 // The target method is determined by <intf_klass, itable_index>. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7824 // The receiver klass is in recv_klass. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7825 // On success, the result will be in method_result, and execution falls through. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7826 // On failure, execution transfers to the given label. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7827 void MacroAssembler::lookup_interface_method(Register recv_klass, |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7828 Register intf_klass, |
|
665
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
647
diff
changeset
|
7829 RegisterOrConstant itable_index, |
|
623
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7830 Register method_result, |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7831 Register scan_temp, |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7832 Label& L_no_such_interface) { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7833 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7834 assert(itable_index.is_constant() || itable_index.as_register() == method_result, |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7835 "caller must use same register for non-constant itable index as for method"); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7836 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7837 // Compute start of first itableOffsetEntry (which is at the end of the vtable) |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7838 int vtable_base = instanceKlass::vtable_start_offset() * wordSize; |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7839 int itentry_off = itableMethodEntry::method_offset_in_bytes(); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7840 int scan_step = itableOffsetEntry::size() * wordSize; |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7841 int vte_size = vtableEntry::size() * wordSize; |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7842 Address::ScaleFactor times_vte_scale = Address::times_ptr; |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7843 assert(vte_size == wordSize, "else adjust times_vte_scale"); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7844 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7845 movl(scan_temp, Address(recv_klass, instanceKlass::vtable_length_offset() * wordSize)); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7846 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7847 // %%% Could store the aligned, prescaled offset in the klassoop. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7848 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base)); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7849 if (HeapWordsPerLong > 1) { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7850 // Round up to align_object_offset boundary |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7851 // see code for instanceKlass::start_of_itable! |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7852 round_to(scan_temp, BytesPerLong); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7853 } |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7854 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7855 // Adjust recv_klass by scaled itable_index, so we can free itable_index. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7856 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below"); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7857 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off)); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7858 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7859 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7860 // if (scan->interface() == intf) { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7861 // result = (klass + scan->offset() + itable_index); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7862 // } |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7863 // } |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7864 Label search, found_method; |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7865 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7866 for (int peel = 1; peel >= 0; peel--) { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7867 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes())); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7868 cmpptr(intf_klass, method_result); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7869 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7870 if (peel) { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7871 jccb(Assembler::equal, found_method); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7872 } else { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7873 jccb(Assembler::notEqual, search); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7874 // (invert the test to fall through to found_method...) |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7875 } |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7876 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7877 if (!peel) break; |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7878 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7879 bind(search); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7880 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7881 // Check that the previous entry is non-null. A null entry means that |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7882 // the receiver class doesn't implement the interface, and wasn't the |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7883 // same as when the caller was compiled. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7884 testptr(method_result, method_result); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7885 jcc(Assembler::zero, L_no_such_interface); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7886 addptr(scan_temp, scan_step); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7887 } |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7888 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7889 bind(found_method); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7890 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7891 // Got a hit. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7892 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes())); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7893 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1)); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7894 } |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7895 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7896 |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7897 void MacroAssembler::check_klass_subtype(Register sub_klass, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7898 Register super_klass, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7899 Register temp_reg, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7900 Label& L_success) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7901 Label L_failure; |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7902 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7903 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7904 bind(L_failure); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7905 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7906 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7907 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7908 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7909 Register super_klass, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7910 Register temp_reg, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7911 Label* L_success, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7912 Label* L_failure, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7913 Label* L_slow_path, |
|
665
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
647
diff
changeset
|
7914 RegisterOrConstant super_check_offset) { |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7915 assert_different_registers(sub_klass, super_klass, temp_reg); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7916 bool must_load_sco = (super_check_offset.constant_or_zero() == -1); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7917 if (super_check_offset.is_register()) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7918 assert_different_registers(sub_klass, super_klass, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7919 super_check_offset.as_register()); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7920 } else if (must_load_sco) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7921 assert(temp_reg != noreg, "supply either a temp or a register offset"); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7922 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7923 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7924 Label L_fallthrough; |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7925 int label_nulls = 0; |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7926 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7927 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7928 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7929 assert(label_nulls <= 1, "at most one NULL in the batch"); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7930 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7931 int sc_offset = (klassOopDesc::header_size() * HeapWordSize + |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7932 Klass::secondary_super_cache_offset_in_bytes()); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7933 int sco_offset = (klassOopDesc::header_size() * HeapWordSize + |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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changeset
|
7934 Klass::super_check_offset_offset_in_bytes()); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
7935 Address super_check_offset_addr(super_klass, sco_offset); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7936 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
7937 // Hacked jcc, which "knows" that L_fallthrough, at least, is in |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
7938 // range of a jccb. If this routine grows larger, reconsider at |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7939 // least some of these. |
|
c517646eef23
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643
diff
changeset
|
7940 #define local_jcc(assembler_cond, label) \ |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
7941 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \ |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7942 else jcc( assembler_cond, label) /*omit semi*/ |
|
c517646eef23
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643
diff
changeset
|
7943 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7944 // Hacked jmp, which may only be used just before L_fallthrough. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
7945 #define final_jmp(label) \ |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
7946 if (&(label) == &L_fallthrough) { /*do nothing*/ } \ |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
7947 else jmp(label) /*omit semi*/ |
|
c517646eef23
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643
diff
changeset
|
7948 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
7949 // If the pointers are equal, we are done (e.g., String[] elements). |
|
c517646eef23
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diff
changeset
|
7950 // This self-check enables sharing of secondary supertype arrays among |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7951 // non-primary types such as array-of-interface. Otherwise, each such |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7952 // type would need its own customized SSA. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
7953 // We move this check to the front of the fast path because many |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7954 // type checks are in fact trivially successful in this manner, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7955 // so we get a nicely predicted branch right at the start of the check. |
|
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diff
changeset
|
7956 cmpptr(sub_klass, super_klass); |
|
c517646eef23
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diff
changeset
|
7957 local_jcc(Assembler::equal, *L_success); |
|
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diff
changeset
|
7958 |
|
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
7959 // Check the supertype display: |
|
c517646eef23
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diff
changeset
|
7960 if (must_load_sco) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7961 // Positive movl does right thing on LP64. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
7962 movl(temp_reg, super_check_offset_addr); |
|
665
c89f86385056
6814659: separable cleanups and subroutines for 6655638
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diff
changeset
|
7963 super_check_offset = RegisterOrConstant(temp_reg); |
|
644
c517646eef23
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diff
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|
7964 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7965 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
7966 cmpptr(super_klass, super_check_addr); // load displayed supertype |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7967 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7968 // This check has worked decisively for primary supers. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
7969 // Secondary supers are sought in the super_cache ('super_cache_addr'). |
|
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7970 // (Secondary supers are interfaces and very deeply nested subtypes.) |
|
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643
diff
changeset
|
7971 // This works in the same check above because of a tricky aliasing |
|
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
7972 // between the super_cache and the primary super display elements. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
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|
7973 // (The 'super_check_addr' can address either, as the case requires.) |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7974 // Note that the cache is updated below if it does not help us find |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7975 // what we need immediately. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7976 // So if it was a primary super, we can just fail immediately. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
7977 // Otherwise, it's the slow path for us (no success at this point). |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
7978 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
7979 if (super_check_offset.is_register()) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
7980 local_jcc(Assembler::equal, *L_success); |
|
c517646eef23
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diff
changeset
|
7981 cmpl(super_check_offset.as_register(), sc_offset); |
|
c517646eef23
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|
7982 if (L_failure == &L_fallthrough) { |
|
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diff
changeset
|
7983 local_jcc(Assembler::equal, *L_slow_path); |
|
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diff
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|
7984 } else { |
|
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diff
changeset
|
7985 local_jcc(Assembler::notEqual, *L_failure); |
|
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|
7986 final_jmp(*L_slow_path); |
|
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diff
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|
7987 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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|
7988 } else if (super_check_offset.as_constant() == sc_offset) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
7989 // Need a slow path; fast failure is impossible. |
|
c517646eef23
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|
7990 if (L_slow_path == &L_fallthrough) { |
|
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diff
changeset
|
7991 local_jcc(Assembler::equal, *L_success); |
|
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|
7992 } else { |
|
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|
7993 local_jcc(Assembler::notEqual, *L_slow_path); |
|
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changeset
|
7994 final_jmp(*L_success); |
|
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diff
changeset
|
7995 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
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|
7996 } else { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
7997 // No slow path; it's a fast decision. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
7998 if (L_failure == &L_fallthrough) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
7999 local_jcc(Assembler::equal, *L_success); |
|
c517646eef23
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diff
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|
8000 } else { |
|
c517646eef23
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diff
changeset
|
8001 local_jcc(Assembler::notEqual, *L_failure); |
|
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changeset
|
8002 final_jmp(*L_success); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
8003 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
8004 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
8005 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
8006 bind(L_fallthrough); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
8007 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
8008 #undef local_jcc |
|
c517646eef23
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diff
changeset
|
8009 #undef final_jmp |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
8010 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
8011 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
8012 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
8013 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass, |
|
c517646eef23
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jrose
parents:
643
diff
changeset
|
8014 Register super_klass, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
8015 Register temp_reg, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
8016 Register temp2_reg, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8017 Label* L_success, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8018 Label* L_failure, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
8019 bool set_cond_codes) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
8020 assert_different_registers(sub_klass, super_klass, temp_reg); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
8021 if (temp2_reg != noreg) |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
8022 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
8023 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg) |
|
c517646eef23
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643
diff
changeset
|
8024 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8025 Label L_fallthrough; |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8026 int label_nulls = 0; |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
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643
diff
changeset
|
8027 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8028 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8029 assert(label_nulls <= 1, "at most one NULL in the batch"); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
8030 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8031 // a couple of useful fields in sub_klass: |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8032 int ss_offset = (klassOopDesc::header_size() * HeapWordSize + |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8033 Klass::secondary_supers_offset_in_bytes()); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
8034 int sc_offset = (klassOopDesc::header_size() * HeapWordSize + |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
8035 Klass::secondary_super_cache_offset_in_bytes()); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
8036 Address secondary_supers_addr(sub_klass, ss_offset); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
8037 Address super_cache_addr( sub_klass, sc_offset); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8038 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
8039 // Do a linear scan of the secondary super-klass chain. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
8040 // This code is rarely used, so simplicity is a virtue here. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8041 // The repne_scan instruction uses fixed registers, which we must spill. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
8042 // Don't worry too much about pre-existing connections with the input regs. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8043 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8044 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super) |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8045 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter) |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
8046 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8047 // Get super_klass value into rax (even if it was in rdi or rcx). |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
8048 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false; |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8049 if (super_klass != rax || UseCompressedOops) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8050 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; } |
|
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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changeset
|
8051 mov(rax, super_klass); |
|
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
8052 } |
|
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
8053 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; } |
|
c517646eef23
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643
diff
changeset
|
8054 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; } |
|
c517646eef23
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643
diff
changeset
|
8055 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
8056 #ifndef PRODUCT |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
8057 int* pst_counter = &SharedRuntime::_partial_subtype_ctr; |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
8058 ExternalAddress pst_counter_addr((address) pst_counter); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
8059 NOT_LP64( incrementl(pst_counter_addr) ); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
8060 LP64_ONLY( lea(rcx, pst_counter_addr) ); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
8061 LP64_ONLY( incrementl(Address(rcx, 0)) ); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
8062 #endif //PRODUCT |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
8063 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
8064 // We will consult the secondary-super array. |
|
c517646eef23
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643
diff
changeset
|
8065 movptr(rdi, secondary_supers_addr); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
8066 // Load the array length. (Positive movl does right thing on LP64.) |
|
c517646eef23
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643
diff
changeset
|
8067 movl(rcx, Address(rdi, arrayOopDesc::length_offset_in_bytes())); |
|
c517646eef23
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643
diff
changeset
|
8068 // Skip to start of data. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
8069 addptr(rdi, arrayOopDesc::base_offset_in_bytes(T_OBJECT)); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
8070 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
8071 // Scan RCX words at [RDI] for an occurrence of RAX. |
|
c517646eef23
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diff
changeset
|
8072 // Set NZ/Z based on last compare. |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8073 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8074 // not change flags (only scas instruction which is repeated sets flags). |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8075 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found. |
|
644
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643
diff
changeset
|
8076 #ifdef _LP64 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
8077 // This part is tricky, as values in supers array could be 32 or 64 bit wide |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
8078 // and we store values in objArrays always encoded, thus we need to encode |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8079 // the value of rax before repne. Note that rax is dead after the repne. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8080 if (UseCompressedOops) { |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8081 encode_heap_oop_not_null(rax); // Changes flags. |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8082 // The superclass is never null; it would be a basic system error if a null |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8083 // pointer were to sneak in here. Note that we have already loaded the |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8084 // Klass::super_check_offset from the super_klass in the fast path, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8085 // so if there is a null in that register, we are already in the afterlife. |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8086 testl(rax,rax); // Set Z = 0 |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8087 repne_scanl(); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8088 } else |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8089 #endif // _LP64 |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8090 { |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8091 testptr(rax,rax); // Set Z = 0 |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8092 repne_scan(); |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8093 } |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8094 // Unspill the temp. registers: |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8095 if (pushed_rdi) pop(rdi); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8096 if (pushed_rcx) pop(rcx); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8097 if (pushed_rax) pop(rax); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8098 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8099 if (set_cond_codes) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8100 // Special hack for the AD files: rdi is guaranteed non-zero. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8101 assert(!pushed_rdi, "rdi must be left non-NULL"); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8102 // Also, the condition codes are properly set Z/NZ on succeed/failure. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8103 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8104 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8105 if (L_failure == &L_fallthrough) |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8106 jccb(Assembler::notEqual, *L_failure); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8107 else jcc(Assembler::notEqual, *L_failure); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8108 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8109 // Success. Cache the super we found and proceed in triumph. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8110 movptr(super_cache_addr, super_klass); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8111 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8112 if (L_success != &L_fallthrough) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8113 jmp(*L_success); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8114 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8115 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8116 #undef IS_A_TEMP |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8117 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8118 bind(L_fallthrough); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8119 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8120 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
8121 |
| 304 | 8122 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) { |
| 4759 | 8123 if (reachable(src)) { |
| 8124 Assembler::ucomisd(dst, as_Address(src)); | |
| 8125 } else { | |
| 8126 lea(rscratch1, src); | |
| 8127 Assembler::ucomisd(dst, Address(rscratch1, 0)); | |
| 8128 } | |
| 304 | 8129 } |
| 8130 | |
| 8131 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) { | |
| 4759 | 8132 if (reachable(src)) { |
| 8133 Assembler::ucomiss(dst, as_Address(src)); | |
| 8134 } else { | |
| 8135 lea(rscratch1, src); | |
| 8136 Assembler::ucomiss(dst, Address(rscratch1, 0)); | |
| 8137 } | |
| 304 | 8138 } |
| 8139 | |
| 8140 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) { | |
| 4759 | 8141 // Used in sign-bit flipping with aligned address. |
| 8142 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); | |
| 304 | 8143 if (reachable(src)) { |
| 4759 | 8144 Assembler::xorpd(dst, as_Address(src)); |
| 304 | 8145 } else { |
| 8146 lea(rscratch1, src); | |
| 4759 | 8147 Assembler::xorpd(dst, Address(rscratch1, 0)); |
| 304 | 8148 } |
| 8149 } | |
| 8150 | |
| 8151 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) { | |
| 4759 | 8152 // Used in sign-bit flipping with aligned address. |
| 8153 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); | |
| 304 | 8154 if (reachable(src)) { |
| 4759 | 8155 Assembler::xorps(dst, as_Address(src)); |
| 304 | 8156 } else { |
| 8157 lea(rscratch1, src); | |
| 4759 | 8158 Assembler::xorps(dst, Address(rscratch1, 0)); |
| 304 | 8159 } |
| 8160 } | |
| 8161 | |
|
2415
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
8162 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) { |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
8163 if (VM_Version::supports_cmov()) { |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
8164 cmovl(cc, dst, src); |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
8165 } else { |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
8166 Label L; |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
8167 jccb(negate_condition(cc), L); |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
8168 movl(dst, src); |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
8169 bind(L); |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
8170 } |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
8171 } |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
8172 |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
8173 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) { |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
8174 if (VM_Version::supports_cmov()) { |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
8175 cmovl(cc, dst, src); |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
8176 } else { |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
8177 Label L; |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
8178 jccb(negate_condition(cc), L); |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
8179 movl(dst, src); |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
8180 bind(L); |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
8181 } |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
8182 } |
|
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
8183 |
| 0 | 8184 void MacroAssembler::verify_oop(Register reg, const char* s) { |
| 8185 if (!VerifyOops) return; | |
| 304 | 8186 |
| 0 | 8187 // Pass register number to verify_oop_subroutine |
| 8188 char* b = new char[strlen(s) + 50]; | |
| 8189 sprintf(b, "verify_oop: %s: %s", reg->name(), s); | |
| 1583 | 8190 #ifdef _LP64 |
| 8191 push(rscratch1); // save r10, trashed by movptr() | |
| 8192 #endif | |
| 304 | 8193 push(rax); // save rax, |
| 8194 push(reg); // pass register argument | |
| 0 | 8195 ExternalAddress buffer((address) b); |
| 304 | 8196 // avoid using pushptr, as it modifies scratch registers |
| 8197 // and our contract is not to modify anything | |
| 8198 movptr(rax, buffer.addr()); | |
| 8199 push(rax); | |
| 0 | 8200 // call indirectly to solve generation ordering problem |
| 8201 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); | |
| 8202 call(rax); | |
| 1583 | 8203 // Caller pops the arguments (oop, message) and restores rax, r10 |
| 0 | 8204 } |
| 8205 | |
| 8206 | |
|
665
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
647
diff
changeset
|
8207 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr, |
|
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
647
diff
changeset
|
8208 Register tmp, |
|
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
647
diff
changeset
|
8209 int offset) { |
|
622
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
8210 intptr_t value = *delayed_value_addr; |
|
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
8211 if (value != 0) |
|
665
c89f86385056
6814659: separable cleanups and subroutines for 6655638
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8212 return RegisterOrConstant(value + offset); |
|
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8213 |
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8214 // load indirectly to solve generation ordering problem |
|
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|
8215 movptr(tmp, ExternalAddress((address) delayed_value_addr)); |
|
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8216 |
|
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|
8217 #ifdef ASSERT |
|
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8218 { Label L; |
|
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|
8219 testptr(tmp, tmp); |
|
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8220 if (WizardMode) { |
|
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8221 jcc(Assembler::notZero, L); |
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8222 char* buf = new char[40]; |
|
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8223 sprintf(buf, "DelayedValue="INTPTR_FORMAT, delayed_value_addr[1]); |
|
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8224 stop(buf); |
|
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|
8225 } else { |
|
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|
8226 jccb(Assembler::notZero, L); |
|
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8227 hlt(); |
|
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|
8228 } |
|
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|
8229 bind(L); |
|
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|
8230 } |
|
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8231 #endif |
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8232 |
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8233 if (offset != 0) |
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8234 addptr(tmp, offset); |
|
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|
8235 |
|
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8236 return RegisterOrConstant(tmp); |
|
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8237 } |
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8238 |
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|
8239 |
| 710 | 8240 // registers on entry: |
| 8241 // - rax ('check' register): required MethodType | |
| 8242 // - rcx: method handle | |
| 8243 // - rdx, rsi, or ?: killable temp | |
| 8244 void MacroAssembler::check_method_handle_type(Register mtype_reg, Register mh_reg, | |
| 8245 Register temp_reg, | |
| 8246 Label& wrong_method_type) { | |
|
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|
8247 Address type_addr(mh_reg, delayed_value(java_lang_invoke_MethodHandle::type_offset_in_bytes, temp_reg)); |
| 710 | 8248 // compare method type against that of the receiver |
| 1846 | 8249 if (UseCompressedOops) { |
| 8250 load_heap_oop(temp_reg, type_addr); | |
| 8251 cmpptr(mtype_reg, temp_reg); | |
| 8252 } else { | |
| 8253 cmpptr(mtype_reg, type_addr); | |
| 8254 } | |
| 710 | 8255 jcc(Assembler::notEqual, wrong_method_type); |
| 8256 } | |
| 8257 | |
| 8258 | |
| 8259 // A method handle has a "vmslots" field which gives the size of its | |
| 8260 // argument list in JVM stack slots. This field is either located directly | |
| 8261 // in every method handle, or else is indirectly accessed through the | |
| 8262 // method handle's MethodType. This macro hides the distinction. | |
| 8263 void MacroAssembler::load_method_handle_vmslots(Register vmslots_reg, Register mh_reg, | |
| 8264 Register temp_reg) { | |
| 1503 | 8265 assert_different_registers(vmslots_reg, mh_reg, temp_reg); |
| 710 | 8266 // load mh.type.form.vmslots |
| 3938 | 8267 Register temp2_reg = vmslots_reg; |
| 8268 load_heap_oop(temp2_reg, Address(mh_reg, delayed_value(java_lang_invoke_MethodHandle::type_offset_in_bytes, temp_reg))); | |
| 8269 load_heap_oop(temp2_reg, Address(temp2_reg, delayed_value(java_lang_invoke_MethodType::form_offset_in_bytes, temp_reg))); | |
| 8270 movl(vmslots_reg, Address(temp2_reg, delayed_value(java_lang_invoke_MethodTypeForm::vmslots_offset_in_bytes, temp_reg))); | |
| 710 | 8271 } |
| 8272 | |
| 8273 | |
| 8274 // registers on entry: | |
| 8275 // - rcx: method handle | |
| 8276 // - rdx: killable temp (interpreted only) | |
| 8277 // - rax: killable temp (compiled only) | |
| 8278 void MacroAssembler::jump_to_method_handle_entry(Register mh_reg, Register temp_reg) { | |
| 8279 assert(mh_reg == rcx, "caller must put MH object in rcx"); | |
| 8280 assert_different_registers(mh_reg, temp_reg); | |
| 8281 | |
| 8282 // pick out the interpreted side of the handler | |
| 1846 | 8283 // NOTE: vmentry is not an oop! |
|
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|
8284 movptr(temp_reg, Address(mh_reg, delayed_value(java_lang_invoke_MethodHandle::vmentry_offset_in_bytes, temp_reg))); |
| 710 | 8285 |
| 8286 // off we go... | |
| 8287 jmp(Address(temp_reg, MethodHandleEntry::from_interpreted_entry_offset_in_bytes())); | |
| 8288 | |
| 8289 // for the various stubs which take control at this point, | |
| 8290 // see MethodHandles::generate_method_handle_stub | |
| 8291 } | |
| 8292 | |
| 8293 | |
| 8294 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot, | |
| 8295 int extra_slot_offset) { | |
| 8296 // cf. TemplateTable::prepare_invoke(), if (load_receiver). | |
| 1506 | 8297 int stackElementSize = Interpreter::stackElementSize; |
| 710 | 8298 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0); |
| 8299 #ifdef ASSERT | |
| 8300 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1); | |
| 8301 assert(offset1 - offset == stackElementSize, "correct arithmetic"); | |
| 8302 #endif | |
| 8303 Register scale_reg = noreg; | |
| 8304 Address::ScaleFactor scale_factor = Address::no_scale; | |
| 8305 if (arg_slot.is_constant()) { | |
| 8306 offset += arg_slot.as_constant() * stackElementSize; | |
| 8307 } else { | |
| 8308 scale_reg = arg_slot.as_register(); | |
| 8309 scale_factor = Address::times(stackElementSize); | |
| 8310 } | |
| 8311 offset += wordSize; // return PC is on stack | |
| 8312 return Address(rsp, scale_reg, scale_factor, offset); | |
| 8313 } | |
| 8314 | |
| 8315 | |
| 0 | 8316 void MacroAssembler::verify_oop_addr(Address addr, const char* s) { |
| 8317 if (!VerifyOops) return; | |
| 304 | 8318 |
| 0 | 8319 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord); |
| 8320 // Pass register number to verify_oop_subroutine | |
| 8321 char* b = new char[strlen(s) + 50]; | |
| 8322 sprintf(b, "verify_oop_addr: %s", s); | |
| 304 | 8323 |
| 1583 | 8324 #ifdef _LP64 |
| 8325 push(rscratch1); // save r10, trashed by movptr() | |
| 8326 #endif | |
| 304 | 8327 push(rax); // save rax, |
| 0 | 8328 // addr may contain rsp so we will have to adjust it based on the push |
|
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diff
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|
8329 // we just did (and on 64 bit we do two pushes) |
| 304 | 8330 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which |
| 8331 // stores rax into addr which is backwards of what was intended. | |
| 0 | 8332 if (addr.uses(rsp)) { |
| 304 | 8333 lea(rax, addr); |
|
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|
8334 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord)); |
| 0 | 8335 } else { |
| 304 | 8336 pushptr(addr); |
| 8337 } | |
| 8338 | |
| 0 | 8339 ExternalAddress buffer((address) b); |
| 8340 // pass msg argument | |
| 304 | 8341 // avoid using pushptr, as it modifies scratch registers |
| 8342 // and our contract is not to modify anything | |
| 8343 movptr(rax, buffer.addr()); | |
| 8344 push(rax); | |
| 8345 | |
| 0 | 8346 // call indirectly to solve generation ordering problem |
| 8347 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); | |
| 8348 call(rax); | |
| 1583 | 8349 // Caller pops the arguments (addr, message) and restores rax, r10. |
| 0 | 8350 } |
| 8351 | |
| 304 | 8352 void MacroAssembler::verify_tlab() { |
| 8353 #ifdef ASSERT | |
| 8354 if (UseTLAB && VerifyOops) { | |
| 8355 Label next, ok; | |
| 8356 Register t1 = rsi; | |
| 8357 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread); | |
| 8358 | |
| 8359 push(t1); | |
| 8360 NOT_LP64(push(thread_reg)); | |
| 8361 NOT_LP64(get_thread(thread_reg)); | |
| 8362 | |
| 8363 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); | |
| 8364 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); | |
| 8365 jcc(Assembler::aboveEqual, next); | |
| 8366 stop("assert(top >= start)"); | |
| 8367 should_not_reach_here(); | |
| 8368 | |
| 8369 bind(next); | |
| 8370 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); | |
| 8371 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); | |
| 8372 jcc(Assembler::aboveEqual, ok); | |
| 8373 stop("assert(top <= end)"); | |
| 8374 should_not_reach_here(); | |
| 8375 | |
| 8376 bind(ok); | |
| 8377 NOT_LP64(pop(thread_reg)); | |
| 8378 pop(t1); | |
| 8379 } | |
| 8380 #endif | |
| 8381 } | |
| 0 | 8382 |
| 8383 class ControlWord { | |
| 8384 public: | |
| 8385 int32_t _value; | |
| 8386 | |
| 8387 int rounding_control() const { return (_value >> 10) & 3 ; } | |
| 8388 int precision_control() const { return (_value >> 8) & 3 ; } | |
| 8389 bool precision() const { return ((_value >> 5) & 1) != 0; } | |
| 8390 bool underflow() const { return ((_value >> 4) & 1) != 0; } | |
| 8391 bool overflow() const { return ((_value >> 3) & 1) != 0; } | |
| 8392 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } | |
| 8393 bool denormalized() const { return ((_value >> 1) & 1) != 0; } | |
| 8394 bool invalid() const { return ((_value >> 0) & 1) != 0; } | |
| 8395 | |
| 8396 void print() const { | |
| 8397 // rounding control | |
| 8398 const char* rc; | |
| 8399 switch (rounding_control()) { | |
| 8400 case 0: rc = "round near"; break; | |
| 8401 case 1: rc = "round down"; break; | |
| 8402 case 2: rc = "round up "; break; | |
| 8403 case 3: rc = "chop "; break; | |
| 8404 }; | |
| 8405 // precision control | |
| 8406 const char* pc; | |
| 8407 switch (precision_control()) { | |
| 8408 case 0: pc = "24 bits "; break; | |
| 8409 case 1: pc = "reserved"; break; | |
| 8410 case 2: pc = "53 bits "; break; | |
| 8411 case 3: pc = "64 bits "; break; | |
| 8412 }; | |
| 8413 // flags | |
| 8414 char f[9]; | |
| 8415 f[0] = ' '; | |
| 8416 f[1] = ' '; | |
| 8417 f[2] = (precision ()) ? 'P' : 'p'; | |
| 8418 f[3] = (underflow ()) ? 'U' : 'u'; | |
| 8419 f[4] = (overflow ()) ? 'O' : 'o'; | |
| 8420 f[5] = (zero_divide ()) ? 'Z' : 'z'; | |
| 8421 f[6] = (denormalized()) ? 'D' : 'd'; | |
| 8422 f[7] = (invalid ()) ? 'I' : 'i'; | |
| 8423 f[8] = '\x0'; | |
| 8424 // output | |
| 8425 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc); | |
| 8426 } | |
| 8427 | |
| 8428 }; | |
| 8429 | |
| 8430 class StatusWord { | |
| 8431 public: | |
| 8432 int32_t _value; | |
| 8433 | |
| 8434 bool busy() const { return ((_value >> 15) & 1) != 0; } | |
| 8435 bool C3() const { return ((_value >> 14) & 1) != 0; } | |
| 8436 bool C2() const { return ((_value >> 10) & 1) != 0; } | |
| 8437 bool C1() const { return ((_value >> 9) & 1) != 0; } | |
| 8438 bool C0() const { return ((_value >> 8) & 1) != 0; } | |
| 8439 int top() const { return (_value >> 11) & 7 ; } | |
| 8440 bool error_status() const { return ((_value >> 7) & 1) != 0; } | |
| 8441 bool stack_fault() const { return ((_value >> 6) & 1) != 0; } | |
| 8442 bool precision() const { return ((_value >> 5) & 1) != 0; } | |
| 8443 bool underflow() const { return ((_value >> 4) & 1) != 0; } | |
| 8444 bool overflow() const { return ((_value >> 3) & 1) != 0; } | |
| 8445 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } | |
| 8446 bool denormalized() const { return ((_value >> 1) & 1) != 0; } | |
| 8447 bool invalid() const { return ((_value >> 0) & 1) != 0; } | |
| 8448 | |
| 8449 void print() const { | |
| 8450 // condition codes | |
| 8451 char c[5]; | |
| 8452 c[0] = (C3()) ? '3' : '-'; | |
| 8453 c[1] = (C2()) ? '2' : '-'; | |
| 8454 c[2] = (C1()) ? '1' : '-'; | |
| 8455 c[3] = (C0()) ? '0' : '-'; | |
| 8456 c[4] = '\x0'; | |
| 8457 // flags | |
| 8458 char f[9]; | |
| 8459 f[0] = (error_status()) ? 'E' : '-'; | |
| 8460 f[1] = (stack_fault ()) ? 'S' : '-'; | |
| 8461 f[2] = (precision ()) ? 'P' : '-'; | |
| 8462 f[3] = (underflow ()) ? 'U' : '-'; | |
| 8463 f[4] = (overflow ()) ? 'O' : '-'; | |
| 8464 f[5] = (zero_divide ()) ? 'Z' : '-'; | |
| 8465 f[6] = (denormalized()) ? 'D' : '-'; | |
| 8466 f[7] = (invalid ()) ? 'I' : '-'; | |
| 8467 f[8] = '\x0'; | |
| 8468 // output | |
| 8469 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top()); | |
| 8470 } | |
| 8471 | |
| 8472 }; | |
| 8473 | |
| 8474 class TagWord { | |
| 8475 public: | |
| 8476 int32_t _value; | |
| 8477 | |
| 8478 int tag_at(int i) const { return (_value >> (i*2)) & 3; } | |
| 8479 | |
| 8480 void print() const { | |
| 8481 printf("%04x", _value & 0xFFFF); | |
| 8482 } | |
| 8483 | |
| 8484 }; | |
| 8485 | |
| 8486 class FPU_Register { | |
| 8487 public: | |
| 8488 int32_t _m0; | |
| 8489 int32_t _m1; | |
| 8490 int16_t _ex; | |
| 8491 | |
| 8492 bool is_indefinite() const { | |
| 8493 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0; | |
| 8494 } | |
| 8495 | |
| 8496 void print() const { | |
| 8497 char sign = (_ex < 0) ? '-' : '+'; | |
| 8498 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " "; | |
| 8499 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind); | |
| 8500 }; | |
| 8501 | |
| 8502 }; | |
| 8503 | |
| 8504 class FPU_State { | |
| 8505 public: | |
| 8506 enum { | |
| 8507 register_size = 10, | |
| 8508 number_of_registers = 8, | |
| 8509 register_mask = 7 | |
| 8510 }; | |
| 8511 | |
| 8512 ControlWord _control_word; | |
| 8513 StatusWord _status_word; | |
| 8514 TagWord _tag_word; | |
| 8515 int32_t _error_offset; | |
| 8516 int32_t _error_selector; | |
| 8517 int32_t _data_offset; | |
| 8518 int32_t _data_selector; | |
| 8519 int8_t _register[register_size * number_of_registers]; | |
| 8520 | |
| 8521 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); } | |
| 8522 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; } | |
| 8523 | |
| 8524 const char* tag_as_string(int tag) const { | |
| 8525 switch (tag) { | |
| 8526 case 0: return "valid"; | |
| 8527 case 1: return "zero"; | |
| 8528 case 2: return "special"; | |
| 8529 case 3: return "empty"; | |
| 8530 } | |
|
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diff
changeset
|
8531 ShouldNotReachHere(); |
| 0 | 8532 return NULL; |
| 8533 } | |
| 8534 | |
| 8535 void print() const { | |
| 8536 // print computation registers | |
| 8537 { int t = _status_word.top(); | |
| 8538 for (int i = 0; i < number_of_registers; i++) { | |
| 8539 int j = (i - t) & register_mask; | |
| 8540 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j); | |
| 8541 st(j)->print(); | |
| 8542 printf(" %s\n", tag_as_string(_tag_word.tag_at(i))); | |
| 8543 } | |
| 8544 } | |
| 8545 printf("\n"); | |
| 8546 // print control registers | |
| 8547 printf("ctrl = "); _control_word.print(); printf("\n"); | |
| 8548 printf("stat = "); _status_word .print(); printf("\n"); | |
| 8549 printf("tags = "); _tag_word .print(); printf("\n"); | |
| 8550 } | |
| 8551 | |
| 8552 }; | |
| 8553 | |
| 8554 class Flag_Register { | |
| 8555 public: | |
| 8556 int32_t _value; | |
| 8557 | |
| 8558 bool overflow() const { return ((_value >> 11) & 1) != 0; } | |
| 8559 bool direction() const { return ((_value >> 10) & 1) != 0; } | |
| 8560 bool sign() const { return ((_value >> 7) & 1) != 0; } | |
| 8561 bool zero() const { return ((_value >> 6) & 1) != 0; } | |
| 8562 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; } | |
| 8563 bool parity() const { return ((_value >> 2) & 1) != 0; } | |
| 8564 bool carry() const { return ((_value >> 0) & 1) != 0; } | |
| 8565 | |
| 8566 void print() const { | |
| 8567 // flags | |
| 8568 char f[8]; | |
| 8569 f[0] = (overflow ()) ? 'O' : '-'; | |
| 8570 f[1] = (direction ()) ? 'D' : '-'; | |
| 8571 f[2] = (sign ()) ? 'S' : '-'; | |
| 8572 f[3] = (zero ()) ? 'Z' : '-'; | |
| 8573 f[4] = (auxiliary_carry()) ? 'A' : '-'; | |
| 8574 f[5] = (parity ()) ? 'P' : '-'; | |
| 8575 f[6] = (carry ()) ? 'C' : '-'; | |
| 8576 f[7] = '\x0'; | |
| 8577 // output | |
| 8578 printf("%08x flags = %s", _value, f); | |
| 8579 } | |
| 8580 | |
| 8581 }; | |
| 8582 | |
| 8583 class IU_Register { | |
| 8584 public: | |
| 8585 int32_t _value; | |
| 8586 | |
| 8587 void print() const { | |
| 8588 printf("%08x %11d", _value, _value); | |
| 8589 } | |
| 8590 | |
| 8591 }; | |
| 8592 | |
| 8593 class IU_State { | |
| 8594 public: | |
| 8595 Flag_Register _eflags; | |
| 8596 IU_Register _rdi; | |
| 8597 IU_Register _rsi; | |
| 8598 IU_Register _rbp; | |
| 8599 IU_Register _rsp; | |
| 8600 IU_Register _rbx; | |
| 8601 IU_Register _rdx; | |
| 8602 IU_Register _rcx; | |
| 8603 IU_Register _rax; | |
| 8604 | |
| 8605 void print() const { | |
| 8606 // computation registers | |
| 8607 printf("rax, = "); _rax.print(); printf("\n"); | |
| 8608 printf("rbx, = "); _rbx.print(); printf("\n"); | |
| 8609 printf("rcx = "); _rcx.print(); printf("\n"); | |
| 8610 printf("rdx = "); _rdx.print(); printf("\n"); | |
| 8611 printf("rdi = "); _rdi.print(); printf("\n"); | |
| 8612 printf("rsi = "); _rsi.print(); printf("\n"); | |
| 8613 printf("rbp, = "); _rbp.print(); printf("\n"); | |
| 8614 printf("rsp = "); _rsp.print(); printf("\n"); | |
| 8615 printf("\n"); | |
| 8616 // control registers | |
| 8617 printf("flgs = "); _eflags.print(); printf("\n"); | |
| 8618 } | |
| 8619 }; | |
| 8620 | |
| 8621 | |
| 8622 class CPU_State { | |
| 8623 public: | |
| 8624 FPU_State _fpu_state; | |
| 8625 IU_State _iu_state; | |
| 8626 | |
| 8627 void print() const { | |
| 8628 printf("--------------------------------------------------\n"); | |
| 8629 _iu_state .print(); | |
| 8630 printf("\n"); | |
| 8631 _fpu_state.print(); | |
| 8632 printf("--------------------------------------------------\n"); | |
| 8633 } | |
| 8634 | |
| 8635 }; | |
| 8636 | |
| 8637 | |
| 8638 static void _print_CPU_state(CPU_State* state) { | |
| 8639 state->print(); | |
| 8640 }; | |
| 8641 | |
| 8642 | |
| 8643 void MacroAssembler::print_CPU_state() { | |
| 8644 push_CPU_state(); | |
| 304 | 8645 push(rsp); // pass CPU state |
| 0 | 8646 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state))); |
| 304 | 8647 addptr(rsp, wordSize); // discard argument |
| 0 | 8648 pop_CPU_state(); |
| 8649 } | |
| 8650 | |
| 8651 | |
| 8652 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) { | |
| 8653 static int counter = 0; | |
| 8654 FPU_State* fs = &state->_fpu_state; | |
| 8655 counter++; | |
| 8656 // For leaf calls, only verify that the top few elements remain empty. | |
| 8657 // We only need 1 empty at the top for C2 code. | |
| 8658 if( stack_depth < 0 ) { | |
| 8659 if( fs->tag_for_st(7) != 3 ) { | |
| 8660 printf("FPR7 not empty\n"); | |
| 8661 state->print(); | |
| 8662 assert(false, "error"); | |
| 8663 return false; | |
| 8664 } | |
| 8665 return true; // All other stack states do not matter | |
| 8666 } | |
| 8667 | |
| 8668 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std, | |
| 8669 "bad FPU control word"); | |
| 8670 | |
| 8671 // compute stack depth | |
| 8672 int i = 0; | |
| 8673 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++; | |
| 8674 int d = i; | |
| 8675 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++; | |
| 8676 // verify findings | |
| 8677 if (i != FPU_State::number_of_registers) { | |
| 8678 // stack not contiguous | |
| 8679 printf("%s: stack not contiguous at ST%d\n", s, i); | |
| 8680 state->print(); | |
| 8681 assert(false, "error"); | |
| 8682 return false; | |
| 8683 } | |
| 8684 // check if computed stack depth corresponds to expected stack depth | |
| 8685 if (stack_depth < 0) { | |
| 8686 // expected stack depth is -stack_depth or less | |
| 8687 if (d > -stack_depth) { | |
| 8688 // too many elements on the stack | |
| 8689 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d); | |
| 8690 state->print(); | |
| 8691 assert(false, "error"); | |
| 8692 return false; | |
| 8693 } | |
| 8694 } else { | |
| 8695 // expected stack depth is stack_depth | |
| 8696 if (d != stack_depth) { | |
| 8697 // wrong stack depth | |
| 8698 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d); | |
| 8699 state->print(); | |
| 8700 assert(false, "error"); | |
| 8701 return false; | |
| 8702 } | |
| 8703 } | |
| 8704 // everything is cool | |
| 8705 return true; | |
| 8706 } | |
| 8707 | |
| 8708 | |
| 8709 void MacroAssembler::verify_FPU(int stack_depth, const char* s) { | |
| 8710 if (!VerifyFPU) return; | |
| 8711 push_CPU_state(); | |
| 304 | 8712 push(rsp); // pass CPU state |
| 0 | 8713 ExternalAddress msg((address) s); |
| 8714 // pass message string s | |
| 8715 pushptr(msg.addr()); | |
| 304 | 8716 push(stack_depth); // pass stack depth |
| 0 | 8717 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU))); |
| 304 | 8718 addptr(rsp, 3 * wordSize); // discard arguments |
| 0 | 8719 // check for error |
| 8720 { Label L; | |
| 8721 testl(rax, rax); | |
| 8722 jcc(Assembler::notZero, L); | |
| 8723 int3(); // break if error condition | |
| 8724 bind(L); | |
| 8725 } | |
| 8726 pop_CPU_state(); | |
| 8727 } | |
| 8728 | |
| 304 | 8729 void MacroAssembler::load_klass(Register dst, Register src) { |
| 8730 #ifdef _LP64 | |
| 8731 if (UseCompressedOops) { | |
| 8732 movl(dst, Address(src, oopDesc::klass_offset_in_bytes())); | |
| 8733 decode_heap_oop_not_null(dst); | |
| 8734 } else | |
| 8735 #endif | |
| 8736 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes())); | |
| 8737 } | |
| 8738 | |
| 8739 void MacroAssembler::load_prototype_header(Register dst, Register src) { | |
| 8740 #ifdef _LP64 | |
| 8741 if (UseCompressedOops) { | |
|
642
660978a2a31a
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|
8742 assert (Universe::heap() != NULL, "java heap should be initialized"); |
| 304 | 8743 movl(dst, Address(src, oopDesc::klass_offset_in_bytes())); |
|
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|
8744 if (Universe::narrow_oop_shift() != 0) { |
|
1571
2d127394260e
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1513
diff
changeset
|
8745 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
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diff
changeset
|
8746 if (LogMinObjAlignmentInBytes == Address::times_8) { |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
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parents:
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diff
changeset
|
8747 movq(dst, Address(r12_heapbase, dst, Address::times_8, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
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changeset
|
8748 } else { |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
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parents:
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diff
changeset
|
8749 // OK to use shift since we don't need to preserve flags. |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8750 shlq(dst, LogMinObjAlignmentInBytes); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8751 movq(dst, Address(r12_heapbase, dst, Address::times_1, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); |
|
2d127394260e
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changeset
|
8752 } |
|
642
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changeset
|
8753 } else { |
|
660978a2a31a
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diff
changeset
|
8754 movq(dst, Address(dst, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); |
|
660978a2a31a
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|
8755 } |
| 304 | 8756 } else |
| 8757 #endif | |
|
642
660978a2a31a
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changeset
|
8758 { |
|
660978a2a31a
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changeset
|
8759 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes())); |
|
660978a2a31a
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624
diff
changeset
|
8760 movptr(dst, Address(dst, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); |
|
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|
8761 } |
| 304 | 8762 } |
| 8763 | |
| 8764 void MacroAssembler::store_klass(Register dst, Register src) { | |
| 8765 #ifdef _LP64 | |
| 8766 if (UseCompressedOops) { | |
| 8767 encode_heap_oop_not_null(src); | |
| 8768 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src); | |
| 8769 } else | |
| 8770 #endif | |
| 8771 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src); | |
| 8772 } | |
| 8773 | |
| 1846 | 8774 void MacroAssembler::load_heap_oop(Register dst, Address src) { |
| 8775 #ifdef _LP64 | |
| 8776 if (UseCompressedOops) { | |
| 8777 movl(dst, src); | |
| 8778 decode_heap_oop(dst); | |
| 8779 } else | |
| 8780 #endif | |
| 8781 movptr(dst, src); | |
| 8782 } | |
| 8783 | |
|
2464
d86923d96dca
7034967: C1: assert(false) failed: error (assembler_sparc.cpp:2043)
iveresov
parents:
2415
diff
changeset
|
8784 // Doesn't do verfication, generates fixed size code |
|
d86923d96dca
7034967: C1: assert(false) failed: error (assembler_sparc.cpp:2043)
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diff
changeset
|
8785 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) { |
|
d86923d96dca
7034967: C1: assert(false) failed: error (assembler_sparc.cpp:2043)
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diff
changeset
|
8786 #ifdef _LP64 |
|
d86923d96dca
7034967: C1: assert(false) failed: error (assembler_sparc.cpp:2043)
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diff
changeset
|
8787 if (UseCompressedOops) { |
|
d86923d96dca
7034967: C1: assert(false) failed: error (assembler_sparc.cpp:2043)
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diff
changeset
|
8788 movl(dst, src); |
|
d86923d96dca
7034967: C1: assert(false) failed: error (assembler_sparc.cpp:2043)
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diff
changeset
|
8789 decode_heap_oop_not_null(dst); |
|
d86923d96dca
7034967: C1: assert(false) failed: error (assembler_sparc.cpp:2043)
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diff
changeset
|
8790 } else |
|
d86923d96dca
7034967: C1: assert(false) failed: error (assembler_sparc.cpp:2043)
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diff
changeset
|
8791 #endif |
|
d86923d96dca
7034967: C1: assert(false) failed: error (assembler_sparc.cpp:2043)
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parents:
2415
diff
changeset
|
8792 movptr(dst, src); |
|
d86923d96dca
7034967: C1: assert(false) failed: error (assembler_sparc.cpp:2043)
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|
8793 } |
|
d86923d96dca
7034967: C1: assert(false) failed: error (assembler_sparc.cpp:2043)
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|
8794 |
| 1846 | 8795 void MacroAssembler::store_heap_oop(Address dst, Register src) { |
| 8796 #ifdef _LP64 | |
| 8797 if (UseCompressedOops) { | |
| 8798 assert(!dst.uses(src), "not enough registers"); | |
| 8799 encode_heap_oop(src); | |
| 8800 movl(dst, src); | |
| 8801 } else | |
| 8802 #endif | |
| 8803 movptr(dst, src); | |
| 8804 } | |
| 8805 | |
| 8806 // Used for storing NULLs. | |
| 8807 void MacroAssembler::store_heap_oop_null(Address dst) { | |
| 8808 #ifdef _LP64 | |
| 8809 if (UseCompressedOops) { | |
| 8810 movl(dst, (int32_t)NULL_WORD); | |
| 8811 } else { | |
| 8812 movslq(dst, (int32_t)NULL_WORD); | |
| 8813 } | |
| 8814 #else | |
| 8815 movl(dst, (int32_t)NULL_WORD); | |
| 8816 #endif | |
| 8817 } | |
| 8818 | |
| 304 | 8819 #ifdef _LP64 |
| 8820 void MacroAssembler::store_klass_gap(Register dst, Register src) { | |
| 8821 if (UseCompressedOops) { | |
| 8822 // Store to klass gap in destination | |
| 8823 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src); | |
| 8824 } | |
| 8825 } | |
| 8826 | |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
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diff
changeset
|
8827 #ifdef ASSERT |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
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parents:
1583
diff
changeset
|
8828 void MacroAssembler::verify_heapbase(const char* msg) { |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
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parents:
1583
diff
changeset
|
8829 assert (UseCompressedOops, "should be compressed"); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
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parents:
1583
diff
changeset
|
8830 assert (Universe::heap() != NULL, "java heap should be initialized"); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
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parents:
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diff
changeset
|
8831 if (CheckCompressedOops) { |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
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parents:
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diff
changeset
|
8832 Label ok; |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
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parents:
1583
diff
changeset
|
8833 push(rscratch1); // cmpptr trashes rscratch1 |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
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parents:
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diff
changeset
|
8834 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_oop_base_addr())); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
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1583
diff
changeset
|
8835 jcc(Assembler::equal, ok); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
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diff
changeset
|
8836 stop(msg); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
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parents:
1583
diff
changeset
|
8837 bind(ok); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
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parents:
1583
diff
changeset
|
8838 pop(rscratch1); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
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parents:
1583
diff
changeset
|
8839 } |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
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parents:
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diff
changeset
|
8840 } |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
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parents:
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diff
changeset
|
8841 #endif |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
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diff
changeset
|
8842 |
| 304 | 8843 // Algorithm must match oop.inline.hpp encode_heap_oop. |
| 8844 void MacroAssembler::encode_heap_oop(Register r) { | |
|
1684
66c5dadb4d61
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parents:
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diff
changeset
|
8845 #ifdef ASSERT |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
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parents:
1583
diff
changeset
|
8846 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?"); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
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diff
changeset
|
8847 #endif |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
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parents:
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diff
changeset
|
8848 verify_oop(r, "broken oop in encode_heap_oop"); |
|
642
660978a2a31a
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changeset
|
8849 if (Universe::narrow_oop_base() == NULL) { |
|
660978a2a31a
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changeset
|
8850 if (Universe::narrow_oop_shift() != 0) { |
|
660978a2a31a
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diff
changeset
|
8851 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
|
660978a2a31a
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diff
changeset
|
8852 shrq(r, LogMinObjAlignmentInBytes); |
|
660978a2a31a
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|
8853 } |
|
660978a2a31a
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diff
changeset
|
8854 return; |
|
660978a2a31a
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diff
changeset
|
8855 } |
| 304 | 8856 testq(r, r); |
| 8857 cmovq(Assembler::equal, r, r12_heapbase); | |
| 8858 subq(r, r12_heapbase); | |
| 8859 shrq(r, LogMinObjAlignmentInBytes); | |
| 8860 } | |
| 8861 | |
| 8862 void MacroAssembler::encode_heap_oop_not_null(Register r) { | |
| 0 | 8863 #ifdef ASSERT |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
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diff
changeset
|
8864 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?"); |
| 304 | 8865 if (CheckCompressedOops) { |
| 0 | 8866 Label ok; |
| 304 | 8867 testq(r, r); |
| 8868 jcc(Assembler::notEqual, ok); | |
| 8869 stop("null oop passed to encode_heap_oop_not_null"); | |
| 0 | 8870 bind(ok); |
| 304 | 8871 } |
| 8872 #endif | |
| 8873 verify_oop(r, "broken oop in encode_heap_oop_not_null"); | |
|
642
660978a2a31a
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diff
changeset
|
8874 if (Universe::narrow_oop_base() != NULL) { |
|
660978a2a31a
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624
diff
changeset
|
8875 subq(r, r12_heapbase); |
|
660978a2a31a
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624
diff
changeset
|
8876 } |
|
660978a2a31a
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diff
changeset
|
8877 if (Universe::narrow_oop_shift() != 0) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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diff
changeset
|
8878 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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changeset
|
8879 shrq(r, LogMinObjAlignmentInBytes); |
|
660978a2a31a
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changeset
|
8880 } |
| 304 | 8881 } |
| 8882 | |
| 8883 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) { | |
| 8884 #ifdef ASSERT | |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8885 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?"); |
| 304 | 8886 if (CheckCompressedOops) { |
| 8887 Label ok; | |
| 8888 testq(src, src); | |
| 8889 jcc(Assembler::notEqual, ok); | |
| 8890 stop("null oop passed to encode_heap_oop_not_null2"); | |
| 8891 bind(ok); | |
| 0 | 8892 } |
| 8893 #endif | |
| 304 | 8894 verify_oop(src, "broken oop in encode_heap_oop_not_null2"); |
| 8895 if (dst != src) { | |
| 8896 movq(dst, src); | |
| 8897 } | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8898 if (Universe::narrow_oop_base() != NULL) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8899 subq(dst, r12_heapbase); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8900 } |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8901 if (Universe::narrow_oop_shift() != 0) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8902 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8903 shrq(dst, LogMinObjAlignmentInBytes); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8904 } |
| 304 | 8905 } |
| 8906 | |
| 8907 void MacroAssembler::decode_heap_oop(Register r) { | |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8908 #ifdef ASSERT |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8909 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?"); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8910 #endif |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8911 if (Universe::narrow_oop_base() == NULL) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8912 if (Universe::narrow_oop_shift() != 0) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8913 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8914 shlq(r, LogMinObjAlignmentInBytes); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8915 } |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8916 } else { |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8917 Label done; |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8918 shlq(r, LogMinObjAlignmentInBytes); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8919 jccb(Assembler::equal, done); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8920 addq(r, r12_heapbase); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8921 bind(done); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8922 } |
| 304 | 8923 verify_oop(r, "broken oop in decode_heap_oop"); |
| 8924 } | |
| 8925 | |
| 8926 void MacroAssembler::decode_heap_oop_not_null(Register r) { | |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8927 // Note: it will change flags |
| 304 | 8928 assert (UseCompressedOops, "should only be used for compressed headers"); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8929 assert (Universe::heap() != NULL, "java heap should be initialized"); |
| 304 | 8930 // Cannot assert, unverified entry point counts instructions (see .ad file) |
| 8931 // vtableStubs also counts instructions in pd_code_size_limit. | |
| 8932 // Also do not verify_oop as this is called by verify_oop. | |
|
898
60fea60a6db5
6864914: SPECjvm2008 produces invalid result with zero based Compressed Oops
kvn
parents:
845
diff
changeset
|
8933 if (Universe::narrow_oop_shift() != 0) { |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8934 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8935 shlq(r, LogMinObjAlignmentInBytes); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8936 if (Universe::narrow_oop_base() != NULL) { |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8937 addq(r, r12_heapbase); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8938 } |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8939 } else { |
|
898
60fea60a6db5
6864914: SPECjvm2008 produces invalid result with zero based Compressed Oops
kvn
parents:
845
diff
changeset
|
8940 assert (Universe::narrow_oop_base() == NULL, "sanity"); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8941 } |
| 304 | 8942 } |
| 8943 | |
| 8944 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) { | |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8945 // Note: it will change flags |
| 304 | 8946 assert (UseCompressedOops, "should only be used for compressed headers"); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8947 assert (Universe::heap() != NULL, "java heap should be initialized"); |
| 304 | 8948 // Cannot assert, unverified entry point counts instructions (see .ad file) |
| 8949 // vtableStubs also counts instructions in pd_code_size_limit. | |
| 8950 // Also do not verify_oop as this is called by verify_oop. | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8951 if (Universe::narrow_oop_shift() != 0) { |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8952 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8953 if (LogMinObjAlignmentInBytes == Address::times_8) { |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8954 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0)); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8955 } else { |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8956 if (dst != src) { |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8957 movq(dst, src); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8958 } |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8959 shlq(dst, LogMinObjAlignmentInBytes); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8960 if (Universe::narrow_oop_base() != NULL) { |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8961 addq(dst, r12_heapbase); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8962 } |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8963 } |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8964 } else { |
|
898
60fea60a6db5
6864914: SPECjvm2008 produces invalid result with zero based Compressed Oops
kvn
parents:
845
diff
changeset
|
8965 assert (Universe::narrow_oop_base() == NULL, "sanity"); |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8966 if (dst != src) { |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8967 movq(dst, src); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8968 } |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8969 } |
| 304 | 8970 } |
| 8971 | |
| 8972 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) { | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8973 assert (UseCompressedOops, "should only be used for compressed headers"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8974 assert (Universe::heap() != NULL, "java heap should be initialized"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8975 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8976 int oop_index = oop_recorder()->find_index(obj); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8977 RelocationHolder rspec = oop_Relocation::spec(oop_index); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8978 mov_narrow_oop(dst, oop_index, rspec); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8979 } |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8980 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8981 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8982 assert (UseCompressedOops, "should only be used for compressed headers"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8983 assert (Universe::heap() != NULL, "java heap should be initialized"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8984 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
| 304 | 8985 int oop_index = oop_recorder()->find_index(obj); |
| 8986 RelocationHolder rspec = oop_Relocation::spec(oop_index); | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8987 mov_narrow_oop(dst, oop_index, rspec); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8988 } |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8989 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8990 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8991 assert (UseCompressedOops, "should only be used for compressed headers"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8992 assert (Universe::heap() != NULL, "java heap should be initialized"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8993 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8994 int oop_index = oop_recorder()->find_index(obj); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8995 RelocationHolder rspec = oop_Relocation::spec(oop_index); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8996 Assembler::cmp_narrow_oop(dst, oop_index, rspec); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8997 } |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8998 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8999 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9000 assert (UseCompressedOops, "should only be used for compressed headers"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9001 assert (Universe::heap() != NULL, "java heap should be initialized"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9002 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9003 int oop_index = oop_recorder()->find_index(obj); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9004 RelocationHolder rspec = oop_Relocation::spec(oop_index); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9005 Assembler::cmp_narrow_oop(dst, oop_index, rspec); |
| 304 | 9006 } |
| 9007 | |
| 9008 void MacroAssembler::reinit_heapbase() { | |
| 9009 if (UseCompressedOops) { | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
9010 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_oop_base_addr())); |
| 304 | 9011 } |
| 9012 } | |
| 9013 #endif // _LP64 | |
| 0 | 9014 |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9015 // IndexOf for constant substrings with size >= 8 chars |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9016 // which don't need to be loaded through stack. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9017 void MacroAssembler::string_indexofC8(Register str1, Register str2, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9018 Register cnt1, Register cnt2, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9019 int int_cnt2, Register result, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9020 XMMRegister vec, Register tmp) { |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9021 assert(UseSSE42Intrinsics, "SSE4.2 is required"); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9022 |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9023 // This method uses pcmpestri inxtruction with bound registers |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9024 // inputs: |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9025 // xmm - substring |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9026 // rax - substring length (elements count) |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9027 // mem - scanned string |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9028 // rdx - string length (elements count) |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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diff
changeset
|
9029 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts) |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
9030 // outputs: |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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diff
changeset
|
9031 // rcx - matched index in string |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
9032 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
9033 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
9034 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
9035 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
9036 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
9037 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
9038 // Note, inline_string_indexOf() generates checks: |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
9039 // if (substr.count > string.count) return -1; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
9040 // if (substr.count == 0) return 0; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
9041 assert(int_cnt2 >= 8, "this code isused only for cnt2 >= 8 chars"); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
9042 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
9043 // Load substring. |
|
41d4973cf100
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parents:
2262
diff
changeset
|
9044 movdqu(vec, Address(str2, 0)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
9045 movl(cnt2, int_cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
9046 movptr(result, str1); // string addr |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
9047 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
9048 if (int_cnt2 > 8) { |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
9049 jmpb(SCAN_TO_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
9050 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
9051 // Reload substr for rescan, this code |
|
41d4973cf100
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parents:
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diff
changeset
|
9052 // is executed only for large substrings (> 8 chars) |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
9053 bind(RELOAD_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
9054 movdqu(vec, Address(str2, 0)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
9055 negptr(cnt2); // Jumped here with negative cnt2, convert to positive |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
9056 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
9057 bind(RELOAD_STR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
9058 // We came here after the beginning of the substring was |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
9059 // matched but the rest of it was not so we need to search |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
9060 // again. Start from the next element after the previous match. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9061 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
9062 // cnt2 is number of substring reminding elements and |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
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changeset
|
9063 // cnt1 is number of string reminding elements when cmp failed. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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changeset
|
9064 // Restored cnt1 = cnt1 - cnt2 + int_cnt2 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
9065 subl(cnt1, cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
9066 addl(cnt1, int_cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
9067 movl(cnt2, int_cnt2); // Now restore cnt2 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9068 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
9069 decrementl(cnt1); // Shift to next element |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
9070 cmpl(cnt1, cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
9071 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9072 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9073 addptr(result, 2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9074 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
9075 } // (int_cnt2 > 8) |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9076 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9077 // Scan string for start of substr in 16-byte vectors |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
9078 bind(SCAN_TO_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
9079 pcmpestri(vec, Address(result, 0), 0x0d); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9080 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9081 subl(cnt1, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9082 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9083 cmpl(cnt1, cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9084 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9085 addptr(result, 16); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9086 jmpb(SCAN_TO_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9087 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9088 // Found a potential substr |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9089 bind(FOUND_CANDIDATE); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9090 // Matched whole vector if first element matched (tmp(rcx) == 0). |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9091 if (int_cnt2 == 8) { |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9092 jccb(Assembler::overflow, RET_FOUND); // OF == 1 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9093 } else { // int_cnt2 > 8 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9094 jccb(Assembler::overflow, FOUND_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9095 } |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9096 // After pcmpestri tmp(rcx) contains matched element index |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9097 // Compute start addr of substr |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9098 lea(result, Address(result, tmp, Address::times_2)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9099 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9100 // Make sure string is still long enough |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9101 subl(cnt1, tmp); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9102 cmpl(cnt1, cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9103 if (int_cnt2 == 8) { |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9104 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9105 } else { // int_cnt2 > 8 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9106 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9107 } |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9108 // Left less then substring. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9109 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9110 bind(RET_NOT_FOUND); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9111 movl(result, -1); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9112 jmpb(EXIT); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9113 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9114 if (int_cnt2 > 8) { |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9115 // This code is optimized for the case when whole substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9116 // is matched if its head is matched. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9117 bind(MATCH_SUBSTR_HEAD); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9118 pcmpestri(vec, Address(result, 0), 0x0d); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9119 // Reload only string if does not match |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9120 jccb(Assembler::noOverflow, RELOAD_STR); // OF == 0 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9121 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9122 Label CONT_SCAN_SUBSTR; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9123 // Compare the rest of substring (> 8 chars). |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9124 bind(FOUND_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9125 // First 8 chars are already matched. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9126 negptr(cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9127 addptr(cnt2, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9128 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9129 bind(SCAN_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9130 subl(cnt1, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9131 cmpl(cnt2, -8); // Do not read beyond substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9132 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9133 // Back-up strings to avoid reading beyond substring: |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9134 // cnt1 = cnt1 - cnt2 + 8 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9135 addl(cnt1, cnt2); // cnt2 is negative |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9136 addl(cnt1, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9137 movl(cnt2, 8); negptr(cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9138 bind(CONT_SCAN_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9139 if (int_cnt2 < (int)G) { |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9140 movdqu(vec, Address(str2, cnt2, Address::times_2, int_cnt2*2)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9141 pcmpestri(vec, Address(result, cnt2, Address::times_2, int_cnt2*2), 0x0d); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9142 } else { |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9143 // calculate index in register to avoid integer overflow (int_cnt2*2) |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9144 movl(tmp, int_cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9145 addptr(tmp, cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9146 movdqu(vec, Address(str2, tmp, Address::times_2, 0)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
9147 pcmpestri(vec, Address(result, tmp, Address::times_2, 0), 0x0d); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9148 } |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
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diff
changeset
|
9149 // Need to reload strings pointers if not matched whole vector |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9150 jccb(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9151 addptr(cnt2, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9152 jccb(Assembler::negative, SCAN_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9153 // Fall through if found full substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9154 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
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diff
changeset
|
9155 } // (int_cnt2 > 8) |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9156 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
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diff
changeset
|
9157 bind(RET_FOUND); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
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diff
changeset
|
9158 // Found result if we matched full small substring. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9159 // Compute substr offset |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9160 subptr(result, str1); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9161 shrl(result, 1); // index |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9162 bind(EXIT); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9163 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
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diff
changeset
|
9164 } // string_indexofC8 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9165 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
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diff
changeset
|
9166 // Small strings are loaded through stack if they cross page boundary. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9167 void MacroAssembler::string_indexof(Register str1, Register str2, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9168 Register cnt1, Register cnt2, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9169 int int_cnt2, Register result, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9170 XMMRegister vec, Register tmp) { |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9171 assert(UseSSE42Intrinsics, "SSE4.2 is required"); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9172 // |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
9173 // int_cnt2 is length of small (< 8 chars) constant substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
9174 // or (-1) for non constant substring in which case its length |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
9175 // is in cnt2 register. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9176 // |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
9177 // Note, inline_string_indexOf() generates checks: |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9178 // if (substr.count > string.count) return -1; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
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diff
changeset
|
9179 // if (substr.count == 0) return 0; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9180 // |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
9181 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < 8), "should be != 0"); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
9182 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9183 // This method uses pcmpestri inxtruction with bound registers |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
9184 // inputs: |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
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diff
changeset
|
9185 // xmm - substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
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diff
changeset
|
9186 // rax - substring length (elements count) |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9187 // mem - scanned string |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9188 // rdx - string length (elements count) |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9189 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts) |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9190 // outputs: |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9191 // rcx - matched index in string |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9192 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9193 |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9194 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9195 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9196 FOUND_CANDIDATE; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9197 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9198 { //======================================================== |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
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parents:
2262
diff
changeset
|
9199 // We don't know where these strings are located |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9200 // and we can't read beyond them. Load them through stack. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9201 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9202 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9203 movptr(tmp, rsp); // save old SP |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9204 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9205 if (int_cnt2 > 0) { // small (< 8 chars) constant substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9206 if (int_cnt2 == 1) { // One char |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9207 load_unsigned_short(result, Address(str2, 0)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9208 movdl(vec, result); // move 32 bits |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9209 } else if (int_cnt2 == 2) { // Two chars |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9210 movdl(vec, Address(str2, 0)); // move 32 bits |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9211 } else if (int_cnt2 == 4) { // Four chars |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9212 movq(vec, Address(str2, 0)); // move 64 bits |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9213 } else { // cnt2 = { 3, 5, 6, 7 } |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9214 // Array header size is 12 bytes in 32-bit VM |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9215 // + 6 bytes for 3 chars == 18 bytes, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9216 // enough space to load vec and shift. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9217 assert(HeapWordSize*typeArrayKlass::header_size() >= 12,"sanity"); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9218 movdqu(vec, Address(str2, (int_cnt2*2)-16)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9219 psrldq(vec, 16-(int_cnt2*2)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9220 } |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9221 } else { // not constant substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9222 cmpl(cnt2, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9223 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9224 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9225 // We can read beyond string if srt+16 does not cross page boundary |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9226 // since heaps are aligned and mapped by pages. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9227 assert(os::vm_page_size() < (int)G, "default page should be small"); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9228 movl(result, str2); // We need only low 32 bits |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9229 andl(result, (os::vm_page_size()-1)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9230 cmpl(result, (os::vm_page_size()-16)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9231 jccb(Assembler::belowEqual, CHECK_STR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9232 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9233 // Move small strings to stack to allow load 16 bytes into vec. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9234 subptr(rsp, 16); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9235 int stk_offset = wordSize-2; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9236 push(cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9237 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9238 bind(COPY_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9239 load_unsigned_short(result, Address(str2, cnt2, Address::times_2, -2)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9240 movw(Address(rsp, cnt2, Address::times_2, stk_offset), result); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9241 decrement(cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9242 jccb(Assembler::notZero, COPY_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9243 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9244 pop(cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9245 movptr(str2, rsp); // New substring address |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9246 } // non constant |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9247 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9248 bind(CHECK_STR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9249 cmpl(cnt1, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9250 jccb(Assembler::aboveEqual, BIG_STRINGS); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9251 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9252 // Check cross page boundary. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9253 movl(result, str1); // We need only low 32 bits |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9254 andl(result, (os::vm_page_size()-1)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9255 cmpl(result, (os::vm_page_size()-16)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9256 jccb(Assembler::belowEqual, BIG_STRINGS); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9257 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9258 subptr(rsp, 16); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9259 int stk_offset = -2; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9260 if (int_cnt2 < 0) { // not constant |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9261 push(cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9262 stk_offset += wordSize; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9263 } |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9264 movl(cnt2, cnt1); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9265 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9266 bind(COPY_STR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9267 load_unsigned_short(result, Address(str1, cnt2, Address::times_2, -2)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9268 movw(Address(rsp, cnt2, Address::times_2, stk_offset), result); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9269 decrement(cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9270 jccb(Assembler::notZero, COPY_STR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9271 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9272 if (int_cnt2 < 0) { // not constant |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9273 pop(cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9274 } |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9275 movptr(str1, rsp); // New string address |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9276 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9277 bind(BIG_STRINGS); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9278 // Load substring. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9279 if (int_cnt2 < 0) { // -1 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9280 movdqu(vec, Address(str2, 0)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9281 push(cnt2); // substr count |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9282 push(str2); // substr addr |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9283 push(str1); // string addr |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9284 } else { |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9285 // Small (< 8 chars) constant substrings are loaded already. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9286 movl(cnt2, int_cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9287 } |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9288 push(tmp); // original SP |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9289 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9290 } // Finished loading |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9291 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9292 //======================================================== |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9293 // Start search |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9294 // |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9295 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9296 movptr(result, str1); // string addr |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9297 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9298 if (int_cnt2 < 0) { // Only for non constant substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9299 jmpb(SCAN_TO_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9300 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9301 // SP saved at sp+0 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9302 // String saved at sp+1*wordSize |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9303 // Substr saved at sp+2*wordSize |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9304 // Substr count saved at sp+3*wordSize |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9305 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9306 // Reload substr for rescan, this code |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9307 // is executed only for large substrings (> 8 chars) |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9308 bind(RELOAD_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9309 movptr(str2, Address(rsp, 2*wordSize)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9310 movl(cnt2, Address(rsp, 3*wordSize)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9311 movdqu(vec, Address(str2, 0)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9312 // We came here after the beginning of the substring was |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9313 // matched but the rest of it was not so we need to search |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9314 // again. Start from the next element after the previous match. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9315 subptr(str1, result); // Restore counter |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9316 shrl(str1, 1); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9317 addl(cnt1, str1); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9318 decrementl(cnt1); // Shift to next element |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9319 cmpl(cnt1, cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9320 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9321 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9322 addptr(result, 2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9323 } // non constant |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9324 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9325 // Scan string for start of substr in 16-byte vectors |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9326 bind(SCAN_TO_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9327 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9328 pcmpestri(vec, Address(result, 0), 0x0d); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9329 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9330 subl(cnt1, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9331 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9332 cmpl(cnt1, cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9333 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9334 addptr(result, 16); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9335 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9336 bind(ADJUST_STR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9337 cmpl(cnt1, 8); // Do not read beyond string |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9338 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9339 // Back-up string to avoid reading beyond string. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9340 lea(result, Address(result, cnt1, Address::times_2, -16)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9341 movl(cnt1, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9342 jmpb(SCAN_TO_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9343 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9344 // Found a potential substr |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9345 bind(FOUND_CANDIDATE); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9346 // After pcmpestri tmp(rcx) contains matched element index |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9347 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9348 // Make sure string is still long enough |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9349 subl(cnt1, tmp); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9350 cmpl(cnt1, cnt2); |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9351 jccb(Assembler::greaterEqual, FOUND_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9352 // Left less then substring. |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9353 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9354 bind(RET_NOT_FOUND); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9355 movl(result, -1); |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9356 jmpb(CLEANUP); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9357 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9358 bind(FOUND_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9359 // Compute start addr of substr |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9360 lea(result, Address(result, tmp, Address::times_2)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9361 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9362 if (int_cnt2 > 0) { // Constant substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9363 // Repeat search for small substring (< 8 chars) |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9364 // from new point without reloading substring. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9365 // Have to check that we don't read beyond string. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9366 cmpl(tmp, 8-int_cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9367 jccb(Assembler::greater, ADJUST_STR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9368 // Fall through if matched whole substring. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9369 } else { // non constant |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9370 assert(int_cnt2 == -1, "should be != 0"); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9371 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9372 addl(tmp, cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9373 // Found result if we matched whole substring. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9374 cmpl(tmp, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9375 jccb(Assembler::lessEqual, RET_FOUND); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9376 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9377 // Repeat search for small substring (<= 8 chars) |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9378 // from new point 'str1' without reloading substring. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9379 cmpl(cnt2, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9380 // Have to check that we don't read beyond string. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9381 jccb(Assembler::lessEqual, ADJUST_STR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9382 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9383 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9384 // Compare the rest of substring (> 8 chars). |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9385 movptr(str1, result); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9386 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9387 cmpl(tmp, cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9388 // First 8 chars are already matched. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9389 jccb(Assembler::equal, CHECK_NEXT); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9390 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9391 bind(SCAN_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9392 pcmpestri(vec, Address(str1, 0), 0x0d); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9393 // Need to reload strings pointers if not matched whole vector |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9394 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9395 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9396 bind(CHECK_NEXT); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9397 subl(cnt2, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9398 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9399 addptr(str1, 16); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9400 addptr(str2, 16); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9401 subl(cnt1, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9402 cmpl(cnt2, 8); // Do not read beyond substring |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9403 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9404 // Back-up strings to avoid reading beyond substring. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9405 lea(str2, Address(str2, cnt2, Address::times_2, -16)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9406 lea(str1, Address(str1, cnt2, Address::times_2, -16)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9407 subl(cnt1, cnt2); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9408 movl(cnt2, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9409 addl(cnt1, 8); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9410 bind(CONT_SCAN_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9411 movdqu(vec, Address(str2, 0)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9412 jmpb(SCAN_SUBSTR); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9413 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9414 bind(RET_FOUND_LONG); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9415 movptr(str1, Address(rsp, wordSize)); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9416 } // non constant |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9417 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9418 bind(RET_FOUND); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9419 // Compute substr offset |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9420 subptr(result, str1); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9421 shrl(result, 1); // index |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9422 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9423 bind(CLEANUP); |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9424 pop(rsp); // restore SP |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9425 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
9426 } // string_indexof |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9427 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9428 // Compare strings. |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9429 void MacroAssembler::string_compare(Register str1, Register str2, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9430 Register cnt1, Register cnt2, Register result, |
| 2262 | 9431 XMMRegister vec1) { |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9432 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL; |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9433 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9434 // Compute the minimum of the string lengths and the |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9435 // difference of the string lengths (stack). |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9436 // Do the conditional move stuff |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9437 movl(result, cnt1); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9438 subl(cnt1, cnt2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9439 push(cnt1); |
|
2415
09f96c3ff1ad
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
2404
diff
changeset
|
9440 cmov32(Assembler::lessEqual, cnt2, result); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9441 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9442 // Is the minimum length zero? |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9443 testl(cnt2, cnt2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9444 jcc(Assembler::zero, LENGTH_DIFF_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9445 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9446 // Load first characters |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9447 load_unsigned_short(result, Address(str1, 0)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9448 load_unsigned_short(cnt1, Address(str2, 0)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9449 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9450 // Compare first characters |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9451 subl(result, cnt1); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9452 jcc(Assembler::notZero, POP_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9453 decrementl(cnt2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9454 jcc(Assembler::zero, LENGTH_DIFF_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9455 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9456 { |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9457 // Check after comparing first character to see if strings are equivalent |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9458 Label LSkip2; |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9459 // Check if the strings start at same location |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9460 cmpptr(str1, str2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9461 jccb(Assembler::notEqual, LSkip2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9462 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9463 // Check if the length difference is zero (from stack) |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9464 cmpl(Address(rsp, 0), 0x0); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9465 jcc(Assembler::equal, LENGTH_DIFF_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9466 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9467 // Strings might not be equivalent |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9468 bind(LSkip2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9469 } |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9470 |
| 2262 | 9471 Address::ScaleFactor scale = Address::times_2; |
| 9472 int stride = 8; | |
| 9473 | |
| 9474 // Advance to next element | |
| 9475 addptr(str1, 16/stride); | |
| 9476 addptr(str2, 16/stride); | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9477 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9478 if (UseSSE42Intrinsics) { |
| 2262 | 9479 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL; |
| 9480 int pcmpmask = 0x19; | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9481 // Setup to compare 16-byte vectors |
| 2262 | 9482 movl(result, cnt2); |
| 9483 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9484 jccb(Assembler::zero, COMPARE_TAIL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9485 |
| 2262 | 9486 lea(str1, Address(str1, result, scale)); |
| 9487 lea(str2, Address(str2, result, scale)); | |
| 9488 negptr(result); | |
| 9489 | |
| 9490 // pcmpestri | |
| 9491 // inputs: | |
| 9492 // vec1- substring | |
| 9493 // rax - negative string length (elements count) | |
| 9494 // mem - scaned string | |
| 9495 // rdx - string length (elements count) | |
| 9496 // pcmpmask - cmp mode: 11000 (string compare with negated result) | |
| 9497 // + 00 (unsigned bytes) or + 01 (unsigned shorts) | |
| 9498 // outputs: | |
| 9499 // rcx - first mismatched element index | |
| 9500 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri"); | |
| 9501 | |
| 9502 bind(COMPARE_WIDE_VECTORS); | |
| 9503 movdqu(vec1, Address(str1, result, scale)); | |
| 9504 pcmpestri(vec1, Address(str2, result, scale), pcmpmask); | |
| 9505 // After pcmpestri cnt1(rcx) contains mismatched element index | |
| 9506 | |
| 9507 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1 | |
| 9508 addptr(result, stride); | |
| 9509 subptr(cnt2, stride); | |
| 9510 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS); | |
| 9511 | |
| 9512 // compare wide vectors tail | |
| 9513 testl(result, result); | |
| 9514 jccb(Assembler::zero, LENGTH_DIFF_LABEL); | |
| 9515 | |
| 9516 movl(cnt2, stride); | |
| 9517 movl(result, stride); | |
| 9518 negptr(result); | |
| 9519 movdqu(vec1, Address(str1, result, scale)); | |
| 9520 pcmpestri(vec1, Address(str2, result, scale), pcmpmask); | |
| 9521 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL); | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9522 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9523 // Mismatched characters in the vectors |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9524 bind(VECTOR_NOT_EQUAL); |
| 2262 | 9525 addptr(result, cnt1); |
| 9526 movptr(cnt2, result); | |
| 9527 load_unsigned_short(result, Address(str1, cnt2, scale)); | |
| 9528 load_unsigned_short(cnt1, Address(str2, cnt2, scale)); | |
| 9529 subl(result, cnt1); | |
| 9530 jmpb(POP_LABEL); | |
| 9531 | |
| 9532 bind(COMPARE_TAIL); // limit is zero | |
| 9533 movl(cnt2, result); | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9534 // Fallthru to tail compare |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9535 } |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9536 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9537 // Shift str2 and str1 to the end of the arrays, negate min |
| 2262 | 9538 lea(str1, Address(str1, cnt2, scale, 0)); |
| 9539 lea(str2, Address(str2, cnt2, scale, 0)); | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9540 negptr(cnt2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9541 |
| 2262 | 9542 // Compare the rest of the elements |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9543 bind(WHILE_HEAD_LABEL); |
| 2262 | 9544 load_unsigned_short(result, Address(str1, cnt2, scale, 0)); |
| 9545 load_unsigned_short(cnt1, Address(str2, cnt2, scale, 0)); | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9546 subl(result, cnt1); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9547 jccb(Assembler::notZero, POP_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9548 increment(cnt2); |
| 2262 | 9549 jccb(Assembler::notZero, WHILE_HEAD_LABEL); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9550 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9551 // Strings are equal up to min length. Return the length difference. |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9552 bind(LENGTH_DIFF_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9553 pop(result); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9554 jmpb(DONE_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9555 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
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diff
changeset
|
9556 // Discard the stored length difference |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
changeset
|
9557 bind(POP_LABEL); |
| 2262 | 9558 pop(cnt1); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
9559 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
9560 // That's it |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9561 bind(DONE_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
9562 } |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9563 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
9564 // Compare char[] arrays aligned to 4 bytes or substrings. |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9565 void MacroAssembler::char_arrays_equals(bool is_array_equ, Register ary1, Register ary2, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
9566 Register limit, Register result, Register chr, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
9567 XMMRegister vec1, XMMRegister vec2) { |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
changeset
|
9568 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR; |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
changeset
|
9569 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
9570 int length_offset = arrayOopDesc::length_offset_in_bytes(); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
changeset
|
9571 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
changeset
|
9572 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
9573 // Check the input args |
|
62001a362ce9
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parents:
898
diff
changeset
|
9574 cmpptr(ary1, ary2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
changeset
|
9575 jcc(Assembler::equal, TRUE_LABEL); |
|
62001a362ce9
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parents:
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diff
changeset
|
9576 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
9577 if (is_array_equ) { |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
changeset
|
9578 // Need additional checks for arrays_equals. |
| 1016 | 9579 testptr(ary1, ary1); |
| 9580 jcc(Assembler::zero, FALSE_LABEL); | |
| 9581 testptr(ary2, ary2); | |
| 9582 jcc(Assembler::zero, FALSE_LABEL); | |
|
986
62001a362ce9
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parents:
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diff
changeset
|
9583 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
9584 // Check the lengths |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
changeset
|
9585 movl(limit, Address(ary1, length_offset)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9586 cmpl(limit, Address(ary2, length_offset)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9587 jcc(Assembler::notEqual, FALSE_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9588 } |
|
62001a362ce9
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kvn
parents:
898
diff
changeset
|
9589 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
9590 // count == 0 |
|
62001a362ce9
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parents:
898
diff
changeset
|
9591 testl(limit, limit); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
9592 jcc(Assembler::zero, TRUE_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
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diff
changeset
|
9593 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
9594 if (is_array_equ) { |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
9595 // Load array address |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
9596 lea(ary1, Address(ary1, base_offset)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9597 lea(ary2, Address(ary2, base_offset)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9598 } |
|
62001a362ce9
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kvn
parents:
898
diff
changeset
|
9599 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
9600 shll(limit, 1); // byte count != 0 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9601 movl(result, limit); // copy |
|
62001a362ce9
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kvn
parents:
898
diff
changeset
|
9602 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
9603 if (UseSSE42Intrinsics) { |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
9604 // With SSE4.2, use double quad vector compare |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9605 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; |
| 2262 | 9606 |
|
986
62001a362ce9
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parents:
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diff
changeset
|
9607 // Compare 16-byte vectors |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9608 andl(result, 0x0000000e); // tail count (in bytes) |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9609 andl(limit, 0xfffffff0); // vector count (in bytes) |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9610 jccb(Assembler::zero, COMPARE_TAIL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9611 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9612 lea(ary1, Address(ary1, limit, Address::times_1)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9613 lea(ary2, Address(ary2, limit, Address::times_1)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9614 negptr(limit); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9615 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9616 bind(COMPARE_WIDE_VECTORS); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9617 movdqu(vec1, Address(ary1, limit, Address::times_1)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9618 movdqu(vec2, Address(ary2, limit, Address::times_1)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9619 pxor(vec1, vec2); |
| 2262 | 9620 |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9621 ptest(vec1, vec1); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9622 jccb(Assembler::notZero, FALSE_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9623 addptr(limit, 16); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9624 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9625 |
| 2262 | 9626 testl(result, result); |
| 9627 jccb(Assembler::zero, TRUE_LABEL); | |
| 9628 | |
| 9629 movdqu(vec1, Address(ary1, result, Address::times_1, -16)); | |
| 9630 movdqu(vec2, Address(ary2, result, Address::times_1, -16)); | |
| 9631 pxor(vec1, vec2); | |
| 9632 | |
| 9633 ptest(vec1, vec1); | |
| 9634 jccb(Assembler::notZero, FALSE_LABEL); | |
| 9635 jmpb(TRUE_LABEL); | |
| 9636 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9637 bind(COMPARE_TAIL); // limit is zero |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9638 movl(limit, result); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9639 // Fallthru to tail compare |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9640 } |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9641 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
9642 // Compare 4-byte vectors |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9643 andl(limit, 0xfffffffc); // vector count (in bytes) |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9644 jccb(Assembler::zero, COMPARE_CHAR); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9645 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9646 lea(ary1, Address(ary1, limit, Address::times_1)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9647 lea(ary2, Address(ary2, limit, Address::times_1)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9648 negptr(limit); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9649 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9650 bind(COMPARE_VECTORS); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9651 movl(chr, Address(ary1, limit, Address::times_1)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9652 cmpl(chr, Address(ary2, limit, Address::times_1)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9653 jccb(Assembler::notEqual, FALSE_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9654 addptr(limit, 4); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9655 jcc(Assembler::notZero, COMPARE_VECTORS); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9656 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9657 // Compare trailing char (final 2 bytes), if any |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9658 bind(COMPARE_CHAR); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9659 testl(result, 0x2); // tail char |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9660 jccb(Assembler::zero, TRUE_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9661 load_unsigned_short(chr, Address(ary1, 0)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9662 load_unsigned_short(limit, Address(ary2, 0)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9663 cmpl(chr, limit); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9664 jccb(Assembler::notEqual, FALSE_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9665 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9666 bind(TRUE_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9667 movl(result, 1); // return true |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9668 jmpb(DONE); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9669 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9670 bind(FALSE_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9671 xorl(result, result); // return false |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9672 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9673 // That's it |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9674 bind(DONE); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
9675 } |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
9676 |
| 1763 | 9677 #ifdef PRODUCT |
| 9678 #define BLOCK_COMMENT(str) /* nothing */ | |
| 9679 #else | |
| 9680 #define BLOCK_COMMENT(str) block_comment(str) | |
| 9681 #endif | |
| 9682 | |
| 9683 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") | |
| 9684 void MacroAssembler::generate_fill(BasicType t, bool aligned, | |
| 9685 Register to, Register value, Register count, | |
| 9686 Register rtmp, XMMRegister xtmp) { | |
| 9687 assert_different_registers(to, value, count, rtmp); | |
| 9688 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte; | |
| 9689 Label L_fill_2_bytes, L_fill_4_bytes; | |
| 9690 | |
| 9691 int shift = -1; | |
| 9692 switch (t) { | |
| 9693 case T_BYTE: | |
| 9694 shift = 2; | |
| 9695 break; | |
| 9696 case T_SHORT: | |
| 9697 shift = 1; | |
| 9698 break; | |
| 9699 case T_INT: | |
| 9700 shift = 0; | |
| 9701 break; | |
| 9702 default: ShouldNotReachHere(); | |
| 9703 } | |
| 9704 | |
| 9705 if (t == T_BYTE) { | |
| 9706 andl(value, 0xff); | |
| 9707 movl(rtmp, value); | |
| 9708 shll(rtmp, 8); | |
| 9709 orl(value, rtmp); | |
| 9710 } | |
| 9711 if (t == T_SHORT) { | |
| 9712 andl(value, 0xffff); | |
| 9713 } | |
| 9714 if (t == T_BYTE || t == T_SHORT) { | |
| 9715 movl(rtmp, value); | |
| 9716 shll(rtmp, 16); | |
| 9717 orl(value, rtmp); | |
| 9718 } | |
| 9719 | |
| 9720 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element | |
| 9721 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp | |
| 9722 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) { | |
| 9723 // align source address at 4 bytes address boundary | |
| 9724 if (t == T_BYTE) { | |
| 9725 // One byte misalignment happens only for byte arrays | |
| 9726 testptr(to, 1); | |
| 9727 jccb(Assembler::zero, L_skip_align1); | |
| 9728 movb(Address(to, 0), value); | |
| 9729 increment(to); | |
| 9730 decrement(count); | |
| 9731 BIND(L_skip_align1); | |
| 9732 } | |
| 9733 // Two bytes misalignment happens only for byte and short (char) arrays | |
| 9734 testptr(to, 2); | |
| 9735 jccb(Assembler::zero, L_skip_align2); | |
| 9736 movw(Address(to, 0), value); | |
| 9737 addptr(to, 2); | |
| 9738 subl(count, 1<<(shift-1)); | |
| 9739 BIND(L_skip_align2); | |
| 9740 } | |
| 9741 if (UseSSE < 2) { | |
| 9742 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; | |
| 9743 // Fill 32-byte chunks | |
| 9744 subl(count, 8 << shift); | |
| 9745 jcc(Assembler::less, L_check_fill_8_bytes); | |
| 9746 align(16); | |
| 9747 | |
| 9748 BIND(L_fill_32_bytes_loop); | |
| 9749 | |
| 9750 for (int i = 0; i < 32; i += 4) { | |
| 9751 movl(Address(to, i), value); | |
| 9752 } | |
| 9753 | |
| 9754 addptr(to, 32); | |
| 9755 subl(count, 8 << shift); | |
| 9756 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); | |
| 9757 BIND(L_check_fill_8_bytes); | |
| 9758 addl(count, 8 << shift); | |
| 9759 jccb(Assembler::zero, L_exit); | |
| 9760 jmpb(L_fill_8_bytes); | |
| 9761 | |
| 9762 // | |
| 9763 // length is too short, just fill qwords | |
| 9764 // | |
| 9765 BIND(L_fill_8_bytes_loop); | |
| 9766 movl(Address(to, 0), value); | |
| 9767 movl(Address(to, 4), value); | |
| 9768 addptr(to, 8); | |
| 9769 BIND(L_fill_8_bytes); | |
| 9770 subl(count, 1 << (shift + 1)); | |
| 9771 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); | |
| 9772 // fall through to fill 4 bytes | |
| 9773 } else { | |
| 9774 Label L_fill_32_bytes; | |
| 9775 if (!UseUnalignedLoadStores) { | |
| 9776 // align to 8 bytes, we know we are 4 byte aligned to start | |
| 9777 testptr(to, 4); | |
| 9778 jccb(Assembler::zero, L_fill_32_bytes); | |
| 9779 movl(Address(to, 0), value); | |
| 9780 addptr(to, 4); | |
| 9781 subl(count, 1<<shift); | |
| 9782 } | |
| 9783 BIND(L_fill_32_bytes); | |
| 9784 { | |
| 9785 assert( UseSSE >= 2, "supported cpu only" ); | |
| 9786 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; | |
| 9787 // Fill 32-byte chunks | |
| 9788 movdl(xtmp, value); | |
| 9789 pshufd(xtmp, xtmp, 0); | |
| 9790 | |
| 9791 subl(count, 8 << shift); | |
| 9792 jcc(Assembler::less, L_check_fill_8_bytes); | |
| 9793 align(16); | |
| 9794 | |
| 9795 BIND(L_fill_32_bytes_loop); | |
| 9796 | |
| 9797 if (UseUnalignedLoadStores) { | |
| 9798 movdqu(Address(to, 0), xtmp); | |
| 9799 movdqu(Address(to, 16), xtmp); | |
| 9800 } else { | |
| 9801 movq(Address(to, 0), xtmp); | |
| 9802 movq(Address(to, 8), xtmp); | |
| 9803 movq(Address(to, 16), xtmp); | |
| 9804 movq(Address(to, 24), xtmp); | |
| 9805 } | |
| 9806 | |
| 9807 addptr(to, 32); | |
| 9808 subl(count, 8 << shift); | |
| 9809 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); | |
| 9810 BIND(L_check_fill_8_bytes); | |
| 9811 addl(count, 8 << shift); | |
| 9812 jccb(Assembler::zero, L_exit); | |
| 9813 jmpb(L_fill_8_bytes); | |
| 9814 | |
| 9815 // | |
| 9816 // length is too short, just fill qwords | |
| 9817 // | |
| 9818 BIND(L_fill_8_bytes_loop); | |
| 9819 movq(Address(to, 0), xtmp); | |
| 9820 addptr(to, 8); | |
| 9821 BIND(L_fill_8_bytes); | |
| 9822 subl(count, 1 << (shift + 1)); | |
| 9823 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); | |
| 9824 } | |
| 9825 } | |
| 9826 // fill trailing 4 bytes | |
| 9827 BIND(L_fill_4_bytes); | |
| 9828 testl(count, 1<<shift); | |
| 9829 jccb(Assembler::zero, L_fill_2_bytes); | |
| 9830 movl(Address(to, 0), value); | |
| 9831 if (t == T_BYTE || t == T_SHORT) { | |
| 9832 addptr(to, 4); | |
| 9833 BIND(L_fill_2_bytes); | |
| 9834 // fill trailing 2 bytes | |
| 9835 testl(count, 1<<(shift-1)); | |
| 9836 jccb(Assembler::zero, L_fill_byte); | |
| 9837 movw(Address(to, 0), value); | |
| 9838 if (t == T_BYTE) { | |
| 9839 addptr(to, 2); | |
| 9840 BIND(L_fill_byte); | |
| 9841 // fill trailing byte | |
| 9842 testl(count, 1); | |
| 9843 jccb(Assembler::zero, L_exit); | |
| 9844 movb(Address(to, 0), value); | |
| 9845 } else { | |
| 9846 BIND(L_fill_byte); | |
| 9847 } | |
| 9848 } else { | |
| 9849 BIND(L_fill_2_bytes); | |
| 9850 } | |
| 9851 BIND(L_exit); | |
| 9852 } | |
| 9853 #undef BIND | |
| 9854 #undef BLOCK_COMMENT | |
| 9855 | |
| 9856 | |
| 0 | 9857 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) { |
| 9858 switch (cond) { | |
| 9859 // Note some conditions are synonyms for others | |
| 9860 case Assembler::zero: return Assembler::notZero; | |
| 9861 case Assembler::notZero: return Assembler::zero; | |
| 9862 case Assembler::less: return Assembler::greaterEqual; | |
| 9863 case Assembler::lessEqual: return Assembler::greater; | |
| 9864 case Assembler::greater: return Assembler::lessEqual; | |
| 9865 case Assembler::greaterEqual: return Assembler::less; | |
| 9866 case Assembler::below: return Assembler::aboveEqual; | |
| 9867 case Assembler::belowEqual: return Assembler::above; | |
| 9868 case Assembler::above: return Assembler::belowEqual; | |
| 9869 case Assembler::aboveEqual: return Assembler::below; | |
| 9870 case Assembler::overflow: return Assembler::noOverflow; | |
| 9871 case Assembler::noOverflow: return Assembler::overflow; | |
| 9872 case Assembler::negative: return Assembler::positive; | |
| 9873 case Assembler::positive: return Assembler::negative; | |
| 9874 case Assembler::parity: return Assembler::noParity; | |
| 9875 case Assembler::noParity: return Assembler::parity; | |
| 9876 } | |
| 9877 ShouldNotReachHere(); return Assembler::overflow; | |
| 9878 } | |
| 9879 | |
| 9880 SkipIfEqual::SkipIfEqual( | |
| 9881 MacroAssembler* masm, const bool* flag_addr, bool value) { | |
| 9882 _masm = masm; | |
| 9883 _masm->cmp8(ExternalAddress((address)flag_addr), value); | |
| 9884 _masm->jcc(Assembler::equal, _label); | |
| 9885 } | |
| 9886 | |
| 9887 SkipIfEqual::~SkipIfEqual() { | |
| 9888 _masm->bind(_label); | |
| 9889 } |