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comparison src/cpu/sparc/vm/sparc.ad @ 17795:a9becfeecd1b

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Merge
author kvn
date Wed, 22 Jan 2014 17:42:23 -0800
parents 50fdb38839eb 9ecf408d4568
children f040cf9fc9c0
comparison
equal deleted inserted replaced
17794:3514ee402842 17795:a9becfeecd1b
755 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]); 755 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
756 } 756 }
757 #endif 757 #endif
758 758
759 759
760 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary, 760 void emit_form3_mem_reg(CodeBuffer &cbuf, PhaseRegAlloc* ra, const MachNode* n, int primary, int tertiary,
761 int src1_enc, int disp32, int src2_enc, int dst_enc) { 761 int src1_enc, int disp32, int src2_enc, int dst_enc) {
762 762
763 #ifdef ASSERT 763 #ifdef ASSERT
764 // The following code implements the +VerifyOops feature. 764 // The following code implements the +VerifyOops feature.
765 // It verifies oop values which are loaded into or stored out of 765 // It verifies oop values which are loaded into or stored out of
910 | (src1_enc << 14); 910 | (src1_enc << 14);
911 911
912 uint index = src2_enc; 912 uint index = src2_enc;
913 int disp = disp32; 913 int disp = disp32;
914 914
915 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) 915 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) {
916 disp += STACK_BIAS; 916 disp += STACK_BIAS;
917 // Quick fix for JDK-8029668: check that stack offset fits, bailout if not
918 if (!Assembler::is_simm13(disp)) {
919 ra->C->record_method_not_compilable("unable to handle large constant offsets");
920 return;
921 }
922 }
917 923
918 // We should have a compiler bailout here rather than a guarantee. 924 // We should have a compiler bailout here rather than a guarantee.
919 // Better yet would be some mechanism to handle variable-size matches correctly. 925 // Better yet would be some mechanism to handle variable-size matches correctly.
920 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" ); 926 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
921 927
1282 if (r->is_Register()) return rc_int; 1288 if (r->is_Register()) return rc_int;
1283 assert(r->is_FloatRegister(), "must be"); 1289 assert(r->is_FloatRegister(), "must be");
1284 return rc_float; 1290 return rc_float;
1285 } 1291 }
1286 1292
1287 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) { 1293 static int impl_helper(const MachNode* mach, CodeBuffer* cbuf, PhaseRegAlloc* ra, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
1288 if( cbuf ) { 1294 if (cbuf) {
1289 // Better yet would be some mechanism to handle variable-size matches correctly 1295 emit_form3_mem_reg(*cbuf, ra, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1290 if (!Assembler::is_simm13(offset + STACK_BIAS)) {
1291 ra_->C->record_method_not_compilable("unable to handle large constant offsets");
1292 } else {
1293 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1294 }
1295 } 1296 }
1296 #ifndef PRODUCT 1297 #ifndef PRODUCT
1297 else if( !do_size ) { 1298 else if (!do_size) {
1298 if( size != 0 ) st->print("\n\t"); 1299 if (size != 0) st->print("\n\t");
1299 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg)); 1300 if (is_load) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
1300 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset); 1301 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
1301 } 1302 }
1302 #endif 1303 #endif
1303 return size+4; 1304 return size+4;
1304 } 1305 }
1305 1306
2093 __ untested("encoding"); 2094 __ untested("encoding");
2094 #endif 2095 #endif
2095 %} 2096 %}
2096 2097
2097 enc_class form3_mem_reg( memory mem, iRegI dst ) %{ 2098 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
2098 emit_form3_mem_reg(cbuf, this, $primary, $tertiary, 2099 emit_form3_mem_reg(cbuf, ra_, this, $primary, $tertiary,
2099 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); 2100 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2100 %} 2101 %}
2101 2102
2102 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{ 2103 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
2103 emit_form3_mem_reg(cbuf, this, $primary, -1, 2104 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2104 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); 2105 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2105 %} 2106 %}
2106 2107
2107 enc_class form3_mem_prefetch_read( memory mem ) %{ 2108 enc_class form3_mem_prefetch_read( memory mem ) %{
2108 emit_form3_mem_reg(cbuf, this, $primary, -1, 2109 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2109 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/); 2110 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
2110 %} 2111 %}
2111 2112
2112 enc_class form3_mem_prefetch_write( memory mem ) %{ 2113 enc_class form3_mem_prefetch_write( memory mem ) %{
2113 emit_form3_mem_reg(cbuf, this, $primary, -1, 2114 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2114 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/); 2115 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
2115 %} 2116 %}
2116 2117
2117 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{ 2118 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
2118 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4"); 2119 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2119 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4"); 2120 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2120 guarantee($mem$$index == R_G0_enc, "double index?"); 2121 guarantee($mem$$index == R_G0_enc, "double index?");
2121 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc ); 2122 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
2122 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg ); 2123 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
2123 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 ); 2124 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
2124 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc ); 2125 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
2125 %} 2126 %}
2126 2127
2127 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{ 2128 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
2128 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4"); 2129 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2129 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4"); 2130 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2130 guarantee($mem$$index == R_G0_enc, "double index?"); 2131 guarantee($mem$$index == R_G0_enc, "double index?");
2131 // Load long with 2 instructions 2132 // Load long with 2 instructions
2132 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 ); 2133 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
2133 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 ); 2134 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
2134 %} 2135 %}
2135 2136
2136 //%%% form3_mem_plus_4_reg is a hack--get rid of it 2137 //%%% form3_mem_plus_4_reg is a hack--get rid of it
2137 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{ 2138 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
2138 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4"); 2139 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
2139 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg); 2140 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
2140 %} 2141 %}
2141 2142
2142 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{ 2143 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
2143 // Encode a reg-reg copy. If it is useless, then empty encoding. 2144 // Encode a reg-reg copy. If it is useless, then empty encoding.
2144 if( $rs2$$reg != $rd$$reg ) 2145 if( $rs2$$reg != $rd$$reg )