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comparison src/cpu/sparc/vm/sparc.ad @ 14456:abec000618bf

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Merge
author kvn
date Tue, 28 Jan 2014 12:25:34 -0800
parents 00f5eff62d18 50fdb38839eb
children 45467c53f178
comparison
equal deleted inserted replaced
14269:2a8891e0a082 14456:abec000618bf
1038 } 1038 }
1039 return offset; 1039 return offset;
1040 } 1040 }
1041 } 1041 }
1042 1042
1043 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1044 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1045 ShouldNotReachHere();
1046 }
1047
1043 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { 1048 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1044 Compile* C = ra_->C; 1049 Compile* C = ra_->C;
1045 Compile::ConstantTable& constant_table = C->constant_table(); 1050 Compile::ConstantTable& constant_table = C->constant_table();
1046 MacroAssembler _masm(&cbuf); 1051 MacroAssembler _masm(&cbuf);
1047 1052
1888 1893
1889 // CMOVF/CMOVD are expensive on T4 and on SPARC64. 1894 // CMOVF/CMOVD are expensive on T4 and on SPARC64.
1890 const int Matcher::float_cmove_cost() { 1895 const int Matcher::float_cmove_cost() {
1891 return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0; 1896 return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0;
1892 } 1897 }
1898
1899 // Does the CPU require late expand (see block.cpp for description of late expand)?
1900 const bool Matcher::require_postalloc_expand = false;
1893 1901
1894 // Should the Matcher clone shifts on addressing modes, expecting them to 1902 // Should the Matcher clone shifts on addressing modes, expecting them to
1895 // be subsumed into complex addressing expressions or compute them into 1903 // be subsumed into complex addressing expressions or compute them into
1896 // registers? True for Intel but false for most RISCs 1904 // registers? True for Intel but false for most RISCs
1897 const bool Matcher::clone_shift_expressions = false; 1905 const bool Matcher::clone_shift_expressions = false;
3246 // Body of function which returns an OptoRegs array locating 3254 // Body of function which returns an OptoRegs array locating
3247 // arguments either in registers or in stack slots for callin 3255 // arguments either in registers or in stack slots for callin
3248 // C. 3256 // C.
3249 c_calling_convention %{ 3257 c_calling_convention %{
3250 // This is obviously always outgoing 3258 // This is obviously always outgoing
3251 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); 3259 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3252 %} 3260 %}
3253 3261
3254 // Location of native (C/C++) and interpreter return values. This is specified to 3262 // Location of native (C/C++) and interpreter return values. This is specified to
3255 // be the same as Java. In the 32-bit VM, long values are actually returned from 3263 // be the same as Java. In the 32-bit VM, long values are actually returned from
3256 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying 3264 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
6648 //----------MemBar Instructions----------------------------------------------- 6656 //----------MemBar Instructions-----------------------------------------------
6649 // Memory barrier flavors 6657 // Memory barrier flavors
6650 6658
6651 instruct membar_acquire() %{ 6659 instruct membar_acquire() %{
6652 match(MemBarAcquire); 6660 match(MemBarAcquire);
6661 match(LoadFence);
6653 ins_cost(4*MEMORY_REF_COST); 6662 ins_cost(4*MEMORY_REF_COST);
6654 6663
6655 size(0); 6664 size(0);
6656 format %{ "MEMBAR-acquire" %} 6665 format %{ "MEMBAR-acquire" %}
6657 ins_encode( enc_membar_acquire ); 6666 ins_encode( enc_membar_acquire );
6668 ins_pipe(empty); 6677 ins_pipe(empty);
6669 %} 6678 %}
6670 6679
6671 instruct membar_release() %{ 6680 instruct membar_release() %{
6672 match(MemBarRelease); 6681 match(MemBarRelease);
6682 match(StoreFence);
6673 ins_cost(4*MEMORY_REF_COST); 6683 ins_cost(4*MEMORY_REF_COST);
6674 6684
6675 size(0); 6685 size(0);
6676 format %{ "MEMBAR-release" %} 6686 format %{ "MEMBAR-release" %}
6677 ins_encode( enc_membar_release ); 6687 ins_encode( enc_membar_release );
9169 effect(USE labl); 9179 effect(USE labl);
9170 9180
9171 size(4); 9181 size(4);
9172 ins_cost(BRANCH_COST); 9182 ins_cost(BRANCH_COST);
9173 format %{ "BA $labl\t! short branch" %} 9183 format %{ "BA $labl\t! short branch" %}
9174 ins_encode %{ 9184 ins_encode %{
9175 Label* L = $labl$$label; 9185 Label* L = $labl$$label;
9176 assert(__ use_cbcond(*L), "back to back cbcond"); 9186 assert(__ use_cbcond(*L), "back to back cbcond");
9177 __ ba_short(*L); 9187 __ ba_short(*L);
9178 %} 9188 %}
9179 ins_short_branch(1); 9189 ins_short_branch(1);