Mercurial > hg > truffle
diff src/cpu/sparc/vm/sparc.ad @ 14456:abec000618bf
Merge
author | kvn |
---|---|
date | Tue, 28 Jan 2014 12:25:34 -0800 |
parents | 00f5eff62d18 50fdb38839eb |
children | 45467c53f178 |
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--- a/src/cpu/sparc/vm/sparc.ad Tue Jan 28 11:21:43 2014 -0800 +++ b/src/cpu/sparc/vm/sparc.ad Tue Jan 28 12:25:34 2014 -0800 @@ -1040,6 +1040,11 @@ } } +bool MachConstantBaseNode::requires_postalloc_expand() const { return false; } +void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) { + ShouldNotReachHere(); +} + void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { Compile* C = ra_->C; Compile::ConstantTable& constant_table = C->constant_table(); @@ -1891,6 +1896,9 @@ return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0; } +// Does the CPU require late expand (see block.cpp for description of late expand)? +const bool Matcher::require_postalloc_expand = false; + // Should the Matcher clone shifts on addressing modes, expecting them to // be subsumed into complex addressing expressions or compute them into // registers? True for Intel but false for most RISCs @@ -3248,7 +3256,7 @@ // C. c_calling_convention %{ // This is obviously always outgoing - (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); + (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length); %} // Location of native (C/C++) and interpreter return values. This is specified to @@ -6650,6 +6658,7 @@ instruct membar_acquire() %{ match(MemBarAcquire); + match(LoadFence); ins_cost(4*MEMORY_REF_COST); size(0); @@ -6670,6 +6679,7 @@ instruct membar_release() %{ match(MemBarRelease); + match(StoreFence); ins_cost(4*MEMORY_REF_COST); size(0); @@ -9171,7 +9181,7 @@ size(4); ins_cost(BRANCH_COST); format %{ "BA $labl\t! short branch" %} - ins_encode %{ + ins_encode %{ Label* L = $labl$$label; assert(__ use_cbcond(*L), "back to back cbcond"); __ ba_short(*L);