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comparison src/cpu/x86/vm/x86_64.ad @ 124:b130b98db9cf

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6689060: Escape Analysis does not work with Compressed Oops Summary: 64-bits VM crashes with -XX:+AggresiveOpts (Escape Analysis + Compressed Oops) Reviewed-by: never, sgoldman
author kvn
date Wed, 23 Apr 2008 11:20:36 -0700
parents ba764ed4b6f2
children f3de1255b035
comparison
equal deleted inserted replaced
123:9e5a7340635e 124:b130b98db9cf
6078 %{ 6078 %{
6079 match(Set dst (LoadKlass mem)); 6079 match(Set dst (LoadKlass mem));
6080 predicate(n->in(MemNode::Address)->bottom_type()->is_narrow()); 6080 predicate(n->in(MemNode::Address)->bottom_type()->is_narrow());
6081 6081
6082 ins_cost(125); // XXX 6082 ins_cost(125); // XXX
6083 format %{ "movl $dst, $mem\t# compressed class" %} 6083 format %{ "movl $dst, $mem\t# compressed class\n\t"
6084 "decode_heap_oop $dst,$dst" %}
6084 ins_encode %{ 6085 ins_encode %{
6085 Address addr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp); 6086 Address addr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
6086 Register dst = as_Register($dst$$reg); 6087 Register dst = as_Register($dst$$reg);
6087 __ movl(dst, addr); 6088 __ movl(dst, addr);
6088 // klass is never null in the header but this is generated for all 6089 // klass is never null in the header but this is generated for all
6347 %} 6348 %}
6348 6349
6349 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{ 6350 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
6350 match(Set dst src); 6351 match(Set dst src);
6351 effect(KILL cr); 6352 effect(KILL cr);
6352 format %{ "xorq $dst, $src\t# compressed ptr" %} 6353 format %{ "xorq $dst, $src\t# compressed NULL ptr" %}
6353 ins_encode %{ 6354 ins_encode %{
6354 Register dst = $dst$$Register; 6355 Register dst = $dst$$Register;
6355 __ xorq(dst, dst); 6356 __ xorq(dst, dst);
6356 %} 6357 %}
6357 ins_pipe(ialu_reg); 6358 ins_pipe(ialu_reg);
6359 6360
6360 instruct loadConN(rRegN dst, immN src) %{ 6361 instruct loadConN(rRegN dst, immN src) %{
6361 match(Set dst src); 6362 match(Set dst src);
6362 6363
6363 ins_cost(125); 6364 ins_cost(125);
6364 format %{ "movl $dst, $src\t# compressed ptr" %} 6365 format %{ "movq $dst, $src\t# compressed ptr\n\t"
6366 "encode_heap_oop_not_null $dst,$dst" %}
6365 ins_encode %{ 6367 ins_encode %{
6366 address con = (address)$src$$constant; 6368 address con = (address)$src$$constant;
6367 Register dst = $dst$$Register; 6369 Register dst = $dst$$Register;
6368 if (con == NULL) { 6370 if (con == NULL) {
6369 ShouldNotReachHere(); 6371 ShouldNotReachHere();
6994 %} 6996 %}
6995 6997
6996 6998
6997 // Convert oop pointer into compressed form 6999 // Convert oop pointer into compressed form
6998 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{ 7000 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
7001 predicate(n->bottom_type()->is_narrowoop()->make_oopptr()->ptr() != TypePtr::NotNull);
6999 match(Set dst (EncodeP src)); 7002 match(Set dst (EncodeP src));
7000 effect(KILL cr); 7003 effect(KILL cr);
7001 format %{ "encode_heap_oop $dst,$src" %} 7004 format %{ "encode_heap_oop $dst,$src" %}
7002 ins_encode %{ 7005 ins_encode %{
7003 Register s = $src$$Register; 7006 Register s = $src$$Register;
7008 __ encode_heap_oop(d); 7011 __ encode_heap_oop(d);
7009 %} 7012 %}
7010 ins_pipe(ialu_reg_long); 7013 ins_pipe(ialu_reg_long);
7011 %} 7014 %}
7012 7015
7016 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
7017 predicate(n->bottom_type()->is_narrowoop()->make_oopptr()->ptr() == TypePtr::NotNull);
7018 match(Set dst (EncodeP src));
7019 effect(KILL cr);
7020 format %{ "encode_heap_oop_not_null $dst,$src" %}
7021 ins_encode %{
7022 Register s = $src$$Register;
7023 Register d = $dst$$Register;
7024 __ encode_heap_oop_not_null(d, s);
7025 %}
7026 ins_pipe(ialu_reg_long);
7027 %}
7028
7013 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{ 7029 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
7030 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull);
7014 match(Set dst (DecodeN src)); 7031 match(Set dst (DecodeN src));
7015 effect(KILL cr); 7032 effect(KILL cr);
7016 format %{ "decode_heap_oop $dst,$src" %} 7033 format %{ "decode_heap_oop $dst,$src" %}
7017 ins_encode %{ 7034 ins_encode %{
7018 Register s = $src$$Register; 7035 Register s = $src$$Register;
7019 Register d = $dst$$Register; 7036 Register d = $dst$$Register;
7020 if (s != d) { 7037 if (s != d) {
7021 __ movq(d, s); 7038 __ movq(d, s);
7022 } 7039 }
7023 __ decode_heap_oop(d); 7040 __ decode_heap_oop(d);
7041 %}
7042 ins_pipe(ialu_reg_long);
7043 %}
7044
7045 instruct decodeHeapOop_not_null(rRegP dst, rRegN src) %{
7046 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull);
7047 match(Set dst (DecodeN src));
7048 format %{ "decode_heap_oop_not_null $dst,$src" %}
7049 ins_encode %{
7050 Register s = $src$$Register;
7051 Register d = $dst$$Register;
7052 __ decode_heap_oop_not_null(d, s);
7024 %} 7053 %}
7025 ins_pipe(ialu_reg_long); 7054 ins_pipe(ialu_reg_long);
7026 %} 7055 %}
7027 7056
7028 7057