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6964458: Reimplement class meta-data storage to use native memory Summary: Remove PermGen, allocate meta-data in metaspace linked to class loaders, rewrite GC walking, rewrite and rename metadata to be C++ classes Reviewed-by: jmasa, stefank, never, coleenp, kvn, brutisso, mgerdin, dholmes, jrose, twisti, roland Contributed-by: jmasa <jon.masamitsu@oracle.com>, stefank <stefan.karlsson@oracle.com>, mgerdin <mikael.gerdin@oracle.com>, never <tom.rodriguez@oracle.com>
author coleenp
date Sat, 01 Sep 2012 13:25:18 -0400
parents 006050192a5a
children 7eca5de9e0b6
comparison
equal deleted inserted replaced
6724:36d1d483d5d6 6725:da91efe96a93
365 emit_d32(cbuf, disp); // Displacement // R/M byte 365 emit_d32(cbuf, disp); // Displacement // R/M byte
366 } 366 }
367 } 367 }
368 368
369 // rRegI ereg, memory mem) %{ // emit_reg_mem 369 // rRegI ereg, memory mem) %{ // emit_reg_mem
370 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, bool displace_is_oop ) { 370 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, relocInfo::relocType disp_reloc ) {
371 // There is no index & no scale, use form without SIB byte 371 // There is no index & no scale, use form without SIB byte
372 if ((index == 0x4) && 372 if ((index == 0x4) &&
373 (scale == 0) && (base != ESP_enc)) { 373 (scale == 0) && (base != ESP_enc)) {
374 // If no displacement, mode is 0x0; unless base is [EBP] 374 // If no displacement, mode is 0x0; unless base is [EBP]
375 if ( (displace == 0) && (base != EBP_enc) ) { 375 if ( (displace == 0) && (base != EBP_enc) ) {
376 emit_rm(cbuf, 0x0, reg_encoding, base); 376 emit_rm(cbuf, 0x0, reg_encoding, base);
377 } 377 }
378 else { // If 8-bit displacement, mode 0x1 378 else { // If 8-bit displacement, mode 0x1
379 if ((displace >= -128) && (displace <= 127) 379 if ((displace >= -128) && (displace <= 127)
380 && !(displace_is_oop) ) { 380 && (disp_reloc == relocInfo::none) ) {
381 emit_rm(cbuf, 0x1, reg_encoding, base); 381 emit_rm(cbuf, 0x1, reg_encoding, base);
382 emit_d8(cbuf, displace); 382 emit_d8(cbuf, displace);
383 } 383 }
384 else { // If 32-bit displacement 384 else { // If 32-bit displacement
385 if (base == -1) { // Special flag for absolute address 385 if (base == -1) { // Special flag for absolute address
386 emit_rm(cbuf, 0x0, reg_encoding, 0x5); 386 emit_rm(cbuf, 0x0, reg_encoding, 0x5);
387 // (manual lies; no SIB needed here) 387 // (manual lies; no SIB needed here)
388 if ( displace_is_oop ) { 388 if ( disp_reloc != relocInfo::none ) {
389 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1); 389 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
390 } else { 390 } else {
391 emit_d32 (cbuf, displace); 391 emit_d32 (cbuf, displace);
392 } 392 }
393 } 393 }
394 else { // Normal base + offset 394 else { // Normal base + offset
395 emit_rm(cbuf, 0x2, reg_encoding, base); 395 emit_rm(cbuf, 0x2, reg_encoding, base);
396 if ( displace_is_oop ) { 396 if ( disp_reloc != relocInfo::none ) {
397 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1); 397 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
398 } else { 398 } else {
399 emit_d32 (cbuf, displace); 399 emit_d32 (cbuf, displace);
400 } 400 }
401 } 401 }
402 } 402 }
408 emit_rm(cbuf, 0x0, reg_encoding, 0x4); 408 emit_rm(cbuf, 0x0, reg_encoding, 0x4);
409 emit_rm(cbuf, scale, index, base); 409 emit_rm(cbuf, scale, index, base);
410 } 410 }
411 else { // If 8-bit displacement, mode 0x1 411 else { // If 8-bit displacement, mode 0x1
412 if ((displace >= -128) && (displace <= 127) 412 if ((displace >= -128) && (displace <= 127)
413 && !(displace_is_oop) ) { 413 && (disp_reloc == relocInfo::none) ) {
414 emit_rm(cbuf, 0x1, reg_encoding, 0x4); 414 emit_rm(cbuf, 0x1, reg_encoding, 0x4);
415 emit_rm(cbuf, scale, index, base); 415 emit_rm(cbuf, scale, index, base);
416 emit_d8(cbuf, displace); 416 emit_d8(cbuf, displace);
417 } 417 }
418 else { // If 32-bit displacement 418 else { // If 32-bit displacement
421 emit_rm(cbuf, scale, index, 0x04); 421 emit_rm(cbuf, scale, index, 0x04);
422 } else { 422 } else {
423 emit_rm(cbuf, 0x2, reg_encoding, 0x4); 423 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
424 emit_rm(cbuf, scale, index, base); 424 emit_rm(cbuf, scale, index, base);
425 } 425 }
426 if ( displace_is_oop ) { 426 if ( disp_reloc != relocInfo::none ) {
427 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1); 427 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
428 } else { 428 } else {
429 emit_d32 (cbuf, displace); 429 emit_d32 (cbuf, displace);
430 } 430 }
431 } 431 }
432 } 432 }
687 687
688 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg, 688 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg,
689 int opcode, const char *op_str, int size, outputStream* st ) { 689 int opcode, const char *op_str, int size, outputStream* st ) {
690 if( cbuf ) { 690 if( cbuf ) {
691 emit_opcode (*cbuf, opcode ); 691 emit_opcode (*cbuf, opcode );
692 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, false); 692 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, relocInfo::none);
693 #ifndef PRODUCT 693 #ifndef PRODUCT
694 } else if( !do_size ) { 694 } else if( !do_size ) {
695 if( size != 0 ) st->print("\n\t"); 695 if( size != 0 ) st->print("\n\t");
696 if( opcode == 0x8B || opcode == 0x89 ) { // MOV 696 if( opcode == 0x8B || opcode == 0x89 ) { // MOV
697 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset); 697 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
1088 op = 0xD9; 1088 op = 0xD9;
1089 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" ); 1089 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
1090 } 1090 }
1091 if( cbuf ) { 1091 if( cbuf ) {
1092 emit_opcode (*cbuf, op ); 1092 emit_opcode (*cbuf, op );
1093 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, false); 1093 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, relocInfo::none);
1094 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i) 1094 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1095 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] ); 1095 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1096 #ifndef PRODUCT 1096 #ifndef PRODUCT
1097 } else if( !do_size ) { 1097 } else if( !do_size ) {
1098 if( size != 0 ) st->print("\n\t"); 1098 if( size != 0 ) st->print("\n\t");
1258 address base = 1258 address base =
1259 __ start_a_stub(Compile::MAX_stubs_size); 1259 __ start_a_stub(Compile::MAX_stubs_size);
1260 if (base == NULL) return; // CodeBuffer::expand failed 1260 if (base == NULL) return; // CodeBuffer::expand failed
1261 // static stub relocation stores the instruction address of the call 1261 // static stub relocation stores the instruction address of the call
1262 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM32); 1262 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM32);
1263 // static stub relocation also tags the methodOop in the code-stream. 1263 // static stub relocation also tags the Method* in the code-stream.
1264 __ movoop(rbx, (jobject)NULL); // method is zapped till fixup time 1264 __ mov_metadata(rbx, (Metadata*)NULL); // method is zapped till fixup time
1265 // This is recognized as unresolved by relocs/nativeInst/ic code 1265 // This is recognized as unresolved by relocs/nativeInst/ic code
1266 __ jump(RuntimeAddress(__ pc())); 1266 __ jump(RuntimeAddress(__ pc()));
1267 1267
1268 __ end_a_stub(); 1268 __ end_a_stub();
1269 // Update current stubs pointer and restore insts_end. 1269 // Update current stubs pointer and restore insts_end.
1889 emit_java_to_interp(cbuf); 1889 emit_java_to_interp(cbuf);
1890 } 1890 }
1891 %} 1891 %}
1892 1892
1893 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL 1893 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
1894 // !!!!! 1894 MacroAssembler _masm(&cbuf);
1895 // Generate "Mov EAX,0x00", placeholder instruction to load oop-info 1895 __ ic_call((address)$meth$$method);
1896 // emit_call_dynamic_prologue( cbuf );
1897 cbuf.set_insts_mark();
1898 emit_opcode(cbuf, 0xB8 + EAX_enc); // mov EAX,-1
1899 emit_d32_reloc(cbuf, (int)Universe::non_oop_word(), oop_Relocation::spec_for_immediate(), RELOC_IMM32);
1900 address virtual_call_oop_addr = cbuf.insts_mark();
1901 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1902 // who we intended to call.
1903 cbuf.set_insts_mark();
1904 $$$emit8$primary;
1905 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1906 virtual_call_Relocation::spec(virtual_call_oop_addr), RELOC_IMM32 );
1907 %} 1896 %}
1908 1897
1909 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL 1898 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
1910 int disp = in_bytes(methodOopDesc::from_compiled_offset()); 1899 int disp = in_bytes(Method::from_compiled_offset());
1911 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small"); 1900 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1912 1901
1913 // CALL *[EAX+in_bytes(methodOopDesc::from_compiled_code_entry_point_offset())] 1902 // CALL *[EAX+in_bytes(Method::from_compiled_code_entry_point_offset())]
1914 cbuf.set_insts_mark(); 1903 cbuf.set_insts_mark();
1915 $$$emit8$primary; 1904 $$$emit8$primary;
1916 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte 1905 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte
1917 emit_d8(cbuf, disp); // Displacement 1906 emit_d8(cbuf, disp); // Displacement
1918 1907
2125 int reg_encoding = $ereg$$reg; 2114 int reg_encoding = $ereg$$reg;
2126 int base = $mem$$base; 2115 int base = $mem$$base;
2127 int index = $mem$$index; 2116 int index = $mem$$index;
2128 int scale = $mem$$scale; 2117 int scale = $mem$$scale;
2129 int displace = $mem$$disp; 2118 int displace = $mem$$disp;
2130 bool disp_is_oop = $mem->disp_is_oop(); 2119 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2131 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); 2120 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2132 %} 2121 %}
2133 2122
2134 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem 2123 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem
2135 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo 2124 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo
2136 int base = $mem$$base; 2125 int base = $mem$$base;
2137 int index = $mem$$index; 2126 int index = $mem$$index;
2138 int scale = $mem$$scale; 2127 int scale = $mem$$scale;
2139 int displace = $mem$$disp + 4; // Offset is 4 further in memory 2128 int displace = $mem$$disp + 4; // Offset is 4 further in memory
2140 assert( !$mem->disp_is_oop(), "Cannot add 4 to oop" ); 2129 assert( $mem->disp_reloc() == relocInfo::none, "Cannot add 4 to oop" );
2141 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, false/*disp_is_oop*/); 2130 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, relocInfo::none);
2142 %} 2131 %}
2143 2132
2144 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{ 2133 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2145 int r1, r2; 2134 int r1, r2;
2146 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); } 2135 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2190 int reg_encoding = $rm_reg$$reg; 2179 int reg_encoding = $rm_reg$$reg;
2191 int base = $mem$$base; 2180 int base = $mem$$base;
2192 int index = $mem$$index; 2181 int index = $mem$$index;
2193 int scale = $mem$$scale; 2182 int scale = $mem$$scale;
2194 int displace = $mem$$disp + $disp_for_half$$constant; 2183 int displace = $mem$$disp + $disp_for_half$$constant;
2195 bool disp_is_oop = false; 2184 relocInfo::relocType disp_reloc = relocInfo::none;
2196 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); 2185 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2197 %} 2186 %}
2198 2187
2199 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!! 2188 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2200 // 2189 //
2201 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant 2190 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2205 int rm_byte_opcode = $rm_opcode$$constant; 2194 int rm_byte_opcode = $rm_opcode$$constant;
2206 int base = $mem$$base; 2195 int base = $mem$$base;
2207 int index = $mem$$index; 2196 int index = $mem$$index;
2208 int scale = $mem$$scale; 2197 int scale = $mem$$scale;
2209 int displace = $mem$$disp; 2198 int displace = $mem$$disp;
2210 assert( !$mem->disp_is_oop(), "No oops here because no relo info allowed" ); 2199 assert( $mem->disp_reloc() == relocInfo::none, "No oops here because no reloc info allowed" );
2211 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, false); 2200 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, relocInfo::none);
2212 %} 2201 %}
2213 2202
2214 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{ 2203 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2215 int rm_byte_opcode = $rm_opcode$$constant; 2204 int rm_byte_opcode = $rm_opcode$$constant;
2216 int base = $mem$$base; 2205 int base = $mem$$base;
2217 int index = $mem$$index; 2206 int index = $mem$$index;
2218 int scale = $mem$$scale; 2207 int scale = $mem$$scale;
2219 int displace = $mem$$disp; 2208 int displace = $mem$$disp;
2220 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals 2209 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
2221 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop); 2210 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
2222 %} 2211 %}
2223 2212
2224 enc_class RegLea (rRegI dst, rRegI src0, immI src1 ) %{ // emit_reg_lea 2213 enc_class RegLea (rRegI dst, rRegI src0, immI src1 ) %{ // emit_reg_lea
2225 int reg_encoding = $dst$$reg; 2214 int reg_encoding = $dst$$reg;
2226 int base = $src0$$reg; // 0xFFFFFFFF indicates no base 2215 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2227 int index = 0x04; // 0x04 indicates no index 2216 int index = 0x04; // 0x04 indicates no index
2228 int scale = 0x00; // 0x00 indicates no scale 2217 int scale = 0x00; // 0x00 indicates no scale
2229 int displace = $src1$$constant; // 0x00 indicates no displacement 2218 int displace = $src1$$constant; // 0x00 indicates no displacement
2230 bool disp_is_oop = false; 2219 relocInfo::relocType disp_reloc = relocInfo::none;
2231 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); 2220 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2232 %} 2221 %}
2233 2222
2234 enc_class min_enc (rRegI dst, rRegI src) %{ // MIN 2223 enc_class min_enc (rRegI dst, rRegI src) %{ // MIN
2235 // Compare dst,src 2224 // Compare dst,src
2236 emit_opcode(cbuf,0x3B); 2225 emit_opcode(cbuf,0x3B);
2261 int reg_encoding = 0x2; // Just store 2250 int reg_encoding = 0x2; // Just store
2262 int base = $mem$$base; 2251 int base = $mem$$base;
2263 int index = $mem$$index; 2252 int index = $mem$$index;
2264 int scale = $mem$$scale; 2253 int scale = $mem$$scale;
2265 int displace = $mem$$disp; 2254 int displace = $mem$$disp;
2266 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals 2255 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
2267 if( $src$$reg != FPR1L_enc ) { 2256 if( $src$$reg != FPR1L_enc ) {
2268 reg_encoding = 0x3; // Store & pop 2257 reg_encoding = 0x3; // Store & pop
2269 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it) 2258 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2270 emit_d8( cbuf, 0xC0-1+$src$$reg ); 2259 emit_d8( cbuf, 0xC0-1+$src$$reg );
2271 } 2260 }
2272 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand 2261 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2273 emit_opcode(cbuf,$primary); 2262 emit_opcode(cbuf,$primary);
2274 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); 2263 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2275 %} 2264 %}
2276 2265
2277 enc_class neg_reg(rRegI dst) %{ 2266 enc_class neg_reg(rRegI dst) %{
2278 // NEG $dst 2267 // NEG $dst
2279 emit_opcode(cbuf,0xF7); 2268 emit_opcode(cbuf,0xF7);
2319 int reg_encoding = tmpReg; 2308 int reg_encoding = tmpReg;
2320 int base = $mem$$base; 2309 int base = $mem$$base;
2321 int index = $mem$$index; 2310 int index = $mem$$index;
2322 int scale = $mem$$scale; 2311 int scale = $mem$$scale;
2323 int displace = $mem$$disp; 2312 int displace = $mem$$disp;
2324 bool disp_is_oop = $mem->disp_is_oop(); 2313 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2325 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); 2314 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2326 // ADD $p,$tmp 2315 // ADD $p,$tmp
2327 emit_opcode(cbuf,0x03); 2316 emit_opcode(cbuf,0x03);
2328 emit_rm(cbuf, 0x3, $p$$reg, tmpReg); 2317 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2329 %} 2318 %}
2330 2319
3643 int rm_byte_opcode = 0x05; 3632 int rm_byte_opcode = 0x05;
3644 int base = $mem$$base; 3633 int base = $mem$$base;
3645 int index = $mem$$index; 3634 int index = $mem$$index;
3646 int scale = $mem$$scale; 3635 int scale = $mem$$scale;
3647 int displace = $mem$$disp; 3636 int displace = $mem$$disp;
3648 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals 3637 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
3649 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop); 3638 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
3650 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp ); 3639 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
3651 %} 3640 %}
3652 3641
3653 // Volatile Store Long. Must be atomic, so move it into 3642 // Volatile Store Long. Must be atomic, so move it into
3654 // the FP TOS and then do a 64-bit FIST. Has to probe the 3643 // the FP TOS and then do a 64-bit FIST. Has to probe the
3661 int rm_byte_opcode = 0x07; 3650 int rm_byte_opcode = 0x07;
3662 int base = $mem$$base; 3651 int base = $mem$$base;
3663 int index = $mem$$index; 3652 int index = $mem$$index;
3664 int scale = $mem$$scale; 3653 int scale = $mem$$scale;
3665 int displace = $mem$$disp; 3654 int displace = $mem$$disp;
3666 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals 3655 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
3667 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop); 3656 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
3668 %} 3657 %}
3669 3658
3670 // Safepoint Poll. This polls the safepoint page, and causes an 3659 // Safepoint Poll. This polls the safepoint page, and causes an
3671 // exception if it is not readable. Unfortunately, it kills the condition code 3660 // exception if it is not readable. Unfortunately, it kills the condition code
3672 // in the process 3661 // in the process
5815 "POPCNT $tmp, $mem+4\n\t" 5804 "POPCNT $tmp, $mem+4\n\t"
5816 "ADD $dst, $tmp" %} 5805 "ADD $dst, $tmp" %}
5817 ins_encode %{ 5806 ins_encode %{
5818 //__ popcntl($dst$$Register, $mem$$Address$$first); 5807 //__ popcntl($dst$$Register, $mem$$Address$$first);
5819 //__ popcntl($tmp$$Register, $mem$$Address$$second); 5808 //__ popcntl($tmp$$Register, $mem$$Address$$second);
5820 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false)); 5809 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none));
5821 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false)); 5810 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none));
5822 __ addl($dst$$Register, $tmp$$Register); 5811 __ addl($dst$$Register, $tmp$$Register);
5823 %} 5812 %}
5824 ins_pipe(ialu_reg); 5813 ins_pipe(ialu_reg);
5825 %} 5814 %}
5826 5815
6183 ins_cost(250); 6172 ins_cost(250);
6184 format %{ "MOV $dst.lo,$mem\t# long\n\t" 6173 format %{ "MOV $dst.lo,$mem\t# long\n\t"
6185 "MOV $dst.hi,$mem+4" %} 6174 "MOV $dst.hi,$mem+4" %}
6186 6175
6187 ins_encode %{ 6176 ins_encode %{
6188 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false); 6177 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
6189 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false); 6178 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none);
6190 __ movl($dst$$Register, Amemlo); 6179 __ movl($dst$$Register, Amemlo);
6191 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi); 6180 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi);
6192 %} 6181 %}
6193 6182
6194 ins_pipe(ialu_reg_long_mem); 6183 ins_pipe(ialu_reg_long_mem);
11793 11782
11794 // Compare raw pointer (used in out-of-heap check). 11783 // Compare raw pointer (used in out-of-heap check).
11795 // Only works because non-oop pointers must be raw pointers 11784 // Only works because non-oop pointers must be raw pointers
11796 // and raw pointers have no anti-dependencies. 11785 // and raw pointers have no anti-dependencies.
11797 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{ 11786 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
11798 predicate( !n->in(2)->in(2)->bottom_type()->isa_oop_ptr() ); 11787 predicate( n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none );
11799 match(Set cr (CmpP op1 (LoadP op2))); 11788 match(Set cr (CmpP op1 (LoadP op2)));
11800 11789
11801 format %{ "CMPu $op1,$op2" %} 11790 format %{ "CMPu $op1,$op2" %}
11802 opcode(0x3B); /* Opcode 3B /r */ 11791 opcode(0x3B); /* Opcode 3B /r */
11803 ins_encode( OpcP, RegMem( op1, op2) ); 11792 ins_encode( OpcP, RegMem( op1, op2) );