Mercurial > hg > truffle
annotate src/cpu/x86/vm/x86_32.ad @ 6725:da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
Summary: Remove PermGen, allocate meta-data in metaspace linked to class loaders, rewrite GC walking, rewrite and rename metadata to be C++ classes
Reviewed-by: jmasa, stefank, never, coleenp, kvn, brutisso, mgerdin, dholmes, jrose, twisti, roland
Contributed-by: jmasa <jon.masamitsu@oracle.com>, stefank <stefan.karlsson@oracle.com>, mgerdin <mikael.gerdin@oracle.com>, never <tom.rodriguez@oracle.com>
| author | coleenp |
|---|---|
| date | Sat, 01 Sep 2012 13:25:18 -0400 |
| parents | 006050192a5a |
| children | 7eca5de9e0b6 |
| rev | line source |
|---|---|
| 0 | 1 // |
| 4950 | 2 // Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 // | |
| 5 // This code is free software; you can redistribute it and/or modify it | |
| 6 // under the terms of the GNU General Public License version 2 only, as | |
| 7 // published by the Free Software Foundation. | |
| 8 // | |
| 9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 // version 2 for more details (a copy is included in the LICENSE file that | |
| 13 // accompanied this code). | |
| 14 // | |
| 15 // You should have received a copy of the GNU General Public License version | |
| 16 // 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 // | |
|
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19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 // or visit www.oracle.com if you need additional information or have any |
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21 // questions. |
| 0 | 22 // |
| 23 // | |
| 24 | |
| 25 // X86 Architecture Description File | |
| 26 | |
| 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ | |
| 28 // This information is used by the matcher and the register allocator to | |
| 29 // describe individual registers and classes of registers within the target | |
| 30 // archtecture. | |
| 31 | |
| 32 register %{ | |
| 33 //----------Architecture Description Register Definitions---------------------- | |
| 34 // General Registers | |
| 35 // "reg_def" name ( register save type, C convention save type, | |
| 36 // ideal register type, encoding ); | |
| 37 // Register Save Types: | |
| 38 // | |
| 39 // NS = No-Save: The register allocator assumes that these registers | |
| 40 // can be used without saving upon entry to the method, & | |
| 41 // that they do not need to be saved at call sites. | |
| 42 // | |
| 43 // SOC = Save-On-Call: The register allocator assumes that these registers | |
| 44 // can be used without saving upon entry to the method, | |
| 45 // but that they must be saved at call sites. | |
| 46 // | |
| 47 // SOE = Save-On-Entry: The register allocator assumes that these registers | |
| 48 // must be saved before using them upon entry to the | |
| 49 // method, but they do not need to be saved at call | |
| 50 // sites. | |
| 51 // | |
| 52 // AS = Always-Save: The register allocator assumes that these registers | |
| 53 // must be saved before using them upon entry to the | |
| 54 // method, & that they must be saved at call sites. | |
| 55 // | |
| 56 // Ideal Register Type is used to determine how to save & restore a | |
| 57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get | |
| 58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. | |
| 59 // | |
| 60 // The encoding number is the actual bit-pattern placed into the opcodes. | |
| 61 | |
| 62 // General Registers | |
| 63 // Previously set EBX, ESI, and EDI as save-on-entry for java code | |
| 64 // Turn off SOE in java-code due to frequent use of uncommon-traps. | |
| 65 // Now that allocator is better, turn on ESI and EDI as SOE registers. | |
| 66 | |
| 67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()); | |
| 68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()); | |
| 69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()); | |
| 70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()); | |
| 71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code | |
| 72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg()); | |
| 73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()); | |
| 74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg()); | |
| 75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg()); | |
| 76 | |
| 77 // Float registers. We treat TOS/FPR0 special. It is invisible to the | |
| 78 // allocator, and only shows up in the encodings. | |
| 79 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad()); | |
| 80 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad()); | |
| 81 // Ok so here's the trick FPR1 is really st(0) except in the midst | |
| 82 // of emission of assembly for a machnode. During the emission the fpu stack | |
| 83 // is pushed making FPR1 == st(1) temporarily. However at any safepoint | |
| 84 // the stack will not have this element so FPR1 == st(0) from the | |
| 85 // oopMap viewpoint. This same weirdness with numbering causes | |
| 86 // instruction encoding to have to play games with the register | |
| 87 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation | |
| 88 // where it does flt->flt moves to see an example | |
| 89 // | |
| 90 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()); | |
| 91 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next()); | |
| 92 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()); | |
| 93 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next()); | |
| 94 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()); | |
| 95 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next()); | |
| 96 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()); | |
| 97 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next()); | |
| 98 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()); | |
| 99 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next()); | |
| 100 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()); | |
| 101 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next()); | |
| 102 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()); | |
| 103 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next()); | |
| 104 | |
| 105 // Specify priority of register selection within phases of register | |
| 106 // allocation. Highest priority is first. A useful heuristic is to | |
| 107 // give registers a low priority when they are required by machine | |
| 108 // instructions, like EAX and EDX. Registers which are used as | |
| 605 | 109 // pairs must fall on an even boundary (witness the FPR#L's in this list). |
| 0 | 110 // For the Intel integer registers, the equivalent Long pairs are |
| 111 // EDX:EAX, EBX:ECX, and EDI:EBP. | |
| 112 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP, | |
| 113 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H, | |
| 114 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H, | |
| 115 FPR6L, FPR6H, FPR7L, FPR7H ); | |
| 116 | |
| 117 | |
| 118 //----------Architecture Description Register Classes-------------------------- | |
| 119 // Several register classes are automatically defined based upon information in | |
| 120 // this architecture description. | |
| 121 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ ) | |
| 122 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ ) | |
| 123 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ ) | |
| 124 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) | |
| 125 // | |
| 126 // Class for all registers | |
| 127 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP); | |
| 128 // Class for general registers | |
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129 reg_class int_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX); |
| 0 | 130 // Class for general registers which may be used for implicit null checks on win95 |
| 131 // Also safe for use by tailjump. We don't want to allocate in rbp, | |
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132 reg_class int_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX); |
| 0 | 133 // Class of "X" registers |
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134 reg_class int_x_reg(EBX, ECX, EDX, EAX); |
| 0 | 135 // Class of registers that can appear in an address with no offset. |
| 136 // EBP and ESP require an extra instruction byte for zero offset. | |
| 137 // Used in fast-unlock | |
| 138 reg_class p_reg(EDX, EDI, ESI, EBX); | |
| 139 // Class for general registers not including ECX | |
| 140 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX); | |
| 141 // Class for general registers not including EAX | |
| 142 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX); | |
| 143 // Class for general registers not including EAX or EBX. | |
| 144 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP); | |
| 145 // Class of EAX (for multiply and divide operations) | |
| 146 reg_class eax_reg(EAX); | |
| 147 // Class of EBX (for atomic add) | |
| 148 reg_class ebx_reg(EBX); | |
| 149 // Class of ECX (for shift and JCXZ operations and cmpLTMask) | |
| 150 reg_class ecx_reg(ECX); | |
| 151 // Class of EDX (for multiply and divide operations) | |
| 152 reg_class edx_reg(EDX); | |
| 153 // Class of EDI (for synchronization) | |
| 154 reg_class edi_reg(EDI); | |
| 155 // Class of ESI (for synchronization) | |
| 156 reg_class esi_reg(ESI); | |
| 157 // Singleton class for interpreter's stack pointer | |
| 158 reg_class ebp_reg(EBP); | |
| 159 // Singleton class for stack pointer | |
| 160 reg_class sp_reg(ESP); | |
| 161 // Singleton class for instruction pointer | |
| 162 // reg_class ip_reg(EIP); | |
| 163 // Class of integer register pairs | |
| 164 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI ); | |
| 165 // Class of integer register pairs that aligns with calling convention | |
| 166 reg_class eadx_reg( EAX,EDX ); | |
| 167 reg_class ebcx_reg( ECX,EBX ); | |
| 168 // Not AX or DX, used in divides | |
| 169 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP ); | |
| 170 | |
| 171 // Floating point registers. Notice FPR0 is not a choice. | |
| 172 // FPR0 is not ever allocated; we use clever encodings to fake | |
| 173 // a 2-address instructions out of Intels FP stack. | |
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174 reg_class fp_flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L ); |
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175 |
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176 reg_class fp_dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H, |
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177 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H, |
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178 FPR7L,FPR7H ); |
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179 |
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180 reg_class fp_flt_reg0( FPR1L ); |
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181 reg_class fp_dbl_reg0( FPR1L,FPR1H ); |
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182 reg_class fp_dbl_reg1( FPR2L,FPR2H ); |
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183 reg_class fp_dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H, |
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184 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H ); |
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185 |
| 0 | 186 %} |
| 187 | |
| 188 | |
| 189 //----------SOURCE BLOCK------------------------------------------------------- | |
| 190 // This is a block of C++ code which provides values, functions, and | |
| 191 // definitions necessary in the rest of the architecture description | |
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192 source_hpp %{ |
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193 // Must be visible to the DFA in dfa_x86_32.cpp |
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194 extern bool is_operand_hi32_zero(Node* n); |
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195 %} |
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196 |
| 0 | 197 source %{ |
| 304 | 198 #define RELOC_IMM32 Assembler::imm_operand |
| 0 | 199 #define RELOC_DISP32 Assembler::disp32_operand |
| 200 | |
| 201 #define __ _masm. | |
| 202 | |
| 203 // How to find the high register of a Long pair, given the low register | |
| 204 #define HIGH_FROM_LOW(x) ((x)+2) | |
| 205 | |
| 206 // These masks are used to provide 128-bit aligned bitmasks to the XMM | |
| 207 // instructions, to allow sign-masking or sign-bit flipping. They allow | |
| 208 // fast versions of NegF/NegD and AbsF/AbsD. | |
| 209 | |
| 210 // Note: 'double' and 'long long' have 32-bits alignment on x86. | |
| 211 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { | |
| 212 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address | |
| 213 // of 128-bits operands for SSE instructions. | |
| 214 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF))); | |
| 215 // Store the value to a 128-bits operand. | |
| 216 operand[0] = lo; | |
| 217 operand[1] = hi; | |
| 218 return operand; | |
| 219 } | |
| 220 | |
| 221 // Buffer for 128-bits masks used by SSE instructions. | |
| 222 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) | |
| 223 | |
| 224 // Static initialization during VM startup. | |
| 225 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); | |
| 226 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); | |
| 227 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000)); | |
| 228 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000)); | |
| 229 | |
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230 // Offset hacking within calls. |
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231 static int pre_call_FPU_size() { |
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232 if (Compile::current()->in_24_bit_fp_mode()) |
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233 return 6; // fldcw |
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234 return 0; |
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235 } |
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236 |
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237 static int preserve_SP_size() { |
| 4759 | 238 return 2; // op, rm(reg/reg) |
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239 } |
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240 |
| 0 | 241 // !!!!! Special hack to get all type of calls to specify the byte offset |
| 242 // from the start of the call to the point where the return address | |
| 243 // will point. | |
| 244 int MachCallStaticJavaNode::ret_addr_offset() { | |
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245 int offset = 5 + pre_call_FPU_size(); // 5 bytes from start of call to where return address points |
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246 if (_method_handle_invoke) |
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247 offset += preserve_SP_size(); |
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248 return offset; |
| 0 | 249 } |
| 250 | |
| 251 int MachCallDynamicJavaNode::ret_addr_offset() { | |
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252 return 10 + pre_call_FPU_size(); // 10 bytes from start of call to where return address points |
| 0 | 253 } |
| 254 | |
| 255 static int sizeof_FFree_Float_Stack_All = -1; | |
| 256 | |
| 257 int MachCallRuntimeNode::ret_addr_offset() { | |
| 258 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already"); | |
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259 return sizeof_FFree_Float_Stack_All + 5 + pre_call_FPU_size(); |
| 0 | 260 } |
| 261 | |
| 262 // Indicate if the safepoint node needs the polling page as an input. | |
| 263 // Since x86 does have absolute addressing, it doesn't. | |
| 264 bool SafePointNode::needs_polling_address_input() { | |
| 265 return false; | |
| 266 } | |
| 267 | |
| 268 // | |
| 269 // Compute padding required for nodes which need alignment | |
| 270 // | |
| 271 | |
| 272 // The address of the call instruction needs to be 4-byte aligned to | |
| 273 // ensure that it does not span a cache line so that it can be patched. | |
| 274 int CallStaticJavaDirectNode::compute_padding(int current_offset) const { | |
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275 current_offset += pre_call_FPU_size(); // skip fldcw, if any |
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276 current_offset += 1; // skip call opcode byte |
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277 return round_to(current_offset, alignment_required()) - current_offset; |
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278 } |
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279 |
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280 // The address of the call instruction needs to be 4-byte aligned to |
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281 // ensure that it does not span a cache line so that it can be patched. |
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282 int CallStaticJavaHandleNode::compute_padding(int current_offset) const { |
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283 current_offset += pre_call_FPU_size(); // skip fldcw, if any |
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284 current_offset += preserve_SP_size(); // skip mov rbp, rsp |
| 0 | 285 current_offset += 1; // skip call opcode byte |
| 286 return round_to(current_offset, alignment_required()) - current_offset; | |
| 287 } | |
| 288 | |
| 289 // The address of the call instruction needs to be 4-byte aligned to | |
| 290 // ensure that it does not span a cache line so that it can be patched. | |
| 291 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const { | |
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292 current_offset += pre_call_FPU_size(); // skip fldcw, if any |
| 0 | 293 current_offset += 5; // skip MOV instruction |
| 294 current_offset += 1; // skip call opcode byte | |
| 295 return round_to(current_offset, alignment_required()) - current_offset; | |
| 296 } | |
| 297 | |
| 298 // EMIT_RM() | |
| 299 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) { | |
| 300 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3); | |
| 1748 | 301 cbuf.insts()->emit_int8(c); |
| 0 | 302 } |
| 303 | |
| 304 // EMIT_CC() | |
| 305 void emit_cc(CodeBuffer &cbuf, int f1, int f2) { | |
| 306 unsigned char c = (unsigned char)( f1 | f2 ); | |
| 1748 | 307 cbuf.insts()->emit_int8(c); |
| 0 | 308 } |
| 309 | |
| 310 // EMIT_OPCODE() | |
| 311 void emit_opcode(CodeBuffer &cbuf, int code) { | |
| 1748 | 312 cbuf.insts()->emit_int8((unsigned char) code); |
| 0 | 313 } |
| 314 | |
| 315 // EMIT_OPCODE() w/ relocation information | |
| 316 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) { | |
| 1748 | 317 cbuf.relocate(cbuf.insts_mark() + offset, reloc); |
| 0 | 318 emit_opcode(cbuf, code); |
| 319 } | |
| 320 | |
| 321 // EMIT_D8() | |
| 322 void emit_d8(CodeBuffer &cbuf, int d8) { | |
| 1748 | 323 cbuf.insts()->emit_int8((unsigned char) d8); |
| 0 | 324 } |
| 325 | |
| 326 // EMIT_D16() | |
| 327 void emit_d16(CodeBuffer &cbuf, int d16) { | |
| 1748 | 328 cbuf.insts()->emit_int16(d16); |
| 0 | 329 } |
| 330 | |
| 331 // EMIT_D32() | |
| 332 void emit_d32(CodeBuffer &cbuf, int d32) { | |
| 1748 | 333 cbuf.insts()->emit_int32(d32); |
| 0 | 334 } |
| 335 | |
| 336 // emit 32 bit value and construct relocation entry from relocInfo::relocType | |
| 337 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc, | |
| 338 int format) { | |
| 1748 | 339 cbuf.relocate(cbuf.insts_mark(), reloc, format); |
| 340 cbuf.insts()->emit_int32(d32); | |
| 0 | 341 } |
| 342 | |
| 343 // emit 32 bit value and construct relocation entry from RelocationHolder | |
| 344 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec, | |
| 345 int format) { | |
| 346 #ifdef ASSERT | |
| 347 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) { | |
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348 assert(oop(d32)->is_oop() && (ScavengeRootsInCode || !oop(d32)->is_scavengable()), "cannot embed scavengable oops in code"); |
| 0 | 349 } |
| 350 #endif | |
| 1748 | 351 cbuf.relocate(cbuf.insts_mark(), rspec, format); |
| 352 cbuf.insts()->emit_int32(d32); | |
| 0 | 353 } |
| 354 | |
| 355 // Access stack slot for load or store | |
| 356 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) { | |
| 357 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src]) | |
| 358 if( -128 <= disp && disp <= 127 ) { | |
| 359 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte | |
| 360 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte | |
| 361 emit_d8 (cbuf, disp); // Displacement // R/M byte | |
| 362 } else { | |
| 363 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte | |
| 364 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte | |
| 365 emit_d32(cbuf, disp); // Displacement // R/M byte | |
| 366 } | |
| 367 } | |
| 368 | |
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369 // rRegI ereg, memory mem) %{ // emit_reg_mem |
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370 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, relocInfo::relocType disp_reloc ) { |
| 0 | 371 // There is no index & no scale, use form without SIB byte |
| 372 if ((index == 0x4) && | |
| 373 (scale == 0) && (base != ESP_enc)) { | |
| 374 // If no displacement, mode is 0x0; unless base is [EBP] | |
| 375 if ( (displace == 0) && (base != EBP_enc) ) { | |
| 376 emit_rm(cbuf, 0x0, reg_encoding, base); | |
| 377 } | |
| 378 else { // If 8-bit displacement, mode 0x1 | |
| 379 if ((displace >= -128) && (displace <= 127) | |
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380 && (disp_reloc == relocInfo::none) ) { |
| 0 | 381 emit_rm(cbuf, 0x1, reg_encoding, base); |
| 382 emit_d8(cbuf, displace); | |
| 383 } | |
| 384 else { // If 32-bit displacement | |
| 385 if (base == -1) { // Special flag for absolute address | |
| 386 emit_rm(cbuf, 0x0, reg_encoding, 0x5); | |
| 387 // (manual lies; no SIB needed here) | |
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388 if ( disp_reloc != relocInfo::none ) { |
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389 emit_d32_reloc(cbuf, displace, disp_reloc, 1); |
| 0 | 390 } else { |
| 391 emit_d32 (cbuf, displace); | |
| 392 } | |
| 393 } | |
| 394 else { // Normal base + offset | |
| 395 emit_rm(cbuf, 0x2, reg_encoding, base); | |
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396 if ( disp_reloc != relocInfo::none ) { |
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397 emit_d32_reloc(cbuf, displace, disp_reloc, 1); |
| 0 | 398 } else { |
| 399 emit_d32 (cbuf, displace); | |
| 400 } | |
| 401 } | |
| 402 } | |
| 403 } | |
| 404 } | |
| 405 else { // Else, encode with the SIB byte | |
| 406 // If no displacement, mode is 0x0; unless base is [EBP] | |
| 407 if (displace == 0 && (base != EBP_enc)) { // If no displacement | |
| 408 emit_rm(cbuf, 0x0, reg_encoding, 0x4); | |
| 409 emit_rm(cbuf, scale, index, base); | |
| 410 } | |
| 411 else { // If 8-bit displacement, mode 0x1 | |
| 412 if ((displace >= -128) && (displace <= 127) | |
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413 && (disp_reloc == relocInfo::none) ) { |
| 0 | 414 emit_rm(cbuf, 0x1, reg_encoding, 0x4); |
| 415 emit_rm(cbuf, scale, index, base); | |
| 416 emit_d8(cbuf, displace); | |
| 417 } | |
| 418 else { // If 32-bit displacement | |
| 419 if (base == 0x04 ) { | |
| 420 emit_rm(cbuf, 0x2, reg_encoding, 0x4); | |
| 421 emit_rm(cbuf, scale, index, 0x04); | |
| 422 } else { | |
| 423 emit_rm(cbuf, 0x2, reg_encoding, 0x4); | |
| 424 emit_rm(cbuf, scale, index, base); | |
| 425 } | |
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426 if ( disp_reloc != relocInfo::none ) { |
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427 emit_d32_reloc(cbuf, displace, disp_reloc, 1); |
| 0 | 428 } else { |
| 429 emit_d32 (cbuf, displace); | |
| 430 } | |
| 431 } | |
| 432 } | |
| 433 } | |
| 434 } | |
| 435 | |
| 436 | |
| 437 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) { | |
| 438 if( dst_encoding == src_encoding ) { | |
| 439 // reg-reg copy, use an empty encoding | |
| 440 } else { | |
| 441 emit_opcode( cbuf, 0x8B ); | |
| 442 emit_rm(cbuf, 0x3, dst_encoding, src_encoding ); | |
| 443 } | |
| 444 } | |
| 445 | |
| 4759 | 446 void emit_cmpfp_fixup(MacroAssembler& _masm) { |
| 447 Label exit; | |
| 448 __ jccb(Assembler::noParity, exit); | |
| 449 __ pushf(); | |
| 450 // | |
| 451 // comiss/ucomiss instructions set ZF,PF,CF flags and | |
| 452 // zero OF,AF,SF for NaN values. | |
| 453 // Fixup flags by zeroing ZF,PF so that compare of NaN | |
| 454 // values returns 'less than' result (CF is set). | |
| 455 // Leave the rest of flags unchanged. | |
| 456 // | |
| 457 // 7 6 5 4 3 2 1 0 | |
| 458 // |S|Z|r|A|r|P|r|C| (r - reserved bit) | |
| 459 // 0 0 1 0 1 0 1 1 (0x2B) | |
| 460 // | |
| 461 __ andl(Address(rsp, 0), 0xffffff2b); | |
| 462 __ popf(); | |
| 463 __ bind(exit); | |
| 464 } | |
| 465 | |
| 466 void emit_cmpfp3(MacroAssembler& _masm, Register dst) { | |
| 467 Label done; | |
| 468 __ movl(dst, -1); | |
| 469 __ jcc(Assembler::parity, done); | |
| 470 __ jcc(Assembler::below, done); | |
| 471 __ setb(Assembler::notEqual, dst); | |
| 472 __ movzbl(dst, dst); | |
| 473 __ bind(done); | |
| 0 | 474 } |
| 475 | |
| 476 | |
| 477 //============================================================================= | |
| 2008 | 478 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty; |
| 479 | |
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480 int Compile::ConstantTable::calculate_table_base_offset() const { |
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481 return 0; // absolute addressing, no offset |
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482 } |
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483 |
| 2008 | 484 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { |
| 485 // Empty encoding | |
| 486 } | |
| 487 | |
| 488 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const { | |
| 489 return 0; | |
| 490 } | |
| 491 | |
| 492 #ifndef PRODUCT | |
| 493 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { | |
| 494 st->print("# MachConstantBaseNode (empty encoding)"); | |
| 495 } | |
| 496 #endif | |
| 497 | |
| 498 | |
| 499 //============================================================================= | |
| 0 | 500 #ifndef PRODUCT |
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501 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const { |
| 0 | 502 Compile* C = ra_->C; |
| 503 | |
| 504 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 505 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
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506 // Remove wordSize for return addr which is already pushed. |
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507 framesize -= wordSize; |
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508 |
| 0 | 509 if (C->need_stack_bang(framesize)) { |
| 510 framesize -= wordSize; | |
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511 st->print("# stack bang"); |
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512 st->print("\n\t"); |
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513 st->print("PUSH EBP\t# Save EBP"); |
| 0 | 514 if (framesize) { |
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515 st->print("\n\t"); |
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516 st->print("SUB ESP, #%d\t# Create frame",framesize); |
| 0 | 517 } |
| 518 } else { | |
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519 st->print("SUB ESP, #%d\t# Create frame",framesize); |
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520 st->print("\n\t"); |
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521 framesize -= wordSize; |
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522 st->print("MOV [ESP + #%d], EBP\t# Save EBP",framesize); |
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523 } |
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524 |
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525 if (VerifyStackAtCalls) { |
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526 st->print("\n\t"); |
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527 framesize -= wordSize; |
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528 st->print("MOV [ESP + #%d], 0xBADB100D\t# Majik cookie for stack depth check",framesize); |
| 0 | 529 } |
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530 |
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531 if( C->in_24_bit_fp_mode() ) { |
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532 st->print("\n\t"); |
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533 st->print("FLDCW \t# load 24 bit fpu control word"); |
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534 } |
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535 if (UseSSE >= 2 && VerifyFPU) { |
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536 st->print("\n\t"); |
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537 st->print("# verify FPU stack (must be clean on entry)"); |
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538 } |
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539 |
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540 #ifdef ASSERT |
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541 if (VerifyStackAtCalls) { |
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542 st->print("\n\t"); |
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543 st->print("# stack alignment check"); |
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544 } |
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545 #endif |
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546 st->cr(); |
| 0 | 547 } |
| 548 #endif | |
| 549 | |
| 550 | |
| 551 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 552 Compile* C = ra_->C; | |
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553 MacroAssembler _masm(&cbuf); |
| 0 | 554 |
| 555 int framesize = C->frame_slots() << LogBytesPerInt; | |
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556 |
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557 __ verified_entry(framesize, C->need_stack_bang(framesize), C->in_24_bit_fp_mode()); |
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558 |
| 1748 | 559 C->set_frame_complete(cbuf.insts_size()); |
| 0 | 560 |
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561 if (C->has_mach_constant_base_node()) { |
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562 // NOTE: We set the table base offset here because users might be |
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563 // emitted before MachConstantBaseNode. |
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564 Compile::ConstantTable& constant_table = C->constant_table(); |
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565 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset()); |
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566 } |
| 0 | 567 } |
| 568 | |
| 569 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { | |
| 570 return MachNode::size(ra_); // too many variables; just compute it the hard way | |
| 571 } | |
| 572 | |
| 573 int MachPrologNode::reloc() const { | |
| 574 return 0; // a large enough number | |
| 575 } | |
| 576 | |
| 577 //============================================================================= | |
| 578 #ifndef PRODUCT | |
| 579 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { | |
| 580 Compile *C = ra_->C; | |
| 581 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 582 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 583 // Remove two words for return addr and rbp, | |
| 584 framesize -= 2*wordSize; | |
| 585 | |
| 586 if( C->in_24_bit_fp_mode() ) { | |
| 587 st->print("FLDCW standard control word"); | |
| 588 st->cr(); st->print("\t"); | |
| 589 } | |
| 590 if( framesize ) { | |
| 591 st->print("ADD ESP,%d\t# Destroy frame",framesize); | |
| 592 st->cr(); st->print("\t"); | |
| 593 } | |
| 594 st->print_cr("POPL EBP"); st->print("\t"); | |
| 595 if( do_polling() && C->is_method_compilation() ) { | |
| 596 st->print("TEST PollPage,EAX\t! Poll Safepoint"); | |
| 597 st->cr(); st->print("\t"); | |
| 598 } | |
| 599 } | |
| 600 #endif | |
| 601 | |
| 602 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 603 Compile *C = ra_->C; | |
| 604 | |
| 605 // If method set FPU control word, restore to standard control word | |
| 606 if( C->in_24_bit_fp_mode() ) { | |
| 607 MacroAssembler masm(&cbuf); | |
| 608 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
| 609 } | |
| 610 | |
| 611 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 612 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 613 // Remove two words for return addr and rbp, | |
| 614 framesize -= 2*wordSize; | |
| 615 | |
| 616 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here | |
| 617 | |
| 618 if( framesize >= 128 ) { | |
| 619 emit_opcode(cbuf, 0x81); // add SP, #framesize | |
| 620 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 621 emit_d32(cbuf, framesize); | |
| 622 } | |
| 623 else if( framesize ) { | |
| 624 emit_opcode(cbuf, 0x83); // add SP, #framesize | |
| 625 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 626 emit_d8(cbuf, framesize); | |
| 627 } | |
| 628 | |
| 629 emit_opcode(cbuf, 0x58 | EBP_enc); | |
| 630 | |
| 631 if( do_polling() && C->is_method_compilation() ) { | |
| 1748 | 632 cbuf.relocate(cbuf.insts_end(), relocInfo::poll_return_type, 0); |
| 0 | 633 emit_opcode(cbuf,0x85); |
| 634 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX | |
| 635 emit_d32(cbuf, (intptr_t)os::get_polling_page()); | |
| 636 } | |
| 637 } | |
| 638 | |
| 639 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { | |
| 640 Compile *C = ra_->C; | |
| 641 // If method set FPU control word, restore to standard control word | |
| 642 int size = C->in_24_bit_fp_mode() ? 6 : 0; | |
| 643 if( do_polling() && C->is_method_compilation() ) size += 6; | |
| 644 | |
| 645 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 646 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 647 // Remove two words for return addr and rbp, | |
| 648 framesize -= 2*wordSize; | |
| 649 | |
| 650 size++; // popl rbp, | |
| 651 | |
| 652 if( framesize >= 128 ) { | |
| 653 size += 6; | |
| 654 } else { | |
| 655 size += framesize ? 3 : 0; | |
| 656 } | |
| 657 return size; | |
| 658 } | |
| 659 | |
| 660 int MachEpilogNode::reloc() const { | |
| 661 return 0; // a large enough number | |
| 662 } | |
| 663 | |
| 664 const Pipeline * MachEpilogNode::pipeline() const { | |
| 665 return MachNode::pipeline_class(); | |
| 666 } | |
| 667 | |
| 668 int MachEpilogNode::safepoint_offset() const { return 0; } | |
| 669 | |
| 670 //============================================================================= | |
| 671 | |
| 672 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack }; | |
| 673 static enum RC rc_class( OptoReg::Name reg ) { | |
| 674 | |
| 675 if( !OptoReg::is_valid(reg) ) return rc_bad; | |
| 676 if (OptoReg::is_stack(reg)) return rc_stack; | |
| 677 | |
| 678 VMReg r = OptoReg::as_VMReg(reg); | |
| 679 if (r->is_Register()) return rc_int; | |
| 680 if (r->is_FloatRegister()) { | |
| 681 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode"); | |
| 682 return rc_float; | |
| 683 } | |
| 684 assert(r->is_XMMRegister(), "must be"); | |
| 685 return rc_xmm; | |
| 686 } | |
| 687 | |
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688 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg, |
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689 int opcode, const char *op_str, int size, outputStream* st ) { |
| 0 | 690 if( cbuf ) { |
| 691 emit_opcode (*cbuf, opcode ); | |
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692 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, relocInfo::none); |
| 0 | 693 #ifndef PRODUCT |
| 694 } else if( !do_size ) { | |
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695 if( size != 0 ) st->print("\n\t"); |
| 0 | 696 if( opcode == 0x8B || opcode == 0x89 ) { // MOV |
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697 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset); |
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698 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]); |
| 0 | 699 } else { // FLD, FST, PUSH, POP |
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700 st->print("%s [ESP + #%d]",op_str,offset); |
| 0 | 701 } |
| 702 #endif | |
| 703 } | |
| 704 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); | |
| 705 return size+3+offset_size; | |
| 706 } | |
| 707 | |
| 708 // Helper for XMM registers. Extra opcode bits, limited syntax. | |
| 709 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load, | |
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710 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) { |
| 4759 | 711 if (cbuf) { |
| 712 MacroAssembler _masm(cbuf); | |
| 713 if (reg_lo+1 == reg_hi) { // double move? | |
| 714 if (is_load) { | |
| 715 __ movdbl(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset)); | |
| 716 } else { | |
| 717 __ movdbl(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo])); | |
| 718 } | |
| 0 | 719 } else { |
| 4759 | 720 if (is_load) { |
| 721 __ movflt(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset)); | |
| 722 } else { | |
| 723 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo])); | |
| 724 } | |
| 0 | 725 } |
| 726 #ifndef PRODUCT | |
| 4759 | 727 } else if (!do_size) { |
| 728 if (size != 0) st->print("\n\t"); | |
| 729 if (reg_lo+1 == reg_hi) { // double move? | |
| 730 if (is_load) st->print("%s %s,[ESP + #%d]", | |
| 731 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD", | |
| 732 Matcher::regName[reg_lo], offset); | |
| 733 else st->print("MOVSD [ESP + #%d],%s", | |
| 734 offset, Matcher::regName[reg_lo]); | |
| 0 | 735 } else { |
| 4759 | 736 if (is_load) st->print("MOVSS %s,[ESP + #%d]", |
| 737 Matcher::regName[reg_lo], offset); | |
| 738 else st->print("MOVSS [ESP + #%d],%s", | |
| 739 offset, Matcher::regName[reg_lo]); | |
| 0 | 740 } |
| 741 #endif | |
| 742 } | |
| 743 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); | |
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744 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix. |
| 0 | 745 return size+5+offset_size; |
| 746 } | |
| 747 | |
| 748 | |
| 749 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, | |
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750 int src_hi, int dst_hi, int size, outputStream* st ) { |
| 4759 | 751 if (cbuf) { |
| 752 MacroAssembler _masm(cbuf); | |
| 753 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move? | |
| 754 __ movdbl(as_XMMRegister(Matcher::_regEncode[dst_lo]), | |
| 755 as_XMMRegister(Matcher::_regEncode[src_lo])); | |
| 756 } else { | |
| 757 __ movflt(as_XMMRegister(Matcher::_regEncode[dst_lo]), | |
| 758 as_XMMRegister(Matcher::_regEncode[src_lo])); | |
| 759 } | |
| 0 | 760 #ifndef PRODUCT |
| 4759 | 761 } else if (!do_size) { |
| 762 if (size != 0) st->print("\n\t"); | |
| 763 if (UseXmmRegToRegMoveAll) {//Use movaps,movapd to move between xmm registers | |
| 764 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move? | |
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765 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 766 } else { |
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767 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 768 } |
| 4759 | 769 } else { |
| 0 | 770 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move? |
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771 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 772 } else { |
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773 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 774 } |
| 4759 | 775 } |
| 0 | 776 #endif |
| 777 } | |
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778 // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes as SIMD prefix. |
| 4759 | 779 // Only MOVAPS SSE prefix uses 1 byte. |
| 780 int sz = 4; | |
| 781 if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) && | |
| 782 UseXmmRegToRegMoveAll && (UseAVX == 0)) sz = 3; | |
| 783 return size + sz; | |
| 0 | 784 } |
| 785 | |
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786 static int impl_movgpr2x_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, |
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787 int src_hi, int dst_hi, int size, outputStream* st ) { |
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788 // 32-bit |
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789 if (cbuf) { |
| 4759 | 790 MacroAssembler _masm(cbuf); |
| 791 __ movdl(as_XMMRegister(Matcher::_regEncode[dst_lo]), | |
| 792 as_Register(Matcher::_regEncode[src_lo])); | |
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793 #ifndef PRODUCT |
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794 } else if (!do_size) { |
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795 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]); |
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796 #endif |
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797 } |
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798 return 4; |
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799 } |
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800 |
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801 |
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802 static int impl_movx2gpr_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, |
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803 int src_hi, int dst_hi, int size, outputStream* st ) { |
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804 // 32-bit |
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805 if (cbuf) { |
| 4759 | 806 MacroAssembler _masm(cbuf); |
| 807 __ movdl(as_Register(Matcher::_regEncode[dst_lo]), | |
| 808 as_XMMRegister(Matcher::_regEncode[src_lo])); | |
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809 #ifndef PRODUCT |
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810 } else if (!do_size) { |
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811 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]); |
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812 #endif |
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813 } |
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814 return 4; |
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815 } |
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816 |
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817 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) { |
| 0 | 818 if( cbuf ) { |
| 819 emit_opcode(*cbuf, 0x8B ); | |
| 820 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] ); | |
| 821 #ifndef PRODUCT | |
| 822 } else if( !do_size ) { | |
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823 if( size != 0 ) st->print("\n\t"); |
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824 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]); |
| 0 | 825 #endif |
| 826 } | |
| 827 return size+2; | |
| 828 } | |
| 829 | |
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830 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi, |
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831 int offset, int size, outputStream* st ) { |
| 0 | 832 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there |
| 833 if( cbuf ) { | |
| 834 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it) | |
| 835 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] ); | |
| 836 #ifndef PRODUCT | |
| 837 } else if( !do_size ) { | |
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838 if( size != 0 ) st->print("\n\t"); |
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839 st->print("FLD %s",Matcher::regName[src_lo]); |
| 0 | 840 #endif |
| 841 } | |
| 842 size += 2; | |
| 843 } | |
| 844 | |
| 845 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/; | |
| 846 const char *op_str; | |
| 847 int op; | |
| 848 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store? | |
| 849 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D "; | |
| 850 op = 0xDD; | |
| 851 } else { // 32-bit store | |
| 852 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S "; | |
| 853 op = 0xD9; | |
| 854 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" ); | |
| 855 } | |
| 856 | |
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857 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st); |
| 0 | 858 } |
| 859 | |
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860 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad. |
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861 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, |
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862 int src_hi, int dst_hi, uint ireg, outputStream* st); |
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863 |
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864 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load, |
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865 int stack_offset, int reg, uint ireg, outputStream* st); |
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866 |
|
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867 static int vec_stack_to_stack_helper(CodeBuffer *cbuf, bool do_size, int src_offset, |
|
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868 int dst_offset, uint ireg, outputStream* st) { |
|
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869 int calc_size = 0; |
|
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|
870 int src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4); |
|
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871 int dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4); |
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|
872 switch (ireg) { |
|
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|
873 case Op_VecS: |
|
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874 calc_size = 3+src_offset_size + 3+dst_offset_size; |
|
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|
875 break; |
|
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|
876 case Op_VecD: |
|
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877 calc_size = 3+src_offset_size + 3+dst_offset_size; |
|
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878 src_offset += 4; |
|
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879 dst_offset += 4; |
|
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880 src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4); |
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881 dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4); |
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882 calc_size += 3+src_offset_size + 3+dst_offset_size; |
|
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|
883 break; |
|
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|
884 case Op_VecX: |
|
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885 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size; |
|
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886 break; |
|
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887 case Op_VecY: |
|
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888 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size; |
|
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|
889 break; |
|
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|
890 default: |
|
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891 ShouldNotReachHere(); |
|
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|
892 } |
|
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893 if (cbuf) { |
|
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894 MacroAssembler _masm(cbuf); |
|
8c92982cbbc4
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895 int offset = __ offset(); |
|
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896 switch (ireg) { |
|
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|
897 case Op_VecS: |
|
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|
898 __ pushl(Address(rsp, src_offset)); |
|
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899 __ popl (Address(rsp, dst_offset)); |
|
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|
900 break; |
|
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|
901 case Op_VecD: |
|
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902 __ pushl(Address(rsp, src_offset)); |
|
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903 __ popl (Address(rsp, dst_offset)); |
|
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904 __ pushl(Address(rsp, src_offset+4)); |
|
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905 __ popl (Address(rsp, dst_offset+4)); |
|
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|
906 break; |
|
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|
907 case Op_VecX: |
|
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|
908 __ movdqu(Address(rsp, -16), xmm0); |
|
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|
909 __ movdqu(xmm0, Address(rsp, src_offset)); |
|
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910 __ movdqu(Address(rsp, dst_offset), xmm0); |
|
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911 __ movdqu(xmm0, Address(rsp, -16)); |
|
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|
912 break; |
|
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|
913 case Op_VecY: |
|
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|
914 __ vmovdqu(Address(rsp, -32), xmm0); |
|
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915 __ vmovdqu(xmm0, Address(rsp, src_offset)); |
|
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916 __ vmovdqu(Address(rsp, dst_offset), xmm0); |
|
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917 __ vmovdqu(xmm0, Address(rsp, -32)); |
|
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|
918 break; |
|
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|
919 default: |
|
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|
920 ShouldNotReachHere(); |
|
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|
921 } |
|
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|
922 int size = __ offset() - offset; |
|
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923 assert(size == calc_size, "incorrect size calculattion"); |
|
8c92982cbbc4
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|
924 return size; |
|
8c92982cbbc4
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|
925 #ifndef PRODUCT |
|
8c92982cbbc4
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|
926 } else if (!do_size) { |
|
8c92982cbbc4
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|
927 switch (ireg) { |
|
8c92982cbbc4
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|
928 case Op_VecS: |
|
8c92982cbbc4
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|
929 st->print("pushl [rsp + #%d]\t# 32-bit mem-mem spill\n\t" |
|
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|
930 "popl [rsp + #%d]", |
|
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|
931 src_offset, dst_offset); |
|
8c92982cbbc4
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changeset
|
932 break; |
|
8c92982cbbc4
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diff
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|
933 case Op_VecD: |
|
8c92982cbbc4
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|
934 st->print("pushl [rsp + #%d]\t# 64-bit mem-mem spill\n\t" |
|
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|
935 "popq [rsp + #%d]\n\t" |
|
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|
936 "pushl [rsp + #%d]\n\t" |
|
8c92982cbbc4
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|
937 "popq [rsp + #%d]", |
|
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938 src_offset, dst_offset, src_offset+4, dst_offset+4); |
|
8c92982cbbc4
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|
939 break; |
|
8c92982cbbc4
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changeset
|
940 case Op_VecX: |
|
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|
941 st->print("movdqu [rsp - #16], xmm0\t# 128-bit mem-mem spill\n\t" |
|
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|
942 "movdqu xmm0, [rsp + #%d]\n\t" |
|
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|
943 "movdqu [rsp + #%d], xmm0\n\t" |
|
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|
944 "movdqu xmm0, [rsp - #16]", |
|
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|
945 src_offset, dst_offset); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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changeset
|
946 break; |
|
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diff
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|
947 case Op_VecY: |
|
8c92982cbbc4
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|
948 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t" |
|
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|
949 "vmovdqu xmm0, [rsp + #%d]\n\t" |
|
8c92982cbbc4
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|
950 "vmovdqu [rsp + #%d], xmm0\n\t" |
|
8c92982cbbc4
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|
951 "vmovdqu xmm0, [rsp - #32]", |
|
8c92982cbbc4
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|
952 src_offset, dst_offset); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
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changeset
|
953 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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diff
changeset
|
954 default: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
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|
955 ShouldNotReachHere(); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
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|
956 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
957 #endif |
|
8c92982cbbc4
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|
958 } |
|
8c92982cbbc4
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|
959 return calc_size; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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changeset
|
960 } |
|
8c92982cbbc4
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|
961 |
| 0 | 962 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const { |
| 963 // Get registers to move | |
| 964 OptoReg::Name src_second = ra_->get_reg_second(in(1)); | |
| 965 OptoReg::Name src_first = ra_->get_reg_first(in(1)); | |
| 966 OptoReg::Name dst_second = ra_->get_reg_second(this ); | |
| 967 OptoReg::Name dst_first = ra_->get_reg_first(this ); | |
| 968 | |
| 969 enum RC src_second_rc = rc_class(src_second); | |
| 970 enum RC src_first_rc = rc_class(src_first); | |
| 971 enum RC dst_second_rc = rc_class(dst_second); | |
| 972 enum RC dst_first_rc = rc_class(dst_first); | |
| 973 | |
| 974 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); | |
| 975 | |
| 976 // Generate spill code! | |
| 977 int size = 0; | |
| 978 | |
| 979 if( src_first == dst_first && src_second == dst_second ) | |
| 980 return size; // Self copy, no move | |
| 981 | |
|
6179
8c92982cbbc4
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982 if (bottom_type()->isa_vect() != NULL) { |
|
8c92982cbbc4
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983 uint ireg = ideal_reg(); |
|
8c92982cbbc4
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984 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity"); |
|
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985 assert((src_first_rc != rc_float && dst_first_rc != rc_float), "sanity"); |
|
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|
986 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity"); |
|
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987 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { |
|
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988 // mem -> mem |
|
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989 int src_offset = ra_->reg2offset(src_first); |
|
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|
990 int dst_offset = ra_->reg2offset(dst_first); |
|
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991 return vec_stack_to_stack_helper(cbuf, do_size, src_offset, dst_offset, ireg, st); |
|
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992 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) { |
|
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|
993 return vec_mov_helper(cbuf, do_size, src_first, dst_first, src_second, dst_second, ireg, st); |
|
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|
994 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_stack ) { |
|
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|
995 int stack_offset = ra_->reg2offset(dst_first); |
|
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|
996 return vec_spill_helper(cbuf, do_size, false, stack_offset, src_first, ireg, st); |
|
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|
997 } else if (src_first_rc == rc_stack && dst_first_rc == rc_xmm ) { |
|
8c92982cbbc4
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998 int stack_offset = ra_->reg2offset(src_first); |
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999 return vec_spill_helper(cbuf, do_size, true, stack_offset, dst_first, ireg, st); |
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1000 } else { |
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1001 ShouldNotReachHere(); |
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1002 } |
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1003 } |
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1004 |
| 0 | 1005 // -------------------------------------- |
| 1006 // Check for mem-mem move. push/pop to move. | |
| 1007 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { | |
| 1008 if( src_second == dst_first ) { // overlapping stack copy ranges | |
| 1009 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" ); | |
|
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1010 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st); |
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1011 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st); |
| 0 | 1012 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits |
| 1013 } | |
| 1014 // move low bits | |
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1015 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st); |
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1016 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st); |
| 0 | 1017 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits |
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1018 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st); |
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1019 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st); |
| 0 | 1020 } |
| 1021 return size; | |
| 1022 } | |
| 1023 | |
| 1024 // -------------------------------------- | |
| 1025 // Check for integer reg-reg copy | |
| 1026 if( src_first_rc == rc_int && dst_first_rc == rc_int ) | |
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1027 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st); |
| 0 | 1028 |
| 1029 // Check for integer store | |
| 1030 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) | |
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1031 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st); |
| 0 | 1032 |
| 1033 // Check for integer load | |
| 1034 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) | |
|
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1035 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st); |
| 0 | 1036 |
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1037 // Check for integer reg-xmm reg copy |
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1038 if( src_first_rc == rc_int && dst_first_rc == rc_xmm ) { |
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1039 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad), |
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1040 "no 64 bit integer-float reg moves" ); |
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1041 return impl_movgpr2x_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st); |
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1042 } |
| 0 | 1043 // -------------------------------------- |
| 1044 // Check for float reg-reg copy | |
| 1045 if( src_first_rc == rc_float && dst_first_rc == rc_float ) { | |
| 1046 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) || | |
| 1047 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" ); | |
| 1048 if( cbuf ) { | |
| 1049 | |
| 1050 // Note the mucking with the register encode to compensate for the 0/1 | |
| 1051 // indexing issue mentioned in a comment in the reg_def sections | |
| 1052 // for FPR registers many lines above here. | |
| 1053 | |
| 1054 if( src_first != FPR1L_num ) { | |
| 1055 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i) | |
| 1056 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 ); | |
| 1057 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i) | |
| 1058 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] ); | |
| 1059 } else { | |
| 1060 emit_opcode (*cbuf, 0xDD ); // FST ST(i) | |
| 1061 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 ); | |
| 1062 } | |
| 1063 #ifndef PRODUCT | |
| 1064 } else if( !do_size ) { | |
| 1065 if( size != 0 ) st->print("\n\t"); | |
| 1066 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]); | |
| 1067 else st->print( "FST %s", Matcher::regName[dst_first]); | |
| 1068 #endif | |
| 1069 } | |
| 1070 return size + ((src_first != FPR1L_num) ? 2+2 : 2); | |
| 1071 } | |
| 1072 | |
| 1073 // Check for float store | |
| 1074 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { | |
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1075 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st); |
| 0 | 1076 } |
| 1077 | |
| 1078 // Check for float load | |
| 1079 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { | |
| 1080 int offset = ra_->reg2offset(src_first); | |
| 1081 const char *op_str; | |
| 1082 int op; | |
| 1083 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load? | |
| 1084 op_str = "FLD_D"; | |
| 1085 op = 0xDD; | |
| 1086 } else { // 32-bit load | |
| 1087 op_str = "FLD_S"; | |
| 1088 op = 0xD9; | |
| 1089 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" ); | |
| 1090 } | |
| 1091 if( cbuf ) { | |
| 1092 emit_opcode (*cbuf, op ); | |
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1093 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, relocInfo::none); |
| 0 | 1094 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i) |
| 1095 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] ); | |
| 1096 #ifndef PRODUCT | |
| 1097 } else if( !do_size ) { | |
| 1098 if( size != 0 ) st->print("\n\t"); | |
| 1099 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]); | |
| 1100 #endif | |
| 1101 } | |
| 1102 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); | |
| 1103 return size + 3+offset_size+2; | |
| 1104 } | |
| 1105 | |
| 1106 // Check for xmm reg-reg copy | |
| 1107 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) { | |
| 1108 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) || | |
| 1109 (src_first+1 == src_second && dst_first+1 == dst_second), | |
| 1110 "no non-adjacent float-moves" ); | |
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1111 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st); |
| 0 | 1112 } |
| 1113 | |
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1114 // Check for xmm reg-integer reg copy |
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1115 if( src_first_rc == rc_xmm && dst_first_rc == rc_int ) { |
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1116 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad), |
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1117 "no 64 bit float-integer reg moves" ); |
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1118 return impl_movx2gpr_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st); |
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1119 } |
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1120 |
| 0 | 1121 // Check for xmm store |
| 1122 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) { | |
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1123 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st); |
| 0 | 1124 } |
| 1125 | |
| 1126 // Check for float xmm load | |
| 1127 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) { | |
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1128 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st); |
| 0 | 1129 } |
| 1130 | |
| 1131 // Copy from float reg to xmm reg | |
| 1132 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) { | |
| 1133 // copy to the top of stack from floating point reg | |
| 1134 // and use LEA to preserve flags | |
| 1135 if( cbuf ) { | |
| 1136 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8] | |
| 1137 emit_rm(*cbuf, 0x1, ESP_enc, 0x04); | |
| 1138 emit_rm(*cbuf, 0x0, 0x04, ESP_enc); | |
| 1139 emit_d8(*cbuf,0xF8); | |
| 1140 #ifndef PRODUCT | |
| 1141 } else if( !do_size ) { | |
| 1142 if( size != 0 ) st->print("\n\t"); | |
| 1143 st->print("LEA ESP,[ESP-8]"); | |
| 1144 #endif | |
| 1145 } | |
| 1146 size += 4; | |
| 1147 | |
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1148 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st); |
| 0 | 1149 |
| 1150 // Copy from the temp memory to the xmm reg. | |
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1151 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st); |
| 0 | 1152 |
| 1153 if( cbuf ) { | |
| 1154 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8] | |
| 1155 emit_rm(*cbuf, 0x1, ESP_enc, 0x04); | |
| 1156 emit_rm(*cbuf, 0x0, 0x04, ESP_enc); | |
| 1157 emit_d8(*cbuf,0x08); | |
| 1158 #ifndef PRODUCT | |
| 1159 } else if( !do_size ) { | |
| 1160 if( size != 0 ) st->print("\n\t"); | |
| 1161 st->print("LEA ESP,[ESP+8]"); | |
| 1162 #endif | |
| 1163 } | |
| 1164 size += 4; | |
| 1165 return size; | |
| 1166 } | |
| 1167 | |
| 1168 assert( size > 0, "missed a case" ); | |
| 1169 | |
| 1170 // -------------------------------------------------------------------- | |
| 1171 // Check for second bits still needing moving. | |
| 1172 if( src_second == dst_second ) | |
| 1173 return size; // Self copy; no move | |
| 1174 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); | |
| 1175 | |
| 1176 // Check for second word int-int move | |
| 1177 if( src_second_rc == rc_int && dst_second_rc == rc_int ) | |
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1178 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st); |
| 0 | 1179 |
| 1180 // Check for second word integer store | |
| 1181 if( src_second_rc == rc_int && dst_second_rc == rc_stack ) | |
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1182 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st); |
| 0 | 1183 |
| 1184 // Check for second word integer load | |
| 1185 if( dst_second_rc == rc_int && src_second_rc == rc_stack ) | |
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1186 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st); |
| 0 | 1187 |
| 1188 | |
| 1189 Unimplemented(); | |
| 1190 } | |
| 1191 | |
| 1192 #ifndef PRODUCT | |
| 4950 | 1193 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const { |
| 0 | 1194 implementation( NULL, ra_, false, st ); |
| 1195 } | |
| 1196 #endif | |
| 1197 | |
| 1198 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1199 implementation( &cbuf, ra_, false, NULL ); | |
| 1200 } | |
| 1201 | |
| 1202 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { | |
| 1203 return implementation( NULL, ra_, true, NULL ); | |
| 1204 } | |
| 1205 | |
| 1206 | |
| 1207 //============================================================================= | |
| 1208 #ifndef PRODUCT | |
| 1209 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { | |
| 1210 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1211 int reg = ra_->get_reg_first(this); | |
| 1212 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset); | |
| 1213 } | |
| 1214 #endif | |
| 1215 | |
| 1216 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1217 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1218 int reg = ra_->get_encode(this); | |
| 1219 if( offset >= 128 ) { | |
| 1220 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1221 emit_rm(cbuf, 0x2, reg, 0x04); | |
| 1222 emit_rm(cbuf, 0x0, 0x04, ESP_enc); | |
| 1223 emit_d32(cbuf, offset); | |
| 1224 } | |
| 1225 else { | |
| 1226 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1227 emit_rm(cbuf, 0x1, reg, 0x04); | |
| 1228 emit_rm(cbuf, 0x0, 0x04, ESP_enc); | |
| 1229 emit_d8(cbuf, offset); | |
| 1230 } | |
| 1231 } | |
| 1232 | |
| 1233 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { | |
| 1234 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1235 if( offset >= 128 ) { | |
| 1236 return 7; | |
| 1237 } | |
| 1238 else { | |
| 1239 return 4; | |
| 1240 } | |
| 1241 } | |
| 1242 | |
| 1243 //============================================================================= | |
| 1244 | |
| 1245 // emit call stub, compiled java to interpreter | |
| 1246 void emit_java_to_interp(CodeBuffer &cbuf ) { | |
| 1247 // Stub is fixed up when the corresponding call is converted from calling | |
| 1248 // compiled code to calling interpreted code. | |
| 1249 // mov rbx,0 | |
| 1250 // jmp -1 | |
| 1251 | |
| 1748 | 1252 address mark = cbuf.insts_mark(); // get mark within main instrs section |
| 1253 | |
| 1254 // Note that the code buffer's insts_mark is always relative to insts. | |
| 0 | 1255 // That's why we must use the macroassembler to generate a stub. |
| 1256 MacroAssembler _masm(&cbuf); | |
| 1257 | |
| 1258 address base = | |
| 1259 __ start_a_stub(Compile::MAX_stubs_size); | |
| 1260 if (base == NULL) return; // CodeBuffer::expand failed | |
| 1261 // static stub relocation stores the instruction address of the call | |
| 1262 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM32); | |
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1263 // static stub relocation also tags the Method* in the code-stream. |
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1264 __ mov_metadata(rbx, (Metadata*)NULL); // method is zapped till fixup time |
| 304 | 1265 // This is recognized as unresolved by relocs/nativeInst/ic code |
| 1266 __ jump(RuntimeAddress(__ pc())); | |
| 0 | 1267 |
| 1268 __ end_a_stub(); | |
| 1748 | 1269 // Update current stubs pointer and restore insts_end. |
| 0 | 1270 } |
| 1271 // size of call stub, compiled java to interpretor | |
| 1272 uint size_java_to_interp() { | |
| 1273 return 10; // movl; jmp | |
| 1274 } | |
| 1275 // relocation entries for call stub, compiled java to interpretor | |
| 1276 uint reloc_java_to_interp() { | |
| 1277 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call | |
| 1278 } | |
| 1279 | |
| 1280 //============================================================================= | |
| 1281 #ifndef PRODUCT | |
| 1282 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { | |
| 1283 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check"); | |
| 1284 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub"); | |
| 1285 st->print_cr("\tNOP"); | |
| 1286 st->print_cr("\tNOP"); | |
| 1287 if( !OptoBreakpoint ) | |
| 1288 st->print_cr("\tNOP"); | |
| 1289 } | |
| 1290 #endif | |
| 1291 | |
| 1292 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1293 MacroAssembler masm(&cbuf); | |
| 1294 #ifdef ASSERT | |
| 1748 | 1295 uint insts_size = cbuf.insts_size(); |
| 0 | 1296 #endif |
| 304 | 1297 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes())); |
| 0 | 1298 masm.jump_cc(Assembler::notEqual, |
| 1299 RuntimeAddress(SharedRuntime::get_ic_miss_stub())); | |
| 1300 /* WARNING these NOPs are critical so that verified entry point is properly | |
| 1301 aligned for patching by NativeJump::patch_verified_entry() */ | |
| 1302 int nops_cnt = 2; | |
| 1303 if( !OptoBreakpoint ) // Leave space for int3 | |
| 1304 nops_cnt += 1; | |
| 1305 masm.nop(nops_cnt); | |
| 1306 | |
| 1748 | 1307 assert(cbuf.insts_size() - insts_size == size(ra_), "checking code size of inline cache node"); |
| 0 | 1308 } |
| 1309 | |
| 1310 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { | |
| 1311 return OptoBreakpoint ? 11 : 12; | |
| 1312 } | |
| 1313 | |
| 1314 | |
| 1315 //============================================================================= | |
| 1316 uint size_exception_handler() { | |
| 1317 // NativeCall instruction size is the same as NativeJump. | |
| 1318 // exception handler starts out as jump and can be patched to | |
| 1319 // a call be deoptimization. (4932387) | |
| 1320 // Note that this value is also credited (in output.cpp) to | |
| 1321 // the size of the code section. | |
| 1322 return NativeJump::instruction_size; | |
| 1323 } | |
| 1324 | |
| 1325 // Emit exception handler code. Stuff framesize into a register | |
| 1326 // and call a VM stub routine. | |
| 1327 int emit_exception_handler(CodeBuffer& cbuf) { | |
| 1328 | |
| 1748 | 1329 // Note that the code buffer's insts_mark is always relative to insts. |
| 0 | 1330 // That's why we must use the macroassembler to generate a handler. |
| 1331 MacroAssembler _masm(&cbuf); | |
| 1332 address base = | |
| 1333 __ start_a_stub(size_exception_handler()); | |
| 1334 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1335 int offset = __ offset(); | |
| 1748 | 1336 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point())); |
| 0 | 1337 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); |
| 1338 __ end_a_stub(); | |
| 1339 return offset; | |
| 1340 } | |
| 1341 | |
| 1342 uint size_deopt_handler() { | |
| 1343 // NativeCall instruction size is the same as NativeJump. | |
| 1344 // exception handler starts out as jump and can be patched to | |
| 1345 // a call be deoptimization. (4932387) | |
| 1346 // Note that this value is also credited (in output.cpp) to | |
| 1347 // the size of the code section. | |
| 1348 return 5 + NativeJump::instruction_size; // pushl(); jmp; | |
| 1349 } | |
| 1350 | |
| 1351 // Emit deopt handler code. | |
| 1352 int emit_deopt_handler(CodeBuffer& cbuf) { | |
| 1353 | |
| 1748 | 1354 // Note that the code buffer's insts_mark is always relative to insts. |
| 0 | 1355 // That's why we must use the macroassembler to generate a handler. |
| 1356 MacroAssembler _masm(&cbuf); | |
| 1357 address base = | |
| 1358 __ start_a_stub(size_exception_handler()); | |
| 1359 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1360 int offset = __ offset(); | |
| 1361 InternalAddress here(__ pc()); | |
| 1362 __ pushptr(here.addr()); | |
| 1363 | |
| 1364 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); | |
| 1365 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); | |
| 1366 __ end_a_stub(); | |
| 1367 return offset; | |
| 1368 } | |
| 1369 | |
| 1370 int Matcher::regnum_to_fpu_offset(int regnum) { | |
| 1371 return regnum - 32; // The FP registers are in the second chunk | |
| 1372 } | |
| 1373 | |
| 1374 // This is UltraSparc specific, true just means we have fast l2f conversion | |
| 1375 const bool Matcher::convL2FSupported(void) { | |
| 1376 return true; | |
| 1377 } | |
| 1378 | |
| 1379 // Is this branch offset short enough that a short branch can be used? | |
| 1380 // | |
| 1381 // NOTE: If the platform does not provide any short branch variants, then | |
| 1382 // this method should return false for offset 0. | |
| 3851 | 1383 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { |
| 1384 // The passed offset is relative to address of the branch. | |
| 1385 // On 86 a branch displacement is calculated relative to address | |
| 1386 // of a next instruction. | |
| 1387 offset -= br_size; | |
| 1388 | |
|
415
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1389 // the short version of jmpConUCF2 contains multiple branches, |
|
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|
1390 // making the reach slightly less |
|
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|
1391 if (rule == jmpConUCF2_rule) |
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1392 return (-126 <= offset && offset <= 125); |
| 0 | 1393 return (-128 <= offset && offset <= 127); |
| 1394 } | |
| 1395 | |
| 1396 const bool Matcher::isSimpleConstant64(jlong value) { | |
| 1397 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. | |
| 1398 return false; | |
| 1399 } | |
| 1400 | |
| 1401 // The ecx parameter to rep stos for the ClearArray node is in dwords. | |
| 1402 const bool Matcher::init_array_count_is_in_bytes = false; | |
| 1403 | |
| 1404 // Threshold size for cleararray. | |
| 1405 const int Matcher::init_array_short_size = 8 * BytesPerLong; | |
| 1406 | |
| 4047 | 1407 // Needs 2 CMOV's for longs. |
| 1408 const int Matcher::long_cmove_cost() { return 1; } | |
| 1409 | |
| 1410 // No CMOVF/CMOVD with SSE/SSE2 | |
| 1411 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; } | |
| 1412 | |
| 0 | 1413 // Should the Matcher clone shifts on addressing modes, expecting them to |
| 1414 // be subsumed into complex addressing expressions or compute them into | |
| 1415 // registers? True for Intel but false for most RISCs | |
| 1416 const bool Matcher::clone_shift_expressions = true; | |
| 1417 | |
|
2401
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|
1418 // Do we need to mask the count passed to shift instructions or does |
|
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1419 // the cpu only look at the lower 5/6 bits anyway? |
|
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1420 const bool Matcher::need_masked_shift_count = false; |
|
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|
1421 |
|
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|
1422 bool Matcher::narrow_oop_use_complex_address() { |
|
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|
1423 ShouldNotCallThis(); |
|
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|
1424 return true; |
|
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|
1425 } |
|
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|
1426 |
|
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|
1427 |
| 0 | 1428 // Is it better to copy float constants, or load them directly from memory? |
| 1429 // Intel can load a float constant from a direct address, requiring no | |
| 1430 // extra registers. Most RISCs will have to materialize an address into a | |
| 1431 // register first, so they would do better to copy the constant from stack. | |
| 1432 const bool Matcher::rematerialize_float_constants = true; | |
| 1433 | |
| 1434 // If CPU can load and store mis-aligned doubles directly then no fixup is | |
| 1435 // needed. Else we split the double into 2 integer pieces and move it | |
| 1436 // piece-by-piece. Only happens when passing doubles into C code as the | |
| 1437 // Java calling convention forces doubles to be aligned. | |
| 1438 const bool Matcher::misaligned_doubles_ok = true; | |
| 1439 | |
| 1440 | |
| 1441 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { | |
| 1442 // Get the memory operand from the node | |
| 1443 uint numopnds = node->num_opnds(); // Virtual call for number of operands | |
| 1444 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far | |
| 1445 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" ); | |
| 1446 uint opcnt = 1; // First operand | |
| 1447 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand | |
| 1448 while( idx >= skipped+num_edges ) { | |
| 1449 skipped += num_edges; | |
| 1450 opcnt++; // Bump operand count | |
| 1451 assert( opcnt < numopnds, "Accessing non-existent operand" ); | |
| 1452 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand | |
| 1453 } | |
| 1454 | |
| 1455 MachOper *memory = node->_opnds[opcnt]; | |
| 1456 MachOper *new_memory = NULL; | |
| 1457 switch (memory->opcode()) { | |
| 1458 case DIRECT: | |
| 1459 case INDOFFSET32X: | |
| 1460 // No transformation necessary. | |
| 1461 return; | |
| 1462 case INDIRECT: | |
| 1463 new_memory = new (C) indirect_win95_safeOper( ); | |
| 1464 break; | |
| 1465 case INDOFFSET8: | |
| 1466 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0)); | |
| 1467 break; | |
| 1468 case INDOFFSET32: | |
| 1469 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0)); | |
| 1470 break; | |
| 1471 case INDINDEXOFFSET: | |
| 1472 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0)); | |
| 1473 break; | |
| 1474 case INDINDEXSCALE: | |
| 1475 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale()); | |
| 1476 break; | |
| 1477 case INDINDEXSCALEOFFSET: | |
| 1478 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0)); | |
| 1479 break; | |
| 1480 case LOAD_LONG_INDIRECT: | |
| 1481 case LOAD_LONG_INDOFFSET32: | |
| 1482 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI} | |
| 1483 return; | |
| 1484 default: | |
| 1485 assert(false, "unexpected memory operand in pd_implicit_null_fixup()"); | |
| 1486 return; | |
| 1487 } | |
| 1488 node->_opnds[opcnt] = new_memory; | |
| 1489 } | |
| 1490 | |
| 1491 // Advertise here if the CPU requires explicit rounding operations | |
| 1492 // to implement the UseStrictFP mode. | |
| 1493 const bool Matcher::strict_fp_requires_explicit_rounding = true; | |
| 1494 | |
|
1274
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|
1495 // Are floats conerted to double when stored to stack during deoptimization? |
|
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|
1496 // On x32 it is stored with convertion only when FPU is used for floats. |
|
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|
1497 bool Matcher::float_in_double() { return (UseSSE == 0); } |
|
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|
1498 |
| 0 | 1499 // Do ints take an entire long register or just half? |
| 1500 const bool Matcher::int_in_long = false; | |
| 1501 | |
| 1502 // Return whether or not this register is ever used as an argument. This | |
| 1503 // function is used on startup to build the trampoline stubs in generateOptoStub. | |
| 1504 // Registers not mentioned will be killed by the VM call in the trampoline, and | |
| 1505 // arguments in those registers not be available to the callee. | |
| 1506 bool Matcher::can_be_java_arg( int reg ) { | |
| 1507 if( reg == ECX_num || reg == EDX_num ) return true; | |
|
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|
1508 if( (reg == XMM0_num || reg == XMM1_num ) && UseSSE>=1 ) return true; |
| 0 | 1509 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true; |
| 1510 return false; | |
| 1511 } | |
| 1512 | |
| 1513 bool Matcher::is_spillable_arg( int reg ) { | |
| 1514 return can_be_java_arg(reg); | |
| 1515 } | |
| 1516 | |
|
1914
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|
1517 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) { |
|
ae065c367d93
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|
1518 // Use hardware integer DIV instruction when |
|
ae065c367d93
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|
1519 // it is faster than a code which use multiply. |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
1520 // Only when constant divisor fits into 32 bit |
|
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|
1521 // (min_jint is excluded to get only correct |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
1522 // positive 32 bit values from negative). |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
1523 return VM_Version::has_fast_idiv() && |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
1524 (divisor == (int)divisor && divisor != min_jint); |
|
ae065c367d93
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|
1525 } |
|
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|
1526 |
| 0 | 1527 // Register for DIVI projection of divmodI |
| 1528 RegMask Matcher::divI_proj_mask() { | |
|
4121
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|
1529 return EAX_REG_mask(); |
| 0 | 1530 } |
| 1531 | |
| 1532 // Register for MODI projection of divmodI | |
| 1533 RegMask Matcher::modI_proj_mask() { | |
|
4121
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|
1534 return EDX_REG_mask(); |
| 0 | 1535 } |
| 1536 | |
| 1537 // Register for DIVL projection of divmodL | |
| 1538 RegMask Matcher::divL_proj_mask() { | |
| 1539 ShouldNotReachHere(); | |
| 1540 return RegMask(); | |
| 1541 } | |
| 1542 | |
| 1543 // Register for MODL projection of divmodL | |
| 1544 RegMask Matcher::modL_proj_mask() { | |
| 1545 ShouldNotReachHere(); | |
| 1546 return RegMask(); | |
| 1547 } | |
| 1548 | |
|
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6829187: compiler optimizations required for JSR 292
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|
1549 const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
|
4121
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|
1550 return EBP_REG_mask(); |
|
1137
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6829187: compiler optimizations required for JSR 292
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|
1551 } |
|
97125851f396
6829187: compiler optimizations required for JSR 292
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|
1552 |
|
1209
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|
1553 // Returns true if the high 32 bits of the value is known to be zero. |
|
e8443c7be117
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|
1554 bool is_operand_hi32_zero(Node* n) { |
|
e8443c7be117
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|
1555 int opc = n->Opcode(); |
|
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|
1556 if (opc == Op_LoadUI2L) { |
|
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|
1557 return true; |
|
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|
1558 } |
|
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|
1559 if (opc == Op_AndL) { |
|
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|
1560 Node* o2 = n->in(2); |
|
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|
1561 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) { |
|
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|
1562 return true; |
|
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|
1563 } |
|
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|
1564 } |
|
1914
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|
1565 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) { |
|
ae065c367d93
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|
1566 return true; |
|
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|
1567 } |
|
1209
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|
1568 return false; |
|
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|
1569 } |
|
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|
1570 |
| 0 | 1571 %} |
| 1572 | |
| 1573 //----------ENCODING BLOCK----------------------------------------------------- | |
| 1574 // This block specifies the encoding classes used by the compiler to output | |
| 1575 // byte streams. Encoding classes generate functions which are called by | |
| 1576 // Machine Instruction Nodes in order to generate the bit encoding of the | |
| 1577 // instruction. Operands specify their base encoding interface with the | |
| 1578 // interface keyword. There are currently supported four interfaces, | |
| 1579 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an | |
| 1580 // operand to generate a function which returns its register number when | |
| 1581 // queried. CONST_INTER causes an operand to generate a function which | |
| 1582 // returns the value of the constant when queried. MEMORY_INTER causes an | |
| 1583 // operand to generate four functions which return the Base Register, the | |
| 1584 // Index Register, the Scale Value, and the Offset Value of the operand when | |
| 1585 // queried. COND_INTER causes an operand to generate six functions which | |
| 1586 // return the encoding code (ie - encoding bits for the instruction) | |
| 1587 // associated with each basic boolean condition for a conditional instruction. | |
| 1588 // Instructions specify two basic values for encoding. They use the | |
| 1589 // ins_encode keyword to specify their encoding class (which must be one of | |
| 1590 // the class names specified in the encoding block), and they use the | |
| 1591 // opcode keyword to specify, in order, their primary, secondary, and | |
| 1592 // tertiary opcode. Only the opcode sections which a particular instruction | |
| 1593 // needs for encoding need to be specified. | |
| 1594 encode %{ | |
| 1595 // Build emit functions for each basic byte or larger field in the intel | |
| 1596 // encoding scheme (opcode, rm, sib, immediate), and call them from C++ | |
| 1597 // code in the enc_class source block. Emit functions will live in the | |
| 1598 // main source block for now. In future, we can generalize this by | |
| 1599 // adding a syntax that specifies the sizes of fields in an order, | |
| 1600 // so that the adlc can build the emit functions automagically | |
|
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|
1601 |
|
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|
1602 // Emit primary opcode |
|
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|
1603 enc_class OpcP %{ |
|
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|
1604 emit_opcode(cbuf, $primary); |
|
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diff
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|
1605 %} |
|
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diff
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|
1606 |
|
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|
1607 // Emit secondary opcode |
|
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diff
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|
1608 enc_class OpcS %{ |
|
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1609 emit_opcode(cbuf, $secondary); |
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1610 %} |
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1611 |
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1612 // Emit opcode directly |
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1613 enc_class Opcode(immI d8) %{ |
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1614 emit_opcode(cbuf, $d8$$constant); |
| 0 | 1615 %} |
| 1616 | |
| 1617 enc_class SizePrefix %{ | |
| 1618 emit_opcode(cbuf,0x66); | |
| 1619 %} | |
| 1620 | |
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1621 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many) |
| 0 | 1622 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); |
| 1623 %} | |
| 1624 | |
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1625 enc_class OpcRegReg (immI opcode, rRegI dst, rRegI src) %{ // OpcRegReg(Many) |
| 0 | 1626 emit_opcode(cbuf,$opcode$$constant); |
| 1627 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 1628 %} | |
| 1629 | |
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1630 enc_class mov_r32_imm0( rRegI dst ) %{ |
| 0 | 1631 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32 |
| 1632 emit_d32 ( cbuf, 0x0 ); // imm32==0x0 | |
| 1633 %} | |
| 1634 | |
| 1635 enc_class cdq_enc %{ | |
| 1636 // Full implementation of Java idiv and irem; checks for | |
| 1637 // special case as described in JVM spec., p.243 & p.271. | |
| 1638 // | |
| 1639 // normal case special case | |
| 1640 // | |
| 1641 // input : rax,: dividend min_int | |
| 1642 // reg: divisor -1 | |
| 1643 // | |
| 1644 // output: rax,: quotient (= rax, idiv reg) min_int | |
| 1645 // rdx: remainder (= rax, irem reg) 0 | |
| 1646 // | |
| 1647 // Code sequnce: | |
| 1648 // | |
| 1649 // 81 F8 00 00 00 80 cmp rax,80000000h | |
| 1650 // 0F 85 0B 00 00 00 jne normal_case | |
| 1651 // 33 D2 xor rdx,edx | |
| 1652 // 83 F9 FF cmp rcx,0FFh | |
| 1653 // 0F 84 03 00 00 00 je done | |
| 1654 // normal_case: | |
| 1655 // 99 cdq | |
| 1656 // F7 F9 idiv rax,ecx | |
| 1657 // done: | |
| 1658 // | |
| 1659 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8); | |
| 1660 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); | |
| 1661 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h | |
| 1662 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85); | |
| 1663 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00); | |
| 1664 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case | |
| 1665 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx | |
| 1666 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh | |
| 1667 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84); | |
| 1668 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00); | |
| 1669 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done | |
| 1670 // normal_case: | |
| 1671 emit_opcode(cbuf,0x99); // cdq | |
| 1672 // idiv (note: must be emitted by the user of this rule) | |
| 1673 // normal: | |
| 1674 %} | |
| 1675 | |
| 1676 // Dense encoding for older common ops | |
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1677 enc_class Opc_plus(immI opcode, rRegI reg) %{ |
| 0 | 1678 emit_opcode(cbuf, $opcode$$constant + $reg$$reg); |
| 1679 %} | |
| 1680 | |
| 1681 | |
| 1682 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension | |
| 1683 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit | |
| 1684 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1685 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { | |
| 1686 emit_opcode(cbuf, $primary | 0x02); | |
| 1687 } | |
| 1688 else { // If 32-bit immediate | |
| 1689 emit_opcode(cbuf, $primary); | |
| 1690 } | |
| 1691 %} | |
| 1692 | |
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1693 enc_class OpcSErm (rRegI dst, immI imm) %{ // OpcSEr/m |
| 0 | 1694 // Emit primary opcode and set sign-extend bit |
| 1695 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1696 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { | |
| 1697 emit_opcode(cbuf, $primary | 0x02); } | |
| 1698 else { // If 32-bit immediate | |
| 1699 emit_opcode(cbuf, $primary); | |
| 1700 } | |
| 1701 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 1702 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); | |
| 1703 %} | |
| 1704 | |
| 1705 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits | |
| 1706 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1707 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { | |
| 1708 $$$emit8$imm$$constant; | |
| 1709 } | |
| 1710 else { // If 32-bit immediate | |
| 1711 // Output immediate | |
| 1712 $$$emit32$imm$$constant; | |
| 1713 } | |
| 1714 %} | |
| 1715 | |
| 1716 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{ | |
| 1717 // Emit primary opcode and set sign-extend bit | |
| 1718 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1719 int con = (int)$imm$$constant; // Throw away top bits | |
| 1720 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary); | |
| 1721 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 1722 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); | |
| 1723 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con); | |
| 1724 else emit_d32(cbuf,con); | |
| 1725 %} | |
| 1726 | |
| 1727 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{ | |
| 1728 // Emit primary opcode and set sign-extend bit | |
| 1729 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1730 int con = (int)($imm$$constant >> 32); // Throw away bottom bits | |
| 1731 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary); | |
| 1732 // Emit r/m byte with tertiary opcode, after primary opcode. | |
| 1733 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg)); | |
| 1734 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con); | |
| 1735 else emit_d32(cbuf,con); | |
| 1736 %} | |
| 1737 | |
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1738 enc_class OpcSReg (rRegI dst) %{ // BSWAP |
| 0 | 1739 emit_cc(cbuf, $secondary, $dst$$reg ); |
| 1740 %} | |
| 1741 | |
| 1742 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP | |
| 1743 int destlo = $dst$$reg; | |
| 1744 int desthi = HIGH_FROM_LOW(destlo); | |
| 1745 // bswap lo | |
| 1746 emit_opcode(cbuf, 0x0F); | |
| 1747 emit_cc(cbuf, 0xC8, destlo); | |
| 1748 // bswap hi | |
| 1749 emit_opcode(cbuf, 0x0F); | |
| 1750 emit_cc(cbuf, 0xC8, desthi); | |
| 1751 // xchg lo and hi | |
| 1752 emit_opcode(cbuf, 0x87); | |
| 1753 emit_rm(cbuf, 0x3, destlo, desthi); | |
| 1754 %} | |
| 1755 | |
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1756 enc_class RegOpc (rRegI div) %{ // IDIV, IMOD, JMP indirect, ... |
| 0 | 1757 emit_rm(cbuf, 0x3, $secondary, $div$$reg ); |
| 1758 %} | |
| 1759 | |
| 1760 enc_class enc_cmov(cmpOp cop ) %{ // CMOV | |
| 1761 $$$emit8$primary; | |
| 1762 emit_cc(cbuf, $secondary, $cop$$cmpcode); | |
| 1763 %} | |
| 1764 | |
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1765 enc_class enc_cmov_dpr(cmpOp cop, regDPR src ) %{ // CMOV |
| 0 | 1766 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1); |
| 1767 emit_d8(cbuf, op >> 8 ); | |
| 1768 emit_d8(cbuf, op & 255); | |
| 1769 %} | |
| 1770 | |
| 1771 // emulate a CMOV with a conditional branch around a MOV | |
| 1772 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV | |
| 1773 // Invert sense of branch from sense of CMOV | |
| 1774 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) ); | |
| 1775 emit_d8( cbuf, $brOffs$$constant ); | |
| 1776 %} | |
| 1777 | |
| 1778 enc_class enc_PartialSubtypeCheck( ) %{ | |
| 1779 Register Redi = as_Register(EDI_enc); // result register | |
| 1780 Register Reax = as_Register(EAX_enc); // super class | |
| 1781 Register Recx = as_Register(ECX_enc); // killed | |
| 1782 Register Resi = as_Register(ESI_enc); // sub class | |
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1783 Label miss; |
| 0 | 1784 |
| 1785 MacroAssembler _masm(&cbuf); | |
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1786 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi, |
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1787 NULL, &miss, |
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1788 /*set_cond_codes:*/ true); |
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1789 if ($primary) { |
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1790 __ xorptr(Redi, Redi); |
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1791 } |
| 0 | 1792 __ bind(miss); |
| 1793 %} | |
| 1794 | |
| 1795 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All | |
| 1796 MacroAssembler masm(&cbuf); | |
| 1797 int start = masm.offset(); | |
| 1798 if (UseSSE >= 2) { | |
| 1799 if (VerifyFPU) { | |
| 1800 masm.verify_FPU(0, "must be empty in SSE2+ mode"); | |
| 1801 } | |
| 1802 } else { | |
| 1803 // External c_calling_convention expects the FPU stack to be 'clean'. | |
| 1804 // Compiled code leaves it dirty. Do cleanup now. | |
| 1805 masm.empty_FPU_stack(); | |
| 1806 } | |
| 1807 if (sizeof_FFree_Float_Stack_All == -1) { | |
| 1808 sizeof_FFree_Float_Stack_All = masm.offset() - start; | |
| 1809 } else { | |
| 1810 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size"); | |
| 1811 } | |
| 1812 %} | |
| 1813 | |
| 1814 enc_class Verify_FPU_For_Leaf %{ | |
| 1815 if( VerifyFPU ) { | |
| 1816 MacroAssembler masm(&cbuf); | |
| 1817 masm.verify_FPU( -3, "Returning from Runtime Leaf call"); | |
| 1818 } | |
| 1819 %} | |
| 1820 | |
| 1821 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf | |
| 1822 // This is the instruction starting address for relocation info. | |
| 1748 | 1823 cbuf.set_insts_mark(); |
| 0 | 1824 $$$emit8$primary; |
| 1825 // CALL directly to the runtime | |
| 1748 | 1826 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), |
| 0 | 1827 runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 1828 | |
| 1829 if (UseSSE >= 2) { | |
| 1830 MacroAssembler _masm(&cbuf); | |
| 1831 BasicType rt = tf()->return_type(); | |
| 1832 | |
| 1833 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) { | |
| 1834 // A C runtime call where the return value is unused. In SSE2+ | |
| 1835 // mode the result needs to be removed from the FPU stack. It's | |
| 1836 // likely that this function call could be removed by the | |
| 1837 // optimizer if the C function is a pure function. | |
| 1838 __ ffree(0); | |
| 1839 } else if (rt == T_FLOAT) { | |
| 304 | 1840 __ lea(rsp, Address(rsp, -4)); |
| 0 | 1841 __ fstp_s(Address(rsp, 0)); |
| 1842 __ movflt(xmm0, Address(rsp, 0)); | |
| 304 | 1843 __ lea(rsp, Address(rsp, 4)); |
| 0 | 1844 } else if (rt == T_DOUBLE) { |
| 304 | 1845 __ lea(rsp, Address(rsp, -8)); |
| 0 | 1846 __ fstp_d(Address(rsp, 0)); |
| 1847 __ movdbl(xmm0, Address(rsp, 0)); | |
| 304 | 1848 __ lea(rsp, Address(rsp, 8)); |
| 0 | 1849 } |
| 1850 } | |
| 1851 %} | |
| 1852 | |
| 1853 | |
| 1854 enc_class pre_call_FPU %{ | |
| 1855 // If method sets FPU control word restore it here | |
| 1748 | 1856 debug_only(int off0 = cbuf.insts_size()); |
| 0 | 1857 if( Compile::current()->in_24_bit_fp_mode() ) { |
| 1858 MacroAssembler masm(&cbuf); | |
| 1859 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
| 1860 } | |
| 1748 | 1861 debug_only(int off1 = cbuf.insts_size()); |
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1862 assert(off1 - off0 == pre_call_FPU_size(), "correct size prediction"); |
| 0 | 1863 %} |
| 1864 | |
| 1865 enc_class post_call_FPU %{ | |
| 1866 // If method sets FPU control word do it here also | |
| 1867 if( Compile::current()->in_24_bit_fp_mode() ) { | |
| 1868 MacroAssembler masm(&cbuf); | |
| 1869 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); | |
| 1870 } | |
| 1871 %} | |
| 1872 | |
| 1873 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL | |
| 1874 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
| 1875 // who we intended to call. | |
| 1748 | 1876 cbuf.set_insts_mark(); |
| 0 | 1877 $$$emit8$primary; |
| 1878 if ( !_method ) { | |
| 1748 | 1879 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), |
| 0 | 1880 runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 1881 } else if(_optimized_virtual) { | |
| 1748 | 1882 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), |
| 0 | 1883 opt_virtual_call_Relocation::spec(), RELOC_IMM32 ); |
| 1884 } else { | |
| 1748 | 1885 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), |
| 0 | 1886 static_call_Relocation::spec(), RELOC_IMM32 ); |
| 1887 } | |
| 1888 if( _method ) { // Emit stub for static call | |
| 1889 emit_java_to_interp(cbuf); | |
| 1890 } | |
| 1891 %} | |
| 1892 | |
| 1893 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL | |
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1894 MacroAssembler _masm(&cbuf); |
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1895 __ ic_call((address)$meth$$method); |
| 0 | 1896 %} |
| 1897 | |
| 1898 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL | |
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1899 int disp = in_bytes(Method::from_compiled_offset()); |
| 0 | 1900 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small"); |
| 1901 | |
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1902 // CALL *[EAX+in_bytes(Method::from_compiled_code_entry_point_offset())] |
| 1748 | 1903 cbuf.set_insts_mark(); |
| 0 | 1904 $$$emit8$primary; |
| 1905 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte | |
| 1906 emit_d8(cbuf, disp); // Displacement | |
| 1907 | |
| 1908 %} | |
| 1909 | |
| 1910 // Following encoding is no longer used, but may be restored if calling | |
| 1911 // convention changes significantly. | |
| 1912 // Became: Xor_Reg(EBP), Java_To_Runtime( labl ) | |
| 1913 // | |
| 1914 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL | |
| 1915 // // int ic_reg = Matcher::inline_cache_reg(); | |
| 1916 // // int ic_encode = Matcher::_regEncode[ic_reg]; | |
| 1917 // // int imo_reg = Matcher::interpreter_method_oop_reg(); | |
| 1918 // // int imo_encode = Matcher::_regEncode[imo_reg]; | |
| 1919 // | |
| 1920 // // // Interpreter expects method_oop in EBX, currently a callee-saved register, | |
| 1921 // // // so we load it immediately before the call | |
| 1922 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop | |
| 1923 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte | |
| 1924 // | |
| 1925 // // xor rbp,ebp | |
| 1926 // emit_opcode(cbuf, 0x33); | |
| 1927 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc); | |
| 1928 // | |
| 1929 // // CALL to interpreter. | |
| 1748 | 1930 // cbuf.set_insts_mark(); |
| 0 | 1931 // $$$emit8$primary; |
| 1748 | 1932 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4), |
| 0 | 1933 // runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 1934 // %} | |
| 1935 | |
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1936 enc_class RegOpcImm (rRegI dst, immI8 shift) %{ // SHL, SAR, SHR |
| 0 | 1937 $$$emit8$primary; |
| 1938 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); | |
| 1939 $$$emit8$shift$$constant; | |
| 1940 %} | |
| 1941 | |
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1942 enc_class LdImmI (rRegI dst, immI src) %{ // Load Immediate |
| 0 | 1943 // Load immediate does not have a zero or sign extended version |
| 1944 // for 8-bit immediates | |
| 1945 emit_opcode(cbuf, 0xB8 + $dst$$reg); | |
| 1946 $$$emit32$src$$constant; | |
| 1947 %} | |
| 1948 | |
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1949 enc_class LdImmP (rRegI dst, immI src) %{ // Load Immediate |
| 0 | 1950 // Load immediate does not have a zero or sign extended version |
| 1951 // for 8-bit immediates | |
| 1952 emit_opcode(cbuf, $primary + $dst$$reg); | |
| 1953 $$$emit32$src$$constant; | |
| 1954 %} | |
| 1955 | |
| 1956 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate | |
| 1957 // Load immediate does not have a zero or sign extended version | |
| 1958 // for 8-bit immediates | |
| 1959 int dst_enc = $dst$$reg; | |
| 1960 int src_con = $src$$constant & 0x0FFFFFFFFL; | |
| 1961 if (src_con == 0) { | |
| 1962 // xor dst, dst | |
| 1963 emit_opcode(cbuf, 0x33); | |
| 1964 emit_rm(cbuf, 0x3, dst_enc, dst_enc); | |
| 1965 } else { | |
| 1966 emit_opcode(cbuf, $primary + dst_enc); | |
| 1967 emit_d32(cbuf, src_con); | |
| 1968 } | |
| 1969 %} | |
| 1970 | |
| 1971 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate | |
| 1972 // Load immediate does not have a zero or sign extended version | |
| 1973 // for 8-bit immediates | |
| 1974 int dst_enc = $dst$$reg + 2; | |
| 1975 int src_con = ((julong)($src$$constant)) >> 32; | |
| 1976 if (src_con == 0) { | |
| 1977 // xor dst, dst | |
| 1978 emit_opcode(cbuf, 0x33); | |
| 1979 emit_rm(cbuf, 0x3, dst_enc, dst_enc); | |
| 1980 } else { | |
| 1981 emit_opcode(cbuf, $primary + dst_enc); | |
| 1982 emit_d32(cbuf, src_con); | |
| 1983 } | |
| 1984 %} | |
| 1985 | |
| 1986 | |
| 1987 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
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1988 enc_class enc_Copy( rRegI dst, rRegI src ) %{ |
| 0 | 1989 encode_Copy( cbuf, $dst$$reg, $src$$reg ); |
| 1990 %} | |
| 1991 | |
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1992 enc_class enc_CopyL_Lo( rRegI dst, eRegL src ) %{ |
| 0 | 1993 encode_Copy( cbuf, $dst$$reg, $src$$reg ); |
| 1994 %} | |
| 1995 | |
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1996 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many) |
| 0 | 1997 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); |
| 1998 %} | |
| 1999 | |
| 2000 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 2001 $$$emit8$primary; | |
| 2002 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2003 %} | |
| 2004 | |
| 2005 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 2006 $$$emit8$secondary; | |
| 2007 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg)); | |
| 2008 %} | |
| 2009 | |
| 2010 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 2011 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2012 %} | |
| 2013 | |
| 2014 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 2015 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg)); | |
| 2016 %} | |
| 2017 | |
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2018 enc_class RegReg_HiLo( eRegL src, rRegI dst ) %{ |
| 0 | 2019 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg)); |
| 2020 %} | |
| 2021 | |
| 2022 enc_class Con32 (immI src) %{ // Con32(storeImmI) | |
| 2023 // Output immediate | |
| 2024 $$$emit32$src$$constant; | |
| 2025 %} | |
| 2026 | |
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2027 enc_class Con32FPR_as_bits(immFPR src) %{ // storeF_imm |
| 0 | 2028 // Output Float immediate bits |
| 2029 jfloat jf = $src$$constant; | |
| 2030 int jf_as_bits = jint_cast( jf ); | |
| 2031 emit_d32(cbuf, jf_as_bits); | |
| 2032 %} | |
| 2033 | |
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2034 enc_class Con32F_as_bits(immF src) %{ // storeX_imm |
| 0 | 2035 // Output Float immediate bits |
| 2036 jfloat jf = $src$$constant; | |
| 2037 int jf_as_bits = jint_cast( jf ); | |
| 2038 emit_d32(cbuf, jf_as_bits); | |
| 2039 %} | |
| 2040 | |
| 2041 enc_class Con16 (immI src) %{ // Con16(storeImmI) | |
| 2042 // Output immediate | |
| 2043 $$$emit16$src$$constant; | |
| 2044 %} | |
| 2045 | |
| 2046 enc_class Con_d32(immI src) %{ | |
| 2047 emit_d32(cbuf,$src$$constant); | |
| 2048 %} | |
| 2049 | |
| 2050 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI) | |
| 2051 // Output immediate memory reference | |
| 2052 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 ); | |
| 2053 emit_d32(cbuf, 0x00); | |
| 2054 %} | |
| 2055 | |
| 2056 enc_class lock_prefix( ) %{ | |
| 2057 if( os::is_MP() ) | |
| 2058 emit_opcode(cbuf,0xF0); // [Lock] | |
| 2059 %} | |
| 2060 | |
| 2061 // Cmp-xchg long value. | |
| 2062 // Note: we need to swap rbx, and rcx before and after the | |
| 2063 // cmpxchg8 instruction because the instruction uses | |
| 2064 // rcx as the high order word of the new value to store but | |
| 2065 // our register encoding uses rbx,. | |
| 2066 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{ | |
| 2067 | |
| 2068 // XCHG rbx,ecx | |
| 2069 emit_opcode(cbuf,0x87); | |
| 2070 emit_opcode(cbuf,0xD9); | |
| 2071 // [Lock] | |
| 2072 if( os::is_MP() ) | |
| 2073 emit_opcode(cbuf,0xF0); | |
| 2074 // CMPXCHG8 [Eptr] | |
| 2075 emit_opcode(cbuf,0x0F); | |
| 2076 emit_opcode(cbuf,0xC7); | |
| 2077 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg ); | |
| 2078 // XCHG rbx,ecx | |
| 2079 emit_opcode(cbuf,0x87); | |
| 2080 emit_opcode(cbuf,0xD9); | |
| 2081 %} | |
| 2082 | |
| 2083 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{ | |
| 2084 // [Lock] | |
| 2085 if( os::is_MP() ) | |
| 2086 emit_opcode(cbuf,0xF0); | |
| 2087 | |
| 2088 // CMPXCHG [Eptr] | |
| 2089 emit_opcode(cbuf,0x0F); | |
| 2090 emit_opcode(cbuf,0xB1); | |
| 2091 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg ); | |
| 2092 %} | |
| 2093 | |
| 2094 enc_class enc_flags_ne_to_boolean( iRegI res ) %{ | |
| 2095 int res_encoding = $res$$reg; | |
| 2096 | |
| 2097 // MOV res,0 | |
| 2098 emit_opcode( cbuf, 0xB8 + res_encoding); | |
| 2099 emit_d32( cbuf, 0 ); | |
| 2100 // JNE,s fail | |
| 2101 emit_opcode(cbuf,0x75); | |
| 2102 emit_d8(cbuf, 5 ); | |
| 2103 // MOV res,1 | |
| 2104 emit_opcode( cbuf, 0xB8 + res_encoding); | |
| 2105 emit_d32( cbuf, 1 ); | |
| 2106 // fail: | |
| 2107 %} | |
| 2108 | |
| 2109 enc_class set_instruction_start( ) %{ | |
| 1748 | 2110 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand |
| 0 | 2111 %} |
| 2112 | |
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2113 enc_class RegMem (rRegI ereg, memory mem) %{ // emit_reg_mem |
| 0 | 2114 int reg_encoding = $ereg$$reg; |
| 2115 int base = $mem$$base; | |
| 2116 int index = $mem$$index; | |
| 2117 int scale = $mem$$scale; | |
| 2118 int displace = $mem$$disp; | |
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2119 relocInfo::relocType disp_reloc = $mem->disp_reloc(); |
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2120 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc); |
| 0 | 2121 %} |
| 2122 | |
| 2123 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem | |
| 2124 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo | |
| 2125 int base = $mem$$base; | |
| 2126 int index = $mem$$index; | |
| 2127 int scale = $mem$$scale; | |
| 2128 int displace = $mem$$disp + 4; // Offset is 4 further in memory | |
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2129 assert( $mem->disp_reloc() == relocInfo::none, "Cannot add 4 to oop" ); |
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2130 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, relocInfo::none); |
| 0 | 2131 %} |
| 2132 | |
| 2133 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{ | |
| 2134 int r1, r2; | |
| 2135 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); } | |
| 2136 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); } | |
| 2137 emit_opcode(cbuf,0x0F); | |
| 2138 emit_opcode(cbuf,$tertiary); | |
| 2139 emit_rm(cbuf, 0x3, r1, r2); | |
| 2140 emit_d8(cbuf,$cnt$$constant); | |
| 2141 emit_d8(cbuf,$primary); | |
| 2142 emit_rm(cbuf, 0x3, $secondary, r1); | |
| 2143 emit_d8(cbuf,$cnt$$constant); | |
| 2144 %} | |
| 2145 | |
| 2146 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{ | |
| 2147 emit_opcode( cbuf, 0x8B ); // Move | |
| 2148 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg)); | |
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2149 if( $cnt$$constant > 32 ) { // Shift, if not by zero |
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2150 emit_d8(cbuf,$primary); |
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2151 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); |
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2152 emit_d8(cbuf,$cnt$$constant-32); |
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2153 } |
| 0 | 2154 emit_d8(cbuf,$primary); |
| 2155 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg)); | |
| 2156 emit_d8(cbuf,31); | |
| 2157 %} | |
| 2158 | |
| 2159 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{ | |
| 2160 int r1, r2; | |
| 2161 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); } | |
| 2162 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); } | |
| 2163 | |
| 2164 emit_opcode( cbuf, 0x8B ); // Move r1,r2 | |
| 2165 emit_rm(cbuf, 0x3, r1, r2); | |
| 2166 if( $cnt$$constant > 32 ) { // Shift, if not by zero | |
| 2167 emit_opcode(cbuf,$primary); | |
| 2168 emit_rm(cbuf, 0x3, $secondary, r1); | |
| 2169 emit_d8(cbuf,$cnt$$constant-32); | |
| 2170 } | |
| 2171 emit_opcode(cbuf,0x33); // XOR r2,r2 | |
| 2172 emit_rm(cbuf, 0x3, r2, r2); | |
| 2173 %} | |
| 2174 | |
| 2175 // Clone of RegMem but accepts an extra parameter to access each | |
| 2176 // half of a double in memory; it never needs relocation info. | |
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2177 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, rRegI rm_reg) %{ |
| 0 | 2178 emit_opcode(cbuf,$opcode$$constant); |
| 2179 int reg_encoding = $rm_reg$$reg; | |
| 2180 int base = $mem$$base; | |
| 2181 int index = $mem$$index; | |
| 2182 int scale = $mem$$scale; | |
| 2183 int displace = $mem$$disp + $disp_for_half$$constant; | |
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2184 relocInfo::relocType disp_reloc = relocInfo::none; |
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2185 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc); |
| 0 | 2186 %} |
| 2187 | |
| 2188 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!! | |
| 2189 // | |
| 2190 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant | |
| 2191 // and it never needs relocation information. | |
| 2192 // Frequently used to move data between FPU's Stack Top and memory. | |
| 2193 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{ | |
| 2194 int rm_byte_opcode = $rm_opcode$$constant; | |
| 2195 int base = $mem$$base; | |
| 2196 int index = $mem$$index; | |
| 2197 int scale = $mem$$scale; | |
| 2198 int displace = $mem$$disp; | |
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2199 assert( $mem->disp_reloc() == relocInfo::none, "No oops here because no reloc info allowed" ); |
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2200 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, relocInfo::none); |
| 0 | 2201 %} |
| 2202 | |
| 2203 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{ | |
| 2204 int rm_byte_opcode = $rm_opcode$$constant; | |
| 2205 int base = $mem$$base; | |
| 2206 int index = $mem$$index; | |
| 2207 int scale = $mem$$scale; | |
| 2208 int displace = $mem$$disp; | |
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2209 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals |
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2210 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc); |
| 0 | 2211 %} |
| 2212 | |
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2213 enc_class RegLea (rRegI dst, rRegI src0, immI src1 ) %{ // emit_reg_lea |
| 0 | 2214 int reg_encoding = $dst$$reg; |
| 2215 int base = $src0$$reg; // 0xFFFFFFFF indicates no base | |
| 2216 int index = 0x04; // 0x04 indicates no index | |
| 2217 int scale = 0x00; // 0x00 indicates no scale | |
| 2218 int displace = $src1$$constant; // 0x00 indicates no displacement | |
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2219 relocInfo::relocType disp_reloc = relocInfo::none; |
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2220 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc); |
| 0 | 2221 %} |
| 2222 | |
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2223 enc_class min_enc (rRegI dst, rRegI src) %{ // MIN |
| 0 | 2224 // Compare dst,src |
| 2225 emit_opcode(cbuf,0x3B); | |
| 2226 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2227 // jmp dst < src around move | |
| 2228 emit_opcode(cbuf,0x7C); | |
| 2229 emit_d8(cbuf,2); | |
| 2230 // move dst,src | |
| 2231 emit_opcode(cbuf,0x8B); | |
| 2232 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2233 %} | |
| 2234 | |
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2235 enc_class max_enc (rRegI dst, rRegI src) %{ // MAX |
| 0 | 2236 // Compare dst,src |
| 2237 emit_opcode(cbuf,0x3B); | |
| 2238 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2239 // jmp dst > src around move | |
| 2240 emit_opcode(cbuf,0x7F); | |
| 2241 emit_d8(cbuf,2); | |
| 2242 // move dst,src | |
| 2243 emit_opcode(cbuf,0x8B); | |
| 2244 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2245 %} | |
| 2246 | |
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2247 enc_class enc_FPR_store(memory mem, regDPR src) %{ |
| 0 | 2248 // If src is FPR1, we can just FST to store it. |
| 2249 // Else we need to FLD it to FPR1, then FSTP to store/pop it. | |
| 2250 int reg_encoding = 0x2; // Just store | |
| 2251 int base = $mem$$base; | |
| 2252 int index = $mem$$index; | |
| 2253 int scale = $mem$$scale; | |
| 2254 int displace = $mem$$disp; | |
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2255 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals |
| 0 | 2256 if( $src$$reg != FPR1L_enc ) { |
| 2257 reg_encoding = 0x3; // Store & pop | |
| 2258 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it) | |
| 2259 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2260 } | |
| 1748 | 2261 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand |
| 0 | 2262 emit_opcode(cbuf,$primary); |
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2263 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc); |
| 0 | 2264 %} |
| 2265 | |
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2266 enc_class neg_reg(rRegI dst) %{ |
| 0 | 2267 // NEG $dst |
| 2268 emit_opcode(cbuf,0xF7); | |
| 2269 emit_rm(cbuf, 0x3, 0x03, $dst$$reg ); | |
| 2270 %} | |
| 2271 | |
| 2272 enc_class setLT_reg(eCXRegI dst) %{ | |
| 2273 // SETLT $dst | |
| 2274 emit_opcode(cbuf,0x0F); | |
| 2275 emit_opcode(cbuf,0x9C); | |
| 2276 emit_rm( cbuf, 0x3, 0x4, $dst$$reg ); | |
| 2277 %} | |
| 2278 | |
| 2279 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT | |
| 2280 int tmpReg = $tmp$$reg; | |
| 2281 | |
| 2282 // SUB $p,$q | |
| 2283 emit_opcode(cbuf,0x2B); | |
| 2284 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg); | |
| 2285 // SBB $tmp,$tmp | |
| 2286 emit_opcode(cbuf,0x1B); | |
| 2287 emit_rm(cbuf, 0x3, tmpReg, tmpReg); | |
| 2288 // AND $tmp,$y | |
| 2289 emit_opcode(cbuf,0x23); | |
| 2290 emit_rm(cbuf, 0x3, tmpReg, $y$$reg); | |
| 2291 // ADD $p,$tmp | |
| 2292 emit_opcode(cbuf,0x03); | |
| 2293 emit_rm(cbuf, 0x3, $p$$reg, tmpReg); | |
| 2294 %} | |
| 2295 | |
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2296 enc_class enc_cmpLTP_mem(rRegI p, rRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT |
| 0 | 2297 int tmpReg = $tmp$$reg; |
| 2298 | |
| 2299 // SUB $p,$q | |
| 2300 emit_opcode(cbuf,0x2B); | |
| 2301 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg); | |
| 2302 // SBB $tmp,$tmp | |
| 2303 emit_opcode(cbuf,0x1B); | |
| 2304 emit_rm(cbuf, 0x3, tmpReg, tmpReg); | |
| 2305 // AND $tmp,$y | |
| 1748 | 2306 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand |
| 0 | 2307 emit_opcode(cbuf,0x23); |
| 2308 int reg_encoding = tmpReg; | |
| 2309 int base = $mem$$base; | |
| 2310 int index = $mem$$index; | |
| 2311 int scale = $mem$$scale; | |
| 2312 int displace = $mem$$disp; | |
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2313 relocInfo::relocType disp_reloc = $mem->disp_reloc(); |
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2314 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc); |
| 0 | 2315 // ADD $p,$tmp |
| 2316 emit_opcode(cbuf,0x03); | |
| 2317 emit_rm(cbuf, 0x3, $p$$reg, tmpReg); | |
| 2318 %} | |
| 2319 | |
| 2320 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{ | |
| 2321 // TEST shift,32 | |
| 2322 emit_opcode(cbuf,0xF7); | |
| 2323 emit_rm(cbuf, 0x3, 0, ECX_enc); | |
| 2324 emit_d32(cbuf,0x20); | |
| 2325 // JEQ,s small | |
| 2326 emit_opcode(cbuf, 0x74); | |
| 2327 emit_d8(cbuf, 0x04); | |
| 2328 // MOV $dst.hi,$dst.lo | |
| 2329 emit_opcode( cbuf, 0x8B ); | |
| 2330 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg ); | |
| 2331 // CLR $dst.lo | |
| 2332 emit_opcode(cbuf, 0x33); | |
| 2333 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg); | |
| 2334 // small: | |
| 2335 // SHLD $dst.hi,$dst.lo,$shift | |
| 2336 emit_opcode(cbuf,0x0F); | |
| 2337 emit_opcode(cbuf,0xA5); | |
| 2338 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg)); | |
| 2339 // SHL $dst.lo,$shift" | |
| 2340 emit_opcode(cbuf,0xD3); | |
| 2341 emit_rm(cbuf, 0x3, 0x4, $dst$$reg ); | |
| 2342 %} | |
| 2343 | |
| 2344 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{ | |
| 2345 // TEST shift,32 | |
| 2346 emit_opcode(cbuf,0xF7); | |
| 2347 emit_rm(cbuf, 0x3, 0, ECX_enc); | |
| 2348 emit_d32(cbuf,0x20); | |
| 2349 // JEQ,s small | |
| 2350 emit_opcode(cbuf, 0x74); | |
| 2351 emit_d8(cbuf, 0x04); | |
| 2352 // MOV $dst.lo,$dst.hi | |
| 2353 emit_opcode( cbuf, 0x8B ); | |
| 2354 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2355 // CLR $dst.hi | |
| 2356 emit_opcode(cbuf, 0x33); | |
| 2357 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg)); | |
| 2358 // small: | |
| 2359 // SHRD $dst.lo,$dst.hi,$shift | |
| 2360 emit_opcode(cbuf,0x0F); | |
| 2361 emit_opcode(cbuf,0xAD); | |
| 2362 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg); | |
| 2363 // SHR $dst.hi,$shift" | |
| 2364 emit_opcode(cbuf,0xD3); | |
| 2365 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) ); | |
| 2366 %} | |
| 2367 | |
| 2368 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{ | |
| 2369 // TEST shift,32 | |
| 2370 emit_opcode(cbuf,0xF7); | |
| 2371 emit_rm(cbuf, 0x3, 0, ECX_enc); | |
| 2372 emit_d32(cbuf,0x20); | |
| 2373 // JEQ,s small | |
| 2374 emit_opcode(cbuf, 0x74); | |
| 2375 emit_d8(cbuf, 0x05); | |
| 2376 // MOV $dst.lo,$dst.hi | |
| 2377 emit_opcode( cbuf, 0x8B ); | |
| 2378 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2379 // SAR $dst.hi,31 | |
| 2380 emit_opcode(cbuf, 0xC1); | |
| 2381 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) ); | |
| 2382 emit_d8(cbuf, 0x1F ); | |
| 2383 // small: | |
| 2384 // SHRD $dst.lo,$dst.hi,$shift | |
| 2385 emit_opcode(cbuf,0x0F); | |
| 2386 emit_opcode(cbuf,0xAD); | |
| 2387 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg); | |
| 2388 // SAR $dst.hi,$shift" | |
| 2389 emit_opcode(cbuf,0xD3); | |
| 2390 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) ); | |
| 2391 %} | |
| 2392 | |
| 2393 | |
| 2394 // ----------------- Encodings for floating point unit ----------------- | |
| 2395 // May leave result in FPU-TOS or FPU reg depending on opcodes | |
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2396 enc_class OpcReg_FPR(regFPR src) %{ // FMUL, FDIV |
| 0 | 2397 $$$emit8$primary; |
| 2398 emit_rm(cbuf, 0x3, $secondary, $src$$reg ); | |
| 2399 %} | |
| 2400 | |
| 2401 // Pop argument in FPR0 with FSTP ST(0) | |
| 2402 enc_class PopFPU() %{ | |
| 2403 emit_opcode( cbuf, 0xDD ); | |
| 2404 emit_d8( cbuf, 0xD8 ); | |
| 2405 %} | |
| 2406 | |
| 2407 // !!!!! equivalent to Pop_Reg_F | |
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2408 enc_class Pop_Reg_DPR( regDPR dst ) %{ |
| 0 | 2409 emit_opcode( cbuf, 0xDD ); // FSTP ST(i) |
| 2410 emit_d8( cbuf, 0xD8+$dst$$reg ); | |
| 2411 %} | |
| 2412 | |
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2413 enc_class Push_Reg_DPR( regDPR dst ) %{ |
| 0 | 2414 emit_opcode( cbuf, 0xD9 ); |
| 2415 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1) | |
| 2416 %} | |
| 2417 | |
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2418 enc_class strictfp_bias1( regDPR dst ) %{ |
| 0 | 2419 emit_opcode( cbuf, 0xDB ); // FLD m80real |
| 2420 emit_opcode( cbuf, 0x2D ); | |
| 2421 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() ); | |
| 2422 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0 | |
| 2423 emit_opcode( cbuf, 0xC8+$dst$$reg ); | |
| 2424 %} | |
| 2425 | |
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2426 enc_class strictfp_bias2( regDPR dst ) %{ |
| 0 | 2427 emit_opcode( cbuf, 0xDB ); // FLD m80real |
| 2428 emit_opcode( cbuf, 0x2D ); | |
| 2429 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() ); | |
| 2430 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0 | |
| 2431 emit_opcode( cbuf, 0xC8+$dst$$reg ); | |
| 2432 %} | |
| 2433 | |
| 2434 // Special case for moving an integer register to a stack slot. | |
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2435 enc_class OpcPRegSS( stackSlotI dst, rRegI src ) %{ // RegSS |
| 0 | 2436 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp ); |
| 2437 %} | |
| 2438 | |
| 2439 // Special case for moving a register to a stack slot. | |
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2440 enc_class RegSS( stackSlotI dst, rRegI src ) %{ // RegSS |
| 0 | 2441 // Opcode already emitted |
| 2442 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte | |
| 2443 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte | |
| 2444 emit_d32(cbuf, $dst$$disp); // Displacement | |
| 2445 %} | |
| 2446 | |
| 2447 // Push the integer in stackSlot 'src' onto FP-stack | |
| 2448 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src] | |
| 2449 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp ); | |
| 2450 %} | |
| 2451 | |
| 2452 // Push FPU's TOS float to a stack-slot, and pop FPU-stack | |
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2453 enc_class Pop_Mem_FPR( stackSlotF dst ) %{ // FSTP_S [ESP+dst] |
| 0 | 2454 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp ); |
| 2455 %} | |
| 2456 | |
| 2457 // Same as Pop_Mem_F except for opcode | |
| 2458 // Push FPU's TOS double to a stack-slot, and pop FPU-stack | |
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2459 enc_class Pop_Mem_DPR( stackSlotD dst ) %{ // FSTP_D [ESP+dst] |
| 0 | 2460 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp ); |
| 2461 %} | |
| 2462 | |
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2463 enc_class Pop_Reg_FPR( regFPR dst ) %{ |
| 0 | 2464 emit_opcode( cbuf, 0xDD ); // FSTP ST(i) |
| 2465 emit_d8( cbuf, 0xD8+$dst$$reg ); | |
| 2466 %} | |
| 2467 | |
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2468 enc_class Push_Reg_FPR( regFPR dst ) %{ |
| 0 | 2469 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) |
| 2470 emit_d8( cbuf, 0xC0-1+$dst$$reg ); | |
| 2471 %} | |
| 2472 | |
| 2473 // Push FPU's float to a stack-slot, and pop FPU-stack | |
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2474 enc_class Pop_Mem_Reg_FPR( stackSlotF dst, regFPR src ) %{ |
| 0 | 2475 int pop = 0x02; |
| 2476 if ($src$$reg != FPR1L_enc) { | |
| 2477 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) | |
| 2478 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2479 pop = 0x03; | |
| 2480 } | |
| 2481 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst] | |
| 2482 %} | |
| 2483 | |
| 2484 // Push FPU's double to a stack-slot, and pop FPU-stack | |
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2485 enc_class Pop_Mem_Reg_DPR( stackSlotD dst, regDPR src ) %{ |
| 0 | 2486 int pop = 0x02; |
| 2487 if ($src$$reg != FPR1L_enc) { | |
| 2488 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) | |
| 2489 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2490 pop = 0x03; | |
| 2491 } | |
| 2492 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst] | |
| 2493 %} | |
| 2494 | |
| 2495 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack | |
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2496 enc_class Pop_Reg_Reg_DPR( regDPR dst, regFPR src ) %{ |
| 0 | 2497 int pop = 0xD0 - 1; // -1 since we skip FLD |
| 2498 if ($src$$reg != FPR1L_enc) { | |
| 2499 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1) | |
| 2500 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2501 pop = 0xD8; | |
| 2502 } | |
| 2503 emit_opcode( cbuf, 0xDD ); | |
| 2504 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i) | |
| 2505 %} | |
| 2506 | |
| 2507 | |
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2508 enc_class Push_Reg_Mod_DPR( regDPR dst, regDPR src) %{ |
| 0 | 2509 // load dst in FPR0 |
| 2510 emit_opcode( cbuf, 0xD9 ); | |
| 2511 emit_d8( cbuf, 0xC0-1+$dst$$reg ); | |
| 2512 if ($src$$reg != FPR1L_enc) { | |
| 2513 // fincstp | |
| 2514 emit_opcode (cbuf, 0xD9); | |
| 2515 emit_opcode (cbuf, 0xF7); | |
| 2516 // swap src with FPR1: | |
| 2517 // FXCH FPR1 with src | |
| 2518 emit_opcode(cbuf, 0xD9); | |
| 2519 emit_d8(cbuf, 0xC8-1+$src$$reg ); | |
| 2520 // fdecstp | |
| 2521 emit_opcode (cbuf, 0xD9); | |
| 2522 emit_opcode (cbuf, 0xF6); | |
| 2523 } | |
| 2524 %} | |
| 2525 | |
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2526 enc_class Push_ModD_encoding(regD src0, regD src1) %{ |
| 4759 | 2527 MacroAssembler _masm(&cbuf); |
| 2528 __ subptr(rsp, 8); | |
| 2529 __ movdbl(Address(rsp, 0), $src1$$XMMRegister); | |
| 2530 __ fld_d(Address(rsp, 0)); | |
| 2531 __ movdbl(Address(rsp, 0), $src0$$XMMRegister); | |
| 2532 __ fld_d(Address(rsp, 0)); | |
| 2533 %} | |
| 2534 | |
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2535 enc_class Push_ModF_encoding(regF src0, regF src1) %{ |
| 4759 | 2536 MacroAssembler _masm(&cbuf); |
| 2537 __ subptr(rsp, 4); | |
| 2538 __ movflt(Address(rsp, 0), $src1$$XMMRegister); | |
| 2539 __ fld_s(Address(rsp, 0)); | |
| 2540 __ movflt(Address(rsp, 0), $src0$$XMMRegister); | |
| 2541 __ fld_s(Address(rsp, 0)); | |
| 0 | 2542 %} |
| 2543 | |
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2544 enc_class Push_ResultD(regD dst) %{ |
| 4759 | 2545 MacroAssembler _masm(&cbuf); |
| 2546 __ fstp_d(Address(rsp, 0)); | |
| 2547 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); | |
| 2548 __ addptr(rsp, 8); | |
| 0 | 2549 %} |
| 2550 | |
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2551 enc_class Push_ResultF(regF dst, immI d8) %{ |
| 4759 | 2552 MacroAssembler _masm(&cbuf); |
| 2553 __ fstp_s(Address(rsp, 0)); | |
| 2554 __ movflt($dst$$XMMRegister, Address(rsp, 0)); | |
| 2555 __ addptr(rsp, $d8$$constant); | |
| 0 | 2556 %} |
| 2557 | |
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2558 enc_class Push_SrcD(regD src) %{ |
| 4759 | 2559 MacroAssembler _masm(&cbuf); |
| 2560 __ subptr(rsp, 8); | |
| 2561 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 2562 __ fld_d(Address(rsp, 0)); | |
| 0 | 2563 %} |
| 2564 | |
| 2565 enc_class push_stack_temp_qword() %{ | |
| 4759 | 2566 MacroAssembler _masm(&cbuf); |
| 2567 __ subptr(rsp, 8); | |
| 0 | 2568 %} |
| 2569 | |
| 2570 enc_class pop_stack_temp_qword() %{ | |
| 4759 | 2571 MacroAssembler _masm(&cbuf); |
| 2572 __ addptr(rsp, 8); | |
| 2573 %} | |
| 2574 | |
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2575 enc_class push_xmm_to_fpr1(regD src) %{ |
| 4759 | 2576 MacroAssembler _masm(&cbuf); |
| 2577 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 2578 __ fld_d(Address(rsp, 0)); | |
| 0 | 2579 %} |
| 2580 | |
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2581 enc_class Push_Result_Mod_DPR( regDPR src) %{ |
| 0 | 2582 if ($src$$reg != FPR1L_enc) { |
| 2583 // fincstp | |
| 2584 emit_opcode (cbuf, 0xD9); | |
| 2585 emit_opcode (cbuf, 0xF7); | |
| 2586 // FXCH FPR1 with src | |
| 2587 emit_opcode(cbuf, 0xD9); | |
| 2588 emit_d8(cbuf, 0xC8-1+$src$$reg ); | |
| 2589 // fdecstp | |
| 2590 emit_opcode (cbuf, 0xD9); | |
| 2591 emit_opcode (cbuf, 0xF6); | |
| 2592 } | |
| 2593 // // following asm replaced with Pop_Reg_F or Pop_Mem_F | |
| 2594 // // FSTP FPR$dst$$reg | |
| 2595 // emit_opcode( cbuf, 0xDD ); | |
| 2596 // emit_d8( cbuf, 0xD8+$dst$$reg ); | |
| 2597 %} | |
| 2598 | |
| 2599 enc_class fnstsw_sahf_skip_parity() %{ | |
| 2600 // fnstsw ax | |
| 2601 emit_opcode( cbuf, 0xDF ); | |
| 2602 emit_opcode( cbuf, 0xE0 ); | |
| 2603 // sahf | |
| 2604 emit_opcode( cbuf, 0x9E ); | |
| 2605 // jnp ::skip | |
| 2606 emit_opcode( cbuf, 0x7B ); | |
| 2607 emit_opcode( cbuf, 0x05 ); | |
| 2608 %} | |
| 2609 | |
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2610 enc_class emitModDPR() %{ |
| 0 | 2611 // fprem must be iterative |
| 2612 // :: loop | |
| 2613 // fprem | |
| 2614 emit_opcode( cbuf, 0xD9 ); | |
| 2615 emit_opcode( cbuf, 0xF8 ); | |
| 2616 // wait | |
| 2617 emit_opcode( cbuf, 0x9b ); | |
| 2618 // fnstsw ax | |
| 2619 emit_opcode( cbuf, 0xDF ); | |
| 2620 emit_opcode( cbuf, 0xE0 ); | |
| 2621 // sahf | |
| 2622 emit_opcode( cbuf, 0x9E ); | |
| 2623 // jp ::loop | |
| 2624 emit_opcode( cbuf, 0x0F ); | |
| 2625 emit_opcode( cbuf, 0x8A ); | |
| 2626 emit_opcode( cbuf, 0xF4 ); | |
| 2627 emit_opcode( cbuf, 0xFF ); | |
| 2628 emit_opcode( cbuf, 0xFF ); | |
| 2629 emit_opcode( cbuf, 0xFF ); | |
| 2630 %} | |
| 2631 | |
| 2632 enc_class fpu_flags() %{ | |
| 2633 // fnstsw_ax | |
| 2634 emit_opcode( cbuf, 0xDF); | |
| 2635 emit_opcode( cbuf, 0xE0); | |
| 2636 // test ax,0x0400 | |
| 2637 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate | |
| 2638 emit_opcode( cbuf, 0xA9 ); | |
| 2639 emit_d16 ( cbuf, 0x0400 ); | |
| 2640 // // // This sequence works, but stalls for 12-16 cycles on PPro | |
| 2641 // // test rax,0x0400 | |
| 2642 // emit_opcode( cbuf, 0xA9 ); | |
| 2643 // emit_d32 ( cbuf, 0x00000400 ); | |
| 2644 // | |
| 2645 // jz exit (no unordered comparison) | |
| 2646 emit_opcode( cbuf, 0x74 ); | |
| 2647 emit_d8 ( cbuf, 0x02 ); | |
| 2648 // mov ah,1 - treat as LT case (set carry flag) | |
| 2649 emit_opcode( cbuf, 0xB4 ); | |
| 2650 emit_d8 ( cbuf, 0x01 ); | |
| 2651 // sahf | |
| 2652 emit_opcode( cbuf, 0x9E); | |
| 2653 %} | |
| 2654 | |
| 2655 enc_class cmpF_P6_fixup() %{ | |
| 2656 // Fixup the integer flags in case comparison involved a NaN | |
| 2657 // | |
| 2658 // JNP exit (no unordered comparison, P-flag is set by NaN) | |
| 2659 emit_opcode( cbuf, 0x7B ); | |
| 2660 emit_d8 ( cbuf, 0x03 ); | |
| 2661 // MOV AH,1 - treat as LT case (set carry flag) | |
| 2662 emit_opcode( cbuf, 0xB4 ); | |
| 2663 emit_d8 ( cbuf, 0x01 ); | |
| 2664 // SAHF | |
| 2665 emit_opcode( cbuf, 0x9E); | |
| 2666 // NOP // target for branch to avoid branch to branch | |
| 2667 emit_opcode( cbuf, 0x90); | |
| 2668 %} | |
| 2669 | |
| 2670 // fnstsw_ax(); | |
| 2671 // sahf(); | |
| 2672 // movl(dst, nan_result); | |
| 2673 // jcc(Assembler::parity, exit); | |
| 2674 // movl(dst, less_result); | |
| 2675 // jcc(Assembler::below, exit); | |
| 2676 // movl(dst, equal_result); | |
| 2677 // jcc(Assembler::equal, exit); | |
| 2678 // movl(dst, greater_result); | |
| 2679 | |
| 2680 // less_result = 1; | |
| 2681 // greater_result = -1; | |
| 2682 // equal_result = 0; | |
| 2683 // nan_result = -1; | |
| 2684 | |
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2685 enc_class CmpF_Result(rRegI dst) %{ |
| 0 | 2686 // fnstsw_ax(); |
| 2687 emit_opcode( cbuf, 0xDF); | |
| 2688 emit_opcode( cbuf, 0xE0); | |
| 2689 // sahf | |
| 2690 emit_opcode( cbuf, 0x9E); | |
| 2691 // movl(dst, nan_result); | |
| 2692 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2693 emit_d32( cbuf, -1 ); | |
| 2694 // jcc(Assembler::parity, exit); | |
| 2695 emit_opcode( cbuf, 0x7A ); | |
| 2696 emit_d8 ( cbuf, 0x13 ); | |
| 2697 // movl(dst, less_result); | |
| 2698 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2699 emit_d32( cbuf, -1 ); | |
| 2700 // jcc(Assembler::below, exit); | |
| 2701 emit_opcode( cbuf, 0x72 ); | |
| 2702 emit_d8 ( cbuf, 0x0C ); | |
| 2703 // movl(dst, equal_result); | |
| 2704 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2705 emit_d32( cbuf, 0 ); | |
| 2706 // jcc(Assembler::equal, exit); | |
| 2707 emit_opcode( cbuf, 0x74 ); | |
| 2708 emit_d8 ( cbuf, 0x05 ); | |
| 2709 // movl(dst, greater_result); | |
| 2710 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2711 emit_d32( cbuf, 1 ); | |
| 2712 %} | |
| 2713 | |
| 2714 | |
| 2715 // Compare the longs and set flags | |
| 2716 // BROKEN! Do Not use as-is | |
| 2717 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{ | |
| 2718 // CMP $src1.hi,$src2.hi | |
| 2719 emit_opcode( cbuf, 0x3B ); | |
| 2720 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) ); | |
| 2721 // JNE,s done | |
| 2722 emit_opcode(cbuf,0x75); | |
| 2723 emit_d8(cbuf, 2 ); | |
| 2724 // CMP $src1.lo,$src2.lo | |
| 2725 emit_opcode( cbuf, 0x3B ); | |
| 2726 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); | |
| 2727 // done: | |
| 2728 %} | |
| 2729 | |
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2730 enc_class convert_int_long( regL dst, rRegI src ) %{ |
| 0 | 2731 // mov $dst.lo,$src |
| 2732 int dst_encoding = $dst$$reg; | |
| 2733 int src_encoding = $src$$reg; | |
| 2734 encode_Copy( cbuf, dst_encoding , src_encoding ); | |
| 2735 // mov $dst.hi,$src | |
| 2736 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding ); | |
| 2737 // sar $dst.hi,31 | |
| 2738 emit_opcode( cbuf, 0xC1 ); | |
| 2739 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) ); | |
| 2740 emit_d8(cbuf, 0x1F ); | |
| 2741 %} | |
| 2742 | |
| 2743 enc_class convert_long_double( eRegL src ) %{ | |
| 2744 // push $src.hi | |
| 2745 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg)); | |
| 2746 // push $src.lo | |
| 2747 emit_opcode(cbuf, 0x50+$src$$reg ); | |
| 2748 // fild 64-bits at [SP] | |
| 2749 emit_opcode(cbuf,0xdf); | |
| 2750 emit_d8(cbuf, 0x6C); | |
| 2751 emit_d8(cbuf, 0x24); | |
| 2752 emit_d8(cbuf, 0x00); | |
| 2753 // pop stack | |
| 2754 emit_opcode(cbuf, 0x83); // add SP, #8 | |
| 2755 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 2756 emit_d8(cbuf, 0x8); | |
| 2757 %} | |
| 2758 | |
| 2759 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{ | |
| 2760 // IMUL EDX:EAX,$src1 | |
| 2761 emit_opcode( cbuf, 0xF7 ); | |
| 2762 emit_rm( cbuf, 0x3, 0x5, $src1$$reg ); | |
| 2763 // SAR EDX,$cnt-32 | |
| 2764 int shift_count = ((int)$cnt$$constant) - 32; | |
| 2765 if (shift_count > 0) { | |
| 2766 emit_opcode(cbuf, 0xC1); | |
| 2767 emit_rm(cbuf, 0x3, 7, $dst$$reg ); | |
| 2768 emit_d8(cbuf, shift_count); | |
| 2769 } | |
| 2770 %} | |
| 2771 | |
| 2772 // this version doesn't have add sp, 8 | |
| 2773 enc_class convert_long_double2( eRegL src ) %{ | |
| 2774 // push $src.hi | |
| 2775 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg)); | |
| 2776 // push $src.lo | |
| 2777 emit_opcode(cbuf, 0x50+$src$$reg ); | |
| 2778 // fild 64-bits at [SP] | |
| 2779 emit_opcode(cbuf,0xdf); | |
| 2780 emit_d8(cbuf, 0x6C); | |
| 2781 emit_d8(cbuf, 0x24); | |
| 2782 emit_d8(cbuf, 0x00); | |
| 2783 %} | |
| 2784 | |
| 2785 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{ | |
| 2786 // Basic idea: long = (long)int * (long)int | |
| 2787 // IMUL EDX:EAX, src | |
| 2788 emit_opcode( cbuf, 0xF7 ); | |
| 2789 emit_rm( cbuf, 0x3, 0x5, $src$$reg); | |
| 2790 %} | |
| 2791 | |
| 2792 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{ | |
| 2793 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL) | |
| 2794 // MUL EDX:EAX, src | |
| 2795 emit_opcode( cbuf, 0xF7 ); | |
| 2796 emit_rm( cbuf, 0x3, 0x4, $src$$reg); | |
| 2797 %} | |
| 2798 | |
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2799 enc_class long_multiply( eADXRegL dst, eRegL src, rRegI tmp ) %{ |
| 0 | 2800 // Basic idea: lo(result) = lo(x_lo * y_lo) |
| 2801 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) | |
| 2802 // MOV $tmp,$src.lo | |
| 2803 encode_Copy( cbuf, $tmp$$reg, $src$$reg ); | |
| 2804 // IMUL $tmp,EDX | |
| 2805 emit_opcode( cbuf, 0x0F ); | |
| 2806 emit_opcode( cbuf, 0xAF ); | |
| 2807 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2808 // MOV EDX,$src.hi | |
| 2809 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) ); | |
| 2810 // IMUL EDX,EAX | |
| 2811 emit_opcode( cbuf, 0x0F ); | |
| 2812 emit_opcode( cbuf, 0xAF ); | |
| 2813 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg ); | |
| 2814 // ADD $tmp,EDX | |
| 2815 emit_opcode( cbuf, 0x03 ); | |
| 2816 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2817 // MUL EDX:EAX,$src.lo | |
| 2818 emit_opcode( cbuf, 0xF7 ); | |
| 2819 emit_rm( cbuf, 0x3, 0x4, $src$$reg ); | |
| 2820 // ADD EDX,ESI | |
| 2821 emit_opcode( cbuf, 0x03 ); | |
| 2822 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg ); | |
| 2823 %} | |
| 2824 | |
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2825 enc_class long_multiply_con( eADXRegL dst, immL_127 src, rRegI tmp ) %{ |
| 0 | 2826 // Basic idea: lo(result) = lo(src * y_lo) |
| 2827 // hi(result) = hi(src * y_lo) + lo(src * y_hi) | |
| 2828 // IMUL $tmp,EDX,$src | |
| 2829 emit_opcode( cbuf, 0x6B ); | |
| 2830 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2831 emit_d8( cbuf, (int)$src$$constant ); | |
| 2832 // MOV EDX,$src | |
| 2833 emit_opcode(cbuf, 0xB8 + EDX_enc); | |
| 2834 emit_d32( cbuf, (int)$src$$constant ); | |
| 2835 // MUL EDX:EAX,EDX | |
| 2836 emit_opcode( cbuf, 0xF7 ); | |
| 2837 emit_rm( cbuf, 0x3, 0x4, EDX_enc ); | |
| 2838 // ADD EDX,ESI | |
| 2839 emit_opcode( cbuf, 0x03 ); | |
| 2840 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg ); | |
| 2841 %} | |
| 2842 | |
| 2843 enc_class long_div( eRegL src1, eRegL src2 ) %{ | |
| 2844 // PUSH src1.hi | |
| 2845 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) ); | |
| 2846 // PUSH src1.lo | |
| 2847 emit_opcode(cbuf, 0x50+$src1$$reg ); | |
| 2848 // PUSH src2.hi | |
| 2849 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) ); | |
| 2850 // PUSH src2.lo | |
| 2851 emit_opcode(cbuf, 0x50+$src2$$reg ); | |
| 2852 // CALL directly to the runtime | |
| 1748 | 2853 cbuf.set_insts_mark(); |
| 0 | 2854 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 2855 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 2856 // Restore stack |
| 2857 emit_opcode(cbuf, 0x83); // add SP, #framesize | |
| 2858 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 2859 emit_d8(cbuf, 4*4); | |
| 2860 %} | |
| 2861 | |
| 2862 enc_class long_mod( eRegL src1, eRegL src2 ) %{ | |
| 2863 // PUSH src1.hi | |
| 2864 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) ); | |
| 2865 // PUSH src1.lo | |
| 2866 emit_opcode(cbuf, 0x50+$src1$$reg ); | |
| 2867 // PUSH src2.hi | |
| 2868 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) ); | |
| 2869 // PUSH src2.lo | |
| 2870 emit_opcode(cbuf, 0x50+$src2$$reg ); | |
| 2871 // CALL directly to the runtime | |
| 1748 | 2872 cbuf.set_insts_mark(); |
| 0 | 2873 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 2874 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 2875 // Restore stack |
| 2876 emit_opcode(cbuf, 0x83); // add SP, #framesize | |
| 2877 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 2878 emit_d8(cbuf, 4*4); | |
| 2879 %} | |
| 2880 | |
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2881 enc_class long_cmp_flags0( eRegL src, rRegI tmp ) %{ |
| 0 | 2882 // MOV $tmp,$src.lo |
| 2883 emit_opcode(cbuf, 0x8B); | |
| 2884 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg); | |
| 2885 // OR $tmp,$src.hi | |
| 2886 emit_opcode(cbuf, 0x0B); | |
| 2887 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg)); | |
| 2888 %} | |
| 2889 | |
| 2890 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{ | |
| 2891 // CMP $src1.lo,$src2.lo | |
| 2892 emit_opcode( cbuf, 0x3B ); | |
| 2893 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); | |
| 2894 // JNE,s skip | |
| 2895 emit_cc(cbuf, 0x70, 0x5); | |
| 2896 emit_d8(cbuf,2); | |
| 2897 // CMP $src1.hi,$src2.hi | |
| 2898 emit_opcode( cbuf, 0x3B ); | |
| 2899 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) ); | |
| 2900 %} | |
| 2901 | |
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2902 enc_class long_cmp_flags2( eRegL src1, eRegL src2, rRegI tmp ) %{ |
| 0 | 2903 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits |
| 2904 emit_opcode( cbuf, 0x3B ); | |
| 2905 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); | |
| 2906 // MOV $tmp,$src1.hi | |
| 2907 emit_opcode( cbuf, 0x8B ); | |
| 2908 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) ); | |
| 2909 // SBB $tmp,$src2.hi\t! Compute flags for long compare | |
| 2910 emit_opcode( cbuf, 0x1B ); | |
| 2911 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) ); | |
| 2912 %} | |
| 2913 | |
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2914 enc_class long_cmp_flags3( eRegL src, rRegI tmp ) %{ |
| 0 | 2915 // XOR $tmp,$tmp |
| 2916 emit_opcode(cbuf,0x33); // XOR | |
| 2917 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg); | |
| 2918 // CMP $tmp,$src.lo | |
| 2919 emit_opcode( cbuf, 0x3B ); | |
| 2920 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg ); | |
| 2921 // SBB $tmp,$src.hi | |
| 2922 emit_opcode( cbuf, 0x1B ); | |
| 2923 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) ); | |
| 2924 %} | |
| 2925 | |
| 2926 // Sniff, sniff... smells like Gnu Superoptimizer | |
| 2927 enc_class neg_long( eRegL dst ) %{ | |
| 2928 emit_opcode(cbuf,0xF7); // NEG hi | |
| 2929 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg)); | |
| 2930 emit_opcode(cbuf,0xF7); // NEG lo | |
| 2931 emit_rm (cbuf,0x3, 0x3, $dst$$reg ); | |
| 2932 emit_opcode(cbuf,0x83); // SBB hi,0 | |
| 2933 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg)); | |
| 2934 emit_d8 (cbuf,0 ); | |
| 2935 %} | |
| 2936 | |
| 2937 | |
| 2938 // Because the transitions from emitted code to the runtime | |
| 2939 // monitorenter/exit helper stubs are so slow it's critical that | |
| 2940 // we inline both the stack-locking fast-path and the inflated fast path. | |
| 2941 // | |
| 2942 // See also: cmpFastLock and cmpFastUnlock. | |
| 2943 // | |
| 2944 // What follows is a specialized inline transliteration of the code | |
| 2945 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat | |
| 2946 // another option would be to emit TrySlowEnter and TrySlowExit methods | |
| 2947 // at startup-time. These methods would accept arguments as | |
| 2948 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure | |
| 2949 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply | |
| 2950 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit. | |
| 2951 // In practice, however, the # of lock sites is bounded and is usually small. | |
| 2952 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer | |
| 2953 // if the processor uses simple bimodal branch predictors keyed by EIP | |
| 2954 // Since the helper routines would be called from multiple synchronization | |
| 2955 // sites. | |
| 2956 // | |
| 2957 // An even better approach would be write "MonitorEnter()" and "MonitorExit()" | |
| 2958 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites | |
| 2959 // to those specialized methods. That'd give us a mostly platform-independent | |
| 2960 // implementation that the JITs could optimize and inline at their pleasure. | |
| 2961 // Done correctly, the only time we'd need to cross to native could would be | |
| 2962 // to park() or unpark() threads. We'd also need a few more unsafe operators | |
| 2963 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and | |
| 2964 // (b) explicit barriers or fence operations. | |
| 2965 // | |
| 2966 // TODO: | |
| 2967 // | |
| 2968 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr). | |
| 2969 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals. | |
| 2970 // Given TLAB allocation, Self is usually manifested in a register, so passing it into | |
| 2971 // the lock operators would typically be faster than reifying Self. | |
| 2972 // | |
| 2973 // * Ideally I'd define the primitives as: | |
| 2974 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED. | |
| 2975 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED | |
| 2976 // Unfortunately ADLC bugs prevent us from expressing the ideal form. | |
| 2977 // Instead, we're stuck with a rather awkward and brittle register assignments below. | |
| 2978 // Furthermore the register assignments are overconstrained, possibly resulting in | |
| 2979 // sub-optimal code near the synchronization site. | |
| 2980 // | |
| 2981 // * Eliminate the sp-proximity tests and just use "== Self" tests instead. | |
| 2982 // Alternately, use a better sp-proximity test. | |
| 2983 // | |
| 2984 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value. | |
| 2985 // Either one is sufficient to uniquely identify a thread. | |
| 2986 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead. | |
| 2987 // | |
| 2988 // * Intrinsify notify() and notifyAll() for the common cases where the | |
| 2989 // object is locked by the calling thread but the waitlist is empty. | |
| 2990 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll(). | |
| 2991 // | |
| 2992 // * use jccb and jmpb instead of jcc and jmp to improve code density. | |
| 2993 // But beware of excessive branch density on AMD Opterons. | |
| 2994 // | |
| 2995 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success | |
| 2996 // or failure of the fast-path. If the fast-path fails then we pass | |
| 2997 // control to the slow-path, typically in C. In Fast_Lock and | |
| 2998 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2 | |
| 2999 // will emit a conditional branch immediately after the node. | |
| 3000 // So we have branches to branches and lots of ICC.ZF games. | |
| 3001 // Instead, it might be better to have C2 pass a "FailureLabel" | |
| 3002 // into Fast_Lock and Fast_Unlock. In the case of success, control | |
| 3003 // will drop through the node. ICC.ZF is undefined at exit. | |
| 3004 // In the case of failure, the node will branch directly to the | |
| 3005 // FailureLabel | |
| 3006 | |
| 3007 | |
| 3008 // obj: object to lock | |
| 3009 // box: on-stack box address (displaced header location) - KILLED | |
| 3010 // rax,: tmp -- KILLED | |
| 3011 // scr: tmp -- KILLED | |
| 3012 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{ | |
| 3013 | |
| 3014 Register objReg = as_Register($obj$$reg); | |
| 3015 Register boxReg = as_Register($box$$reg); | |
| 3016 Register tmpReg = as_Register($tmp$$reg); | |
| 3017 Register scrReg = as_Register($scr$$reg); | |
| 3018 | |
| 3019 // Ensure the register assignents are disjoint | |
| 3020 guarantee (objReg != boxReg, "") ; | |
| 3021 guarantee (objReg != tmpReg, "") ; | |
| 3022 guarantee (objReg != scrReg, "") ; | |
| 3023 guarantee (boxReg != tmpReg, "") ; | |
| 3024 guarantee (boxReg != scrReg, "") ; | |
| 3025 guarantee (tmpReg == as_Register(EAX_enc), "") ; | |
| 3026 | |
| 3027 MacroAssembler masm(&cbuf); | |
| 3028 | |
| 3029 if (_counters != NULL) { | |
| 3030 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr())); | |
| 3031 } | |
| 3032 if (EmitSync & 1) { | |
| 3033 // set box->dhw = unused_mark (3) | |
| 304 | 3034 // Force all sync thru slow-path: slow_enter() and slow_exit() |
| 3035 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ; | |
| 3036 masm.cmpptr (rsp, (int32_t)0) ; | |
| 3037 } else | |
| 3038 if (EmitSync & 2) { | |
| 3039 Label DONE_LABEL ; | |
| 0 | 3040 if (UseBiasedLocking) { |
| 3041 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument. | |
| 3042 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters); | |
| 3043 } | |
| 3044 | |
| 304 | 3045 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword |
| 3046 masm.orptr (tmpReg, 0x1); | |
| 3047 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS | |
| 0 | 3048 if (os::is_MP()) { masm.lock(); } |
| 304 | 3049 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg |
| 0 | 3050 masm.jcc(Assembler::equal, DONE_LABEL); |
| 3051 // Recursive locking | |
| 304 | 3052 masm.subptr(tmpReg, rsp); |
| 3053 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 ); | |
| 3054 masm.movptr(Address(boxReg, 0), tmpReg); | |
| 3055 masm.bind(DONE_LABEL) ; | |
| 3056 } else { | |
| 3057 // Possible cases that we'll encounter in fast_lock | |
| 0 | 3058 // ------------------------------------------------ |
| 3059 // * Inflated | |
| 3060 // -- unlocked | |
| 3061 // -- Locked | |
| 3062 // = by self | |
| 3063 // = by other | |
| 3064 // * biased | |
| 3065 // -- by Self | |
| 3066 // -- by other | |
| 3067 // * neutral | |
| 3068 // * stack-locked | |
| 3069 // -- by self | |
| 3070 // = sp-proximity test hits | |
| 3071 // = sp-proximity test generates false-negative | |
| 3072 // -- by other | |
| 3073 // | |
| 3074 | |
| 3075 Label IsInflated, DONE_LABEL, PopDone ; | |
| 3076 | |
| 3077 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage | |
| 3078 // order to reduce the number of conditional branches in the most common cases. | |
| 3079 // Beware -- there's a subtle invariant that fetch of the markword | |
| 3080 // at [FETCH], below, will never observe a biased encoding (*101b). | |
| 3081 // If this invariant is not held we risk exclusion (safety) failure. | |
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|
3082 if (UseBiasedLocking && !UseOptoBiasInlining) { |
| 0 | 3083 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters); |
| 3084 } | |
| 3085 | |
| 304 | 3086 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH] |
| 3087 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral) | |
| 0 | 3088 masm.jccb (Assembler::notZero, IsInflated) ; |
| 3089 | |
| 3090 // Attempt stack-locking ... | |
| 304 | 3091 masm.orptr (tmpReg, 0x1); |
| 3092 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS | |
| 0 | 3093 if (os::is_MP()) { masm.lock(); } |
| 304 | 3094 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg |
| 0 | 3095 if (_counters != NULL) { |
| 3096 masm.cond_inc32(Assembler::equal, | |
| 3097 ExternalAddress((address)_counters->fast_path_entry_count_addr())); | |
| 3098 } | |
| 3099 masm.jccb (Assembler::equal, DONE_LABEL); | |
| 3100 | |
| 3101 // Recursive locking | |
| 304 | 3102 masm.subptr(tmpReg, rsp); |
| 3103 masm.andptr(tmpReg, 0xFFFFF003 ); | |
| 3104 masm.movptr(Address(boxReg, 0), tmpReg); | |
| 0 | 3105 if (_counters != NULL) { |
| 3106 masm.cond_inc32(Assembler::equal, | |
| 3107 ExternalAddress((address)_counters->fast_path_entry_count_addr())); | |
| 3108 } | |
| 3109 masm.jmp (DONE_LABEL) ; | |
| 3110 | |
| 3111 masm.bind (IsInflated) ; | |
| 3112 | |
| 3113 // The object is inflated. | |
| 3114 // | |
| 3115 // TODO-FIXME: eliminate the ugly use of manifest constants: | |
| 3116 // Use markOopDesc::monitor_value instead of "2". | |
| 3117 // use markOop::unused_mark() instead of "3". | |
| 3118 // The tmpReg value is an objectMonitor reference ORed with | |
| 3119 // markOopDesc::monitor_value (2). We can either convert tmpReg to an | |
| 3120 // objectmonitor pointer by masking off the "2" bit or we can just | |
| 3121 // use tmpReg as an objectmonitor pointer but bias the objectmonitor | |
| 3122 // field offsets with "-2" to compensate for and annul the low-order tag bit. | |
| 3123 // | |
| 3124 // I use the latter as it avoids AGI stalls. | |
| 3125 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]" | |
| 3126 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]". | |
| 3127 // | |
| 3128 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2) | |
| 3129 | |
| 3130 // boxReg refers to the on-stack BasicLock in the current frame. | |
| 3131 // We'd like to write: | |
| 3132 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices. | |
| 3133 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers | |
| 3134 // additional latency as we have another ST in the store buffer that must drain. | |
| 3135 | |
| 304 | 3136 if (EmitSync & 8192) { |
| 3137 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty | |
| 3138 masm.get_thread (scrReg) ; | |
| 3139 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2] | |
|
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3140 masm.movptr(tmpReg, NULL_WORD); // consider: xor vs mov |
| 304 | 3141 if (os::is_MP()) { masm.lock(); } |
| 3142 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; | |
| 3143 } else | |
| 0 | 3144 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS |
| 304 | 3145 masm.movptr(scrReg, boxReg) ; |
| 3146 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2] | |
| 0 | 3147 |
| 3148 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes | |
| 2479 | 3149 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { |
| 0 | 3150 // prefetchw [eax + Offset(_owner)-2] |
| 304 | 3151 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2)); |
| 0 | 3152 } |
| 3153 | |
| 3154 if ((EmitSync & 64) == 0) { | |
| 3155 // Optimistic form: consider XORL tmpReg,tmpReg | |
|
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|
3156 masm.movptr(tmpReg, NULL_WORD) ; |
| 304 | 3157 } else { |
| 0 | 3158 // Can suffer RTS->RTO upgrades on shared or cold $ lines |
| 3159 // Test-And-CAS instead of CAS | |
| 304 | 3160 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner |
| 3161 masm.testptr(tmpReg, tmpReg) ; // Locked ? | |
| 3162 masm.jccb (Assembler::notZero, DONE_LABEL) ; | |
| 0 | 3163 } |
| 3164 | |
| 3165 // Appears unlocked - try to swing _owner from null to non-null. | |
| 3166 // Ideally, I'd manifest "Self" with get_thread and then attempt | |
| 3167 // to CAS the register containing Self into m->Owner. | |
| 3168 // But we don't have enough registers, so instead we can either try to CAS | |
| 3169 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds | |
| 3170 // we later store "Self" into m->Owner. Transiently storing a stack address | |
| 3171 // (rsp or the address of the box) into m->owner is harmless. | |
| 3172 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. | |
| 3173 if (os::is_MP()) { masm.lock(); } | |
| 304 | 3174 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
| 3175 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3 | |
| 3176 masm.jccb (Assembler::notZero, DONE_LABEL) ; | |
| 0 | 3177 masm.get_thread (scrReg) ; // beware: clobbers ICCs |
| 304 | 3178 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ; |
| 3179 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success | |
| 3180 | |
| 3181 // If the CAS fails we can either retry or pass control to the slow-path. | |
| 3182 // We use the latter tactic. | |
| 0 | 3183 // Pass the CAS result in the icc.ZFlag into DONE_LABEL |
| 3184 // If the CAS was successful ... | |
| 3185 // Self has acquired the lock | |
| 3186 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. | |
| 3187 // Intentional fall-through into DONE_LABEL ... | |
| 3188 } else { | |
| 304 | 3189 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty |
| 3190 masm.movptr(boxReg, tmpReg) ; | |
| 0 | 3191 |
| 3192 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes | |
| 2479 | 3193 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { |
| 0 | 3194 // prefetchw [eax + Offset(_owner)-2] |
| 304 | 3195 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2)); |
| 0 | 3196 } |
| 3197 | |
| 3198 if ((EmitSync & 64) == 0) { | |
| 3199 // Optimistic form | |
| 304 | 3200 masm.xorptr (tmpReg, tmpReg) ; |
| 3201 } else { | |
| 0 | 3202 // Can suffer RTS->RTO upgrades on shared or cold $ lines |
| 304 | 3203 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner |
| 3204 masm.testptr(tmpReg, tmpReg) ; // Locked ? | |
| 3205 masm.jccb (Assembler::notZero, DONE_LABEL) ; | |
| 0 | 3206 } |
| 3207 | |
| 3208 // Appears unlocked - try to swing _owner from null to non-null. | |
| 3209 // Use either "Self" (in scr) or rsp as thread identity in _owner. | |
| 3210 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. | |
| 3211 masm.get_thread (scrReg) ; | |
| 3212 if (os::is_MP()) { masm.lock(); } | |
| 304 | 3213 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
| 0 | 3214 |
| 3215 // If the CAS fails we can either retry or pass control to the slow-path. | |
| 3216 // We use the latter tactic. | |
| 3217 // Pass the CAS result in the icc.ZFlag into DONE_LABEL | |
| 3218 // If the CAS was successful ... | |
| 3219 // Self has acquired the lock | |
| 3220 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. | |
| 3221 // Intentional fall-through into DONE_LABEL ... | |
| 3222 } | |
| 3223 | |
| 3224 // DONE_LABEL is a hot target - we'd really like to place it at the | |
| 3225 // start of cache line by padding with NOPs. | |
| 3226 // See the AMD and Intel software optimization manuals for the | |
| 3227 // most efficient "long" NOP encodings. | |
| 3228 // Unfortunately none of our alignment mechanisms suffice. | |
| 3229 masm.bind(DONE_LABEL); | |
| 3230 | |
| 3231 // Avoid branch-to-branch on AMD processors | |
| 3232 // This appears to be superstition. | |
| 3233 if (EmitSync & 32) masm.nop() ; | |
| 3234 | |
| 3235 | |
| 3236 // At DONE_LABEL the icc ZFlag is set as follows ... | |
| 3237 // Fast_Unlock uses the same protocol. | |
| 3238 // ZFlag == 1 -> Success | |
| 3239 // ZFlag == 0 -> Failure - force control through the slow-path | |
| 3240 } | |
| 3241 %} | |
| 3242 | |
| 3243 // obj: object to unlock | |
| 3244 // box: box address (displaced header location), killed. Must be EAX. | |
| 3245 // rbx,: killed tmp; cannot be obj nor box. | |
| 3246 // | |
| 3247 // Some commentary on balanced locking: | |
| 3248 // | |
| 3249 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites. | |
| 3250 // Methods that don't have provably balanced locking are forced to run in the | |
| 3251 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock. | |
| 3252 // The interpreter provides two properties: | |
| 3253 // I1: At return-time the interpreter automatically and quietly unlocks any | |
| 3254 // objects acquired the current activation (frame). Recall that the | |
| 3255 // interpreter maintains an on-stack list of locks currently held by | |
| 3256 // a frame. | |
| 3257 // I2: If a method attempts to unlock an object that is not held by the | |
| 3258 // the frame the interpreter throws IMSX. | |
| 3259 // | |
| 3260 // Lets say A(), which has provably balanced locking, acquires O and then calls B(). | |
| 3261 // B() doesn't have provably balanced locking so it runs in the interpreter. | |
| 3262 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O | |
| 3263 // is still locked by A(). | |
| 3264 // | |
| 3265 // The only other source of unbalanced locking would be JNI. The "Java Native Interface: | |
| 3266 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter | |
| 3267 // should not be unlocked by "normal" java-level locking and vice-versa. The specification | |
| 3268 // doesn't specify what will occur if a program engages in such mixed-mode locking, however. | |
| 3269 | |
| 3270 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{ | |
| 3271 | |
| 3272 Register objReg = as_Register($obj$$reg); | |
| 3273 Register boxReg = as_Register($box$$reg); | |
| 3274 Register tmpReg = as_Register($tmp$$reg); | |
| 3275 | |
| 3276 guarantee (objReg != boxReg, "") ; | |
| 3277 guarantee (objReg != tmpReg, "") ; | |
| 3278 guarantee (boxReg != tmpReg, "") ; | |
| 3279 guarantee (boxReg == as_Register(EAX_enc), "") ; | |
| 3280 MacroAssembler masm(&cbuf); | |
| 3281 | |
| 3282 if (EmitSync & 4) { | |
| 3283 // Disable - inhibit all inlining. Force control through the slow-path | |
| 304 | 3284 masm.cmpptr (rsp, 0) ; |
| 3285 } else | |
| 0 | 3286 if (EmitSync & 8) { |
| 3287 Label DONE_LABEL ; | |
| 3288 if (UseBiasedLocking) { | |
| 3289 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); | |
| 3290 } | |
| 3291 // classic stack-locking code ... | |
| 304 | 3292 masm.movptr(tmpReg, Address(boxReg, 0)) ; |
| 3293 masm.testptr(tmpReg, tmpReg) ; | |
| 0 | 3294 masm.jcc (Assembler::zero, DONE_LABEL) ; |
| 3295 if (os::is_MP()) { masm.lock(); } | |
| 304 | 3296 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box |
| 0 | 3297 masm.bind(DONE_LABEL); |
| 3298 } else { | |
| 3299 Label DONE_LABEL, Stacked, CheckSucc, Inflated ; | |
| 3300 | |
| 3301 // Critically, the biased locking test must have precedence over | |
| 3302 // and appear before the (box->dhw == 0) recursive stack-lock test. | |
|
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3303 if (UseBiasedLocking && !UseOptoBiasInlining) { |
| 0 | 3304 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); |
| 3305 } | |
| 304 | 3306 |
| 3307 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header | |
| 3308 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword | |
| 0 | 3309 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock |
| 3310 | |
| 304 | 3311 masm.testptr(tmpReg, 0x02) ; // Inflated? |
| 0 | 3312 masm.jccb (Assembler::zero, Stacked) ; |
| 3313 | |
| 3314 masm.bind (Inflated) ; | |
| 3315 // It's inflated. | |
| 3316 // Despite our balanced locking property we still check that m->_owner == Self | |
| 3317 // as java routines or native JNI code called by this thread might | |
| 3318 // have released the lock. | |
| 3319 // Refer to the comments in synchronizer.cpp for how we might encode extra | |
| 3320 // state in _succ so we can avoid fetching EntryList|cxq. | |
| 3321 // | |
| 3322 // I'd like to add more cases in fast_lock() and fast_unlock() -- | |
| 3323 // such as recursive enter and exit -- but we have to be wary of | |
| 3324 // I$ bloat, T$ effects and BP$ effects. | |
| 3325 // | |
| 3326 // If there's no contention try a 1-0 exit. That is, exit without | |
| 3327 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how | |
| 3328 // we detect and recover from the race that the 1-0 exit admits. | |
| 3329 // | |
| 3330 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier | |
| 3331 // before it STs null into _owner, releasing the lock. Updates | |
| 3332 // to data protected by the critical section must be visible before | |
| 3333 // we drop the lock (and thus before any other thread could acquire | |
| 3334 // the lock and observe the fields protected by the lock). | |
| 3335 // IA32's memory-model is SPO, so STs are ordered with respect to | |
| 3336 // each other and there's no need for an explicit barrier (fence). | |
| 3337 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html. | |
| 3338 | |
| 3339 masm.get_thread (boxReg) ; | |
| 2479 | 3340 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { |
| 304 | 3341 // prefetchw [ebx + Offset(_owner)-2] |
| 3342 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2)); | |
| 0 | 3343 } |
| 3344 | |
| 3345 // Note that we could employ various encoding schemes to reduce | |
| 3346 // the number of loads below (currently 4) to just 2 or 3. | |
| 3347 // Refer to the comments in synchronizer.cpp. | |
| 3348 // In practice the chain of fetches doesn't seem to impact performance, however. | |
| 3349 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) { | |
| 3350 // Attempt to reduce branch density - AMD's branch predictor. | |
| 304 | 3351 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
| 3352 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ; | |
| 3353 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ; | |
| 3354 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ; | |
| 3355 masm.jccb (Assembler::notZero, DONE_LABEL) ; | |
|
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3356 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ; |
| 304 | 3357 masm.jmpb (DONE_LABEL) ; |
| 3358 } else { | |
| 3359 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; | |
| 3360 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ; | |
| 3361 masm.jccb (Assembler::notZero, DONE_LABEL) ; | |
| 3362 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ; | |
| 3363 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ; | |
| 3364 masm.jccb (Assembler::notZero, CheckSucc) ; | |
|
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|
3365 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ; |
| 304 | 3366 masm.jmpb (DONE_LABEL) ; |
| 0 | 3367 } |
| 3368 | |
| 3369 // The Following code fragment (EmitSync & 65536) improves the performance of | |
| 3370 // contended applications and contended synchronization microbenchmarks. | |
| 3371 // Unfortunately the emission of the code - even though not executed - causes regressions | |
| 3372 // in scimark and jetstream, evidently because of $ effects. Replacing the code | |
| 3373 // with an equal number of never-executed NOPs results in the same regression. | |
| 3374 // We leave it off by default. | |
| 3375 | |
| 3376 if ((EmitSync & 65536) != 0) { | |
| 3377 Label LSuccess, LGoSlowPath ; | |
| 3378 | |
| 3379 masm.bind (CheckSucc) ; | |
| 3380 | |
| 3381 // Optional pre-test ... it's safe to elide this | |
| 304 | 3382 if ((EmitSync & 16) == 0) { |
| 3383 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ; | |
| 3384 masm.jccb (Assembler::zero, LGoSlowPath) ; | |
| 0 | 3385 } |
| 3386 | |
| 3387 // We have a classic Dekker-style idiom: | |
| 3388 // ST m->_owner = 0 ; MEMBAR; LD m->_succ | |
| 3389 // There are a number of ways to implement the barrier: | |
| 3390 // (1) lock:andl &m->_owner, 0 | |
| 3391 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form. | |
| 3392 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0 | |
| 3393 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8 | |
| 3394 // (2) If supported, an explicit MFENCE is appealing. | |
| 3395 // In older IA32 processors MFENCE is slower than lock:add or xchg | |
| 3396 // particularly if the write-buffer is full as might be the case if | |
| 3397 // if stores closely precede the fence or fence-equivalent instruction. | |
| 3398 // In more modern implementations MFENCE appears faster, however. | |
| 3399 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack | |
| 3400 // The $lines underlying the top-of-stack should be in M-state. | |
| 3401 // The locked add instruction is serializing, of course. | |
| 3402 // (4) Use xchg, which is serializing | |
| 3403 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works | |
| 3404 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0. | |
| 3405 // The integer condition codes will tell us if succ was 0. | |
| 3406 // Since _succ and _owner should reside in the same $line and | |
| 3407 // we just stored into _owner, it's likely that the $line | |
| 3408 // remains in M-state for the lock:orl. | |
| 3409 // | |
| 3410 // We currently use (3), although it's likely that switching to (2) | |
| 3411 // is correct for the future. | |
| 304 | 3412 |
|
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3413 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ; |
| 304 | 3414 if (os::is_MP()) { |
| 3415 if (VM_Version::supports_sse2() && 1 == FenceInstruction) { | |
| 3416 masm.mfence(); | |
| 3417 } else { | |
| 3418 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ; | |
| 0 | 3419 } |
| 3420 } | |
| 3421 // Ratify _succ remains non-null | |
| 304 | 3422 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ; |
| 3423 masm.jccb (Assembler::notZero, LSuccess) ; | |
| 3424 | |
| 3425 masm.xorptr(boxReg, boxReg) ; // box is really EAX | |
| 0 | 3426 if (os::is_MP()) { masm.lock(); } |
| 304 | 3427 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)); |
| 0 | 3428 masm.jccb (Assembler::notEqual, LSuccess) ; |
| 3429 // Since we're low on registers we installed rsp as a placeholding in _owner. | |
| 3430 // Now install Self over rsp. This is safe as we're transitioning from | |
| 3431 // non-null to non=null | |
| 3432 masm.get_thread (boxReg) ; | |
| 304 | 3433 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ; |
| 0 | 3434 // Intentional fall-through into LGoSlowPath ... |
| 3435 | |
| 304 | 3436 masm.bind (LGoSlowPath) ; |
| 3437 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure | |
| 3438 masm.jmpb (DONE_LABEL) ; | |
| 3439 | |
| 3440 masm.bind (LSuccess) ; | |
| 3441 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success | |
| 3442 masm.jmpb (DONE_LABEL) ; | |
| 0 | 3443 } |
| 3444 | |
| 3445 masm.bind (Stacked) ; | |
| 3446 // It's not inflated and it's not recursively stack-locked and it's not biased. | |
| 3447 // It must be stack-locked. | |
| 3448 // Try to reset the header to displaced header. | |
| 3449 // The "box" value on the stack is stable, so we can reload | |
| 3450 // and be assured we observe the same value as above. | |
| 304 | 3451 masm.movptr(tmpReg, Address(boxReg, 0)) ; |
| 0 | 3452 if (os::is_MP()) { masm.lock(); } |
| 304 | 3453 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box |
| 0 | 3454 // Intention fall-thru into DONE_LABEL |
| 3455 | |
| 3456 | |
| 3457 // DONE_LABEL is a hot target - we'd really like to place it at the | |
| 3458 // start of cache line by padding with NOPs. | |
| 3459 // See the AMD and Intel software optimization manuals for the | |
| 3460 // most efficient "long" NOP encodings. | |
| 3461 // Unfortunately none of our alignment mechanisms suffice. | |
| 3462 if ((EmitSync & 65536) == 0) { | |
| 3463 masm.bind (CheckSucc) ; | |
| 3464 } | |
| 3465 masm.bind(DONE_LABEL); | |
| 3466 | |
| 3467 // Avoid branch to branch on AMD processors | |
| 3468 if (EmitSync & 32768) { masm.nop() ; } | |
| 3469 } | |
| 3470 %} | |
| 3471 | |
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3472 |
| 0 | 3473 enc_class enc_pop_rdx() %{ |
| 3474 emit_opcode(cbuf,0x5A); | |
| 3475 %} | |
| 3476 | |
| 3477 enc_class enc_rethrow() %{ | |
| 1748 | 3478 cbuf.set_insts_mark(); |
| 0 | 3479 emit_opcode(cbuf, 0xE9); // jmp entry |
| 1748 | 3480 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.insts_end())-4, |
| 0 | 3481 runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 3482 %} | |
| 3483 | |
| 3484 | |
| 3485 // Convert a double to an int. Java semantics require we do complex | |
| 3486 // manglelations in the corner cases. So we set the rounding mode to | |
| 3487 // 'zero', store the darned double down as an int, and reset the | |
| 3488 // rounding mode to 'nearest'. The hardware throws an exception which | |
| 3489 // patches up the correct value directly to the stack. | |
|
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3490 enc_class DPR2I_encoding( regDPR src ) %{ |
| 0 | 3491 // Flip to round-to-zero mode. We attempted to allow invalid-op |
| 3492 // exceptions here, so that a NAN or other corner-case value will | |
| 3493 // thrown an exception (but normal values get converted at full speed). | |
| 3494 // However, I2C adapters and other float-stack manglers leave pending | |
| 3495 // invalid-op exceptions hanging. We would have to clear them before | |
| 3496 // enabling them and that is more expensive than just testing for the | |
| 3497 // invalid value Intel stores down in the corner cases. | |
| 3498 emit_opcode(cbuf,0xD9); // FLDCW trunc | |
| 3499 emit_opcode(cbuf,0x2D); | |
| 3500 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); | |
| 3501 // Allocate a word | |
| 3502 emit_opcode(cbuf,0x83); // SUB ESP,4 | |
| 3503 emit_opcode(cbuf,0xEC); | |
| 3504 emit_d8(cbuf,0x04); | |
| 3505 // Encoding assumes a double has been pushed into FPR0. | |
| 3506 // Store down the double as an int, popping the FPU stack | |
| 3507 emit_opcode(cbuf,0xDB); // FISTP [ESP] | |
| 3508 emit_opcode(cbuf,0x1C); | |
| 3509 emit_d8(cbuf,0x24); | |
| 3510 // Restore the rounding mode; mask the exception | |
| 3511 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode | |
| 3512 emit_opcode(cbuf,0x2D); | |
| 3513 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() | |
| 3514 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() | |
| 3515 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); | |
| 3516 | |
| 3517 // Load the converted int; adjust CPU stack | |
| 3518 emit_opcode(cbuf,0x58); // POP EAX | |
| 3519 emit_opcode(cbuf,0x3D); // CMP EAX,imm | |
| 3520 emit_d32 (cbuf,0x80000000); // 0x80000000 | |
| 3521 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 3522 emit_d8 (cbuf,0x07); // Size of slow_call | |
| 3523 // Push src onto stack slow-path | |
| 3524 emit_opcode(cbuf,0xD9 ); // FLD ST(i) | |
| 3525 emit_d8 (cbuf,0xC0-1+$src$$reg ); | |
| 3526 // CALL directly to the runtime | |
| 1748 | 3527 cbuf.set_insts_mark(); |
| 0 | 3528 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 3529 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 3530 // Carry on here... |
| 3531 %} | |
| 3532 | |
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3533 enc_class DPR2L_encoding( regDPR src ) %{ |
| 0 | 3534 emit_opcode(cbuf,0xD9); // FLDCW trunc |
| 3535 emit_opcode(cbuf,0x2D); | |
| 3536 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); | |
| 3537 // Allocate a word | |
| 3538 emit_opcode(cbuf,0x83); // SUB ESP,8 | |
| 3539 emit_opcode(cbuf,0xEC); | |
| 3540 emit_d8(cbuf,0x08); | |
| 3541 // Encoding assumes a double has been pushed into FPR0. | |
| 3542 // Store down the double as a long, popping the FPU stack | |
| 3543 emit_opcode(cbuf,0xDF); // FISTP [ESP] | |
| 3544 emit_opcode(cbuf,0x3C); | |
| 3545 emit_d8(cbuf,0x24); | |
| 3546 // Restore the rounding mode; mask the exception | |
| 3547 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode | |
| 3548 emit_opcode(cbuf,0x2D); | |
| 3549 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() | |
| 3550 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() | |
| 3551 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); | |
| 3552 | |
| 3553 // Load the converted int; adjust CPU stack | |
| 3554 emit_opcode(cbuf,0x58); // POP EAX | |
| 3555 emit_opcode(cbuf,0x5A); // POP EDX | |
| 3556 emit_opcode(cbuf,0x81); // CMP EDX,imm | |
| 3557 emit_d8 (cbuf,0xFA); // rdx | |
| 3558 emit_d32 (cbuf,0x80000000); // 0x80000000 | |
| 3559 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 3560 emit_d8 (cbuf,0x07+4); // Size of slow_call | |
| 3561 emit_opcode(cbuf,0x85); // TEST EAX,EAX | |
| 3562 emit_opcode(cbuf,0xC0); // 2/rax,/rax, | |
| 3563 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 3564 emit_d8 (cbuf,0x07); // Size of slow_call | |
| 3565 // Push src onto stack slow-path | |
| 3566 emit_opcode(cbuf,0xD9 ); // FLD ST(i) | |
| 3567 emit_d8 (cbuf,0xC0-1+$src$$reg ); | |
| 3568 // CALL directly to the runtime | |
| 1748 | 3569 cbuf.set_insts_mark(); |
| 0 | 3570 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 3571 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 3572 // Carry on here... |
| 3573 %} | |
| 3574 | |
|
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3575 enc_class FMul_ST_reg( eRegFPR src1 ) %{ |
| 0 | 3576 // Operand was loaded from memory into fp ST (stack top) |
| 3577 // FMUL ST,$src /* D8 C8+i */ | |
| 3578 emit_opcode(cbuf, 0xD8); | |
| 3579 emit_opcode(cbuf, 0xC8 + $src1$$reg); | |
| 3580 %} | |
| 3581 | |
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3582 enc_class FAdd_ST_reg( eRegFPR src2 ) %{ |
| 0 | 3583 // FADDP ST,src2 /* D8 C0+i */ |
| 3584 emit_opcode(cbuf, 0xD8); | |
| 3585 emit_opcode(cbuf, 0xC0 + $src2$$reg); | |
| 3586 //could use FADDP src2,fpST /* DE C0+i */ | |
| 3587 %} | |
| 3588 | |
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3589 enc_class FAddP_reg_ST( eRegFPR src2 ) %{ |
| 0 | 3590 // FADDP src2,ST /* DE C0+i */ |
| 3591 emit_opcode(cbuf, 0xDE); | |
| 3592 emit_opcode(cbuf, 0xC0 + $src2$$reg); | |
| 3593 %} | |
| 3594 | |
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3595 enc_class subFPR_divFPR_encode( eRegFPR src1, eRegFPR src2) %{ |
| 0 | 3596 // Operand has been loaded into fp ST (stack top) |
| 3597 // FSUB ST,$src1 | |
| 3598 emit_opcode(cbuf, 0xD8); | |
| 3599 emit_opcode(cbuf, 0xE0 + $src1$$reg); | |
| 3600 | |
| 3601 // FDIV | |
| 3602 emit_opcode(cbuf, 0xD8); | |
| 3603 emit_opcode(cbuf, 0xF0 + $src2$$reg); | |
| 3604 %} | |
| 3605 | |
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3606 enc_class MulFAddF (eRegFPR src1, eRegFPR src2) %{ |
| 0 | 3607 // Operand was loaded from memory into fp ST (stack top) |
| 3608 // FADD ST,$src /* D8 C0+i */ | |
| 3609 emit_opcode(cbuf, 0xD8); | |
| 3610 emit_opcode(cbuf, 0xC0 + $src1$$reg); | |
| 3611 | |
| 3612 // FMUL ST,src2 /* D8 C*+i */ | |
| 3613 emit_opcode(cbuf, 0xD8); | |
| 3614 emit_opcode(cbuf, 0xC8 + $src2$$reg); | |
| 3615 %} | |
| 3616 | |
| 3617 | |
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3618 enc_class MulFAddFreverse (eRegFPR src1, eRegFPR src2) %{ |
| 0 | 3619 // Operand was loaded from memory into fp ST (stack top) |
| 3620 // FADD ST,$src /* D8 C0+i */ | |
| 3621 emit_opcode(cbuf, 0xD8); | |
| 3622 emit_opcode(cbuf, 0xC0 + $src1$$reg); | |
| 3623 | |
| 3624 // FMULP src2,ST /* DE C8+i */ | |
| 3625 emit_opcode(cbuf, 0xDE); | |
| 3626 emit_opcode(cbuf, 0xC8 + $src2$$reg); | |
| 3627 %} | |
| 3628 | |
| 3629 // Atomically load the volatile long | |
| 3630 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{ | |
| 3631 emit_opcode(cbuf,0xDF); | |
| 3632 int rm_byte_opcode = 0x05; | |
| 3633 int base = $mem$$base; | |
| 3634 int index = $mem$$index; | |
| 3635 int scale = $mem$$scale; | |
| 3636 int displace = $mem$$disp; | |
|
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3637 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals |
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3638 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc); |
| 0 | 3639 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp ); |
| 3640 %} | |
| 3641 | |
| 3642 // Volatile Store Long. Must be atomic, so move it into | |
| 3643 // the FP TOS and then do a 64-bit FIST. Has to probe the | |
| 3644 // target address before the store (for null-ptr checks) | |
| 3645 // so the memory operand is used twice in the encoding. | |
| 3646 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{ | |
| 3647 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp ); | |
| 1748 | 3648 cbuf.set_insts_mark(); // Mark start of FIST in case $mem has an oop |
| 0 | 3649 emit_opcode(cbuf,0xDF); |
| 3650 int rm_byte_opcode = 0x07; | |
| 3651 int base = $mem$$base; | |
| 3652 int index = $mem$$index; | |
| 3653 int scale = $mem$$scale; | |
| 3654 int displace = $mem$$disp; | |
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3655 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals |
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3656 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc); |
| 0 | 3657 %} |
| 3658 | |
| 3659 // Safepoint Poll. This polls the safepoint page, and causes an | |
| 3660 // exception if it is not readable. Unfortunately, it kills the condition code | |
| 3661 // in the process | |
| 3662 // We current use TESTL [spp],EDI | |
| 3663 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0 | |
| 3664 | |
| 3665 enc_class Safepoint_Poll() %{ | |
| 1748 | 3666 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0); |
| 0 | 3667 emit_opcode(cbuf,0x85); |
| 3668 emit_rm (cbuf, 0x0, 0x7, 0x5); | |
| 3669 emit_d32(cbuf, (intptr_t)os::get_polling_page()); | |
| 3670 %} | |
| 3671 %} | |
| 3672 | |
| 3673 | |
| 3674 //----------FRAME-------------------------------------------------------------- | |
| 3675 // Definition of frame structure and management information. | |
| 3676 // | |
| 3677 // S T A C K L A Y O U T Allocators stack-slot number | |
| 3678 // | (to get allocators register number | |
| 3679 // G Owned by | | v add OptoReg::stack0()) | |
| 3680 // r CALLER | | | |
| 3681 // o | +--------+ pad to even-align allocators stack-slot | |
| 3682 // w V | pad0 | numbers; owned by CALLER | |
| 3683 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned | |
| 3684 // h ^ | in | 5 | |
| 3685 // | | args | 4 Holes in incoming args owned by SELF | |
| 3686 // | | | | 3 | |
| 3687 // | | +--------+ | |
| 3688 // V | | old out| Empty on Intel, window on Sparc | |
| 3689 // | old |preserve| Must be even aligned. | |
| 3690 // | SP-+--------+----> Matcher::_old_SP, even aligned | |
| 3691 // | | in | 3 area for Intel ret address | |
| 3692 // Owned by |preserve| Empty on Sparc. | |
| 3693 // SELF +--------+ | |
| 3694 // | | pad2 | 2 pad to align old SP | |
| 3695 // | +--------+ 1 | |
| 3696 // | | locks | 0 | |
| 3697 // | +--------+----> OptoReg::stack0(), even aligned | |
| 3698 // | | pad1 | 11 pad to align new SP | |
| 3699 // | +--------+ | |
| 3700 // | | | 10 | |
| 3701 // | | spills | 9 spills | |
| 3702 // V | | 8 (pad0 slot for callee) | |
| 3703 // -----------+--------+----> Matcher::_out_arg_limit, unaligned | |
| 3704 // ^ | out | 7 | |
| 3705 // | | args | 6 Holes in outgoing args owned by CALLEE | |
| 3706 // Owned by +--------+ | |
| 3707 // CALLEE | new out| 6 Empty on Intel, window on Sparc | |
| 3708 // | new |preserve| Must be even-aligned. | |
| 3709 // | SP-+--------+----> Matcher::_new_SP, even aligned | |
| 3710 // | | | | |
| 3711 // | |
| 3712 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is | |
| 3713 // known from SELF's arguments and the Java calling convention. | |
| 3714 // Region 6-7 is determined per call site. | |
| 3715 // Note 2: If the calling convention leaves holes in the incoming argument | |
| 3716 // area, those holes are owned by SELF. Holes in the outgoing area | |
| 3717 // are owned by the CALLEE. Holes should not be nessecary in the | |
| 3718 // incoming area, as the Java calling convention is completely under | |
| 3719 // the control of the AD file. Doubles can be sorted and packed to | |
| 3720 // avoid holes. Holes in the outgoing arguments may be nessecary for | |
| 3721 // varargs C calling conventions. | |
| 3722 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is | |
| 3723 // even aligned with pad0 as needed. | |
| 3724 // Region 6 is even aligned. Region 6-7 is NOT even aligned; | |
| 3725 // region 6-11 is even aligned; it may be padded out more so that | |
| 3726 // the region from SP to FP meets the minimum stack alignment. | |
| 3727 | |
| 3728 frame %{ | |
| 3729 // What direction does stack grow in (assumed to be same for C & Java) | |
| 3730 stack_direction(TOWARDS_LOW); | |
| 3731 | |
| 3732 // These three registers define part of the calling convention | |
| 3733 // between compiled code and the interpreter. | |
| 3734 inline_cache_reg(EAX); // Inline Cache Register | |
| 3735 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter | |
| 3736 | |
| 3737 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] | |
| 3738 cisc_spilling_operand_name(indOffset32); | |
| 3739 | |
| 3740 // Number of stack slots consumed by locking an object | |
| 3741 sync_stack_slots(1); | |
| 3742 | |
| 3743 // Compiled code's Frame Pointer | |
| 3744 frame_pointer(ESP); | |
| 3745 // Interpreter stores its frame pointer in a register which is | |
| 3746 // stored to the stack by I2CAdaptors. | |
| 3747 // I2CAdaptors convert from interpreted java to compiled java. | |
| 3748 interpreter_frame_pointer(EBP); | |
| 3749 | |
| 3750 // Stack alignment requirement | |
| 3751 // Alignment size in bytes (128-bit -> 16 bytes) | |
| 3752 stack_alignment(StackAlignmentInBytes); | |
| 3753 | |
| 3754 // Number of stack slots between incoming argument block and the start of | |
| 3755 // a new frame. The PROLOG must add this many slots to the stack. The | |
| 3756 // EPILOG must remove this many slots. Intel needs one slot for | |
| 3757 // return address and one for rbp, (must save rbp) | |
| 3758 in_preserve_stack_slots(2+VerifyStackAtCalls); | |
| 3759 | |
| 3760 // Number of outgoing stack slots killed above the out_preserve_stack_slots | |
| 3761 // for calls to C. Supports the var-args backing area for register parms. | |
| 3762 varargs_C_out_slots_killed(0); | |
| 3763 | |
| 3764 // The after-PROLOG location of the return address. Location of | |
| 3765 // return address specifies a type (REG or STACK) and a number | |
| 3766 // representing the register number (i.e. - use a register name) or | |
| 3767 // stack slot. | |
| 3768 // Ret Addr is on stack in slot 0 if no locks or verification or alignment. | |
| 3769 // Otherwise, it is above the locks and verification slot and alignment word | |
| 3770 return_addr(STACK - 1 + | |
| 4950 | 3771 round_to((Compile::current()->in_preserve_stack_slots() + |
| 3772 Compile::current()->fixed_slots()), | |
| 3773 stack_alignment_in_slots())); | |
| 0 | 3774 |
| 3775 // Body of function which returns an integer array locating | |
| 3776 // arguments either in registers or in stack slots. Passed an array | |
| 3777 // of ideal registers called "sig" and a "length" count. Stack-slot | |
| 3778 // offsets are based on outgoing arguments, i.e. a CALLER setting up | |
| 3779 // arguments for a CALLEE. Incoming stack arguments are | |
| 3780 // automatically biased by the preserve_stack_slots field above. | |
| 3781 calling_convention %{ | |
| 3782 // No difference between ingoing/outgoing just pass false | |
| 3783 SharedRuntime::java_calling_convention(sig_bt, regs, length, false); | |
| 3784 %} | |
| 3785 | |
| 3786 | |
| 3787 // Body of function which returns an integer array locating | |
| 3788 // arguments either in registers or in stack slots. Passed an array | |
| 3789 // of ideal registers called "sig" and a "length" count. Stack-slot | |
| 3790 // offsets are based on outgoing arguments, i.e. a CALLER setting up | |
| 3791 // arguments for a CALLEE. Incoming stack arguments are | |
| 3792 // automatically biased by the preserve_stack_slots field above. | |
| 3793 c_calling_convention %{ | |
| 3794 // This is obviously always outgoing | |
| 3795 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); | |
| 3796 %} | |
| 3797 | |
| 3798 // Location of C & interpreter return values | |
| 3799 c_return_value %{ | |
| 3800 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
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3801 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num }; |
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3802 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num }; |
| 0 | 3803 |
| 3804 // in SSE2+ mode we want to keep the FPU stack clean so pretend | |
| 3805 // that C functions return float and double results in XMM0. | |
| 3806 if( ideal_reg == Op_RegD && UseSSE>=2 ) | |
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3807 return OptoRegPair(XMM0b_num,XMM0_num); |
| 0 | 3808 if( ideal_reg == Op_RegF && UseSSE>=2 ) |
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3809 return OptoRegPair(OptoReg::Bad,XMM0_num); |
| 0 | 3810 |
| 3811 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]); | |
| 3812 %} | |
| 3813 | |
| 3814 // Location of return values | |
| 3815 return_value %{ | |
| 3816 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
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3817 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num }; |
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3818 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num }; |
| 0 | 3819 if( ideal_reg == Op_RegD && UseSSE>=2 ) |
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3820 return OptoRegPair(XMM0b_num,XMM0_num); |
| 0 | 3821 if( ideal_reg == Op_RegF && UseSSE>=1 ) |
|
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3822 return OptoRegPair(OptoReg::Bad,XMM0_num); |
| 0 | 3823 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]); |
| 3824 %} | |
| 3825 | |
| 3826 %} | |
| 3827 | |
| 3828 //----------ATTRIBUTES--------------------------------------------------------- | |
| 3829 //----------Operand Attributes------------------------------------------------- | |
| 3830 op_attrib op_cost(0); // Required cost attribute | |
| 3831 | |
| 3832 //----------Instruction Attributes--------------------------------------------- | |
| 3833 ins_attrib ins_cost(100); // Required cost attribute | |
| 3834 ins_attrib ins_size(8); // Required size attribute (in bits) | |
| 3835 ins_attrib ins_short_branch(0); // Required flag: is this instruction a | |
| 3836 // non-matching short branch variant of some | |
| 3837 // long branch? | |
| 3838 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2) | |
| 3839 // specifies the alignment that some part of the instruction (not | |
| 3840 // necessarily the start) requires. If > 1, a compute_padding() | |
| 3841 // function must be provided for the instruction | |
| 3842 | |
| 3843 //----------OPERANDS----------------------------------------------------------- | |
| 3844 // Operand definitions must precede instruction definitions for correct parsing | |
| 3845 // in the ADLC because operands constitute user defined types which are used in | |
| 3846 // instruction definitions. | |
| 3847 | |
| 3848 //----------Simple Operands---------------------------------------------------- | |
| 3849 // Immediate Operands | |
| 3850 // Integer Immediate | |
| 3851 operand immI() %{ | |
| 3852 match(ConI); | |
| 3853 | |
| 3854 op_cost(10); | |
| 3855 format %{ %} | |
| 3856 interface(CONST_INTER); | |
| 3857 %} | |
| 3858 | |
| 3859 // Constant for test vs zero | |
| 3860 operand immI0() %{ | |
| 3861 predicate(n->get_int() == 0); | |
| 3862 match(ConI); | |
| 3863 | |
| 3864 op_cost(0); | |
| 3865 format %{ %} | |
| 3866 interface(CONST_INTER); | |
| 3867 %} | |
| 3868 | |
| 3869 // Constant for increment | |
| 3870 operand immI1() %{ | |
| 3871 predicate(n->get_int() == 1); | |
| 3872 match(ConI); | |
| 3873 | |
| 3874 op_cost(0); | |
| 3875 format %{ %} | |
| 3876 interface(CONST_INTER); | |
| 3877 %} | |
| 3878 | |
| 3879 // Constant for decrement | |
| 3880 operand immI_M1() %{ | |
| 3881 predicate(n->get_int() == -1); | |
| 3882 match(ConI); | |
| 3883 | |
| 3884 op_cost(0); | |
| 3885 format %{ %} | |
| 3886 interface(CONST_INTER); | |
| 3887 %} | |
| 3888 | |
| 3889 // Valid scale values for addressing modes | |
| 3890 operand immI2() %{ | |
| 3891 predicate(0 <= n->get_int() && (n->get_int() <= 3)); | |
| 3892 match(ConI); | |
| 3893 | |
| 3894 format %{ %} | |
| 3895 interface(CONST_INTER); | |
| 3896 %} | |
| 3897 | |
| 3898 operand immI8() %{ | |
| 3899 predicate((-128 <= n->get_int()) && (n->get_int() <= 127)); | |
| 3900 match(ConI); | |
| 3901 | |
| 3902 op_cost(5); | |
| 3903 format %{ %} | |
| 3904 interface(CONST_INTER); | |
| 3905 %} | |
| 3906 | |
| 3907 operand immI16() %{ | |
| 3908 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767)); | |
| 3909 match(ConI); | |
| 3910 | |
| 3911 op_cost(10); | |
| 3912 format %{ %} | |
| 3913 interface(CONST_INTER); | |
| 3914 %} | |
| 3915 | |
| 3916 // Constant for long shifts | |
| 3917 operand immI_32() %{ | |
| 3918 predicate( n->get_int() == 32 ); | |
| 3919 match(ConI); | |
| 3920 | |
| 3921 op_cost(0); | |
| 3922 format %{ %} | |
| 3923 interface(CONST_INTER); | |
| 3924 %} | |
| 3925 | |
| 3926 operand immI_1_31() %{ | |
| 3927 predicate( n->get_int() >= 1 && n->get_int() <= 31 ); | |
| 3928 match(ConI); | |
| 3929 | |
| 3930 op_cost(0); | |
| 3931 format %{ %} | |
| 3932 interface(CONST_INTER); | |
| 3933 %} | |
| 3934 | |
| 3935 operand immI_32_63() %{ | |
| 3936 predicate( n->get_int() >= 32 && n->get_int() <= 63 ); | |
| 3937 match(ConI); | |
| 3938 op_cost(0); | |
| 3939 | |
| 3940 format %{ %} | |
| 3941 interface(CONST_INTER); | |
| 3942 %} | |
| 3943 | |
| 219 | 3944 operand immI_1() %{ |
| 3945 predicate( n->get_int() == 1 ); | |
| 3946 match(ConI); | |
| 3947 | |
| 3948 op_cost(0); | |
| 3949 format %{ %} | |
| 3950 interface(CONST_INTER); | |
| 3951 %} | |
| 3952 | |
| 3953 operand immI_2() %{ | |
| 3954 predicate( n->get_int() == 2 ); | |
| 3955 match(ConI); | |
| 3956 | |
| 3957 op_cost(0); | |
| 3958 format %{ %} | |
| 3959 interface(CONST_INTER); | |
| 3960 %} | |
| 3961 | |
| 3962 operand immI_3() %{ | |
| 3963 predicate( n->get_int() == 3 ); | |
| 3964 match(ConI); | |
| 3965 | |
| 3966 op_cost(0); | |
| 3967 format %{ %} | |
| 3968 interface(CONST_INTER); | |
| 3969 %} | |
| 3970 | |
| 0 | 3971 // Pointer Immediate |
| 3972 operand immP() %{ | |
| 3973 match(ConP); | |
| 3974 | |
| 3975 op_cost(10); | |
| 3976 format %{ %} | |
| 3977 interface(CONST_INTER); | |
| 3978 %} | |
| 3979 | |
| 3980 // NULL Pointer Immediate | |
| 3981 operand immP0() %{ | |
| 3982 predicate( n->get_ptr() == 0 ); | |
| 3983 match(ConP); | |
| 3984 op_cost(0); | |
| 3985 | |
| 3986 format %{ %} | |
| 3987 interface(CONST_INTER); | |
| 3988 %} | |
| 3989 | |
| 3990 // Long Immediate | |
| 3991 operand immL() %{ | |
| 3992 match(ConL); | |
| 3993 | |
| 3994 op_cost(20); | |
| 3995 format %{ %} | |
| 3996 interface(CONST_INTER); | |
| 3997 %} | |
| 3998 | |
| 3999 // Long Immediate zero | |
| 4000 operand immL0() %{ | |
| 4001 predicate( n->get_long() == 0L ); | |
| 4002 match(ConL); | |
| 4003 op_cost(0); | |
| 4004 | |
| 4005 format %{ %} | |
| 4006 interface(CONST_INTER); | |
| 4007 %} | |
| 4008 | |
| 403 | 4009 // Long Immediate zero |
| 4010 operand immL_M1() %{ | |
| 4011 predicate( n->get_long() == -1L ); | |
| 4012 match(ConL); | |
| 4013 op_cost(0); | |
| 4014 | |
| 4015 format %{ %} | |
| 4016 interface(CONST_INTER); | |
| 4017 %} | |
| 4018 | |
| 0 | 4019 // Long immediate from 0 to 127. |
| 4020 // Used for a shorter form of long mul by 10. | |
| 4021 operand immL_127() %{ | |
| 4022 predicate((0 <= n->get_long()) && (n->get_long() <= 127)); | |
| 4023 match(ConL); | |
| 4024 op_cost(0); | |
| 4025 | |
| 4026 format %{ %} | |
| 4027 interface(CONST_INTER); | |
| 4028 %} | |
| 4029 | |
| 4030 // Long Immediate: low 32-bit mask | |
| 4031 operand immL_32bits() %{ | |
| 4032 predicate(n->get_long() == 0xFFFFFFFFL); | |
| 4033 match(ConL); | |
| 4034 op_cost(0); | |
| 4035 | |
| 4036 format %{ %} | |
| 4037 interface(CONST_INTER); | |
| 4038 %} | |
| 4039 | |
| 4040 // Long Immediate: low 32-bit mask | |
| 4041 operand immL32() %{ | |
| 4042 predicate(n->get_long() == (int)(n->get_long())); | |
| 4043 match(ConL); | |
| 4044 op_cost(20); | |
| 4045 | |
| 4046 format %{ %} | |
| 4047 interface(CONST_INTER); | |
| 4048 %} | |
| 4049 | |
| 4050 //Double Immediate zero | |
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4051 operand immDPR0() %{ |
| 0 | 4052 // Do additional (and counter-intuitive) test against NaN to work around VC++ |
| 4053 // bug that generates code such that NaNs compare equal to 0.0 | |
| 4054 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) ); | |
| 4055 match(ConD); | |
| 4056 | |
| 4057 op_cost(5); | |
| 4058 format %{ %} | |
| 4059 interface(CONST_INTER); | |
| 4060 %} | |
| 4061 | |
| 2008 | 4062 // Double Immediate one |
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4063 operand immDPR1() %{ |
| 0 | 4064 predicate( UseSSE<=1 && n->getd() == 1.0 ); |
| 4065 match(ConD); | |
| 4066 | |
| 4067 op_cost(5); | |
| 4068 format %{ %} | |
| 4069 interface(CONST_INTER); | |
| 4070 %} | |
| 4071 | |
| 4072 // Double Immediate | |
|
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4073 operand immDPR() %{ |
| 0 | 4074 predicate(UseSSE<=1); |
| 4075 match(ConD); | |
| 4076 | |
| 4077 op_cost(5); | |
| 4078 format %{ %} | |
| 4079 interface(CONST_INTER); | |
| 4080 %} | |
| 4081 | |
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4082 operand immD() %{ |
| 0 | 4083 predicate(UseSSE>=2); |
| 4084 match(ConD); | |
| 4085 | |
| 4086 op_cost(5); | |
| 4087 format %{ %} | |
| 4088 interface(CONST_INTER); | |
| 4089 %} | |
| 4090 | |
| 4091 // Double Immediate zero | |
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4092 operand immD0() %{ |
| 0 | 4093 // Do additional (and counter-intuitive) test against NaN to work around VC++ |
| 4094 // bug that generates code such that NaNs compare equal to 0.0 AND do not | |
| 4095 // compare equal to -0.0. | |
| 4096 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 ); | |
| 4097 match(ConD); | |
| 4098 | |
| 4099 format %{ %} | |
| 4100 interface(CONST_INTER); | |
| 4101 %} | |
| 4102 | |
| 4103 // Float Immediate zero | |
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4104 operand immFPR0() %{ |
| 2008 | 4105 predicate(UseSSE == 0 && n->getf() == 0.0F); |
| 4106 match(ConF); | |
| 4107 | |
| 4108 op_cost(5); | |
| 4109 format %{ %} | |
| 4110 interface(CONST_INTER); | |
| 4111 %} | |
| 4112 | |
| 4113 // Float Immediate one | |
|
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4114 operand immFPR1() %{ |
| 2008 | 4115 predicate(UseSSE == 0 && n->getf() == 1.0F); |
| 0 | 4116 match(ConF); |
| 4117 | |
| 4118 op_cost(5); | |
| 4119 format %{ %} | |
| 4120 interface(CONST_INTER); | |
| 4121 %} | |
| 4122 | |
| 4123 // Float Immediate | |
|
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4124 operand immFPR() %{ |
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4125 predicate( UseSSE == 0 ); |
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4126 match(ConF); |
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4127 |
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4128 op_cost(5); |
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4129 format %{ %} |
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4130 interface(CONST_INTER); |
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4131 %} |
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4132 |
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4133 // Float Immediate |
| 0 | 4134 operand immF() %{ |
| 4135 predicate(UseSSE >= 1); | |
| 4136 match(ConF); | |
| 4137 | |
| 4138 op_cost(5); | |
| 4139 format %{ %} | |
| 4140 interface(CONST_INTER); | |
| 4141 %} | |
| 4142 | |
| 4143 // Float Immediate zero. Zero and not -0.0 | |
|
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4144 operand immF0() %{ |
| 0 | 4145 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 ); |
| 4146 match(ConF); | |
| 4147 | |
| 4148 op_cost(5); | |
| 4149 format %{ %} | |
| 4150 interface(CONST_INTER); | |
| 4151 %} | |
| 4152 | |
| 4153 // Immediates for special shifts (sign extend) | |
| 4154 | |
| 4155 // Constants for increment | |
| 4156 operand immI_16() %{ | |
| 4157 predicate( n->get_int() == 16 ); | |
| 4158 match(ConI); | |
| 4159 | |
| 4160 format %{ %} | |
| 4161 interface(CONST_INTER); | |
| 4162 %} | |
| 4163 | |
| 4164 operand immI_24() %{ | |
| 4165 predicate( n->get_int() == 24 ); | |
| 4166 match(ConI); | |
| 4167 | |
| 4168 format %{ %} | |
| 4169 interface(CONST_INTER); | |
| 4170 %} | |
| 4171 | |
| 4172 // Constant for byte-wide masking | |
| 4173 operand immI_255() %{ | |
| 4174 predicate( n->get_int() == 255 ); | |
| 4175 match(ConI); | |
| 4176 | |
| 4177 format %{ %} | |
| 4178 interface(CONST_INTER); | |
| 4179 %} | |
| 4180 | |
| 785 | 4181 // Constant for short-wide masking |
| 4182 operand immI_65535() %{ | |
| 4183 predicate(n->get_int() == 65535); | |
| 4184 match(ConI); | |
| 4185 | |
| 4186 format %{ %} | |
| 4187 interface(CONST_INTER); | |
| 4188 %} | |
| 4189 | |
| 0 | 4190 // Register Operands |
| 4191 // Integer Register | |
|
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4192 operand rRegI() %{ |
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4193 constraint(ALLOC_IN_RC(int_reg)); |
| 0 | 4194 match(RegI); |
| 4195 match(xRegI); | |
| 4196 match(eAXRegI); | |
| 4197 match(eBXRegI); | |
| 4198 match(eCXRegI); | |
| 4199 match(eDXRegI); | |
| 4200 match(eDIRegI); | |
| 4201 match(eSIRegI); | |
| 4202 | |
| 4203 format %{ %} | |
| 4204 interface(REG_INTER); | |
| 4205 %} | |
| 4206 | |
| 4207 // Subset of Integer Register | |
|
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4208 operand xRegI(rRegI reg) %{ |
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4209 constraint(ALLOC_IN_RC(int_x_reg)); |
| 0 | 4210 match(reg); |
| 4211 match(eAXRegI); | |
| 4212 match(eBXRegI); | |
| 4213 match(eCXRegI); | |
| 4214 match(eDXRegI); | |
| 4215 | |
| 4216 format %{ %} | |
| 4217 interface(REG_INTER); | |
| 4218 %} | |
| 4219 | |
| 4220 // Special Registers | |
| 4221 operand eAXRegI(xRegI reg) %{ | |
| 4222 constraint(ALLOC_IN_RC(eax_reg)); | |
| 4223 match(reg); | |
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4224 match(rRegI); |
| 0 | 4225 |
| 4226 format %{ "EAX" %} | |
| 4227 interface(REG_INTER); | |
| 4228 %} | |
| 4229 | |
| 4230 // Special Registers | |
| 4231 operand eBXRegI(xRegI reg) %{ | |
| 4232 constraint(ALLOC_IN_RC(ebx_reg)); | |
| 4233 match(reg); | |
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4234 match(rRegI); |
| 0 | 4235 |
| 4236 format %{ "EBX" %} | |
| 4237 interface(REG_INTER); | |
| 4238 %} | |
| 4239 | |
| 4240 operand eCXRegI(xRegI reg) %{ | |
| 4241 constraint(ALLOC_IN_RC(ecx_reg)); | |
| 4242 match(reg); | |
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4243 match(rRegI); |
| 0 | 4244 |
| 4245 format %{ "ECX" %} | |
| 4246 interface(REG_INTER); | |
| 4247 %} | |
| 4248 | |
| 4249 operand eDXRegI(xRegI reg) %{ | |
| 4250 constraint(ALLOC_IN_RC(edx_reg)); | |
| 4251 match(reg); | |
|
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4252 match(rRegI); |
| 0 | 4253 |
| 4254 format %{ "EDX" %} | |
| 4255 interface(REG_INTER); | |
| 4256 %} | |
| 4257 | |
| 4258 operand eDIRegI(xRegI reg) %{ | |
| 4259 constraint(ALLOC_IN_RC(edi_reg)); | |
| 4260 match(reg); | |
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4261 match(rRegI); |
| 0 | 4262 |
| 4263 format %{ "EDI" %} | |
| 4264 interface(REG_INTER); | |
| 4265 %} | |
| 4266 | |
| 4267 operand naxRegI() %{ | |
| 4268 constraint(ALLOC_IN_RC(nax_reg)); | |
| 4269 match(RegI); | |
| 4270 match(eCXRegI); | |
| 4271 match(eDXRegI); | |
| 4272 match(eSIRegI); | |
| 4273 match(eDIRegI); | |
| 4274 | |
| 4275 format %{ %} | |
| 4276 interface(REG_INTER); | |
| 4277 %} | |
| 4278 | |
| 4279 operand nadxRegI() %{ | |
| 4280 constraint(ALLOC_IN_RC(nadx_reg)); | |
| 4281 match(RegI); | |
| 4282 match(eBXRegI); | |
| 4283 match(eCXRegI); | |
| 4284 match(eSIRegI); | |
| 4285 match(eDIRegI); | |
| 4286 | |
| 4287 format %{ %} | |
| 4288 interface(REG_INTER); | |
| 4289 %} | |
| 4290 | |
| 4291 operand ncxRegI() %{ | |
| 4292 constraint(ALLOC_IN_RC(ncx_reg)); | |
| 4293 match(RegI); | |
| 4294 match(eAXRegI); | |
| 4295 match(eDXRegI); | |
| 4296 match(eSIRegI); | |
| 4297 match(eDIRegI); | |
| 4298 | |
| 4299 format %{ %} | |
| 4300 interface(REG_INTER); | |
| 4301 %} | |
| 4302 | |
| 4303 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg | |
| 4304 // // | |
| 4305 operand eSIRegI(xRegI reg) %{ | |
| 4306 constraint(ALLOC_IN_RC(esi_reg)); | |
| 4307 match(reg); | |
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4308 match(rRegI); |
| 0 | 4309 |
| 4310 format %{ "ESI" %} | |
| 4311 interface(REG_INTER); | |
| 4312 %} | |
| 4313 | |
| 4314 // Pointer Register | |
| 4315 operand anyRegP() %{ | |
| 4316 constraint(ALLOC_IN_RC(any_reg)); | |
| 4317 match(RegP); | |
| 4318 match(eAXRegP); | |
| 4319 match(eBXRegP); | |
| 4320 match(eCXRegP); | |
| 4321 match(eDIRegP); | |
| 4322 match(eRegP); | |
| 4323 | |
| 4324 format %{ %} | |
| 4325 interface(REG_INTER); | |
| 4326 %} | |
| 4327 | |
| 4328 operand eRegP() %{ | |
|
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4329 constraint(ALLOC_IN_RC(int_reg)); |
| 0 | 4330 match(RegP); |
| 4331 match(eAXRegP); | |
| 4332 match(eBXRegP); | |
| 4333 match(eCXRegP); | |
| 4334 match(eDIRegP); | |
| 4335 | |
| 4336 format %{ %} | |
| 4337 interface(REG_INTER); | |
| 4338 %} | |
| 4339 | |
| 4340 // On windows95, EBP is not safe to use for implicit null tests. | |
| 4341 operand eRegP_no_EBP() %{ | |
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|
4342 constraint(ALLOC_IN_RC(int_reg_no_rbp)); |
| 0 | 4343 match(RegP); |
| 4344 match(eAXRegP); | |
| 4345 match(eBXRegP); | |
| 4346 match(eCXRegP); | |
| 4347 match(eDIRegP); | |
| 4348 | |
| 4349 op_cost(100); | |
| 4350 format %{ %} | |
| 4351 interface(REG_INTER); | |
| 4352 %} | |
| 4353 | |
| 4354 operand naxRegP() %{ | |
| 4355 constraint(ALLOC_IN_RC(nax_reg)); | |
| 4356 match(RegP); | |
| 4357 match(eBXRegP); | |
| 4358 match(eDXRegP); | |
| 4359 match(eCXRegP); | |
| 4360 match(eSIRegP); | |
| 4361 match(eDIRegP); | |
| 4362 | |
| 4363 format %{ %} | |
| 4364 interface(REG_INTER); | |
| 4365 %} | |
| 4366 | |
| 4367 operand nabxRegP() %{ | |
| 4368 constraint(ALLOC_IN_RC(nabx_reg)); | |
| 4369 match(RegP); | |
| 4370 match(eCXRegP); | |
| 4371 match(eDXRegP); | |
| 4372 match(eSIRegP); | |
| 4373 match(eDIRegP); | |
| 4374 | |
| 4375 format %{ %} | |
| 4376 interface(REG_INTER); | |
| 4377 %} | |
| 4378 | |
| 4379 operand pRegP() %{ | |
| 4380 constraint(ALLOC_IN_RC(p_reg)); | |
| 4381 match(RegP); | |
| 4382 match(eBXRegP); | |
| 4383 match(eDXRegP); | |
| 4384 match(eSIRegP); | |
| 4385 match(eDIRegP); | |
| 4386 | |
| 4387 format %{ %} | |
| 4388 interface(REG_INTER); | |
| 4389 %} | |
| 4390 | |
| 4391 // Special Registers | |
| 4392 // Return a pointer value | |
| 4393 operand eAXRegP(eRegP reg) %{ | |
| 4394 constraint(ALLOC_IN_RC(eax_reg)); | |
| 4395 match(reg); | |
| 4396 format %{ "EAX" %} | |
| 4397 interface(REG_INTER); | |
| 4398 %} | |
| 4399 | |
| 4400 // Used in AtomicAdd | |
| 4401 operand eBXRegP(eRegP reg) %{ | |
| 4402 constraint(ALLOC_IN_RC(ebx_reg)); | |
| 4403 match(reg); | |
| 4404 format %{ "EBX" %} | |
| 4405 interface(REG_INTER); | |
| 4406 %} | |
| 4407 | |
| 4408 // Tail-call (interprocedural jump) to interpreter | |
| 4409 operand eCXRegP(eRegP reg) %{ | |
| 4410 constraint(ALLOC_IN_RC(ecx_reg)); | |
| 4411 match(reg); | |
| 4412 format %{ "ECX" %} | |
| 4413 interface(REG_INTER); | |
| 4414 %} | |
| 4415 | |
| 4416 operand eSIRegP(eRegP reg) %{ | |
| 4417 constraint(ALLOC_IN_RC(esi_reg)); | |
| 4418 match(reg); | |
| 4419 format %{ "ESI" %} | |
| 4420 interface(REG_INTER); | |
| 4421 %} | |
| 4422 | |
| 4423 // Used in rep stosw | |
| 4424 operand eDIRegP(eRegP reg) %{ | |
| 4425 constraint(ALLOC_IN_RC(edi_reg)); | |
| 4426 match(reg); | |
| 4427 format %{ "EDI" %} | |
| 4428 interface(REG_INTER); | |
| 4429 %} | |
| 4430 | |
| 4431 operand eBPRegP() %{ | |
| 4432 constraint(ALLOC_IN_RC(ebp_reg)); | |
| 4433 match(RegP); | |
| 4434 format %{ "EBP" %} | |
| 4435 interface(REG_INTER); | |
| 4436 %} | |
| 4437 | |
| 4438 operand eRegL() %{ | |
| 4439 constraint(ALLOC_IN_RC(long_reg)); | |
| 4440 match(RegL); | |
| 4441 match(eADXRegL); | |
| 4442 | |
| 4443 format %{ %} | |
| 4444 interface(REG_INTER); | |
| 4445 %} | |
| 4446 | |
| 4447 operand eADXRegL( eRegL reg ) %{ | |
| 4448 constraint(ALLOC_IN_RC(eadx_reg)); | |
| 4449 match(reg); | |
| 4450 | |
| 4451 format %{ "EDX:EAX" %} | |
| 4452 interface(REG_INTER); | |
| 4453 %} | |
| 4454 | |
| 4455 operand eBCXRegL( eRegL reg ) %{ | |
| 4456 constraint(ALLOC_IN_RC(ebcx_reg)); | |
| 4457 match(reg); | |
| 4458 | |
| 4459 format %{ "EBX:ECX" %} | |
| 4460 interface(REG_INTER); | |
| 4461 %} | |
| 4462 | |
| 4463 // Special case for integer high multiply | |
| 4464 operand eADXRegL_low_only() %{ | |
| 4465 constraint(ALLOC_IN_RC(eadx_reg)); | |
| 4466 match(RegL); | |
| 4467 | |
| 4468 format %{ "EAX" %} | |
| 4469 interface(REG_INTER); | |
| 4470 %} | |
| 4471 | |
| 4472 // Flags register, used as output of compare instructions | |
| 4473 operand eFlagsReg() %{ | |
| 4474 constraint(ALLOC_IN_RC(int_flags)); | |
| 4475 match(RegFlags); | |
| 4476 | |
| 4477 format %{ "EFLAGS" %} | |
| 4478 interface(REG_INTER); | |
| 4479 %} | |
| 4480 | |
| 4481 // Flags register, used as output of FLOATING POINT compare instructions | |
| 4482 operand eFlagsRegU() %{ | |
| 4483 constraint(ALLOC_IN_RC(int_flags)); | |
| 4484 match(RegFlags); | |
| 4485 | |
| 4486 format %{ "EFLAGS_U" %} | |
| 4487 interface(REG_INTER); | |
| 4488 %} | |
| 4489 | |
|
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|
4490 operand eFlagsRegUCF() %{ |
|
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|
4491 constraint(ALLOC_IN_RC(int_flags)); |
|
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|
4492 match(RegFlags); |
|
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|
4493 predicate(false); |
|
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|
4494 |
|
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|
4495 format %{ "EFLAGS_U_CF" %} |
|
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|
4496 interface(REG_INTER); |
|
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|
4497 %} |
|
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|
4498 |
| 0 | 4499 // Condition Code Register used by long compare |
| 4500 operand flagsReg_long_LTGE() %{ | |
| 4501 constraint(ALLOC_IN_RC(int_flags)); | |
| 4502 match(RegFlags); | |
| 4503 format %{ "FLAGS_LTGE" %} | |
| 4504 interface(REG_INTER); | |
| 4505 %} | |
| 4506 operand flagsReg_long_EQNE() %{ | |
| 4507 constraint(ALLOC_IN_RC(int_flags)); | |
| 4508 match(RegFlags); | |
| 4509 format %{ "FLAGS_EQNE" %} | |
| 4510 interface(REG_INTER); | |
| 4511 %} | |
| 4512 operand flagsReg_long_LEGT() %{ | |
| 4513 constraint(ALLOC_IN_RC(int_flags)); | |
| 4514 match(RegFlags); | |
| 4515 format %{ "FLAGS_LEGT" %} | |
| 4516 interface(REG_INTER); | |
| 4517 %} | |
| 4518 | |
| 4519 // Float register operands | |
|
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|
4520 operand regDPR() %{ |
| 0 | 4521 predicate( UseSSE < 2 ); |
|
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|
4522 constraint(ALLOC_IN_RC(fp_dbl_reg)); |
| 0 | 4523 match(RegD); |
| 4524 match(regDPR1); | |
| 4525 match(regDPR2); | |
| 4526 format %{ %} | |
| 4527 interface(REG_INTER); | |
| 4528 %} | |
| 4529 | |
|
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|
4530 operand regDPR1(regDPR reg) %{ |
| 0 | 4531 predicate( UseSSE < 2 ); |
|
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|
4532 constraint(ALLOC_IN_RC(fp_dbl_reg0)); |
| 0 | 4533 match(reg); |
| 4534 format %{ "FPR1" %} | |
| 4535 interface(REG_INTER); | |
| 4536 %} | |
| 4537 | |
|
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|
4538 operand regDPR2(regDPR reg) %{ |
| 0 | 4539 predicate( UseSSE < 2 ); |
|
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|
4540 constraint(ALLOC_IN_RC(fp_dbl_reg1)); |
| 0 | 4541 match(reg); |
| 4542 format %{ "FPR2" %} | |
| 4543 interface(REG_INTER); | |
| 4544 %} | |
| 4545 | |
|
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|
4546 operand regnotDPR1(regDPR reg) %{ |
| 0 | 4547 predicate( UseSSE < 2 ); |
|
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|
4548 constraint(ALLOC_IN_RC(fp_dbl_notreg0)); |
| 0 | 4549 match(reg); |
| 4550 format %{ %} | |
| 4551 interface(REG_INTER); | |
| 4552 %} | |
| 4553 | |
| 4554 // Float register operands | |
|
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|
4555 operand regFPR() %{ |
| 0 | 4556 predicate( UseSSE < 2 ); |
|
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|
4557 constraint(ALLOC_IN_RC(fp_flt_reg)); |
| 0 | 4558 match(RegF); |
| 4559 match(regFPR1); | |
| 4560 format %{ %} | |
| 4561 interface(REG_INTER); | |
| 4562 %} | |
| 4563 | |
| 4564 // Float register operands | |
|
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|
4565 operand regFPR1(regFPR reg) %{ |
| 0 | 4566 predicate( UseSSE < 2 ); |
|
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|
4567 constraint(ALLOC_IN_RC(fp_flt_reg0)); |
| 0 | 4568 match(reg); |
| 4569 format %{ "FPR1" %} | |
| 4570 interface(REG_INTER); | |
| 4571 %} | |
| 4572 | |
|
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|
4573 // XMM Float register operands |
|
4761
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|
4574 operand regF() %{ |
| 0 | 4575 predicate( UseSSE>=1 ); |
|
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|
4576 constraint(ALLOC_IN_RC(float_reg)); |
| 0 | 4577 match(RegF); |
| 4578 format %{ %} | |
| 4579 interface(REG_INTER); | |
| 4580 %} | |
| 4581 | |
|
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|
4582 // XMM Double register operands |
|
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|
4583 operand regD() %{ |
|
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|
4584 predicate( UseSSE>=2 ); |
|
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|
4585 constraint(ALLOC_IN_RC(double_reg)); |
|
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|
4586 match(RegD); |
|
8c92982cbbc4
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|
4587 format %{ %} |
|
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|
4588 interface(REG_INTER); |
|
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|
4589 %} |
|
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|
4590 |
| 0 | 4591 |
| 4592 //----------Memory Operands---------------------------------------------------- | |
| 4593 // Direct Memory Operand | |
| 4594 operand direct(immP addr) %{ | |
| 4595 match(addr); | |
| 4596 | |
| 4597 format %{ "[$addr]" %} | |
| 4598 interface(MEMORY_INTER) %{ | |
| 4599 base(0xFFFFFFFF); | |
| 4600 index(0x4); | |
| 4601 scale(0x0); | |
| 4602 disp($addr); | |
| 4603 %} | |
| 4604 %} | |
| 4605 | |
| 4606 // Indirect Memory Operand | |
| 4607 operand indirect(eRegP reg) %{ | |
|
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|
4608 constraint(ALLOC_IN_RC(int_reg)); |
| 0 | 4609 match(reg); |
| 4610 | |
| 4611 format %{ "[$reg]" %} | |
| 4612 interface(MEMORY_INTER) %{ | |
| 4613 base($reg); | |
| 4614 index(0x4); | |
| 4615 scale(0x0); | |
| 4616 disp(0x0); | |
| 4617 %} | |
| 4618 %} | |
| 4619 | |
| 4620 // Indirect Memory Plus Short Offset Operand | |
| 4621 operand indOffset8(eRegP reg, immI8 off) %{ | |
| 4622 match(AddP reg off); | |
| 4623 | |
| 4624 format %{ "[$reg + $off]" %} | |
| 4625 interface(MEMORY_INTER) %{ | |
| 4626 base($reg); | |
| 4627 index(0x4); | |
| 4628 scale(0x0); | |
| 4629 disp($off); | |
| 4630 %} | |
| 4631 %} | |
| 4632 | |
| 4633 // Indirect Memory Plus Long Offset Operand | |
| 4634 operand indOffset32(eRegP reg, immI off) %{ | |
| 4635 match(AddP reg off); | |
| 4636 | |
| 4637 format %{ "[$reg + $off]" %} | |
| 4638 interface(MEMORY_INTER) %{ | |
| 4639 base($reg); | |
| 4640 index(0x4); | |
| 4641 scale(0x0); | |
| 4642 disp($off); | |
| 4643 %} | |
| 4644 %} | |
| 4645 | |
| 4646 // Indirect Memory Plus Long Offset Operand | |
|
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|
4647 operand indOffset32X(rRegI reg, immP off) %{ |
| 0 | 4648 match(AddP off reg); |
| 4649 | |
| 4650 format %{ "[$reg + $off]" %} | |
| 4651 interface(MEMORY_INTER) %{ | |
| 4652 base($reg); | |
| 4653 index(0x4); | |
| 4654 scale(0x0); | |
| 4655 disp($off); | |
| 4656 %} | |
| 4657 %} | |
| 4658 | |
| 4659 // Indirect Memory Plus Index Register Plus Offset Operand | |
|
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|
4660 operand indIndexOffset(eRegP reg, rRegI ireg, immI off) %{ |
| 0 | 4661 match(AddP (AddP reg ireg) off); |
| 4662 | |
| 4663 op_cost(10); | |
| 4664 format %{"[$reg + $off + $ireg]" %} | |
| 4665 interface(MEMORY_INTER) %{ | |
| 4666 base($reg); | |
| 4667 index($ireg); | |
| 4668 scale(0x0); | |
| 4669 disp($off); | |
| 4670 %} | |
| 4671 %} | |
| 4672 | |
| 4673 // Indirect Memory Plus Index Register Plus Offset Operand | |
|
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|
4674 operand indIndex(eRegP reg, rRegI ireg) %{ |
| 0 | 4675 match(AddP reg ireg); |
| 4676 | |
| 4677 op_cost(10); | |
| 4678 format %{"[$reg + $ireg]" %} | |
| 4679 interface(MEMORY_INTER) %{ | |
| 4680 base($reg); | |
| 4681 index($ireg); | |
| 4682 scale(0x0); | |
| 4683 disp(0x0); | |
| 4684 %} | |
| 4685 %} | |
| 4686 | |
| 4687 // // ------------------------------------------------------------------------- | |
| 4688 // // 486 architecture doesn't support "scale * index + offset" with out a base | |
| 4689 // // ------------------------------------------------------------------------- | |
| 4690 // // Scaled Memory Operands | |
| 4691 // // Indirect Memory Times Scale Plus Offset Operand | |
|
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|
4692 // operand indScaleOffset(immP off, rRegI ireg, immI2 scale) %{ |
| 0 | 4693 // match(AddP off (LShiftI ireg scale)); |
| 4694 // | |
| 4695 // op_cost(10); | |
| 4696 // format %{"[$off + $ireg << $scale]" %} | |
| 4697 // interface(MEMORY_INTER) %{ | |
| 4698 // base(0x4); | |
| 4699 // index($ireg); | |
| 4700 // scale($scale); | |
| 4701 // disp($off); | |
| 4702 // %} | |
| 4703 // %} | |
| 4704 | |
| 4705 // Indirect Memory Times Scale Plus Index Register | |
|
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|
4706 operand indIndexScale(eRegP reg, rRegI ireg, immI2 scale) %{ |
| 0 | 4707 match(AddP reg (LShiftI ireg scale)); |
| 4708 | |
| 4709 op_cost(10); | |
| 4710 format %{"[$reg + $ireg << $scale]" %} | |
| 4711 interface(MEMORY_INTER) %{ | |
| 4712 base($reg); | |
| 4713 index($ireg); | |
| 4714 scale($scale); | |
| 4715 disp(0x0); | |
| 4716 %} | |
| 4717 %} | |
| 4718 | |
| 4719 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand | |
|
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|
4720 operand indIndexScaleOffset(eRegP reg, immI off, rRegI ireg, immI2 scale) %{ |
| 0 | 4721 match(AddP (AddP reg (LShiftI ireg scale)) off); |
| 4722 | |
| 4723 op_cost(10); | |
| 4724 format %{"[$reg + $off + $ireg << $scale]" %} | |
| 4725 interface(MEMORY_INTER) %{ | |
| 4726 base($reg); | |
| 4727 index($ireg); | |
| 4728 scale($scale); | |
| 4729 disp($off); | |
| 4730 %} | |
| 4731 %} | |
| 4732 | |
| 4733 //----------Load Long Memory Operands------------------------------------------ | |
| 4734 // The load-long idiom will use it's address expression again after loading | |
| 4735 // the first word of the long. If the load-long destination overlaps with | |
| 4736 // registers used in the addressing expression, the 2nd half will be loaded | |
| 4737 // from a clobbered address. Fix this by requiring that load-long use | |
| 4738 // address registers that do not overlap with the load-long target. | |
| 4739 | |
| 4740 // load-long support | |
| 4741 operand load_long_RegP() %{ | |
| 4742 constraint(ALLOC_IN_RC(esi_reg)); | |
| 4743 match(RegP); | |
| 4744 match(eSIRegP); | |
| 4745 op_cost(100); | |
| 4746 format %{ %} | |
| 4747 interface(REG_INTER); | |
| 4748 %} | |
| 4749 | |
| 4750 // Indirect Memory Operand Long | |
| 4751 operand load_long_indirect(load_long_RegP reg) %{ | |
| 4752 constraint(ALLOC_IN_RC(esi_reg)); | |
| 4753 match(reg); | |
| 4754 | |
| 4755 format %{ "[$reg]" %} | |
| 4756 interface(MEMORY_INTER) %{ | |
| 4757 base($reg); | |
| 4758 index(0x4); | |
| 4759 scale(0x0); | |
| 4760 disp(0x0); | |
| 4761 %} | |
| 4762 %} | |
| 4763 | |
| 4764 // Indirect Memory Plus Long Offset Operand | |
| 4765 operand load_long_indOffset32(load_long_RegP reg, immI off) %{ | |
| 4766 match(AddP reg off); | |
| 4767 | |
| 4768 format %{ "[$reg + $off]" %} | |
| 4769 interface(MEMORY_INTER) %{ | |
| 4770 base($reg); | |
| 4771 index(0x4); | |
| 4772 scale(0x0); | |
| 4773 disp($off); | |
| 4774 %} | |
| 4775 %} | |
| 4776 | |
| 4777 opclass load_long_memory(load_long_indirect, load_long_indOffset32); | |
| 4778 | |
| 4779 | |
| 4780 //----------Special Memory Operands-------------------------------------------- | |
| 4781 // Stack Slot Operand - This operand is used for loading and storing temporary | |
| 4782 // values on the stack where a match requires a value to | |
| 4783 // flow through memory. | |
| 4784 operand stackSlotP(sRegP reg) %{ | |
| 4785 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4786 // No match rule because this operand is only generated in matching | |
| 4787 format %{ "[$reg]" %} | |
| 4788 interface(MEMORY_INTER) %{ | |
| 4789 base(0x4); // ESP | |
| 4790 index(0x4); // No Index | |
| 4791 scale(0x0); // No Scale | |
| 4792 disp($reg); // Stack Offset | |
| 4793 %} | |
| 4794 %} | |
| 4795 | |
| 4796 operand stackSlotI(sRegI reg) %{ | |
| 4797 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4798 // No match rule because this operand is only generated in matching | |
| 4799 format %{ "[$reg]" %} | |
| 4800 interface(MEMORY_INTER) %{ | |
| 4801 base(0x4); // ESP | |
| 4802 index(0x4); // No Index | |
| 4803 scale(0x0); // No Scale | |
| 4804 disp($reg); // Stack Offset | |
| 4805 %} | |
| 4806 %} | |
| 4807 | |
| 4808 operand stackSlotF(sRegF reg) %{ | |
| 4809 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4810 // No match rule because this operand is only generated in matching | |
| 4811 format %{ "[$reg]" %} | |
| 4812 interface(MEMORY_INTER) %{ | |
| 4813 base(0x4); // ESP | |
| 4814 index(0x4); // No Index | |
| 4815 scale(0x0); // No Scale | |
| 4816 disp($reg); // Stack Offset | |
| 4817 %} | |
| 4818 %} | |
| 4819 | |
| 4820 operand stackSlotD(sRegD reg) %{ | |
| 4821 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4822 // No match rule because this operand is only generated in matching | |
| 4823 format %{ "[$reg]" %} | |
| 4824 interface(MEMORY_INTER) %{ | |
| 4825 base(0x4); // ESP | |
| 4826 index(0x4); // No Index | |
| 4827 scale(0x0); // No Scale | |
| 4828 disp($reg); // Stack Offset | |
| 4829 %} | |
| 4830 %} | |
| 4831 | |
| 4832 operand stackSlotL(sRegL reg) %{ | |
| 4833 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4834 // No match rule because this operand is only generated in matching | |
| 4835 format %{ "[$reg]" %} | |
| 4836 interface(MEMORY_INTER) %{ | |
| 4837 base(0x4); // ESP | |
| 4838 index(0x4); // No Index | |
| 4839 scale(0x0); // No Scale | |
| 4840 disp($reg); // Stack Offset | |
| 4841 %} | |
| 4842 %} | |
| 4843 | |
| 4844 //----------Memory Operands - Win95 Implicit Null Variants---------------- | |
| 4845 // Indirect Memory Operand | |
| 4846 operand indirect_win95_safe(eRegP_no_EBP reg) | |
| 4847 %{ | |
|
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4848 constraint(ALLOC_IN_RC(int_reg)); |
| 0 | 4849 match(reg); |
| 4850 | |
| 4851 op_cost(100); | |
| 4852 format %{ "[$reg]" %} | |
| 4853 interface(MEMORY_INTER) %{ | |
| 4854 base($reg); | |
| 4855 index(0x4); | |
| 4856 scale(0x0); | |
| 4857 disp(0x0); | |
| 4858 %} | |
| 4859 %} | |
| 4860 | |
| 4861 // Indirect Memory Plus Short Offset Operand | |
| 4862 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off) | |
| 4863 %{ | |
| 4864 match(AddP reg off); | |
| 4865 | |
| 4866 op_cost(100); | |
| 4867 format %{ "[$reg + $off]" %} | |
| 4868 interface(MEMORY_INTER) %{ | |
| 4869 base($reg); | |
| 4870 index(0x4); | |
| 4871 scale(0x0); | |
| 4872 disp($off); | |
| 4873 %} | |
| 4874 %} | |
| 4875 | |
| 4876 // Indirect Memory Plus Long Offset Operand | |
| 4877 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off) | |
| 4878 %{ | |
| 4879 match(AddP reg off); | |
| 4880 | |
| 4881 op_cost(100); | |
| 4882 format %{ "[$reg + $off]" %} | |
| 4883 interface(MEMORY_INTER) %{ | |
| 4884 base($reg); | |
| 4885 index(0x4); | |
| 4886 scale(0x0); | |
| 4887 disp($off); | |
| 4888 %} | |
| 4889 %} | |
| 4890 | |
| 4891 // Indirect Memory Plus Index Register Plus Offset Operand | |
|
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4892 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI off) |
| 0 | 4893 %{ |
| 4894 match(AddP (AddP reg ireg) off); | |
| 4895 | |
| 4896 op_cost(100); | |
| 4897 format %{"[$reg + $off + $ireg]" %} | |
| 4898 interface(MEMORY_INTER) %{ | |
| 4899 base($reg); | |
| 4900 index($ireg); | |
| 4901 scale(0x0); | |
| 4902 disp($off); | |
| 4903 %} | |
| 4904 %} | |
| 4905 | |
| 4906 // Indirect Memory Times Scale Plus Index Register | |
|
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4907 operand indIndexScale_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI2 scale) |
| 0 | 4908 %{ |
| 4909 match(AddP reg (LShiftI ireg scale)); | |
| 4910 | |
| 4911 op_cost(100); | |
| 4912 format %{"[$reg + $ireg << $scale]" %} | |
| 4913 interface(MEMORY_INTER) %{ | |
| 4914 base($reg); | |
| 4915 index($ireg); | |
| 4916 scale($scale); | |
| 4917 disp(0x0); | |
| 4918 %} | |
| 4919 %} | |
| 4920 | |
| 4921 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand | |
|
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4922 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, rRegI ireg, immI2 scale) |
| 0 | 4923 %{ |
| 4924 match(AddP (AddP reg (LShiftI ireg scale)) off); | |
| 4925 | |
| 4926 op_cost(100); | |
| 4927 format %{"[$reg + $off + $ireg << $scale]" %} | |
| 4928 interface(MEMORY_INTER) %{ | |
| 4929 base($reg); | |
| 4930 index($ireg); | |
| 4931 scale($scale); | |
| 4932 disp($off); | |
| 4933 %} | |
| 4934 %} | |
| 4935 | |
| 4936 //----------Conditional Branch Operands---------------------------------------- | |
| 4937 // Comparison Op - This is the operation of the comparison, and is limited to | |
| 4938 // the following set of codes: | |
| 4939 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) | |
| 4940 // | |
| 4941 // Other attributes of the comparison, such as unsignedness, are specified | |
| 4942 // by the comparison instruction that sets a condition code flags register. | |
| 4943 // That result is represented by a flags operand whose subtype is appropriate | |
| 4944 // to the unsignedness (etc.) of the comparison. | |
| 4945 // | |
| 4946 // Later, the instruction which matches both the Comparison Op (a Bool) and | |
| 4947 // the flags (produced by the Cmp) specifies the coding of the comparison op | |
| 4948 // by matching a specific subtype of Bool operand below, such as cmpOpU. | |
| 4949 | |
| 4950 // Comparision Code | |
| 4951 operand cmpOp() %{ | |
| 4952 match(Bool); | |
| 4953 | |
| 4954 format %{ "" %} | |
| 4955 interface(COND_INTER) %{ | |
|
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4956 equal(0x4, "e"); |
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4957 not_equal(0x5, "ne"); |
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4958 less(0xC, "l"); |
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4959 greater_equal(0xD, "ge"); |
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4960 less_equal(0xE, "le"); |
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4961 greater(0xF, "g"); |
| 0 | 4962 %} |
| 4963 %} | |
| 4964 | |
| 4965 // Comparison Code, unsigned compare. Used by FP also, with | |
| 4966 // C2 (unordered) turned into GT or LT already. The other bits | |
| 4967 // C0 and C3 are turned into Carry & Zero flags. | |
| 4968 operand cmpOpU() %{ | |
| 4969 match(Bool); | |
| 4970 | |
| 4971 format %{ "" %} | |
| 4972 interface(COND_INTER) %{ | |
|
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4973 equal(0x4, "e"); |
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|
4974 not_equal(0x5, "ne"); |
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4975 less(0x2, "b"); |
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4976 greater_equal(0x3, "nb"); |
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4977 less_equal(0x6, "be"); |
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|
4978 greater(0x7, "nbe"); |
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4979 %} |
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4980 %} |
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|
4981 |
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4982 // Floating comparisons that don't require any fixup for the unordered case |
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4983 operand cmpOpUCF() %{ |
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4984 match(Bool); |
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4985 predicate(n->as_Bool()->_test._test == BoolTest::lt || |
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4986 n->as_Bool()->_test._test == BoolTest::ge || |
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4987 n->as_Bool()->_test._test == BoolTest::le || |
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4988 n->as_Bool()->_test._test == BoolTest::gt); |
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|
4989 format %{ "" %} |
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|
4990 interface(COND_INTER) %{ |
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|
4991 equal(0x4, "e"); |
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|
4992 not_equal(0x5, "ne"); |
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4993 less(0x2, "b"); |
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|
4994 greater_equal(0x3, "nb"); |
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4995 less_equal(0x6, "be"); |
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|
4996 greater(0x7, "nbe"); |
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|
4997 %} |
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4998 %} |
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|
4999 |
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|
5000 |
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5001 // Floating comparisons that can be fixed up with extra conditional jumps |
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5002 operand cmpOpUCF2() %{ |
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5003 match(Bool); |
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5004 predicate(n->as_Bool()->_test._test == BoolTest::ne || |
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5005 n->as_Bool()->_test._test == BoolTest::eq); |
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|
5006 format %{ "" %} |
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|
5007 interface(COND_INTER) %{ |
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|
5008 equal(0x4, "e"); |
|
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|
5009 not_equal(0x5, "ne"); |
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|
5010 less(0x2, "b"); |
|
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|
5011 greater_equal(0x3, "nb"); |
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|
5012 less_equal(0x6, "be"); |
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5013 greater(0x7, "nbe"); |
| 0 | 5014 %} |
| 5015 %} | |
| 5016 | |
| 5017 // Comparison Code for FP conditional move | |
| 5018 operand cmpOp_fcmov() %{ | |
| 5019 match(Bool); | |
| 5020 | |
| 5021 format %{ "" %} | |
| 5022 interface(COND_INTER) %{ | |
| 5023 equal (0x0C8); | |
| 5024 not_equal (0x1C8); | |
| 5025 less (0x0C0); | |
| 5026 greater_equal(0x1C0); | |
| 5027 less_equal (0x0D0); | |
| 5028 greater (0x1D0); | |
| 5029 %} | |
| 5030 %} | |
| 5031 | |
| 5032 // Comparision Code used in long compares | |
| 5033 operand cmpOp_commute() %{ | |
| 5034 match(Bool); | |
| 5035 | |
| 5036 format %{ "" %} | |
| 5037 interface(COND_INTER) %{ | |
|
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|
5038 equal(0x4, "e"); |
|
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|
5039 not_equal(0x5, "ne"); |
|
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|
5040 less(0xF, "g"); |
|
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|
5041 greater_equal(0xE, "le"); |
|
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|
5042 less_equal(0xD, "ge"); |
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|
5043 greater(0xC, "l"); |
| 0 | 5044 %} |
| 5045 %} | |
| 5046 | |
| 5047 //----------OPERAND CLASSES---------------------------------------------------- | |
| 5048 // Operand Classes are groups of operands that are used as to simplify | |
| 605 | 5049 // instruction definitions by not requiring the AD writer to specify separate |
| 0 | 5050 // instructions for every form of operand when the instruction accepts |
| 5051 // multiple operand types with the same basic encoding and format. The classic | |
| 5052 // case of this is memory operands. | |
| 5053 | |
| 5054 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset, | |
| 5055 indIndex, indIndexScale, indIndexScaleOffset); | |
| 5056 | |
| 5057 // Long memory operations are encoded in 2 instructions and a +4 offset. | |
| 5058 // This means some kind of offset is always required and you cannot use | |
| 5059 // an oop as the offset (done when working on static globals). | |
| 5060 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset, | |
| 5061 indIndex, indIndexScale, indIndexScaleOffset); | |
| 5062 | |
| 5063 | |
| 5064 //----------PIPELINE----------------------------------------------------------- | |
| 5065 // Rules which define the behavior of the target architectures pipeline. | |
| 5066 pipeline %{ | |
| 5067 | |
| 5068 //----------ATTRIBUTES--------------------------------------------------------- | |
| 5069 attributes %{ | |
| 5070 variable_size_instructions; // Fixed size instructions | |
| 5071 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle | |
| 5072 instruction_unit_size = 1; // An instruction is 1 bytes long | |
| 5073 instruction_fetch_unit_size = 16; // The processor fetches one line | |
| 5074 instruction_fetch_units = 1; // of 16 bytes | |
| 5075 | |
| 5076 // List of nop instructions | |
| 5077 nops( MachNop ); | |
| 5078 %} | |
| 5079 | |
| 5080 //----------RESOURCES---------------------------------------------------------- | |
| 5081 // Resources are the functional units available to the machine | |
| 5082 | |
| 5083 // Generic P2/P3 pipeline | |
| 5084 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of | |
| 5085 // 3 instructions decoded per cycle. | |
| 5086 // 2 load/store ops per cycle, 1 branch, 1 FPU, | |
| 5087 // 2 ALU op, only ALU0 handles mul/div instructions. | |
| 5088 resources( D0, D1, D2, DECODE = D0 | D1 | D2, | |
| 5089 MS0, MS1, MEM = MS0 | MS1, | |
| 5090 BR, FPU, | |
| 5091 ALU0, ALU1, ALU = ALU0 | ALU1 ); | |
| 5092 | |
| 5093 //----------PIPELINE DESCRIPTION----------------------------------------------- | |
| 5094 // Pipeline Description specifies the stages in the machine's pipeline | |
| 5095 | |
| 5096 // Generic P2/P3 pipeline | |
| 5097 pipe_desc(S0, S1, S2, S3, S4, S5); | |
| 5098 | |
| 5099 //----------PIPELINE CLASSES--------------------------------------------------- | |
| 5100 // Pipeline Classes describe the stages in which input and output are | |
| 5101 // referenced by the hardware pipeline. | |
| 5102 | |
| 5103 // Naming convention: ialu or fpu | |
| 5104 // Then: _reg | |
| 5105 // Then: _reg if there is a 2nd register | |
| 5106 // Then: _long if it's a pair of instructions implementing a long | |
| 5107 // Then: _fat if it requires the big decoder | |
| 5108 // Or: _mem if it requires the big decoder and a memory unit. | |
| 5109 | |
| 5110 // Integer ALU reg operation | |
|
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5111 pipe_class ialu_reg(rRegI dst) %{ |
| 0 | 5112 single_instruction; |
| 5113 dst : S4(write); | |
| 5114 dst : S3(read); | |
| 5115 DECODE : S0; // any decoder | |
| 5116 ALU : S3; // any alu | |
| 5117 %} | |
| 5118 | |
| 5119 // Long ALU reg operation | |
| 5120 pipe_class ialu_reg_long(eRegL dst) %{ | |
| 5121 instruction_count(2); | |
| 5122 dst : S4(write); | |
| 5123 dst : S3(read); | |
| 5124 DECODE : S0(2); // any 2 decoders | |
| 5125 ALU : S3(2); // both alus | |
| 5126 %} | |
| 5127 | |
| 5128 // Integer ALU reg operation using big decoder | |
|
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5129 pipe_class ialu_reg_fat(rRegI dst) %{ |
| 0 | 5130 single_instruction; |
| 5131 dst : S4(write); | |
| 5132 dst : S3(read); | |
| 5133 D0 : S0; // big decoder only | |
| 5134 ALU : S3; // any alu | |
| 5135 %} | |
| 5136 | |
| 5137 // Long ALU reg operation using big decoder | |
| 5138 pipe_class ialu_reg_long_fat(eRegL dst) %{ | |
| 5139 instruction_count(2); | |
| 5140 dst : S4(write); | |
| 5141 dst : S3(read); | |
| 5142 D0 : S0(2); // big decoder only; twice | |
| 5143 ALU : S3(2); // any 2 alus | |
| 5144 %} | |
| 5145 | |
| 5146 // Integer ALU reg-reg operation | |
|
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5147 pipe_class ialu_reg_reg(rRegI dst, rRegI src) %{ |
| 0 | 5148 single_instruction; |
| 5149 dst : S4(write); | |
| 5150 src : S3(read); | |
| 5151 DECODE : S0; // any decoder | |
| 5152 ALU : S3; // any alu | |
| 5153 %} | |
| 5154 | |
| 5155 // Long ALU reg-reg operation | |
| 5156 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{ | |
| 5157 instruction_count(2); | |
| 5158 dst : S4(write); | |
| 5159 src : S3(read); | |
| 5160 DECODE : S0(2); // any 2 decoders | |
| 5161 ALU : S3(2); // both alus | |
| 5162 %} | |
| 5163 | |
| 5164 // Integer ALU reg-reg operation | |
|
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5165 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) %{ |
| 0 | 5166 single_instruction; |
| 5167 dst : S4(write); | |
| 5168 src : S3(read); | |
| 5169 D0 : S0; // big decoder only | |
| 5170 ALU : S3; // any alu | |
| 5171 %} | |
| 5172 | |
| 5173 // Long ALU reg-reg operation | |
| 5174 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{ | |
| 5175 instruction_count(2); | |
| 5176 dst : S4(write); | |
| 5177 src : S3(read); | |
| 5178 D0 : S0(2); // big decoder only; twice | |
| 5179 ALU : S3(2); // both alus | |
| 5180 %} | |
| 5181 | |
| 5182 // Integer ALU reg-mem operation | |
|
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5183 pipe_class ialu_reg_mem(rRegI dst, memory mem) %{ |
| 0 | 5184 single_instruction; |
| 5185 dst : S5(write); | |
| 5186 mem : S3(read); | |
| 5187 D0 : S0; // big decoder only | |
| 5188 ALU : S4; // any alu | |
| 5189 MEM : S3; // any mem | |
| 5190 %} | |
| 5191 | |
| 5192 // Long ALU reg-mem operation | |
| 5193 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{ | |
| 5194 instruction_count(2); | |
| 5195 dst : S5(write); | |
| 5196 mem : S3(read); | |
| 5197 D0 : S0(2); // big decoder only; twice | |
| 5198 ALU : S4(2); // any 2 alus | |
| 5199 MEM : S3(2); // both mems | |
| 5200 %} | |
| 5201 | |
| 5202 // Integer mem operation (prefetch) | |
| 5203 pipe_class ialu_mem(memory mem) | |
| 5204 %{ | |
| 5205 single_instruction; | |
| 5206 mem : S3(read); | |
| 5207 D0 : S0; // big decoder only | |
| 5208 MEM : S3; // any mem | |
| 5209 %} | |
| 5210 | |
| 5211 // Integer Store to Memory | |
|
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5212 pipe_class ialu_mem_reg(memory mem, rRegI src) %{ |
| 0 | 5213 single_instruction; |
| 5214 mem : S3(read); | |
| 5215 src : S5(read); | |
| 5216 D0 : S0; // big decoder only | |
| 5217 ALU : S4; // any alu | |
| 5218 MEM : S3; | |
| 5219 %} | |
| 5220 | |
| 5221 // Long Store to Memory | |
| 5222 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{ | |
| 5223 instruction_count(2); | |
| 5224 mem : S3(read); | |
| 5225 src : S5(read); | |
| 5226 D0 : S0(2); // big decoder only; twice | |
| 5227 ALU : S4(2); // any 2 alus | |
| 5228 MEM : S3(2); // Both mems | |
| 5229 %} | |
| 5230 | |
| 5231 // Integer Store to Memory | |
| 5232 pipe_class ialu_mem_imm(memory mem) %{ | |
| 5233 single_instruction; | |
| 5234 mem : S3(read); | |
| 5235 D0 : S0; // big decoder only | |
| 5236 ALU : S4; // any alu | |
| 5237 MEM : S3; | |
| 5238 %} | |
| 5239 | |
| 5240 // Integer ALU0 reg-reg operation | |
|
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5241 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) %{ |
| 0 | 5242 single_instruction; |
| 5243 dst : S4(write); | |
| 5244 src : S3(read); | |
| 5245 D0 : S0; // Big decoder only | |
| 5246 ALU0 : S3; // only alu0 | |
| 5247 %} | |
| 5248 | |
| 5249 // Integer ALU0 reg-mem operation | |
|
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5250 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) %{ |
| 0 | 5251 single_instruction; |
| 5252 dst : S5(write); | |
| 5253 mem : S3(read); | |
| 5254 D0 : S0; // big decoder only | |
| 5255 ALU0 : S4; // ALU0 only | |
| 5256 MEM : S3; // any mem | |
| 5257 %} | |
| 5258 | |
| 5259 // Integer ALU reg-reg operation | |
|
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5260 pipe_class ialu_cr_reg_reg(eFlagsReg cr, rRegI src1, rRegI src2) %{ |
| 0 | 5261 single_instruction; |
| 5262 cr : S4(write); | |
| 5263 src1 : S3(read); | |
| 5264 src2 : S3(read); | |
| 5265 DECODE : S0; // any decoder | |
| 5266 ALU : S3; // any alu | |
| 5267 %} | |
| 5268 | |
| 5269 // Integer ALU reg-imm operation | |
|
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5270 pipe_class ialu_cr_reg_imm(eFlagsReg cr, rRegI src1) %{ |
| 0 | 5271 single_instruction; |
| 5272 cr : S4(write); | |
| 5273 src1 : S3(read); | |
| 5274 DECODE : S0; // any decoder | |
| 5275 ALU : S3; // any alu | |
| 5276 %} | |
| 5277 | |
| 5278 // Integer ALU reg-mem operation | |
|
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5279 pipe_class ialu_cr_reg_mem(eFlagsReg cr, rRegI src1, memory src2) %{ |
| 0 | 5280 single_instruction; |
| 5281 cr : S4(write); | |
| 5282 src1 : S3(read); | |
| 5283 src2 : S3(read); | |
| 5284 D0 : S0; // big decoder only | |
| 5285 ALU : S4; // any alu | |
| 5286 MEM : S3; | |
| 5287 %} | |
| 5288 | |
| 5289 // Conditional move reg-reg | |
|
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5290 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y ) %{ |
| 0 | 5291 instruction_count(4); |
| 5292 y : S4(read); | |
| 5293 q : S3(read); | |
| 5294 p : S3(read); | |
| 5295 DECODE : S0(4); // any decoder | |
| 5296 %} | |
| 5297 | |
| 5298 // Conditional move reg-reg | |
|
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5299 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, eFlagsReg cr ) %{ |
| 0 | 5300 single_instruction; |
| 5301 dst : S4(write); | |
| 5302 src : S3(read); | |
| 5303 cr : S3(read); | |
| 5304 DECODE : S0; // any decoder | |
| 5305 %} | |
| 5306 | |
| 5307 // Conditional move reg-mem | |
|
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5308 pipe_class pipe_cmov_mem( eFlagsReg cr, rRegI dst, memory src) %{ |
| 0 | 5309 single_instruction; |
| 5310 dst : S4(write); | |
| 5311 src : S3(read); | |
| 5312 cr : S3(read); | |
| 5313 DECODE : S0; // any decoder | |
| 5314 MEM : S3; | |
| 5315 %} | |
| 5316 | |
| 5317 // Conditional move reg-reg long | |
| 5318 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{ | |
| 5319 single_instruction; | |
| 5320 dst : S4(write); | |
| 5321 src : S3(read); | |
| 5322 cr : S3(read); | |
| 5323 DECODE : S0(2); // any 2 decoders | |
| 5324 %} | |
| 5325 | |
| 5326 // Conditional move double reg-reg | |
|
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5327 pipe_class pipe_cmovDPR_reg( eFlagsReg cr, regDPR1 dst, regDPR src) %{ |
| 0 | 5328 single_instruction; |
| 5329 dst : S4(write); | |
| 5330 src : S3(read); | |
| 5331 cr : S3(read); | |
| 5332 DECODE : S0; // any decoder | |
| 5333 %} | |
| 5334 | |
| 5335 // Float reg-reg operation | |
|
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5336 pipe_class fpu_reg(regDPR dst) %{ |
| 0 | 5337 instruction_count(2); |
| 5338 dst : S3(read); | |
| 5339 DECODE : S0(2); // any 2 decoders | |
| 5340 FPU : S3; | |
| 5341 %} | |
| 5342 | |
| 5343 // Float reg-reg operation | |
|
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5344 pipe_class fpu_reg_reg(regDPR dst, regDPR src) %{ |
| 0 | 5345 instruction_count(2); |
| 5346 dst : S4(write); | |
| 5347 src : S3(read); | |
| 5348 DECODE : S0(2); // any 2 decoders | |
| 5349 FPU : S3; | |
| 5350 %} | |
| 5351 | |
| 5352 // Float reg-reg operation | |
|
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5353 pipe_class fpu_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2) %{ |
| 0 | 5354 instruction_count(3); |
| 5355 dst : S4(write); | |
| 5356 src1 : S3(read); | |
| 5357 src2 : S3(read); | |
| 5358 DECODE : S0(3); // any 3 decoders | |
| 5359 FPU : S3(2); | |
| 5360 %} | |
| 5361 | |
| 5362 // Float reg-reg operation | |
|
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5363 pipe_class fpu_reg_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2, regDPR src3) %{ |
| 0 | 5364 instruction_count(4); |
| 5365 dst : S4(write); | |
| 5366 src1 : S3(read); | |
| 5367 src2 : S3(read); | |
| 5368 src3 : S3(read); | |
| 5369 DECODE : S0(4); // any 3 decoders | |
| 5370 FPU : S3(2); | |
| 5371 %} | |
| 5372 | |
| 5373 // Float reg-reg operation | |
|
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5374 pipe_class fpu_reg_mem_reg_reg(regDPR dst, memory src1, regDPR src2, regDPR src3) %{ |
| 0 | 5375 instruction_count(4); |
| 5376 dst : S4(write); | |
| 5377 src1 : S3(read); | |
| 5378 src2 : S3(read); | |
| 5379 src3 : S3(read); | |
| 5380 DECODE : S1(3); // any 3 decoders | |
| 5381 D0 : S0; // Big decoder only | |
| 5382 FPU : S3(2); | |
| 5383 MEM : S3; | |
| 5384 %} | |
| 5385 | |
| 5386 // Float reg-mem operation | |
|
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5387 pipe_class fpu_reg_mem(regDPR dst, memory mem) %{ |
| 0 | 5388 instruction_count(2); |
| 5389 dst : S5(write); | |
| 5390 mem : S3(read); | |
| 5391 D0 : S0; // big decoder only | |
| 5392 DECODE : S1; // any decoder for FPU POP | |
| 5393 FPU : S4; | |
| 5394 MEM : S3; // any mem | |
| 5395 %} | |
| 5396 | |
| 5397 // Float reg-mem operation | |
|
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5398 pipe_class fpu_reg_reg_mem(regDPR dst, regDPR src1, memory mem) %{ |
| 0 | 5399 instruction_count(3); |
| 5400 dst : S5(write); | |
| 5401 src1 : S3(read); | |
| 5402 mem : S3(read); | |
| 5403 D0 : S0; // big decoder only | |
| 5404 DECODE : S1(2); // any decoder for FPU POP | |
| 5405 FPU : S4; | |
| 5406 MEM : S3; // any mem | |
| 5407 %} | |
| 5408 | |
| 5409 // Float mem-reg operation | |
|
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5410 pipe_class fpu_mem_reg(memory mem, regDPR src) %{ |
| 0 | 5411 instruction_count(2); |
| 5412 src : S5(read); | |
| 5413 mem : S3(read); | |
| 5414 DECODE : S0; // any decoder for FPU PUSH | |
| 5415 D0 : S1; // big decoder only | |
| 5416 FPU : S4; | |
| 5417 MEM : S3; // any mem | |
| 5418 %} | |
| 5419 | |
|
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5420 pipe_class fpu_mem_reg_reg(memory mem, regDPR src1, regDPR src2) %{ |
| 0 | 5421 instruction_count(3); |
| 5422 src1 : S3(read); | |
| 5423 src2 : S3(read); | |
| 5424 mem : S3(read); | |
| 5425 DECODE : S0(2); // any decoder for FPU PUSH | |
| 5426 D0 : S1; // big decoder only | |
| 5427 FPU : S4; | |
| 5428 MEM : S3; // any mem | |
| 5429 %} | |
| 5430 | |
|
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5431 pipe_class fpu_mem_reg_mem(memory mem, regDPR src1, memory src2) %{ |
| 0 | 5432 instruction_count(3); |
| 5433 src1 : S3(read); | |
| 5434 src2 : S3(read); | |
| 5435 mem : S4(read); | |
| 5436 DECODE : S0; // any decoder for FPU PUSH | |
| 5437 D0 : S0(2); // big decoder only | |
| 5438 FPU : S4; | |
| 5439 MEM : S3(2); // any mem | |
| 5440 %} | |
| 5441 | |
| 5442 pipe_class fpu_mem_mem(memory dst, memory src1) %{ | |
| 5443 instruction_count(2); | |
| 5444 src1 : S3(read); | |
| 5445 dst : S4(read); | |
| 5446 D0 : S0(2); // big decoder only | |
| 5447 MEM : S3(2); // any mem | |
| 5448 %} | |
| 5449 | |
| 5450 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{ | |
| 5451 instruction_count(3); | |
| 5452 src1 : S3(read); | |
| 5453 src2 : S3(read); | |
| 5454 dst : S4(read); | |
| 5455 D0 : S0(3); // big decoder only | |
| 5456 FPU : S4; | |
| 5457 MEM : S3(3); // any mem | |
| 5458 %} | |
| 5459 | |
|
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5460 pipe_class fpu_mem_reg_con(memory mem, regDPR src1) %{ |
| 0 | 5461 instruction_count(3); |
| 5462 src1 : S4(read); | |
| 5463 mem : S4(read); | |
| 5464 DECODE : S0; // any decoder for FPU PUSH | |
| 5465 D0 : S0(2); // big decoder only | |
| 5466 FPU : S4; | |
| 5467 MEM : S3(2); // any mem | |
| 5468 %} | |
| 5469 | |
| 5470 // Float load constant | |
|
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5471 pipe_class fpu_reg_con(regDPR dst) %{ |
| 0 | 5472 instruction_count(2); |
| 5473 dst : S5(write); | |
| 5474 D0 : S0; // big decoder only for the load | |
| 5475 DECODE : S1; // any decoder for FPU POP | |
| 5476 FPU : S4; | |
| 5477 MEM : S3; // any mem | |
| 5478 %} | |
| 5479 | |
| 5480 // Float load constant | |
|
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5481 pipe_class fpu_reg_reg_con(regDPR dst, regDPR src) %{ |
| 0 | 5482 instruction_count(3); |
| 5483 dst : S5(write); | |
| 5484 src : S3(read); | |
| 5485 D0 : S0; // big decoder only for the load | |
| 5486 DECODE : S1(2); // any decoder for FPU POP | |
| 5487 FPU : S4; | |
| 5488 MEM : S3; // any mem | |
| 5489 %} | |
| 5490 | |
| 5491 // UnConditional branch | |
| 5492 pipe_class pipe_jmp( label labl ) %{ | |
| 5493 single_instruction; | |
| 5494 BR : S3; | |
| 5495 %} | |
| 5496 | |
| 5497 // Conditional branch | |
| 5498 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{ | |
| 5499 single_instruction; | |
| 5500 cr : S1(read); | |
| 5501 BR : S3; | |
| 5502 %} | |
| 5503 | |
| 5504 // Allocation idiom | |
| 5505 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{ | |
| 5506 instruction_count(1); force_serialization; | |
| 5507 fixed_latency(6); | |
| 5508 heap_ptr : S3(read); | |
| 5509 DECODE : S0(3); | |
| 5510 D0 : S2; | |
| 5511 MEM : S3; | |
| 5512 ALU : S3(2); | |
| 5513 dst : S5(write); | |
| 5514 BR : S5; | |
| 5515 %} | |
| 5516 | |
| 5517 // Generic big/slow expanded idiom | |
| 5518 pipe_class pipe_slow( ) %{ | |
| 5519 instruction_count(10); multiple_bundles; force_serialization; | |
| 5520 fixed_latency(100); | |
| 5521 D0 : S0(2); | |
| 5522 MEM : S3(2); | |
| 5523 %} | |
| 5524 | |
| 5525 // The real do-nothing guy | |
| 5526 pipe_class empty( ) %{ | |
| 5527 instruction_count(0); | |
| 5528 %} | |
| 5529 | |
| 5530 // Define the class for the Nop node | |
| 5531 define %{ | |
| 5532 MachNop = empty; | |
| 5533 %} | |
| 5534 | |
| 5535 %} | |
| 5536 | |
| 5537 //----------INSTRUCTIONS------------------------------------------------------- | |
| 5538 // | |
| 5539 // match -- States which machine-independent subtree may be replaced | |
| 5540 // by this instruction. | |
| 5541 // ins_cost -- The estimated cost of this instruction is used by instruction | |
| 5542 // selection to identify a minimum cost tree of machine | |
| 5543 // instructions that matches a tree of machine-independent | |
| 5544 // instructions. | |
| 5545 // format -- A string providing the disassembly for this instruction. | |
| 5546 // The value of an instruction's operand may be inserted | |
| 5547 // by referring to it with a '$' prefix. | |
| 5548 // opcode -- Three instruction opcodes may be provided. These are referred | |
| 5549 // to within an encode class as $primary, $secondary, and $tertiary | |
| 5550 // respectively. The primary opcode is commonly used to | |
| 5551 // indicate the type of machine instruction, while secondary | |
| 5552 // and tertiary are often used for prefix options or addressing | |
| 5553 // modes. | |
| 5554 // ins_encode -- A list of encode classes with parameters. The encode class | |
| 5555 // name must have been defined in an 'enc_class' specification | |
| 5556 // in the encode section of the architecture description. | |
| 5557 | |
| 5558 //----------BSWAP-Instruction-------------------------------------------------- | |
|
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5559 instruct bytes_reverse_int(rRegI dst) %{ |
| 0 | 5560 match(Set dst (ReverseBytesI dst)); |
| 5561 | |
| 5562 format %{ "BSWAP $dst" %} | |
| 5563 opcode(0x0F, 0xC8); | |
| 5564 ins_encode( OpcP, OpcSReg(dst) ); | |
| 5565 ins_pipe( ialu_reg ); | |
| 5566 %} | |
| 5567 | |
| 5568 instruct bytes_reverse_long(eRegL dst) %{ | |
| 5569 match(Set dst (ReverseBytesL dst)); | |
| 5570 | |
| 5571 format %{ "BSWAP $dst.lo\n\t" | |
| 5572 "BSWAP $dst.hi\n\t" | |
| 5573 "XCHG $dst.lo $dst.hi" %} | |
| 5574 | |
| 5575 ins_cost(125); | |
| 5576 ins_encode( bswap_long_bytes(dst) ); | |
| 5577 ins_pipe( ialu_reg_reg); | |
| 5578 %} | |
| 5579 | |
|
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diff
changeset
|
5580 instruct bytes_reverse_unsigned_short(rRegI dst, eFlagsReg cr) %{ |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5581 match(Set dst (ReverseBytesUS dst)); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
5582 effect(KILL cr); |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5583 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5584 format %{ "BSWAP $dst\n\t" |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5585 "SHR $dst,16\n\t" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5586 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5587 __ bswapl($dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5588 __ shrl($dst$$Register, 16); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5589 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5590 ins_pipe( ialu_reg ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5591 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5592 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5593 instruct bytes_reverse_short(rRegI dst, eFlagsReg cr) %{ |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5594 match(Set dst (ReverseBytesS dst)); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
5595 effect(KILL cr); |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5596 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5597 format %{ "BSWAP $dst\n\t" |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5598 "SAR $dst,16\n\t" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5599 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5600 __ bswapl($dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5601 __ sarl($dst$$Register, 16); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5602 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5603 ins_pipe( ialu_reg ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5604 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5605 |
| 0 | 5606 |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5607 //---------- Zeros Count Instructions ------------------------------------------ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5608 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5609 instruct countLeadingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5610 predicate(UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5611 match(Set dst (CountLeadingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5612 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5613 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5614 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5615 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5616 __ lzcntl($dst$$Register, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5617 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5618 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5619 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5620 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5621 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, eFlagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5622 predicate(!UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5623 match(Set dst (CountLeadingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5624 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5625 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5626 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5627 "JNZ skip\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5628 "MOV $dst, -1\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5629 "skip:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5630 "NEG $dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5631 "ADD $dst, 31" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5632 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5633 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5634 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5635 Label skip; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5636 __ bsrl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5637 __ jccb(Assembler::notZero, skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5638 __ movl(Rdst, -1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5639 __ bind(skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5640 __ negl(Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5641 __ addl(Rdst, BitsPerInt - 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5642 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5643 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5644 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5645 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5646 instruct countLeadingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5647 predicate(UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5648 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5649 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5650 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5651 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5652 "JNC done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5653 "LZCNT $dst, $src.lo\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5654 "ADD $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5655 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5656 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5657 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5658 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5659 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5660 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5661 __ jccb(Assembler::carryClear, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5662 __ lzcntl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5663 __ addl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5664 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5665 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5666 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5667 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5668 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5669 instruct countLeadingZerosL_bsr(rRegI dst, eRegL src, eFlagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5670 predicate(!UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5671 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5672 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5673 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5674 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5675 "JZ msw_is_zero\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5676 "ADD $dst, 32\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5677 "JMP not_zero\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5678 "msw_is_zero:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5679 "BSR $dst, $src.lo\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5680 "JNZ not_zero\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5681 "MOV $dst, -1\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5682 "not_zero:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5683 "NEG $dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5684 "ADD $dst, 63\n" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5685 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5686 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5687 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5688 Label msw_is_zero; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5689 Label not_zero; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5690 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5691 __ jccb(Assembler::zero, msw_is_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5692 __ addl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5693 __ jmpb(not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5694 __ bind(msw_is_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5695 __ bsrl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5696 __ jccb(Assembler::notZero, not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5697 __ movl(Rdst, -1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5698 __ bind(not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5699 __ negl(Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5700 __ addl(Rdst, BitsPerLong - 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5701 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5702 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5703 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5704 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5705 instruct countTrailingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5706 match(Set dst (CountTrailingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5707 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5708 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5709 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5710 "JNZ done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5711 "MOV $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5712 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5713 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5714 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5715 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5716 __ bsfl(Rdst, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5717 __ jccb(Assembler::notZero, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5718 __ movl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5719 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5720 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5721 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5722 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5723 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5724 instruct countTrailingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5725 match(Set dst (CountTrailingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5726 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5727 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5728 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5729 "JNZ done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5730 "BSF $dst, $src.hi\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5731 "JNZ msw_not_zero\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5732 "MOV $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5733 "msw_not_zero:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5734 "ADD $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5735 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5736 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5737 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5738 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5739 Label msw_not_zero; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5740 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5741 __ bsfl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5742 __ jccb(Assembler::notZero, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5743 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5744 __ jccb(Assembler::notZero, msw_not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5745 __ movl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5746 __ bind(msw_not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5747 __ addl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5748 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5749 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5750 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5751 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5752 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5753 |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5754 //---------- Population Count Instructions ------------------------------------- |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5755 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5756 instruct popCountI(rRegI dst, rRegI src, eFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5757 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5758 match(Set dst (PopCountI src)); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
5759 effect(KILL cr); |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5760 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5761 format %{ "POPCNT $dst, $src" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5762 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5763 __ popcntl($dst$$Register, $src$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5764 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5765 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5766 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5767 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5768 instruct popCountI_mem(rRegI dst, memory mem, eFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5769 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5770 match(Set dst (PopCountI (LoadI mem))); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
5771 effect(KILL cr); |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5772 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5773 format %{ "POPCNT $dst, $mem" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5774 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5775 __ popcntl($dst$$Register, $mem$$Address); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5776 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5777 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5778 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5779 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5780 // Note: Long.bitCount(long) returns an int. |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5781 instruct popCountL(rRegI dst, eRegL src, rRegI tmp, eFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5782 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5783 match(Set dst (PopCountL src)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5784 effect(KILL cr, TEMP tmp, TEMP dst); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5785 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5786 format %{ "POPCNT $dst, $src.lo\n\t" |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5787 "POPCNT $tmp, $src.hi\n\t" |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5788 "ADD $dst, $tmp" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5789 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5790 __ popcntl($dst$$Register, $src$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5791 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5792 __ addl($dst$$Register, $tmp$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5793 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5794 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5795 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5796 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5797 // Note: Long.bitCount(long) returns an int. |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
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|
5798 instruct popCountL_mem(rRegI dst, memory mem, rRegI tmp, eFlagsReg cr) %{ |
|
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5799 predicate(UsePopCountInstruction); |
|
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5800 match(Set dst (PopCountL (LoadL mem))); |
|
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|
5801 effect(KILL cr, TEMP tmp, TEMP dst); |
|
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|
5802 |
|
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|
5803 format %{ "POPCNT $dst, $mem\n\t" |
|
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5804 "POPCNT $tmp, $mem+4\n\t" |
|
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5805 "ADD $dst, $tmp" %} |
|
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|
5806 ins_encode %{ |
|
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|
5807 //__ popcntl($dst$$Register, $mem$$Address$$first); |
|
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|
5808 //__ popcntl($tmp$$Register, $mem$$Address$$second); |
|
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5809 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none)); |
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5810 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none)); |
|
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5811 __ addl($dst$$Register, $tmp$$Register); |
|
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|
5812 %} |
|
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|
5813 ins_pipe(ialu_reg); |
|
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|
5814 %} |
|
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|
5815 |
|
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|
5816 |
| 0 | 5817 //----------Load/Store/Move Instructions--------------------------------------- |
| 5818 //----------Load Instructions-------------------------------------------------- | |
| 5819 // Load Byte (8bit signed) | |
| 5820 instruct loadB(xRegI dst, memory mem) %{ | |
| 5821 match(Set dst (LoadB mem)); | |
| 5822 | |
| 5823 ins_cost(125); | |
| 624 | 5824 format %{ "MOVSX8 $dst,$mem\t# byte" %} |
| 5825 | |
| 5826 ins_encode %{ | |
| 5827 __ movsbl($dst$$Register, $mem$$Address); | |
| 5828 %} | |
| 5829 | |
| 5830 ins_pipe(ialu_reg_mem); | |
| 5831 %} | |
| 5832 | |
| 5833 // Load Byte (8bit signed) into Long Register | |
| 824 | 5834 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 5835 match(Set dst (ConvI2L (LoadB mem))); |
| 824 | 5836 effect(KILL cr); |
| 624 | 5837 |
| 5838 ins_cost(375); | |
| 5839 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t" | |
| 5840 "MOV $dst.hi,$dst.lo\n\t" | |
| 5841 "SAR $dst.hi,7" %} | |
| 5842 | |
| 5843 ins_encode %{ | |
| 5844 __ movsbl($dst$$Register, $mem$$Address); | |
| 5845 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. | |
| 5846 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended. | |
| 5847 %} | |
| 5848 | |
| 5849 ins_pipe(ialu_reg_mem); | |
| 5850 %} | |
| 5851 | |
| 5852 // Load Unsigned Byte (8bit UNsigned) | |
| 5853 instruct loadUB(xRegI dst, memory mem) %{ | |
| 5854 match(Set dst (LoadUB mem)); | |
| 0 | 5855 |
| 5856 ins_cost(125); | |
| 624 | 5857 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %} |
| 5858 | |
| 5859 ins_encode %{ | |
| 5860 __ movzbl($dst$$Register, $mem$$Address); | |
| 5861 %} | |
| 5862 | |
| 5863 ins_pipe(ialu_reg_mem); | |
| 5864 %} | |
| 5865 | |
| 5866 // Load Unsigned Byte (8 bit UNsigned) into Long Register | |
| 824 | 5867 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 5868 match(Set dst (ConvI2L (LoadUB mem))); |
| 824 | 5869 effect(KILL cr); |
| 624 | 5870 |
| 5871 ins_cost(250); | |
| 5872 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t" | |
| 5873 "XOR $dst.hi,$dst.hi" %} | |
| 5874 | |
| 5875 ins_encode %{ | |
| 824 | 5876 Register Rdst = $dst$$Register; |
| 5877 __ movzbl(Rdst, $mem$$Address); | |
| 5878 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 5879 %} | |
| 5880 | |
| 5881 ins_pipe(ialu_reg_mem); | |
| 5882 %} | |
| 5883 | |
| 5884 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register | |
| 5885 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{ | |
| 5886 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); | |
| 5887 effect(KILL cr); | |
| 5888 | |
| 5889 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t" | |
| 5890 "XOR $dst.hi,$dst.hi\n\t" | |
| 5891 "AND $dst.lo,$mask" %} | |
| 5892 ins_encode %{ | |
| 5893 Register Rdst = $dst$$Register; | |
| 5894 __ movzbl(Rdst, $mem$$Address); | |
| 5895 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 5896 __ andl(Rdst, $mask$$constant); | |
| 5897 %} | |
| 624 | 5898 ins_pipe(ialu_reg_mem); |
| 5899 %} | |
| 5900 | |
| 5901 // Load Short (16bit signed) | |
|
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5902 instruct loadS(rRegI dst, memory mem) %{ |
| 624 | 5903 match(Set dst (LoadS mem)); |
| 5904 | |
| 5905 ins_cost(125); | |
| 5906 format %{ "MOVSX $dst,$mem\t# short" %} | |
| 5907 | |
| 5908 ins_encode %{ | |
| 5909 __ movswl($dst$$Register, $mem$$Address); | |
| 5910 %} | |
| 5911 | |
| 5912 ins_pipe(ialu_reg_mem); | |
| 5913 %} | |
| 5914 | |
| 785 | 5915 // Load Short (16 bit signed) to Byte (8 bit signed) |
|
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5916 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{ |
| 785 | 5917 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); |
| 5918 | |
| 5919 ins_cost(125); | |
| 5920 format %{ "MOVSX $dst, $mem\t# short -> byte" %} | |
| 5921 ins_encode %{ | |
| 5922 __ movsbl($dst$$Register, $mem$$Address); | |
| 5923 %} | |
| 5924 ins_pipe(ialu_reg_mem); | |
| 5925 %} | |
| 5926 | |
| 624 | 5927 // Load Short (16bit signed) into Long Register |
| 824 | 5928 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 5929 match(Set dst (ConvI2L (LoadS mem))); |
| 824 | 5930 effect(KILL cr); |
| 624 | 5931 |
| 5932 ins_cost(375); | |
| 5933 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t" | |
| 5934 "MOV $dst.hi,$dst.lo\n\t" | |
| 5935 "SAR $dst.hi,15" %} | |
| 5936 | |
| 5937 ins_encode %{ | |
| 5938 __ movswl($dst$$Register, $mem$$Address); | |
| 5939 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. | |
| 5940 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended. | |
| 5941 %} | |
| 5942 | |
| 5943 ins_pipe(ialu_reg_mem); | |
| 0 | 5944 %} |
| 5945 | |
|
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5946 // Load Unsigned Short/Char (16bit unsigned) |
|
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5947 instruct loadUS(rRegI dst, memory mem) %{ |
|
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5948 match(Set dst (LoadUS mem)); |
| 0 | 5949 |
| 5950 ins_cost(125); | |
| 624 | 5951 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %} |
| 5952 | |
| 5953 ins_encode %{ | |
| 5954 __ movzwl($dst$$Register, $mem$$Address); | |
| 5955 %} | |
| 5956 | |
| 5957 ins_pipe(ialu_reg_mem); | |
| 5958 %} | |
| 5959 | |
| 785 | 5960 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) |
|
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5961 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{ |
| 785 | 5962 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); |
| 5963 | |
| 5964 ins_cost(125); | |
| 5965 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %} | |
| 5966 ins_encode %{ | |
| 5967 __ movsbl($dst$$Register, $mem$$Address); | |
| 5968 %} | |
| 5969 ins_pipe(ialu_reg_mem); | |
| 5970 %} | |
| 5971 | |
| 624 | 5972 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register |
| 824 | 5973 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 5974 match(Set dst (ConvI2L (LoadUS mem))); |
| 824 | 5975 effect(KILL cr); |
| 624 | 5976 |
| 5977 ins_cost(250); | |
| 5978 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t" | |
| 5979 "XOR $dst.hi,$dst.hi" %} | |
| 5980 | |
| 5981 ins_encode %{ | |
| 5982 __ movzwl($dst$$Register, $mem$$Address); | |
| 5983 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register)); | |
| 5984 %} | |
| 5985 | |
| 5986 ins_pipe(ialu_reg_mem); | |
| 0 | 5987 %} |
| 5988 | |
| 824 | 5989 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register |
| 5990 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{ | |
| 5991 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5992 effect(KILL cr); | |
| 5993 | |
| 5994 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t" | |
| 5995 "XOR $dst.hi,$dst.hi" %} | |
| 5996 ins_encode %{ | |
| 5997 Register Rdst = $dst$$Register; | |
| 5998 __ movzbl(Rdst, $mem$$Address); | |
| 5999 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 6000 %} | |
| 6001 ins_pipe(ialu_reg_mem); | |
| 6002 %} | |
| 6003 | |
| 6004 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register | |
| 6005 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{ | |
| 6006 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 6007 effect(KILL cr); | |
| 6008 | |
| 6009 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t" | |
| 6010 "XOR $dst.hi,$dst.hi\n\t" | |
| 6011 "AND $dst.lo,$mask" %} | |
| 6012 ins_encode %{ | |
| 6013 Register Rdst = $dst$$Register; | |
| 6014 __ movzwl(Rdst, $mem$$Address); | |
| 6015 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 6016 __ andl(Rdst, $mask$$constant); | |
| 6017 %} | |
| 6018 ins_pipe(ialu_reg_mem); | |
| 6019 %} | |
| 6020 | |
| 0 | 6021 // Load Integer |
|
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6022 instruct loadI(rRegI dst, memory mem) %{ |
| 0 | 6023 match(Set dst (LoadI mem)); |
| 6024 | |
| 6025 ins_cost(125); | |
| 624 | 6026 format %{ "MOV $dst,$mem\t# int" %} |
| 6027 | |
| 6028 ins_encode %{ | |
| 6029 __ movl($dst$$Register, $mem$$Address); | |
| 6030 %} | |
| 6031 | |
| 6032 ins_pipe(ialu_reg_mem); | |
| 6033 %} | |
| 6034 | |
| 785 | 6035 // Load Integer (32 bit signed) to Byte (8 bit signed) |
|
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6036 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{ |
| 785 | 6037 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); |
| 6038 | |
| 6039 ins_cost(125); | |
| 6040 format %{ "MOVSX $dst, $mem\t# int -> byte" %} | |
| 6041 ins_encode %{ | |
| 6042 __ movsbl($dst$$Register, $mem$$Address); | |
| 6043 %} | |
| 6044 ins_pipe(ialu_reg_mem); | |
| 6045 %} | |
| 6046 | |
| 6047 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned) | |
|
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6048 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{ |
| 785 | 6049 match(Set dst (AndI (LoadI mem) mask)); |
| 6050 | |
| 6051 ins_cost(125); | |
| 6052 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %} | |
| 6053 ins_encode %{ | |
| 6054 __ movzbl($dst$$Register, $mem$$Address); | |
| 6055 %} | |
| 6056 ins_pipe(ialu_reg_mem); | |
| 6057 %} | |
| 6058 | |
| 6059 // Load Integer (32 bit signed) to Short (16 bit signed) | |
|
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|
6060 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{ |
| 785 | 6061 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); |
| 6062 | |
| 6063 ins_cost(125); | |
| 6064 format %{ "MOVSX $dst, $mem\t# int -> short" %} | |
| 6065 ins_encode %{ | |
| 6066 __ movswl($dst$$Register, $mem$$Address); | |
| 6067 %} | |
| 6068 ins_pipe(ialu_reg_mem); | |
| 6069 %} | |
| 6070 | |
| 6071 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned) | |
|
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6072 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{ |
| 785 | 6073 match(Set dst (AndI (LoadI mem) mask)); |
| 6074 | |
| 6075 ins_cost(125); | |
| 6076 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %} | |
| 6077 ins_encode %{ | |
| 6078 __ movzwl($dst$$Register, $mem$$Address); | |
| 6079 %} | |
| 6080 ins_pipe(ialu_reg_mem); | |
| 6081 %} | |
| 6082 | |
| 624 | 6083 // Load Integer into Long Register |
| 824 | 6084 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 6085 match(Set dst (ConvI2L (LoadI mem))); |
| 824 | 6086 effect(KILL cr); |
| 624 | 6087 |
| 6088 ins_cost(375); | |
| 6089 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t" | |
| 6090 "MOV $dst.hi,$dst.lo\n\t" | |
| 6091 "SAR $dst.hi,31" %} | |
| 6092 | |
| 6093 ins_encode %{ | |
| 6094 __ movl($dst$$Register, $mem$$Address); | |
| 6095 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. | |
| 6096 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); | |
| 6097 %} | |
| 6098 | |
| 6099 ins_pipe(ialu_reg_mem); | |
| 6100 %} | |
| 6101 | |
| 824 | 6102 // Load Integer with mask 0xFF into Long Register |
| 6103 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{ | |
| 6104 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 6105 effect(KILL cr); | |
| 6106 | |
| 6107 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t" | |
| 6108 "XOR $dst.hi,$dst.hi" %} | |
| 6109 ins_encode %{ | |
| 6110 Register Rdst = $dst$$Register; | |
| 6111 __ movzbl(Rdst, $mem$$Address); | |
| 6112 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 6113 %} | |
| 6114 ins_pipe(ialu_reg_mem); | |
| 6115 %} | |
| 6116 | |
| 6117 // Load Integer with mask 0xFFFF into Long Register | |
| 6118 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{ | |
| 6119 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 6120 effect(KILL cr); | |
| 6121 | |
| 6122 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t" | |
| 6123 "XOR $dst.hi,$dst.hi" %} | |
| 6124 ins_encode %{ | |
| 6125 Register Rdst = $dst$$Register; | |
| 6126 __ movzwl(Rdst, $mem$$Address); | |
| 6127 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 6128 %} | |
| 6129 ins_pipe(ialu_reg_mem); | |
| 6130 %} | |
| 6131 | |
| 6132 // Load Integer with 32-bit mask into Long Register | |
| 6133 instruct loadI2L_immI(eRegL dst, memory mem, immI mask, eFlagsReg cr) %{ | |
| 6134 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 6135 effect(KILL cr); | |
| 6136 | |
| 6137 format %{ "MOV $dst.lo,$mem\t# int & 32-bit mask -> long\n\t" | |
| 6138 "XOR $dst.hi,$dst.hi\n\t" | |
| 6139 "AND $dst.lo,$mask" %} | |
| 6140 ins_encode %{ | |
| 6141 Register Rdst = $dst$$Register; | |
| 6142 __ movl(Rdst, $mem$$Address); | |
| 6143 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 6144 __ andl(Rdst, $mask$$constant); | |
| 6145 %} | |
| 6146 ins_pipe(ialu_reg_mem); | |
| 6147 %} | |
| 6148 | |
| 624 | 6149 // Load Unsigned Integer into Long Register |
| 824 | 6150 instruct loadUI2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 6151 match(Set dst (LoadUI2L mem)); |
| 824 | 6152 effect(KILL cr); |
| 624 | 6153 |
| 6154 ins_cost(250); | |
| 6155 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t" | |
| 6156 "XOR $dst.hi,$dst.hi" %} | |
| 6157 | |
| 6158 ins_encode %{ | |
| 6159 __ movl($dst$$Register, $mem$$Address); | |
| 6160 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register)); | |
| 6161 %} | |
| 6162 | |
| 6163 ins_pipe(ialu_reg_mem); | |
| 0 | 6164 %} |
| 6165 | |
| 6166 // Load Long. Cannot clobber address while loading, so restrict address | |
| 6167 // register to ESI | |
| 6168 instruct loadL(eRegL dst, load_long_memory mem) %{ | |
| 6169 predicate(!((LoadLNode*)n)->require_atomic_access()); | |
| 6170 match(Set dst (LoadL mem)); | |
| 6171 | |
| 6172 ins_cost(250); | |
| 624 | 6173 format %{ "MOV $dst.lo,$mem\t# long\n\t" |
| 0 | 6174 "MOV $dst.hi,$mem+4" %} |
| 624 | 6175 |
| 6176 ins_encode %{ | |
|
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6177 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none); |
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6178 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none); |
| 624 | 6179 __ movl($dst$$Register, Amemlo); |
| 6180 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi); | |
| 6181 %} | |
| 6182 | |
| 6183 ins_pipe(ialu_reg_long_mem); | |
| 0 | 6184 %} |
| 6185 | |
| 6186 // Volatile Load Long. Must be atomic, so do 64-bit FILD | |
| 6187 // then store it down to the stack and reload on the int | |
| 6188 // side. | |
| 6189 instruct loadL_volatile(stackSlotL dst, memory mem) %{ | |
| 6190 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access()); | |
| 6191 match(Set dst (LoadL mem)); | |
| 6192 | |
| 6193 ins_cost(200); | |
| 6194 format %{ "FILD $mem\t# Atomic volatile long load\n\t" | |
| 6195 "FISTp $dst" %} | |
| 6196 ins_encode(enc_loadL_volatile(mem,dst)); | |
| 6197 ins_pipe( fpu_reg_mem ); | |
| 6198 %} | |
| 6199 | |
|
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6200 instruct loadLX_volatile(stackSlotL dst, memory mem, regD tmp) %{ |
| 0 | 6201 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access()); |
| 6202 match(Set dst (LoadL mem)); | |
| 6203 effect(TEMP tmp); | |
| 6204 ins_cost(180); | |
| 6205 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" | |
| 6206 "MOVSD $dst,$tmp" %} | |
| 4759 | 6207 ins_encode %{ |
| 6208 __ movdbl($tmp$$XMMRegister, $mem$$Address); | |
| 6209 __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister); | |
| 6210 %} | |
| 0 | 6211 ins_pipe( pipe_slow ); |
| 6212 %} | |
| 6213 | |
|
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6214 instruct loadLX_reg_volatile(eRegL dst, memory mem, regD tmp) %{ |
| 0 | 6215 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access()); |
| 6216 match(Set dst (LoadL mem)); | |
| 6217 effect(TEMP tmp); | |
| 6218 ins_cost(160); | |
| 6219 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" | |
| 6220 "MOVD $dst.lo,$tmp\n\t" | |
| 6221 "PSRLQ $tmp,32\n\t" | |
| 6222 "MOVD $dst.hi,$tmp" %} | |
| 4759 | 6223 ins_encode %{ |
| 6224 __ movdbl($tmp$$XMMRegister, $mem$$Address); | |
| 6225 __ movdl($dst$$Register, $tmp$$XMMRegister); | |
| 6226 __ psrlq($tmp$$XMMRegister, 32); | |
| 6227 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister); | |
| 6228 %} | |
| 0 | 6229 ins_pipe( pipe_slow ); |
| 6230 %} | |
| 6231 | |
| 6232 // Load Range | |
|
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6233 instruct loadRange(rRegI dst, memory mem) %{ |
| 0 | 6234 match(Set dst (LoadRange mem)); |
| 6235 | |
| 6236 ins_cost(125); | |
| 6237 format %{ "MOV $dst,$mem" %} | |
| 6238 opcode(0x8B); | |
| 6239 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6240 ins_pipe( ialu_reg_mem ); | |
| 6241 %} | |
| 6242 | |
| 6243 | |
| 6244 // Load Pointer | |
| 6245 instruct loadP(eRegP dst, memory mem) %{ | |
| 6246 match(Set dst (LoadP mem)); | |
| 6247 | |
| 6248 ins_cost(125); | |
| 6249 format %{ "MOV $dst,$mem" %} | |
| 6250 opcode(0x8B); | |
| 6251 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6252 ins_pipe( ialu_reg_mem ); | |
| 6253 %} | |
| 6254 | |
| 6255 // Load Klass Pointer | |
| 6256 instruct loadKlass(eRegP dst, memory mem) %{ | |
| 6257 match(Set dst (LoadKlass mem)); | |
| 6258 | |
| 6259 ins_cost(125); | |
| 6260 format %{ "MOV $dst,$mem" %} | |
| 6261 opcode(0x8B); | |
| 6262 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6263 ins_pipe( ialu_reg_mem ); | |
| 6264 %} | |
| 6265 | |
| 6266 // Load Double | |
|
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6267 instruct loadDPR(regDPR dst, memory mem) %{ |
| 0 | 6268 predicate(UseSSE<=1); |
| 6269 match(Set dst (LoadD mem)); | |
| 6270 | |
| 6271 ins_cost(150); | |
| 6272 format %{ "FLD_D ST,$mem\n\t" | |
| 6273 "FSTP $dst" %} | |
| 6274 opcode(0xDD); /* DD /0 */ | |
| 6275 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
|
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6276 Pop_Reg_DPR(dst) ); |
| 0 | 6277 ins_pipe( fpu_reg_mem ); |
| 6278 %} | |
| 6279 | |
| 6280 // Load Double to XMM | |
|
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6281 instruct loadD(regD dst, memory mem) %{ |
| 0 | 6282 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper); |
| 6283 match(Set dst (LoadD mem)); | |
| 6284 ins_cost(145); | |
| 6285 format %{ "MOVSD $dst,$mem" %} | |
| 4759 | 6286 ins_encode %{ |
| 6287 __ movdbl ($dst$$XMMRegister, $mem$$Address); | |
| 6288 %} | |
| 0 | 6289 ins_pipe( pipe_slow ); |
| 6290 %} | |
| 6291 | |
|
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6292 instruct loadD_partial(regD dst, memory mem) %{ |
| 0 | 6293 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper); |
| 6294 match(Set dst (LoadD mem)); | |
| 6295 ins_cost(145); | |
| 6296 format %{ "MOVLPD $dst,$mem" %} | |
| 4759 | 6297 ins_encode %{ |
| 6298 __ movdbl ($dst$$XMMRegister, $mem$$Address); | |
| 6299 %} | |
| 0 | 6300 ins_pipe( pipe_slow ); |
| 6301 %} | |
| 6302 | |
| 6303 // Load to XMM register (single-precision floating point) | |
| 6304 // MOVSS instruction | |
|
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6305 instruct loadF(regF dst, memory mem) %{ |
| 0 | 6306 predicate(UseSSE>=1); |
| 6307 match(Set dst (LoadF mem)); | |
| 6308 ins_cost(145); | |
| 6309 format %{ "MOVSS $dst,$mem" %} | |
| 4759 | 6310 ins_encode %{ |
| 6311 __ movflt ($dst$$XMMRegister, $mem$$Address); | |
| 6312 %} | |
| 0 | 6313 ins_pipe( pipe_slow ); |
| 6314 %} | |
| 6315 | |
| 6316 // Load Float | |
|
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6317 instruct loadFPR(regFPR dst, memory mem) %{ |
| 0 | 6318 predicate(UseSSE==0); |
| 6319 match(Set dst (LoadF mem)); | |
| 6320 | |
| 6321 ins_cost(150); | |
| 6322 format %{ "FLD_S ST,$mem\n\t" | |
| 6323 "FSTP $dst" %} | |
| 6324 opcode(0xD9); /* D9 /0 */ | |
| 6325 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
|
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6326 Pop_Reg_FPR(dst) ); |
| 0 | 6327 ins_pipe( fpu_reg_mem ); |
| 6328 %} | |
| 6329 | |
| 6330 // Load Effective Address | |
| 6331 instruct leaP8(eRegP dst, indOffset8 mem) %{ | |
| 6332 match(Set dst mem); | |
| 6333 | |
| 6334 ins_cost(110); | |
| 6335 format %{ "LEA $dst,$mem" %} | |
| 6336 opcode(0x8D); | |
| 6337 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6338 ins_pipe( ialu_reg_reg_fat ); | |
| 6339 %} | |
| 6340 | |
| 6341 instruct leaP32(eRegP dst, indOffset32 mem) %{ | |
| 6342 match(Set dst mem); | |
| 6343 | |
| 6344 ins_cost(110); | |
| 6345 format %{ "LEA $dst,$mem" %} | |
| 6346 opcode(0x8D); | |
| 6347 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6348 ins_pipe( ialu_reg_reg_fat ); | |
| 6349 %} | |
| 6350 | |
| 6351 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{ | |
| 6352 match(Set dst mem); | |
| 6353 | |
| 6354 ins_cost(110); | |
| 6355 format %{ "LEA $dst,$mem" %} | |
| 6356 opcode(0x8D); | |
| 6357 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6358 ins_pipe( ialu_reg_reg_fat ); | |
| 6359 %} | |
| 6360 | |
| 6361 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{ | |
| 6362 match(Set dst mem); | |
| 6363 | |
| 6364 ins_cost(110); | |
| 6365 format %{ "LEA $dst,$mem" %} | |
| 6366 opcode(0x8D); | |
| 6367 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6368 ins_pipe( ialu_reg_reg_fat ); | |
| 6369 %} | |
| 6370 | |
| 6371 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{ | |
| 6372 match(Set dst mem); | |
| 6373 | |
| 6374 ins_cost(110); | |
| 6375 format %{ "LEA $dst,$mem" %} | |
| 6376 opcode(0x8D); | |
| 6377 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6378 ins_pipe( ialu_reg_reg_fat ); | |
| 6379 %} | |
| 6380 | |
| 6381 // Load Constant | |
|
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6382 instruct loadConI(rRegI dst, immI src) %{ |
| 0 | 6383 match(Set dst src); |
| 6384 | |
| 6385 format %{ "MOV $dst,$src" %} | |
| 6386 ins_encode( LdImmI(dst, src) ); | |
| 6387 ins_pipe( ialu_reg_fat ); | |
| 6388 %} | |
| 6389 | |
| 6390 // Load Constant zero | |
|
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6391 instruct loadConI0(rRegI dst, immI0 src, eFlagsReg cr) %{ |
| 0 | 6392 match(Set dst src); |
| 6393 effect(KILL cr); | |
| 6394 | |
| 6395 ins_cost(50); | |
| 6396 format %{ "XOR $dst,$dst" %} | |
| 6397 opcode(0x33); /* + rd */ | |
| 6398 ins_encode( OpcP, RegReg( dst, dst ) ); | |
| 6399 ins_pipe( ialu_reg ); | |
| 6400 %} | |
| 6401 | |
| 6402 instruct loadConP(eRegP dst, immP src) %{ | |
| 6403 match(Set dst src); | |
| 6404 | |
| 6405 format %{ "MOV $dst,$src" %} | |
| 6406 opcode(0xB8); /* + rd */ | |
| 6407 ins_encode( LdImmP(dst, src) ); | |
| 6408 ins_pipe( ialu_reg_fat ); | |
| 6409 %} | |
| 6410 | |
| 6411 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 6412 match(Set dst src); | |
| 6413 effect(KILL cr); | |
| 6414 ins_cost(200); | |
| 6415 format %{ "MOV $dst.lo,$src.lo\n\t" | |
| 6416 "MOV $dst.hi,$src.hi" %} | |
| 6417 opcode(0xB8); | |
| 6418 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) ); | |
| 6419 ins_pipe( ialu_reg_long_fat ); | |
| 6420 %} | |
| 6421 | |
| 6422 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{ | |
| 6423 match(Set dst src); | |
| 6424 effect(KILL cr); | |
| 6425 ins_cost(150); | |
| 6426 format %{ "XOR $dst.lo,$dst.lo\n\t" | |
| 6427 "XOR $dst.hi,$dst.hi" %} | |
| 6428 opcode(0x33,0x33); | |
| 6429 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) ); | |
| 6430 ins_pipe( ialu_reg_long ); | |
| 6431 %} | |
| 6432 | |
|
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6433 // The instruction usage is guarded by predicate in operand immFPR(). |
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6434 instruct loadConFPR(regFPR dst, immFPR con) %{ |
| 2008 | 6435 match(Set dst con); |
| 6436 ins_cost(125); | |
| 6437 format %{ "FLD_S ST,[$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 6438 "FSTP $dst" %} | |
| 6439 ins_encode %{ | |
| 6440 __ fld_s($constantaddress($con)); | |
| 6441 __ fstp_d($dst$$reg); | |
| 6442 %} | |
| 6443 ins_pipe(fpu_reg_con); | |
| 6444 %} | |
| 6445 | |
|
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6446 // The instruction usage is guarded by predicate in operand immFPR0(). |
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6447 instruct loadConFPR0(regFPR dst, immFPR0 con) %{ |
| 2008 | 6448 match(Set dst con); |
| 0 | 6449 ins_cost(125); |
| 2008 | 6450 format %{ "FLDZ ST\n\t" |
| 0 | 6451 "FSTP $dst" %} |
| 2008 | 6452 ins_encode %{ |
| 6453 __ fldz(); | |
| 6454 __ fstp_d($dst$$reg); | |
| 6455 %} | |
| 6456 ins_pipe(fpu_reg_con); | |
| 6457 %} | |
| 6458 | |
|
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6459 // The instruction usage is guarded by predicate in operand immFPR1(). |
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6460 instruct loadConFPR1(regFPR dst, immFPR1 con) %{ |
| 2008 | 6461 match(Set dst con); |
| 6462 ins_cost(125); | |
| 6463 format %{ "FLD1 ST\n\t" | |
| 6464 "FSTP $dst" %} | |
| 6465 ins_encode %{ | |
| 6466 __ fld1(); | |
| 6467 __ fstp_d($dst$$reg); | |
| 6468 %} | |
| 6469 ins_pipe(fpu_reg_con); | |
| 0 | 6470 %} |
| 6471 | |
|
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6472 // The instruction usage is guarded by predicate in operand immF(). |
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6473 instruct loadConF(regF dst, immF con) %{ |
| 0 | 6474 match(Set dst con); |
| 6475 ins_cost(125); | |
| 2008 | 6476 format %{ "MOVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %} |
| 6477 ins_encode %{ | |
| 6478 __ movflt($dst$$XMMRegister, $constantaddress($con)); | |
| 6479 %} | |
| 6480 ins_pipe(pipe_slow); | |
| 0 | 6481 %} |
| 6482 | |
|
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6483 // The instruction usage is guarded by predicate in operand immF0(). |
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6484 instruct loadConF0(regF dst, immF0 src) %{ |
| 0 | 6485 match(Set dst src); |
| 6486 ins_cost(100); | |
| 6487 format %{ "XORPS $dst,$dst\t# float 0.0" %} | |
| 2008 | 6488 ins_encode %{ |
| 6489 __ xorps($dst$$XMMRegister, $dst$$XMMRegister); | |
| 6490 %} | |
| 6491 ins_pipe(pipe_slow); | |
| 0 | 6492 %} |
| 6493 | |
|
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6494 // The instruction usage is guarded by predicate in operand immDPR(). |
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6495 instruct loadConDPR(regDPR dst, immDPR con) %{ |
| 2008 | 6496 match(Set dst con); |
| 6497 ins_cost(125); | |
| 6498 | |
| 6499 format %{ "FLD_D ST,[$constantaddress]\t# load from constant table: double=$con\n\t" | |
| 6500 "FSTP $dst" %} | |
| 6501 ins_encode %{ | |
| 6502 __ fld_d($constantaddress($con)); | |
| 6503 __ fstp_d($dst$$reg); | |
| 6504 %} | |
| 6505 ins_pipe(fpu_reg_con); | |
| 6506 %} | |
| 6507 | |
|
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6508 // The instruction usage is guarded by predicate in operand immDPR0(). |
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6509 instruct loadConDPR0(regDPR dst, immDPR0 con) %{ |
| 2008 | 6510 match(Set dst con); |
| 0 | 6511 ins_cost(125); |
| 6512 | |
| 2008 | 6513 format %{ "FLDZ ST\n\t" |
| 0 | 6514 "FSTP $dst" %} |
| 2008 | 6515 ins_encode %{ |
| 6516 __ fldz(); | |
| 6517 __ fstp_d($dst$$reg); | |
| 6518 %} | |
| 6519 ins_pipe(fpu_reg_con); | |
| 6520 %} | |
| 6521 | |
|
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6522 // The instruction usage is guarded by predicate in operand immDPR1(). |
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6523 instruct loadConDPR1(regDPR dst, immDPR1 con) %{ |
| 2008 | 6524 match(Set dst con); |
| 6525 ins_cost(125); | |
| 6526 | |
| 6527 format %{ "FLD1 ST\n\t" | |
| 6528 "FSTP $dst" %} | |
| 6529 ins_encode %{ | |
| 6530 __ fld1(); | |
| 6531 __ fstp_d($dst$$reg); | |
| 6532 %} | |
| 6533 ins_pipe(fpu_reg_con); | |
| 0 | 6534 %} |
| 6535 | |
|
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6536 // The instruction usage is guarded by predicate in operand immD(). |
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6537 instruct loadConD(regD dst, immD con) %{ |
| 0 | 6538 match(Set dst con); |
| 6539 ins_cost(125); | |
| 2008 | 6540 format %{ "MOVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %} |
| 6541 ins_encode %{ | |
| 6542 __ movdbl($dst$$XMMRegister, $constantaddress($con)); | |
| 6543 %} | |
| 6544 ins_pipe(pipe_slow); | |
| 0 | 6545 %} |
| 6546 | |
|
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6547 // The instruction usage is guarded by predicate in operand immD0(). |
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6548 instruct loadConD0(regD dst, immD0 src) %{ |
| 0 | 6549 match(Set dst src); |
| 6550 ins_cost(100); | |
| 6551 format %{ "XORPD $dst,$dst\t# double 0.0" %} | |
| 4759 | 6552 ins_encode %{ |
| 6553 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister); | |
| 6554 %} | |
| 0 | 6555 ins_pipe( pipe_slow ); |
| 6556 %} | |
| 6557 | |
| 6558 // Load Stack Slot | |
|
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6559 instruct loadSSI(rRegI dst, stackSlotI src) %{ |
| 0 | 6560 match(Set dst src); |
| 6561 ins_cost(125); | |
| 6562 | |
| 6563 format %{ "MOV $dst,$src" %} | |
| 6564 opcode(0x8B); | |
| 6565 ins_encode( OpcP, RegMem(dst,src)); | |
| 6566 ins_pipe( ialu_reg_mem ); | |
| 6567 %} | |
| 6568 | |
| 6569 instruct loadSSL(eRegL dst, stackSlotL src) %{ | |
| 6570 match(Set dst src); | |
| 6571 | |
| 6572 ins_cost(200); | |
| 6573 format %{ "MOV $dst,$src.lo\n\t" | |
| 6574 "MOV $dst+4,$src.hi" %} | |
| 6575 opcode(0x8B, 0x8B); | |
| 6576 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) ); | |
| 6577 ins_pipe( ialu_mem_long_reg ); | |
| 6578 %} | |
| 6579 | |
| 6580 // Load Stack Slot | |
| 6581 instruct loadSSP(eRegP dst, stackSlotP src) %{ | |
| 6582 match(Set dst src); | |
| 6583 ins_cost(125); | |
| 6584 | |
| 6585 format %{ "MOV $dst,$src" %} | |
| 6586 opcode(0x8B); | |
| 6587 ins_encode( OpcP, RegMem(dst,src)); | |
| 6588 ins_pipe( ialu_reg_mem ); | |
| 6589 %} | |
| 6590 | |
| 6591 // Load Stack Slot | |
|
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6592 instruct loadSSF(regFPR dst, stackSlotF src) %{ |
| 0 | 6593 match(Set dst src); |
| 6594 ins_cost(125); | |
| 6595 | |
| 6596 format %{ "FLD_S $src\n\t" | |
| 6597 "FSTP $dst" %} | |
| 6598 opcode(0xD9); /* D9 /0, FLD m32real */ | |
| 6599 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
|
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6600 Pop_Reg_FPR(dst) ); |
| 0 | 6601 ins_pipe( fpu_reg_mem ); |
| 6602 %} | |
| 6603 | |
| 6604 // Load Stack Slot | |
|
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6605 instruct loadSSD(regDPR dst, stackSlotD src) %{ |
| 0 | 6606 match(Set dst src); |
| 6607 ins_cost(125); | |
| 6608 | |
| 6609 format %{ "FLD_D $src\n\t" | |
| 6610 "FSTP $dst" %} | |
| 6611 opcode(0xDD); /* DD /0, FLD m64real */ | |
| 6612 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
|
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6613 Pop_Reg_DPR(dst) ); |
| 0 | 6614 ins_pipe( fpu_reg_mem ); |
| 6615 %} | |
| 6616 | |
| 6617 // Prefetch instructions. | |
| 6618 // Must be safe to execute with invalid address (cannot fault). | |
| 6619 | |
| 6620 instruct prefetchr0( memory mem ) %{ | |
| 2479 | 6621 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch()); |
| 0 | 6622 match(PrefetchRead mem); |
| 6623 ins_cost(0); | |
| 6624 size(0); | |
| 6625 format %{ "PREFETCHR (non-SSE is empty encoding)" %} | |
| 6626 ins_encode(); | |
| 6627 ins_pipe(empty); | |
| 6628 %} | |
| 6629 | |
| 6630 instruct prefetchr( memory mem ) %{ | |
| 2479 | 6631 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || ReadPrefetchInstr==3); |
| 0 | 6632 match(PrefetchRead mem); |
| 6633 ins_cost(100); | |
| 6634 | |
| 6635 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %} | |
| 3854 | 6636 ins_encode %{ |
| 6637 __ prefetchr($mem$$Address); | |
| 6638 %} | |
| 0 | 6639 ins_pipe(ialu_mem); |
| 6640 %} | |
| 6641 | |
| 6642 instruct prefetchrNTA( memory mem ) %{ | |
| 6643 predicate(UseSSE>=1 && ReadPrefetchInstr==0); | |
| 6644 match(PrefetchRead mem); | |
| 6645 ins_cost(100); | |
| 6646 | |
| 6647 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %} | |
| 3854 | 6648 ins_encode %{ |
| 6649 __ prefetchnta($mem$$Address); | |
| 6650 %} | |
| 0 | 6651 ins_pipe(ialu_mem); |
| 6652 %} | |
| 6653 | |
| 6654 instruct prefetchrT0( memory mem ) %{ | |
| 6655 predicate(UseSSE>=1 && ReadPrefetchInstr==1); | |
| 6656 match(PrefetchRead mem); | |
| 6657 ins_cost(100); | |
| 6658 | |
| 6659 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %} | |
| 3854 | 6660 ins_encode %{ |
| 6661 __ prefetcht0($mem$$Address); | |
| 6662 %} | |
| 0 | 6663 ins_pipe(ialu_mem); |
| 6664 %} | |
| 6665 | |
| 6666 instruct prefetchrT2( memory mem ) %{ | |
| 6667 predicate(UseSSE>=1 && ReadPrefetchInstr==2); | |
| 6668 match(PrefetchRead mem); | |
| 6669 ins_cost(100); | |
| 6670 | |
| 6671 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %} | |
| 3854 | 6672 ins_encode %{ |
| 6673 __ prefetcht2($mem$$Address); | |
| 6674 %} | |
| 0 | 6675 ins_pipe(ialu_mem); |
| 6676 %} | |
| 6677 | |
| 6678 instruct prefetchw0( memory mem ) %{ | |
| 2479 | 6679 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch()); |
| 0 | 6680 match(PrefetchWrite mem); |
| 6681 ins_cost(0); | |
| 6682 size(0); | |
| 6683 format %{ "Prefetch (non-SSE is empty encoding)" %} | |
| 6684 ins_encode(); | |
| 6685 ins_pipe(empty); | |
| 6686 %} | |
| 6687 | |
| 6688 instruct prefetchw( memory mem ) %{ | |
| 3854 | 6689 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch()); |
| 0 | 6690 match( PrefetchWrite mem ); |
| 6691 ins_cost(100); | |
| 6692 | |
| 6693 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %} | |
| 3854 | 6694 ins_encode %{ |
| 6695 __ prefetchw($mem$$Address); | |
| 6696 %} | |
| 0 | 6697 ins_pipe(ialu_mem); |
| 6698 %} | |
| 6699 | |
| 6700 instruct prefetchwNTA( memory mem ) %{ | |
| 3854 | 6701 predicate(UseSSE>=1); |
| 0 | 6702 match(PrefetchWrite mem); |
| 6703 ins_cost(100); | |
| 6704 | |
| 6705 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %} | |
| 3854 | 6706 ins_encode %{ |
| 6707 __ prefetchnta($mem$$Address); | |
| 6708 %} | |
| 0 | 6709 ins_pipe(ialu_mem); |
| 6710 %} | |
| 6711 | |
| 3854 | 6712 // Prefetch instructions for allocation. |
| 6713 | |
| 6714 instruct prefetchAlloc0( memory mem ) %{ | |
| 6715 predicate(UseSSE==0 && AllocatePrefetchInstr!=3); | |
| 6716 match(PrefetchAllocation mem); | |
| 6717 ins_cost(0); | |
| 6718 size(0); | |
| 6719 format %{ "Prefetch allocation (non-SSE is empty encoding)" %} | |
| 6720 ins_encode(); | |
| 6721 ins_pipe(empty); | |
| 6722 %} | |
| 6723 | |
| 6724 instruct prefetchAlloc( memory mem ) %{ | |
| 6725 predicate(AllocatePrefetchInstr==3); | |
| 6726 match( PrefetchAllocation mem ); | |
| 0 | 6727 ins_cost(100); |
| 6728 | |
| 3854 | 6729 format %{ "PREFETCHW $mem\t! Prefetch allocation into L1 cache and mark modified" %} |
| 6730 ins_encode %{ | |
| 6731 __ prefetchw($mem$$Address); | |
| 6732 %} | |
| 6733 ins_pipe(ialu_mem); | |
| 6734 %} | |
| 6735 | |
| 6736 instruct prefetchAllocNTA( memory mem ) %{ | |
| 6737 predicate(UseSSE>=1 && AllocatePrefetchInstr==0); | |
| 6738 match(PrefetchAllocation mem); | |
| 6739 ins_cost(100); | |
| 6740 | |
| 6741 format %{ "PREFETCHNTA $mem\t! Prefetch allocation into non-temporal cache for write" %} | |
| 6742 ins_encode %{ | |
| 6743 __ prefetchnta($mem$$Address); | |
| 6744 %} | |
| 0 | 6745 ins_pipe(ialu_mem); |
| 6746 %} | |
| 6747 | |
| 3854 | 6748 instruct prefetchAllocT0( memory mem ) %{ |
| 6749 predicate(UseSSE>=1 && AllocatePrefetchInstr==1); | |
| 6750 match(PrefetchAllocation mem); | |
| 0 | 6751 ins_cost(100); |
| 6752 | |
| 3854 | 6753 format %{ "PREFETCHT0 $mem\t! Prefetch allocation into L1 and L2 caches for write" %} |
| 6754 ins_encode %{ | |
| 6755 __ prefetcht0($mem$$Address); | |
| 6756 %} | |
| 6757 ins_pipe(ialu_mem); | |
| 6758 %} | |
| 6759 | |
| 6760 instruct prefetchAllocT2( memory mem ) %{ | |
| 6761 predicate(UseSSE>=1 && AllocatePrefetchInstr==2); | |
| 6762 match(PrefetchAllocation mem); | |
| 6763 ins_cost(100); | |
| 6764 | |
| 6765 format %{ "PREFETCHT2 $mem\t! Prefetch allocation into L2 cache for write" %} | |
| 6766 ins_encode %{ | |
| 6767 __ prefetcht2($mem$$Address); | |
| 6768 %} | |
| 0 | 6769 ins_pipe(ialu_mem); |
| 6770 %} | |
| 6771 | |
| 6772 //----------Store Instructions------------------------------------------------- | |
| 6773 | |
| 6774 // Store Byte | |
| 6775 instruct storeB(memory mem, xRegI src) %{ | |
| 6776 match(Set mem (StoreB mem src)); | |
| 6777 | |
| 6778 ins_cost(125); | |
| 6779 format %{ "MOV8 $mem,$src" %} | |
| 6780 opcode(0x88); | |
| 6781 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 6782 ins_pipe( ialu_mem_reg ); | |
| 6783 %} | |
| 6784 | |
| 6785 // Store Char/Short | |
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6786 instruct storeC(memory mem, rRegI src) %{ |
| 0 | 6787 match(Set mem (StoreC mem src)); |
| 6788 | |
| 6789 ins_cost(125); | |
| 6790 format %{ "MOV16 $mem,$src" %} | |
| 6791 opcode(0x89, 0x66); | |
| 6792 ins_encode( OpcS, OpcP, RegMem( src, mem ) ); | |
| 6793 ins_pipe( ialu_mem_reg ); | |
| 6794 %} | |
| 6795 | |
| 6796 // Store Integer | |
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6797 instruct storeI(memory mem, rRegI src) %{ |
| 0 | 6798 match(Set mem (StoreI mem src)); |
| 6799 | |
| 6800 ins_cost(125); | |
| 6801 format %{ "MOV $mem,$src" %} | |
| 6802 opcode(0x89); | |
| 6803 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 6804 ins_pipe( ialu_mem_reg ); | |
| 6805 %} | |
| 6806 | |
| 6807 // Store Long | |
| 6808 instruct storeL(long_memory mem, eRegL src) %{ | |
| 6809 predicate(!((StoreLNode*)n)->require_atomic_access()); | |
| 6810 match(Set mem (StoreL mem src)); | |
| 6811 | |
| 6812 ins_cost(200); | |
| 6813 format %{ "MOV $mem,$src.lo\n\t" | |
| 6814 "MOV $mem+4,$src.hi" %} | |
| 6815 opcode(0x89, 0x89); | |
| 6816 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) ); | |
| 6817 ins_pipe( ialu_mem_long_reg ); | |
| 6818 %} | |
| 6819 | |
| 824 | 6820 // Store Long to Integer |
| 6821 instruct storeL2I(memory mem, eRegL src) %{ | |
| 6822 match(Set mem (StoreI mem (ConvL2I src))); | |
| 6823 | |
| 6824 format %{ "MOV $mem,$src.lo\t# long -> int" %} | |
| 6825 ins_encode %{ | |
| 6826 __ movl($mem$$Address, $src$$Register); | |
| 6827 %} | |
| 6828 ins_pipe(ialu_mem_reg); | |
| 6829 %} | |
| 6830 | |
| 0 | 6831 // Volatile Store Long. Must be atomic, so move it into |
| 6832 // the FP TOS and then do a 64-bit FIST. Has to probe the | |
| 6833 // target address before the store (for null-ptr checks) | |
| 6834 // so the memory operand is used twice in the encoding. | |
| 6835 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{ | |
| 6836 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access()); | |
| 6837 match(Set mem (StoreL mem src)); | |
| 6838 effect( KILL cr ); | |
| 6839 ins_cost(400); | |
| 6840 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" | |
| 6841 "FILD $src\n\t" | |
| 6842 "FISTp $mem\t # 64-bit atomic volatile long store" %} | |
| 6843 opcode(0x3B); | |
| 6844 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src)); | |
| 6845 ins_pipe( fpu_reg_mem ); | |
| 6846 %} | |
| 6847 | |
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6848 instruct storeLX_volatile(memory mem, stackSlotL src, regD tmp, eFlagsReg cr) %{ |
| 0 | 6849 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access()); |
| 6850 match(Set mem (StoreL mem src)); | |
| 6851 effect( TEMP tmp, KILL cr ); | |
| 6852 ins_cost(380); | |
| 6853 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" | |
| 6854 "MOVSD $tmp,$src\n\t" | |
| 6855 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %} | |
| 4759 | 6856 ins_encode %{ |
| 6857 __ cmpl(rax, $mem$$Address); | |
| 6858 __ movdbl($tmp$$XMMRegister, Address(rsp, $src$$disp)); | |
| 6859 __ movdbl($mem$$Address, $tmp$$XMMRegister); | |
| 6860 %} | |
| 0 | 6861 ins_pipe( pipe_slow ); |
| 6862 %} | |
| 6863 | |
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6864 instruct storeLX_reg_volatile(memory mem, eRegL src, regD tmp2, regD tmp, eFlagsReg cr) %{ |
| 0 | 6865 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access()); |
| 6866 match(Set mem (StoreL mem src)); | |
| 6867 effect( TEMP tmp2 , TEMP tmp, KILL cr ); | |
| 6868 ins_cost(360); | |
| 6869 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" | |
| 6870 "MOVD $tmp,$src.lo\n\t" | |
| 6871 "MOVD $tmp2,$src.hi\n\t" | |
| 6872 "PUNPCKLDQ $tmp,$tmp2\n\t" | |
| 6873 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %} | |
| 4759 | 6874 ins_encode %{ |
| 6875 __ cmpl(rax, $mem$$Address); | |
| 6876 __ movdl($tmp$$XMMRegister, $src$$Register); | |
| 6877 __ movdl($tmp2$$XMMRegister, HIGH_FROM_LOW($src$$Register)); | |
| 6878 __ punpckldq($tmp$$XMMRegister, $tmp2$$XMMRegister); | |
| 6879 __ movdbl($mem$$Address, $tmp$$XMMRegister); | |
| 6880 %} | |
| 0 | 6881 ins_pipe( pipe_slow ); |
| 6882 %} | |
| 6883 | |
| 6884 // Store Pointer; for storing unknown oops and raw pointers | |
| 6885 instruct storeP(memory mem, anyRegP src) %{ | |
| 6886 match(Set mem (StoreP mem src)); | |
| 6887 | |
| 6888 ins_cost(125); | |
| 6889 format %{ "MOV $mem,$src" %} | |
| 6890 opcode(0x89); | |
| 6891 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 6892 ins_pipe( ialu_mem_reg ); | |
| 6893 %} | |
| 6894 | |
| 6895 // Store Integer Immediate | |
| 6896 instruct storeImmI(memory mem, immI src) %{ | |
| 6897 match(Set mem (StoreI mem src)); | |
| 6898 | |
| 6899 ins_cost(150); | |
| 6900 format %{ "MOV $mem,$src" %} | |
| 6901 opcode(0xC7); /* C7 /0 */ | |
| 6902 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src )); | |
| 6903 ins_pipe( ialu_mem_imm ); | |
| 6904 %} | |
| 6905 | |
| 6906 // Store Short/Char Immediate | |
| 6907 instruct storeImmI16(memory mem, immI16 src) %{ | |
| 6908 predicate(UseStoreImmI16); | |
| 6909 match(Set mem (StoreC mem src)); | |
| 6910 | |
| 6911 ins_cost(150); | |
| 6912 format %{ "MOV16 $mem,$src" %} | |
| 6913 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */ | |
| 6914 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src )); | |
| 6915 ins_pipe( ialu_mem_imm ); | |
| 6916 %} | |
| 6917 | |
| 6918 // Store Pointer Immediate; null pointers or constant oops that do not | |
| 6919 // need card-mark barriers. | |
| 6920 instruct storeImmP(memory mem, immP src) %{ | |
| 6921 match(Set mem (StoreP mem src)); | |
| 6922 | |
| 6923 ins_cost(150); | |
| 6924 format %{ "MOV $mem,$src" %} | |
| 6925 opcode(0xC7); /* C7 /0 */ | |
| 6926 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src )); | |
| 6927 ins_pipe( ialu_mem_imm ); | |
| 6928 %} | |
| 6929 | |
| 6930 // Store Byte Immediate | |
| 6931 instruct storeImmB(memory mem, immI8 src) %{ | |
| 6932 match(Set mem (StoreB mem src)); | |
| 6933 | |
| 6934 ins_cost(150); | |
| 6935 format %{ "MOV8 $mem,$src" %} | |
| 6936 opcode(0xC6); /* C6 /0 */ | |
| 6937 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src )); | |
| 6938 ins_pipe( ialu_mem_imm ); | |
| 6939 %} | |
| 6940 | |
| 6941 // Store CMS card-mark Immediate | |
| 6942 instruct storeImmCM(memory mem, immI8 src) %{ | |
| 6943 match(Set mem (StoreCM mem src)); | |
| 6944 | |
| 6945 ins_cost(150); | |
| 6946 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %} | |
| 6947 opcode(0xC6); /* C6 /0 */ | |
| 6948 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src )); | |
| 6949 ins_pipe( ialu_mem_imm ); | |
| 6950 %} | |
| 6951 | |
| 6952 // Store Double | |
|
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6953 instruct storeDPR( memory mem, regDPR1 src) %{ |
| 0 | 6954 predicate(UseSSE<=1); |
| 6955 match(Set mem (StoreD mem src)); | |
| 6956 | |
| 6957 ins_cost(100); | |
| 6958 format %{ "FST_D $mem,$src" %} | |
| 6959 opcode(0xDD); /* DD /2 */ | |
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6960 ins_encode( enc_FPR_store(mem,src) ); |
| 0 | 6961 ins_pipe( fpu_mem_reg ); |
| 6962 %} | |
| 6963 | |
| 6964 // Store double does rounding on x86 | |
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6965 instruct storeDPR_rounded( memory mem, regDPR1 src) %{ |
| 0 | 6966 predicate(UseSSE<=1); |
| 6967 match(Set mem (StoreD mem (RoundDouble src))); | |
| 6968 | |
| 6969 ins_cost(100); | |
| 6970 format %{ "FST_D $mem,$src\t# round" %} | |
| 6971 opcode(0xDD); /* DD /2 */ | |
|
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6972 ins_encode( enc_FPR_store(mem,src) ); |
| 0 | 6973 ins_pipe( fpu_mem_reg ); |
| 6974 %} | |
| 6975 | |
| 6976 // Store XMM register to memory (double-precision floating points) | |
| 6977 // MOVSD instruction | |
|
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6978 instruct storeD(memory mem, regD src) %{ |
| 0 | 6979 predicate(UseSSE>=2); |
| 6980 match(Set mem (StoreD mem src)); | |
| 6981 ins_cost(95); | |
| 6982 format %{ "MOVSD $mem,$src" %} | |
| 4759 | 6983 ins_encode %{ |
| 6984 __ movdbl($mem$$Address, $src$$XMMRegister); | |
| 6985 %} | |
| 0 | 6986 ins_pipe( pipe_slow ); |
| 6987 %} | |
| 6988 | |
| 6989 // Store XMM register to memory (single-precision floating point) | |
| 6990 // MOVSS instruction | |
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6991 instruct storeF(memory mem, regF src) %{ |
| 0 | 6992 predicate(UseSSE>=1); |
| 6993 match(Set mem (StoreF mem src)); | |
| 6994 ins_cost(95); | |
| 6995 format %{ "MOVSS $mem,$src" %} | |
| 4759 | 6996 ins_encode %{ |
| 6997 __ movflt($mem$$Address, $src$$XMMRegister); | |
| 6998 %} | |
| 0 | 6999 ins_pipe( pipe_slow ); |
| 7000 %} | |
| 7001 | |
| 7002 // Store Float | |
|
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7003 instruct storeFPR( memory mem, regFPR1 src) %{ |
| 0 | 7004 predicate(UseSSE==0); |
| 7005 match(Set mem (StoreF mem src)); | |
| 7006 | |
| 7007 ins_cost(100); | |
| 7008 format %{ "FST_S $mem,$src" %} | |
| 7009 opcode(0xD9); /* D9 /2 */ | |
|
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7010 ins_encode( enc_FPR_store(mem,src) ); |
| 0 | 7011 ins_pipe( fpu_mem_reg ); |
| 7012 %} | |
| 7013 | |
| 7014 // Store Float does rounding on x86 | |
|
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7015 instruct storeFPR_rounded( memory mem, regFPR1 src) %{ |
| 0 | 7016 predicate(UseSSE==0); |
| 7017 match(Set mem (StoreF mem (RoundFloat src))); | |
| 7018 | |
| 7019 ins_cost(100); | |
| 7020 format %{ "FST_S $mem,$src\t# round" %} | |
| 7021 opcode(0xD9); /* D9 /2 */ | |
|
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7022 ins_encode( enc_FPR_store(mem,src) ); |
| 0 | 7023 ins_pipe( fpu_mem_reg ); |
| 7024 %} | |
| 7025 | |
| 7026 // Store Float does rounding on x86 | |
|
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7027 instruct storeFPR_Drounded( memory mem, regDPR1 src) %{ |
| 0 | 7028 predicate(UseSSE<=1); |
| 7029 match(Set mem (StoreF mem (ConvD2F src))); | |
| 7030 | |
| 7031 ins_cost(100); | |
| 7032 format %{ "FST_S $mem,$src\t# D-round" %} | |
| 7033 opcode(0xD9); /* D9 /2 */ | |
|
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7034 ins_encode( enc_FPR_store(mem,src) ); |
| 0 | 7035 ins_pipe( fpu_mem_reg ); |
| 7036 %} | |
| 7037 | |
| 7038 // Store immediate Float value (it is faster than store from FPU register) | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
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4759
diff
changeset
|
7039 // The instruction usage is guarded by predicate in operand immFPR(). |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7040 instruct storeFPR_imm( memory mem, immFPR src) %{ |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7041 match(Set mem (StoreF mem src)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7042 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7043 ins_cost(50); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7044 format %{ "MOV $mem,$src\t# store float" %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7045 opcode(0xC7); /* C7 /0 */ |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7046 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32FPR_as_bits( src )); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7047 ins_pipe( ialu_mem_imm ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7048 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7049 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7050 // Store immediate Float value (it is faster than store from XMM register) |
| 0 | 7051 // The instruction usage is guarded by predicate in operand immF(). |
| 7052 instruct storeF_imm( memory mem, immF src) %{ | |
| 7053 match(Set mem (StoreF mem src)); | |
| 7054 | |
| 7055 ins_cost(50); | |
| 7056 format %{ "MOV $mem,$src\t# store float" %} | |
| 7057 opcode(0xC7); /* C7 /0 */ | |
| 7058 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src )); | |
| 7059 ins_pipe( ialu_mem_imm ); | |
| 7060 %} | |
| 7061 | |
| 7062 // Store Integer to stack slot | |
|
6179
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7119644: Increase superword's vector size up to 256 bits
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parents:
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diff
changeset
|
7063 instruct storeSSI(stackSlotI dst, rRegI src) %{ |
| 0 | 7064 match(Set dst src); |
| 7065 | |
| 7066 ins_cost(100); | |
| 7067 format %{ "MOV $dst,$src" %} | |
| 7068 opcode(0x89); | |
| 7069 ins_encode( OpcPRegSS( dst, src ) ); | |
| 7070 ins_pipe( ialu_mem_reg ); | |
| 7071 %} | |
| 7072 | |
| 7073 // Store Integer to stack slot | |
| 7074 instruct storeSSP(stackSlotP dst, eRegP src) %{ | |
| 7075 match(Set dst src); | |
| 7076 | |
| 7077 ins_cost(100); | |
| 7078 format %{ "MOV $dst,$src" %} | |
| 7079 opcode(0x89); | |
| 7080 ins_encode( OpcPRegSS( dst, src ) ); | |
| 7081 ins_pipe( ialu_mem_reg ); | |
| 7082 %} | |
| 7083 | |
| 7084 // Store Long to stack slot | |
| 7085 instruct storeSSL(stackSlotL dst, eRegL src) %{ | |
| 7086 match(Set dst src); | |
| 7087 | |
| 7088 ins_cost(200); | |
| 7089 format %{ "MOV $dst,$src.lo\n\t" | |
| 7090 "MOV $dst+4,$src.hi" %} | |
| 7091 opcode(0x89, 0x89); | |
| 7092 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) ); | |
| 7093 ins_pipe( ialu_mem_long_reg ); | |
| 7094 %} | |
| 7095 | |
| 7096 //----------MemBar Instructions----------------------------------------------- | |
| 7097 // Memory barrier flavors | |
| 7098 | |
| 7099 instruct membar_acquire() %{ | |
| 7100 match(MemBarAcquire); | |
| 7101 ins_cost(400); | |
| 7102 | |
| 7103 size(0); | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7104 format %{ "MEMBAR-acquire ! (empty encoding)" %} |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7105 ins_encode(); |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7106 ins_pipe(empty); |
| 0 | 7107 %} |
| 7108 | |
| 7109 instruct membar_acquire_lock() %{ | |
|
3849
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7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents:
3842
diff
changeset
|
7110 match(MemBarAcquireLock); |
| 0 | 7111 ins_cost(0); |
| 7112 | |
| 7113 size(0); | |
| 7114 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %} | |
| 7115 ins_encode( ); | |
| 7116 ins_pipe(empty); | |
| 7117 %} | |
| 7118 | |
| 7119 instruct membar_release() %{ | |
| 7120 match(MemBarRelease); | |
| 7121 ins_cost(400); | |
| 7122 | |
| 7123 size(0); | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7124 format %{ "MEMBAR-release ! (empty encoding)" %} |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7125 ins_encode( ); |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7126 ins_pipe(empty); |
| 0 | 7127 %} |
| 7128 | |
| 7129 instruct membar_release_lock() %{ | |
|
3849
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7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents:
3842
diff
changeset
|
7130 match(MemBarReleaseLock); |
| 0 | 7131 ins_cost(0); |
| 7132 | |
| 7133 size(0); | |
| 7134 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %} | |
| 7135 ins_encode( ); | |
| 7136 ins_pipe(empty); | |
| 7137 %} | |
| 7138 | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7139 instruct membar_volatile(eFlagsReg cr) %{ |
| 0 | 7140 match(MemBarVolatile); |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7141 effect(KILL cr); |
| 0 | 7142 ins_cost(400); |
| 7143 | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7144 format %{ |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7145 $$template |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7146 if (os::is_MP()) { |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7147 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile" |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7148 } else { |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7149 $$emit$$"MEMBAR-volatile ! (empty encoding)" |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7150 } |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7151 %} |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7152 ins_encode %{ |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7153 __ membar(Assembler::StoreLoad); |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7154 %} |
| 0 | 7155 ins_pipe(pipe_slow); |
| 7156 %} | |
| 7157 | |
| 7158 instruct unnecessary_membar_volatile() %{ | |
| 7159 match(MemBarVolatile); | |
| 7160 predicate(Matcher::post_store_load_barrier(n)); | |
| 7161 ins_cost(0); | |
| 7162 | |
| 7163 size(0); | |
| 7164 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %} | |
| 7165 ins_encode( ); | |
| 7166 ins_pipe(empty); | |
| 7167 %} | |
| 7168 | |
|
4763
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
7169 instruct membar_storestore() %{ |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
7170 match(MemBarStoreStore); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
7171 ins_cost(0); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
7172 |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
7173 size(0); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
7174 format %{ "MEMBAR-storestore (empty encoding)" %} |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
7175 ins_encode( ); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
7176 ins_pipe(empty); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
7177 %} |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
7178 |
| 0 | 7179 //----------Move Instructions-------------------------------------------------- |
| 7180 instruct castX2P(eAXRegP dst, eAXRegI src) %{ | |
| 7181 match(Set dst (CastX2P src)); | |
| 7182 format %{ "# X2P $dst, $src" %} | |
| 7183 ins_encode( /*empty encoding*/ ); | |
| 7184 ins_cost(0); | |
| 7185 ins_pipe(empty); | |
| 7186 %} | |
| 7187 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7188 instruct castP2X(rRegI dst, eRegP src ) %{ |
| 0 | 7189 match(Set dst (CastP2X src)); |
| 7190 ins_cost(50); | |
| 7191 format %{ "MOV $dst, $src\t# CastP2X" %} | |
| 7192 ins_encode( enc_Copy( dst, src) ); | |
| 7193 ins_pipe( ialu_reg_reg ); | |
| 7194 %} | |
| 7195 | |
| 7196 //----------Conditional Move--------------------------------------------------- | |
| 7197 // Conditional move | |
|
6179
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7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7198 instruct jmovI_reg(cmpOp cop, eFlagsReg cr, rRegI dst, rRegI src) %{ |
| 4047 | 7199 predicate(!VM_Version::supports_cmov() ); |
| 7200 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 7201 ins_cost(200); | |
| 7202 format %{ "J$cop,us skip\t# signed cmove\n\t" | |
| 7203 "MOV $dst,$src\n" | |
| 7204 "skip:" %} | |
| 7205 ins_encode %{ | |
| 7206 Label Lskip; | |
| 7207 // Invert sense of branch from sense of CMOV | |
| 7208 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
| 7209 __ movl($dst$$Register, $src$$Register); | |
| 7210 __ bind(Lskip); | |
| 7211 %} | |
| 7212 ins_pipe( pipe_cmov_reg ); | |
| 7213 %} | |
| 7214 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7215 instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src) %{ |
| 4047 | 7216 predicate(!VM_Version::supports_cmov() ); |
| 7217 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 7218 ins_cost(200); | |
| 7219 format %{ "J$cop,us skip\t# unsigned cmove\n\t" | |
| 7220 "MOV $dst,$src\n" | |
| 7221 "skip:" %} | |
| 7222 ins_encode %{ | |
| 7223 Label Lskip; | |
| 7224 // Invert sense of branch from sense of CMOV | |
| 7225 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
| 7226 __ movl($dst$$Register, $src$$Register); | |
| 7227 __ bind(Lskip); | |
| 7228 %} | |
| 7229 ins_pipe( pipe_cmov_reg ); | |
| 7230 %} | |
| 7231 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7232 instruct cmovI_reg(rRegI dst, rRegI src, eFlagsReg cr, cmpOp cop ) %{ |
| 0 | 7233 predicate(VM_Version::supports_cmov() ); |
| 7234 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 7235 ins_cost(200); | |
| 7236 format %{ "CMOV$cop $dst,$src" %} | |
| 7237 opcode(0x0F,0x40); | |
| 7238 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 7239 ins_pipe( pipe_cmov_reg ); | |
| 7240 %} | |
| 7241 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7242 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src ) %{ |
| 0 | 7243 predicate(VM_Version::supports_cmov() ); |
| 7244 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 7245 ins_cost(200); | |
| 7246 format %{ "CMOV$cop $dst,$src" %} | |
| 7247 opcode(0x0F,0x40); | |
| 7248 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 7249 ins_pipe( pipe_cmov_reg ); | |
| 7250 %} | |
| 7251 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7252 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, rRegI src ) %{ |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7253 predicate(VM_Version::supports_cmov() ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7254 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7255 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7256 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7257 cmovI_regU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7258 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7259 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7260 |
| 0 | 7261 // Conditional move |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7262 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, rRegI dst, memory src) %{ |
| 0 | 7263 predicate(VM_Version::supports_cmov() ); |
| 7264 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); | |
| 7265 ins_cost(250); | |
| 7266 format %{ "CMOV$cop $dst,$src" %} | |
| 7267 opcode(0x0F,0x40); | |
| 7268 ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 7269 ins_pipe( pipe_cmov_mem ); | |
| 7270 %} | |
| 7271 | |
| 7272 // Conditional move | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7273 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, rRegI dst, memory src) %{ |
| 0 | 7274 predicate(VM_Version::supports_cmov() ); |
| 7275 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); | |
| 7276 ins_cost(250); | |
| 7277 format %{ "CMOV$cop $dst,$src" %} | |
| 7278 opcode(0x0F,0x40); | |
| 7279 ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 7280 ins_pipe( pipe_cmov_mem ); | |
| 7281 %} | |
| 7282 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7283 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, memory src) %{ |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7284 predicate(VM_Version::supports_cmov() ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7285 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7286 ins_cost(250); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7287 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7288 cmovI_memU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7289 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7290 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7291 |
| 0 | 7292 // Conditional move |
| 7293 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{ | |
| 7294 predicate(VM_Version::supports_cmov() ); | |
| 7295 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 7296 ins_cost(200); | |
| 7297 format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 7298 opcode(0x0F,0x40); | |
| 7299 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 7300 ins_pipe( pipe_cmov_reg ); | |
| 7301 %} | |
| 7302 | |
| 7303 // Conditional move (non-P6 version) | |
| 7304 // Note: a CMoveP is generated for stubs and native wrappers | |
| 7305 // regardless of whether we are on a P6, so we | |
| 7306 // emulate a cmov here | |
| 7307 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{ | |
| 7308 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 7309 ins_cost(300); | |
| 7310 format %{ "Jn$cop skip\n\t" | |
| 7311 "MOV $dst,$src\t# pointer\n" | |
| 7312 "skip:" %} | |
| 7313 opcode(0x8b); | |
| 7314 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src)); | |
| 7315 ins_pipe( pipe_cmov_reg ); | |
| 7316 %} | |
| 7317 | |
| 7318 // Conditional move | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
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changeset
|
7319 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{ |
| 0 | 7320 predicate(VM_Version::supports_cmov() ); |
| 7321 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 7322 ins_cost(200); | |
| 7323 format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 7324 opcode(0x0F,0x40); | |
| 7325 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 7326 ins_pipe( pipe_cmov_reg ); | |
| 7327 %} | |
| 7328 | |
|
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|
7329 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{ |
|
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diff
changeset
|
7330 predicate(VM_Version::supports_cmov() ); |
|
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|
7331 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); |
|
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|
7332 ins_cost(200); |
|
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diff
changeset
|
7333 expand %{ |
|
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diff
changeset
|
7334 cmovP_regU(cop, cr, dst, src); |
|
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diff
changeset
|
7335 %} |
|
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diff
changeset
|
7336 %} |
|
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diff
changeset
|
7337 |
| 0 | 7338 // DISABLED: Requires the ADLC to emit a bottom_type call that |
| 7339 // correctly meets the two pointer arguments; one is an incoming | |
| 7340 // register but the other is a memory operand. ALSO appears to | |
| 7341 // be buggy with implicit null checks. | |
| 7342 // | |
| 7343 //// Conditional move | |
| 7344 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{ | |
| 7345 // predicate(VM_Version::supports_cmov() ); | |
| 7346 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 7347 // ins_cost(250); | |
| 7348 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 7349 // opcode(0x0F,0x40); | |
| 7350 // ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 7351 // ins_pipe( pipe_cmov_mem ); | |
| 7352 //%} | |
| 7353 // | |
| 7354 //// Conditional move | |
| 7355 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{ | |
| 7356 // predicate(VM_Version::supports_cmov() ); | |
| 7357 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 7358 // ins_cost(250); | |
| 7359 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 7360 // opcode(0x0F,0x40); | |
| 7361 // ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 7362 // ins_pipe( pipe_cmov_mem ); | |
| 7363 //%} | |
| 7364 | |
| 7365 // Conditional move | |
|
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|
7366 instruct fcmovDPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regDPR src) %{ |
| 0 | 7367 predicate(UseSSE<=1); |
| 7368 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 7369 ins_cost(200); | |
| 7370 format %{ "FCMOV$cop $dst,$src\t# double" %} | |
| 7371 opcode(0xDA); | |
|
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|
7372 ins_encode( enc_cmov_dpr(cop,src) ); |
|
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|
7373 ins_pipe( pipe_cmovDPR_reg ); |
| 0 | 7374 %} |
| 7375 | |
| 7376 // Conditional move | |
|
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|
7377 instruct fcmovFPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regFPR src) %{ |
| 0 | 7378 predicate(UseSSE==0); |
| 7379 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 7380 ins_cost(200); | |
| 7381 format %{ "FCMOV$cop $dst,$src\t# float" %} | |
| 7382 opcode(0xDA); | |
|
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changeset
|
7383 ins_encode( enc_cmov_dpr(cop,src) ); |
|
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changeset
|
7384 ins_pipe( pipe_cmovDPR_reg ); |
| 0 | 7385 %} |
| 7386 | |
| 7387 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned. | |
|
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|
7388 instruct fcmovDPR_regS(cmpOp cop, eFlagsReg cr, regDPR dst, regDPR src) %{ |
| 0 | 7389 predicate(UseSSE<=1); |
| 7390 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 7391 ins_cost(200); | |
| 7392 format %{ "Jn$cop skip\n\t" | |
| 7393 "MOV $dst,$src\t# double\n" | |
| 7394 "skip:" %} | |
| 7395 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */ | |
|
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changeset
|
7396 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_DPR(src), OpcP, RegOpc(dst) ); |
|
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diff
changeset
|
7397 ins_pipe( pipe_cmovDPR_reg ); |
| 0 | 7398 %} |
| 7399 | |
| 7400 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned. | |
|
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|
7401 instruct fcmovFPR_regS(cmpOp cop, eFlagsReg cr, regFPR dst, regFPR src) %{ |
| 0 | 7402 predicate(UseSSE==0); |
| 7403 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 7404 ins_cost(200); | |
| 7405 format %{ "Jn$cop skip\n\t" | |
| 7406 "MOV $dst,$src\t# float\n" | |
| 7407 "skip:" %} | |
| 7408 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */ | |
|
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diff
changeset
|
7409 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_FPR(src), OpcP, RegOpc(dst) ); |
|
65149e74c706
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diff
changeset
|
7410 ins_pipe( pipe_cmovDPR_reg ); |
| 0 | 7411 %} |
| 7412 | |
| 7413 // No CMOVE with SSE/SSE2 | |
|
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changeset
|
7414 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{ |
| 0 | 7415 predicate (UseSSE>=1); |
| 7416 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 7417 ins_cost(200); | |
| 7418 format %{ "Jn$cop skip\n\t" | |
| 7419 "MOVSS $dst,$src\t# float\n" | |
| 7420 "skip:" %} | |
| 7421 ins_encode %{ | |
| 7422 Label skip; | |
| 7423 // Invert sense of branch from sense of CMOV | |
| 7424 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 7425 __ movflt($dst$$XMMRegister, $src$$XMMRegister); | |
| 7426 __ bind(skip); | |
| 7427 %} | |
| 7428 ins_pipe( pipe_slow ); | |
| 7429 %} | |
| 7430 | |
| 7431 // No CMOVE with SSE/SSE2 | |
|
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changeset
|
7432 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{ |
| 0 | 7433 predicate (UseSSE>=2); |
| 7434 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 7435 ins_cost(200); | |
| 7436 format %{ "Jn$cop skip\n\t" | |
| 7437 "MOVSD $dst,$src\t# float\n" | |
| 7438 "skip:" %} | |
| 7439 ins_encode %{ | |
| 7440 Label skip; | |
| 7441 // Invert sense of branch from sense of CMOV | |
| 7442 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 7443 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); | |
| 7444 __ bind(skip); | |
| 7445 %} | |
| 7446 ins_pipe( pipe_slow ); | |
| 7447 %} | |
| 7448 | |
| 7449 // unsigned version | |
|
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diff
changeset
|
7450 instruct fcmovF_regU(cmpOpU cop, eFlagsRegU cr, regF dst, regF src) %{ |
| 0 | 7451 predicate (UseSSE>=1); |
| 7452 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 7453 ins_cost(200); | |
| 7454 format %{ "Jn$cop skip\n\t" | |
| 7455 "MOVSS $dst,$src\t# float\n" | |
| 7456 "skip:" %} | |
| 7457 ins_encode %{ | |
| 7458 Label skip; | |
| 7459 // Invert sense of branch from sense of CMOV | |
| 7460 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 7461 __ movflt($dst$$XMMRegister, $src$$XMMRegister); | |
| 7462 __ bind(skip); | |
| 7463 %} | |
| 7464 ins_pipe( pipe_slow ); | |
| 7465 %} | |
| 7466 | |
|
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diff
changeset
|
7467 instruct fcmovF_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regF dst, regF src) %{ |
|
415
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403
diff
changeset
|
7468 predicate (UseSSE>=1); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7469 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7470 ins_cost(200); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7471 expand %{ |
|
4761
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7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
7472 fcmovF_regU(cop, cr, dst, src); |
|
415
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parents:
403
diff
changeset
|
7473 %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7474 %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7475 |
| 0 | 7476 // unsigned version |
|
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diff
changeset
|
7477 instruct fcmovD_regU(cmpOpU cop, eFlagsRegU cr, regD dst, regD src) %{ |
| 0 | 7478 predicate (UseSSE>=2); |
| 7479 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 7480 ins_cost(200); | |
| 7481 format %{ "Jn$cop skip\n\t" | |
| 7482 "MOVSD $dst,$src\t# float\n" | |
| 7483 "skip:" %} | |
| 7484 ins_encode %{ | |
| 7485 Label skip; | |
| 7486 // Invert sense of branch from sense of CMOV | |
| 7487 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 7488 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); | |
| 7489 __ bind(skip); | |
| 7490 %} | |
| 7491 ins_pipe( pipe_slow ); | |
| 7492 %} | |
| 7493 | |
|
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diff
changeset
|
7494 instruct fcmovD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regD dst, regD src) %{ |
|
415
4d9884b01ba6
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parents:
403
diff
changeset
|
7495 predicate (UseSSE>=2); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7496 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7497 ins_cost(200); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7498 expand %{ |
|
4761
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diff
changeset
|
7499 fcmovD_regU(cop, cr, dst, src); |
|
415
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parents:
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diff
changeset
|
7500 %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7501 %} |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
7502 |
| 0 | 7503 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{ |
| 7504 predicate(VM_Version::supports_cmov() ); | |
| 7505 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 7506 ins_cost(200); | |
| 7507 format %{ "CMOV$cop $dst.lo,$src.lo\n\t" | |
| 7508 "CMOV$cop $dst.hi,$src.hi" %} | |
| 7509 opcode(0x0F,0x40); | |
| 7510 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) ); | |
| 7511 ins_pipe( pipe_cmov_reg_long ); | |
| 7512 %} | |
| 7513 | |
| 7514 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{ | |
| 7515 predicate(VM_Version::supports_cmov() ); | |
| 7516 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 7517 ins_cost(200); | |
| 7518 format %{ "CMOV$cop $dst.lo,$src.lo\n\t" | |
| 7519 "CMOV$cop $dst.hi,$src.hi" %} | |
| 7520 opcode(0x0F,0x40); | |
| 7521 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) ); | |
| 7522 ins_pipe( pipe_cmov_reg_long ); | |
| 7523 %} | |
| 7524 | |
|
415
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diff
changeset
|
7525 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{ |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
7526 predicate(VM_Version::supports_cmov() ); |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
7527 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
7528 ins_cost(200); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7529 expand %{ |
|
4d9884b01ba6
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403
diff
changeset
|
7530 cmovL_regU(cop, cr, dst, src); |
|
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parents:
403
diff
changeset
|
7531 %} |
|
4d9884b01ba6
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403
diff
changeset
|
7532 %} |
|
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403
diff
changeset
|
7533 |
| 0 | 7534 //----------Arithmetic Instructions-------------------------------------------- |
| 7535 //----------Addition Instructions---------------------------------------------- | |
| 7536 // Integer Addition Instructions | |
|
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|
7537 instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7538 match(Set dst (AddI dst src)); |
| 7539 effect(KILL cr); | |
| 7540 | |
| 7541 size(2); | |
| 7542 format %{ "ADD $dst,$src" %} | |
| 7543 opcode(0x03); | |
| 7544 ins_encode( OpcP, RegReg( dst, src) ); | |
| 7545 ins_pipe( ialu_reg_reg ); | |
| 7546 %} | |
| 7547 | |
|
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diff
changeset
|
7548 instruct addI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ |
| 0 | 7549 match(Set dst (AddI dst src)); |
| 7550 effect(KILL cr); | |
| 7551 | |
| 7552 format %{ "ADD $dst,$src" %} | |
| 7553 opcode(0x81, 0x00); /* /0 id */ | |
| 7554 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 7555 ins_pipe( ialu_reg ); | |
| 7556 %} | |
| 7557 | |
|
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changeset
|
7558 instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{ |
| 0 | 7559 predicate(UseIncDec); |
| 7560 match(Set dst (AddI dst src)); | |
| 7561 effect(KILL cr); | |
| 7562 | |
| 7563 size(1); | |
| 7564 format %{ "INC $dst" %} | |
| 7565 opcode(0x40); /* */ | |
| 7566 ins_encode( Opc_plus( primary, dst ) ); | |
| 7567 ins_pipe( ialu_reg ); | |
| 7568 %} | |
| 7569 | |
|
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diff
changeset
|
7570 instruct leaI_eReg_immI(rRegI dst, rRegI src0, immI src1) %{ |
| 0 | 7571 match(Set dst (AddI src0 src1)); |
| 7572 ins_cost(110); | |
| 7573 | |
| 7574 format %{ "LEA $dst,[$src0 + $src1]" %} | |
| 7575 opcode(0x8D); /* 0x8D /r */ | |
| 7576 ins_encode( OpcP, RegLea( dst, src0, src1 ) ); | |
| 7577 ins_pipe( ialu_reg_reg ); | |
| 7578 %} | |
| 7579 | |
| 7580 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{ | |
| 7581 match(Set dst (AddP src0 src1)); | |
| 7582 ins_cost(110); | |
| 7583 | |
| 7584 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %} | |
| 7585 opcode(0x8D); /* 0x8D /r */ | |
| 7586 ins_encode( OpcP, RegLea( dst, src0, src1 ) ); | |
| 7587 ins_pipe( ialu_reg_reg ); | |
| 7588 %} | |
| 7589 | |
|
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diff
changeset
|
7590 instruct decI_eReg(rRegI dst, immI_M1 src, eFlagsReg cr) %{ |
| 0 | 7591 predicate(UseIncDec); |
| 7592 match(Set dst (AddI dst src)); | |
| 7593 effect(KILL cr); | |
| 7594 | |
| 7595 size(1); | |
| 7596 format %{ "DEC $dst" %} | |
| 7597 opcode(0x48); /* */ | |
| 7598 ins_encode( Opc_plus( primary, dst ) ); | |
| 7599 ins_pipe( ialu_reg ); | |
| 7600 %} | |
| 7601 | |
|
6179
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7602 instruct addP_eReg(eRegP dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7603 match(Set dst (AddP dst src)); |
| 7604 effect(KILL cr); | |
| 7605 | |
| 7606 size(2); | |
| 7607 format %{ "ADD $dst,$src" %} | |
| 7608 opcode(0x03); | |
| 7609 ins_encode( OpcP, RegReg( dst, src) ); | |
| 7610 ins_pipe( ialu_reg_reg ); | |
| 7611 %} | |
| 7612 | |
| 7613 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{ | |
| 7614 match(Set dst (AddP dst src)); | |
| 7615 effect(KILL cr); | |
| 7616 | |
| 7617 format %{ "ADD $dst,$src" %} | |
| 7618 opcode(0x81,0x00); /* Opcode 81 /0 id */ | |
| 7619 // ins_encode( RegImm( dst, src) ); | |
| 7620 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 7621 ins_pipe( ialu_reg ); | |
| 7622 %} | |
| 7623 | |
|
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7624 instruct addI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 7625 match(Set dst (AddI dst (LoadI src))); |
| 7626 effect(KILL cr); | |
| 7627 | |
| 7628 ins_cost(125); | |
| 7629 format %{ "ADD $dst,$src" %} | |
| 7630 opcode(0x03); | |
| 7631 ins_encode( OpcP, RegMem( dst, src) ); | |
| 7632 ins_pipe( ialu_reg_mem ); | |
| 7633 %} | |
| 7634 | |
|
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7635 instruct addI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7636 match(Set dst (StoreI dst (AddI (LoadI dst) src))); |
| 7637 effect(KILL cr); | |
| 7638 | |
| 7639 ins_cost(150); | |
| 7640 format %{ "ADD $dst,$src" %} | |
| 7641 opcode(0x01); /* Opcode 01 /r */ | |
| 7642 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 7643 ins_pipe( ialu_mem_reg ); | |
| 7644 %} | |
| 7645 | |
| 7646 // Add Memory with Immediate | |
| 7647 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 7648 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7649 effect(KILL cr); | |
| 7650 | |
| 7651 ins_cost(125); | |
| 7652 format %{ "ADD $dst,$src" %} | |
| 7653 opcode(0x81); /* Opcode 81 /0 id */ | |
| 7654 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) ); | |
| 7655 ins_pipe( ialu_mem_imm ); | |
| 7656 %} | |
| 7657 | |
| 7658 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{ | |
| 7659 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7660 effect(KILL cr); | |
| 7661 | |
| 7662 ins_cost(125); | |
| 7663 format %{ "INC $dst" %} | |
| 7664 opcode(0xFF); /* Opcode FF /0 */ | |
| 7665 ins_encode( OpcP, RMopc_Mem(0x00,dst)); | |
| 7666 ins_pipe( ialu_mem_imm ); | |
| 7667 %} | |
| 7668 | |
| 7669 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{ | |
| 7670 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7671 effect(KILL cr); | |
| 7672 | |
| 7673 ins_cost(125); | |
| 7674 format %{ "DEC $dst" %} | |
| 7675 opcode(0xFF); /* Opcode FF /1 */ | |
| 7676 ins_encode( OpcP, RMopc_Mem(0x01,dst)); | |
| 7677 ins_pipe( ialu_mem_imm ); | |
| 7678 %} | |
| 7679 | |
| 7680 | |
| 7681 instruct checkCastPP( eRegP dst ) %{ | |
| 7682 match(Set dst (CheckCastPP dst)); | |
| 7683 | |
| 7684 size(0); | |
| 7685 format %{ "#checkcastPP of $dst" %} | |
| 7686 ins_encode( /*empty encoding*/ ); | |
| 7687 ins_pipe( empty ); | |
| 7688 %} | |
| 7689 | |
| 7690 instruct castPP( eRegP dst ) %{ | |
| 7691 match(Set dst (CastPP dst)); | |
| 7692 format %{ "#castPP of $dst" %} | |
| 7693 ins_encode( /*empty encoding*/ ); | |
| 7694 ins_pipe( empty ); | |
| 7695 %} | |
| 7696 | |
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7697 instruct castII( rRegI dst ) %{ |
| 0 | 7698 match(Set dst (CastII dst)); |
| 7699 format %{ "#castII of $dst" %} | |
| 7700 ins_encode( /*empty encoding*/ ); | |
| 7701 ins_cost(0); | |
| 7702 ins_pipe( empty ); | |
| 7703 %} | |
| 7704 | |
| 7705 | |
| 7706 // Load-locked - same as a regular pointer load when used with compare-swap | |
| 7707 instruct loadPLocked(eRegP dst, memory mem) %{ | |
| 7708 match(Set dst (LoadPLocked mem)); | |
| 7709 | |
| 7710 ins_cost(125); | |
| 7711 format %{ "MOV $dst,$mem\t# Load ptr. locked" %} | |
| 7712 opcode(0x8B); | |
| 7713 ins_encode( OpcP, RegMem(dst,mem)); | |
| 7714 ins_pipe( ialu_reg_mem ); | |
| 7715 %} | |
| 7716 | |
| 7717 // Conditional-store of the updated heap-top. | |
| 7718 // Used during allocation of the shared heap. | |
| 7719 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel. | |
| 7720 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{ | |
| 7721 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval))); | |
| 7722 // EAX is killed if there is contention, but then it's also unused. | |
| 7723 // In the common case of no contention, EAX holds the new oop address. | |
| 7724 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %} | |
| 7725 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) ); | |
| 7726 ins_pipe( pipe_cmpxchg ); | |
| 7727 %} | |
| 7728 | |
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7729 // Conditional-store of an int value. |
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7730 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel. |
|
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7731 instruct storeIConditional( memory mem, eAXRegI oldval, rRegI newval, eFlagsReg cr ) %{ |
|
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7732 match(Set cr (StoreIConditional mem (Binary oldval newval))); |
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7733 effect(KILL oldval); |
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7734 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %} |
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7735 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) ); |
| 0 | 7736 ins_pipe( pipe_cmpxchg ); |
| 7737 %} | |
| 7738 | |
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7739 // Conditional-store of a long value. |
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7740 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel. |
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7741 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{ |
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7742 match(Set cr (StoreLConditional mem (Binary oldval newval))); |
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7743 effect(KILL oldval); |
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7744 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t" |
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7745 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t" |
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7746 "XCHG EBX,ECX" |
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7747 %} |
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7748 ins_encode %{ |
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7749 // Note: we need to swap rbx, and rcx before and after the |
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7750 // cmpxchg8 instruction because the instruction uses |
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7751 // rcx as the high order word of the new value to store but |
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7752 // our register encoding uses rbx. |
|
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7753 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc)); |
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7754 if( os::is_MP() ) |
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7755 __ lock(); |
| 624 | 7756 __ cmpxchg8($mem$$Address); |
|
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7757 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc)); |
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7758 %} |
| 0 | 7759 ins_pipe( pipe_cmpxchg ); |
| 7760 %} | |
| 7761 | |
| 7762 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them | |
| 7763 | |
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7764 instruct compareAndSwapL( rRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{ |
| 0 | 7765 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); |
| 7766 effect(KILL cr, KILL oldval); | |
| 7767 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" | |
| 7768 "MOV $res,0\n\t" | |
| 7769 "JNE,s fail\n\t" | |
| 7770 "MOV $res,1\n" | |
| 7771 "fail:" %} | |
| 7772 ins_encode( enc_cmpxchg8(mem_ptr), | |
| 7773 enc_flags_ne_to_boolean(res) ); | |
| 7774 ins_pipe( pipe_cmpxchg ); | |
| 7775 %} | |
| 7776 | |
|
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7777 instruct compareAndSwapP( rRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{ |
| 0 | 7778 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); |
| 7779 effect(KILL cr, KILL oldval); | |
| 7780 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" | |
| 7781 "MOV $res,0\n\t" | |
| 7782 "JNE,s fail\n\t" | |
| 7783 "MOV $res,1\n" | |
| 7784 "fail:" %} | |
| 7785 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) ); | |
| 7786 ins_pipe( pipe_cmpxchg ); | |
| 7787 %} | |
| 7788 | |
|
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7789 instruct compareAndSwapI( rRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{ |
| 0 | 7790 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); |
| 7791 effect(KILL cr, KILL oldval); | |
| 7792 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" | |
| 7793 "MOV $res,0\n\t" | |
| 7794 "JNE,s fail\n\t" | |
| 7795 "MOV $res,1\n" | |
| 7796 "fail:" %} | |
| 7797 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) ); | |
| 7798 ins_pipe( pipe_cmpxchg ); | |
| 7799 %} | |
| 7800 | |
| 7801 //----------Subtraction Instructions------------------------------------------- | |
| 7802 // Integer Subtraction Instructions | |
|
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7803 instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7804 match(Set dst (SubI dst src)); |
| 7805 effect(KILL cr); | |
| 7806 | |
| 7807 size(2); | |
| 7808 format %{ "SUB $dst,$src" %} | |
| 7809 opcode(0x2B); | |
| 7810 ins_encode( OpcP, RegReg( dst, src) ); | |
| 7811 ins_pipe( ialu_reg_reg ); | |
| 7812 %} | |
| 7813 | |
|
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7814 instruct subI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ |
| 0 | 7815 match(Set dst (SubI dst src)); |
| 7816 effect(KILL cr); | |
| 7817 | |
| 7818 format %{ "SUB $dst,$src" %} | |
| 7819 opcode(0x81,0x05); /* Opcode 81 /5 */ | |
| 7820 // ins_encode( RegImm( dst, src) ); | |
| 7821 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 7822 ins_pipe( ialu_reg ); | |
| 7823 %} | |
| 7824 | |
|
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7825 instruct subI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 7826 match(Set dst (SubI dst (LoadI src))); |
| 7827 effect(KILL cr); | |
| 7828 | |
| 7829 ins_cost(125); | |
| 7830 format %{ "SUB $dst,$src" %} | |
| 7831 opcode(0x2B); | |
| 7832 ins_encode( OpcP, RegMem( dst, src) ); | |
| 7833 ins_pipe( ialu_reg_mem ); | |
| 7834 %} | |
| 7835 | |
|
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7836 instruct subI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7837 match(Set dst (StoreI dst (SubI (LoadI dst) src))); |
| 7838 effect(KILL cr); | |
| 7839 | |
| 7840 ins_cost(150); | |
| 7841 format %{ "SUB $dst,$src" %} | |
| 7842 opcode(0x29); /* Opcode 29 /r */ | |
| 7843 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 7844 ins_pipe( ialu_mem_reg ); | |
| 7845 %} | |
| 7846 | |
| 7847 // Subtract from a pointer | |
|
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7848 instruct subP_eReg(eRegP dst, rRegI src, immI0 zero, eFlagsReg cr) %{ |
| 0 | 7849 match(Set dst (AddP dst (SubI zero src))); |
| 7850 effect(KILL cr); | |
| 7851 | |
| 7852 size(2); | |
| 7853 format %{ "SUB $dst,$src" %} | |
| 7854 opcode(0x2B); | |
| 7855 ins_encode( OpcP, RegReg( dst, src) ); | |
| 7856 ins_pipe( ialu_reg_reg ); | |
| 7857 %} | |
| 7858 | |
|
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7859 instruct negI_eReg(rRegI dst, immI0 zero, eFlagsReg cr) %{ |
| 0 | 7860 match(Set dst (SubI zero dst)); |
| 7861 effect(KILL cr); | |
| 7862 | |
| 7863 size(2); | |
| 7864 format %{ "NEG $dst" %} | |
| 7865 opcode(0xF7,0x03); // Opcode F7 /3 | |
| 7866 ins_encode( OpcP, RegOpc( dst ) ); | |
| 7867 ins_pipe( ialu_reg ); | |
| 7868 %} | |
| 7869 | |
| 7870 | |
| 7871 //----------Multiplication/Division Instructions------------------------------- | |
| 7872 // Integer Multiplication Instructions | |
| 7873 // Multiply Register | |
|
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7874 instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7875 match(Set dst (MulI dst src)); |
| 7876 effect(KILL cr); | |
| 7877 | |
| 7878 size(3); | |
| 7879 ins_cost(300); | |
| 7880 format %{ "IMUL $dst,$src" %} | |
| 7881 opcode(0xAF, 0x0F); | |
| 7882 ins_encode( OpcS, OpcP, RegReg( dst, src) ); | |
| 7883 ins_pipe( ialu_reg_reg_alu0 ); | |
| 7884 %} | |
| 7885 | |
| 7886 // Multiply 32-bit Immediate | |
|
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7887 instruct mulI_eReg_imm(rRegI dst, rRegI src, immI imm, eFlagsReg cr) %{ |
| 0 | 7888 match(Set dst (MulI src imm)); |
| 7889 effect(KILL cr); | |
| 7890 | |
| 7891 ins_cost(300); | |
| 7892 format %{ "IMUL $dst,$src,$imm" %} | |
| 7893 opcode(0x69); /* 69 /r id */ | |
| 7894 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) ); | |
| 7895 ins_pipe( ialu_reg_reg_alu0 ); | |
| 7896 %} | |
| 7897 | |
| 7898 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{ | |
| 7899 match(Set dst src); | |
| 7900 effect(KILL cr); | |
| 7901 | |
| 7902 // Note that this is artificially increased to make it more expensive than loadConL | |
| 7903 ins_cost(250); | |
| 7904 format %{ "MOV EAX,$src\t// low word only" %} | |
| 7905 opcode(0xB8); | |
| 7906 ins_encode( LdImmL_Lo(dst, src) ); | |
| 7907 ins_pipe( ialu_reg_fat ); | |
| 7908 %} | |
| 7909 | |
| 7910 // Multiply by 32-bit Immediate, taking the shifted high order results | |
| 7911 // (special case for shift by 32) | |
| 7912 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{ | |
| 7913 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt))); | |
| 7914 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL && | |
| 7915 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint && | |
| 7916 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint ); | |
| 7917 effect(USE src1, KILL cr); | |
| 7918 | |
| 7919 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only | |
| 7920 ins_cost(0*100 + 1*400 - 150); | |
| 7921 format %{ "IMUL EDX:EAX,$src1" %} | |
| 7922 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) ); | |
| 7923 ins_pipe( pipe_slow ); | |
| 7924 %} | |
| 7925 | |
| 7926 // Multiply by 32-bit Immediate, taking the shifted high order results | |
| 7927 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 7928 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt))); | |
| 7929 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL && | |
| 7930 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint && | |
| 7931 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint ); | |
| 7932 effect(USE src1, KILL cr); | |
| 7933 | |
| 7934 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only | |
| 7935 ins_cost(1*100 + 1*400 - 150); | |
| 7936 format %{ "IMUL EDX:EAX,$src1\n\t" | |
| 7937 "SAR EDX,$cnt-32" %} | |
| 7938 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) ); | |
| 7939 ins_pipe( pipe_slow ); | |
| 7940 %} | |
| 7941 | |
| 7942 // Multiply Memory 32-bit Immediate | |
|
6179
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|
7943 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, eFlagsReg cr) %{ |
| 0 | 7944 match(Set dst (MulI (LoadI src) imm)); |
| 7945 effect(KILL cr); | |
| 7946 | |
| 7947 ins_cost(300); | |
| 7948 format %{ "IMUL $dst,$src,$imm" %} | |
| 7949 opcode(0x69); /* 69 /r id */ | |
| 7950 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) ); | |
| 7951 ins_pipe( ialu_reg_mem_alu0 ); | |
| 7952 %} | |
| 7953 | |
| 7954 // Multiply Memory | |
|
6179
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|
7955 instruct mulI(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 7956 match(Set dst (MulI dst (LoadI src))); |
| 7957 effect(KILL cr); | |
| 7958 | |
| 7959 ins_cost(350); | |
| 7960 format %{ "IMUL $dst,$src" %} | |
| 7961 opcode(0xAF, 0x0F); | |
| 7962 ins_encode( OpcS, OpcP, RegMem( dst, src) ); | |
| 7963 ins_pipe( ialu_reg_mem_alu0 ); | |
| 7964 %} | |
| 7965 | |
| 7966 // Multiply Register Int to Long | |
| 7967 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{ | |
| 7968 // Basic Idea: long = (long)int * (long)int | |
| 7969 match(Set dst (MulL (ConvI2L src) (ConvI2L src1))); | |
| 7970 effect(DEF dst, USE src, USE src1, KILL flags); | |
| 7971 | |
| 7972 ins_cost(300); | |
| 7973 format %{ "IMUL $dst,$src1" %} | |
| 7974 | |
| 7975 ins_encode( long_int_multiply( dst, src1 ) ); | |
| 7976 ins_pipe( ialu_reg_reg_alu0 ); | |
| 7977 %} | |
| 7978 | |
| 7979 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{ | |
| 7980 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL) | |
| 7981 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask))); | |
| 7982 effect(KILL flags); | |
| 7983 | |
| 7984 ins_cost(300); | |
| 7985 format %{ "MUL $dst,$src1" %} | |
| 7986 | |
| 7987 ins_encode( long_uint_multiply(dst, src1) ); | |
| 7988 ins_pipe( ialu_reg_reg_alu0 ); | |
| 7989 %} | |
| 7990 | |
| 7991 // Multiply Register Long | |
|
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|
7992 instruct mulL_eReg(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{ |
| 0 | 7993 match(Set dst (MulL dst src)); |
| 7994 effect(KILL cr, TEMP tmp); | |
| 7995 ins_cost(4*100+3*400); | |
| 7996 // Basic idea: lo(result) = lo(x_lo * y_lo) | |
| 7997 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) | |
| 7998 format %{ "MOV $tmp,$src.lo\n\t" | |
| 7999 "IMUL $tmp,EDX\n\t" | |
| 8000 "MOV EDX,$src.hi\n\t" | |
| 8001 "IMUL EDX,EAX\n\t" | |
| 8002 "ADD $tmp,EDX\n\t" | |
| 8003 "MUL EDX:EAX,$src.lo\n\t" | |
| 8004 "ADD EDX,$tmp" %} | |
| 8005 ins_encode( long_multiply( dst, src, tmp ) ); | |
| 8006 ins_pipe( pipe_slow ); | |
| 8007 %} | |
| 8008 | |
|
1209
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|
8009 // Multiply Register Long where the left operand's high 32 bits are zero |
|
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|
8010 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{ |
|
1209
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|
8011 predicate(is_operand_hi32_zero(n->in(1))); |
|
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|
8012 match(Set dst (MulL dst src)); |
|
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changeset
|
8013 effect(KILL cr, TEMP tmp); |
|
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changeset
|
8014 ins_cost(2*100+2*400); |
|
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|
8015 // Basic idea: lo(result) = lo(x_lo * y_lo) |
|
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|
8016 // hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0 |
|
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|
8017 format %{ "MOV $tmp,$src.hi\n\t" |
|
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|
8018 "IMUL $tmp,EAX\n\t" |
|
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|
8019 "MUL EDX:EAX,$src.lo\n\t" |
|
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changeset
|
8020 "ADD EDX,$tmp" %} |
|
e8443c7be117
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diff
changeset
|
8021 ins_encode %{ |
|
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changeset
|
8022 __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register)); |
|
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|
8023 __ imull($tmp$$Register, rax); |
|
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|
8024 __ mull($src$$Register); |
|
e8443c7be117
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changeset
|
8025 __ addl(rdx, $tmp$$Register); |
|
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never
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changeset
|
8026 %} |
|
e8443c7be117
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never
parents:
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diff
changeset
|
8027 ins_pipe( pipe_slow ); |
|
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parents:
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changeset
|
8028 %} |
|
e8443c7be117
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never
parents:
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diff
changeset
|
8029 |
|
e8443c7be117
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diff
changeset
|
8030 // Multiply Register Long where the right operand's high 32 bits are zero |
|
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|
8031 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{ |
|
1209
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|
8032 predicate(is_operand_hi32_zero(n->in(2))); |
|
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|
8033 match(Set dst (MulL dst src)); |
|
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never
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changeset
|
8034 effect(KILL cr, TEMP tmp); |
|
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never
parents:
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changeset
|
8035 ins_cost(2*100+2*400); |
|
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never
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diff
changeset
|
8036 // Basic idea: lo(result) = lo(x_lo * y_lo) |
|
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|
8037 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0 |
|
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diff
changeset
|
8038 format %{ "MOV $tmp,$src.lo\n\t" |
|
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|
8039 "IMUL $tmp,EDX\n\t" |
|
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changeset
|
8040 "MUL EDX:EAX,$src.lo\n\t" |
|
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changeset
|
8041 "ADD EDX,$tmp" %} |
|
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never
parents:
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diff
changeset
|
8042 ins_encode %{ |
|
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changeset
|
8043 __ movl($tmp$$Register, $src$$Register); |
|
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changeset
|
8044 __ imull($tmp$$Register, rdx); |
|
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changeset
|
8045 __ mull($src$$Register); |
|
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parents:
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changeset
|
8046 __ addl(rdx, $tmp$$Register); |
|
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diff
changeset
|
8047 %} |
|
e8443c7be117
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never
parents:
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diff
changeset
|
8048 ins_pipe( pipe_slow ); |
|
e8443c7be117
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never
parents:
1137
diff
changeset
|
8049 %} |
|
e8443c7be117
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never
parents:
1137
diff
changeset
|
8050 |
|
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diff
changeset
|
8051 // Multiply Register Long where the left and the right operands' high 32 bits are zero |
|
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never
parents:
1137
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changeset
|
8052 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{ |
|
e8443c7be117
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|
8053 predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2))); |
|
e8443c7be117
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changeset
|
8054 match(Set dst (MulL dst src)); |
|
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never
parents:
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diff
changeset
|
8055 effect(KILL cr); |
|
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never
parents:
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diff
changeset
|
8056 ins_cost(1*400); |
|
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parents:
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diff
changeset
|
8057 // Basic idea: lo(result) = lo(x_lo * y_lo) |
|
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diff
changeset
|
8058 // hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0 |
|
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changeset
|
8059 format %{ "MUL EDX:EAX,$src.lo\n\t" %} |
|
e8443c7be117
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parents:
1137
diff
changeset
|
8060 ins_encode %{ |
|
e8443c7be117
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never
parents:
1137
diff
changeset
|
8061 __ mull($src$$Register); |
|
e8443c7be117
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never
parents:
1137
diff
changeset
|
8062 %} |
|
e8443c7be117
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never
parents:
1137
diff
changeset
|
8063 ins_pipe( pipe_slow ); |
|
e8443c7be117
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never
parents:
1137
diff
changeset
|
8064 %} |
|
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1137
diff
changeset
|
8065 |
| 0 | 8066 // Multiply Register Long by small constant |
|
6179
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6143
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|
8067 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, rRegI tmp, eFlagsReg cr) %{ |
| 0 | 8068 match(Set dst (MulL dst src)); |
| 8069 effect(KILL cr, TEMP tmp); | |
| 8070 ins_cost(2*100+2*400); | |
| 8071 size(12); | |
| 8072 // Basic idea: lo(result) = lo(src * EAX) | |
| 8073 // hi(result) = hi(src * EAX) + lo(src * EDX) | |
| 8074 format %{ "IMUL $tmp,EDX,$src\n\t" | |
| 8075 "MOV EDX,$src\n\t" | |
| 8076 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t" | |
| 8077 "ADD EDX,$tmp" %} | |
| 8078 ins_encode( long_multiply_con( dst, src, tmp ) ); | |
| 8079 ins_pipe( pipe_slow ); | |
| 8080 %} | |
| 8081 | |
| 8082 // Integer DIV with Register | |
| 8083 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{ | |
| 8084 match(Set rax (DivI rax div)); | |
| 8085 effect(KILL rdx, KILL cr); | |
| 8086 size(26); | |
| 8087 ins_cost(30*100+10*100); | |
| 8088 format %{ "CMP EAX,0x80000000\n\t" | |
| 8089 "JNE,s normal\n\t" | |
| 8090 "XOR EDX,EDX\n\t" | |
| 8091 "CMP ECX,-1\n\t" | |
| 8092 "JE,s done\n" | |
| 8093 "normal: CDQ\n\t" | |
| 8094 "IDIV $div\n\t" | |
| 8095 "done:" %} | |
| 8096 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8097 ins_encode( cdq_enc, OpcP, RegOpc(div) ); | |
| 8098 ins_pipe( ialu_reg_reg_alu0 ); | |
| 8099 %} | |
| 8100 | |
| 8101 // Divide Register Long | |
| 8102 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{ | |
| 8103 match(Set dst (DivL src1 src2)); | |
| 8104 effect( KILL cr, KILL cx, KILL bx ); | |
| 8105 ins_cost(10000); | |
| 8106 format %{ "PUSH $src1.hi\n\t" | |
| 8107 "PUSH $src1.lo\n\t" | |
| 8108 "PUSH $src2.hi\n\t" | |
| 8109 "PUSH $src2.lo\n\t" | |
| 8110 "CALL SharedRuntime::ldiv\n\t" | |
| 8111 "ADD ESP,16" %} | |
| 8112 ins_encode( long_div(src1,src2) ); | |
| 8113 ins_pipe( pipe_slow ); | |
| 8114 %} | |
| 8115 | |
| 8116 // Integer DIVMOD with Register, both quotient and mod results | |
| 8117 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{ | |
| 8118 match(DivModI rax div); | |
| 8119 effect(KILL cr); | |
| 8120 size(26); | |
| 8121 ins_cost(30*100+10*100); | |
| 8122 format %{ "CMP EAX,0x80000000\n\t" | |
| 8123 "JNE,s normal\n\t" | |
| 8124 "XOR EDX,EDX\n\t" | |
| 8125 "CMP ECX,-1\n\t" | |
| 8126 "JE,s done\n" | |
| 8127 "normal: CDQ\n\t" | |
| 8128 "IDIV $div\n\t" | |
| 8129 "done:" %} | |
| 8130 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8131 ins_encode( cdq_enc, OpcP, RegOpc(div) ); | |
| 8132 ins_pipe( pipe_slow ); | |
| 8133 %} | |
| 8134 | |
| 8135 // Integer MOD with Register | |
| 8136 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{ | |
| 8137 match(Set rdx (ModI rax div)); | |
| 8138 effect(KILL rax, KILL cr); | |
| 8139 | |
| 8140 size(26); | |
| 8141 ins_cost(300); | |
| 8142 format %{ "CDQ\n\t" | |
| 8143 "IDIV $div" %} | |
| 8144 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8145 ins_encode( cdq_enc, OpcP, RegOpc(div) ); | |
| 8146 ins_pipe( ialu_reg_reg_alu0 ); | |
| 8147 %} | |
| 8148 | |
| 8149 // Remainder Register Long | |
| 8150 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{ | |
| 8151 match(Set dst (ModL src1 src2)); | |
| 8152 effect( KILL cr, KILL cx, KILL bx ); | |
| 8153 ins_cost(10000); | |
| 8154 format %{ "PUSH $src1.hi\n\t" | |
| 8155 "PUSH $src1.lo\n\t" | |
| 8156 "PUSH $src2.hi\n\t" | |
| 8157 "PUSH $src2.lo\n\t" | |
| 8158 "CALL SharedRuntime::lrem\n\t" | |
| 8159 "ADD ESP,16" %} | |
| 8160 ins_encode( long_mod(src1,src2) ); | |
| 8161 ins_pipe( pipe_slow ); | |
| 8162 %} | |
| 8163 | |
|
1914
ae065c367d93
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diff
changeset
|
8164 // Divide Register Long (no special case since divisor != -1) |
|
6179
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changeset
|
8165 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{ |
|
1914
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changeset
|
8166 match(Set dst (DivL dst imm)); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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diff
changeset
|
8167 effect( TEMP tmp, TEMP tmp2, KILL cr ); |
|
ae065c367d93
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kvn
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diff
changeset
|
8168 ins_cost(1000); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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diff
changeset
|
8169 format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t" |
| 1920 | 8170 "XOR $tmp2,$tmp2\n\t" |
|
1914
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changeset
|
8171 "CMP $tmp,EDX\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
8172 "JA,s fast\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
8173 "MOV $tmp2,EAX\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8174 "MOV EAX,EDX\n\t" |
| 1920 | 8175 "MOV EDX,0\n\t" |
| 8176 "JLE,s pos\n\t" | |
| 8177 "LNEG EAX : $tmp2\n\t" | |
| 8178 "DIV $tmp # unsigned division\n\t" | |
| 8179 "XCHG EAX,$tmp2\n\t" | |
| 8180 "DIV $tmp\n\t" | |
| 8181 "LNEG $tmp2 : EAX\n\t" | |
|
1914
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|
8182 "JMP,s done\n" |
| 1920 | 8183 "pos:\n\t" |
| 8184 "DIV $tmp\n\t" | |
| 8185 "XCHG EAX,$tmp2\n" | |
|
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|
8186 "fast:\n\t" |
| 1920 | 8187 "DIV $tmp\n" |
|
1914
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|
8188 "done:\n\t" |
| 1920 | 8189 "MOV EDX,$tmp2\n\t" |
|
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|
8190 "NEG EDX:EAX # if $imm < 0" %} |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
8191 ins_encode %{ |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
8192 int con = (int)$imm$$constant; |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
8193 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor"); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
8194 int pcon = (con > 0) ? con : -con; |
| 1920 | 8195 Label Lfast, Lpos, Ldone; |
|
1914
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|
8196 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
8197 __ movl($tmp$$Register, pcon); |
| 1920 | 8198 __ xorl($tmp2$$Register,$tmp2$$Register); |
|
1914
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|
8199 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register)); |
| 1920 | 8200 __ jccb(Assembler::above, Lfast); // result fits into 32 bit |
|
1914
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|
8201 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
8202 __ movl($tmp2$$Register, $dst$$Register); // save |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
8203 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register)); |
| 1920 | 8204 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags |
| 8205 __ jccb(Assembler::lessEqual, Lpos); // result is positive | |
| 8206 | |
| 8207 // Negative dividend. | |
| 8208 // convert value to positive to use unsigned division | |
| 8209 __ lneg($dst$$Register, $tmp2$$Register); | |
| 8210 __ divl($tmp$$Register); | |
|
1914
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|
8211 __ xchgl($dst$$Register, $tmp2$$Register); |
| 1920 | 8212 __ divl($tmp$$Register); |
| 8213 // revert result back to negative | |
| 8214 __ lneg($tmp2$$Register, $dst$$Register); | |
|
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|
8215 __ jmpb(Ldone); |
|
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6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
8216 |
| 1920 | 8217 __ bind(Lpos); |
| 8218 __ divl($tmp$$Register); // Use unsigned division | |
| 8219 __ xchgl($dst$$Register, $tmp2$$Register); | |
| 8220 // Fallthrow for final divide, tmp2 has 32 bit hi result | |
| 8221 | |
|
1914
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|
8222 __ bind(Lfast); |
| 1920 | 8223 // fast path: src is positive |
| 8224 __ divl($tmp$$Register); // Use unsigned division | |
|
1914
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|
8225 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
8226 __ bind(Ldone); |
| 1920 | 8227 __ movl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register); |
|
1914
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6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
8228 if (con < 0) { |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
8229 __ lneg(HIGH_FROM_LOW($dst$$Register), $dst$$Register); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
8230 } |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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diff
changeset
|
8231 %} |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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diff
changeset
|
8232 ins_pipe( pipe_slow ); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
8233 %} |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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diff
changeset
|
8234 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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changeset
|
8235 // Remainder Register Long (remainder fit into 32 bits) |
|
6179
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7119644: Increase superword's vector size up to 256 bits
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|
8236 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{ |
|
1914
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6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
8237 match(Set dst (ModL dst imm)); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
8238 effect( TEMP tmp, TEMP tmp2, KILL cr ); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
8239 ins_cost(1000); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
8240 format %{ "MOV $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
8241 "CMP $tmp,EDX\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
8242 "JA,s fast\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
8243 "MOV $tmp2,EAX\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
8244 "MOV EAX,EDX\n\t" |
| 1920 | 8245 "MOV EDX,0\n\t" |
| 8246 "JLE,s pos\n\t" | |
| 8247 "LNEG EAX : $tmp2\n\t" | |
| 8248 "DIV $tmp # unsigned division\n\t" | |
| 8249 "MOV EAX,$tmp2\n\t" | |
| 8250 "DIV $tmp\n\t" | |
| 8251 "NEG EDX\n\t" | |
| 8252 "JMP,s done\n" | |
| 8253 "pos:\n\t" | |
| 8254 "DIV $tmp\n\t" | |
|
1914
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|
8255 "MOV EAX,$tmp2\n" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
8256 "fast:\n\t" |
| 1920 | 8257 "DIV $tmp\n" |
| 8258 "done:\n\t" | |
|
1914
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6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
8259 "MOV EAX,EDX\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
8260 "SAR EDX,31\n\t" %} |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
8261 ins_encode %{ |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
8262 int con = (int)$imm$$constant; |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
8263 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor"); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
8264 int pcon = (con > 0) ? con : -con; |
| 1920 | 8265 Label Lfast, Lpos, Ldone; |
|
1914
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kvn
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|
8266 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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changeset
|
8267 __ movl($tmp$$Register, pcon); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
8268 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register)); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
8269 __ jccb(Assembler::above, Lfast); // src is positive and result fits into 32 bit |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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diff
changeset
|
8270 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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changeset
|
8271 __ movl($tmp2$$Register, $dst$$Register); // save |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
8272 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register)); |
| 1920 | 8273 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags |
| 8274 __ jccb(Assembler::lessEqual, Lpos); // result is positive | |
| 8275 | |
| 8276 // Negative dividend. | |
| 8277 // convert value to positive to use unsigned division | |
| 8278 __ lneg($dst$$Register, $tmp2$$Register); | |
| 8279 __ divl($tmp$$Register); | |
| 8280 __ movl($dst$$Register, $tmp2$$Register); | |
| 8281 __ divl($tmp$$Register); | |
| 8282 // revert remainder back to negative | |
| 8283 __ negl(HIGH_FROM_LOW($dst$$Register)); | |
| 8284 __ jmpb(Ldone); | |
| 8285 | |
| 8286 __ bind(Lpos); | |
| 8287 __ divl($tmp$$Register); | |
|
1914
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|
8288 __ movl($dst$$Register, $tmp2$$Register); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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changeset
|
8289 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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changeset
|
8290 __ bind(Lfast); |
| 1920 | 8291 // fast path: src is positive |
| 8292 __ divl($tmp$$Register); | |
| 8293 | |
| 8294 __ bind(Ldone); | |
|
1914
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6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
8295 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register)); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
8296 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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diff
changeset
|
8297 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
8298 %} |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
8299 ins_pipe( pipe_slow ); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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diff
changeset
|
8300 %} |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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changeset
|
8301 |
| 0 | 8302 // Integer Shift Instructions |
| 8303 // Shift Left by one | |
|
6179
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6143
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changeset
|
8304 instruct shlI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{ |
| 0 | 8305 match(Set dst (LShiftI dst shift)); |
| 8306 effect(KILL cr); | |
| 8307 | |
| 8308 size(2); | |
| 8309 format %{ "SHL $dst,$shift" %} | |
| 8310 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 8311 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8312 ins_pipe( ialu_reg ); | |
| 8313 %} | |
| 8314 | |
| 8315 // Shift Left by 8-bit immediate | |
|
6179
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|
8316 instruct salI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{ |
| 0 | 8317 match(Set dst (LShiftI dst shift)); |
| 8318 effect(KILL cr); | |
| 8319 | |
| 8320 size(3); | |
| 8321 format %{ "SHL $dst,$shift" %} | |
| 8322 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 8323 ins_encode( RegOpcImm( dst, shift) ); | |
| 8324 ins_pipe( ialu_reg ); | |
| 8325 %} | |
| 8326 | |
| 8327 // Shift Left by variable | |
|
6179
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changeset
|
8328 instruct salI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{ |
| 0 | 8329 match(Set dst (LShiftI dst shift)); |
| 8330 effect(KILL cr); | |
| 8331 | |
| 8332 size(2); | |
| 8333 format %{ "SHL $dst,$shift" %} | |
| 8334 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 8335 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8336 ins_pipe( ialu_reg_reg ); | |
| 8337 %} | |
| 8338 | |
| 8339 // Arithmetic shift right by one | |
|
6179
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|
8340 instruct sarI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{ |
| 0 | 8341 match(Set dst (RShiftI dst shift)); |
| 8342 effect(KILL cr); | |
| 8343 | |
| 8344 size(2); | |
| 8345 format %{ "SAR $dst,$shift" %} | |
| 8346 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 8347 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8348 ins_pipe( ialu_reg ); | |
| 8349 %} | |
| 8350 | |
| 8351 // Arithmetic shift right by one | |
| 8352 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{ | |
| 8353 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 8354 effect(KILL cr); | |
| 8355 format %{ "SAR $dst,$shift" %} | |
| 8356 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 8357 ins_encode( OpcP, RMopc_Mem(secondary,dst) ); | |
| 8358 ins_pipe( ialu_mem_imm ); | |
| 8359 %} | |
| 8360 | |
| 8361 // Arithmetic Shift Right by 8-bit immediate | |
|
6179
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changeset
|
8362 instruct sarI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{ |
| 0 | 8363 match(Set dst (RShiftI dst shift)); |
| 8364 effect(KILL cr); | |
| 8365 | |
| 8366 size(3); | |
| 8367 format %{ "SAR $dst,$shift" %} | |
| 8368 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8369 ins_encode( RegOpcImm( dst, shift ) ); | |
| 8370 ins_pipe( ialu_mem_imm ); | |
| 8371 %} | |
| 8372 | |
| 8373 // Arithmetic Shift Right by 8-bit immediate | |
| 8374 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{ | |
| 8375 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 8376 effect(KILL cr); | |
| 8377 | |
| 8378 format %{ "SAR $dst,$shift" %} | |
| 8379 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8380 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) ); | |
| 8381 ins_pipe( ialu_mem_imm ); | |
| 8382 %} | |
| 8383 | |
| 8384 // Arithmetic Shift Right by variable | |
|
6179
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changeset
|
8385 instruct sarI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{ |
| 0 | 8386 match(Set dst (RShiftI dst shift)); |
| 8387 effect(KILL cr); | |
| 8388 | |
| 8389 size(2); | |
| 8390 format %{ "SAR $dst,$shift" %} | |
| 8391 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 8392 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8393 ins_pipe( ialu_reg_reg ); | |
| 8394 %} | |
| 8395 | |
| 8396 // Logical shift right by one | |
|
6179
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changeset
|
8397 instruct shrI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{ |
| 0 | 8398 match(Set dst (URShiftI dst shift)); |
| 8399 effect(KILL cr); | |
| 8400 | |
| 8401 size(2); | |
| 8402 format %{ "SHR $dst,$shift" %} | |
| 8403 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 8404 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8405 ins_pipe( ialu_reg ); | |
| 8406 %} | |
| 8407 | |
| 8408 // Logical Shift Right by 8-bit immediate | |
|
6179
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changeset
|
8409 instruct shrI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{ |
| 0 | 8410 match(Set dst (URShiftI dst shift)); |
| 8411 effect(KILL cr); | |
| 8412 | |
| 8413 size(3); | |
| 8414 format %{ "SHR $dst,$shift" %} | |
| 8415 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 8416 ins_encode( RegOpcImm( dst, shift) ); | |
| 8417 ins_pipe( ialu_reg ); | |
| 8418 %} | |
| 8419 | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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diff
changeset
|
8420 |
| 0 | 8421 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24. |
| 8422 // This idiom is used by the compiler for the i2b bytecode. | |
|
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8423 instruct i2b(rRegI dst, xRegI src, immI_24 twentyfour) %{ |
| 0 | 8424 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour)); |
| 8425 | |
| 8426 size(3); | |
| 8427 format %{ "MOVSX $dst,$src :8" %} | |
| 785 | 8428 ins_encode %{ |
| 8429 __ movsbl($dst$$Register, $src$$Register); | |
| 8430 %} | |
| 8431 ins_pipe(ialu_reg_reg); | |
| 0 | 8432 %} |
| 8433 | |
| 8434 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16. | |
| 8435 // This idiom is used by the compiler the i2s bytecode. | |
|
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8436 instruct i2s(rRegI dst, xRegI src, immI_16 sixteen) %{ |
| 0 | 8437 match(Set dst (RShiftI (LShiftI src sixteen) sixteen)); |
| 8438 | |
| 8439 size(3); | |
| 8440 format %{ "MOVSX $dst,$src :16" %} | |
| 785 | 8441 ins_encode %{ |
| 8442 __ movswl($dst$$Register, $src$$Register); | |
| 8443 %} | |
| 8444 ins_pipe(ialu_reg_reg); | |
| 0 | 8445 %} |
| 8446 | |
| 8447 | |
| 8448 // Logical Shift Right by variable | |
|
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8449 instruct shrI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{ |
| 0 | 8450 match(Set dst (URShiftI dst shift)); |
| 8451 effect(KILL cr); | |
| 8452 | |
| 8453 size(2); | |
| 8454 format %{ "SHR $dst,$shift" %} | |
| 8455 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 8456 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8457 ins_pipe( ialu_reg_reg ); | |
| 8458 %} | |
| 8459 | |
| 8460 | |
| 8461 //----------Logical Instructions----------------------------------------------- | |
| 8462 //----------Integer Logical Instructions--------------------------------------- | |
| 8463 // And Instructions | |
| 8464 // And Register with Register | |
|
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8465 instruct andI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 8466 match(Set dst (AndI dst src)); |
| 8467 effect(KILL cr); | |
| 8468 | |
| 8469 size(2); | |
| 8470 format %{ "AND $dst,$src" %} | |
| 8471 opcode(0x23); | |
| 8472 ins_encode( OpcP, RegReg( dst, src) ); | |
| 8473 ins_pipe( ialu_reg_reg ); | |
| 8474 %} | |
| 8475 | |
| 8476 // And Register with Immediate | |
|
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8477 instruct andI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ |
| 0 | 8478 match(Set dst (AndI dst src)); |
| 8479 effect(KILL cr); | |
| 8480 | |
| 8481 format %{ "AND $dst,$src" %} | |
| 8482 opcode(0x81,0x04); /* Opcode 81 /4 */ | |
| 8483 // ins_encode( RegImm( dst, src) ); | |
| 8484 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 8485 ins_pipe( ialu_reg ); | |
| 8486 %} | |
| 8487 | |
| 8488 // And Register with Memory | |
|
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8489 instruct andI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 8490 match(Set dst (AndI dst (LoadI src))); |
| 8491 effect(KILL cr); | |
| 8492 | |
| 8493 ins_cost(125); | |
| 8494 format %{ "AND $dst,$src" %} | |
| 8495 opcode(0x23); | |
| 8496 ins_encode( OpcP, RegMem( dst, src) ); | |
| 8497 ins_pipe( ialu_reg_mem ); | |
| 8498 %} | |
| 8499 | |
| 8500 // And Memory with Register | |
|
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8501 instruct andI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 8502 match(Set dst (StoreI dst (AndI (LoadI dst) src))); |
| 8503 effect(KILL cr); | |
| 8504 | |
| 8505 ins_cost(150); | |
| 8506 format %{ "AND $dst,$src" %} | |
| 8507 opcode(0x21); /* Opcode 21 /r */ | |
| 8508 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 8509 ins_pipe( ialu_mem_reg ); | |
| 8510 %} | |
| 8511 | |
| 8512 // And Memory with Immediate | |
| 8513 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 8514 match(Set dst (StoreI dst (AndI (LoadI dst) src))); | |
| 8515 effect(KILL cr); | |
| 8516 | |
| 8517 ins_cost(125); | |
| 8518 format %{ "AND $dst,$src" %} | |
| 8519 opcode(0x81, 0x4); /* Opcode 81 /4 id */ | |
| 8520 // ins_encode( MemImm( dst, src) ); | |
| 8521 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); | |
| 8522 ins_pipe( ialu_mem_imm ); | |
| 8523 %} | |
| 8524 | |
| 8525 // Or Instructions | |
| 8526 // Or Register with Register | |
|
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8527 instruct orI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 8528 match(Set dst (OrI dst src)); |
| 8529 effect(KILL cr); | |
| 8530 | |
| 8531 size(2); | |
| 8532 format %{ "OR $dst,$src" %} | |
| 8533 opcode(0x0B); | |
| 8534 ins_encode( OpcP, RegReg( dst, src) ); | |
| 8535 ins_pipe( ialu_reg_reg ); | |
| 8536 %} | |
| 8537 | |
|
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8538 instruct orI_eReg_castP2X(rRegI dst, eRegP src, eFlagsReg cr) %{ |
|
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8539 match(Set dst (OrI dst (CastP2X src))); |
|
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8540 effect(KILL cr); |
|
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8541 |
|
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8542 size(2); |
|
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8543 format %{ "OR $dst,$src" %} |
|
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8544 opcode(0x0B); |
|
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8545 ins_encode( OpcP, RegReg( dst, src) ); |
|
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8546 ins_pipe( ialu_reg_reg ); |
|
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8547 %} |
|
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8548 |
|
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8549 |
| 0 | 8550 // Or Register with Immediate |
|
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8551 instruct orI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ |
| 0 | 8552 match(Set dst (OrI dst src)); |
| 8553 effect(KILL cr); | |
| 8554 | |
| 8555 format %{ "OR $dst,$src" %} | |
| 8556 opcode(0x81,0x01); /* Opcode 81 /1 id */ | |
| 8557 // ins_encode( RegImm( dst, src) ); | |
| 8558 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 8559 ins_pipe( ialu_reg ); | |
| 8560 %} | |
| 8561 | |
| 8562 // Or Register with Memory | |
|
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8563 instruct orI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 8564 match(Set dst (OrI dst (LoadI src))); |
| 8565 effect(KILL cr); | |
| 8566 | |
| 8567 ins_cost(125); | |
| 8568 format %{ "OR $dst,$src" %} | |
| 8569 opcode(0x0B); | |
| 8570 ins_encode( OpcP, RegMem( dst, src) ); | |
| 8571 ins_pipe( ialu_reg_mem ); | |
| 8572 %} | |
| 8573 | |
| 8574 // Or Memory with Register | |
|
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8575 instruct orI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 8576 match(Set dst (StoreI dst (OrI (LoadI dst) src))); |
| 8577 effect(KILL cr); | |
| 8578 | |
| 8579 ins_cost(150); | |
| 8580 format %{ "OR $dst,$src" %} | |
| 8581 opcode(0x09); /* Opcode 09 /r */ | |
| 8582 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 8583 ins_pipe( ialu_mem_reg ); | |
| 8584 %} | |
| 8585 | |
| 8586 // Or Memory with Immediate | |
| 8587 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 8588 match(Set dst (StoreI dst (OrI (LoadI dst) src))); | |
| 8589 effect(KILL cr); | |
| 8590 | |
| 8591 ins_cost(125); | |
| 8592 format %{ "OR $dst,$src" %} | |
| 8593 opcode(0x81,0x1); /* Opcode 81 /1 id */ | |
| 8594 // ins_encode( MemImm( dst, src) ); | |
| 8595 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); | |
| 8596 ins_pipe( ialu_mem_imm ); | |
| 8597 %} | |
| 8598 | |
| 8599 // ROL/ROR | |
| 8600 // ROL expand | |
|
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8601 instruct rolI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{ |
| 0 | 8602 effect(USE_DEF dst, USE shift, KILL cr); |
| 8603 | |
| 8604 format %{ "ROL $dst, $shift" %} | |
| 8605 opcode(0xD1, 0x0); /* Opcode D1 /0 */ | |
| 8606 ins_encode( OpcP, RegOpc( dst )); | |
| 8607 ins_pipe( ialu_reg ); | |
| 8608 %} | |
| 8609 | |
|
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8610 instruct rolI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{ |
| 0 | 8611 effect(USE_DEF dst, USE shift, KILL cr); |
| 8612 | |
| 8613 format %{ "ROL $dst, $shift" %} | |
| 8614 opcode(0xC1, 0x0); /*Opcode /C1 /0 */ | |
| 8615 ins_encode( RegOpcImm(dst, shift) ); | |
| 8616 ins_pipe(ialu_reg); | |
| 8617 %} | |
| 8618 | |
| 8619 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 8620 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8621 | |
| 8622 format %{ "ROL $dst, $shift" %} | |
| 8623 opcode(0xD3, 0x0); /* Opcode D3 /0 */ | |
| 8624 ins_encode(OpcP, RegOpc(dst)); | |
| 8625 ins_pipe( ialu_reg_reg ); | |
| 8626 %} | |
| 8627 // end of ROL expand | |
| 8628 | |
| 8629 // ROL 32bit by one once | |
|
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8630 instruct rolI_eReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{ |
| 0 | 8631 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift))); |
| 8632 | |
| 8633 expand %{ | |
| 8634 rolI_eReg_imm1(dst, lshift, cr); | |
| 8635 %} | |
| 8636 %} | |
| 8637 | |
| 8638 // ROL 32bit var by imm8 once | |
|
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8639 instruct rolI_eReg_i8(rRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{ |
| 0 | 8640 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); |
| 8641 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift))); | |
| 8642 | |
| 8643 expand %{ | |
| 8644 rolI_eReg_imm8(dst, lshift, cr); | |
| 8645 %} | |
| 8646 %} | |
| 8647 | |
| 8648 // ROL 32bit var by var once | |
| 8649 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{ | |
| 8650 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift)))); | |
| 8651 | |
| 8652 expand %{ | |
| 8653 rolI_eReg_CL(dst, shift, cr); | |
| 8654 %} | |
| 8655 %} | |
| 8656 | |
| 8657 // ROL 32bit var by var once | |
| 8658 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{ | |
| 8659 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift)))); | |
| 8660 | |
| 8661 expand %{ | |
| 8662 rolI_eReg_CL(dst, shift, cr); | |
| 8663 %} | |
| 8664 %} | |
| 8665 | |
| 8666 // ROR expand | |
|
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8667 instruct rorI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{ |
| 0 | 8668 effect(USE_DEF dst, USE shift, KILL cr); |
| 8669 | |
| 8670 format %{ "ROR $dst, $shift" %} | |
| 8671 opcode(0xD1,0x1); /* Opcode D1 /1 */ | |
| 8672 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8673 ins_pipe( ialu_reg ); | |
| 8674 %} | |
| 8675 | |
|
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8676 instruct rorI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{ |
| 0 | 8677 effect (USE_DEF dst, USE shift, KILL cr); |
| 8678 | |
| 8679 format %{ "ROR $dst, $shift" %} | |
| 8680 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */ | |
| 8681 ins_encode( RegOpcImm(dst, shift) ); | |
| 8682 ins_pipe( ialu_reg ); | |
| 8683 %} | |
| 8684 | |
| 8685 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{ | |
| 8686 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8687 | |
| 8688 format %{ "ROR $dst, $shift" %} | |
| 8689 opcode(0xD3, 0x1); /* Opcode D3 /1 */ | |
| 8690 ins_encode(OpcP, RegOpc(dst)); | |
| 8691 ins_pipe( ialu_reg_reg ); | |
| 8692 %} | |
| 8693 // end of ROR expand | |
| 8694 | |
| 8695 // ROR right once | |
|
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8696 instruct rorI_eReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{ |
| 0 | 8697 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift))); |
| 8698 | |
| 8699 expand %{ | |
| 8700 rorI_eReg_imm1(dst, rshift, cr); | |
| 8701 %} | |
| 8702 %} | |
| 8703 | |
| 8704 // ROR 32bit by immI8 once | |
|
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8705 instruct rorI_eReg_i8(rRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{ |
| 0 | 8706 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); |
| 8707 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift))); | |
| 8708 | |
| 8709 expand %{ | |
| 8710 rorI_eReg_imm8(dst, rshift, cr); | |
| 8711 %} | |
| 8712 %} | |
| 8713 | |
| 8714 // ROR 32bit var by var once | |
| 8715 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{ | |
| 8716 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift)))); | |
| 8717 | |
| 8718 expand %{ | |
| 8719 rorI_eReg_CL(dst, shift, cr); | |
| 8720 %} | |
| 8721 %} | |
| 8722 | |
| 8723 // ROR 32bit var by var once | |
| 8724 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{ | |
| 8725 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift)))); | |
| 8726 | |
| 8727 expand %{ | |
| 8728 rorI_eReg_CL(dst, shift, cr); | |
| 8729 %} | |
| 8730 %} | |
| 8731 | |
| 8732 // Xor Instructions | |
| 8733 // Xor Register with Register | |
|
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8734 instruct xorI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 8735 match(Set dst (XorI dst src)); |
| 8736 effect(KILL cr); | |
| 8737 | |
| 8738 size(2); | |
| 8739 format %{ "XOR $dst,$src" %} | |
| 8740 opcode(0x33); | |
| 8741 ins_encode( OpcP, RegReg( dst, src) ); | |
| 8742 ins_pipe( ialu_reg_reg ); | |
| 8743 %} | |
| 8744 | |
| 403 | 8745 // Xor Register with Immediate -1 |
|
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8746 instruct xorI_eReg_im1(rRegI dst, immI_M1 imm) %{ |
| 403 | 8747 match(Set dst (XorI dst imm)); |
| 8748 | |
| 8749 size(2); | |
| 8750 format %{ "NOT $dst" %} | |
| 8751 ins_encode %{ | |
| 8752 __ notl($dst$$Register); | |
| 8753 %} | |
| 8754 ins_pipe( ialu_reg ); | |
| 8755 %} | |
| 8756 | |
| 0 | 8757 // Xor Register with Immediate |
|
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8758 instruct xorI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ |
| 0 | 8759 match(Set dst (XorI dst src)); |
| 8760 effect(KILL cr); | |
| 8761 | |
| 8762 format %{ "XOR $dst,$src" %} | |
| 8763 opcode(0x81,0x06); /* Opcode 81 /6 id */ | |
| 8764 // ins_encode( RegImm( dst, src) ); | |
| 8765 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 8766 ins_pipe( ialu_reg ); | |
| 8767 %} | |
| 8768 | |
| 8769 // Xor Register with Memory | |
|
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8770 instruct xorI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 8771 match(Set dst (XorI dst (LoadI src))); |
| 8772 effect(KILL cr); | |
| 8773 | |
| 8774 ins_cost(125); | |
| 8775 format %{ "XOR $dst,$src" %} | |
| 8776 opcode(0x33); | |
| 8777 ins_encode( OpcP, RegMem(dst, src) ); | |
| 8778 ins_pipe( ialu_reg_mem ); | |
| 8779 %} | |
| 8780 | |
| 8781 // Xor Memory with Register | |
|
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8782 instruct xorI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 8783 match(Set dst (StoreI dst (XorI (LoadI dst) src))); |
| 8784 effect(KILL cr); | |
| 8785 | |
| 8786 ins_cost(150); | |
| 8787 format %{ "XOR $dst,$src" %} | |
| 8788 opcode(0x31); /* Opcode 31 /r */ | |
| 8789 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 8790 ins_pipe( ialu_mem_reg ); | |
| 8791 %} | |
| 8792 | |
| 8793 // Xor Memory with Immediate | |
| 8794 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 8795 match(Set dst (StoreI dst (XorI (LoadI dst) src))); | |
| 8796 effect(KILL cr); | |
| 8797 | |
| 8798 ins_cost(125); | |
| 8799 format %{ "XOR $dst,$src" %} | |
| 8800 opcode(0x81,0x6); /* Opcode 81 /6 id */ | |
| 8801 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); | |
| 8802 ins_pipe( ialu_mem_imm ); | |
| 8803 %} | |
| 8804 | |
| 8805 //----------Convert Int to Boolean--------------------------------------------- | |
| 8806 | |
|
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8807 instruct movI_nocopy(rRegI dst, rRegI src) %{ |
| 0 | 8808 effect( DEF dst, USE src ); |
| 8809 format %{ "MOV $dst,$src" %} | |
| 8810 ins_encode( enc_Copy( dst, src) ); | |
| 8811 ins_pipe( ialu_reg_reg ); | |
| 8812 %} | |
| 8813 | |
|
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8814 instruct ci2b( rRegI dst, rRegI src, eFlagsReg cr ) %{ |
| 0 | 8815 effect( USE_DEF dst, USE src, KILL cr ); |
| 8816 | |
| 8817 size(4); | |
| 8818 format %{ "NEG $dst\n\t" | |
| 8819 "ADC $dst,$src" %} | |
| 8820 ins_encode( neg_reg(dst), | |
| 8821 OpcRegReg(0x13,dst,src) ); | |
| 8822 ins_pipe( ialu_reg_reg_long ); | |
| 8823 %} | |
| 8824 | |
|
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8825 instruct convI2B( rRegI dst, rRegI src, eFlagsReg cr ) %{ |
| 0 | 8826 match(Set dst (Conv2B src)); |
| 8827 | |
| 8828 expand %{ | |
| 8829 movI_nocopy(dst,src); | |
| 8830 ci2b(dst,src,cr); | |
| 8831 %} | |
| 8832 %} | |
| 8833 | |
|
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8834 instruct movP_nocopy(rRegI dst, eRegP src) %{ |
| 0 | 8835 effect( DEF dst, USE src ); |
| 8836 format %{ "MOV $dst,$src" %} | |
| 8837 ins_encode( enc_Copy( dst, src) ); | |
| 8838 ins_pipe( ialu_reg_reg ); | |
| 8839 %} | |
| 8840 | |
|
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|
8841 instruct cp2b( rRegI dst, eRegP src, eFlagsReg cr ) %{ |
| 0 | 8842 effect( USE_DEF dst, USE src, KILL cr ); |
| 8843 format %{ "NEG $dst\n\t" | |
| 8844 "ADC $dst,$src" %} | |
| 8845 ins_encode( neg_reg(dst), | |
| 8846 OpcRegReg(0x13,dst,src) ); | |
| 8847 ins_pipe( ialu_reg_reg_long ); | |
| 8848 %} | |
| 8849 | |
|
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8850 instruct convP2B( rRegI dst, eRegP src, eFlagsReg cr ) %{ |
| 0 | 8851 match(Set dst (Conv2B src)); |
| 8852 | |
| 8853 expand %{ | |
| 8854 movP_nocopy(dst,src); | |
| 8855 cp2b(dst,src,cr); | |
| 8856 %} | |
| 8857 %} | |
| 8858 | |
| 8859 instruct cmpLTMask( eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr ) %{ | |
| 8860 match(Set dst (CmpLTMask p q)); | |
| 8861 effect( KILL cr ); | |
| 8862 ins_cost(400); | |
| 8863 | |
| 8864 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination | |
| 8865 format %{ "XOR $dst,$dst\n\t" | |
| 8866 "CMP $p,$q\n\t" | |
| 8867 "SETlt $dst\n\t" | |
| 8868 "NEG $dst" %} | |
| 8869 ins_encode( OpcRegReg(0x33,dst,dst), | |
| 8870 OpcRegReg(0x3B,p,q), | |
| 8871 setLT_reg(dst), neg_reg(dst) ); | |
| 8872 ins_pipe( pipe_slow ); | |
| 8873 %} | |
| 8874 | |
|
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8875 instruct cmpLTMask0( rRegI dst, immI0 zero, eFlagsReg cr ) %{ |
| 0 | 8876 match(Set dst (CmpLTMask dst zero)); |
| 8877 effect( DEF dst, KILL cr ); | |
| 8878 ins_cost(100); | |
| 8879 | |
| 8880 format %{ "SAR $dst,31" %} | |
| 8881 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8882 ins_encode( RegOpcImm( dst, 0x1F ) ); | |
| 8883 ins_pipe( ialu_reg ); | |
| 8884 %} | |
| 8885 | |
| 8886 | |
| 8887 instruct cadd_cmpLTMask( ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp, eFlagsReg cr ) %{ | |
| 8888 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); | |
| 8889 effect( KILL tmp, KILL cr ); | |
| 8890 ins_cost(400); | |
| 8891 // annoyingly, $tmp has no edges so you cant ask for it in | |
| 8892 // any format or encoding | |
| 8893 format %{ "SUB $p,$q\n\t" | |
| 8894 "SBB ECX,ECX\n\t" | |
| 8895 "AND ECX,$y\n\t" | |
| 8896 "ADD $p,ECX" %} | |
| 8897 ins_encode( enc_cmpLTP(p,q,y,tmp) ); | |
| 8898 ins_pipe( pipe_cmplt ); | |
| 8899 %} | |
| 8900 | |
| 8901 /* If I enable this, I encourage spilling in the inner loop of compress. | |
| 8902 instruct cadd_cmpLTMask_mem( ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr ) %{ | |
| 8903 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q))); | |
| 8904 effect( USE_KILL tmp, KILL cr ); | |
| 8905 ins_cost(400); | |
| 8906 | |
| 8907 format %{ "SUB $p,$q\n\t" | |
| 8908 "SBB ECX,ECX\n\t" | |
| 8909 "AND ECX,$y\n\t" | |
| 8910 "ADD $p,ECX" %} | |
| 8911 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) ); | |
| 8912 %} | |
| 8913 */ | |
| 8914 | |
| 8915 //----------Long Instructions------------------------------------------------ | |
| 8916 // Add Long Register with Register | |
| 8917 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 8918 match(Set dst (AddL dst src)); | |
| 8919 effect(KILL cr); | |
| 8920 ins_cost(200); | |
| 8921 format %{ "ADD $dst.lo,$src.lo\n\t" | |
| 8922 "ADC $dst.hi,$src.hi" %} | |
| 8923 opcode(0x03, 0x13); | |
| 8924 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) ); | |
| 8925 ins_pipe( ialu_reg_reg_long ); | |
| 8926 %} | |
| 8927 | |
| 8928 // Add Long Register with Immediate | |
| 8929 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 8930 match(Set dst (AddL dst src)); | |
| 8931 effect(KILL cr); | |
| 8932 format %{ "ADD $dst.lo,$src.lo\n\t" | |
| 8933 "ADC $dst.hi,$src.hi" %} | |
| 8934 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */ | |
| 8935 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 8936 ins_pipe( ialu_reg_long ); | |
| 8937 %} | |
| 8938 | |
| 8939 // Add Long Register with Memory | |
| 8940 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 8941 match(Set dst (AddL dst (LoadL mem))); | |
| 8942 effect(KILL cr); | |
| 8943 ins_cost(125); | |
| 8944 format %{ "ADD $dst.lo,$mem\n\t" | |
| 8945 "ADC $dst.hi,$mem+4" %} | |
| 8946 opcode(0x03, 0x13); | |
| 8947 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 8948 ins_pipe( ialu_reg_long_mem ); | |
| 8949 %} | |
| 8950 | |
| 8951 // Subtract Long Register with Register. | |
| 8952 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 8953 match(Set dst (SubL dst src)); | |
| 8954 effect(KILL cr); | |
| 8955 ins_cost(200); | |
| 8956 format %{ "SUB $dst.lo,$src.lo\n\t" | |
| 8957 "SBB $dst.hi,$src.hi" %} | |
| 8958 opcode(0x2B, 0x1B); | |
| 8959 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) ); | |
| 8960 ins_pipe( ialu_reg_reg_long ); | |
| 8961 %} | |
| 8962 | |
| 8963 // Subtract Long Register with Immediate | |
| 8964 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 8965 match(Set dst (SubL dst src)); | |
| 8966 effect(KILL cr); | |
| 8967 format %{ "SUB $dst.lo,$src.lo\n\t" | |
| 8968 "SBB $dst.hi,$src.hi" %} | |
| 8969 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */ | |
| 8970 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 8971 ins_pipe( ialu_reg_long ); | |
| 8972 %} | |
| 8973 | |
| 8974 // Subtract Long Register with Memory | |
| 8975 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 8976 match(Set dst (SubL dst (LoadL mem))); | |
| 8977 effect(KILL cr); | |
| 8978 ins_cost(125); | |
| 8979 format %{ "SUB $dst.lo,$mem\n\t" | |
| 8980 "SBB $dst.hi,$mem+4" %} | |
| 8981 opcode(0x2B, 0x1B); | |
| 8982 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 8983 ins_pipe( ialu_reg_long_mem ); | |
| 8984 %} | |
| 8985 | |
| 8986 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{ | |
| 8987 match(Set dst (SubL zero dst)); | |
| 8988 effect(KILL cr); | |
| 8989 ins_cost(300); | |
| 8990 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %} | |
| 8991 ins_encode( neg_long(dst) ); | |
| 8992 ins_pipe( ialu_reg_reg_long ); | |
| 8993 %} | |
| 8994 | |
| 8995 // And Long Register with Register | |
| 8996 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 8997 match(Set dst (AndL dst src)); | |
| 8998 effect(KILL cr); | |
| 8999 format %{ "AND $dst.lo,$src.lo\n\t" | |
| 9000 "AND $dst.hi,$src.hi" %} | |
| 9001 opcode(0x23,0x23); | |
| 9002 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); | |
| 9003 ins_pipe( ialu_reg_reg_long ); | |
| 9004 %} | |
| 9005 | |
| 9006 // And Long Register with Immediate | |
| 9007 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 9008 match(Set dst (AndL dst src)); | |
| 9009 effect(KILL cr); | |
| 9010 format %{ "AND $dst.lo,$src.lo\n\t" | |
| 9011 "AND $dst.hi,$src.hi" %} | |
| 9012 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */ | |
| 9013 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 9014 ins_pipe( ialu_reg_long ); | |
| 9015 %} | |
| 9016 | |
| 9017 // And Long Register with Memory | |
| 9018 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 9019 match(Set dst (AndL dst (LoadL mem))); | |
| 9020 effect(KILL cr); | |
| 9021 ins_cost(125); | |
| 9022 format %{ "AND $dst.lo,$mem\n\t" | |
| 9023 "AND $dst.hi,$mem+4" %} | |
| 9024 opcode(0x23, 0x23); | |
| 9025 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 9026 ins_pipe( ialu_reg_long_mem ); | |
| 9027 %} | |
| 9028 | |
| 9029 // Or Long Register with Register | |
| 9030 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 9031 match(Set dst (OrL dst src)); | |
| 9032 effect(KILL cr); | |
| 9033 format %{ "OR $dst.lo,$src.lo\n\t" | |
| 9034 "OR $dst.hi,$src.hi" %} | |
| 9035 opcode(0x0B,0x0B); | |
| 9036 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); | |
| 9037 ins_pipe( ialu_reg_reg_long ); | |
| 9038 %} | |
| 9039 | |
| 9040 // Or Long Register with Immediate | |
| 9041 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 9042 match(Set dst (OrL dst src)); | |
| 9043 effect(KILL cr); | |
| 9044 format %{ "OR $dst.lo,$src.lo\n\t" | |
| 9045 "OR $dst.hi,$src.hi" %} | |
| 9046 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */ | |
| 9047 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 9048 ins_pipe( ialu_reg_long ); | |
| 9049 %} | |
| 9050 | |
| 9051 // Or Long Register with Memory | |
| 9052 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 9053 match(Set dst (OrL dst (LoadL mem))); | |
| 9054 effect(KILL cr); | |
| 9055 ins_cost(125); | |
| 9056 format %{ "OR $dst.lo,$mem\n\t" | |
| 9057 "OR $dst.hi,$mem+4" %} | |
| 9058 opcode(0x0B,0x0B); | |
| 9059 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 9060 ins_pipe( ialu_reg_long_mem ); | |
| 9061 %} | |
| 9062 | |
| 9063 // Xor Long Register with Register | |
| 9064 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 9065 match(Set dst (XorL dst src)); | |
| 9066 effect(KILL cr); | |
| 9067 format %{ "XOR $dst.lo,$src.lo\n\t" | |
| 9068 "XOR $dst.hi,$src.hi" %} | |
| 9069 opcode(0x33,0x33); | |
| 9070 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); | |
| 9071 ins_pipe( ialu_reg_reg_long ); | |
| 9072 %} | |
| 9073 | |
| 403 | 9074 // Xor Long Register with Immediate -1 |
| 9075 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{ | |
| 9076 match(Set dst (XorL dst imm)); | |
| 9077 format %{ "NOT $dst.lo\n\t" | |
| 9078 "NOT $dst.hi" %} | |
| 9079 ins_encode %{ | |
| 9080 __ notl($dst$$Register); | |
| 9081 __ notl(HIGH_FROM_LOW($dst$$Register)); | |
| 9082 %} | |
| 9083 ins_pipe( ialu_reg_long ); | |
| 9084 %} | |
| 9085 | |
| 0 | 9086 // Xor Long Register with Immediate |
| 9087 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 9088 match(Set dst (XorL dst src)); | |
| 9089 effect(KILL cr); | |
| 9090 format %{ "XOR $dst.lo,$src.lo\n\t" | |
| 9091 "XOR $dst.hi,$src.hi" %} | |
| 9092 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */ | |
| 9093 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 9094 ins_pipe( ialu_reg_long ); | |
| 9095 %} | |
| 9096 | |
| 9097 // Xor Long Register with Memory | |
| 9098 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 9099 match(Set dst (XorL dst (LoadL mem))); | |
| 9100 effect(KILL cr); | |
| 9101 ins_cost(125); | |
| 9102 format %{ "XOR $dst.lo,$mem\n\t" | |
| 9103 "XOR $dst.hi,$mem+4" %} | |
| 9104 opcode(0x33,0x33); | |
| 9105 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 9106 ins_pipe( ialu_reg_long_mem ); | |
| 9107 %} | |
| 9108 | |
| 219 | 9109 // Shift Left Long by 1 |
| 9110 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{ | |
| 9111 predicate(UseNewLongLShift); | |
| 9112 match(Set dst (LShiftL dst cnt)); | |
| 9113 effect(KILL cr); | |
| 9114 ins_cost(100); | |
| 9115 format %{ "ADD $dst.lo,$dst.lo\n\t" | |
| 9116 "ADC $dst.hi,$dst.hi" %} | |
| 9117 ins_encode %{ | |
| 9118 __ addl($dst$$Register,$dst$$Register); | |
| 9119 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9120 %} | |
| 9121 ins_pipe( ialu_reg_long ); | |
| 9122 %} | |
| 9123 | |
| 9124 // Shift Left Long by 2 | |
| 9125 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{ | |
| 9126 predicate(UseNewLongLShift); | |
| 9127 match(Set dst (LShiftL dst cnt)); | |
| 9128 effect(KILL cr); | |
| 9129 ins_cost(100); | |
| 9130 format %{ "ADD $dst.lo,$dst.lo\n\t" | |
| 9131 "ADC $dst.hi,$dst.hi\n\t" | |
| 9132 "ADD $dst.lo,$dst.lo\n\t" | |
| 9133 "ADC $dst.hi,$dst.hi" %} | |
| 9134 ins_encode %{ | |
| 9135 __ addl($dst$$Register,$dst$$Register); | |
| 9136 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9137 __ addl($dst$$Register,$dst$$Register); | |
| 9138 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9139 %} | |
| 9140 ins_pipe( ialu_reg_long ); | |
| 9141 %} | |
| 9142 | |
| 9143 // Shift Left Long by 3 | |
| 9144 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{ | |
| 9145 predicate(UseNewLongLShift); | |
| 9146 match(Set dst (LShiftL dst cnt)); | |
| 9147 effect(KILL cr); | |
| 9148 ins_cost(100); | |
| 9149 format %{ "ADD $dst.lo,$dst.lo\n\t" | |
| 9150 "ADC $dst.hi,$dst.hi\n\t" | |
| 9151 "ADD $dst.lo,$dst.lo\n\t" | |
| 9152 "ADC $dst.hi,$dst.hi\n\t" | |
| 9153 "ADD $dst.lo,$dst.lo\n\t" | |
| 9154 "ADC $dst.hi,$dst.hi" %} | |
| 9155 ins_encode %{ | |
| 9156 __ addl($dst$$Register,$dst$$Register); | |
| 9157 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9158 __ addl($dst$$Register,$dst$$Register); | |
| 9159 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9160 __ addl($dst$$Register,$dst$$Register); | |
| 9161 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9162 %} | |
| 9163 ins_pipe( ialu_reg_long ); | |
| 9164 %} | |
| 9165 | |
| 0 | 9166 // Shift Left Long by 1-31 |
| 9167 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ | |
| 9168 match(Set dst (LShiftL dst cnt)); | |
| 9169 effect(KILL cr); | |
| 9170 ins_cost(200); | |
| 9171 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t" | |
| 9172 "SHL $dst.lo,$cnt" %} | |
| 9173 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */ | |
| 9174 ins_encode( move_long_small_shift(dst,cnt) ); | |
| 9175 ins_pipe( ialu_reg_long ); | |
| 9176 %} | |
| 9177 | |
| 9178 // Shift Left Long by 32-63 | |
| 9179 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 9180 match(Set dst (LShiftL dst cnt)); | |
| 9181 effect(KILL cr); | |
| 9182 ins_cost(300); | |
| 9183 format %{ "MOV $dst.hi,$dst.lo\n" | |
| 9184 "\tSHL $dst.hi,$cnt-32\n" | |
| 9185 "\tXOR $dst.lo,$dst.lo" %} | |
| 9186 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 9187 ins_encode( move_long_big_shift_clr(dst,cnt) ); | |
| 9188 ins_pipe( ialu_reg_long ); | |
| 9189 %} | |
| 9190 | |
| 9191 // Shift Left Long by variable | |
| 9192 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 9193 match(Set dst (LShiftL dst shift)); | |
| 9194 effect(KILL cr); | |
| 9195 ins_cost(500+200); | |
| 9196 size(17); | |
| 9197 format %{ "TEST $shift,32\n\t" | |
| 9198 "JEQ,s small\n\t" | |
| 9199 "MOV $dst.hi,$dst.lo\n\t" | |
| 9200 "XOR $dst.lo,$dst.lo\n" | |
| 9201 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t" | |
| 9202 "SHL $dst.lo,$shift" %} | |
| 9203 ins_encode( shift_left_long( dst, shift ) ); | |
| 9204 ins_pipe( pipe_slow ); | |
| 9205 %} | |
| 9206 | |
| 9207 // Shift Right Long by 1-31 | |
| 9208 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ | |
| 9209 match(Set dst (URShiftL dst cnt)); | |
| 9210 effect(KILL cr); | |
| 9211 ins_cost(200); | |
| 9212 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t" | |
| 9213 "SHR $dst.hi,$cnt" %} | |
| 9214 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */ | |
| 9215 ins_encode( move_long_small_shift(dst,cnt) ); | |
| 9216 ins_pipe( ialu_reg_long ); | |
| 9217 %} | |
| 9218 | |
| 9219 // Shift Right Long by 32-63 | |
| 9220 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 9221 match(Set dst (URShiftL dst cnt)); | |
| 9222 effect(KILL cr); | |
| 9223 ins_cost(300); | |
| 9224 format %{ "MOV $dst.lo,$dst.hi\n" | |
| 9225 "\tSHR $dst.lo,$cnt-32\n" | |
| 9226 "\tXOR $dst.hi,$dst.hi" %} | |
| 9227 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 9228 ins_encode( move_long_big_shift_clr(dst,cnt) ); | |
| 9229 ins_pipe( ialu_reg_long ); | |
| 9230 %} | |
| 9231 | |
| 9232 // Shift Right Long by variable | |
| 9233 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 9234 match(Set dst (URShiftL dst shift)); | |
| 9235 effect(KILL cr); | |
| 9236 ins_cost(600); | |
| 9237 size(17); | |
| 9238 format %{ "TEST $shift,32\n\t" | |
| 9239 "JEQ,s small\n\t" | |
| 9240 "MOV $dst.lo,$dst.hi\n\t" | |
| 9241 "XOR $dst.hi,$dst.hi\n" | |
| 9242 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t" | |
| 9243 "SHR $dst.hi,$shift" %} | |
| 9244 ins_encode( shift_right_long( dst, shift ) ); | |
| 9245 ins_pipe( pipe_slow ); | |
| 9246 %} | |
| 9247 | |
| 9248 // Shift Right Long by 1-31 | |
| 9249 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ | |
| 9250 match(Set dst (RShiftL dst cnt)); | |
| 9251 effect(KILL cr); | |
| 9252 ins_cost(200); | |
| 9253 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t" | |
| 9254 "SAR $dst.hi,$cnt" %} | |
| 9255 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */ | |
| 9256 ins_encode( move_long_small_shift(dst,cnt) ); | |
| 9257 ins_pipe( ialu_reg_long ); | |
| 9258 %} | |
| 9259 | |
| 9260 // Shift Right Long by 32-63 | |
| 9261 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 9262 match(Set dst (RShiftL dst cnt)); | |
| 9263 effect(KILL cr); | |
| 9264 ins_cost(300); | |
| 9265 format %{ "MOV $dst.lo,$dst.hi\n" | |
| 9266 "\tSAR $dst.lo,$cnt-32\n" | |
| 9267 "\tSAR $dst.hi,31" %} | |
| 9268 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 9269 ins_encode( move_long_big_shift_sign(dst,cnt) ); | |
| 9270 ins_pipe( ialu_reg_long ); | |
| 9271 %} | |
| 9272 | |
| 9273 // Shift Right arithmetic Long by variable | |
| 9274 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 9275 match(Set dst (RShiftL dst shift)); | |
| 9276 effect(KILL cr); | |
| 9277 ins_cost(600); | |
| 9278 size(18); | |
| 9279 format %{ "TEST $shift,32\n\t" | |
| 9280 "JEQ,s small\n\t" | |
| 9281 "MOV $dst.lo,$dst.hi\n\t" | |
| 9282 "SAR $dst.hi,31\n" | |
| 9283 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t" | |
| 9284 "SAR $dst.hi,$shift" %} | |
| 9285 ins_encode( shift_right_arith_long( dst, shift ) ); | |
| 9286 ins_pipe( pipe_slow ); | |
| 9287 %} | |
| 9288 | |
| 9289 | |
| 9290 //----------Double Instructions------------------------------------------------ | |
| 9291 // Double Math | |
| 9292 | |
| 9293 // Compare & branch | |
| 9294 | |
| 9295 // P6 version of float compare, sets condition codes in EFLAGS | |
|
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9296 instruct cmpDPR_cc_P6(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{ |
| 0 | 9297 predicate(VM_Version::supports_cmov() && UseSSE <=1); |
| 9298 match(Set cr (CmpD src1 src2)); | |
| 9299 effect(KILL rax); | |
| 9300 ins_cost(150); | |
| 9301 format %{ "FLD $src1\n\t" | |
| 9302 "FUCOMIP ST,$src2 // P6 instruction\n\t" | |
| 9303 "JNP exit\n\t" | |
| 9304 "MOV ah,1 // saw a NaN, set CF\n\t" | |
| 9305 "SAHF\n" | |
| 9306 "exit:\tNOP // avoid branch to branch" %} | |
| 9307 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ | |
|
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9308 ins_encode( Push_Reg_DPR(src1), |
| 0 | 9309 OpcP, RegOpc(src2), |
| 9310 cmpF_P6_fixup ); | |
| 9311 ins_pipe( pipe_slow ); | |
| 9312 %} | |
| 9313 | |
|
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9314 instruct cmpDPR_cc_P6CF(eFlagsRegUCF cr, regDPR src1, regDPR src2) %{ |
|
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9315 predicate(VM_Version::supports_cmov() && UseSSE <=1); |
|
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9316 match(Set cr (CmpD src1 src2)); |
|
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9317 ins_cost(150); |
|
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9318 format %{ "FLD $src1\n\t" |
|
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9319 "FUCOMIP ST,$src2 // P6 instruction" %} |
|
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9320 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ |
|
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9321 ins_encode( Push_Reg_DPR(src1), |
|
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|
9322 OpcP, RegOpc(src2)); |
|
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|
9323 ins_pipe( pipe_slow ); |
|
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|
9324 %} |
|
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|
9325 |
| 0 | 9326 // Compare & branch |
|
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9327 instruct cmpDPR_cc(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{ |
| 0 | 9328 predicate(UseSSE<=1); |
| 9329 match(Set cr (CmpD src1 src2)); | |
| 9330 effect(KILL rax); | |
| 9331 ins_cost(200); | |
| 9332 format %{ "FLD $src1\n\t" | |
| 9333 "FCOMp $src2\n\t" | |
| 9334 "FNSTSW AX\n\t" | |
| 9335 "TEST AX,0x400\n\t" | |
| 9336 "JZ,s flags\n\t" | |
| 9337 "MOV AH,1\t# unordered treat as LT\n" | |
| 9338 "flags:\tSAHF" %} | |
| 9339 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
|
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9340 ins_encode( Push_Reg_DPR(src1), |
| 0 | 9341 OpcP, RegOpc(src2), |
| 9342 fpu_flags); | |
| 9343 ins_pipe( pipe_slow ); | |
| 9344 %} | |
| 9345 | |
| 9346 // Compare vs zero into -1,0,1 | |
|
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9347 instruct cmpDPR_0(rRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 9348 predicate(UseSSE<=1); |
| 9349 match(Set dst (CmpD3 src1 zero)); | |
| 9350 effect(KILL cr, KILL rax); | |
| 9351 ins_cost(280); | |
| 9352 format %{ "FTSTD $dst,$src1" %} | |
| 9353 opcode(0xE4, 0xD9); | |
|
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9354 ins_encode( Push_Reg_DPR(src1), |
| 0 | 9355 OpcS, OpcP, PopFPU, |
| 9356 CmpF_Result(dst)); | |
| 9357 ins_pipe( pipe_slow ); | |
| 9358 %} | |
| 9359 | |
| 9360 // Compare into -1,0,1 | |
|
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9361 instruct cmpDPR_reg(rRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 9362 predicate(UseSSE<=1); |
| 9363 match(Set dst (CmpD3 src1 src2)); | |
| 9364 effect(KILL cr, KILL rax); | |
| 9365 ins_cost(300); | |
| 9366 format %{ "FCMPD $dst,$src1,$src2" %} | |
| 9367 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
|
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9368 ins_encode( Push_Reg_DPR(src1), |
| 0 | 9369 OpcP, RegOpc(src2), |
| 9370 CmpF_Result(dst)); | |
| 9371 ins_pipe( pipe_slow ); | |
| 9372 %} | |
| 9373 | |
| 9374 // float compare and set condition codes in EFLAGS by XMM regs | |
|
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9375 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2) %{ |
| 0 | 9376 predicate(UseSSE>=2); |
| 4759 | 9377 match(Set cr (CmpD src1 src2)); |
| 9378 ins_cost(145); | |
| 9379 format %{ "UCOMISD $src1,$src2\n\t" | |
| 9380 "JNP,s exit\n\t" | |
| 9381 "PUSHF\t# saw NaN, set CF\n\t" | |
| 9382 "AND [rsp], #0xffffff2b\n\t" | |
| 9383 "POPF\n" | |
| 9384 "exit:" %} | |
| 9385 ins_encode %{ | |
| 9386 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9387 emit_cmpfp_fixup(_masm); | |
| 9388 %} | |
| 9389 ins_pipe( pipe_slow ); | |
| 9390 %} | |
| 9391 | |
|
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9392 instruct cmpD_ccCF(eFlagsRegUCF cr, regD src1, regD src2) %{ |
|
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|
9393 predicate(UseSSE>=2); |
| 4759 | 9394 match(Set cr (CmpD src1 src2)); |
|
415
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|
9395 ins_cost(100); |
| 4759 | 9396 format %{ "UCOMISD $src1,$src2" %} |
| 9397 ins_encode %{ | |
| 9398 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9399 %} | |
|
415
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|
9400 ins_pipe( pipe_slow ); |
|
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|
9401 %} |
|
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|
9402 |
| 0 | 9403 // float compare and set condition codes in EFLAGS by XMM regs |
|
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|
9404 instruct cmpD_ccmem(eFlagsRegU cr, regD src1, memory src2) %{ |
| 0 | 9405 predicate(UseSSE>=2); |
| 4759 | 9406 match(Set cr (CmpD src1 (LoadD src2))); |
| 0 | 9407 ins_cost(145); |
| 4759 | 9408 format %{ "UCOMISD $src1,$src2\n\t" |
| 9409 "JNP,s exit\n\t" | |
| 9410 "PUSHF\t# saw NaN, set CF\n\t" | |
| 9411 "AND [rsp], #0xffffff2b\n\t" | |
| 9412 "POPF\n" | |
| 9413 "exit:" %} | |
| 9414 ins_encode %{ | |
| 9415 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9416 emit_cmpfp_fixup(_masm); | |
| 9417 %} | |
| 9418 ins_pipe( pipe_slow ); | |
| 9419 %} | |
| 9420 | |
|
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9421 instruct cmpD_ccmemCF(eFlagsRegUCF cr, regD src1, memory src2) %{ |
|
415
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|
9422 predicate(UseSSE>=2); |
| 4759 | 9423 match(Set cr (CmpD src1 (LoadD src2))); |
|
415
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|
9424 ins_cost(100); |
| 4759 | 9425 format %{ "UCOMISD $src1,$src2" %} |
| 9426 ins_encode %{ | |
| 9427 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9428 %} | |
|
415
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|
9429 ins_pipe( pipe_slow ); |
|
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|
9430 %} |
|
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|
9431 |
| 0 | 9432 // Compare into -1,0,1 in XMM |
|
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9433 instruct cmpD_reg(xRegI dst, regD src1, regD src2, eFlagsReg cr) %{ |
| 0 | 9434 predicate(UseSSE>=2); |
| 9435 match(Set dst (CmpD3 src1 src2)); | |
| 9436 effect(KILL cr); | |
| 9437 ins_cost(255); | |
| 4759 | 9438 format %{ "UCOMISD $src1, $src2\n\t" |
| 9439 "MOV $dst, #-1\n\t" | |
| 9440 "JP,s done\n\t" | |
| 9441 "JB,s done\n\t" | |
| 9442 "SETNE $dst\n\t" | |
| 9443 "MOVZB $dst, $dst\n" | |
| 9444 "done:" %} | |
| 9445 ins_encode %{ | |
| 9446 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9447 emit_cmpfp3(_masm, $dst$$Register); | |
| 9448 %} | |
| 0 | 9449 ins_pipe( pipe_slow ); |
| 9450 %} | |
| 9451 | |
| 9452 // Compare into -1,0,1 in XMM and memory | |
|
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9453 instruct cmpD_regmem(xRegI dst, regD src1, memory src2, eFlagsReg cr) %{ |
| 0 | 9454 predicate(UseSSE>=2); |
| 4759 | 9455 match(Set dst (CmpD3 src1 (LoadD src2))); |
| 0 | 9456 effect(KILL cr); |
| 9457 ins_cost(275); | |
| 4759 | 9458 format %{ "UCOMISD $src1, $src2\n\t" |
| 9459 "MOV $dst, #-1\n\t" | |
| 9460 "JP,s done\n\t" | |
| 9461 "JB,s done\n\t" | |
| 9462 "SETNE $dst\n\t" | |
| 9463 "MOVZB $dst, $dst\n" | |
| 9464 "done:" %} | |
| 9465 ins_encode %{ | |
| 9466 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9467 emit_cmpfp3(_masm, $dst$$Register); | |
| 9468 %} | |
| 0 | 9469 ins_pipe( pipe_slow ); |
| 9470 %} | |
| 9471 | |
| 9472 | |
|
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|
9473 instruct subDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9474 predicate (UseSSE <=1); |
| 9475 match(Set dst (SubD dst src)); | |
| 9476 | |
| 9477 format %{ "FLD $src\n\t" | |
| 9478 "DSUBp $dst,ST" %} | |
| 9479 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */ | |
| 9480 ins_cost(150); | |
|
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9481 ins_encode( Push_Reg_DPR(src), |
| 0 | 9482 OpcP, RegOpc(dst) ); |
| 9483 ins_pipe( fpu_reg_reg ); | |
| 9484 %} | |
| 9485 | |
|
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9486 instruct subDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{ |
| 0 | 9487 predicate (UseSSE <=1); |
| 9488 match(Set dst (RoundDouble (SubD src1 src2))); | |
| 9489 ins_cost(250); | |
| 9490 | |
| 9491 format %{ "FLD $src2\n\t" | |
| 9492 "DSUB ST,$src1\n\t" | |
| 9493 "FSTP_D $dst\t# D-round" %} | |
| 9494 opcode(0xD8, 0x5); | |
|
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|
9495 ins_encode( Push_Reg_DPR(src2), |
|
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9496 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) ); |
| 0 | 9497 ins_pipe( fpu_mem_reg_reg ); |
| 9498 %} | |
| 9499 | |
| 9500 | |
|
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9501 instruct subDPR_reg_mem(regDPR dst, memory src) %{ |
| 0 | 9502 predicate (UseSSE <=1); |
| 9503 match(Set dst (SubD dst (LoadD src))); | |
| 9504 ins_cost(150); | |
| 9505 | |
| 9506 format %{ "FLD $src\n\t" | |
| 9507 "DSUBp $dst,ST" %} | |
| 9508 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */ | |
| 9509 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 9510 OpcP, RegOpc(dst) ); | |
| 9511 ins_pipe( fpu_reg_mem ); | |
| 9512 %} | |
| 9513 | |
|
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9514 instruct absDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9515 predicate (UseSSE<=1); |
| 9516 match(Set dst (AbsD src)); | |
| 9517 ins_cost(100); | |
| 9518 format %{ "FABS" %} | |
| 9519 opcode(0xE1, 0xD9); | |
| 9520 ins_encode( OpcS, OpcP ); | |
| 9521 ins_pipe( fpu_reg_reg ); | |
| 9522 %} | |
| 9523 | |
|
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|
9524 instruct negDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9525 predicate(UseSSE<=1); |
| 9526 match(Set dst (NegD src)); | |
| 9527 ins_cost(100); | |
| 9528 format %{ "FCHS" %} | |
| 9529 opcode(0xE0, 0xD9); | |
| 9530 ins_encode( OpcS, OpcP ); | |
| 9531 ins_pipe( fpu_reg_reg ); | |
| 9532 %} | |
| 9533 | |
|
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9534 instruct addDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9535 predicate(UseSSE<=1); |
| 9536 match(Set dst (AddD dst src)); | |
| 9537 format %{ "FLD $src\n\t" | |
| 9538 "DADD $dst,ST" %} | |
| 9539 size(4); | |
| 9540 ins_cost(150); | |
| 9541 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/ | |
|
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|
9542 ins_encode( Push_Reg_DPR(src), |
| 0 | 9543 OpcP, RegOpc(dst) ); |
| 9544 ins_pipe( fpu_reg_reg ); | |
| 9545 %} | |
| 9546 | |
| 9547 | |
|
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|
9548 instruct addDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{ |
| 0 | 9549 predicate(UseSSE<=1); |
| 9550 match(Set dst (RoundDouble (AddD src1 src2))); | |
| 9551 ins_cost(250); | |
| 9552 | |
| 9553 format %{ "FLD $src2\n\t" | |
| 9554 "DADD ST,$src1\n\t" | |
| 9555 "FSTP_D $dst\t# D-round" %} | |
| 9556 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/ | |
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9557 ins_encode( Push_Reg_DPR(src2), |
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9558 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) ); |
| 0 | 9559 ins_pipe( fpu_mem_reg_reg ); |
| 9560 %} | |
| 9561 | |
| 9562 | |
|
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9563 instruct addDPR_reg_mem(regDPR dst, memory src) %{ |
| 0 | 9564 predicate(UseSSE<=1); |
| 9565 match(Set dst (AddD dst (LoadD src))); | |
| 9566 ins_cost(150); | |
| 9567 | |
| 9568 format %{ "FLD $src\n\t" | |
| 9569 "DADDp $dst,ST" %} | |
| 9570 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */ | |
| 9571 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 9572 OpcP, RegOpc(dst) ); | |
| 9573 ins_pipe( fpu_reg_mem ); | |
| 9574 %} | |
| 9575 | |
| 9576 // add-to-memory | |
|
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9577 instruct addDPR_mem_reg(memory dst, regDPR src) %{ |
| 0 | 9578 predicate(UseSSE<=1); |
| 9579 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src)))); | |
| 9580 ins_cost(150); | |
| 9581 | |
| 9582 format %{ "FLD_D $dst\n\t" | |
| 9583 "DADD ST,$src\n\t" | |
| 9584 "FST_D $dst" %} | |
| 9585 opcode(0xDD, 0x0); | |
| 9586 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst), | |
| 9587 Opcode(0xD8), RegOpc(src), | |
| 9588 set_instruction_start, | |
| 9589 Opcode(0xDD), RMopc_Mem(0x03,dst) ); | |
| 9590 ins_pipe( fpu_reg_mem ); | |
| 9591 %} | |
| 9592 | |
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9593 instruct addDPR_reg_imm1(regDPR dst, immDPR1 con) %{ |
| 0 | 9594 predicate(UseSSE<=1); |
| 2008 | 9595 match(Set dst (AddD dst con)); |
| 0 | 9596 ins_cost(125); |
| 9597 format %{ "FLD1\n\t" | |
| 9598 "DADDp $dst,ST" %} | |
| 2008 | 9599 ins_encode %{ |
| 9600 __ fld1(); | |
| 9601 __ faddp($dst$$reg); | |
| 9602 %} | |
| 9603 ins_pipe(fpu_reg); | |
| 9604 %} | |
| 9605 | |
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9606 instruct addDPR_reg_imm(regDPR dst, immDPR con) %{ |
| 0 | 9607 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 ); |
| 2008 | 9608 match(Set dst (AddD dst con)); |
| 0 | 9609 ins_cost(200); |
| 2008 | 9610 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 9611 "DADDp $dst,ST" %} |
| 2008 | 9612 ins_encode %{ |
| 9613 __ fld_d($constantaddress($con)); | |
| 9614 __ faddp($dst$$reg); | |
| 9615 %} | |
| 9616 ins_pipe(fpu_reg_mem); | |
| 0 | 9617 %} |
| 9618 | |
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9619 instruct addDPR_reg_imm_round(stackSlotD dst, regDPR src, immDPR con) %{ |
| 0 | 9620 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 ); |
| 9621 match(Set dst (RoundDouble (AddD src con))); | |
| 9622 ins_cost(200); | |
| 2008 | 9623 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 9624 "DADD ST,$src\n\t" |
| 9625 "FSTP_D $dst\t# D-round" %} | |
| 2008 | 9626 ins_encode %{ |
| 9627 __ fld_d($constantaddress($con)); | |
| 9628 __ fadd($src$$reg); | |
| 9629 __ fstp_d(Address(rsp, $dst$$disp)); | |
| 9630 %} | |
| 9631 ins_pipe(fpu_mem_reg_con); | |
| 0 | 9632 %} |
| 9633 | |
|
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9634 instruct mulDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9635 predicate(UseSSE<=1); |
| 9636 match(Set dst (MulD dst src)); | |
| 9637 format %{ "FLD $src\n\t" | |
| 9638 "DMULp $dst,ST" %} | |
| 9639 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/ | |
| 9640 ins_cost(150); | |
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9641 ins_encode( Push_Reg_DPR(src), |
| 0 | 9642 OpcP, RegOpc(dst) ); |
| 9643 ins_pipe( fpu_reg_reg ); | |
| 9644 %} | |
| 9645 | |
| 9646 // Strict FP instruction biases argument before multiply then | |
| 9647 // biases result to avoid double rounding of subnormals. | |
| 9648 // | |
| 9649 // scale arg1 by multiplying arg1 by 2^(-15360) | |
| 9650 // load arg2 | |
| 9651 // multiply scaled arg1 by arg2 | |
| 9652 // rescale product by 2^(15360) | |
| 9653 // | |
|
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9654 instruct strictfp_mulDPR_reg(regDPR1 dst, regnotDPR1 src) %{ |
| 0 | 9655 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() ); |
| 9656 match(Set dst (MulD dst src)); | |
| 9657 ins_cost(1); // Select this instruction for all strict FP double multiplies | |
| 9658 | |
| 9659 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t" | |
| 9660 "DMULp $dst,ST\n\t" | |
| 9661 "FLD $src\n\t" | |
| 9662 "DMULp $dst,ST\n\t" | |
| 9663 "FLD StubRoutines::_fpu_subnormal_bias2\n\t" | |
| 9664 "DMULp $dst,ST\n\t" %} | |
| 9665 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/ | |
| 9666 ins_encode( strictfp_bias1(dst), | |
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9667 Push_Reg_DPR(src), |
| 0 | 9668 OpcP, RegOpc(dst), |
| 9669 strictfp_bias2(dst) ); | |
| 9670 ins_pipe( fpu_reg_reg ); | |
| 9671 %} | |
| 9672 | |
|
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9673 instruct mulDPR_reg_imm(regDPR dst, immDPR con) %{ |
| 0 | 9674 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 ); |
| 2008 | 9675 match(Set dst (MulD dst con)); |
| 0 | 9676 ins_cost(200); |
| 2008 | 9677 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 9678 "DMULp $dst,ST" %} |
| 2008 | 9679 ins_encode %{ |
| 9680 __ fld_d($constantaddress($con)); | |
| 9681 __ fmulp($dst$$reg); | |
| 9682 %} | |
| 9683 ins_pipe(fpu_reg_mem); | |
| 0 | 9684 %} |
| 9685 | |
| 9686 | |
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9687 instruct mulDPR_reg_mem(regDPR dst, memory src) %{ |
| 0 | 9688 predicate( UseSSE<=1 ); |
| 9689 match(Set dst (MulD dst (LoadD src))); | |
| 9690 ins_cost(200); | |
| 9691 format %{ "FLD_D $src\n\t" | |
| 9692 "DMULp $dst,ST" %} | |
| 9693 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */ | |
| 9694 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 9695 OpcP, RegOpc(dst) ); | |
| 9696 ins_pipe( fpu_reg_mem ); | |
| 9697 %} | |
| 9698 | |
| 9699 // | |
| 9700 // Cisc-alternate to reg-reg multiply | |
|
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9701 instruct mulDPR_reg_mem_cisc(regDPR dst, regDPR src, memory mem) %{ |
| 0 | 9702 predicate( UseSSE<=1 ); |
| 9703 match(Set dst (MulD src (LoadD mem))); | |
| 9704 ins_cost(250); | |
| 9705 format %{ "FLD_D $mem\n\t" | |
| 9706 "DMUL ST,$src\n\t" | |
| 9707 "FSTP_D $dst" %} | |
| 9708 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */ | |
| 9709 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem), | |
|
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9710 OpcReg_FPR(src), |
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9711 Pop_Reg_DPR(dst) ); |
| 0 | 9712 ins_pipe( fpu_reg_reg_mem ); |
| 9713 %} | |
| 9714 | |
| 9715 | |
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9716 // MACRO3 -- addDPR a mulDPR |
| 0 | 9717 // This instruction is a '2-address' instruction in that the result goes |
| 9718 // back to src2. This eliminates a move from the macro; possibly the | |
| 9719 // register allocator will have to add it back (and maybe not). | |
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9720 instruct addDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{ |
| 0 | 9721 predicate( UseSSE<=1 ); |
| 9722 match(Set src2 (AddD (MulD src0 src1) src2)); | |
| 9723 format %{ "FLD $src0\t# ===MACRO3d===\n\t" | |
| 9724 "DMUL ST,$src1\n\t" | |
| 9725 "DADDp $src2,ST" %} | |
| 9726 ins_cost(250); | |
| 9727 opcode(0xDD); /* LoadD DD /0 */ | |
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9728 ins_encode( Push_Reg_FPR(src0), |
| 0 | 9729 FMul_ST_reg(src1), |
| 9730 FAddP_reg_ST(src2) ); | |
| 9731 ins_pipe( fpu_reg_reg_reg ); | |
| 9732 %} | |
| 9733 | |
| 9734 | |
|
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9735 // MACRO3 -- subDPR a mulDPR |
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9736 instruct subDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{ |
| 0 | 9737 predicate( UseSSE<=1 ); |
| 9738 match(Set src2 (SubD (MulD src0 src1) src2)); | |
| 9739 format %{ "FLD $src0\t# ===MACRO3d===\n\t" | |
| 9740 "DMUL ST,$src1\n\t" | |
| 9741 "DSUBRp $src2,ST" %} | |
| 9742 ins_cost(250); | |
|
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9743 ins_encode( Push_Reg_FPR(src0), |
| 0 | 9744 FMul_ST_reg(src1), |
| 9745 Opcode(0xDE), Opc_plus(0xE0,src2)); | |
| 9746 ins_pipe( fpu_reg_reg_reg ); | |
| 9747 %} | |
| 9748 | |
| 9749 | |
|
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9750 instruct divDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9751 predicate( UseSSE<=1 ); |
| 9752 match(Set dst (DivD dst src)); | |
| 9753 | |
| 9754 format %{ "FLD $src\n\t" | |
| 9755 "FDIVp $dst,ST" %} | |
| 9756 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
| 9757 ins_cost(150); | |
|
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9758 ins_encode( Push_Reg_DPR(src), |
| 0 | 9759 OpcP, RegOpc(dst) ); |
| 9760 ins_pipe( fpu_reg_reg ); | |
| 9761 %} | |
| 9762 | |
| 9763 // Strict FP instruction biases argument before division then | |
| 9764 // biases result, to avoid double rounding of subnormals. | |
| 9765 // | |
| 9766 // scale dividend by multiplying dividend by 2^(-15360) | |
| 9767 // load divisor | |
| 9768 // divide scaled dividend by divisor | |
| 9769 // rescale quotient by 2^(15360) | |
| 9770 // | |
|
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9771 instruct strictfp_divDPR_reg(regDPR1 dst, regnotDPR1 src) %{ |
| 0 | 9772 predicate (UseSSE<=1); |
| 9773 match(Set dst (DivD dst src)); | |
| 9774 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() ); | |
| 9775 ins_cost(01); | |
| 9776 | |
| 9777 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t" | |
| 9778 "DMULp $dst,ST\n\t" | |
| 9779 "FLD $src\n\t" | |
| 9780 "FDIVp $dst,ST\n\t" | |
| 9781 "FLD StubRoutines::_fpu_subnormal_bias2\n\t" | |
| 9782 "DMULp $dst,ST\n\t" %} | |
| 9783 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
| 9784 ins_encode( strictfp_bias1(dst), | |
|
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9785 Push_Reg_DPR(src), |
| 0 | 9786 OpcP, RegOpc(dst), |
| 9787 strictfp_bias2(dst) ); | |
| 9788 ins_pipe( fpu_reg_reg ); | |
| 9789 %} | |
| 9790 | |
|
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9791 instruct divDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{ |
| 0 | 9792 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) ); |
| 9793 match(Set dst (RoundDouble (DivD src1 src2))); | |
| 9794 | |
| 9795 format %{ "FLD $src1\n\t" | |
| 9796 "FDIV ST,$src2\n\t" | |
| 9797 "FSTP_D $dst\t# D-round" %} | |
| 9798 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */ | |
|
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9799 ins_encode( Push_Reg_DPR(src1), |
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9800 OpcP, RegOpc(src2), Pop_Mem_DPR(dst) ); |
| 0 | 9801 ins_pipe( fpu_mem_reg_reg ); |
| 9802 %} | |
| 9803 | |
| 9804 | |
|
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9805 instruct modDPR_reg(regDPR dst, regDPR src, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 9806 predicate(UseSSE<=1); |
| 9807 match(Set dst (ModD dst src)); | |
|
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9808 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS |
| 0 | 9809 |
| 9810 format %{ "DMOD $dst,$src" %} | |
| 9811 ins_cost(250); | |
|
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9812 ins_encode(Push_Reg_Mod_DPR(dst, src), |
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9813 emitModDPR(), |
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9814 Push_Result_Mod_DPR(src), |
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9815 Pop_Reg_DPR(dst)); |
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9816 ins_pipe( pipe_slow ); |
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9817 %} |
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9818 |
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9819 instruct modD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 9820 predicate(UseSSE>=2); |
| 9821 match(Set dst (ModD src0 src1)); | |
| 9822 effect(KILL rax, KILL cr); | |
| 9823 | |
| 9824 format %{ "SUB ESP,8\t # DMOD\n" | |
| 9825 "\tMOVSD [ESP+0],$src1\n" | |
| 9826 "\tFLD_D [ESP+0]\n" | |
| 9827 "\tMOVSD [ESP+0],$src0\n" | |
| 9828 "\tFLD_D [ESP+0]\n" | |
| 9829 "loop:\tFPREM\n" | |
| 9830 "\tFWAIT\n" | |
| 9831 "\tFNSTSW AX\n" | |
| 9832 "\tSAHF\n" | |
| 9833 "\tJP loop\n" | |
| 9834 "\tFSTP_D [ESP+0]\n" | |
| 9835 "\tMOVSD $dst,[ESP+0]\n" | |
| 9836 "\tADD ESP,8\n" | |
| 9837 "\tFSTP ST0\t # Restore FPU Stack" | |
| 9838 %} | |
| 9839 ins_cost(250); | |
|
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9840 ins_encode( Push_ModD_encoding(src0, src1), emitModDPR(), Push_ResultD(dst), PopFPU); |
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9841 ins_pipe( pipe_slow ); |
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9842 %} |
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9843 |
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9844 instruct sinDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9845 predicate (UseSSE<=1); |
| 9846 match(Set dst (SinD src)); | |
| 9847 ins_cost(1800); | |
| 9848 format %{ "DSIN $dst" %} | |
| 9849 opcode(0xD9, 0xFE); | |
| 9850 ins_encode( OpcP, OpcS ); | |
| 9851 ins_pipe( pipe_slow ); | |
| 9852 %} | |
| 9853 | |
|
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9854 instruct sinD_reg(regD dst, eFlagsReg cr) %{ |
| 0 | 9855 predicate (UseSSE>=2); |
| 9856 match(Set dst (SinD dst)); | |
|
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9857 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8" |
| 0 | 9858 ins_cost(1800); |
| 9859 format %{ "DSIN $dst" %} | |
| 9860 opcode(0xD9, 0xFE); | |
|
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4759
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changeset
|
9861 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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changeset
|
9862 ins_pipe( pipe_slow ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
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diff
changeset
|
9863 %} |
|
65149e74c706
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diff
changeset
|
9864 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
9865 instruct cosDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9866 predicate (UseSSE<=1); |
| 9867 match(Set dst (CosD src)); | |
| 9868 ins_cost(1800); | |
| 9869 format %{ "DCOS $dst" %} | |
| 9870 opcode(0xD9, 0xFF); | |
| 9871 ins_encode( OpcP, OpcS ); | |
| 9872 ins_pipe( pipe_slow ); | |
| 9873 %} | |
| 9874 | |
|
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65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
9875 instruct cosD_reg(regD dst, eFlagsReg cr) %{ |
| 0 | 9876 predicate (UseSSE>=2); |
| 9877 match(Set dst (CosD dst)); | |
|
4761
65149e74c706
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diff
changeset
|
9878 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8" |
| 0 | 9879 ins_cost(1800); |
| 9880 format %{ "DCOS $dst" %} | |
| 9881 opcode(0xD9, 0xFF); | |
|
4761
65149e74c706
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diff
changeset
|
9882 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) ); |
|
65149e74c706
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changeset
|
9883 ins_pipe( pipe_slow ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
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diff
changeset
|
9884 %} |
|
65149e74c706
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kvn
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diff
changeset
|
9885 |
|
65149e74c706
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diff
changeset
|
9886 instruct tanDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9887 predicate (UseSSE<=1); |
| 9888 match(Set dst(TanD src)); | |
| 9889 format %{ "DTAN $dst" %} | |
| 9890 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan | |
| 9891 Opcode(0xDD), Opcode(0xD8)); // fstp st | |
| 9892 ins_pipe( pipe_slow ); | |
| 9893 %} | |
| 9894 | |
|
4761
65149e74c706
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diff
changeset
|
9895 instruct tanD_reg(regD dst, eFlagsReg cr) %{ |
| 0 | 9896 predicate (UseSSE>=2); |
| 9897 match(Set dst(TanD dst)); | |
|
4761
65149e74c706
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4759
diff
changeset
|
9898 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8" |
| 0 | 9899 format %{ "DTAN $dst" %} |
|
4761
65149e74c706
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4759
diff
changeset
|
9900 ins_encode( Push_SrcD(dst), |
| 0 | 9901 Opcode(0xD9), Opcode(0xF2), // fptan |
| 9902 Opcode(0xDD), Opcode(0xD8), // fstp st | |
|
4761
65149e74c706
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diff
changeset
|
9903 Push_ResultD(dst) ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
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diff
changeset
|
9904 ins_pipe( pipe_slow ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9905 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9906 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
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4759
diff
changeset
|
9907 instruct atanDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9908 predicate (UseSSE<=1); |
| 9909 match(Set dst(AtanD dst src)); | |
| 9910 format %{ "DATA $dst,$src" %} | |
| 9911 opcode(0xD9, 0xF3); | |
|
4761
65149e74c706
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diff
changeset
|
9912 ins_encode( Push_Reg_DPR(src), |
| 0 | 9913 OpcP, OpcS, RegOpc(dst) ); |
| 9914 ins_pipe( pipe_slow ); | |
| 9915 %} | |
| 9916 | |
|
4761
65149e74c706
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changeset
|
9917 instruct atanD_reg(regD dst, regD src, eFlagsReg cr) %{ |
| 0 | 9918 predicate (UseSSE>=2); |
| 9919 match(Set dst(AtanD dst src)); | |
|
4761
65149e74c706
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parents:
4759
diff
changeset
|
9920 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8" |
| 0 | 9921 format %{ "DATA $dst,$src" %} |
| 9922 opcode(0xD9, 0xF3); | |
|
4761
65149e74c706
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parents:
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diff
changeset
|
9923 ins_encode( Push_SrcD(src), |
|
65149e74c706
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diff
changeset
|
9924 OpcP, OpcS, Push_ResultD(dst) ); |
|
65149e74c706
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parents:
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changeset
|
9925 ins_pipe( pipe_slow ); |
|
65149e74c706
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kvn
parents:
4759
diff
changeset
|
9926 %} |
|
65149e74c706
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kvn
parents:
4759
diff
changeset
|
9927 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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parents:
4759
diff
changeset
|
9928 instruct sqrtDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9929 predicate (UseSSE<=1); |
| 9930 match(Set dst (SqrtD src)); | |
| 9931 format %{ "DSQRT $dst,$src" %} | |
| 9932 opcode(0xFA, 0xD9); | |
|
4761
65149e74c706
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parents:
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diff
changeset
|
9933 ins_encode( Push_Reg_DPR(src), |
|
65149e74c706
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changeset
|
9934 OpcS, OpcP, Pop_Reg_DPR(dst) ); |
|
65149e74c706
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parents:
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changeset
|
9935 ins_pipe( pipe_slow ); |
|
65149e74c706
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kvn
parents:
4759
diff
changeset
|
9936 %} |
|
65149e74c706
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kvn
parents:
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diff
changeset
|
9937 |
|
6084
6759698e3140
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roland
parents:
5934
diff
changeset
|
9938 instruct powDPR_reg(regDPR X, regDPR1 Y, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{ |
| 0 | 9939 predicate (UseSSE<=1); |
| 9940 match(Set Y (PowD X Y)); // Raise X to the Yth power | |
|
6084
6759698e3140
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roland
parents:
5934
diff
changeset
|
9941 effect(KILL rax, KILL rdx, KILL rcx, KILL cr); |
|
6759698e3140
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roland
parents:
5934
diff
changeset
|
9942 format %{ "fast_pow $X $Y -> $Y // KILL $rax, $rcx, $rdx" %} |
|
6759698e3140
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roland
parents:
5934
diff
changeset
|
9943 ins_encode %{ |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9944 __ subptr(rsp, 8); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9945 __ fld_s($X$$reg - 1); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9946 __ fast_pow(); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9947 __ addptr(rsp, 8); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9948 %} |
|
6759698e3140
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roland
parents:
5934
diff
changeset
|
9949 ins_pipe( pipe_slow ); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9950 %} |
|
6759698e3140
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roland
parents:
5934
diff
changeset
|
9951 |
|
6759698e3140
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roland
parents:
5934
diff
changeset
|
9952 instruct powD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{ |
| 0 | 9953 predicate (UseSSE>=2); |
| 9954 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power | |
|
6084
6759698e3140
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roland
parents:
5934
diff
changeset
|
9955 effect(KILL rax, KILL rdx, KILL rcx, KILL cr); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9956 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9957 ins_encode %{ |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9958 __ subptr(rsp, 8); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9959 __ movdbl(Address(rsp, 0), $src1$$XMMRegister); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9960 __ fld_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9961 __ movdbl(Address(rsp, 0), $src0$$XMMRegister); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9962 __ fld_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9963 __ fast_pow(); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9964 __ fstp_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9965 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9966 __ addptr(rsp, 8); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9967 %} |
|
6759698e3140
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roland
parents:
5934
diff
changeset
|
9968 ins_pipe( pipe_slow ); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9969 %} |
|
6759698e3140
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roland
parents:
5934
diff
changeset
|
9970 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9971 |
|
6759698e3140
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roland
parents:
5934
diff
changeset
|
9972 instruct expDPR_reg(regDPR1 dpr1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{ |
| 0 | 9973 predicate (UseSSE<=1); |
| 9974 match(Set dpr1 (ExpD dpr1)); | |
|
6084
6759698e3140
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roland
parents:
5934
diff
changeset
|
9975 effect(KILL rax, KILL rcx, KILL rdx, KILL cr); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9976 format %{ "fast_exp $dpr1 -> $dpr1 // KILL $rax, $rcx, $rdx" %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9977 ins_encode %{ |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9978 __ fast_exp(); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9979 %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9980 ins_pipe( pipe_slow ); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9981 %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9982 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9983 instruct expD_reg(regD dst, regD src, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{ |
| 0 | 9984 predicate (UseSSE>=2); |
| 9985 match(Set dst (ExpD src)); | |
|
6084
6759698e3140
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roland
parents:
5934
diff
changeset
|
9986 effect(KILL rax, KILL rcx, KILL rdx, KILL cr); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9987 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9988 ins_encode %{ |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9989 __ subptr(rsp, 8); |
|
6759698e3140
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roland
parents:
5934
diff
changeset
|
9990 __ movdbl(Address(rsp, 0), $src$$XMMRegister); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9991 __ fld_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9992 __ fast_exp(); |
|
6759698e3140
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roland
parents:
5934
diff
changeset
|
9993 __ fstp_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9994 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9995 __ addptr(rsp, 8); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9996 %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9997 ins_pipe( pipe_slow ); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9998 %} |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9999 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
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diff
changeset
|
10000 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 10001 predicate (UseSSE<=1); |
| 10002 // The source Double operand on FPU stack | |
| 10003 match(Set dst (Log10D src)); | |
| 10004 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number | |
| 10005 // fxch ; swap ST(0) with ST(1) | |
| 10006 // fyl2x ; compute log_10(2) * log_2(x) | |
| 10007 format %{ "FLDLG2 \t\t\t#Log10\n\t" | |
| 10008 "FXCH \n\t" | |
| 10009 "FYL2X \t\t\t# Q=Log10*Log_2(x)" | |
| 10010 %} | |
| 10011 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2 | |
| 10012 Opcode(0xD9), Opcode(0xC9), // fxch | |
| 10013 Opcode(0xD9), Opcode(0xF1)); // fyl2x | |
| 10014 | |
| 10015 ins_pipe( pipe_slow ); | |
| 10016 %} | |
| 10017 | |
|
4761
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diff
changeset
|
10018 instruct log10D_reg(regD dst, regD src, eFlagsReg cr) %{ |
| 0 | 10019 predicate (UseSSE>=2); |
| 10020 effect(KILL cr); | |
| 10021 match(Set dst (Log10D src)); | |
| 10022 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number | |
| 10023 // fyl2x ; compute log_10(2) * log_2(x) | |
| 10024 format %{ "FLDLG2 \t\t\t#Log10\n\t" | |
| 10025 "FYL2X \t\t\t# Q=Log10*Log_2(x)" | |
| 10026 %} | |
| 10027 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2 | |
|
4761
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4759
diff
changeset
|
10028 Push_SrcD(src), |
| 0 | 10029 Opcode(0xD9), Opcode(0xF1), // fyl2x |
|
4761
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kvn
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4759
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changeset
|
10030 Push_ResultD(dst)); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
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4759
diff
changeset
|
10031 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
10032 ins_pipe( pipe_slow ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
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10033 %} |
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10034 |
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10035 instruct logDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 10036 predicate (UseSSE<=1); |
| 10037 // The source Double operand on FPU stack | |
| 10038 match(Set dst (LogD src)); | |
| 10039 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number | |
| 10040 // fxch ; swap ST(0) with ST(1) | |
| 10041 // fyl2x ; compute log_e(2) * log_2(x) | |
| 10042 format %{ "FLDLN2 \t\t\t#Log_e\n\t" | |
| 10043 "FXCH \n\t" | |
| 10044 "FYL2X \t\t\t# Q=Log_e*Log_2(x)" | |
| 10045 %} | |
| 10046 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 | |
| 10047 Opcode(0xD9), Opcode(0xC9), // fxch | |
| 10048 Opcode(0xD9), Opcode(0xF1)); // fyl2x | |
| 10049 | |
| 10050 ins_pipe( pipe_slow ); | |
| 10051 %} | |
| 10052 | |
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10053 instruct logD_reg(regD dst, regD src, eFlagsReg cr) %{ |
| 0 | 10054 predicate (UseSSE>=2); |
| 10055 effect(KILL cr); | |
| 10056 // The source and result Double operands in XMM registers | |
| 10057 match(Set dst (LogD src)); | |
| 10058 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number | |
| 10059 // fyl2x ; compute log_e(2) * log_2(x) | |
| 10060 format %{ "FLDLN2 \t\t\t#Log_e\n\t" | |
| 10061 "FYL2X \t\t\t# Q=Log_e*Log_2(x)" | |
| 10062 %} | |
| 10063 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 | |
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10064 Push_SrcD(src), |
| 0 | 10065 Opcode(0xD9), Opcode(0xF1), // fyl2x |
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10066 Push_ResultD(dst)); |
| 0 | 10067 ins_pipe( pipe_slow ); |
| 10068 %} | |
| 10069 | |
| 10070 //-------------Float Instructions------------------------------- | |
| 10071 // Float Math | |
| 10072 | |
| 10073 // Code for float compare: | |
| 10074 // fcompp(); | |
| 10075 // fwait(); fnstsw_ax(); | |
| 10076 // sahf(); | |
| 10077 // movl(dst, unordered_result); | |
| 10078 // jcc(Assembler::parity, exit); | |
| 10079 // movl(dst, less_result); | |
| 10080 // jcc(Assembler::below, exit); | |
| 10081 // movl(dst, equal_result); | |
| 10082 // jcc(Assembler::equal, exit); | |
| 10083 // movl(dst, greater_result); | |
| 10084 // exit: | |
| 10085 | |
| 10086 // P6 version of float compare, sets condition codes in EFLAGS | |
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10087 instruct cmpFPR_cc_P6(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{ |
| 0 | 10088 predicate(VM_Version::supports_cmov() && UseSSE == 0); |
| 10089 match(Set cr (CmpF src1 src2)); | |
| 10090 effect(KILL rax); | |
| 10091 ins_cost(150); | |
| 10092 format %{ "FLD $src1\n\t" | |
| 10093 "FUCOMIP ST,$src2 // P6 instruction\n\t" | |
| 10094 "JNP exit\n\t" | |
| 10095 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t" | |
| 10096 "SAHF\n" | |
| 10097 "exit:\tNOP // avoid branch to branch" %} | |
| 10098 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ | |
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10099 ins_encode( Push_Reg_DPR(src1), |
| 0 | 10100 OpcP, RegOpc(src2), |
| 10101 cmpF_P6_fixup ); | |
| 10102 ins_pipe( pipe_slow ); | |
| 10103 %} | |
| 10104 | |
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10105 instruct cmpFPR_cc_P6CF(eFlagsRegUCF cr, regFPR src1, regFPR src2) %{ |
|
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10106 predicate(VM_Version::supports_cmov() && UseSSE == 0); |
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10107 match(Set cr (CmpF src1 src2)); |
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10108 ins_cost(100); |
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10109 format %{ "FLD $src1\n\t" |
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10110 "FUCOMIP ST,$src2 // P6 instruction" %} |
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10111 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ |
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10112 ins_encode( Push_Reg_DPR(src1), |
|
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10113 OpcP, RegOpc(src2)); |
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10114 ins_pipe( pipe_slow ); |
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10115 %} |
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10116 |
| 0 | 10117 |
| 10118 // Compare & branch | |
|
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10119 instruct cmpFPR_cc(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{ |
| 0 | 10120 predicate(UseSSE == 0); |
| 10121 match(Set cr (CmpF src1 src2)); | |
| 10122 effect(KILL rax); | |
| 10123 ins_cost(200); | |
| 10124 format %{ "FLD $src1\n\t" | |
| 10125 "FCOMp $src2\n\t" | |
| 10126 "FNSTSW AX\n\t" | |
| 10127 "TEST AX,0x400\n\t" | |
| 10128 "JZ,s flags\n\t" | |
| 10129 "MOV AH,1\t# unordered treat as LT\n" | |
| 10130 "flags:\tSAHF" %} | |
| 10131 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
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10132 ins_encode( Push_Reg_DPR(src1), |
| 0 | 10133 OpcP, RegOpc(src2), |
| 10134 fpu_flags); | |
| 10135 ins_pipe( pipe_slow ); | |
| 10136 %} | |
| 10137 | |
| 10138 // Compare vs zero into -1,0,1 | |
|
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10139 instruct cmpFPR_0(rRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 10140 predicate(UseSSE == 0); |
| 10141 match(Set dst (CmpF3 src1 zero)); | |
| 10142 effect(KILL cr, KILL rax); | |
| 10143 ins_cost(280); | |
| 10144 format %{ "FTSTF $dst,$src1" %} | |
| 10145 opcode(0xE4, 0xD9); | |
|
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10146 ins_encode( Push_Reg_DPR(src1), |
| 0 | 10147 OpcS, OpcP, PopFPU, |
| 10148 CmpF_Result(dst)); | |
| 10149 ins_pipe( pipe_slow ); | |
| 10150 %} | |
| 10151 | |
| 10152 // Compare into -1,0,1 | |
|
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10153 instruct cmpFPR_reg(rRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 10154 predicate(UseSSE == 0); |
| 10155 match(Set dst (CmpF3 src1 src2)); | |
| 10156 effect(KILL cr, KILL rax); | |
| 10157 ins_cost(300); | |
| 10158 format %{ "FCMPF $dst,$src1,$src2" %} | |
| 10159 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
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10160 ins_encode( Push_Reg_DPR(src1), |
| 0 | 10161 OpcP, RegOpc(src2), |
| 10162 CmpF_Result(dst)); | |
| 10163 ins_pipe( pipe_slow ); | |
| 10164 %} | |
| 10165 | |
| 10166 // float compare and set condition codes in EFLAGS by XMM regs | |
|
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10167 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2) %{ |
| 0 | 10168 predicate(UseSSE>=1); |
| 4759 | 10169 match(Set cr (CmpF src1 src2)); |
| 0 | 10170 ins_cost(145); |
| 4759 | 10171 format %{ "UCOMISS $src1,$src2\n\t" |
| 10172 "JNP,s exit\n\t" | |
| 10173 "PUSHF\t# saw NaN, set CF\n\t" | |
| 10174 "AND [rsp], #0xffffff2b\n\t" | |
| 10175 "POPF\n" | |
| 10176 "exit:" %} | |
| 10177 ins_encode %{ | |
| 10178 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); | |
| 10179 emit_cmpfp_fixup(_masm); | |
| 10180 %} | |
| 10181 ins_pipe( pipe_slow ); | |
| 10182 %} | |
| 10183 | |
|
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10184 instruct cmpF_ccCF(eFlagsRegUCF cr, regF src1, regF src2) %{ |
|
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10185 predicate(UseSSE>=1); |
| 4759 | 10186 match(Set cr (CmpF src1 src2)); |
|
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10187 ins_cost(100); |
| 4759 | 10188 format %{ "UCOMISS $src1,$src2" %} |
| 10189 ins_encode %{ | |
| 10190 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); | |
| 10191 %} | |
|
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10192 ins_pipe( pipe_slow ); |
|
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10193 %} |
|
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10194 |
| 0 | 10195 // float compare and set condition codes in EFLAGS by XMM regs |
|
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10196 instruct cmpF_ccmem(eFlagsRegU cr, regF src1, memory src2) %{ |
| 0 | 10197 predicate(UseSSE>=1); |
| 4759 | 10198 match(Set cr (CmpF src1 (LoadF src2))); |
| 0 | 10199 ins_cost(165); |
| 4759 | 10200 format %{ "UCOMISS $src1,$src2\n\t" |
| 10201 "JNP,s exit\n\t" | |
| 10202 "PUSHF\t# saw NaN, set CF\n\t" | |
| 10203 "AND [rsp], #0xffffff2b\n\t" | |
| 10204 "POPF\n" | |
| 10205 "exit:" %} | |
| 10206 ins_encode %{ | |
| 10207 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 10208 emit_cmpfp_fixup(_masm); | |
| 10209 %} | |
| 10210 ins_pipe( pipe_slow ); | |
| 10211 %} | |
| 10212 | |
|
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10213 instruct cmpF_ccmemCF(eFlagsRegUCF cr, regF src1, memory src2) %{ |
|
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10214 predicate(UseSSE>=1); |
| 4759 | 10215 match(Set cr (CmpF src1 (LoadF src2))); |
|
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10216 ins_cost(100); |
| 4759 | 10217 format %{ "UCOMISS $src1,$src2" %} |
| 10218 ins_encode %{ | |
| 10219 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 10220 %} | |
|
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|
10221 ins_pipe( pipe_slow ); |
|
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|
10222 %} |
|
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|
10223 |
| 0 | 10224 // Compare into -1,0,1 in XMM |
|
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10225 instruct cmpF_reg(xRegI dst, regF src1, regF src2, eFlagsReg cr) %{ |
| 0 | 10226 predicate(UseSSE>=1); |
| 10227 match(Set dst (CmpF3 src1 src2)); | |
| 10228 effect(KILL cr); | |
| 10229 ins_cost(255); | |
| 4759 | 10230 format %{ "UCOMISS $src1, $src2\n\t" |
| 10231 "MOV $dst, #-1\n\t" | |
| 10232 "JP,s done\n\t" | |
| 10233 "JB,s done\n\t" | |
| 10234 "SETNE $dst\n\t" | |
| 10235 "MOVZB $dst, $dst\n" | |
| 10236 "done:" %} | |
| 10237 ins_encode %{ | |
| 10238 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); | |
| 10239 emit_cmpfp3(_masm, $dst$$Register); | |
| 10240 %} | |
| 0 | 10241 ins_pipe( pipe_slow ); |
| 10242 %} | |
| 10243 | |
| 10244 // Compare into -1,0,1 in XMM and memory | |
|
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10245 instruct cmpF_regmem(xRegI dst, regF src1, memory src2, eFlagsReg cr) %{ |
| 0 | 10246 predicate(UseSSE>=1); |
| 4759 | 10247 match(Set dst (CmpF3 src1 (LoadF src2))); |
| 0 | 10248 effect(KILL cr); |
| 10249 ins_cost(275); | |
| 4759 | 10250 format %{ "UCOMISS $src1, $src2\n\t" |
| 10251 "MOV $dst, #-1\n\t" | |
| 10252 "JP,s done\n\t" | |
| 10253 "JB,s done\n\t" | |
| 10254 "SETNE $dst\n\t" | |
| 10255 "MOVZB $dst, $dst\n" | |
| 10256 "done:" %} | |
| 10257 ins_encode %{ | |
| 10258 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 10259 emit_cmpfp3(_masm, $dst$$Register); | |
| 10260 %} | |
| 0 | 10261 ins_pipe( pipe_slow ); |
| 10262 %} | |
| 10263 | |
| 10264 // Spill to obtain 24-bit precision | |
|
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10265 instruct subFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{ |
| 0 | 10266 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10267 match(Set dst (SubF src1 src2)); | |
| 10268 | |
| 10269 format %{ "FSUB $dst,$src1 - $src2" %} | |
| 10270 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */ | |
|
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10271 ins_encode( Push_Reg_FPR(src1), |
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10272 OpcReg_FPR(src2), |
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10273 Pop_Mem_FPR(dst) ); |
| 0 | 10274 ins_pipe( fpu_mem_reg_reg ); |
| 10275 %} | |
| 10276 // | |
| 10277 // This instruction does not round to 24-bits | |
|
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10278 instruct subFPR_reg(regFPR dst, regFPR src) %{ |
| 0 | 10279 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10280 match(Set dst (SubF dst src)); | |
| 10281 | |
| 10282 format %{ "FSUB $dst,$src" %} | |
| 10283 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */ | |
|
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10284 ins_encode( Push_Reg_FPR(src), |
| 0 | 10285 OpcP, RegOpc(dst) ); |
| 10286 ins_pipe( fpu_reg_reg ); | |
| 10287 %} | |
| 10288 | |
| 10289 // Spill to obtain 24-bit precision | |
|
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10290 instruct addFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{ |
| 0 | 10291 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10292 match(Set dst (AddF src1 src2)); | |
| 10293 | |
| 10294 format %{ "FADD $dst,$src1,$src2" %} | |
| 10295 opcode(0xD8, 0x0); /* D8 C0+i */ | |
|
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10296 ins_encode( Push_Reg_FPR(src2), |
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10297 OpcReg_FPR(src1), |
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10298 Pop_Mem_FPR(dst) ); |
| 0 | 10299 ins_pipe( fpu_mem_reg_reg ); |
| 10300 %} | |
| 10301 // | |
| 10302 // This instruction does not round to 24-bits | |
|
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10303 instruct addFPR_reg(regFPR dst, regFPR src) %{ |
| 0 | 10304 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10305 match(Set dst (AddF dst src)); | |
| 10306 | |
| 10307 format %{ "FLD $src\n\t" | |
| 10308 "FADDp $dst,ST" %} | |
| 10309 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/ | |
|
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10310 ins_encode( Push_Reg_FPR(src), |
| 0 | 10311 OpcP, RegOpc(dst) ); |
| 10312 ins_pipe( fpu_reg_reg ); | |
| 10313 %} | |
| 10314 | |
|
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10315 instruct absFPR_reg(regFPR1 dst, regFPR1 src) %{ |
| 0 | 10316 predicate(UseSSE==0); |
| 10317 match(Set dst (AbsF src)); | |
| 10318 ins_cost(100); | |
| 10319 format %{ "FABS" %} | |
| 10320 opcode(0xE1, 0xD9); | |
| 10321 ins_encode( OpcS, OpcP ); | |
| 10322 ins_pipe( fpu_reg_reg ); | |
| 10323 %} | |
| 10324 | |
|
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10325 instruct negFPR_reg(regFPR1 dst, regFPR1 src) %{ |
| 0 | 10326 predicate(UseSSE==0); |
| 10327 match(Set dst (NegF src)); | |
| 10328 ins_cost(100); | |
| 10329 format %{ "FCHS" %} | |
| 10330 opcode(0xE0, 0xD9); | |
| 10331 ins_encode( OpcS, OpcP ); | |
| 10332 ins_pipe( fpu_reg_reg ); | |
| 10333 %} | |
| 10334 | |
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10335 // Cisc-alternate to addFPR_reg |
| 0 | 10336 // Spill to obtain 24-bit precision |
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10337 instruct addFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{ |
| 0 | 10338 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10339 match(Set dst (AddF src1 (LoadF src2))); | |
| 10340 | |
| 10341 format %{ "FLD $src2\n\t" | |
| 10342 "FADD ST,$src1\n\t" | |
| 10343 "FSTP_S $dst" %} | |
| 10344 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ | |
| 10345 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
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10346 OpcReg_FPR(src1), |
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10347 Pop_Mem_FPR(dst) ); |
| 0 | 10348 ins_pipe( fpu_mem_reg_mem ); |
| 10349 %} | |
| 10350 // | |
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10351 // Cisc-alternate to addFPR_reg |
| 0 | 10352 // This instruction does not round to 24-bits |
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10353 instruct addFPR_reg_mem(regFPR dst, memory src) %{ |
| 0 | 10354 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10355 match(Set dst (AddF dst (LoadF src))); | |
| 10356 | |
| 10357 format %{ "FADD $dst,$src" %} | |
| 10358 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */ | |
| 10359 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 10360 OpcP, RegOpc(dst) ); | |
| 10361 ins_pipe( fpu_reg_mem ); | |
| 10362 %} | |
| 10363 | |
| 10364 // // Following two instructions for _222_mpegaudio | |
| 10365 // Spill to obtain 24-bit precision | |
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10366 instruct addFPR24_mem_reg(stackSlotF dst, regFPR src2, memory src1 ) %{ |
| 0 | 10367 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10368 match(Set dst (AddF src1 src2)); | |
| 10369 | |
| 10370 format %{ "FADD $dst,$src1,$src2" %} | |
| 10371 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ | |
| 10372 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1), | |
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10373 OpcReg_FPR(src2), |
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10374 Pop_Mem_FPR(dst) ); |
| 0 | 10375 ins_pipe( fpu_mem_reg_mem ); |
| 10376 %} | |
| 10377 | |
| 10378 // Cisc-spill variant | |
| 10379 // Spill to obtain 24-bit precision | |
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10380 instruct addFPR24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{ |
| 0 | 10381 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10382 match(Set dst (AddF src1 (LoadF src2))); | |
| 10383 | |
| 10384 format %{ "FADD $dst,$src1,$src2 cisc" %} | |
| 10385 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ | |
| 10386 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 10387 set_instruction_start, | |
| 10388 OpcP, RMopc_Mem(secondary,src1), | |
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10389 Pop_Mem_FPR(dst) ); |
| 0 | 10390 ins_pipe( fpu_mem_mem_mem ); |
| 10391 %} | |
| 10392 | |
| 10393 // Spill to obtain 24-bit precision | |
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10394 instruct addFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{ |
| 0 | 10395 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10396 match(Set dst (AddF src1 src2)); | |
| 10397 | |
| 10398 format %{ "FADD $dst,$src1,$src2" %} | |
| 10399 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */ | |
| 10400 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 10401 set_instruction_start, | |
| 10402 OpcP, RMopc_Mem(secondary,src1), | |
|
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10403 Pop_Mem_FPR(dst) ); |
| 0 | 10404 ins_pipe( fpu_mem_mem_mem ); |
| 10405 %} | |
| 10406 | |
| 10407 | |
| 10408 // Spill to obtain 24-bit precision | |
|
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10409 instruct addFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{ |
| 0 | 10410 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 2008 | 10411 match(Set dst (AddF src con)); |
| 10412 format %{ "FLD $src\n\t" | |
| 10413 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 0 | 10414 "FSTP_S $dst" %} |
| 2008 | 10415 ins_encode %{ |
| 10416 __ fld_s($src$$reg - 1); // FLD ST(i-1) | |
| 10417 __ fadd_s($constantaddress($con)); | |
| 10418 __ fstp_s(Address(rsp, $dst$$disp)); | |
| 10419 %} | |
| 10420 ins_pipe(fpu_mem_reg_con); | |
| 0 | 10421 %} |
| 10422 // | |
| 10423 // This instruction does not round to 24-bits | |
|
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10424 instruct addFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{ |
| 0 | 10425 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 2008 | 10426 match(Set dst (AddF src con)); |
| 10427 format %{ "FLD $src\n\t" | |
| 10428 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 10429 "FSTP $dst" %} | |
| 10430 ins_encode %{ | |
| 10431 __ fld_s($src$$reg - 1); // FLD ST(i-1) | |
| 10432 __ fadd_s($constantaddress($con)); | |
| 10433 __ fstp_d($dst$$reg); | |
| 10434 %} | |
| 10435 ins_pipe(fpu_reg_reg_con); | |
| 0 | 10436 %} |
| 10437 | |
| 10438 // Spill to obtain 24-bit precision | |
|
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10439 instruct mulFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{ |
| 0 | 10440 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10441 match(Set dst (MulF src1 src2)); | |
| 10442 | |
| 10443 format %{ "FLD $src1\n\t" | |
| 10444 "FMUL $src2\n\t" | |
| 10445 "FSTP_S $dst" %} | |
| 10446 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */ | |
|
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10447 ins_encode( Push_Reg_FPR(src1), |
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10448 OpcReg_FPR(src2), |
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10449 Pop_Mem_FPR(dst) ); |
| 0 | 10450 ins_pipe( fpu_mem_reg_reg ); |
| 10451 %} | |
| 10452 // | |
| 10453 // This instruction does not round to 24-bits | |
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10454 instruct mulFPR_reg(regFPR dst, regFPR src1, regFPR src2) %{ |
| 0 | 10455 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10456 match(Set dst (MulF src1 src2)); | |
| 10457 | |
| 10458 format %{ "FLD $src1\n\t" | |
| 10459 "FMUL $src2\n\t" | |
| 10460 "FSTP_S $dst" %} | |
| 10461 opcode(0xD8, 0x1); /* D8 C8+i */ | |
|
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10462 ins_encode( Push_Reg_FPR(src2), |
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10463 OpcReg_FPR(src1), |
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10464 Pop_Reg_FPR(dst) ); |
| 0 | 10465 ins_pipe( fpu_reg_reg_reg ); |
| 10466 %} | |
| 10467 | |
| 10468 | |
| 10469 // Spill to obtain 24-bit precision | |
| 10470 // Cisc-alternate to reg-reg multiply | |
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10471 instruct mulFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{ |
| 0 | 10472 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10473 match(Set dst (MulF src1 (LoadF src2))); | |
| 10474 | |
| 10475 format %{ "FLD_S $src2\n\t" | |
| 10476 "FMUL $src1\n\t" | |
| 10477 "FSTP_S $dst" %} | |
| 10478 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */ | |
| 10479 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
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10480 OpcReg_FPR(src1), |
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10481 Pop_Mem_FPR(dst) ); |
| 0 | 10482 ins_pipe( fpu_mem_reg_mem ); |
| 10483 %} | |
| 10484 // | |
| 10485 // This instruction does not round to 24-bits | |
| 10486 // Cisc-alternate to reg-reg multiply | |
|
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10487 instruct mulFPR_reg_mem(regFPR dst, regFPR src1, memory src2) %{ |
| 0 | 10488 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10489 match(Set dst (MulF src1 (LoadF src2))); | |
| 10490 | |
| 10491 format %{ "FMUL $dst,$src1,$src2" %} | |
| 10492 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */ | |
| 10493 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
|
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10494 OpcReg_FPR(src1), |
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10495 Pop_Reg_FPR(dst) ); |
| 0 | 10496 ins_pipe( fpu_reg_reg_mem ); |
| 10497 %} | |
| 10498 | |
| 10499 // Spill to obtain 24-bit precision | |
|
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10500 instruct mulFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{ |
| 0 | 10501 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10502 match(Set dst (MulF src1 src2)); | |
| 10503 | |
| 10504 format %{ "FMUL $dst,$src1,$src2" %} | |
| 10505 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */ | |
| 10506 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 10507 set_instruction_start, | |
| 10508 OpcP, RMopc_Mem(secondary,src1), | |
|
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10509 Pop_Mem_FPR(dst) ); |
| 0 | 10510 ins_pipe( fpu_mem_mem_mem ); |
| 10511 %} | |
| 10512 | |
| 10513 // Spill to obtain 24-bit precision | |
|
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10514 instruct mulFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{ |
| 0 | 10515 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 2008 | 10516 match(Set dst (MulF src con)); |
| 10517 | |
| 10518 format %{ "FLD $src\n\t" | |
| 10519 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 10520 "FSTP_S $dst" %} | |
| 10521 ins_encode %{ | |
| 10522 __ fld_s($src$$reg - 1); // FLD ST(i-1) | |
| 10523 __ fmul_s($constantaddress($con)); | |
| 10524 __ fstp_s(Address(rsp, $dst$$disp)); | |
| 10525 %} | |
| 10526 ins_pipe(fpu_mem_reg_con); | |
| 0 | 10527 %} |
| 10528 // | |
| 10529 // This instruction does not round to 24-bits | |
|
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10530 instruct mulFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{ |
| 0 | 10531 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 2008 | 10532 match(Set dst (MulF src con)); |
| 10533 | |
| 10534 format %{ "FLD $src\n\t" | |
| 10535 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 10536 "FSTP $dst" %} | |
| 10537 ins_encode %{ | |
| 10538 __ fld_s($src$$reg - 1); // FLD ST(i-1) | |
| 10539 __ fmul_s($constantaddress($con)); | |
| 10540 __ fstp_d($dst$$reg); | |
| 10541 %} | |
| 10542 ins_pipe(fpu_reg_reg_con); | |
| 0 | 10543 %} |
| 10544 | |
| 10545 | |
| 10546 // | |
|
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10547 // MACRO1 -- subsume unshared load into mulFPR |
| 0 | 10548 // This instruction does not round to 24-bits |
|
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10549 instruct mulFPR_reg_load1(regFPR dst, regFPR src, memory mem1 ) %{ |
| 0 | 10550 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10551 match(Set dst (MulF (LoadF mem1) src)); | |
| 10552 | |
| 10553 format %{ "FLD $mem1 ===MACRO1===\n\t" | |
| 10554 "FMUL ST,$src\n\t" | |
| 10555 "FSTP $dst" %} | |
| 10556 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */ | |
| 10557 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1), | |
|
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10558 OpcReg_FPR(src), |
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10559 Pop_Reg_FPR(dst) ); |
| 0 | 10560 ins_pipe( fpu_reg_reg_mem ); |
| 10561 %} | |
| 10562 // | |
|
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10563 // MACRO2 -- addFPR a mulFPR which subsumed an unshared load |
| 0 | 10564 // This instruction does not round to 24-bits |
|
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10565 instruct addFPR_mulFPR_reg_load1(regFPR dst, memory mem1, regFPR src1, regFPR src2) %{ |
| 0 | 10566 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10567 match(Set dst (AddF (MulF (LoadF mem1) src1) src2)); | |
| 10568 ins_cost(95); | |
| 10569 | |
| 10570 format %{ "FLD $mem1 ===MACRO2===\n\t" | |
|
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10571 "FMUL ST,$src1 subsume mulFPR left load\n\t" |
| 0 | 10572 "FADD ST,$src2\n\t" |
| 10573 "FSTP $dst" %} | |
| 10574 opcode(0xD9); /* LoadF D9 /0 */ | |
| 10575 ins_encode( OpcP, RMopc_Mem(0x00,mem1), | |
| 10576 FMul_ST_reg(src1), | |
| 10577 FAdd_ST_reg(src2), | |
|
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10578 Pop_Reg_FPR(dst) ); |
| 0 | 10579 ins_pipe( fpu_reg_mem_reg_reg ); |
| 10580 %} | |
| 10581 | |
|
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10582 // MACRO3 -- addFPR a mulFPR |
| 0 | 10583 // This instruction does not round to 24-bits. It is a '2-address' |
| 10584 // instruction in that the result goes back to src2. This eliminates | |
| 10585 // a move from the macro; possibly the register allocator will have | |
| 10586 // to add it back (and maybe not). | |
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10587 instruct addFPR_mulFPR_reg(regFPR src2, regFPR src1, regFPR src0) %{ |
| 0 | 10588 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10589 match(Set src2 (AddF (MulF src0 src1) src2)); | |
| 10590 | |
| 10591 format %{ "FLD $src0 ===MACRO3===\n\t" | |
| 10592 "FMUL ST,$src1\n\t" | |
| 10593 "FADDP $src2,ST" %} | |
| 10594 opcode(0xD9); /* LoadF D9 /0 */ | |
|
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10595 ins_encode( Push_Reg_FPR(src0), |
| 0 | 10596 FMul_ST_reg(src1), |
| 10597 FAddP_reg_ST(src2) ); | |
| 10598 ins_pipe( fpu_reg_reg_reg ); | |
| 10599 %} | |
| 10600 | |
|
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10601 // MACRO4 -- divFPR subFPR |
| 0 | 10602 // This instruction does not round to 24-bits |
|
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10603 instruct subFPR_divFPR_reg(regFPR dst, regFPR src1, regFPR src2, regFPR src3) %{ |
| 0 | 10604 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10605 match(Set dst (DivF (SubF src2 src1) src3)); | |
| 10606 | |
| 10607 format %{ "FLD $src2 ===MACRO4===\n\t" | |
| 10608 "FSUB ST,$src1\n\t" | |
| 10609 "FDIV ST,$src3\n\t" | |
| 10610 "FSTP $dst" %} | |
| 10611 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
|
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10612 ins_encode( Push_Reg_FPR(src2), |
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10613 subFPR_divFPR_encode(src1,src3), |
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10614 Pop_Reg_FPR(dst) ); |
| 0 | 10615 ins_pipe( fpu_reg_reg_reg_reg ); |
| 10616 %} | |
| 10617 | |
| 10618 // Spill to obtain 24-bit precision | |
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10619 instruct divFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{ |
| 0 | 10620 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10621 match(Set dst (DivF src1 src2)); | |
| 10622 | |
| 10623 format %{ "FDIV $dst,$src1,$src2" %} | |
| 10624 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/ | |
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10625 ins_encode( Push_Reg_FPR(src1), |
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10626 OpcReg_FPR(src2), |
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10627 Pop_Mem_FPR(dst) ); |
| 0 | 10628 ins_pipe( fpu_mem_reg_reg ); |
| 10629 %} | |
| 10630 // | |
| 10631 // This instruction does not round to 24-bits | |
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10632 instruct divFPR_reg(regFPR dst, regFPR src) %{ |
| 0 | 10633 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10634 match(Set dst (DivF dst src)); | |
| 10635 | |
| 10636 format %{ "FDIV $dst,$src" %} | |
| 10637 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
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10638 ins_encode( Push_Reg_FPR(src), |
| 0 | 10639 OpcP, RegOpc(dst) ); |
| 10640 ins_pipe( fpu_reg_reg ); | |
| 10641 %} | |
| 10642 | |
| 10643 | |
| 10644 // Spill to obtain 24-bit precision | |
|
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10645 instruct modFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 10646 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10647 match(Set dst (ModF src1 src2)); | |
|
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10648 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS |
| 0 | 10649 |
| 10650 format %{ "FMOD $dst,$src1,$src2" %} | |
|
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10651 ins_encode( Push_Reg_Mod_DPR(src1, src2), |
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10652 emitModDPR(), |
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10653 Push_Result_Mod_DPR(src2), |
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10654 Pop_Mem_FPR(dst)); |
| 0 | 10655 ins_pipe( pipe_slow ); |
| 10656 %} | |
| 10657 // | |
| 10658 // This instruction does not round to 24-bits | |
|
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10659 instruct modFPR_reg(regFPR dst, regFPR src, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 10660 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10661 match(Set dst (ModF dst src)); | |
|
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10662 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS |
| 0 | 10663 |
| 10664 format %{ "FMOD $dst,$src" %} | |
|
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10665 ins_encode(Push_Reg_Mod_DPR(dst, src), |
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10666 emitModDPR(), |
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10667 Push_Result_Mod_DPR(src), |
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10668 Pop_Reg_FPR(dst)); |
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10669 ins_pipe( pipe_slow ); |
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10670 %} |
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10671 |
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10672 instruct modF_reg(regF dst, regF src0, regF src1, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 10673 predicate(UseSSE>=1); |
| 10674 match(Set dst (ModF src0 src1)); | |
| 10675 effect(KILL rax, KILL cr); | |
| 10676 format %{ "SUB ESP,4\t # FMOD\n" | |
| 10677 "\tMOVSS [ESP+0],$src1\n" | |
| 10678 "\tFLD_S [ESP+0]\n" | |
| 10679 "\tMOVSS [ESP+0],$src0\n" | |
| 10680 "\tFLD_S [ESP+0]\n" | |
| 10681 "loop:\tFPREM\n" | |
| 10682 "\tFWAIT\n" | |
| 10683 "\tFNSTSW AX\n" | |
| 10684 "\tSAHF\n" | |
| 10685 "\tJP loop\n" | |
| 10686 "\tFSTP_S [ESP+0]\n" | |
| 10687 "\tMOVSS $dst,[ESP+0]\n" | |
| 10688 "\tADD ESP,4\n" | |
| 10689 "\tFSTP ST0\t # Restore FPU Stack" | |
| 10690 %} | |
| 10691 ins_cost(250); | |
|
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10692 ins_encode( Push_ModF_encoding(src0, src1), emitModDPR(), Push_ResultF(dst,0x4), PopFPU); |
| 0 | 10693 ins_pipe( pipe_slow ); |
| 10694 %} | |
| 10695 | |
| 10696 | |
| 10697 //----------Arithmetic Conversion Instructions--------------------------------- | |
| 10698 // The conversions operations are all Alpha sorted. Please keep it that way! | |
| 10699 | |
|
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10700 instruct roundFloat_mem_reg(stackSlotF dst, regFPR src) %{ |
| 0 | 10701 predicate(UseSSE==0); |
| 10702 match(Set dst (RoundFloat src)); | |
| 10703 ins_cost(125); | |
| 10704 format %{ "FST_S $dst,$src\t# F-round" %} | |
|
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10705 ins_encode( Pop_Mem_Reg_FPR(dst, src) ); |
| 0 | 10706 ins_pipe( fpu_mem_reg ); |
| 10707 %} | |
| 10708 | |
|
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10709 instruct roundDouble_mem_reg(stackSlotD dst, regDPR src) %{ |
| 0 | 10710 predicate(UseSSE<=1); |
| 10711 match(Set dst (RoundDouble src)); | |
| 10712 ins_cost(125); | |
| 10713 format %{ "FST_D $dst,$src\t# D-round" %} | |
|
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10714 ins_encode( Pop_Mem_Reg_DPR(dst, src) ); |
| 0 | 10715 ins_pipe( fpu_mem_reg ); |
| 10716 %} | |
| 10717 | |
| 10718 // Force rounding to 24-bit precision and 6-bit exponent | |
|
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10719 instruct convDPR2FPR_reg(stackSlotF dst, regDPR src) %{ |
| 0 | 10720 predicate(UseSSE==0); |
| 10721 match(Set dst (ConvD2F src)); | |
| 10722 format %{ "FST_S $dst,$src\t# F-round" %} | |
| 10723 expand %{ | |
| 10724 roundFloat_mem_reg(dst,src); | |
| 10725 %} | |
| 10726 %} | |
| 10727 | |
| 10728 // Force rounding to 24-bit precision and 6-bit exponent | |
|
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10729 instruct convDPR2F_reg(regF dst, regDPR src, eFlagsReg cr) %{ |
| 0 | 10730 predicate(UseSSE==1); |
| 10731 match(Set dst (ConvD2F src)); | |
| 10732 effect( KILL cr ); | |
| 10733 format %{ "SUB ESP,4\n\t" | |
| 10734 "FST_S [ESP],$src\t# F-round\n\t" | |
| 10735 "MOVSS $dst,[ESP]\n\t" | |
| 10736 "ADD ESP,4" %} | |
| 4759 | 10737 ins_encode %{ |
| 10738 __ subptr(rsp, 4); | |
| 10739 if ($src$$reg != FPR1L_enc) { | |
| 10740 __ fld_s($src$$reg-1); | |
| 10741 __ fstp_s(Address(rsp, 0)); | |
| 10742 } else { | |
| 10743 __ fst_s(Address(rsp, 0)); | |
| 10744 } | |
| 10745 __ movflt($dst$$XMMRegister, Address(rsp, 0)); | |
| 10746 __ addptr(rsp, 4); | |
| 10747 %} | |
| 0 | 10748 ins_pipe( pipe_slow ); |
| 10749 %} | |
| 10750 | |
| 10751 // Force rounding double precision to single precision | |
|
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10752 instruct convD2F_reg(regF dst, regD src) %{ |
| 0 | 10753 predicate(UseSSE>=2); |
| 10754 match(Set dst (ConvD2F src)); | |
| 10755 format %{ "CVTSD2SS $dst,$src\t# F-round" %} | |
| 4759 | 10756 ins_encode %{ |
| 10757 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister); | |
| 10758 %} | |
| 0 | 10759 ins_pipe( pipe_slow ); |
| 10760 %} | |
| 10761 | |
|
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10762 instruct convFPR2DPR_reg_reg(regDPR dst, regFPR src) %{ |
| 0 | 10763 predicate(UseSSE==0); |
| 10764 match(Set dst (ConvF2D src)); | |
| 10765 format %{ "FST_S $dst,$src\t# D-round" %} | |
|
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10766 ins_encode( Pop_Reg_Reg_DPR(dst, src)); |
| 0 | 10767 ins_pipe( fpu_reg_reg ); |
| 10768 %} | |
| 10769 | |
|
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10770 instruct convFPR2D_reg(stackSlotD dst, regFPR src) %{ |
| 0 | 10771 predicate(UseSSE==1); |
| 10772 match(Set dst (ConvF2D src)); | |
| 10773 format %{ "FST_D $dst,$src\t# D-round" %} | |
| 10774 expand %{ | |
| 10775 roundDouble_mem_reg(dst,src); | |
| 10776 %} | |
| 10777 %} | |
| 10778 | |
|
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10779 instruct convF2DPR_reg(regDPR dst, regF src, eFlagsReg cr) %{ |
| 0 | 10780 predicate(UseSSE==1); |
| 10781 match(Set dst (ConvF2D src)); | |
| 10782 effect( KILL cr ); | |
| 10783 format %{ "SUB ESP,4\n\t" | |
| 10784 "MOVSS [ESP] $src\n\t" | |
| 10785 "FLD_S [ESP]\n\t" | |
| 10786 "ADD ESP,4\n\t" | |
| 10787 "FSTP $dst\t# D-round" %} | |
| 4759 | 10788 ins_encode %{ |
| 10789 __ subptr(rsp, 4); | |
| 10790 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 10791 __ fld_s(Address(rsp, 0)); | |
| 10792 __ addptr(rsp, 4); | |
| 10793 __ fstp_d($dst$$reg); | |
| 10794 %} | |
| 0 | 10795 ins_pipe( pipe_slow ); |
| 10796 %} | |
| 10797 | |
|
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10798 instruct convF2D_reg(regD dst, regF src) %{ |
| 0 | 10799 predicate(UseSSE>=2); |
| 10800 match(Set dst (ConvF2D src)); | |
| 10801 format %{ "CVTSS2SD $dst,$src\t# D-round" %} | |
| 4759 | 10802 ins_encode %{ |
| 10803 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister); | |
| 10804 %} | |
| 0 | 10805 ins_pipe( pipe_slow ); |
| 10806 %} | |
| 10807 | |
| 10808 // Convert a double to an int. If the double is a NAN, stuff a zero in instead. | |
|
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10809 instruct convDPR2I_reg_reg( eAXRegI dst, eDXRegI tmp, regDPR src, eFlagsReg cr ) %{ |
| 0 | 10810 predicate(UseSSE<=1); |
| 10811 match(Set dst (ConvD2I src)); | |
| 10812 effect( KILL tmp, KILL cr ); | |
| 10813 format %{ "FLD $src\t# Convert double to int \n\t" | |
| 10814 "FLDCW trunc mode\n\t" | |
| 10815 "SUB ESP,4\n\t" | |
| 10816 "FISTp [ESP + #0]\n\t" | |
| 10817 "FLDCW std/24-bit mode\n\t" | |
| 10818 "POP EAX\n\t" | |
| 10819 "CMP EAX,0x80000000\n\t" | |
| 10820 "JNE,s fast\n\t" | |
| 10821 "FLD_D $src\n\t" | |
| 10822 "CALL d2i_wrapper\n" | |
| 10823 "fast:" %} | |
|
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10824 ins_encode( Push_Reg_DPR(src), DPR2I_encoding(src) ); |
| 0 | 10825 ins_pipe( pipe_slow ); |
| 10826 %} | |
| 10827 | |
| 10828 // Convert a double to an int. If the double is a NAN, stuff a zero in instead. | |
|
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10829 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{ |
| 0 | 10830 predicate(UseSSE>=2); |
| 10831 match(Set dst (ConvD2I src)); | |
| 10832 effect( KILL tmp, KILL cr ); | |
| 10833 format %{ "CVTTSD2SI $dst, $src\n\t" | |
| 10834 "CMP $dst,0x80000000\n\t" | |
| 10835 "JNE,s fast\n\t" | |
| 10836 "SUB ESP, 8\n\t" | |
| 10837 "MOVSD [ESP], $src\n\t" | |
| 10838 "FLD_D [ESP]\n\t" | |
| 10839 "ADD ESP, 8\n\t" | |
| 10840 "CALL d2i_wrapper\n" | |
| 10841 "fast:" %} | |
| 4759 | 10842 ins_encode %{ |
| 10843 Label fast; | |
| 10844 __ cvttsd2sil($dst$$Register, $src$$XMMRegister); | |
| 10845 __ cmpl($dst$$Register, 0x80000000); | |
| 10846 __ jccb(Assembler::notEqual, fast); | |
| 10847 __ subptr(rsp, 8); | |
| 10848 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 10849 __ fld_d(Address(rsp, 0)); | |
| 10850 __ addptr(rsp, 8); | |
| 10851 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper()))); | |
| 10852 __ bind(fast); | |
| 10853 %} | |
| 0 | 10854 ins_pipe( pipe_slow ); |
| 10855 %} | |
| 10856 | |
|
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10857 instruct convDPR2L_reg_reg( eADXRegL dst, regDPR src, eFlagsReg cr ) %{ |
| 0 | 10858 predicate(UseSSE<=1); |
| 10859 match(Set dst (ConvD2L src)); | |
| 10860 effect( KILL cr ); | |
| 10861 format %{ "FLD $src\t# Convert double to long\n\t" | |
| 10862 "FLDCW trunc mode\n\t" | |
| 10863 "SUB ESP,8\n\t" | |
| 10864 "FISTp [ESP + #0]\n\t" | |
| 10865 "FLDCW std/24-bit mode\n\t" | |
| 10866 "POP EAX\n\t" | |
| 10867 "POP EDX\n\t" | |
| 10868 "CMP EDX,0x80000000\n\t" | |
| 10869 "JNE,s fast\n\t" | |
| 10870 "TEST EAX,EAX\n\t" | |
| 10871 "JNE,s fast\n\t" | |
| 10872 "FLD $src\n\t" | |
| 10873 "CALL d2l_wrapper\n" | |
| 10874 "fast:" %} | |
|
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10875 ins_encode( Push_Reg_DPR(src), DPR2L_encoding(src) ); |
| 0 | 10876 ins_pipe( pipe_slow ); |
| 10877 %} | |
| 10878 | |
| 10879 // XMM lacks a float/double->long conversion, so use the old FPU stack. | |
|
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10880 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{ |
| 0 | 10881 predicate (UseSSE>=2); |
| 10882 match(Set dst (ConvD2L src)); | |
| 10883 effect( KILL cr ); | |
| 10884 format %{ "SUB ESP,8\t# Convert double to long\n\t" | |
| 10885 "MOVSD [ESP],$src\n\t" | |
| 10886 "FLD_D [ESP]\n\t" | |
| 10887 "FLDCW trunc mode\n\t" | |
| 10888 "FISTp [ESP + #0]\n\t" | |
| 10889 "FLDCW std/24-bit mode\n\t" | |
| 10890 "POP EAX\n\t" | |
| 10891 "POP EDX\n\t" | |
| 10892 "CMP EDX,0x80000000\n\t" | |
| 10893 "JNE,s fast\n\t" | |
| 10894 "TEST EAX,EAX\n\t" | |
| 10895 "JNE,s fast\n\t" | |
| 10896 "SUB ESP,8\n\t" | |
| 10897 "MOVSD [ESP],$src\n\t" | |
| 10898 "FLD_D [ESP]\n\t" | |
| 4759 | 10899 "ADD ESP,8\n\t" |
| 0 | 10900 "CALL d2l_wrapper\n" |
| 10901 "fast:" %} | |
| 4759 | 10902 ins_encode %{ |
| 10903 Label fast; | |
| 10904 __ subptr(rsp, 8); | |
| 10905 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 10906 __ fld_d(Address(rsp, 0)); | |
| 10907 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); | |
| 10908 __ fistp_d(Address(rsp, 0)); | |
| 10909 // Restore the rounding mode, mask the exception | |
| 10910 if (Compile::current()->in_24_bit_fp_mode()) { | |
| 10911 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); | |
| 10912 } else { | |
| 10913 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
| 10914 } | |
| 10915 // Load the converted long, adjust CPU stack | |
| 10916 __ pop(rax); | |
| 10917 __ pop(rdx); | |
| 10918 __ cmpl(rdx, 0x80000000); | |
| 10919 __ jccb(Assembler::notEqual, fast); | |
| 10920 __ testl(rax, rax); | |
| 10921 __ jccb(Assembler::notEqual, fast); | |
| 10922 __ subptr(rsp, 8); | |
| 10923 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 10924 __ fld_d(Address(rsp, 0)); | |
| 10925 __ addptr(rsp, 8); | |
| 10926 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper()))); | |
| 10927 __ bind(fast); | |
| 10928 %} | |
| 0 | 10929 ins_pipe( pipe_slow ); |
| 10930 %} | |
| 10931 | |
| 10932 // Convert a double to an int. Java semantics require we do complex | |
| 10933 // manglations in the corner cases. So we set the rounding mode to | |
| 10934 // 'zero', store the darned double down as an int, and reset the | |
| 10935 // rounding mode to 'nearest'. The hardware stores a flag value down | |
| 10936 // if we would overflow or converted a NAN; we check for this and | |
| 10937 // and go the slow path if needed. | |
|
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10938 instruct convFPR2I_reg_reg(eAXRegI dst, eDXRegI tmp, regFPR src, eFlagsReg cr ) %{ |
| 0 | 10939 predicate(UseSSE==0); |
| 10940 match(Set dst (ConvF2I src)); | |
| 10941 effect( KILL tmp, KILL cr ); | |
| 10942 format %{ "FLD $src\t# Convert float to int \n\t" | |
| 10943 "FLDCW trunc mode\n\t" | |
| 10944 "SUB ESP,4\n\t" | |
| 10945 "FISTp [ESP + #0]\n\t" | |
| 10946 "FLDCW std/24-bit mode\n\t" | |
| 10947 "POP EAX\n\t" | |
| 10948 "CMP EAX,0x80000000\n\t" | |
| 10949 "JNE,s fast\n\t" | |
| 10950 "FLD $src\n\t" | |
| 10951 "CALL d2i_wrapper\n" | |
| 10952 "fast:" %} | |
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10953 // DPR2I_encoding works for FPR2I |
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10954 ins_encode( Push_Reg_FPR(src), DPR2I_encoding(src) ); |
| 0 | 10955 ins_pipe( pipe_slow ); |
| 10956 %} | |
| 10957 | |
| 10958 // Convert a float in xmm to an int reg. | |
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10959 instruct convF2I_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{ |
| 0 | 10960 predicate(UseSSE>=1); |
| 10961 match(Set dst (ConvF2I src)); | |
| 10962 effect( KILL tmp, KILL cr ); | |
| 10963 format %{ "CVTTSS2SI $dst, $src\n\t" | |
| 10964 "CMP $dst,0x80000000\n\t" | |
| 10965 "JNE,s fast\n\t" | |
| 10966 "SUB ESP, 4\n\t" | |
| 10967 "MOVSS [ESP], $src\n\t" | |
| 10968 "FLD [ESP]\n\t" | |
| 10969 "ADD ESP, 4\n\t" | |
| 10970 "CALL d2i_wrapper\n" | |
| 10971 "fast:" %} | |
| 4759 | 10972 ins_encode %{ |
| 10973 Label fast; | |
| 10974 __ cvttss2sil($dst$$Register, $src$$XMMRegister); | |
| 10975 __ cmpl($dst$$Register, 0x80000000); | |
| 10976 __ jccb(Assembler::notEqual, fast); | |
| 10977 __ subptr(rsp, 4); | |
| 10978 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 10979 __ fld_s(Address(rsp, 0)); | |
| 10980 __ addptr(rsp, 4); | |
| 10981 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper()))); | |
| 10982 __ bind(fast); | |
| 10983 %} | |
| 0 | 10984 ins_pipe( pipe_slow ); |
| 10985 %} | |
| 10986 | |
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10987 instruct convFPR2L_reg_reg( eADXRegL dst, regFPR src, eFlagsReg cr ) %{ |
| 0 | 10988 predicate(UseSSE==0); |
| 10989 match(Set dst (ConvF2L src)); | |
| 10990 effect( KILL cr ); | |
| 10991 format %{ "FLD $src\t# Convert float to long\n\t" | |
| 10992 "FLDCW trunc mode\n\t" | |
| 10993 "SUB ESP,8\n\t" | |
| 10994 "FISTp [ESP + #0]\n\t" | |
| 10995 "FLDCW std/24-bit mode\n\t" | |
| 10996 "POP EAX\n\t" | |
| 10997 "POP EDX\n\t" | |
| 10998 "CMP EDX,0x80000000\n\t" | |
| 10999 "JNE,s fast\n\t" | |
| 11000 "TEST EAX,EAX\n\t" | |
| 11001 "JNE,s fast\n\t" | |
| 11002 "FLD $src\n\t" | |
| 11003 "CALL d2l_wrapper\n" | |
| 11004 "fast:" %} | |
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11005 // DPR2L_encoding works for FPR2L |
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11006 ins_encode( Push_Reg_FPR(src), DPR2L_encoding(src) ); |
| 0 | 11007 ins_pipe( pipe_slow ); |
| 11008 %} | |
| 11009 | |
| 11010 // XMM lacks a float/double->long conversion, so use the old FPU stack. | |
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11011 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{ |
| 0 | 11012 predicate (UseSSE>=1); |
| 11013 match(Set dst (ConvF2L src)); | |
| 11014 effect( KILL cr ); | |
| 11015 format %{ "SUB ESP,8\t# Convert float to long\n\t" | |
| 11016 "MOVSS [ESP],$src\n\t" | |
| 11017 "FLD_S [ESP]\n\t" | |
| 11018 "FLDCW trunc mode\n\t" | |
| 11019 "FISTp [ESP + #0]\n\t" | |
| 11020 "FLDCW std/24-bit mode\n\t" | |
| 11021 "POP EAX\n\t" | |
| 11022 "POP EDX\n\t" | |
| 11023 "CMP EDX,0x80000000\n\t" | |
| 11024 "JNE,s fast\n\t" | |
| 11025 "TEST EAX,EAX\n\t" | |
| 11026 "JNE,s fast\n\t" | |
| 11027 "SUB ESP,4\t# Convert float to long\n\t" | |
| 11028 "MOVSS [ESP],$src\n\t" | |
| 11029 "FLD_S [ESP]\n\t" | |
| 11030 "ADD ESP,4\n\t" | |
| 11031 "CALL d2l_wrapper\n" | |
| 11032 "fast:" %} | |
| 4759 | 11033 ins_encode %{ |
| 11034 Label fast; | |
| 11035 __ subptr(rsp, 8); | |
| 11036 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 11037 __ fld_s(Address(rsp, 0)); | |
| 11038 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); | |
| 11039 __ fistp_d(Address(rsp, 0)); | |
| 11040 // Restore the rounding mode, mask the exception | |
| 11041 if (Compile::current()->in_24_bit_fp_mode()) { | |
| 11042 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); | |
| 11043 } else { | |
| 11044 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
| 11045 } | |
| 11046 // Load the converted long, adjust CPU stack | |
| 11047 __ pop(rax); | |
| 11048 __ pop(rdx); | |
| 11049 __ cmpl(rdx, 0x80000000); | |
| 11050 __ jccb(Assembler::notEqual, fast); | |
| 11051 __ testl(rax, rax); | |
| 11052 __ jccb(Assembler::notEqual, fast); | |
| 11053 __ subptr(rsp, 4); | |
| 11054 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 11055 __ fld_s(Address(rsp, 0)); | |
| 11056 __ addptr(rsp, 4); | |
| 11057 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper()))); | |
| 11058 __ bind(fast); | |
| 11059 %} | |
| 0 | 11060 ins_pipe( pipe_slow ); |
| 11061 %} | |
| 11062 | |
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11063 instruct convI2DPR_reg(regDPR dst, stackSlotI src) %{ |
| 0 | 11064 predicate( UseSSE<=1 ); |
| 11065 match(Set dst (ConvI2D src)); | |
| 11066 format %{ "FILD $src\n\t" | |
| 11067 "FSTP $dst" %} | |
| 11068 opcode(0xDB, 0x0); /* DB /0 */ | |
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11069 ins_encode(Push_Mem_I(src), Pop_Reg_DPR(dst)); |
| 0 | 11070 ins_pipe( fpu_reg_mem ); |
| 11071 %} | |
| 11072 | |
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11073 instruct convI2D_reg(regD dst, rRegI src) %{ |
| 71 | 11074 predicate( UseSSE>=2 && !UseXmmI2D ); |
| 0 | 11075 match(Set dst (ConvI2D src)); |
| 11076 format %{ "CVTSI2SD $dst,$src" %} | |
| 4759 | 11077 ins_encode %{ |
| 11078 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register); | |
| 11079 %} | |
| 0 | 11080 ins_pipe( pipe_slow ); |
| 11081 %} | |
| 11082 | |
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11083 instruct convI2D_mem(regD dst, memory mem) %{ |
| 0 | 11084 predicate( UseSSE>=2 ); |
| 11085 match(Set dst (ConvI2D (LoadI mem))); | |
| 11086 format %{ "CVTSI2SD $dst,$mem" %} | |
| 4759 | 11087 ins_encode %{ |
| 11088 __ cvtsi2sdl ($dst$$XMMRegister, $mem$$Address); | |
| 11089 %} | |
| 0 | 11090 ins_pipe( pipe_slow ); |
| 11091 %} | |
| 11092 | |
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11093 instruct convXI2D_reg(regD dst, rRegI src) |
| 71 | 11094 %{ |
| 11095 predicate( UseSSE>=2 && UseXmmI2D ); | |
| 11096 match(Set dst (ConvI2D src)); | |
| 11097 | |
| 11098 format %{ "MOVD $dst,$src\n\t" | |
| 11099 "CVTDQ2PD $dst,$dst\t# i2d" %} | |
| 11100 ins_encode %{ | |
| 304 | 11101 __ movdl($dst$$XMMRegister, $src$$Register); |
| 71 | 11102 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister); |
| 11103 %} | |
| 11104 ins_pipe(pipe_slow); // XXX | |
| 11105 %} | |
| 11106 | |
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11107 instruct convI2DPR_mem(regDPR dst, memory mem) %{ |
| 0 | 11108 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr()); |
| 11109 match(Set dst (ConvI2D (LoadI mem))); | |
| 11110 format %{ "FILD $mem\n\t" | |
| 11111 "FSTP $dst" %} | |
| 11112 opcode(0xDB); /* DB /0 */ | |
| 11113 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
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11114 Pop_Reg_DPR(dst)); |
| 0 | 11115 ins_pipe( fpu_reg_mem ); |
| 11116 %} | |
| 11117 | |
| 11118 // Convert a byte to a float; no rounding step needed. | |
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11119 instruct conv24I2FPR_reg(regFPR dst, stackSlotI src) %{ |
| 0 | 11120 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 ); |
| 11121 match(Set dst (ConvI2F src)); | |
| 11122 format %{ "FILD $src\n\t" | |
| 11123 "FSTP $dst" %} | |
| 11124 | |
| 11125 opcode(0xDB, 0x0); /* DB /0 */ | |
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11126 ins_encode(Push_Mem_I(src), Pop_Reg_FPR(dst)); |
| 0 | 11127 ins_pipe( fpu_reg_mem ); |
| 11128 %} | |
| 11129 | |
| 11130 // In 24-bit mode, force exponent rounding by storing back out | |
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11131 instruct convI2FPR_SSF(stackSlotF dst, stackSlotI src) %{ |
| 0 | 11132 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 11133 match(Set dst (ConvI2F src)); | |
| 11134 ins_cost(200); | |
| 11135 format %{ "FILD $src\n\t" | |
| 11136 "FSTP_S $dst" %} | |
| 11137 opcode(0xDB, 0x0); /* DB /0 */ | |
| 11138 ins_encode( Push_Mem_I(src), | |
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11139 Pop_Mem_FPR(dst)); |
| 0 | 11140 ins_pipe( fpu_mem_mem ); |
| 11141 %} | |
| 11142 | |
| 11143 // In 24-bit mode, force exponent rounding by storing back out | |
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11144 instruct convI2FPR_SSF_mem(stackSlotF dst, memory mem) %{ |
| 0 | 11145 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 11146 match(Set dst (ConvI2F (LoadI mem))); | |
| 11147 ins_cost(200); | |
| 11148 format %{ "FILD $mem\n\t" | |
| 11149 "FSTP_S $dst" %} | |
| 11150 opcode(0xDB); /* DB /0 */ | |
| 11151 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
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11152 Pop_Mem_FPR(dst)); |
| 0 | 11153 ins_pipe( fpu_mem_mem ); |
| 11154 %} | |
| 11155 | |
| 11156 // This instruction does not round to 24-bits | |
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11157 instruct convI2FPR_reg(regFPR dst, stackSlotI src) %{ |
| 0 | 11158 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 11159 match(Set dst (ConvI2F src)); | |
| 11160 format %{ "FILD $src\n\t" | |
| 11161 "FSTP $dst" %} | |
| 11162 opcode(0xDB, 0x0); /* DB /0 */ | |
| 11163 ins_encode( Push_Mem_I(src), | |
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11164 Pop_Reg_FPR(dst)); |
| 0 | 11165 ins_pipe( fpu_reg_mem ); |
| 11166 %} | |
| 11167 | |
| 11168 // This instruction does not round to 24-bits | |
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11169 instruct convI2FPR_mem(regFPR dst, memory mem) %{ |
| 0 | 11170 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 11171 match(Set dst (ConvI2F (LoadI mem))); | |
| 11172 format %{ "FILD $mem\n\t" | |
| 11173 "FSTP $dst" %} | |
| 11174 opcode(0xDB); /* DB /0 */ | |
| 11175 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
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11176 Pop_Reg_FPR(dst)); |
| 0 | 11177 ins_pipe( fpu_reg_mem ); |
| 11178 %} | |
| 11179 | |
| 11180 // Convert an int to a float in xmm; no rounding step needed. | |
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11181 instruct convI2F_reg(regF dst, rRegI src) %{ |
| 71 | 11182 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F ); |
| 0 | 11183 match(Set dst (ConvI2F src)); |
| 11184 format %{ "CVTSI2SS $dst, $src" %} | |
| 4759 | 11185 ins_encode %{ |
| 11186 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register); | |
| 11187 %} | |
| 0 | 11188 ins_pipe( pipe_slow ); |
| 11189 %} | |
| 11190 | |
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11191 instruct convXI2F_reg(regF dst, rRegI src) |
| 71 | 11192 %{ |
| 11193 predicate( UseSSE>=2 && UseXmmI2F ); | |
| 11194 match(Set dst (ConvI2F src)); | |
| 11195 | |
| 11196 format %{ "MOVD $dst,$src\n\t" | |
| 11197 "CVTDQ2PS $dst,$dst\t# i2f" %} | |
| 11198 ins_encode %{ | |
| 304 | 11199 __ movdl($dst$$XMMRegister, $src$$Register); |
| 71 | 11200 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister); |
| 11201 %} | |
| 11202 ins_pipe(pipe_slow); // XXX | |
| 11203 %} | |
| 11204 | |
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11205 instruct convI2L_reg( eRegL dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 11206 match(Set dst (ConvI2L src)); |
| 11207 effect(KILL cr); | |
| 624 | 11208 ins_cost(375); |
| 0 | 11209 format %{ "MOV $dst.lo,$src\n\t" |
| 11210 "MOV $dst.hi,$src\n\t" | |
| 11211 "SAR $dst.hi,31" %} | |
| 11212 ins_encode(convert_int_long(dst,src)); | |
| 11213 ins_pipe( ialu_reg_reg_long ); | |
| 11214 %} | |
| 11215 | |
| 11216 // Zero-extend convert int to long | |
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11217 instruct convI2L_reg_zex(eRegL dst, rRegI src, immL_32bits mask, eFlagsReg flags ) %{ |
| 0 | 11218 match(Set dst (AndL (ConvI2L src) mask) ); |
| 11219 effect( KILL flags ); | |
| 624 | 11220 ins_cost(250); |
| 0 | 11221 format %{ "MOV $dst.lo,$src\n\t" |
| 11222 "XOR $dst.hi,$dst.hi" %} | |
| 11223 opcode(0x33); // XOR | |
| 11224 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) ); | |
| 11225 ins_pipe( ialu_reg_reg_long ); | |
| 11226 %} | |
| 11227 | |
| 11228 // Zero-extend long | |
| 11229 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{ | |
| 11230 match(Set dst (AndL src mask) ); | |
| 11231 effect( KILL flags ); | |
| 624 | 11232 ins_cost(250); |
| 0 | 11233 format %{ "MOV $dst.lo,$src.lo\n\t" |
| 11234 "XOR $dst.hi,$dst.hi\n\t" %} | |
| 11235 opcode(0x33); // XOR | |
| 11236 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) ); | |
| 11237 ins_pipe( ialu_reg_reg_long ); | |
| 11238 %} | |
| 11239 | |
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11240 instruct convL2DPR_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{ |
| 0 | 11241 predicate (UseSSE<=1); |
| 11242 match(Set dst (ConvL2D src)); | |
| 11243 effect( KILL cr ); | |
| 11244 format %{ "PUSH $src.hi\t# Convert long to double\n\t" | |
| 11245 "PUSH $src.lo\n\t" | |
| 11246 "FILD ST,[ESP + #0]\n\t" | |
| 11247 "ADD ESP,8\n\t" | |
| 11248 "FSTP_D $dst\t# D-round" %} | |
| 11249 opcode(0xDF, 0x5); /* DF /5 */ | |
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11250 ins_encode(convert_long_double(src), Pop_Mem_DPR(dst)); |
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11251 ins_pipe( pipe_slow ); |
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11252 %} |
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11253 |
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11254 instruct convL2D_reg( regD dst, eRegL src, eFlagsReg cr) %{ |
| 0 | 11255 predicate (UseSSE>=2); |
| 11256 match(Set dst (ConvL2D src)); | |
| 11257 effect( KILL cr ); | |
| 11258 format %{ "PUSH $src.hi\t# Convert long to double\n\t" | |
| 11259 "PUSH $src.lo\n\t" | |
| 11260 "FILD_D [ESP]\n\t" | |
| 11261 "FSTP_D [ESP]\n\t" | |
| 11262 "MOVSD $dst,[ESP]\n\t" | |
| 11263 "ADD ESP,8" %} | |
| 11264 opcode(0xDF, 0x5); /* DF /5 */ | |
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11265 ins_encode(convert_long_double2(src), Push_ResultD(dst)); |
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11266 ins_pipe( pipe_slow ); |
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11267 %} |
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11268 |
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11269 instruct convL2F_reg( regF dst, eRegL src, eFlagsReg cr) %{ |
| 0 | 11270 predicate (UseSSE>=1); |
| 11271 match(Set dst (ConvL2F src)); | |
| 11272 effect( KILL cr ); | |
| 11273 format %{ "PUSH $src.hi\t# Convert long to single float\n\t" | |
| 11274 "PUSH $src.lo\n\t" | |
| 11275 "FILD_D [ESP]\n\t" | |
| 11276 "FSTP_S [ESP]\n\t" | |
| 11277 "MOVSS $dst,[ESP]\n\t" | |
| 11278 "ADD ESP,8" %} | |
| 11279 opcode(0xDF, 0x5); /* DF /5 */ | |
|
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11280 ins_encode(convert_long_double2(src), Push_ResultF(dst,0x8)); |
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11281 ins_pipe( pipe_slow ); |
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11282 %} |
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11283 |
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11284 instruct convL2FPR_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{ |
| 0 | 11285 match(Set dst (ConvL2F src)); |
| 11286 effect( KILL cr ); | |
| 11287 format %{ "PUSH $src.hi\t# Convert long to single float\n\t" | |
| 11288 "PUSH $src.lo\n\t" | |
| 11289 "FILD ST,[ESP + #0]\n\t" | |
| 11290 "ADD ESP,8\n\t" | |
| 11291 "FSTP_S $dst\t# F-round" %} | |
| 11292 opcode(0xDF, 0x5); /* DF /5 */ | |
|
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11293 ins_encode(convert_long_double(src), Pop_Mem_FPR(dst)); |
| 0 | 11294 ins_pipe( pipe_slow ); |
| 11295 %} | |
| 11296 | |
|
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11297 instruct convL2I_reg( rRegI dst, eRegL src ) %{ |
| 0 | 11298 match(Set dst (ConvL2I src)); |
| 11299 effect( DEF dst, USE src ); | |
| 11300 format %{ "MOV $dst,$src.lo" %} | |
| 11301 ins_encode(enc_CopyL_Lo(dst,src)); | |
| 11302 ins_pipe( ialu_reg_reg ); | |
| 11303 %} | |
| 11304 | |
| 11305 | |
|
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11306 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{ |
| 0 | 11307 match(Set dst (MoveF2I src)); |
| 11308 effect( DEF dst, USE src ); | |
| 11309 ins_cost(100); | |
| 11310 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %} | |
| 4759 | 11311 ins_encode %{ |
| 11312 __ movl($dst$$Register, Address(rsp, $src$$disp)); | |
| 11313 %} | |
| 0 | 11314 ins_pipe( ialu_reg_mem ); |
| 11315 %} | |
| 11316 | |
|
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11317 instruct MoveFPR2I_reg_stack(stackSlotI dst, regFPR src) %{ |
| 0 | 11318 predicate(UseSSE==0); |
| 11319 match(Set dst (MoveF2I src)); | |
| 11320 effect( DEF dst, USE src ); | |
| 11321 | |
| 11322 ins_cost(125); | |
| 11323 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %} | |
|
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11324 ins_encode( Pop_Mem_Reg_FPR(dst, src) ); |
| 0 | 11325 ins_pipe( fpu_mem_reg ); |
| 11326 %} | |
| 11327 | |
|
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11328 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regF src) %{ |
| 0 | 11329 predicate(UseSSE>=1); |
| 11330 match(Set dst (MoveF2I src)); | |
| 11331 effect( DEF dst, USE src ); | |
| 11332 | |
| 11333 ins_cost(95); | |
| 11334 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %} | |
| 4759 | 11335 ins_encode %{ |
| 11336 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister); | |
| 11337 %} | |
| 0 | 11338 ins_pipe( pipe_slow ); |
| 11339 %} | |
| 11340 | |
|
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11341 instruct MoveF2I_reg_reg_sse(rRegI dst, regF src) %{ |
| 0 | 11342 predicate(UseSSE>=2); |
| 11343 match(Set dst (MoveF2I src)); | |
| 11344 effect( DEF dst, USE src ); | |
| 11345 ins_cost(85); | |
| 11346 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %} | |
| 4759 | 11347 ins_encode %{ |
| 11348 __ movdl($dst$$Register, $src$$XMMRegister); | |
| 11349 %} | |
| 0 | 11350 ins_pipe( pipe_slow ); |
| 11351 %} | |
| 11352 | |
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11353 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{ |
| 0 | 11354 match(Set dst (MoveI2F src)); |
| 11355 effect( DEF dst, USE src ); | |
| 11356 | |
| 11357 ins_cost(100); | |
| 11358 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %} | |
| 4759 | 11359 ins_encode %{ |
| 11360 __ movl(Address(rsp, $dst$$disp), $src$$Register); | |
| 11361 %} | |
| 0 | 11362 ins_pipe( ialu_mem_reg ); |
| 11363 %} | |
| 11364 | |
| 11365 | |
|
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11366 instruct MoveI2FPR_stack_reg(regFPR dst, stackSlotI src) %{ |
| 0 | 11367 predicate(UseSSE==0); |
| 11368 match(Set dst (MoveI2F src)); | |
| 11369 effect(DEF dst, USE src); | |
| 11370 | |
| 11371 ins_cost(125); | |
| 11372 format %{ "FLD_S $src\n\t" | |
| 11373 "FSTP $dst\t# MoveI2F_stack_reg" %} | |
| 11374 opcode(0xD9); /* D9 /0, FLD m32real */ | |
| 11375 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
|
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11376 Pop_Reg_FPR(dst) ); |
| 0 | 11377 ins_pipe( fpu_reg_mem ); |
| 11378 %} | |
| 11379 | |
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11380 instruct MoveI2F_stack_reg_sse(regF dst, stackSlotI src) %{ |
| 0 | 11381 predicate(UseSSE>=1); |
| 11382 match(Set dst (MoveI2F src)); | |
| 11383 effect( DEF dst, USE src ); | |
| 11384 | |
| 11385 ins_cost(95); | |
| 11386 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %} | |
| 4759 | 11387 ins_encode %{ |
| 11388 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 11389 %} | |
| 0 | 11390 ins_pipe( pipe_slow ); |
| 11391 %} | |
| 11392 | |
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11393 instruct MoveI2F_reg_reg_sse(regF dst, rRegI src) %{ |
| 0 | 11394 predicate(UseSSE>=2); |
| 11395 match(Set dst (MoveI2F src)); | |
| 11396 effect( DEF dst, USE src ); | |
| 11397 | |
| 11398 ins_cost(85); | |
| 11399 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %} | |
| 4759 | 11400 ins_encode %{ |
| 11401 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 11402 %} | |
| 0 | 11403 ins_pipe( pipe_slow ); |
| 11404 %} | |
| 11405 | |
| 11406 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{ | |
| 11407 match(Set dst (MoveD2L src)); | |
| 11408 effect(DEF dst, USE src); | |
| 11409 | |
| 11410 ins_cost(250); | |
| 11411 format %{ "MOV $dst.lo,$src\n\t" | |
| 11412 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %} | |
| 11413 opcode(0x8B, 0x8B); | |
| 11414 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src)); | |
| 11415 ins_pipe( ialu_mem_long_reg ); | |
| 11416 %} | |
| 11417 | |
|
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11418 instruct MoveDPR2L_reg_stack(stackSlotL dst, regDPR src) %{ |
| 0 | 11419 predicate(UseSSE<=1); |
| 11420 match(Set dst (MoveD2L src)); | |
| 11421 effect(DEF dst, USE src); | |
| 11422 | |
| 11423 ins_cost(125); | |
| 11424 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %} | |
|
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11425 ins_encode( Pop_Mem_Reg_DPR(dst, src) ); |
| 0 | 11426 ins_pipe( fpu_mem_reg ); |
| 11427 %} | |
| 11428 | |
|
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11429 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regD src) %{ |
| 0 | 11430 predicate(UseSSE>=2); |
| 11431 match(Set dst (MoveD2L src)); | |
| 11432 effect(DEF dst, USE src); | |
| 11433 ins_cost(95); | |
| 11434 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %} | |
| 4759 | 11435 ins_encode %{ |
| 11436 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister); | |
| 11437 %} | |
| 0 | 11438 ins_pipe( pipe_slow ); |
| 11439 %} | |
| 11440 | |
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11441 instruct MoveD2L_reg_reg_sse(eRegL dst, regD src, regD tmp) %{ |
| 0 | 11442 predicate(UseSSE>=2); |
| 11443 match(Set dst (MoveD2L src)); | |
| 11444 effect(DEF dst, USE src, TEMP tmp); | |
| 11445 ins_cost(85); | |
| 11446 format %{ "MOVD $dst.lo,$src\n\t" | |
| 11447 "PSHUFLW $tmp,$src,0x4E\n\t" | |
| 11448 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %} | |
| 4759 | 11449 ins_encode %{ |
| 11450 __ movdl($dst$$Register, $src$$XMMRegister); | |
| 11451 __ pshuflw($tmp$$XMMRegister, $src$$XMMRegister, 0x4e); | |
| 11452 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister); | |
| 11453 %} | |
| 0 | 11454 ins_pipe( pipe_slow ); |
| 11455 %} | |
| 11456 | |
| 11457 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{ | |
| 11458 match(Set dst (MoveL2D src)); | |
| 11459 effect(DEF dst, USE src); | |
| 11460 | |
| 11461 ins_cost(200); | |
| 11462 format %{ "MOV $dst,$src.lo\n\t" | |
| 11463 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %} | |
| 11464 opcode(0x89, 0x89); | |
| 11465 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) ); | |
| 11466 ins_pipe( ialu_mem_long_reg ); | |
| 11467 %} | |
| 11468 | |
| 11469 | |
|
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11470 instruct MoveL2DPR_stack_reg(regDPR dst, stackSlotL src) %{ |
| 0 | 11471 predicate(UseSSE<=1); |
| 11472 match(Set dst (MoveL2D src)); | |
| 11473 effect(DEF dst, USE src); | |
| 11474 ins_cost(125); | |
| 11475 | |
| 11476 format %{ "FLD_D $src\n\t" | |
| 11477 "FSTP $dst\t# MoveL2D_stack_reg" %} | |
| 11478 opcode(0xDD); /* DD /0, FLD m64real */ | |
| 11479 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
|
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11480 Pop_Reg_DPR(dst) ); |
| 0 | 11481 ins_pipe( fpu_reg_mem ); |
| 11482 %} | |
| 11483 | |
| 11484 | |
|
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11485 instruct MoveL2D_stack_reg_sse(regD dst, stackSlotL src) %{ |
| 0 | 11486 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper); |
| 11487 match(Set dst (MoveL2D src)); | |
| 11488 effect(DEF dst, USE src); | |
| 11489 | |
| 11490 ins_cost(95); | |
| 11491 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %} | |
| 4759 | 11492 ins_encode %{ |
| 11493 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 11494 %} | |
| 0 | 11495 ins_pipe( pipe_slow ); |
| 11496 %} | |
| 11497 | |
|
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11498 instruct MoveL2D_stack_reg_sse_partial(regD dst, stackSlotL src) %{ |
| 0 | 11499 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper); |
| 11500 match(Set dst (MoveL2D src)); | |
| 11501 effect(DEF dst, USE src); | |
| 11502 | |
| 11503 ins_cost(95); | |
| 11504 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %} | |
| 4759 | 11505 ins_encode %{ |
| 11506 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 11507 %} | |
| 0 | 11508 ins_pipe( pipe_slow ); |
| 11509 %} | |
| 11510 | |
|
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11511 instruct MoveL2D_reg_reg_sse(regD dst, eRegL src, regD tmp) %{ |
| 0 | 11512 predicate(UseSSE>=2); |
| 11513 match(Set dst (MoveL2D src)); | |
| 11514 effect(TEMP dst, USE src, TEMP tmp); | |
| 11515 ins_cost(85); | |
| 11516 format %{ "MOVD $dst,$src.lo\n\t" | |
| 11517 "MOVD $tmp,$src.hi\n\t" | |
| 11518 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %} | |
| 4759 | 11519 ins_encode %{ |
| 11520 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 11521 __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register)); | |
| 11522 __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister); | |
| 11523 %} | |
| 0 | 11524 ins_pipe( pipe_slow ); |
| 11525 %} | |
| 11526 | |
| 11527 | |
| 11528 // ======================================================================= | |
| 11529 // fast clearing of an array | |
| 11530 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{ | |
| 11531 match(Set dummy (ClearArray cnt base)); | |
| 11532 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr); | |
| 11533 format %{ "SHL ECX,1\t# Convert doublewords to words\n\t" | |
| 11534 "XOR EAX,EAX\n\t" | |
| 11535 "REP STOS\t# store EAX into [EDI++] while ECX--" %} | |
| 11536 opcode(0,0x4); | |
| 11537 ins_encode( Opcode(0xD1), RegOpc(ECX), | |
| 11538 OpcRegReg(0x33,EAX,EAX), | |
| 11539 Opcode(0xF3), Opcode(0xAB) ); | |
| 11540 ins_pipe( pipe_slow ); | |
| 11541 %} | |
| 11542 | |
| 2262 | 11543 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eDXRegI cnt2, |
|
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11544 eAXRegI result, regD tmp1, eFlagsReg cr) %{ |
|
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11545 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); |
| 2262 | 11546 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr); |
| 11547 | |
| 11548 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %} | |
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11549 ins_encode %{ |
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11550 __ string_compare($str1$$Register, $str2$$Register, |
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11551 $cnt1$$Register, $cnt2$$Register, $result$$Register, |
| 2262 | 11552 $tmp1$$XMMRegister); |
|
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11553 %} |
| 681 | 11554 ins_pipe( pipe_slow ); |
| 11555 %} | |
| 11556 | |
| 11557 // fast string equals | |
|
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11558 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result, |
|
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11559 regD tmp1, regD tmp2, eBXRegI tmp3, eFlagsReg cr) %{ |
|
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11560 match(Set result (StrEquals (Binary str1 str2) cnt)); |
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11561 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr); |
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11562 |
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11563 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %} |
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11564 ins_encode %{ |
|
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11565 __ char_arrays_equals(false, $str1$$Register, $str2$$Register, |
|
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11566 $cnt$$Register, $result$$Register, $tmp3$$Register, |
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11567 $tmp1$$XMMRegister, $tmp2$$XMMRegister); |
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11568 %} |
|
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|
11569 ins_pipe( pipe_slow ); |
|
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|
11570 %} |
|
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11571 |
|
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11572 // fast search of substring with known size. |
|
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11573 instruct string_indexof_con(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, immI int_cnt2, |
|
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11574 eBXRegI result, regD vec, eAXRegI cnt2, eCXRegI tmp, eFlagsReg cr) %{ |
|
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|
11575 predicate(UseSSE42Intrinsics); |
|
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11576 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2))); |
|
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|
11577 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr); |
|
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|
11578 |
|
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|
11579 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %} |
|
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|
11580 ins_encode %{ |
|
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|
11581 int icnt2 = (int)$int_cnt2$$constant; |
|
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|
11582 if (icnt2 >= 8) { |
|
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|
11583 // IndexOf for constant substrings with size >= 8 elements |
|
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11584 // which don't need to be loaded through stack. |
|
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|
11585 __ string_indexofC8($str1$$Register, $str2$$Register, |
|
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11586 $cnt1$$Register, $cnt2$$Register, |
|
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|
11587 icnt2, $result$$Register, |
|
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11588 $vec$$XMMRegister, $tmp$$Register); |
|
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|
11589 } else { |
|
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|
11590 // Small strings are loaded through stack if they cross page boundary. |
|
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11591 __ string_indexof($str1$$Register, $str2$$Register, |
|
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|
11592 $cnt1$$Register, $cnt2$$Register, |
|
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|
11593 icnt2, $result$$Register, |
|
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11594 $vec$$XMMRegister, $tmp$$Register); |
|
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|
11595 } |
|
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|
11596 %} |
|
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|
11597 ins_pipe( pipe_slow ); |
|
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|
11598 %} |
|
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|
11599 |
|
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|
11600 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2, |
|
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|
11601 eBXRegI result, regD vec, eCXRegI tmp, eFlagsReg cr) %{ |
| 681 | 11602 predicate(UseSSE42Intrinsics); |
|
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11603 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2))); |
|
2320
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11604 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr); |
|
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|
11605 |
|
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|
11606 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %} |
|
986
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|
11607 ins_encode %{ |
|
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|
11608 __ string_indexof($str1$$Register, $str2$$Register, |
|
2320
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11609 $cnt1$$Register, $cnt2$$Register, |
|
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|
11610 (-1), $result$$Register, |
|
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|
11611 $vec$$XMMRegister, $tmp$$Register); |
|
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|
11612 %} |
| 0 | 11613 ins_pipe( pipe_slow ); |
| 11614 %} | |
| 11615 | |
|
169
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|
11616 // fast array equals |
|
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|
11617 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result, |
|
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11618 regD tmp1, regD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr) |
|
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11619 %{ |
|
169
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|
11620 match(Set result (AryEq ary1 ary2)); |
| 681 | 11621 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr); |
|
169
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|
11622 //ins_cost(300); |
|
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|
11623 |
|
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|
11624 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %} |
|
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|
11625 ins_encode %{ |
|
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|
11626 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register, |
|
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|
11627 $tmp3$$Register, $result$$Register, $tmp4$$Register, |
|
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|
11628 $tmp1$$XMMRegister, $tmp2$$XMMRegister); |
|
62001a362ce9
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|
11629 %} |
|
169
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changeset
|
11630 ins_pipe( pipe_slow ); |
|
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|
11631 %} |
|
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|
11632 |
| 0 | 11633 //----------Control Flow Instructions------------------------------------------ |
| 11634 // Signed compare Instructions | |
|
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|
11635 instruct compI_eReg(eFlagsReg cr, rRegI op1, rRegI op2) %{ |
| 0 | 11636 match(Set cr (CmpI op1 op2)); |
| 11637 effect( DEF cr, USE op1, USE op2 ); | |
| 11638 format %{ "CMP $op1,$op2" %} | |
| 11639 opcode(0x3B); /* Opcode 3B /r */ | |
| 11640 ins_encode( OpcP, RegReg( op1, op2) ); | |
| 11641 ins_pipe( ialu_cr_reg_reg ); | |
| 11642 %} | |
| 11643 | |
|
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|
11644 instruct compI_eReg_imm(eFlagsReg cr, rRegI op1, immI op2) %{ |
| 0 | 11645 match(Set cr (CmpI op1 op2)); |
| 11646 effect( DEF cr, USE op1 ); | |
| 11647 format %{ "CMP $op1,$op2" %} | |
| 11648 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 11649 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */ | |
| 11650 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); | |
| 11651 ins_pipe( ialu_cr_reg_imm ); | |
| 11652 %} | |
| 11653 | |
| 11654 // Cisc-spilled version of cmpI_eReg | |
|
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|
11655 instruct compI_eReg_mem(eFlagsReg cr, rRegI op1, memory op2) %{ |
| 0 | 11656 match(Set cr (CmpI op1 (LoadI op2))); |
| 11657 | |
| 11658 format %{ "CMP $op1,$op2" %} | |
| 11659 ins_cost(500); | |
| 11660 opcode(0x3B); /* Opcode 3B /r */ | |
| 11661 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11662 ins_pipe( ialu_cr_reg_mem ); | |
| 11663 %} | |
| 11664 | |
|
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|
11665 instruct testI_reg( eFlagsReg cr, rRegI src, immI0 zero ) %{ |
| 0 | 11666 match(Set cr (CmpI src zero)); |
| 11667 effect( DEF cr, USE src ); | |
| 11668 | |
| 11669 format %{ "TEST $src,$src" %} | |
| 11670 opcode(0x85); | |
| 11671 ins_encode( OpcP, RegReg( src, src ) ); | |
| 11672 ins_pipe( ialu_cr_reg_imm ); | |
| 11673 %} | |
| 11674 | |
|
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changeset
|
11675 instruct testI_reg_imm( eFlagsReg cr, rRegI src, immI con, immI0 zero ) %{ |
| 0 | 11676 match(Set cr (CmpI (AndI src con) zero)); |
| 11677 | |
| 11678 format %{ "TEST $src,$con" %} | |
| 11679 opcode(0xF7,0x00); | |
| 11680 ins_encode( OpcP, RegOpc(src), Con32(con) ); | |
| 11681 ins_pipe( ialu_cr_reg_imm ); | |
| 11682 %} | |
| 11683 | |
|
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|
11684 instruct testI_reg_mem( eFlagsReg cr, rRegI src, memory mem, immI0 zero ) %{ |
| 0 | 11685 match(Set cr (CmpI (AndI src mem) zero)); |
| 11686 | |
| 11687 format %{ "TEST $src,$mem" %} | |
| 11688 opcode(0x85); | |
| 11689 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 11690 ins_pipe( ialu_cr_reg_mem ); | |
| 11691 %} | |
| 11692 | |
| 11693 // Unsigned compare Instructions; really, same as signed except they | |
| 11694 // produce an eFlagsRegU instead of eFlagsReg. | |
|
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|
11695 instruct compU_eReg(eFlagsRegU cr, rRegI op1, rRegI op2) %{ |
| 0 | 11696 match(Set cr (CmpU op1 op2)); |
| 11697 | |
| 11698 format %{ "CMPu $op1,$op2" %} | |
| 11699 opcode(0x3B); /* Opcode 3B /r */ | |
| 11700 ins_encode( OpcP, RegReg( op1, op2) ); | |
| 11701 ins_pipe( ialu_cr_reg_reg ); | |
| 11702 %} | |
| 11703 | |
|
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changeset
|
11704 instruct compU_eReg_imm(eFlagsRegU cr, rRegI op1, immI op2) %{ |
| 0 | 11705 match(Set cr (CmpU op1 op2)); |
| 11706 | |
| 11707 format %{ "CMPu $op1,$op2" %} | |
| 11708 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 11709 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); | |
| 11710 ins_pipe( ialu_cr_reg_imm ); | |
| 11711 %} | |
| 11712 | |
| 11713 // // Cisc-spilled version of cmpU_eReg | |
|
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|
11714 instruct compU_eReg_mem(eFlagsRegU cr, rRegI op1, memory op2) %{ |
| 0 | 11715 match(Set cr (CmpU op1 (LoadI op2))); |
| 11716 | |
| 11717 format %{ "CMPu $op1,$op2" %} | |
| 11718 ins_cost(500); | |
| 11719 opcode(0x3B); /* Opcode 3B /r */ | |
| 11720 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11721 ins_pipe( ialu_cr_reg_mem ); | |
| 11722 %} | |
| 11723 | |
| 11724 // // Cisc-spilled version of cmpU_eReg | |
|
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|
11725 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, rRegI op2) %{ |
| 0 | 11726 // match(Set cr (CmpU (LoadI op1) op2)); |
| 11727 // | |
| 11728 // format %{ "CMPu $op1,$op2" %} | |
| 11729 // ins_cost(500); | |
| 11730 // opcode(0x39); /* Opcode 39 /r */ | |
| 11731 // ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11732 //%} | |
| 11733 | |
|
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|
11734 instruct testU_reg( eFlagsRegU cr, rRegI src, immI0 zero ) %{ |
| 0 | 11735 match(Set cr (CmpU src zero)); |
| 11736 | |
| 11737 format %{ "TESTu $src,$src" %} | |
| 11738 opcode(0x85); | |
| 11739 ins_encode( OpcP, RegReg( src, src ) ); | |
| 11740 ins_pipe( ialu_cr_reg_imm ); | |
| 11741 %} | |
| 11742 | |
| 11743 // Unsigned pointer compare Instructions | |
| 11744 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{ | |
| 11745 match(Set cr (CmpP op1 op2)); | |
| 11746 | |
| 11747 format %{ "CMPu $op1,$op2" %} | |
| 11748 opcode(0x3B); /* Opcode 3B /r */ | |
| 11749 ins_encode( OpcP, RegReg( op1, op2) ); | |
| 11750 ins_pipe( ialu_cr_reg_reg ); | |
| 11751 %} | |
| 11752 | |
| 11753 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{ | |
| 11754 match(Set cr (CmpP op1 op2)); | |
| 11755 | |
| 11756 format %{ "CMPu $op1,$op2" %} | |
| 11757 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 11758 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); | |
| 11759 ins_pipe( ialu_cr_reg_imm ); | |
| 11760 %} | |
| 11761 | |
| 11762 // // Cisc-spilled version of cmpP_eReg | |
| 11763 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{ | |
| 11764 match(Set cr (CmpP op1 (LoadP op2))); | |
| 11765 | |
| 11766 format %{ "CMPu $op1,$op2" %} | |
| 11767 ins_cost(500); | |
| 11768 opcode(0x3B); /* Opcode 3B /r */ | |
| 11769 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11770 ins_pipe( ialu_cr_reg_mem ); | |
| 11771 %} | |
| 11772 | |
| 11773 // // Cisc-spilled version of cmpP_eReg | |
| 11774 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{ | |
| 11775 // match(Set cr (CmpP (LoadP op1) op2)); | |
| 11776 // | |
| 11777 // format %{ "CMPu $op1,$op2" %} | |
| 11778 // ins_cost(500); | |
| 11779 // opcode(0x39); /* Opcode 39 /r */ | |
| 11780 // ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11781 //%} | |
| 11782 | |
| 11783 // Compare raw pointer (used in out-of-heap check). | |
| 11784 // Only works because non-oop pointers must be raw pointers | |
| 11785 // and raw pointers have no anti-dependencies. | |
| 11786 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{ | |
|
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|
11787 predicate( n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none ); |
| 0 | 11788 match(Set cr (CmpP op1 (LoadP op2))); |
| 11789 | |
| 11790 format %{ "CMPu $op1,$op2" %} | |
| 11791 opcode(0x3B); /* Opcode 3B /r */ | |
| 11792 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11793 ins_pipe( ialu_cr_reg_mem ); | |
| 11794 %} | |
| 11795 | |
| 11796 // | |
| 11797 // This will generate a signed flags result. This should be ok | |
| 11798 // since any compare to a zero should be eq/neq. | |
| 11799 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{ | |
| 11800 match(Set cr (CmpP src zero)); | |
| 11801 | |
| 11802 format %{ "TEST $src,$src" %} | |
| 11803 opcode(0x85); | |
| 11804 ins_encode( OpcP, RegReg( src, src ) ); | |
| 11805 ins_pipe( ialu_cr_reg_imm ); | |
| 11806 %} | |
| 11807 | |
| 11808 // Cisc-spilled version of testP_reg | |
| 11809 // This will generate a signed flags result. This should be ok | |
| 11810 // since any compare to a zero should be eq/neq. | |
| 11811 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{ | |
| 11812 match(Set cr (CmpP (LoadP op) zero)); | |
| 11813 | |
| 11814 format %{ "TEST $op,0xFFFFFFFF" %} | |
| 11815 ins_cost(500); | |
| 11816 opcode(0xF7); /* Opcode F7 /0 */ | |
| 11817 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) ); | |
| 11818 ins_pipe( ialu_cr_reg_imm ); | |
| 11819 %} | |
| 11820 | |
| 11821 // Yanked all unsigned pointer compare operations. | |
| 11822 // Pointer compares are done with CmpP which is already unsigned. | |
| 11823 | |
| 11824 //----------Max and Min-------------------------------------------------------- | |
| 11825 // Min Instructions | |
| 11826 //// | |
| 11827 // *** Min and Max using the conditional move are slower than the | |
| 11828 // *** branch version on a Pentium III. | |
| 11829 // // Conditional move for min | |
|
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|
11830 //instruct cmovI_reg_lt( rRegI op2, rRegI op1, eFlagsReg cr ) %{ |
| 0 | 11831 // effect( USE_DEF op2, USE op1, USE cr ); |
| 11832 // format %{ "CMOVlt $op2,$op1\t! min" %} | |
| 11833 // opcode(0x4C,0x0F); | |
| 11834 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) ); | |
| 11835 // ins_pipe( pipe_cmov_reg ); | |
| 11836 //%} | |
| 11837 // | |
| 11838 //// Min Register with Register (P6 version) | |
|
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11839 //instruct minI_eReg_p6( rRegI op1, rRegI op2 ) %{ |
| 0 | 11840 // predicate(VM_Version::supports_cmov() ); |
| 11841 // match(Set op2 (MinI op1 op2)); | |
| 11842 // ins_cost(200); | |
| 11843 // expand %{ | |
| 11844 // eFlagsReg cr; | |
| 11845 // compI_eReg(cr,op1,op2); | |
| 11846 // cmovI_reg_lt(op2,op1,cr); | |
| 11847 // %} | |
| 11848 //%} | |
| 11849 | |
| 11850 // Min Register with Register (generic version) | |
|
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11851 instruct minI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{ |
| 0 | 11852 match(Set dst (MinI dst src)); |
| 11853 effect(KILL flags); | |
| 11854 ins_cost(300); | |
| 11855 | |
| 11856 format %{ "MIN $dst,$src" %} | |
| 11857 opcode(0xCC); | |
| 11858 ins_encode( min_enc(dst,src) ); | |
| 11859 ins_pipe( pipe_slow ); | |
| 11860 %} | |
| 11861 | |
| 11862 // Max Register with Register | |
| 11863 // *** Min and Max using the conditional move are slower than the | |
| 11864 // *** branch version on a Pentium III. | |
| 11865 // // Conditional move for max | |
|
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11866 //instruct cmovI_reg_gt( rRegI op2, rRegI op1, eFlagsReg cr ) %{ |
| 0 | 11867 // effect( USE_DEF op2, USE op1, USE cr ); |
| 11868 // format %{ "CMOVgt $op2,$op1\t! max" %} | |
| 11869 // opcode(0x4F,0x0F); | |
| 11870 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) ); | |
| 11871 // ins_pipe( pipe_cmov_reg ); | |
| 11872 //%} | |
| 11873 // | |
| 11874 // // Max Register with Register (P6 version) | |
|
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11875 //instruct maxI_eReg_p6( rRegI op1, rRegI op2 ) %{ |
| 0 | 11876 // predicate(VM_Version::supports_cmov() ); |
| 11877 // match(Set op2 (MaxI op1 op2)); | |
| 11878 // ins_cost(200); | |
| 11879 // expand %{ | |
| 11880 // eFlagsReg cr; | |
| 11881 // compI_eReg(cr,op1,op2); | |
| 11882 // cmovI_reg_gt(op2,op1,cr); | |
| 11883 // %} | |
| 11884 //%} | |
| 11885 | |
| 11886 // Max Register with Register (generic version) | |
|
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11887 instruct maxI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{ |
| 0 | 11888 match(Set dst (MaxI dst src)); |
| 11889 effect(KILL flags); | |
| 11890 ins_cost(300); | |
| 11891 | |
| 11892 format %{ "MAX $dst,$src" %} | |
| 11893 opcode(0xCC); | |
| 11894 ins_encode( max_enc(dst,src) ); | |
| 11895 ins_pipe( pipe_slow ); | |
| 11896 %} | |
| 11897 | |
| 11898 // ============================================================================ | |
| 3345 | 11899 // Counted Loop limit node which represents exact final iterator value. |
| 11900 // Note: the resulting value should fit into integer range since | |
| 11901 // counted loops have limit check on overflow. | |
| 11902 instruct loopLimit_eReg(eAXRegI limit, nadxRegI init, immI stride, eDXRegI limit_hi, nadxRegI tmp, eFlagsReg flags) %{ | |
| 11903 match(Set limit (LoopLimit (Binary init limit) stride)); | |
| 11904 effect(TEMP limit_hi, TEMP tmp, KILL flags); | |
| 11905 ins_cost(300); | |
| 11906 | |
| 11907 format %{ "loopLimit $init,$limit,$stride # $limit = $init + $stride *( $limit - $init + $stride -1)/ $stride, kills $limit_hi" %} | |
| 11908 ins_encode %{ | |
| 11909 int strd = (int)$stride$$constant; | |
| 11910 assert(strd != 1 && strd != -1, "sanity"); | |
| 11911 int m1 = (strd > 0) ? 1 : -1; | |
| 11912 // Convert limit to long (EAX:EDX) | |
| 11913 __ cdql(); | |
| 11914 // Convert init to long (init:tmp) | |
| 11915 __ movl($tmp$$Register, $init$$Register); | |
| 11916 __ sarl($tmp$$Register, 31); | |
| 11917 // $limit - $init | |
| 11918 __ subl($limit$$Register, $init$$Register); | |
| 11919 __ sbbl($limit_hi$$Register, $tmp$$Register); | |
| 11920 // + ($stride - 1) | |
| 11921 if (strd > 0) { | |
| 11922 __ addl($limit$$Register, (strd - 1)); | |
| 11923 __ adcl($limit_hi$$Register, 0); | |
| 11924 __ movl($tmp$$Register, strd); | |
| 11925 } else { | |
| 11926 __ addl($limit$$Register, (strd + 1)); | |
| 11927 __ adcl($limit_hi$$Register, -1); | |
| 11928 __ lneg($limit_hi$$Register, $limit$$Register); | |
| 11929 __ movl($tmp$$Register, -strd); | |
| 11930 } | |
| 11931 // signed devision: (EAX:EDX) / pos_stride | |
| 11932 __ idivl($tmp$$Register); | |
| 11933 if (strd < 0) { | |
| 11934 // restore sign | |
| 11935 __ negl($tmp$$Register); | |
| 11936 } | |
| 11937 // (EAX) * stride | |
| 11938 __ mull($tmp$$Register); | |
| 11939 // + init (ignore upper bits) | |
| 11940 __ addl($limit$$Register, $init$$Register); | |
| 11941 %} | |
| 11942 ins_pipe( pipe_slow ); | |
| 11943 %} | |
| 11944 | |
| 11945 // ============================================================================ | |
| 0 | 11946 // Branch Instructions |
| 11947 // Jump Table | |
|
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11948 instruct jumpXtnd(rRegI switch_val) %{ |
| 0 | 11949 match(Jump switch_val); |
| 11950 ins_cost(350); | |
| 2008 | 11951 format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %} |
| 11952 ins_encode %{ | |
| 0 | 11953 // Jump to Address(table_base + switch_reg) |
| 11954 Address index(noreg, $switch_val$$Register, Address::times_1); | |
| 2008 | 11955 __ jump(ArrayAddress($constantaddress, index)); |
| 0 | 11956 %} |
| 11957 ins_pipe(pipe_jmp); | |
| 11958 %} | |
| 11959 | |
| 11960 // Jump Direct - Label defines a relative address from JMP+1 | |
| 11961 instruct jmpDir(label labl) %{ | |
| 11962 match(Goto); | |
| 11963 effect(USE labl); | |
| 11964 | |
| 11965 ins_cost(300); | |
| 11966 format %{ "JMP $labl" %} | |
| 11967 size(5); | |
| 3851 | 11968 ins_encode %{ |
| 11969 Label* L = $labl$$label; | |
| 11970 __ jmp(*L, false); // Always long jump | |
| 11971 %} | |
| 0 | 11972 ins_pipe( pipe_jmp ); |
| 11973 %} | |
| 11974 | |
| 11975 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 11976 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 11977 match(If cop cr); | |
| 11978 effect(USE labl); | |
| 11979 | |
| 11980 ins_cost(300); | |
| 11981 format %{ "J$cop $labl" %} | |
| 11982 size(6); | |
| 3851 | 11983 ins_encode %{ |
| 11984 Label* L = $labl$$label; | |
| 11985 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 11986 %} | |
| 0 | 11987 ins_pipe( pipe_jcc ); |
| 11988 %} | |
| 11989 | |
| 11990 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 11991 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 11992 match(CountedLoopEnd cop cr); | |
| 11993 effect(USE labl); | |
| 11994 | |
| 11995 ins_cost(300); | |
| 11996 format %{ "J$cop $labl\t# Loop end" %} | |
| 11997 size(6); | |
| 3851 | 11998 ins_encode %{ |
| 11999 Label* L = $labl$$label; | |
| 12000 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 12001 %} | |
| 0 | 12002 ins_pipe( pipe_jcc ); |
| 12003 %} | |
| 12004 | |
| 12005 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12006 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 12007 match(CountedLoopEnd cop cmp); | |
| 12008 effect(USE labl); | |
| 12009 | |
| 12010 ins_cost(300); | |
| 12011 format %{ "J$cop,u $labl\t# Loop end" %} | |
| 12012 size(6); | |
| 3851 | 12013 ins_encode %{ |
| 12014 Label* L = $labl$$label; | |
| 12015 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 12016 %} | |
| 0 | 12017 ins_pipe( pipe_jcc ); |
| 12018 %} | |
| 12019 | |
|
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12020 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
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12021 match(CountedLoopEnd cop cmp); |
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12022 effect(USE labl); |
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12023 |
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12024 ins_cost(200); |
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12025 format %{ "J$cop,u $labl\t# Loop end" %} |
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12026 size(6); |
| 3851 | 12027 ins_encode %{ |
| 12028 Label* L = $labl$$label; | |
| 12029 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 12030 %} | |
|
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12031 ins_pipe( pipe_jcc ); |
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12032 %} |
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12033 |
| 0 | 12034 // Jump Direct Conditional - using unsigned comparison |
| 12035 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 12036 match(If cop cmp); | |
| 12037 effect(USE labl); | |
| 12038 | |
| 12039 ins_cost(300); | |
| 12040 format %{ "J$cop,u $labl" %} | |
| 12041 size(6); | |
| 3851 | 12042 ins_encode %{ |
| 12043 Label* L = $labl$$label; | |
| 12044 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 12045 %} | |
|
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12046 ins_pipe(pipe_jcc); |
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12047 %} |
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12048 |
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12049 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
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12050 match(If cop cmp); |
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12051 effect(USE labl); |
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12052 |
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12053 ins_cost(200); |
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12054 format %{ "J$cop,u $labl" %} |
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12055 size(6); |
| 3851 | 12056 ins_encode %{ |
| 12057 Label* L = $labl$$label; | |
| 12058 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 12059 %} | |
|
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12060 ins_pipe(pipe_jcc); |
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12061 %} |
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12062 |
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12063 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{ |
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12064 match(If cop cmp); |
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12065 effect(USE labl); |
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12066 |
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12067 ins_cost(200); |
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12068 format %{ $$template |
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12069 if ($cop$$cmpcode == Assembler::notEqual) { |
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12070 $$emit$$"JP,u $labl\n\t" |
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12071 $$emit$$"J$cop,u $labl" |
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12072 } else { |
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12073 $$emit$$"JP,u done\n\t" |
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12074 $$emit$$"J$cop,u $labl\n\t" |
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12075 $$emit$$"done:" |
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12076 } |
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12077 %} |
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12078 ins_encode %{ |
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12079 Label* l = $labl$$label; |
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12080 if ($cop$$cmpcode == Assembler::notEqual) { |
| 3851 | 12081 __ jcc(Assembler::parity, *l, false); |
| 12082 __ jcc(Assembler::notEqual, *l, false); | |
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12083 } else if ($cop$$cmpcode == Assembler::equal) { |
| 3851 | 12084 Label done; |
| 12085 __ jccb(Assembler::parity, done); | |
| 12086 __ jcc(Assembler::equal, *l, false); | |
| 12087 __ bind(done); | |
|
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12088 } else { |
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|
12089 ShouldNotReachHere(); |
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12090 } |
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12091 %} |
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12092 ins_pipe(pipe_jcc); |
| 0 | 12093 %} |
| 12094 | |
| 12095 // ============================================================================ | |
| 12096 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass | |
| 12097 // array for an instance of the superklass. Set a hidden internal cache on a | |
| 12098 // hit (cache is checked with exposed code in gen_subtype_check()). Return | |
| 12099 // NZ for a miss or zero for a hit. The encoding ALSO sets flags. | |
| 12100 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{ | |
| 12101 match(Set result (PartialSubtypeCheck sub super)); | |
| 12102 effect( KILL rcx, KILL cr ); | |
| 12103 | |
| 12104 ins_cost(1100); // slightly larger than the next version | |
|
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12105 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t" |
| 0 | 12106 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t" |
| 12107 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t" | |
| 12108 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t" | |
| 12109 "JNE,s miss\t\t# Missed: EDI not-zero\n\t" | |
| 12110 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t" | |
| 12111 "XOR $result,$result\t\t Hit: EDI zero\n\t" | |
| 12112 "miss:\t" %} | |
| 12113 | |
| 12114 opcode(0x1); // Force a XOR of EDI | |
| 12115 ins_encode( enc_PartialSubtypeCheck() ); | |
| 12116 ins_pipe( pipe_slow ); | |
| 12117 %} | |
| 12118 | |
| 12119 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{ | |
| 12120 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero)); | |
| 12121 effect( KILL rcx, KILL result ); | |
| 12122 | |
| 12123 ins_cost(1000); | |
|
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12124 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t" |
| 0 | 12125 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t" |
| 12126 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t" | |
| 12127 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t" | |
| 12128 "JNE,s miss\t\t# Missed: flags NZ\n\t" | |
| 12129 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t" | |
| 12130 "miss:\t" %} | |
| 12131 | |
| 12132 opcode(0x0); // No need to XOR EDI | |
| 12133 ins_encode( enc_PartialSubtypeCheck() ); | |
| 12134 ins_pipe( pipe_slow ); | |
| 12135 %} | |
| 12136 | |
| 12137 // ============================================================================ | |
| 12138 // Branch Instructions -- short offset versions | |
| 12139 // | |
| 12140 // These instructions are used to replace jumps of a long offset (the default | |
| 12141 // match) with jumps of a shorter offset. These instructions are all tagged | |
| 12142 // with the ins_short_branch attribute, which causes the ADLC to suppress the | |
| 12143 // match rules in general matching. Instead, the ADLC generates a conversion | |
| 12144 // method in the MachNode which can be used to do in-place replacement of the | |
| 12145 // long variant with the shorter variant. The compiler will determine if a | |
| 12146 // branch can be taken by the is_short_branch_offset() predicate in the machine | |
| 12147 // specific code section of the file. | |
| 12148 | |
| 12149 // Jump Direct - Label defines a relative address from JMP+1 | |
| 12150 instruct jmpDir_short(label labl) %{ | |
| 12151 match(Goto); | |
| 12152 effect(USE labl); | |
| 12153 | |
| 12154 ins_cost(300); | |
| 12155 format %{ "JMP,s $labl" %} | |
| 12156 size(2); | |
| 3851 | 12157 ins_encode %{ |
| 12158 Label* L = $labl$$label; | |
| 12159 __ jmpb(*L); | |
| 12160 %} | |
| 0 | 12161 ins_pipe( pipe_jmp ); |
| 12162 ins_short_branch(1); | |
| 12163 %} | |
| 12164 | |
| 12165 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12166 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 12167 match(If cop cr); | |
| 12168 effect(USE labl); | |
| 12169 | |
| 12170 ins_cost(300); | |
| 12171 format %{ "J$cop,s $labl" %} | |
| 12172 size(2); | |
| 3851 | 12173 ins_encode %{ |
| 12174 Label* L = $labl$$label; | |
| 12175 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12176 %} | |
| 0 | 12177 ins_pipe( pipe_jcc ); |
| 12178 ins_short_branch(1); | |
| 12179 %} | |
| 12180 | |
| 12181 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12182 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 12183 match(CountedLoopEnd cop cr); | |
| 12184 effect(USE labl); | |
| 12185 | |
| 12186 ins_cost(300); | |
|
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|
12187 format %{ "J$cop,s $labl\t# Loop end" %} |
| 0 | 12188 size(2); |
| 3851 | 12189 ins_encode %{ |
| 12190 Label* L = $labl$$label; | |
| 12191 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12192 %} | |
| 0 | 12193 ins_pipe( pipe_jcc ); |
| 12194 ins_short_branch(1); | |
| 12195 %} | |
| 12196 | |
| 12197 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12198 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 12199 match(CountedLoopEnd cop cmp); | |
| 12200 effect(USE labl); | |
| 12201 | |
| 12202 ins_cost(300); | |
|
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|
12203 format %{ "J$cop,us $labl\t# Loop end" %} |
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|
12204 size(2); |
| 3851 | 12205 ins_encode %{ |
| 12206 Label* L = $labl$$label; | |
| 12207 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12208 %} | |
|
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|
12209 ins_pipe( pipe_jcc ); |
|
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|
12210 ins_short_branch(1); |
|
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|
12211 %} |
|
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|
12212 |
|
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|
12213 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
|
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12214 match(CountedLoopEnd cop cmp); |
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|
12215 effect(USE labl); |
|
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|
12216 |
|
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|
12217 ins_cost(300); |
|
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|
12218 format %{ "J$cop,us $labl\t# Loop end" %} |
| 0 | 12219 size(2); |
| 3851 | 12220 ins_encode %{ |
| 12221 Label* L = $labl$$label; | |
| 12222 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12223 %} | |
| 0 | 12224 ins_pipe( pipe_jcc ); |
| 12225 ins_short_branch(1); | |
| 12226 %} | |
| 12227 | |
| 12228 // Jump Direct Conditional - using unsigned comparison | |
| 12229 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 12230 match(If cop cmp); | |
| 12231 effect(USE labl); | |
| 12232 | |
| 12233 ins_cost(300); | |
| 12234 format %{ "J$cop,us $labl" %} | |
| 12235 size(2); | |
| 3851 | 12236 ins_encode %{ |
| 12237 Label* L = $labl$$label; | |
| 12238 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12239 %} | |
| 0 | 12240 ins_pipe( pipe_jcc ); |
| 12241 ins_short_branch(1); | |
| 12242 %} | |
| 12243 | |
|
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12244 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
|
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|
12245 match(If cop cmp); |
|
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|
12246 effect(USE labl); |
|
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|
12247 |
|
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|
12248 ins_cost(300); |
|
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|
12249 format %{ "J$cop,us $labl" %} |
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|
12250 size(2); |
| 3851 | 12251 ins_encode %{ |
| 12252 Label* L = $labl$$label; | |
| 12253 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12254 %} | |
|
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|
12255 ins_pipe( pipe_jcc ); |
|
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|
12256 ins_short_branch(1); |
|
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|
12257 %} |
|
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|
12258 |
|
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|
12259 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{ |
|
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|
12260 match(If cop cmp); |
|
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|
12261 effect(USE labl); |
|
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|
12262 |
|
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|
12263 ins_cost(300); |
|
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|
12264 format %{ $$template |
|
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|
12265 if ($cop$$cmpcode == Assembler::notEqual) { |
|
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12266 $$emit$$"JP,u,s $labl\n\t" |
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12267 $$emit$$"J$cop,u,s $labl" |
|
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|
12268 } else { |
|
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|
12269 $$emit$$"JP,u,s done\n\t" |
|
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|
12270 $$emit$$"J$cop,u,s $labl\n\t" |
|
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|
12271 $$emit$$"done:" |
|
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|
12272 } |
|
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|
12273 %} |
|
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|
12274 size(4); |
|
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parents:
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|
12275 ins_encode %{ |
|
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|
12276 Label* l = $labl$$label; |
|
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|
12277 if ($cop$$cmpcode == Assembler::notEqual) { |
| 3851 | 12278 __ jccb(Assembler::parity, *l); |
| 12279 __ jccb(Assembler::notEqual, *l); | |
|
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|
12280 } else if ($cop$$cmpcode == Assembler::equal) { |
| 3851 | 12281 Label done; |
| 12282 __ jccb(Assembler::parity, done); | |
| 12283 __ jccb(Assembler::equal, *l); | |
| 12284 __ bind(done); | |
|
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|
12285 } else { |
| 3851 | 12286 ShouldNotReachHere(); |
| 12287 } | |
|
415
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|
12288 %} |
|
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|
12289 ins_pipe(pipe_jcc); |
|
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|
12290 ins_short_branch(1); |
|
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|
12291 %} |
|
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|
12292 |
| 0 | 12293 // ============================================================================ |
| 12294 // Long Compare | |
| 12295 // | |
| 12296 // Currently we hold longs in 2 registers. Comparing such values efficiently | |
| 12297 // is tricky. The flavor of compare used depends on whether we are testing | |
| 12298 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit. | |
| 12299 // The GE test is the negated LT test. The LE test can be had by commuting | |
| 12300 // the operands (yielding a GE test) and then negating; negate again for the | |
| 12301 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the | |
| 12302 // NE test is negated from that. | |
| 12303 | |
| 12304 // Due to a shortcoming in the ADLC, it mixes up expressions like: | |
| 12305 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the | |
| 12306 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections | |
| 12307 // are collapsed internally in the ADLC's dfa-gen code. The match for | |
| 12308 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the | |
| 12309 // foo match ends up with the wrong leaf. One fix is to not match both | |
| 12310 // reg-reg and reg-zero forms of long-compare. This is unfortunate because | |
| 12311 // both forms beat the trinary form of long-compare and both are very useful | |
| 12312 // on Intel which has so few registers. | |
| 12313 | |
| 12314 // Manifest a CmpL result in an integer register. Very painful. | |
| 12315 // This is the test to avoid. | |
| 12316 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{ | |
| 12317 match(Set dst (CmpL3 src1 src2)); | |
| 12318 effect( KILL flags ); | |
| 12319 ins_cost(1000); | |
| 12320 format %{ "XOR $dst,$dst\n\t" | |
| 12321 "CMP $src1.hi,$src2.hi\n\t" | |
| 12322 "JLT,s m_one\n\t" | |
| 12323 "JGT,s p_one\n\t" | |
| 12324 "CMP $src1.lo,$src2.lo\n\t" | |
| 12325 "JB,s m_one\n\t" | |
| 12326 "JEQ,s done\n" | |
| 12327 "p_one:\tINC $dst\n\t" | |
| 12328 "JMP,s done\n" | |
| 12329 "m_one:\tDEC $dst\n" | |
| 12330 "done:" %} | |
| 12331 ins_encode %{ | |
| 12332 Label p_one, m_one, done; | |
| 304 | 12333 __ xorptr($dst$$Register, $dst$$Register); |
| 0 | 12334 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register)); |
| 12335 __ jccb(Assembler::less, m_one); | |
| 12336 __ jccb(Assembler::greater, p_one); | |
| 12337 __ cmpl($src1$$Register, $src2$$Register); | |
| 12338 __ jccb(Assembler::below, m_one); | |
| 12339 __ jccb(Assembler::equal, done); | |
| 12340 __ bind(p_one); | |
| 304 | 12341 __ incrementl($dst$$Register); |
| 0 | 12342 __ jmpb(done); |
| 12343 __ bind(m_one); | |
| 304 | 12344 __ decrementl($dst$$Register); |
| 0 | 12345 __ bind(done); |
| 12346 %} | |
| 12347 ins_pipe( pipe_slow ); | |
| 12348 %} | |
| 12349 | |
| 12350 //====== | |
| 12351 // Manifest a CmpL result in the normal flags. Only good for LT or GE | |
| 12352 // compares. Can be used for LE or GT compares by reversing arguments. | |
| 12353 // NOT GOOD FOR EQ/NE tests. | |
| 12354 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{ | |
| 12355 match( Set flags (CmpL src zero )); | |
| 12356 ins_cost(100); | |
| 12357 format %{ "TEST $src.hi,$src.hi" %} | |
| 12358 opcode(0x85); | |
| 12359 ins_encode( OpcP, RegReg_Hi2( src, src ) ); | |
| 12360 ins_pipe( ialu_cr_reg_reg ); | |
| 12361 %} | |
| 12362 | |
| 12363 // Manifest a CmpL result in the normal flags. Only good for LT or GE | |
| 12364 // compares. Can be used for LE or GT compares by reversing arguments. | |
| 12365 // NOT GOOD FOR EQ/NE tests. | |
|
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12366 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, rRegI tmp ) %{ |
| 0 | 12367 match( Set flags (CmpL src1 src2 )); |
| 12368 effect( TEMP tmp ); | |
| 12369 ins_cost(300); | |
| 12370 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t" | |
| 12371 "MOV $tmp,$src1.hi\n\t" | |
| 12372 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %} | |
| 12373 ins_encode( long_cmp_flags2( src1, src2, tmp ) ); | |
| 12374 ins_pipe( ialu_cr_reg_reg ); | |
| 12375 %} | |
| 12376 | |
| 12377 // Long compares reg < zero/req OR reg >= zero/req. | |
| 12378 // Just a wrapper for a normal branch, plus the predicate test. | |
| 12379 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{ | |
| 12380 match(If cmp flags); | |
| 12381 effect(USE labl); | |
| 12382 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); | |
| 12383 expand %{ | |
| 12384 jmpCon(cmp,flags,labl); // JLT or JGE... | |
| 12385 %} | |
| 12386 %} | |
| 12387 | |
| 12388 // Compare 2 longs and CMOVE longs. | |
| 12389 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{ | |
| 12390 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); | |
| 12391 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 12392 ins_cost(400); | |
| 12393 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12394 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12395 opcode(0x0F,0x40); | |
| 12396 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); | |
| 12397 ins_pipe( pipe_cmov_reg_long ); | |
| 12398 %} | |
| 12399 | |
| 12400 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{ | |
| 12401 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); | |
| 12402 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 12403 ins_cost(500); | |
| 12404 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12405 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12406 opcode(0x0F,0x40); | |
| 12407 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); | |
| 12408 ins_pipe( pipe_cmov_reg_long ); | |
| 12409 %} | |
| 12410 | |
| 12411 // Compare 2 longs and CMOVE ints. | |
|
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|
12412 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, rRegI src) %{ |
| 0 | 12413 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); |
| 12414 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); | |
| 12415 ins_cost(200); | |
| 12416 format %{ "CMOV$cmp $dst,$src" %} | |
| 12417 opcode(0x0F,0x40); | |
| 12418 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12419 ins_pipe( pipe_cmov_reg ); | |
| 12420 %} | |
| 12421 | |
|
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|
12422 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, memory src) %{ |
| 0 | 12423 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); |
| 12424 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); | |
| 12425 ins_cost(250); | |
| 12426 format %{ "CMOV$cmp $dst,$src" %} | |
| 12427 opcode(0x0F,0x40); | |
| 12428 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); | |
| 12429 ins_pipe( pipe_cmov_mem ); | |
| 12430 %} | |
| 12431 | |
| 12432 // Compare 2 longs and CMOVE ints. | |
| 12433 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{ | |
| 12434 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 12435 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); | |
| 12436 ins_cost(200); | |
| 12437 format %{ "CMOV$cmp $dst,$src" %} | |
| 12438 opcode(0x0F,0x40); | |
| 12439 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12440 ins_pipe( pipe_cmov_reg ); | |
| 12441 %} | |
| 12442 | |
| 12443 // Compare 2 longs and CMOVE doubles | |
|
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12444 instruct cmovDDPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regDPR dst, regDPR src) %{ |
| 0 | 12445 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); |
| 12446 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12447 ins_cost(200); | |
| 12448 expand %{ | |
|
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12449 fcmovDPR_regS(cmp,flags,dst,src); |
| 0 | 12450 %} |
| 12451 %} | |
| 12452 | |
| 12453 // Compare 2 longs and CMOVE doubles | |
|
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12454 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{ |
| 0 | 12455 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); |
| 12456 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12457 ins_cost(200); | |
| 12458 expand %{ | |
|
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12459 fcmovD_regS(cmp,flags,dst,src); |
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12460 %} |
|
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12461 %} |
|
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12462 |
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12463 instruct cmovFFPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regFPR dst, regFPR src) %{ |
|
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12464 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); |
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12465 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
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12466 ins_cost(200); |
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12467 expand %{ |
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12468 fcmovFPR_regS(cmp,flags,dst,src); |
| 0 | 12469 %} |
| 12470 %} | |
| 12471 | |
| 12472 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{ | |
|
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12473 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); |
| 0 | 12474 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
| 12475 ins_cost(200); | |
| 12476 expand %{ | |
| 12477 fcmovF_regS(cmp,flags,dst,src); | |
| 12478 %} | |
| 12479 %} | |
| 12480 | |
| 12481 //====== | |
| 12482 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares. | |
|
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12483 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, rRegI tmp ) %{ |
| 0 | 12484 match( Set flags (CmpL src zero )); |
| 12485 effect(TEMP tmp); | |
| 12486 ins_cost(200); | |
| 12487 format %{ "MOV $tmp,$src.lo\n\t" | |
| 12488 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %} | |
| 12489 ins_encode( long_cmp_flags0( src, tmp ) ); | |
| 12490 ins_pipe( ialu_reg_reg_long ); | |
| 12491 %} | |
| 12492 | |
| 12493 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares. | |
| 12494 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{ | |
| 12495 match( Set flags (CmpL src1 src2 )); | |
| 12496 ins_cost(200+300); | |
| 12497 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t" | |
| 12498 "JNE,s skip\n\t" | |
| 12499 "CMP $src1.hi,$src2.hi\n\t" | |
| 12500 "skip:\t" %} | |
| 12501 ins_encode( long_cmp_flags1( src1, src2 ) ); | |
| 12502 ins_pipe( ialu_cr_reg_reg ); | |
| 12503 %} | |
| 12504 | |
| 12505 // Long compare reg == zero/reg OR reg != zero/reg | |
| 12506 // Just a wrapper for a normal branch, plus the predicate test. | |
| 12507 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{ | |
| 12508 match(If cmp flags); | |
| 12509 effect(USE labl); | |
| 12510 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); | |
| 12511 expand %{ | |
| 12512 jmpCon(cmp,flags,labl); // JEQ or JNE... | |
| 12513 %} | |
| 12514 %} | |
| 12515 | |
| 12516 // Compare 2 longs and CMOVE longs. | |
| 12517 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{ | |
| 12518 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); | |
| 12519 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 12520 ins_cost(400); | |
| 12521 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12522 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12523 opcode(0x0F,0x40); | |
| 12524 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); | |
| 12525 ins_pipe( pipe_cmov_reg_long ); | |
| 12526 %} | |
| 12527 | |
| 12528 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{ | |
| 12529 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); | |
| 12530 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 12531 ins_cost(500); | |
| 12532 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12533 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12534 opcode(0x0F,0x40); | |
| 12535 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); | |
| 12536 ins_pipe( pipe_cmov_reg_long ); | |
| 12537 %} | |
| 12538 | |
| 12539 // Compare 2 longs and CMOVE ints. | |
|
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12540 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, rRegI src) %{ |
| 0 | 12541 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); |
| 12542 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); | |
| 12543 ins_cost(200); | |
| 12544 format %{ "CMOV$cmp $dst,$src" %} | |
| 12545 opcode(0x0F,0x40); | |
| 12546 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12547 ins_pipe( pipe_cmov_reg ); | |
| 12548 %} | |
| 12549 | |
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12550 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, memory src) %{ |
| 0 | 12551 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); |
| 12552 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); | |
| 12553 ins_cost(250); | |
| 12554 format %{ "CMOV$cmp $dst,$src" %} | |
| 12555 opcode(0x0F,0x40); | |
| 12556 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); | |
| 12557 ins_pipe( pipe_cmov_mem ); | |
| 12558 %} | |
| 12559 | |
| 12560 // Compare 2 longs and CMOVE ints. | |
| 12561 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{ | |
| 12562 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 12563 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); | |
| 12564 ins_cost(200); | |
| 12565 format %{ "CMOV$cmp $dst,$src" %} | |
| 12566 opcode(0x0F,0x40); | |
| 12567 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12568 ins_pipe( pipe_cmov_reg ); | |
| 12569 %} | |
| 12570 | |
| 12571 // Compare 2 longs and CMOVE doubles | |
|
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12572 instruct cmovDDPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regDPR dst, regDPR src) %{ |
| 0 | 12573 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); |
| 12574 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12575 ins_cost(200); | |
| 12576 expand %{ | |
|
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12577 fcmovDPR_regS(cmp,flags,dst,src); |
| 0 | 12578 %} |
| 12579 %} | |
| 12580 | |
| 12581 // Compare 2 longs and CMOVE doubles | |
|
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12582 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{ |
| 0 | 12583 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); |
| 12584 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12585 ins_cost(200); | |
| 12586 expand %{ | |
|
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12587 fcmovD_regS(cmp,flags,dst,src); |
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12588 %} |
|
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|
12589 %} |
|
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12590 |
|
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12591 instruct cmovFFPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regFPR dst, regFPR src) %{ |
|
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12592 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); |
|
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12593 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
|
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12594 ins_cost(200); |
|
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|
12595 expand %{ |
|
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12596 fcmovFPR_regS(cmp,flags,dst,src); |
| 0 | 12597 %} |
| 12598 %} | |
| 12599 | |
| 12600 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{ | |
|
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12601 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); |
| 0 | 12602 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
| 12603 ins_cost(200); | |
| 12604 expand %{ | |
| 12605 fcmovF_regS(cmp,flags,dst,src); | |
| 12606 %} | |
| 12607 %} | |
| 12608 | |
| 12609 //====== | |
| 12610 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares. | |
| 12611 // Same as cmpL_reg_flags_LEGT except must negate src | |
|
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12612 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, rRegI tmp ) %{ |
| 0 | 12613 match( Set flags (CmpL src zero )); |
| 12614 effect( TEMP tmp ); | |
| 12615 ins_cost(300); | |
| 12616 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t" | |
| 12617 "CMP $tmp,$src.lo\n\t" | |
| 12618 "SBB $tmp,$src.hi\n\t" %} | |
| 12619 ins_encode( long_cmp_flags3(src, tmp) ); | |
| 12620 ins_pipe( ialu_reg_reg_long ); | |
| 12621 %} | |
| 12622 | |
| 12623 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares. | |
| 12624 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands | |
| 12625 // requires a commuted test to get the same result. | |
|
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12626 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, rRegI tmp ) %{ |
| 0 | 12627 match( Set flags (CmpL src1 src2 )); |
| 12628 effect( TEMP tmp ); | |
| 12629 ins_cost(300); | |
| 12630 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t" | |
| 12631 "MOV $tmp,$src2.hi\n\t" | |
| 12632 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %} | |
| 12633 ins_encode( long_cmp_flags2( src2, src1, tmp ) ); | |
| 12634 ins_pipe( ialu_cr_reg_reg ); | |
| 12635 %} | |
| 12636 | |
| 12637 // Long compares reg < zero/req OR reg >= zero/req. | |
| 12638 // Just a wrapper for a normal branch, plus the predicate test | |
| 12639 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{ | |
| 12640 match(If cmp flags); | |
| 12641 effect(USE labl); | |
| 12642 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le ); | |
| 12643 ins_cost(300); | |
| 12644 expand %{ | |
| 12645 jmpCon(cmp,flags,labl); // JGT or JLE... | |
| 12646 %} | |
| 12647 %} | |
| 12648 | |
| 12649 // Compare 2 longs and CMOVE longs. | |
| 12650 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{ | |
| 12651 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); | |
| 12652 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 12653 ins_cost(400); | |
| 12654 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12655 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12656 opcode(0x0F,0x40); | |
| 12657 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); | |
| 12658 ins_pipe( pipe_cmov_reg_long ); | |
| 12659 %} | |
| 12660 | |
| 12661 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{ | |
| 12662 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); | |
| 12663 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 12664 ins_cost(500); | |
| 12665 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12666 "CMOV$cmp $dst.hi,$src.hi+4" %} | |
| 12667 opcode(0x0F,0x40); | |
| 12668 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); | |
| 12669 ins_pipe( pipe_cmov_reg_long ); | |
| 12670 %} | |
| 12671 | |
| 12672 // Compare 2 longs and CMOVE ints. | |
|
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12673 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, rRegI src) %{ |
| 0 | 12674 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); |
| 12675 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); | |
| 12676 ins_cost(200); | |
| 12677 format %{ "CMOV$cmp $dst,$src" %} | |
| 12678 opcode(0x0F,0x40); | |
| 12679 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12680 ins_pipe( pipe_cmov_reg ); | |
| 12681 %} | |
| 12682 | |
|
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12683 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, memory src) %{ |
| 0 | 12684 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); |
| 12685 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); | |
| 12686 ins_cost(250); | |
| 12687 format %{ "CMOV$cmp $dst,$src" %} | |
| 12688 opcode(0x0F,0x40); | |
| 12689 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); | |
| 12690 ins_pipe( pipe_cmov_mem ); | |
| 12691 %} | |
| 12692 | |
| 12693 // Compare 2 longs and CMOVE ptrs. | |
| 12694 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{ | |
| 12695 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 12696 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); | |
| 12697 ins_cost(200); | |
| 12698 format %{ "CMOV$cmp $dst,$src" %} | |
| 12699 opcode(0x0F,0x40); | |
| 12700 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12701 ins_pipe( pipe_cmov_reg ); | |
| 12702 %} | |
| 12703 | |
| 12704 // Compare 2 longs and CMOVE doubles | |
|
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12705 instruct cmovDDPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regDPR dst, regDPR src) %{ |
| 0 | 12706 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); |
| 12707 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12708 ins_cost(200); | |
| 12709 expand %{ | |
|
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12710 fcmovDPR_regS(cmp,flags,dst,src); |
| 0 | 12711 %} |
| 12712 %} | |
| 12713 | |
| 12714 // Compare 2 longs and CMOVE doubles | |
|
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12715 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{ |
| 0 | 12716 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); |
| 12717 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12718 ins_cost(200); | |
| 12719 expand %{ | |
|
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12720 fcmovD_regS(cmp,flags,dst,src); |
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12721 %} |
|
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12722 %} |
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12723 |
|
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12724 instruct cmovFFPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regFPR dst, regFPR src) %{ |
|
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12725 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); |
|
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12726 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
|
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12727 ins_cost(200); |
|
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12728 expand %{ |
|
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12729 fcmovFPR_regS(cmp,flags,dst,src); |
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12730 %} |
|
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12731 %} |
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12732 |
| 0 | 12733 |
| 12734 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{ | |
|
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12735 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); |
| 0 | 12736 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
| 12737 ins_cost(200); | |
| 12738 expand %{ | |
| 12739 fcmovF_regS(cmp,flags,dst,src); | |
| 12740 %} | |
| 12741 %} | |
| 12742 | |
| 12743 | |
| 12744 // ============================================================================ | |
| 12745 // Procedure Call/Return Instructions | |
| 12746 // Call Java Static Instruction | |
| 12747 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 12748 // compute_padding() functions will have to be adjusted. | |
| 12749 instruct CallStaticJavaDirect(method meth) %{ | |
| 12750 match(CallStaticJava); | |
|
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12751 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke()); |
| 0 | 12752 effect(USE meth); |
| 12753 | |
| 12754 ins_cost(300); | |
| 12755 format %{ "CALL,static " %} | |
| 12756 opcode(0xE8); /* E8 cd */ | |
| 12757 ins_encode( pre_call_FPU, | |
| 12758 Java_Static_Call( meth ), | |
| 12759 call_epilog, | |
| 12760 post_call_FPU ); | |
| 12761 ins_pipe( pipe_slow ); | |
| 12762 ins_alignment(4); | |
| 12763 %} | |
| 12764 | |
|
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12765 // Call Java Static Instruction (method handle version) |
|
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12766 // Note: If this code changes, the corresponding ret_addr_offset() and |
|
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12767 // compute_padding() functions will have to be adjusted. |
| 1567 | 12768 instruct CallStaticJavaHandle(method meth, eBPRegP ebp_mh_SP_save) %{ |
|
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12769 match(CallStaticJava); |
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12770 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke()); |
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12771 effect(USE meth); |
|
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12772 // EBP is saved by all callees (for interpreter stack correction). |
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12773 // We use it here for a similar purpose, in {preserve,restore}_SP. |
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12774 |
|
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12775 ins_cost(300); |
|
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12776 format %{ "CALL,static/MethodHandle " %} |
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12777 opcode(0xE8); /* E8 cd */ |
|
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12778 ins_encode( pre_call_FPU, |
|
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|
12779 preserve_SP, |
|
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12780 Java_Static_Call( meth ), |
|
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12781 restore_SP, |
|
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12782 call_epilog, |
|
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12783 post_call_FPU ); |
|
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12784 ins_pipe( pipe_slow ); |
|
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12785 ins_alignment(4); |
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12786 %} |
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12787 |
| 0 | 12788 // Call Java Dynamic Instruction |
| 12789 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 12790 // compute_padding() functions will have to be adjusted. | |
| 12791 instruct CallDynamicJavaDirect(method meth) %{ | |
| 12792 match(CallDynamicJava); | |
| 12793 effect(USE meth); | |
| 12794 | |
| 12795 ins_cost(300); | |
| 12796 format %{ "MOV EAX,(oop)-1\n\t" | |
| 12797 "CALL,dynamic" %} | |
| 12798 opcode(0xE8); /* E8 cd */ | |
| 12799 ins_encode( pre_call_FPU, | |
| 12800 Java_Dynamic_Call( meth ), | |
| 12801 call_epilog, | |
| 12802 post_call_FPU ); | |
| 12803 ins_pipe( pipe_slow ); | |
| 12804 ins_alignment(4); | |
| 12805 %} | |
| 12806 | |
| 12807 // Call Runtime Instruction | |
| 12808 instruct CallRuntimeDirect(method meth) %{ | |
| 12809 match(CallRuntime ); | |
| 12810 effect(USE meth); | |
| 12811 | |
| 12812 ins_cost(300); | |
| 12813 format %{ "CALL,runtime " %} | |
| 12814 opcode(0xE8); /* E8 cd */ | |
| 12815 // Use FFREEs to clear entries in float stack | |
| 12816 ins_encode( pre_call_FPU, | |
| 12817 FFree_Float_Stack_All, | |
| 12818 Java_To_Runtime( meth ), | |
| 12819 post_call_FPU ); | |
| 12820 ins_pipe( pipe_slow ); | |
| 12821 %} | |
| 12822 | |
| 12823 // Call runtime without safepoint | |
| 12824 instruct CallLeafDirect(method meth) %{ | |
| 12825 match(CallLeaf); | |
| 12826 effect(USE meth); | |
| 12827 | |
| 12828 ins_cost(300); | |
| 12829 format %{ "CALL_LEAF,runtime " %} | |
| 12830 opcode(0xE8); /* E8 cd */ | |
| 12831 ins_encode( pre_call_FPU, | |
| 12832 FFree_Float_Stack_All, | |
| 12833 Java_To_Runtime( meth ), | |
| 12834 Verify_FPU_For_Leaf, post_call_FPU ); | |
| 12835 ins_pipe( pipe_slow ); | |
| 12836 %} | |
| 12837 | |
| 12838 instruct CallLeafNoFPDirect(method meth) %{ | |
| 12839 match(CallLeafNoFP); | |
| 12840 effect(USE meth); | |
| 12841 | |
| 12842 ins_cost(300); | |
| 12843 format %{ "CALL_LEAF_NOFP,runtime " %} | |
| 12844 opcode(0xE8); /* E8 cd */ | |
| 12845 ins_encode(Java_To_Runtime(meth)); | |
| 12846 ins_pipe( pipe_slow ); | |
| 12847 %} | |
| 12848 | |
| 12849 | |
| 12850 // Return Instruction | |
| 12851 // Remove the return address & jump to it. | |
| 12852 instruct Ret() %{ | |
| 12853 match(Return); | |
| 12854 format %{ "RET" %} | |
| 12855 opcode(0xC3); | |
| 12856 ins_encode(OpcP); | |
| 12857 ins_pipe( pipe_jmp ); | |
| 12858 %} | |
| 12859 | |
| 12860 // Tail Call; Jump from runtime stub to Java code. | |
| 12861 // Also known as an 'interprocedural jump'. | |
| 12862 // Target of jump will eventually return to caller. | |
| 12863 // TailJump below removes the return address. | |
| 12864 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{ | |
| 12865 match(TailCall jump_target method_oop ); | |
| 12866 ins_cost(300); | |
| 12867 format %{ "JMP $jump_target \t# EBX holds method oop" %} | |
| 12868 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 12869 ins_encode( OpcP, RegOpc(jump_target) ); | |
| 12870 ins_pipe( pipe_jmp ); | |
| 12871 %} | |
| 12872 | |
| 12873 | |
| 12874 // Tail Jump; remove the return address; jump to target. | |
| 12875 // TailCall above leaves the return address around. | |
| 12876 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{ | |
| 12877 match( TailJump jump_target ex_oop ); | |
| 12878 ins_cost(300); | |
| 12879 format %{ "POP EDX\t# pop return address into dummy\n\t" | |
| 12880 "JMP $jump_target " %} | |
| 12881 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 12882 ins_encode( enc_pop_rdx, | |
| 12883 OpcP, RegOpc(jump_target) ); | |
| 12884 ins_pipe( pipe_jmp ); | |
| 12885 %} | |
| 12886 | |
| 12887 // Create exception oop: created by stack-crawling runtime code. | |
| 12888 // Created exception is now available to this handler, and is setup | |
| 12889 // just prior to jumping to this handler. No code emitted. | |
| 12890 instruct CreateException( eAXRegP ex_oop ) | |
| 12891 %{ | |
| 12892 match(Set ex_oop (CreateEx)); | |
| 12893 | |
| 12894 size(0); | |
| 12895 // use the following format syntax | |
| 12896 format %{ "# exception oop is in EAX; no code emitted" %} | |
| 12897 ins_encode(); | |
| 12898 ins_pipe( empty ); | |
| 12899 %} | |
| 12900 | |
| 12901 | |
| 12902 // Rethrow exception: | |
| 12903 // The exception oop will come in the first argument position. | |
| 12904 // Then JUMP (not call) to the rethrow stub code. | |
| 12905 instruct RethrowException() | |
| 12906 %{ | |
| 12907 match(Rethrow); | |
| 12908 | |
| 12909 // use the following format syntax | |
| 12910 format %{ "JMP rethrow_stub" %} | |
| 12911 ins_encode(enc_rethrow); | |
| 12912 ins_pipe( pipe_jmp ); | |
| 12913 %} | |
| 12914 | |
| 12915 // inlined locking and unlocking | |
| 12916 | |
| 12917 | |
| 4777 | 12918 instruct cmpFastLock( eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eRegP scr) %{ |
| 0 | 12919 match( Set cr (FastLock object box) ); |
| 4777 | 12920 effect( TEMP tmp, TEMP scr, USE_KILL box ); |
| 0 | 12921 ins_cost(300); |
| 4777 | 12922 format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr" %} |
| 0 | 12923 ins_encode( Fast_Lock(object,box,tmp,scr) ); |
| 12924 ins_pipe( pipe_slow ); | |
| 12925 %} | |
| 12926 | |
| 12927 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{ | |
| 12928 match( Set cr (FastUnlock object box) ); | |
| 4777 | 12929 effect( TEMP tmp, USE_KILL box ); |
| 0 | 12930 ins_cost(300); |
| 4777 | 12931 format %{ "FASTUNLOCK $object,$box\t! kills $box,$tmp" %} |
| 0 | 12932 ins_encode( Fast_Unlock(object,box,tmp) ); |
| 12933 ins_pipe( pipe_slow ); | |
| 12934 %} | |
| 12935 | |
| 12936 | |
| 12937 | |
| 12938 // ============================================================================ | |
| 12939 // Safepoint Instruction | |
| 12940 instruct safePoint_poll(eFlagsReg cr) %{ | |
| 12941 match(SafePoint); | |
| 12942 effect(KILL cr); | |
| 12943 | |
| 12944 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page. | |
| 12945 // On SPARC that might be acceptable as we can generate the address with | |
| 12946 // just a sethi, saving an or. By polling at offset 0 we can end up | |
| 12947 // putting additional pressure on the index-0 in the D$. Because of | |
| 12948 // alignment (just like the situation at hand) the lower indices tend | |
| 12949 // to see more traffic. It'd be better to change the polling address | |
| 12950 // to offset 0 of the last $line in the polling page. | |
| 12951 | |
| 12952 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %} | |
| 12953 ins_cost(125); | |
| 12954 size(6) ; | |
| 12955 ins_encode( Safepoint_Poll() ); | |
| 12956 ins_pipe( ialu_reg_mem ); | |
| 12957 %} | |
| 12958 | |
| 4950 | 12959 |
| 12960 // ============================================================================ | |
| 12961 // This name is KNOWN by the ADLC and cannot be changed. | |
| 12962 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type | |
| 12963 // for this guy. | |
| 12964 instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{ | |
| 12965 match(Set dst (ThreadLocal)); | |
| 12966 effect(DEF dst, KILL cr); | |
| 12967 | |
| 12968 format %{ "MOV $dst, Thread::current()" %} | |
| 12969 ins_encode %{ | |
| 12970 Register dstReg = as_Register($dst$$reg); | |
| 12971 __ get_thread(dstReg); | |
| 12972 %} | |
| 12973 ins_pipe( ialu_reg_fat ); | |
| 12974 %} | |
| 12975 | |
| 12976 | |
| 12977 | |
| 0 | 12978 //----------PEEPHOLE RULES----------------------------------------------------- |
| 12979 // These must follow all instruction definitions as they use the names | |
| 12980 // defined in the instructions definitions. | |
| 12981 // | |
| 605 | 12982 // peepmatch ( root_instr_name [preceding_instruction]* ); |
| 0 | 12983 // |
| 12984 // peepconstraint %{ | |
| 12985 // (instruction_number.operand_name relational_op instruction_number.operand_name | |
| 12986 // [, ...] ); | |
| 12987 // // instruction numbers are zero-based using left to right order in peepmatch | |
| 12988 // | |
| 12989 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); | |
| 12990 // // provide an instruction_number.operand_name for each operand that appears | |
| 12991 // // in the replacement instruction's match rule | |
| 12992 // | |
| 12993 // ---------VM FLAGS--------------------------------------------------------- | |
| 12994 // | |
| 12995 // All peephole optimizations can be turned off using -XX:-OptoPeephole | |
| 12996 // | |
| 12997 // Each peephole rule is given an identifying number starting with zero and | |
| 12998 // increasing by one in the order seen by the parser. An individual peephole | |
| 12999 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# | |
| 13000 // on the command-line. | |
| 13001 // | |
| 13002 // ---------CURRENT LIMITATIONS---------------------------------------------- | |
| 13003 // | |
| 13004 // Only match adjacent instructions in same basic block | |
| 13005 // Only equality constraints | |
| 13006 // Only constraints between operands, not (0.dest_reg == EAX_enc) | |
| 13007 // Only one replacement instruction | |
| 13008 // | |
| 13009 // ---------EXAMPLE---------------------------------------------------------- | |
| 13010 // | |
| 13011 // // pertinent parts of existing instructions in architecture description | |
|
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13012 // instruct movI(rRegI dst, rRegI src) %{ |
| 0 | 13013 // match(Set dst (CopyI src)); |
| 13014 // %} | |
| 13015 // | |
|
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13016 // instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{ |
| 0 | 13017 // match(Set dst (AddI dst src)); |
| 13018 // effect(KILL cr); | |
| 13019 // %} | |
| 13020 // | |
| 13021 // // Change (inc mov) to lea | |
| 13022 // peephole %{ | |
| 13023 // // increment preceeded by register-register move | |
| 13024 // peepmatch ( incI_eReg movI ); | |
| 13025 // // require that the destination register of the increment | |
| 13026 // // match the destination register of the move | |
| 13027 // peepconstraint ( 0.dst == 1.dst ); | |
| 13028 // // construct a replacement instruction that sets | |
| 13029 // // the destination to ( move's source register + one ) | |
| 13030 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13031 // %} | |
| 13032 // | |
| 13033 // Implementation no longer uses movX instructions since | |
| 13034 // machine-independent system no longer uses CopyX nodes. | |
| 13035 // | |
| 13036 // peephole %{ | |
| 13037 // peepmatch ( incI_eReg movI ); | |
| 13038 // peepconstraint ( 0.dst == 1.dst ); | |
| 13039 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13040 // %} | |
| 13041 // | |
| 13042 // peephole %{ | |
| 13043 // peepmatch ( decI_eReg movI ); | |
| 13044 // peepconstraint ( 0.dst == 1.dst ); | |
| 13045 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13046 // %} | |
| 13047 // | |
| 13048 // peephole %{ | |
| 13049 // peepmatch ( addI_eReg_imm movI ); | |
| 13050 // peepconstraint ( 0.dst == 1.dst ); | |
| 13051 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13052 // %} | |
| 13053 // | |
| 13054 // peephole %{ | |
| 13055 // peepmatch ( addP_eReg_imm movP ); | |
| 13056 // peepconstraint ( 0.dst == 1.dst ); | |
| 13057 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13058 // %} | |
| 13059 | |
| 13060 // // Change load of spilled value to only a spill | |
|
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13061 // instruct storeI(memory mem, rRegI src) %{ |
| 0 | 13062 // match(Set mem (StoreI mem src)); |
| 13063 // %} | |
| 13064 // | |
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changeset
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13065 // instruct loadI(rRegI dst, memory mem) %{ |
| 0 | 13066 // match(Set dst (LoadI mem)); |
| 13067 // %} | |
| 13068 // | |
| 13069 peephole %{ | |
| 13070 peepmatch ( loadI storeI ); | |
| 13071 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); | |
| 13072 peepreplace ( storeI( 1.mem 1.mem 1.src ) ); | |
| 13073 %} | |
| 13074 | |
| 13075 //----------SMARTSPILL RULES--------------------------------------------------- | |
| 13076 // These must follow all instruction definitions as they use the names | |
| 13077 // defined in the instructions definitions. |