Mercurial > hg > truffle
annotate src/cpu/x86/vm/x86_32.ad @ 2008:2f644f85485d
6961690: load oops from constant table on SPARC
Summary: oops should be loaded from the constant table of an nmethod instead of materializing them with a long code sequence.
Reviewed-by: never, kvn
| author | twisti |
|---|---|
| date | Fri, 03 Dec 2010 01:34:31 -0800 |
| parents | 2fe998383789 |
| children | 6bbaedb03534 |
| rev | line source |
|---|---|
| 0 | 1 // |
|
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2 // Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 // | |
| 5 // This code is free software; you can redistribute it and/or modify it | |
| 6 // under the terms of the GNU General Public License version 2 only, as | |
| 7 // published by the Free Software Foundation. | |
| 8 // | |
| 9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 // version 2 for more details (a copy is included in the LICENSE file that | |
| 13 // accompanied this code). | |
| 14 // | |
| 15 // You should have received a copy of the GNU General Public License version | |
| 16 // 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 // | |
|
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19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 // or visit www.oracle.com if you need additional information or have any |
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21 // questions. |
| 0 | 22 // |
| 23 // | |
| 24 | |
| 25 // X86 Architecture Description File | |
| 26 | |
| 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ | |
| 28 // This information is used by the matcher and the register allocator to | |
| 29 // describe individual registers and classes of registers within the target | |
| 30 // archtecture. | |
| 31 | |
| 32 register %{ | |
| 33 //----------Architecture Description Register Definitions---------------------- | |
| 34 // General Registers | |
| 35 // "reg_def" name ( register save type, C convention save type, | |
| 36 // ideal register type, encoding ); | |
| 37 // Register Save Types: | |
| 38 // | |
| 39 // NS = No-Save: The register allocator assumes that these registers | |
| 40 // can be used without saving upon entry to the method, & | |
| 41 // that they do not need to be saved at call sites. | |
| 42 // | |
| 43 // SOC = Save-On-Call: The register allocator assumes that these registers | |
| 44 // can be used without saving upon entry to the method, | |
| 45 // but that they must be saved at call sites. | |
| 46 // | |
| 47 // SOE = Save-On-Entry: The register allocator assumes that these registers | |
| 48 // must be saved before using them upon entry to the | |
| 49 // method, but they do not need to be saved at call | |
| 50 // sites. | |
| 51 // | |
| 52 // AS = Always-Save: The register allocator assumes that these registers | |
| 53 // must be saved before using them upon entry to the | |
| 54 // method, & that they must be saved at call sites. | |
| 55 // | |
| 56 // Ideal Register Type is used to determine how to save & restore a | |
| 57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get | |
| 58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. | |
| 59 // | |
| 60 // The encoding number is the actual bit-pattern placed into the opcodes. | |
| 61 | |
| 62 // General Registers | |
| 63 // Previously set EBX, ESI, and EDI as save-on-entry for java code | |
| 64 // Turn off SOE in java-code due to frequent use of uncommon-traps. | |
| 65 // Now that allocator is better, turn on ESI and EDI as SOE registers. | |
| 66 | |
| 67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()); | |
| 68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()); | |
| 69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()); | |
| 70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()); | |
| 71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code | |
| 72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg()); | |
| 73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()); | |
| 74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg()); | |
| 75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg()); | |
| 76 | |
| 77 // Special Registers | |
| 78 reg_def EFLAGS(SOC, SOC, 0, 8, VMRegImpl::Bad()); | |
| 79 | |
| 80 // Float registers. We treat TOS/FPR0 special. It is invisible to the | |
| 81 // allocator, and only shows up in the encodings. | |
| 82 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad()); | |
| 83 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad()); | |
| 84 // Ok so here's the trick FPR1 is really st(0) except in the midst | |
| 85 // of emission of assembly for a machnode. During the emission the fpu stack | |
| 86 // is pushed making FPR1 == st(1) temporarily. However at any safepoint | |
| 87 // the stack will not have this element so FPR1 == st(0) from the | |
| 88 // oopMap viewpoint. This same weirdness with numbering causes | |
| 89 // instruction encoding to have to play games with the register | |
| 90 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation | |
| 91 // where it does flt->flt moves to see an example | |
| 92 // | |
| 93 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()); | |
| 94 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next()); | |
| 95 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()); | |
| 96 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next()); | |
| 97 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()); | |
| 98 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next()); | |
| 99 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()); | |
| 100 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next()); | |
| 101 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()); | |
| 102 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next()); | |
| 103 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()); | |
| 104 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next()); | |
| 105 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()); | |
| 106 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next()); | |
| 107 | |
| 108 // XMM registers. 128-bit registers or 4 words each, labeled a-d. | |
| 109 // Word a in each register holds a Float, words ab hold a Double. | |
| 110 // We currently do not use the SIMD capabilities, so registers cd | |
| 111 // are unused at the moment. | |
| 112 reg_def XMM0a( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()); | |
| 113 reg_def XMM0b( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next()); | |
| 114 reg_def XMM1a( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()); | |
| 115 reg_def XMM1b( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next()); | |
| 116 reg_def XMM2a( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()); | |
| 117 reg_def XMM2b( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next()); | |
| 118 reg_def XMM3a( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()); | |
| 119 reg_def XMM3b( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next()); | |
| 120 reg_def XMM4a( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()); | |
| 121 reg_def XMM4b( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next()); | |
| 122 reg_def XMM5a( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()); | |
| 123 reg_def XMM5b( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next()); | |
| 124 reg_def XMM6a( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()); | |
| 125 reg_def XMM6b( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next()); | |
| 126 reg_def XMM7a( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()); | |
| 127 reg_def XMM7b( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next()); | |
| 128 | |
| 129 // Specify priority of register selection within phases of register | |
| 130 // allocation. Highest priority is first. A useful heuristic is to | |
| 131 // give registers a low priority when they are required by machine | |
| 132 // instructions, like EAX and EDX. Registers which are used as | |
| 605 | 133 // pairs must fall on an even boundary (witness the FPR#L's in this list). |
| 0 | 134 // For the Intel integer registers, the equivalent Long pairs are |
| 135 // EDX:EAX, EBX:ECX, and EDI:EBP. | |
| 136 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP, | |
| 137 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H, | |
| 138 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H, | |
| 139 FPR6L, FPR6H, FPR7L, FPR7H ); | |
| 140 | |
| 141 alloc_class chunk1( XMM0a, XMM0b, | |
| 142 XMM1a, XMM1b, | |
| 143 XMM2a, XMM2b, | |
| 144 XMM3a, XMM3b, | |
| 145 XMM4a, XMM4b, | |
| 146 XMM5a, XMM5b, | |
| 147 XMM6a, XMM6b, | |
| 148 XMM7a, XMM7b, EFLAGS); | |
| 149 | |
| 150 | |
| 151 //----------Architecture Description Register Classes-------------------------- | |
| 152 // Several register classes are automatically defined based upon information in | |
| 153 // this architecture description. | |
| 154 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ ) | |
| 155 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ ) | |
| 156 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ ) | |
| 157 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) | |
| 158 // | |
| 159 // Class for all registers | |
| 160 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP); | |
| 161 // Class for general registers | |
| 162 reg_class e_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX); | |
| 163 // Class for general registers which may be used for implicit null checks on win95 | |
| 164 // Also safe for use by tailjump. We don't want to allocate in rbp, | |
| 165 reg_class e_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX); | |
| 166 // Class of "X" registers | |
| 167 reg_class x_reg(EBX, ECX, EDX, EAX); | |
| 168 // Class of registers that can appear in an address with no offset. | |
| 169 // EBP and ESP require an extra instruction byte for zero offset. | |
| 170 // Used in fast-unlock | |
| 171 reg_class p_reg(EDX, EDI, ESI, EBX); | |
| 172 // Class for general registers not including ECX | |
| 173 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX); | |
| 174 // Class for general registers not including EAX | |
| 175 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX); | |
| 176 // Class for general registers not including EAX or EBX. | |
| 177 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP); | |
| 178 // Class of EAX (for multiply and divide operations) | |
| 179 reg_class eax_reg(EAX); | |
| 180 // Class of EBX (for atomic add) | |
| 181 reg_class ebx_reg(EBX); | |
| 182 // Class of ECX (for shift and JCXZ operations and cmpLTMask) | |
| 183 reg_class ecx_reg(ECX); | |
| 184 // Class of EDX (for multiply and divide operations) | |
| 185 reg_class edx_reg(EDX); | |
| 186 // Class of EDI (for synchronization) | |
| 187 reg_class edi_reg(EDI); | |
| 188 // Class of ESI (for synchronization) | |
| 189 reg_class esi_reg(ESI); | |
| 190 // Singleton class for interpreter's stack pointer | |
| 191 reg_class ebp_reg(EBP); | |
| 192 // Singleton class for stack pointer | |
| 193 reg_class sp_reg(ESP); | |
| 194 // Singleton class for instruction pointer | |
| 195 // reg_class ip_reg(EIP); | |
| 196 // Singleton class for condition codes | |
| 197 reg_class int_flags(EFLAGS); | |
| 198 // Class of integer register pairs | |
| 199 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI ); | |
| 200 // Class of integer register pairs that aligns with calling convention | |
| 201 reg_class eadx_reg( EAX,EDX ); | |
| 202 reg_class ebcx_reg( ECX,EBX ); | |
| 203 // Not AX or DX, used in divides | |
| 204 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP ); | |
| 205 | |
| 206 // Floating point registers. Notice FPR0 is not a choice. | |
| 207 // FPR0 is not ever allocated; we use clever encodings to fake | |
| 208 // a 2-address instructions out of Intels FP stack. | |
| 209 reg_class flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L ); | |
| 210 | |
| 211 // make a register class for SSE registers | |
| 212 reg_class xmm_reg(XMM0a, XMM1a, XMM2a, XMM3a, XMM4a, XMM5a, XMM6a, XMM7a); | |
| 213 | |
| 214 // make a double register class for SSE2 registers | |
| 215 reg_class xdb_reg(XMM0a,XMM0b, XMM1a,XMM1b, XMM2a,XMM2b, XMM3a,XMM3b, | |
| 216 XMM4a,XMM4b, XMM5a,XMM5b, XMM6a,XMM6b, XMM7a,XMM7b ); | |
| 217 | |
| 218 reg_class dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H, | |
| 219 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H, | |
| 220 FPR7L,FPR7H ); | |
| 221 | |
| 222 reg_class flt_reg0( FPR1L ); | |
| 223 reg_class dbl_reg0( FPR1L,FPR1H ); | |
| 224 reg_class dbl_reg1( FPR2L,FPR2H ); | |
| 225 reg_class dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H, | |
| 226 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H ); | |
| 227 | |
| 228 // XMM6 and XMM7 could be used as temporary registers for long, float and | |
| 229 // double values for SSE2. | |
| 230 reg_class xdb_reg6( XMM6a,XMM6b ); | |
| 231 reg_class xdb_reg7( XMM7a,XMM7b ); | |
| 232 %} | |
| 233 | |
| 234 | |
| 235 //----------SOURCE BLOCK------------------------------------------------------- | |
| 236 // This is a block of C++ code which provides values, functions, and | |
| 237 // definitions necessary in the rest of the architecture description | |
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238 source_hpp %{ |
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239 // Must be visible to the DFA in dfa_x86_32.cpp |
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240 extern bool is_operand_hi32_zero(Node* n); |
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241 %} |
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242 |
| 0 | 243 source %{ |
| 304 | 244 #define RELOC_IMM32 Assembler::imm_operand |
| 0 | 245 #define RELOC_DISP32 Assembler::disp32_operand |
| 246 | |
| 247 #define __ _masm. | |
| 248 | |
| 249 // How to find the high register of a Long pair, given the low register | |
| 250 #define HIGH_FROM_LOW(x) ((x)+2) | |
| 251 | |
| 252 // These masks are used to provide 128-bit aligned bitmasks to the XMM | |
| 253 // instructions, to allow sign-masking or sign-bit flipping. They allow | |
| 254 // fast versions of NegF/NegD and AbsF/AbsD. | |
| 255 | |
| 256 // Note: 'double' and 'long long' have 32-bits alignment on x86. | |
| 257 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { | |
| 258 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address | |
| 259 // of 128-bits operands for SSE instructions. | |
| 260 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF))); | |
| 261 // Store the value to a 128-bits operand. | |
| 262 operand[0] = lo; | |
| 263 operand[1] = hi; | |
| 264 return operand; | |
| 265 } | |
| 266 | |
| 267 // Buffer for 128-bits masks used by SSE instructions. | |
| 268 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) | |
| 269 | |
| 270 // Static initialization during VM startup. | |
| 271 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); | |
| 272 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); | |
| 273 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000)); | |
| 274 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000)); | |
| 275 | |
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276 // Offset hacking within calls. |
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277 static int pre_call_FPU_size() { |
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278 if (Compile::current()->in_24_bit_fp_mode()) |
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279 return 6; // fldcw |
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280 return 0; |
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281 } |
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282 |
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283 static int preserve_SP_size() { |
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284 return LP64_ONLY(1 +) 2; // [rex,] op, rm(reg/reg) |
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285 } |
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286 |
| 0 | 287 // !!!!! Special hack to get all type of calls to specify the byte offset |
| 288 // from the start of the call to the point where the return address | |
| 289 // will point. | |
| 290 int MachCallStaticJavaNode::ret_addr_offset() { | |
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291 int offset = 5 + pre_call_FPU_size(); // 5 bytes from start of call to where return address points |
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292 if (_method_handle_invoke) |
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293 offset += preserve_SP_size(); |
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294 return offset; |
| 0 | 295 } |
| 296 | |
| 297 int MachCallDynamicJavaNode::ret_addr_offset() { | |
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298 return 10 + pre_call_FPU_size(); // 10 bytes from start of call to where return address points |
| 0 | 299 } |
| 300 | |
| 301 static int sizeof_FFree_Float_Stack_All = -1; | |
| 302 | |
| 303 int MachCallRuntimeNode::ret_addr_offset() { | |
| 304 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already"); | |
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305 return sizeof_FFree_Float_Stack_All + 5 + pre_call_FPU_size(); |
| 0 | 306 } |
| 307 | |
| 308 // Indicate if the safepoint node needs the polling page as an input. | |
| 309 // Since x86 does have absolute addressing, it doesn't. | |
| 310 bool SafePointNode::needs_polling_address_input() { | |
| 311 return false; | |
| 312 } | |
| 313 | |
| 314 // | |
| 315 // Compute padding required for nodes which need alignment | |
| 316 // | |
| 317 | |
| 318 // The address of the call instruction needs to be 4-byte aligned to | |
| 319 // ensure that it does not span a cache line so that it can be patched. | |
| 320 int CallStaticJavaDirectNode::compute_padding(int current_offset) const { | |
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321 current_offset += pre_call_FPU_size(); // skip fldcw, if any |
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322 current_offset += 1; // skip call opcode byte |
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323 return round_to(current_offset, alignment_required()) - current_offset; |
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324 } |
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325 |
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326 // The address of the call instruction needs to be 4-byte aligned to |
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327 // ensure that it does not span a cache line so that it can be patched. |
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328 int CallStaticJavaHandleNode::compute_padding(int current_offset) const { |
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329 current_offset += pre_call_FPU_size(); // skip fldcw, if any |
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330 current_offset += preserve_SP_size(); // skip mov rbp, rsp |
| 0 | 331 current_offset += 1; // skip call opcode byte |
| 332 return round_to(current_offset, alignment_required()) - current_offset; | |
| 333 } | |
| 334 | |
| 335 // The address of the call instruction needs to be 4-byte aligned to | |
| 336 // ensure that it does not span a cache line so that it can be patched. | |
| 337 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const { | |
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338 current_offset += pre_call_FPU_size(); // skip fldcw, if any |
| 0 | 339 current_offset += 5; // skip MOV instruction |
| 340 current_offset += 1; // skip call opcode byte | |
| 341 return round_to(current_offset, alignment_required()) - current_offset; | |
| 342 } | |
| 343 | |
| 344 #ifndef PRODUCT | |
| 345 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream* st ) const { | |
| 346 st->print("INT3"); | |
| 347 } | |
| 348 #endif | |
| 349 | |
| 350 // EMIT_RM() | |
| 351 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) { | |
| 352 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3); | |
| 1748 | 353 cbuf.insts()->emit_int8(c); |
| 0 | 354 } |
| 355 | |
| 356 // EMIT_CC() | |
| 357 void emit_cc(CodeBuffer &cbuf, int f1, int f2) { | |
| 358 unsigned char c = (unsigned char)( f1 | f2 ); | |
| 1748 | 359 cbuf.insts()->emit_int8(c); |
| 0 | 360 } |
| 361 | |
| 362 // EMIT_OPCODE() | |
| 363 void emit_opcode(CodeBuffer &cbuf, int code) { | |
| 1748 | 364 cbuf.insts()->emit_int8((unsigned char) code); |
| 0 | 365 } |
| 366 | |
| 367 // EMIT_OPCODE() w/ relocation information | |
| 368 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) { | |
| 1748 | 369 cbuf.relocate(cbuf.insts_mark() + offset, reloc); |
| 0 | 370 emit_opcode(cbuf, code); |
| 371 } | |
| 372 | |
| 373 // EMIT_D8() | |
| 374 void emit_d8(CodeBuffer &cbuf, int d8) { | |
| 1748 | 375 cbuf.insts()->emit_int8((unsigned char) d8); |
| 0 | 376 } |
| 377 | |
| 378 // EMIT_D16() | |
| 379 void emit_d16(CodeBuffer &cbuf, int d16) { | |
| 1748 | 380 cbuf.insts()->emit_int16(d16); |
| 0 | 381 } |
| 382 | |
| 383 // EMIT_D32() | |
| 384 void emit_d32(CodeBuffer &cbuf, int d32) { | |
| 1748 | 385 cbuf.insts()->emit_int32(d32); |
| 0 | 386 } |
| 387 | |
| 388 // emit 32 bit value and construct relocation entry from relocInfo::relocType | |
| 389 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc, | |
| 390 int format) { | |
| 1748 | 391 cbuf.relocate(cbuf.insts_mark(), reloc, format); |
| 392 cbuf.insts()->emit_int32(d32); | |
| 0 | 393 } |
| 394 | |
| 395 // emit 32 bit value and construct relocation entry from RelocationHolder | |
| 396 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec, | |
| 397 int format) { | |
| 398 #ifdef ASSERT | |
| 399 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) { | |
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400 assert(oop(d32)->is_oop() && (ScavengeRootsInCode || !oop(d32)->is_scavengable()), "cannot embed scavengable oops in code"); |
| 0 | 401 } |
| 402 #endif | |
| 1748 | 403 cbuf.relocate(cbuf.insts_mark(), rspec, format); |
| 404 cbuf.insts()->emit_int32(d32); | |
| 0 | 405 } |
| 406 | |
| 407 // Access stack slot for load or store | |
| 408 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) { | |
| 409 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src]) | |
| 410 if( -128 <= disp && disp <= 127 ) { | |
| 411 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte | |
| 412 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte | |
| 413 emit_d8 (cbuf, disp); // Displacement // R/M byte | |
| 414 } else { | |
| 415 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte | |
| 416 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte | |
| 417 emit_d32(cbuf, disp); // Displacement // R/M byte | |
| 418 } | |
| 419 } | |
| 420 | |
| 421 // eRegI ereg, memory mem) %{ // emit_reg_mem | |
| 422 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, bool displace_is_oop ) { | |
| 423 // There is no index & no scale, use form without SIB byte | |
| 424 if ((index == 0x4) && | |
| 425 (scale == 0) && (base != ESP_enc)) { | |
| 426 // If no displacement, mode is 0x0; unless base is [EBP] | |
| 427 if ( (displace == 0) && (base != EBP_enc) ) { | |
| 428 emit_rm(cbuf, 0x0, reg_encoding, base); | |
| 429 } | |
| 430 else { // If 8-bit displacement, mode 0x1 | |
| 431 if ((displace >= -128) && (displace <= 127) | |
| 432 && !(displace_is_oop) ) { | |
| 433 emit_rm(cbuf, 0x1, reg_encoding, base); | |
| 434 emit_d8(cbuf, displace); | |
| 435 } | |
| 436 else { // If 32-bit displacement | |
| 437 if (base == -1) { // Special flag for absolute address | |
| 438 emit_rm(cbuf, 0x0, reg_encoding, 0x5); | |
| 439 // (manual lies; no SIB needed here) | |
| 440 if ( displace_is_oop ) { | |
| 441 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1); | |
| 442 } else { | |
| 443 emit_d32 (cbuf, displace); | |
| 444 } | |
| 445 } | |
| 446 else { // Normal base + offset | |
| 447 emit_rm(cbuf, 0x2, reg_encoding, base); | |
| 448 if ( displace_is_oop ) { | |
| 449 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1); | |
| 450 } else { | |
| 451 emit_d32 (cbuf, displace); | |
| 452 } | |
| 453 } | |
| 454 } | |
| 455 } | |
| 456 } | |
| 457 else { // Else, encode with the SIB byte | |
| 458 // If no displacement, mode is 0x0; unless base is [EBP] | |
| 459 if (displace == 0 && (base != EBP_enc)) { // If no displacement | |
| 460 emit_rm(cbuf, 0x0, reg_encoding, 0x4); | |
| 461 emit_rm(cbuf, scale, index, base); | |
| 462 } | |
| 463 else { // If 8-bit displacement, mode 0x1 | |
| 464 if ((displace >= -128) && (displace <= 127) | |
| 465 && !(displace_is_oop) ) { | |
| 466 emit_rm(cbuf, 0x1, reg_encoding, 0x4); | |
| 467 emit_rm(cbuf, scale, index, base); | |
| 468 emit_d8(cbuf, displace); | |
| 469 } | |
| 470 else { // If 32-bit displacement | |
| 471 if (base == 0x04 ) { | |
| 472 emit_rm(cbuf, 0x2, reg_encoding, 0x4); | |
| 473 emit_rm(cbuf, scale, index, 0x04); | |
| 474 } else { | |
| 475 emit_rm(cbuf, 0x2, reg_encoding, 0x4); | |
| 476 emit_rm(cbuf, scale, index, base); | |
| 477 } | |
| 478 if ( displace_is_oop ) { | |
| 479 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1); | |
| 480 } else { | |
| 481 emit_d32 (cbuf, displace); | |
| 482 } | |
| 483 } | |
| 484 } | |
| 485 } | |
| 486 } | |
| 487 | |
| 488 | |
| 489 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) { | |
| 490 if( dst_encoding == src_encoding ) { | |
| 491 // reg-reg copy, use an empty encoding | |
| 492 } else { | |
| 493 emit_opcode( cbuf, 0x8B ); | |
| 494 emit_rm(cbuf, 0x3, dst_encoding, src_encoding ); | |
| 495 } | |
| 496 } | |
| 497 | |
| 498 void encode_CopyXD( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) { | |
| 499 if( dst_encoding == src_encoding ) { | |
| 500 // reg-reg copy, use an empty encoding | |
| 501 } else { | |
| 502 MacroAssembler _masm(&cbuf); | |
| 503 | |
| 504 __ movdqa(as_XMMRegister(dst_encoding), as_XMMRegister(src_encoding)); | |
| 505 } | |
| 506 } | |
| 507 | |
| 508 | |
| 509 //============================================================================= | |
| 2008 | 510 const bool Matcher::constant_table_absolute_addressing = true; |
| 511 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty; | |
| 512 | |
| 513 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { | |
| 514 // Empty encoding | |
| 515 } | |
| 516 | |
| 517 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const { | |
| 518 return 0; | |
| 519 } | |
| 520 | |
| 521 #ifndef PRODUCT | |
| 522 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { | |
| 523 st->print("# MachConstantBaseNode (empty encoding)"); | |
| 524 } | |
| 525 #endif | |
| 526 | |
| 527 | |
| 528 //============================================================================= | |
| 0 | 529 #ifndef PRODUCT |
| 530 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { | |
| 531 Compile* C = ra_->C; | |
| 532 if( C->in_24_bit_fp_mode() ) { | |
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533 st->print("FLDCW 24 bit fpu control word"); |
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534 st->print_cr(""); st->print("\t"); |
| 0 | 535 } |
| 536 | |
| 537 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 538 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 539 // Remove two words for return addr and rbp, | |
| 540 framesize -= 2*wordSize; | |
| 541 | |
| 542 // Calls to C2R adapters often do not accept exceptional returns. | |
| 543 // We require that their callers must bang for them. But be careful, because | |
| 544 // some VM calls (such as call site linkage) can use several kilobytes of | |
| 545 // stack. But the stack safety zone should account for that. | |
| 546 // See bugs 4446381, 4468289, 4497237. | |
| 547 if (C->need_stack_bang(framesize)) { | |
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548 st->print_cr("# stack bang"); st->print("\t"); |
| 0 | 549 } |
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550 st->print_cr("PUSHL EBP"); st->print("\t"); |
| 0 | 551 |
| 552 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth | |
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553 st->print("PUSH 0xBADB100D\t# Majik cookie for stack depth check"); |
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554 st->print_cr(""); st->print("\t"); |
| 0 | 555 framesize -= wordSize; |
| 556 } | |
| 557 | |
| 558 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) { | |
| 559 if (framesize) { | |
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560 st->print("SUB ESP,%d\t# Create frame",framesize); |
| 0 | 561 } |
| 562 } else { | |
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563 st->print("SUB ESP,%d\t# Create frame",framesize); |
| 0 | 564 } |
| 565 } | |
| 566 #endif | |
| 567 | |
| 568 | |
| 569 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 570 Compile* C = ra_->C; | |
| 571 | |
| 572 if (UseSSE >= 2 && VerifyFPU) { | |
| 573 MacroAssembler masm(&cbuf); | |
| 574 masm.verify_FPU(0, "FPU stack must be clean on entry"); | |
| 575 } | |
| 576 | |
| 577 // WARNING: Initial instruction MUST be 5 bytes or longer so that | |
| 578 // NativeJump::patch_verified_entry will be able to patch out the entry | |
| 579 // code safely. The fldcw is ok at 6 bytes, the push to verify stack | |
| 580 // depth is ok at 5 bytes, the frame allocation can be either 3 or | |
| 581 // 6 bytes. So if we don't do the fldcw or the push then we must | |
| 582 // use the 6 byte frame allocation even if we have no frame. :-( | |
| 583 // If method sets FPU control word do it now | |
| 584 if( C->in_24_bit_fp_mode() ) { | |
| 585 MacroAssembler masm(&cbuf); | |
| 586 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); | |
| 587 } | |
| 588 | |
| 589 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 590 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 591 // Remove two words for return addr and rbp, | |
| 592 framesize -= 2*wordSize; | |
| 593 | |
| 594 // Calls to C2R adapters often do not accept exceptional returns. | |
| 595 // We require that their callers must bang for them. But be careful, because | |
| 596 // some VM calls (such as call site linkage) can use several kilobytes of | |
| 597 // stack. But the stack safety zone should account for that. | |
| 598 // See bugs 4446381, 4468289, 4497237. | |
| 599 if (C->need_stack_bang(framesize)) { | |
| 600 MacroAssembler masm(&cbuf); | |
| 601 masm.generate_stack_overflow_check(framesize); | |
| 602 } | |
| 603 | |
| 604 // We always push rbp, so that on return to interpreter rbp, will be | |
| 605 // restored correctly and we can correct the stack. | |
| 606 emit_opcode(cbuf, 0x50 | EBP_enc); | |
| 607 | |
| 608 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth | |
| 609 emit_opcode(cbuf, 0x68); // push 0xbadb100d | |
| 610 emit_d32(cbuf, 0xbadb100d); | |
| 611 framesize -= wordSize; | |
| 612 } | |
| 613 | |
| 614 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) { | |
| 615 if (framesize) { | |
| 616 emit_opcode(cbuf, 0x83); // sub SP,#framesize | |
| 617 emit_rm(cbuf, 0x3, 0x05, ESP_enc); | |
| 618 emit_d8(cbuf, framesize); | |
| 619 } | |
| 620 } else { | |
| 621 emit_opcode(cbuf, 0x81); // sub SP,#framesize | |
| 622 emit_rm(cbuf, 0x3, 0x05, ESP_enc); | |
| 623 emit_d32(cbuf, framesize); | |
| 624 } | |
| 1748 | 625 C->set_frame_complete(cbuf.insts_size()); |
| 0 | 626 |
| 627 #ifdef ASSERT | |
| 628 if (VerifyStackAtCalls) { | |
| 629 Label L; | |
| 630 MacroAssembler masm(&cbuf); | |
| 304 | 631 masm.push(rax); |
| 632 masm.mov(rax, rsp); | |
| 633 masm.andptr(rax, StackAlignmentInBytes-1); | |
| 634 masm.cmpptr(rax, StackAlignmentInBytes-wordSize); | |
| 635 masm.pop(rax); | |
| 0 | 636 masm.jcc(Assembler::equal, L); |
| 637 masm.stop("Stack is not properly aligned!"); | |
| 638 masm.bind(L); | |
| 639 } | |
| 640 #endif | |
| 641 | |
| 642 } | |
| 643 | |
| 644 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { | |
| 645 return MachNode::size(ra_); // too many variables; just compute it the hard way | |
| 646 } | |
| 647 | |
| 648 int MachPrologNode::reloc() const { | |
| 649 return 0; // a large enough number | |
| 650 } | |
| 651 | |
| 652 //============================================================================= | |
| 653 #ifndef PRODUCT | |
| 654 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { | |
| 655 Compile *C = ra_->C; | |
| 656 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 657 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 658 // Remove two words for return addr and rbp, | |
| 659 framesize -= 2*wordSize; | |
| 660 | |
| 661 if( C->in_24_bit_fp_mode() ) { | |
| 662 st->print("FLDCW standard control word"); | |
| 663 st->cr(); st->print("\t"); | |
| 664 } | |
| 665 if( framesize ) { | |
| 666 st->print("ADD ESP,%d\t# Destroy frame",framesize); | |
| 667 st->cr(); st->print("\t"); | |
| 668 } | |
| 669 st->print_cr("POPL EBP"); st->print("\t"); | |
| 670 if( do_polling() && C->is_method_compilation() ) { | |
| 671 st->print("TEST PollPage,EAX\t! Poll Safepoint"); | |
| 672 st->cr(); st->print("\t"); | |
| 673 } | |
| 674 } | |
| 675 #endif | |
| 676 | |
| 677 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 678 Compile *C = ra_->C; | |
| 679 | |
| 680 // If method set FPU control word, restore to standard control word | |
| 681 if( C->in_24_bit_fp_mode() ) { | |
| 682 MacroAssembler masm(&cbuf); | |
| 683 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
| 684 } | |
| 685 | |
| 686 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 687 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 688 // Remove two words for return addr and rbp, | |
| 689 framesize -= 2*wordSize; | |
| 690 | |
| 691 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here | |
| 692 | |
| 693 if( framesize >= 128 ) { | |
| 694 emit_opcode(cbuf, 0x81); // add SP, #framesize | |
| 695 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 696 emit_d32(cbuf, framesize); | |
| 697 } | |
| 698 else if( framesize ) { | |
| 699 emit_opcode(cbuf, 0x83); // add SP, #framesize | |
| 700 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 701 emit_d8(cbuf, framesize); | |
| 702 } | |
| 703 | |
| 704 emit_opcode(cbuf, 0x58 | EBP_enc); | |
| 705 | |
| 706 if( do_polling() && C->is_method_compilation() ) { | |
| 1748 | 707 cbuf.relocate(cbuf.insts_end(), relocInfo::poll_return_type, 0); |
| 0 | 708 emit_opcode(cbuf,0x85); |
| 709 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX | |
| 710 emit_d32(cbuf, (intptr_t)os::get_polling_page()); | |
| 711 } | |
| 712 } | |
| 713 | |
| 714 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { | |
| 715 Compile *C = ra_->C; | |
| 716 // If method set FPU control word, restore to standard control word | |
| 717 int size = C->in_24_bit_fp_mode() ? 6 : 0; | |
| 718 if( do_polling() && C->is_method_compilation() ) size += 6; | |
| 719 | |
| 720 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 721 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 722 // Remove two words for return addr and rbp, | |
| 723 framesize -= 2*wordSize; | |
| 724 | |
| 725 size++; // popl rbp, | |
| 726 | |
| 727 if( framesize >= 128 ) { | |
| 728 size += 6; | |
| 729 } else { | |
| 730 size += framesize ? 3 : 0; | |
| 731 } | |
| 732 return size; | |
| 733 } | |
| 734 | |
| 735 int MachEpilogNode::reloc() const { | |
| 736 return 0; // a large enough number | |
| 737 } | |
| 738 | |
| 739 const Pipeline * MachEpilogNode::pipeline() const { | |
| 740 return MachNode::pipeline_class(); | |
| 741 } | |
| 742 | |
| 743 int MachEpilogNode::safepoint_offset() const { return 0; } | |
| 744 | |
| 745 //============================================================================= | |
| 746 | |
| 747 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack }; | |
| 748 static enum RC rc_class( OptoReg::Name reg ) { | |
| 749 | |
| 750 if( !OptoReg::is_valid(reg) ) return rc_bad; | |
| 751 if (OptoReg::is_stack(reg)) return rc_stack; | |
| 752 | |
| 753 VMReg r = OptoReg::as_VMReg(reg); | |
| 754 if (r->is_Register()) return rc_int; | |
| 755 if (r->is_FloatRegister()) { | |
| 756 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode"); | |
| 757 return rc_float; | |
| 758 } | |
| 759 assert(r->is_XMMRegister(), "must be"); | |
| 760 return rc_xmm; | |
| 761 } | |
| 762 | |
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763 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg, |
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764 int opcode, const char *op_str, int size, outputStream* st ) { |
| 0 | 765 if( cbuf ) { |
| 766 emit_opcode (*cbuf, opcode ); | |
| 767 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, false); | |
| 768 #ifndef PRODUCT | |
| 769 } else if( !do_size ) { | |
|
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770 if( size != 0 ) st->print("\n\t"); |
| 0 | 771 if( opcode == 0x8B || opcode == 0x89 ) { // MOV |
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772 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset); |
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773 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]); |
| 0 | 774 } else { // FLD, FST, PUSH, POP |
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775 st->print("%s [ESP + #%d]",op_str,offset); |
| 0 | 776 } |
| 777 #endif | |
| 778 } | |
| 779 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); | |
| 780 return size+3+offset_size; | |
| 781 } | |
| 782 | |
| 783 // Helper for XMM registers. Extra opcode bits, limited syntax. | |
| 784 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load, | |
|
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785 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) { |
| 0 | 786 if( cbuf ) { |
| 787 if( reg_lo+1 == reg_hi ) { // double move? | |
| 788 if( is_load && !UseXmmLoadAndClearUpper ) | |
| 789 emit_opcode(*cbuf, 0x66 ); // use 'movlpd' for load | |
| 790 else | |
| 791 emit_opcode(*cbuf, 0xF2 ); // use 'movsd' otherwise | |
| 792 } else { | |
| 793 emit_opcode(*cbuf, 0xF3 ); | |
| 794 } | |
| 795 emit_opcode(*cbuf, 0x0F ); | |
| 796 if( reg_lo+1 == reg_hi && is_load && !UseXmmLoadAndClearUpper ) | |
| 797 emit_opcode(*cbuf, 0x12 ); // use 'movlpd' for load | |
| 798 else | |
| 799 emit_opcode(*cbuf, is_load ? 0x10 : 0x11 ); | |
| 800 encode_RegMem(*cbuf, Matcher::_regEncode[reg_lo], ESP_enc, 0x4, 0, offset, false); | |
| 801 #ifndef PRODUCT | |
| 802 } else if( !do_size ) { | |
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803 if( size != 0 ) st->print("\n\t"); |
| 0 | 804 if( reg_lo+1 == reg_hi ) { // double move? |
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805 if( is_load ) st->print("%s %s,[ESP + #%d]", |
| 0 | 806 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD", |
| 807 Matcher::regName[reg_lo], offset); | |
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808 else st->print("MOVSD [ESP + #%d],%s", |
| 0 | 809 offset, Matcher::regName[reg_lo]); |
| 810 } else { | |
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811 if( is_load ) st->print("MOVSS %s,[ESP + #%d]", |
| 0 | 812 Matcher::regName[reg_lo], offset); |
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813 else st->print("MOVSS [ESP + #%d],%s", |
| 0 | 814 offset, Matcher::regName[reg_lo]); |
| 815 } | |
| 816 #endif | |
| 817 } | |
| 818 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); | |
| 819 return size+5+offset_size; | |
| 820 } | |
| 821 | |
| 822 | |
| 823 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, | |
|
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824 int src_hi, int dst_hi, int size, outputStream* st ) { |
| 0 | 825 if( UseXmmRegToRegMoveAll ) {//Use movaps,movapd to move between xmm registers |
| 826 if( cbuf ) { | |
| 827 if( (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ) { | |
| 828 emit_opcode(*cbuf, 0x66 ); | |
| 829 } | |
| 830 emit_opcode(*cbuf, 0x0F ); | |
| 831 emit_opcode(*cbuf, 0x28 ); | |
| 832 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] ); | |
| 833 #ifndef PRODUCT | |
| 834 } else if( !do_size ) { | |
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835 if( size != 0 ) st->print("\n\t"); |
| 0 | 836 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move? |
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837 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 838 } else { |
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839 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 840 } |
| 841 #endif | |
| 842 } | |
| 843 return size + ((src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 4 : 3); | |
| 844 } else { | |
| 845 if( cbuf ) { | |
| 846 emit_opcode(*cbuf, (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 0xF2 : 0xF3 ); | |
| 847 emit_opcode(*cbuf, 0x0F ); | |
| 848 emit_opcode(*cbuf, 0x10 ); | |
| 849 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] ); | |
| 850 #ifndef PRODUCT | |
| 851 } else if( !do_size ) { | |
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852 if( size != 0 ) st->print("\n\t"); |
| 0 | 853 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move? |
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854 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 855 } else { |
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856 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 857 } |
| 858 #endif | |
| 859 } | |
| 860 return size+4; | |
| 861 } | |
| 862 } | |
| 863 | |
|
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864 static int impl_movgpr2x_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, |
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865 int src_hi, int dst_hi, int size, outputStream* st ) { |
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866 // 32-bit |
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867 if (cbuf) { |
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868 emit_opcode(*cbuf, 0x66); |
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869 emit_opcode(*cbuf, 0x0F); |
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870 emit_opcode(*cbuf, 0x6E); |
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871 emit_rm(*cbuf, 0x3, Matcher::_regEncode[dst_lo] & 7, Matcher::_regEncode[src_lo] & 7); |
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872 #ifndef PRODUCT |
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873 } else if (!do_size) { |
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874 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]); |
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875 #endif |
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876 } |
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877 return 4; |
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878 } |
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879 |
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880 |
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881 static int impl_movx2gpr_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, |
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882 int src_hi, int dst_hi, int size, outputStream* st ) { |
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883 // 32-bit |
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884 if (cbuf) { |
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885 emit_opcode(*cbuf, 0x66); |
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886 emit_opcode(*cbuf, 0x0F); |
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887 emit_opcode(*cbuf, 0x7E); |
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888 emit_rm(*cbuf, 0x3, Matcher::_regEncode[src_lo] & 7, Matcher::_regEncode[dst_lo] & 7); |
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889 #ifndef PRODUCT |
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890 } else if (!do_size) { |
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891 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]); |
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892 #endif |
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893 } |
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894 return 4; |
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895 } |
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896 |
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897 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) { |
| 0 | 898 if( cbuf ) { |
| 899 emit_opcode(*cbuf, 0x8B ); | |
| 900 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] ); | |
| 901 #ifndef PRODUCT | |
| 902 } else if( !do_size ) { | |
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903 if( size != 0 ) st->print("\n\t"); |
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904 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]); |
| 0 | 905 #endif |
| 906 } | |
| 907 return size+2; | |
| 908 } | |
| 909 | |
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910 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi, |
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911 int offset, int size, outputStream* st ) { |
| 0 | 912 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there |
| 913 if( cbuf ) { | |
| 914 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it) | |
| 915 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] ); | |
| 916 #ifndef PRODUCT | |
| 917 } else if( !do_size ) { | |
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918 if( size != 0 ) st->print("\n\t"); |
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919 st->print("FLD %s",Matcher::regName[src_lo]); |
| 0 | 920 #endif |
| 921 } | |
| 922 size += 2; | |
| 923 } | |
| 924 | |
| 925 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/; | |
| 926 const char *op_str; | |
| 927 int op; | |
| 928 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store? | |
| 929 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D "; | |
| 930 op = 0xDD; | |
| 931 } else { // 32-bit store | |
| 932 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S "; | |
| 933 op = 0xD9; | |
| 934 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" ); | |
| 935 } | |
| 936 | |
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937 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st); |
| 0 | 938 } |
| 939 | |
| 940 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const { | |
| 941 // Get registers to move | |
| 942 OptoReg::Name src_second = ra_->get_reg_second(in(1)); | |
| 943 OptoReg::Name src_first = ra_->get_reg_first(in(1)); | |
| 944 OptoReg::Name dst_second = ra_->get_reg_second(this ); | |
| 945 OptoReg::Name dst_first = ra_->get_reg_first(this ); | |
| 946 | |
| 947 enum RC src_second_rc = rc_class(src_second); | |
| 948 enum RC src_first_rc = rc_class(src_first); | |
| 949 enum RC dst_second_rc = rc_class(dst_second); | |
| 950 enum RC dst_first_rc = rc_class(dst_first); | |
| 951 | |
| 952 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); | |
| 953 | |
| 954 // Generate spill code! | |
| 955 int size = 0; | |
| 956 | |
| 957 if( src_first == dst_first && src_second == dst_second ) | |
| 958 return size; // Self copy, no move | |
| 959 | |
| 960 // -------------------------------------- | |
| 961 // Check for mem-mem move. push/pop to move. | |
| 962 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { | |
| 963 if( src_second == dst_first ) { // overlapping stack copy ranges | |
| 964 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" ); | |
|
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965 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st); |
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966 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st); |
| 0 | 967 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits |
| 968 } | |
| 969 // move low bits | |
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970 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st); |
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971 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st); |
| 0 | 972 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits |
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973 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st); |
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974 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st); |
| 0 | 975 } |
| 976 return size; | |
| 977 } | |
| 978 | |
| 979 // -------------------------------------- | |
| 980 // Check for integer reg-reg copy | |
| 981 if( src_first_rc == rc_int && dst_first_rc == rc_int ) | |
|
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982 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st); |
| 0 | 983 |
| 984 // Check for integer store | |
| 985 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) | |
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986 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st); |
| 0 | 987 |
| 988 // Check for integer load | |
| 989 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) | |
|
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990 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st); |
| 0 | 991 |
|
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992 // Check for integer reg-xmm reg copy |
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993 if( src_first_rc == rc_int && dst_first_rc == rc_xmm ) { |
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994 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad), |
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995 "no 64 bit integer-float reg moves" ); |
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996 return impl_movgpr2x_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st); |
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997 } |
| 0 | 998 // -------------------------------------- |
| 999 // Check for float reg-reg copy | |
| 1000 if( src_first_rc == rc_float && dst_first_rc == rc_float ) { | |
| 1001 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) || | |
| 1002 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" ); | |
| 1003 if( cbuf ) { | |
| 1004 | |
| 1005 // Note the mucking with the register encode to compensate for the 0/1 | |
| 1006 // indexing issue mentioned in a comment in the reg_def sections | |
| 1007 // for FPR registers many lines above here. | |
| 1008 | |
| 1009 if( src_first != FPR1L_num ) { | |
| 1010 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i) | |
| 1011 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 ); | |
| 1012 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i) | |
| 1013 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] ); | |
| 1014 } else { | |
| 1015 emit_opcode (*cbuf, 0xDD ); // FST ST(i) | |
| 1016 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 ); | |
| 1017 } | |
| 1018 #ifndef PRODUCT | |
| 1019 } else if( !do_size ) { | |
| 1020 if( size != 0 ) st->print("\n\t"); | |
| 1021 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]); | |
| 1022 else st->print( "FST %s", Matcher::regName[dst_first]); | |
| 1023 #endif | |
| 1024 } | |
| 1025 return size + ((src_first != FPR1L_num) ? 2+2 : 2); | |
| 1026 } | |
| 1027 | |
| 1028 // Check for float store | |
| 1029 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { | |
|
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1030 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st); |
| 0 | 1031 } |
| 1032 | |
| 1033 // Check for float load | |
| 1034 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { | |
| 1035 int offset = ra_->reg2offset(src_first); | |
| 1036 const char *op_str; | |
| 1037 int op; | |
| 1038 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load? | |
| 1039 op_str = "FLD_D"; | |
| 1040 op = 0xDD; | |
| 1041 } else { // 32-bit load | |
| 1042 op_str = "FLD_S"; | |
| 1043 op = 0xD9; | |
| 1044 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" ); | |
| 1045 } | |
| 1046 if( cbuf ) { | |
| 1047 emit_opcode (*cbuf, op ); | |
| 1048 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, false); | |
| 1049 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i) | |
| 1050 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] ); | |
| 1051 #ifndef PRODUCT | |
| 1052 } else if( !do_size ) { | |
| 1053 if( size != 0 ) st->print("\n\t"); | |
| 1054 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]); | |
| 1055 #endif | |
| 1056 } | |
| 1057 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); | |
| 1058 return size + 3+offset_size+2; | |
| 1059 } | |
| 1060 | |
| 1061 // Check for xmm reg-reg copy | |
| 1062 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) { | |
| 1063 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) || | |
| 1064 (src_first+1 == src_second && dst_first+1 == dst_second), | |
| 1065 "no non-adjacent float-moves" ); | |
|
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1066 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st); |
| 0 | 1067 } |
| 1068 | |
|
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1069 // Check for xmm reg-integer reg copy |
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1070 if( src_first_rc == rc_xmm && dst_first_rc == rc_int ) { |
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1071 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad), |
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1072 "no 64 bit float-integer reg moves" ); |
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1073 return impl_movx2gpr_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st); |
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1074 } |
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1075 |
| 0 | 1076 // Check for xmm store |
| 1077 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) { | |
|
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1078 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st); |
| 0 | 1079 } |
| 1080 | |
| 1081 // Check for float xmm load | |
| 1082 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) { | |
|
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1083 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st); |
| 0 | 1084 } |
| 1085 | |
| 1086 // Copy from float reg to xmm reg | |
| 1087 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) { | |
| 1088 // copy to the top of stack from floating point reg | |
| 1089 // and use LEA to preserve flags | |
| 1090 if( cbuf ) { | |
| 1091 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8] | |
| 1092 emit_rm(*cbuf, 0x1, ESP_enc, 0x04); | |
| 1093 emit_rm(*cbuf, 0x0, 0x04, ESP_enc); | |
| 1094 emit_d8(*cbuf,0xF8); | |
| 1095 #ifndef PRODUCT | |
| 1096 } else if( !do_size ) { | |
| 1097 if( size != 0 ) st->print("\n\t"); | |
| 1098 st->print("LEA ESP,[ESP-8]"); | |
| 1099 #endif | |
| 1100 } | |
| 1101 size += 4; | |
| 1102 | |
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1103 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st); |
| 0 | 1104 |
| 1105 // Copy from the temp memory to the xmm reg. | |
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1106 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st); |
| 0 | 1107 |
| 1108 if( cbuf ) { | |
| 1109 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8] | |
| 1110 emit_rm(*cbuf, 0x1, ESP_enc, 0x04); | |
| 1111 emit_rm(*cbuf, 0x0, 0x04, ESP_enc); | |
| 1112 emit_d8(*cbuf,0x08); | |
| 1113 #ifndef PRODUCT | |
| 1114 } else if( !do_size ) { | |
| 1115 if( size != 0 ) st->print("\n\t"); | |
| 1116 st->print("LEA ESP,[ESP+8]"); | |
| 1117 #endif | |
| 1118 } | |
| 1119 size += 4; | |
| 1120 return size; | |
| 1121 } | |
| 1122 | |
| 1123 assert( size > 0, "missed a case" ); | |
| 1124 | |
| 1125 // -------------------------------------------------------------------- | |
| 1126 // Check for second bits still needing moving. | |
| 1127 if( src_second == dst_second ) | |
| 1128 return size; // Self copy; no move | |
| 1129 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); | |
| 1130 | |
| 1131 // Check for second word int-int move | |
| 1132 if( src_second_rc == rc_int && dst_second_rc == rc_int ) | |
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1133 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st); |
| 0 | 1134 |
| 1135 // Check for second word integer store | |
| 1136 if( src_second_rc == rc_int && dst_second_rc == rc_stack ) | |
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1137 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st); |
| 0 | 1138 |
| 1139 // Check for second word integer load | |
| 1140 if( dst_second_rc == rc_int && src_second_rc == rc_stack ) | |
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1141 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st); |
| 0 | 1142 |
| 1143 | |
| 1144 Unimplemented(); | |
| 1145 } | |
| 1146 | |
| 1147 #ifndef PRODUCT | |
| 1148 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { | |
| 1149 implementation( NULL, ra_, false, st ); | |
| 1150 } | |
| 1151 #endif | |
| 1152 | |
| 1153 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1154 implementation( &cbuf, ra_, false, NULL ); | |
| 1155 } | |
| 1156 | |
| 1157 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { | |
| 1158 return implementation( NULL, ra_, true, NULL ); | |
| 1159 } | |
| 1160 | |
| 1161 //============================================================================= | |
| 1162 #ifndef PRODUCT | |
| 1163 void MachNopNode::format( PhaseRegAlloc *, outputStream* st ) const { | |
| 1164 st->print("NOP \t# %d bytes pad for loops and calls", _count); | |
| 1165 } | |
| 1166 #endif | |
| 1167 | |
| 1168 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const { | |
| 1169 MacroAssembler _masm(&cbuf); | |
| 1170 __ nop(_count); | |
| 1171 } | |
| 1172 | |
| 1173 uint MachNopNode::size(PhaseRegAlloc *) const { | |
| 1174 return _count; | |
| 1175 } | |
| 1176 | |
| 1177 | |
| 1178 //============================================================================= | |
| 1179 #ifndef PRODUCT | |
| 1180 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { | |
| 1181 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1182 int reg = ra_->get_reg_first(this); | |
| 1183 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset); | |
| 1184 } | |
| 1185 #endif | |
| 1186 | |
| 1187 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1188 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1189 int reg = ra_->get_encode(this); | |
| 1190 if( offset >= 128 ) { | |
| 1191 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1192 emit_rm(cbuf, 0x2, reg, 0x04); | |
| 1193 emit_rm(cbuf, 0x0, 0x04, ESP_enc); | |
| 1194 emit_d32(cbuf, offset); | |
| 1195 } | |
| 1196 else { | |
| 1197 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1198 emit_rm(cbuf, 0x1, reg, 0x04); | |
| 1199 emit_rm(cbuf, 0x0, 0x04, ESP_enc); | |
| 1200 emit_d8(cbuf, offset); | |
| 1201 } | |
| 1202 } | |
| 1203 | |
| 1204 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { | |
| 1205 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1206 if( offset >= 128 ) { | |
| 1207 return 7; | |
| 1208 } | |
| 1209 else { | |
| 1210 return 4; | |
| 1211 } | |
| 1212 } | |
| 1213 | |
| 1214 //============================================================================= | |
| 1215 | |
| 1216 // emit call stub, compiled java to interpreter | |
| 1217 void emit_java_to_interp(CodeBuffer &cbuf ) { | |
| 1218 // Stub is fixed up when the corresponding call is converted from calling | |
| 1219 // compiled code to calling interpreted code. | |
| 1220 // mov rbx,0 | |
| 1221 // jmp -1 | |
| 1222 | |
| 1748 | 1223 address mark = cbuf.insts_mark(); // get mark within main instrs section |
| 1224 | |
| 1225 // Note that the code buffer's insts_mark is always relative to insts. | |
| 0 | 1226 // That's why we must use the macroassembler to generate a stub. |
| 1227 MacroAssembler _masm(&cbuf); | |
| 1228 | |
| 1229 address base = | |
| 1230 __ start_a_stub(Compile::MAX_stubs_size); | |
| 1231 if (base == NULL) return; // CodeBuffer::expand failed | |
| 1232 // static stub relocation stores the instruction address of the call | |
| 1233 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM32); | |
| 1234 // static stub relocation also tags the methodOop in the code-stream. | |
| 1235 __ movoop(rbx, (jobject)NULL); // method is zapped till fixup time | |
| 304 | 1236 // This is recognized as unresolved by relocs/nativeInst/ic code |
| 1237 __ jump(RuntimeAddress(__ pc())); | |
| 0 | 1238 |
| 1239 __ end_a_stub(); | |
| 1748 | 1240 // Update current stubs pointer and restore insts_end. |
| 0 | 1241 } |
| 1242 // size of call stub, compiled java to interpretor | |
| 1243 uint size_java_to_interp() { | |
| 1244 return 10; // movl; jmp | |
| 1245 } | |
| 1246 // relocation entries for call stub, compiled java to interpretor | |
| 1247 uint reloc_java_to_interp() { | |
| 1248 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call | |
| 1249 } | |
| 1250 | |
| 1251 //============================================================================= | |
| 1252 #ifndef PRODUCT | |
| 1253 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { | |
| 1254 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check"); | |
| 1255 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub"); | |
| 1256 st->print_cr("\tNOP"); | |
| 1257 st->print_cr("\tNOP"); | |
| 1258 if( !OptoBreakpoint ) | |
| 1259 st->print_cr("\tNOP"); | |
| 1260 } | |
| 1261 #endif | |
| 1262 | |
| 1263 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1264 MacroAssembler masm(&cbuf); | |
| 1265 #ifdef ASSERT | |
| 1748 | 1266 uint insts_size = cbuf.insts_size(); |
| 0 | 1267 #endif |
| 304 | 1268 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes())); |
| 0 | 1269 masm.jump_cc(Assembler::notEqual, |
| 1270 RuntimeAddress(SharedRuntime::get_ic_miss_stub())); | |
| 1271 /* WARNING these NOPs are critical so that verified entry point is properly | |
| 1272 aligned for patching by NativeJump::patch_verified_entry() */ | |
| 1273 int nops_cnt = 2; | |
| 1274 if( !OptoBreakpoint ) // Leave space for int3 | |
| 1275 nops_cnt += 1; | |
| 1276 masm.nop(nops_cnt); | |
| 1277 | |
| 1748 | 1278 assert(cbuf.insts_size() - insts_size == size(ra_), "checking code size of inline cache node"); |
| 0 | 1279 } |
| 1280 | |
| 1281 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { | |
| 1282 return OptoBreakpoint ? 11 : 12; | |
| 1283 } | |
| 1284 | |
| 1285 | |
| 1286 //============================================================================= | |
| 1287 uint size_exception_handler() { | |
| 1288 // NativeCall instruction size is the same as NativeJump. | |
| 1289 // exception handler starts out as jump and can be patched to | |
| 1290 // a call be deoptimization. (4932387) | |
| 1291 // Note that this value is also credited (in output.cpp) to | |
| 1292 // the size of the code section. | |
| 1293 return NativeJump::instruction_size; | |
| 1294 } | |
| 1295 | |
| 1296 // Emit exception handler code. Stuff framesize into a register | |
| 1297 // and call a VM stub routine. | |
| 1298 int emit_exception_handler(CodeBuffer& cbuf) { | |
| 1299 | |
| 1748 | 1300 // Note that the code buffer's insts_mark is always relative to insts. |
| 0 | 1301 // That's why we must use the macroassembler to generate a handler. |
| 1302 MacroAssembler _masm(&cbuf); | |
| 1303 address base = | |
| 1304 __ start_a_stub(size_exception_handler()); | |
| 1305 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1306 int offset = __ offset(); | |
| 1748 | 1307 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point())); |
| 0 | 1308 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); |
| 1309 __ end_a_stub(); | |
| 1310 return offset; | |
| 1311 } | |
| 1312 | |
| 1313 uint size_deopt_handler() { | |
| 1314 // NativeCall instruction size is the same as NativeJump. | |
| 1315 // exception handler starts out as jump and can be patched to | |
| 1316 // a call be deoptimization. (4932387) | |
| 1317 // Note that this value is also credited (in output.cpp) to | |
| 1318 // the size of the code section. | |
| 1319 return 5 + NativeJump::instruction_size; // pushl(); jmp; | |
| 1320 } | |
| 1321 | |
| 1322 // Emit deopt handler code. | |
| 1323 int emit_deopt_handler(CodeBuffer& cbuf) { | |
| 1324 | |
| 1748 | 1325 // Note that the code buffer's insts_mark is always relative to insts. |
| 0 | 1326 // That's why we must use the macroassembler to generate a handler. |
| 1327 MacroAssembler _masm(&cbuf); | |
| 1328 address base = | |
| 1329 __ start_a_stub(size_exception_handler()); | |
| 1330 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1331 int offset = __ offset(); | |
| 1332 InternalAddress here(__ pc()); | |
| 1333 __ pushptr(here.addr()); | |
| 1334 | |
| 1335 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); | |
| 1336 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); | |
| 1337 __ end_a_stub(); | |
| 1338 return offset; | |
| 1339 } | |
| 1340 | |
| 1341 | |
|
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1342 const bool Matcher::match_rule_supported(int opcode) { |
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1343 if (!has_match_rule(opcode)) |
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1344 return false; |
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1345 |
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1346 return true; // Per default match rules are supported. |
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1347 } |
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1348 |
| 0 | 1349 int Matcher::regnum_to_fpu_offset(int regnum) { |
| 1350 return regnum - 32; // The FP registers are in the second chunk | |
| 1351 } | |
| 1352 | |
| 1353 // This is UltraSparc specific, true just means we have fast l2f conversion | |
| 1354 const bool Matcher::convL2FSupported(void) { | |
| 1355 return true; | |
| 1356 } | |
| 1357 | |
| 1358 // Vector width in bytes | |
| 1359 const uint Matcher::vector_width_in_bytes(void) { | |
| 1360 return UseSSE >= 2 ? 8 : 0; | |
| 1361 } | |
| 1362 | |
| 1363 // Vector ideal reg | |
| 1364 const uint Matcher::vector_ideal_reg(void) { | |
| 1365 return Op_RegD; | |
| 1366 } | |
| 1367 | |
| 1368 // Is this branch offset short enough that a short branch can be used? | |
| 1369 // | |
| 1370 // NOTE: If the platform does not provide any short branch variants, then | |
| 1371 // this method should return false for offset 0. | |
|
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1372 bool Matcher::is_short_branch_offset(int rule, int offset) { |
|
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1373 // the short version of jmpConUCF2 contains multiple branches, |
|
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1374 // making the reach slightly less |
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1375 if (rule == jmpConUCF2_rule) |
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1376 return (-126 <= offset && offset <= 125); |
| 0 | 1377 return (-128 <= offset && offset <= 127); |
| 1378 } | |
| 1379 | |
| 1380 const bool Matcher::isSimpleConstant64(jlong value) { | |
| 1381 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. | |
| 1382 return false; | |
| 1383 } | |
| 1384 | |
| 1385 // The ecx parameter to rep stos for the ClearArray node is in dwords. | |
| 1386 const bool Matcher::init_array_count_is_in_bytes = false; | |
| 1387 | |
| 1388 // Threshold size for cleararray. | |
| 1389 const int Matcher::init_array_short_size = 8 * BytesPerLong; | |
| 1390 | |
| 1391 // Should the Matcher clone shifts on addressing modes, expecting them to | |
| 1392 // be subsumed into complex addressing expressions or compute them into | |
| 1393 // registers? True for Intel but false for most RISCs | |
| 1394 const bool Matcher::clone_shift_expressions = true; | |
| 1395 | |
|
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|
1396 bool Matcher::narrow_oop_use_complex_address() { |
|
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|
1397 ShouldNotCallThis(); |
|
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|
1398 return true; |
|
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|
1399 } |
|
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|
1400 |
|
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|
1401 |
| 0 | 1402 // Is it better to copy float constants, or load them directly from memory? |
| 1403 // Intel can load a float constant from a direct address, requiring no | |
| 1404 // extra registers. Most RISCs will have to materialize an address into a | |
| 1405 // register first, so they would do better to copy the constant from stack. | |
| 1406 const bool Matcher::rematerialize_float_constants = true; | |
| 1407 | |
| 1408 // If CPU can load and store mis-aligned doubles directly then no fixup is | |
| 1409 // needed. Else we split the double into 2 integer pieces and move it | |
| 1410 // piece-by-piece. Only happens when passing doubles into C code as the | |
| 1411 // Java calling convention forces doubles to be aligned. | |
| 1412 const bool Matcher::misaligned_doubles_ok = true; | |
| 1413 | |
| 1414 | |
| 1415 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { | |
| 1416 // Get the memory operand from the node | |
| 1417 uint numopnds = node->num_opnds(); // Virtual call for number of operands | |
| 1418 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far | |
| 1419 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" ); | |
| 1420 uint opcnt = 1; // First operand | |
| 1421 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand | |
| 1422 while( idx >= skipped+num_edges ) { | |
| 1423 skipped += num_edges; | |
| 1424 opcnt++; // Bump operand count | |
| 1425 assert( opcnt < numopnds, "Accessing non-existent operand" ); | |
| 1426 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand | |
| 1427 } | |
| 1428 | |
| 1429 MachOper *memory = node->_opnds[opcnt]; | |
| 1430 MachOper *new_memory = NULL; | |
| 1431 switch (memory->opcode()) { | |
| 1432 case DIRECT: | |
| 1433 case INDOFFSET32X: | |
| 1434 // No transformation necessary. | |
| 1435 return; | |
| 1436 case INDIRECT: | |
| 1437 new_memory = new (C) indirect_win95_safeOper( ); | |
| 1438 break; | |
| 1439 case INDOFFSET8: | |
| 1440 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0)); | |
| 1441 break; | |
| 1442 case INDOFFSET32: | |
| 1443 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0)); | |
| 1444 break; | |
| 1445 case INDINDEXOFFSET: | |
| 1446 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0)); | |
| 1447 break; | |
| 1448 case INDINDEXSCALE: | |
| 1449 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale()); | |
| 1450 break; | |
| 1451 case INDINDEXSCALEOFFSET: | |
| 1452 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0)); | |
| 1453 break; | |
| 1454 case LOAD_LONG_INDIRECT: | |
| 1455 case LOAD_LONG_INDOFFSET32: | |
| 1456 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI} | |
| 1457 return; | |
| 1458 default: | |
| 1459 assert(false, "unexpected memory operand in pd_implicit_null_fixup()"); | |
| 1460 return; | |
| 1461 } | |
| 1462 node->_opnds[opcnt] = new_memory; | |
| 1463 } | |
| 1464 | |
| 1465 // Advertise here if the CPU requires explicit rounding operations | |
| 1466 // to implement the UseStrictFP mode. | |
| 1467 const bool Matcher::strict_fp_requires_explicit_rounding = true; | |
| 1468 | |
|
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1469 // Are floats conerted to double when stored to stack during deoptimization? |
|
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1470 // On x32 it is stored with convertion only when FPU is used for floats. |
|
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1471 bool Matcher::float_in_double() { return (UseSSE == 0); } |
|
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|
1472 |
| 0 | 1473 // Do ints take an entire long register or just half? |
| 1474 const bool Matcher::int_in_long = false; | |
| 1475 | |
| 1476 // Return whether or not this register is ever used as an argument. This | |
| 1477 // function is used on startup to build the trampoline stubs in generateOptoStub. | |
| 1478 // Registers not mentioned will be killed by the VM call in the trampoline, and | |
| 1479 // arguments in those registers not be available to the callee. | |
| 1480 bool Matcher::can_be_java_arg( int reg ) { | |
| 1481 if( reg == ECX_num || reg == EDX_num ) return true; | |
| 1482 if( (reg == XMM0a_num || reg == XMM1a_num) && UseSSE>=1 ) return true; | |
| 1483 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true; | |
| 1484 return false; | |
| 1485 } | |
| 1486 | |
| 1487 bool Matcher::is_spillable_arg( int reg ) { | |
| 1488 return can_be_java_arg(reg); | |
| 1489 } | |
| 1490 | |
|
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|
1491 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) { |
|
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|
1492 // Use hardware integer DIV instruction when |
|
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|
1493 // it is faster than a code which use multiply. |
|
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|
1494 // Only when constant divisor fits into 32 bit |
|
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|
1495 // (min_jint is excluded to get only correct |
|
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|
1496 // positive 32 bit values from negative). |
|
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|
1497 return VM_Version::has_fast_idiv() && |
|
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|
1498 (divisor == (int)divisor && divisor != min_jint); |
|
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|
1499 } |
|
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|
1500 |
| 0 | 1501 // Register for DIVI projection of divmodI |
| 1502 RegMask Matcher::divI_proj_mask() { | |
| 1503 return EAX_REG_mask; | |
| 1504 } | |
| 1505 | |
| 1506 // Register for MODI projection of divmodI | |
| 1507 RegMask Matcher::modI_proj_mask() { | |
| 1508 return EDX_REG_mask; | |
| 1509 } | |
| 1510 | |
| 1511 // Register for DIVL projection of divmodL | |
| 1512 RegMask Matcher::divL_proj_mask() { | |
| 1513 ShouldNotReachHere(); | |
| 1514 return RegMask(); | |
| 1515 } | |
| 1516 | |
| 1517 // Register for MODL projection of divmodL | |
| 1518 RegMask Matcher::modL_proj_mask() { | |
| 1519 ShouldNotReachHere(); | |
| 1520 return RegMask(); | |
| 1521 } | |
| 1522 | |
|
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|
1523 const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
|
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1524 return EBP_REG_mask; |
|
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|
1525 } |
|
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|
1526 |
|
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|
1527 // Returns true if the high 32 bits of the value is known to be zero. |
|
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|
1528 bool is_operand_hi32_zero(Node* n) { |
|
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|
1529 int opc = n->Opcode(); |
|
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|
1530 if (opc == Op_LoadUI2L) { |
|
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|
1531 return true; |
|
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|
1532 } |
|
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|
1533 if (opc == Op_AndL) { |
|
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|
1534 Node* o2 = n->in(2); |
|
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|
1535 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) { |
|
e8443c7be117
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|
1536 return true; |
|
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|
1537 } |
|
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|
1538 } |
|
1914
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|
1539 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) { |
|
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|
1540 return true; |
|
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|
1541 } |
|
1209
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|
1542 return false; |
|
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|
1543 } |
|
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|
1544 |
| 0 | 1545 %} |
| 1546 | |
| 1547 //----------ENCODING BLOCK----------------------------------------------------- | |
| 1548 // This block specifies the encoding classes used by the compiler to output | |
| 1549 // byte streams. Encoding classes generate functions which are called by | |
| 1550 // Machine Instruction Nodes in order to generate the bit encoding of the | |
| 1551 // instruction. Operands specify their base encoding interface with the | |
| 1552 // interface keyword. There are currently supported four interfaces, | |
| 1553 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an | |
| 1554 // operand to generate a function which returns its register number when | |
| 1555 // queried. CONST_INTER causes an operand to generate a function which | |
| 1556 // returns the value of the constant when queried. MEMORY_INTER causes an | |
| 1557 // operand to generate four functions which return the Base Register, the | |
| 1558 // Index Register, the Scale Value, and the Offset Value of the operand when | |
| 1559 // queried. COND_INTER causes an operand to generate six functions which | |
| 1560 // return the encoding code (ie - encoding bits for the instruction) | |
| 1561 // associated with each basic boolean condition for a conditional instruction. | |
| 1562 // Instructions specify two basic values for encoding. They use the | |
| 1563 // ins_encode keyword to specify their encoding class (which must be one of | |
| 1564 // the class names specified in the encoding block), and they use the | |
| 1565 // opcode keyword to specify, in order, their primary, secondary, and | |
| 1566 // tertiary opcode. Only the opcode sections which a particular instruction | |
| 1567 // needs for encoding need to be specified. | |
| 1568 encode %{ | |
| 1569 // Build emit functions for each basic byte or larger field in the intel | |
| 1570 // encoding scheme (opcode, rm, sib, immediate), and call them from C++ | |
| 1571 // code in the enc_class source block. Emit functions will live in the | |
| 1572 // main source block for now. In future, we can generalize this by | |
| 1573 // adding a syntax that specifies the sizes of fields in an order, | |
| 1574 // so that the adlc can build the emit functions automagically | |
|
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|
1575 |
|
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|
1576 // Emit primary opcode |
|
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|
1577 enc_class OpcP %{ |
|
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|
1578 emit_opcode(cbuf, $primary); |
|
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|
1579 %} |
|
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|
1580 |
|
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|
1581 // Emit secondary opcode |
|
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|
1582 enc_class OpcS %{ |
|
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|
1583 emit_opcode(cbuf, $secondary); |
|
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|
1584 %} |
|
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|
1585 |
|
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|
1586 // Emit opcode directly |
|
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|
1587 enc_class Opcode(immI d8) %{ |
|
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|
1588 emit_opcode(cbuf, $d8$$constant); |
| 0 | 1589 %} |
| 1590 | |
| 1591 enc_class SizePrefix %{ | |
| 1592 emit_opcode(cbuf,0x66); | |
| 1593 %} | |
| 1594 | |
| 1595 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many) | |
| 1596 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 1597 %} | |
| 1598 | |
| 1599 enc_class OpcRegReg (immI opcode, eRegI dst, eRegI src) %{ // OpcRegReg(Many) | |
| 1600 emit_opcode(cbuf,$opcode$$constant); | |
| 1601 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 1602 %} | |
| 1603 | |
| 1604 enc_class mov_r32_imm0( eRegI dst ) %{ | |
| 1605 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32 | |
| 1606 emit_d32 ( cbuf, 0x0 ); // imm32==0x0 | |
| 1607 %} | |
| 1608 | |
| 1609 enc_class cdq_enc %{ | |
| 1610 // Full implementation of Java idiv and irem; checks for | |
| 1611 // special case as described in JVM spec., p.243 & p.271. | |
| 1612 // | |
| 1613 // normal case special case | |
| 1614 // | |
| 1615 // input : rax,: dividend min_int | |
| 1616 // reg: divisor -1 | |
| 1617 // | |
| 1618 // output: rax,: quotient (= rax, idiv reg) min_int | |
| 1619 // rdx: remainder (= rax, irem reg) 0 | |
| 1620 // | |
| 1621 // Code sequnce: | |
| 1622 // | |
| 1623 // 81 F8 00 00 00 80 cmp rax,80000000h | |
| 1624 // 0F 85 0B 00 00 00 jne normal_case | |
| 1625 // 33 D2 xor rdx,edx | |
| 1626 // 83 F9 FF cmp rcx,0FFh | |
| 1627 // 0F 84 03 00 00 00 je done | |
| 1628 // normal_case: | |
| 1629 // 99 cdq | |
| 1630 // F7 F9 idiv rax,ecx | |
| 1631 // done: | |
| 1632 // | |
| 1633 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8); | |
| 1634 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); | |
| 1635 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h | |
| 1636 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85); | |
| 1637 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00); | |
| 1638 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case | |
| 1639 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx | |
| 1640 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh | |
| 1641 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84); | |
| 1642 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00); | |
| 1643 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done | |
| 1644 // normal_case: | |
| 1645 emit_opcode(cbuf,0x99); // cdq | |
| 1646 // idiv (note: must be emitted by the user of this rule) | |
| 1647 // normal: | |
| 1648 %} | |
| 1649 | |
| 1650 // Dense encoding for older common ops | |
| 1651 enc_class Opc_plus(immI opcode, eRegI reg) %{ | |
| 1652 emit_opcode(cbuf, $opcode$$constant + $reg$$reg); | |
| 1653 %} | |
| 1654 | |
| 1655 | |
| 1656 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension | |
| 1657 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit | |
| 1658 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1659 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { | |
| 1660 emit_opcode(cbuf, $primary | 0x02); | |
| 1661 } | |
| 1662 else { // If 32-bit immediate | |
| 1663 emit_opcode(cbuf, $primary); | |
| 1664 } | |
| 1665 %} | |
| 1666 | |
| 1667 enc_class OpcSErm (eRegI dst, immI imm) %{ // OpcSEr/m | |
| 1668 // Emit primary opcode and set sign-extend bit | |
| 1669 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1670 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { | |
| 1671 emit_opcode(cbuf, $primary | 0x02); } | |
| 1672 else { // If 32-bit immediate | |
| 1673 emit_opcode(cbuf, $primary); | |
| 1674 } | |
| 1675 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 1676 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); | |
| 1677 %} | |
| 1678 | |
| 1679 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits | |
| 1680 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1681 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { | |
| 1682 $$$emit8$imm$$constant; | |
| 1683 } | |
| 1684 else { // If 32-bit immediate | |
| 1685 // Output immediate | |
| 1686 $$$emit32$imm$$constant; | |
| 1687 } | |
| 1688 %} | |
| 1689 | |
| 1690 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{ | |
| 1691 // Emit primary opcode and set sign-extend bit | |
| 1692 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1693 int con = (int)$imm$$constant; // Throw away top bits | |
| 1694 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary); | |
| 1695 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 1696 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); | |
| 1697 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con); | |
| 1698 else emit_d32(cbuf,con); | |
| 1699 %} | |
| 1700 | |
| 1701 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{ | |
| 1702 // Emit primary opcode and set sign-extend bit | |
| 1703 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1704 int con = (int)($imm$$constant >> 32); // Throw away bottom bits | |
| 1705 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary); | |
| 1706 // Emit r/m byte with tertiary opcode, after primary opcode. | |
| 1707 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg)); | |
| 1708 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con); | |
| 1709 else emit_d32(cbuf,con); | |
| 1710 %} | |
| 1711 | |
| 1712 enc_class Lbl (label labl) %{ // JMP, CALL | |
| 1713 Label *l = $labl$$label; | |
| 1748 | 1714 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.insts_size()+4)) : 0); |
| 0 | 1715 %} |
| 1716 | |
| 1717 enc_class LblShort (label labl) %{ // JMP, CALL | |
| 1718 Label *l = $labl$$label; | |
| 1748 | 1719 int disp = l ? (l->loc_pos() - (cbuf.insts_size()+1)) : 0; |
| 0 | 1720 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp"); |
| 1721 emit_d8(cbuf, disp); | |
| 1722 %} | |
| 1723 | |
| 1724 enc_class OpcSReg (eRegI dst) %{ // BSWAP | |
| 1725 emit_cc(cbuf, $secondary, $dst$$reg ); | |
| 1726 %} | |
| 1727 | |
| 1728 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP | |
| 1729 int destlo = $dst$$reg; | |
| 1730 int desthi = HIGH_FROM_LOW(destlo); | |
| 1731 // bswap lo | |
| 1732 emit_opcode(cbuf, 0x0F); | |
| 1733 emit_cc(cbuf, 0xC8, destlo); | |
| 1734 // bswap hi | |
| 1735 emit_opcode(cbuf, 0x0F); | |
| 1736 emit_cc(cbuf, 0xC8, desthi); | |
| 1737 // xchg lo and hi | |
| 1738 emit_opcode(cbuf, 0x87); | |
| 1739 emit_rm(cbuf, 0x3, destlo, desthi); | |
| 1740 %} | |
| 1741 | |
| 1742 enc_class RegOpc (eRegI div) %{ // IDIV, IMOD, JMP indirect, ... | |
| 1743 emit_rm(cbuf, 0x3, $secondary, $div$$reg ); | |
| 1744 %} | |
| 1745 | |
| 1746 enc_class Jcc (cmpOp cop, label labl) %{ // JCC | |
| 1747 Label *l = $labl$$label; | |
| 1748 $$$emit8$primary; | |
| 1749 emit_cc(cbuf, $secondary, $cop$$cmpcode); | |
| 1748 | 1750 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.insts_size()+4)) : 0); |
| 0 | 1751 %} |
| 1752 | |
| 1753 enc_class JccShort (cmpOp cop, label labl) %{ // JCC | |
| 1754 Label *l = $labl$$label; | |
| 1755 emit_cc(cbuf, $primary, $cop$$cmpcode); | |
| 1748 | 1756 int disp = l ? (l->loc_pos() - (cbuf.insts_size()+1)) : 0; |
| 0 | 1757 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp"); |
| 1758 emit_d8(cbuf, disp); | |
| 1759 %} | |
| 1760 | |
| 1761 enc_class enc_cmov(cmpOp cop ) %{ // CMOV | |
| 1762 $$$emit8$primary; | |
| 1763 emit_cc(cbuf, $secondary, $cop$$cmpcode); | |
| 1764 %} | |
| 1765 | |
| 1766 enc_class enc_cmov_d(cmpOp cop, regD src ) %{ // CMOV | |
| 1767 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1); | |
| 1768 emit_d8(cbuf, op >> 8 ); | |
| 1769 emit_d8(cbuf, op & 255); | |
| 1770 %} | |
| 1771 | |
| 1772 // emulate a CMOV with a conditional branch around a MOV | |
| 1773 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV | |
| 1774 // Invert sense of branch from sense of CMOV | |
| 1775 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) ); | |
| 1776 emit_d8( cbuf, $brOffs$$constant ); | |
| 1777 %} | |
| 1778 | |
| 1779 enc_class enc_PartialSubtypeCheck( ) %{ | |
| 1780 Register Redi = as_Register(EDI_enc); // result register | |
| 1781 Register Reax = as_Register(EAX_enc); // super class | |
| 1782 Register Recx = as_Register(ECX_enc); // killed | |
| 1783 Register Resi = as_Register(ESI_enc); // sub class | |
|
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1784 Label miss; |
| 0 | 1785 |
| 1786 MacroAssembler _masm(&cbuf); | |
|
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1787 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi, |
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1788 NULL, &miss, |
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1789 /*set_cond_codes:*/ true); |
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1790 if ($primary) { |
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1791 __ xorptr(Redi, Redi); |
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1792 } |
| 0 | 1793 __ bind(miss); |
| 1794 %} | |
| 1795 | |
| 1796 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All | |
| 1797 MacroAssembler masm(&cbuf); | |
| 1798 int start = masm.offset(); | |
| 1799 if (UseSSE >= 2) { | |
| 1800 if (VerifyFPU) { | |
| 1801 masm.verify_FPU(0, "must be empty in SSE2+ mode"); | |
| 1802 } | |
| 1803 } else { | |
| 1804 // External c_calling_convention expects the FPU stack to be 'clean'. | |
| 1805 // Compiled code leaves it dirty. Do cleanup now. | |
| 1806 masm.empty_FPU_stack(); | |
| 1807 } | |
| 1808 if (sizeof_FFree_Float_Stack_All == -1) { | |
| 1809 sizeof_FFree_Float_Stack_All = masm.offset() - start; | |
| 1810 } else { | |
| 1811 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size"); | |
| 1812 } | |
| 1813 %} | |
| 1814 | |
| 1815 enc_class Verify_FPU_For_Leaf %{ | |
| 1816 if( VerifyFPU ) { | |
| 1817 MacroAssembler masm(&cbuf); | |
| 1818 masm.verify_FPU( -3, "Returning from Runtime Leaf call"); | |
| 1819 } | |
| 1820 %} | |
| 1821 | |
| 1822 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf | |
| 1823 // This is the instruction starting address for relocation info. | |
| 1748 | 1824 cbuf.set_insts_mark(); |
| 0 | 1825 $$$emit8$primary; |
| 1826 // CALL directly to the runtime | |
| 1748 | 1827 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), |
| 0 | 1828 runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 1829 | |
| 1830 if (UseSSE >= 2) { | |
| 1831 MacroAssembler _masm(&cbuf); | |
| 1832 BasicType rt = tf()->return_type(); | |
| 1833 | |
| 1834 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) { | |
| 1835 // A C runtime call where the return value is unused. In SSE2+ | |
| 1836 // mode the result needs to be removed from the FPU stack. It's | |
| 1837 // likely that this function call could be removed by the | |
| 1838 // optimizer if the C function is a pure function. | |
| 1839 __ ffree(0); | |
| 1840 } else if (rt == T_FLOAT) { | |
| 304 | 1841 __ lea(rsp, Address(rsp, -4)); |
| 0 | 1842 __ fstp_s(Address(rsp, 0)); |
| 1843 __ movflt(xmm0, Address(rsp, 0)); | |
| 304 | 1844 __ lea(rsp, Address(rsp, 4)); |
| 0 | 1845 } else if (rt == T_DOUBLE) { |
| 304 | 1846 __ lea(rsp, Address(rsp, -8)); |
| 0 | 1847 __ fstp_d(Address(rsp, 0)); |
| 1848 __ movdbl(xmm0, Address(rsp, 0)); | |
| 304 | 1849 __ lea(rsp, Address(rsp, 8)); |
| 0 | 1850 } |
| 1851 } | |
| 1852 %} | |
| 1853 | |
| 1854 | |
| 1855 enc_class pre_call_FPU %{ | |
| 1856 // If method sets FPU control word restore it here | |
| 1748 | 1857 debug_only(int off0 = cbuf.insts_size()); |
| 0 | 1858 if( Compile::current()->in_24_bit_fp_mode() ) { |
| 1859 MacroAssembler masm(&cbuf); | |
| 1860 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
| 1861 } | |
| 1748 | 1862 debug_only(int off1 = cbuf.insts_size()); |
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1863 assert(off1 - off0 == pre_call_FPU_size(), "correct size prediction"); |
| 0 | 1864 %} |
| 1865 | |
| 1866 enc_class post_call_FPU %{ | |
| 1867 // If method sets FPU control word do it here also | |
| 1868 if( Compile::current()->in_24_bit_fp_mode() ) { | |
| 1869 MacroAssembler masm(&cbuf); | |
| 1870 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); | |
| 1871 } | |
| 1872 %} | |
| 1873 | |
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1874 enc_class preserve_SP %{ |
| 1748 | 1875 debug_only(int off0 = cbuf.insts_size()); |
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1876 MacroAssembler _masm(&cbuf); |
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1877 // RBP is preserved across all calls, even compiled calls. |
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1878 // Use it to preserve RSP in places where the callee might change the SP. |
| 1567 | 1879 __ movptr(rbp_mh_SP_save, rsp); |
| 1748 | 1880 debug_only(int off1 = cbuf.insts_size()); |
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1881 assert(off1 - off0 == preserve_SP_size(), "correct size prediction"); |
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1882 %} |
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1883 |
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1884 enc_class restore_SP %{ |
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1885 MacroAssembler _masm(&cbuf); |
| 1567 | 1886 __ movptr(rsp, rbp_mh_SP_save); |
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1887 %} |
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1888 |
| 0 | 1889 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL |
| 1890 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
| 1891 // who we intended to call. | |
| 1748 | 1892 cbuf.set_insts_mark(); |
| 0 | 1893 $$$emit8$primary; |
| 1894 if ( !_method ) { | |
| 1748 | 1895 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), |
| 0 | 1896 runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 1897 } else if(_optimized_virtual) { | |
| 1748 | 1898 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), |
| 0 | 1899 opt_virtual_call_Relocation::spec(), RELOC_IMM32 ); |
| 1900 } else { | |
| 1748 | 1901 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), |
| 0 | 1902 static_call_Relocation::spec(), RELOC_IMM32 ); |
| 1903 } | |
| 1904 if( _method ) { // Emit stub for static call | |
| 1905 emit_java_to_interp(cbuf); | |
| 1906 } | |
| 1907 %} | |
| 1908 | |
| 1909 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL | |
| 1910 // !!!!! | |
| 1911 // Generate "Mov EAX,0x00", placeholder instruction to load oop-info | |
| 1912 // emit_call_dynamic_prologue( cbuf ); | |
| 1748 | 1913 cbuf.set_insts_mark(); |
| 0 | 1914 emit_opcode(cbuf, 0xB8 + EAX_enc); // mov EAX,-1 |
| 1915 emit_d32_reloc(cbuf, (int)Universe::non_oop_word(), oop_Relocation::spec_for_immediate(), RELOC_IMM32); | |
| 1748 | 1916 address virtual_call_oop_addr = cbuf.insts_mark(); |
| 0 | 1917 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine |
| 1918 // who we intended to call. | |
| 1748 | 1919 cbuf.set_insts_mark(); |
| 0 | 1920 $$$emit8$primary; |
| 1748 | 1921 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), |
| 0 | 1922 virtual_call_Relocation::spec(virtual_call_oop_addr), RELOC_IMM32 ); |
| 1923 %} | |
| 1924 | |
| 1925 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL | |
| 1926 int disp = in_bytes(methodOopDesc::from_compiled_offset()); | |
| 1927 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small"); | |
| 1928 | |
| 1929 // CALL *[EAX+in_bytes(methodOopDesc::from_compiled_code_entry_point_offset())] | |
| 1748 | 1930 cbuf.set_insts_mark(); |
| 0 | 1931 $$$emit8$primary; |
| 1932 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte | |
| 1933 emit_d8(cbuf, disp); // Displacement | |
| 1934 | |
| 1935 %} | |
| 1936 | |
| 1937 enc_class Xor_Reg (eRegI dst) %{ | |
| 1938 emit_opcode(cbuf, 0x33); | |
| 1939 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg); | |
| 1940 %} | |
| 1941 | |
| 1942 // Following encoding is no longer used, but may be restored if calling | |
| 1943 // convention changes significantly. | |
| 1944 // Became: Xor_Reg(EBP), Java_To_Runtime( labl ) | |
| 1945 // | |
| 1946 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL | |
| 1947 // // int ic_reg = Matcher::inline_cache_reg(); | |
| 1948 // // int ic_encode = Matcher::_regEncode[ic_reg]; | |
| 1949 // // int imo_reg = Matcher::interpreter_method_oop_reg(); | |
| 1950 // // int imo_encode = Matcher::_regEncode[imo_reg]; | |
| 1951 // | |
| 1952 // // // Interpreter expects method_oop in EBX, currently a callee-saved register, | |
| 1953 // // // so we load it immediately before the call | |
| 1954 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop | |
| 1955 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte | |
| 1956 // | |
| 1957 // // xor rbp,ebp | |
| 1958 // emit_opcode(cbuf, 0x33); | |
| 1959 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc); | |
| 1960 // | |
| 1961 // // CALL to interpreter. | |
| 1748 | 1962 // cbuf.set_insts_mark(); |
| 0 | 1963 // $$$emit8$primary; |
| 1748 | 1964 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4), |
| 0 | 1965 // runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 1966 // %} | |
| 1967 | |
| 1968 enc_class RegOpcImm (eRegI dst, immI8 shift) %{ // SHL, SAR, SHR | |
| 1969 $$$emit8$primary; | |
| 1970 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); | |
| 1971 $$$emit8$shift$$constant; | |
| 1972 %} | |
| 1973 | |
| 1974 enc_class LdImmI (eRegI dst, immI src) %{ // Load Immediate | |
| 1975 // Load immediate does not have a zero or sign extended version | |
| 1976 // for 8-bit immediates | |
| 1977 emit_opcode(cbuf, 0xB8 + $dst$$reg); | |
| 1978 $$$emit32$src$$constant; | |
| 1979 %} | |
| 1980 | |
| 1981 enc_class LdImmP (eRegI dst, immI src) %{ // Load Immediate | |
| 1982 // Load immediate does not have a zero or sign extended version | |
| 1983 // for 8-bit immediates | |
| 1984 emit_opcode(cbuf, $primary + $dst$$reg); | |
| 1985 $$$emit32$src$$constant; | |
| 1986 %} | |
| 1987 | |
| 1988 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate | |
| 1989 // Load immediate does not have a zero or sign extended version | |
| 1990 // for 8-bit immediates | |
| 1991 int dst_enc = $dst$$reg; | |
| 1992 int src_con = $src$$constant & 0x0FFFFFFFFL; | |
| 1993 if (src_con == 0) { | |
| 1994 // xor dst, dst | |
| 1995 emit_opcode(cbuf, 0x33); | |
| 1996 emit_rm(cbuf, 0x3, dst_enc, dst_enc); | |
| 1997 } else { | |
| 1998 emit_opcode(cbuf, $primary + dst_enc); | |
| 1999 emit_d32(cbuf, src_con); | |
| 2000 } | |
| 2001 %} | |
| 2002 | |
| 2003 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate | |
| 2004 // Load immediate does not have a zero or sign extended version | |
| 2005 // for 8-bit immediates | |
| 2006 int dst_enc = $dst$$reg + 2; | |
| 2007 int src_con = ((julong)($src$$constant)) >> 32; | |
| 2008 if (src_con == 0) { | |
| 2009 // xor dst, dst | |
| 2010 emit_opcode(cbuf, 0x33); | |
| 2011 emit_rm(cbuf, 0x3, dst_enc, dst_enc); | |
| 2012 } else { | |
| 2013 emit_opcode(cbuf, $primary + dst_enc); | |
| 2014 emit_d32(cbuf, src_con); | |
| 2015 } | |
| 2016 %} | |
| 2017 | |
| 2018 | |
| 2019 enc_class MovI2X_reg(regX dst, eRegI src) %{ | |
| 2020 emit_opcode(cbuf, 0x66 ); // MOVD dst,src | |
| 2021 emit_opcode(cbuf, 0x0F ); | |
| 2022 emit_opcode(cbuf, 0x6E ); | |
| 2023 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2024 %} | |
| 2025 | |
| 2026 enc_class MovX2I_reg(eRegI dst, regX src) %{ | |
| 2027 emit_opcode(cbuf, 0x66 ); // MOVD dst,src | |
| 2028 emit_opcode(cbuf, 0x0F ); | |
| 2029 emit_opcode(cbuf, 0x7E ); | |
| 2030 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg); | |
| 2031 %} | |
| 2032 | |
| 2033 enc_class MovL2XD_reg(regXD dst, eRegL src, regXD tmp) %{ | |
| 2034 { // MOVD $dst,$src.lo | |
| 2035 emit_opcode(cbuf,0x66); | |
| 2036 emit_opcode(cbuf,0x0F); | |
| 2037 emit_opcode(cbuf,0x6E); | |
| 2038 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2039 } | |
| 2040 { // MOVD $tmp,$src.hi | |
| 2041 emit_opcode(cbuf,0x66); | |
| 2042 emit_opcode(cbuf,0x0F); | |
| 2043 emit_opcode(cbuf,0x6E); | |
| 2044 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg)); | |
| 2045 } | |
| 2046 { // PUNPCKLDQ $dst,$tmp | |
| 2047 emit_opcode(cbuf,0x66); | |
| 2048 emit_opcode(cbuf,0x0F); | |
| 2049 emit_opcode(cbuf,0x62); | |
| 2050 emit_rm(cbuf, 0x3, $dst$$reg, $tmp$$reg); | |
| 2051 } | |
| 2052 %} | |
| 2053 | |
| 2054 enc_class MovXD2L_reg(eRegL dst, regXD src, regXD tmp) %{ | |
| 2055 { // MOVD $dst.lo,$src | |
| 2056 emit_opcode(cbuf,0x66); | |
| 2057 emit_opcode(cbuf,0x0F); | |
| 2058 emit_opcode(cbuf,0x7E); | |
| 2059 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg); | |
| 2060 } | |
| 2061 { // PSHUFLW $tmp,$src,0x4E (01001110b) | |
| 2062 emit_opcode(cbuf,0xF2); | |
| 2063 emit_opcode(cbuf,0x0F); | |
| 2064 emit_opcode(cbuf,0x70); | |
| 2065 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg); | |
| 2066 emit_d8(cbuf, 0x4E); | |
| 2067 } | |
| 2068 { // MOVD $dst.hi,$tmp | |
| 2069 emit_opcode(cbuf,0x66); | |
| 2070 emit_opcode(cbuf,0x0F); | |
| 2071 emit_opcode(cbuf,0x7E); | |
| 2072 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg)); | |
| 2073 } | |
| 2074 %} | |
| 2075 | |
| 2076 | |
| 2077 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 2078 enc_class enc_Copy( eRegI dst, eRegI src ) %{ | |
| 2079 encode_Copy( cbuf, $dst$$reg, $src$$reg ); | |
| 2080 %} | |
| 2081 | |
| 2082 enc_class enc_CopyL_Lo( eRegI dst, eRegL src ) %{ | |
| 2083 encode_Copy( cbuf, $dst$$reg, $src$$reg ); | |
| 2084 %} | |
| 2085 | |
| 2086 // Encode xmm reg-reg copy. If it is useless, then empty encoding. | |
| 2087 enc_class enc_CopyXD( RegXD dst, RegXD src ) %{ | |
| 2088 encode_CopyXD( cbuf, $dst$$reg, $src$$reg ); | |
| 2089 %} | |
| 2090 | |
| 2091 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many) | |
| 2092 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2093 %} | |
| 2094 | |
| 2095 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 2096 $$$emit8$primary; | |
| 2097 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2098 %} | |
| 2099 | |
| 2100 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 2101 $$$emit8$secondary; | |
| 2102 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg)); | |
| 2103 %} | |
| 2104 | |
| 2105 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 2106 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2107 %} | |
| 2108 | |
| 2109 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 2110 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg)); | |
| 2111 %} | |
| 2112 | |
| 2113 enc_class RegReg_HiLo( eRegL src, eRegI dst ) %{ | |
| 2114 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg)); | |
| 2115 %} | |
| 2116 | |
| 2117 enc_class Con32 (immI src) %{ // Con32(storeImmI) | |
| 2118 // Output immediate | |
| 2119 $$$emit32$src$$constant; | |
| 2120 %} | |
| 2121 | |
| 2122 enc_class Con32F_as_bits(immF src) %{ // storeF_imm | |
| 2123 // Output Float immediate bits | |
| 2124 jfloat jf = $src$$constant; | |
| 2125 int jf_as_bits = jint_cast( jf ); | |
| 2126 emit_d32(cbuf, jf_as_bits); | |
| 2127 %} | |
| 2128 | |
| 2129 enc_class Con32XF_as_bits(immXF src) %{ // storeX_imm | |
| 2130 // Output Float immediate bits | |
| 2131 jfloat jf = $src$$constant; | |
| 2132 int jf_as_bits = jint_cast( jf ); | |
| 2133 emit_d32(cbuf, jf_as_bits); | |
| 2134 %} | |
| 2135 | |
| 2136 enc_class Con16 (immI src) %{ // Con16(storeImmI) | |
| 2137 // Output immediate | |
| 2138 $$$emit16$src$$constant; | |
| 2139 %} | |
| 2140 | |
| 2141 enc_class Con_d32(immI src) %{ | |
| 2142 emit_d32(cbuf,$src$$constant); | |
| 2143 %} | |
| 2144 | |
| 2145 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI) | |
| 2146 // Output immediate memory reference | |
| 2147 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 ); | |
| 2148 emit_d32(cbuf, 0x00); | |
| 2149 %} | |
| 2150 | |
| 2151 enc_class lock_prefix( ) %{ | |
| 2152 if( os::is_MP() ) | |
| 2153 emit_opcode(cbuf,0xF0); // [Lock] | |
| 2154 %} | |
| 2155 | |
| 2156 // Cmp-xchg long value. | |
| 2157 // Note: we need to swap rbx, and rcx before and after the | |
| 2158 // cmpxchg8 instruction because the instruction uses | |
| 2159 // rcx as the high order word of the new value to store but | |
| 2160 // our register encoding uses rbx,. | |
| 2161 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{ | |
| 2162 | |
| 2163 // XCHG rbx,ecx | |
| 2164 emit_opcode(cbuf,0x87); | |
| 2165 emit_opcode(cbuf,0xD9); | |
| 2166 // [Lock] | |
| 2167 if( os::is_MP() ) | |
| 2168 emit_opcode(cbuf,0xF0); | |
| 2169 // CMPXCHG8 [Eptr] | |
| 2170 emit_opcode(cbuf,0x0F); | |
| 2171 emit_opcode(cbuf,0xC7); | |
| 2172 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg ); | |
| 2173 // XCHG rbx,ecx | |
| 2174 emit_opcode(cbuf,0x87); | |
| 2175 emit_opcode(cbuf,0xD9); | |
| 2176 %} | |
| 2177 | |
| 2178 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{ | |
| 2179 // [Lock] | |
| 2180 if( os::is_MP() ) | |
| 2181 emit_opcode(cbuf,0xF0); | |
| 2182 | |
| 2183 // CMPXCHG [Eptr] | |
| 2184 emit_opcode(cbuf,0x0F); | |
| 2185 emit_opcode(cbuf,0xB1); | |
| 2186 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg ); | |
| 2187 %} | |
| 2188 | |
| 2189 enc_class enc_flags_ne_to_boolean( iRegI res ) %{ | |
| 2190 int res_encoding = $res$$reg; | |
| 2191 | |
| 2192 // MOV res,0 | |
| 2193 emit_opcode( cbuf, 0xB8 + res_encoding); | |
| 2194 emit_d32( cbuf, 0 ); | |
| 2195 // JNE,s fail | |
| 2196 emit_opcode(cbuf,0x75); | |
| 2197 emit_d8(cbuf, 5 ); | |
| 2198 // MOV res,1 | |
| 2199 emit_opcode( cbuf, 0xB8 + res_encoding); | |
| 2200 emit_d32( cbuf, 1 ); | |
| 2201 // fail: | |
| 2202 %} | |
| 2203 | |
| 2204 enc_class set_instruction_start( ) %{ | |
| 1748 | 2205 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand |
| 0 | 2206 %} |
| 2207 | |
| 2208 enc_class RegMem (eRegI ereg, memory mem) %{ // emit_reg_mem | |
| 2209 int reg_encoding = $ereg$$reg; | |
| 2210 int base = $mem$$base; | |
| 2211 int index = $mem$$index; | |
| 2212 int scale = $mem$$scale; | |
| 2213 int displace = $mem$$disp; | |
| 2214 bool disp_is_oop = $mem->disp_is_oop(); | |
| 2215 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); | |
| 2216 %} | |
| 2217 | |
| 2218 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem | |
| 2219 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo | |
| 2220 int base = $mem$$base; | |
| 2221 int index = $mem$$index; | |
| 2222 int scale = $mem$$scale; | |
| 2223 int displace = $mem$$disp + 4; // Offset is 4 further in memory | |
| 2224 assert( !$mem->disp_is_oop(), "Cannot add 4 to oop" ); | |
| 2225 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, false/*disp_is_oop*/); | |
| 2226 %} | |
| 2227 | |
| 2228 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{ | |
| 2229 int r1, r2; | |
| 2230 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); } | |
| 2231 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); } | |
| 2232 emit_opcode(cbuf,0x0F); | |
| 2233 emit_opcode(cbuf,$tertiary); | |
| 2234 emit_rm(cbuf, 0x3, r1, r2); | |
| 2235 emit_d8(cbuf,$cnt$$constant); | |
| 2236 emit_d8(cbuf,$primary); | |
| 2237 emit_rm(cbuf, 0x3, $secondary, r1); | |
| 2238 emit_d8(cbuf,$cnt$$constant); | |
| 2239 %} | |
| 2240 | |
| 2241 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{ | |
| 2242 emit_opcode( cbuf, 0x8B ); // Move | |
| 2243 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg)); | |
|
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2244 if( $cnt$$constant > 32 ) { // Shift, if not by zero |
|
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2245 emit_d8(cbuf,$primary); |
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2246 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); |
|
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2247 emit_d8(cbuf,$cnt$$constant-32); |
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2248 } |
| 0 | 2249 emit_d8(cbuf,$primary); |
| 2250 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg)); | |
| 2251 emit_d8(cbuf,31); | |
| 2252 %} | |
| 2253 | |
| 2254 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{ | |
| 2255 int r1, r2; | |
| 2256 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); } | |
| 2257 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); } | |
| 2258 | |
| 2259 emit_opcode( cbuf, 0x8B ); // Move r1,r2 | |
| 2260 emit_rm(cbuf, 0x3, r1, r2); | |
| 2261 if( $cnt$$constant > 32 ) { // Shift, if not by zero | |
| 2262 emit_opcode(cbuf,$primary); | |
| 2263 emit_rm(cbuf, 0x3, $secondary, r1); | |
| 2264 emit_d8(cbuf,$cnt$$constant-32); | |
| 2265 } | |
| 2266 emit_opcode(cbuf,0x33); // XOR r2,r2 | |
| 2267 emit_rm(cbuf, 0x3, r2, r2); | |
| 2268 %} | |
| 2269 | |
| 2270 // Clone of RegMem but accepts an extra parameter to access each | |
| 2271 // half of a double in memory; it never needs relocation info. | |
| 2272 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, eRegI rm_reg) %{ | |
| 2273 emit_opcode(cbuf,$opcode$$constant); | |
| 2274 int reg_encoding = $rm_reg$$reg; | |
| 2275 int base = $mem$$base; | |
| 2276 int index = $mem$$index; | |
| 2277 int scale = $mem$$scale; | |
| 2278 int displace = $mem$$disp + $disp_for_half$$constant; | |
| 2279 bool disp_is_oop = false; | |
| 2280 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); | |
| 2281 %} | |
| 2282 | |
| 2283 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!! | |
| 2284 // | |
| 2285 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant | |
| 2286 // and it never needs relocation information. | |
| 2287 // Frequently used to move data between FPU's Stack Top and memory. | |
| 2288 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{ | |
| 2289 int rm_byte_opcode = $rm_opcode$$constant; | |
| 2290 int base = $mem$$base; | |
| 2291 int index = $mem$$index; | |
| 2292 int scale = $mem$$scale; | |
| 2293 int displace = $mem$$disp; | |
| 2294 assert( !$mem->disp_is_oop(), "No oops here because no relo info allowed" ); | |
| 2295 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, false); | |
| 2296 %} | |
| 2297 | |
| 2298 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{ | |
| 2299 int rm_byte_opcode = $rm_opcode$$constant; | |
| 2300 int base = $mem$$base; | |
| 2301 int index = $mem$$index; | |
| 2302 int scale = $mem$$scale; | |
| 2303 int displace = $mem$$disp; | |
| 2304 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals | |
| 2305 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop); | |
| 2306 %} | |
| 2307 | |
| 2308 enc_class RegLea (eRegI dst, eRegI src0, immI src1 ) %{ // emit_reg_lea | |
| 2309 int reg_encoding = $dst$$reg; | |
| 2310 int base = $src0$$reg; // 0xFFFFFFFF indicates no base | |
| 2311 int index = 0x04; // 0x04 indicates no index | |
| 2312 int scale = 0x00; // 0x00 indicates no scale | |
| 2313 int displace = $src1$$constant; // 0x00 indicates no displacement | |
| 2314 bool disp_is_oop = false; | |
| 2315 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); | |
| 2316 %} | |
| 2317 | |
| 2318 enc_class min_enc (eRegI dst, eRegI src) %{ // MIN | |
| 2319 // Compare dst,src | |
| 2320 emit_opcode(cbuf,0x3B); | |
| 2321 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2322 // jmp dst < src around move | |
| 2323 emit_opcode(cbuf,0x7C); | |
| 2324 emit_d8(cbuf,2); | |
| 2325 // move dst,src | |
| 2326 emit_opcode(cbuf,0x8B); | |
| 2327 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2328 %} | |
| 2329 | |
| 2330 enc_class max_enc (eRegI dst, eRegI src) %{ // MAX | |
| 2331 // Compare dst,src | |
| 2332 emit_opcode(cbuf,0x3B); | |
| 2333 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2334 // jmp dst > src around move | |
| 2335 emit_opcode(cbuf,0x7F); | |
| 2336 emit_d8(cbuf,2); | |
| 2337 // move dst,src | |
| 2338 emit_opcode(cbuf,0x8B); | |
| 2339 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2340 %} | |
| 2341 | |
| 2342 enc_class enc_FP_store(memory mem, regD src) %{ | |
| 2343 // If src is FPR1, we can just FST to store it. | |
| 2344 // Else we need to FLD it to FPR1, then FSTP to store/pop it. | |
| 2345 int reg_encoding = 0x2; // Just store | |
| 2346 int base = $mem$$base; | |
| 2347 int index = $mem$$index; | |
| 2348 int scale = $mem$$scale; | |
| 2349 int displace = $mem$$disp; | |
| 2350 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals | |
| 2351 if( $src$$reg != FPR1L_enc ) { | |
| 2352 reg_encoding = 0x3; // Store & pop | |
| 2353 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it) | |
| 2354 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2355 } | |
| 1748 | 2356 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand |
| 0 | 2357 emit_opcode(cbuf,$primary); |
| 2358 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); | |
| 2359 %} | |
| 2360 | |
| 2361 enc_class neg_reg(eRegI dst) %{ | |
| 2362 // NEG $dst | |
| 2363 emit_opcode(cbuf,0xF7); | |
| 2364 emit_rm(cbuf, 0x3, 0x03, $dst$$reg ); | |
| 2365 %} | |
| 2366 | |
| 2367 enc_class setLT_reg(eCXRegI dst) %{ | |
| 2368 // SETLT $dst | |
| 2369 emit_opcode(cbuf,0x0F); | |
| 2370 emit_opcode(cbuf,0x9C); | |
| 2371 emit_rm( cbuf, 0x3, 0x4, $dst$$reg ); | |
| 2372 %} | |
| 2373 | |
| 2374 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT | |
| 2375 int tmpReg = $tmp$$reg; | |
| 2376 | |
| 2377 // SUB $p,$q | |
| 2378 emit_opcode(cbuf,0x2B); | |
| 2379 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg); | |
| 2380 // SBB $tmp,$tmp | |
| 2381 emit_opcode(cbuf,0x1B); | |
| 2382 emit_rm(cbuf, 0x3, tmpReg, tmpReg); | |
| 2383 // AND $tmp,$y | |
| 2384 emit_opcode(cbuf,0x23); | |
| 2385 emit_rm(cbuf, 0x3, tmpReg, $y$$reg); | |
| 2386 // ADD $p,$tmp | |
| 2387 emit_opcode(cbuf,0x03); | |
| 2388 emit_rm(cbuf, 0x3, $p$$reg, tmpReg); | |
| 2389 %} | |
| 2390 | |
| 2391 enc_class enc_cmpLTP_mem(eRegI p, eRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT | |
| 2392 int tmpReg = $tmp$$reg; | |
| 2393 | |
| 2394 // SUB $p,$q | |
| 2395 emit_opcode(cbuf,0x2B); | |
| 2396 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg); | |
| 2397 // SBB $tmp,$tmp | |
| 2398 emit_opcode(cbuf,0x1B); | |
| 2399 emit_rm(cbuf, 0x3, tmpReg, tmpReg); | |
| 2400 // AND $tmp,$y | |
| 1748 | 2401 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand |
| 0 | 2402 emit_opcode(cbuf,0x23); |
| 2403 int reg_encoding = tmpReg; | |
| 2404 int base = $mem$$base; | |
| 2405 int index = $mem$$index; | |
| 2406 int scale = $mem$$scale; | |
| 2407 int displace = $mem$$disp; | |
| 2408 bool disp_is_oop = $mem->disp_is_oop(); | |
| 2409 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); | |
| 2410 // ADD $p,$tmp | |
| 2411 emit_opcode(cbuf,0x03); | |
| 2412 emit_rm(cbuf, 0x3, $p$$reg, tmpReg); | |
| 2413 %} | |
| 2414 | |
| 2415 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{ | |
| 2416 // TEST shift,32 | |
| 2417 emit_opcode(cbuf,0xF7); | |
| 2418 emit_rm(cbuf, 0x3, 0, ECX_enc); | |
| 2419 emit_d32(cbuf,0x20); | |
| 2420 // JEQ,s small | |
| 2421 emit_opcode(cbuf, 0x74); | |
| 2422 emit_d8(cbuf, 0x04); | |
| 2423 // MOV $dst.hi,$dst.lo | |
| 2424 emit_opcode( cbuf, 0x8B ); | |
| 2425 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg ); | |
| 2426 // CLR $dst.lo | |
| 2427 emit_opcode(cbuf, 0x33); | |
| 2428 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg); | |
| 2429 // small: | |
| 2430 // SHLD $dst.hi,$dst.lo,$shift | |
| 2431 emit_opcode(cbuf,0x0F); | |
| 2432 emit_opcode(cbuf,0xA5); | |
| 2433 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg)); | |
| 2434 // SHL $dst.lo,$shift" | |
| 2435 emit_opcode(cbuf,0xD3); | |
| 2436 emit_rm(cbuf, 0x3, 0x4, $dst$$reg ); | |
| 2437 %} | |
| 2438 | |
| 2439 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{ | |
| 2440 // TEST shift,32 | |
| 2441 emit_opcode(cbuf,0xF7); | |
| 2442 emit_rm(cbuf, 0x3, 0, ECX_enc); | |
| 2443 emit_d32(cbuf,0x20); | |
| 2444 // JEQ,s small | |
| 2445 emit_opcode(cbuf, 0x74); | |
| 2446 emit_d8(cbuf, 0x04); | |
| 2447 // MOV $dst.lo,$dst.hi | |
| 2448 emit_opcode( cbuf, 0x8B ); | |
| 2449 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2450 // CLR $dst.hi | |
| 2451 emit_opcode(cbuf, 0x33); | |
| 2452 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg)); | |
| 2453 // small: | |
| 2454 // SHRD $dst.lo,$dst.hi,$shift | |
| 2455 emit_opcode(cbuf,0x0F); | |
| 2456 emit_opcode(cbuf,0xAD); | |
| 2457 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg); | |
| 2458 // SHR $dst.hi,$shift" | |
| 2459 emit_opcode(cbuf,0xD3); | |
| 2460 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) ); | |
| 2461 %} | |
| 2462 | |
| 2463 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{ | |
| 2464 // TEST shift,32 | |
| 2465 emit_opcode(cbuf,0xF7); | |
| 2466 emit_rm(cbuf, 0x3, 0, ECX_enc); | |
| 2467 emit_d32(cbuf,0x20); | |
| 2468 // JEQ,s small | |
| 2469 emit_opcode(cbuf, 0x74); | |
| 2470 emit_d8(cbuf, 0x05); | |
| 2471 // MOV $dst.lo,$dst.hi | |
| 2472 emit_opcode( cbuf, 0x8B ); | |
| 2473 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2474 // SAR $dst.hi,31 | |
| 2475 emit_opcode(cbuf, 0xC1); | |
| 2476 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) ); | |
| 2477 emit_d8(cbuf, 0x1F ); | |
| 2478 // small: | |
| 2479 // SHRD $dst.lo,$dst.hi,$shift | |
| 2480 emit_opcode(cbuf,0x0F); | |
| 2481 emit_opcode(cbuf,0xAD); | |
| 2482 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg); | |
| 2483 // SAR $dst.hi,$shift" | |
| 2484 emit_opcode(cbuf,0xD3); | |
| 2485 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) ); | |
| 2486 %} | |
| 2487 | |
| 2488 | |
| 2489 // ----------------- Encodings for floating point unit ----------------- | |
| 2490 // May leave result in FPU-TOS or FPU reg depending on opcodes | |
| 2491 enc_class OpcReg_F (regF src) %{ // FMUL, FDIV | |
| 2492 $$$emit8$primary; | |
| 2493 emit_rm(cbuf, 0x3, $secondary, $src$$reg ); | |
| 2494 %} | |
| 2495 | |
| 2496 // Pop argument in FPR0 with FSTP ST(0) | |
| 2497 enc_class PopFPU() %{ | |
| 2498 emit_opcode( cbuf, 0xDD ); | |
| 2499 emit_d8( cbuf, 0xD8 ); | |
| 2500 %} | |
| 2501 | |
| 2502 // !!!!! equivalent to Pop_Reg_F | |
| 2503 enc_class Pop_Reg_D( regD dst ) %{ | |
| 2504 emit_opcode( cbuf, 0xDD ); // FSTP ST(i) | |
| 2505 emit_d8( cbuf, 0xD8+$dst$$reg ); | |
| 2506 %} | |
| 2507 | |
| 2508 enc_class Push_Reg_D( regD dst ) %{ | |
| 2509 emit_opcode( cbuf, 0xD9 ); | |
| 2510 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1) | |
| 2511 %} | |
| 2512 | |
| 2513 enc_class strictfp_bias1( regD dst ) %{ | |
| 2514 emit_opcode( cbuf, 0xDB ); // FLD m80real | |
| 2515 emit_opcode( cbuf, 0x2D ); | |
| 2516 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() ); | |
| 2517 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0 | |
| 2518 emit_opcode( cbuf, 0xC8+$dst$$reg ); | |
| 2519 %} | |
| 2520 | |
| 2521 enc_class strictfp_bias2( regD dst ) %{ | |
| 2522 emit_opcode( cbuf, 0xDB ); // FLD m80real | |
| 2523 emit_opcode( cbuf, 0x2D ); | |
| 2524 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() ); | |
| 2525 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0 | |
| 2526 emit_opcode( cbuf, 0xC8+$dst$$reg ); | |
| 2527 %} | |
| 2528 | |
| 2529 // Special case for moving an integer register to a stack slot. | |
| 2530 enc_class OpcPRegSS( stackSlotI dst, eRegI src ) %{ // RegSS | |
| 2531 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp ); | |
| 2532 %} | |
| 2533 | |
| 2534 // Special case for moving a register to a stack slot. | |
| 2535 enc_class RegSS( stackSlotI dst, eRegI src ) %{ // RegSS | |
| 2536 // Opcode already emitted | |
| 2537 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte | |
| 2538 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte | |
| 2539 emit_d32(cbuf, $dst$$disp); // Displacement | |
| 2540 %} | |
| 2541 | |
| 2542 // Push the integer in stackSlot 'src' onto FP-stack | |
| 2543 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src] | |
| 2544 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp ); | |
| 2545 %} | |
| 2546 | |
| 2547 // Push the float in stackSlot 'src' onto FP-stack | |
| 2548 enc_class Push_Mem_F( memory src ) %{ // FLD_S [ESP+src] | |
| 2549 store_to_stackslot( cbuf, 0xD9, 0x00, $src$$disp ); | |
| 2550 %} | |
| 2551 | |
| 2552 // Push the double in stackSlot 'src' onto FP-stack | |
| 2553 enc_class Push_Mem_D( memory src ) %{ // FLD_D [ESP+src] | |
| 2554 store_to_stackslot( cbuf, 0xDD, 0x00, $src$$disp ); | |
| 2555 %} | |
| 2556 | |
| 2557 // Push FPU's TOS float to a stack-slot, and pop FPU-stack | |
| 2558 enc_class Pop_Mem_F( stackSlotF dst ) %{ // FSTP_S [ESP+dst] | |
| 2559 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp ); | |
| 2560 %} | |
| 2561 | |
| 2562 // Same as Pop_Mem_F except for opcode | |
| 2563 // Push FPU's TOS double to a stack-slot, and pop FPU-stack | |
| 2564 enc_class Pop_Mem_D( stackSlotD dst ) %{ // FSTP_D [ESP+dst] | |
| 2565 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp ); | |
| 2566 %} | |
| 2567 | |
| 2568 enc_class Pop_Reg_F( regF dst ) %{ | |
| 2569 emit_opcode( cbuf, 0xDD ); // FSTP ST(i) | |
| 2570 emit_d8( cbuf, 0xD8+$dst$$reg ); | |
| 2571 %} | |
| 2572 | |
| 2573 enc_class Push_Reg_F( regF dst ) %{ | |
| 2574 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) | |
| 2575 emit_d8( cbuf, 0xC0-1+$dst$$reg ); | |
| 2576 %} | |
| 2577 | |
| 2578 // Push FPU's float to a stack-slot, and pop FPU-stack | |
| 2579 enc_class Pop_Mem_Reg_F( stackSlotF dst, regF src ) %{ | |
| 2580 int pop = 0x02; | |
| 2581 if ($src$$reg != FPR1L_enc) { | |
| 2582 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) | |
| 2583 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2584 pop = 0x03; | |
| 2585 } | |
| 2586 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst] | |
| 2587 %} | |
| 2588 | |
| 2589 // Push FPU's double to a stack-slot, and pop FPU-stack | |
| 2590 enc_class Pop_Mem_Reg_D( stackSlotD dst, regD src ) %{ | |
| 2591 int pop = 0x02; | |
| 2592 if ($src$$reg != FPR1L_enc) { | |
| 2593 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) | |
| 2594 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2595 pop = 0x03; | |
| 2596 } | |
| 2597 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst] | |
| 2598 %} | |
| 2599 | |
| 2600 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack | |
| 2601 enc_class Pop_Reg_Reg_D( regD dst, regF src ) %{ | |
| 2602 int pop = 0xD0 - 1; // -1 since we skip FLD | |
| 2603 if ($src$$reg != FPR1L_enc) { | |
| 2604 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1) | |
| 2605 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2606 pop = 0xD8; | |
| 2607 } | |
| 2608 emit_opcode( cbuf, 0xDD ); | |
| 2609 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i) | |
| 2610 %} | |
| 2611 | |
| 2612 | |
| 2613 enc_class Mul_Add_F( regF dst, regF src, regF src1, regF src2 ) %{ | |
| 2614 MacroAssembler masm(&cbuf); | |
| 2615 masm.fld_s( $src1$$reg-1); // nothing at TOS, load TOS from src1.reg | |
| 2616 masm.fmul( $src2$$reg+0); // value at TOS | |
| 2617 masm.fadd( $src$$reg+0); // value at TOS | |
| 2618 masm.fstp_d( $dst$$reg+0); // value at TOS, popped off after store | |
| 2619 %} | |
| 2620 | |
| 2621 | |
| 2622 enc_class Push_Reg_Mod_D( regD dst, regD src) %{ | |
| 2623 // load dst in FPR0 | |
| 2624 emit_opcode( cbuf, 0xD9 ); | |
| 2625 emit_d8( cbuf, 0xC0-1+$dst$$reg ); | |
| 2626 if ($src$$reg != FPR1L_enc) { | |
| 2627 // fincstp | |
| 2628 emit_opcode (cbuf, 0xD9); | |
| 2629 emit_opcode (cbuf, 0xF7); | |
| 2630 // swap src with FPR1: | |
| 2631 // FXCH FPR1 with src | |
| 2632 emit_opcode(cbuf, 0xD9); | |
| 2633 emit_d8(cbuf, 0xC8-1+$src$$reg ); | |
| 2634 // fdecstp | |
| 2635 emit_opcode (cbuf, 0xD9); | |
| 2636 emit_opcode (cbuf, 0xF6); | |
| 2637 } | |
| 2638 %} | |
| 2639 | |
| 2640 enc_class Push_ModD_encoding( regXD src0, regXD src1) %{ | |
| 2641 // Allocate a word | |
| 2642 emit_opcode(cbuf,0x83); // SUB ESP,8 | |
| 2643 emit_opcode(cbuf,0xEC); | |
| 2644 emit_d8(cbuf,0x08); | |
| 2645 | |
| 2646 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src1 | |
| 2647 emit_opcode (cbuf, 0x0F ); | |
| 2648 emit_opcode (cbuf, 0x11 ); | |
| 2649 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 2650 | |
| 2651 emit_opcode(cbuf,0xDD ); // FLD_D [ESP] | |
| 2652 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 2653 | |
| 2654 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src0 | |
| 2655 emit_opcode (cbuf, 0x0F ); | |
| 2656 emit_opcode (cbuf, 0x11 ); | |
| 2657 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 2658 | |
| 2659 emit_opcode(cbuf,0xDD ); // FLD_D [ESP] | |
| 2660 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 2661 | |
| 2662 %} | |
| 2663 | |
| 2664 enc_class Push_ModX_encoding( regX src0, regX src1) %{ | |
| 2665 // Allocate a word | |
| 2666 emit_opcode(cbuf,0x83); // SUB ESP,4 | |
| 2667 emit_opcode(cbuf,0xEC); | |
| 2668 emit_d8(cbuf,0x04); | |
| 2669 | |
| 2670 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src1 | |
| 2671 emit_opcode (cbuf, 0x0F ); | |
| 2672 emit_opcode (cbuf, 0x11 ); | |
| 2673 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 2674 | |
| 2675 emit_opcode(cbuf,0xD9 ); // FLD [ESP] | |
| 2676 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 2677 | |
| 2678 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src0 | |
| 2679 emit_opcode (cbuf, 0x0F ); | |
| 2680 emit_opcode (cbuf, 0x11 ); | |
| 2681 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 2682 | |
| 2683 emit_opcode(cbuf,0xD9 ); // FLD [ESP] | |
| 2684 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 2685 | |
| 2686 %} | |
| 2687 | |
| 2688 enc_class Push_ResultXD(regXD dst) %{ | |
| 2689 store_to_stackslot( cbuf, 0xDD, 0x03, 0 ); //FSTP [ESP] | |
| 2690 | |
| 2691 // UseXmmLoadAndClearUpper ? movsd dst,[esp] : movlpd dst,[esp] | |
| 2692 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66); | |
| 2693 emit_opcode (cbuf, 0x0F ); | |
| 2694 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12); | |
| 2695 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 2696 | |
| 2697 emit_opcode(cbuf,0x83); // ADD ESP,8 | |
| 2698 emit_opcode(cbuf,0xC4); | |
| 2699 emit_d8(cbuf,0x08); | |
| 2700 %} | |
| 2701 | |
| 2702 enc_class Push_ResultX(regX dst, immI d8) %{ | |
| 2703 store_to_stackslot( cbuf, 0xD9, 0x03, 0 ); //FSTP_S [ESP] | |
| 2704 | |
| 2705 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP] | |
| 2706 emit_opcode (cbuf, 0x0F ); | |
| 2707 emit_opcode (cbuf, 0x10 ); | |
| 2708 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 2709 | |
| 2710 emit_opcode(cbuf,0x83); // ADD ESP,d8 (4 or 8) | |
| 2711 emit_opcode(cbuf,0xC4); | |
| 2712 emit_d8(cbuf,$d8$$constant); | |
| 2713 %} | |
| 2714 | |
| 2715 enc_class Push_SrcXD(regXD src) %{ | |
| 2716 // Allocate a word | |
| 2717 emit_opcode(cbuf,0x83); // SUB ESP,8 | |
| 2718 emit_opcode(cbuf,0xEC); | |
| 2719 emit_d8(cbuf,0x08); | |
| 2720 | |
| 2721 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src | |
| 2722 emit_opcode (cbuf, 0x0F ); | |
| 2723 emit_opcode (cbuf, 0x11 ); | |
| 2724 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 2725 | |
| 2726 emit_opcode(cbuf,0xDD ); // FLD_D [ESP] | |
| 2727 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 2728 %} | |
| 2729 | |
| 2730 enc_class push_stack_temp_qword() %{ | |
| 2731 emit_opcode(cbuf,0x83); // SUB ESP,8 | |
| 2732 emit_opcode(cbuf,0xEC); | |
| 2733 emit_d8 (cbuf,0x08); | |
| 2734 %} | |
| 2735 | |
| 2736 enc_class pop_stack_temp_qword() %{ | |
| 2737 emit_opcode(cbuf,0x83); // ADD ESP,8 | |
| 2738 emit_opcode(cbuf,0xC4); | |
| 2739 emit_d8 (cbuf,0x08); | |
| 2740 %} | |
| 2741 | |
| 2742 enc_class push_xmm_to_fpr1( regXD xmm_src ) %{ | |
| 2743 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], xmm_src | |
| 2744 emit_opcode (cbuf, 0x0F ); | |
| 2745 emit_opcode (cbuf, 0x11 ); | |
| 2746 encode_RegMem(cbuf, $xmm_src$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 2747 | |
| 2748 emit_opcode(cbuf,0xDD ); // FLD_D [ESP] | |
| 2749 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 2750 %} | |
| 2751 | |
| 2752 // Compute X^Y using Intel's fast hardware instructions, if possible. | |
| 2753 // Otherwise return a NaN. | |
| 2754 enc_class pow_exp_core_encoding %{ | |
| 2755 // FPR1 holds Y*ln2(X). Compute FPR1 = 2^(Y*ln2(X)) | |
| 2756 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xC0); // fdup = fld st(0) Q Q | |
| 2757 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xFC); // frndint int(Q) Q | |
| 2758 emit_opcode(cbuf,0xDC); emit_opcode(cbuf,0xE9); // fsub st(1) -= st(0); int(Q) frac(Q) | |
| 2759 emit_opcode(cbuf,0xDB); // FISTP [ESP] frac(Q) | |
| 2760 emit_opcode(cbuf,0x1C); | |
| 2761 emit_d8(cbuf,0x24); | |
| 2762 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xF0); // f2xm1 2^frac(Q)-1 | |
| 2763 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xE8); // fld1 1 2^frac(Q)-1 | |
| 2764 emit_opcode(cbuf,0xDE); emit_opcode(cbuf,0xC1); // faddp 2^frac(Q) | |
| 2765 emit_opcode(cbuf,0x8B); // mov rax,[esp+0]=int(Q) | |
| 2766 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 0, false); | |
| 2767 emit_opcode(cbuf,0xC7); // mov rcx,0xFFFFF800 - overflow mask | |
| 2768 emit_rm(cbuf, 0x3, 0x0, ECX_enc); | |
| 2769 emit_d32(cbuf,0xFFFFF800); | |
| 2770 emit_opcode(cbuf,0x81); // add rax,1023 - the double exponent bias | |
| 2771 emit_rm(cbuf, 0x3, 0x0, EAX_enc); | |
| 2772 emit_d32(cbuf,1023); | |
| 2773 emit_opcode(cbuf,0x8B); // mov rbx,eax | |
| 2774 emit_rm(cbuf, 0x3, EBX_enc, EAX_enc); | |
| 2775 emit_opcode(cbuf,0xC1); // shl rax,20 - Slide to exponent position | |
| 2776 emit_rm(cbuf,0x3,0x4,EAX_enc); | |
| 2777 emit_d8(cbuf,20); | |
| 2778 emit_opcode(cbuf,0x85); // test rbx,ecx - check for overflow | |
| 2779 emit_rm(cbuf, 0x3, EBX_enc, ECX_enc); | |
| 2780 emit_opcode(cbuf,0x0F); emit_opcode(cbuf,0x45); // CMOVne rax,ecx - overflow; stuff NAN into EAX | |
| 2781 emit_rm(cbuf, 0x3, EAX_enc, ECX_enc); | |
| 2782 emit_opcode(cbuf,0x89); // mov [esp+4],eax - Store as part of double word | |
| 2783 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 4, false); | |
| 2784 emit_opcode(cbuf,0xC7); // mov [esp+0],0 - [ESP] = (double)(1<<int(Q)) = 2^int(Q) | |
| 2785 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 2786 emit_d32(cbuf,0); | |
| 2787 emit_opcode(cbuf,0xDC); // fmul dword st(0),[esp+0]; FPR1 = 2^int(Q)*2^frac(Q) = 2^Q | |
| 2788 encode_RegMem(cbuf, 0x1, ESP_enc, 0x4, 0, 0, false); | |
| 2789 %} | |
| 2790 | |
| 2791 // enc_class Pop_Reg_Mod_D( regD dst, regD src) | |
| 2792 // was replaced by Push_Result_Mod_D followed by Pop_Reg_X() or Pop_Mem_X() | |
| 2793 | |
| 2794 enc_class Push_Result_Mod_D( regD src) %{ | |
| 2795 if ($src$$reg != FPR1L_enc) { | |
| 2796 // fincstp | |
| 2797 emit_opcode (cbuf, 0xD9); | |
| 2798 emit_opcode (cbuf, 0xF7); | |
| 2799 // FXCH FPR1 with src | |
| 2800 emit_opcode(cbuf, 0xD9); | |
| 2801 emit_d8(cbuf, 0xC8-1+$src$$reg ); | |
| 2802 // fdecstp | |
| 2803 emit_opcode (cbuf, 0xD9); | |
| 2804 emit_opcode (cbuf, 0xF6); | |
| 2805 } | |
| 2806 // // following asm replaced with Pop_Reg_F or Pop_Mem_F | |
| 2807 // // FSTP FPR$dst$$reg | |
| 2808 // emit_opcode( cbuf, 0xDD ); | |
| 2809 // emit_d8( cbuf, 0xD8+$dst$$reg ); | |
| 2810 %} | |
| 2811 | |
| 2812 enc_class fnstsw_sahf_skip_parity() %{ | |
| 2813 // fnstsw ax | |
| 2814 emit_opcode( cbuf, 0xDF ); | |
| 2815 emit_opcode( cbuf, 0xE0 ); | |
| 2816 // sahf | |
| 2817 emit_opcode( cbuf, 0x9E ); | |
| 2818 // jnp ::skip | |
| 2819 emit_opcode( cbuf, 0x7B ); | |
| 2820 emit_opcode( cbuf, 0x05 ); | |
| 2821 %} | |
| 2822 | |
| 2823 enc_class emitModD() %{ | |
| 2824 // fprem must be iterative | |
| 2825 // :: loop | |
| 2826 // fprem | |
| 2827 emit_opcode( cbuf, 0xD9 ); | |
| 2828 emit_opcode( cbuf, 0xF8 ); | |
| 2829 // wait | |
| 2830 emit_opcode( cbuf, 0x9b ); | |
| 2831 // fnstsw ax | |
| 2832 emit_opcode( cbuf, 0xDF ); | |
| 2833 emit_opcode( cbuf, 0xE0 ); | |
| 2834 // sahf | |
| 2835 emit_opcode( cbuf, 0x9E ); | |
| 2836 // jp ::loop | |
| 2837 emit_opcode( cbuf, 0x0F ); | |
| 2838 emit_opcode( cbuf, 0x8A ); | |
| 2839 emit_opcode( cbuf, 0xF4 ); | |
| 2840 emit_opcode( cbuf, 0xFF ); | |
| 2841 emit_opcode( cbuf, 0xFF ); | |
| 2842 emit_opcode( cbuf, 0xFF ); | |
| 2843 %} | |
| 2844 | |
| 2845 enc_class fpu_flags() %{ | |
| 2846 // fnstsw_ax | |
| 2847 emit_opcode( cbuf, 0xDF); | |
| 2848 emit_opcode( cbuf, 0xE0); | |
| 2849 // test ax,0x0400 | |
| 2850 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate | |
| 2851 emit_opcode( cbuf, 0xA9 ); | |
| 2852 emit_d16 ( cbuf, 0x0400 ); | |
| 2853 // // // This sequence works, but stalls for 12-16 cycles on PPro | |
| 2854 // // test rax,0x0400 | |
| 2855 // emit_opcode( cbuf, 0xA9 ); | |
| 2856 // emit_d32 ( cbuf, 0x00000400 ); | |
| 2857 // | |
| 2858 // jz exit (no unordered comparison) | |
| 2859 emit_opcode( cbuf, 0x74 ); | |
| 2860 emit_d8 ( cbuf, 0x02 ); | |
| 2861 // mov ah,1 - treat as LT case (set carry flag) | |
| 2862 emit_opcode( cbuf, 0xB4 ); | |
| 2863 emit_d8 ( cbuf, 0x01 ); | |
| 2864 // sahf | |
| 2865 emit_opcode( cbuf, 0x9E); | |
| 2866 %} | |
| 2867 | |
| 2868 enc_class cmpF_P6_fixup() %{ | |
| 2869 // Fixup the integer flags in case comparison involved a NaN | |
| 2870 // | |
| 2871 // JNP exit (no unordered comparison, P-flag is set by NaN) | |
| 2872 emit_opcode( cbuf, 0x7B ); | |
| 2873 emit_d8 ( cbuf, 0x03 ); | |
| 2874 // MOV AH,1 - treat as LT case (set carry flag) | |
| 2875 emit_opcode( cbuf, 0xB4 ); | |
| 2876 emit_d8 ( cbuf, 0x01 ); | |
| 2877 // SAHF | |
| 2878 emit_opcode( cbuf, 0x9E); | |
| 2879 // NOP // target for branch to avoid branch to branch | |
| 2880 emit_opcode( cbuf, 0x90); | |
| 2881 %} | |
| 2882 | |
| 2883 // fnstsw_ax(); | |
| 2884 // sahf(); | |
| 2885 // movl(dst, nan_result); | |
| 2886 // jcc(Assembler::parity, exit); | |
| 2887 // movl(dst, less_result); | |
| 2888 // jcc(Assembler::below, exit); | |
| 2889 // movl(dst, equal_result); | |
| 2890 // jcc(Assembler::equal, exit); | |
| 2891 // movl(dst, greater_result); | |
| 2892 | |
| 2893 // less_result = 1; | |
| 2894 // greater_result = -1; | |
| 2895 // equal_result = 0; | |
| 2896 // nan_result = -1; | |
| 2897 | |
| 2898 enc_class CmpF_Result(eRegI dst) %{ | |
| 2899 // fnstsw_ax(); | |
| 2900 emit_opcode( cbuf, 0xDF); | |
| 2901 emit_opcode( cbuf, 0xE0); | |
| 2902 // sahf | |
| 2903 emit_opcode( cbuf, 0x9E); | |
| 2904 // movl(dst, nan_result); | |
| 2905 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2906 emit_d32( cbuf, -1 ); | |
| 2907 // jcc(Assembler::parity, exit); | |
| 2908 emit_opcode( cbuf, 0x7A ); | |
| 2909 emit_d8 ( cbuf, 0x13 ); | |
| 2910 // movl(dst, less_result); | |
| 2911 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2912 emit_d32( cbuf, -1 ); | |
| 2913 // jcc(Assembler::below, exit); | |
| 2914 emit_opcode( cbuf, 0x72 ); | |
| 2915 emit_d8 ( cbuf, 0x0C ); | |
| 2916 // movl(dst, equal_result); | |
| 2917 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2918 emit_d32( cbuf, 0 ); | |
| 2919 // jcc(Assembler::equal, exit); | |
| 2920 emit_opcode( cbuf, 0x74 ); | |
| 2921 emit_d8 ( cbuf, 0x05 ); | |
| 2922 // movl(dst, greater_result); | |
| 2923 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2924 emit_d32( cbuf, 1 ); | |
| 2925 %} | |
| 2926 | |
| 2927 | |
| 2928 // XMM version of CmpF_Result. Because the XMM compare | |
| 2929 // instructions set the EFLAGS directly. It becomes simpler than | |
| 2930 // the float version above. | |
| 2931 enc_class CmpX_Result(eRegI dst) %{ | |
| 2932 MacroAssembler _masm(&cbuf); | |
| 2933 Label nan, inc, done; | |
| 2934 | |
| 2935 __ jccb(Assembler::parity, nan); | |
| 2936 __ jccb(Assembler::equal, done); | |
| 2937 __ jccb(Assembler::above, inc); | |
| 2938 __ bind(nan); | |
| 304 | 2939 __ decrement(as_Register($dst$$reg)); // NO L qqq |
| 0 | 2940 __ jmpb(done); |
| 2941 __ bind(inc); | |
| 304 | 2942 __ increment(as_Register($dst$$reg)); // NO L qqq |
| 0 | 2943 __ bind(done); |
| 2944 %} | |
| 2945 | |
| 2946 // Compare the longs and set flags | |
| 2947 // BROKEN! Do Not use as-is | |
| 2948 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{ | |
| 2949 // CMP $src1.hi,$src2.hi | |
| 2950 emit_opcode( cbuf, 0x3B ); | |
| 2951 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) ); | |
| 2952 // JNE,s done | |
| 2953 emit_opcode(cbuf,0x75); | |
| 2954 emit_d8(cbuf, 2 ); | |
| 2955 // CMP $src1.lo,$src2.lo | |
| 2956 emit_opcode( cbuf, 0x3B ); | |
| 2957 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); | |
| 2958 // done: | |
| 2959 %} | |
| 2960 | |
| 2961 enc_class convert_int_long( regL dst, eRegI src ) %{ | |
| 2962 // mov $dst.lo,$src | |
| 2963 int dst_encoding = $dst$$reg; | |
| 2964 int src_encoding = $src$$reg; | |
| 2965 encode_Copy( cbuf, dst_encoding , src_encoding ); | |
| 2966 // mov $dst.hi,$src | |
| 2967 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding ); | |
| 2968 // sar $dst.hi,31 | |
| 2969 emit_opcode( cbuf, 0xC1 ); | |
| 2970 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) ); | |
| 2971 emit_d8(cbuf, 0x1F ); | |
| 2972 %} | |
| 2973 | |
| 2974 enc_class convert_long_double( eRegL src ) %{ | |
| 2975 // push $src.hi | |
| 2976 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg)); | |
| 2977 // push $src.lo | |
| 2978 emit_opcode(cbuf, 0x50+$src$$reg ); | |
| 2979 // fild 64-bits at [SP] | |
| 2980 emit_opcode(cbuf,0xdf); | |
| 2981 emit_d8(cbuf, 0x6C); | |
| 2982 emit_d8(cbuf, 0x24); | |
| 2983 emit_d8(cbuf, 0x00); | |
| 2984 // pop stack | |
| 2985 emit_opcode(cbuf, 0x83); // add SP, #8 | |
| 2986 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 2987 emit_d8(cbuf, 0x8); | |
| 2988 %} | |
| 2989 | |
| 2990 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{ | |
| 2991 // IMUL EDX:EAX,$src1 | |
| 2992 emit_opcode( cbuf, 0xF7 ); | |
| 2993 emit_rm( cbuf, 0x3, 0x5, $src1$$reg ); | |
| 2994 // SAR EDX,$cnt-32 | |
| 2995 int shift_count = ((int)$cnt$$constant) - 32; | |
| 2996 if (shift_count > 0) { | |
| 2997 emit_opcode(cbuf, 0xC1); | |
| 2998 emit_rm(cbuf, 0x3, 7, $dst$$reg ); | |
| 2999 emit_d8(cbuf, shift_count); | |
| 3000 } | |
| 3001 %} | |
| 3002 | |
| 3003 // this version doesn't have add sp, 8 | |
| 3004 enc_class convert_long_double2( eRegL src ) %{ | |
| 3005 // push $src.hi | |
| 3006 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg)); | |
| 3007 // push $src.lo | |
| 3008 emit_opcode(cbuf, 0x50+$src$$reg ); | |
| 3009 // fild 64-bits at [SP] | |
| 3010 emit_opcode(cbuf,0xdf); | |
| 3011 emit_d8(cbuf, 0x6C); | |
| 3012 emit_d8(cbuf, 0x24); | |
| 3013 emit_d8(cbuf, 0x00); | |
| 3014 %} | |
| 3015 | |
| 3016 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{ | |
| 3017 // Basic idea: long = (long)int * (long)int | |
| 3018 // IMUL EDX:EAX, src | |
| 3019 emit_opcode( cbuf, 0xF7 ); | |
| 3020 emit_rm( cbuf, 0x3, 0x5, $src$$reg); | |
| 3021 %} | |
| 3022 | |
| 3023 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{ | |
| 3024 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL) | |
| 3025 // MUL EDX:EAX, src | |
| 3026 emit_opcode( cbuf, 0xF7 ); | |
| 3027 emit_rm( cbuf, 0x3, 0x4, $src$$reg); | |
| 3028 %} | |
| 3029 | |
| 3030 enc_class long_multiply( eADXRegL dst, eRegL src, eRegI tmp ) %{ | |
| 3031 // Basic idea: lo(result) = lo(x_lo * y_lo) | |
| 3032 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) | |
| 3033 // MOV $tmp,$src.lo | |
| 3034 encode_Copy( cbuf, $tmp$$reg, $src$$reg ); | |
| 3035 // IMUL $tmp,EDX | |
| 3036 emit_opcode( cbuf, 0x0F ); | |
| 3037 emit_opcode( cbuf, 0xAF ); | |
| 3038 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 3039 // MOV EDX,$src.hi | |
| 3040 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) ); | |
| 3041 // IMUL EDX,EAX | |
| 3042 emit_opcode( cbuf, 0x0F ); | |
| 3043 emit_opcode( cbuf, 0xAF ); | |
| 3044 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg ); | |
| 3045 // ADD $tmp,EDX | |
| 3046 emit_opcode( cbuf, 0x03 ); | |
| 3047 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 3048 // MUL EDX:EAX,$src.lo | |
| 3049 emit_opcode( cbuf, 0xF7 ); | |
| 3050 emit_rm( cbuf, 0x3, 0x4, $src$$reg ); | |
| 3051 // ADD EDX,ESI | |
| 3052 emit_opcode( cbuf, 0x03 ); | |
| 3053 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg ); | |
| 3054 %} | |
| 3055 | |
| 3056 enc_class long_multiply_con( eADXRegL dst, immL_127 src, eRegI tmp ) %{ | |
| 3057 // Basic idea: lo(result) = lo(src * y_lo) | |
| 3058 // hi(result) = hi(src * y_lo) + lo(src * y_hi) | |
| 3059 // IMUL $tmp,EDX,$src | |
| 3060 emit_opcode( cbuf, 0x6B ); | |
| 3061 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 3062 emit_d8( cbuf, (int)$src$$constant ); | |
| 3063 // MOV EDX,$src | |
| 3064 emit_opcode(cbuf, 0xB8 + EDX_enc); | |
| 3065 emit_d32( cbuf, (int)$src$$constant ); | |
| 3066 // MUL EDX:EAX,EDX | |
| 3067 emit_opcode( cbuf, 0xF7 ); | |
| 3068 emit_rm( cbuf, 0x3, 0x4, EDX_enc ); | |
| 3069 // ADD EDX,ESI | |
| 3070 emit_opcode( cbuf, 0x03 ); | |
| 3071 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg ); | |
| 3072 %} | |
| 3073 | |
| 3074 enc_class long_div( eRegL src1, eRegL src2 ) %{ | |
| 3075 // PUSH src1.hi | |
| 3076 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) ); | |
| 3077 // PUSH src1.lo | |
| 3078 emit_opcode(cbuf, 0x50+$src1$$reg ); | |
| 3079 // PUSH src2.hi | |
| 3080 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) ); | |
| 3081 // PUSH src2.lo | |
| 3082 emit_opcode(cbuf, 0x50+$src2$$reg ); | |
| 3083 // CALL directly to the runtime | |
| 1748 | 3084 cbuf.set_insts_mark(); |
| 0 | 3085 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 3086 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 3087 // Restore stack |
| 3088 emit_opcode(cbuf, 0x83); // add SP, #framesize | |
| 3089 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 3090 emit_d8(cbuf, 4*4); | |
| 3091 %} | |
| 3092 | |
| 3093 enc_class long_mod( eRegL src1, eRegL src2 ) %{ | |
| 3094 // PUSH src1.hi | |
| 3095 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) ); | |
| 3096 // PUSH src1.lo | |
| 3097 emit_opcode(cbuf, 0x50+$src1$$reg ); | |
| 3098 // PUSH src2.hi | |
| 3099 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) ); | |
| 3100 // PUSH src2.lo | |
| 3101 emit_opcode(cbuf, 0x50+$src2$$reg ); | |
| 3102 // CALL directly to the runtime | |
| 1748 | 3103 cbuf.set_insts_mark(); |
| 0 | 3104 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 3105 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 3106 // Restore stack |
| 3107 emit_opcode(cbuf, 0x83); // add SP, #framesize | |
| 3108 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 3109 emit_d8(cbuf, 4*4); | |
| 3110 %} | |
| 3111 | |
| 3112 enc_class long_cmp_flags0( eRegL src, eRegI tmp ) %{ | |
| 3113 // MOV $tmp,$src.lo | |
| 3114 emit_opcode(cbuf, 0x8B); | |
| 3115 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg); | |
| 3116 // OR $tmp,$src.hi | |
| 3117 emit_opcode(cbuf, 0x0B); | |
| 3118 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg)); | |
| 3119 %} | |
| 3120 | |
| 3121 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{ | |
| 3122 // CMP $src1.lo,$src2.lo | |
| 3123 emit_opcode( cbuf, 0x3B ); | |
| 3124 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); | |
| 3125 // JNE,s skip | |
| 3126 emit_cc(cbuf, 0x70, 0x5); | |
| 3127 emit_d8(cbuf,2); | |
| 3128 // CMP $src1.hi,$src2.hi | |
| 3129 emit_opcode( cbuf, 0x3B ); | |
| 3130 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) ); | |
| 3131 %} | |
| 3132 | |
| 3133 enc_class long_cmp_flags2( eRegL src1, eRegL src2, eRegI tmp ) %{ | |
| 3134 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits | |
| 3135 emit_opcode( cbuf, 0x3B ); | |
| 3136 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); | |
| 3137 // MOV $tmp,$src1.hi | |
| 3138 emit_opcode( cbuf, 0x8B ); | |
| 3139 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) ); | |
| 3140 // SBB $tmp,$src2.hi\t! Compute flags for long compare | |
| 3141 emit_opcode( cbuf, 0x1B ); | |
| 3142 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) ); | |
| 3143 %} | |
| 3144 | |
| 3145 enc_class long_cmp_flags3( eRegL src, eRegI tmp ) %{ | |
| 3146 // XOR $tmp,$tmp | |
| 3147 emit_opcode(cbuf,0x33); // XOR | |
| 3148 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg); | |
| 3149 // CMP $tmp,$src.lo | |
| 3150 emit_opcode( cbuf, 0x3B ); | |
| 3151 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg ); | |
| 3152 // SBB $tmp,$src.hi | |
| 3153 emit_opcode( cbuf, 0x1B ); | |
| 3154 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) ); | |
| 3155 %} | |
| 3156 | |
| 3157 // Sniff, sniff... smells like Gnu Superoptimizer | |
| 3158 enc_class neg_long( eRegL dst ) %{ | |
| 3159 emit_opcode(cbuf,0xF7); // NEG hi | |
| 3160 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg)); | |
| 3161 emit_opcode(cbuf,0xF7); // NEG lo | |
| 3162 emit_rm (cbuf,0x3, 0x3, $dst$$reg ); | |
| 3163 emit_opcode(cbuf,0x83); // SBB hi,0 | |
| 3164 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg)); | |
| 3165 emit_d8 (cbuf,0 ); | |
| 3166 %} | |
| 3167 | |
| 3168 enc_class movq_ld(regXD dst, memory mem) %{ | |
| 3169 MacroAssembler _masm(&cbuf); | |
| 624 | 3170 __ movq($dst$$XMMRegister, $mem$$Address); |
| 0 | 3171 %} |
| 3172 | |
| 3173 enc_class movq_st(memory mem, regXD src) %{ | |
| 3174 MacroAssembler _masm(&cbuf); | |
| 624 | 3175 __ movq($mem$$Address, $src$$XMMRegister); |
| 0 | 3176 %} |
| 3177 | |
| 3178 enc_class pshufd_8x8(regX dst, regX src) %{ | |
| 3179 MacroAssembler _masm(&cbuf); | |
| 3180 | |
| 3181 encode_CopyXD(cbuf, $dst$$reg, $src$$reg); | |
| 3182 __ punpcklbw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg)); | |
| 3183 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg), 0x00); | |
| 3184 %} | |
| 3185 | |
| 3186 enc_class pshufd_4x16(regX dst, regX src) %{ | |
| 3187 MacroAssembler _masm(&cbuf); | |
| 3188 | |
| 3189 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), 0x00); | |
| 3190 %} | |
| 3191 | |
| 3192 enc_class pshufd(regXD dst, regXD src, int mode) %{ | |
| 3193 MacroAssembler _masm(&cbuf); | |
| 3194 | |
| 3195 __ pshufd(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), $mode); | |
| 3196 %} | |
| 3197 | |
| 3198 enc_class pxor(regXD dst, regXD src) %{ | |
| 3199 MacroAssembler _masm(&cbuf); | |
| 3200 | |
| 3201 __ pxor(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg)); | |
| 3202 %} | |
| 3203 | |
| 3204 enc_class mov_i2x(regXD dst, eRegI src) %{ | |
| 3205 MacroAssembler _masm(&cbuf); | |
| 3206 | |
| 304 | 3207 __ movdl(as_XMMRegister($dst$$reg), as_Register($src$$reg)); |
| 0 | 3208 %} |
| 3209 | |
| 3210 | |
| 3211 // Because the transitions from emitted code to the runtime | |
| 3212 // monitorenter/exit helper stubs are so slow it's critical that | |
| 3213 // we inline both the stack-locking fast-path and the inflated fast path. | |
| 3214 // | |
| 3215 // See also: cmpFastLock and cmpFastUnlock. | |
| 3216 // | |
| 3217 // What follows is a specialized inline transliteration of the code | |
| 3218 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat | |
| 3219 // another option would be to emit TrySlowEnter and TrySlowExit methods | |
| 3220 // at startup-time. These methods would accept arguments as | |
| 3221 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure | |
| 3222 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply | |
| 3223 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit. | |
| 3224 // In practice, however, the # of lock sites is bounded and is usually small. | |
| 3225 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer | |
| 3226 // if the processor uses simple bimodal branch predictors keyed by EIP | |
| 3227 // Since the helper routines would be called from multiple synchronization | |
| 3228 // sites. | |
| 3229 // | |
| 3230 // An even better approach would be write "MonitorEnter()" and "MonitorExit()" | |
| 3231 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites | |
| 3232 // to those specialized methods. That'd give us a mostly platform-independent | |
| 3233 // implementation that the JITs could optimize and inline at their pleasure. | |
| 3234 // Done correctly, the only time we'd need to cross to native could would be | |
| 3235 // to park() or unpark() threads. We'd also need a few more unsafe operators | |
| 3236 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and | |
| 3237 // (b) explicit barriers or fence operations. | |
| 3238 // | |
| 3239 // TODO: | |
| 3240 // | |
| 3241 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr). | |
| 3242 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals. | |
| 3243 // Given TLAB allocation, Self is usually manifested in a register, so passing it into | |
| 3244 // the lock operators would typically be faster than reifying Self. | |
| 3245 // | |
| 3246 // * Ideally I'd define the primitives as: | |
| 3247 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED. | |
| 3248 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED | |
| 3249 // Unfortunately ADLC bugs prevent us from expressing the ideal form. | |
| 3250 // Instead, we're stuck with a rather awkward and brittle register assignments below. | |
| 3251 // Furthermore the register assignments are overconstrained, possibly resulting in | |
| 3252 // sub-optimal code near the synchronization site. | |
| 3253 // | |
| 3254 // * Eliminate the sp-proximity tests and just use "== Self" tests instead. | |
| 3255 // Alternately, use a better sp-proximity test. | |
| 3256 // | |
| 3257 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value. | |
| 3258 // Either one is sufficient to uniquely identify a thread. | |
| 3259 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead. | |
| 3260 // | |
| 3261 // * Intrinsify notify() and notifyAll() for the common cases where the | |
| 3262 // object is locked by the calling thread but the waitlist is empty. | |
| 3263 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll(). | |
| 3264 // | |
| 3265 // * use jccb and jmpb instead of jcc and jmp to improve code density. | |
| 3266 // But beware of excessive branch density on AMD Opterons. | |
| 3267 // | |
| 3268 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success | |
| 3269 // or failure of the fast-path. If the fast-path fails then we pass | |
| 3270 // control to the slow-path, typically in C. In Fast_Lock and | |
| 3271 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2 | |
| 3272 // will emit a conditional branch immediately after the node. | |
| 3273 // So we have branches to branches and lots of ICC.ZF games. | |
| 3274 // Instead, it might be better to have C2 pass a "FailureLabel" | |
| 3275 // into Fast_Lock and Fast_Unlock. In the case of success, control | |
| 3276 // will drop through the node. ICC.ZF is undefined at exit. | |
| 3277 // In the case of failure, the node will branch directly to the | |
| 3278 // FailureLabel | |
| 3279 | |
| 3280 | |
| 3281 // obj: object to lock | |
| 3282 // box: on-stack box address (displaced header location) - KILLED | |
| 3283 // rax,: tmp -- KILLED | |
| 3284 // scr: tmp -- KILLED | |
| 3285 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{ | |
| 3286 | |
| 3287 Register objReg = as_Register($obj$$reg); | |
| 3288 Register boxReg = as_Register($box$$reg); | |
| 3289 Register tmpReg = as_Register($tmp$$reg); | |
| 3290 Register scrReg = as_Register($scr$$reg); | |
| 3291 | |
| 3292 // Ensure the register assignents are disjoint | |
| 3293 guarantee (objReg != boxReg, "") ; | |
| 3294 guarantee (objReg != tmpReg, "") ; | |
| 3295 guarantee (objReg != scrReg, "") ; | |
| 3296 guarantee (boxReg != tmpReg, "") ; | |
| 3297 guarantee (boxReg != scrReg, "") ; | |
| 3298 guarantee (tmpReg == as_Register(EAX_enc), "") ; | |
| 3299 | |
| 3300 MacroAssembler masm(&cbuf); | |
| 3301 | |
| 3302 if (_counters != NULL) { | |
| 3303 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr())); | |
| 3304 } | |
| 3305 if (EmitSync & 1) { | |
| 3306 // set box->dhw = unused_mark (3) | |
| 304 | 3307 // Force all sync thru slow-path: slow_enter() and slow_exit() |
| 3308 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ; | |
| 3309 masm.cmpptr (rsp, (int32_t)0) ; | |
| 3310 } else | |
| 3311 if (EmitSync & 2) { | |
| 3312 Label DONE_LABEL ; | |
| 0 | 3313 if (UseBiasedLocking) { |
| 3314 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument. | |
| 3315 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters); | |
| 3316 } | |
| 3317 | |
| 304 | 3318 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword |
| 3319 masm.orptr (tmpReg, 0x1); | |
| 3320 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS | |
| 0 | 3321 if (os::is_MP()) { masm.lock(); } |
| 304 | 3322 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg |
| 0 | 3323 masm.jcc(Assembler::equal, DONE_LABEL); |
| 3324 // Recursive locking | |
| 304 | 3325 masm.subptr(tmpReg, rsp); |
| 3326 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 ); | |
| 3327 masm.movptr(Address(boxReg, 0), tmpReg); | |
| 3328 masm.bind(DONE_LABEL) ; | |
| 3329 } else { | |
| 3330 // Possible cases that we'll encounter in fast_lock | |
| 0 | 3331 // ------------------------------------------------ |
| 3332 // * Inflated | |
| 3333 // -- unlocked | |
| 3334 // -- Locked | |
| 3335 // = by self | |
| 3336 // = by other | |
| 3337 // * biased | |
| 3338 // -- by Self | |
| 3339 // -- by other | |
| 3340 // * neutral | |
| 3341 // * stack-locked | |
| 3342 // -- by self | |
| 3343 // = sp-proximity test hits | |
| 3344 // = sp-proximity test generates false-negative | |
| 3345 // -- by other | |
| 3346 // | |
| 3347 | |
| 3348 Label IsInflated, DONE_LABEL, PopDone ; | |
| 3349 | |
| 3350 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage | |
| 3351 // order to reduce the number of conditional branches in the most common cases. | |
| 3352 // Beware -- there's a subtle invariant that fetch of the markword | |
| 3353 // at [FETCH], below, will never observe a biased encoding (*101b). | |
| 3354 // If this invariant is not held we risk exclusion (safety) failure. | |
|
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3355 if (UseBiasedLocking && !UseOptoBiasInlining) { |
| 0 | 3356 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters); |
| 3357 } | |
| 3358 | |
| 304 | 3359 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH] |
| 3360 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral) | |
| 0 | 3361 masm.jccb (Assembler::notZero, IsInflated) ; |
| 3362 | |
| 3363 // Attempt stack-locking ... | |
| 304 | 3364 masm.orptr (tmpReg, 0x1); |
| 3365 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS | |
| 0 | 3366 if (os::is_MP()) { masm.lock(); } |
| 304 | 3367 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg |
| 0 | 3368 if (_counters != NULL) { |
| 3369 masm.cond_inc32(Assembler::equal, | |
| 3370 ExternalAddress((address)_counters->fast_path_entry_count_addr())); | |
| 3371 } | |
| 3372 masm.jccb (Assembler::equal, DONE_LABEL); | |
| 3373 | |
| 3374 // Recursive locking | |
| 304 | 3375 masm.subptr(tmpReg, rsp); |
| 3376 masm.andptr(tmpReg, 0xFFFFF003 ); | |
| 3377 masm.movptr(Address(boxReg, 0), tmpReg); | |
| 0 | 3378 if (_counters != NULL) { |
| 3379 masm.cond_inc32(Assembler::equal, | |
| 3380 ExternalAddress((address)_counters->fast_path_entry_count_addr())); | |
| 3381 } | |
| 3382 masm.jmp (DONE_LABEL) ; | |
| 3383 | |
| 3384 masm.bind (IsInflated) ; | |
| 3385 | |
| 3386 // The object is inflated. | |
| 3387 // | |
| 3388 // TODO-FIXME: eliminate the ugly use of manifest constants: | |
| 3389 // Use markOopDesc::monitor_value instead of "2". | |
| 3390 // use markOop::unused_mark() instead of "3". | |
| 3391 // The tmpReg value is an objectMonitor reference ORed with | |
| 3392 // markOopDesc::monitor_value (2). We can either convert tmpReg to an | |
| 3393 // objectmonitor pointer by masking off the "2" bit or we can just | |
| 3394 // use tmpReg as an objectmonitor pointer but bias the objectmonitor | |
| 3395 // field offsets with "-2" to compensate for and annul the low-order tag bit. | |
| 3396 // | |
| 3397 // I use the latter as it avoids AGI stalls. | |
| 3398 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]" | |
| 3399 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]". | |
| 3400 // | |
| 3401 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2) | |
| 3402 | |
| 3403 // boxReg refers to the on-stack BasicLock in the current frame. | |
| 3404 // We'd like to write: | |
| 3405 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices. | |
| 3406 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers | |
| 3407 // additional latency as we have another ST in the store buffer that must drain. | |
| 3408 | |
| 304 | 3409 if (EmitSync & 8192) { |
| 3410 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty | |
| 3411 masm.get_thread (scrReg) ; | |
| 3412 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2] | |
|
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3413 masm.movptr(tmpReg, NULL_WORD); // consider: xor vs mov |
| 304 | 3414 if (os::is_MP()) { masm.lock(); } |
| 3415 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; | |
| 3416 } else | |
| 0 | 3417 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS |
| 304 | 3418 masm.movptr(scrReg, boxReg) ; |
| 3419 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2] | |
| 0 | 3420 |
| 3421 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes | |
| 3422 if ((EmitSync & 2048) && VM_Version::supports_3dnow() && os::is_MP()) { | |
| 3423 // prefetchw [eax + Offset(_owner)-2] | |
| 304 | 3424 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2)); |
| 0 | 3425 } |
| 3426 | |
| 3427 if ((EmitSync & 64) == 0) { | |
| 3428 // Optimistic form: consider XORL tmpReg,tmpReg | |
|
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3429 masm.movptr(tmpReg, NULL_WORD) ; |
| 304 | 3430 } else { |
| 0 | 3431 // Can suffer RTS->RTO upgrades on shared or cold $ lines |
| 3432 // Test-And-CAS instead of CAS | |
| 304 | 3433 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner |
| 3434 masm.testptr(tmpReg, tmpReg) ; // Locked ? | |
| 3435 masm.jccb (Assembler::notZero, DONE_LABEL) ; | |
| 0 | 3436 } |
| 3437 | |
| 3438 // Appears unlocked - try to swing _owner from null to non-null. | |
| 3439 // Ideally, I'd manifest "Self" with get_thread and then attempt | |
| 3440 // to CAS the register containing Self into m->Owner. | |
| 3441 // But we don't have enough registers, so instead we can either try to CAS | |
| 3442 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds | |
| 3443 // we later store "Self" into m->Owner. Transiently storing a stack address | |
| 3444 // (rsp or the address of the box) into m->owner is harmless. | |
| 3445 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. | |
| 3446 if (os::is_MP()) { masm.lock(); } | |
| 304 | 3447 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
| 3448 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3 | |
| 3449 masm.jccb (Assembler::notZero, DONE_LABEL) ; | |
| 0 | 3450 masm.get_thread (scrReg) ; // beware: clobbers ICCs |
| 304 | 3451 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ; |
| 3452 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success | |
| 3453 | |
| 3454 // If the CAS fails we can either retry or pass control to the slow-path. | |
| 3455 // We use the latter tactic. | |
| 0 | 3456 // Pass the CAS result in the icc.ZFlag into DONE_LABEL |
| 3457 // If the CAS was successful ... | |
| 3458 // Self has acquired the lock | |
| 3459 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. | |
| 3460 // Intentional fall-through into DONE_LABEL ... | |
| 3461 } else { | |
| 304 | 3462 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty |
| 3463 masm.movptr(boxReg, tmpReg) ; | |
| 0 | 3464 |
| 3465 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes | |
| 3466 if ((EmitSync & 2048) && VM_Version::supports_3dnow() && os::is_MP()) { | |
| 3467 // prefetchw [eax + Offset(_owner)-2] | |
| 304 | 3468 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2)); |
| 0 | 3469 } |
| 3470 | |
| 3471 if ((EmitSync & 64) == 0) { | |
| 3472 // Optimistic form | |
| 304 | 3473 masm.xorptr (tmpReg, tmpReg) ; |
| 3474 } else { | |
| 0 | 3475 // Can suffer RTS->RTO upgrades on shared or cold $ lines |
| 304 | 3476 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner |
| 3477 masm.testptr(tmpReg, tmpReg) ; // Locked ? | |
| 3478 masm.jccb (Assembler::notZero, DONE_LABEL) ; | |
| 0 | 3479 } |
| 3480 | |
| 3481 // Appears unlocked - try to swing _owner from null to non-null. | |
| 3482 // Use either "Self" (in scr) or rsp as thread identity in _owner. | |
| 3483 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. | |
| 3484 masm.get_thread (scrReg) ; | |
| 3485 if (os::is_MP()) { masm.lock(); } | |
| 304 | 3486 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
| 0 | 3487 |
| 3488 // If the CAS fails we can either retry or pass control to the slow-path. | |
| 3489 // We use the latter tactic. | |
| 3490 // Pass the CAS result in the icc.ZFlag into DONE_LABEL | |
| 3491 // If the CAS was successful ... | |
| 3492 // Self has acquired the lock | |
| 3493 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. | |
| 3494 // Intentional fall-through into DONE_LABEL ... | |
| 3495 } | |
| 3496 | |
| 3497 // DONE_LABEL is a hot target - we'd really like to place it at the | |
| 3498 // start of cache line by padding with NOPs. | |
| 3499 // See the AMD and Intel software optimization manuals for the | |
| 3500 // most efficient "long" NOP encodings. | |
| 3501 // Unfortunately none of our alignment mechanisms suffice. | |
| 3502 masm.bind(DONE_LABEL); | |
| 3503 | |
| 3504 // Avoid branch-to-branch on AMD processors | |
| 3505 // This appears to be superstition. | |
| 3506 if (EmitSync & 32) masm.nop() ; | |
| 3507 | |
| 3508 | |
| 3509 // At DONE_LABEL the icc ZFlag is set as follows ... | |
| 3510 // Fast_Unlock uses the same protocol. | |
| 3511 // ZFlag == 1 -> Success | |
| 3512 // ZFlag == 0 -> Failure - force control through the slow-path | |
| 3513 } | |
| 3514 %} | |
| 3515 | |
| 3516 // obj: object to unlock | |
| 3517 // box: box address (displaced header location), killed. Must be EAX. | |
| 3518 // rbx,: killed tmp; cannot be obj nor box. | |
| 3519 // | |
| 3520 // Some commentary on balanced locking: | |
| 3521 // | |
| 3522 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites. | |
| 3523 // Methods that don't have provably balanced locking are forced to run in the | |
| 3524 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock. | |
| 3525 // The interpreter provides two properties: | |
| 3526 // I1: At return-time the interpreter automatically and quietly unlocks any | |
| 3527 // objects acquired the current activation (frame). Recall that the | |
| 3528 // interpreter maintains an on-stack list of locks currently held by | |
| 3529 // a frame. | |
| 3530 // I2: If a method attempts to unlock an object that is not held by the | |
| 3531 // the frame the interpreter throws IMSX. | |
| 3532 // | |
| 3533 // Lets say A(), which has provably balanced locking, acquires O and then calls B(). | |
| 3534 // B() doesn't have provably balanced locking so it runs in the interpreter. | |
| 3535 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O | |
| 3536 // is still locked by A(). | |
| 3537 // | |
| 3538 // The only other source of unbalanced locking would be JNI. The "Java Native Interface: | |
| 3539 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter | |
| 3540 // should not be unlocked by "normal" java-level locking and vice-versa. The specification | |
| 3541 // doesn't specify what will occur if a program engages in such mixed-mode locking, however. | |
| 3542 | |
| 3543 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{ | |
| 3544 | |
| 3545 Register objReg = as_Register($obj$$reg); | |
| 3546 Register boxReg = as_Register($box$$reg); | |
| 3547 Register tmpReg = as_Register($tmp$$reg); | |
| 3548 | |
| 3549 guarantee (objReg != boxReg, "") ; | |
| 3550 guarantee (objReg != tmpReg, "") ; | |
| 3551 guarantee (boxReg != tmpReg, "") ; | |
| 3552 guarantee (boxReg == as_Register(EAX_enc), "") ; | |
| 3553 MacroAssembler masm(&cbuf); | |
| 3554 | |
| 3555 if (EmitSync & 4) { | |
| 3556 // Disable - inhibit all inlining. Force control through the slow-path | |
| 304 | 3557 masm.cmpptr (rsp, 0) ; |
| 3558 } else | |
| 0 | 3559 if (EmitSync & 8) { |
| 3560 Label DONE_LABEL ; | |
| 3561 if (UseBiasedLocking) { | |
| 3562 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); | |
| 3563 } | |
| 3564 // classic stack-locking code ... | |
| 304 | 3565 masm.movptr(tmpReg, Address(boxReg, 0)) ; |
| 3566 masm.testptr(tmpReg, tmpReg) ; | |
| 0 | 3567 masm.jcc (Assembler::zero, DONE_LABEL) ; |
| 3568 if (os::is_MP()) { masm.lock(); } | |
| 304 | 3569 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box |
| 0 | 3570 masm.bind(DONE_LABEL); |
| 3571 } else { | |
| 3572 Label DONE_LABEL, Stacked, CheckSucc, Inflated ; | |
| 3573 | |
| 3574 // Critically, the biased locking test must have precedence over | |
| 3575 // and appear before the (box->dhw == 0) recursive stack-lock test. | |
|
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3576 if (UseBiasedLocking && !UseOptoBiasInlining) { |
| 0 | 3577 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); |
| 3578 } | |
| 304 | 3579 |
| 3580 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header | |
| 3581 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword | |
| 0 | 3582 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock |
| 3583 | |
| 304 | 3584 masm.testptr(tmpReg, 0x02) ; // Inflated? |
| 0 | 3585 masm.jccb (Assembler::zero, Stacked) ; |
| 3586 | |
| 3587 masm.bind (Inflated) ; | |
| 3588 // It's inflated. | |
| 3589 // Despite our balanced locking property we still check that m->_owner == Self | |
| 3590 // as java routines or native JNI code called by this thread might | |
| 3591 // have released the lock. | |
| 3592 // Refer to the comments in synchronizer.cpp for how we might encode extra | |
| 3593 // state in _succ so we can avoid fetching EntryList|cxq. | |
| 3594 // | |
| 3595 // I'd like to add more cases in fast_lock() and fast_unlock() -- | |
| 3596 // such as recursive enter and exit -- but we have to be wary of | |
| 3597 // I$ bloat, T$ effects and BP$ effects. | |
| 3598 // | |
| 3599 // If there's no contention try a 1-0 exit. That is, exit without | |
| 3600 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how | |
| 3601 // we detect and recover from the race that the 1-0 exit admits. | |
| 3602 // | |
| 3603 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier | |
| 3604 // before it STs null into _owner, releasing the lock. Updates | |
| 3605 // to data protected by the critical section must be visible before | |
| 3606 // we drop the lock (and thus before any other thread could acquire | |
| 3607 // the lock and observe the fields protected by the lock). | |
| 3608 // IA32's memory-model is SPO, so STs are ordered with respect to | |
| 3609 // each other and there's no need for an explicit barrier (fence). | |
| 3610 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html. | |
| 3611 | |
| 3612 masm.get_thread (boxReg) ; | |
| 3613 if ((EmitSync & 4096) && VM_Version::supports_3dnow() && os::is_MP()) { | |
| 304 | 3614 // prefetchw [ebx + Offset(_owner)-2] |
| 3615 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2)); | |
| 0 | 3616 } |
| 3617 | |
| 3618 // Note that we could employ various encoding schemes to reduce | |
| 3619 // the number of loads below (currently 4) to just 2 or 3. | |
| 3620 // Refer to the comments in synchronizer.cpp. | |
| 3621 // In practice the chain of fetches doesn't seem to impact performance, however. | |
| 3622 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) { | |
| 3623 // Attempt to reduce branch density - AMD's branch predictor. | |
| 304 | 3624 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
| 3625 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ; | |
| 3626 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ; | |
| 3627 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ; | |
| 3628 masm.jccb (Assembler::notZero, DONE_LABEL) ; | |
|
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3629 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ; |
| 304 | 3630 masm.jmpb (DONE_LABEL) ; |
| 3631 } else { | |
| 3632 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; | |
| 3633 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ; | |
| 3634 masm.jccb (Assembler::notZero, DONE_LABEL) ; | |
| 3635 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ; | |
| 3636 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ; | |
| 3637 masm.jccb (Assembler::notZero, CheckSucc) ; | |
|
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3638 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ; |
| 304 | 3639 masm.jmpb (DONE_LABEL) ; |
| 0 | 3640 } |
| 3641 | |
| 3642 // The Following code fragment (EmitSync & 65536) improves the performance of | |
| 3643 // contended applications and contended synchronization microbenchmarks. | |
| 3644 // Unfortunately the emission of the code - even though not executed - causes regressions | |
| 3645 // in scimark and jetstream, evidently because of $ effects. Replacing the code | |
| 3646 // with an equal number of never-executed NOPs results in the same regression. | |
| 3647 // We leave it off by default. | |
| 3648 | |
| 3649 if ((EmitSync & 65536) != 0) { | |
| 3650 Label LSuccess, LGoSlowPath ; | |
| 3651 | |
| 3652 masm.bind (CheckSucc) ; | |
| 3653 | |
| 3654 // Optional pre-test ... it's safe to elide this | |
| 304 | 3655 if ((EmitSync & 16) == 0) { |
| 3656 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ; | |
| 3657 masm.jccb (Assembler::zero, LGoSlowPath) ; | |
| 0 | 3658 } |
| 3659 | |
| 3660 // We have a classic Dekker-style idiom: | |
| 3661 // ST m->_owner = 0 ; MEMBAR; LD m->_succ | |
| 3662 // There are a number of ways to implement the barrier: | |
| 3663 // (1) lock:andl &m->_owner, 0 | |
| 3664 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form. | |
| 3665 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0 | |
| 3666 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8 | |
| 3667 // (2) If supported, an explicit MFENCE is appealing. | |
| 3668 // In older IA32 processors MFENCE is slower than lock:add or xchg | |
| 3669 // particularly if the write-buffer is full as might be the case if | |
| 3670 // if stores closely precede the fence or fence-equivalent instruction. | |
| 3671 // In more modern implementations MFENCE appears faster, however. | |
| 3672 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack | |
| 3673 // The $lines underlying the top-of-stack should be in M-state. | |
| 3674 // The locked add instruction is serializing, of course. | |
| 3675 // (4) Use xchg, which is serializing | |
| 3676 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works | |
| 3677 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0. | |
| 3678 // The integer condition codes will tell us if succ was 0. | |
| 3679 // Since _succ and _owner should reside in the same $line and | |
| 3680 // we just stored into _owner, it's likely that the $line | |
| 3681 // remains in M-state for the lock:orl. | |
| 3682 // | |
| 3683 // We currently use (3), although it's likely that switching to (2) | |
| 3684 // is correct for the future. | |
| 304 | 3685 |
|
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|
3686 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ; |
| 304 | 3687 if (os::is_MP()) { |
| 3688 if (VM_Version::supports_sse2() && 1 == FenceInstruction) { | |
| 3689 masm.mfence(); | |
| 3690 } else { | |
| 3691 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ; | |
| 0 | 3692 } |
| 3693 } | |
| 3694 // Ratify _succ remains non-null | |
| 304 | 3695 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ; |
| 3696 masm.jccb (Assembler::notZero, LSuccess) ; | |
| 3697 | |
| 3698 masm.xorptr(boxReg, boxReg) ; // box is really EAX | |
| 0 | 3699 if (os::is_MP()) { masm.lock(); } |
| 304 | 3700 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)); |
| 0 | 3701 masm.jccb (Assembler::notEqual, LSuccess) ; |
| 3702 // Since we're low on registers we installed rsp as a placeholding in _owner. | |
| 3703 // Now install Self over rsp. This is safe as we're transitioning from | |
| 3704 // non-null to non=null | |
| 3705 masm.get_thread (boxReg) ; | |
| 304 | 3706 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ; |
| 0 | 3707 // Intentional fall-through into LGoSlowPath ... |
| 3708 | |
| 304 | 3709 masm.bind (LGoSlowPath) ; |
| 3710 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure | |
| 3711 masm.jmpb (DONE_LABEL) ; | |
| 3712 | |
| 3713 masm.bind (LSuccess) ; | |
| 3714 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success | |
| 3715 masm.jmpb (DONE_LABEL) ; | |
| 0 | 3716 } |
| 3717 | |
| 3718 masm.bind (Stacked) ; | |
| 3719 // It's not inflated and it's not recursively stack-locked and it's not biased. | |
| 3720 // It must be stack-locked. | |
| 3721 // Try to reset the header to displaced header. | |
| 3722 // The "box" value on the stack is stable, so we can reload | |
| 3723 // and be assured we observe the same value as above. | |
| 304 | 3724 masm.movptr(tmpReg, Address(boxReg, 0)) ; |
| 0 | 3725 if (os::is_MP()) { masm.lock(); } |
| 304 | 3726 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box |
| 0 | 3727 // Intention fall-thru into DONE_LABEL |
| 3728 | |
| 3729 | |
| 3730 // DONE_LABEL is a hot target - we'd really like to place it at the | |
| 3731 // start of cache line by padding with NOPs. | |
| 3732 // See the AMD and Intel software optimization manuals for the | |
| 3733 // most efficient "long" NOP encodings. | |
| 3734 // Unfortunately none of our alignment mechanisms suffice. | |
| 3735 if ((EmitSync & 65536) == 0) { | |
| 3736 masm.bind (CheckSucc) ; | |
| 3737 } | |
| 3738 masm.bind(DONE_LABEL); | |
| 3739 | |
| 3740 // Avoid branch to branch on AMD processors | |
| 3741 if (EmitSync & 32768) { masm.nop() ; } | |
| 3742 } | |
| 3743 %} | |
| 3744 | |
|
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6695049: (coll) Create an x86 intrinsic for Arrays.equals
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113
diff
changeset
|
3745 |
| 0 | 3746 enc_class enc_pop_rdx() %{ |
| 3747 emit_opcode(cbuf,0x5A); | |
| 3748 %} | |
| 3749 | |
| 3750 enc_class enc_rethrow() %{ | |
| 1748 | 3751 cbuf.set_insts_mark(); |
| 0 | 3752 emit_opcode(cbuf, 0xE9); // jmp entry |
| 1748 | 3753 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.insts_end())-4, |
| 0 | 3754 runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 3755 %} | |
| 3756 | |
| 3757 | |
| 3758 // Convert a double to an int. Java semantics require we do complex | |
| 3759 // manglelations in the corner cases. So we set the rounding mode to | |
| 3760 // 'zero', store the darned double down as an int, and reset the | |
| 3761 // rounding mode to 'nearest'. The hardware throws an exception which | |
| 3762 // patches up the correct value directly to the stack. | |
| 3763 enc_class D2I_encoding( regD src ) %{ | |
| 3764 // Flip to round-to-zero mode. We attempted to allow invalid-op | |
| 3765 // exceptions here, so that a NAN or other corner-case value will | |
| 3766 // thrown an exception (but normal values get converted at full speed). | |
| 3767 // However, I2C adapters and other float-stack manglers leave pending | |
| 3768 // invalid-op exceptions hanging. We would have to clear them before | |
| 3769 // enabling them and that is more expensive than just testing for the | |
| 3770 // invalid value Intel stores down in the corner cases. | |
| 3771 emit_opcode(cbuf,0xD9); // FLDCW trunc | |
| 3772 emit_opcode(cbuf,0x2D); | |
| 3773 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); | |
| 3774 // Allocate a word | |
| 3775 emit_opcode(cbuf,0x83); // SUB ESP,4 | |
| 3776 emit_opcode(cbuf,0xEC); | |
| 3777 emit_d8(cbuf,0x04); | |
| 3778 // Encoding assumes a double has been pushed into FPR0. | |
| 3779 // Store down the double as an int, popping the FPU stack | |
| 3780 emit_opcode(cbuf,0xDB); // FISTP [ESP] | |
| 3781 emit_opcode(cbuf,0x1C); | |
| 3782 emit_d8(cbuf,0x24); | |
| 3783 // Restore the rounding mode; mask the exception | |
| 3784 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode | |
| 3785 emit_opcode(cbuf,0x2D); | |
| 3786 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() | |
| 3787 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() | |
| 3788 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); | |
| 3789 | |
| 3790 // Load the converted int; adjust CPU stack | |
| 3791 emit_opcode(cbuf,0x58); // POP EAX | |
| 3792 emit_opcode(cbuf,0x3D); // CMP EAX,imm | |
| 3793 emit_d32 (cbuf,0x80000000); // 0x80000000 | |
| 3794 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 3795 emit_d8 (cbuf,0x07); // Size of slow_call | |
| 3796 // Push src onto stack slow-path | |
| 3797 emit_opcode(cbuf,0xD9 ); // FLD ST(i) | |
| 3798 emit_d8 (cbuf,0xC0-1+$src$$reg ); | |
| 3799 // CALL directly to the runtime | |
| 1748 | 3800 cbuf.set_insts_mark(); |
| 0 | 3801 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 3802 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 3803 // Carry on here... |
| 3804 %} | |
| 3805 | |
| 3806 enc_class D2L_encoding( regD src ) %{ | |
| 3807 emit_opcode(cbuf,0xD9); // FLDCW trunc | |
| 3808 emit_opcode(cbuf,0x2D); | |
| 3809 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); | |
| 3810 // Allocate a word | |
| 3811 emit_opcode(cbuf,0x83); // SUB ESP,8 | |
| 3812 emit_opcode(cbuf,0xEC); | |
| 3813 emit_d8(cbuf,0x08); | |
| 3814 // Encoding assumes a double has been pushed into FPR0. | |
| 3815 // Store down the double as a long, popping the FPU stack | |
| 3816 emit_opcode(cbuf,0xDF); // FISTP [ESP] | |
| 3817 emit_opcode(cbuf,0x3C); | |
| 3818 emit_d8(cbuf,0x24); | |
| 3819 // Restore the rounding mode; mask the exception | |
| 3820 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode | |
| 3821 emit_opcode(cbuf,0x2D); | |
| 3822 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() | |
| 3823 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() | |
| 3824 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); | |
| 3825 | |
| 3826 // Load the converted int; adjust CPU stack | |
| 3827 emit_opcode(cbuf,0x58); // POP EAX | |
| 3828 emit_opcode(cbuf,0x5A); // POP EDX | |
| 3829 emit_opcode(cbuf,0x81); // CMP EDX,imm | |
| 3830 emit_d8 (cbuf,0xFA); // rdx | |
| 3831 emit_d32 (cbuf,0x80000000); // 0x80000000 | |
| 3832 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 3833 emit_d8 (cbuf,0x07+4); // Size of slow_call | |
| 3834 emit_opcode(cbuf,0x85); // TEST EAX,EAX | |
| 3835 emit_opcode(cbuf,0xC0); // 2/rax,/rax, | |
| 3836 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 3837 emit_d8 (cbuf,0x07); // Size of slow_call | |
| 3838 // Push src onto stack slow-path | |
| 3839 emit_opcode(cbuf,0xD9 ); // FLD ST(i) | |
| 3840 emit_d8 (cbuf,0xC0-1+$src$$reg ); | |
| 3841 // CALL directly to the runtime | |
| 1748 | 3842 cbuf.set_insts_mark(); |
| 0 | 3843 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 3844 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 3845 // Carry on here... |
| 3846 %} | |
| 3847 | |
| 3848 enc_class X2L_encoding( regX src ) %{ | |
| 3849 // Allocate a word | |
| 3850 emit_opcode(cbuf,0x83); // SUB ESP,8 | |
| 3851 emit_opcode(cbuf,0xEC); | |
| 3852 emit_d8(cbuf,0x08); | |
| 3853 | |
| 3854 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src | |
| 3855 emit_opcode (cbuf, 0x0F ); | |
| 3856 emit_opcode (cbuf, 0x11 ); | |
| 3857 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 3858 | |
| 3859 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP] | |
| 3860 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 3861 | |
| 3862 emit_opcode(cbuf,0xD9); // FLDCW trunc | |
| 3863 emit_opcode(cbuf,0x2D); | |
| 3864 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); | |
| 3865 | |
| 3866 // Encoding assumes a double has been pushed into FPR0. | |
| 3867 // Store down the double as a long, popping the FPU stack | |
| 3868 emit_opcode(cbuf,0xDF); // FISTP [ESP] | |
| 3869 emit_opcode(cbuf,0x3C); | |
| 3870 emit_d8(cbuf,0x24); | |
| 3871 | |
| 3872 // Restore the rounding mode; mask the exception | |
| 3873 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode | |
| 3874 emit_opcode(cbuf,0x2D); | |
| 3875 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() | |
| 3876 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() | |
| 3877 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); | |
| 3878 | |
| 3879 // Load the converted int; adjust CPU stack | |
| 3880 emit_opcode(cbuf,0x58); // POP EAX | |
| 3881 | |
| 3882 emit_opcode(cbuf,0x5A); // POP EDX | |
| 3883 | |
| 3884 emit_opcode(cbuf,0x81); // CMP EDX,imm | |
| 3885 emit_d8 (cbuf,0xFA); // rdx | |
| 3886 emit_d32 (cbuf,0x80000000);// 0x80000000 | |
| 3887 | |
| 3888 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 3889 emit_d8 (cbuf,0x13+4); // Size of slow_call | |
| 3890 | |
| 3891 emit_opcode(cbuf,0x85); // TEST EAX,EAX | |
| 3892 emit_opcode(cbuf,0xC0); // 2/rax,/rax, | |
| 3893 | |
| 3894 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 3895 emit_d8 (cbuf,0x13); // Size of slow_call | |
| 3896 | |
| 3897 // Allocate a word | |
| 3898 emit_opcode(cbuf,0x83); // SUB ESP,4 | |
| 3899 emit_opcode(cbuf,0xEC); | |
| 3900 emit_d8(cbuf,0x04); | |
| 3901 | |
| 3902 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src | |
| 3903 emit_opcode (cbuf, 0x0F ); | |
| 3904 emit_opcode (cbuf, 0x11 ); | |
| 3905 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 3906 | |
| 3907 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP] | |
| 3908 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 3909 | |
| 3910 emit_opcode(cbuf,0x83); // ADD ESP,4 | |
| 3911 emit_opcode(cbuf,0xC4); | |
| 3912 emit_d8(cbuf,0x04); | |
| 3913 | |
| 3914 // CALL directly to the runtime | |
| 1748 | 3915 cbuf.set_insts_mark(); |
| 0 | 3916 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 3917 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 3918 // Carry on here... |
| 3919 %} | |
| 3920 | |
| 3921 enc_class XD2L_encoding( regXD src ) %{ | |
| 3922 // Allocate a word | |
| 3923 emit_opcode(cbuf,0x83); // SUB ESP,8 | |
| 3924 emit_opcode(cbuf,0xEC); | |
| 3925 emit_d8(cbuf,0x08); | |
| 3926 | |
| 3927 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src | |
| 3928 emit_opcode (cbuf, 0x0F ); | |
| 3929 emit_opcode (cbuf, 0x11 ); | |
| 3930 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 3931 | |
| 3932 emit_opcode(cbuf,0xDD ); // FLD_D [ESP] | |
| 3933 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 3934 | |
| 3935 emit_opcode(cbuf,0xD9); // FLDCW trunc | |
| 3936 emit_opcode(cbuf,0x2D); | |
| 3937 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); | |
| 3938 | |
| 3939 // Encoding assumes a double has been pushed into FPR0. | |
| 3940 // Store down the double as a long, popping the FPU stack | |
| 3941 emit_opcode(cbuf,0xDF); // FISTP [ESP] | |
| 3942 emit_opcode(cbuf,0x3C); | |
| 3943 emit_d8(cbuf,0x24); | |
| 3944 | |
| 3945 // Restore the rounding mode; mask the exception | |
| 3946 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode | |
| 3947 emit_opcode(cbuf,0x2D); | |
| 3948 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() | |
| 3949 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() | |
| 3950 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); | |
| 3951 | |
| 3952 // Load the converted int; adjust CPU stack | |
| 3953 emit_opcode(cbuf,0x58); // POP EAX | |
| 3954 | |
| 3955 emit_opcode(cbuf,0x5A); // POP EDX | |
| 3956 | |
| 3957 emit_opcode(cbuf,0x81); // CMP EDX,imm | |
| 3958 emit_d8 (cbuf,0xFA); // rdx | |
| 3959 emit_d32 (cbuf,0x80000000); // 0x80000000 | |
| 3960 | |
| 3961 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 3962 emit_d8 (cbuf,0x13+4); // Size of slow_call | |
| 3963 | |
| 3964 emit_opcode(cbuf,0x85); // TEST EAX,EAX | |
| 3965 emit_opcode(cbuf,0xC0); // 2/rax,/rax, | |
| 3966 | |
| 3967 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 3968 emit_d8 (cbuf,0x13); // Size of slow_call | |
| 3969 | |
| 3970 // Push src onto stack slow-path | |
| 3971 // Allocate a word | |
| 3972 emit_opcode(cbuf,0x83); // SUB ESP,8 | |
| 3973 emit_opcode(cbuf,0xEC); | |
| 3974 emit_d8(cbuf,0x08); | |
| 3975 | |
| 3976 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src | |
| 3977 emit_opcode (cbuf, 0x0F ); | |
| 3978 emit_opcode (cbuf, 0x11 ); | |
| 3979 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 3980 | |
| 3981 emit_opcode(cbuf,0xDD ); // FLD_D [ESP] | |
| 3982 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 3983 | |
| 3984 emit_opcode(cbuf,0x83); // ADD ESP,8 | |
| 3985 emit_opcode(cbuf,0xC4); | |
| 3986 emit_d8(cbuf,0x08); | |
| 3987 | |
| 3988 // CALL directly to the runtime | |
| 1748 | 3989 cbuf.set_insts_mark(); |
| 0 | 3990 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 3991 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 3992 // Carry on here... |
| 3993 %} | |
| 3994 | |
| 3995 enc_class D2X_encoding( regX dst, regD src ) %{ | |
| 3996 // Allocate a word | |
| 3997 emit_opcode(cbuf,0x83); // SUB ESP,4 | |
| 3998 emit_opcode(cbuf,0xEC); | |
| 3999 emit_d8(cbuf,0x04); | |
| 4000 int pop = 0x02; | |
| 4001 if ($src$$reg != FPR1L_enc) { | |
| 4002 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) | |
| 4003 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 4004 pop = 0x03; | |
| 4005 } | |
| 4006 store_to_stackslot( cbuf, 0xD9, pop, 0 ); // FST<P>_S [ESP] | |
| 4007 | |
| 4008 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP] | |
| 4009 emit_opcode (cbuf, 0x0F ); | |
| 4010 emit_opcode (cbuf, 0x10 ); | |
| 4011 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 4012 | |
| 4013 emit_opcode(cbuf,0x83); // ADD ESP,4 | |
| 4014 emit_opcode(cbuf,0xC4); | |
| 4015 emit_d8(cbuf,0x04); | |
| 4016 // Carry on here... | |
| 4017 %} | |
| 4018 | |
| 4019 enc_class FX2I_encoding( regX src, eRegI dst ) %{ | |
| 4020 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 4021 | |
| 4022 // Compare the result to see if we need to go to the slow path | |
| 4023 emit_opcode(cbuf,0x81); // CMP dst,imm | |
| 4024 emit_rm (cbuf,0x3,0x7,$dst$$reg); | |
| 4025 emit_d32 (cbuf,0x80000000); // 0x80000000 | |
| 4026 | |
| 4027 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 4028 emit_d8 (cbuf,0x13); // Size of slow_call | |
| 4029 // Store xmm to a temp memory | |
| 4030 // location and push it onto stack. | |
| 4031 | |
| 4032 emit_opcode(cbuf,0x83); // SUB ESP,4 | |
| 4033 emit_opcode(cbuf,0xEC); | |
| 4034 emit_d8(cbuf, $primary ? 0x8 : 0x4); | |
| 4035 | |
| 4036 emit_opcode (cbuf, $primary ? 0xF2 : 0xF3 ); // MOVSS [ESP], xmm | |
| 4037 emit_opcode (cbuf, 0x0F ); | |
| 4038 emit_opcode (cbuf, 0x11 ); | |
| 4039 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 4040 | |
| 4041 emit_opcode(cbuf, $primary ? 0xDD : 0xD9 ); // FLD [ESP] | |
| 4042 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 4043 | |
| 4044 emit_opcode(cbuf,0x83); // ADD ESP,4 | |
| 4045 emit_opcode(cbuf,0xC4); | |
| 4046 emit_d8(cbuf, $primary ? 0x8 : 0x4); | |
| 4047 | |
| 4048 // CALL directly to the runtime | |
| 1748 | 4049 cbuf.set_insts_mark(); |
| 0 | 4050 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 4051 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 4052 |
| 4053 // Carry on here... | |
| 4054 %} | |
| 4055 | |
| 4056 enc_class X2D_encoding( regD dst, regX src ) %{ | |
| 4057 // Allocate a word | |
| 4058 emit_opcode(cbuf,0x83); // SUB ESP,4 | |
| 4059 emit_opcode(cbuf,0xEC); | |
| 4060 emit_d8(cbuf,0x04); | |
| 4061 | |
| 4062 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], xmm | |
| 4063 emit_opcode (cbuf, 0x0F ); | |
| 4064 emit_opcode (cbuf, 0x11 ); | |
| 4065 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); | |
| 4066 | |
| 4067 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP] | |
| 4068 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); | |
| 4069 | |
| 4070 emit_opcode(cbuf,0x83); // ADD ESP,4 | |
| 4071 emit_opcode(cbuf,0xC4); | |
| 4072 emit_d8(cbuf,0x04); | |
| 4073 | |
| 4074 // Carry on here... | |
| 4075 %} | |
| 4076 | |
| 4077 enc_class AbsXF_encoding(regX dst) %{ | |
| 4078 address signmask_address=(address)float_signmask_pool; | |
| 4079 // andpd:\tANDPS $dst,[signconst] | |
| 4080 emit_opcode(cbuf, 0x0F); | |
| 4081 emit_opcode(cbuf, 0x54); | |
| 4082 emit_rm(cbuf, 0x0, $dst$$reg, 0x5); | |
| 4083 emit_d32(cbuf, (int)signmask_address); | |
| 4084 %} | |
| 4085 | |
| 4086 enc_class AbsXD_encoding(regXD dst) %{ | |
| 4087 address signmask_address=(address)double_signmask_pool; | |
| 4088 // andpd:\tANDPD $dst,[signconst] | |
| 4089 emit_opcode(cbuf, 0x66); | |
| 4090 emit_opcode(cbuf, 0x0F); | |
| 4091 emit_opcode(cbuf, 0x54); | |
| 4092 emit_rm(cbuf, 0x0, $dst$$reg, 0x5); | |
| 4093 emit_d32(cbuf, (int)signmask_address); | |
| 4094 %} | |
| 4095 | |
| 4096 enc_class NegXF_encoding(regX dst) %{ | |
| 4097 address signmask_address=(address)float_signflip_pool; | |
| 4098 // andpd:\tXORPS $dst,[signconst] | |
| 4099 emit_opcode(cbuf, 0x0F); | |
| 4100 emit_opcode(cbuf, 0x57); | |
| 4101 emit_rm(cbuf, 0x0, $dst$$reg, 0x5); | |
| 4102 emit_d32(cbuf, (int)signmask_address); | |
| 4103 %} | |
| 4104 | |
| 4105 enc_class NegXD_encoding(regXD dst) %{ | |
| 4106 address signmask_address=(address)double_signflip_pool; | |
| 4107 // andpd:\tXORPD $dst,[signconst] | |
| 4108 emit_opcode(cbuf, 0x66); | |
| 4109 emit_opcode(cbuf, 0x0F); | |
| 4110 emit_opcode(cbuf, 0x57); | |
| 4111 emit_rm(cbuf, 0x0, $dst$$reg, 0x5); | |
| 4112 emit_d32(cbuf, (int)signmask_address); | |
| 4113 %} | |
| 4114 | |
| 4115 enc_class FMul_ST_reg( eRegF src1 ) %{ | |
| 4116 // Operand was loaded from memory into fp ST (stack top) | |
| 4117 // FMUL ST,$src /* D8 C8+i */ | |
| 4118 emit_opcode(cbuf, 0xD8); | |
| 4119 emit_opcode(cbuf, 0xC8 + $src1$$reg); | |
| 4120 %} | |
| 4121 | |
| 4122 enc_class FAdd_ST_reg( eRegF src2 ) %{ | |
| 4123 // FADDP ST,src2 /* D8 C0+i */ | |
| 4124 emit_opcode(cbuf, 0xD8); | |
| 4125 emit_opcode(cbuf, 0xC0 + $src2$$reg); | |
| 4126 //could use FADDP src2,fpST /* DE C0+i */ | |
| 4127 %} | |
| 4128 | |
| 4129 enc_class FAddP_reg_ST( eRegF src2 ) %{ | |
| 4130 // FADDP src2,ST /* DE C0+i */ | |
| 4131 emit_opcode(cbuf, 0xDE); | |
| 4132 emit_opcode(cbuf, 0xC0 + $src2$$reg); | |
| 4133 %} | |
| 4134 | |
| 4135 enc_class subF_divF_encode( eRegF src1, eRegF src2) %{ | |
| 4136 // Operand has been loaded into fp ST (stack top) | |
| 4137 // FSUB ST,$src1 | |
| 4138 emit_opcode(cbuf, 0xD8); | |
| 4139 emit_opcode(cbuf, 0xE0 + $src1$$reg); | |
| 4140 | |
| 4141 // FDIV | |
| 4142 emit_opcode(cbuf, 0xD8); | |
| 4143 emit_opcode(cbuf, 0xF0 + $src2$$reg); | |
| 4144 %} | |
| 4145 | |
| 4146 enc_class MulFAddF (eRegF src1, eRegF src2) %{ | |
| 4147 // Operand was loaded from memory into fp ST (stack top) | |
| 4148 // FADD ST,$src /* D8 C0+i */ | |
| 4149 emit_opcode(cbuf, 0xD8); | |
| 4150 emit_opcode(cbuf, 0xC0 + $src1$$reg); | |
| 4151 | |
| 4152 // FMUL ST,src2 /* D8 C*+i */ | |
| 4153 emit_opcode(cbuf, 0xD8); | |
| 4154 emit_opcode(cbuf, 0xC8 + $src2$$reg); | |
| 4155 %} | |
| 4156 | |
| 4157 | |
| 4158 enc_class MulFAddFreverse (eRegF src1, eRegF src2) %{ | |
| 4159 // Operand was loaded from memory into fp ST (stack top) | |
| 4160 // FADD ST,$src /* D8 C0+i */ | |
| 4161 emit_opcode(cbuf, 0xD8); | |
| 4162 emit_opcode(cbuf, 0xC0 + $src1$$reg); | |
| 4163 | |
| 4164 // FMULP src2,ST /* DE C8+i */ | |
| 4165 emit_opcode(cbuf, 0xDE); | |
| 4166 emit_opcode(cbuf, 0xC8 + $src2$$reg); | |
| 4167 %} | |
| 4168 | |
| 4169 // Atomically load the volatile long | |
| 4170 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{ | |
| 4171 emit_opcode(cbuf,0xDF); | |
| 4172 int rm_byte_opcode = 0x05; | |
| 4173 int base = $mem$$base; | |
| 4174 int index = $mem$$index; | |
| 4175 int scale = $mem$$scale; | |
| 4176 int displace = $mem$$disp; | |
| 4177 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals | |
| 4178 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop); | |
| 4179 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp ); | |
| 4180 %} | |
| 4181 | |
| 4182 enc_class enc_loadLX_volatile( memory mem, stackSlotL dst, regXD tmp ) %{ | |
| 4183 { // Atomic long load | |
| 4184 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem | |
| 4185 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66); | |
| 4186 emit_opcode(cbuf,0x0F); | |
| 4187 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12); | |
| 4188 int base = $mem$$base; | |
| 4189 int index = $mem$$index; | |
| 4190 int scale = $mem$$scale; | |
| 4191 int displace = $mem$$disp; | |
| 4192 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals | |
| 4193 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop); | |
| 4194 } | |
| 4195 { // MOVSD $dst,$tmp ! atomic long store | |
| 4196 emit_opcode(cbuf,0xF2); | |
| 4197 emit_opcode(cbuf,0x0F); | |
| 4198 emit_opcode(cbuf,0x11); | |
| 4199 int base = $dst$$base; | |
| 4200 int index = $dst$$index; | |
| 4201 int scale = $dst$$scale; | |
| 4202 int displace = $dst$$disp; | |
| 4203 bool disp_is_oop = $dst->disp_is_oop(); // disp-as-oop when working with static globals | |
| 4204 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop); | |
| 4205 } | |
| 4206 %} | |
| 4207 | |
| 4208 enc_class enc_loadLX_reg_volatile( memory mem, eRegL dst, regXD tmp ) %{ | |
| 4209 { // Atomic long load | |
| 4210 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem | |
| 4211 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66); | |
| 4212 emit_opcode(cbuf,0x0F); | |
| 4213 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12); | |
| 4214 int base = $mem$$base; | |
| 4215 int index = $mem$$index; | |
| 4216 int scale = $mem$$scale; | |
| 4217 int displace = $mem$$disp; | |
| 4218 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals | |
| 4219 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop); | |
| 4220 } | |
| 4221 { // MOVD $dst.lo,$tmp | |
| 4222 emit_opcode(cbuf,0x66); | |
| 4223 emit_opcode(cbuf,0x0F); | |
| 4224 emit_opcode(cbuf,0x7E); | |
| 4225 emit_rm(cbuf, 0x3, $tmp$$reg, $dst$$reg); | |
| 4226 } | |
| 4227 { // PSRLQ $tmp,32 | |
| 4228 emit_opcode(cbuf,0x66); | |
| 4229 emit_opcode(cbuf,0x0F); | |
| 4230 emit_opcode(cbuf,0x73); | |
| 4231 emit_rm(cbuf, 0x3, 0x02, $tmp$$reg); | |
| 4232 emit_d8(cbuf, 0x20); | |
| 4233 } | |
| 4234 { // MOVD $dst.hi,$tmp | |
| 4235 emit_opcode(cbuf,0x66); | |
| 4236 emit_opcode(cbuf,0x0F); | |
| 4237 emit_opcode(cbuf,0x7E); | |
| 4238 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg)); | |
| 4239 } | |
| 4240 %} | |
| 4241 | |
| 4242 // Volatile Store Long. Must be atomic, so move it into | |
| 4243 // the FP TOS and then do a 64-bit FIST. Has to probe the | |
| 4244 // target address before the store (for null-ptr checks) | |
| 4245 // so the memory operand is used twice in the encoding. | |
| 4246 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{ | |
| 4247 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp ); | |
| 1748 | 4248 cbuf.set_insts_mark(); // Mark start of FIST in case $mem has an oop |
| 0 | 4249 emit_opcode(cbuf,0xDF); |
| 4250 int rm_byte_opcode = 0x07; | |
| 4251 int base = $mem$$base; | |
| 4252 int index = $mem$$index; | |
| 4253 int scale = $mem$$scale; | |
| 4254 int displace = $mem$$disp; | |
| 4255 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals | |
| 4256 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop); | |
| 4257 %} | |
| 4258 | |
| 4259 enc_class enc_storeLX_volatile( memory mem, stackSlotL src, regXD tmp) %{ | |
| 4260 { // Atomic long load | |
| 4261 // UseXmmLoadAndClearUpper ? movsd $tmp,[$src] : movlpd $tmp,[$src] | |
| 4262 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66); | |
| 4263 emit_opcode(cbuf,0x0F); | |
| 4264 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12); | |
| 4265 int base = $src$$base; | |
| 4266 int index = $src$$index; | |
| 4267 int scale = $src$$scale; | |
| 4268 int displace = $src$$disp; | |
| 4269 bool disp_is_oop = $src->disp_is_oop(); // disp-as-oop when working with static globals | |
| 4270 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop); | |
| 4271 } | |
| 1748 | 4272 cbuf.set_insts_mark(); // Mark start of MOVSD in case $mem has an oop |
| 0 | 4273 { // MOVSD $mem,$tmp ! atomic long store |
| 4274 emit_opcode(cbuf,0xF2); | |
| 4275 emit_opcode(cbuf,0x0F); | |
| 4276 emit_opcode(cbuf,0x11); | |
| 4277 int base = $mem$$base; | |
| 4278 int index = $mem$$index; | |
| 4279 int scale = $mem$$scale; | |
| 4280 int displace = $mem$$disp; | |
| 4281 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals | |
| 4282 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop); | |
| 4283 } | |
| 4284 %} | |
| 4285 | |
| 4286 enc_class enc_storeLX_reg_volatile( memory mem, eRegL src, regXD tmp, regXD tmp2) %{ | |
| 4287 { // MOVD $tmp,$src.lo | |
| 4288 emit_opcode(cbuf,0x66); | |
| 4289 emit_opcode(cbuf,0x0F); | |
| 4290 emit_opcode(cbuf,0x6E); | |
| 4291 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg); | |
| 4292 } | |
| 4293 { // MOVD $tmp2,$src.hi | |
| 4294 emit_opcode(cbuf,0x66); | |
| 4295 emit_opcode(cbuf,0x0F); | |
| 4296 emit_opcode(cbuf,0x6E); | |
| 4297 emit_rm(cbuf, 0x3, $tmp2$$reg, HIGH_FROM_LOW($src$$reg)); | |
| 4298 } | |
| 4299 { // PUNPCKLDQ $tmp,$tmp2 | |
| 4300 emit_opcode(cbuf,0x66); | |
| 4301 emit_opcode(cbuf,0x0F); | |
| 4302 emit_opcode(cbuf,0x62); | |
| 4303 emit_rm(cbuf, 0x3, $tmp$$reg, $tmp2$$reg); | |
| 4304 } | |
| 1748 | 4305 cbuf.set_insts_mark(); // Mark start of MOVSD in case $mem has an oop |
| 0 | 4306 { // MOVSD $mem,$tmp ! atomic long store |
| 4307 emit_opcode(cbuf,0xF2); | |
| 4308 emit_opcode(cbuf,0x0F); | |
| 4309 emit_opcode(cbuf,0x11); | |
| 4310 int base = $mem$$base; | |
| 4311 int index = $mem$$index; | |
| 4312 int scale = $mem$$scale; | |
| 4313 int displace = $mem$$disp; | |
| 4314 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals | |
| 4315 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop); | |
| 4316 } | |
| 4317 %} | |
| 4318 | |
| 4319 // Safepoint Poll. This polls the safepoint page, and causes an | |
| 4320 // exception if it is not readable. Unfortunately, it kills the condition code | |
| 4321 // in the process | |
| 4322 // We current use TESTL [spp],EDI | |
| 4323 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0 | |
| 4324 | |
| 4325 enc_class Safepoint_Poll() %{ | |
| 1748 | 4326 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0); |
| 0 | 4327 emit_opcode(cbuf,0x85); |
| 4328 emit_rm (cbuf, 0x0, 0x7, 0x5); | |
| 4329 emit_d32(cbuf, (intptr_t)os::get_polling_page()); | |
| 4330 %} | |
| 4331 %} | |
| 4332 | |
| 4333 | |
| 4334 //----------FRAME-------------------------------------------------------------- | |
| 4335 // Definition of frame structure and management information. | |
| 4336 // | |
| 4337 // S T A C K L A Y O U T Allocators stack-slot number | |
| 4338 // | (to get allocators register number | |
| 4339 // G Owned by | | v add OptoReg::stack0()) | |
| 4340 // r CALLER | | | |
| 4341 // o | +--------+ pad to even-align allocators stack-slot | |
| 4342 // w V | pad0 | numbers; owned by CALLER | |
| 4343 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned | |
| 4344 // h ^ | in | 5 | |
| 4345 // | | args | 4 Holes in incoming args owned by SELF | |
| 4346 // | | | | 3 | |
| 4347 // | | +--------+ | |
| 4348 // V | | old out| Empty on Intel, window on Sparc | |
| 4349 // | old |preserve| Must be even aligned. | |
| 4350 // | SP-+--------+----> Matcher::_old_SP, even aligned | |
| 4351 // | | in | 3 area for Intel ret address | |
| 4352 // Owned by |preserve| Empty on Sparc. | |
| 4353 // SELF +--------+ | |
| 4354 // | | pad2 | 2 pad to align old SP | |
| 4355 // | +--------+ 1 | |
| 4356 // | | locks | 0 | |
| 4357 // | +--------+----> OptoReg::stack0(), even aligned | |
| 4358 // | | pad1 | 11 pad to align new SP | |
| 4359 // | +--------+ | |
| 4360 // | | | 10 | |
| 4361 // | | spills | 9 spills | |
| 4362 // V | | 8 (pad0 slot for callee) | |
| 4363 // -----------+--------+----> Matcher::_out_arg_limit, unaligned | |
| 4364 // ^ | out | 7 | |
| 4365 // | | args | 6 Holes in outgoing args owned by CALLEE | |
| 4366 // Owned by +--------+ | |
| 4367 // CALLEE | new out| 6 Empty on Intel, window on Sparc | |
| 4368 // | new |preserve| Must be even-aligned. | |
| 4369 // | SP-+--------+----> Matcher::_new_SP, even aligned | |
| 4370 // | | | | |
| 4371 // | |
| 4372 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is | |
| 4373 // known from SELF's arguments and the Java calling convention. | |
| 4374 // Region 6-7 is determined per call site. | |
| 4375 // Note 2: If the calling convention leaves holes in the incoming argument | |
| 4376 // area, those holes are owned by SELF. Holes in the outgoing area | |
| 4377 // are owned by the CALLEE. Holes should not be nessecary in the | |
| 4378 // incoming area, as the Java calling convention is completely under | |
| 4379 // the control of the AD file. Doubles can be sorted and packed to | |
| 4380 // avoid holes. Holes in the outgoing arguments may be nessecary for | |
| 4381 // varargs C calling conventions. | |
| 4382 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is | |
| 4383 // even aligned with pad0 as needed. | |
| 4384 // Region 6 is even aligned. Region 6-7 is NOT even aligned; | |
| 4385 // region 6-11 is even aligned; it may be padded out more so that | |
| 4386 // the region from SP to FP meets the minimum stack alignment. | |
| 4387 | |
| 4388 frame %{ | |
| 4389 // What direction does stack grow in (assumed to be same for C & Java) | |
| 4390 stack_direction(TOWARDS_LOW); | |
| 4391 | |
| 4392 // These three registers define part of the calling convention | |
| 4393 // between compiled code and the interpreter. | |
| 4394 inline_cache_reg(EAX); // Inline Cache Register | |
| 4395 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter | |
| 4396 | |
| 4397 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] | |
| 4398 cisc_spilling_operand_name(indOffset32); | |
| 4399 | |
| 4400 // Number of stack slots consumed by locking an object | |
| 4401 sync_stack_slots(1); | |
| 4402 | |
| 4403 // Compiled code's Frame Pointer | |
| 4404 frame_pointer(ESP); | |
| 4405 // Interpreter stores its frame pointer in a register which is | |
| 4406 // stored to the stack by I2CAdaptors. | |
| 4407 // I2CAdaptors convert from interpreted java to compiled java. | |
| 4408 interpreter_frame_pointer(EBP); | |
| 4409 | |
| 4410 // Stack alignment requirement | |
| 4411 // Alignment size in bytes (128-bit -> 16 bytes) | |
| 4412 stack_alignment(StackAlignmentInBytes); | |
| 4413 | |
| 4414 // Number of stack slots between incoming argument block and the start of | |
| 4415 // a new frame. The PROLOG must add this many slots to the stack. The | |
| 4416 // EPILOG must remove this many slots. Intel needs one slot for | |
| 4417 // return address and one for rbp, (must save rbp) | |
| 4418 in_preserve_stack_slots(2+VerifyStackAtCalls); | |
| 4419 | |
| 4420 // Number of outgoing stack slots killed above the out_preserve_stack_slots | |
| 4421 // for calls to C. Supports the var-args backing area for register parms. | |
| 4422 varargs_C_out_slots_killed(0); | |
| 4423 | |
| 4424 // The after-PROLOG location of the return address. Location of | |
| 4425 // return address specifies a type (REG or STACK) and a number | |
| 4426 // representing the register number (i.e. - use a register name) or | |
| 4427 // stack slot. | |
| 4428 // Ret Addr is on stack in slot 0 if no locks or verification or alignment. | |
| 4429 // Otherwise, it is above the locks and verification slot and alignment word | |
| 4430 return_addr(STACK - 1 + | |
| 4431 round_to(1+VerifyStackAtCalls+ | |
| 4432 Compile::current()->fixed_slots(), | |
| 4433 (StackAlignmentInBytes/wordSize))); | |
| 4434 | |
| 4435 // Body of function which returns an integer array locating | |
| 4436 // arguments either in registers or in stack slots. Passed an array | |
| 4437 // of ideal registers called "sig" and a "length" count. Stack-slot | |
| 4438 // offsets are based on outgoing arguments, i.e. a CALLER setting up | |
| 4439 // arguments for a CALLEE. Incoming stack arguments are | |
| 4440 // automatically biased by the preserve_stack_slots field above. | |
| 4441 calling_convention %{ | |
| 4442 // No difference between ingoing/outgoing just pass false | |
| 4443 SharedRuntime::java_calling_convention(sig_bt, regs, length, false); | |
| 4444 %} | |
| 4445 | |
| 4446 | |
| 4447 // Body of function which returns an integer array locating | |
| 4448 // arguments either in registers or in stack slots. Passed an array | |
| 4449 // of ideal registers called "sig" and a "length" count. Stack-slot | |
| 4450 // offsets are based on outgoing arguments, i.e. a CALLER setting up | |
| 4451 // arguments for a CALLEE. Incoming stack arguments are | |
| 4452 // automatically biased by the preserve_stack_slots field above. | |
| 4453 c_calling_convention %{ | |
| 4454 // This is obviously always outgoing | |
| 4455 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); | |
| 4456 %} | |
| 4457 | |
| 4458 // Location of C & interpreter return values | |
| 4459 c_return_value %{ | |
| 4460 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
|
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4461 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num }; |
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4462 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num }; |
| 0 | 4463 |
| 4464 // in SSE2+ mode we want to keep the FPU stack clean so pretend | |
| 4465 // that C functions return float and double results in XMM0. | |
| 4466 if( ideal_reg == Op_RegD && UseSSE>=2 ) | |
| 4467 return OptoRegPair(XMM0b_num,XMM0a_num); | |
| 4468 if( ideal_reg == Op_RegF && UseSSE>=2 ) | |
| 4469 return OptoRegPair(OptoReg::Bad,XMM0a_num); | |
| 4470 | |
| 4471 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]); | |
| 4472 %} | |
| 4473 | |
| 4474 // Location of return values | |
| 4475 return_value %{ | |
| 4476 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
|
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4477 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num }; |
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|
4478 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num }; |
| 0 | 4479 if( ideal_reg == Op_RegD && UseSSE>=2 ) |
| 4480 return OptoRegPair(XMM0b_num,XMM0a_num); | |
| 4481 if( ideal_reg == Op_RegF && UseSSE>=1 ) | |
| 4482 return OptoRegPair(OptoReg::Bad,XMM0a_num); | |
| 4483 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]); | |
| 4484 %} | |
| 4485 | |
| 4486 %} | |
| 4487 | |
| 4488 //----------ATTRIBUTES--------------------------------------------------------- | |
| 4489 //----------Operand Attributes------------------------------------------------- | |
| 4490 op_attrib op_cost(0); // Required cost attribute | |
| 4491 | |
| 4492 //----------Instruction Attributes--------------------------------------------- | |
| 4493 ins_attrib ins_cost(100); // Required cost attribute | |
| 4494 ins_attrib ins_size(8); // Required size attribute (in bits) | |
| 4495 ins_attrib ins_pc_relative(0); // Required PC Relative flag | |
| 4496 ins_attrib ins_short_branch(0); // Required flag: is this instruction a | |
| 4497 // non-matching short branch variant of some | |
| 4498 // long branch? | |
| 4499 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2) | |
| 4500 // specifies the alignment that some part of the instruction (not | |
| 4501 // necessarily the start) requires. If > 1, a compute_padding() | |
| 4502 // function must be provided for the instruction | |
| 4503 | |
| 4504 //----------OPERANDS----------------------------------------------------------- | |
| 4505 // Operand definitions must precede instruction definitions for correct parsing | |
| 4506 // in the ADLC because operands constitute user defined types which are used in | |
| 4507 // instruction definitions. | |
| 4508 | |
| 4509 //----------Simple Operands---------------------------------------------------- | |
| 4510 // Immediate Operands | |
| 4511 // Integer Immediate | |
| 4512 operand immI() %{ | |
| 4513 match(ConI); | |
| 4514 | |
| 4515 op_cost(10); | |
| 4516 format %{ %} | |
| 4517 interface(CONST_INTER); | |
| 4518 %} | |
| 4519 | |
| 4520 // Constant for test vs zero | |
| 4521 operand immI0() %{ | |
| 4522 predicate(n->get_int() == 0); | |
| 4523 match(ConI); | |
| 4524 | |
| 4525 op_cost(0); | |
| 4526 format %{ %} | |
| 4527 interface(CONST_INTER); | |
| 4528 %} | |
| 4529 | |
| 4530 // Constant for increment | |
| 4531 operand immI1() %{ | |
| 4532 predicate(n->get_int() == 1); | |
| 4533 match(ConI); | |
| 4534 | |
| 4535 op_cost(0); | |
| 4536 format %{ %} | |
| 4537 interface(CONST_INTER); | |
| 4538 %} | |
| 4539 | |
| 4540 // Constant for decrement | |
| 4541 operand immI_M1() %{ | |
| 4542 predicate(n->get_int() == -1); | |
| 4543 match(ConI); | |
| 4544 | |
| 4545 op_cost(0); | |
| 4546 format %{ %} | |
| 4547 interface(CONST_INTER); | |
| 4548 %} | |
| 4549 | |
| 4550 // Valid scale values for addressing modes | |
| 4551 operand immI2() %{ | |
| 4552 predicate(0 <= n->get_int() && (n->get_int() <= 3)); | |
| 4553 match(ConI); | |
| 4554 | |
| 4555 format %{ %} | |
| 4556 interface(CONST_INTER); | |
| 4557 %} | |
| 4558 | |
| 4559 operand immI8() %{ | |
| 4560 predicate((-128 <= n->get_int()) && (n->get_int() <= 127)); | |
| 4561 match(ConI); | |
| 4562 | |
| 4563 op_cost(5); | |
| 4564 format %{ %} | |
| 4565 interface(CONST_INTER); | |
| 4566 %} | |
| 4567 | |
| 4568 operand immI16() %{ | |
| 4569 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767)); | |
| 4570 match(ConI); | |
| 4571 | |
| 4572 op_cost(10); | |
| 4573 format %{ %} | |
| 4574 interface(CONST_INTER); | |
| 4575 %} | |
| 4576 | |
| 4577 // Constant for long shifts | |
| 4578 operand immI_32() %{ | |
| 4579 predicate( n->get_int() == 32 ); | |
| 4580 match(ConI); | |
| 4581 | |
| 4582 op_cost(0); | |
| 4583 format %{ %} | |
| 4584 interface(CONST_INTER); | |
| 4585 %} | |
| 4586 | |
| 4587 operand immI_1_31() %{ | |
| 4588 predicate( n->get_int() >= 1 && n->get_int() <= 31 ); | |
| 4589 match(ConI); | |
| 4590 | |
| 4591 op_cost(0); | |
| 4592 format %{ %} | |
| 4593 interface(CONST_INTER); | |
| 4594 %} | |
| 4595 | |
| 4596 operand immI_32_63() %{ | |
| 4597 predicate( n->get_int() >= 32 && n->get_int() <= 63 ); | |
| 4598 match(ConI); | |
| 4599 op_cost(0); | |
| 4600 | |
| 4601 format %{ %} | |
| 4602 interface(CONST_INTER); | |
| 4603 %} | |
| 4604 | |
| 219 | 4605 operand immI_1() %{ |
| 4606 predicate( n->get_int() == 1 ); | |
| 4607 match(ConI); | |
| 4608 | |
| 4609 op_cost(0); | |
| 4610 format %{ %} | |
| 4611 interface(CONST_INTER); | |
| 4612 %} | |
| 4613 | |
| 4614 operand immI_2() %{ | |
| 4615 predicate( n->get_int() == 2 ); | |
| 4616 match(ConI); | |
| 4617 | |
| 4618 op_cost(0); | |
| 4619 format %{ %} | |
| 4620 interface(CONST_INTER); | |
| 4621 %} | |
| 4622 | |
| 4623 operand immI_3() %{ | |
| 4624 predicate( n->get_int() == 3 ); | |
| 4625 match(ConI); | |
| 4626 | |
| 4627 op_cost(0); | |
| 4628 format %{ %} | |
| 4629 interface(CONST_INTER); | |
| 4630 %} | |
| 4631 | |
| 0 | 4632 // Pointer Immediate |
| 4633 operand immP() %{ | |
| 4634 match(ConP); | |
| 4635 | |
| 4636 op_cost(10); | |
| 4637 format %{ %} | |
| 4638 interface(CONST_INTER); | |
| 4639 %} | |
| 4640 | |
| 4641 // NULL Pointer Immediate | |
| 4642 operand immP0() %{ | |
| 4643 predicate( n->get_ptr() == 0 ); | |
| 4644 match(ConP); | |
| 4645 op_cost(0); | |
| 4646 | |
| 4647 format %{ %} | |
| 4648 interface(CONST_INTER); | |
| 4649 %} | |
| 4650 | |
| 4651 // Long Immediate | |
| 4652 operand immL() %{ | |
| 4653 match(ConL); | |
| 4654 | |
| 4655 op_cost(20); | |
| 4656 format %{ %} | |
| 4657 interface(CONST_INTER); | |
| 4658 %} | |
| 4659 | |
| 4660 // Long Immediate zero | |
| 4661 operand immL0() %{ | |
| 4662 predicate( n->get_long() == 0L ); | |
| 4663 match(ConL); | |
| 4664 op_cost(0); | |
| 4665 | |
| 4666 format %{ %} | |
| 4667 interface(CONST_INTER); | |
| 4668 %} | |
| 4669 | |
| 403 | 4670 // Long Immediate zero |
| 4671 operand immL_M1() %{ | |
| 4672 predicate( n->get_long() == -1L ); | |
| 4673 match(ConL); | |
| 4674 op_cost(0); | |
| 4675 | |
| 4676 format %{ %} | |
| 4677 interface(CONST_INTER); | |
| 4678 %} | |
| 4679 | |
| 0 | 4680 // Long immediate from 0 to 127. |
| 4681 // Used for a shorter form of long mul by 10. | |
| 4682 operand immL_127() %{ | |
| 4683 predicate((0 <= n->get_long()) && (n->get_long() <= 127)); | |
| 4684 match(ConL); | |
| 4685 op_cost(0); | |
| 4686 | |
| 4687 format %{ %} | |
| 4688 interface(CONST_INTER); | |
| 4689 %} | |
| 4690 | |
| 4691 // Long Immediate: low 32-bit mask | |
| 4692 operand immL_32bits() %{ | |
| 4693 predicate(n->get_long() == 0xFFFFFFFFL); | |
| 4694 match(ConL); | |
| 4695 op_cost(0); | |
| 4696 | |
| 4697 format %{ %} | |
| 4698 interface(CONST_INTER); | |
| 4699 %} | |
| 4700 | |
| 4701 // Long Immediate: low 32-bit mask | |
| 4702 operand immL32() %{ | |
| 4703 predicate(n->get_long() == (int)(n->get_long())); | |
| 4704 match(ConL); | |
| 4705 op_cost(20); | |
| 4706 | |
| 4707 format %{ %} | |
| 4708 interface(CONST_INTER); | |
| 4709 %} | |
| 4710 | |
| 4711 //Double Immediate zero | |
| 4712 operand immD0() %{ | |
| 4713 // Do additional (and counter-intuitive) test against NaN to work around VC++ | |
| 4714 // bug that generates code such that NaNs compare equal to 0.0 | |
| 4715 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) ); | |
| 4716 match(ConD); | |
| 4717 | |
| 4718 op_cost(5); | |
| 4719 format %{ %} | |
| 4720 interface(CONST_INTER); | |
| 4721 %} | |
| 4722 | |
| 2008 | 4723 // Double Immediate one |
| 0 | 4724 operand immD1() %{ |
| 4725 predicate( UseSSE<=1 && n->getd() == 1.0 ); | |
| 4726 match(ConD); | |
| 4727 | |
| 4728 op_cost(5); | |
| 4729 format %{ %} | |
| 4730 interface(CONST_INTER); | |
| 4731 %} | |
| 4732 | |
| 4733 // Double Immediate | |
| 4734 operand immD() %{ | |
| 4735 predicate(UseSSE<=1); | |
| 4736 match(ConD); | |
| 4737 | |
| 4738 op_cost(5); | |
| 4739 format %{ %} | |
| 4740 interface(CONST_INTER); | |
| 4741 %} | |
| 4742 | |
| 4743 operand immXD() %{ | |
| 4744 predicate(UseSSE>=2); | |
| 4745 match(ConD); | |
| 4746 | |
| 4747 op_cost(5); | |
| 4748 format %{ %} | |
| 4749 interface(CONST_INTER); | |
| 4750 %} | |
| 4751 | |
| 4752 // Double Immediate zero | |
| 4753 operand immXD0() %{ | |
| 4754 // Do additional (and counter-intuitive) test against NaN to work around VC++ | |
| 4755 // bug that generates code such that NaNs compare equal to 0.0 AND do not | |
| 4756 // compare equal to -0.0. | |
| 4757 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 ); | |
| 4758 match(ConD); | |
| 4759 | |
| 4760 format %{ %} | |
| 4761 interface(CONST_INTER); | |
| 4762 %} | |
| 4763 | |
| 4764 // Float Immediate zero | |
| 4765 operand immF0() %{ | |
| 2008 | 4766 predicate(UseSSE == 0 && n->getf() == 0.0F); |
| 4767 match(ConF); | |
| 4768 | |
| 4769 op_cost(5); | |
| 4770 format %{ %} | |
| 4771 interface(CONST_INTER); | |
| 4772 %} | |
| 4773 | |
| 4774 // Float Immediate one | |
| 4775 operand immF1() %{ | |
| 4776 predicate(UseSSE == 0 && n->getf() == 1.0F); | |
| 0 | 4777 match(ConF); |
| 4778 | |
| 4779 op_cost(5); | |
| 4780 format %{ %} | |
| 4781 interface(CONST_INTER); | |
| 4782 %} | |
| 4783 | |
| 4784 // Float Immediate | |
| 4785 operand immF() %{ | |
| 4786 predicate( UseSSE == 0 ); | |
| 4787 match(ConF); | |
| 4788 | |
| 4789 op_cost(5); | |
| 4790 format %{ %} | |
| 4791 interface(CONST_INTER); | |
| 4792 %} | |
| 4793 | |
| 4794 // Float Immediate | |
| 4795 operand immXF() %{ | |
| 4796 predicate(UseSSE >= 1); | |
| 4797 match(ConF); | |
| 4798 | |
| 4799 op_cost(5); | |
| 4800 format %{ %} | |
| 4801 interface(CONST_INTER); | |
| 4802 %} | |
| 4803 | |
| 4804 // Float Immediate zero. Zero and not -0.0 | |
| 4805 operand immXF0() %{ | |
| 4806 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 ); | |
| 4807 match(ConF); | |
| 4808 | |
| 4809 op_cost(5); | |
| 4810 format %{ %} | |
| 4811 interface(CONST_INTER); | |
| 4812 %} | |
| 4813 | |
| 4814 // Immediates for special shifts (sign extend) | |
| 4815 | |
| 4816 // Constants for increment | |
| 4817 operand immI_16() %{ | |
| 4818 predicate( n->get_int() == 16 ); | |
| 4819 match(ConI); | |
| 4820 | |
| 4821 format %{ %} | |
| 4822 interface(CONST_INTER); | |
| 4823 %} | |
| 4824 | |
| 4825 operand immI_24() %{ | |
| 4826 predicate( n->get_int() == 24 ); | |
| 4827 match(ConI); | |
| 4828 | |
| 4829 format %{ %} | |
| 4830 interface(CONST_INTER); | |
| 4831 %} | |
| 4832 | |
| 4833 // Constant for byte-wide masking | |
| 4834 operand immI_255() %{ | |
| 4835 predicate( n->get_int() == 255 ); | |
| 4836 match(ConI); | |
| 4837 | |
| 4838 format %{ %} | |
| 4839 interface(CONST_INTER); | |
| 4840 %} | |
| 4841 | |
| 785 | 4842 // Constant for short-wide masking |
| 4843 operand immI_65535() %{ | |
| 4844 predicate(n->get_int() == 65535); | |
| 4845 match(ConI); | |
| 4846 | |
| 4847 format %{ %} | |
| 4848 interface(CONST_INTER); | |
| 4849 %} | |
| 4850 | |
| 0 | 4851 // Register Operands |
| 4852 // Integer Register | |
| 4853 operand eRegI() %{ | |
| 4854 constraint(ALLOC_IN_RC(e_reg)); | |
| 4855 match(RegI); | |
| 4856 match(xRegI); | |
| 4857 match(eAXRegI); | |
| 4858 match(eBXRegI); | |
| 4859 match(eCXRegI); | |
| 4860 match(eDXRegI); | |
| 4861 match(eDIRegI); | |
| 4862 match(eSIRegI); | |
| 4863 | |
| 4864 format %{ %} | |
| 4865 interface(REG_INTER); | |
| 4866 %} | |
| 4867 | |
| 4868 // Subset of Integer Register | |
| 4869 operand xRegI(eRegI reg) %{ | |
| 4870 constraint(ALLOC_IN_RC(x_reg)); | |
| 4871 match(reg); | |
| 4872 match(eAXRegI); | |
| 4873 match(eBXRegI); | |
| 4874 match(eCXRegI); | |
| 4875 match(eDXRegI); | |
| 4876 | |
| 4877 format %{ %} | |
| 4878 interface(REG_INTER); | |
| 4879 %} | |
| 4880 | |
| 4881 // Special Registers | |
| 4882 operand eAXRegI(xRegI reg) %{ | |
| 4883 constraint(ALLOC_IN_RC(eax_reg)); | |
| 4884 match(reg); | |
| 4885 match(eRegI); | |
| 4886 | |
| 4887 format %{ "EAX" %} | |
| 4888 interface(REG_INTER); | |
| 4889 %} | |
| 4890 | |
| 4891 // Special Registers | |
| 4892 operand eBXRegI(xRegI reg) %{ | |
| 4893 constraint(ALLOC_IN_RC(ebx_reg)); | |
| 4894 match(reg); | |
| 4895 match(eRegI); | |
| 4896 | |
| 4897 format %{ "EBX" %} | |
| 4898 interface(REG_INTER); | |
| 4899 %} | |
| 4900 | |
| 4901 operand eCXRegI(xRegI reg) %{ | |
| 4902 constraint(ALLOC_IN_RC(ecx_reg)); | |
| 4903 match(reg); | |
| 4904 match(eRegI); | |
| 4905 | |
| 4906 format %{ "ECX" %} | |
| 4907 interface(REG_INTER); | |
| 4908 %} | |
| 4909 | |
| 4910 operand eDXRegI(xRegI reg) %{ | |
| 4911 constraint(ALLOC_IN_RC(edx_reg)); | |
| 4912 match(reg); | |
| 4913 match(eRegI); | |
| 4914 | |
| 4915 format %{ "EDX" %} | |
| 4916 interface(REG_INTER); | |
| 4917 %} | |
| 4918 | |
| 4919 operand eDIRegI(xRegI reg) %{ | |
| 4920 constraint(ALLOC_IN_RC(edi_reg)); | |
| 4921 match(reg); | |
| 4922 match(eRegI); | |
| 4923 | |
| 4924 format %{ "EDI" %} | |
| 4925 interface(REG_INTER); | |
| 4926 %} | |
| 4927 | |
| 4928 operand naxRegI() %{ | |
| 4929 constraint(ALLOC_IN_RC(nax_reg)); | |
| 4930 match(RegI); | |
| 4931 match(eCXRegI); | |
| 4932 match(eDXRegI); | |
| 4933 match(eSIRegI); | |
| 4934 match(eDIRegI); | |
| 4935 | |
| 4936 format %{ %} | |
| 4937 interface(REG_INTER); | |
| 4938 %} | |
| 4939 | |
| 4940 operand nadxRegI() %{ | |
| 4941 constraint(ALLOC_IN_RC(nadx_reg)); | |
| 4942 match(RegI); | |
| 4943 match(eBXRegI); | |
| 4944 match(eCXRegI); | |
| 4945 match(eSIRegI); | |
| 4946 match(eDIRegI); | |
| 4947 | |
| 4948 format %{ %} | |
| 4949 interface(REG_INTER); | |
| 4950 %} | |
| 4951 | |
| 4952 operand ncxRegI() %{ | |
| 4953 constraint(ALLOC_IN_RC(ncx_reg)); | |
| 4954 match(RegI); | |
| 4955 match(eAXRegI); | |
| 4956 match(eDXRegI); | |
| 4957 match(eSIRegI); | |
| 4958 match(eDIRegI); | |
| 4959 | |
| 4960 format %{ %} | |
| 4961 interface(REG_INTER); | |
| 4962 %} | |
| 4963 | |
| 4964 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg | |
| 4965 // // | |
| 4966 operand eSIRegI(xRegI reg) %{ | |
| 4967 constraint(ALLOC_IN_RC(esi_reg)); | |
| 4968 match(reg); | |
| 4969 match(eRegI); | |
| 4970 | |
| 4971 format %{ "ESI" %} | |
| 4972 interface(REG_INTER); | |
| 4973 %} | |
| 4974 | |
| 4975 // Pointer Register | |
| 4976 operand anyRegP() %{ | |
| 4977 constraint(ALLOC_IN_RC(any_reg)); | |
| 4978 match(RegP); | |
| 4979 match(eAXRegP); | |
| 4980 match(eBXRegP); | |
| 4981 match(eCXRegP); | |
| 4982 match(eDIRegP); | |
| 4983 match(eRegP); | |
| 4984 | |
| 4985 format %{ %} | |
| 4986 interface(REG_INTER); | |
| 4987 %} | |
| 4988 | |
| 4989 operand eRegP() %{ | |
| 4990 constraint(ALLOC_IN_RC(e_reg)); | |
| 4991 match(RegP); | |
| 4992 match(eAXRegP); | |
| 4993 match(eBXRegP); | |
| 4994 match(eCXRegP); | |
| 4995 match(eDIRegP); | |
| 4996 | |
| 4997 format %{ %} | |
| 4998 interface(REG_INTER); | |
| 4999 %} | |
| 5000 | |
| 5001 // On windows95, EBP is not safe to use for implicit null tests. | |
| 5002 operand eRegP_no_EBP() %{ | |
| 5003 constraint(ALLOC_IN_RC(e_reg_no_rbp)); | |
| 5004 match(RegP); | |
| 5005 match(eAXRegP); | |
| 5006 match(eBXRegP); | |
| 5007 match(eCXRegP); | |
| 5008 match(eDIRegP); | |
| 5009 | |
| 5010 op_cost(100); | |
| 5011 format %{ %} | |
| 5012 interface(REG_INTER); | |
| 5013 %} | |
| 5014 | |
| 5015 operand naxRegP() %{ | |
| 5016 constraint(ALLOC_IN_RC(nax_reg)); | |
| 5017 match(RegP); | |
| 5018 match(eBXRegP); | |
| 5019 match(eDXRegP); | |
| 5020 match(eCXRegP); | |
| 5021 match(eSIRegP); | |
| 5022 match(eDIRegP); | |
| 5023 | |
| 5024 format %{ %} | |
| 5025 interface(REG_INTER); | |
| 5026 %} | |
| 5027 | |
| 5028 operand nabxRegP() %{ | |
| 5029 constraint(ALLOC_IN_RC(nabx_reg)); | |
| 5030 match(RegP); | |
| 5031 match(eCXRegP); | |
| 5032 match(eDXRegP); | |
| 5033 match(eSIRegP); | |
| 5034 match(eDIRegP); | |
| 5035 | |
| 5036 format %{ %} | |
| 5037 interface(REG_INTER); | |
| 5038 %} | |
| 5039 | |
| 5040 operand pRegP() %{ | |
| 5041 constraint(ALLOC_IN_RC(p_reg)); | |
| 5042 match(RegP); | |
| 5043 match(eBXRegP); | |
| 5044 match(eDXRegP); | |
| 5045 match(eSIRegP); | |
| 5046 match(eDIRegP); | |
| 5047 | |
| 5048 format %{ %} | |
| 5049 interface(REG_INTER); | |
| 5050 %} | |
| 5051 | |
| 5052 // Special Registers | |
| 5053 // Return a pointer value | |
| 5054 operand eAXRegP(eRegP reg) %{ | |
| 5055 constraint(ALLOC_IN_RC(eax_reg)); | |
| 5056 match(reg); | |
| 5057 format %{ "EAX" %} | |
| 5058 interface(REG_INTER); | |
| 5059 %} | |
| 5060 | |
| 5061 // Used in AtomicAdd | |
| 5062 operand eBXRegP(eRegP reg) %{ | |
| 5063 constraint(ALLOC_IN_RC(ebx_reg)); | |
| 5064 match(reg); | |
| 5065 format %{ "EBX" %} | |
| 5066 interface(REG_INTER); | |
| 5067 %} | |
| 5068 | |
| 5069 // Tail-call (interprocedural jump) to interpreter | |
| 5070 operand eCXRegP(eRegP reg) %{ | |
| 5071 constraint(ALLOC_IN_RC(ecx_reg)); | |
| 5072 match(reg); | |
| 5073 format %{ "ECX" %} | |
| 5074 interface(REG_INTER); | |
| 5075 %} | |
| 5076 | |
| 5077 operand eSIRegP(eRegP reg) %{ | |
| 5078 constraint(ALLOC_IN_RC(esi_reg)); | |
| 5079 match(reg); | |
| 5080 format %{ "ESI" %} | |
| 5081 interface(REG_INTER); | |
| 5082 %} | |
| 5083 | |
| 5084 // Used in rep stosw | |
| 5085 operand eDIRegP(eRegP reg) %{ | |
| 5086 constraint(ALLOC_IN_RC(edi_reg)); | |
| 5087 match(reg); | |
| 5088 format %{ "EDI" %} | |
| 5089 interface(REG_INTER); | |
| 5090 %} | |
| 5091 | |
| 5092 operand eBPRegP() %{ | |
| 5093 constraint(ALLOC_IN_RC(ebp_reg)); | |
| 5094 match(RegP); | |
| 5095 format %{ "EBP" %} | |
| 5096 interface(REG_INTER); | |
| 5097 %} | |
| 5098 | |
| 5099 operand eRegL() %{ | |
| 5100 constraint(ALLOC_IN_RC(long_reg)); | |
| 5101 match(RegL); | |
| 5102 match(eADXRegL); | |
| 5103 | |
| 5104 format %{ %} | |
| 5105 interface(REG_INTER); | |
| 5106 %} | |
| 5107 | |
| 5108 operand eADXRegL( eRegL reg ) %{ | |
| 5109 constraint(ALLOC_IN_RC(eadx_reg)); | |
| 5110 match(reg); | |
| 5111 | |
| 5112 format %{ "EDX:EAX" %} | |
| 5113 interface(REG_INTER); | |
| 5114 %} | |
| 5115 | |
| 5116 operand eBCXRegL( eRegL reg ) %{ | |
| 5117 constraint(ALLOC_IN_RC(ebcx_reg)); | |
| 5118 match(reg); | |
| 5119 | |
| 5120 format %{ "EBX:ECX" %} | |
| 5121 interface(REG_INTER); | |
| 5122 %} | |
| 5123 | |
| 5124 // Special case for integer high multiply | |
| 5125 operand eADXRegL_low_only() %{ | |
| 5126 constraint(ALLOC_IN_RC(eadx_reg)); | |
| 5127 match(RegL); | |
| 5128 | |
| 5129 format %{ "EAX" %} | |
| 5130 interface(REG_INTER); | |
| 5131 %} | |
| 5132 | |
| 5133 // Flags register, used as output of compare instructions | |
| 5134 operand eFlagsReg() %{ | |
| 5135 constraint(ALLOC_IN_RC(int_flags)); | |
| 5136 match(RegFlags); | |
| 5137 | |
| 5138 format %{ "EFLAGS" %} | |
| 5139 interface(REG_INTER); | |
| 5140 %} | |
| 5141 | |
| 5142 // Flags register, used as output of FLOATING POINT compare instructions | |
| 5143 operand eFlagsRegU() %{ | |
| 5144 constraint(ALLOC_IN_RC(int_flags)); | |
| 5145 match(RegFlags); | |
| 5146 | |
| 5147 format %{ "EFLAGS_U" %} | |
| 5148 interface(REG_INTER); | |
| 5149 %} | |
| 5150 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
5151 operand eFlagsRegUCF() %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
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|
5152 constraint(ALLOC_IN_RC(int_flags)); |
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5153 match(RegFlags); |
|
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5154 predicate(false); |
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|
5155 |
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|
5156 format %{ "EFLAGS_U_CF" %} |
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5157 interface(REG_INTER); |
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5158 %} |
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|
5159 |
| 0 | 5160 // Condition Code Register used by long compare |
| 5161 operand flagsReg_long_LTGE() %{ | |
| 5162 constraint(ALLOC_IN_RC(int_flags)); | |
| 5163 match(RegFlags); | |
| 5164 format %{ "FLAGS_LTGE" %} | |
| 5165 interface(REG_INTER); | |
| 5166 %} | |
| 5167 operand flagsReg_long_EQNE() %{ | |
| 5168 constraint(ALLOC_IN_RC(int_flags)); | |
| 5169 match(RegFlags); | |
| 5170 format %{ "FLAGS_EQNE" %} | |
| 5171 interface(REG_INTER); | |
| 5172 %} | |
| 5173 operand flagsReg_long_LEGT() %{ | |
| 5174 constraint(ALLOC_IN_RC(int_flags)); | |
| 5175 match(RegFlags); | |
| 5176 format %{ "FLAGS_LEGT" %} | |
| 5177 interface(REG_INTER); | |
| 5178 %} | |
| 5179 | |
| 5180 // Float register operands | |
| 5181 operand regD() %{ | |
| 5182 predicate( UseSSE < 2 ); | |
| 5183 constraint(ALLOC_IN_RC(dbl_reg)); | |
| 5184 match(RegD); | |
| 5185 match(regDPR1); | |
| 5186 match(regDPR2); | |
| 5187 format %{ %} | |
| 5188 interface(REG_INTER); | |
| 5189 %} | |
| 5190 | |
| 5191 operand regDPR1(regD reg) %{ | |
| 5192 predicate( UseSSE < 2 ); | |
| 5193 constraint(ALLOC_IN_RC(dbl_reg0)); | |
| 5194 match(reg); | |
| 5195 format %{ "FPR1" %} | |
| 5196 interface(REG_INTER); | |
| 5197 %} | |
| 5198 | |
| 5199 operand regDPR2(regD reg) %{ | |
| 5200 predicate( UseSSE < 2 ); | |
| 5201 constraint(ALLOC_IN_RC(dbl_reg1)); | |
| 5202 match(reg); | |
| 5203 format %{ "FPR2" %} | |
| 5204 interface(REG_INTER); | |
| 5205 %} | |
| 5206 | |
| 5207 operand regnotDPR1(regD reg) %{ | |
| 5208 predicate( UseSSE < 2 ); | |
| 5209 constraint(ALLOC_IN_RC(dbl_notreg0)); | |
| 5210 match(reg); | |
| 5211 format %{ %} | |
| 5212 interface(REG_INTER); | |
| 5213 %} | |
| 5214 | |
| 5215 // XMM Double register operands | |
| 5216 operand regXD() %{ | |
| 5217 predicate( UseSSE>=2 ); | |
| 5218 constraint(ALLOC_IN_RC(xdb_reg)); | |
| 5219 match(RegD); | |
| 5220 match(regXD6); | |
| 5221 match(regXD7); | |
| 5222 format %{ %} | |
| 5223 interface(REG_INTER); | |
| 5224 %} | |
| 5225 | |
| 5226 // XMM6 double register operands | |
| 5227 operand regXD6(regXD reg) %{ | |
| 5228 predicate( UseSSE>=2 ); | |
| 5229 constraint(ALLOC_IN_RC(xdb_reg6)); | |
| 5230 match(reg); | |
| 5231 format %{ "XMM6" %} | |
| 5232 interface(REG_INTER); | |
| 5233 %} | |
| 5234 | |
| 5235 // XMM7 double register operands | |
| 5236 operand regXD7(regXD reg) %{ | |
| 5237 predicate( UseSSE>=2 ); | |
| 5238 constraint(ALLOC_IN_RC(xdb_reg7)); | |
| 5239 match(reg); | |
| 5240 format %{ "XMM7" %} | |
| 5241 interface(REG_INTER); | |
| 5242 %} | |
| 5243 | |
| 5244 // Float register operands | |
| 5245 operand regF() %{ | |
| 5246 predicate( UseSSE < 2 ); | |
| 5247 constraint(ALLOC_IN_RC(flt_reg)); | |
| 5248 match(RegF); | |
| 5249 match(regFPR1); | |
| 5250 format %{ %} | |
| 5251 interface(REG_INTER); | |
| 5252 %} | |
| 5253 | |
| 5254 // Float register operands | |
| 5255 operand regFPR1(regF reg) %{ | |
| 5256 predicate( UseSSE < 2 ); | |
| 5257 constraint(ALLOC_IN_RC(flt_reg0)); | |
| 5258 match(reg); | |
| 5259 format %{ "FPR1" %} | |
| 5260 interface(REG_INTER); | |
| 5261 %} | |
| 5262 | |
| 5263 // XMM register operands | |
| 5264 operand regX() %{ | |
| 5265 predicate( UseSSE>=1 ); | |
| 5266 constraint(ALLOC_IN_RC(xmm_reg)); | |
| 5267 match(RegF); | |
| 5268 format %{ %} | |
| 5269 interface(REG_INTER); | |
| 5270 %} | |
| 5271 | |
| 5272 | |
| 5273 //----------Memory Operands---------------------------------------------------- | |
| 5274 // Direct Memory Operand | |
| 5275 operand direct(immP addr) %{ | |
| 5276 match(addr); | |
| 5277 | |
| 5278 format %{ "[$addr]" %} | |
| 5279 interface(MEMORY_INTER) %{ | |
| 5280 base(0xFFFFFFFF); | |
| 5281 index(0x4); | |
| 5282 scale(0x0); | |
| 5283 disp($addr); | |
| 5284 %} | |
| 5285 %} | |
| 5286 | |
| 5287 // Indirect Memory Operand | |
| 5288 operand indirect(eRegP reg) %{ | |
| 5289 constraint(ALLOC_IN_RC(e_reg)); | |
| 5290 match(reg); | |
| 5291 | |
| 5292 format %{ "[$reg]" %} | |
| 5293 interface(MEMORY_INTER) %{ | |
| 5294 base($reg); | |
| 5295 index(0x4); | |
| 5296 scale(0x0); | |
| 5297 disp(0x0); | |
| 5298 %} | |
| 5299 %} | |
| 5300 | |
| 5301 // Indirect Memory Plus Short Offset Operand | |
| 5302 operand indOffset8(eRegP reg, immI8 off) %{ | |
| 5303 match(AddP reg off); | |
| 5304 | |
| 5305 format %{ "[$reg + $off]" %} | |
| 5306 interface(MEMORY_INTER) %{ | |
| 5307 base($reg); | |
| 5308 index(0x4); | |
| 5309 scale(0x0); | |
| 5310 disp($off); | |
| 5311 %} | |
| 5312 %} | |
| 5313 | |
| 5314 // Indirect Memory Plus Long Offset Operand | |
| 5315 operand indOffset32(eRegP reg, immI off) %{ | |
| 5316 match(AddP reg off); | |
| 5317 | |
| 5318 format %{ "[$reg + $off]" %} | |
| 5319 interface(MEMORY_INTER) %{ | |
| 5320 base($reg); | |
| 5321 index(0x4); | |
| 5322 scale(0x0); | |
| 5323 disp($off); | |
| 5324 %} | |
| 5325 %} | |
| 5326 | |
| 5327 // Indirect Memory Plus Long Offset Operand | |
| 5328 operand indOffset32X(eRegI reg, immP off) %{ | |
| 5329 match(AddP off reg); | |
| 5330 | |
| 5331 format %{ "[$reg + $off]" %} | |
| 5332 interface(MEMORY_INTER) %{ | |
| 5333 base($reg); | |
| 5334 index(0x4); | |
| 5335 scale(0x0); | |
| 5336 disp($off); | |
| 5337 %} | |
| 5338 %} | |
| 5339 | |
| 5340 // Indirect Memory Plus Index Register Plus Offset Operand | |
| 5341 operand indIndexOffset(eRegP reg, eRegI ireg, immI off) %{ | |
| 5342 match(AddP (AddP reg ireg) off); | |
| 5343 | |
| 5344 op_cost(10); | |
| 5345 format %{"[$reg + $off + $ireg]" %} | |
| 5346 interface(MEMORY_INTER) %{ | |
| 5347 base($reg); | |
| 5348 index($ireg); | |
| 5349 scale(0x0); | |
| 5350 disp($off); | |
| 5351 %} | |
| 5352 %} | |
| 5353 | |
| 5354 // Indirect Memory Plus Index Register Plus Offset Operand | |
| 5355 operand indIndex(eRegP reg, eRegI ireg) %{ | |
| 5356 match(AddP reg ireg); | |
| 5357 | |
| 5358 op_cost(10); | |
| 5359 format %{"[$reg + $ireg]" %} | |
| 5360 interface(MEMORY_INTER) %{ | |
| 5361 base($reg); | |
| 5362 index($ireg); | |
| 5363 scale(0x0); | |
| 5364 disp(0x0); | |
| 5365 %} | |
| 5366 %} | |
| 5367 | |
| 5368 // // ------------------------------------------------------------------------- | |
| 5369 // // 486 architecture doesn't support "scale * index + offset" with out a base | |
| 5370 // // ------------------------------------------------------------------------- | |
| 5371 // // Scaled Memory Operands | |
| 5372 // // Indirect Memory Times Scale Plus Offset Operand | |
| 5373 // operand indScaleOffset(immP off, eRegI ireg, immI2 scale) %{ | |
| 5374 // match(AddP off (LShiftI ireg scale)); | |
| 5375 // | |
| 5376 // op_cost(10); | |
| 5377 // format %{"[$off + $ireg << $scale]" %} | |
| 5378 // interface(MEMORY_INTER) %{ | |
| 5379 // base(0x4); | |
| 5380 // index($ireg); | |
| 5381 // scale($scale); | |
| 5382 // disp($off); | |
| 5383 // %} | |
| 5384 // %} | |
| 5385 | |
| 5386 // Indirect Memory Times Scale Plus Index Register | |
| 5387 operand indIndexScale(eRegP reg, eRegI ireg, immI2 scale) %{ | |
| 5388 match(AddP reg (LShiftI ireg scale)); | |
| 5389 | |
| 5390 op_cost(10); | |
| 5391 format %{"[$reg + $ireg << $scale]" %} | |
| 5392 interface(MEMORY_INTER) %{ | |
| 5393 base($reg); | |
| 5394 index($ireg); | |
| 5395 scale($scale); | |
| 5396 disp(0x0); | |
| 5397 %} | |
| 5398 %} | |
| 5399 | |
| 5400 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand | |
| 5401 operand indIndexScaleOffset(eRegP reg, immI off, eRegI ireg, immI2 scale) %{ | |
| 5402 match(AddP (AddP reg (LShiftI ireg scale)) off); | |
| 5403 | |
| 5404 op_cost(10); | |
| 5405 format %{"[$reg + $off + $ireg << $scale]" %} | |
| 5406 interface(MEMORY_INTER) %{ | |
| 5407 base($reg); | |
| 5408 index($ireg); | |
| 5409 scale($scale); | |
| 5410 disp($off); | |
| 5411 %} | |
| 5412 %} | |
| 5413 | |
| 5414 //----------Load Long Memory Operands------------------------------------------ | |
| 5415 // The load-long idiom will use it's address expression again after loading | |
| 5416 // the first word of the long. If the load-long destination overlaps with | |
| 5417 // registers used in the addressing expression, the 2nd half will be loaded | |
| 5418 // from a clobbered address. Fix this by requiring that load-long use | |
| 5419 // address registers that do not overlap with the load-long target. | |
| 5420 | |
| 5421 // load-long support | |
| 5422 operand load_long_RegP() %{ | |
| 5423 constraint(ALLOC_IN_RC(esi_reg)); | |
| 5424 match(RegP); | |
| 5425 match(eSIRegP); | |
| 5426 op_cost(100); | |
| 5427 format %{ %} | |
| 5428 interface(REG_INTER); | |
| 5429 %} | |
| 5430 | |
| 5431 // Indirect Memory Operand Long | |
| 5432 operand load_long_indirect(load_long_RegP reg) %{ | |
| 5433 constraint(ALLOC_IN_RC(esi_reg)); | |
| 5434 match(reg); | |
| 5435 | |
| 5436 format %{ "[$reg]" %} | |
| 5437 interface(MEMORY_INTER) %{ | |
| 5438 base($reg); | |
| 5439 index(0x4); | |
| 5440 scale(0x0); | |
| 5441 disp(0x0); | |
| 5442 %} | |
| 5443 %} | |
| 5444 | |
| 5445 // Indirect Memory Plus Long Offset Operand | |
| 5446 operand load_long_indOffset32(load_long_RegP reg, immI off) %{ | |
| 5447 match(AddP reg off); | |
| 5448 | |
| 5449 format %{ "[$reg + $off]" %} | |
| 5450 interface(MEMORY_INTER) %{ | |
| 5451 base($reg); | |
| 5452 index(0x4); | |
| 5453 scale(0x0); | |
| 5454 disp($off); | |
| 5455 %} | |
| 5456 %} | |
| 5457 | |
| 5458 opclass load_long_memory(load_long_indirect, load_long_indOffset32); | |
| 5459 | |
| 5460 | |
| 5461 //----------Special Memory Operands-------------------------------------------- | |
| 5462 // Stack Slot Operand - This operand is used for loading and storing temporary | |
| 5463 // values on the stack where a match requires a value to | |
| 5464 // flow through memory. | |
| 5465 operand stackSlotP(sRegP reg) %{ | |
| 5466 constraint(ALLOC_IN_RC(stack_slots)); | |
| 5467 // No match rule because this operand is only generated in matching | |
| 5468 format %{ "[$reg]" %} | |
| 5469 interface(MEMORY_INTER) %{ | |
| 5470 base(0x4); // ESP | |
| 5471 index(0x4); // No Index | |
| 5472 scale(0x0); // No Scale | |
| 5473 disp($reg); // Stack Offset | |
| 5474 %} | |
| 5475 %} | |
| 5476 | |
| 5477 operand stackSlotI(sRegI reg) %{ | |
| 5478 constraint(ALLOC_IN_RC(stack_slots)); | |
| 5479 // No match rule because this operand is only generated in matching | |
| 5480 format %{ "[$reg]" %} | |
| 5481 interface(MEMORY_INTER) %{ | |
| 5482 base(0x4); // ESP | |
| 5483 index(0x4); // No Index | |
| 5484 scale(0x0); // No Scale | |
| 5485 disp($reg); // Stack Offset | |
| 5486 %} | |
| 5487 %} | |
| 5488 | |
| 5489 operand stackSlotF(sRegF reg) %{ | |
| 5490 constraint(ALLOC_IN_RC(stack_slots)); | |
| 5491 // No match rule because this operand is only generated in matching | |
| 5492 format %{ "[$reg]" %} | |
| 5493 interface(MEMORY_INTER) %{ | |
| 5494 base(0x4); // ESP | |
| 5495 index(0x4); // No Index | |
| 5496 scale(0x0); // No Scale | |
| 5497 disp($reg); // Stack Offset | |
| 5498 %} | |
| 5499 %} | |
| 5500 | |
| 5501 operand stackSlotD(sRegD reg) %{ | |
| 5502 constraint(ALLOC_IN_RC(stack_slots)); | |
| 5503 // No match rule because this operand is only generated in matching | |
| 5504 format %{ "[$reg]" %} | |
| 5505 interface(MEMORY_INTER) %{ | |
| 5506 base(0x4); // ESP | |
| 5507 index(0x4); // No Index | |
| 5508 scale(0x0); // No Scale | |
| 5509 disp($reg); // Stack Offset | |
| 5510 %} | |
| 5511 %} | |
| 5512 | |
| 5513 operand stackSlotL(sRegL reg) %{ | |
| 5514 constraint(ALLOC_IN_RC(stack_slots)); | |
| 5515 // No match rule because this operand is only generated in matching | |
| 5516 format %{ "[$reg]" %} | |
| 5517 interface(MEMORY_INTER) %{ | |
| 5518 base(0x4); // ESP | |
| 5519 index(0x4); // No Index | |
| 5520 scale(0x0); // No Scale | |
| 5521 disp($reg); // Stack Offset | |
| 5522 %} | |
| 5523 %} | |
| 5524 | |
| 5525 //----------Memory Operands - Win95 Implicit Null Variants---------------- | |
| 5526 // Indirect Memory Operand | |
| 5527 operand indirect_win95_safe(eRegP_no_EBP reg) | |
| 5528 %{ | |
| 5529 constraint(ALLOC_IN_RC(e_reg)); | |
| 5530 match(reg); | |
| 5531 | |
| 5532 op_cost(100); | |
| 5533 format %{ "[$reg]" %} | |
| 5534 interface(MEMORY_INTER) %{ | |
| 5535 base($reg); | |
| 5536 index(0x4); | |
| 5537 scale(0x0); | |
| 5538 disp(0x0); | |
| 5539 %} | |
| 5540 %} | |
| 5541 | |
| 5542 // Indirect Memory Plus Short Offset Operand | |
| 5543 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off) | |
| 5544 %{ | |
| 5545 match(AddP reg off); | |
| 5546 | |
| 5547 op_cost(100); | |
| 5548 format %{ "[$reg + $off]" %} | |
| 5549 interface(MEMORY_INTER) %{ | |
| 5550 base($reg); | |
| 5551 index(0x4); | |
| 5552 scale(0x0); | |
| 5553 disp($off); | |
| 5554 %} | |
| 5555 %} | |
| 5556 | |
| 5557 // Indirect Memory Plus Long Offset Operand | |
| 5558 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off) | |
| 5559 %{ | |
| 5560 match(AddP reg off); | |
| 5561 | |
| 5562 op_cost(100); | |
| 5563 format %{ "[$reg + $off]" %} | |
| 5564 interface(MEMORY_INTER) %{ | |
| 5565 base($reg); | |
| 5566 index(0x4); | |
| 5567 scale(0x0); | |
| 5568 disp($off); | |
| 5569 %} | |
| 5570 %} | |
| 5571 | |
| 5572 // Indirect Memory Plus Index Register Plus Offset Operand | |
| 5573 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI off) | |
| 5574 %{ | |
| 5575 match(AddP (AddP reg ireg) off); | |
| 5576 | |
| 5577 op_cost(100); | |
| 5578 format %{"[$reg + $off + $ireg]" %} | |
| 5579 interface(MEMORY_INTER) %{ | |
| 5580 base($reg); | |
| 5581 index($ireg); | |
| 5582 scale(0x0); | |
| 5583 disp($off); | |
| 5584 %} | |
| 5585 %} | |
| 5586 | |
| 5587 // Indirect Memory Times Scale Plus Index Register | |
| 5588 operand indIndexScale_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI2 scale) | |
| 5589 %{ | |
| 5590 match(AddP reg (LShiftI ireg scale)); | |
| 5591 | |
| 5592 op_cost(100); | |
| 5593 format %{"[$reg + $ireg << $scale]" %} | |
| 5594 interface(MEMORY_INTER) %{ | |
| 5595 base($reg); | |
| 5596 index($ireg); | |
| 5597 scale($scale); | |
| 5598 disp(0x0); | |
| 5599 %} | |
| 5600 %} | |
| 5601 | |
| 5602 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand | |
| 5603 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, eRegI ireg, immI2 scale) | |
| 5604 %{ | |
| 5605 match(AddP (AddP reg (LShiftI ireg scale)) off); | |
| 5606 | |
| 5607 op_cost(100); | |
| 5608 format %{"[$reg + $off + $ireg << $scale]" %} | |
| 5609 interface(MEMORY_INTER) %{ | |
| 5610 base($reg); | |
| 5611 index($ireg); | |
| 5612 scale($scale); | |
| 5613 disp($off); | |
| 5614 %} | |
| 5615 %} | |
| 5616 | |
| 5617 //----------Conditional Branch Operands---------------------------------------- | |
| 5618 // Comparison Op - This is the operation of the comparison, and is limited to | |
| 5619 // the following set of codes: | |
| 5620 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) | |
| 5621 // | |
| 5622 // Other attributes of the comparison, such as unsignedness, are specified | |
| 5623 // by the comparison instruction that sets a condition code flags register. | |
| 5624 // That result is represented by a flags operand whose subtype is appropriate | |
| 5625 // to the unsignedness (etc.) of the comparison. | |
| 5626 // | |
| 5627 // Later, the instruction which matches both the Comparison Op (a Bool) and | |
| 5628 // the flags (produced by the Cmp) specifies the coding of the comparison op | |
| 5629 // by matching a specific subtype of Bool operand below, such as cmpOpU. | |
| 5630 | |
| 5631 // Comparision Code | |
| 5632 operand cmpOp() %{ | |
| 5633 match(Bool); | |
| 5634 | |
| 5635 format %{ "" %} | |
| 5636 interface(COND_INTER) %{ | |
|
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5637 equal(0x4, "e"); |
|
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5638 not_equal(0x5, "ne"); |
|
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5639 less(0xC, "l"); |
|
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|
5640 greater_equal(0xD, "ge"); |
|
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|
5641 less_equal(0xE, "le"); |
|
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|
5642 greater(0xF, "g"); |
| 0 | 5643 %} |
| 5644 %} | |
| 5645 | |
| 5646 // Comparison Code, unsigned compare. Used by FP also, with | |
| 5647 // C2 (unordered) turned into GT or LT already. The other bits | |
| 5648 // C0 and C3 are turned into Carry & Zero flags. | |
| 5649 operand cmpOpU() %{ | |
| 5650 match(Bool); | |
| 5651 | |
| 5652 format %{ "" %} | |
| 5653 interface(COND_INTER) %{ | |
|
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5654 equal(0x4, "e"); |
|
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diff
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|
5655 not_equal(0x5, "ne"); |
|
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diff
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|
5656 less(0x2, "b"); |
|
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|
5657 greater_equal(0x3, "nb"); |
|
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|
5658 less_equal(0x6, "be"); |
|
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|
5659 greater(0x7, "nbe"); |
|
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diff
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|
5660 %} |
|
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diff
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|
5661 %} |
|
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|
5662 |
|
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|
5663 // Floating comparisons that don't require any fixup for the unordered case |
|
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|
5664 operand cmpOpUCF() %{ |
|
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diff
changeset
|
5665 match(Bool); |
|
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diff
changeset
|
5666 predicate(n->as_Bool()->_test._test == BoolTest::lt || |
|
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|
5667 n->as_Bool()->_test._test == BoolTest::ge || |
|
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|
5668 n->as_Bool()->_test._test == BoolTest::le || |
|
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|
5669 n->as_Bool()->_test._test == BoolTest::gt); |
|
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|
5670 format %{ "" %} |
|
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|
5671 interface(COND_INTER) %{ |
|
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|
5672 equal(0x4, "e"); |
|
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|
5673 not_equal(0x5, "ne"); |
|
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|
5674 less(0x2, "b"); |
|
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|
5675 greater_equal(0x3, "nb"); |
|
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|
5676 less_equal(0x6, "be"); |
|
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|
5677 greater(0x7, "nbe"); |
|
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|
5678 %} |
|
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|
5679 %} |
|
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|
5680 |
|
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changeset
|
5681 |
|
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diff
changeset
|
5682 // Floating comparisons that can be fixed up with extra conditional jumps |
|
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|
5683 operand cmpOpUCF2() %{ |
|
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|
5684 match(Bool); |
|
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changeset
|
5685 predicate(n->as_Bool()->_test._test == BoolTest::ne || |
|
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|
5686 n->as_Bool()->_test._test == BoolTest::eq); |
|
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|
5687 format %{ "" %} |
|
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diff
changeset
|
5688 interface(COND_INTER) %{ |
|
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diff
changeset
|
5689 equal(0x4, "e"); |
|
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diff
changeset
|
5690 not_equal(0x5, "ne"); |
|
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diff
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|
5691 less(0x2, "b"); |
|
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changeset
|
5692 greater_equal(0x3, "nb"); |
|
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|
5693 less_equal(0x6, "be"); |
|
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|
5694 greater(0x7, "nbe"); |
| 0 | 5695 %} |
| 5696 %} | |
| 5697 | |
| 5698 // Comparison Code for FP conditional move | |
| 5699 operand cmpOp_fcmov() %{ | |
| 5700 match(Bool); | |
| 5701 | |
| 5702 format %{ "" %} | |
| 5703 interface(COND_INTER) %{ | |
| 5704 equal (0x0C8); | |
| 5705 not_equal (0x1C8); | |
| 5706 less (0x0C0); | |
| 5707 greater_equal(0x1C0); | |
| 5708 less_equal (0x0D0); | |
| 5709 greater (0x1D0); | |
| 5710 %} | |
| 5711 %} | |
| 5712 | |
| 5713 // Comparision Code used in long compares | |
| 5714 operand cmpOp_commute() %{ | |
| 5715 match(Bool); | |
| 5716 | |
| 5717 format %{ "" %} | |
| 5718 interface(COND_INTER) %{ | |
|
415
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|
5719 equal(0x4, "e"); |
|
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|
5720 not_equal(0x5, "ne"); |
|
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|
5721 less(0xF, "g"); |
|
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diff
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|
5722 greater_equal(0xE, "le"); |
|
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|
5723 less_equal(0xD, "ge"); |
|
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|
5724 greater(0xC, "l"); |
| 0 | 5725 %} |
| 5726 %} | |
| 5727 | |
| 5728 //----------OPERAND CLASSES---------------------------------------------------- | |
| 5729 // Operand Classes are groups of operands that are used as to simplify | |
| 605 | 5730 // instruction definitions by not requiring the AD writer to specify separate |
| 0 | 5731 // instructions for every form of operand when the instruction accepts |
| 5732 // multiple operand types with the same basic encoding and format. The classic | |
| 5733 // case of this is memory operands. | |
| 5734 | |
| 5735 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset, | |
| 5736 indIndex, indIndexScale, indIndexScaleOffset); | |
| 5737 | |
| 5738 // Long memory operations are encoded in 2 instructions and a +4 offset. | |
| 5739 // This means some kind of offset is always required and you cannot use | |
| 5740 // an oop as the offset (done when working on static globals). | |
| 5741 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset, | |
| 5742 indIndex, indIndexScale, indIndexScaleOffset); | |
| 5743 | |
| 5744 | |
| 5745 //----------PIPELINE----------------------------------------------------------- | |
| 5746 // Rules which define the behavior of the target architectures pipeline. | |
| 5747 pipeline %{ | |
| 5748 | |
| 5749 //----------ATTRIBUTES--------------------------------------------------------- | |
| 5750 attributes %{ | |
| 5751 variable_size_instructions; // Fixed size instructions | |
| 5752 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle | |
| 5753 instruction_unit_size = 1; // An instruction is 1 bytes long | |
| 5754 instruction_fetch_unit_size = 16; // The processor fetches one line | |
| 5755 instruction_fetch_units = 1; // of 16 bytes | |
| 5756 | |
| 5757 // List of nop instructions | |
| 5758 nops( MachNop ); | |
| 5759 %} | |
| 5760 | |
| 5761 //----------RESOURCES---------------------------------------------------------- | |
| 5762 // Resources are the functional units available to the machine | |
| 5763 | |
| 5764 // Generic P2/P3 pipeline | |
| 5765 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of | |
| 5766 // 3 instructions decoded per cycle. | |
| 5767 // 2 load/store ops per cycle, 1 branch, 1 FPU, | |
| 5768 // 2 ALU op, only ALU0 handles mul/div instructions. | |
| 5769 resources( D0, D1, D2, DECODE = D0 | D1 | D2, | |
| 5770 MS0, MS1, MEM = MS0 | MS1, | |
| 5771 BR, FPU, | |
| 5772 ALU0, ALU1, ALU = ALU0 | ALU1 ); | |
| 5773 | |
| 5774 //----------PIPELINE DESCRIPTION----------------------------------------------- | |
| 5775 // Pipeline Description specifies the stages in the machine's pipeline | |
| 5776 | |
| 5777 // Generic P2/P3 pipeline | |
| 5778 pipe_desc(S0, S1, S2, S3, S4, S5); | |
| 5779 | |
| 5780 //----------PIPELINE CLASSES--------------------------------------------------- | |
| 5781 // Pipeline Classes describe the stages in which input and output are | |
| 5782 // referenced by the hardware pipeline. | |
| 5783 | |
| 5784 // Naming convention: ialu or fpu | |
| 5785 // Then: _reg | |
| 5786 // Then: _reg if there is a 2nd register | |
| 5787 // Then: _long if it's a pair of instructions implementing a long | |
| 5788 // Then: _fat if it requires the big decoder | |
| 5789 // Or: _mem if it requires the big decoder and a memory unit. | |
| 5790 | |
| 5791 // Integer ALU reg operation | |
| 5792 pipe_class ialu_reg(eRegI dst) %{ | |
| 5793 single_instruction; | |
| 5794 dst : S4(write); | |
| 5795 dst : S3(read); | |
| 5796 DECODE : S0; // any decoder | |
| 5797 ALU : S3; // any alu | |
| 5798 %} | |
| 5799 | |
| 5800 // Long ALU reg operation | |
| 5801 pipe_class ialu_reg_long(eRegL dst) %{ | |
| 5802 instruction_count(2); | |
| 5803 dst : S4(write); | |
| 5804 dst : S3(read); | |
| 5805 DECODE : S0(2); // any 2 decoders | |
| 5806 ALU : S3(2); // both alus | |
| 5807 %} | |
| 5808 | |
| 5809 // Integer ALU reg operation using big decoder | |
| 5810 pipe_class ialu_reg_fat(eRegI dst) %{ | |
| 5811 single_instruction; | |
| 5812 dst : S4(write); | |
| 5813 dst : S3(read); | |
| 5814 D0 : S0; // big decoder only | |
| 5815 ALU : S3; // any alu | |
| 5816 %} | |
| 5817 | |
| 5818 // Long ALU reg operation using big decoder | |
| 5819 pipe_class ialu_reg_long_fat(eRegL dst) %{ | |
| 5820 instruction_count(2); | |
| 5821 dst : S4(write); | |
| 5822 dst : S3(read); | |
| 5823 D0 : S0(2); // big decoder only; twice | |
| 5824 ALU : S3(2); // any 2 alus | |
| 5825 %} | |
| 5826 | |
| 5827 // Integer ALU reg-reg operation | |
| 5828 pipe_class ialu_reg_reg(eRegI dst, eRegI src) %{ | |
| 5829 single_instruction; | |
| 5830 dst : S4(write); | |
| 5831 src : S3(read); | |
| 5832 DECODE : S0; // any decoder | |
| 5833 ALU : S3; // any alu | |
| 5834 %} | |
| 5835 | |
| 5836 // Long ALU reg-reg operation | |
| 5837 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{ | |
| 5838 instruction_count(2); | |
| 5839 dst : S4(write); | |
| 5840 src : S3(read); | |
| 5841 DECODE : S0(2); // any 2 decoders | |
| 5842 ALU : S3(2); // both alus | |
| 5843 %} | |
| 5844 | |
| 5845 // Integer ALU reg-reg operation | |
| 5846 pipe_class ialu_reg_reg_fat(eRegI dst, memory src) %{ | |
| 5847 single_instruction; | |
| 5848 dst : S4(write); | |
| 5849 src : S3(read); | |
| 5850 D0 : S0; // big decoder only | |
| 5851 ALU : S3; // any alu | |
| 5852 %} | |
| 5853 | |
| 5854 // Long ALU reg-reg operation | |
| 5855 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{ | |
| 5856 instruction_count(2); | |
| 5857 dst : S4(write); | |
| 5858 src : S3(read); | |
| 5859 D0 : S0(2); // big decoder only; twice | |
| 5860 ALU : S3(2); // both alus | |
| 5861 %} | |
| 5862 | |
| 5863 // Integer ALU reg-mem operation | |
| 5864 pipe_class ialu_reg_mem(eRegI dst, memory mem) %{ | |
| 5865 single_instruction; | |
| 5866 dst : S5(write); | |
| 5867 mem : S3(read); | |
| 5868 D0 : S0; // big decoder only | |
| 5869 ALU : S4; // any alu | |
| 5870 MEM : S3; // any mem | |
| 5871 %} | |
| 5872 | |
| 5873 // Long ALU reg-mem operation | |
| 5874 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{ | |
| 5875 instruction_count(2); | |
| 5876 dst : S5(write); | |
| 5877 mem : S3(read); | |
| 5878 D0 : S0(2); // big decoder only; twice | |
| 5879 ALU : S4(2); // any 2 alus | |
| 5880 MEM : S3(2); // both mems | |
| 5881 %} | |
| 5882 | |
| 5883 // Integer mem operation (prefetch) | |
| 5884 pipe_class ialu_mem(memory mem) | |
| 5885 %{ | |
| 5886 single_instruction; | |
| 5887 mem : S3(read); | |
| 5888 D0 : S0; // big decoder only | |
| 5889 MEM : S3; // any mem | |
| 5890 %} | |
| 5891 | |
| 5892 // Integer Store to Memory | |
| 5893 pipe_class ialu_mem_reg(memory mem, eRegI src) %{ | |
| 5894 single_instruction; | |
| 5895 mem : S3(read); | |
| 5896 src : S5(read); | |
| 5897 D0 : S0; // big decoder only | |
| 5898 ALU : S4; // any alu | |
| 5899 MEM : S3; | |
| 5900 %} | |
| 5901 | |
| 5902 // Long Store to Memory | |
| 5903 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{ | |
| 5904 instruction_count(2); | |
| 5905 mem : S3(read); | |
| 5906 src : S5(read); | |
| 5907 D0 : S0(2); // big decoder only; twice | |
| 5908 ALU : S4(2); // any 2 alus | |
| 5909 MEM : S3(2); // Both mems | |
| 5910 %} | |
| 5911 | |
| 5912 // Integer Store to Memory | |
| 5913 pipe_class ialu_mem_imm(memory mem) %{ | |
| 5914 single_instruction; | |
| 5915 mem : S3(read); | |
| 5916 D0 : S0; // big decoder only | |
| 5917 ALU : S4; // any alu | |
| 5918 MEM : S3; | |
| 5919 %} | |
| 5920 | |
| 5921 // Integer ALU0 reg-reg operation | |
| 5922 pipe_class ialu_reg_reg_alu0(eRegI dst, eRegI src) %{ | |
| 5923 single_instruction; | |
| 5924 dst : S4(write); | |
| 5925 src : S3(read); | |
| 5926 D0 : S0; // Big decoder only | |
| 5927 ALU0 : S3; // only alu0 | |
| 5928 %} | |
| 5929 | |
| 5930 // Integer ALU0 reg-mem operation | |
| 5931 pipe_class ialu_reg_mem_alu0(eRegI dst, memory mem) %{ | |
| 5932 single_instruction; | |
| 5933 dst : S5(write); | |
| 5934 mem : S3(read); | |
| 5935 D0 : S0; // big decoder only | |
| 5936 ALU0 : S4; // ALU0 only | |
| 5937 MEM : S3; // any mem | |
| 5938 %} | |
| 5939 | |
| 5940 // Integer ALU reg-reg operation | |
| 5941 pipe_class ialu_cr_reg_reg(eFlagsReg cr, eRegI src1, eRegI src2) %{ | |
| 5942 single_instruction; | |
| 5943 cr : S4(write); | |
| 5944 src1 : S3(read); | |
| 5945 src2 : S3(read); | |
| 5946 DECODE : S0; // any decoder | |
| 5947 ALU : S3; // any alu | |
| 5948 %} | |
| 5949 | |
| 5950 // Integer ALU reg-imm operation | |
| 5951 pipe_class ialu_cr_reg_imm(eFlagsReg cr, eRegI src1) %{ | |
| 5952 single_instruction; | |
| 5953 cr : S4(write); | |
| 5954 src1 : S3(read); | |
| 5955 DECODE : S0; // any decoder | |
| 5956 ALU : S3; // any alu | |
| 5957 %} | |
| 5958 | |
| 5959 // Integer ALU reg-mem operation | |
| 5960 pipe_class ialu_cr_reg_mem(eFlagsReg cr, eRegI src1, memory src2) %{ | |
| 5961 single_instruction; | |
| 5962 cr : S4(write); | |
| 5963 src1 : S3(read); | |
| 5964 src2 : S3(read); | |
| 5965 D0 : S0; // big decoder only | |
| 5966 ALU : S4; // any alu | |
| 5967 MEM : S3; | |
| 5968 %} | |
| 5969 | |
| 5970 // Conditional move reg-reg | |
| 5971 pipe_class pipe_cmplt( eRegI p, eRegI q, eRegI y ) %{ | |
| 5972 instruction_count(4); | |
| 5973 y : S4(read); | |
| 5974 q : S3(read); | |
| 5975 p : S3(read); | |
| 5976 DECODE : S0(4); // any decoder | |
| 5977 %} | |
| 5978 | |
| 5979 // Conditional move reg-reg | |
| 5980 pipe_class pipe_cmov_reg( eRegI dst, eRegI src, eFlagsReg cr ) %{ | |
| 5981 single_instruction; | |
| 5982 dst : S4(write); | |
| 5983 src : S3(read); | |
| 5984 cr : S3(read); | |
| 5985 DECODE : S0; // any decoder | |
| 5986 %} | |
| 5987 | |
| 5988 // Conditional move reg-mem | |
| 5989 pipe_class pipe_cmov_mem( eFlagsReg cr, eRegI dst, memory src) %{ | |
| 5990 single_instruction; | |
| 5991 dst : S4(write); | |
| 5992 src : S3(read); | |
| 5993 cr : S3(read); | |
| 5994 DECODE : S0; // any decoder | |
| 5995 MEM : S3; | |
| 5996 %} | |
| 5997 | |
| 5998 // Conditional move reg-reg long | |
| 5999 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{ | |
| 6000 single_instruction; | |
| 6001 dst : S4(write); | |
| 6002 src : S3(read); | |
| 6003 cr : S3(read); | |
| 6004 DECODE : S0(2); // any 2 decoders | |
| 6005 %} | |
| 6006 | |
| 6007 // Conditional move double reg-reg | |
| 6008 pipe_class pipe_cmovD_reg( eFlagsReg cr, regDPR1 dst, regD src) %{ | |
| 6009 single_instruction; | |
| 6010 dst : S4(write); | |
| 6011 src : S3(read); | |
| 6012 cr : S3(read); | |
| 6013 DECODE : S0; // any decoder | |
| 6014 %} | |
| 6015 | |
| 6016 // Float reg-reg operation | |
| 6017 pipe_class fpu_reg(regD dst) %{ | |
| 6018 instruction_count(2); | |
| 6019 dst : S3(read); | |
| 6020 DECODE : S0(2); // any 2 decoders | |
| 6021 FPU : S3; | |
| 6022 %} | |
| 6023 | |
| 6024 // Float reg-reg operation | |
| 6025 pipe_class fpu_reg_reg(regD dst, regD src) %{ | |
| 6026 instruction_count(2); | |
| 6027 dst : S4(write); | |
| 6028 src : S3(read); | |
| 6029 DECODE : S0(2); // any 2 decoders | |
| 6030 FPU : S3; | |
| 6031 %} | |
| 6032 | |
| 6033 // Float reg-reg operation | |
| 6034 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 6035 instruction_count(3); | |
| 6036 dst : S4(write); | |
| 6037 src1 : S3(read); | |
| 6038 src2 : S3(read); | |
| 6039 DECODE : S0(3); // any 3 decoders | |
| 6040 FPU : S3(2); | |
| 6041 %} | |
| 6042 | |
| 6043 // Float reg-reg operation | |
| 6044 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3) %{ | |
| 6045 instruction_count(4); | |
| 6046 dst : S4(write); | |
| 6047 src1 : S3(read); | |
| 6048 src2 : S3(read); | |
| 6049 src3 : S3(read); | |
| 6050 DECODE : S0(4); // any 3 decoders | |
| 6051 FPU : S3(2); | |
| 6052 %} | |
| 6053 | |
| 6054 // Float reg-reg operation | |
| 6055 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3) %{ | |
| 6056 instruction_count(4); | |
| 6057 dst : S4(write); | |
| 6058 src1 : S3(read); | |
| 6059 src2 : S3(read); | |
| 6060 src3 : S3(read); | |
| 6061 DECODE : S1(3); // any 3 decoders | |
| 6062 D0 : S0; // Big decoder only | |
| 6063 FPU : S3(2); | |
| 6064 MEM : S3; | |
| 6065 %} | |
| 6066 | |
| 6067 // Float reg-mem operation | |
| 6068 pipe_class fpu_reg_mem(regD dst, memory mem) %{ | |
| 6069 instruction_count(2); | |
| 6070 dst : S5(write); | |
| 6071 mem : S3(read); | |
| 6072 D0 : S0; // big decoder only | |
| 6073 DECODE : S1; // any decoder for FPU POP | |
| 6074 FPU : S4; | |
| 6075 MEM : S3; // any mem | |
| 6076 %} | |
| 6077 | |
| 6078 // Float reg-mem operation | |
| 6079 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem) %{ | |
| 6080 instruction_count(3); | |
| 6081 dst : S5(write); | |
| 6082 src1 : S3(read); | |
| 6083 mem : S3(read); | |
| 6084 D0 : S0; // big decoder only | |
| 6085 DECODE : S1(2); // any decoder for FPU POP | |
| 6086 FPU : S4; | |
| 6087 MEM : S3; // any mem | |
| 6088 %} | |
| 6089 | |
| 6090 // Float mem-reg operation | |
| 6091 pipe_class fpu_mem_reg(memory mem, regD src) %{ | |
| 6092 instruction_count(2); | |
| 6093 src : S5(read); | |
| 6094 mem : S3(read); | |
| 6095 DECODE : S0; // any decoder for FPU PUSH | |
| 6096 D0 : S1; // big decoder only | |
| 6097 FPU : S4; | |
| 6098 MEM : S3; // any mem | |
| 6099 %} | |
| 6100 | |
| 6101 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2) %{ | |
| 6102 instruction_count(3); | |
| 6103 src1 : S3(read); | |
| 6104 src2 : S3(read); | |
| 6105 mem : S3(read); | |
| 6106 DECODE : S0(2); // any decoder for FPU PUSH | |
| 6107 D0 : S1; // big decoder only | |
| 6108 FPU : S4; | |
| 6109 MEM : S3; // any mem | |
| 6110 %} | |
| 6111 | |
| 6112 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2) %{ | |
| 6113 instruction_count(3); | |
| 6114 src1 : S3(read); | |
| 6115 src2 : S3(read); | |
| 6116 mem : S4(read); | |
| 6117 DECODE : S0; // any decoder for FPU PUSH | |
| 6118 D0 : S0(2); // big decoder only | |
| 6119 FPU : S4; | |
| 6120 MEM : S3(2); // any mem | |
| 6121 %} | |
| 6122 | |
| 6123 pipe_class fpu_mem_mem(memory dst, memory src1) %{ | |
| 6124 instruction_count(2); | |
| 6125 src1 : S3(read); | |
| 6126 dst : S4(read); | |
| 6127 D0 : S0(2); // big decoder only | |
| 6128 MEM : S3(2); // any mem | |
| 6129 %} | |
| 6130 | |
| 6131 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{ | |
| 6132 instruction_count(3); | |
| 6133 src1 : S3(read); | |
| 6134 src2 : S3(read); | |
| 6135 dst : S4(read); | |
| 6136 D0 : S0(3); // big decoder only | |
| 6137 FPU : S4; | |
| 6138 MEM : S3(3); // any mem | |
| 6139 %} | |
| 6140 | |
| 6141 pipe_class fpu_mem_reg_con(memory mem, regD src1) %{ | |
| 6142 instruction_count(3); | |
| 6143 src1 : S4(read); | |
| 6144 mem : S4(read); | |
| 6145 DECODE : S0; // any decoder for FPU PUSH | |
| 6146 D0 : S0(2); // big decoder only | |
| 6147 FPU : S4; | |
| 6148 MEM : S3(2); // any mem | |
| 6149 %} | |
| 6150 | |
| 6151 // Float load constant | |
| 6152 pipe_class fpu_reg_con(regD dst) %{ | |
| 6153 instruction_count(2); | |
| 6154 dst : S5(write); | |
| 6155 D0 : S0; // big decoder only for the load | |
| 6156 DECODE : S1; // any decoder for FPU POP | |
| 6157 FPU : S4; | |
| 6158 MEM : S3; // any mem | |
| 6159 %} | |
| 6160 | |
| 6161 // Float load constant | |
| 6162 pipe_class fpu_reg_reg_con(regD dst, regD src) %{ | |
| 6163 instruction_count(3); | |
| 6164 dst : S5(write); | |
| 6165 src : S3(read); | |
| 6166 D0 : S0; // big decoder only for the load | |
| 6167 DECODE : S1(2); // any decoder for FPU POP | |
| 6168 FPU : S4; | |
| 6169 MEM : S3; // any mem | |
| 6170 %} | |
| 6171 | |
| 6172 // UnConditional branch | |
| 6173 pipe_class pipe_jmp( label labl ) %{ | |
| 6174 single_instruction; | |
| 6175 BR : S3; | |
| 6176 %} | |
| 6177 | |
| 6178 // Conditional branch | |
| 6179 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{ | |
| 6180 single_instruction; | |
| 6181 cr : S1(read); | |
| 6182 BR : S3; | |
| 6183 %} | |
| 6184 | |
| 6185 // Allocation idiom | |
| 6186 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{ | |
| 6187 instruction_count(1); force_serialization; | |
| 6188 fixed_latency(6); | |
| 6189 heap_ptr : S3(read); | |
| 6190 DECODE : S0(3); | |
| 6191 D0 : S2; | |
| 6192 MEM : S3; | |
| 6193 ALU : S3(2); | |
| 6194 dst : S5(write); | |
| 6195 BR : S5; | |
| 6196 %} | |
| 6197 | |
| 6198 // Generic big/slow expanded idiom | |
| 6199 pipe_class pipe_slow( ) %{ | |
| 6200 instruction_count(10); multiple_bundles; force_serialization; | |
| 6201 fixed_latency(100); | |
| 6202 D0 : S0(2); | |
| 6203 MEM : S3(2); | |
| 6204 %} | |
| 6205 | |
| 6206 // The real do-nothing guy | |
| 6207 pipe_class empty( ) %{ | |
| 6208 instruction_count(0); | |
| 6209 %} | |
| 6210 | |
| 6211 // Define the class for the Nop node | |
| 6212 define %{ | |
| 6213 MachNop = empty; | |
| 6214 %} | |
| 6215 | |
| 6216 %} | |
| 6217 | |
| 6218 //----------INSTRUCTIONS------------------------------------------------------- | |
| 6219 // | |
| 6220 // match -- States which machine-independent subtree may be replaced | |
| 6221 // by this instruction. | |
| 6222 // ins_cost -- The estimated cost of this instruction is used by instruction | |
| 6223 // selection to identify a minimum cost tree of machine | |
| 6224 // instructions that matches a tree of machine-independent | |
| 6225 // instructions. | |
| 6226 // format -- A string providing the disassembly for this instruction. | |
| 6227 // The value of an instruction's operand may be inserted | |
| 6228 // by referring to it with a '$' prefix. | |
| 6229 // opcode -- Three instruction opcodes may be provided. These are referred | |
| 6230 // to within an encode class as $primary, $secondary, and $tertiary | |
| 6231 // respectively. The primary opcode is commonly used to | |
| 6232 // indicate the type of machine instruction, while secondary | |
| 6233 // and tertiary are often used for prefix options or addressing | |
| 6234 // modes. | |
| 6235 // ins_encode -- A list of encode classes with parameters. The encode class | |
| 6236 // name must have been defined in an 'enc_class' specification | |
| 6237 // in the encode section of the architecture description. | |
| 6238 | |
| 6239 //----------BSWAP-Instruction-------------------------------------------------- | |
| 6240 instruct bytes_reverse_int(eRegI dst) %{ | |
| 6241 match(Set dst (ReverseBytesI dst)); | |
| 6242 | |
| 6243 format %{ "BSWAP $dst" %} | |
| 6244 opcode(0x0F, 0xC8); | |
| 6245 ins_encode( OpcP, OpcSReg(dst) ); | |
| 6246 ins_pipe( ialu_reg ); | |
| 6247 %} | |
| 6248 | |
| 6249 instruct bytes_reverse_long(eRegL dst) %{ | |
| 6250 match(Set dst (ReverseBytesL dst)); | |
| 6251 | |
| 6252 format %{ "BSWAP $dst.lo\n\t" | |
| 6253 "BSWAP $dst.hi\n\t" | |
| 6254 "XCHG $dst.lo $dst.hi" %} | |
| 6255 | |
| 6256 ins_cost(125); | |
| 6257 ins_encode( bswap_long_bytes(dst) ); | |
| 6258 ins_pipe( ialu_reg_reg); | |
| 6259 %} | |
| 6260 | |
|
1396
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|
6261 instruct bytes_reverse_unsigned_short(eRegI dst) %{ |
|
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|
6262 match(Set dst (ReverseBytesUS dst)); |
|
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|
6263 |
|
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|
6264 format %{ "BSWAP $dst\n\t" |
|
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|
6265 "SHR $dst,16\n\t" %} |
|
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|
6266 ins_encode %{ |
|
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|
6267 __ bswapl($dst$$Register); |
|
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|
6268 __ shrl($dst$$Register, 16); |
|
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|
6269 %} |
|
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|
6270 ins_pipe( ialu_reg ); |
|
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|
6271 %} |
|
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|
6272 |
|
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|
6273 instruct bytes_reverse_short(eRegI dst) %{ |
|
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|
6274 match(Set dst (ReverseBytesS dst)); |
|
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changeset
|
6275 |
|
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|
6276 format %{ "BSWAP $dst\n\t" |
|
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|
6277 "SAR $dst,16\n\t" %} |
|
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|
6278 ins_encode %{ |
|
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|
6279 __ bswapl($dst$$Register); |
|
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|
6280 __ sarl($dst$$Register, 16); |
|
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|
6281 %} |
|
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|
6282 ins_pipe( ialu_reg ); |
|
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|
6283 %} |
|
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|
6284 |
| 0 | 6285 |
|
775
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|
6286 //---------- Zeros Count Instructions ------------------------------------------ |
|
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|
6287 |
|
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|
6288 instruct countLeadingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{ |
|
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|
6289 predicate(UseCountLeadingZerosInstruction); |
|
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|
6290 match(Set dst (CountLeadingZerosI src)); |
|
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|
6291 effect(KILL cr); |
|
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|
6292 |
|
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|
6293 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %} |
|
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|
6294 ins_encode %{ |
|
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|
6295 __ lzcntl($dst$$Register, $src$$Register); |
|
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6296 %} |
|
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|
6297 ins_pipe(ialu_reg); |
|
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|
6298 %} |
|
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|
6299 |
|
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|
6300 instruct countLeadingZerosI_bsr(eRegI dst, eRegI src, eFlagsReg cr) %{ |
|
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|
6301 predicate(!UseCountLeadingZerosInstruction); |
|
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|
6302 match(Set dst (CountLeadingZerosI src)); |
|
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|
6303 effect(KILL cr); |
|
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|
6304 |
|
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|
6305 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t" |
|
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|
6306 "JNZ skip\n\t" |
|
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|
6307 "MOV $dst, -1\n" |
|
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|
6308 "skip:\n\t" |
|
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|
6309 "NEG $dst\n\t" |
|
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|
6310 "ADD $dst, 31" %} |
|
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|
6311 ins_encode %{ |
|
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|
6312 Register Rdst = $dst$$Register; |
|
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|
6313 Register Rsrc = $src$$Register; |
|
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|
6314 Label skip; |
|
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|
6315 __ bsrl(Rdst, Rsrc); |
|
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|
6316 __ jccb(Assembler::notZero, skip); |
|
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|
6317 __ movl(Rdst, -1); |
|
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|
6318 __ bind(skip); |
|
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|
6319 __ negl(Rdst); |
|
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|
6320 __ addl(Rdst, BitsPerInt - 1); |
|
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|
6321 %} |
|
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|
6322 ins_pipe(ialu_reg); |
|
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|
6323 %} |
|
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changeset
|
6324 |
|
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6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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|
6325 instruct countLeadingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{ |
|
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changeset
|
6326 predicate(UseCountLeadingZerosInstruction); |
|
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6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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681
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|
6327 match(Set dst (CountLeadingZerosL src)); |
|
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6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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|
6328 effect(TEMP dst, KILL cr); |
|
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6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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changeset
|
6329 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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681
diff
changeset
|
6330 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t" |
|
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6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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|
6331 "JNC done\n\t" |
|
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6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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|
6332 "LZCNT $dst, $src.lo\n\t" |
|
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6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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|
6333 "ADD $dst, 32\n" |
|
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6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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diff
changeset
|
6334 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6335 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6336 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6337 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6338 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6339 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6340 __ jccb(Assembler::carryClear, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6341 __ lzcntl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6342 __ addl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6343 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6344 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6345 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6346 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6347 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6348 instruct countLeadingZerosL_bsr(eRegI dst, eRegL src, eFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6349 predicate(!UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6350 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6351 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6352 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6353 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6354 "JZ msw_is_zero\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6355 "ADD $dst, 32\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6356 "JMP not_zero\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6357 "msw_is_zero:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6358 "BSR $dst, $src.lo\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6359 "JNZ not_zero\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6360 "MOV $dst, -1\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6361 "not_zero:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6362 "NEG $dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6363 "ADD $dst, 63\n" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6364 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6365 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6366 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6367 Label msw_is_zero; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6368 Label not_zero; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6369 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6370 __ jccb(Assembler::zero, msw_is_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6371 __ addl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6372 __ jmpb(not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6373 __ bind(msw_is_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6374 __ bsrl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6375 __ jccb(Assembler::notZero, not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6376 __ movl(Rdst, -1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6377 __ bind(not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6378 __ negl(Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6379 __ addl(Rdst, BitsPerLong - 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6380 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6381 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6382 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6383 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6384 instruct countTrailingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6385 match(Set dst (CountTrailingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6386 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6387 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6388 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6389 "JNZ done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6390 "MOV $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6391 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6392 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6393 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6394 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6395 __ bsfl(Rdst, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6396 __ jccb(Assembler::notZero, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6397 __ movl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6398 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6399 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6400 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6401 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6402 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6403 instruct countTrailingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6404 match(Set dst (CountTrailingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6405 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6406 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6407 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6408 "JNZ done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6409 "BSF $dst, $src.hi\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6410 "JNZ msw_not_zero\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6411 "MOV $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6412 "msw_not_zero:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6413 "ADD $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6414 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6415 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6416 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6417 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6418 Label msw_not_zero; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6419 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6420 __ bsfl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6421 __ jccb(Assembler::notZero, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6422 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6423 __ jccb(Assembler::notZero, msw_not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6424 __ movl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6425 __ bind(msw_not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6426 __ addl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6427 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6428 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6429 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6430 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6431 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6432 |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6433 //---------- Population Count Instructions ------------------------------------- |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6434 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6435 instruct popCountI(eRegI dst, eRegI src) %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6436 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
6437 match(Set dst (PopCountI src)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
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diff
changeset
|
6438 |
|
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|
6439 format %{ "POPCNT $dst, $src" %} |
|
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diff
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|
6440 ins_encode %{ |
|
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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624
diff
changeset
|
6441 __ popcntl($dst$$Register, $src$$Register); |
|
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diff
changeset
|
6442 %} |
|
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diff
changeset
|
6443 ins_pipe(ialu_reg); |
|
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624
diff
changeset
|
6444 %} |
|
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624
diff
changeset
|
6445 |
|
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diff
changeset
|
6446 instruct popCountI_mem(eRegI dst, memory mem) %{ |
|
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|
6447 predicate(UsePopCountInstruction); |
|
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|
6448 match(Set dst (PopCountI (LoadI mem))); |
|
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624
diff
changeset
|
6449 |
|
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parents:
624
diff
changeset
|
6450 format %{ "POPCNT $dst, $mem" %} |
|
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parents:
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diff
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|
6451 ins_encode %{ |
|
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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624
diff
changeset
|
6452 __ popcntl($dst$$Register, $mem$$Address); |
|
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diff
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|
6453 %} |
|
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diff
changeset
|
6454 ins_pipe(ialu_reg); |
|
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624
diff
changeset
|
6455 %} |
|
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624
diff
changeset
|
6456 |
|
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624
diff
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|
6457 // Note: Long.bitCount(long) returns an int. |
|
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|
6458 instruct popCountL(eRegI dst, eRegL src, eRegI tmp, eFlagsReg cr) %{ |
|
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|
6459 predicate(UsePopCountInstruction); |
|
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|
6460 match(Set dst (PopCountL src)); |
|
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diff
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|
6461 effect(KILL cr, TEMP tmp, TEMP dst); |
|
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diff
changeset
|
6462 |
|
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diff
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|
6463 format %{ "POPCNT $dst, $src.lo\n\t" |
|
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|
6464 "POPCNT $tmp, $src.hi\n\t" |
|
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|
6465 "ADD $dst, $tmp" %} |
|
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|
6466 ins_encode %{ |
|
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diff
changeset
|
6467 __ popcntl($dst$$Register, $src$$Register); |
|
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|
6468 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register)); |
|
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|
6469 __ addl($dst$$Register, $tmp$$Register); |
|
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diff
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|
6470 %} |
|
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diff
changeset
|
6471 ins_pipe(ialu_reg); |
|
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diff
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|
6472 %} |
|
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624
diff
changeset
|
6473 |
|
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|
6474 // Note: Long.bitCount(long) returns an int. |
|
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|
6475 instruct popCountL_mem(eRegI dst, memory mem, eRegI tmp, eFlagsReg cr) %{ |
|
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|
6476 predicate(UsePopCountInstruction); |
|
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|
6477 match(Set dst (PopCountL (LoadL mem))); |
|
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|
6478 effect(KILL cr, TEMP tmp, TEMP dst); |
|
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diff
changeset
|
6479 |
|
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diff
changeset
|
6480 format %{ "POPCNT $dst, $mem\n\t" |
|
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|
6481 "POPCNT $tmp, $mem+4\n\t" |
|
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|
6482 "ADD $dst, $tmp" %} |
|
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|
6483 ins_encode %{ |
|
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|
6484 //__ popcntl($dst$$Register, $mem$$Address$$first); |
|
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|
6485 //__ popcntl($tmp$$Register, $mem$$Address$$second); |
|
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|
6486 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false)); |
|
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|
6487 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false)); |
|
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|
6488 __ addl($dst$$Register, $tmp$$Register); |
|
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624
diff
changeset
|
6489 %} |
|
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624
diff
changeset
|
6490 ins_pipe(ialu_reg); |
|
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624
diff
changeset
|
6491 %} |
|
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624
diff
changeset
|
6492 |
|
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diff
changeset
|
6493 |
| 0 | 6494 //----------Load/Store/Move Instructions--------------------------------------- |
| 6495 //----------Load Instructions-------------------------------------------------- | |
| 6496 // Load Byte (8bit signed) | |
| 6497 instruct loadB(xRegI dst, memory mem) %{ | |
| 6498 match(Set dst (LoadB mem)); | |
| 6499 | |
| 6500 ins_cost(125); | |
| 624 | 6501 format %{ "MOVSX8 $dst,$mem\t# byte" %} |
| 6502 | |
| 6503 ins_encode %{ | |
| 6504 __ movsbl($dst$$Register, $mem$$Address); | |
| 6505 %} | |
| 6506 | |
| 6507 ins_pipe(ialu_reg_mem); | |
| 6508 %} | |
| 6509 | |
| 6510 // Load Byte (8bit signed) into Long Register | |
| 824 | 6511 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 6512 match(Set dst (ConvI2L (LoadB mem))); |
| 824 | 6513 effect(KILL cr); |
| 624 | 6514 |
| 6515 ins_cost(375); | |
| 6516 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t" | |
| 6517 "MOV $dst.hi,$dst.lo\n\t" | |
| 6518 "SAR $dst.hi,7" %} | |
| 6519 | |
| 6520 ins_encode %{ | |
| 6521 __ movsbl($dst$$Register, $mem$$Address); | |
| 6522 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. | |
| 6523 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended. | |
| 6524 %} | |
| 6525 | |
| 6526 ins_pipe(ialu_reg_mem); | |
| 6527 %} | |
| 6528 | |
| 6529 // Load Unsigned Byte (8bit UNsigned) | |
| 6530 instruct loadUB(xRegI dst, memory mem) %{ | |
| 6531 match(Set dst (LoadUB mem)); | |
| 0 | 6532 |
| 6533 ins_cost(125); | |
| 624 | 6534 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %} |
| 6535 | |
| 6536 ins_encode %{ | |
| 6537 __ movzbl($dst$$Register, $mem$$Address); | |
| 6538 %} | |
| 6539 | |
| 6540 ins_pipe(ialu_reg_mem); | |
| 6541 %} | |
| 6542 | |
| 6543 // Load Unsigned Byte (8 bit UNsigned) into Long Register | |
| 824 | 6544 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 6545 match(Set dst (ConvI2L (LoadUB mem))); |
| 824 | 6546 effect(KILL cr); |
| 624 | 6547 |
| 6548 ins_cost(250); | |
| 6549 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t" | |
| 6550 "XOR $dst.hi,$dst.hi" %} | |
| 6551 | |
| 6552 ins_encode %{ | |
| 824 | 6553 Register Rdst = $dst$$Register; |
| 6554 __ movzbl(Rdst, $mem$$Address); | |
| 6555 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 6556 %} | |
| 6557 | |
| 6558 ins_pipe(ialu_reg_mem); | |
| 6559 %} | |
| 6560 | |
| 6561 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register | |
| 6562 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{ | |
| 6563 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); | |
| 6564 effect(KILL cr); | |
| 6565 | |
| 6566 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t" | |
| 6567 "XOR $dst.hi,$dst.hi\n\t" | |
| 6568 "AND $dst.lo,$mask" %} | |
| 6569 ins_encode %{ | |
| 6570 Register Rdst = $dst$$Register; | |
| 6571 __ movzbl(Rdst, $mem$$Address); | |
| 6572 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 6573 __ andl(Rdst, $mask$$constant); | |
| 6574 %} | |
| 624 | 6575 ins_pipe(ialu_reg_mem); |
| 6576 %} | |
| 6577 | |
| 6578 // Load Short (16bit signed) | |
| 6579 instruct loadS(eRegI dst, memory mem) %{ | |
| 6580 match(Set dst (LoadS mem)); | |
| 6581 | |
| 6582 ins_cost(125); | |
| 6583 format %{ "MOVSX $dst,$mem\t# short" %} | |
| 6584 | |
| 6585 ins_encode %{ | |
| 6586 __ movswl($dst$$Register, $mem$$Address); | |
| 6587 %} | |
| 6588 | |
| 6589 ins_pipe(ialu_reg_mem); | |
| 6590 %} | |
| 6591 | |
| 785 | 6592 // Load Short (16 bit signed) to Byte (8 bit signed) |
| 6593 instruct loadS2B(eRegI dst, memory mem, immI_24 twentyfour) %{ | |
| 6594 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); | |
| 6595 | |
| 6596 ins_cost(125); | |
| 6597 format %{ "MOVSX $dst, $mem\t# short -> byte" %} | |
| 6598 ins_encode %{ | |
| 6599 __ movsbl($dst$$Register, $mem$$Address); | |
| 6600 %} | |
| 6601 ins_pipe(ialu_reg_mem); | |
| 6602 %} | |
| 6603 | |
| 624 | 6604 // Load Short (16bit signed) into Long Register |
| 824 | 6605 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 6606 match(Set dst (ConvI2L (LoadS mem))); |
| 824 | 6607 effect(KILL cr); |
| 624 | 6608 |
| 6609 ins_cost(375); | |
| 6610 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t" | |
| 6611 "MOV $dst.hi,$dst.lo\n\t" | |
| 6612 "SAR $dst.hi,15" %} | |
| 6613 | |
| 6614 ins_encode %{ | |
| 6615 __ movswl($dst$$Register, $mem$$Address); | |
| 6616 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. | |
| 6617 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended. | |
| 6618 %} | |
| 6619 | |
| 6620 ins_pipe(ialu_reg_mem); | |
| 0 | 6621 %} |
| 6622 | |
|
558
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
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parents:
420
diff
changeset
|
6623 // Load Unsigned Short/Char (16bit unsigned) |
|
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
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420
diff
changeset
|
6624 instruct loadUS(eRegI dst, memory mem) %{ |
|
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
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420
diff
changeset
|
6625 match(Set dst (LoadUS mem)); |
| 0 | 6626 |
| 6627 ins_cost(125); | |
| 624 | 6628 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %} |
| 6629 | |
| 6630 ins_encode %{ | |
| 6631 __ movzwl($dst$$Register, $mem$$Address); | |
| 6632 %} | |
| 6633 | |
| 6634 ins_pipe(ialu_reg_mem); | |
| 6635 %} | |
| 6636 | |
| 785 | 6637 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) |
| 6638 instruct loadUS2B(eRegI dst, memory mem, immI_24 twentyfour) %{ | |
| 6639 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); | |
| 6640 | |
| 6641 ins_cost(125); | |
| 6642 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %} | |
| 6643 ins_encode %{ | |
| 6644 __ movsbl($dst$$Register, $mem$$Address); | |
| 6645 %} | |
| 6646 ins_pipe(ialu_reg_mem); | |
| 6647 %} | |
| 6648 | |
| 624 | 6649 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register |
| 824 | 6650 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 6651 match(Set dst (ConvI2L (LoadUS mem))); |
| 824 | 6652 effect(KILL cr); |
| 624 | 6653 |
| 6654 ins_cost(250); | |
| 6655 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t" | |
| 6656 "XOR $dst.hi,$dst.hi" %} | |
| 6657 | |
| 6658 ins_encode %{ | |
| 6659 __ movzwl($dst$$Register, $mem$$Address); | |
| 6660 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register)); | |
| 6661 %} | |
| 6662 | |
| 6663 ins_pipe(ialu_reg_mem); | |
| 0 | 6664 %} |
| 6665 | |
| 824 | 6666 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register |
| 6667 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{ | |
| 6668 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 6669 effect(KILL cr); | |
| 6670 | |
| 6671 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t" | |
| 6672 "XOR $dst.hi,$dst.hi" %} | |
| 6673 ins_encode %{ | |
| 6674 Register Rdst = $dst$$Register; | |
| 6675 __ movzbl(Rdst, $mem$$Address); | |
| 6676 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 6677 %} | |
| 6678 ins_pipe(ialu_reg_mem); | |
| 6679 %} | |
| 6680 | |
| 6681 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register | |
| 6682 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{ | |
| 6683 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 6684 effect(KILL cr); | |
| 6685 | |
| 6686 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t" | |
| 6687 "XOR $dst.hi,$dst.hi\n\t" | |
| 6688 "AND $dst.lo,$mask" %} | |
| 6689 ins_encode %{ | |
| 6690 Register Rdst = $dst$$Register; | |
| 6691 __ movzwl(Rdst, $mem$$Address); | |
| 6692 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 6693 __ andl(Rdst, $mask$$constant); | |
| 6694 %} | |
| 6695 ins_pipe(ialu_reg_mem); | |
| 6696 %} | |
| 6697 | |
| 0 | 6698 // Load Integer |
| 6699 instruct loadI(eRegI dst, memory mem) %{ | |
| 6700 match(Set dst (LoadI mem)); | |
| 6701 | |
| 6702 ins_cost(125); | |
| 624 | 6703 format %{ "MOV $dst,$mem\t# int" %} |
| 6704 | |
| 6705 ins_encode %{ | |
| 6706 __ movl($dst$$Register, $mem$$Address); | |
| 6707 %} | |
| 6708 | |
| 6709 ins_pipe(ialu_reg_mem); | |
| 6710 %} | |
| 6711 | |
| 785 | 6712 // Load Integer (32 bit signed) to Byte (8 bit signed) |
| 6713 instruct loadI2B(eRegI dst, memory mem, immI_24 twentyfour) %{ | |
| 6714 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); | |
| 6715 | |
| 6716 ins_cost(125); | |
| 6717 format %{ "MOVSX $dst, $mem\t# int -> byte" %} | |
| 6718 ins_encode %{ | |
| 6719 __ movsbl($dst$$Register, $mem$$Address); | |
| 6720 %} | |
| 6721 ins_pipe(ialu_reg_mem); | |
| 6722 %} | |
| 6723 | |
| 6724 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned) | |
| 6725 instruct loadI2UB(eRegI dst, memory mem, immI_255 mask) %{ | |
| 6726 match(Set dst (AndI (LoadI mem) mask)); | |
| 6727 | |
| 6728 ins_cost(125); | |
| 6729 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %} | |
| 6730 ins_encode %{ | |
| 6731 __ movzbl($dst$$Register, $mem$$Address); | |
| 6732 %} | |
| 6733 ins_pipe(ialu_reg_mem); | |
| 6734 %} | |
| 6735 | |
| 6736 // Load Integer (32 bit signed) to Short (16 bit signed) | |
| 6737 instruct loadI2S(eRegI dst, memory mem, immI_16 sixteen) %{ | |
| 6738 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); | |
| 6739 | |
| 6740 ins_cost(125); | |
| 6741 format %{ "MOVSX $dst, $mem\t# int -> short" %} | |
| 6742 ins_encode %{ | |
| 6743 __ movswl($dst$$Register, $mem$$Address); | |
| 6744 %} | |
| 6745 ins_pipe(ialu_reg_mem); | |
| 6746 %} | |
| 6747 | |
| 6748 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned) | |
| 6749 instruct loadI2US(eRegI dst, memory mem, immI_65535 mask) %{ | |
| 6750 match(Set dst (AndI (LoadI mem) mask)); | |
| 6751 | |
| 6752 ins_cost(125); | |
| 6753 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %} | |
| 6754 ins_encode %{ | |
| 6755 __ movzwl($dst$$Register, $mem$$Address); | |
| 6756 %} | |
| 6757 ins_pipe(ialu_reg_mem); | |
| 6758 %} | |
| 6759 | |
| 624 | 6760 // Load Integer into Long Register |
| 824 | 6761 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 6762 match(Set dst (ConvI2L (LoadI mem))); |
| 824 | 6763 effect(KILL cr); |
| 624 | 6764 |
| 6765 ins_cost(375); | |
| 6766 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t" | |
| 6767 "MOV $dst.hi,$dst.lo\n\t" | |
| 6768 "SAR $dst.hi,31" %} | |
| 6769 | |
| 6770 ins_encode %{ | |
| 6771 __ movl($dst$$Register, $mem$$Address); | |
| 6772 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. | |
| 6773 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); | |
| 6774 %} | |
| 6775 | |
| 6776 ins_pipe(ialu_reg_mem); | |
| 6777 %} | |
| 6778 | |
| 824 | 6779 // Load Integer with mask 0xFF into Long Register |
| 6780 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{ | |
| 6781 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 6782 effect(KILL cr); | |
| 6783 | |
| 6784 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t" | |
| 6785 "XOR $dst.hi,$dst.hi" %} | |
| 6786 ins_encode %{ | |
| 6787 Register Rdst = $dst$$Register; | |
| 6788 __ movzbl(Rdst, $mem$$Address); | |
| 6789 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 6790 %} | |
| 6791 ins_pipe(ialu_reg_mem); | |
| 6792 %} | |
| 6793 | |
| 6794 // Load Integer with mask 0xFFFF into Long Register | |
| 6795 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{ | |
| 6796 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 6797 effect(KILL cr); | |
| 6798 | |
| 6799 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t" | |
| 6800 "XOR $dst.hi,$dst.hi" %} | |
| 6801 ins_encode %{ | |
| 6802 Register Rdst = $dst$$Register; | |
| 6803 __ movzwl(Rdst, $mem$$Address); | |
| 6804 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 6805 %} | |
| 6806 ins_pipe(ialu_reg_mem); | |
| 6807 %} | |
| 6808 | |
| 6809 // Load Integer with 32-bit mask into Long Register | |
| 6810 instruct loadI2L_immI(eRegL dst, memory mem, immI mask, eFlagsReg cr) %{ | |
| 6811 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 6812 effect(KILL cr); | |
| 6813 | |
| 6814 format %{ "MOV $dst.lo,$mem\t# int & 32-bit mask -> long\n\t" | |
| 6815 "XOR $dst.hi,$dst.hi\n\t" | |
| 6816 "AND $dst.lo,$mask" %} | |
| 6817 ins_encode %{ | |
| 6818 Register Rdst = $dst$$Register; | |
| 6819 __ movl(Rdst, $mem$$Address); | |
| 6820 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 6821 __ andl(Rdst, $mask$$constant); | |
| 6822 %} | |
| 6823 ins_pipe(ialu_reg_mem); | |
| 6824 %} | |
| 6825 | |
| 624 | 6826 // Load Unsigned Integer into Long Register |
| 824 | 6827 instruct loadUI2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 6828 match(Set dst (LoadUI2L mem)); |
| 824 | 6829 effect(KILL cr); |
| 624 | 6830 |
| 6831 ins_cost(250); | |
| 6832 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t" | |
| 6833 "XOR $dst.hi,$dst.hi" %} | |
| 6834 | |
| 6835 ins_encode %{ | |
| 6836 __ movl($dst$$Register, $mem$$Address); | |
| 6837 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register)); | |
| 6838 %} | |
| 6839 | |
| 6840 ins_pipe(ialu_reg_mem); | |
| 0 | 6841 %} |
| 6842 | |
| 6843 // Load Long. Cannot clobber address while loading, so restrict address | |
| 6844 // register to ESI | |
| 6845 instruct loadL(eRegL dst, load_long_memory mem) %{ | |
| 6846 predicate(!((LoadLNode*)n)->require_atomic_access()); | |
| 6847 match(Set dst (LoadL mem)); | |
| 6848 | |
| 6849 ins_cost(250); | |
| 624 | 6850 format %{ "MOV $dst.lo,$mem\t# long\n\t" |
| 0 | 6851 "MOV $dst.hi,$mem+4" %} |
| 624 | 6852 |
| 6853 ins_encode %{ | |
| 6854 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false); | |
| 6855 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false); | |
| 6856 __ movl($dst$$Register, Amemlo); | |
| 6857 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi); | |
| 6858 %} | |
| 6859 | |
| 6860 ins_pipe(ialu_reg_long_mem); | |
| 0 | 6861 %} |
| 6862 | |
| 6863 // Volatile Load Long. Must be atomic, so do 64-bit FILD | |
| 6864 // then store it down to the stack and reload on the int | |
| 6865 // side. | |
| 6866 instruct loadL_volatile(stackSlotL dst, memory mem) %{ | |
| 6867 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access()); | |
| 6868 match(Set dst (LoadL mem)); | |
| 6869 | |
| 6870 ins_cost(200); | |
| 6871 format %{ "FILD $mem\t# Atomic volatile long load\n\t" | |
| 6872 "FISTp $dst" %} | |
| 6873 ins_encode(enc_loadL_volatile(mem,dst)); | |
| 6874 ins_pipe( fpu_reg_mem ); | |
| 6875 %} | |
| 6876 | |
| 6877 instruct loadLX_volatile(stackSlotL dst, memory mem, regXD tmp) %{ | |
| 6878 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access()); | |
| 6879 match(Set dst (LoadL mem)); | |
| 6880 effect(TEMP tmp); | |
| 6881 ins_cost(180); | |
| 6882 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" | |
| 6883 "MOVSD $dst,$tmp" %} | |
| 6884 ins_encode(enc_loadLX_volatile(mem, dst, tmp)); | |
| 6885 ins_pipe( pipe_slow ); | |
| 6886 %} | |
| 6887 | |
| 6888 instruct loadLX_reg_volatile(eRegL dst, memory mem, regXD tmp) %{ | |
| 6889 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access()); | |
| 6890 match(Set dst (LoadL mem)); | |
| 6891 effect(TEMP tmp); | |
| 6892 ins_cost(160); | |
| 6893 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" | |
| 6894 "MOVD $dst.lo,$tmp\n\t" | |
| 6895 "PSRLQ $tmp,32\n\t" | |
| 6896 "MOVD $dst.hi,$tmp" %} | |
| 6897 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp)); | |
| 6898 ins_pipe( pipe_slow ); | |
| 6899 %} | |
| 6900 | |
| 6901 // Load Range | |
| 6902 instruct loadRange(eRegI dst, memory mem) %{ | |
| 6903 match(Set dst (LoadRange mem)); | |
| 6904 | |
| 6905 ins_cost(125); | |
| 6906 format %{ "MOV $dst,$mem" %} | |
| 6907 opcode(0x8B); | |
| 6908 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6909 ins_pipe( ialu_reg_mem ); | |
| 6910 %} | |
| 6911 | |
| 6912 | |
| 6913 // Load Pointer | |
| 6914 instruct loadP(eRegP dst, memory mem) %{ | |
| 6915 match(Set dst (LoadP mem)); | |
| 6916 | |
| 6917 ins_cost(125); | |
| 6918 format %{ "MOV $dst,$mem" %} | |
| 6919 opcode(0x8B); | |
| 6920 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6921 ins_pipe( ialu_reg_mem ); | |
| 6922 %} | |
| 6923 | |
| 6924 // Load Klass Pointer | |
| 6925 instruct loadKlass(eRegP dst, memory mem) %{ | |
| 6926 match(Set dst (LoadKlass mem)); | |
| 6927 | |
| 6928 ins_cost(125); | |
| 6929 format %{ "MOV $dst,$mem" %} | |
| 6930 opcode(0x8B); | |
| 6931 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6932 ins_pipe( ialu_reg_mem ); | |
| 6933 %} | |
| 6934 | |
| 6935 // Load Double | |
| 6936 instruct loadD(regD dst, memory mem) %{ | |
| 6937 predicate(UseSSE<=1); | |
| 6938 match(Set dst (LoadD mem)); | |
| 6939 | |
| 6940 ins_cost(150); | |
| 6941 format %{ "FLD_D ST,$mem\n\t" | |
| 6942 "FSTP $dst" %} | |
| 6943 opcode(0xDD); /* DD /0 */ | |
| 6944 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
| 6945 Pop_Reg_D(dst) ); | |
| 6946 ins_pipe( fpu_reg_mem ); | |
| 6947 %} | |
| 6948 | |
| 6949 // Load Double to XMM | |
| 6950 instruct loadXD(regXD dst, memory mem) %{ | |
| 6951 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper); | |
| 6952 match(Set dst (LoadD mem)); | |
| 6953 ins_cost(145); | |
| 6954 format %{ "MOVSD $dst,$mem" %} | |
| 6955 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem)); | |
| 6956 ins_pipe( pipe_slow ); | |
| 6957 %} | |
| 6958 | |
| 6959 instruct loadXD_partial(regXD dst, memory mem) %{ | |
| 6960 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper); | |
| 6961 match(Set dst (LoadD mem)); | |
| 6962 ins_cost(145); | |
| 6963 format %{ "MOVLPD $dst,$mem" %} | |
| 6964 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,mem)); | |
| 6965 ins_pipe( pipe_slow ); | |
| 6966 %} | |
| 6967 | |
| 6968 // Load to XMM register (single-precision floating point) | |
| 6969 // MOVSS instruction | |
| 6970 instruct loadX(regX dst, memory mem) %{ | |
| 6971 predicate(UseSSE>=1); | |
| 6972 match(Set dst (LoadF mem)); | |
| 6973 ins_cost(145); | |
| 6974 format %{ "MOVSS $dst,$mem" %} | |
| 6975 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem)); | |
| 6976 ins_pipe( pipe_slow ); | |
| 6977 %} | |
| 6978 | |
| 6979 // Load Float | |
| 6980 instruct loadF(regF dst, memory mem) %{ | |
| 6981 predicate(UseSSE==0); | |
| 6982 match(Set dst (LoadF mem)); | |
| 6983 | |
| 6984 ins_cost(150); | |
| 6985 format %{ "FLD_S ST,$mem\n\t" | |
| 6986 "FSTP $dst" %} | |
| 6987 opcode(0xD9); /* D9 /0 */ | |
| 6988 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
| 6989 Pop_Reg_F(dst) ); | |
| 6990 ins_pipe( fpu_reg_mem ); | |
| 6991 %} | |
| 6992 | |
| 6993 // Load Aligned Packed Byte to XMM register | |
| 6994 instruct loadA8B(regXD dst, memory mem) %{ | |
| 6995 predicate(UseSSE>=1); | |
| 6996 match(Set dst (Load8B mem)); | |
| 6997 ins_cost(125); | |
| 6998 format %{ "MOVQ $dst,$mem\t! packed8B" %} | |
| 6999 ins_encode( movq_ld(dst, mem)); | |
| 7000 ins_pipe( pipe_slow ); | |
| 7001 %} | |
| 7002 | |
| 7003 // Load Aligned Packed Short to XMM register | |
| 7004 instruct loadA4S(regXD dst, memory mem) %{ | |
| 7005 predicate(UseSSE>=1); | |
| 7006 match(Set dst (Load4S mem)); | |
| 7007 ins_cost(125); | |
| 7008 format %{ "MOVQ $dst,$mem\t! packed4S" %} | |
| 7009 ins_encode( movq_ld(dst, mem)); | |
| 7010 ins_pipe( pipe_slow ); | |
| 7011 %} | |
| 7012 | |
| 7013 // Load Aligned Packed Char to XMM register | |
| 7014 instruct loadA4C(regXD dst, memory mem) %{ | |
| 7015 predicate(UseSSE>=1); | |
| 7016 match(Set dst (Load4C mem)); | |
| 7017 ins_cost(125); | |
| 7018 format %{ "MOVQ $dst,$mem\t! packed4C" %} | |
| 7019 ins_encode( movq_ld(dst, mem)); | |
| 7020 ins_pipe( pipe_slow ); | |
| 7021 %} | |
| 7022 | |
| 7023 // Load Aligned Packed Integer to XMM register | |
| 7024 instruct load2IU(regXD dst, memory mem) %{ | |
| 7025 predicate(UseSSE>=1); | |
| 7026 match(Set dst (Load2I mem)); | |
| 7027 ins_cost(125); | |
| 7028 format %{ "MOVQ $dst,$mem\t! packed2I" %} | |
| 7029 ins_encode( movq_ld(dst, mem)); | |
| 7030 ins_pipe( pipe_slow ); | |
| 7031 %} | |
| 7032 | |
| 7033 // Load Aligned Packed Single to XMM | |
| 7034 instruct loadA2F(regXD dst, memory mem) %{ | |
| 7035 predicate(UseSSE>=1); | |
| 7036 match(Set dst (Load2F mem)); | |
| 7037 ins_cost(145); | |
| 7038 format %{ "MOVQ $dst,$mem\t! packed2F" %} | |
| 7039 ins_encode( movq_ld(dst, mem)); | |
| 7040 ins_pipe( pipe_slow ); | |
| 7041 %} | |
| 7042 | |
| 7043 // Load Effective Address | |
| 7044 instruct leaP8(eRegP dst, indOffset8 mem) %{ | |
| 7045 match(Set dst mem); | |
| 7046 | |
| 7047 ins_cost(110); | |
| 7048 format %{ "LEA $dst,$mem" %} | |
| 7049 opcode(0x8D); | |
| 7050 ins_encode( OpcP, RegMem(dst,mem)); | |
| 7051 ins_pipe( ialu_reg_reg_fat ); | |
| 7052 %} | |
| 7053 | |
| 7054 instruct leaP32(eRegP dst, indOffset32 mem) %{ | |
| 7055 match(Set dst mem); | |
| 7056 | |
| 7057 ins_cost(110); | |
| 7058 format %{ "LEA $dst,$mem" %} | |
| 7059 opcode(0x8D); | |
| 7060 ins_encode( OpcP, RegMem(dst,mem)); | |
| 7061 ins_pipe( ialu_reg_reg_fat ); | |
| 7062 %} | |
| 7063 | |
| 7064 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{ | |
| 7065 match(Set dst mem); | |
| 7066 | |
| 7067 ins_cost(110); | |
| 7068 format %{ "LEA $dst,$mem" %} | |
| 7069 opcode(0x8D); | |
| 7070 ins_encode( OpcP, RegMem(dst,mem)); | |
| 7071 ins_pipe( ialu_reg_reg_fat ); | |
| 7072 %} | |
| 7073 | |
| 7074 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{ | |
| 7075 match(Set dst mem); | |
| 7076 | |
| 7077 ins_cost(110); | |
| 7078 format %{ "LEA $dst,$mem" %} | |
| 7079 opcode(0x8D); | |
| 7080 ins_encode( OpcP, RegMem(dst,mem)); | |
| 7081 ins_pipe( ialu_reg_reg_fat ); | |
| 7082 %} | |
| 7083 | |
| 7084 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{ | |
| 7085 match(Set dst mem); | |
| 7086 | |
| 7087 ins_cost(110); | |
| 7088 format %{ "LEA $dst,$mem" %} | |
| 7089 opcode(0x8D); | |
| 7090 ins_encode( OpcP, RegMem(dst,mem)); | |
| 7091 ins_pipe( ialu_reg_reg_fat ); | |
| 7092 %} | |
| 7093 | |
| 7094 // Load Constant | |
| 7095 instruct loadConI(eRegI dst, immI src) %{ | |
| 7096 match(Set dst src); | |
| 7097 | |
| 7098 format %{ "MOV $dst,$src" %} | |
| 7099 ins_encode( LdImmI(dst, src) ); | |
| 7100 ins_pipe( ialu_reg_fat ); | |
| 7101 %} | |
| 7102 | |
| 7103 // Load Constant zero | |
| 7104 instruct loadConI0(eRegI dst, immI0 src, eFlagsReg cr) %{ | |
| 7105 match(Set dst src); | |
| 7106 effect(KILL cr); | |
| 7107 | |
| 7108 ins_cost(50); | |
| 7109 format %{ "XOR $dst,$dst" %} | |
| 7110 opcode(0x33); /* + rd */ | |
| 7111 ins_encode( OpcP, RegReg( dst, dst ) ); | |
| 7112 ins_pipe( ialu_reg ); | |
| 7113 %} | |
| 7114 | |
| 7115 instruct loadConP(eRegP dst, immP src) %{ | |
| 7116 match(Set dst src); | |
| 7117 | |
| 7118 format %{ "MOV $dst,$src" %} | |
| 7119 opcode(0xB8); /* + rd */ | |
| 7120 ins_encode( LdImmP(dst, src) ); | |
| 7121 ins_pipe( ialu_reg_fat ); | |
| 7122 %} | |
| 7123 | |
| 7124 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 7125 match(Set dst src); | |
| 7126 effect(KILL cr); | |
| 7127 ins_cost(200); | |
| 7128 format %{ "MOV $dst.lo,$src.lo\n\t" | |
| 7129 "MOV $dst.hi,$src.hi" %} | |
| 7130 opcode(0xB8); | |
| 7131 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) ); | |
| 7132 ins_pipe( ialu_reg_long_fat ); | |
| 7133 %} | |
| 7134 | |
| 7135 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{ | |
| 7136 match(Set dst src); | |
| 7137 effect(KILL cr); | |
| 7138 ins_cost(150); | |
| 7139 format %{ "XOR $dst.lo,$dst.lo\n\t" | |
| 7140 "XOR $dst.hi,$dst.hi" %} | |
| 7141 opcode(0x33,0x33); | |
| 7142 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) ); | |
| 7143 ins_pipe( ialu_reg_long ); | |
| 7144 %} | |
| 7145 | |
| 7146 // The instruction usage is guarded by predicate in operand immF(). | |
| 2008 | 7147 instruct loadConF(regF dst, immF con) %{ |
| 7148 match(Set dst con); | |
| 7149 ins_cost(125); | |
| 7150 format %{ "FLD_S ST,[$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 7151 "FSTP $dst" %} | |
| 7152 ins_encode %{ | |
| 7153 __ fld_s($constantaddress($con)); | |
| 7154 __ fstp_d($dst$$reg); | |
| 7155 %} | |
| 7156 ins_pipe(fpu_reg_con); | |
| 7157 %} | |
| 7158 | |
| 7159 // The instruction usage is guarded by predicate in operand immF0(). | |
| 7160 instruct loadConF0(regF dst, immF0 con) %{ | |
| 7161 match(Set dst con); | |
| 0 | 7162 ins_cost(125); |
| 2008 | 7163 format %{ "FLDZ ST\n\t" |
| 0 | 7164 "FSTP $dst" %} |
| 2008 | 7165 ins_encode %{ |
| 7166 __ fldz(); | |
| 7167 __ fstp_d($dst$$reg); | |
| 7168 %} | |
| 7169 ins_pipe(fpu_reg_con); | |
| 7170 %} | |
| 7171 | |
| 7172 // The instruction usage is guarded by predicate in operand immF1(). | |
| 7173 instruct loadConF1(regF dst, immF1 con) %{ | |
| 7174 match(Set dst con); | |
| 7175 ins_cost(125); | |
| 7176 format %{ "FLD1 ST\n\t" | |
| 7177 "FSTP $dst" %} | |
| 7178 ins_encode %{ | |
| 7179 __ fld1(); | |
| 7180 __ fstp_d($dst$$reg); | |
| 7181 %} | |
| 7182 ins_pipe(fpu_reg_con); | |
| 0 | 7183 %} |
| 7184 | |
| 7185 // The instruction usage is guarded by predicate in operand immXF(). | |
| 7186 instruct loadConX(regX dst, immXF con) %{ | |
| 7187 match(Set dst con); | |
| 7188 ins_cost(125); | |
| 2008 | 7189 format %{ "MOVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %} |
| 7190 ins_encode %{ | |
| 7191 __ movflt($dst$$XMMRegister, $constantaddress($con)); | |
| 7192 %} | |
| 7193 ins_pipe(pipe_slow); | |
| 0 | 7194 %} |
| 7195 | |
| 7196 // The instruction usage is guarded by predicate in operand immXF0(). | |
| 7197 instruct loadConX0(regX dst, immXF0 src) %{ | |
| 7198 match(Set dst src); | |
| 7199 ins_cost(100); | |
| 7200 format %{ "XORPS $dst,$dst\t# float 0.0" %} | |
| 2008 | 7201 ins_encode %{ |
| 7202 __ xorps($dst$$XMMRegister, $dst$$XMMRegister); | |
| 7203 %} | |
| 7204 ins_pipe(pipe_slow); | |
| 0 | 7205 %} |
| 7206 | |
| 7207 // The instruction usage is guarded by predicate in operand immD(). | |
| 2008 | 7208 instruct loadConD(regD dst, immD con) %{ |
| 7209 match(Set dst con); | |
| 7210 ins_cost(125); | |
| 7211 | |
| 7212 format %{ "FLD_D ST,[$constantaddress]\t# load from constant table: double=$con\n\t" | |
| 7213 "FSTP $dst" %} | |
| 7214 ins_encode %{ | |
| 7215 __ fld_d($constantaddress($con)); | |
| 7216 __ fstp_d($dst$$reg); | |
| 7217 %} | |
| 7218 ins_pipe(fpu_reg_con); | |
| 7219 %} | |
| 7220 | |
| 7221 // The instruction usage is guarded by predicate in operand immD0(). | |
| 7222 instruct loadConD0(regD dst, immD0 con) %{ | |
| 7223 match(Set dst con); | |
| 0 | 7224 ins_cost(125); |
| 7225 | |
| 2008 | 7226 format %{ "FLDZ ST\n\t" |
| 0 | 7227 "FSTP $dst" %} |
| 2008 | 7228 ins_encode %{ |
| 7229 __ fldz(); | |
| 7230 __ fstp_d($dst$$reg); | |
| 7231 %} | |
| 7232 ins_pipe(fpu_reg_con); | |
| 7233 %} | |
| 7234 | |
| 7235 // The instruction usage is guarded by predicate in operand immD1(). | |
| 7236 instruct loadConD1(regD dst, immD1 con) %{ | |
| 7237 match(Set dst con); | |
| 7238 ins_cost(125); | |
| 7239 | |
| 7240 format %{ "FLD1 ST\n\t" | |
| 7241 "FSTP $dst" %} | |
| 7242 ins_encode %{ | |
| 7243 __ fld1(); | |
| 7244 __ fstp_d($dst$$reg); | |
| 7245 %} | |
| 7246 ins_pipe(fpu_reg_con); | |
| 0 | 7247 %} |
| 7248 | |
| 7249 // The instruction usage is guarded by predicate in operand immXD(). | |
| 7250 instruct loadConXD(regXD dst, immXD con) %{ | |
| 7251 match(Set dst con); | |
| 7252 ins_cost(125); | |
| 2008 | 7253 format %{ "MOVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %} |
| 7254 ins_encode %{ | |
| 7255 __ movdbl($dst$$XMMRegister, $constantaddress($con)); | |
| 7256 %} | |
| 7257 ins_pipe(pipe_slow); | |
| 0 | 7258 %} |
| 7259 | |
| 7260 // The instruction usage is guarded by predicate in operand immXD0(). | |
| 7261 instruct loadConXD0(regXD dst, immXD0 src) %{ | |
| 7262 match(Set dst src); | |
| 7263 ins_cost(100); | |
| 7264 format %{ "XORPD $dst,$dst\t# double 0.0" %} | |
| 7265 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x57), RegReg(dst,dst)); | |
| 7266 ins_pipe( pipe_slow ); | |
| 7267 %} | |
| 7268 | |
| 7269 // Load Stack Slot | |
| 7270 instruct loadSSI(eRegI dst, stackSlotI src) %{ | |
| 7271 match(Set dst src); | |
| 7272 ins_cost(125); | |
| 7273 | |
| 7274 format %{ "MOV $dst,$src" %} | |
| 7275 opcode(0x8B); | |
| 7276 ins_encode( OpcP, RegMem(dst,src)); | |
| 7277 ins_pipe( ialu_reg_mem ); | |
| 7278 %} | |
| 7279 | |
| 7280 instruct loadSSL(eRegL dst, stackSlotL src) %{ | |
| 7281 match(Set dst src); | |
| 7282 | |
| 7283 ins_cost(200); | |
| 7284 format %{ "MOV $dst,$src.lo\n\t" | |
| 7285 "MOV $dst+4,$src.hi" %} | |
| 7286 opcode(0x8B, 0x8B); | |
| 7287 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) ); | |
| 7288 ins_pipe( ialu_mem_long_reg ); | |
| 7289 %} | |
| 7290 | |
| 7291 // Load Stack Slot | |
| 7292 instruct loadSSP(eRegP dst, stackSlotP src) %{ | |
| 7293 match(Set dst src); | |
| 7294 ins_cost(125); | |
| 7295 | |
| 7296 format %{ "MOV $dst,$src" %} | |
| 7297 opcode(0x8B); | |
| 7298 ins_encode( OpcP, RegMem(dst,src)); | |
| 7299 ins_pipe( ialu_reg_mem ); | |
| 7300 %} | |
| 7301 | |
| 7302 // Load Stack Slot | |
| 7303 instruct loadSSF(regF dst, stackSlotF src) %{ | |
| 7304 match(Set dst src); | |
| 7305 ins_cost(125); | |
| 7306 | |
| 7307 format %{ "FLD_S $src\n\t" | |
| 7308 "FSTP $dst" %} | |
| 7309 opcode(0xD9); /* D9 /0, FLD m32real */ | |
| 7310 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
| 7311 Pop_Reg_F(dst) ); | |
| 7312 ins_pipe( fpu_reg_mem ); | |
| 7313 %} | |
| 7314 | |
| 7315 // Load Stack Slot | |
| 7316 instruct loadSSD(regD dst, stackSlotD src) %{ | |
| 7317 match(Set dst src); | |
| 7318 ins_cost(125); | |
| 7319 | |
| 7320 format %{ "FLD_D $src\n\t" | |
| 7321 "FSTP $dst" %} | |
| 7322 opcode(0xDD); /* DD /0, FLD m64real */ | |
| 7323 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
| 7324 Pop_Reg_D(dst) ); | |
| 7325 ins_pipe( fpu_reg_mem ); | |
| 7326 %} | |
| 7327 | |
| 7328 // Prefetch instructions. | |
| 7329 // Must be safe to execute with invalid address (cannot fault). | |
| 7330 | |
| 7331 instruct prefetchr0( memory mem ) %{ | |
| 7332 predicate(UseSSE==0 && !VM_Version::supports_3dnow()); | |
| 7333 match(PrefetchRead mem); | |
| 7334 ins_cost(0); | |
| 7335 size(0); | |
| 7336 format %{ "PREFETCHR (non-SSE is empty encoding)" %} | |
| 7337 ins_encode(); | |
| 7338 ins_pipe(empty); | |
| 7339 %} | |
| 7340 | |
| 7341 instruct prefetchr( memory mem ) %{ | |
| 7342 predicate(UseSSE==0 && VM_Version::supports_3dnow() || ReadPrefetchInstr==3); | |
| 7343 match(PrefetchRead mem); | |
| 7344 ins_cost(100); | |
| 7345 | |
| 7346 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %} | |
| 7347 opcode(0x0F, 0x0d); /* Opcode 0F 0d /0 */ | |
| 7348 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem)); | |
| 7349 ins_pipe(ialu_mem); | |
| 7350 %} | |
| 7351 | |
| 7352 instruct prefetchrNTA( memory mem ) %{ | |
| 7353 predicate(UseSSE>=1 && ReadPrefetchInstr==0); | |
| 7354 match(PrefetchRead mem); | |
| 7355 ins_cost(100); | |
| 7356 | |
| 7357 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %} | |
| 7358 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */ | |
| 7359 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem)); | |
| 7360 ins_pipe(ialu_mem); | |
| 7361 %} | |
| 7362 | |
| 7363 instruct prefetchrT0( memory mem ) %{ | |
| 7364 predicate(UseSSE>=1 && ReadPrefetchInstr==1); | |
| 7365 match(PrefetchRead mem); | |
| 7366 ins_cost(100); | |
| 7367 | |
| 7368 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %} | |
| 7369 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */ | |
| 7370 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem)); | |
| 7371 ins_pipe(ialu_mem); | |
| 7372 %} | |
| 7373 | |
| 7374 instruct prefetchrT2( memory mem ) %{ | |
| 7375 predicate(UseSSE>=1 && ReadPrefetchInstr==2); | |
| 7376 match(PrefetchRead mem); | |
| 7377 ins_cost(100); | |
| 7378 | |
| 7379 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %} | |
| 7380 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */ | |
| 7381 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem)); | |
| 7382 ins_pipe(ialu_mem); | |
| 7383 %} | |
| 7384 | |
| 7385 instruct prefetchw0( memory mem ) %{ | |
| 7386 predicate(UseSSE==0 && !VM_Version::supports_3dnow()); | |
| 7387 match(PrefetchWrite mem); | |
| 7388 ins_cost(0); | |
| 7389 size(0); | |
| 7390 format %{ "Prefetch (non-SSE is empty encoding)" %} | |
| 7391 ins_encode(); | |
| 7392 ins_pipe(empty); | |
| 7393 %} | |
| 7394 | |
| 7395 instruct prefetchw( memory mem ) %{ | |
| 7396 predicate(UseSSE==0 && VM_Version::supports_3dnow() || AllocatePrefetchInstr==3); | |
| 7397 match( PrefetchWrite mem ); | |
| 7398 ins_cost(100); | |
| 7399 | |
| 7400 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %} | |
| 7401 opcode(0x0F, 0x0D); /* Opcode 0F 0D /1 */ | |
| 7402 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem)); | |
| 7403 ins_pipe(ialu_mem); | |
| 7404 %} | |
| 7405 | |
| 7406 instruct prefetchwNTA( memory mem ) %{ | |
| 7407 predicate(UseSSE>=1 && AllocatePrefetchInstr==0); | |
| 7408 match(PrefetchWrite mem); | |
| 7409 ins_cost(100); | |
| 7410 | |
| 7411 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %} | |
| 7412 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */ | |
| 7413 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem)); | |
| 7414 ins_pipe(ialu_mem); | |
| 7415 %} | |
| 7416 | |
| 7417 instruct prefetchwT0( memory mem ) %{ | |
| 7418 predicate(UseSSE>=1 && AllocatePrefetchInstr==1); | |
| 7419 match(PrefetchWrite mem); | |
| 7420 ins_cost(100); | |
| 7421 | |
| 7422 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for write" %} | |
| 7423 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */ | |
| 7424 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem)); | |
| 7425 ins_pipe(ialu_mem); | |
| 7426 %} | |
| 7427 | |
| 7428 instruct prefetchwT2( memory mem ) %{ | |
| 7429 predicate(UseSSE>=1 && AllocatePrefetchInstr==2); | |
| 7430 match(PrefetchWrite mem); | |
| 7431 ins_cost(100); | |
| 7432 | |
| 7433 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for write" %} | |
| 7434 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */ | |
| 7435 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem)); | |
| 7436 ins_pipe(ialu_mem); | |
| 7437 %} | |
| 7438 | |
| 7439 //----------Store Instructions------------------------------------------------- | |
| 7440 | |
| 7441 // Store Byte | |
| 7442 instruct storeB(memory mem, xRegI src) %{ | |
| 7443 match(Set mem (StoreB mem src)); | |
| 7444 | |
| 7445 ins_cost(125); | |
| 7446 format %{ "MOV8 $mem,$src" %} | |
| 7447 opcode(0x88); | |
| 7448 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 7449 ins_pipe( ialu_mem_reg ); | |
| 7450 %} | |
| 7451 | |
| 7452 // Store Char/Short | |
| 7453 instruct storeC(memory mem, eRegI src) %{ | |
| 7454 match(Set mem (StoreC mem src)); | |
| 7455 | |
| 7456 ins_cost(125); | |
| 7457 format %{ "MOV16 $mem,$src" %} | |
| 7458 opcode(0x89, 0x66); | |
| 7459 ins_encode( OpcS, OpcP, RegMem( src, mem ) ); | |
| 7460 ins_pipe( ialu_mem_reg ); | |
| 7461 %} | |
| 7462 | |
| 7463 // Store Integer | |
| 7464 instruct storeI(memory mem, eRegI src) %{ | |
| 7465 match(Set mem (StoreI mem src)); | |
| 7466 | |
| 7467 ins_cost(125); | |
| 7468 format %{ "MOV $mem,$src" %} | |
| 7469 opcode(0x89); | |
| 7470 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 7471 ins_pipe( ialu_mem_reg ); | |
| 7472 %} | |
| 7473 | |
| 7474 // Store Long | |
| 7475 instruct storeL(long_memory mem, eRegL src) %{ | |
| 7476 predicate(!((StoreLNode*)n)->require_atomic_access()); | |
| 7477 match(Set mem (StoreL mem src)); | |
| 7478 | |
| 7479 ins_cost(200); | |
| 7480 format %{ "MOV $mem,$src.lo\n\t" | |
| 7481 "MOV $mem+4,$src.hi" %} | |
| 7482 opcode(0x89, 0x89); | |
| 7483 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) ); | |
| 7484 ins_pipe( ialu_mem_long_reg ); | |
| 7485 %} | |
| 7486 | |
| 824 | 7487 // Store Long to Integer |
| 7488 instruct storeL2I(memory mem, eRegL src) %{ | |
| 7489 match(Set mem (StoreI mem (ConvL2I src))); | |
| 7490 | |
| 7491 format %{ "MOV $mem,$src.lo\t# long -> int" %} | |
| 7492 ins_encode %{ | |
| 7493 __ movl($mem$$Address, $src$$Register); | |
| 7494 %} | |
| 7495 ins_pipe(ialu_mem_reg); | |
| 7496 %} | |
| 7497 | |
| 0 | 7498 // Volatile Store Long. Must be atomic, so move it into |
| 7499 // the FP TOS and then do a 64-bit FIST. Has to probe the | |
| 7500 // target address before the store (for null-ptr checks) | |
| 7501 // so the memory operand is used twice in the encoding. | |
| 7502 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{ | |
| 7503 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access()); | |
| 7504 match(Set mem (StoreL mem src)); | |
| 7505 effect( KILL cr ); | |
| 7506 ins_cost(400); | |
| 7507 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" | |
| 7508 "FILD $src\n\t" | |
| 7509 "FISTp $mem\t # 64-bit atomic volatile long store" %} | |
| 7510 opcode(0x3B); | |
| 7511 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src)); | |
| 7512 ins_pipe( fpu_reg_mem ); | |
| 7513 %} | |
| 7514 | |
| 7515 instruct storeLX_volatile(memory mem, stackSlotL src, regXD tmp, eFlagsReg cr) %{ | |
| 7516 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access()); | |
| 7517 match(Set mem (StoreL mem src)); | |
| 7518 effect( TEMP tmp, KILL cr ); | |
| 7519 ins_cost(380); | |
| 7520 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" | |
| 7521 "MOVSD $tmp,$src\n\t" | |
| 7522 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %} | |
| 7523 opcode(0x3B); | |
| 7524 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_volatile(mem, src, tmp)); | |
| 7525 ins_pipe( pipe_slow ); | |
| 7526 %} | |
| 7527 | |
| 7528 instruct storeLX_reg_volatile(memory mem, eRegL src, regXD tmp2, regXD tmp, eFlagsReg cr) %{ | |
| 7529 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access()); | |
| 7530 match(Set mem (StoreL mem src)); | |
| 7531 effect( TEMP tmp2 , TEMP tmp, KILL cr ); | |
| 7532 ins_cost(360); | |
| 7533 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" | |
| 7534 "MOVD $tmp,$src.lo\n\t" | |
| 7535 "MOVD $tmp2,$src.hi\n\t" | |
| 7536 "PUNPCKLDQ $tmp,$tmp2\n\t" | |
| 7537 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %} | |
| 7538 opcode(0x3B); | |
| 7539 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_reg_volatile(mem, src, tmp, tmp2)); | |
| 7540 ins_pipe( pipe_slow ); | |
| 7541 %} | |
| 7542 | |
| 7543 // Store Pointer; for storing unknown oops and raw pointers | |
| 7544 instruct storeP(memory mem, anyRegP src) %{ | |
| 7545 match(Set mem (StoreP mem src)); | |
| 7546 | |
| 7547 ins_cost(125); | |
| 7548 format %{ "MOV $mem,$src" %} | |
| 7549 opcode(0x89); | |
| 7550 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 7551 ins_pipe( ialu_mem_reg ); | |
| 7552 %} | |
| 7553 | |
| 7554 // Store Integer Immediate | |
| 7555 instruct storeImmI(memory mem, immI src) %{ | |
| 7556 match(Set mem (StoreI mem src)); | |
| 7557 | |
| 7558 ins_cost(150); | |
| 7559 format %{ "MOV $mem,$src" %} | |
| 7560 opcode(0xC7); /* C7 /0 */ | |
| 7561 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src )); | |
| 7562 ins_pipe( ialu_mem_imm ); | |
| 7563 %} | |
| 7564 | |
| 7565 // Store Short/Char Immediate | |
| 7566 instruct storeImmI16(memory mem, immI16 src) %{ | |
| 7567 predicate(UseStoreImmI16); | |
| 7568 match(Set mem (StoreC mem src)); | |
| 7569 | |
| 7570 ins_cost(150); | |
| 7571 format %{ "MOV16 $mem,$src" %} | |
| 7572 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */ | |
| 7573 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src )); | |
| 7574 ins_pipe( ialu_mem_imm ); | |
| 7575 %} | |
| 7576 | |
| 7577 // Store Pointer Immediate; null pointers or constant oops that do not | |
| 7578 // need card-mark barriers. | |
| 7579 instruct storeImmP(memory mem, immP src) %{ | |
| 7580 match(Set mem (StoreP mem src)); | |
| 7581 | |
| 7582 ins_cost(150); | |
| 7583 format %{ "MOV $mem,$src" %} | |
| 7584 opcode(0xC7); /* C7 /0 */ | |
| 7585 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src )); | |
| 7586 ins_pipe( ialu_mem_imm ); | |
| 7587 %} | |
| 7588 | |
| 7589 // Store Byte Immediate | |
| 7590 instruct storeImmB(memory mem, immI8 src) %{ | |
| 7591 match(Set mem (StoreB mem src)); | |
| 7592 | |
| 7593 ins_cost(150); | |
| 7594 format %{ "MOV8 $mem,$src" %} | |
| 7595 opcode(0xC6); /* C6 /0 */ | |
| 7596 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src )); | |
| 7597 ins_pipe( ialu_mem_imm ); | |
| 7598 %} | |
| 7599 | |
| 7600 // Store Aligned Packed Byte XMM register to memory | |
| 7601 instruct storeA8B(memory mem, regXD src) %{ | |
| 7602 predicate(UseSSE>=1); | |
| 7603 match(Set mem (Store8B mem src)); | |
| 7604 ins_cost(145); | |
| 7605 format %{ "MOVQ $mem,$src\t! packed8B" %} | |
| 7606 ins_encode( movq_st(mem, src)); | |
| 7607 ins_pipe( pipe_slow ); | |
| 7608 %} | |
| 7609 | |
| 7610 // Store Aligned Packed Char/Short XMM register to memory | |
| 7611 instruct storeA4C(memory mem, regXD src) %{ | |
| 7612 predicate(UseSSE>=1); | |
| 7613 match(Set mem (Store4C mem src)); | |
| 7614 ins_cost(145); | |
| 7615 format %{ "MOVQ $mem,$src\t! packed4C" %} | |
| 7616 ins_encode( movq_st(mem, src)); | |
| 7617 ins_pipe( pipe_slow ); | |
| 7618 %} | |
| 7619 | |
| 7620 // Store Aligned Packed Integer XMM register to memory | |
| 7621 instruct storeA2I(memory mem, regXD src) %{ | |
| 7622 predicate(UseSSE>=1); | |
| 7623 match(Set mem (Store2I mem src)); | |
| 7624 ins_cost(145); | |
| 7625 format %{ "MOVQ $mem,$src\t! packed2I" %} | |
| 7626 ins_encode( movq_st(mem, src)); | |
| 7627 ins_pipe( pipe_slow ); | |
| 7628 %} | |
| 7629 | |
| 7630 // Store CMS card-mark Immediate | |
| 7631 instruct storeImmCM(memory mem, immI8 src) %{ | |
| 7632 match(Set mem (StoreCM mem src)); | |
| 7633 | |
| 7634 ins_cost(150); | |
| 7635 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %} | |
| 7636 opcode(0xC6); /* C6 /0 */ | |
| 7637 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src )); | |
| 7638 ins_pipe( ialu_mem_imm ); | |
| 7639 %} | |
| 7640 | |
| 7641 // Store Double | |
| 7642 instruct storeD( memory mem, regDPR1 src) %{ | |
| 7643 predicate(UseSSE<=1); | |
| 7644 match(Set mem (StoreD mem src)); | |
| 7645 | |
| 7646 ins_cost(100); | |
| 7647 format %{ "FST_D $mem,$src" %} | |
| 7648 opcode(0xDD); /* DD /2 */ | |
| 7649 ins_encode( enc_FP_store(mem,src) ); | |
| 7650 ins_pipe( fpu_mem_reg ); | |
| 7651 %} | |
| 7652 | |
| 7653 // Store double does rounding on x86 | |
| 7654 instruct storeD_rounded( memory mem, regDPR1 src) %{ | |
| 7655 predicate(UseSSE<=1); | |
| 7656 match(Set mem (StoreD mem (RoundDouble src))); | |
| 7657 | |
| 7658 ins_cost(100); | |
| 7659 format %{ "FST_D $mem,$src\t# round" %} | |
| 7660 opcode(0xDD); /* DD /2 */ | |
| 7661 ins_encode( enc_FP_store(mem,src) ); | |
| 7662 ins_pipe( fpu_mem_reg ); | |
| 7663 %} | |
| 7664 | |
| 7665 // Store XMM register to memory (double-precision floating points) | |
| 7666 // MOVSD instruction | |
| 7667 instruct storeXD(memory mem, regXD src) %{ | |
| 7668 predicate(UseSSE>=2); | |
| 7669 match(Set mem (StoreD mem src)); | |
| 7670 ins_cost(95); | |
| 7671 format %{ "MOVSD $mem,$src" %} | |
| 7672 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src, mem)); | |
| 7673 ins_pipe( pipe_slow ); | |
| 7674 %} | |
| 7675 | |
| 7676 // Store XMM register to memory (single-precision floating point) | |
| 7677 // MOVSS instruction | |
| 7678 instruct storeX(memory mem, regX src) %{ | |
| 7679 predicate(UseSSE>=1); | |
| 7680 match(Set mem (StoreF mem src)); | |
| 7681 ins_cost(95); | |
| 7682 format %{ "MOVSS $mem,$src" %} | |
| 7683 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, mem)); | |
| 7684 ins_pipe( pipe_slow ); | |
| 7685 %} | |
| 7686 | |
| 7687 // Store Aligned Packed Single Float XMM register to memory | |
| 7688 instruct storeA2F(memory mem, regXD src) %{ | |
| 7689 predicate(UseSSE>=1); | |
| 7690 match(Set mem (Store2F mem src)); | |
| 7691 ins_cost(145); | |
| 7692 format %{ "MOVQ $mem,$src\t! packed2F" %} | |
| 7693 ins_encode( movq_st(mem, src)); | |
| 7694 ins_pipe( pipe_slow ); | |
| 7695 %} | |
| 7696 | |
| 7697 // Store Float | |
| 7698 instruct storeF( memory mem, regFPR1 src) %{ | |
| 7699 predicate(UseSSE==0); | |
| 7700 match(Set mem (StoreF mem src)); | |
| 7701 | |
| 7702 ins_cost(100); | |
| 7703 format %{ "FST_S $mem,$src" %} | |
| 7704 opcode(0xD9); /* D9 /2 */ | |
| 7705 ins_encode( enc_FP_store(mem,src) ); | |
| 7706 ins_pipe( fpu_mem_reg ); | |
| 7707 %} | |
| 7708 | |
| 7709 // Store Float does rounding on x86 | |
| 7710 instruct storeF_rounded( memory mem, regFPR1 src) %{ | |
| 7711 predicate(UseSSE==0); | |
| 7712 match(Set mem (StoreF mem (RoundFloat src))); | |
| 7713 | |
| 7714 ins_cost(100); | |
| 7715 format %{ "FST_S $mem,$src\t# round" %} | |
| 7716 opcode(0xD9); /* D9 /2 */ | |
| 7717 ins_encode( enc_FP_store(mem,src) ); | |
| 7718 ins_pipe( fpu_mem_reg ); | |
| 7719 %} | |
| 7720 | |
| 7721 // Store Float does rounding on x86 | |
| 7722 instruct storeF_Drounded( memory mem, regDPR1 src) %{ | |
| 7723 predicate(UseSSE<=1); | |
| 7724 match(Set mem (StoreF mem (ConvD2F src))); | |
| 7725 | |
| 7726 ins_cost(100); | |
| 7727 format %{ "FST_S $mem,$src\t# D-round" %} | |
| 7728 opcode(0xD9); /* D9 /2 */ | |
| 7729 ins_encode( enc_FP_store(mem,src) ); | |
| 7730 ins_pipe( fpu_mem_reg ); | |
| 7731 %} | |
| 7732 | |
| 7733 // Store immediate Float value (it is faster than store from FPU register) | |
| 7734 // The instruction usage is guarded by predicate in operand immF(). | |
| 7735 instruct storeF_imm( memory mem, immF src) %{ | |
| 7736 match(Set mem (StoreF mem src)); | |
| 7737 | |
| 7738 ins_cost(50); | |
| 7739 format %{ "MOV $mem,$src\t# store float" %} | |
| 7740 opcode(0xC7); /* C7 /0 */ | |
| 7741 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src )); | |
| 7742 ins_pipe( ialu_mem_imm ); | |
| 7743 %} | |
| 7744 | |
| 7745 // Store immediate Float value (it is faster than store from XMM register) | |
| 7746 // The instruction usage is guarded by predicate in operand immXF(). | |
| 7747 instruct storeX_imm( memory mem, immXF src) %{ | |
| 7748 match(Set mem (StoreF mem src)); | |
| 7749 | |
| 7750 ins_cost(50); | |
| 7751 format %{ "MOV $mem,$src\t# store float" %} | |
| 7752 opcode(0xC7); /* C7 /0 */ | |
| 7753 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32XF_as_bits( src )); | |
| 7754 ins_pipe( ialu_mem_imm ); | |
| 7755 %} | |
| 7756 | |
| 7757 // Store Integer to stack slot | |
| 7758 instruct storeSSI(stackSlotI dst, eRegI src) %{ | |
| 7759 match(Set dst src); | |
| 7760 | |
| 7761 ins_cost(100); | |
| 7762 format %{ "MOV $dst,$src" %} | |
| 7763 opcode(0x89); | |
| 7764 ins_encode( OpcPRegSS( dst, src ) ); | |
| 7765 ins_pipe( ialu_mem_reg ); | |
| 7766 %} | |
| 7767 | |
| 7768 // Store Integer to stack slot | |
| 7769 instruct storeSSP(stackSlotP dst, eRegP src) %{ | |
| 7770 match(Set dst src); | |
| 7771 | |
| 7772 ins_cost(100); | |
| 7773 format %{ "MOV $dst,$src" %} | |
| 7774 opcode(0x89); | |
| 7775 ins_encode( OpcPRegSS( dst, src ) ); | |
| 7776 ins_pipe( ialu_mem_reg ); | |
| 7777 %} | |
| 7778 | |
| 7779 // Store Long to stack slot | |
| 7780 instruct storeSSL(stackSlotL dst, eRegL src) %{ | |
| 7781 match(Set dst src); | |
| 7782 | |
| 7783 ins_cost(200); | |
| 7784 format %{ "MOV $dst,$src.lo\n\t" | |
| 7785 "MOV $dst+4,$src.hi" %} | |
| 7786 opcode(0x89, 0x89); | |
| 7787 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) ); | |
| 7788 ins_pipe( ialu_mem_long_reg ); | |
| 7789 %} | |
| 7790 | |
| 7791 //----------MemBar Instructions----------------------------------------------- | |
| 7792 // Memory barrier flavors | |
| 7793 | |
| 7794 instruct membar_acquire() %{ | |
| 7795 match(MemBarAcquire); | |
| 7796 ins_cost(400); | |
| 7797 | |
| 7798 size(0); | |
|
671
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diff
changeset
|
7799 format %{ "MEMBAR-acquire ! (empty encoding)" %} |
|
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6822204: volatile fences should prefer lock:addl to actual mfence instructions
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647
diff
changeset
|
7800 ins_encode(); |
|
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diff
changeset
|
7801 ins_pipe(empty); |
| 0 | 7802 %} |
| 7803 | |
| 7804 instruct membar_acquire_lock() %{ | |
| 7805 match(MemBarAcquire); | |
| 7806 predicate(Matcher::prior_fast_lock(n)); | |
| 7807 ins_cost(0); | |
| 7808 | |
| 7809 size(0); | |
| 7810 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %} | |
| 7811 ins_encode( ); | |
| 7812 ins_pipe(empty); | |
| 7813 %} | |
| 7814 | |
| 7815 instruct membar_release() %{ | |
| 7816 match(MemBarRelease); | |
| 7817 ins_cost(400); | |
| 7818 | |
| 7819 size(0); | |
|
671
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changeset
|
7820 format %{ "MEMBAR-release ! (empty encoding)" %} |
|
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6822204: volatile fences should prefer lock:addl to actual mfence instructions
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647
diff
changeset
|
7821 ins_encode( ); |
|
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never
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diff
changeset
|
7822 ins_pipe(empty); |
| 0 | 7823 %} |
| 7824 | |
| 7825 instruct membar_release_lock() %{ | |
| 7826 match(MemBarRelease); | |
| 7827 predicate(Matcher::post_fast_unlock(n)); | |
| 7828 ins_cost(0); | |
| 7829 | |
| 7830 size(0); | |
| 7831 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %} | |
| 7832 ins_encode( ); | |
| 7833 ins_pipe(empty); | |
| 7834 %} | |
| 7835 | |
|
671
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6822204: volatile fences should prefer lock:addl to actual mfence instructions
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diff
changeset
|
7836 instruct membar_volatile(eFlagsReg cr) %{ |
| 0 | 7837 match(MemBarVolatile); |
|
671
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diff
changeset
|
7838 effect(KILL cr); |
| 0 | 7839 ins_cost(400); |
| 7840 | |
|
671
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diff
changeset
|
7841 format %{ |
|
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6822204: volatile fences should prefer lock:addl to actual mfence instructions
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diff
changeset
|
7842 $$template |
|
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6822204: volatile fences should prefer lock:addl to actual mfence instructions
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diff
changeset
|
7843 if (os::is_MP()) { |
|
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6822204: volatile fences should prefer lock:addl to actual mfence instructions
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diff
changeset
|
7844 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile" |
|
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6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7845 } else { |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
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647
diff
changeset
|
7846 $$emit$$"MEMBAR-volatile ! (empty encoding)" |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7847 } |
|
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6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7848 %} |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7849 ins_encode %{ |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7850 __ membar(Assembler::StoreLoad); |
|
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6822204: volatile fences should prefer lock:addl to actual mfence instructions
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647
diff
changeset
|
7851 %} |
| 0 | 7852 ins_pipe(pipe_slow); |
| 7853 %} | |
| 7854 | |
| 7855 instruct unnecessary_membar_volatile() %{ | |
| 7856 match(MemBarVolatile); | |
| 7857 predicate(Matcher::post_store_load_barrier(n)); | |
| 7858 ins_cost(0); | |
| 7859 | |
| 7860 size(0); | |
| 7861 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %} | |
| 7862 ins_encode( ); | |
| 7863 ins_pipe(empty); | |
| 7864 %} | |
| 7865 | |
| 7866 //----------Move Instructions-------------------------------------------------- | |
| 7867 instruct castX2P(eAXRegP dst, eAXRegI src) %{ | |
| 7868 match(Set dst (CastX2P src)); | |
| 7869 format %{ "# X2P $dst, $src" %} | |
| 7870 ins_encode( /*empty encoding*/ ); | |
| 7871 ins_cost(0); | |
| 7872 ins_pipe(empty); | |
| 7873 %} | |
| 7874 | |
| 7875 instruct castP2X(eRegI dst, eRegP src ) %{ | |
| 7876 match(Set dst (CastP2X src)); | |
| 7877 ins_cost(50); | |
| 7878 format %{ "MOV $dst, $src\t# CastP2X" %} | |
| 7879 ins_encode( enc_Copy( dst, src) ); | |
| 7880 ins_pipe( ialu_reg_reg ); | |
| 7881 %} | |
| 7882 | |
| 7883 //----------Conditional Move--------------------------------------------------- | |
| 7884 // Conditional move | |
| 7885 instruct cmovI_reg(eRegI dst, eRegI src, eFlagsReg cr, cmpOp cop ) %{ | |
| 7886 predicate(VM_Version::supports_cmov() ); | |
| 7887 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 7888 ins_cost(200); | |
| 7889 format %{ "CMOV$cop $dst,$src" %} | |
| 7890 opcode(0x0F,0x40); | |
| 7891 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 7892 ins_pipe( pipe_cmov_reg ); | |
| 7893 %} | |
| 7894 | |
|
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diff
changeset
|
7895 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, eRegI dst, eRegI src ) %{ |
| 0 | 7896 predicate(VM_Version::supports_cmov() ); |
| 7897 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 7898 ins_cost(200); | |
| 7899 format %{ "CMOV$cop $dst,$src" %} | |
| 7900 opcode(0x0F,0x40); | |
| 7901 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 7902 ins_pipe( pipe_cmov_reg ); | |
| 7903 %} | |
| 7904 | |
|
415
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diff
changeset
|
7905 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, eRegI src ) %{ |
|
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diff
changeset
|
7906 predicate(VM_Version::supports_cmov() ); |
|
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diff
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|
7907 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
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403
diff
changeset
|
7908 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
7909 expand %{ |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
7910 cmovI_regU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7911 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
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diff
changeset
|
7912 %} |
|
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6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
7913 |
| 0 | 7914 // Conditional move |
| 7915 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, eRegI dst, memory src) %{ | |
| 7916 predicate(VM_Version::supports_cmov() ); | |
| 7917 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); | |
| 7918 ins_cost(250); | |
| 7919 format %{ "CMOV$cop $dst,$src" %} | |
| 7920 opcode(0x0F,0x40); | |
| 7921 ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 7922 ins_pipe( pipe_cmov_mem ); | |
| 7923 %} | |
| 7924 | |
| 7925 // Conditional move | |
|
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diff
changeset
|
7926 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, eRegI dst, memory src) %{ |
| 0 | 7927 predicate(VM_Version::supports_cmov() ); |
| 7928 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); | |
| 7929 ins_cost(250); | |
| 7930 format %{ "CMOV$cop $dst,$src" %} | |
| 7931 opcode(0x0F,0x40); | |
| 7932 ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 7933 ins_pipe( pipe_cmov_mem ); | |
| 7934 %} | |
| 7935 | |
|
415
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diff
changeset
|
7936 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, memory src) %{ |
|
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diff
changeset
|
7937 predicate(VM_Version::supports_cmov() ); |
|
4d9884b01ba6
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diff
changeset
|
7938 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); |
|
4d9884b01ba6
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403
diff
changeset
|
7939 ins_cost(250); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7940 expand %{ |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
7941 cmovI_memU(cop, cr, dst, src); |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
7942 %} |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
7943 %} |
|
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parents:
403
diff
changeset
|
7944 |
| 0 | 7945 // Conditional move |
| 7946 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{ | |
| 7947 predicate(VM_Version::supports_cmov() ); | |
| 7948 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 7949 ins_cost(200); | |
| 7950 format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 7951 opcode(0x0F,0x40); | |
| 7952 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 7953 ins_pipe( pipe_cmov_reg ); | |
| 7954 %} | |
| 7955 | |
| 7956 // Conditional move (non-P6 version) | |
| 7957 // Note: a CMoveP is generated for stubs and native wrappers | |
| 7958 // regardless of whether we are on a P6, so we | |
| 7959 // emulate a cmov here | |
| 7960 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{ | |
| 7961 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 7962 ins_cost(300); | |
| 7963 format %{ "Jn$cop skip\n\t" | |
| 7964 "MOV $dst,$src\t# pointer\n" | |
| 7965 "skip:" %} | |
| 7966 opcode(0x8b); | |
| 7967 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src)); | |
| 7968 ins_pipe( pipe_cmov_reg ); | |
| 7969 %} | |
| 7970 | |
| 7971 // Conditional move | |
|
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diff
changeset
|
7972 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{ |
| 0 | 7973 predicate(VM_Version::supports_cmov() ); |
| 7974 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 7975 ins_cost(200); | |
| 7976 format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 7977 opcode(0x0F,0x40); | |
| 7978 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 7979 ins_pipe( pipe_cmov_reg ); | |
| 7980 %} | |
| 7981 | |
|
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diff
changeset
|
7982 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{ |
|
4d9884b01ba6
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diff
changeset
|
7983 predicate(VM_Version::supports_cmov() ); |
|
4d9884b01ba6
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diff
changeset
|
7984 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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403
diff
changeset
|
7985 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7986 expand %{ |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7987 cmovP_regU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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403
diff
changeset
|
7988 %} |
|
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diff
changeset
|
7989 %} |
|
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diff
changeset
|
7990 |
| 0 | 7991 // DISABLED: Requires the ADLC to emit a bottom_type call that |
| 7992 // correctly meets the two pointer arguments; one is an incoming | |
| 7993 // register but the other is a memory operand. ALSO appears to | |
| 7994 // be buggy with implicit null checks. | |
| 7995 // | |
| 7996 //// Conditional move | |
| 7997 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{ | |
| 7998 // predicate(VM_Version::supports_cmov() ); | |
| 7999 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 8000 // ins_cost(250); | |
| 8001 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 8002 // opcode(0x0F,0x40); | |
| 8003 // ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 8004 // ins_pipe( pipe_cmov_mem ); | |
| 8005 //%} | |
| 8006 // | |
| 8007 //// Conditional move | |
| 8008 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{ | |
| 8009 // predicate(VM_Version::supports_cmov() ); | |
| 8010 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 8011 // ins_cost(250); | |
| 8012 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 8013 // opcode(0x0F,0x40); | |
| 8014 // ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 8015 // ins_pipe( pipe_cmov_mem ); | |
| 8016 //%} | |
| 8017 | |
| 8018 // Conditional move | |
| 8019 instruct fcmovD_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regD src) %{ | |
| 8020 predicate(UseSSE<=1); | |
| 8021 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 8022 ins_cost(200); | |
| 8023 format %{ "FCMOV$cop $dst,$src\t# double" %} | |
| 8024 opcode(0xDA); | |
| 8025 ins_encode( enc_cmov_d(cop,src) ); | |
| 8026 ins_pipe( pipe_cmovD_reg ); | |
| 8027 %} | |
| 8028 | |
| 8029 // Conditional move | |
| 8030 instruct fcmovF_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regF src) %{ | |
| 8031 predicate(UseSSE==0); | |
| 8032 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 8033 ins_cost(200); | |
| 8034 format %{ "FCMOV$cop $dst,$src\t# float" %} | |
| 8035 opcode(0xDA); | |
| 8036 ins_encode( enc_cmov_d(cop,src) ); | |
| 8037 ins_pipe( pipe_cmovD_reg ); | |
| 8038 %} | |
| 8039 | |
| 8040 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned. | |
| 8041 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{ | |
| 8042 predicate(UseSSE<=1); | |
| 8043 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 8044 ins_cost(200); | |
| 8045 format %{ "Jn$cop skip\n\t" | |
| 8046 "MOV $dst,$src\t# double\n" | |
| 8047 "skip:" %} | |
| 8048 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */ | |
| 8049 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_D(src), OpcP, RegOpc(dst) ); | |
| 8050 ins_pipe( pipe_cmovD_reg ); | |
| 8051 %} | |
| 8052 | |
| 8053 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned. | |
| 8054 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{ | |
| 8055 predicate(UseSSE==0); | |
| 8056 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 8057 ins_cost(200); | |
| 8058 format %{ "Jn$cop skip\n\t" | |
| 8059 "MOV $dst,$src\t# float\n" | |
| 8060 "skip:" %} | |
| 8061 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */ | |
| 8062 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_F(src), OpcP, RegOpc(dst) ); | |
| 8063 ins_pipe( pipe_cmovD_reg ); | |
| 8064 %} | |
| 8065 | |
| 8066 // No CMOVE with SSE/SSE2 | |
| 8067 instruct fcmovX_regS(cmpOp cop, eFlagsReg cr, regX dst, regX src) %{ | |
| 8068 predicate (UseSSE>=1); | |
| 8069 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 8070 ins_cost(200); | |
| 8071 format %{ "Jn$cop skip\n\t" | |
| 8072 "MOVSS $dst,$src\t# float\n" | |
| 8073 "skip:" %} | |
| 8074 ins_encode %{ | |
| 8075 Label skip; | |
| 8076 // Invert sense of branch from sense of CMOV | |
| 8077 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 8078 __ movflt($dst$$XMMRegister, $src$$XMMRegister); | |
| 8079 __ bind(skip); | |
| 8080 %} | |
| 8081 ins_pipe( pipe_slow ); | |
| 8082 %} | |
| 8083 | |
| 8084 // No CMOVE with SSE/SSE2 | |
| 8085 instruct fcmovXD_regS(cmpOp cop, eFlagsReg cr, regXD dst, regXD src) %{ | |
| 8086 predicate (UseSSE>=2); | |
| 8087 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 8088 ins_cost(200); | |
| 8089 format %{ "Jn$cop skip\n\t" | |
| 8090 "MOVSD $dst,$src\t# float\n" | |
| 8091 "skip:" %} | |
| 8092 ins_encode %{ | |
| 8093 Label skip; | |
| 8094 // Invert sense of branch from sense of CMOV | |
| 8095 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 8096 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); | |
| 8097 __ bind(skip); | |
| 8098 %} | |
| 8099 ins_pipe( pipe_slow ); | |
| 8100 %} | |
| 8101 | |
| 8102 // unsigned version | |
| 8103 instruct fcmovX_regU(cmpOpU cop, eFlagsRegU cr, regX dst, regX src) %{ | |
| 8104 predicate (UseSSE>=1); | |
| 8105 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 8106 ins_cost(200); | |
| 8107 format %{ "Jn$cop skip\n\t" | |
| 8108 "MOVSS $dst,$src\t# float\n" | |
| 8109 "skip:" %} | |
| 8110 ins_encode %{ | |
| 8111 Label skip; | |
| 8112 // Invert sense of branch from sense of CMOV | |
| 8113 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 8114 __ movflt($dst$$XMMRegister, $src$$XMMRegister); | |
| 8115 __ bind(skip); | |
| 8116 %} | |
| 8117 ins_pipe( pipe_slow ); | |
| 8118 %} | |
| 8119 | |
|
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8120 instruct fcmovX_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regX dst, regX src) %{ |
|
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|
8121 predicate (UseSSE>=1); |
|
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|
8122 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); |
|
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|
8123 ins_cost(200); |
|
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|
8124 expand %{ |
|
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|
8125 fcmovX_regU(cop, cr, dst, src); |
|
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|
8126 %} |
|
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|
8127 %} |
|
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|
8128 |
| 0 | 8129 // unsigned version |
| 8130 instruct fcmovXD_regU(cmpOpU cop, eFlagsRegU cr, regXD dst, regXD src) %{ | |
| 8131 predicate (UseSSE>=2); | |
| 8132 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 8133 ins_cost(200); | |
| 8134 format %{ "Jn$cop skip\n\t" | |
| 8135 "MOVSD $dst,$src\t# float\n" | |
| 8136 "skip:" %} | |
| 8137 ins_encode %{ | |
| 8138 Label skip; | |
| 8139 // Invert sense of branch from sense of CMOV | |
| 8140 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 8141 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); | |
| 8142 __ bind(skip); | |
| 8143 %} | |
| 8144 ins_pipe( pipe_slow ); | |
| 8145 %} | |
| 8146 | |
|
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|
8147 instruct fcmovXD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regXD dst, regXD src) %{ |
|
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|
8148 predicate (UseSSE>=2); |
|
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|
8149 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); |
|
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|
8150 ins_cost(200); |
|
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|
8151 expand %{ |
|
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|
8152 fcmovXD_regU(cop, cr, dst, src); |
|
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|
8153 %} |
|
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|
8154 %} |
|
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|
8155 |
| 0 | 8156 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{ |
| 8157 predicate(VM_Version::supports_cmov() ); | |
| 8158 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 8159 ins_cost(200); | |
| 8160 format %{ "CMOV$cop $dst.lo,$src.lo\n\t" | |
| 8161 "CMOV$cop $dst.hi,$src.hi" %} | |
| 8162 opcode(0x0F,0x40); | |
| 8163 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) ); | |
| 8164 ins_pipe( pipe_cmov_reg_long ); | |
| 8165 %} | |
| 8166 | |
| 8167 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{ | |
| 8168 predicate(VM_Version::supports_cmov() ); | |
| 8169 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 8170 ins_cost(200); | |
| 8171 format %{ "CMOV$cop $dst.lo,$src.lo\n\t" | |
| 8172 "CMOV$cop $dst.hi,$src.hi" %} | |
| 8173 opcode(0x0F,0x40); | |
| 8174 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) ); | |
| 8175 ins_pipe( pipe_cmov_reg_long ); | |
| 8176 %} | |
| 8177 | |
|
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|
8178 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{ |
|
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|
8179 predicate(VM_Version::supports_cmov() ); |
|
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|
8180 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); |
|
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|
8181 ins_cost(200); |
|
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|
8182 expand %{ |
|
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|
8183 cmovL_regU(cop, cr, dst, src); |
|
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|
8184 %} |
|
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|
8185 %} |
|
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|
8186 |
| 0 | 8187 //----------Arithmetic Instructions-------------------------------------------- |
| 8188 //----------Addition Instructions---------------------------------------------- | |
| 8189 // Integer Addition Instructions | |
| 8190 instruct addI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ | |
| 8191 match(Set dst (AddI dst src)); | |
| 8192 effect(KILL cr); | |
| 8193 | |
| 8194 size(2); | |
| 8195 format %{ "ADD $dst,$src" %} | |
| 8196 opcode(0x03); | |
| 8197 ins_encode( OpcP, RegReg( dst, src) ); | |
| 8198 ins_pipe( ialu_reg_reg ); | |
| 8199 %} | |
| 8200 | |
| 8201 instruct addI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ | |
| 8202 match(Set dst (AddI dst src)); | |
| 8203 effect(KILL cr); | |
| 8204 | |
| 8205 format %{ "ADD $dst,$src" %} | |
| 8206 opcode(0x81, 0x00); /* /0 id */ | |
| 8207 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 8208 ins_pipe( ialu_reg ); | |
| 8209 %} | |
| 8210 | |
| 8211 instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ | |
| 8212 predicate(UseIncDec); | |
| 8213 match(Set dst (AddI dst src)); | |
| 8214 effect(KILL cr); | |
| 8215 | |
| 8216 size(1); | |
| 8217 format %{ "INC $dst" %} | |
| 8218 opcode(0x40); /* */ | |
| 8219 ins_encode( Opc_plus( primary, dst ) ); | |
| 8220 ins_pipe( ialu_reg ); | |
| 8221 %} | |
| 8222 | |
| 8223 instruct leaI_eReg_immI(eRegI dst, eRegI src0, immI src1) %{ | |
| 8224 match(Set dst (AddI src0 src1)); | |
| 8225 ins_cost(110); | |
| 8226 | |
| 8227 format %{ "LEA $dst,[$src0 + $src1]" %} | |
| 8228 opcode(0x8D); /* 0x8D /r */ | |
| 8229 ins_encode( OpcP, RegLea( dst, src0, src1 ) ); | |
| 8230 ins_pipe( ialu_reg_reg ); | |
| 8231 %} | |
| 8232 | |
| 8233 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{ | |
| 8234 match(Set dst (AddP src0 src1)); | |
| 8235 ins_cost(110); | |
| 8236 | |
| 8237 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %} | |
| 8238 opcode(0x8D); /* 0x8D /r */ | |
| 8239 ins_encode( OpcP, RegLea( dst, src0, src1 ) ); | |
| 8240 ins_pipe( ialu_reg_reg ); | |
| 8241 %} | |
| 8242 | |
| 8243 instruct decI_eReg(eRegI dst, immI_M1 src, eFlagsReg cr) %{ | |
| 8244 predicate(UseIncDec); | |
| 8245 match(Set dst (AddI dst src)); | |
| 8246 effect(KILL cr); | |
| 8247 | |
| 8248 size(1); | |
| 8249 format %{ "DEC $dst" %} | |
| 8250 opcode(0x48); /* */ | |
| 8251 ins_encode( Opc_plus( primary, dst ) ); | |
| 8252 ins_pipe( ialu_reg ); | |
| 8253 %} | |
| 8254 | |
| 8255 instruct addP_eReg(eRegP dst, eRegI src, eFlagsReg cr) %{ | |
| 8256 match(Set dst (AddP dst src)); | |
| 8257 effect(KILL cr); | |
| 8258 | |
| 8259 size(2); | |
| 8260 format %{ "ADD $dst,$src" %} | |
| 8261 opcode(0x03); | |
| 8262 ins_encode( OpcP, RegReg( dst, src) ); | |
| 8263 ins_pipe( ialu_reg_reg ); | |
| 8264 %} | |
| 8265 | |
| 8266 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{ | |
| 8267 match(Set dst (AddP dst src)); | |
| 8268 effect(KILL cr); | |
| 8269 | |
| 8270 format %{ "ADD $dst,$src" %} | |
| 8271 opcode(0x81,0x00); /* Opcode 81 /0 id */ | |
| 8272 // ins_encode( RegImm( dst, src) ); | |
| 8273 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 8274 ins_pipe( ialu_reg ); | |
| 8275 %} | |
| 8276 | |
| 8277 instruct addI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ | |
| 8278 match(Set dst (AddI dst (LoadI src))); | |
| 8279 effect(KILL cr); | |
| 8280 | |
| 8281 ins_cost(125); | |
| 8282 format %{ "ADD $dst,$src" %} | |
| 8283 opcode(0x03); | |
| 8284 ins_encode( OpcP, RegMem( dst, src) ); | |
| 8285 ins_pipe( ialu_reg_mem ); | |
| 8286 %} | |
| 8287 | |
| 8288 instruct addI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ | |
| 8289 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 8290 effect(KILL cr); | |
| 8291 | |
| 8292 ins_cost(150); | |
| 8293 format %{ "ADD $dst,$src" %} | |
| 8294 opcode(0x01); /* Opcode 01 /r */ | |
| 8295 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 8296 ins_pipe( ialu_mem_reg ); | |
| 8297 %} | |
| 8298 | |
| 8299 // Add Memory with Immediate | |
| 8300 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 8301 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 8302 effect(KILL cr); | |
| 8303 | |
| 8304 ins_cost(125); | |
| 8305 format %{ "ADD $dst,$src" %} | |
| 8306 opcode(0x81); /* Opcode 81 /0 id */ | |
| 8307 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) ); | |
| 8308 ins_pipe( ialu_mem_imm ); | |
| 8309 %} | |
| 8310 | |
| 8311 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{ | |
| 8312 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 8313 effect(KILL cr); | |
| 8314 | |
| 8315 ins_cost(125); | |
| 8316 format %{ "INC $dst" %} | |
| 8317 opcode(0xFF); /* Opcode FF /0 */ | |
| 8318 ins_encode( OpcP, RMopc_Mem(0x00,dst)); | |
| 8319 ins_pipe( ialu_mem_imm ); | |
| 8320 %} | |
| 8321 | |
| 8322 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{ | |
| 8323 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 8324 effect(KILL cr); | |
| 8325 | |
| 8326 ins_cost(125); | |
| 8327 format %{ "DEC $dst" %} | |
| 8328 opcode(0xFF); /* Opcode FF /1 */ | |
| 8329 ins_encode( OpcP, RMopc_Mem(0x01,dst)); | |
| 8330 ins_pipe( ialu_mem_imm ); | |
| 8331 %} | |
| 8332 | |
| 8333 | |
| 8334 instruct checkCastPP( eRegP dst ) %{ | |
| 8335 match(Set dst (CheckCastPP dst)); | |
| 8336 | |
| 8337 size(0); | |
| 8338 format %{ "#checkcastPP of $dst" %} | |
| 8339 ins_encode( /*empty encoding*/ ); | |
| 8340 ins_pipe( empty ); | |
| 8341 %} | |
| 8342 | |
| 8343 instruct castPP( eRegP dst ) %{ | |
| 8344 match(Set dst (CastPP dst)); | |
| 8345 format %{ "#castPP of $dst" %} | |
| 8346 ins_encode( /*empty encoding*/ ); | |
| 8347 ins_pipe( empty ); | |
| 8348 %} | |
| 8349 | |
| 8350 instruct castII( eRegI dst ) %{ | |
| 8351 match(Set dst (CastII dst)); | |
| 8352 format %{ "#castII of $dst" %} | |
| 8353 ins_encode( /*empty encoding*/ ); | |
| 8354 ins_cost(0); | |
| 8355 ins_pipe( empty ); | |
| 8356 %} | |
| 8357 | |
| 8358 | |
| 8359 // Load-locked - same as a regular pointer load when used with compare-swap | |
| 8360 instruct loadPLocked(eRegP dst, memory mem) %{ | |
| 8361 match(Set dst (LoadPLocked mem)); | |
| 8362 | |
| 8363 ins_cost(125); | |
| 8364 format %{ "MOV $dst,$mem\t# Load ptr. locked" %} | |
| 8365 opcode(0x8B); | |
| 8366 ins_encode( OpcP, RegMem(dst,mem)); | |
| 8367 ins_pipe( ialu_reg_mem ); | |
| 8368 %} | |
| 8369 | |
| 8370 // LoadLong-locked - same as a volatile long load when used with compare-swap | |
| 8371 instruct loadLLocked(stackSlotL dst, load_long_memory mem) %{ | |
| 8372 predicate(UseSSE<=1); | |
| 8373 match(Set dst (LoadLLocked mem)); | |
| 8374 | |
| 8375 ins_cost(200); | |
| 8376 format %{ "FILD $mem\t# Atomic volatile long load\n\t" | |
| 8377 "FISTp $dst" %} | |
| 8378 ins_encode(enc_loadL_volatile(mem,dst)); | |
| 8379 ins_pipe( fpu_reg_mem ); | |
| 8380 %} | |
| 8381 | |
| 8382 instruct loadLX_Locked(stackSlotL dst, load_long_memory mem, regXD tmp) %{ | |
| 8383 predicate(UseSSE>=2); | |
| 8384 match(Set dst (LoadLLocked mem)); | |
| 8385 effect(TEMP tmp); | |
| 8386 ins_cost(180); | |
| 8387 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" | |
| 8388 "MOVSD $dst,$tmp" %} | |
| 8389 ins_encode(enc_loadLX_volatile(mem, dst, tmp)); | |
| 8390 ins_pipe( pipe_slow ); | |
| 8391 %} | |
| 8392 | |
| 8393 instruct loadLX_reg_Locked(eRegL dst, load_long_memory mem, regXD tmp) %{ | |
| 8394 predicate(UseSSE>=2); | |
| 8395 match(Set dst (LoadLLocked mem)); | |
| 8396 effect(TEMP tmp); | |
| 8397 ins_cost(160); | |
| 8398 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" | |
| 8399 "MOVD $dst.lo,$tmp\n\t" | |
| 8400 "PSRLQ $tmp,32\n\t" | |
| 8401 "MOVD $dst.hi,$tmp" %} | |
| 8402 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp)); | |
| 8403 ins_pipe( pipe_slow ); | |
| 8404 %} | |
| 8405 | |
| 8406 // Conditional-store of the updated heap-top. | |
| 8407 // Used during allocation of the shared heap. | |
| 8408 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel. | |
| 8409 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{ | |
| 8410 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval))); | |
| 8411 // EAX is killed if there is contention, but then it's also unused. | |
| 8412 // In the common case of no contention, EAX holds the new oop address. | |
| 8413 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %} | |
| 8414 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) ); | |
| 8415 ins_pipe( pipe_cmpxchg ); | |
| 8416 %} | |
| 8417 | |
|
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8418 // Conditional-store of an int value. |
|
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8419 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel. |
|
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|
8420 instruct storeIConditional( memory mem, eAXRegI oldval, eRegI newval, eFlagsReg cr ) %{ |
|
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6462850: generate biased locking code in C2 ideal graph
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|
8421 match(Set cr (StoreIConditional mem (Binary oldval newval))); |
|
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6462850: generate biased locking code in C2 ideal graph
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|
8422 effect(KILL oldval); |
|
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6462850: generate biased locking code in C2 ideal graph
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|
8423 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %} |
|
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|
8424 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) ); |
| 0 | 8425 ins_pipe( pipe_cmpxchg ); |
| 8426 %} | |
| 8427 | |
|
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6462850: generate biased locking code in C2 ideal graph
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|
8428 // Conditional-store of a long value. |
|
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|
8429 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel. |
|
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|
8430 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{ |
|
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6462850: generate biased locking code in C2 ideal graph
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|
8431 match(Set cr (StoreLConditional mem (Binary oldval newval))); |
|
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|
8432 effect(KILL oldval); |
|
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|
8433 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t" |
|
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|
8434 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t" |
|
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|
8435 "XCHG EBX,ECX" |
|
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|
8436 %} |
|
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|
8437 ins_encode %{ |
|
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|
8438 // Note: we need to swap rbx, and rcx before and after the |
|
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|
8439 // cmpxchg8 instruction because the instruction uses |
|
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|
8440 // rcx as the high order word of the new value to store but |
|
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|
8441 // our register encoding uses rbx. |
|
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|
8442 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc)); |
|
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|
8443 if( os::is_MP() ) |
|
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|
8444 __ lock(); |
| 624 | 8445 __ cmpxchg8($mem$$Address); |
|
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|
8446 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc)); |
|
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|
8447 %} |
| 0 | 8448 ins_pipe( pipe_cmpxchg ); |
| 8449 %} | |
| 8450 | |
| 8451 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them | |
| 8452 | |
| 8453 instruct compareAndSwapL( eRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{ | |
| 8454 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); | |
| 8455 effect(KILL cr, KILL oldval); | |
| 8456 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" | |
| 8457 "MOV $res,0\n\t" | |
| 8458 "JNE,s fail\n\t" | |
| 8459 "MOV $res,1\n" | |
| 8460 "fail:" %} | |
| 8461 ins_encode( enc_cmpxchg8(mem_ptr), | |
| 8462 enc_flags_ne_to_boolean(res) ); | |
| 8463 ins_pipe( pipe_cmpxchg ); | |
| 8464 %} | |
| 8465 | |
| 8466 instruct compareAndSwapP( eRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{ | |
| 8467 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); | |
| 8468 effect(KILL cr, KILL oldval); | |
| 8469 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" | |
| 8470 "MOV $res,0\n\t" | |
| 8471 "JNE,s fail\n\t" | |
| 8472 "MOV $res,1\n" | |
| 8473 "fail:" %} | |
| 8474 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) ); | |
| 8475 ins_pipe( pipe_cmpxchg ); | |
| 8476 %} | |
| 8477 | |
| 8478 instruct compareAndSwapI( eRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{ | |
| 8479 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); | |
| 8480 effect(KILL cr, KILL oldval); | |
| 8481 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" | |
| 8482 "MOV $res,0\n\t" | |
| 8483 "JNE,s fail\n\t" | |
| 8484 "MOV $res,1\n" | |
| 8485 "fail:" %} | |
| 8486 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) ); | |
| 8487 ins_pipe( pipe_cmpxchg ); | |
| 8488 %} | |
| 8489 | |
| 8490 //----------Subtraction Instructions------------------------------------------- | |
| 8491 // Integer Subtraction Instructions | |
| 8492 instruct subI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ | |
| 8493 match(Set dst (SubI dst src)); | |
| 8494 effect(KILL cr); | |
| 8495 | |
| 8496 size(2); | |
| 8497 format %{ "SUB $dst,$src" %} | |
| 8498 opcode(0x2B); | |
| 8499 ins_encode( OpcP, RegReg( dst, src) ); | |
| 8500 ins_pipe( ialu_reg_reg ); | |
| 8501 %} | |
| 8502 | |
| 8503 instruct subI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ | |
| 8504 match(Set dst (SubI dst src)); | |
| 8505 effect(KILL cr); | |
| 8506 | |
| 8507 format %{ "SUB $dst,$src" %} | |
| 8508 opcode(0x81,0x05); /* Opcode 81 /5 */ | |
| 8509 // ins_encode( RegImm( dst, src) ); | |
| 8510 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 8511 ins_pipe( ialu_reg ); | |
| 8512 %} | |
| 8513 | |
| 8514 instruct subI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ | |
| 8515 match(Set dst (SubI dst (LoadI src))); | |
| 8516 effect(KILL cr); | |
| 8517 | |
| 8518 ins_cost(125); | |
| 8519 format %{ "SUB $dst,$src" %} | |
| 8520 opcode(0x2B); | |
| 8521 ins_encode( OpcP, RegMem( dst, src) ); | |
| 8522 ins_pipe( ialu_reg_mem ); | |
| 8523 %} | |
| 8524 | |
| 8525 instruct subI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ | |
| 8526 match(Set dst (StoreI dst (SubI (LoadI dst) src))); | |
| 8527 effect(KILL cr); | |
| 8528 | |
| 8529 ins_cost(150); | |
| 8530 format %{ "SUB $dst,$src" %} | |
| 8531 opcode(0x29); /* Opcode 29 /r */ | |
| 8532 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 8533 ins_pipe( ialu_mem_reg ); | |
| 8534 %} | |
| 8535 | |
| 8536 // Subtract from a pointer | |
| 8537 instruct subP_eReg(eRegP dst, eRegI src, immI0 zero, eFlagsReg cr) %{ | |
| 8538 match(Set dst (AddP dst (SubI zero src))); | |
| 8539 effect(KILL cr); | |
| 8540 | |
| 8541 size(2); | |
| 8542 format %{ "SUB $dst,$src" %} | |
| 8543 opcode(0x2B); | |
| 8544 ins_encode( OpcP, RegReg( dst, src) ); | |
| 8545 ins_pipe( ialu_reg_reg ); | |
| 8546 %} | |
| 8547 | |
| 8548 instruct negI_eReg(eRegI dst, immI0 zero, eFlagsReg cr) %{ | |
| 8549 match(Set dst (SubI zero dst)); | |
| 8550 effect(KILL cr); | |
| 8551 | |
| 8552 size(2); | |
| 8553 format %{ "NEG $dst" %} | |
| 8554 opcode(0xF7,0x03); // Opcode F7 /3 | |
| 8555 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8556 ins_pipe( ialu_reg ); | |
| 8557 %} | |
| 8558 | |
| 8559 | |
| 8560 //----------Multiplication/Division Instructions------------------------------- | |
| 8561 // Integer Multiplication Instructions | |
| 8562 // Multiply Register | |
| 8563 instruct mulI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ | |
| 8564 match(Set dst (MulI dst src)); | |
| 8565 effect(KILL cr); | |
| 8566 | |
| 8567 size(3); | |
| 8568 ins_cost(300); | |
| 8569 format %{ "IMUL $dst,$src" %} | |
| 8570 opcode(0xAF, 0x0F); | |
| 8571 ins_encode( OpcS, OpcP, RegReg( dst, src) ); | |
| 8572 ins_pipe( ialu_reg_reg_alu0 ); | |
| 8573 %} | |
| 8574 | |
| 8575 // Multiply 32-bit Immediate | |
| 8576 instruct mulI_eReg_imm(eRegI dst, eRegI src, immI imm, eFlagsReg cr) %{ | |
| 8577 match(Set dst (MulI src imm)); | |
| 8578 effect(KILL cr); | |
| 8579 | |
| 8580 ins_cost(300); | |
| 8581 format %{ "IMUL $dst,$src,$imm" %} | |
| 8582 opcode(0x69); /* 69 /r id */ | |
| 8583 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) ); | |
| 8584 ins_pipe( ialu_reg_reg_alu0 ); | |
| 8585 %} | |
| 8586 | |
| 8587 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{ | |
| 8588 match(Set dst src); | |
| 8589 effect(KILL cr); | |
| 8590 | |
| 8591 // Note that this is artificially increased to make it more expensive than loadConL | |
| 8592 ins_cost(250); | |
| 8593 format %{ "MOV EAX,$src\t// low word only" %} | |
| 8594 opcode(0xB8); | |
| 8595 ins_encode( LdImmL_Lo(dst, src) ); | |
| 8596 ins_pipe( ialu_reg_fat ); | |
| 8597 %} | |
| 8598 | |
| 8599 // Multiply by 32-bit Immediate, taking the shifted high order results | |
| 8600 // (special case for shift by 32) | |
| 8601 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{ | |
| 8602 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt))); | |
| 8603 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL && | |
| 8604 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint && | |
| 8605 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint ); | |
| 8606 effect(USE src1, KILL cr); | |
| 8607 | |
| 8608 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only | |
| 8609 ins_cost(0*100 + 1*400 - 150); | |
| 8610 format %{ "IMUL EDX:EAX,$src1" %} | |
| 8611 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) ); | |
| 8612 ins_pipe( pipe_slow ); | |
| 8613 %} | |
| 8614 | |
| 8615 // Multiply by 32-bit Immediate, taking the shifted high order results | |
| 8616 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 8617 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt))); | |
| 8618 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL && | |
| 8619 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint && | |
| 8620 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint ); | |
| 8621 effect(USE src1, KILL cr); | |
| 8622 | |
| 8623 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only | |
| 8624 ins_cost(1*100 + 1*400 - 150); | |
| 8625 format %{ "IMUL EDX:EAX,$src1\n\t" | |
| 8626 "SAR EDX,$cnt-32" %} | |
| 8627 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) ); | |
| 8628 ins_pipe( pipe_slow ); | |
| 8629 %} | |
| 8630 | |
| 8631 // Multiply Memory 32-bit Immediate | |
| 8632 instruct mulI_mem_imm(eRegI dst, memory src, immI imm, eFlagsReg cr) %{ | |
| 8633 match(Set dst (MulI (LoadI src) imm)); | |
| 8634 effect(KILL cr); | |
| 8635 | |
| 8636 ins_cost(300); | |
| 8637 format %{ "IMUL $dst,$src,$imm" %} | |
| 8638 opcode(0x69); /* 69 /r id */ | |
| 8639 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) ); | |
| 8640 ins_pipe( ialu_reg_mem_alu0 ); | |
| 8641 %} | |
| 8642 | |
| 8643 // Multiply Memory | |
| 8644 instruct mulI(eRegI dst, memory src, eFlagsReg cr) %{ | |
| 8645 match(Set dst (MulI dst (LoadI src))); | |
| 8646 effect(KILL cr); | |
| 8647 | |
| 8648 ins_cost(350); | |
| 8649 format %{ "IMUL $dst,$src" %} | |
| 8650 opcode(0xAF, 0x0F); | |
| 8651 ins_encode( OpcS, OpcP, RegMem( dst, src) ); | |
| 8652 ins_pipe( ialu_reg_mem_alu0 ); | |
| 8653 %} | |
| 8654 | |
| 8655 // Multiply Register Int to Long | |
| 8656 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{ | |
| 8657 // Basic Idea: long = (long)int * (long)int | |
| 8658 match(Set dst (MulL (ConvI2L src) (ConvI2L src1))); | |
| 8659 effect(DEF dst, USE src, USE src1, KILL flags); | |
| 8660 | |
| 8661 ins_cost(300); | |
| 8662 format %{ "IMUL $dst,$src1" %} | |
| 8663 | |
| 8664 ins_encode( long_int_multiply( dst, src1 ) ); | |
| 8665 ins_pipe( ialu_reg_reg_alu0 ); | |
| 8666 %} | |
| 8667 | |
| 8668 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{ | |
| 8669 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL) | |
| 8670 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask))); | |
| 8671 effect(KILL flags); | |
| 8672 | |
| 8673 ins_cost(300); | |
| 8674 format %{ "MUL $dst,$src1" %} | |
| 8675 | |
| 8676 ins_encode( long_uint_multiply(dst, src1) ); | |
| 8677 ins_pipe( ialu_reg_reg_alu0 ); | |
| 8678 %} | |
| 8679 | |
| 8680 // Multiply Register Long | |
| 8681 instruct mulL_eReg(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{ | |
| 8682 match(Set dst (MulL dst src)); | |
| 8683 effect(KILL cr, TEMP tmp); | |
| 8684 ins_cost(4*100+3*400); | |
| 8685 // Basic idea: lo(result) = lo(x_lo * y_lo) | |
| 8686 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) | |
| 8687 format %{ "MOV $tmp,$src.lo\n\t" | |
| 8688 "IMUL $tmp,EDX\n\t" | |
| 8689 "MOV EDX,$src.hi\n\t" | |
| 8690 "IMUL EDX,EAX\n\t" | |
| 8691 "ADD $tmp,EDX\n\t" | |
| 8692 "MUL EDX:EAX,$src.lo\n\t" | |
| 8693 "ADD EDX,$tmp" %} | |
| 8694 ins_encode( long_multiply( dst, src, tmp ) ); | |
| 8695 ins_pipe( pipe_slow ); | |
| 8696 %} | |
| 8697 | |
|
1209
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|
8698 // Multiply Register Long where the left operand's high 32 bits are zero |
|
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|
8699 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{ |
|
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|
8700 predicate(is_operand_hi32_zero(n->in(1))); |
|
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|
8701 match(Set dst (MulL dst src)); |
|
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|
8702 effect(KILL cr, TEMP tmp); |
|
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|
8703 ins_cost(2*100+2*400); |
|
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|
8704 // Basic idea: lo(result) = lo(x_lo * y_lo) |
|
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|
8705 // hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0 |
|
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|
8706 format %{ "MOV $tmp,$src.hi\n\t" |
|
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|
8707 "IMUL $tmp,EAX\n\t" |
|
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|
8708 "MUL EDX:EAX,$src.lo\n\t" |
|
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|
8709 "ADD EDX,$tmp" %} |
|
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|
8710 ins_encode %{ |
|
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|
8711 __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register)); |
|
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|
8712 __ imull($tmp$$Register, rax); |
|
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|
8713 __ mull($src$$Register); |
|
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|
8714 __ addl(rdx, $tmp$$Register); |
|
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|
8715 %} |
|
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|
8716 ins_pipe( pipe_slow ); |
|
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|
8717 %} |
|
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|
8718 |
|
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|
8719 // Multiply Register Long where the right operand's high 32 bits are zero |
|
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|
8720 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{ |
|
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|
8721 predicate(is_operand_hi32_zero(n->in(2))); |
|
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|
8722 match(Set dst (MulL dst src)); |
|
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|
8723 effect(KILL cr, TEMP tmp); |
|
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|
8724 ins_cost(2*100+2*400); |
|
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|
8725 // Basic idea: lo(result) = lo(x_lo * y_lo) |
|
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|
8726 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0 |
|
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|
8727 format %{ "MOV $tmp,$src.lo\n\t" |
|
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|
8728 "IMUL $tmp,EDX\n\t" |
|
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|
8729 "MUL EDX:EAX,$src.lo\n\t" |
|
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|
8730 "ADD EDX,$tmp" %} |
|
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|
8731 ins_encode %{ |
|
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changeset
|
8732 __ movl($tmp$$Register, $src$$Register); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
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1137
diff
changeset
|
8733 __ imull($tmp$$Register, rdx); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
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1137
diff
changeset
|
8734 __ mull($src$$Register); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8735 __ addl(rdx, $tmp$$Register); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8736 %} |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8737 ins_pipe( pipe_slow ); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8738 %} |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8739 |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8740 // Multiply Register Long where the left and the right operands' high 32 bits are zero |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8741 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{ |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8742 predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2))); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
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diff
changeset
|
8743 match(Set dst (MulL dst src)); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8744 effect(KILL cr); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8745 ins_cost(1*400); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8746 // Basic idea: lo(result) = lo(x_lo * y_lo) |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8747 // hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0 |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
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1137
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changeset
|
8748 format %{ "MUL EDX:EAX,$src.lo\n\t" %} |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
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1137
diff
changeset
|
8749 ins_encode %{ |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8750 __ mull($src$$Register); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8751 %} |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8752 ins_pipe( pipe_slow ); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
8753 %} |
|
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6921969: optimize 64 long multiply for case with high bits zero
never
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1137
diff
changeset
|
8754 |
| 0 | 8755 // Multiply Register Long by small constant |
| 8756 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, eRegI tmp, eFlagsReg cr) %{ | |
| 8757 match(Set dst (MulL dst src)); | |
| 8758 effect(KILL cr, TEMP tmp); | |
| 8759 ins_cost(2*100+2*400); | |
| 8760 size(12); | |
| 8761 // Basic idea: lo(result) = lo(src * EAX) | |
| 8762 // hi(result) = hi(src * EAX) + lo(src * EDX) | |
| 8763 format %{ "IMUL $tmp,EDX,$src\n\t" | |
| 8764 "MOV EDX,$src\n\t" | |
| 8765 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t" | |
| 8766 "ADD EDX,$tmp" %} | |
| 8767 ins_encode( long_multiply_con( dst, src, tmp ) ); | |
| 8768 ins_pipe( pipe_slow ); | |
| 8769 %} | |
| 8770 | |
| 8771 // Integer DIV with Register | |
| 8772 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{ | |
| 8773 match(Set rax (DivI rax div)); | |
| 8774 effect(KILL rdx, KILL cr); | |
| 8775 size(26); | |
| 8776 ins_cost(30*100+10*100); | |
| 8777 format %{ "CMP EAX,0x80000000\n\t" | |
| 8778 "JNE,s normal\n\t" | |
| 8779 "XOR EDX,EDX\n\t" | |
| 8780 "CMP ECX,-1\n\t" | |
| 8781 "JE,s done\n" | |
| 8782 "normal: CDQ\n\t" | |
| 8783 "IDIV $div\n\t" | |
| 8784 "done:" %} | |
| 8785 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8786 ins_encode( cdq_enc, OpcP, RegOpc(div) ); | |
| 8787 ins_pipe( ialu_reg_reg_alu0 ); | |
| 8788 %} | |
| 8789 | |
| 8790 // Divide Register Long | |
| 8791 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{ | |
| 8792 match(Set dst (DivL src1 src2)); | |
| 8793 effect( KILL cr, KILL cx, KILL bx ); | |
| 8794 ins_cost(10000); | |
| 8795 format %{ "PUSH $src1.hi\n\t" | |
| 8796 "PUSH $src1.lo\n\t" | |
| 8797 "PUSH $src2.hi\n\t" | |
| 8798 "PUSH $src2.lo\n\t" | |
| 8799 "CALL SharedRuntime::ldiv\n\t" | |
| 8800 "ADD ESP,16" %} | |
| 8801 ins_encode( long_div(src1,src2) ); | |
| 8802 ins_pipe( pipe_slow ); | |
| 8803 %} | |
| 8804 | |
| 8805 // Integer DIVMOD with Register, both quotient and mod results | |
| 8806 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{ | |
| 8807 match(DivModI rax div); | |
| 8808 effect(KILL cr); | |
| 8809 size(26); | |
| 8810 ins_cost(30*100+10*100); | |
| 8811 format %{ "CMP EAX,0x80000000\n\t" | |
| 8812 "JNE,s normal\n\t" | |
| 8813 "XOR EDX,EDX\n\t" | |
| 8814 "CMP ECX,-1\n\t" | |
| 8815 "JE,s done\n" | |
| 8816 "normal: CDQ\n\t" | |
| 8817 "IDIV $div\n\t" | |
| 8818 "done:" %} | |
| 8819 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8820 ins_encode( cdq_enc, OpcP, RegOpc(div) ); | |
| 8821 ins_pipe( pipe_slow ); | |
| 8822 %} | |
| 8823 | |
| 8824 // Integer MOD with Register | |
| 8825 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{ | |
| 8826 match(Set rdx (ModI rax div)); | |
| 8827 effect(KILL rax, KILL cr); | |
| 8828 | |
| 8829 size(26); | |
| 8830 ins_cost(300); | |
| 8831 format %{ "CDQ\n\t" | |
| 8832 "IDIV $div" %} | |
| 8833 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8834 ins_encode( cdq_enc, OpcP, RegOpc(div) ); | |
| 8835 ins_pipe( ialu_reg_reg_alu0 ); | |
| 8836 %} | |
| 8837 | |
| 8838 // Remainder Register Long | |
| 8839 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{ | |
| 8840 match(Set dst (ModL src1 src2)); | |
| 8841 effect( KILL cr, KILL cx, KILL bx ); | |
| 8842 ins_cost(10000); | |
| 8843 format %{ "PUSH $src1.hi\n\t" | |
| 8844 "PUSH $src1.lo\n\t" | |
| 8845 "PUSH $src2.hi\n\t" | |
| 8846 "PUSH $src2.lo\n\t" | |
| 8847 "CALL SharedRuntime::lrem\n\t" | |
| 8848 "ADD ESP,16" %} | |
| 8849 ins_encode( long_mod(src1,src2) ); | |
| 8850 ins_pipe( pipe_slow ); | |
| 8851 %} | |
| 8852 | |
|
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kvn
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diff
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|
8853 // Divide Register Long (no special case since divisor != -1) |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
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|
8854 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, eRegI tmp, eRegI tmp2, eFlagsReg cr ) %{ |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
8855 match(Set dst (DivL dst imm)); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
8856 effect( TEMP tmp, TEMP tmp2, KILL cr ); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8857 ins_cost(1000); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8858 format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t" |
| 1920 | 8859 "XOR $tmp2,$tmp2\n\t" |
|
1914
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6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
8860 "CMP $tmp,EDX\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
8861 "JA,s fast\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8862 "MOV $tmp2,EAX\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8863 "MOV EAX,EDX\n\t" |
| 1920 | 8864 "MOV EDX,0\n\t" |
| 8865 "JLE,s pos\n\t" | |
| 8866 "LNEG EAX : $tmp2\n\t" | |
| 8867 "DIV $tmp # unsigned division\n\t" | |
| 8868 "XCHG EAX,$tmp2\n\t" | |
| 8869 "DIV $tmp\n\t" | |
| 8870 "LNEG $tmp2 : EAX\n\t" | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8871 "JMP,s done\n" |
| 1920 | 8872 "pos:\n\t" |
| 8873 "DIV $tmp\n\t" | |
| 8874 "XCHG EAX,$tmp2\n" | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
8875 "fast:\n\t" |
| 1920 | 8876 "DIV $tmp\n" |
|
1914
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6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8877 "done:\n\t" |
| 1920 | 8878 "MOV EDX,$tmp2\n\t" |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8879 "NEG EDX:EAX # if $imm < 0" %} |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8880 ins_encode %{ |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8881 int con = (int)$imm$$constant; |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8882 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor"); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
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diff
changeset
|
8883 int pcon = (con > 0) ? con : -con; |
| 1920 | 8884 Label Lfast, Lpos, Ldone; |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
8885 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
8886 __ movl($tmp$$Register, pcon); |
| 1920 | 8887 __ xorl($tmp2$$Register,$tmp2$$Register); |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8888 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register)); |
| 1920 | 8889 __ jccb(Assembler::above, Lfast); // result fits into 32 bit |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8890 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
8891 __ movl($tmp2$$Register, $dst$$Register); // save |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8892 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register)); |
| 1920 | 8893 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags |
| 8894 __ jccb(Assembler::lessEqual, Lpos); // result is positive | |
| 8895 | |
| 8896 // Negative dividend. | |
| 8897 // convert value to positive to use unsigned division | |
| 8898 __ lneg($dst$$Register, $tmp2$$Register); | |
| 8899 __ divl($tmp$$Register); | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8900 __ xchgl($dst$$Register, $tmp2$$Register); |
| 1920 | 8901 __ divl($tmp$$Register); |
| 8902 // revert result back to negative | |
| 8903 __ lneg($tmp2$$Register, $dst$$Register); | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8904 __ jmpb(Ldone); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8905 |
| 1920 | 8906 __ bind(Lpos); |
| 8907 __ divl($tmp$$Register); // Use unsigned division | |
| 8908 __ xchgl($dst$$Register, $tmp2$$Register); | |
| 8909 // Fallthrow for final divide, tmp2 has 32 bit hi result | |
| 8910 | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8911 __ bind(Lfast); |
| 1920 | 8912 // fast path: src is positive |
| 8913 __ divl($tmp$$Register); // Use unsigned division | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
8914 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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diff
changeset
|
8915 __ bind(Ldone); |
| 1920 | 8916 __ movl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register); |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8917 if (con < 0) { |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8918 __ lneg(HIGH_FROM_LOW($dst$$Register), $dst$$Register); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8919 } |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
8920 %} |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8921 ins_pipe( pipe_slow ); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8922 %} |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
8923 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
8924 // Remainder Register Long (remainder fit into 32 bits) |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
8925 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, eRegI tmp, eRegI tmp2, eFlagsReg cr ) %{ |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8926 match(Set dst (ModL dst imm)); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
8927 effect( TEMP tmp, TEMP tmp2, KILL cr ); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8928 ins_cost(1000); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8929 format %{ "MOV $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
8930 "CMP $tmp,EDX\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
8931 "JA,s fast\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
8932 "MOV $tmp2,EAX\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
8933 "MOV EAX,EDX\n\t" |
| 1920 | 8934 "MOV EDX,0\n\t" |
| 8935 "JLE,s pos\n\t" | |
| 8936 "LNEG EAX : $tmp2\n\t" | |
| 8937 "DIV $tmp # unsigned division\n\t" | |
| 8938 "MOV EAX,$tmp2\n\t" | |
| 8939 "DIV $tmp\n\t" | |
| 8940 "NEG EDX\n\t" | |
| 8941 "JMP,s done\n" | |
| 8942 "pos:\n\t" | |
| 8943 "DIV $tmp\n\t" | |
|
1914
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6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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diff
changeset
|
8944 "MOV EAX,$tmp2\n" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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diff
changeset
|
8945 "fast:\n\t" |
| 1920 | 8946 "DIV $tmp\n" |
| 8947 "done:\n\t" | |
|
1914
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6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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diff
changeset
|
8948 "MOV EAX,EDX\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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diff
changeset
|
8949 "SAR EDX,31\n\t" %} |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
8950 ins_encode %{ |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
8951 int con = (int)$imm$$constant; |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
8952 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor"); |
|
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8953 int pcon = (con > 0) ? con : -con; |
| 1920 | 8954 Label Lfast, Lpos, Ldone; |
|
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8955 |
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|
8956 __ movl($tmp$$Register, pcon); |
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8957 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register)); |
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8958 __ jccb(Assembler::above, Lfast); // src is positive and result fits into 32 bit |
|
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|
8959 |
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|
8960 __ movl($tmp2$$Register, $dst$$Register); // save |
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|
8961 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register)); |
| 1920 | 8962 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags |
| 8963 __ jccb(Assembler::lessEqual, Lpos); // result is positive | |
| 8964 | |
| 8965 // Negative dividend. | |
| 8966 // convert value to positive to use unsigned division | |
| 8967 __ lneg($dst$$Register, $tmp2$$Register); | |
| 8968 __ divl($tmp$$Register); | |
| 8969 __ movl($dst$$Register, $tmp2$$Register); | |
| 8970 __ divl($tmp$$Register); | |
| 8971 // revert remainder back to negative | |
| 8972 __ negl(HIGH_FROM_LOW($dst$$Register)); | |
| 8973 __ jmpb(Ldone); | |
| 8974 | |
| 8975 __ bind(Lpos); | |
| 8976 __ divl($tmp$$Register); | |
|
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|
8977 __ movl($dst$$Register, $tmp2$$Register); |
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|
8978 |
|
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|
8979 __ bind(Lfast); |
| 1920 | 8980 // fast path: src is positive |
| 8981 __ divl($tmp$$Register); | |
| 8982 | |
| 8983 __ bind(Ldone); | |
|
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|
8984 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register)); |
|
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|
8985 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign |
|
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|
8986 |
|
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|
8987 %} |
|
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|
8988 ins_pipe( pipe_slow ); |
|
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|
8989 %} |
|
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|
8990 |
| 0 | 8991 // Integer Shift Instructions |
| 8992 // Shift Left by one | |
| 8993 instruct shlI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{ | |
| 8994 match(Set dst (LShiftI dst shift)); | |
| 8995 effect(KILL cr); | |
| 8996 | |
| 8997 size(2); | |
| 8998 format %{ "SHL $dst,$shift" %} | |
| 8999 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 9000 ins_encode( OpcP, RegOpc( dst ) ); | |
| 9001 ins_pipe( ialu_reg ); | |
| 9002 %} | |
| 9003 | |
| 9004 // Shift Left by 8-bit immediate | |
| 9005 instruct salI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{ | |
| 9006 match(Set dst (LShiftI dst shift)); | |
| 9007 effect(KILL cr); | |
| 9008 | |
| 9009 size(3); | |
| 9010 format %{ "SHL $dst,$shift" %} | |
| 9011 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 9012 ins_encode( RegOpcImm( dst, shift) ); | |
| 9013 ins_pipe( ialu_reg ); | |
| 9014 %} | |
| 9015 | |
| 9016 // Shift Left by variable | |
| 9017 instruct salI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 9018 match(Set dst (LShiftI dst shift)); | |
| 9019 effect(KILL cr); | |
| 9020 | |
| 9021 size(2); | |
| 9022 format %{ "SHL $dst,$shift" %} | |
| 9023 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 9024 ins_encode( OpcP, RegOpc( dst ) ); | |
| 9025 ins_pipe( ialu_reg_reg ); | |
| 9026 %} | |
| 9027 | |
| 9028 // Arithmetic shift right by one | |
| 9029 instruct sarI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{ | |
| 9030 match(Set dst (RShiftI dst shift)); | |
| 9031 effect(KILL cr); | |
| 9032 | |
| 9033 size(2); | |
| 9034 format %{ "SAR $dst,$shift" %} | |
| 9035 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 9036 ins_encode( OpcP, RegOpc( dst ) ); | |
| 9037 ins_pipe( ialu_reg ); | |
| 9038 %} | |
| 9039 | |
| 9040 // Arithmetic shift right by one | |
| 9041 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{ | |
| 9042 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 9043 effect(KILL cr); | |
| 9044 format %{ "SAR $dst,$shift" %} | |
| 9045 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 9046 ins_encode( OpcP, RMopc_Mem(secondary,dst) ); | |
| 9047 ins_pipe( ialu_mem_imm ); | |
| 9048 %} | |
| 9049 | |
| 9050 // Arithmetic Shift Right by 8-bit immediate | |
| 9051 instruct sarI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{ | |
| 9052 match(Set dst (RShiftI dst shift)); | |
| 9053 effect(KILL cr); | |
| 9054 | |
| 9055 size(3); | |
| 9056 format %{ "SAR $dst,$shift" %} | |
| 9057 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 9058 ins_encode( RegOpcImm( dst, shift ) ); | |
| 9059 ins_pipe( ialu_mem_imm ); | |
| 9060 %} | |
| 9061 | |
| 9062 // Arithmetic Shift Right by 8-bit immediate | |
| 9063 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{ | |
| 9064 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 9065 effect(KILL cr); | |
| 9066 | |
| 9067 format %{ "SAR $dst,$shift" %} | |
| 9068 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 9069 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) ); | |
| 9070 ins_pipe( ialu_mem_imm ); | |
| 9071 %} | |
| 9072 | |
| 9073 // Arithmetic Shift Right by variable | |
| 9074 instruct sarI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 9075 match(Set dst (RShiftI dst shift)); | |
| 9076 effect(KILL cr); | |
| 9077 | |
| 9078 size(2); | |
| 9079 format %{ "SAR $dst,$shift" %} | |
| 9080 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 9081 ins_encode( OpcP, RegOpc( dst ) ); | |
| 9082 ins_pipe( ialu_reg_reg ); | |
| 9083 %} | |
| 9084 | |
| 9085 // Logical shift right by one | |
| 9086 instruct shrI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{ | |
| 9087 match(Set dst (URShiftI dst shift)); | |
| 9088 effect(KILL cr); | |
| 9089 | |
| 9090 size(2); | |
| 9091 format %{ "SHR $dst,$shift" %} | |
| 9092 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 9093 ins_encode( OpcP, RegOpc( dst ) ); | |
| 9094 ins_pipe( ialu_reg ); | |
| 9095 %} | |
| 9096 | |
| 9097 // Logical Shift Right by 8-bit immediate | |
| 9098 instruct shrI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{ | |
| 9099 match(Set dst (URShiftI dst shift)); | |
| 9100 effect(KILL cr); | |
| 9101 | |
| 9102 size(3); | |
| 9103 format %{ "SHR $dst,$shift" %} | |
| 9104 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 9105 ins_encode( RegOpcImm( dst, shift) ); | |
| 9106 ins_pipe( ialu_reg ); | |
| 9107 %} | |
| 9108 | |
|
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|
9109 |
| 0 | 9110 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24. |
| 9111 // This idiom is used by the compiler for the i2b bytecode. | |
| 785 | 9112 instruct i2b(eRegI dst, xRegI src, immI_24 twentyfour) %{ |
| 0 | 9113 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour)); |
| 9114 | |
| 9115 size(3); | |
| 9116 format %{ "MOVSX $dst,$src :8" %} | |
| 785 | 9117 ins_encode %{ |
| 9118 __ movsbl($dst$$Register, $src$$Register); | |
| 9119 %} | |
| 9120 ins_pipe(ialu_reg_reg); | |
| 0 | 9121 %} |
| 9122 | |
| 9123 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16. | |
| 9124 // This idiom is used by the compiler the i2s bytecode. | |
| 785 | 9125 instruct i2s(eRegI dst, xRegI src, immI_16 sixteen) %{ |
| 0 | 9126 match(Set dst (RShiftI (LShiftI src sixteen) sixteen)); |
| 9127 | |
| 9128 size(3); | |
| 9129 format %{ "MOVSX $dst,$src :16" %} | |
| 785 | 9130 ins_encode %{ |
| 9131 __ movswl($dst$$Register, $src$$Register); | |
| 9132 %} | |
| 9133 ins_pipe(ialu_reg_reg); | |
| 0 | 9134 %} |
| 9135 | |
| 9136 | |
| 9137 // Logical Shift Right by variable | |
| 9138 instruct shrI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 9139 match(Set dst (URShiftI dst shift)); | |
| 9140 effect(KILL cr); | |
| 9141 | |
| 9142 size(2); | |
| 9143 format %{ "SHR $dst,$shift" %} | |
| 9144 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 9145 ins_encode( OpcP, RegOpc( dst ) ); | |
| 9146 ins_pipe( ialu_reg_reg ); | |
| 9147 %} | |
| 9148 | |
| 9149 | |
| 9150 //----------Logical Instructions----------------------------------------------- | |
| 9151 //----------Integer Logical Instructions--------------------------------------- | |
| 9152 // And Instructions | |
| 9153 // And Register with Register | |
| 9154 instruct andI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ | |
| 9155 match(Set dst (AndI dst src)); | |
| 9156 effect(KILL cr); | |
| 9157 | |
| 9158 size(2); | |
| 9159 format %{ "AND $dst,$src" %} | |
| 9160 opcode(0x23); | |
| 9161 ins_encode( OpcP, RegReg( dst, src) ); | |
| 9162 ins_pipe( ialu_reg_reg ); | |
| 9163 %} | |
| 9164 | |
| 9165 // And Register with Immediate | |
| 9166 instruct andI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ | |
| 9167 match(Set dst (AndI dst src)); | |
| 9168 effect(KILL cr); | |
| 9169 | |
| 9170 format %{ "AND $dst,$src" %} | |
| 9171 opcode(0x81,0x04); /* Opcode 81 /4 */ | |
| 9172 // ins_encode( RegImm( dst, src) ); | |
| 9173 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 9174 ins_pipe( ialu_reg ); | |
| 9175 %} | |
| 9176 | |
| 9177 // And Register with Memory | |
| 9178 instruct andI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ | |
| 9179 match(Set dst (AndI dst (LoadI src))); | |
| 9180 effect(KILL cr); | |
| 9181 | |
| 9182 ins_cost(125); | |
| 9183 format %{ "AND $dst,$src" %} | |
| 9184 opcode(0x23); | |
| 9185 ins_encode( OpcP, RegMem( dst, src) ); | |
| 9186 ins_pipe( ialu_reg_mem ); | |
| 9187 %} | |
| 9188 | |
| 9189 // And Memory with Register | |
| 9190 instruct andI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ | |
| 9191 match(Set dst (StoreI dst (AndI (LoadI dst) src))); | |
| 9192 effect(KILL cr); | |
| 9193 | |
| 9194 ins_cost(150); | |
| 9195 format %{ "AND $dst,$src" %} | |
| 9196 opcode(0x21); /* Opcode 21 /r */ | |
| 9197 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 9198 ins_pipe( ialu_mem_reg ); | |
| 9199 %} | |
| 9200 | |
| 9201 // And Memory with Immediate | |
| 9202 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 9203 match(Set dst (StoreI dst (AndI (LoadI dst) src))); | |
| 9204 effect(KILL cr); | |
| 9205 | |
| 9206 ins_cost(125); | |
| 9207 format %{ "AND $dst,$src" %} | |
| 9208 opcode(0x81, 0x4); /* Opcode 81 /4 id */ | |
| 9209 // ins_encode( MemImm( dst, src) ); | |
| 9210 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); | |
| 9211 ins_pipe( ialu_mem_imm ); | |
| 9212 %} | |
| 9213 | |
| 9214 // Or Instructions | |
| 9215 // Or Register with Register | |
| 9216 instruct orI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ | |
| 9217 match(Set dst (OrI dst src)); | |
| 9218 effect(KILL cr); | |
| 9219 | |
| 9220 size(2); | |
| 9221 format %{ "OR $dst,$src" %} | |
| 9222 opcode(0x0B); | |
| 9223 ins_encode( OpcP, RegReg( dst, src) ); | |
| 9224 ins_pipe( ialu_reg_reg ); | |
| 9225 %} | |
| 9226 | |
|
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|
9227 instruct orI_eReg_castP2X(eRegI dst, eRegP src, eFlagsReg cr) %{ |
|
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|
9228 match(Set dst (OrI dst (CastP2X src))); |
|
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|
9229 effect(KILL cr); |
|
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|
9230 |
|
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|
9231 size(2); |
|
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|
9232 format %{ "OR $dst,$src" %} |
|
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|
9233 opcode(0x0B); |
|
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|
9234 ins_encode( OpcP, RegReg( dst, src) ); |
|
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|
9235 ins_pipe( ialu_reg_reg ); |
|
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|
9236 %} |
|
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|
9237 |
|
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|
9238 |
| 0 | 9239 // Or Register with Immediate |
| 9240 instruct orI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ | |
| 9241 match(Set dst (OrI dst src)); | |
| 9242 effect(KILL cr); | |
| 9243 | |
| 9244 format %{ "OR $dst,$src" %} | |
| 9245 opcode(0x81,0x01); /* Opcode 81 /1 id */ | |
| 9246 // ins_encode( RegImm( dst, src) ); | |
| 9247 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 9248 ins_pipe( ialu_reg ); | |
| 9249 %} | |
| 9250 | |
| 9251 // Or Register with Memory | |
| 9252 instruct orI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ | |
| 9253 match(Set dst (OrI dst (LoadI src))); | |
| 9254 effect(KILL cr); | |
| 9255 | |
| 9256 ins_cost(125); | |
| 9257 format %{ "OR $dst,$src" %} | |
| 9258 opcode(0x0B); | |
| 9259 ins_encode( OpcP, RegMem( dst, src) ); | |
| 9260 ins_pipe( ialu_reg_mem ); | |
| 9261 %} | |
| 9262 | |
| 9263 // Or Memory with Register | |
| 9264 instruct orI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ | |
| 9265 match(Set dst (StoreI dst (OrI (LoadI dst) src))); | |
| 9266 effect(KILL cr); | |
| 9267 | |
| 9268 ins_cost(150); | |
| 9269 format %{ "OR $dst,$src" %} | |
| 9270 opcode(0x09); /* Opcode 09 /r */ | |
| 9271 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 9272 ins_pipe( ialu_mem_reg ); | |
| 9273 %} | |
| 9274 | |
| 9275 // Or Memory with Immediate | |
| 9276 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 9277 match(Set dst (StoreI dst (OrI (LoadI dst) src))); | |
| 9278 effect(KILL cr); | |
| 9279 | |
| 9280 ins_cost(125); | |
| 9281 format %{ "OR $dst,$src" %} | |
| 9282 opcode(0x81,0x1); /* Opcode 81 /1 id */ | |
| 9283 // ins_encode( MemImm( dst, src) ); | |
| 9284 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); | |
| 9285 ins_pipe( ialu_mem_imm ); | |
| 9286 %} | |
| 9287 | |
| 9288 // ROL/ROR | |
| 9289 // ROL expand | |
| 9290 instruct rolI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{ | |
| 9291 effect(USE_DEF dst, USE shift, KILL cr); | |
| 9292 | |
| 9293 format %{ "ROL $dst, $shift" %} | |
| 9294 opcode(0xD1, 0x0); /* Opcode D1 /0 */ | |
| 9295 ins_encode( OpcP, RegOpc( dst )); | |
| 9296 ins_pipe( ialu_reg ); | |
| 9297 %} | |
| 9298 | |
| 9299 instruct rolI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{ | |
| 9300 effect(USE_DEF dst, USE shift, KILL cr); | |
| 9301 | |
| 9302 format %{ "ROL $dst, $shift" %} | |
| 9303 opcode(0xC1, 0x0); /*Opcode /C1 /0 */ | |
| 9304 ins_encode( RegOpcImm(dst, shift) ); | |
| 9305 ins_pipe(ialu_reg); | |
| 9306 %} | |
| 9307 | |
| 9308 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 9309 effect(USE_DEF dst, USE shift, KILL cr); | |
| 9310 | |
| 9311 format %{ "ROL $dst, $shift" %} | |
| 9312 opcode(0xD3, 0x0); /* Opcode D3 /0 */ | |
| 9313 ins_encode(OpcP, RegOpc(dst)); | |
| 9314 ins_pipe( ialu_reg_reg ); | |
| 9315 %} | |
| 9316 // end of ROL expand | |
| 9317 | |
| 9318 // ROL 32bit by one once | |
| 9319 instruct rolI_eReg_i1(eRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{ | |
| 9320 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift))); | |
| 9321 | |
| 9322 expand %{ | |
| 9323 rolI_eReg_imm1(dst, lshift, cr); | |
| 9324 %} | |
| 9325 %} | |
| 9326 | |
| 9327 // ROL 32bit var by imm8 once | |
| 9328 instruct rolI_eReg_i8(eRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{ | |
| 9329 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); | |
| 9330 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift))); | |
| 9331 | |
| 9332 expand %{ | |
| 9333 rolI_eReg_imm8(dst, lshift, cr); | |
| 9334 %} | |
| 9335 %} | |
| 9336 | |
| 9337 // ROL 32bit var by var once | |
| 9338 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{ | |
| 9339 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift)))); | |
| 9340 | |
| 9341 expand %{ | |
| 9342 rolI_eReg_CL(dst, shift, cr); | |
| 9343 %} | |
| 9344 %} | |
| 9345 | |
| 9346 // ROL 32bit var by var once | |
| 9347 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{ | |
| 9348 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift)))); | |
| 9349 | |
| 9350 expand %{ | |
| 9351 rolI_eReg_CL(dst, shift, cr); | |
| 9352 %} | |
| 9353 %} | |
| 9354 | |
| 9355 // ROR expand | |
| 9356 instruct rorI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{ | |
| 9357 effect(USE_DEF dst, USE shift, KILL cr); | |
| 9358 | |
| 9359 format %{ "ROR $dst, $shift" %} | |
| 9360 opcode(0xD1,0x1); /* Opcode D1 /1 */ | |
| 9361 ins_encode( OpcP, RegOpc( dst ) ); | |
| 9362 ins_pipe( ialu_reg ); | |
| 9363 %} | |
| 9364 | |
| 9365 instruct rorI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{ | |
| 9366 effect (USE_DEF dst, USE shift, KILL cr); | |
| 9367 | |
| 9368 format %{ "ROR $dst, $shift" %} | |
| 9369 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */ | |
| 9370 ins_encode( RegOpcImm(dst, shift) ); | |
| 9371 ins_pipe( ialu_reg ); | |
| 9372 %} | |
| 9373 | |
| 9374 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{ | |
| 9375 effect(USE_DEF dst, USE shift, KILL cr); | |
| 9376 | |
| 9377 format %{ "ROR $dst, $shift" %} | |
| 9378 opcode(0xD3, 0x1); /* Opcode D3 /1 */ | |
| 9379 ins_encode(OpcP, RegOpc(dst)); | |
| 9380 ins_pipe( ialu_reg_reg ); | |
| 9381 %} | |
| 9382 // end of ROR expand | |
| 9383 | |
| 9384 // ROR right once | |
| 9385 instruct rorI_eReg_i1(eRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{ | |
| 9386 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift))); | |
| 9387 | |
| 9388 expand %{ | |
| 9389 rorI_eReg_imm1(dst, rshift, cr); | |
| 9390 %} | |
| 9391 %} | |
| 9392 | |
| 9393 // ROR 32bit by immI8 once | |
| 9394 instruct rorI_eReg_i8(eRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{ | |
| 9395 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); | |
| 9396 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift))); | |
| 9397 | |
| 9398 expand %{ | |
| 9399 rorI_eReg_imm8(dst, rshift, cr); | |
| 9400 %} | |
| 9401 %} | |
| 9402 | |
| 9403 // ROR 32bit var by var once | |
| 9404 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{ | |
| 9405 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift)))); | |
| 9406 | |
| 9407 expand %{ | |
| 9408 rorI_eReg_CL(dst, shift, cr); | |
| 9409 %} | |
| 9410 %} | |
| 9411 | |
| 9412 // ROR 32bit var by var once | |
| 9413 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{ | |
| 9414 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift)))); | |
| 9415 | |
| 9416 expand %{ | |
| 9417 rorI_eReg_CL(dst, shift, cr); | |
| 9418 %} | |
| 9419 %} | |
| 9420 | |
| 9421 // Xor Instructions | |
| 9422 // Xor Register with Register | |
| 9423 instruct xorI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ | |
| 9424 match(Set dst (XorI dst src)); | |
| 9425 effect(KILL cr); | |
| 9426 | |
| 9427 size(2); | |
| 9428 format %{ "XOR $dst,$src" %} | |
| 9429 opcode(0x33); | |
| 9430 ins_encode( OpcP, RegReg( dst, src) ); | |
| 9431 ins_pipe( ialu_reg_reg ); | |
| 9432 %} | |
| 9433 | |
| 403 | 9434 // Xor Register with Immediate -1 |
| 9435 instruct xorI_eReg_im1(eRegI dst, immI_M1 imm) %{ | |
| 9436 match(Set dst (XorI dst imm)); | |
| 9437 | |
| 9438 size(2); | |
| 9439 format %{ "NOT $dst" %} | |
| 9440 ins_encode %{ | |
| 9441 __ notl($dst$$Register); | |
| 9442 %} | |
| 9443 ins_pipe( ialu_reg ); | |
| 9444 %} | |
| 9445 | |
| 0 | 9446 // Xor Register with Immediate |
| 9447 instruct xorI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ | |
| 9448 match(Set dst (XorI dst src)); | |
| 9449 effect(KILL cr); | |
| 9450 | |
| 9451 format %{ "XOR $dst,$src" %} | |
| 9452 opcode(0x81,0x06); /* Opcode 81 /6 id */ | |
| 9453 // ins_encode( RegImm( dst, src) ); | |
| 9454 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 9455 ins_pipe( ialu_reg ); | |
| 9456 %} | |
| 9457 | |
| 9458 // Xor Register with Memory | |
| 9459 instruct xorI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ | |
| 9460 match(Set dst (XorI dst (LoadI src))); | |
| 9461 effect(KILL cr); | |
| 9462 | |
| 9463 ins_cost(125); | |
| 9464 format %{ "XOR $dst,$src" %} | |
| 9465 opcode(0x33); | |
| 9466 ins_encode( OpcP, RegMem(dst, src) ); | |
| 9467 ins_pipe( ialu_reg_mem ); | |
| 9468 %} | |
| 9469 | |
| 9470 // Xor Memory with Register | |
| 9471 instruct xorI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ | |
| 9472 match(Set dst (StoreI dst (XorI (LoadI dst) src))); | |
| 9473 effect(KILL cr); | |
| 9474 | |
| 9475 ins_cost(150); | |
| 9476 format %{ "XOR $dst,$src" %} | |
| 9477 opcode(0x31); /* Opcode 31 /r */ | |
| 9478 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 9479 ins_pipe( ialu_mem_reg ); | |
| 9480 %} | |
| 9481 | |
| 9482 // Xor Memory with Immediate | |
| 9483 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 9484 match(Set dst (StoreI dst (XorI (LoadI dst) src))); | |
| 9485 effect(KILL cr); | |
| 9486 | |
| 9487 ins_cost(125); | |
| 9488 format %{ "XOR $dst,$src" %} | |
| 9489 opcode(0x81,0x6); /* Opcode 81 /6 id */ | |
| 9490 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); | |
| 9491 ins_pipe( ialu_mem_imm ); | |
| 9492 %} | |
| 9493 | |
| 9494 //----------Convert Int to Boolean--------------------------------------------- | |
| 9495 | |
| 9496 instruct movI_nocopy(eRegI dst, eRegI src) %{ | |
| 9497 effect( DEF dst, USE src ); | |
| 9498 format %{ "MOV $dst,$src" %} | |
| 9499 ins_encode( enc_Copy( dst, src) ); | |
| 9500 ins_pipe( ialu_reg_reg ); | |
| 9501 %} | |
| 9502 | |
| 9503 instruct ci2b( eRegI dst, eRegI src, eFlagsReg cr ) %{ | |
| 9504 effect( USE_DEF dst, USE src, KILL cr ); | |
| 9505 | |
| 9506 size(4); | |
| 9507 format %{ "NEG $dst\n\t" | |
| 9508 "ADC $dst,$src" %} | |
| 9509 ins_encode( neg_reg(dst), | |
| 9510 OpcRegReg(0x13,dst,src) ); | |
| 9511 ins_pipe( ialu_reg_reg_long ); | |
| 9512 %} | |
| 9513 | |
| 9514 instruct convI2B( eRegI dst, eRegI src, eFlagsReg cr ) %{ | |
| 9515 match(Set dst (Conv2B src)); | |
| 9516 | |
| 9517 expand %{ | |
| 9518 movI_nocopy(dst,src); | |
| 9519 ci2b(dst,src,cr); | |
| 9520 %} | |
| 9521 %} | |
| 9522 | |
| 9523 instruct movP_nocopy(eRegI dst, eRegP src) %{ | |
| 9524 effect( DEF dst, USE src ); | |
| 9525 format %{ "MOV $dst,$src" %} | |
| 9526 ins_encode( enc_Copy( dst, src) ); | |
| 9527 ins_pipe( ialu_reg_reg ); | |
| 9528 %} | |
| 9529 | |
| 9530 instruct cp2b( eRegI dst, eRegP src, eFlagsReg cr ) %{ | |
| 9531 effect( USE_DEF dst, USE src, KILL cr ); | |
| 9532 format %{ "NEG $dst\n\t" | |
| 9533 "ADC $dst,$src" %} | |
| 9534 ins_encode( neg_reg(dst), | |
| 9535 OpcRegReg(0x13,dst,src) ); | |
| 9536 ins_pipe( ialu_reg_reg_long ); | |
| 9537 %} | |
| 9538 | |
| 9539 instruct convP2B( eRegI dst, eRegP src, eFlagsReg cr ) %{ | |
| 9540 match(Set dst (Conv2B src)); | |
| 9541 | |
| 9542 expand %{ | |
| 9543 movP_nocopy(dst,src); | |
| 9544 cp2b(dst,src,cr); | |
| 9545 %} | |
| 9546 %} | |
| 9547 | |
| 9548 instruct cmpLTMask( eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr ) %{ | |
| 9549 match(Set dst (CmpLTMask p q)); | |
| 9550 effect( KILL cr ); | |
| 9551 ins_cost(400); | |
| 9552 | |
| 9553 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination | |
| 9554 format %{ "XOR $dst,$dst\n\t" | |
| 9555 "CMP $p,$q\n\t" | |
| 9556 "SETlt $dst\n\t" | |
| 9557 "NEG $dst" %} | |
| 9558 ins_encode( OpcRegReg(0x33,dst,dst), | |
| 9559 OpcRegReg(0x3B,p,q), | |
| 9560 setLT_reg(dst), neg_reg(dst) ); | |
| 9561 ins_pipe( pipe_slow ); | |
| 9562 %} | |
| 9563 | |
| 9564 instruct cmpLTMask0( eRegI dst, immI0 zero, eFlagsReg cr ) %{ | |
| 9565 match(Set dst (CmpLTMask dst zero)); | |
| 9566 effect( DEF dst, KILL cr ); | |
| 9567 ins_cost(100); | |
| 9568 | |
| 9569 format %{ "SAR $dst,31" %} | |
| 9570 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 9571 ins_encode( RegOpcImm( dst, 0x1F ) ); | |
| 9572 ins_pipe( ialu_reg ); | |
| 9573 %} | |
| 9574 | |
| 9575 | |
| 9576 instruct cadd_cmpLTMask( ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp, eFlagsReg cr ) %{ | |
| 9577 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); | |
| 9578 effect( KILL tmp, KILL cr ); | |
| 9579 ins_cost(400); | |
| 9580 // annoyingly, $tmp has no edges so you cant ask for it in | |
| 9581 // any format or encoding | |
| 9582 format %{ "SUB $p,$q\n\t" | |
| 9583 "SBB ECX,ECX\n\t" | |
| 9584 "AND ECX,$y\n\t" | |
| 9585 "ADD $p,ECX" %} | |
| 9586 ins_encode( enc_cmpLTP(p,q,y,tmp) ); | |
| 9587 ins_pipe( pipe_cmplt ); | |
| 9588 %} | |
| 9589 | |
| 9590 /* If I enable this, I encourage spilling in the inner loop of compress. | |
| 9591 instruct cadd_cmpLTMask_mem( ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr ) %{ | |
| 9592 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q))); | |
| 9593 effect( USE_KILL tmp, KILL cr ); | |
| 9594 ins_cost(400); | |
| 9595 | |
| 9596 format %{ "SUB $p,$q\n\t" | |
| 9597 "SBB ECX,ECX\n\t" | |
| 9598 "AND ECX,$y\n\t" | |
| 9599 "ADD $p,ECX" %} | |
| 9600 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) ); | |
| 9601 %} | |
| 9602 */ | |
| 9603 | |
| 9604 //----------Long Instructions------------------------------------------------ | |
| 9605 // Add Long Register with Register | |
| 9606 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 9607 match(Set dst (AddL dst src)); | |
| 9608 effect(KILL cr); | |
| 9609 ins_cost(200); | |
| 9610 format %{ "ADD $dst.lo,$src.lo\n\t" | |
| 9611 "ADC $dst.hi,$src.hi" %} | |
| 9612 opcode(0x03, 0x13); | |
| 9613 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) ); | |
| 9614 ins_pipe( ialu_reg_reg_long ); | |
| 9615 %} | |
| 9616 | |
| 9617 // Add Long Register with Immediate | |
| 9618 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 9619 match(Set dst (AddL dst src)); | |
| 9620 effect(KILL cr); | |
| 9621 format %{ "ADD $dst.lo,$src.lo\n\t" | |
| 9622 "ADC $dst.hi,$src.hi" %} | |
| 9623 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */ | |
| 9624 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 9625 ins_pipe( ialu_reg_long ); | |
| 9626 %} | |
| 9627 | |
| 9628 // Add Long Register with Memory | |
| 9629 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 9630 match(Set dst (AddL dst (LoadL mem))); | |
| 9631 effect(KILL cr); | |
| 9632 ins_cost(125); | |
| 9633 format %{ "ADD $dst.lo,$mem\n\t" | |
| 9634 "ADC $dst.hi,$mem+4" %} | |
| 9635 opcode(0x03, 0x13); | |
| 9636 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 9637 ins_pipe( ialu_reg_long_mem ); | |
| 9638 %} | |
| 9639 | |
| 9640 // Subtract Long Register with Register. | |
| 9641 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 9642 match(Set dst (SubL dst src)); | |
| 9643 effect(KILL cr); | |
| 9644 ins_cost(200); | |
| 9645 format %{ "SUB $dst.lo,$src.lo\n\t" | |
| 9646 "SBB $dst.hi,$src.hi" %} | |
| 9647 opcode(0x2B, 0x1B); | |
| 9648 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) ); | |
| 9649 ins_pipe( ialu_reg_reg_long ); | |
| 9650 %} | |
| 9651 | |
| 9652 // Subtract Long Register with Immediate | |
| 9653 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 9654 match(Set dst (SubL dst src)); | |
| 9655 effect(KILL cr); | |
| 9656 format %{ "SUB $dst.lo,$src.lo\n\t" | |
| 9657 "SBB $dst.hi,$src.hi" %} | |
| 9658 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */ | |
| 9659 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 9660 ins_pipe( ialu_reg_long ); | |
| 9661 %} | |
| 9662 | |
| 9663 // Subtract Long Register with Memory | |
| 9664 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 9665 match(Set dst (SubL dst (LoadL mem))); | |
| 9666 effect(KILL cr); | |
| 9667 ins_cost(125); | |
| 9668 format %{ "SUB $dst.lo,$mem\n\t" | |
| 9669 "SBB $dst.hi,$mem+4" %} | |
| 9670 opcode(0x2B, 0x1B); | |
| 9671 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 9672 ins_pipe( ialu_reg_long_mem ); | |
| 9673 %} | |
| 9674 | |
| 9675 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{ | |
| 9676 match(Set dst (SubL zero dst)); | |
| 9677 effect(KILL cr); | |
| 9678 ins_cost(300); | |
| 9679 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %} | |
| 9680 ins_encode( neg_long(dst) ); | |
| 9681 ins_pipe( ialu_reg_reg_long ); | |
| 9682 %} | |
| 9683 | |
| 9684 // And Long Register with Register | |
| 9685 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 9686 match(Set dst (AndL dst src)); | |
| 9687 effect(KILL cr); | |
| 9688 format %{ "AND $dst.lo,$src.lo\n\t" | |
| 9689 "AND $dst.hi,$src.hi" %} | |
| 9690 opcode(0x23,0x23); | |
| 9691 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); | |
| 9692 ins_pipe( ialu_reg_reg_long ); | |
| 9693 %} | |
| 9694 | |
| 9695 // And Long Register with Immediate | |
| 9696 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 9697 match(Set dst (AndL dst src)); | |
| 9698 effect(KILL cr); | |
| 9699 format %{ "AND $dst.lo,$src.lo\n\t" | |
| 9700 "AND $dst.hi,$src.hi" %} | |
| 9701 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */ | |
| 9702 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 9703 ins_pipe( ialu_reg_long ); | |
| 9704 %} | |
| 9705 | |
| 9706 // And Long Register with Memory | |
| 9707 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 9708 match(Set dst (AndL dst (LoadL mem))); | |
| 9709 effect(KILL cr); | |
| 9710 ins_cost(125); | |
| 9711 format %{ "AND $dst.lo,$mem\n\t" | |
| 9712 "AND $dst.hi,$mem+4" %} | |
| 9713 opcode(0x23, 0x23); | |
| 9714 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 9715 ins_pipe( ialu_reg_long_mem ); | |
| 9716 %} | |
| 9717 | |
| 9718 // Or Long Register with Register | |
| 9719 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 9720 match(Set dst (OrL dst src)); | |
| 9721 effect(KILL cr); | |
| 9722 format %{ "OR $dst.lo,$src.lo\n\t" | |
| 9723 "OR $dst.hi,$src.hi" %} | |
| 9724 opcode(0x0B,0x0B); | |
| 9725 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); | |
| 9726 ins_pipe( ialu_reg_reg_long ); | |
| 9727 %} | |
| 9728 | |
| 9729 // Or Long Register with Immediate | |
| 9730 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 9731 match(Set dst (OrL dst src)); | |
| 9732 effect(KILL cr); | |
| 9733 format %{ "OR $dst.lo,$src.lo\n\t" | |
| 9734 "OR $dst.hi,$src.hi" %} | |
| 9735 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */ | |
| 9736 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 9737 ins_pipe( ialu_reg_long ); | |
| 9738 %} | |
| 9739 | |
| 9740 // Or Long Register with Memory | |
| 9741 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 9742 match(Set dst (OrL dst (LoadL mem))); | |
| 9743 effect(KILL cr); | |
| 9744 ins_cost(125); | |
| 9745 format %{ "OR $dst.lo,$mem\n\t" | |
| 9746 "OR $dst.hi,$mem+4" %} | |
| 9747 opcode(0x0B,0x0B); | |
| 9748 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 9749 ins_pipe( ialu_reg_long_mem ); | |
| 9750 %} | |
| 9751 | |
| 9752 // Xor Long Register with Register | |
| 9753 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 9754 match(Set dst (XorL dst src)); | |
| 9755 effect(KILL cr); | |
| 9756 format %{ "XOR $dst.lo,$src.lo\n\t" | |
| 9757 "XOR $dst.hi,$src.hi" %} | |
| 9758 opcode(0x33,0x33); | |
| 9759 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); | |
| 9760 ins_pipe( ialu_reg_reg_long ); | |
| 9761 %} | |
| 9762 | |
| 403 | 9763 // Xor Long Register with Immediate -1 |
| 9764 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{ | |
| 9765 match(Set dst (XorL dst imm)); | |
| 9766 format %{ "NOT $dst.lo\n\t" | |
| 9767 "NOT $dst.hi" %} | |
| 9768 ins_encode %{ | |
| 9769 __ notl($dst$$Register); | |
| 9770 __ notl(HIGH_FROM_LOW($dst$$Register)); | |
| 9771 %} | |
| 9772 ins_pipe( ialu_reg_long ); | |
| 9773 %} | |
| 9774 | |
| 0 | 9775 // Xor Long Register with Immediate |
| 9776 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 9777 match(Set dst (XorL dst src)); | |
| 9778 effect(KILL cr); | |
| 9779 format %{ "XOR $dst.lo,$src.lo\n\t" | |
| 9780 "XOR $dst.hi,$src.hi" %} | |
| 9781 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */ | |
| 9782 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 9783 ins_pipe( ialu_reg_long ); | |
| 9784 %} | |
| 9785 | |
| 9786 // Xor Long Register with Memory | |
| 9787 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 9788 match(Set dst (XorL dst (LoadL mem))); | |
| 9789 effect(KILL cr); | |
| 9790 ins_cost(125); | |
| 9791 format %{ "XOR $dst.lo,$mem\n\t" | |
| 9792 "XOR $dst.hi,$mem+4" %} | |
| 9793 opcode(0x33,0x33); | |
| 9794 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 9795 ins_pipe( ialu_reg_long_mem ); | |
| 9796 %} | |
| 9797 | |
| 219 | 9798 // Shift Left Long by 1 |
| 9799 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{ | |
| 9800 predicate(UseNewLongLShift); | |
| 9801 match(Set dst (LShiftL dst cnt)); | |
| 9802 effect(KILL cr); | |
| 9803 ins_cost(100); | |
| 9804 format %{ "ADD $dst.lo,$dst.lo\n\t" | |
| 9805 "ADC $dst.hi,$dst.hi" %} | |
| 9806 ins_encode %{ | |
| 9807 __ addl($dst$$Register,$dst$$Register); | |
| 9808 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9809 %} | |
| 9810 ins_pipe( ialu_reg_long ); | |
| 9811 %} | |
| 9812 | |
| 9813 // Shift Left Long by 2 | |
| 9814 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{ | |
| 9815 predicate(UseNewLongLShift); | |
| 9816 match(Set dst (LShiftL dst cnt)); | |
| 9817 effect(KILL cr); | |
| 9818 ins_cost(100); | |
| 9819 format %{ "ADD $dst.lo,$dst.lo\n\t" | |
| 9820 "ADC $dst.hi,$dst.hi\n\t" | |
| 9821 "ADD $dst.lo,$dst.lo\n\t" | |
| 9822 "ADC $dst.hi,$dst.hi" %} | |
| 9823 ins_encode %{ | |
| 9824 __ addl($dst$$Register,$dst$$Register); | |
| 9825 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9826 __ addl($dst$$Register,$dst$$Register); | |
| 9827 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9828 %} | |
| 9829 ins_pipe( ialu_reg_long ); | |
| 9830 %} | |
| 9831 | |
| 9832 // Shift Left Long by 3 | |
| 9833 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{ | |
| 9834 predicate(UseNewLongLShift); | |
| 9835 match(Set dst (LShiftL dst cnt)); | |
| 9836 effect(KILL cr); | |
| 9837 ins_cost(100); | |
| 9838 format %{ "ADD $dst.lo,$dst.lo\n\t" | |
| 9839 "ADC $dst.hi,$dst.hi\n\t" | |
| 9840 "ADD $dst.lo,$dst.lo\n\t" | |
| 9841 "ADC $dst.hi,$dst.hi\n\t" | |
| 9842 "ADD $dst.lo,$dst.lo\n\t" | |
| 9843 "ADC $dst.hi,$dst.hi" %} | |
| 9844 ins_encode %{ | |
| 9845 __ addl($dst$$Register,$dst$$Register); | |
| 9846 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9847 __ addl($dst$$Register,$dst$$Register); | |
| 9848 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9849 __ addl($dst$$Register,$dst$$Register); | |
| 9850 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9851 %} | |
| 9852 ins_pipe( ialu_reg_long ); | |
| 9853 %} | |
| 9854 | |
| 0 | 9855 // Shift Left Long by 1-31 |
| 9856 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ | |
| 9857 match(Set dst (LShiftL dst cnt)); | |
| 9858 effect(KILL cr); | |
| 9859 ins_cost(200); | |
| 9860 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t" | |
| 9861 "SHL $dst.lo,$cnt" %} | |
| 9862 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */ | |
| 9863 ins_encode( move_long_small_shift(dst,cnt) ); | |
| 9864 ins_pipe( ialu_reg_long ); | |
| 9865 %} | |
| 9866 | |
| 9867 // Shift Left Long by 32-63 | |
| 9868 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 9869 match(Set dst (LShiftL dst cnt)); | |
| 9870 effect(KILL cr); | |
| 9871 ins_cost(300); | |
| 9872 format %{ "MOV $dst.hi,$dst.lo\n" | |
| 9873 "\tSHL $dst.hi,$cnt-32\n" | |
| 9874 "\tXOR $dst.lo,$dst.lo" %} | |
| 9875 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 9876 ins_encode( move_long_big_shift_clr(dst,cnt) ); | |
| 9877 ins_pipe( ialu_reg_long ); | |
| 9878 %} | |
| 9879 | |
| 9880 // Shift Left Long by variable | |
| 9881 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 9882 match(Set dst (LShiftL dst shift)); | |
| 9883 effect(KILL cr); | |
| 9884 ins_cost(500+200); | |
| 9885 size(17); | |
| 9886 format %{ "TEST $shift,32\n\t" | |
| 9887 "JEQ,s small\n\t" | |
| 9888 "MOV $dst.hi,$dst.lo\n\t" | |
| 9889 "XOR $dst.lo,$dst.lo\n" | |
| 9890 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t" | |
| 9891 "SHL $dst.lo,$shift" %} | |
| 9892 ins_encode( shift_left_long( dst, shift ) ); | |
| 9893 ins_pipe( pipe_slow ); | |
| 9894 %} | |
| 9895 | |
| 9896 // Shift Right Long by 1-31 | |
| 9897 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ | |
| 9898 match(Set dst (URShiftL dst cnt)); | |
| 9899 effect(KILL cr); | |
| 9900 ins_cost(200); | |
| 9901 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t" | |
| 9902 "SHR $dst.hi,$cnt" %} | |
| 9903 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */ | |
| 9904 ins_encode( move_long_small_shift(dst,cnt) ); | |
| 9905 ins_pipe( ialu_reg_long ); | |
| 9906 %} | |
| 9907 | |
| 9908 // Shift Right Long by 32-63 | |
| 9909 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 9910 match(Set dst (URShiftL dst cnt)); | |
| 9911 effect(KILL cr); | |
| 9912 ins_cost(300); | |
| 9913 format %{ "MOV $dst.lo,$dst.hi\n" | |
| 9914 "\tSHR $dst.lo,$cnt-32\n" | |
| 9915 "\tXOR $dst.hi,$dst.hi" %} | |
| 9916 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 9917 ins_encode( move_long_big_shift_clr(dst,cnt) ); | |
| 9918 ins_pipe( ialu_reg_long ); | |
| 9919 %} | |
| 9920 | |
| 9921 // Shift Right Long by variable | |
| 9922 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 9923 match(Set dst (URShiftL dst shift)); | |
| 9924 effect(KILL cr); | |
| 9925 ins_cost(600); | |
| 9926 size(17); | |
| 9927 format %{ "TEST $shift,32\n\t" | |
| 9928 "JEQ,s small\n\t" | |
| 9929 "MOV $dst.lo,$dst.hi\n\t" | |
| 9930 "XOR $dst.hi,$dst.hi\n" | |
| 9931 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t" | |
| 9932 "SHR $dst.hi,$shift" %} | |
| 9933 ins_encode( shift_right_long( dst, shift ) ); | |
| 9934 ins_pipe( pipe_slow ); | |
| 9935 %} | |
| 9936 | |
| 9937 // Shift Right Long by 1-31 | |
| 9938 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ | |
| 9939 match(Set dst (RShiftL dst cnt)); | |
| 9940 effect(KILL cr); | |
| 9941 ins_cost(200); | |
| 9942 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t" | |
| 9943 "SAR $dst.hi,$cnt" %} | |
| 9944 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */ | |
| 9945 ins_encode( move_long_small_shift(dst,cnt) ); | |
| 9946 ins_pipe( ialu_reg_long ); | |
| 9947 %} | |
| 9948 | |
| 9949 // Shift Right Long by 32-63 | |
| 9950 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 9951 match(Set dst (RShiftL dst cnt)); | |
| 9952 effect(KILL cr); | |
| 9953 ins_cost(300); | |
| 9954 format %{ "MOV $dst.lo,$dst.hi\n" | |
| 9955 "\tSAR $dst.lo,$cnt-32\n" | |
| 9956 "\tSAR $dst.hi,31" %} | |
| 9957 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 9958 ins_encode( move_long_big_shift_sign(dst,cnt) ); | |
| 9959 ins_pipe( ialu_reg_long ); | |
| 9960 %} | |
| 9961 | |
| 9962 // Shift Right arithmetic Long by variable | |
| 9963 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 9964 match(Set dst (RShiftL dst shift)); | |
| 9965 effect(KILL cr); | |
| 9966 ins_cost(600); | |
| 9967 size(18); | |
| 9968 format %{ "TEST $shift,32\n\t" | |
| 9969 "JEQ,s small\n\t" | |
| 9970 "MOV $dst.lo,$dst.hi\n\t" | |
| 9971 "SAR $dst.hi,31\n" | |
| 9972 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t" | |
| 9973 "SAR $dst.hi,$shift" %} | |
| 9974 ins_encode( shift_right_arith_long( dst, shift ) ); | |
| 9975 ins_pipe( pipe_slow ); | |
| 9976 %} | |
| 9977 | |
| 9978 | |
| 9979 //----------Double Instructions------------------------------------------------ | |
| 9980 // Double Math | |
| 9981 | |
| 9982 // Compare & branch | |
| 9983 | |
| 9984 // P6 version of float compare, sets condition codes in EFLAGS | |
| 9985 instruct cmpD_cc_P6(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{ | |
| 9986 predicate(VM_Version::supports_cmov() && UseSSE <=1); | |
| 9987 match(Set cr (CmpD src1 src2)); | |
| 9988 effect(KILL rax); | |
| 9989 ins_cost(150); | |
| 9990 format %{ "FLD $src1\n\t" | |
| 9991 "FUCOMIP ST,$src2 // P6 instruction\n\t" | |
| 9992 "JNP exit\n\t" | |
| 9993 "MOV ah,1 // saw a NaN, set CF\n\t" | |
| 9994 "SAHF\n" | |
| 9995 "exit:\tNOP // avoid branch to branch" %} | |
| 9996 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ | |
| 9997 ins_encode( Push_Reg_D(src1), | |
| 9998 OpcP, RegOpc(src2), | |
| 9999 cmpF_P6_fixup ); | |
| 10000 ins_pipe( pipe_slow ); | |
| 10001 %} | |
| 10002 | |
|
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10003 instruct cmpD_cc_P6CF(eFlagsRegUCF cr, regD src1, regD src2) %{ |
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10004 predicate(VM_Version::supports_cmov() && UseSSE <=1); |
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10005 match(Set cr (CmpD src1 src2)); |
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10006 ins_cost(150); |
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10007 format %{ "FLD $src1\n\t" |
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10008 "FUCOMIP ST,$src2 // P6 instruction" %} |
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10009 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ |
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10010 ins_encode( Push_Reg_D(src1), |
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10011 OpcP, RegOpc(src2)); |
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10012 ins_pipe( pipe_slow ); |
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10013 %} |
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10014 |
| 0 | 10015 // Compare & branch |
| 10016 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{ | |
| 10017 predicate(UseSSE<=1); | |
| 10018 match(Set cr (CmpD src1 src2)); | |
| 10019 effect(KILL rax); | |
| 10020 ins_cost(200); | |
| 10021 format %{ "FLD $src1\n\t" | |
| 10022 "FCOMp $src2\n\t" | |
| 10023 "FNSTSW AX\n\t" | |
| 10024 "TEST AX,0x400\n\t" | |
| 10025 "JZ,s flags\n\t" | |
| 10026 "MOV AH,1\t# unordered treat as LT\n" | |
| 10027 "flags:\tSAHF" %} | |
| 10028 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
| 10029 ins_encode( Push_Reg_D(src1), | |
| 10030 OpcP, RegOpc(src2), | |
| 10031 fpu_flags); | |
| 10032 ins_pipe( pipe_slow ); | |
| 10033 %} | |
| 10034 | |
| 10035 // Compare vs zero into -1,0,1 | |
| 10036 instruct cmpD_0(eRegI dst, regD src1, immD0 zero, eAXRegI rax, eFlagsReg cr) %{ | |
| 10037 predicate(UseSSE<=1); | |
| 10038 match(Set dst (CmpD3 src1 zero)); | |
| 10039 effect(KILL cr, KILL rax); | |
| 10040 ins_cost(280); | |
| 10041 format %{ "FTSTD $dst,$src1" %} | |
| 10042 opcode(0xE4, 0xD9); | |
| 10043 ins_encode( Push_Reg_D(src1), | |
| 10044 OpcS, OpcP, PopFPU, | |
| 10045 CmpF_Result(dst)); | |
| 10046 ins_pipe( pipe_slow ); | |
| 10047 %} | |
| 10048 | |
| 10049 // Compare into -1,0,1 | |
| 10050 instruct cmpD_reg(eRegI dst, regD src1, regD src2, eAXRegI rax, eFlagsReg cr) %{ | |
| 10051 predicate(UseSSE<=1); | |
| 10052 match(Set dst (CmpD3 src1 src2)); | |
| 10053 effect(KILL cr, KILL rax); | |
| 10054 ins_cost(300); | |
| 10055 format %{ "FCMPD $dst,$src1,$src2" %} | |
| 10056 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
| 10057 ins_encode( Push_Reg_D(src1), | |
| 10058 OpcP, RegOpc(src2), | |
| 10059 CmpF_Result(dst)); | |
| 10060 ins_pipe( pipe_slow ); | |
| 10061 %} | |
| 10062 | |
| 10063 // float compare and set condition codes in EFLAGS by XMM regs | |
| 10064 instruct cmpXD_cc(eFlagsRegU cr, regXD dst, regXD src, eAXRegI rax) %{ | |
| 10065 predicate(UseSSE>=2); | |
| 10066 match(Set cr (CmpD dst src)); | |
| 10067 effect(KILL rax); | |
| 10068 ins_cost(125); | |
| 10069 format %{ "COMISD $dst,$src\n" | |
| 10070 "\tJNP exit\n" | |
| 10071 "\tMOV ah,1 // saw a NaN, set CF\n" | |
| 10072 "\tSAHF\n" | |
| 10073 "exit:\tNOP // avoid branch to branch" %} | |
| 10074 opcode(0x66, 0x0F, 0x2F); | |
| 10075 ins_encode(OpcP, OpcS, Opcode(tertiary), RegReg(dst, src), cmpF_P6_fixup); | |
| 10076 ins_pipe( pipe_slow ); | |
| 10077 %} | |
| 10078 | |
|
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10079 instruct cmpXD_ccCF(eFlagsRegUCF cr, regXD dst, regXD src) %{ |
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10080 predicate(UseSSE>=2); |
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10081 match(Set cr (CmpD dst src)); |
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10082 ins_cost(100); |
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10083 format %{ "COMISD $dst,$src" %} |
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10084 opcode(0x66, 0x0F, 0x2F); |
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10085 ins_encode(OpcP, OpcS, Opcode(tertiary), RegReg(dst, src)); |
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10086 ins_pipe( pipe_slow ); |
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10087 %} |
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10088 |
| 0 | 10089 // float compare and set condition codes in EFLAGS by XMM regs |
| 10090 instruct cmpXD_ccmem(eFlagsRegU cr, regXD dst, memory src, eAXRegI rax) %{ | |
| 10091 predicate(UseSSE>=2); | |
| 10092 match(Set cr (CmpD dst (LoadD src))); | |
| 10093 effect(KILL rax); | |
| 10094 ins_cost(145); | |
| 10095 format %{ "COMISD $dst,$src\n" | |
| 10096 "\tJNP exit\n" | |
| 10097 "\tMOV ah,1 // saw a NaN, set CF\n" | |
| 10098 "\tSAHF\n" | |
| 10099 "exit:\tNOP // avoid branch to branch" %} | |
| 10100 opcode(0x66, 0x0F, 0x2F); | |
| 10101 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(dst, src), cmpF_P6_fixup); | |
| 10102 ins_pipe( pipe_slow ); | |
| 10103 %} | |
| 10104 | |
|
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10105 instruct cmpXD_ccmemCF(eFlagsRegUCF cr, regXD dst, memory src) %{ |
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10106 predicate(UseSSE>=2); |
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10107 match(Set cr (CmpD dst (LoadD src))); |
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10108 ins_cost(100); |
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10109 format %{ "COMISD $dst,$src" %} |
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10110 opcode(0x66, 0x0F, 0x2F); |
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10111 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(dst, src)); |
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10112 ins_pipe( pipe_slow ); |
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10113 %} |
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10114 |
| 0 | 10115 // Compare into -1,0,1 in XMM |
| 10116 instruct cmpXD_reg(eRegI dst, regXD src1, regXD src2, eFlagsReg cr) %{ | |
| 10117 predicate(UseSSE>=2); | |
| 10118 match(Set dst (CmpD3 src1 src2)); | |
| 10119 effect(KILL cr); | |
| 10120 ins_cost(255); | |
| 10121 format %{ "XOR $dst,$dst\n" | |
| 10122 "\tCOMISD $src1,$src2\n" | |
| 10123 "\tJP,s nan\n" | |
| 10124 "\tJEQ,s exit\n" | |
| 10125 "\tJA,s inc\n" | |
| 10126 "nan:\tDEC $dst\n" | |
| 10127 "\tJMP,s exit\n" | |
| 10128 "inc:\tINC $dst\n" | |
| 10129 "exit:" | |
| 10130 %} | |
| 10131 opcode(0x66, 0x0F, 0x2F); | |
| 10132 ins_encode(Xor_Reg(dst), OpcP, OpcS, Opcode(tertiary), RegReg(src1, src2), | |
| 10133 CmpX_Result(dst)); | |
| 10134 ins_pipe( pipe_slow ); | |
| 10135 %} | |
| 10136 | |
| 10137 // Compare into -1,0,1 in XMM and memory | |
| 10138 instruct cmpXD_regmem(eRegI dst, regXD src1, memory mem, eFlagsReg cr) %{ | |
| 10139 predicate(UseSSE>=2); | |
| 10140 match(Set dst (CmpD3 src1 (LoadD mem))); | |
| 10141 effect(KILL cr); | |
| 10142 ins_cost(275); | |
| 10143 format %{ "COMISD $src1,$mem\n" | |
| 10144 "\tMOV $dst,0\t\t# do not blow flags\n" | |
| 10145 "\tJP,s nan\n" | |
| 10146 "\tJEQ,s exit\n" | |
| 10147 "\tJA,s inc\n" | |
| 10148 "nan:\tDEC $dst\n" | |
| 10149 "\tJMP,s exit\n" | |
| 10150 "inc:\tINC $dst\n" | |
| 10151 "exit:" | |
| 10152 %} | |
| 10153 opcode(0x66, 0x0F, 0x2F); | |
| 10154 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(src1, mem), | |
| 10155 LdImmI(dst,0x0), CmpX_Result(dst)); | |
| 10156 ins_pipe( pipe_slow ); | |
| 10157 %} | |
| 10158 | |
| 10159 | |
| 10160 instruct subD_reg(regD dst, regD src) %{ | |
| 10161 predicate (UseSSE <=1); | |
| 10162 match(Set dst (SubD dst src)); | |
| 10163 | |
| 10164 format %{ "FLD $src\n\t" | |
| 10165 "DSUBp $dst,ST" %} | |
| 10166 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */ | |
| 10167 ins_cost(150); | |
| 10168 ins_encode( Push_Reg_D(src), | |
| 10169 OpcP, RegOpc(dst) ); | |
| 10170 ins_pipe( fpu_reg_reg ); | |
| 10171 %} | |
| 10172 | |
| 10173 instruct subD_reg_round(stackSlotD dst, regD src1, regD src2) %{ | |
| 10174 predicate (UseSSE <=1); | |
| 10175 match(Set dst (RoundDouble (SubD src1 src2))); | |
| 10176 ins_cost(250); | |
| 10177 | |
| 10178 format %{ "FLD $src2\n\t" | |
| 10179 "DSUB ST,$src1\n\t" | |
| 10180 "FSTP_D $dst\t# D-round" %} | |
| 10181 opcode(0xD8, 0x5); | |
| 10182 ins_encode( Push_Reg_D(src2), | |
| 10183 OpcP, RegOpc(src1), Pop_Mem_D(dst) ); | |
| 10184 ins_pipe( fpu_mem_reg_reg ); | |
| 10185 %} | |
| 10186 | |
| 10187 | |
| 10188 instruct subD_reg_mem(regD dst, memory src) %{ | |
| 10189 predicate (UseSSE <=1); | |
| 10190 match(Set dst (SubD dst (LoadD src))); | |
| 10191 ins_cost(150); | |
| 10192 | |
| 10193 format %{ "FLD $src\n\t" | |
| 10194 "DSUBp $dst,ST" %} | |
| 10195 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */ | |
| 10196 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 10197 OpcP, RegOpc(dst) ); | |
| 10198 ins_pipe( fpu_reg_mem ); | |
| 10199 %} | |
| 10200 | |
| 10201 instruct absD_reg(regDPR1 dst, regDPR1 src) %{ | |
| 10202 predicate (UseSSE<=1); | |
| 10203 match(Set dst (AbsD src)); | |
| 10204 ins_cost(100); | |
| 10205 format %{ "FABS" %} | |
| 10206 opcode(0xE1, 0xD9); | |
| 10207 ins_encode( OpcS, OpcP ); | |
| 10208 ins_pipe( fpu_reg_reg ); | |
| 10209 %} | |
| 10210 | |
| 10211 instruct absXD_reg( regXD dst ) %{ | |
| 10212 predicate(UseSSE>=2); | |
| 10213 match(Set dst (AbsD dst)); | |
| 10214 format %{ "ANDPD $dst,[0x7FFFFFFFFFFFFFFF]\t# ABS D by sign masking" %} | |
| 10215 ins_encode( AbsXD_encoding(dst)); | |
| 10216 ins_pipe( pipe_slow ); | |
| 10217 %} | |
| 10218 | |
| 10219 instruct negD_reg(regDPR1 dst, regDPR1 src) %{ | |
| 10220 predicate(UseSSE<=1); | |
| 10221 match(Set dst (NegD src)); | |
| 10222 ins_cost(100); | |
| 10223 format %{ "FCHS" %} | |
| 10224 opcode(0xE0, 0xD9); | |
| 10225 ins_encode( OpcS, OpcP ); | |
| 10226 ins_pipe( fpu_reg_reg ); | |
| 10227 %} | |
| 10228 | |
| 10229 instruct negXD_reg( regXD dst ) %{ | |
| 10230 predicate(UseSSE>=2); | |
| 10231 match(Set dst (NegD dst)); | |
| 10232 format %{ "XORPD $dst,[0x8000000000000000]\t# CHS D by sign flipping" %} | |
| 10233 ins_encode %{ | |
| 10234 __ xorpd($dst$$XMMRegister, | |
| 10235 ExternalAddress((address)double_signflip_pool)); | |
| 10236 %} | |
| 10237 ins_pipe( pipe_slow ); | |
| 10238 %} | |
| 10239 | |
| 10240 instruct addD_reg(regD dst, regD src) %{ | |
| 10241 predicate(UseSSE<=1); | |
| 10242 match(Set dst (AddD dst src)); | |
| 10243 format %{ "FLD $src\n\t" | |
| 10244 "DADD $dst,ST" %} | |
| 10245 size(4); | |
| 10246 ins_cost(150); | |
| 10247 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/ | |
| 10248 ins_encode( Push_Reg_D(src), | |
| 10249 OpcP, RegOpc(dst) ); | |
| 10250 ins_pipe( fpu_reg_reg ); | |
| 10251 %} | |
| 10252 | |
| 10253 | |
| 10254 instruct addD_reg_round(stackSlotD dst, regD src1, regD src2) %{ | |
| 10255 predicate(UseSSE<=1); | |
| 10256 match(Set dst (RoundDouble (AddD src1 src2))); | |
| 10257 ins_cost(250); | |
| 10258 | |
| 10259 format %{ "FLD $src2\n\t" | |
| 10260 "DADD ST,$src1\n\t" | |
| 10261 "FSTP_D $dst\t# D-round" %} | |
| 10262 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/ | |
| 10263 ins_encode( Push_Reg_D(src2), | |
| 10264 OpcP, RegOpc(src1), Pop_Mem_D(dst) ); | |
| 10265 ins_pipe( fpu_mem_reg_reg ); | |
| 10266 %} | |
| 10267 | |
| 10268 | |
| 10269 instruct addD_reg_mem(regD dst, memory src) %{ | |
| 10270 predicate(UseSSE<=1); | |
| 10271 match(Set dst (AddD dst (LoadD src))); | |
| 10272 ins_cost(150); | |
| 10273 | |
| 10274 format %{ "FLD $src\n\t" | |
| 10275 "DADDp $dst,ST" %} | |
| 10276 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */ | |
| 10277 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 10278 OpcP, RegOpc(dst) ); | |
| 10279 ins_pipe( fpu_reg_mem ); | |
| 10280 %} | |
| 10281 | |
| 10282 // add-to-memory | |
| 10283 instruct addD_mem_reg(memory dst, regD src) %{ | |
| 10284 predicate(UseSSE<=1); | |
| 10285 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src)))); | |
| 10286 ins_cost(150); | |
| 10287 | |
| 10288 format %{ "FLD_D $dst\n\t" | |
| 10289 "DADD ST,$src\n\t" | |
| 10290 "FST_D $dst" %} | |
| 10291 opcode(0xDD, 0x0); | |
| 10292 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst), | |
| 10293 Opcode(0xD8), RegOpc(src), | |
| 10294 set_instruction_start, | |
| 10295 Opcode(0xDD), RMopc_Mem(0x03,dst) ); | |
| 10296 ins_pipe( fpu_reg_mem ); | |
| 10297 %} | |
| 10298 | |
| 2008 | 10299 instruct addD_reg_imm1(regD dst, immD1 con) %{ |
| 0 | 10300 predicate(UseSSE<=1); |
| 2008 | 10301 match(Set dst (AddD dst con)); |
| 0 | 10302 ins_cost(125); |
| 10303 format %{ "FLD1\n\t" | |
| 10304 "DADDp $dst,ST" %} | |
| 2008 | 10305 ins_encode %{ |
| 10306 __ fld1(); | |
| 10307 __ faddp($dst$$reg); | |
| 10308 %} | |
| 10309 ins_pipe(fpu_reg); | |
| 10310 %} | |
| 10311 | |
| 10312 instruct addD_reg_imm(regD dst, immD con) %{ | |
| 0 | 10313 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 ); |
| 2008 | 10314 match(Set dst (AddD dst con)); |
| 0 | 10315 ins_cost(200); |
| 2008 | 10316 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 10317 "DADDp $dst,ST" %} |
| 2008 | 10318 ins_encode %{ |
| 10319 __ fld_d($constantaddress($con)); | |
| 10320 __ faddp($dst$$reg); | |
| 10321 %} | |
| 10322 ins_pipe(fpu_reg_mem); | |
| 0 | 10323 %} |
| 10324 | |
| 10325 instruct addD_reg_imm_round(stackSlotD dst, regD src, immD con) %{ | |
| 10326 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 ); | |
| 10327 match(Set dst (RoundDouble (AddD src con))); | |
| 10328 ins_cost(200); | |
| 2008 | 10329 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 10330 "DADD ST,$src\n\t" |
| 10331 "FSTP_D $dst\t# D-round" %} | |
| 2008 | 10332 ins_encode %{ |
| 10333 __ fld_d($constantaddress($con)); | |
| 10334 __ fadd($src$$reg); | |
| 10335 __ fstp_d(Address(rsp, $dst$$disp)); | |
| 10336 %} | |
| 10337 ins_pipe(fpu_mem_reg_con); | |
| 0 | 10338 %} |
| 10339 | |
| 10340 // Add two double precision floating point values in xmm | |
| 10341 instruct addXD_reg(regXD dst, regXD src) %{ | |
| 10342 predicate(UseSSE>=2); | |
| 10343 match(Set dst (AddD dst src)); | |
| 10344 format %{ "ADDSD $dst,$src" %} | |
| 10345 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegReg(dst, src)); | |
| 10346 ins_pipe( pipe_slow ); | |
| 10347 %} | |
| 10348 | |
| 10349 instruct addXD_imm(regXD dst, immXD con) %{ | |
| 10350 predicate(UseSSE>=2); | |
| 10351 match(Set dst (AddD dst con)); | |
| 2008 | 10352 format %{ "ADDSD $dst,[$constantaddress]\t# load from constant table: double=$con" %} |
| 10353 ins_encode %{ | |
| 10354 __ addsd($dst$$XMMRegister, $constantaddress($con)); | |
| 10355 %} | |
| 10356 ins_pipe(pipe_slow); | |
| 0 | 10357 %} |
| 10358 | |
| 10359 instruct addXD_mem(regXD dst, memory mem) %{ | |
| 10360 predicate(UseSSE>=2); | |
| 10361 match(Set dst (AddD dst (LoadD mem))); | |
| 10362 format %{ "ADDSD $dst,$mem" %} | |
| 10363 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegMem(dst,mem)); | |
| 10364 ins_pipe( pipe_slow ); | |
| 10365 %} | |
| 10366 | |
| 10367 // Sub two double precision floating point values in xmm | |
| 10368 instruct subXD_reg(regXD dst, regXD src) %{ | |
| 10369 predicate(UseSSE>=2); | |
| 10370 match(Set dst (SubD dst src)); | |
| 10371 format %{ "SUBSD $dst,$src" %} | |
| 10372 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src)); | |
| 10373 ins_pipe( pipe_slow ); | |
| 10374 %} | |
| 10375 | |
| 10376 instruct subXD_imm(regXD dst, immXD con) %{ | |
| 10377 predicate(UseSSE>=2); | |
| 10378 match(Set dst (SubD dst con)); | |
| 2008 | 10379 format %{ "SUBSD $dst,[$constantaddress]\t# load from constant table: double=$con" %} |
| 10380 ins_encode %{ | |
| 10381 __ subsd($dst$$XMMRegister, $constantaddress($con)); | |
| 10382 %} | |
| 10383 ins_pipe(pipe_slow); | |
| 0 | 10384 %} |
| 10385 | |
| 10386 instruct subXD_mem(regXD dst, memory mem) %{ | |
| 10387 predicate(UseSSE>=2); | |
| 10388 match(Set dst (SubD dst (LoadD mem))); | |
| 10389 format %{ "SUBSD $dst,$mem" %} | |
| 10390 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem)); | |
| 10391 ins_pipe( pipe_slow ); | |
| 10392 %} | |
| 10393 | |
| 10394 // Mul two double precision floating point values in xmm | |
| 10395 instruct mulXD_reg(regXD dst, regXD src) %{ | |
| 10396 predicate(UseSSE>=2); | |
| 10397 match(Set dst (MulD dst src)); | |
| 10398 format %{ "MULSD $dst,$src" %} | |
| 10399 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegReg(dst, src)); | |
| 10400 ins_pipe( pipe_slow ); | |
| 10401 %} | |
| 10402 | |
| 10403 instruct mulXD_imm(regXD dst, immXD con) %{ | |
| 10404 predicate(UseSSE>=2); | |
| 10405 match(Set dst (MulD dst con)); | |
| 2008 | 10406 format %{ "MULSD $dst,[$constantaddress]\t# load from constant table: double=$con" %} |
| 10407 ins_encode %{ | |
| 10408 __ mulsd($dst$$XMMRegister, $constantaddress($con)); | |
| 10409 %} | |
| 10410 ins_pipe(pipe_slow); | |
| 0 | 10411 %} |
| 10412 | |
| 10413 instruct mulXD_mem(regXD dst, memory mem) %{ | |
| 10414 predicate(UseSSE>=2); | |
| 10415 match(Set dst (MulD dst (LoadD mem))); | |
| 10416 format %{ "MULSD $dst,$mem" %} | |
| 10417 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem)); | |
| 10418 ins_pipe( pipe_slow ); | |
| 10419 %} | |
| 10420 | |
| 10421 // Div two double precision floating point values in xmm | |
| 10422 instruct divXD_reg(regXD dst, regXD src) %{ | |
| 10423 predicate(UseSSE>=2); | |
| 10424 match(Set dst (DivD dst src)); | |
| 10425 format %{ "DIVSD $dst,$src" %} | |
| 10426 opcode(0xF2, 0x0F, 0x5E); | |
| 10427 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src)); | |
| 10428 ins_pipe( pipe_slow ); | |
| 10429 %} | |
| 10430 | |
| 10431 instruct divXD_imm(regXD dst, immXD con) %{ | |
| 10432 predicate(UseSSE>=2); | |
| 10433 match(Set dst (DivD dst con)); | |
| 2008 | 10434 format %{ "DIVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %} |
| 10435 ins_encode %{ | |
| 10436 __ divsd($dst$$XMMRegister, $constantaddress($con)); | |
| 10437 %} | |
| 10438 ins_pipe(pipe_slow); | |
| 0 | 10439 %} |
| 10440 | |
| 10441 instruct divXD_mem(regXD dst, memory mem) %{ | |
| 10442 predicate(UseSSE>=2); | |
| 10443 match(Set dst (DivD dst (LoadD mem))); | |
| 10444 format %{ "DIVSD $dst,$mem" %} | |
| 10445 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem)); | |
| 10446 ins_pipe( pipe_slow ); | |
| 10447 %} | |
| 10448 | |
| 10449 | |
| 10450 instruct mulD_reg(regD dst, regD src) %{ | |
| 10451 predicate(UseSSE<=1); | |
| 10452 match(Set dst (MulD dst src)); | |
| 10453 format %{ "FLD $src\n\t" | |
| 10454 "DMULp $dst,ST" %} | |
| 10455 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/ | |
| 10456 ins_cost(150); | |
| 10457 ins_encode( Push_Reg_D(src), | |
| 10458 OpcP, RegOpc(dst) ); | |
| 10459 ins_pipe( fpu_reg_reg ); | |
| 10460 %} | |
| 10461 | |
| 10462 // Strict FP instruction biases argument before multiply then | |
| 10463 // biases result to avoid double rounding of subnormals. | |
| 10464 // | |
| 10465 // scale arg1 by multiplying arg1 by 2^(-15360) | |
| 10466 // load arg2 | |
| 10467 // multiply scaled arg1 by arg2 | |
| 10468 // rescale product by 2^(15360) | |
| 10469 // | |
| 10470 instruct strictfp_mulD_reg(regDPR1 dst, regnotDPR1 src) %{ | |
| 10471 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() ); | |
| 10472 match(Set dst (MulD dst src)); | |
| 10473 ins_cost(1); // Select this instruction for all strict FP double multiplies | |
| 10474 | |
| 10475 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t" | |
| 10476 "DMULp $dst,ST\n\t" | |
| 10477 "FLD $src\n\t" | |
| 10478 "DMULp $dst,ST\n\t" | |
| 10479 "FLD StubRoutines::_fpu_subnormal_bias2\n\t" | |
| 10480 "DMULp $dst,ST\n\t" %} | |
| 10481 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/ | |
| 10482 ins_encode( strictfp_bias1(dst), | |
| 10483 Push_Reg_D(src), | |
| 10484 OpcP, RegOpc(dst), | |
| 10485 strictfp_bias2(dst) ); | |
| 10486 ins_pipe( fpu_reg_reg ); | |
| 10487 %} | |
| 10488 | |
| 2008 | 10489 instruct mulD_reg_imm(regD dst, immD con) %{ |
| 0 | 10490 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 ); |
| 2008 | 10491 match(Set dst (MulD dst con)); |
| 0 | 10492 ins_cost(200); |
| 2008 | 10493 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 10494 "DMULp $dst,ST" %} |
| 2008 | 10495 ins_encode %{ |
| 10496 __ fld_d($constantaddress($con)); | |
| 10497 __ fmulp($dst$$reg); | |
| 10498 %} | |
| 10499 ins_pipe(fpu_reg_mem); | |
| 0 | 10500 %} |
| 10501 | |
| 10502 | |
| 10503 instruct mulD_reg_mem(regD dst, memory src) %{ | |
| 10504 predicate( UseSSE<=1 ); | |
| 10505 match(Set dst (MulD dst (LoadD src))); | |
| 10506 ins_cost(200); | |
| 10507 format %{ "FLD_D $src\n\t" | |
| 10508 "DMULp $dst,ST" %} | |
| 10509 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */ | |
| 10510 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 10511 OpcP, RegOpc(dst) ); | |
| 10512 ins_pipe( fpu_reg_mem ); | |
| 10513 %} | |
| 10514 | |
| 10515 // | |
| 10516 // Cisc-alternate to reg-reg multiply | |
| 10517 instruct mulD_reg_mem_cisc(regD dst, regD src, memory mem) %{ | |
| 10518 predicate( UseSSE<=1 ); | |
| 10519 match(Set dst (MulD src (LoadD mem))); | |
| 10520 ins_cost(250); | |
| 10521 format %{ "FLD_D $mem\n\t" | |
| 10522 "DMUL ST,$src\n\t" | |
| 10523 "FSTP_D $dst" %} | |
| 10524 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */ | |
| 10525 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem), | |
| 10526 OpcReg_F(src), | |
| 10527 Pop_Reg_D(dst) ); | |
| 10528 ins_pipe( fpu_reg_reg_mem ); | |
| 10529 %} | |
| 10530 | |
| 10531 | |
| 10532 // MACRO3 -- addD a mulD | |
| 10533 // This instruction is a '2-address' instruction in that the result goes | |
| 10534 // back to src2. This eliminates a move from the macro; possibly the | |
| 10535 // register allocator will have to add it back (and maybe not). | |
| 10536 instruct addD_mulD_reg(regD src2, regD src1, regD src0) %{ | |
| 10537 predicate( UseSSE<=1 ); | |
| 10538 match(Set src2 (AddD (MulD src0 src1) src2)); | |
| 10539 format %{ "FLD $src0\t# ===MACRO3d===\n\t" | |
| 10540 "DMUL ST,$src1\n\t" | |
| 10541 "DADDp $src2,ST" %} | |
| 10542 ins_cost(250); | |
| 10543 opcode(0xDD); /* LoadD DD /0 */ | |
| 10544 ins_encode( Push_Reg_F(src0), | |
| 10545 FMul_ST_reg(src1), | |
| 10546 FAddP_reg_ST(src2) ); | |
| 10547 ins_pipe( fpu_reg_reg_reg ); | |
| 10548 %} | |
| 10549 | |
| 10550 | |
| 10551 // MACRO3 -- subD a mulD | |
| 10552 instruct subD_mulD_reg(regD src2, regD src1, regD src0) %{ | |
| 10553 predicate( UseSSE<=1 ); | |
| 10554 match(Set src2 (SubD (MulD src0 src1) src2)); | |
| 10555 format %{ "FLD $src0\t# ===MACRO3d===\n\t" | |
| 10556 "DMUL ST,$src1\n\t" | |
| 10557 "DSUBRp $src2,ST" %} | |
| 10558 ins_cost(250); | |
| 10559 ins_encode( Push_Reg_F(src0), | |
| 10560 FMul_ST_reg(src1), | |
| 10561 Opcode(0xDE), Opc_plus(0xE0,src2)); | |
| 10562 ins_pipe( fpu_reg_reg_reg ); | |
| 10563 %} | |
| 10564 | |
| 10565 | |
| 10566 instruct divD_reg(regD dst, regD src) %{ | |
| 10567 predicate( UseSSE<=1 ); | |
| 10568 match(Set dst (DivD dst src)); | |
| 10569 | |
| 10570 format %{ "FLD $src\n\t" | |
| 10571 "FDIVp $dst,ST" %} | |
| 10572 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
| 10573 ins_cost(150); | |
| 10574 ins_encode( Push_Reg_D(src), | |
| 10575 OpcP, RegOpc(dst) ); | |
| 10576 ins_pipe( fpu_reg_reg ); | |
| 10577 %} | |
| 10578 | |
| 10579 // Strict FP instruction biases argument before division then | |
| 10580 // biases result, to avoid double rounding of subnormals. | |
| 10581 // | |
| 10582 // scale dividend by multiplying dividend by 2^(-15360) | |
| 10583 // load divisor | |
| 10584 // divide scaled dividend by divisor | |
| 10585 // rescale quotient by 2^(15360) | |
| 10586 // | |
| 10587 instruct strictfp_divD_reg(regDPR1 dst, regnotDPR1 src) %{ | |
| 10588 predicate (UseSSE<=1); | |
| 10589 match(Set dst (DivD dst src)); | |
| 10590 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() ); | |
| 10591 ins_cost(01); | |
| 10592 | |
| 10593 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t" | |
| 10594 "DMULp $dst,ST\n\t" | |
| 10595 "FLD $src\n\t" | |
| 10596 "FDIVp $dst,ST\n\t" | |
| 10597 "FLD StubRoutines::_fpu_subnormal_bias2\n\t" | |
| 10598 "DMULp $dst,ST\n\t" %} | |
| 10599 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
| 10600 ins_encode( strictfp_bias1(dst), | |
| 10601 Push_Reg_D(src), | |
| 10602 OpcP, RegOpc(dst), | |
| 10603 strictfp_bias2(dst) ); | |
| 10604 ins_pipe( fpu_reg_reg ); | |
| 10605 %} | |
| 10606 | |
| 10607 instruct divD_reg_round(stackSlotD dst, regD src1, regD src2) %{ | |
| 10608 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) ); | |
| 10609 match(Set dst (RoundDouble (DivD src1 src2))); | |
| 10610 | |
| 10611 format %{ "FLD $src1\n\t" | |
| 10612 "FDIV ST,$src2\n\t" | |
| 10613 "FSTP_D $dst\t# D-round" %} | |
| 10614 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */ | |
| 10615 ins_encode( Push_Reg_D(src1), | |
| 10616 OpcP, RegOpc(src2), Pop_Mem_D(dst) ); | |
| 10617 ins_pipe( fpu_mem_reg_reg ); | |
| 10618 %} | |
| 10619 | |
| 10620 | |
| 10621 instruct modD_reg(regD dst, regD src, eAXRegI rax, eFlagsReg cr) %{ | |
| 10622 predicate(UseSSE<=1); | |
| 10623 match(Set dst (ModD dst src)); | |
| 10624 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS | |
| 10625 | |
| 10626 format %{ "DMOD $dst,$src" %} | |
| 10627 ins_cost(250); | |
| 10628 ins_encode(Push_Reg_Mod_D(dst, src), | |
| 10629 emitModD(), | |
| 10630 Push_Result_Mod_D(src), | |
| 10631 Pop_Reg_D(dst)); | |
| 10632 ins_pipe( pipe_slow ); | |
| 10633 %} | |
| 10634 | |
| 10635 instruct modXD_reg(regXD dst, regXD src0, regXD src1, eAXRegI rax, eFlagsReg cr) %{ | |
| 10636 predicate(UseSSE>=2); | |
| 10637 match(Set dst (ModD src0 src1)); | |
| 10638 effect(KILL rax, KILL cr); | |
| 10639 | |
| 10640 format %{ "SUB ESP,8\t # DMOD\n" | |
| 10641 "\tMOVSD [ESP+0],$src1\n" | |
| 10642 "\tFLD_D [ESP+0]\n" | |
| 10643 "\tMOVSD [ESP+0],$src0\n" | |
| 10644 "\tFLD_D [ESP+0]\n" | |
| 10645 "loop:\tFPREM\n" | |
| 10646 "\tFWAIT\n" | |
| 10647 "\tFNSTSW AX\n" | |
| 10648 "\tSAHF\n" | |
| 10649 "\tJP loop\n" | |
| 10650 "\tFSTP_D [ESP+0]\n" | |
| 10651 "\tMOVSD $dst,[ESP+0]\n" | |
| 10652 "\tADD ESP,8\n" | |
| 10653 "\tFSTP ST0\t # Restore FPU Stack" | |
| 10654 %} | |
| 10655 ins_cost(250); | |
| 10656 ins_encode( Push_ModD_encoding(src0, src1), emitModD(), Push_ResultXD(dst), PopFPU); | |
| 10657 ins_pipe( pipe_slow ); | |
| 10658 %} | |
| 10659 | |
| 10660 instruct sinD_reg(regDPR1 dst, regDPR1 src) %{ | |
| 10661 predicate (UseSSE<=1); | |
| 10662 match(Set dst (SinD src)); | |
| 10663 ins_cost(1800); | |
| 10664 format %{ "DSIN $dst" %} | |
| 10665 opcode(0xD9, 0xFE); | |
| 10666 ins_encode( OpcP, OpcS ); | |
| 10667 ins_pipe( pipe_slow ); | |
| 10668 %} | |
| 10669 | |
| 10670 instruct sinXD_reg(regXD dst, eFlagsReg cr) %{ | |
| 10671 predicate (UseSSE>=2); | |
| 10672 match(Set dst (SinD dst)); | |
| 10673 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8" | |
| 10674 ins_cost(1800); | |
| 10675 format %{ "DSIN $dst" %} | |
| 10676 opcode(0xD9, 0xFE); | |
| 10677 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) ); | |
| 10678 ins_pipe( pipe_slow ); | |
| 10679 %} | |
| 10680 | |
| 10681 instruct cosD_reg(regDPR1 dst, regDPR1 src) %{ | |
| 10682 predicate (UseSSE<=1); | |
| 10683 match(Set dst (CosD src)); | |
| 10684 ins_cost(1800); | |
| 10685 format %{ "DCOS $dst" %} | |
| 10686 opcode(0xD9, 0xFF); | |
| 10687 ins_encode( OpcP, OpcS ); | |
| 10688 ins_pipe( pipe_slow ); | |
| 10689 %} | |
| 10690 | |
| 10691 instruct cosXD_reg(regXD dst, eFlagsReg cr) %{ | |
| 10692 predicate (UseSSE>=2); | |
| 10693 match(Set dst (CosD dst)); | |
| 10694 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8" | |
| 10695 ins_cost(1800); | |
| 10696 format %{ "DCOS $dst" %} | |
| 10697 opcode(0xD9, 0xFF); | |
| 10698 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) ); | |
| 10699 ins_pipe( pipe_slow ); | |
| 10700 %} | |
| 10701 | |
| 10702 instruct tanD_reg(regDPR1 dst, regDPR1 src) %{ | |
| 10703 predicate (UseSSE<=1); | |
| 10704 match(Set dst(TanD src)); | |
| 10705 format %{ "DTAN $dst" %} | |
| 10706 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan | |
| 10707 Opcode(0xDD), Opcode(0xD8)); // fstp st | |
| 10708 ins_pipe( pipe_slow ); | |
| 10709 %} | |
| 10710 | |
| 10711 instruct tanXD_reg(regXD dst, eFlagsReg cr) %{ | |
| 10712 predicate (UseSSE>=2); | |
| 10713 match(Set dst(TanD dst)); | |
| 10714 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8" | |
| 10715 format %{ "DTAN $dst" %} | |
| 10716 ins_encode( Push_SrcXD(dst), | |
| 10717 Opcode(0xD9), Opcode(0xF2), // fptan | |
| 10718 Opcode(0xDD), Opcode(0xD8), // fstp st | |
| 10719 Push_ResultXD(dst) ); | |
| 10720 ins_pipe( pipe_slow ); | |
| 10721 %} | |
| 10722 | |
| 10723 instruct atanD_reg(regD dst, regD src) %{ | |
| 10724 predicate (UseSSE<=1); | |
| 10725 match(Set dst(AtanD dst src)); | |
| 10726 format %{ "DATA $dst,$src" %} | |
| 10727 opcode(0xD9, 0xF3); | |
| 10728 ins_encode( Push_Reg_D(src), | |
| 10729 OpcP, OpcS, RegOpc(dst) ); | |
| 10730 ins_pipe( pipe_slow ); | |
| 10731 %} | |
| 10732 | |
| 10733 instruct atanXD_reg(regXD dst, regXD src, eFlagsReg cr) %{ | |
| 10734 predicate (UseSSE>=2); | |
| 10735 match(Set dst(AtanD dst src)); | |
| 10736 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8" | |
| 10737 format %{ "DATA $dst,$src" %} | |
| 10738 opcode(0xD9, 0xF3); | |
| 10739 ins_encode( Push_SrcXD(src), | |
| 10740 OpcP, OpcS, Push_ResultXD(dst) ); | |
| 10741 ins_pipe( pipe_slow ); | |
| 10742 %} | |
| 10743 | |
| 10744 instruct sqrtD_reg(regD dst, regD src) %{ | |
| 10745 predicate (UseSSE<=1); | |
| 10746 match(Set dst (SqrtD src)); | |
| 10747 format %{ "DSQRT $dst,$src" %} | |
| 10748 opcode(0xFA, 0xD9); | |
| 10749 ins_encode( Push_Reg_D(src), | |
| 10750 OpcS, OpcP, Pop_Reg_D(dst) ); | |
| 10751 ins_pipe( pipe_slow ); | |
| 10752 %} | |
| 10753 | |
| 10754 instruct powD_reg(regD X, regDPR1 Y, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{ | |
| 10755 predicate (UseSSE<=1); | |
| 10756 match(Set Y (PowD X Y)); // Raise X to the Yth power | |
| 10757 effect(KILL rax, KILL rbx, KILL rcx); | |
| 10758 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t" | |
| 10759 "FLD_D $X\n\t" | |
| 10760 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t" | |
| 10761 | |
| 10762 "FDUP \t\t\t# Q Q\n\t" | |
| 10763 "FRNDINT\t\t\t# int(Q) Q\n\t" | |
| 10764 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t" | |
| 10765 "FISTP dword [ESP]\n\t" | |
| 10766 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t" | |
| 10767 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t" | |
| 10768 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead | |
| 10769 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t" | |
| 10770 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t" | |
| 10771 "ADD EAX,1023\t\t# Double exponent bias\n\t" | |
| 10772 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t" | |
| 10773 "SHL EAX,20\t\t# Shift exponent into place\n\t" | |
| 10774 "TEST EBX,ECX\t\t# Check for overflow\n\t" | |
| 10775 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t" | |
| 10776 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t" | |
| 10777 "MOV [ESP+0],0\n\t" | |
| 10778 "FMUL ST(0),[ESP+0]\t# Scale\n\t" | |
| 10779 | |
| 10780 "ADD ESP,8" | |
| 10781 %} | |
| 10782 ins_encode( push_stack_temp_qword, | |
| 10783 Push_Reg_D(X), | |
| 10784 Opcode(0xD9), Opcode(0xF1), // fyl2x | |
| 10785 pow_exp_core_encoding, | |
| 10786 pop_stack_temp_qword); | |
| 10787 ins_pipe( pipe_slow ); | |
| 10788 %} | |
| 10789 | |
| 10790 instruct powXD_reg(regXD dst, regXD src0, regXD src1, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx ) %{ | |
| 10791 predicate (UseSSE>=2); | |
| 10792 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power | |
| 10793 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx ); | |
| 10794 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t" | |
| 10795 "MOVSD [ESP],$src1\n\t" | |
| 10796 "FLD FPR1,$src1\n\t" | |
| 10797 "MOVSD [ESP],$src0\n\t" | |
| 10798 "FLD FPR1,$src0\n\t" | |
| 10799 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t" | |
| 10800 | |
| 10801 "FDUP \t\t\t# Q Q\n\t" | |
| 10802 "FRNDINT\t\t\t# int(Q) Q\n\t" | |
| 10803 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t" | |
| 10804 "FISTP dword [ESP]\n\t" | |
| 10805 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t" | |
| 10806 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t" | |
| 10807 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead | |
| 10808 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t" | |
| 10809 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t" | |
| 10810 "ADD EAX,1023\t\t# Double exponent bias\n\t" | |
| 10811 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t" | |
| 10812 "SHL EAX,20\t\t# Shift exponent into place\n\t" | |
| 10813 "TEST EBX,ECX\t\t# Check for overflow\n\t" | |
| 10814 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t" | |
| 10815 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t" | |
| 10816 "MOV [ESP+0],0\n\t" | |
| 10817 "FMUL ST(0),[ESP+0]\t# Scale\n\t" | |
| 10818 | |
| 10819 "FST_D [ESP]\n\t" | |
| 10820 "MOVSD $dst,[ESP]\n\t" | |
| 10821 "ADD ESP,8" | |
| 10822 %} | |
| 10823 ins_encode( push_stack_temp_qword, | |
| 10824 push_xmm_to_fpr1(src1), | |
| 10825 push_xmm_to_fpr1(src0), | |
| 10826 Opcode(0xD9), Opcode(0xF1), // fyl2x | |
| 10827 pow_exp_core_encoding, | |
| 10828 Push_ResultXD(dst) ); | |
| 10829 ins_pipe( pipe_slow ); | |
| 10830 %} | |
| 10831 | |
| 10832 | |
| 10833 instruct expD_reg(regDPR1 dpr1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{ | |
| 10834 predicate (UseSSE<=1); | |
| 10835 match(Set dpr1 (ExpD dpr1)); | |
| 10836 effect(KILL rax, KILL rbx, KILL rcx); | |
| 10837 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding" | |
| 10838 "FLDL2E \t\t\t# Ld log2(e) X\n\t" | |
| 10839 "FMULP \t\t\t# Q=X*log2(e)\n\t" | |
| 10840 | |
| 10841 "FDUP \t\t\t# Q Q\n\t" | |
| 10842 "FRNDINT\t\t\t# int(Q) Q\n\t" | |
| 10843 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t" | |
| 10844 "FISTP dword [ESP]\n\t" | |
| 10845 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t" | |
| 10846 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t" | |
| 10847 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead | |
| 10848 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t" | |
| 10849 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t" | |
| 10850 "ADD EAX,1023\t\t# Double exponent bias\n\t" | |
| 10851 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t" | |
| 10852 "SHL EAX,20\t\t# Shift exponent into place\n\t" | |
| 10853 "TEST EBX,ECX\t\t# Check for overflow\n\t" | |
| 10854 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t" | |
| 10855 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t" | |
| 10856 "MOV [ESP+0],0\n\t" | |
| 10857 "FMUL ST(0),[ESP+0]\t# Scale\n\t" | |
| 10858 | |
| 10859 "ADD ESP,8" | |
| 10860 %} | |
| 10861 ins_encode( push_stack_temp_qword, | |
| 10862 Opcode(0xD9), Opcode(0xEA), // fldl2e | |
| 10863 Opcode(0xDE), Opcode(0xC9), // fmulp | |
| 10864 pow_exp_core_encoding, | |
| 10865 pop_stack_temp_qword); | |
| 10866 ins_pipe( pipe_slow ); | |
| 10867 %} | |
| 10868 | |
| 10869 instruct expXD_reg(regXD dst, regXD src, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{ | |
| 10870 predicate (UseSSE>=2); | |
| 10871 match(Set dst (ExpD src)); | |
| 10872 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx); | |
| 10873 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding\n\t" | |
| 10874 "MOVSD [ESP],$src\n\t" | |
| 10875 "FLDL2E \t\t\t# Ld log2(e) X\n\t" | |
| 10876 "FMULP \t\t\t# Q=X*log2(e) X\n\t" | |
| 10877 | |
| 10878 "FDUP \t\t\t# Q Q\n\t" | |
| 10879 "FRNDINT\t\t\t# int(Q) Q\n\t" | |
| 10880 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t" | |
| 10881 "FISTP dword [ESP]\n\t" | |
| 10882 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t" | |
| 10883 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t" | |
| 10884 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead | |
| 10885 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t" | |
| 10886 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t" | |
| 10887 "ADD EAX,1023\t\t# Double exponent bias\n\t" | |
| 10888 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t" | |
| 10889 "SHL EAX,20\t\t# Shift exponent into place\n\t" | |
| 10890 "TEST EBX,ECX\t\t# Check for overflow\n\t" | |
| 10891 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t" | |
| 10892 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t" | |
| 10893 "MOV [ESP+0],0\n\t" | |
| 10894 "FMUL ST(0),[ESP+0]\t# Scale\n\t" | |
| 10895 | |
| 10896 "FST_D [ESP]\n\t" | |
| 10897 "MOVSD $dst,[ESP]\n\t" | |
| 10898 "ADD ESP,8" | |
| 10899 %} | |
| 10900 ins_encode( Push_SrcXD(src), | |
| 10901 Opcode(0xD9), Opcode(0xEA), // fldl2e | |
| 10902 Opcode(0xDE), Opcode(0xC9), // fmulp | |
| 10903 pow_exp_core_encoding, | |
| 10904 Push_ResultXD(dst) ); | |
| 10905 ins_pipe( pipe_slow ); | |
| 10906 %} | |
| 10907 | |
| 10908 | |
| 10909 | |
| 10910 instruct log10D_reg(regDPR1 dst, regDPR1 src) %{ | |
| 10911 predicate (UseSSE<=1); | |
| 10912 // The source Double operand on FPU stack | |
| 10913 match(Set dst (Log10D src)); | |
| 10914 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number | |
| 10915 // fxch ; swap ST(0) with ST(1) | |
| 10916 // fyl2x ; compute log_10(2) * log_2(x) | |
| 10917 format %{ "FLDLG2 \t\t\t#Log10\n\t" | |
| 10918 "FXCH \n\t" | |
| 10919 "FYL2X \t\t\t# Q=Log10*Log_2(x)" | |
| 10920 %} | |
| 10921 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2 | |
| 10922 Opcode(0xD9), Opcode(0xC9), // fxch | |
| 10923 Opcode(0xD9), Opcode(0xF1)); // fyl2x | |
| 10924 | |
| 10925 ins_pipe( pipe_slow ); | |
| 10926 %} | |
| 10927 | |
| 10928 instruct log10XD_reg(regXD dst, regXD src, eFlagsReg cr) %{ | |
| 10929 predicate (UseSSE>=2); | |
| 10930 effect(KILL cr); | |
| 10931 match(Set dst (Log10D src)); | |
| 10932 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number | |
| 10933 // fyl2x ; compute log_10(2) * log_2(x) | |
| 10934 format %{ "FLDLG2 \t\t\t#Log10\n\t" | |
| 10935 "FYL2X \t\t\t# Q=Log10*Log_2(x)" | |
| 10936 %} | |
| 10937 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2 | |
| 10938 Push_SrcXD(src), | |
| 10939 Opcode(0xD9), Opcode(0xF1), // fyl2x | |
| 10940 Push_ResultXD(dst)); | |
| 10941 | |
| 10942 ins_pipe( pipe_slow ); | |
| 10943 %} | |
| 10944 | |
| 10945 instruct logD_reg(regDPR1 dst, regDPR1 src) %{ | |
| 10946 predicate (UseSSE<=1); | |
| 10947 // The source Double operand on FPU stack | |
| 10948 match(Set dst (LogD src)); | |
| 10949 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number | |
| 10950 // fxch ; swap ST(0) with ST(1) | |
| 10951 // fyl2x ; compute log_e(2) * log_2(x) | |
| 10952 format %{ "FLDLN2 \t\t\t#Log_e\n\t" | |
| 10953 "FXCH \n\t" | |
| 10954 "FYL2X \t\t\t# Q=Log_e*Log_2(x)" | |
| 10955 %} | |
| 10956 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 | |
| 10957 Opcode(0xD9), Opcode(0xC9), // fxch | |
| 10958 Opcode(0xD9), Opcode(0xF1)); // fyl2x | |
| 10959 | |
| 10960 ins_pipe( pipe_slow ); | |
| 10961 %} | |
| 10962 | |
| 10963 instruct logXD_reg(regXD dst, regXD src, eFlagsReg cr) %{ | |
| 10964 predicate (UseSSE>=2); | |
| 10965 effect(KILL cr); | |
| 10966 // The source and result Double operands in XMM registers | |
| 10967 match(Set dst (LogD src)); | |
| 10968 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number | |
| 10969 // fyl2x ; compute log_e(2) * log_2(x) | |
| 10970 format %{ "FLDLN2 \t\t\t#Log_e\n\t" | |
| 10971 "FYL2X \t\t\t# Q=Log_e*Log_2(x)" | |
| 10972 %} | |
| 10973 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 | |
| 10974 Push_SrcXD(src), | |
| 10975 Opcode(0xD9), Opcode(0xF1), // fyl2x | |
| 10976 Push_ResultXD(dst)); | |
| 10977 ins_pipe( pipe_slow ); | |
| 10978 %} | |
| 10979 | |
| 10980 //-------------Float Instructions------------------------------- | |
| 10981 // Float Math | |
| 10982 | |
| 10983 // Code for float compare: | |
| 10984 // fcompp(); | |
| 10985 // fwait(); fnstsw_ax(); | |
| 10986 // sahf(); | |
| 10987 // movl(dst, unordered_result); | |
| 10988 // jcc(Assembler::parity, exit); | |
| 10989 // movl(dst, less_result); | |
| 10990 // jcc(Assembler::below, exit); | |
| 10991 // movl(dst, equal_result); | |
| 10992 // jcc(Assembler::equal, exit); | |
| 10993 // movl(dst, greater_result); | |
| 10994 // exit: | |
| 10995 | |
| 10996 // P6 version of float compare, sets condition codes in EFLAGS | |
| 10997 instruct cmpF_cc_P6(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{ | |
| 10998 predicate(VM_Version::supports_cmov() && UseSSE == 0); | |
| 10999 match(Set cr (CmpF src1 src2)); | |
| 11000 effect(KILL rax); | |
| 11001 ins_cost(150); | |
| 11002 format %{ "FLD $src1\n\t" | |
| 11003 "FUCOMIP ST,$src2 // P6 instruction\n\t" | |
| 11004 "JNP exit\n\t" | |
| 11005 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t" | |
| 11006 "SAHF\n" | |
| 11007 "exit:\tNOP // avoid branch to branch" %} | |
| 11008 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ | |
| 11009 ins_encode( Push_Reg_D(src1), | |
| 11010 OpcP, RegOpc(src2), | |
| 11011 cmpF_P6_fixup ); | |
| 11012 ins_pipe( pipe_slow ); | |
| 11013 %} | |
| 11014 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11015 instruct cmpF_cc_P6CF(eFlagsRegUCF cr, regF src1, regF src2) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11016 predicate(VM_Version::supports_cmov() && UseSSE == 0); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11017 match(Set cr (CmpF src1 src2)); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11018 ins_cost(100); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
11019 format %{ "FLD $src1\n\t" |
|
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11020 "FUCOMIP ST,$src2 // P6 instruction" %} |
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11021 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ |
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11022 ins_encode( Push_Reg_D(src1), |
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11023 OpcP, RegOpc(src2)); |
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11024 ins_pipe( pipe_slow ); |
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11025 %} |
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11026 |
| 0 | 11027 |
| 11028 // Compare & branch | |
| 11029 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{ | |
| 11030 predicate(UseSSE == 0); | |
| 11031 match(Set cr (CmpF src1 src2)); | |
| 11032 effect(KILL rax); | |
| 11033 ins_cost(200); | |
| 11034 format %{ "FLD $src1\n\t" | |
| 11035 "FCOMp $src2\n\t" | |
| 11036 "FNSTSW AX\n\t" | |
| 11037 "TEST AX,0x400\n\t" | |
| 11038 "JZ,s flags\n\t" | |
| 11039 "MOV AH,1\t# unordered treat as LT\n" | |
| 11040 "flags:\tSAHF" %} | |
| 11041 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
| 11042 ins_encode( Push_Reg_D(src1), | |
| 11043 OpcP, RegOpc(src2), | |
| 11044 fpu_flags); | |
| 11045 ins_pipe( pipe_slow ); | |
| 11046 %} | |
| 11047 | |
| 11048 // Compare vs zero into -1,0,1 | |
| 11049 instruct cmpF_0(eRegI dst, regF src1, immF0 zero, eAXRegI rax, eFlagsReg cr) %{ | |
| 11050 predicate(UseSSE == 0); | |
| 11051 match(Set dst (CmpF3 src1 zero)); | |
| 11052 effect(KILL cr, KILL rax); | |
| 11053 ins_cost(280); | |
| 11054 format %{ "FTSTF $dst,$src1" %} | |
| 11055 opcode(0xE4, 0xD9); | |
| 11056 ins_encode( Push_Reg_D(src1), | |
| 11057 OpcS, OpcP, PopFPU, | |
| 11058 CmpF_Result(dst)); | |
| 11059 ins_pipe( pipe_slow ); | |
| 11060 %} | |
| 11061 | |
| 11062 // Compare into -1,0,1 | |
| 11063 instruct cmpF_reg(eRegI dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{ | |
| 11064 predicate(UseSSE == 0); | |
| 11065 match(Set dst (CmpF3 src1 src2)); | |
| 11066 effect(KILL cr, KILL rax); | |
| 11067 ins_cost(300); | |
| 11068 format %{ "FCMPF $dst,$src1,$src2" %} | |
| 11069 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
| 11070 ins_encode( Push_Reg_D(src1), | |
| 11071 OpcP, RegOpc(src2), | |
| 11072 CmpF_Result(dst)); | |
| 11073 ins_pipe( pipe_slow ); | |
| 11074 %} | |
| 11075 | |
| 11076 // float compare and set condition codes in EFLAGS by XMM regs | |
| 11077 instruct cmpX_cc(eFlagsRegU cr, regX dst, regX src, eAXRegI rax) %{ | |
| 11078 predicate(UseSSE>=1); | |
| 11079 match(Set cr (CmpF dst src)); | |
| 11080 effect(KILL rax); | |
| 11081 ins_cost(145); | |
| 11082 format %{ "COMISS $dst,$src\n" | |
| 11083 "\tJNP exit\n" | |
| 11084 "\tMOV ah,1 // saw a NaN, set CF\n" | |
| 11085 "\tSAHF\n" | |
| 11086 "exit:\tNOP // avoid branch to branch" %} | |
| 11087 opcode(0x0F, 0x2F); | |
| 11088 ins_encode(OpcP, OpcS, RegReg(dst, src), cmpF_P6_fixup); | |
| 11089 ins_pipe( pipe_slow ); | |
| 11090 %} | |
| 11091 | |
|
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11092 instruct cmpX_ccCF(eFlagsRegUCF cr, regX dst, regX src) %{ |
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11093 predicate(UseSSE>=1); |
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11094 match(Set cr (CmpF dst src)); |
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11095 ins_cost(100); |
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11096 format %{ "COMISS $dst,$src" %} |
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11097 opcode(0x0F, 0x2F); |
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11098 ins_encode(OpcP, OpcS, RegReg(dst, src)); |
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11099 ins_pipe( pipe_slow ); |
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11100 %} |
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11101 |
| 0 | 11102 // float compare and set condition codes in EFLAGS by XMM regs |
| 11103 instruct cmpX_ccmem(eFlagsRegU cr, regX dst, memory src, eAXRegI rax) %{ | |
| 11104 predicate(UseSSE>=1); | |
| 11105 match(Set cr (CmpF dst (LoadF src))); | |
| 11106 effect(KILL rax); | |
| 11107 ins_cost(165); | |
| 11108 format %{ "COMISS $dst,$src\n" | |
| 11109 "\tJNP exit\n" | |
| 11110 "\tMOV ah,1 // saw a NaN, set CF\n" | |
| 11111 "\tSAHF\n" | |
| 11112 "exit:\tNOP // avoid branch to branch" %} | |
| 11113 opcode(0x0F, 0x2F); | |
| 11114 ins_encode(OpcP, OpcS, RegMem(dst, src), cmpF_P6_fixup); | |
| 11115 ins_pipe( pipe_slow ); | |
| 11116 %} | |
| 11117 | |
|
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11118 instruct cmpX_ccmemCF(eFlagsRegUCF cr, regX dst, memory src) %{ |
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11119 predicate(UseSSE>=1); |
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11120 match(Set cr (CmpF dst (LoadF src))); |
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11121 ins_cost(100); |
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11122 format %{ "COMISS $dst,$src" %} |
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11123 opcode(0x0F, 0x2F); |
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11124 ins_encode(OpcP, OpcS, RegMem(dst, src)); |
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11125 ins_pipe( pipe_slow ); |
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11126 %} |
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11127 |
| 0 | 11128 // Compare into -1,0,1 in XMM |
| 11129 instruct cmpX_reg(eRegI dst, regX src1, regX src2, eFlagsReg cr) %{ | |
| 11130 predicate(UseSSE>=1); | |
| 11131 match(Set dst (CmpF3 src1 src2)); | |
| 11132 effect(KILL cr); | |
| 11133 ins_cost(255); | |
| 11134 format %{ "XOR $dst,$dst\n" | |
| 11135 "\tCOMISS $src1,$src2\n" | |
| 11136 "\tJP,s nan\n" | |
| 11137 "\tJEQ,s exit\n" | |
| 11138 "\tJA,s inc\n" | |
| 11139 "nan:\tDEC $dst\n" | |
| 11140 "\tJMP,s exit\n" | |
| 11141 "inc:\tINC $dst\n" | |
| 11142 "exit:" | |
| 11143 %} | |
| 11144 opcode(0x0F, 0x2F); | |
| 11145 ins_encode(Xor_Reg(dst), OpcP, OpcS, RegReg(src1, src2), CmpX_Result(dst)); | |
| 11146 ins_pipe( pipe_slow ); | |
| 11147 %} | |
| 11148 | |
| 11149 // Compare into -1,0,1 in XMM and memory | |
| 11150 instruct cmpX_regmem(eRegI dst, regX src1, memory mem, eFlagsReg cr) %{ | |
| 11151 predicate(UseSSE>=1); | |
| 11152 match(Set dst (CmpF3 src1 (LoadF mem))); | |
| 11153 effect(KILL cr); | |
| 11154 ins_cost(275); | |
| 11155 format %{ "COMISS $src1,$mem\n" | |
| 11156 "\tMOV $dst,0\t\t# do not blow flags\n" | |
| 11157 "\tJP,s nan\n" | |
| 11158 "\tJEQ,s exit\n" | |
| 11159 "\tJA,s inc\n" | |
| 11160 "nan:\tDEC $dst\n" | |
| 11161 "\tJMP,s exit\n" | |
| 11162 "inc:\tINC $dst\n" | |
| 11163 "exit:" | |
| 11164 %} | |
| 11165 opcode(0x0F, 0x2F); | |
| 11166 ins_encode(OpcP, OpcS, RegMem(src1, mem), LdImmI(dst,0x0), CmpX_Result(dst)); | |
| 11167 ins_pipe( pipe_slow ); | |
| 11168 %} | |
| 11169 | |
| 11170 // Spill to obtain 24-bit precision | |
| 11171 instruct subF24_reg(stackSlotF dst, regF src1, regF src2) %{ | |
| 11172 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 11173 match(Set dst (SubF src1 src2)); | |
| 11174 | |
| 11175 format %{ "FSUB $dst,$src1 - $src2" %} | |
| 11176 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */ | |
| 11177 ins_encode( Push_Reg_F(src1), | |
| 11178 OpcReg_F(src2), | |
| 11179 Pop_Mem_F(dst) ); | |
| 11180 ins_pipe( fpu_mem_reg_reg ); | |
| 11181 %} | |
| 11182 // | |
| 11183 // This instruction does not round to 24-bits | |
| 11184 instruct subF_reg(regF dst, regF src) %{ | |
| 11185 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 11186 match(Set dst (SubF dst src)); | |
| 11187 | |
| 11188 format %{ "FSUB $dst,$src" %} | |
| 11189 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */ | |
| 11190 ins_encode( Push_Reg_F(src), | |
| 11191 OpcP, RegOpc(dst) ); | |
| 11192 ins_pipe( fpu_reg_reg ); | |
| 11193 %} | |
| 11194 | |
| 11195 // Spill to obtain 24-bit precision | |
| 11196 instruct addF24_reg(stackSlotF dst, regF src1, regF src2) %{ | |
| 11197 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 11198 match(Set dst (AddF src1 src2)); | |
| 11199 | |
| 11200 format %{ "FADD $dst,$src1,$src2" %} | |
| 11201 opcode(0xD8, 0x0); /* D8 C0+i */ | |
| 11202 ins_encode( Push_Reg_F(src2), | |
| 11203 OpcReg_F(src1), | |
| 11204 Pop_Mem_F(dst) ); | |
| 11205 ins_pipe( fpu_mem_reg_reg ); | |
| 11206 %} | |
| 11207 // | |
| 11208 // This instruction does not round to 24-bits | |
| 11209 instruct addF_reg(regF dst, regF src) %{ | |
| 11210 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 11211 match(Set dst (AddF dst src)); | |
| 11212 | |
| 11213 format %{ "FLD $src\n\t" | |
| 11214 "FADDp $dst,ST" %} | |
| 11215 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/ | |
| 11216 ins_encode( Push_Reg_F(src), | |
| 11217 OpcP, RegOpc(dst) ); | |
| 11218 ins_pipe( fpu_reg_reg ); | |
| 11219 %} | |
| 11220 | |
| 11221 // Add two single precision floating point values in xmm | |
| 11222 instruct addX_reg(regX dst, regX src) %{ | |
| 11223 predicate(UseSSE>=1); | |
| 11224 match(Set dst (AddF dst src)); | |
| 11225 format %{ "ADDSS $dst,$src" %} | |
| 11226 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegReg(dst, src)); | |
| 11227 ins_pipe( pipe_slow ); | |
| 11228 %} | |
| 11229 | |
| 11230 instruct addX_imm(regX dst, immXF con) %{ | |
| 11231 predicate(UseSSE>=1); | |
| 11232 match(Set dst (AddF dst con)); | |
| 2008 | 11233 format %{ "ADDSS $dst,[$constantaddress]\t# load from constant table: float=$con" %} |
| 11234 ins_encode %{ | |
| 11235 __ addss($dst$$XMMRegister, $constantaddress($con)); | |
| 11236 %} | |
| 11237 ins_pipe(pipe_slow); | |
| 0 | 11238 %} |
| 11239 | |
| 11240 instruct addX_mem(regX dst, memory mem) %{ | |
| 11241 predicate(UseSSE>=1); | |
| 11242 match(Set dst (AddF dst (LoadF mem))); | |
| 11243 format %{ "ADDSS $dst,$mem" %} | |
| 11244 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegMem(dst, mem)); | |
| 11245 ins_pipe( pipe_slow ); | |
| 11246 %} | |
| 11247 | |
| 11248 // Subtract two single precision floating point values in xmm | |
| 11249 instruct subX_reg(regX dst, regX src) %{ | |
| 11250 predicate(UseSSE>=1); | |
| 11251 match(Set dst (SubF dst src)); | |
| 11252 format %{ "SUBSS $dst,$src" %} | |
| 11253 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src)); | |
| 11254 ins_pipe( pipe_slow ); | |
| 11255 %} | |
| 11256 | |
| 11257 instruct subX_imm(regX dst, immXF con) %{ | |
| 11258 predicate(UseSSE>=1); | |
| 11259 match(Set dst (SubF dst con)); | |
| 2008 | 11260 format %{ "SUBSS $dst,[$constantaddress]\t# load from constant table: float=$con" %} |
| 11261 ins_encode %{ | |
| 11262 __ subss($dst$$XMMRegister, $constantaddress($con)); | |
| 11263 %} | |
| 11264 ins_pipe(pipe_slow); | |
| 0 | 11265 %} |
| 11266 | |
| 11267 instruct subX_mem(regX dst, memory mem) %{ | |
| 11268 predicate(UseSSE>=1); | |
| 11269 match(Set dst (SubF dst (LoadF mem))); | |
| 11270 format %{ "SUBSS $dst,$mem" %} | |
| 11271 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem)); | |
| 11272 ins_pipe( pipe_slow ); | |
| 11273 %} | |
| 11274 | |
| 11275 // Multiply two single precision floating point values in xmm | |
| 11276 instruct mulX_reg(regX dst, regX src) %{ | |
| 11277 predicate(UseSSE>=1); | |
| 11278 match(Set dst (MulF dst src)); | |
| 11279 format %{ "MULSS $dst,$src" %} | |
| 11280 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegReg(dst, src)); | |
| 11281 ins_pipe( pipe_slow ); | |
| 11282 %} | |
| 11283 | |
| 11284 instruct mulX_imm(regX dst, immXF con) %{ | |
| 11285 predicate(UseSSE>=1); | |
| 11286 match(Set dst (MulF dst con)); | |
| 2008 | 11287 format %{ "MULSS $dst,[$constantaddress]\t# load from constant table: float=$con" %} |
| 11288 ins_encode %{ | |
| 11289 __ mulss($dst$$XMMRegister, $constantaddress($con)); | |
| 11290 %} | |
| 11291 ins_pipe(pipe_slow); | |
| 0 | 11292 %} |
| 11293 | |
| 11294 instruct mulX_mem(regX dst, memory mem) %{ | |
| 11295 predicate(UseSSE>=1); | |
| 11296 match(Set dst (MulF dst (LoadF mem))); | |
| 11297 format %{ "MULSS $dst,$mem" %} | |
| 11298 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem)); | |
| 11299 ins_pipe( pipe_slow ); | |
| 11300 %} | |
| 11301 | |
| 11302 // Divide two single precision floating point values in xmm | |
| 11303 instruct divX_reg(regX dst, regX src) %{ | |
| 11304 predicate(UseSSE>=1); | |
| 11305 match(Set dst (DivF dst src)); | |
| 11306 format %{ "DIVSS $dst,$src" %} | |
| 11307 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src)); | |
| 11308 ins_pipe( pipe_slow ); | |
| 11309 %} | |
| 11310 | |
| 11311 instruct divX_imm(regX dst, immXF con) %{ | |
| 11312 predicate(UseSSE>=1); | |
| 11313 match(Set dst (DivF dst con)); | |
| 2008 | 11314 format %{ "DIVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %} |
| 11315 ins_encode %{ | |
| 11316 __ divss($dst$$XMMRegister, $constantaddress($con)); | |
| 11317 %} | |
| 11318 ins_pipe(pipe_slow); | |
| 0 | 11319 %} |
| 11320 | |
| 11321 instruct divX_mem(regX dst, memory mem) %{ | |
| 11322 predicate(UseSSE>=1); | |
| 11323 match(Set dst (DivF dst (LoadF mem))); | |
| 11324 format %{ "DIVSS $dst,$mem" %} | |
| 11325 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem)); | |
| 11326 ins_pipe( pipe_slow ); | |
| 11327 %} | |
| 11328 | |
| 11329 // Get the square root of a single precision floating point values in xmm | |
| 11330 instruct sqrtX_reg(regX dst, regX src) %{ | |
| 11331 predicate(UseSSE>=1); | |
| 11332 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); | |
| 11333 format %{ "SQRTSS $dst,$src" %} | |
| 11334 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegReg(dst, src)); | |
| 11335 ins_pipe( pipe_slow ); | |
| 11336 %} | |
| 11337 | |
| 11338 instruct sqrtX_mem(regX dst, memory mem) %{ | |
| 11339 predicate(UseSSE>=1); | |
| 11340 match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF mem))))); | |
| 11341 format %{ "SQRTSS $dst,$mem" %} | |
| 11342 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem)); | |
| 11343 ins_pipe( pipe_slow ); | |
| 11344 %} | |
| 11345 | |
| 11346 // Get the square root of a double precision floating point values in xmm | |
| 11347 instruct sqrtXD_reg(regXD dst, regXD src) %{ | |
| 11348 predicate(UseSSE>=2); | |
| 11349 match(Set dst (SqrtD src)); | |
| 11350 format %{ "SQRTSD $dst,$src" %} | |
| 11351 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegReg(dst, src)); | |
| 11352 ins_pipe( pipe_slow ); | |
| 11353 %} | |
| 11354 | |
| 11355 instruct sqrtXD_mem(regXD dst, memory mem) %{ | |
| 11356 predicate(UseSSE>=2); | |
| 11357 match(Set dst (SqrtD (LoadD mem))); | |
| 11358 format %{ "SQRTSD $dst,$mem" %} | |
| 11359 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem)); | |
| 11360 ins_pipe( pipe_slow ); | |
| 11361 %} | |
| 11362 | |
| 11363 instruct absF_reg(regFPR1 dst, regFPR1 src) %{ | |
| 11364 predicate(UseSSE==0); | |
| 11365 match(Set dst (AbsF src)); | |
| 11366 ins_cost(100); | |
| 11367 format %{ "FABS" %} | |
| 11368 opcode(0xE1, 0xD9); | |
| 11369 ins_encode( OpcS, OpcP ); | |
| 11370 ins_pipe( fpu_reg_reg ); | |
| 11371 %} | |
| 11372 | |
| 11373 instruct absX_reg(regX dst ) %{ | |
| 11374 predicate(UseSSE>=1); | |
| 11375 match(Set dst (AbsF dst)); | |
| 11376 format %{ "ANDPS $dst,[0x7FFFFFFF]\t# ABS F by sign masking" %} | |
| 11377 ins_encode( AbsXF_encoding(dst)); | |
| 11378 ins_pipe( pipe_slow ); | |
| 11379 %} | |
| 11380 | |
| 11381 instruct negF_reg(regFPR1 dst, regFPR1 src) %{ | |
| 11382 predicate(UseSSE==0); | |
| 11383 match(Set dst (NegF src)); | |
| 11384 ins_cost(100); | |
| 11385 format %{ "FCHS" %} | |
| 11386 opcode(0xE0, 0xD9); | |
| 11387 ins_encode( OpcS, OpcP ); | |
| 11388 ins_pipe( fpu_reg_reg ); | |
| 11389 %} | |
| 11390 | |
| 11391 instruct negX_reg( regX dst ) %{ | |
| 11392 predicate(UseSSE>=1); | |
| 11393 match(Set dst (NegF dst)); | |
| 11394 format %{ "XORPS $dst,[0x80000000]\t# CHS F by sign flipping" %} | |
| 11395 ins_encode( NegXF_encoding(dst)); | |
| 11396 ins_pipe( pipe_slow ); | |
| 11397 %} | |
| 11398 | |
| 11399 // Cisc-alternate to addF_reg | |
| 11400 // Spill to obtain 24-bit precision | |
| 11401 instruct addF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{ | |
| 11402 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 11403 match(Set dst (AddF src1 (LoadF src2))); | |
| 11404 | |
| 11405 format %{ "FLD $src2\n\t" | |
| 11406 "FADD ST,$src1\n\t" | |
| 11407 "FSTP_S $dst" %} | |
| 11408 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ | |
| 11409 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 11410 OpcReg_F(src1), | |
| 11411 Pop_Mem_F(dst) ); | |
| 11412 ins_pipe( fpu_mem_reg_mem ); | |
| 11413 %} | |
| 11414 // | |
| 11415 // Cisc-alternate to addF_reg | |
| 11416 // This instruction does not round to 24-bits | |
| 11417 instruct addF_reg_mem(regF dst, memory src) %{ | |
| 11418 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 11419 match(Set dst (AddF dst (LoadF src))); | |
| 11420 | |
| 11421 format %{ "FADD $dst,$src" %} | |
| 11422 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */ | |
| 11423 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 11424 OpcP, RegOpc(dst) ); | |
| 11425 ins_pipe( fpu_reg_mem ); | |
| 11426 %} | |
| 11427 | |
| 11428 // // Following two instructions for _222_mpegaudio | |
| 11429 // Spill to obtain 24-bit precision | |
| 11430 instruct addF24_mem_reg(stackSlotF dst, regF src2, memory src1 ) %{ | |
| 11431 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 11432 match(Set dst (AddF src1 src2)); | |
| 11433 | |
| 11434 format %{ "FADD $dst,$src1,$src2" %} | |
| 11435 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ | |
| 11436 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1), | |
| 11437 OpcReg_F(src2), | |
| 11438 Pop_Mem_F(dst) ); | |
| 11439 ins_pipe( fpu_mem_reg_mem ); | |
| 11440 %} | |
| 11441 | |
| 11442 // Cisc-spill variant | |
| 11443 // Spill to obtain 24-bit precision | |
| 11444 instruct addF24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{ | |
| 11445 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 11446 match(Set dst (AddF src1 (LoadF src2))); | |
| 11447 | |
| 11448 format %{ "FADD $dst,$src1,$src2 cisc" %} | |
| 11449 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ | |
| 11450 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 11451 set_instruction_start, | |
| 11452 OpcP, RMopc_Mem(secondary,src1), | |
| 11453 Pop_Mem_F(dst) ); | |
| 11454 ins_pipe( fpu_mem_mem_mem ); | |
| 11455 %} | |
| 11456 | |
| 11457 // Spill to obtain 24-bit precision | |
| 11458 instruct addF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{ | |
| 11459 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 11460 match(Set dst (AddF src1 src2)); | |
| 11461 | |
| 11462 format %{ "FADD $dst,$src1,$src2" %} | |
| 11463 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */ | |
| 11464 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 11465 set_instruction_start, | |
| 11466 OpcP, RMopc_Mem(secondary,src1), | |
| 11467 Pop_Mem_F(dst) ); | |
| 11468 ins_pipe( fpu_mem_mem_mem ); | |
| 11469 %} | |
| 11470 | |
| 11471 | |
| 11472 // Spill to obtain 24-bit precision | |
| 2008 | 11473 instruct addF24_reg_imm(stackSlotF dst, regF src, immF con) %{ |
| 0 | 11474 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 2008 | 11475 match(Set dst (AddF src con)); |
| 11476 format %{ "FLD $src\n\t" | |
| 11477 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 0 | 11478 "FSTP_S $dst" %} |
| 2008 | 11479 ins_encode %{ |
| 11480 __ fld_s($src$$reg - 1); // FLD ST(i-1) | |
| 11481 __ fadd_s($constantaddress($con)); | |
| 11482 __ fstp_s(Address(rsp, $dst$$disp)); | |
| 11483 %} | |
| 11484 ins_pipe(fpu_mem_reg_con); | |
| 0 | 11485 %} |
| 11486 // | |
| 11487 // This instruction does not round to 24-bits | |
| 2008 | 11488 instruct addF_reg_imm(regF dst, regF src, immF con) %{ |
| 0 | 11489 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 2008 | 11490 match(Set dst (AddF src con)); |
| 11491 format %{ "FLD $src\n\t" | |
| 11492 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 11493 "FSTP $dst" %} | |
| 11494 ins_encode %{ | |
| 11495 __ fld_s($src$$reg - 1); // FLD ST(i-1) | |
| 11496 __ fadd_s($constantaddress($con)); | |
| 11497 __ fstp_d($dst$$reg); | |
| 11498 %} | |
| 11499 ins_pipe(fpu_reg_reg_con); | |
| 0 | 11500 %} |
| 11501 | |
| 11502 // Spill to obtain 24-bit precision | |
| 11503 instruct mulF24_reg(stackSlotF dst, regF src1, regF src2) %{ | |
| 11504 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 11505 match(Set dst (MulF src1 src2)); | |
| 11506 | |
| 11507 format %{ "FLD $src1\n\t" | |
| 11508 "FMUL $src2\n\t" | |
| 11509 "FSTP_S $dst" %} | |
| 11510 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */ | |
| 11511 ins_encode( Push_Reg_F(src1), | |
| 11512 OpcReg_F(src2), | |
| 11513 Pop_Mem_F(dst) ); | |
| 11514 ins_pipe( fpu_mem_reg_reg ); | |
| 11515 %} | |
| 11516 // | |
| 11517 // This instruction does not round to 24-bits | |
| 11518 instruct mulF_reg(regF dst, regF src1, regF src2) %{ | |
| 11519 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 11520 match(Set dst (MulF src1 src2)); | |
| 11521 | |
| 11522 format %{ "FLD $src1\n\t" | |
| 11523 "FMUL $src2\n\t" | |
| 11524 "FSTP_S $dst" %} | |
| 11525 opcode(0xD8, 0x1); /* D8 C8+i */ | |
| 11526 ins_encode( Push_Reg_F(src2), | |
| 11527 OpcReg_F(src1), | |
| 11528 Pop_Reg_F(dst) ); | |
| 11529 ins_pipe( fpu_reg_reg_reg ); | |
| 11530 %} | |
| 11531 | |
| 11532 | |
| 11533 // Spill to obtain 24-bit precision | |
| 11534 // Cisc-alternate to reg-reg multiply | |
| 11535 instruct mulF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{ | |
| 11536 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 11537 match(Set dst (MulF src1 (LoadF src2))); | |
| 11538 | |
| 11539 format %{ "FLD_S $src2\n\t" | |
| 11540 "FMUL $src1\n\t" | |
| 11541 "FSTP_S $dst" %} | |
| 11542 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */ | |
| 11543 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 11544 OpcReg_F(src1), | |
| 11545 Pop_Mem_F(dst) ); | |
| 11546 ins_pipe( fpu_mem_reg_mem ); | |
| 11547 %} | |
| 11548 // | |
| 11549 // This instruction does not round to 24-bits | |
| 11550 // Cisc-alternate to reg-reg multiply | |
| 11551 instruct mulF_reg_mem(regF dst, regF src1, memory src2) %{ | |
| 11552 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 11553 match(Set dst (MulF src1 (LoadF src2))); | |
| 11554 | |
| 11555 format %{ "FMUL $dst,$src1,$src2" %} | |
| 11556 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */ | |
| 11557 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 11558 OpcReg_F(src1), | |
| 11559 Pop_Reg_F(dst) ); | |
| 11560 ins_pipe( fpu_reg_reg_mem ); | |
| 11561 %} | |
| 11562 | |
| 11563 // Spill to obtain 24-bit precision | |
| 11564 instruct mulF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{ | |
| 11565 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 11566 match(Set dst (MulF src1 src2)); | |
| 11567 | |
| 11568 format %{ "FMUL $dst,$src1,$src2" %} | |
| 11569 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */ | |
| 11570 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 11571 set_instruction_start, | |
| 11572 OpcP, RMopc_Mem(secondary,src1), | |
| 11573 Pop_Mem_F(dst) ); | |
| 11574 ins_pipe( fpu_mem_mem_mem ); | |
| 11575 %} | |
| 11576 | |
| 11577 // Spill to obtain 24-bit precision | |
| 2008 | 11578 instruct mulF24_reg_imm(stackSlotF dst, regF src, immF con) %{ |
| 0 | 11579 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 2008 | 11580 match(Set dst (MulF src con)); |
| 11581 | |
| 11582 format %{ "FLD $src\n\t" | |
| 11583 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 11584 "FSTP_S $dst" %} | |
| 11585 ins_encode %{ | |
| 11586 __ fld_s($src$$reg - 1); // FLD ST(i-1) | |
| 11587 __ fmul_s($constantaddress($con)); | |
| 11588 __ fstp_s(Address(rsp, $dst$$disp)); | |
| 11589 %} | |
| 11590 ins_pipe(fpu_mem_reg_con); | |
| 0 | 11591 %} |
| 11592 // | |
| 11593 // This instruction does not round to 24-bits | |
| 2008 | 11594 instruct mulF_reg_imm(regF dst, regF src, immF con) %{ |
| 0 | 11595 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 2008 | 11596 match(Set dst (MulF src con)); |
| 11597 | |
| 11598 format %{ "FLD $src\n\t" | |
| 11599 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 11600 "FSTP $dst" %} | |
| 11601 ins_encode %{ | |
| 11602 __ fld_s($src$$reg - 1); // FLD ST(i-1) | |
| 11603 __ fmul_s($constantaddress($con)); | |
| 11604 __ fstp_d($dst$$reg); | |
| 11605 %} | |
| 11606 ins_pipe(fpu_reg_reg_con); | |
| 0 | 11607 %} |
| 11608 | |
| 11609 | |
| 11610 // | |
| 11611 // MACRO1 -- subsume unshared load into mulF | |
| 11612 // This instruction does not round to 24-bits | |
| 11613 instruct mulF_reg_load1(regF dst, regF src, memory mem1 ) %{ | |
| 11614 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 11615 match(Set dst (MulF (LoadF mem1) src)); | |
| 11616 | |
| 11617 format %{ "FLD $mem1 ===MACRO1===\n\t" | |
| 11618 "FMUL ST,$src\n\t" | |
| 11619 "FSTP $dst" %} | |
| 11620 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */ | |
| 11621 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1), | |
| 11622 OpcReg_F(src), | |
| 11623 Pop_Reg_F(dst) ); | |
| 11624 ins_pipe( fpu_reg_reg_mem ); | |
| 11625 %} | |
| 11626 // | |
| 11627 // MACRO2 -- addF a mulF which subsumed an unshared load | |
| 11628 // This instruction does not round to 24-bits | |
| 11629 instruct addF_mulF_reg_load1(regF dst, memory mem1, regF src1, regF src2) %{ | |
| 11630 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 11631 match(Set dst (AddF (MulF (LoadF mem1) src1) src2)); | |
| 11632 ins_cost(95); | |
| 11633 | |
| 11634 format %{ "FLD $mem1 ===MACRO2===\n\t" | |
| 11635 "FMUL ST,$src1 subsume mulF left load\n\t" | |
| 11636 "FADD ST,$src2\n\t" | |
| 11637 "FSTP $dst" %} | |
| 11638 opcode(0xD9); /* LoadF D9 /0 */ | |
| 11639 ins_encode( OpcP, RMopc_Mem(0x00,mem1), | |
| 11640 FMul_ST_reg(src1), | |
| 11641 FAdd_ST_reg(src2), | |
| 11642 Pop_Reg_F(dst) ); | |
| 11643 ins_pipe( fpu_reg_mem_reg_reg ); | |
| 11644 %} | |
| 11645 | |
| 11646 // MACRO3 -- addF a mulF | |
| 11647 // This instruction does not round to 24-bits. It is a '2-address' | |
| 11648 // instruction in that the result goes back to src2. This eliminates | |
| 11649 // a move from the macro; possibly the register allocator will have | |
| 11650 // to add it back (and maybe not). | |
| 11651 instruct addF_mulF_reg(regF src2, regF src1, regF src0) %{ | |
| 11652 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 11653 match(Set src2 (AddF (MulF src0 src1) src2)); | |
| 11654 | |
| 11655 format %{ "FLD $src0 ===MACRO3===\n\t" | |
| 11656 "FMUL ST,$src1\n\t" | |
| 11657 "FADDP $src2,ST" %} | |
| 11658 opcode(0xD9); /* LoadF D9 /0 */ | |
| 11659 ins_encode( Push_Reg_F(src0), | |
| 11660 FMul_ST_reg(src1), | |
| 11661 FAddP_reg_ST(src2) ); | |
| 11662 ins_pipe( fpu_reg_reg_reg ); | |
| 11663 %} | |
| 11664 | |
| 11665 // MACRO4 -- divF subF | |
| 11666 // This instruction does not round to 24-bits | |
| 11667 instruct subF_divF_reg(regF dst, regF src1, regF src2, regF src3) %{ | |
| 11668 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 11669 match(Set dst (DivF (SubF src2 src1) src3)); | |
| 11670 | |
| 11671 format %{ "FLD $src2 ===MACRO4===\n\t" | |
| 11672 "FSUB ST,$src1\n\t" | |
| 11673 "FDIV ST,$src3\n\t" | |
| 11674 "FSTP $dst" %} | |
| 11675 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
| 11676 ins_encode( Push_Reg_F(src2), | |
| 11677 subF_divF_encode(src1,src3), | |
| 11678 Pop_Reg_F(dst) ); | |
| 11679 ins_pipe( fpu_reg_reg_reg_reg ); | |
| 11680 %} | |
| 11681 | |
| 11682 // Spill to obtain 24-bit precision | |
| 11683 instruct divF24_reg(stackSlotF dst, regF src1, regF src2) %{ | |
| 11684 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 11685 match(Set dst (DivF src1 src2)); | |
| 11686 | |
| 11687 format %{ "FDIV $dst,$src1,$src2" %} | |
| 11688 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/ | |
| 11689 ins_encode( Push_Reg_F(src1), | |
| 11690 OpcReg_F(src2), | |
| 11691 Pop_Mem_F(dst) ); | |
| 11692 ins_pipe( fpu_mem_reg_reg ); | |
| 11693 %} | |
| 11694 // | |
| 11695 // This instruction does not round to 24-bits | |
| 11696 instruct divF_reg(regF dst, regF src) %{ | |
| 11697 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 11698 match(Set dst (DivF dst src)); | |
| 11699 | |
| 11700 format %{ "FDIV $dst,$src" %} | |
| 11701 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
| 11702 ins_encode( Push_Reg_F(src), | |
| 11703 OpcP, RegOpc(dst) ); | |
| 11704 ins_pipe( fpu_reg_reg ); | |
| 11705 %} | |
| 11706 | |
| 11707 | |
| 11708 // Spill to obtain 24-bit precision | |
| 11709 instruct modF24_reg(stackSlotF dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{ | |
| 11710 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 11711 match(Set dst (ModF src1 src2)); | |
| 11712 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS | |
| 11713 | |
| 11714 format %{ "FMOD $dst,$src1,$src2" %} | |
| 11715 ins_encode( Push_Reg_Mod_D(src1, src2), | |
| 11716 emitModD(), | |
| 11717 Push_Result_Mod_D(src2), | |
| 11718 Pop_Mem_F(dst)); | |
| 11719 ins_pipe( pipe_slow ); | |
| 11720 %} | |
| 11721 // | |
| 11722 // This instruction does not round to 24-bits | |
| 11723 instruct modF_reg(regF dst, regF src, eAXRegI rax, eFlagsReg cr) %{ | |
| 11724 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 11725 match(Set dst (ModF dst src)); | |
| 11726 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS | |
| 11727 | |
| 11728 format %{ "FMOD $dst,$src" %} | |
| 11729 ins_encode(Push_Reg_Mod_D(dst, src), | |
| 11730 emitModD(), | |
| 11731 Push_Result_Mod_D(src), | |
| 11732 Pop_Reg_F(dst)); | |
| 11733 ins_pipe( pipe_slow ); | |
| 11734 %} | |
| 11735 | |
| 11736 instruct modX_reg(regX dst, regX src0, regX src1, eAXRegI rax, eFlagsReg cr) %{ | |
| 11737 predicate(UseSSE>=1); | |
| 11738 match(Set dst (ModF src0 src1)); | |
| 11739 effect(KILL rax, KILL cr); | |
| 11740 format %{ "SUB ESP,4\t # FMOD\n" | |
| 11741 "\tMOVSS [ESP+0],$src1\n" | |
| 11742 "\tFLD_S [ESP+0]\n" | |
| 11743 "\tMOVSS [ESP+0],$src0\n" | |
| 11744 "\tFLD_S [ESP+0]\n" | |
| 11745 "loop:\tFPREM\n" | |
| 11746 "\tFWAIT\n" | |
| 11747 "\tFNSTSW AX\n" | |
| 11748 "\tSAHF\n" | |
| 11749 "\tJP loop\n" | |
| 11750 "\tFSTP_S [ESP+0]\n" | |
| 11751 "\tMOVSS $dst,[ESP+0]\n" | |
| 11752 "\tADD ESP,4\n" | |
| 11753 "\tFSTP ST0\t # Restore FPU Stack" | |
| 11754 %} | |
| 11755 ins_cost(250); | |
| 11756 ins_encode( Push_ModX_encoding(src0, src1), emitModD(), Push_ResultX(dst,0x4), PopFPU); | |
| 11757 ins_pipe( pipe_slow ); | |
| 11758 %} | |
| 11759 | |
| 11760 | |
| 11761 //----------Arithmetic Conversion Instructions--------------------------------- | |
| 11762 // The conversions operations are all Alpha sorted. Please keep it that way! | |
| 11763 | |
| 11764 instruct roundFloat_mem_reg(stackSlotF dst, regF src) %{ | |
| 11765 predicate(UseSSE==0); | |
| 11766 match(Set dst (RoundFloat src)); | |
| 11767 ins_cost(125); | |
| 11768 format %{ "FST_S $dst,$src\t# F-round" %} | |
| 11769 ins_encode( Pop_Mem_Reg_F(dst, src) ); | |
| 11770 ins_pipe( fpu_mem_reg ); | |
| 11771 %} | |
| 11772 | |
| 11773 instruct roundDouble_mem_reg(stackSlotD dst, regD src) %{ | |
| 11774 predicate(UseSSE<=1); | |
| 11775 match(Set dst (RoundDouble src)); | |
| 11776 ins_cost(125); | |
| 11777 format %{ "FST_D $dst,$src\t# D-round" %} | |
| 11778 ins_encode( Pop_Mem_Reg_D(dst, src) ); | |
| 11779 ins_pipe( fpu_mem_reg ); | |
| 11780 %} | |
| 11781 | |
| 11782 // Force rounding to 24-bit precision and 6-bit exponent | |
| 11783 instruct convD2F_reg(stackSlotF dst, regD src) %{ | |
| 11784 predicate(UseSSE==0); | |
| 11785 match(Set dst (ConvD2F src)); | |
| 11786 format %{ "FST_S $dst,$src\t# F-round" %} | |
| 11787 expand %{ | |
| 11788 roundFloat_mem_reg(dst,src); | |
| 11789 %} | |
| 11790 %} | |
| 11791 | |
| 11792 // Force rounding to 24-bit precision and 6-bit exponent | |
| 11793 instruct convD2X_reg(regX dst, regD src, eFlagsReg cr) %{ | |
| 11794 predicate(UseSSE==1); | |
| 11795 match(Set dst (ConvD2F src)); | |
| 11796 effect( KILL cr ); | |
| 11797 format %{ "SUB ESP,4\n\t" | |
| 11798 "FST_S [ESP],$src\t# F-round\n\t" | |
| 11799 "MOVSS $dst,[ESP]\n\t" | |
| 11800 "ADD ESP,4" %} | |
| 11801 ins_encode( D2X_encoding(dst, src) ); | |
| 11802 ins_pipe( pipe_slow ); | |
| 11803 %} | |
| 11804 | |
| 11805 // Force rounding double precision to single precision | |
| 11806 instruct convXD2X_reg(regX dst, regXD src) %{ | |
| 11807 predicate(UseSSE>=2); | |
| 11808 match(Set dst (ConvD2F src)); | |
| 11809 format %{ "CVTSD2SS $dst,$src\t# F-round" %} | |
| 11810 opcode(0xF2, 0x0F, 0x5A); | |
| 11811 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src)); | |
| 11812 ins_pipe( pipe_slow ); | |
| 11813 %} | |
| 11814 | |
| 11815 instruct convF2D_reg_reg(regD dst, regF src) %{ | |
| 11816 predicate(UseSSE==0); | |
| 11817 match(Set dst (ConvF2D src)); | |
| 11818 format %{ "FST_S $dst,$src\t# D-round" %} | |
| 11819 ins_encode( Pop_Reg_Reg_D(dst, src)); | |
| 11820 ins_pipe( fpu_reg_reg ); | |
| 11821 %} | |
| 11822 | |
| 11823 instruct convF2D_reg(stackSlotD dst, regF src) %{ | |
| 11824 predicate(UseSSE==1); | |
| 11825 match(Set dst (ConvF2D src)); | |
| 11826 format %{ "FST_D $dst,$src\t# D-round" %} | |
| 11827 expand %{ | |
| 11828 roundDouble_mem_reg(dst,src); | |
| 11829 %} | |
| 11830 %} | |
| 11831 | |
| 11832 instruct convX2D_reg(regD dst, regX src, eFlagsReg cr) %{ | |
| 11833 predicate(UseSSE==1); | |
| 11834 match(Set dst (ConvF2D src)); | |
| 11835 effect( KILL cr ); | |
| 11836 format %{ "SUB ESP,4\n\t" | |
| 11837 "MOVSS [ESP] $src\n\t" | |
| 11838 "FLD_S [ESP]\n\t" | |
| 11839 "ADD ESP,4\n\t" | |
| 11840 "FSTP $dst\t# D-round" %} | |
| 11841 ins_encode( X2D_encoding(dst, src), Pop_Reg_D(dst)); | |
| 11842 ins_pipe( pipe_slow ); | |
| 11843 %} | |
| 11844 | |
| 11845 instruct convX2XD_reg(regXD dst, regX src) %{ | |
| 11846 predicate(UseSSE>=2); | |
| 11847 match(Set dst (ConvF2D src)); | |
| 11848 format %{ "CVTSS2SD $dst,$src\t# D-round" %} | |
| 11849 opcode(0xF3, 0x0F, 0x5A); | |
| 11850 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src)); | |
| 11851 ins_pipe( pipe_slow ); | |
| 11852 %} | |
| 11853 | |
| 11854 // Convert a double to an int. If the double is a NAN, stuff a zero in instead. | |
| 11855 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{ | |
| 11856 predicate(UseSSE<=1); | |
| 11857 match(Set dst (ConvD2I src)); | |
| 11858 effect( KILL tmp, KILL cr ); | |
| 11859 format %{ "FLD $src\t# Convert double to int \n\t" | |
| 11860 "FLDCW trunc mode\n\t" | |
| 11861 "SUB ESP,4\n\t" | |
| 11862 "FISTp [ESP + #0]\n\t" | |
| 11863 "FLDCW std/24-bit mode\n\t" | |
| 11864 "POP EAX\n\t" | |
| 11865 "CMP EAX,0x80000000\n\t" | |
| 11866 "JNE,s fast\n\t" | |
| 11867 "FLD_D $src\n\t" | |
| 11868 "CALL d2i_wrapper\n" | |
| 11869 "fast:" %} | |
| 11870 ins_encode( Push_Reg_D(src), D2I_encoding(src) ); | |
| 11871 ins_pipe( pipe_slow ); | |
| 11872 %} | |
| 11873 | |
| 11874 // Convert a double to an int. If the double is a NAN, stuff a zero in instead. | |
| 11875 instruct convXD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regXD src, eFlagsReg cr ) %{ | |
| 11876 predicate(UseSSE>=2); | |
| 11877 match(Set dst (ConvD2I src)); | |
| 11878 effect( KILL tmp, KILL cr ); | |
| 11879 format %{ "CVTTSD2SI $dst, $src\n\t" | |
| 11880 "CMP $dst,0x80000000\n\t" | |
| 11881 "JNE,s fast\n\t" | |
| 11882 "SUB ESP, 8\n\t" | |
| 11883 "MOVSD [ESP], $src\n\t" | |
| 11884 "FLD_D [ESP]\n\t" | |
| 11885 "ADD ESP, 8\n\t" | |
| 11886 "CALL d2i_wrapper\n" | |
| 11887 "fast:" %} | |
| 11888 opcode(0x1); // double-precision conversion | |
| 11889 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst)); | |
| 11890 ins_pipe( pipe_slow ); | |
| 11891 %} | |
| 11892 | |
| 11893 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{ | |
| 11894 predicate(UseSSE<=1); | |
| 11895 match(Set dst (ConvD2L src)); | |
| 11896 effect( KILL cr ); | |
| 11897 format %{ "FLD $src\t# Convert double to long\n\t" | |
| 11898 "FLDCW trunc mode\n\t" | |
| 11899 "SUB ESP,8\n\t" | |
| 11900 "FISTp [ESP + #0]\n\t" | |
| 11901 "FLDCW std/24-bit mode\n\t" | |
| 11902 "POP EAX\n\t" | |
| 11903 "POP EDX\n\t" | |
| 11904 "CMP EDX,0x80000000\n\t" | |
| 11905 "JNE,s fast\n\t" | |
| 11906 "TEST EAX,EAX\n\t" | |
| 11907 "JNE,s fast\n\t" | |
| 11908 "FLD $src\n\t" | |
| 11909 "CALL d2l_wrapper\n" | |
| 11910 "fast:" %} | |
| 11911 ins_encode( Push_Reg_D(src), D2L_encoding(src) ); | |
| 11912 ins_pipe( pipe_slow ); | |
| 11913 %} | |
| 11914 | |
| 11915 // XMM lacks a float/double->long conversion, so use the old FPU stack. | |
| 11916 instruct convXD2L_reg_reg( eADXRegL dst, regXD src, eFlagsReg cr ) %{ | |
| 11917 predicate (UseSSE>=2); | |
| 11918 match(Set dst (ConvD2L src)); | |
| 11919 effect( KILL cr ); | |
| 11920 format %{ "SUB ESP,8\t# Convert double to long\n\t" | |
| 11921 "MOVSD [ESP],$src\n\t" | |
| 11922 "FLD_D [ESP]\n\t" | |
| 11923 "FLDCW trunc mode\n\t" | |
| 11924 "FISTp [ESP + #0]\n\t" | |
| 11925 "FLDCW std/24-bit mode\n\t" | |
| 11926 "POP EAX\n\t" | |
| 11927 "POP EDX\n\t" | |
| 11928 "CMP EDX,0x80000000\n\t" | |
| 11929 "JNE,s fast\n\t" | |
| 11930 "TEST EAX,EAX\n\t" | |
| 11931 "JNE,s fast\n\t" | |
| 11932 "SUB ESP,8\n\t" | |
| 11933 "MOVSD [ESP],$src\n\t" | |
| 11934 "FLD_D [ESP]\n\t" | |
| 11935 "CALL d2l_wrapper\n" | |
| 11936 "fast:" %} | |
| 11937 ins_encode( XD2L_encoding(src) ); | |
| 11938 ins_pipe( pipe_slow ); | |
| 11939 %} | |
| 11940 | |
| 11941 // Convert a double to an int. Java semantics require we do complex | |
| 11942 // manglations in the corner cases. So we set the rounding mode to | |
| 11943 // 'zero', store the darned double down as an int, and reset the | |
| 11944 // rounding mode to 'nearest'. The hardware stores a flag value down | |
| 11945 // if we would overflow or converted a NAN; we check for this and | |
| 11946 // and go the slow path if needed. | |
| 11947 instruct convF2I_reg_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{ | |
| 11948 predicate(UseSSE==0); | |
| 11949 match(Set dst (ConvF2I src)); | |
| 11950 effect( KILL tmp, KILL cr ); | |
| 11951 format %{ "FLD $src\t# Convert float to int \n\t" | |
| 11952 "FLDCW trunc mode\n\t" | |
| 11953 "SUB ESP,4\n\t" | |
| 11954 "FISTp [ESP + #0]\n\t" | |
| 11955 "FLDCW std/24-bit mode\n\t" | |
| 11956 "POP EAX\n\t" | |
| 11957 "CMP EAX,0x80000000\n\t" | |
| 11958 "JNE,s fast\n\t" | |
| 11959 "FLD $src\n\t" | |
| 11960 "CALL d2i_wrapper\n" | |
| 11961 "fast:" %} | |
| 11962 // D2I_encoding works for F2I | |
| 11963 ins_encode( Push_Reg_F(src), D2I_encoding(src) ); | |
| 11964 ins_pipe( pipe_slow ); | |
| 11965 %} | |
| 11966 | |
| 11967 // Convert a float in xmm to an int reg. | |
| 11968 instruct convX2I_reg(eAXRegI dst, eDXRegI tmp, regX src, eFlagsReg cr ) %{ | |
| 11969 predicate(UseSSE>=1); | |
| 11970 match(Set dst (ConvF2I src)); | |
| 11971 effect( KILL tmp, KILL cr ); | |
| 11972 format %{ "CVTTSS2SI $dst, $src\n\t" | |
| 11973 "CMP $dst,0x80000000\n\t" | |
| 11974 "JNE,s fast\n\t" | |
| 11975 "SUB ESP, 4\n\t" | |
| 11976 "MOVSS [ESP], $src\n\t" | |
| 11977 "FLD [ESP]\n\t" | |
| 11978 "ADD ESP, 4\n\t" | |
| 11979 "CALL d2i_wrapper\n" | |
| 11980 "fast:" %} | |
| 11981 opcode(0x0); // single-precision conversion | |
| 11982 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst)); | |
| 11983 ins_pipe( pipe_slow ); | |
| 11984 %} | |
| 11985 | |
| 11986 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{ | |
| 11987 predicate(UseSSE==0); | |
| 11988 match(Set dst (ConvF2L src)); | |
| 11989 effect( KILL cr ); | |
| 11990 format %{ "FLD $src\t# Convert float to long\n\t" | |
| 11991 "FLDCW trunc mode\n\t" | |
| 11992 "SUB ESP,8\n\t" | |
| 11993 "FISTp [ESP + #0]\n\t" | |
| 11994 "FLDCW std/24-bit mode\n\t" | |
| 11995 "POP EAX\n\t" | |
| 11996 "POP EDX\n\t" | |
| 11997 "CMP EDX,0x80000000\n\t" | |
| 11998 "JNE,s fast\n\t" | |
| 11999 "TEST EAX,EAX\n\t" | |
| 12000 "JNE,s fast\n\t" | |
| 12001 "FLD $src\n\t" | |
| 12002 "CALL d2l_wrapper\n" | |
| 12003 "fast:" %} | |
| 12004 // D2L_encoding works for F2L | |
| 12005 ins_encode( Push_Reg_F(src), D2L_encoding(src) ); | |
| 12006 ins_pipe( pipe_slow ); | |
| 12007 %} | |
| 12008 | |
| 12009 // XMM lacks a float/double->long conversion, so use the old FPU stack. | |
| 12010 instruct convX2L_reg_reg( eADXRegL dst, regX src, eFlagsReg cr ) %{ | |
| 12011 predicate (UseSSE>=1); | |
| 12012 match(Set dst (ConvF2L src)); | |
| 12013 effect( KILL cr ); | |
| 12014 format %{ "SUB ESP,8\t# Convert float to long\n\t" | |
| 12015 "MOVSS [ESP],$src\n\t" | |
| 12016 "FLD_S [ESP]\n\t" | |
| 12017 "FLDCW trunc mode\n\t" | |
| 12018 "FISTp [ESP + #0]\n\t" | |
| 12019 "FLDCW std/24-bit mode\n\t" | |
| 12020 "POP EAX\n\t" | |
| 12021 "POP EDX\n\t" | |
| 12022 "CMP EDX,0x80000000\n\t" | |
| 12023 "JNE,s fast\n\t" | |
| 12024 "TEST EAX,EAX\n\t" | |
| 12025 "JNE,s fast\n\t" | |
| 12026 "SUB ESP,4\t# Convert float to long\n\t" | |
| 12027 "MOVSS [ESP],$src\n\t" | |
| 12028 "FLD_S [ESP]\n\t" | |
| 12029 "ADD ESP,4\n\t" | |
| 12030 "CALL d2l_wrapper\n" | |
| 12031 "fast:" %} | |
| 12032 ins_encode( X2L_encoding(src) ); | |
| 12033 ins_pipe( pipe_slow ); | |
| 12034 %} | |
| 12035 | |
| 12036 instruct convI2D_reg(regD dst, stackSlotI src) %{ | |
| 12037 predicate( UseSSE<=1 ); | |
| 12038 match(Set dst (ConvI2D src)); | |
| 12039 format %{ "FILD $src\n\t" | |
| 12040 "FSTP $dst" %} | |
| 12041 opcode(0xDB, 0x0); /* DB /0 */ | |
| 12042 ins_encode(Push_Mem_I(src), Pop_Reg_D(dst)); | |
| 12043 ins_pipe( fpu_reg_mem ); | |
| 12044 %} | |
| 12045 | |
| 12046 instruct convI2XD_reg(regXD dst, eRegI src) %{ | |
| 71 | 12047 predicate( UseSSE>=2 && !UseXmmI2D ); |
| 0 | 12048 match(Set dst (ConvI2D src)); |
| 12049 format %{ "CVTSI2SD $dst,$src" %} | |
| 12050 opcode(0xF2, 0x0F, 0x2A); | |
| 12051 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src)); | |
| 12052 ins_pipe( pipe_slow ); | |
| 12053 %} | |
| 12054 | |
| 12055 instruct convI2XD_mem(regXD dst, memory mem) %{ | |
| 12056 predicate( UseSSE>=2 ); | |
| 12057 match(Set dst (ConvI2D (LoadI mem))); | |
| 12058 format %{ "CVTSI2SD $dst,$mem" %} | |
| 12059 opcode(0xF2, 0x0F, 0x2A); | |
| 12060 ins_encode( OpcP, OpcS, Opcode(tertiary), RegMem(dst, mem)); | |
| 12061 ins_pipe( pipe_slow ); | |
| 12062 %} | |
| 12063 | |
| 71 | 12064 instruct convXI2XD_reg(regXD dst, eRegI src) |
| 12065 %{ | |
| 12066 predicate( UseSSE>=2 && UseXmmI2D ); | |
| 12067 match(Set dst (ConvI2D src)); | |
| 12068 | |
| 12069 format %{ "MOVD $dst,$src\n\t" | |
| 12070 "CVTDQ2PD $dst,$dst\t# i2d" %} | |
| 12071 ins_encode %{ | |
| 304 | 12072 __ movdl($dst$$XMMRegister, $src$$Register); |
| 71 | 12073 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister); |
| 12074 %} | |
| 12075 ins_pipe(pipe_slow); // XXX | |
| 12076 %} | |
| 12077 | |
| 0 | 12078 instruct convI2D_mem(regD dst, memory mem) %{ |
| 12079 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr()); | |
| 12080 match(Set dst (ConvI2D (LoadI mem))); | |
| 12081 format %{ "FILD $mem\n\t" | |
| 12082 "FSTP $dst" %} | |
| 12083 opcode(0xDB); /* DB /0 */ | |
| 12084 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
| 12085 Pop_Reg_D(dst)); | |
| 12086 ins_pipe( fpu_reg_mem ); | |
| 12087 %} | |
| 12088 | |
| 12089 // Convert a byte to a float; no rounding step needed. | |
| 12090 instruct conv24I2F_reg(regF dst, stackSlotI src) %{ | |
| 12091 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 ); | |
| 12092 match(Set dst (ConvI2F src)); | |
| 12093 format %{ "FILD $src\n\t" | |
| 12094 "FSTP $dst" %} | |
| 12095 | |
| 12096 opcode(0xDB, 0x0); /* DB /0 */ | |
| 12097 ins_encode(Push_Mem_I(src), Pop_Reg_F(dst)); | |
| 12098 ins_pipe( fpu_reg_mem ); | |
| 12099 %} | |
| 12100 | |
| 12101 // In 24-bit mode, force exponent rounding by storing back out | |
| 12102 instruct convI2F_SSF(stackSlotF dst, stackSlotI src) %{ | |
| 12103 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 12104 match(Set dst (ConvI2F src)); | |
| 12105 ins_cost(200); | |
| 12106 format %{ "FILD $src\n\t" | |
| 12107 "FSTP_S $dst" %} | |
| 12108 opcode(0xDB, 0x0); /* DB /0 */ | |
| 12109 ins_encode( Push_Mem_I(src), | |
| 12110 Pop_Mem_F(dst)); | |
| 12111 ins_pipe( fpu_mem_mem ); | |
| 12112 %} | |
| 12113 | |
| 12114 // In 24-bit mode, force exponent rounding by storing back out | |
| 12115 instruct convI2F_SSF_mem(stackSlotF dst, memory mem) %{ | |
| 12116 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); | |
| 12117 match(Set dst (ConvI2F (LoadI mem))); | |
| 12118 ins_cost(200); | |
| 12119 format %{ "FILD $mem\n\t" | |
| 12120 "FSTP_S $dst" %} | |
| 12121 opcode(0xDB); /* DB /0 */ | |
| 12122 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
| 12123 Pop_Mem_F(dst)); | |
| 12124 ins_pipe( fpu_mem_mem ); | |
| 12125 %} | |
| 12126 | |
| 12127 // This instruction does not round to 24-bits | |
| 12128 instruct convI2F_reg(regF dst, stackSlotI src) %{ | |
| 12129 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 12130 match(Set dst (ConvI2F src)); | |
| 12131 format %{ "FILD $src\n\t" | |
| 12132 "FSTP $dst" %} | |
| 12133 opcode(0xDB, 0x0); /* DB /0 */ | |
| 12134 ins_encode( Push_Mem_I(src), | |
| 12135 Pop_Reg_F(dst)); | |
| 12136 ins_pipe( fpu_reg_mem ); | |
| 12137 %} | |
| 12138 | |
| 12139 // This instruction does not round to 24-bits | |
| 12140 instruct convI2F_mem(regF dst, memory mem) %{ | |
| 12141 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); | |
| 12142 match(Set dst (ConvI2F (LoadI mem))); | |
| 12143 format %{ "FILD $mem\n\t" | |
| 12144 "FSTP $dst" %} | |
| 12145 opcode(0xDB); /* DB /0 */ | |
| 12146 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
| 12147 Pop_Reg_F(dst)); | |
| 12148 ins_pipe( fpu_reg_mem ); | |
| 12149 %} | |
| 12150 | |
| 12151 // Convert an int to a float in xmm; no rounding step needed. | |
| 12152 instruct convI2X_reg(regX dst, eRegI src) %{ | |
| 71 | 12153 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F ); |
| 0 | 12154 match(Set dst (ConvI2F src)); |
| 12155 format %{ "CVTSI2SS $dst, $src" %} | |
| 12156 | |
| 12157 opcode(0xF3, 0x0F, 0x2A); /* F3 0F 2A /r */ | |
| 12158 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src)); | |
| 12159 ins_pipe( pipe_slow ); | |
| 12160 %} | |
| 12161 | |
| 71 | 12162 instruct convXI2X_reg(regX dst, eRegI src) |
| 12163 %{ | |
| 12164 predicate( UseSSE>=2 && UseXmmI2F ); | |
| 12165 match(Set dst (ConvI2F src)); | |
| 12166 | |
| 12167 format %{ "MOVD $dst,$src\n\t" | |
| 12168 "CVTDQ2PS $dst,$dst\t# i2f" %} | |
| 12169 ins_encode %{ | |
| 304 | 12170 __ movdl($dst$$XMMRegister, $src$$Register); |
| 71 | 12171 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister); |
| 12172 %} | |
| 12173 ins_pipe(pipe_slow); // XXX | |
| 12174 %} | |
| 12175 | |
| 0 | 12176 instruct convI2L_reg( eRegL dst, eRegI src, eFlagsReg cr) %{ |
| 12177 match(Set dst (ConvI2L src)); | |
| 12178 effect(KILL cr); | |
| 624 | 12179 ins_cost(375); |
| 0 | 12180 format %{ "MOV $dst.lo,$src\n\t" |
| 12181 "MOV $dst.hi,$src\n\t" | |
| 12182 "SAR $dst.hi,31" %} | |
| 12183 ins_encode(convert_int_long(dst,src)); | |
| 12184 ins_pipe( ialu_reg_reg_long ); | |
| 12185 %} | |
| 12186 | |
| 12187 // Zero-extend convert int to long | |
| 12188 instruct convI2L_reg_zex(eRegL dst, eRegI src, immL_32bits mask, eFlagsReg flags ) %{ | |
| 12189 match(Set dst (AndL (ConvI2L src) mask) ); | |
| 12190 effect( KILL flags ); | |
| 624 | 12191 ins_cost(250); |
| 0 | 12192 format %{ "MOV $dst.lo,$src\n\t" |
| 12193 "XOR $dst.hi,$dst.hi" %} | |
| 12194 opcode(0x33); // XOR | |
| 12195 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) ); | |
| 12196 ins_pipe( ialu_reg_reg_long ); | |
| 12197 %} | |
| 12198 | |
| 12199 // Zero-extend long | |
| 12200 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{ | |
| 12201 match(Set dst (AndL src mask) ); | |
| 12202 effect( KILL flags ); | |
| 624 | 12203 ins_cost(250); |
| 0 | 12204 format %{ "MOV $dst.lo,$src.lo\n\t" |
| 12205 "XOR $dst.hi,$dst.hi\n\t" %} | |
| 12206 opcode(0x33); // XOR | |
| 12207 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) ); | |
| 12208 ins_pipe( ialu_reg_reg_long ); | |
| 12209 %} | |
| 12210 | |
| 12211 instruct convL2D_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{ | |
| 12212 predicate (UseSSE<=1); | |
| 12213 match(Set dst (ConvL2D src)); | |
| 12214 effect( KILL cr ); | |
| 12215 format %{ "PUSH $src.hi\t# Convert long to double\n\t" | |
| 12216 "PUSH $src.lo\n\t" | |
| 12217 "FILD ST,[ESP + #0]\n\t" | |
| 12218 "ADD ESP,8\n\t" | |
| 12219 "FSTP_D $dst\t# D-round" %} | |
| 12220 opcode(0xDF, 0x5); /* DF /5 */ | |
| 12221 ins_encode(convert_long_double(src), Pop_Mem_D(dst)); | |
| 12222 ins_pipe( pipe_slow ); | |
| 12223 %} | |
| 12224 | |
| 12225 instruct convL2XD_reg( regXD dst, eRegL src, eFlagsReg cr) %{ | |
| 12226 predicate (UseSSE>=2); | |
| 12227 match(Set dst (ConvL2D src)); | |
| 12228 effect( KILL cr ); | |
| 12229 format %{ "PUSH $src.hi\t# Convert long to double\n\t" | |
| 12230 "PUSH $src.lo\n\t" | |
| 12231 "FILD_D [ESP]\n\t" | |
| 12232 "FSTP_D [ESP]\n\t" | |
| 12233 "MOVSD $dst,[ESP]\n\t" | |
| 12234 "ADD ESP,8" %} | |
| 12235 opcode(0xDF, 0x5); /* DF /5 */ | |
| 12236 ins_encode(convert_long_double2(src), Push_ResultXD(dst)); | |
| 12237 ins_pipe( pipe_slow ); | |
| 12238 %} | |
| 12239 | |
| 12240 instruct convL2X_reg( regX dst, eRegL src, eFlagsReg cr) %{ | |
| 12241 predicate (UseSSE>=1); | |
| 12242 match(Set dst (ConvL2F src)); | |
| 12243 effect( KILL cr ); | |
| 12244 format %{ "PUSH $src.hi\t# Convert long to single float\n\t" | |
| 12245 "PUSH $src.lo\n\t" | |
| 12246 "FILD_D [ESP]\n\t" | |
| 12247 "FSTP_S [ESP]\n\t" | |
| 12248 "MOVSS $dst,[ESP]\n\t" | |
| 12249 "ADD ESP,8" %} | |
| 12250 opcode(0xDF, 0x5); /* DF /5 */ | |
| 12251 ins_encode(convert_long_double2(src), Push_ResultX(dst,0x8)); | |
| 12252 ins_pipe( pipe_slow ); | |
| 12253 %} | |
| 12254 | |
| 12255 instruct convL2F_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{ | |
| 12256 match(Set dst (ConvL2F src)); | |
| 12257 effect( KILL cr ); | |
| 12258 format %{ "PUSH $src.hi\t# Convert long to single float\n\t" | |
| 12259 "PUSH $src.lo\n\t" | |
| 12260 "FILD ST,[ESP + #0]\n\t" | |
| 12261 "ADD ESP,8\n\t" | |
| 12262 "FSTP_S $dst\t# F-round" %} | |
| 12263 opcode(0xDF, 0x5); /* DF /5 */ | |
| 12264 ins_encode(convert_long_double(src), Pop_Mem_F(dst)); | |
| 12265 ins_pipe( pipe_slow ); | |
| 12266 %} | |
| 12267 | |
| 12268 instruct convL2I_reg( eRegI dst, eRegL src ) %{ | |
| 12269 match(Set dst (ConvL2I src)); | |
| 12270 effect( DEF dst, USE src ); | |
| 12271 format %{ "MOV $dst,$src.lo" %} | |
| 12272 ins_encode(enc_CopyL_Lo(dst,src)); | |
| 12273 ins_pipe( ialu_reg_reg ); | |
| 12274 %} | |
| 12275 | |
| 12276 | |
| 12277 instruct MoveF2I_stack_reg(eRegI dst, stackSlotF src) %{ | |
| 12278 match(Set dst (MoveF2I src)); | |
| 12279 effect( DEF dst, USE src ); | |
| 12280 ins_cost(100); | |
| 12281 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %} | |
| 12282 opcode(0x8B); | |
| 12283 ins_encode( OpcP, RegMem(dst,src)); | |
| 12284 ins_pipe( ialu_reg_mem ); | |
| 12285 %} | |
| 12286 | |
| 12287 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ | |
| 12288 predicate(UseSSE==0); | |
| 12289 match(Set dst (MoveF2I src)); | |
| 12290 effect( DEF dst, USE src ); | |
| 12291 | |
| 12292 ins_cost(125); | |
| 12293 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %} | |
| 12294 ins_encode( Pop_Mem_Reg_F(dst, src) ); | |
| 12295 ins_pipe( fpu_mem_reg ); | |
| 12296 %} | |
| 12297 | |
| 12298 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regX src) %{ | |
| 12299 predicate(UseSSE>=1); | |
| 12300 match(Set dst (MoveF2I src)); | |
| 12301 effect( DEF dst, USE src ); | |
| 12302 | |
| 12303 ins_cost(95); | |
| 12304 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %} | |
| 12305 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, dst)); | |
| 12306 ins_pipe( pipe_slow ); | |
| 12307 %} | |
| 12308 | |
| 12309 instruct MoveF2I_reg_reg_sse(eRegI dst, regX src) %{ | |
| 12310 predicate(UseSSE>=2); | |
| 12311 match(Set dst (MoveF2I src)); | |
| 12312 effect( DEF dst, USE src ); | |
| 12313 ins_cost(85); | |
| 12314 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %} | |
| 12315 ins_encode( MovX2I_reg(dst, src)); | |
| 12316 ins_pipe( pipe_slow ); | |
| 12317 %} | |
| 12318 | |
| 12319 instruct MoveI2F_reg_stack(stackSlotF dst, eRegI src) %{ | |
| 12320 match(Set dst (MoveI2F src)); | |
| 12321 effect( DEF dst, USE src ); | |
| 12322 | |
| 12323 ins_cost(100); | |
| 12324 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %} | |
| 12325 opcode(0x89); | |
| 12326 ins_encode( OpcPRegSS( dst, src ) ); | |
| 12327 ins_pipe( ialu_mem_reg ); | |
| 12328 %} | |
| 12329 | |
| 12330 | |
| 12331 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ | |
| 12332 predicate(UseSSE==0); | |
| 12333 match(Set dst (MoveI2F src)); | |
| 12334 effect(DEF dst, USE src); | |
| 12335 | |
| 12336 ins_cost(125); | |
| 12337 format %{ "FLD_S $src\n\t" | |
| 12338 "FSTP $dst\t# MoveI2F_stack_reg" %} | |
| 12339 opcode(0xD9); /* D9 /0, FLD m32real */ | |
| 12340 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
| 12341 Pop_Reg_F(dst) ); | |
| 12342 ins_pipe( fpu_reg_mem ); | |
| 12343 %} | |
| 12344 | |
| 12345 instruct MoveI2F_stack_reg_sse(regX dst, stackSlotI src) %{ | |
| 12346 predicate(UseSSE>=1); | |
| 12347 match(Set dst (MoveI2F src)); | |
| 12348 effect( DEF dst, USE src ); | |
| 12349 | |
| 12350 ins_cost(95); | |
| 12351 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %} | |
| 12352 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,src)); | |
| 12353 ins_pipe( pipe_slow ); | |
| 12354 %} | |
| 12355 | |
| 12356 instruct MoveI2F_reg_reg_sse(regX dst, eRegI src) %{ | |
| 12357 predicate(UseSSE>=2); | |
| 12358 match(Set dst (MoveI2F src)); | |
| 12359 effect( DEF dst, USE src ); | |
| 12360 | |
| 12361 ins_cost(85); | |
| 12362 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %} | |
| 12363 ins_encode( MovI2X_reg(dst, src) ); | |
| 12364 ins_pipe( pipe_slow ); | |
| 12365 %} | |
| 12366 | |
| 12367 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{ | |
| 12368 match(Set dst (MoveD2L src)); | |
| 12369 effect(DEF dst, USE src); | |
| 12370 | |
| 12371 ins_cost(250); | |
| 12372 format %{ "MOV $dst.lo,$src\n\t" | |
| 12373 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %} | |
| 12374 opcode(0x8B, 0x8B); | |
| 12375 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src)); | |
| 12376 ins_pipe( ialu_mem_long_reg ); | |
| 12377 %} | |
| 12378 | |
| 12379 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ | |
| 12380 predicate(UseSSE<=1); | |
| 12381 match(Set dst (MoveD2L src)); | |
| 12382 effect(DEF dst, USE src); | |
| 12383 | |
| 12384 ins_cost(125); | |
| 12385 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %} | |
| 12386 ins_encode( Pop_Mem_Reg_D(dst, src) ); | |
| 12387 ins_pipe( fpu_mem_reg ); | |
| 12388 %} | |
| 12389 | |
| 12390 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regXD src) %{ | |
| 12391 predicate(UseSSE>=2); | |
| 12392 match(Set dst (MoveD2L src)); | |
| 12393 effect(DEF dst, USE src); | |
| 12394 ins_cost(95); | |
| 12395 | |
| 12396 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %} | |
| 12397 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src,dst)); | |
| 12398 ins_pipe( pipe_slow ); | |
| 12399 %} | |
| 12400 | |
| 12401 instruct MoveD2L_reg_reg_sse(eRegL dst, regXD src, regXD tmp) %{ | |
| 12402 predicate(UseSSE>=2); | |
| 12403 match(Set dst (MoveD2L src)); | |
| 12404 effect(DEF dst, USE src, TEMP tmp); | |
| 12405 ins_cost(85); | |
| 12406 format %{ "MOVD $dst.lo,$src\n\t" | |
| 12407 "PSHUFLW $tmp,$src,0x4E\n\t" | |
| 12408 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %} | |
| 12409 ins_encode( MovXD2L_reg(dst, src, tmp) ); | |
| 12410 ins_pipe( pipe_slow ); | |
| 12411 %} | |
| 12412 | |
| 12413 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{ | |
| 12414 match(Set dst (MoveL2D src)); | |
| 12415 effect(DEF dst, USE src); | |
| 12416 | |
| 12417 ins_cost(200); | |
| 12418 format %{ "MOV $dst,$src.lo\n\t" | |
| 12419 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %} | |
| 12420 opcode(0x89, 0x89); | |
| 12421 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) ); | |
| 12422 ins_pipe( ialu_mem_long_reg ); | |
| 12423 %} | |
| 12424 | |
| 12425 | |
| 12426 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ | |
| 12427 predicate(UseSSE<=1); | |
| 12428 match(Set dst (MoveL2D src)); | |
| 12429 effect(DEF dst, USE src); | |
| 12430 ins_cost(125); | |
| 12431 | |
| 12432 format %{ "FLD_D $src\n\t" | |
| 12433 "FSTP $dst\t# MoveL2D_stack_reg" %} | |
| 12434 opcode(0xDD); /* DD /0, FLD m64real */ | |
| 12435 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
| 12436 Pop_Reg_D(dst) ); | |
| 12437 ins_pipe( fpu_reg_mem ); | |
| 12438 %} | |
| 12439 | |
| 12440 | |
| 12441 instruct MoveL2D_stack_reg_sse(regXD dst, stackSlotL src) %{ | |
| 12442 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper); | |
| 12443 match(Set dst (MoveL2D src)); | |
| 12444 effect(DEF dst, USE src); | |
| 12445 | |
| 12446 ins_cost(95); | |
| 12447 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %} | |
| 12448 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,src)); | |
| 12449 ins_pipe( pipe_slow ); | |
| 12450 %} | |
| 12451 | |
| 12452 instruct MoveL2D_stack_reg_sse_partial(regXD dst, stackSlotL src) %{ | |
| 12453 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper); | |
| 12454 match(Set dst (MoveL2D src)); | |
| 12455 effect(DEF dst, USE src); | |
| 12456 | |
| 12457 ins_cost(95); | |
| 12458 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %} | |
| 12459 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,src)); | |
| 12460 ins_pipe( pipe_slow ); | |
| 12461 %} | |
| 12462 | |
| 12463 instruct MoveL2D_reg_reg_sse(regXD dst, eRegL src, regXD tmp) %{ | |
| 12464 predicate(UseSSE>=2); | |
| 12465 match(Set dst (MoveL2D src)); | |
| 12466 effect(TEMP dst, USE src, TEMP tmp); | |
| 12467 ins_cost(85); | |
| 12468 format %{ "MOVD $dst,$src.lo\n\t" | |
| 12469 "MOVD $tmp,$src.hi\n\t" | |
| 12470 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %} | |
| 12471 ins_encode( MovL2XD_reg(dst, src, tmp) ); | |
| 12472 ins_pipe( pipe_slow ); | |
| 12473 %} | |
| 12474 | |
| 12475 // Replicate scalar to packed byte (1 byte) values in xmm | |
| 12476 instruct Repl8B_reg(regXD dst, regXD src) %{ | |
| 12477 predicate(UseSSE>=2); | |
| 12478 match(Set dst (Replicate8B src)); | |
| 12479 format %{ "MOVDQA $dst,$src\n\t" | |
| 12480 "PUNPCKLBW $dst,$dst\n\t" | |
| 12481 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %} | |
| 12482 ins_encode( pshufd_8x8(dst, src)); | |
| 12483 ins_pipe( pipe_slow ); | |
| 12484 %} | |
| 12485 | |
| 12486 // Replicate scalar to packed byte (1 byte) values in xmm | |
| 12487 instruct Repl8B_eRegI(regXD dst, eRegI src) %{ | |
| 12488 predicate(UseSSE>=2); | |
| 12489 match(Set dst (Replicate8B src)); | |
| 12490 format %{ "MOVD $dst,$src\n\t" | |
| 12491 "PUNPCKLBW $dst,$dst\n\t" | |
| 12492 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %} | |
| 12493 ins_encode( mov_i2x(dst, src), pshufd_8x8(dst, dst)); | |
| 12494 ins_pipe( pipe_slow ); | |
| 12495 %} | |
| 12496 | |
| 12497 // Replicate scalar zero to packed byte (1 byte) values in xmm | |
| 12498 instruct Repl8B_immI0(regXD dst, immI0 zero) %{ | |
| 12499 predicate(UseSSE>=2); | |
| 12500 match(Set dst (Replicate8B zero)); | |
| 12501 format %{ "PXOR $dst,$dst\t! replicate8B" %} | |
| 12502 ins_encode( pxor(dst, dst)); | |
| 12503 ins_pipe( fpu_reg_reg ); | |
| 12504 %} | |
| 12505 | |
| 12506 // Replicate scalar to packed shore (2 byte) values in xmm | |
| 12507 instruct Repl4S_reg(regXD dst, regXD src) %{ | |
| 12508 predicate(UseSSE>=2); | |
| 12509 match(Set dst (Replicate4S src)); | |
| 12510 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %} | |
| 12511 ins_encode( pshufd_4x16(dst, src)); | |
| 12512 ins_pipe( fpu_reg_reg ); | |
| 12513 %} | |
| 12514 | |
| 12515 // Replicate scalar to packed shore (2 byte) values in xmm | |
| 12516 instruct Repl4S_eRegI(regXD dst, eRegI src) %{ | |
| 12517 predicate(UseSSE>=2); | |
| 12518 match(Set dst (Replicate4S src)); | |
| 12519 format %{ "MOVD $dst,$src\n\t" | |
| 12520 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %} | |
| 12521 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst)); | |
| 12522 ins_pipe( fpu_reg_reg ); | |
| 12523 %} | |
| 12524 | |
| 12525 // Replicate scalar zero to packed short (2 byte) values in xmm | |
| 12526 instruct Repl4S_immI0(regXD dst, immI0 zero) %{ | |
| 12527 predicate(UseSSE>=2); | |
| 12528 match(Set dst (Replicate4S zero)); | |
| 12529 format %{ "PXOR $dst,$dst\t! replicate4S" %} | |
| 12530 ins_encode( pxor(dst, dst)); | |
| 12531 ins_pipe( fpu_reg_reg ); | |
| 12532 %} | |
| 12533 | |
| 12534 // Replicate scalar to packed char (2 byte) values in xmm | |
| 12535 instruct Repl4C_reg(regXD dst, regXD src) %{ | |
| 12536 predicate(UseSSE>=2); | |
| 12537 match(Set dst (Replicate4C src)); | |
| 12538 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %} | |
| 12539 ins_encode( pshufd_4x16(dst, src)); | |
| 12540 ins_pipe( fpu_reg_reg ); | |
| 12541 %} | |
| 12542 | |
| 12543 // Replicate scalar to packed char (2 byte) values in xmm | |
| 12544 instruct Repl4C_eRegI(regXD dst, eRegI src) %{ | |
| 12545 predicate(UseSSE>=2); | |
| 12546 match(Set dst (Replicate4C src)); | |
| 12547 format %{ "MOVD $dst,$src\n\t" | |
| 12548 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %} | |
| 12549 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst)); | |
| 12550 ins_pipe( fpu_reg_reg ); | |
| 12551 %} | |
| 12552 | |
| 12553 // Replicate scalar zero to packed char (2 byte) values in xmm | |
| 12554 instruct Repl4C_immI0(regXD dst, immI0 zero) %{ | |
| 12555 predicate(UseSSE>=2); | |
| 12556 match(Set dst (Replicate4C zero)); | |
| 12557 format %{ "PXOR $dst,$dst\t! replicate4C" %} | |
| 12558 ins_encode( pxor(dst, dst)); | |
| 12559 ins_pipe( fpu_reg_reg ); | |
| 12560 %} | |
| 12561 | |
| 12562 // Replicate scalar to packed integer (4 byte) values in xmm | |
| 12563 instruct Repl2I_reg(regXD dst, regXD src) %{ | |
| 12564 predicate(UseSSE>=2); | |
| 12565 match(Set dst (Replicate2I src)); | |
| 12566 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %} | |
| 12567 ins_encode( pshufd(dst, src, 0x00)); | |
| 12568 ins_pipe( fpu_reg_reg ); | |
| 12569 %} | |
| 12570 | |
| 12571 // Replicate scalar to packed integer (4 byte) values in xmm | |
| 12572 instruct Repl2I_eRegI(regXD dst, eRegI src) %{ | |
| 12573 predicate(UseSSE>=2); | |
| 12574 match(Set dst (Replicate2I src)); | |
| 12575 format %{ "MOVD $dst,$src\n\t" | |
| 12576 "PSHUFD $dst,$dst,0x00\t! replicate2I" %} | |
| 12577 ins_encode( mov_i2x(dst, src), pshufd(dst, dst, 0x00)); | |
| 12578 ins_pipe( fpu_reg_reg ); | |
| 12579 %} | |
| 12580 | |
| 12581 // Replicate scalar zero to packed integer (2 byte) values in xmm | |
| 12582 instruct Repl2I_immI0(regXD dst, immI0 zero) %{ | |
| 12583 predicate(UseSSE>=2); | |
| 12584 match(Set dst (Replicate2I zero)); | |
| 12585 format %{ "PXOR $dst,$dst\t! replicate2I" %} | |
| 12586 ins_encode( pxor(dst, dst)); | |
| 12587 ins_pipe( fpu_reg_reg ); | |
| 12588 %} | |
| 12589 | |
| 12590 // Replicate scalar to packed single precision floating point values in xmm | |
| 12591 instruct Repl2F_reg(regXD dst, regXD src) %{ | |
| 12592 predicate(UseSSE>=2); | |
| 12593 match(Set dst (Replicate2F src)); | |
| 12594 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %} | |
| 12595 ins_encode( pshufd(dst, src, 0xe0)); | |
| 12596 ins_pipe( fpu_reg_reg ); | |
| 12597 %} | |
| 12598 | |
| 12599 // Replicate scalar to packed single precision floating point values in xmm | |
| 12600 instruct Repl2F_regX(regXD dst, regX src) %{ | |
| 12601 predicate(UseSSE>=2); | |
| 12602 match(Set dst (Replicate2F src)); | |
| 12603 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %} | |
| 12604 ins_encode( pshufd(dst, src, 0xe0)); | |
| 12605 ins_pipe( fpu_reg_reg ); | |
| 12606 %} | |
| 12607 | |
| 12608 // Replicate scalar to packed single precision floating point values in xmm | |
| 12609 instruct Repl2F_immXF0(regXD dst, immXF0 zero) %{ | |
| 12610 predicate(UseSSE>=2); | |
| 12611 match(Set dst (Replicate2F zero)); | |
| 12612 format %{ "PXOR $dst,$dst\t! replicate2F" %} | |
| 12613 ins_encode( pxor(dst, dst)); | |
| 12614 ins_pipe( fpu_reg_reg ); | |
| 12615 %} | |
| 12616 | |
| 12617 // ======================================================================= | |
| 12618 // fast clearing of an array | |
| 12619 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{ | |
| 12620 match(Set dummy (ClearArray cnt base)); | |
| 12621 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr); | |
| 12622 format %{ "SHL ECX,1\t# Convert doublewords to words\n\t" | |
| 12623 "XOR EAX,EAX\n\t" | |
| 12624 "REP STOS\t# store EAX into [EDI++] while ECX--" %} | |
| 12625 opcode(0,0x4); | |
| 12626 ins_encode( Opcode(0xD1), RegOpc(ECX), | |
| 12627 OpcRegReg(0x33,EAX,EAX), | |
| 12628 Opcode(0xF3), Opcode(0xAB) ); | |
| 12629 ins_pipe( pipe_slow ); | |
| 12630 %} | |
| 12631 | |
|
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12632 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eBXRegI cnt2, |
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12633 eAXRegI result, regXD tmp1, regXD tmp2, eFlagsReg cr) %{ |
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12634 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); |
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12635 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr); |
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12636 |
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12637 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1, $tmp2" %} |
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12638 ins_encode %{ |
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12639 __ string_compare($str1$$Register, $str2$$Register, |
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12640 $cnt1$$Register, $cnt2$$Register, $result$$Register, |
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12641 $tmp1$$XMMRegister, $tmp2$$XMMRegister); |
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12642 %} |
| 681 | 12643 ins_pipe( pipe_slow ); |
| 12644 %} | |
| 12645 | |
| 12646 // fast string equals | |
|
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12647 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result, |
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12648 regXD tmp1, regXD tmp2, eBXRegI tmp3, eFlagsReg cr) %{ |
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12649 match(Set result (StrEquals (Binary str1 str2) cnt)); |
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12650 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr); |
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12651 |
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12652 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %} |
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12653 ins_encode %{ |
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12654 __ char_arrays_equals(false, $str1$$Register, $str2$$Register, |
|
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12655 $cnt$$Register, $result$$Register, $tmp3$$Register, |
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12656 $tmp1$$XMMRegister, $tmp2$$XMMRegister); |
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12657 %} |
|
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12658 ins_pipe( pipe_slow ); |
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12659 %} |
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12660 |
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12661 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2, |
|
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12662 eBXRegI result, regXD tmp1, eCXRegI tmp2, eFlagsReg cr) %{ |
| 681 | 12663 predicate(UseSSE42Intrinsics); |
|
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12664 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2))); |
|
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12665 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp2, KILL cr); |
|
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12666 |
|
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12667 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp2, $tmp1" %} |
|
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12668 ins_encode %{ |
|
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12669 __ string_indexof($str1$$Register, $str2$$Register, |
|
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12670 $cnt1$$Register, $cnt2$$Register, $result$$Register, |
|
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12671 $tmp1$$XMMRegister, $tmp2$$Register); |
|
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12672 %} |
| 0 | 12673 ins_pipe( pipe_slow ); |
| 12674 %} | |
| 12675 | |
|
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12676 // fast array equals |
|
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12677 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result, |
|
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12678 regXD tmp1, regXD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr) |
|
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12679 %{ |
|
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12680 match(Set result (AryEq ary1 ary2)); |
| 681 | 12681 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr); |
|
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12682 //ins_cost(300); |
|
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12683 |
|
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12684 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %} |
|
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|
12685 ins_encode %{ |
|
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12686 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register, |
|
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12687 $tmp3$$Register, $result$$Register, $tmp4$$Register, |
|
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|
12688 $tmp1$$XMMRegister, $tmp2$$XMMRegister); |
|
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|
12689 %} |
|
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|
12690 ins_pipe( pipe_slow ); |
|
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|
12691 %} |
|
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|
12692 |
| 0 | 12693 //----------Control Flow Instructions------------------------------------------ |
| 12694 // Signed compare Instructions | |
| 12695 instruct compI_eReg(eFlagsReg cr, eRegI op1, eRegI op2) %{ | |
| 12696 match(Set cr (CmpI op1 op2)); | |
| 12697 effect( DEF cr, USE op1, USE op2 ); | |
| 12698 format %{ "CMP $op1,$op2" %} | |
| 12699 opcode(0x3B); /* Opcode 3B /r */ | |
| 12700 ins_encode( OpcP, RegReg( op1, op2) ); | |
| 12701 ins_pipe( ialu_cr_reg_reg ); | |
| 12702 %} | |
| 12703 | |
| 12704 instruct compI_eReg_imm(eFlagsReg cr, eRegI op1, immI op2) %{ | |
| 12705 match(Set cr (CmpI op1 op2)); | |
| 12706 effect( DEF cr, USE op1 ); | |
| 12707 format %{ "CMP $op1,$op2" %} | |
| 12708 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 12709 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */ | |
| 12710 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); | |
| 12711 ins_pipe( ialu_cr_reg_imm ); | |
| 12712 %} | |
| 12713 | |
| 12714 // Cisc-spilled version of cmpI_eReg | |
| 12715 instruct compI_eReg_mem(eFlagsReg cr, eRegI op1, memory op2) %{ | |
| 12716 match(Set cr (CmpI op1 (LoadI op2))); | |
| 12717 | |
| 12718 format %{ "CMP $op1,$op2" %} | |
| 12719 ins_cost(500); | |
| 12720 opcode(0x3B); /* Opcode 3B /r */ | |
| 12721 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 12722 ins_pipe( ialu_cr_reg_mem ); | |
| 12723 %} | |
| 12724 | |
| 12725 instruct testI_reg( eFlagsReg cr, eRegI src, immI0 zero ) %{ | |
| 12726 match(Set cr (CmpI src zero)); | |
| 12727 effect( DEF cr, USE src ); | |
| 12728 | |
| 12729 format %{ "TEST $src,$src" %} | |
| 12730 opcode(0x85); | |
| 12731 ins_encode( OpcP, RegReg( src, src ) ); | |
| 12732 ins_pipe( ialu_cr_reg_imm ); | |
| 12733 %} | |
| 12734 | |
| 12735 instruct testI_reg_imm( eFlagsReg cr, eRegI src, immI con, immI0 zero ) %{ | |
| 12736 match(Set cr (CmpI (AndI src con) zero)); | |
| 12737 | |
| 12738 format %{ "TEST $src,$con" %} | |
| 12739 opcode(0xF7,0x00); | |
| 12740 ins_encode( OpcP, RegOpc(src), Con32(con) ); | |
| 12741 ins_pipe( ialu_cr_reg_imm ); | |
| 12742 %} | |
| 12743 | |
| 12744 instruct testI_reg_mem( eFlagsReg cr, eRegI src, memory mem, immI0 zero ) %{ | |
| 12745 match(Set cr (CmpI (AndI src mem) zero)); | |
| 12746 | |
| 12747 format %{ "TEST $src,$mem" %} | |
| 12748 opcode(0x85); | |
| 12749 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 12750 ins_pipe( ialu_cr_reg_mem ); | |
| 12751 %} | |
| 12752 | |
| 12753 // Unsigned compare Instructions; really, same as signed except they | |
| 12754 // produce an eFlagsRegU instead of eFlagsReg. | |
| 12755 instruct compU_eReg(eFlagsRegU cr, eRegI op1, eRegI op2) %{ | |
| 12756 match(Set cr (CmpU op1 op2)); | |
| 12757 | |
| 12758 format %{ "CMPu $op1,$op2" %} | |
| 12759 opcode(0x3B); /* Opcode 3B /r */ | |
| 12760 ins_encode( OpcP, RegReg( op1, op2) ); | |
| 12761 ins_pipe( ialu_cr_reg_reg ); | |
| 12762 %} | |
| 12763 | |
| 12764 instruct compU_eReg_imm(eFlagsRegU cr, eRegI op1, immI op2) %{ | |
| 12765 match(Set cr (CmpU op1 op2)); | |
| 12766 | |
| 12767 format %{ "CMPu $op1,$op2" %} | |
| 12768 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 12769 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); | |
| 12770 ins_pipe( ialu_cr_reg_imm ); | |
| 12771 %} | |
| 12772 | |
| 12773 // // Cisc-spilled version of cmpU_eReg | |
| 12774 instruct compU_eReg_mem(eFlagsRegU cr, eRegI op1, memory op2) %{ | |
| 12775 match(Set cr (CmpU op1 (LoadI op2))); | |
| 12776 | |
| 12777 format %{ "CMPu $op1,$op2" %} | |
| 12778 ins_cost(500); | |
| 12779 opcode(0x3B); /* Opcode 3B /r */ | |
| 12780 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 12781 ins_pipe( ialu_cr_reg_mem ); | |
| 12782 %} | |
| 12783 | |
| 12784 // // Cisc-spilled version of cmpU_eReg | |
| 12785 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, eRegI op2) %{ | |
| 12786 // match(Set cr (CmpU (LoadI op1) op2)); | |
| 12787 // | |
| 12788 // format %{ "CMPu $op1,$op2" %} | |
| 12789 // ins_cost(500); | |
| 12790 // opcode(0x39); /* Opcode 39 /r */ | |
| 12791 // ins_encode( OpcP, RegMem( op1, op2) ); | |
| 12792 //%} | |
| 12793 | |
| 12794 instruct testU_reg( eFlagsRegU cr, eRegI src, immI0 zero ) %{ | |
| 12795 match(Set cr (CmpU src zero)); | |
| 12796 | |
| 12797 format %{ "TESTu $src,$src" %} | |
| 12798 opcode(0x85); | |
| 12799 ins_encode( OpcP, RegReg( src, src ) ); | |
| 12800 ins_pipe( ialu_cr_reg_imm ); | |
| 12801 %} | |
| 12802 | |
| 12803 // Unsigned pointer compare Instructions | |
| 12804 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{ | |
| 12805 match(Set cr (CmpP op1 op2)); | |
| 12806 | |
| 12807 format %{ "CMPu $op1,$op2" %} | |
| 12808 opcode(0x3B); /* Opcode 3B /r */ | |
| 12809 ins_encode( OpcP, RegReg( op1, op2) ); | |
| 12810 ins_pipe( ialu_cr_reg_reg ); | |
| 12811 %} | |
| 12812 | |
| 12813 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{ | |
| 12814 match(Set cr (CmpP op1 op2)); | |
| 12815 | |
| 12816 format %{ "CMPu $op1,$op2" %} | |
| 12817 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 12818 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); | |
| 12819 ins_pipe( ialu_cr_reg_imm ); | |
| 12820 %} | |
| 12821 | |
| 12822 // // Cisc-spilled version of cmpP_eReg | |
| 12823 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{ | |
| 12824 match(Set cr (CmpP op1 (LoadP op2))); | |
| 12825 | |
| 12826 format %{ "CMPu $op1,$op2" %} | |
| 12827 ins_cost(500); | |
| 12828 opcode(0x3B); /* Opcode 3B /r */ | |
| 12829 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 12830 ins_pipe( ialu_cr_reg_mem ); | |
| 12831 %} | |
| 12832 | |
| 12833 // // Cisc-spilled version of cmpP_eReg | |
| 12834 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{ | |
| 12835 // match(Set cr (CmpP (LoadP op1) op2)); | |
| 12836 // | |
| 12837 // format %{ "CMPu $op1,$op2" %} | |
| 12838 // ins_cost(500); | |
| 12839 // opcode(0x39); /* Opcode 39 /r */ | |
| 12840 // ins_encode( OpcP, RegMem( op1, op2) ); | |
| 12841 //%} | |
| 12842 | |
| 12843 // Compare raw pointer (used in out-of-heap check). | |
| 12844 // Only works because non-oop pointers must be raw pointers | |
| 12845 // and raw pointers have no anti-dependencies. | |
| 12846 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{ | |
| 12847 predicate( !n->in(2)->in(2)->bottom_type()->isa_oop_ptr() ); | |
| 12848 match(Set cr (CmpP op1 (LoadP op2))); | |
| 12849 | |
| 12850 format %{ "CMPu $op1,$op2" %} | |
| 12851 opcode(0x3B); /* Opcode 3B /r */ | |
| 12852 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 12853 ins_pipe( ialu_cr_reg_mem ); | |
| 12854 %} | |
| 12855 | |
| 12856 // | |
| 12857 // This will generate a signed flags result. This should be ok | |
| 12858 // since any compare to a zero should be eq/neq. | |
| 12859 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{ | |
| 12860 match(Set cr (CmpP src zero)); | |
| 12861 | |
| 12862 format %{ "TEST $src,$src" %} | |
| 12863 opcode(0x85); | |
| 12864 ins_encode( OpcP, RegReg( src, src ) ); | |
| 12865 ins_pipe( ialu_cr_reg_imm ); | |
| 12866 %} | |
| 12867 | |
| 12868 // Cisc-spilled version of testP_reg | |
| 12869 // This will generate a signed flags result. This should be ok | |
| 12870 // since any compare to a zero should be eq/neq. | |
| 12871 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{ | |
| 12872 match(Set cr (CmpP (LoadP op) zero)); | |
| 12873 | |
| 12874 format %{ "TEST $op,0xFFFFFFFF" %} | |
| 12875 ins_cost(500); | |
| 12876 opcode(0xF7); /* Opcode F7 /0 */ | |
| 12877 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) ); | |
| 12878 ins_pipe( ialu_cr_reg_imm ); | |
| 12879 %} | |
| 12880 | |
| 12881 // Yanked all unsigned pointer compare operations. | |
| 12882 // Pointer compares are done with CmpP which is already unsigned. | |
| 12883 | |
| 12884 //----------Max and Min-------------------------------------------------------- | |
| 12885 // Min Instructions | |
| 12886 //// | |
| 12887 // *** Min and Max using the conditional move are slower than the | |
| 12888 // *** branch version on a Pentium III. | |
| 12889 // // Conditional move for min | |
| 12890 //instruct cmovI_reg_lt( eRegI op2, eRegI op1, eFlagsReg cr ) %{ | |
| 12891 // effect( USE_DEF op2, USE op1, USE cr ); | |
| 12892 // format %{ "CMOVlt $op2,$op1\t! min" %} | |
| 12893 // opcode(0x4C,0x0F); | |
| 12894 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) ); | |
| 12895 // ins_pipe( pipe_cmov_reg ); | |
| 12896 //%} | |
| 12897 // | |
| 12898 //// Min Register with Register (P6 version) | |
| 12899 //instruct minI_eReg_p6( eRegI op1, eRegI op2 ) %{ | |
| 12900 // predicate(VM_Version::supports_cmov() ); | |
| 12901 // match(Set op2 (MinI op1 op2)); | |
| 12902 // ins_cost(200); | |
| 12903 // expand %{ | |
| 12904 // eFlagsReg cr; | |
| 12905 // compI_eReg(cr,op1,op2); | |
| 12906 // cmovI_reg_lt(op2,op1,cr); | |
| 12907 // %} | |
| 12908 //%} | |
| 12909 | |
| 12910 // Min Register with Register (generic version) | |
| 12911 instruct minI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{ | |
| 12912 match(Set dst (MinI dst src)); | |
| 12913 effect(KILL flags); | |
| 12914 ins_cost(300); | |
| 12915 | |
| 12916 format %{ "MIN $dst,$src" %} | |
| 12917 opcode(0xCC); | |
| 12918 ins_encode( min_enc(dst,src) ); | |
| 12919 ins_pipe( pipe_slow ); | |
| 12920 %} | |
| 12921 | |
| 12922 // Max Register with Register | |
| 12923 // *** Min and Max using the conditional move are slower than the | |
| 12924 // *** branch version on a Pentium III. | |
| 12925 // // Conditional move for max | |
| 12926 //instruct cmovI_reg_gt( eRegI op2, eRegI op1, eFlagsReg cr ) %{ | |
| 12927 // effect( USE_DEF op2, USE op1, USE cr ); | |
| 12928 // format %{ "CMOVgt $op2,$op1\t! max" %} | |
| 12929 // opcode(0x4F,0x0F); | |
| 12930 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) ); | |
| 12931 // ins_pipe( pipe_cmov_reg ); | |
| 12932 //%} | |
| 12933 // | |
| 12934 // // Max Register with Register (P6 version) | |
| 12935 //instruct maxI_eReg_p6( eRegI op1, eRegI op2 ) %{ | |
| 12936 // predicate(VM_Version::supports_cmov() ); | |
| 12937 // match(Set op2 (MaxI op1 op2)); | |
| 12938 // ins_cost(200); | |
| 12939 // expand %{ | |
| 12940 // eFlagsReg cr; | |
| 12941 // compI_eReg(cr,op1,op2); | |
| 12942 // cmovI_reg_gt(op2,op1,cr); | |
| 12943 // %} | |
| 12944 //%} | |
| 12945 | |
| 12946 // Max Register with Register (generic version) | |
| 12947 instruct maxI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{ | |
| 12948 match(Set dst (MaxI dst src)); | |
| 12949 effect(KILL flags); | |
| 12950 ins_cost(300); | |
| 12951 | |
| 12952 format %{ "MAX $dst,$src" %} | |
| 12953 opcode(0xCC); | |
| 12954 ins_encode( max_enc(dst,src) ); | |
| 12955 ins_pipe( pipe_slow ); | |
| 12956 %} | |
| 12957 | |
| 12958 // ============================================================================ | |
| 12959 // Branch Instructions | |
| 12960 // Jump Table | |
| 12961 instruct jumpXtnd(eRegI switch_val) %{ | |
| 12962 match(Jump switch_val); | |
| 12963 ins_cost(350); | |
| 2008 | 12964 format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %} |
| 12965 ins_encode %{ | |
| 0 | 12966 // Jump to Address(table_base + switch_reg) |
| 12967 Address index(noreg, $switch_val$$Register, Address::times_1); | |
| 2008 | 12968 __ jump(ArrayAddress($constantaddress, index)); |
| 0 | 12969 %} |
| 12970 ins_pc_relative(1); | |
| 12971 ins_pipe(pipe_jmp); | |
| 12972 %} | |
| 12973 | |
| 12974 // Jump Direct - Label defines a relative address from JMP+1 | |
| 12975 instruct jmpDir(label labl) %{ | |
| 12976 match(Goto); | |
| 12977 effect(USE labl); | |
| 12978 | |
| 12979 ins_cost(300); | |
| 12980 format %{ "JMP $labl" %} | |
| 12981 size(5); | |
| 12982 opcode(0xE9); | |
| 12983 ins_encode( OpcP, Lbl( labl ) ); | |
| 12984 ins_pipe( pipe_jmp ); | |
| 12985 ins_pc_relative(1); | |
| 12986 %} | |
| 12987 | |
| 12988 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12989 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 12990 match(If cop cr); | |
| 12991 effect(USE labl); | |
| 12992 | |
| 12993 ins_cost(300); | |
| 12994 format %{ "J$cop $labl" %} | |
| 12995 size(6); | |
| 12996 opcode(0x0F, 0x80); | |
| 12997 ins_encode( Jcc( cop, labl) ); | |
| 12998 ins_pipe( pipe_jcc ); | |
| 12999 ins_pc_relative(1); | |
| 13000 %} | |
| 13001 | |
| 13002 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 13003 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 13004 match(CountedLoopEnd cop cr); | |
| 13005 effect(USE labl); | |
| 13006 | |
| 13007 ins_cost(300); | |
| 13008 format %{ "J$cop $labl\t# Loop end" %} | |
| 13009 size(6); | |
| 13010 opcode(0x0F, 0x80); | |
| 13011 ins_encode( Jcc( cop, labl) ); | |
| 13012 ins_pipe( pipe_jcc ); | |
| 13013 ins_pc_relative(1); | |
| 13014 %} | |
| 13015 | |
| 13016 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 13017 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 13018 match(CountedLoopEnd cop cmp); | |
| 13019 effect(USE labl); | |
| 13020 | |
| 13021 ins_cost(300); | |
| 13022 format %{ "J$cop,u $labl\t# Loop end" %} | |
| 13023 size(6); | |
| 13024 opcode(0x0F, 0x80); | |
| 13025 ins_encode( Jcc( cop, labl) ); | |
| 13026 ins_pipe( pipe_jcc ); | |
| 13027 ins_pc_relative(1); | |
| 13028 %} | |
| 13029 | |
|
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13030 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
|
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|
13031 match(CountedLoopEnd cop cmp); |
|
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diff
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|
13032 effect(USE labl); |
|
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|
13033 |
|
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|
13034 ins_cost(200); |
|
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|
13035 format %{ "J$cop,u $labl\t# Loop end" %} |
|
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|
13036 size(6); |
|
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|
13037 opcode(0x0F, 0x80); |
|
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|
13038 ins_encode( Jcc( cop, labl) ); |
|
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|
13039 ins_pipe( pipe_jcc ); |
|
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|
13040 ins_pc_relative(1); |
|
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|
13041 %} |
|
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|
13042 |
| 0 | 13043 // Jump Direct Conditional - using unsigned comparison |
| 13044 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 13045 match(If cop cmp); | |
| 13046 effect(USE labl); | |
| 13047 | |
| 13048 ins_cost(300); | |
| 13049 format %{ "J$cop,u $labl" %} | |
| 13050 size(6); | |
| 13051 opcode(0x0F, 0x80); | |
|
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|
13052 ins_encode(Jcc(cop, labl)); |
|
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|
13053 ins_pipe(pipe_jcc); |
|
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|
13054 ins_pc_relative(1); |
|
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|
13055 %} |
|
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|
13056 |
|
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|
13057 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
|
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|
13058 match(If cop cmp); |
|
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|
13059 effect(USE labl); |
|
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|
13060 |
|
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|
13061 ins_cost(200); |
|
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|
13062 format %{ "J$cop,u $labl" %} |
|
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|
13063 size(6); |
|
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|
13064 opcode(0x0F, 0x80); |
|
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|
13065 ins_encode(Jcc(cop, labl)); |
|
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|
13066 ins_pipe(pipe_jcc); |
|
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|
13067 ins_pc_relative(1); |
|
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|
13068 %} |
|
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|
13069 |
|
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|
13070 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{ |
|
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|
13071 match(If cop cmp); |
|
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|
13072 effect(USE labl); |
|
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|
13073 |
|
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|
13074 ins_cost(200); |
|
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|
13075 format %{ $$template |
|
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|
13076 if ($cop$$cmpcode == Assembler::notEqual) { |
|
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|
13077 $$emit$$"JP,u $labl\n\t" |
|
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|
13078 $$emit$$"J$cop,u $labl" |
|
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|
13079 } else { |
|
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|
13080 $$emit$$"JP,u done\n\t" |
|
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|
13081 $$emit$$"J$cop,u $labl\n\t" |
|
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|
13082 $$emit$$"done:" |
|
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|
13083 } |
|
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|
13084 %} |
|
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|
13085 size(12); |
|
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changeset
|
13086 opcode(0x0F, 0x80); |
|
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|
13087 ins_encode %{ |
|
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|
13088 Label* l = $labl$$label; |
|
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|
13089 $$$emit8$primary; |
|
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|
13090 emit_cc(cbuf, $secondary, Assembler::parity); |
|
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|
13091 int parity_disp = -1; |
|
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|
13092 bool ok = false; |
|
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|
13093 if ($cop$$cmpcode == Assembler::notEqual) { |
|
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|
13094 // the two jumps 6 bytes apart so the jump distances are too |
| 1748 | 13095 parity_disp = l ? (l->loc_pos() - (cbuf.insts_size() + 4)) : 0; |
|
415
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|
13096 } else if ($cop$$cmpcode == Assembler::equal) { |
|
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|
13097 parity_disp = 6; |
|
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|
13098 ok = true; |
|
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|
13099 } else { |
|
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changeset
|
13100 ShouldNotReachHere(); |
|
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|
13101 } |
|
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|
13102 emit_d32(cbuf, parity_disp); |
|
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|
13103 $$$emit8$primary; |
|
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|
13104 emit_cc(cbuf, $secondary, $cop$$cmpcode); |
| 1748 | 13105 int disp = l ? (l->loc_pos() - (cbuf.insts_size() + 4)) : 0; |
|
415
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|
13106 emit_d32(cbuf, disp); |
|
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|
13107 %} |
|
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|
13108 ins_pipe(pipe_jcc); |
| 0 | 13109 ins_pc_relative(1); |
| 13110 %} | |
| 13111 | |
| 13112 // ============================================================================ | |
| 13113 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass | |
| 13114 // array for an instance of the superklass. Set a hidden internal cache on a | |
| 13115 // hit (cache is checked with exposed code in gen_subtype_check()). Return | |
| 13116 // NZ for a miss or zero for a hit. The encoding ALSO sets flags. | |
| 13117 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{ | |
| 13118 match(Set result (PartialSubtypeCheck sub super)); | |
| 13119 effect( KILL rcx, KILL cr ); | |
| 13120 | |
| 13121 ins_cost(1100); // slightly larger than the next version | |
|
644
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|
13122 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t" |
| 0 | 13123 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t" |
| 13124 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t" | |
| 13125 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t" | |
| 13126 "JNE,s miss\t\t# Missed: EDI not-zero\n\t" | |
| 13127 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t" | |
| 13128 "XOR $result,$result\t\t Hit: EDI zero\n\t" | |
| 13129 "miss:\t" %} | |
| 13130 | |
| 13131 opcode(0x1); // Force a XOR of EDI | |
| 13132 ins_encode( enc_PartialSubtypeCheck() ); | |
| 13133 ins_pipe( pipe_slow ); | |
| 13134 %} | |
| 13135 | |
| 13136 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{ | |
| 13137 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero)); | |
| 13138 effect( KILL rcx, KILL result ); | |
| 13139 | |
| 13140 ins_cost(1000); | |
|
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|
13141 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t" |
| 0 | 13142 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t" |
| 13143 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t" | |
| 13144 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t" | |
| 13145 "JNE,s miss\t\t# Missed: flags NZ\n\t" | |
| 13146 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t" | |
| 13147 "miss:\t" %} | |
| 13148 | |
| 13149 opcode(0x0); // No need to XOR EDI | |
| 13150 ins_encode( enc_PartialSubtypeCheck() ); | |
| 13151 ins_pipe( pipe_slow ); | |
| 13152 %} | |
| 13153 | |
| 13154 // ============================================================================ | |
| 13155 // Branch Instructions -- short offset versions | |
| 13156 // | |
| 13157 // These instructions are used to replace jumps of a long offset (the default | |
| 13158 // match) with jumps of a shorter offset. These instructions are all tagged | |
| 13159 // with the ins_short_branch attribute, which causes the ADLC to suppress the | |
| 13160 // match rules in general matching. Instead, the ADLC generates a conversion | |
| 13161 // method in the MachNode which can be used to do in-place replacement of the | |
| 13162 // long variant with the shorter variant. The compiler will determine if a | |
| 13163 // branch can be taken by the is_short_branch_offset() predicate in the machine | |
| 13164 // specific code section of the file. | |
| 13165 | |
| 13166 // Jump Direct - Label defines a relative address from JMP+1 | |
| 13167 instruct jmpDir_short(label labl) %{ | |
| 13168 match(Goto); | |
| 13169 effect(USE labl); | |
| 13170 | |
| 13171 ins_cost(300); | |
| 13172 format %{ "JMP,s $labl" %} | |
| 13173 size(2); | |
| 13174 opcode(0xEB); | |
| 13175 ins_encode( OpcP, LblShort( labl ) ); | |
| 13176 ins_pipe( pipe_jmp ); | |
| 13177 ins_pc_relative(1); | |
| 13178 ins_short_branch(1); | |
| 13179 %} | |
| 13180 | |
| 13181 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 13182 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 13183 match(If cop cr); | |
| 13184 effect(USE labl); | |
| 13185 | |
| 13186 ins_cost(300); | |
| 13187 format %{ "J$cop,s $labl" %} | |
| 13188 size(2); | |
| 13189 opcode(0x70); | |
| 13190 ins_encode( JccShort( cop, labl) ); | |
| 13191 ins_pipe( pipe_jcc ); | |
| 13192 ins_pc_relative(1); | |
| 13193 ins_short_branch(1); | |
| 13194 %} | |
| 13195 | |
| 13196 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 13197 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 13198 match(CountedLoopEnd cop cr); | |
| 13199 effect(USE labl); | |
| 13200 | |
| 13201 ins_cost(300); | |
|
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|
13202 format %{ "J$cop,s $labl\t# Loop end" %} |
| 0 | 13203 size(2); |
| 13204 opcode(0x70); | |
| 13205 ins_encode( JccShort( cop, labl) ); | |
| 13206 ins_pipe( pipe_jcc ); | |
| 13207 ins_pc_relative(1); | |
| 13208 ins_short_branch(1); | |
| 13209 %} | |
| 13210 | |
| 13211 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 13212 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 13213 match(CountedLoopEnd cop cmp); | |
| 13214 effect(USE labl); | |
| 13215 | |
| 13216 ins_cost(300); | |
|
415
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|
13217 format %{ "J$cop,us $labl\t# Loop end" %} |
|
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|
13218 size(2); |
|
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changeset
|
13219 opcode(0x70); |
|
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|
13220 ins_encode( JccShort( cop, labl) ); |
|
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|
13221 ins_pipe( pipe_jcc ); |
|
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|
13222 ins_pc_relative(1); |
|
4d9884b01ba6
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|
13223 ins_short_branch(1); |
|
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|
13224 %} |
|
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changeset
|
13225 |
|
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changeset
|
13226 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
|
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|
13227 match(CountedLoopEnd cop cmp); |
|
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|
13228 effect(USE labl); |
|
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|
13229 |
|
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changeset
|
13230 ins_cost(300); |
|
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|
13231 format %{ "J$cop,us $labl\t# Loop end" %} |
| 0 | 13232 size(2); |
| 13233 opcode(0x70); | |
| 13234 ins_encode( JccShort( cop, labl) ); | |
| 13235 ins_pipe( pipe_jcc ); | |
| 13236 ins_pc_relative(1); | |
| 13237 ins_short_branch(1); | |
| 13238 %} | |
| 13239 | |
| 13240 // Jump Direct Conditional - using unsigned comparison | |
| 13241 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 13242 match(If cop cmp); | |
| 13243 effect(USE labl); | |
| 13244 | |
| 13245 ins_cost(300); | |
| 13246 format %{ "J$cop,us $labl" %} | |
| 13247 size(2); | |
| 13248 opcode(0x70); | |
| 13249 ins_encode( JccShort( cop, labl) ); | |
| 13250 ins_pipe( pipe_jcc ); | |
| 13251 ins_pc_relative(1); | |
| 13252 ins_short_branch(1); | |
| 13253 %} | |
| 13254 | |
|
415
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changeset
|
13255 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
|
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|
13256 match(If cop cmp); |
|
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|
13257 effect(USE labl); |
|
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diff
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|
13258 |
|
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diff
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|
13259 ins_cost(300); |
|
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|
13260 format %{ "J$cop,us $labl" %} |
|
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parents:
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diff
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|
13261 size(2); |
|
4d9884b01ba6
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parents:
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|
13262 opcode(0x70); |
|
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|
13263 ins_encode( JccShort( cop, labl) ); |
|
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|
13264 ins_pipe( pipe_jcc ); |
|
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|
13265 ins_pc_relative(1); |
|
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|
13266 ins_short_branch(1); |
|
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|
13267 %} |
|
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|
13268 |
|
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never
parents:
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diff
changeset
|
13269 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{ |
|
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|
13270 match(If cop cmp); |
|
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|
13271 effect(USE labl); |
|
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|
13272 |
|
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|
13273 ins_cost(300); |
|
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diff
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|
13274 format %{ $$template |
|
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|
13275 if ($cop$$cmpcode == Assembler::notEqual) { |
|
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|
13276 $$emit$$"JP,u,s $labl\n\t" |
|
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|
13277 $$emit$$"J$cop,u,s $labl" |
|
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|
13278 } else { |
|
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|
13279 $$emit$$"JP,u,s done\n\t" |
|
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13280 $$emit$$"J$cop,u,s $labl\n\t" |
|
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|
13281 $$emit$$"done:" |
|
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|
13282 } |
|
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|
13283 %} |
|
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never
parents:
403
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changeset
|
13284 size(4); |
|
4d9884b01ba6
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never
parents:
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changeset
|
13285 opcode(0x70); |
|
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parents:
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changeset
|
13286 ins_encode %{ |
|
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changeset
|
13287 Label* l = $labl$$label; |
|
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|
13288 emit_cc(cbuf, $primary, Assembler::parity); |
|
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|
13289 int parity_disp = -1; |
|
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|
13290 if ($cop$$cmpcode == Assembler::notEqual) { |
| 1748 | 13291 parity_disp = l ? (l->loc_pos() - (cbuf.insts_size() + 1)) : 0; |
|
415
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|
13292 } else if ($cop$$cmpcode == Assembler::equal) { |
|
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|
13293 parity_disp = 2; |
|
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|
13294 } else { |
|
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changeset
|
13295 ShouldNotReachHere(); |
|
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|
13296 } |
|
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|
13297 emit_d8(cbuf, parity_disp); |
|
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|
13298 emit_cc(cbuf, $primary, $cop$$cmpcode); |
| 1748 | 13299 int disp = l ? (l->loc_pos() - (cbuf.insts_size() + 1)) : 0; |
|
415
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|
13300 emit_d8(cbuf, disp); |
|
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|
13301 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp"); |
|
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|
13302 assert(-128 <= parity_disp && parity_disp <= 127, "Displacement too large for short jmp"); |
|
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|
13303 %} |
|
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|
13304 ins_pipe(pipe_jcc); |
|
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|
13305 ins_pc_relative(1); |
|
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|
13306 ins_short_branch(1); |
|
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|
13307 %} |
|
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|
13308 |
| 0 | 13309 // ============================================================================ |
| 13310 // Long Compare | |
| 13311 // | |
| 13312 // Currently we hold longs in 2 registers. Comparing such values efficiently | |
| 13313 // is tricky. The flavor of compare used depends on whether we are testing | |
| 13314 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit. | |
| 13315 // The GE test is the negated LT test. The LE test can be had by commuting | |
| 13316 // the operands (yielding a GE test) and then negating; negate again for the | |
| 13317 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the | |
| 13318 // NE test is negated from that. | |
| 13319 | |
| 13320 // Due to a shortcoming in the ADLC, it mixes up expressions like: | |
| 13321 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the | |
| 13322 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections | |
| 13323 // are collapsed internally in the ADLC's dfa-gen code. The match for | |
| 13324 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the | |
| 13325 // foo match ends up with the wrong leaf. One fix is to not match both | |
| 13326 // reg-reg and reg-zero forms of long-compare. This is unfortunate because | |
| 13327 // both forms beat the trinary form of long-compare and both are very useful | |
| 13328 // on Intel which has so few registers. | |
| 13329 | |
| 13330 // Manifest a CmpL result in an integer register. Very painful. | |
| 13331 // This is the test to avoid. | |
| 13332 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{ | |
| 13333 match(Set dst (CmpL3 src1 src2)); | |
| 13334 effect( KILL flags ); | |
| 13335 ins_cost(1000); | |
| 13336 format %{ "XOR $dst,$dst\n\t" | |
| 13337 "CMP $src1.hi,$src2.hi\n\t" | |
| 13338 "JLT,s m_one\n\t" | |
| 13339 "JGT,s p_one\n\t" | |
| 13340 "CMP $src1.lo,$src2.lo\n\t" | |
| 13341 "JB,s m_one\n\t" | |
| 13342 "JEQ,s done\n" | |
| 13343 "p_one:\tINC $dst\n\t" | |
| 13344 "JMP,s done\n" | |
| 13345 "m_one:\tDEC $dst\n" | |
| 13346 "done:" %} | |
| 13347 ins_encode %{ | |
| 13348 Label p_one, m_one, done; | |
| 304 | 13349 __ xorptr($dst$$Register, $dst$$Register); |
| 0 | 13350 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register)); |
| 13351 __ jccb(Assembler::less, m_one); | |
| 13352 __ jccb(Assembler::greater, p_one); | |
| 13353 __ cmpl($src1$$Register, $src2$$Register); | |
| 13354 __ jccb(Assembler::below, m_one); | |
| 13355 __ jccb(Assembler::equal, done); | |
| 13356 __ bind(p_one); | |
| 304 | 13357 __ incrementl($dst$$Register); |
| 0 | 13358 __ jmpb(done); |
| 13359 __ bind(m_one); | |
| 304 | 13360 __ decrementl($dst$$Register); |
| 0 | 13361 __ bind(done); |
| 13362 %} | |
| 13363 ins_pipe( pipe_slow ); | |
| 13364 %} | |
| 13365 | |
| 13366 //====== | |
| 13367 // Manifest a CmpL result in the normal flags. Only good for LT or GE | |
| 13368 // compares. Can be used for LE or GT compares by reversing arguments. | |
| 13369 // NOT GOOD FOR EQ/NE tests. | |
| 13370 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{ | |
| 13371 match( Set flags (CmpL src zero )); | |
| 13372 ins_cost(100); | |
| 13373 format %{ "TEST $src.hi,$src.hi" %} | |
| 13374 opcode(0x85); | |
| 13375 ins_encode( OpcP, RegReg_Hi2( src, src ) ); | |
| 13376 ins_pipe( ialu_cr_reg_reg ); | |
| 13377 %} | |
| 13378 | |
| 13379 // Manifest a CmpL result in the normal flags. Only good for LT or GE | |
| 13380 // compares. Can be used for LE or GT compares by reversing arguments. | |
| 13381 // NOT GOOD FOR EQ/NE tests. | |
| 13382 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, eRegI tmp ) %{ | |
| 13383 match( Set flags (CmpL src1 src2 )); | |
| 13384 effect( TEMP tmp ); | |
| 13385 ins_cost(300); | |
| 13386 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t" | |
| 13387 "MOV $tmp,$src1.hi\n\t" | |
| 13388 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %} | |
| 13389 ins_encode( long_cmp_flags2( src1, src2, tmp ) ); | |
| 13390 ins_pipe( ialu_cr_reg_reg ); | |
| 13391 %} | |
| 13392 | |
| 13393 // Long compares reg < zero/req OR reg >= zero/req. | |
| 13394 // Just a wrapper for a normal branch, plus the predicate test. | |
| 13395 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{ | |
| 13396 match(If cmp flags); | |
| 13397 effect(USE labl); | |
| 13398 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); | |
| 13399 expand %{ | |
| 13400 jmpCon(cmp,flags,labl); // JLT or JGE... | |
| 13401 %} | |
| 13402 %} | |
| 13403 | |
| 13404 // Compare 2 longs and CMOVE longs. | |
| 13405 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{ | |
| 13406 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); | |
| 13407 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 13408 ins_cost(400); | |
| 13409 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 13410 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 13411 opcode(0x0F,0x40); | |
| 13412 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); | |
| 13413 ins_pipe( pipe_cmov_reg_long ); | |
| 13414 %} | |
| 13415 | |
| 13416 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{ | |
| 13417 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); | |
| 13418 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 13419 ins_cost(500); | |
| 13420 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 13421 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 13422 opcode(0x0F,0x40); | |
| 13423 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); | |
| 13424 ins_pipe( pipe_cmov_reg_long ); | |
| 13425 %} | |
| 13426 | |
| 13427 // Compare 2 longs and CMOVE ints. | |
| 13428 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, eRegI src) %{ | |
| 13429 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 13430 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); | |
| 13431 ins_cost(200); | |
| 13432 format %{ "CMOV$cmp $dst,$src" %} | |
| 13433 opcode(0x0F,0x40); | |
| 13434 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 13435 ins_pipe( pipe_cmov_reg ); | |
| 13436 %} | |
| 13437 | |
| 13438 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, memory src) %{ | |
| 13439 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 13440 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); | |
| 13441 ins_cost(250); | |
| 13442 format %{ "CMOV$cmp $dst,$src" %} | |
| 13443 opcode(0x0F,0x40); | |
| 13444 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); | |
| 13445 ins_pipe( pipe_cmov_mem ); | |
| 13446 %} | |
| 13447 | |
| 13448 // Compare 2 longs and CMOVE ints. | |
| 13449 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{ | |
| 13450 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 13451 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); | |
| 13452 ins_cost(200); | |
| 13453 format %{ "CMOV$cmp $dst,$src" %} | |
| 13454 opcode(0x0F,0x40); | |
| 13455 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 13456 ins_pipe( pipe_cmov_reg ); | |
| 13457 %} | |
| 13458 | |
| 13459 // Compare 2 longs and CMOVE doubles | |
| 13460 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{ | |
| 13461 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); | |
| 13462 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 13463 ins_cost(200); | |
| 13464 expand %{ | |
| 13465 fcmovD_regS(cmp,flags,dst,src); | |
| 13466 %} | |
| 13467 %} | |
| 13468 | |
| 13469 // Compare 2 longs and CMOVE doubles | |
| 13470 instruct cmovXDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regXD dst, regXD src) %{ | |
| 13471 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); | |
| 13472 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 13473 ins_cost(200); | |
| 13474 expand %{ | |
| 13475 fcmovXD_regS(cmp,flags,dst,src); | |
| 13476 %} | |
| 13477 %} | |
| 13478 | |
| 13479 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{ | |
| 13480 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); | |
| 13481 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); | |
| 13482 ins_cost(200); | |
| 13483 expand %{ | |
| 13484 fcmovF_regS(cmp,flags,dst,src); | |
| 13485 %} | |
| 13486 %} | |
| 13487 | |
| 13488 instruct cmovXX_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regX dst, regX src) %{ | |
| 13489 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); | |
| 13490 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); | |
| 13491 ins_cost(200); | |
| 13492 expand %{ | |
| 13493 fcmovX_regS(cmp,flags,dst,src); | |
| 13494 %} | |
| 13495 %} | |
| 13496 | |
| 13497 //====== | |
| 13498 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares. | |
| 13499 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, eRegI tmp ) %{ | |
| 13500 match( Set flags (CmpL src zero )); | |
| 13501 effect(TEMP tmp); | |
| 13502 ins_cost(200); | |
| 13503 format %{ "MOV $tmp,$src.lo\n\t" | |
| 13504 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %} | |
| 13505 ins_encode( long_cmp_flags0( src, tmp ) ); | |
| 13506 ins_pipe( ialu_reg_reg_long ); | |
| 13507 %} | |
| 13508 | |
| 13509 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares. | |
| 13510 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{ | |
| 13511 match( Set flags (CmpL src1 src2 )); | |
| 13512 ins_cost(200+300); | |
| 13513 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t" | |
| 13514 "JNE,s skip\n\t" | |
| 13515 "CMP $src1.hi,$src2.hi\n\t" | |
| 13516 "skip:\t" %} | |
| 13517 ins_encode( long_cmp_flags1( src1, src2 ) ); | |
| 13518 ins_pipe( ialu_cr_reg_reg ); | |
| 13519 %} | |
| 13520 | |
| 13521 // Long compare reg == zero/reg OR reg != zero/reg | |
| 13522 // Just a wrapper for a normal branch, plus the predicate test. | |
| 13523 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{ | |
| 13524 match(If cmp flags); | |
| 13525 effect(USE labl); | |
| 13526 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); | |
| 13527 expand %{ | |
| 13528 jmpCon(cmp,flags,labl); // JEQ or JNE... | |
| 13529 %} | |
| 13530 %} | |
| 13531 | |
| 13532 // Compare 2 longs and CMOVE longs. | |
| 13533 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{ | |
| 13534 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); | |
| 13535 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 13536 ins_cost(400); | |
| 13537 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 13538 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 13539 opcode(0x0F,0x40); | |
| 13540 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); | |
| 13541 ins_pipe( pipe_cmov_reg_long ); | |
| 13542 %} | |
| 13543 | |
| 13544 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{ | |
| 13545 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); | |
| 13546 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 13547 ins_cost(500); | |
| 13548 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 13549 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 13550 opcode(0x0F,0x40); | |
| 13551 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); | |
| 13552 ins_pipe( pipe_cmov_reg_long ); | |
| 13553 %} | |
| 13554 | |
| 13555 // Compare 2 longs and CMOVE ints. | |
| 13556 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, eRegI src) %{ | |
| 13557 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 13558 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); | |
| 13559 ins_cost(200); | |
| 13560 format %{ "CMOV$cmp $dst,$src" %} | |
| 13561 opcode(0x0F,0x40); | |
| 13562 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 13563 ins_pipe( pipe_cmov_reg ); | |
| 13564 %} | |
| 13565 | |
| 13566 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, memory src) %{ | |
| 13567 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 13568 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); | |
| 13569 ins_cost(250); | |
| 13570 format %{ "CMOV$cmp $dst,$src" %} | |
| 13571 opcode(0x0F,0x40); | |
| 13572 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); | |
| 13573 ins_pipe( pipe_cmov_mem ); | |
| 13574 %} | |
| 13575 | |
| 13576 // Compare 2 longs and CMOVE ints. | |
| 13577 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{ | |
| 13578 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 13579 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); | |
| 13580 ins_cost(200); | |
| 13581 format %{ "CMOV$cmp $dst,$src" %} | |
| 13582 opcode(0x0F,0x40); | |
| 13583 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 13584 ins_pipe( pipe_cmov_reg ); | |
| 13585 %} | |
| 13586 | |
| 13587 // Compare 2 longs and CMOVE doubles | |
| 13588 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{ | |
| 13589 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); | |
| 13590 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 13591 ins_cost(200); | |
| 13592 expand %{ | |
| 13593 fcmovD_regS(cmp,flags,dst,src); | |
| 13594 %} | |
| 13595 %} | |
| 13596 | |
| 13597 // Compare 2 longs and CMOVE doubles | |
| 13598 instruct cmovXDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regXD dst, regXD src) %{ | |
| 13599 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); | |
| 13600 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 13601 ins_cost(200); | |
| 13602 expand %{ | |
| 13603 fcmovXD_regS(cmp,flags,dst,src); | |
| 13604 %} | |
| 13605 %} | |
| 13606 | |
| 13607 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{ | |
| 13608 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); | |
| 13609 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); | |
| 13610 ins_cost(200); | |
| 13611 expand %{ | |
| 13612 fcmovF_regS(cmp,flags,dst,src); | |
| 13613 %} | |
| 13614 %} | |
| 13615 | |
| 13616 instruct cmovXX_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regX dst, regX src) %{ | |
| 13617 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); | |
| 13618 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); | |
| 13619 ins_cost(200); | |
| 13620 expand %{ | |
| 13621 fcmovX_regS(cmp,flags,dst,src); | |
| 13622 %} | |
| 13623 %} | |
| 13624 | |
| 13625 //====== | |
| 13626 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares. | |
| 13627 // Same as cmpL_reg_flags_LEGT except must negate src | |
| 13628 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, eRegI tmp ) %{ | |
| 13629 match( Set flags (CmpL src zero )); | |
| 13630 effect( TEMP tmp ); | |
| 13631 ins_cost(300); | |
| 13632 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t" | |
| 13633 "CMP $tmp,$src.lo\n\t" | |
| 13634 "SBB $tmp,$src.hi\n\t" %} | |
| 13635 ins_encode( long_cmp_flags3(src, tmp) ); | |
| 13636 ins_pipe( ialu_reg_reg_long ); | |
| 13637 %} | |
| 13638 | |
| 13639 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares. | |
| 13640 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands | |
| 13641 // requires a commuted test to get the same result. | |
| 13642 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, eRegI tmp ) %{ | |
| 13643 match( Set flags (CmpL src1 src2 )); | |
| 13644 effect( TEMP tmp ); | |
| 13645 ins_cost(300); | |
| 13646 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t" | |
| 13647 "MOV $tmp,$src2.hi\n\t" | |
| 13648 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %} | |
| 13649 ins_encode( long_cmp_flags2( src2, src1, tmp ) ); | |
| 13650 ins_pipe( ialu_cr_reg_reg ); | |
| 13651 %} | |
| 13652 | |
| 13653 // Long compares reg < zero/req OR reg >= zero/req. | |
| 13654 // Just a wrapper for a normal branch, plus the predicate test | |
| 13655 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{ | |
| 13656 match(If cmp flags); | |
| 13657 effect(USE labl); | |
| 13658 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le ); | |
| 13659 ins_cost(300); | |
| 13660 expand %{ | |
| 13661 jmpCon(cmp,flags,labl); // JGT or JLE... | |
| 13662 %} | |
| 13663 %} | |
| 13664 | |
| 13665 // Compare 2 longs and CMOVE longs. | |
| 13666 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{ | |
| 13667 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); | |
| 13668 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 13669 ins_cost(400); | |
| 13670 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 13671 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 13672 opcode(0x0F,0x40); | |
| 13673 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); | |
| 13674 ins_pipe( pipe_cmov_reg_long ); | |
| 13675 %} | |
| 13676 | |
| 13677 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{ | |
| 13678 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); | |
| 13679 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 13680 ins_cost(500); | |
| 13681 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 13682 "CMOV$cmp $dst.hi,$src.hi+4" %} | |
| 13683 opcode(0x0F,0x40); | |
| 13684 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); | |
| 13685 ins_pipe( pipe_cmov_reg_long ); | |
| 13686 %} | |
| 13687 | |
| 13688 // Compare 2 longs and CMOVE ints. | |
| 13689 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, eRegI src) %{ | |
| 13690 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 13691 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); | |
| 13692 ins_cost(200); | |
| 13693 format %{ "CMOV$cmp $dst,$src" %} | |
| 13694 opcode(0x0F,0x40); | |
| 13695 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 13696 ins_pipe( pipe_cmov_reg ); | |
| 13697 %} | |
| 13698 | |
| 13699 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, memory src) %{ | |
| 13700 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 13701 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); | |
| 13702 ins_cost(250); | |
| 13703 format %{ "CMOV$cmp $dst,$src" %} | |
| 13704 opcode(0x0F,0x40); | |
| 13705 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); | |
| 13706 ins_pipe( pipe_cmov_mem ); | |
| 13707 %} | |
| 13708 | |
| 13709 // Compare 2 longs and CMOVE ptrs. | |
| 13710 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{ | |
| 13711 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 13712 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); | |
| 13713 ins_cost(200); | |
| 13714 format %{ "CMOV$cmp $dst,$src" %} | |
| 13715 opcode(0x0F,0x40); | |
| 13716 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 13717 ins_pipe( pipe_cmov_reg ); | |
| 13718 %} | |
| 13719 | |
| 13720 // Compare 2 longs and CMOVE doubles | |
| 13721 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{ | |
| 13722 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); | |
| 13723 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 13724 ins_cost(200); | |
| 13725 expand %{ | |
| 13726 fcmovD_regS(cmp,flags,dst,src); | |
| 13727 %} | |
| 13728 %} | |
| 13729 | |
| 13730 // Compare 2 longs and CMOVE doubles | |
| 13731 instruct cmovXDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regXD dst, regXD src) %{ | |
| 13732 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); | |
| 13733 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 13734 ins_cost(200); | |
| 13735 expand %{ | |
| 13736 fcmovXD_regS(cmp,flags,dst,src); | |
| 13737 %} | |
| 13738 %} | |
| 13739 | |
| 13740 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{ | |
| 13741 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); | |
| 13742 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); | |
| 13743 ins_cost(200); | |
| 13744 expand %{ | |
| 13745 fcmovF_regS(cmp,flags,dst,src); | |
| 13746 %} | |
| 13747 %} | |
| 13748 | |
| 13749 | |
| 13750 instruct cmovXX_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regX dst, regX src) %{ | |
| 13751 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); | |
| 13752 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); | |
| 13753 ins_cost(200); | |
| 13754 expand %{ | |
| 13755 fcmovX_regS(cmp,flags,dst,src); | |
| 13756 %} | |
| 13757 %} | |
| 13758 | |
| 13759 | |
| 13760 // ============================================================================ | |
| 13761 // Procedure Call/Return Instructions | |
| 13762 // Call Java Static Instruction | |
| 13763 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 13764 // compute_padding() functions will have to be adjusted. | |
| 13765 instruct CallStaticJavaDirect(method meth) %{ | |
| 13766 match(CallStaticJava); | |
|
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13767 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke()); |
| 0 | 13768 effect(USE meth); |
| 13769 | |
| 13770 ins_cost(300); | |
| 13771 format %{ "CALL,static " %} | |
| 13772 opcode(0xE8); /* E8 cd */ | |
| 13773 ins_encode( pre_call_FPU, | |
| 13774 Java_Static_Call( meth ), | |
| 13775 call_epilog, | |
| 13776 post_call_FPU ); | |
| 13777 ins_pipe( pipe_slow ); | |
| 13778 ins_pc_relative(1); | |
| 13779 ins_alignment(4); | |
| 13780 %} | |
| 13781 | |
|
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13782 // Call Java Static Instruction (method handle version) |
|
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13783 // Note: If this code changes, the corresponding ret_addr_offset() and |
|
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13784 // compute_padding() functions will have to be adjusted. |
| 1567 | 13785 instruct CallStaticJavaHandle(method meth, eBPRegP ebp_mh_SP_save) %{ |
|
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13786 match(CallStaticJava); |
|
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13787 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke()); |
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13788 effect(USE meth); |
|
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13789 // EBP is saved by all callees (for interpreter stack correction). |
|
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13790 // We use it here for a similar purpose, in {preserve,restore}_SP. |
|
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13791 |
|
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13792 ins_cost(300); |
|
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13793 format %{ "CALL,static/MethodHandle " %} |
|
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13794 opcode(0xE8); /* E8 cd */ |
|
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13795 ins_encode( pre_call_FPU, |
|
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13796 preserve_SP, |
|
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13797 Java_Static_Call( meth ), |
|
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13798 restore_SP, |
|
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13799 call_epilog, |
|
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13800 post_call_FPU ); |
|
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13801 ins_pipe( pipe_slow ); |
|
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13802 ins_pc_relative(1); |
|
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13803 ins_alignment(4); |
|
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|
13804 %} |
|
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|
13805 |
| 0 | 13806 // Call Java Dynamic Instruction |
| 13807 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 13808 // compute_padding() functions will have to be adjusted. | |
| 13809 instruct CallDynamicJavaDirect(method meth) %{ | |
| 13810 match(CallDynamicJava); | |
| 13811 effect(USE meth); | |
| 13812 | |
| 13813 ins_cost(300); | |
| 13814 format %{ "MOV EAX,(oop)-1\n\t" | |
| 13815 "CALL,dynamic" %} | |
| 13816 opcode(0xE8); /* E8 cd */ | |
| 13817 ins_encode( pre_call_FPU, | |
| 13818 Java_Dynamic_Call( meth ), | |
| 13819 call_epilog, | |
| 13820 post_call_FPU ); | |
| 13821 ins_pipe( pipe_slow ); | |
| 13822 ins_pc_relative(1); | |
| 13823 ins_alignment(4); | |
| 13824 %} | |
| 13825 | |
| 13826 // Call Runtime Instruction | |
| 13827 instruct CallRuntimeDirect(method meth) %{ | |
| 13828 match(CallRuntime ); | |
| 13829 effect(USE meth); | |
| 13830 | |
| 13831 ins_cost(300); | |
| 13832 format %{ "CALL,runtime " %} | |
| 13833 opcode(0xE8); /* E8 cd */ | |
| 13834 // Use FFREEs to clear entries in float stack | |
| 13835 ins_encode( pre_call_FPU, | |
| 13836 FFree_Float_Stack_All, | |
| 13837 Java_To_Runtime( meth ), | |
| 13838 post_call_FPU ); | |
| 13839 ins_pipe( pipe_slow ); | |
| 13840 ins_pc_relative(1); | |
| 13841 %} | |
| 13842 | |
| 13843 // Call runtime without safepoint | |
| 13844 instruct CallLeafDirect(method meth) %{ | |
| 13845 match(CallLeaf); | |
| 13846 effect(USE meth); | |
| 13847 | |
| 13848 ins_cost(300); | |
| 13849 format %{ "CALL_LEAF,runtime " %} | |
| 13850 opcode(0xE8); /* E8 cd */ | |
| 13851 ins_encode( pre_call_FPU, | |
| 13852 FFree_Float_Stack_All, | |
| 13853 Java_To_Runtime( meth ), | |
| 13854 Verify_FPU_For_Leaf, post_call_FPU ); | |
| 13855 ins_pipe( pipe_slow ); | |
| 13856 ins_pc_relative(1); | |
| 13857 %} | |
| 13858 | |
| 13859 instruct CallLeafNoFPDirect(method meth) %{ | |
| 13860 match(CallLeafNoFP); | |
| 13861 effect(USE meth); | |
| 13862 | |
| 13863 ins_cost(300); | |
| 13864 format %{ "CALL_LEAF_NOFP,runtime " %} | |
| 13865 opcode(0xE8); /* E8 cd */ | |
| 13866 ins_encode(Java_To_Runtime(meth)); | |
| 13867 ins_pipe( pipe_slow ); | |
| 13868 ins_pc_relative(1); | |
| 13869 %} | |
| 13870 | |
| 13871 | |
| 13872 // Return Instruction | |
| 13873 // Remove the return address & jump to it. | |
| 13874 instruct Ret() %{ | |
| 13875 match(Return); | |
| 13876 format %{ "RET" %} | |
| 13877 opcode(0xC3); | |
| 13878 ins_encode(OpcP); | |
| 13879 ins_pipe( pipe_jmp ); | |
| 13880 %} | |
| 13881 | |
| 13882 // Tail Call; Jump from runtime stub to Java code. | |
| 13883 // Also known as an 'interprocedural jump'. | |
| 13884 // Target of jump will eventually return to caller. | |
| 13885 // TailJump below removes the return address. | |
| 13886 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{ | |
| 13887 match(TailCall jump_target method_oop ); | |
| 13888 ins_cost(300); | |
| 13889 format %{ "JMP $jump_target \t# EBX holds method oop" %} | |
| 13890 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 13891 ins_encode( OpcP, RegOpc(jump_target) ); | |
| 13892 ins_pipe( pipe_jmp ); | |
| 13893 %} | |
| 13894 | |
| 13895 | |
| 13896 // Tail Jump; remove the return address; jump to target. | |
| 13897 // TailCall above leaves the return address around. | |
| 13898 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{ | |
| 13899 match( TailJump jump_target ex_oop ); | |
| 13900 ins_cost(300); | |
| 13901 format %{ "POP EDX\t# pop return address into dummy\n\t" | |
| 13902 "JMP $jump_target " %} | |
| 13903 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 13904 ins_encode( enc_pop_rdx, | |
| 13905 OpcP, RegOpc(jump_target) ); | |
| 13906 ins_pipe( pipe_jmp ); | |
| 13907 %} | |
| 13908 | |
| 13909 // Create exception oop: created by stack-crawling runtime code. | |
| 13910 // Created exception is now available to this handler, and is setup | |
| 13911 // just prior to jumping to this handler. No code emitted. | |
| 13912 instruct CreateException( eAXRegP ex_oop ) | |
| 13913 %{ | |
| 13914 match(Set ex_oop (CreateEx)); | |
| 13915 | |
| 13916 size(0); | |
| 13917 // use the following format syntax | |
| 13918 format %{ "# exception oop is in EAX; no code emitted" %} | |
| 13919 ins_encode(); | |
| 13920 ins_pipe( empty ); | |
| 13921 %} | |
| 13922 | |
| 13923 | |
| 13924 // Rethrow exception: | |
| 13925 // The exception oop will come in the first argument position. | |
| 13926 // Then JUMP (not call) to the rethrow stub code. | |
| 13927 instruct RethrowException() | |
| 13928 %{ | |
| 13929 match(Rethrow); | |
| 13930 | |
| 13931 // use the following format syntax | |
| 13932 format %{ "JMP rethrow_stub" %} | |
| 13933 ins_encode(enc_rethrow); | |
| 13934 ins_pipe( pipe_jmp ); | |
| 13935 %} | |
| 13936 | |
| 13937 // inlined locking and unlocking | |
| 13938 | |
| 13939 | |
| 13940 instruct cmpFastLock( eFlagsReg cr, eRegP object, eRegP box, eAXRegI tmp, eRegP scr) %{ | |
| 13941 match( Set cr (FastLock object box) ); | |
| 13942 effect( TEMP tmp, TEMP scr ); | |
| 13943 ins_cost(300); | |
| 13944 format %{ "FASTLOCK $object, $box KILLS $tmp,$scr" %} | |
| 13945 ins_encode( Fast_Lock(object,box,tmp,scr) ); | |
| 13946 ins_pipe( pipe_slow ); | |
| 13947 ins_pc_relative(1); | |
| 13948 %} | |
| 13949 | |
| 13950 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{ | |
| 13951 match( Set cr (FastUnlock object box) ); | |
| 13952 effect( TEMP tmp ); | |
| 13953 ins_cost(300); | |
| 13954 format %{ "FASTUNLOCK $object, $box, $tmp" %} | |
| 13955 ins_encode( Fast_Unlock(object,box,tmp) ); | |
| 13956 ins_pipe( pipe_slow ); | |
| 13957 ins_pc_relative(1); | |
| 13958 %} | |
| 13959 | |
| 13960 | |
| 13961 | |
| 13962 // ============================================================================ | |
| 13963 // Safepoint Instruction | |
| 13964 instruct safePoint_poll(eFlagsReg cr) %{ | |
| 13965 match(SafePoint); | |
| 13966 effect(KILL cr); | |
| 13967 | |
| 13968 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page. | |
| 13969 // On SPARC that might be acceptable as we can generate the address with | |
| 13970 // just a sethi, saving an or. By polling at offset 0 we can end up | |
| 13971 // putting additional pressure on the index-0 in the D$. Because of | |
| 13972 // alignment (just like the situation at hand) the lower indices tend | |
| 13973 // to see more traffic. It'd be better to change the polling address | |
| 13974 // to offset 0 of the last $line in the polling page. | |
| 13975 | |
| 13976 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %} | |
| 13977 ins_cost(125); | |
| 13978 size(6) ; | |
| 13979 ins_encode( Safepoint_Poll() ); | |
| 13980 ins_pipe( ialu_reg_mem ); | |
| 13981 %} | |
| 13982 | |
| 13983 //----------PEEPHOLE RULES----------------------------------------------------- | |
| 13984 // These must follow all instruction definitions as they use the names | |
| 13985 // defined in the instructions definitions. | |
| 13986 // | |
| 605 | 13987 // peepmatch ( root_instr_name [preceding_instruction]* ); |
| 0 | 13988 // |
| 13989 // peepconstraint %{ | |
| 13990 // (instruction_number.operand_name relational_op instruction_number.operand_name | |
| 13991 // [, ...] ); | |
| 13992 // // instruction numbers are zero-based using left to right order in peepmatch | |
| 13993 // | |
| 13994 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); | |
| 13995 // // provide an instruction_number.operand_name for each operand that appears | |
| 13996 // // in the replacement instruction's match rule | |
| 13997 // | |
| 13998 // ---------VM FLAGS--------------------------------------------------------- | |
| 13999 // | |
| 14000 // All peephole optimizations can be turned off using -XX:-OptoPeephole | |
| 14001 // | |
| 14002 // Each peephole rule is given an identifying number starting with zero and | |
| 14003 // increasing by one in the order seen by the parser. An individual peephole | |
| 14004 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# | |
| 14005 // on the command-line. | |
| 14006 // | |
| 14007 // ---------CURRENT LIMITATIONS---------------------------------------------- | |
| 14008 // | |
| 14009 // Only match adjacent instructions in same basic block | |
| 14010 // Only equality constraints | |
| 14011 // Only constraints between operands, not (0.dest_reg == EAX_enc) | |
| 14012 // Only one replacement instruction | |
| 14013 // | |
| 14014 // ---------EXAMPLE---------------------------------------------------------- | |
| 14015 // | |
| 14016 // // pertinent parts of existing instructions in architecture description | |
| 14017 // instruct movI(eRegI dst, eRegI src) %{ | |
| 14018 // match(Set dst (CopyI src)); | |
| 14019 // %} | |
| 14020 // | |
| 14021 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ | |
| 14022 // match(Set dst (AddI dst src)); | |
| 14023 // effect(KILL cr); | |
| 14024 // %} | |
| 14025 // | |
| 14026 // // Change (inc mov) to lea | |
| 14027 // peephole %{ | |
| 14028 // // increment preceeded by register-register move | |
| 14029 // peepmatch ( incI_eReg movI ); | |
| 14030 // // require that the destination register of the increment | |
| 14031 // // match the destination register of the move | |
| 14032 // peepconstraint ( 0.dst == 1.dst ); | |
| 14033 // // construct a replacement instruction that sets | |
| 14034 // // the destination to ( move's source register + one ) | |
| 14035 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 14036 // %} | |
| 14037 // | |
| 14038 // Implementation no longer uses movX instructions since | |
| 14039 // machine-independent system no longer uses CopyX nodes. | |
| 14040 // | |
| 14041 // peephole %{ | |
| 14042 // peepmatch ( incI_eReg movI ); | |
| 14043 // peepconstraint ( 0.dst == 1.dst ); | |
| 14044 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 14045 // %} | |
| 14046 // | |
| 14047 // peephole %{ | |
| 14048 // peepmatch ( decI_eReg movI ); | |
| 14049 // peepconstraint ( 0.dst == 1.dst ); | |
| 14050 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 14051 // %} | |
| 14052 // | |
| 14053 // peephole %{ | |
| 14054 // peepmatch ( addI_eReg_imm movI ); | |
| 14055 // peepconstraint ( 0.dst == 1.dst ); | |
| 14056 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 14057 // %} | |
| 14058 // | |
| 14059 // peephole %{ | |
| 14060 // peepmatch ( addP_eReg_imm movP ); | |
| 14061 // peepconstraint ( 0.dst == 1.dst ); | |
| 14062 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 14063 // %} | |
| 14064 | |
| 14065 // // Change load of spilled value to only a spill | |
| 14066 // instruct storeI(memory mem, eRegI src) %{ | |
| 14067 // match(Set mem (StoreI mem src)); | |
| 14068 // %} | |
| 14069 // | |
| 14070 // instruct loadI(eRegI dst, memory mem) %{ | |
| 14071 // match(Set dst (LoadI mem)); | |
| 14072 // %} | |
| 14073 // | |
| 14074 peephole %{ | |
| 14075 peepmatch ( loadI storeI ); | |
| 14076 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); | |
| 14077 peepreplace ( storeI( 1.mem 1.mem 1.src ) ); | |
| 14078 %} | |
| 14079 | |
| 14080 //----------SMARTSPILL RULES--------------------------------------------------- | |
| 14081 // These must follow all instruction definitions as they use the names | |
| 14082 // defined in the instructions definitions. |